+++ /dev/null
-LIBRARY ieee;\r
-use ieee.std_logic_1164.all;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-use IEEE.std_logic_arith.all;\r
-\r
-library work;\r
-\r
-entity feeder is\r
-port( CLK : in std_logic;\r
- RESET : in std_logic;\r
- -- IPU interface directed toward the CTS\r
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
- CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
- CTS_START_READOUT_IN : in std_logic;\r
- CTS_READ_IN : in std_logic;\r
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
- CTS_DATAREADY_OUT : out std_logic;\r
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM\r
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
- -- Data from Frontends\r
- FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
- FEE_DATAREADY_IN : in std_logic;\r
- FEE_READ_OUT : out std_logic;\r
- FEE_BUSY_IN : in std_logic;\r
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); \r
- -- PacketConstructor interface\r
- PC_WR_EN_OUT : out std_logic;\r
- PC_DATA_OUT : out std_logic_vector (7 downto 0);\r
- PC_READY_IN : in std_logic;\r
- PC_SOS_OUT : out std_logic;\r
- PC_EOD_OUT : out std_logic;\r
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);\r
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);\r
- PC_PADDING_OUT : out std_logic;\r
- -- Debug\r
- BSM_SAVE_OUT : out std_logic_vector(3 downto 0);\r
- BSM_LOAD_OUT : out std_logic_vector(3 downto 0);\r
- DBG_REM_CTR_OUT : out std_logic_vector(3 downto 0);\r
- DBG_CTS_CTR_OUT : out std_logic_vector(2 downto 0);\r
- DBG_SF_WCNT_OUT : out std_logic_vector(15 downto 0);\r
- DBG_SF_RCNT_OUT : out std_logic_vector(16 downto 0);\r
- DBG_SF_DATA_OUT : out std_logic_vector(15 downto 0);\r
- DBG_SF_RD_EN_OUT : out std_logic;\r
- DBG_SF_WR_EN_OUT : out std_logic;\r
- DBG_SF_EMPTY_OUT : out std_logic;\r
- DBG_SF_FULL_OUT : out std_logic;\r
- DBG_SF_AFULL_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
-);\r
-end entity;\r
-\r
-architecture feeder of feeder is\r
-\r
-component fifo_32kx16x8_mb\r
-port( Data : in std_logic_vector(15 downto 0); \r
- WrClock : in std_logic;\r
- RdClock : in std_logic; \r
- WrEn : in std_logic;\r
- RdEn : in std_logic;\r
- Reset : in std_logic; \r
- RPReset : in std_logic; \r
- AmFullThresh : in std_logic_vector(14 downto 0); \r
- Q : out std_logic_vector(7 downto 0); \r
- WCNT : out std_logic_vector(15 downto 0); \r
- RCNT : out std_logic_vector(16 downto 0);\r
- Empty : out std_logic; \r
- Full : out std_logic;\r
- AlmostFull : out std_logic\r
- );\r
-end component;\r
-\r
-type saveStates is (SIDLE, WAIT_FOR_DATA, SAVE_DATA, TERMINATE, SCLOSE);\r
-signal saveCurrentState, saveNextState : saveStates;\r
-signal state : std_logic_vector(3 downto 0);\r
-signal data_req_comb : std_logic;\r
-signal data_req : std_logic; -- request data signal, will be used for fee_read generation\r
-signal rst_saved_ctr_comb : std_logic;\r
-signal rst_saved_ctr : std_logic;\r
-\r
-signal fee_read_comb : std_logic;\r
-signal fee_read : std_logic; -- fee_read signal\r
-signal saved_ctr : std_logic_vector(16 downto 0);\r
-signal ce_saved_ctr : std_logic;\r
-\r
--- header data\r
-signal cts_rnd : std_logic_vector(15 downto 0);\r
-signal cts_rnd_saved : std_logic;\r
-signal cts_trg : std_logic_vector(15 downto 0);\r
-signal cts_trg_saved : std_logic;\r
-signal cts_len : std_logic_vector(16 downto 0);\r
-signal cts_len_saved : std_logic;\r
-\r
--- CTS interface\r
-signal cts_error_pattern : std_logic_vector(31 downto 0);\r
-signal cts_length : std_logic_vector(15 downto 0);\r
-signal cts_readout_finished : std_logic;\r
-signal cts_dataready : std_logic;\r
-signal cts_data : std_logic_vector(31 downto 0);\r
-\r
--- Split FIFO signals\r
-signal sf_data : std_logic_vector(15 downto 0);\r
-signal sf_wr_en_comb : std_logic;\r
-signal sf_wr_en : std_logic; -- write signal for FIFO\r
-signal sf_rd_en : std_logic;\r
-signal sf_wcnt : std_logic_vector(15 downto 0);\r
-signal sf_rcnt : std_logic_vector(16 downto 0);\r
-signal sf_empty : std_logic;\r
-signal sf_full : std_logic;\r
-signal sf_afull : std_logic;\r
-\r
--------------------------------------------------------------------\r
-type loadStates is (LIDLE, INIT, REMOVE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, WAIT_PC, CLOSE);\r
-signal loadCurrentState, loadNextState : loadStates;\r
-signal state2 : std_logic_vector(3 downto 0);\r
-\r
-signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data\r
-signal rst_rem_ctr_comb : std_logic;\r
-signal rst_rem_ctr : std_logic;\r
-signal rst_regs_comb : std_logic;\r
-signal rst_regs : std_logic;\r
-signal ce_rem_ctr_comb : std_logic;\r
-signal ce_rem_ctr : std_logic;\r
-signal remove_done_comb : std_logic;\r
-signal remove_done : std_logic; -- end of header stripping process\r
-signal load_done_comb : std_logic;\r
-signal load_done : std_logic; -- end of data transfer into PC\r
-signal calc_pad_comb : std_logic;\r
-signal calc_pad : std_logic; -- add padding bytes, if needed\r
-signal read_data_comb : std_logic;\r
-signal read_data : std_logic; -- fetch data from split fifo\r
-signal data_phase_comb : std_logic;\r
-signal data_phase : std_logic; -- data transport phase from split fifo to PC\r
-signal pc_sos_comb : std_logic;\r
-signal pc_sos : std_logic; -- start of data signal\r
-signal pc_eod_comb : std_logic;\r
-signal pc_eod : std_logic; -- end of data signal\r
-signal pad_data_comb : std_logic;\r
-signal pad_data : std_logic; -- insert padding bytes\r
-\r
-signal pc_data : std_logic_vector(7 downto 0);\r
-signal pc_data_q : std_logic_vector(7 downto 0);\r
-signal pc_trig_nr : std_logic_vector(15 downto 0);\r
-signal pc_sub_size : std_logic_vector(17 downto 0);\r
-signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo\r
-signal padding_needed : std_logic;\r
-signal pc_wr_en_q : std_logic;\r
-signal pc_wr_en_qq : std_logic;\r
-signal pc_eod_q : std_logic;\r
-\r
-signal debug : std_logic_vector(31 downto 0);\r
-\r
-begin\r
-\r
--- CTS interface signals\r
-cts_error_pattern <= (others => '0'); -- FAKE\r
-cts_dataready <= '1'; -- FAKE\r
-\r
-cts_length <= x"0000"; -- length of data payload is always 0\r
-cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'\r
-\r
-cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';\r
-\r
-\r
--- Sync all critical pathes\r
-THE_SYNC_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- sf_data <= FEE_DATA_IN;\r
- sf_wr_en <= sf_wr_en_comb;\r
- fee_read <= fee_read_comb;\r
- load_done <= load_done_comb;\r
- pc_eod_q <= pc_eod;\r
- pc_wr_en_qq <= pc_wr_en_q;\r
- pc_wr_en_q <= data_phase;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
--- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY\r
-fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) \r
- else '0';\r
-\r
--- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY\r
-sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') )\r
- else '0';\r
-\r
--- Counter for header word storage\r
-THE_CTS_SAVED_CTR: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then\r
- saved_ctr <= (others => '0');\r
- elsif( ce_saved_ctr = '1' ) then\r
- saved_ctr <= saved_ctr + 1;\r
- end if;\r
- end if;\r
-end process THE_CTS_SAVED_CTR;\r
-\r
-ce_saved_ctr <= sf_wr_en;\r
-\r
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO\r
-saveMachineProc: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if RESET = '1' then\r
- saveCurrentState <= SIDLE;\r
- data_req <= '0';\r
- rst_saved_ctr <= '0';\r
- else\r
- saveCurrentState <= saveNextState;\r
- data_req <= data_req_comb;\r
- rst_saved_ctr <= rst_saved_ctr_comb;\r
- end if;\r
- end if;\r
-end process saveMachineProc;\r
-\r
-saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN )\r
-begin\r
- saveNextState <= SIDLE;\r
- data_req_comb <= '0';\r
- rst_saved_ctr_comb <= '0';\r
- case saveCurrentState is\r
- when SIDLE =>\r
- state <= x"0";\r
- if (CTS_START_READOUT_IN = '1') then\r
- saveNextState <= WAIT_FOR_DATA;\r
- data_req_comb <= '1';\r
- rst_saved_ctr_comb <= '1';\r
- else\r
- saveNextState <= SIDLE;\r
- end if;\r
- when WAIT_FOR_DATA =>\r
- state <= x"1";\r
- if (FEE_BUSY_IN = '1') then\r
- saveNextState <= SAVE_DATA;\r
- data_req_comb <= '1';\r
- else\r
- saveNextState <= WAIT_FOR_DATA;\r
- data_req_comb <= '1';\r
- end if;\r
- when SAVE_DATA =>\r
- state <= x"2";\r
- if (FEE_BUSY_IN = '0') then\r
- saveNextState <= TERMINATE;\r
- else\r
- saveNextState <= SAVE_DATA;\r
- data_req_comb <= '1';\r
- end if;\r
- when TERMINATE =>\r
- state <= x"3";\r
- if (CTS_READ_IN = '1') then\r
- saveNextState <= SCLOSE;\r
- else\r
- saveNextState <= TERMINATE;\r
- end if;\r
- when SCLOSE =>\r
- state <= x"4";\r
- if (CTS_START_READOUT_IN = '0') then\r
- saveNextState <= SIDLE;\r
- else\r
- saveNextState <= SCLOSE;\r
- end if;\r
- when others =>\r
- state <= x"f";\r
- saveNextState <= SIDLE;\r
- end case;\r
-end process saveMachine;\r
-\r
--- save triggerRnd from incoming data for cts response\r
-CTS_RND_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then\r
- cts_rnd <= (others => '0');\r
- cts_rnd_saved <= '0';\r
- elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then\r
- cts_rnd <= sf_data;\r
- cts_rnd_saved <= '1';\r
- end if;\r
- end if;\r
-end process CTS_RND_PROC;\r
-\r
--- save triggerNr from incoming data for cts response\r
-CTS_TRG_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then\r
- cts_trg <= (others => '0');\r
- cts_trg_saved <= '0';\r
- elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then\r
- cts_trg <= sf_data;\r
- cts_trg_saved <= '1';\r
- end if;\r
- end if;\r
-end process CTS_TRG_PROC;\r
-\r
--- save size from incoming data for cts response (future) and to get rid of padding\r
-CTS_SIZE_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then\r
- cts_len <= (others => '0');\r
- cts_len_saved <= '0';\r
- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then\r
- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words\r
- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then\r
- cts_len <= cts_len + x"4";\r
- cts_len_saved <= '1';\r
- end if;\r
- end if;\r
-end process CTS_SIZE_PROC;\r
-\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-\r
--- Split FIFO\r
-THE_SPLIT_FIFO: fifo_32kx16x8_mb\r
-port map( Data => sf_data,\r
- WrClock => CLK,\r
- RdClock => CLK, \r
- WrEn => sf_wr_en,\r
- RdEn => sf_rd_en,\r
- Reset => RESET, \r
- RPReset => RESET, \r
- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751\r
- Q => pc_data, --open,\r
- WCNT => sf_wcnt,\r
- RCNT => sf_rcnt,\r
- Empty => sf_empty,\r
- Full => sf_full,\r
- AlmostFull => sf_afull\r
- );\r
-\r
-sf_rd_en <= read_data;\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-\r
--- FIFO data delay process (also forces padding bytes to known value)\r
-THE_DATA_DELAY_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if( pad_data = '1' ) then\r
- pc_data_q <= x"ee";\r
- else\r
- pc_data_q <= pc_data;\r
- end if;\r
- end if;\r
-end process THE_DATA_DELAY_PROC;\r
-\r
--- Statemachine for reading the data payload from the SPLIT_FIFO and feeding\r
--- it into the packet constructor\r
-loadMachineProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if RESET = '1' then\r
- loadCurrentState <= LIDLE;\r
- rst_regs <= '0';\r
- rst_rem_ctr <= '0';\r
- ce_rem_ctr <= '0';\r
- calc_pad <= '0';\r
- read_data <= '0';\r
- data_phase <= '0';\r
- pc_sos <= '0';\r
- pc_eod <= '0';\r
- pad_data <= '0';\r
- else\r
- loadCurrentState <= loadNextState;\r
- rst_regs <= rst_regs_comb;\r
- rst_rem_ctr <= rst_rem_ctr_comb;\r
- ce_rem_ctr <= ce_rem_ctr_comb;\r
- calc_pad <= calc_pad_comb;\r
- read_data <= read_data_comb;\r
- data_phase <= data_phase_comb;\r
- pc_sos <= pc_sos_comb;\r
- pc_eod <= pc_eod_comb;\r
- pad_data <= pad_data_comb;\r
- end if;\r
- end if;\r
-end process loadMachineProc;\r
-\r
-loadMachine : process( loadCurrentState, sf_empty, remove_done, load_done, padding_needed, PC_READY_IN )\r
-begin\r
- loadNextState <= LIDLE;\r
- rst_regs_comb <= '0';\r
- rst_rem_ctr_comb <= '0';\r
- ce_rem_ctr_comb <= '0';\r
- calc_pad_comb <= '0';\r
- read_data_comb <= '0';\r
- data_phase_comb <= '0';\r
- pc_sos_comb <= '0';\r
- pc_eod_comb <= '0';\r
- pad_data_comb <= '0';\r
- case loadCurrentState is\r
- when LIDLE =>\r
- state2 <= x"0";\r
- if( (sf_empty = '0') and (PC_READY_IN = '1') ) then\r
- loadNextState <= INIT;\r
- rst_regs_comb <= '1';\r
- rst_rem_ctr_comb <= '1';\r
- else\r
- loadNextState <= LIDLE;\r
- end if;\r
- when INIT =>\r
- state2 <= x"1";\r
- loadNextState <= REMOVE;\r
- ce_rem_ctr_comb <= '1';\r
- read_data_comb <= '1';\r
- when REMOVE =>\r
- state2 <= x"2";\r
- if( remove_done = '1' ) then\r
- loadNextState <= CALCA;\r
- calc_pad_comb <= '1';\r
- else\r
- loadNextState <= REMOVE;\r
- ce_rem_ctr_comb <= '1';\r
- read_data_comb <= '1';\r
- end if;\r
- when CALCA =>\r
- state2 <= x"3";\r
- loadNextState <= CALCB;\r
- when CALCB =>\r
- -- we need a branch in case of length "0"!!!!\r
- state2 <= x"4";\r
- loadNextState <= LOAD;\r
- read_data_comb <= '1';\r
- data_phase_comb <= '1';\r
- pc_sos_comb <= '1';\r
- when LOAD =>\r
- state2 <= x"5";\r
- if ( (load_done = '1') and (padding_needed = '0') ) then\r
- loadNextState <= CLOSE;\r
- elsif( (load_done = '1') and (padding_needed = '1') ) then\r
- loadNextState <= PAD0;\r
- data_phase_comb <= '1';\r
- else\r
- loadNextState <= LOAD;\r
- read_data_comb <= '1';\r
- data_phase_comb <= '1';\r
- end if;\r
- when PAD0 =>\r
- state2 <= x"5";\r
- loadNextState <= PAD1;\r
- data_phase_comb <= '1';\r
- pad_data_comb <= '1';\r
- when PAD1 =>\r
- state2 <= x"6";\r
- loadNextState <= PAD2;\r
- data_phase_comb <= '1';\r
- pad_data_comb <= '1';\r
- when PAD2 =>\r
- state2 <= x"7";\r
- loadNextState <= PAD3;\r
- data_phase_comb <= '1';\r
- pad_data_comb <= '1';\r
- when PAD3 =>\r
- state2 <= x"8";\r
- loadNextState <= CLOSE;\r
- pad_data_comb <= '1';\r
- when CLOSE =>\r
- state2 <= x"9";\r
- loadNextState <= WAIT_PC;\r
- pc_eod_comb <= '1';\r
- when WAIT_PC =>\r
- state2 <= x"a";\r
- if( PC_READY_IN = '1' ) then\r
- loadNextState <= LIDLE;\r
- rst_rem_ctr_comb <= '1';\r
- rst_regs_comb <= '1';\r
- else\r
- loadNextState <= WAIT_PC;\r
- end if;\r
- when others =>\r
- state2 <= x"f";\r
- loadNextState <= LIDLE;\r
- end case;\r
-end process loadMachine;\r
-\r
--- Counter for stripping the unneeded parts of the data stream, and saving the important parts\r
-THE_REMOVE_CTR: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then\r
- rem_ctr <= (others => '0');\r
- elsif( ce_rem_ctr = '1' ) then\r
- rem_ctr <= rem_ctr + 1;\r
- end if;\r
- end if;\r
-end process THE_REMOVE_CTR;\r
-\r
-remove_done_comb <= '1' when ( rem_ctr = x"6" ) else '0';\r
-\r
-THE_REM_DONE_SYNC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then\r
- remove_done <= '0';\r
- else\r
- remove_done <= remove_done_comb;\r
- end if;\r
- end if;\r
-end process THE_REM_DONE_SYNC;\r
-\r
--- extract the trigger number from splitfifo data\r
-THE_TRG_NR_PROC: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if ( (RESET = '1') or (rst_regs = '1') ) then\r
- pc_trig_nr <= (others => '0');\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"3") ) then\r
- pc_trig_nr(7 downto 0) <= pc_data;\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"4") ) then\r
- pc_trig_nr(15 downto 8) <= pc_data;\r
- end if;\r
- end if;\r
-end process THE_TRG_NR_PROC;\r
-\r
--- check for padding\r
-THE_PADDING_NEEDED_PROC: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if ( (RESET = '1') or (rst_regs = '1') ) then\r
- padding_needed <= '0';\r
- elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then\r
- padding_needed <= '1';\r
- elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then\r
- padding_needed <= '0';\r
- end if;\r
- end if;\r
-end process THE_PADDING_NEEDED_PROC;\r
-\r
--- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,\r
--- and in case of padding needed increase it accordingly\r
-THE_SUB_SIZE_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_regs = '1') ) then\r
- pc_sub_size <= (others => '0');\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then\r
- pc_sub_size(9 downto 2) <= pc_data;\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then\r
- pc_sub_size(17 downto 10) <= pc_data;\r
- elsif( (calc_pad = '1') and (padding_needed = '1') ) then\r
- pc_sub_size <= pc_sub_size + 4;\r
- end if;\r
- end if;\r
-end process THE_SUB_SIZE_PROC;\r
-\r
--- number of bytes to read from split fifo\r
-THE_READ_SIZE_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then\r
- read_size <= (others => '0');\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then\r
- read_size(9 downto 2) <= pc_data;\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then\r
- read_size(17 downto 10) <= pc_data;\r
- elsif( ((calc_pad = '1') and (load_done = '0')) ) then\r
- read_size <= read_size - 2;\r
- elsif( ((read_data = '1') and (data_phase = '1')) ) then\r
- read_size <= read_size - 1;\r
- end if;\r
- end if;\r
-end process THE_READ_SIZE_PROC;\r
-\r
-load_done_comb <= '1' when (read_size = 0) else '0';\r
-\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-\r
--- Debug signals\r
-debug(31) <= remove_done;\r
-debug(30) <= load_done;\r
-debug(29) <= ce_rem_ctr;\r
-debug(28) <= rst_rem_ctr;\r
-debug(27) <= rst_regs;\r
-debug(26) <= data_phase;\r
-debug(25) <= read_data;\r
-debug(24) <= pad_data;\r
-debug(23 downto 18) <= (others => '0');\r
-debug(17 downto 0) <= read_size;\r
-\r
--- Outputs\r
-FEE_READ_OUT <= fee_read;\r
-CTS_ERROR_PATTERN_OUT <= cts_error_pattern;\r
-CTS_DATA_OUT <= cts_data;\r
-CTS_DATAREADY_OUT <= cts_dataready;\r
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;\r
-CTS_LENGTH_OUT <= cts_length;\r
-\r
-PC_SOS_OUT <= pc_sos;\r
-PC_EOD_OUT <= pc_eod_q;\r
-PC_DATA_OUT <= pc_data_q;\r
-PC_WR_EN_OUT <= pc_wr_en_qq;\r
-PC_TRIG_NR_OUT <= x"0000" & pc_trig_nr;\r
-PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size;\r
-PC_PADDING_OUT <= padding_needed;\r
-\r
-BSM_SAVE_OUT <= state;\r
-BSM_LOAD_OUT <= state2;\r
-DBG_CTS_CTR_OUT <= saved_ctr(2 downto 0);\r
-DBG_REM_CTR_OUT <= rem_ctr;\r
-DBG_SF_DATA_OUT <= sf_data;\r
-DBG_SF_WCNT_OUT <= sf_wcnt;\r
-DBG_SF_RCNT_OUT <= sf_rcnt;\r
-DBG_SF_RD_EN_OUT <= sf_rd_en;\r
-DBG_SF_WR_EN_OUT <= sf_wr_en;\r
-DBG_SF_EMPTY_OUT <= sf_empty;\r
-DBG_SF_FULL_OUT <= sf_full;\r
-DBG_SF_AFULL_OUT <= sf_afull;\r
-\r
-DEBUG_OUT <= debug;\r
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;\r
-use ieee.std_logic_1164.all;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-use IEEE.std_logic_arith.all;\r
-\r
-library work;\r
-\r
-entity ip_configurator is\r
-port( \r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- -- configuration interface\r
- START_CONFIG_IN : in std_logic; -- start configuration run\r
- BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank \r
- CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used\r
- MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for\r
- MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory\r
- MEM_CLK_OUT : out std_logic; -- clock for BlockRAM\r
- -- information for IP cores\r
- DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address\r
- DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address\r
- DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port\r
- SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address\r
- SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address\r
- SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port\r
- MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size)\r
- -- Debug\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
-);\r
-end entity;\r
-\r
-architecture ip_configurator of ip_configurator is\r
-\r
--- -- Placer Directives\r
--- attribute HGROUP : string;\r
--- -- for whole architecture\r
--- attribute HGROUP of ip_configurator : architecture is "GBE_conf_group";\r
-\r
-type STATES is (IDLE, LOAD_REG, DELAY0, DELAY1, DELAY2, LOAD_DONE);\r
-signal CURRENT_STATE, NEXT_STATE : STATES;\r
-signal bsm : std_logic_vector(3 downto 0);\r
-signal ce_ctr_comb : std_logic;\r
-signal ce_ctr : std_logic;\r
-signal rst_ctr_comb : std_logic;\r
-signal rst_ctr : std_logic;\r
-signal cfg_done_comb : std_logic;\r
-signal cfg_done : std_logic;\r
-\r
-signal ctr_done_comb : std_logic;\r
-signal ctr_done : std_logic;\r
-\r
-signal wr_select_comb : std_logic_vector(15 downto 0);\r
-signal wr_select : std_logic_vector(15 downto 0);\r
-signal wr_select_q : std_logic_vector(15 downto 0);\r
-\r
-signal addr_ctr : std_logic_vector(3 downto 0);\r
-signal dest_mac : std_logic_vector(47 downto 0);\r
-signal dest_ip : std_logic_vector(31 downto 0);\r
-signal dest_udp : std_logic_vector(15 downto 0);\r
-signal src_mac : std_logic_vector(47 downto 0);\r
-signal src_ip : std_logic_vector(31 downto 0);\r
-signal src_udp : std_logic_vector(15 downto 0);\r
-signal mtu : std_logic_vector(15 downto 0);\r
-\r
-signal debug : std_logic_vector(31 downto 0);\r
-\r
-begin\r
-\r
-\r
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO\r
-STATE_MACHINE_PROC: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if RESET = '1' then\r
- CURRENT_STATE <= IDLE;\r
- ce_ctr <= '0';\r
- rst_ctr <= '0';\r
- cfg_done <= '0';\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- ce_ctr <= ce_ctr_comb;\r
- rst_ctr <= rst_ctr_comb;\r
- cfg_done <= cfg_done_comb;\r
- end if;\r
- end if;\r
-end process STATE_MACHINE_PROC;\r
-\r
-STATE_MACHINE_TRANS: process( CURRENT_STATE, START_CONFIG_IN, ctr_done )\r
-begin\r
- NEXT_STATE <= IDLE;\r
- ce_ctr_comb <= '0';\r
- rst_ctr_comb <= '0';\r
- cfg_done_comb <= '0';\r
- case CURRENT_STATE is\r
- when IDLE =>\r
- bsm <= x"0";\r
- if( START_CONFIG_IN = '1' ) then\r
- NEXT_STATE <= LOAD_REG;\r
- ce_ctr_comb <= '1';\r
- else\r
- NEXT_STATE <= IDLE;\r
- end if;\r
- when LOAD_REG =>\r
- bsm <= x"1";\r
- if( ctr_done = '1' ) then\r
- NEXT_STATE <= DELAY0;\r
- rst_ctr_comb <= '1';\r
- else\r
- NEXT_STATE <= LOAD_REG;\r
- ce_ctr_comb <= '1';\r
- end if;\r
- when DELAY0 =>\r
- bsm <= x"2";\r
- NEXT_STATE <= DELAY1;\r
- when DELAY1 =>\r
- bsm <= x"3";\r
- NEXT_STATE <= DELAY2;\r
- when DELAY2 =>\r
- bsm <= x"4";\r
- NEXT_STATE <= LOAD_DONE;\r
- cfg_done_comb <= '1';\r
- when LOAD_DONE =>\r
- bsm <= x"2";\r
- if( START_CONFIG_IN = '0' ) then\r
- NEXT_STATE <= IDLE;\r
- else\r
- NEXT_STATE <= LOAD_DONE;\r
- cfg_done_comb <= '1';\r
- end if;\r
- when others =>\r
- bsm <= x"f";\r
- NEXT_STATE <= IDLE;\r
- end case;\r
-end process STATE_MACHINE_TRANS;\r
-\r
--- address counter\r
-THE_ADDR_CTR_PROC: process( CLK )\r
-begin\r
- if ( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_ctr = '1') ) then\r
- addr_ctr <= (others => '0');\r
- elsif( ce_ctr = '1' ) then\r
- addr_ctr <= addr_ctr + 1;\r
- end if; \r
- end if;\r
-end process THE_ADDR_CTR_PROC;\r
-\r
-ctr_done_comb <= '1' when (addr_ctr = x"e") else '0';\r
-\r
-THE_SYNC_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- ctr_done <= ctr_done_comb;\r
- wr_select_q <= wr_select;\r
- wr_select <= wr_select_comb;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
--- generate combinatorial write select signals, register and delay the (output registers in EBR!)\r
-wr_select_comb(0) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"0") ) else '0'; -- dest MAC low\r
-wr_select_comb(1) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"1") ) else '0'; -- dest MAC high\r
-wr_select_comb(2) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"2") ) else '0'; -- dest IP \r
-wr_select_comb(3) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"3") ) else '0'; -- dest port\r
-wr_select_comb(4) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"4") ) else '0'; -- src MAC low\r
-wr_select_comb(5) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"5") ) else '0'; -- src MAC high\r
-wr_select_comb(6) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"6") ) else '0'; -- src IP\r
-wr_select_comb(7) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"7") ) else '0'; -- src port\r
-wr_select_comb(8) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"8") ) else '0'; -- MTU\r
-wr_select_comb(9) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"9") ) else '0';\r
-wr_select_comb(10) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"a") ) else '0';\r
-wr_select_comb(11) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"b") ) else '0';\r
-wr_select_comb(12) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"c") ) else '0';\r
-wr_select_comb(13) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"d") ) else '0';\r
-wr_select_comb(14) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"e") ) else '0';\r
-wr_select_comb(15) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"f") ) else '0';\r
-\r
--- destination MAC low register\r
-THE_D_MAC_LOW_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- dest_mac(31 downto 0) <= (others => '0');\r
- elsif( wr_select_q(0) = '1') then\r
- dest_mac(31 downto 0) <= mem_data_in;\r
- end if;\r
- end if;\r
-end process THE_D_MAC_LOW_PROC;\r
-\r
--- destination MAC high register\r
-THE_D_MAC_HIGH_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- dest_mac(47 downto 32) <= (others => '0');\r
- elsif( wr_select_q(1) = '1') then\r
- dest_mac(47 downto 32) <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_D_MAC_HIGH_PROC;\r
-\r
--- destination IP register\r
-THE_D_IP_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- dest_ip <= (others => '0');\r
- elsif( wr_select_q(2) = '1') then\r
- dest_ip <= mem_data_in;\r
- end if;\r
- end if;\r
-end process THE_D_IP_PROC;\r
-\r
--- destination PORT register\r
-THE_D_PORT_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- dest_udp <= (others => '0');\r
- elsif( wr_select_q(3) = '1') then\r
- dest_udp <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_D_PORT_PROC;\r
-\r
--- source MAC low register\r
-THE_S_MAC_LOW_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- src_mac(31 downto 0) <= (others => '0');\r
- elsif( wr_select_q(4) = '1') then\r
- src_mac(31 downto 0) <= mem_data_in;\r
- end if;\r
- end if;\r
-end process THE_S_MAC_LOW_PROC;\r
-\r
--- source MAC high register\r
-THE_S_MAC_HIGH_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- src_mac(47 downto 32) <= (others => '0');\r
- elsif( wr_select_q(5) = '1') then\r
- src_mac(47 downto 32) <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_S_MAC_HIGH_PROC;\r
-\r
--- source IP register\r
-THE_S_IP_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- src_ip <= (others => '0');\r
- elsif( wr_select_q(6) = '1') then\r
- src_ip <= mem_data_in;\r
- end if;\r
- end if;\r
-end process THE_S_IP_PROC;\r
-\r
--- source PORT register\r
-THE_S_PORT_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- src_udp <= (others => '0');\r
- elsif( wr_select_q(7) = '1') then\r
- src_udp <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_S_PORT_PROC;\r
-\r
--- MTU size register\r
-THE_MTU_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- mtu <= (others => '0');\r
- elsif( wr_select_q(8) = '1') then\r
- mtu <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_MTU_PROC;\r
-\r
-\r
--- Debug signals\r
-debug(31 downto 12) <= (others => '0');\r
-debug(11 downto 8) <= addr_ctr;\r
-debug(7) <= '0';\r
-debug(6) <= ctr_done;\r
-debug(5) <= ce_ctr;\r
-debug(4) <= rst_ctr;\r
-debug(3 downto 0) <= bsm;\r
--- Outputs\r
-MEM_ADDR_OUT(7 downto 4) <= BANK_SELECT_IN;\r
-MEM_ADDR_OUT(3 downto 0) <= addr_ctr;\r
-MEM_CLK_OUT <= CLK;\r
-CONFIG_DONE_OUT <= cfg_done;\r
-\r
--- destination MAC address - swap for user convinience\r
-DEST_MAC_OUT(47 downto 40) <= dest_mac(7 downto 0);\r
-DEST_MAC_OUT(39 downto 32) <= dest_mac(15 downto 8);\r
-DEST_MAC_OUT(31 downto 24) <= dest_mac(23 downto 16);\r
-DEST_MAC_OUT(23 downto 16) <= dest_mac(31 downto 24);\r
-DEST_MAC_OUT(15 downto 8) <= dest_mac(39 downto 32);\r
-DEST_MAC_OUT(7 downto 0) <= dest_mac(47 downto 40);\r
-\r
--- destination IP address - swap for user convinience\r
-DEST_IP_OUT(31 downto 24) <= dest_ip(7 downto 0);\r
-DEST_IP_OUT(23 downto 16) <= dest_ip(15 downto 8);\r
-DEST_IP_OUT(15 downto 8) <= dest_ip(23 downto 16);\r
-DEST_IP_OUT(7 downto 0) <= dest_ip(31 downto 24);\r
-\r
--- destination port address - swap for user convinience\r
-DEST_UDP_OUT(15 downto 8) <= dest_udp(7 downto 0);\r
-DEST_UDP_OUT(7 downto 0) <= dest_udp(15 downto 8);\r
-\r
--- source MAC address - swap for user convinience\r
-SRC_MAC_OUT(47 downto 40) <= src_mac(7 downto 0);\r
-SRC_MAC_OUT(39 downto 32) <= src_mac(15 downto 8);\r
-SRC_MAC_OUT(31 downto 24) <= src_mac(23 downto 16);\r
-SRC_MAC_OUT(23 downto 16) <= src_mac(31 downto 24);\r
-SRC_MAC_OUT(15 downto 8) <= src_mac(39 downto 32);\r
-SRC_MAC_OUT(7 downto 0) <= src_mac(47 downto 40);\r
-\r
--- source IP address - swap for user convinience\r
-SRC_IP_OUT(31 downto 24) <= src_ip(7 downto 0);\r
-SRC_IP_OUT(23 downto 16) <= src_ip(15 downto 8);\r
-SRC_IP_OUT(15 downto 8) <= src_ip(23 downto 16);\r
-SRC_IP_OUT(7 downto 0) <= src_ip(31 downto 24);\r
-\r
--- source port address - swap for user convinience\r
-SRC_UDP_OUT(15 downto 8) <= src_udp(7 downto 0);\r
-SRC_UDP_OUT(7 downto 0) <= src_udp(15 downto 8);\r
-\r
--- DO NOT SWAP!\r
-MTU_OUT <= mtu;\r
-\r
-DEBUG_OUT <= debug;\r
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 5.2
---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 16 -depth 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -e
-
--- Wed Jul 21 14:35:10 2010
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity debug_fifo_2kx16 is
- port (
- Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(15 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end debug_fifo_2kx16;
-
-architecture Structure of debug_fifo_2kx16 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5: std_logic;
- signal wcount_11: std_logic;
- signal co4: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5_1: std_logic;
- signal rcount_11: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_10: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_10: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
- attribute initval of LUT4_31 : label is "0x6996";
- attribute initval of LUT4_30 : label is "0x6996";
- attribute initval of LUT4_29 : label is "0x6996";
- attribute initval of LUT4_28 : label is "0x6996";
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "debug_fifo_2kx16.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL";
- attribute GSR of pdp_ram_0_0_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "debug_fifo_2kx16.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute CSDECODE_B of pdp_ram_0_1_0 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_1_0 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_1_0 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_1_0 : label is "NORMAL";
- attribute GSR of pdp_ram_0_1_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_1_0 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_1_0 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_1_0 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_0_1_0 : label is "9";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t24: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t23: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t22: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t21: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t9: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t8: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t7: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t6: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t5: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t4: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t3: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t2: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t1: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t0: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- LUT4_31: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5),
- DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(9),
- DOB1=>Q(10), DOB2=>Q(11), DOB3=>Q(12), DOB4=>Q(13),
- DOB5=>Q(14), DOB6=>Q(15), DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_121: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_120: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_119: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_118: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_117: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_116: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_115: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_114: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_113: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_112: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_111: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_110: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_109: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_108: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_107: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_106: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_105: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_104: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_103: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_102: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_101: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_85: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_71: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_61: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_60: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_59: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_58: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_57: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_56: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_55: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_54: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_53: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_52: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_51: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_50: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10,
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10,
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of debug_fifo_2kx16 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
--- Module Version: 5.4
---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 8 -depth 16384 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Mon Dec 6 19:08:10 2010
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity fifo_16kx8 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_16kx8;
-
-architecture Structure of fifo_16kx8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal co7: std_logic;
- signal wcount_14: std_logic;
- signal co6: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal co7_1: std_logic;
- signal rcount_14: std_logic;
- signal co6_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal wcount_r12: std_logic;
- signal wcount_r13: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal rcount_w12: std_logic;
- signal rcount_w13: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
- attribute initval of LUT4_41 : label is "0x6996";
- attribute initval of LUT4_40 : label is "0x6996";
- attribute initval of LUT4_39 : label is "0x6996";
- attribute initval of LUT4_38 : label is "0x6996";
- attribute initval of LUT4_37 : label is "0x6996";
- attribute initval of LUT4_36 : label is "0x6996";
- attribute initval of LUT4_35 : label is "0x6996";
- attribute initval of LUT4_34 : label is "0x6996";
- attribute initval of LUT4_33 : label is "0x6996";
- attribute initval of LUT4_32 : label is "0x6996";
- attribute initval of LUT4_31 : label is "0x6996";
- attribute initval of LUT4_30 : label is "0x6996";
- attribute initval of LUT4_29 : label is "0x6996";
- attribute initval of LUT4_28 : label is "0x6996";
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
- attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL";
- attribute GSR of pdp_ram_0_0_7 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
- attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL";
- attribute GSR of pdp_ram_0_1_6 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is "";
- attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL";
- attribute GSR of pdp_ram_0_2_5 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is "";
- attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL";
- attribute GSR of pdp_ram_0_3_4 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is "";
- attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL";
- attribute GSR of pdp_ram_0_4_3 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is "";
- attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL";
- attribute GSR of pdp_ram_0_5_2 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is "";
- attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL";
- attribute GSR of pdp_ram_0_6_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is "";
- attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL";
- attribute GSR of pdp_ram_0_7_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "1";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t30: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t29: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t28: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t27: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t26: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t25: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t24: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t23: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t22: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t21: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t20: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t19: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t18: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t17: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t16: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t15: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t14: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t13: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t12: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t11: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t10: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t9: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t8: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t7: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t6: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t5: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t4: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t3: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t2: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t1: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t0: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- LUT4_41: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>w_gcount_r214,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_40: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>w_gcount_r210,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_39: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_gcount_r26,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_38: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_37: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>scuba_vlo, DO0=>wcount_r12);
-
- LUT4_36: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_35: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9);
-
- LUT4_34: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r8);
-
- LUT4_33: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_32: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r6);
-
- LUT4_31: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>wcount_r5);
-
- LUT4_30: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_29: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_28: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r22, DO0=>wcount_r2);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r1);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r0);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>r_gcount_w214,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>r_gcount_w210,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_gcount_w26,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w13);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>scuba_vlo, DO0=>rcount_w12);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w8);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w25, AD0=>r_gcount_w26, DO0=>rcount_w5);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w22, DO0=>rcount_w2);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_7: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(0), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_1_6: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(1), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_2_5: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(2), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_3_4: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(3), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_4_3: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(4), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_5_2: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(5), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_6_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(6), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_7_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(7), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- FF_151: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_150: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_149: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_148: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_147: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_146: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_145: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_144: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_143: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_142: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_141: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_140: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_139: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_138: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_137: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_136: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_135: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_134: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_133: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_132: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_131: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_130: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_129: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_128: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_127: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_126: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_125: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_124: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_123: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_122: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_121: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_120: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_119: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_118: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_117: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_116: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_115: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_114: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_113: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_112: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_111: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_110: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_109: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_108: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_107: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_106: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_105: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_104: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_103: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_102: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_101: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_85: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_71: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_61: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_60: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_59: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_58: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_57: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_56: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_55: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_54: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_53: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_52: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_51: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_50: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7,
- NC0=>iwcount_14, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_1,
- NC0=>ircount_14, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>w_g2b_xor_cluster_0, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12,
- B1=>wcount_r13, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co6_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>r_g2b_xor_cluster_0, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12,
- B1=>rcount_w13, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co6_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of fifo_16kx8 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_2048x8
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:23:58
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=2048
-Width=8
-RDepth=2048
-RWidth=8
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Sat Dec 26 00:12:59 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_2048x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e \r
- Circuit name : fifo_2048x8\r
- Module type : ebfifo\r
- Module Version : 5.2\r
- Ports : \r
- Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
- Outputs : Q[7:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_2048x8.vhd\r
- VHDL template : fifo_2048x8_tmpl.vhd\r
- VHDL testbench : tb_fifo_2048x8_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_2048x8.srp\r
- Element Usage :\r
- AGEB2 : 12\r
- AND2 : 2\r
- CU2 : 12\r
- FADD2B : 6\r
- FD1P3BX : 2\r
- FD1P3DX : 70\r
- FD1S3BX : 1\r
- FD1S3DX : 49\r
- INV : 2\r
- OR2 : 1\r
- ROM16X1 : 32\r
- XOR2 : 22\r
- DP16KB : 1\r
- Estimated Resource Usage:\r
- LUT : 117\r
- EBR : 1\r
- Reg : 122\r
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:23:58 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_2048x8 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_2048x8;
-
-architecture Structure of fifo_2048x8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5: std_logic;
- signal wcount_11: std_logic;
- signal co4: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5_1: std_logic;
- signal rcount_11: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_10: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_10: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t24: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t23: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t22: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t21: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t9: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t8: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t7: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t6: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t5: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t4: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t3: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t2: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t1: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t0: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2),
- DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7),
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_121: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_119: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_118: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_117: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_116: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_115: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_114: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_113: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_112: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_111: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_110: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_107: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_106: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_105: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_104: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_103: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_102: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_101: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_100: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_99: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_98: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_97: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_96: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_95: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_94: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_93: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_92: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_91: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_90: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_89: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_88: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_87: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_86: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_85: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_84: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_83: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_82: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_81: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_80: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_79: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_78: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_77: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_76: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_75: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_74: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_66: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_65: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_64: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_63: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_62: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_61: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_60: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_59: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_58: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_57: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_56: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_55: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_54: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_53: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_52: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_51: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_50: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10,
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10,
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_2048x8 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Sat Dec 26 00:12:59 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_2048x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e \r
- Circuit name : fifo_2048x8\r
- Module type : ebfifo\r
- Module Version : 5.2\r
- Ports : \r
- Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
- Outputs : Q[7:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_2048x8.vhd\r
- VHDL template : fifo_2048x8_tmpl.vhd\r
- VHDL testbench : tb_fifo_2048x8_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_2048x8.srp\r
- Estimated Resource Usage:\r
- LUT : 117\r
- EBR : 1\r
- Reg : 122\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: fifo_2048x8.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:23:58 2011
-
--- parameterized module component declaration
-component fifo_2048x8
- port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_2048x8
- port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-MODULE fifo_32kx16x8_mb DEFIN fifo_32kx16x8_mb.vhd\r
- SUBMODULE FADD2B\r
- INSTANCE a3\r
- SUBMODULE VLO\r
- INSTANCE scuba_vlo_inst\r
- SUBMODULE AGEB2\r
- INSTANCE af_d_cmp_7\r
- SUBMODULE AGEB2\r
- INSTANCE af_d_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE af_d_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE af_d_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE af_d_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE af_d_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE af_d_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE af_d_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE af_d_cmp_ci_a\r
- SUBMODULE FADD2B\r
- INSTANCE a2\r
- SUBMODULE AGEB2\r
- INSTANCE ae_cmp_8\r
- SUBMODULE AGEB2\r
- INSTANCE ae_cmp_7\r
- SUBMODULE AGEB2\r
- INSTANCE ae_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE ae_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE ae_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE ae_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE ae_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE ae_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE ae_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE ae_cmp_ci_a\r
- SUBMODULE FADD2B\r
- INSTANCE a1\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_7\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE full_cmp_ci_a\r
- SUBMODULE FADD2B\r
- INSTANCE a0\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_8\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_7\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE empty_cmp_ci_a\r
- SUBMODULE FADD2B\r
- INSTANCE rfilld\r
- SUBMODULE FSUB2B\r
- INSTANCE rfill_8\r
- SUBMODULE FSUB2B\r
- INSTANCE rfill_7\r
- SUBMODULE FSUB2B\r
- INSTANCE rfill_6\r
- SUBMODULE FSUB2B\r
- INSTANCE rfill_5\r
- SUBMODULE FSUB2B\r
- INSTANCE rfill_4\r
- SUBMODULE FSUB2B\r
- INSTANCE rfill_3\r
- SUBMODULE FSUB2B\r
- INSTANCE rfill_2\r
- SUBMODULE FSUB2B\r
- INSTANCE rfill_1\r
- SUBMODULE FSUB2B\r
- INSTANCE rfill_0\r
- SUBMODULE VHI\r
- INSTANCE scuba_vhi_inst\r
- SUBMODULE FSUB2B\r
- INSTANCE wfill_8\r
- SUBMODULE FSUB2B\r
- INSTANCE wfill_7\r
- SUBMODULE FSUB2B\r
- INSTANCE wfill_6\r
- SUBMODULE FSUB2B\r
- INSTANCE wfill_5\r
- SUBMODULE FSUB2B\r
- INSTANCE wfill_4\r
- SUBMODULE FSUB2B\r
- INSTANCE wfill_3\r
- SUBMODULE FSUB2B\r
- INSTANCE wfill_2\r
- SUBMODULE FSUB2B\r
- INSTANCE wfill_1\r
- SUBMODULE FSUB2B\r
- INSTANCE wfill_0\r
- SUBMODULE FADD2B\r
- INSTANCE rcntd\r
- SUBMODULE FSUB2B\r
- INSTANCE rcnt_8\r
- SUBMODULE FSUB2B\r
- INSTANCE rcnt_7\r
- SUBMODULE FSUB2B\r
- INSTANCE rcnt_6\r
- SUBMODULE FSUB2B\r
- INSTANCE rcnt_5\r
- SUBMODULE FSUB2B\r
- INSTANCE rcnt_4\r
- SUBMODULE FSUB2B\r
- INSTANCE rcnt_3\r
- SUBMODULE FSUB2B\r
- INSTANCE rcnt_2\r
- SUBMODULE FSUB2B\r
- INSTANCE rcnt_1\r
- SUBMODULE FSUB2B\r
- INSTANCE rcnt_0\r
- SUBMODULE FSUB2B\r
- INSTANCE wcnt_8\r
- SUBMODULE FSUB2B\r
- INSTANCE wcnt_7\r
- SUBMODULE FSUB2B\r
- INSTANCE wcnt_6\r
- SUBMODULE FSUB2B\r
- INSTANCE wcnt_5\r
- SUBMODULE FSUB2B\r
- INSTANCE wcnt_4\r
- SUBMODULE FSUB2B\r
- INSTANCE wcnt_3\r
- SUBMODULE FSUB2B\r
- INSTANCE wcnt_2\r
- SUBMODULE FSUB2B\r
- INSTANCE wcnt_1\r
- SUBMODULE FSUB2B\r
- INSTANCE wcnt_0\r
- SUBMODULE MUX41\r
- INSTANCE mux_0\r
- SUBMODULE MUX41\r
- INSTANCE mux_1\r
- SUBMODULE MUX41\r
- INSTANCE mux_2\r
- SUBMODULE MUX41\r
- INSTANCE mux_3\r
- SUBMODULE MUX41\r
- INSTANCE mux_4\r
- SUBMODULE MUX41\r
- INSTANCE mux_5\r
- SUBMODULE MUX41\r
- INSTANCE mux_6\r
- SUBMODULE MUX41\r
- INSTANCE mux_7\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_8\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_7\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_6\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_5\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_4\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_3\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_2\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_1\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_0\r
- SUBMODULE FADD2B\r
- INSTANCE r_gctr_cia\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_7\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_6\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_5\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_4\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_3\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_2\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_1\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_0\r
- SUBMODULE FADD2B\r
- INSTANCE w_gctr_cia\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_0\r
- SUBMODULE FD1S3BX\r
- INSTANCE FF_1\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_2\r
- SUBMODULE FD1S3BX\r
- INSTANCE FF_3\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_4\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_5\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_6\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_7\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_8\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_9\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_10\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_11\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_12\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_13\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_14\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_15\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_16\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_17\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_18\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_19\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_20\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_21\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_22\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_23\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_24\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_25\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_26\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_27\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_28\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_29\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_30\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_31\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_32\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_33\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_34\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_35\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_36\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_37\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_38\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_39\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_40\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_41\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_42\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_43\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_44\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_45\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_46\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_47\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_48\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_49\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_50\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_51\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_52\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_53\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_54\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_55\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_56\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_57\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_58\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_59\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_60\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_61\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_62\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_63\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_64\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_65\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_66\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_67\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_68\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_69\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_70\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_71\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_72\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_73\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_74\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_75\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_76\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_77\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_78\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_79\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_80\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_81\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_82\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_83\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_84\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_85\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_86\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_87\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_88\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_89\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_90\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_91\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_92\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_93\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_94\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_95\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_96\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_97\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_98\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_99\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_100\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_101\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_102\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_103\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_104\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_105\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_106\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_107\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_108\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_109\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_110\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_111\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_112\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_113\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_114\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_115\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_116\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_117\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_118\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_119\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_120\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_121\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_122\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_123\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_124\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_125\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_126\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_127\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_128\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_129\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_130\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_131\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_132\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_133\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_134\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_135\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_136\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_137\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_138\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_139\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_140\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_141\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_142\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_143\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_144\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_145\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_146\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_147\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_148\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_149\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_150\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_151\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_152\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_153\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_154\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_155\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_156\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_157\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_158\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_159\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_160\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_161\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_162\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_163\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_164\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_165\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_166\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_167\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_168\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_169\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_170\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_171\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_172\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_173\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_174\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_175\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_176\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_177\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_178\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_179\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_180\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_181\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_182\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_183\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_184\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_185\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_186\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_187\r
- SUBMODULE FD1P3BX\r
- INSTANCE FF_188\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_189\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_190\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_191\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_192\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_193\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_194\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_195\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_196\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_197\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_198\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_199\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_200\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_201\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_202\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_203\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_204\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_205\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_206\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_207\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_208\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_209\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_210\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_211\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_212\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_213\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_214\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_215\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_216\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_217\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_218\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_219\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_220\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_221\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_222\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_223\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_224\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_225\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_226\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_227\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_228\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_229\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_230\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_231\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_232\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_233\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_234\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_235\r
- SUBMODULE FD1P3BX\r
- INSTANCE FF_236\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_7_0\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_6_1\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_5_2\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_4_3\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_3_4\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_2_5\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_1_6\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_0_7\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_7_8\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_6_9\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_5_10\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_4_11\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_3_12\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_2_13\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_1_14\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_0_15\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_7_16\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_6_17\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_5_18\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_4_19\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_3_20\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_2_21\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_1_22\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_0_23\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_7_24\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_6_25\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_5_26\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_4_27\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_3_28\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_2_29\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_1_30\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_0_31\r
- SUBMODULE AND2\r
- INSTANCE AND2_t0\r
- SUBMODULE AND2\r
- INSTANCE AND2_t1\r
- SUBMODULE INV\r
- INSTANCE INV_0\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_0\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_1\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_2\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_3\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t2\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t3\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t4\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t5\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_4\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_5\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_6\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_7\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_8\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_9\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_10\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_11\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_12\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_13\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_14\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_15\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_16\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_17\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_18\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_19\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_20\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_21\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_22\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_23\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_24\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_25\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_26\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_27\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_28\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_29\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_30\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_31\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_32\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_33\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_34\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_35\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_36\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_37\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_38\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_39\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_40\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_41\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_42\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_43\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_44\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_45\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_46\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_47\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_48\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_49\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_50\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_51\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_52\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t6\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t7\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t8\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t9\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t10\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t11\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t12\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t13\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t14\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t15\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t16\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t17\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t18\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t19\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t20\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t21\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t22\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t23\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t24\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t25\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t26\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t27\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t28\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t29\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t30\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t31\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t32\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t33\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t34\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t35\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t36\r
- SUBMODULE OR2\r
- INSTANCE OR2_t37\r
- SUBMODULE INV\r
- INSTANCE INV_1\r
- SUBMODULE AND2\r
- INSTANCE AND2_t38\r
- SUBMODULE INV\r
- INSTANCE INV_2\r
- SUBMODULE AND2\r
- INSTANCE AND2_t39\r
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_32kx16x8_mb
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:22:35
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=32768
-Width=16
-RDepth=65536
-RWidth=8
-regout=0
-CtrlByRdEn=0
-EmpFlg=1
-PeMode=Dynamic - Single Threshold
-PeAssert=16
-PeDeassert=12
-FullFlg=1
-PfMode=Dynamic - Single Threshold
-PfAssert=32752
-PfDeassert=506
-RDataCount=1
-WDataCount=1
-EnECC=0
+++ /dev/null
-Data[15] i\r
-Data[14] i\r
-Data[13] i\r
-Data[12] i\r
-Data[11] i\r
-Data[10] i\r
-Data[9] i\r
-Data[8] i\r
-Data[7] i\r
-Data[6] i\r
-Data[5] i\r
-Data[4] i\r
-Data[3] i\r
-Data[2] i\r
-Data[1] i\r
-Data[0] i\r
-WrClock i\r
-RdClock i\r
-WrEn i\r
-RdEn i\r
-Reset i\r
-RPReset i\r
-AmEmptyThresh[15] i\r
-AmEmptyThresh[14] i\r
-AmEmptyThresh[13] i\r
-AmEmptyThresh[12] i\r
-AmEmptyThresh[11] i\r
-AmEmptyThresh[10] i\r
-AmEmptyThresh[9] i\r
-AmEmptyThresh[8] i\r
-AmEmptyThresh[7] i\r
-AmEmptyThresh[6] i\r
-AmEmptyThresh[5] i\r
-AmEmptyThresh[4] i\r
-AmEmptyThresh[3] i\r
-AmEmptyThresh[2] i\r
-AmEmptyThresh[1] i\r
-AmEmptyThresh[0] i\r
-AmFullThresh[14] i\r
-AmFullThresh[13] i\r
-AmFullThresh[12] i\r
-AmFullThresh[11] i\r
-AmFullThresh[10] i\r
-AmFullThresh[9] i\r
-AmFullThresh[8] i\r
-AmFullThresh[7] i\r
-AmFullThresh[6] i\r
-AmFullThresh[5] i\r
-AmFullThresh[4] i\r
-AmFullThresh[3] i\r
-AmFullThresh[2] i\r
-AmFullThresh[1] i\r
-AmFullThresh[0] i\r
-Q[7] o\r
-Q[6] o\r
-Q[5] o\r
-Q[4] o\r
-Q[3] o\r
-Q[2] o\r
-Q[1] o\r
-Q[0] o\r
-WCNT[15] o\r
-WCNT[14] o\r
-WCNT[13] o\r
-WCNT[12] o\r
-WCNT[11] o\r
-WCNT[10] o\r
-WCNT[9] o\r
-WCNT[8] o\r
-WCNT[7] o\r
-WCNT[6] o\r
-WCNT[5] o\r
-WCNT[4] o\r
-WCNT[3] o\r
-WCNT[2] o\r
-WCNT[1] o\r
-WCNT[0] o\r
-RCNT[16] o\r
-RCNT[15] o\r
-RCNT[14] o\r
-RCNT[13] o\r
-RCNT[12] o\r
-RCNT[11] o\r
-RCNT[10] o\r
-RCNT[9] o\r
-RCNT[8] o\r
-RCNT[7] o\r
-RCNT[6] o\r
-RCNT[5] o\r
-RCNT[4] o\r
-RCNT[3] o\r
-RCNT[2] o\r
-RCNT[1] o\r
-RCNT[0] o\r
-Empty o\r
-Full o\r
-AlmostEmpty o\r
-AlmostFull o\r
+++ /dev/null
-SCUBA, Version ispLever_v8.0_PROD_Build (41)
-Fri Feb 05 16:48:12 2010
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_32kx16x8_mb -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 16 -num_words 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e
- Circuit name : fifo_32kx16x8_mb
- Module type : ebfifo
- Module Version : 5.3
- Ports :
- Inputs : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]
- Outputs : Q[7:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_32kx16x8_mb.vhd
- VHDL template : fifo_32kx16x8_mb_tmpl.vhd
- VHDL testbench : tb_fifo_32kx16x8_mb_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_32kx16x8_mb.srp
- Element Usage :
- AGEB2 : 34
- AND2 : 4
- CU2 : 17
- FADD2B : 12
- FSUB2B : 36
- FD1P3BX : 2
- FD1P3DX : 99
- FD1S3BX : 2
- FD1S3DX : 134
- INV : 3
- MUX41 : 8
- OR2 : 1
- ROM16X1 : 53
- XOR2 : 35
- DP16KB : 32
- Estimated Resource Usage:
- LUT : 299
- EBR : 32
- Reg : 237
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e
-
--- Thu Sep 22 11:22:35 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_32kx16x8_mb is
- port (
- Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(7 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end fifo_32kx16x8_mb;
-
-architecture Structure of fifo_32kx16x8_mb is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal rcount_w0: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal rcnt_reg_15_inv: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal wptr_15: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_16: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal rcnt_reg_16: std_logic;
- signal empty_i: std_logic;
- signal full_i: std_logic;
- signal rRst: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co7: std_logic;
- signal wcount_15: std_logic;
- signal co6: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal wcnt_sub_0: std_logic;
- signal wcnt_sub_1: std_logic;
- signal wcnt_sub_2: std_logic;
- signal co0_2: std_logic;
- signal wcnt_sub_3: std_logic;
- signal wcnt_sub_4: std_logic;
- signal co1_2: std_logic;
- signal wcnt_sub_5: std_logic;
- signal wcnt_sub_6: std_logic;
- signal co2_2: std_logic;
- signal wcnt_sub_7: std_logic;
- signal wcnt_sub_8: std_logic;
- signal co3_2: std_logic;
- signal wcnt_sub_9: std_logic;
- signal wcnt_sub_10: std_logic;
- signal co4_2: std_logic;
- signal wcnt_sub_11: std_logic;
- signal wcnt_sub_12: std_logic;
- signal co5_2: std_logic;
- signal wcnt_sub_13: std_logic;
- signal wcnt_sub_14: std_logic;
- signal co6_2: std_logic;
- signal wcnt_sub_15: std_logic;
- signal co7_2: std_logic;
- signal wcnt_sub_msb: std_logic;
- signal rcnt_sub_0: std_logic;
- signal rcnt_sub_1: std_logic;
- signal rcnt_sub_2: std_logic;
- signal co0_3: std_logic;
- signal rcnt_sub_3: std_logic;
- signal rcnt_sub_4: std_logic;
- signal co1_3: std_logic;
- signal rcnt_sub_5: std_logic;
- signal rcnt_sub_6: std_logic;
- signal co2_3: std_logic;
- signal rcnt_sub_7: std_logic;
- signal rcnt_sub_8: std_logic;
- signal co3_3: std_logic;
- signal rcnt_sub_9: std_logic;
- signal rcnt_sub_10: std_logic;
- signal co4_3: std_logic;
- signal rcnt_sub_11: std_logic;
- signal rcnt_sub_12: std_logic;
- signal co5_3: std_logic;
- signal rcnt_sub_13: std_logic;
- signal rcnt_sub_14: std_logic;
- signal co6_3: std_logic;
- signal rcnt_sub_15: std_logic;
- signal rcnt_sub_16: std_logic;
- signal co7_3: std_logic;
- signal rcnt_sub_msb: std_logic;
- signal co8_1d: std_logic;
- signal co8_1: std_logic;
- signal wfill_sub_0: std_logic;
- signal wptr_0: std_logic;
- signal wfill_sub_1: std_logic;
- signal wfill_sub_2: std_logic;
- signal co0_4: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wfill_sub_3: std_logic;
- signal wfill_sub_4: std_logic;
- signal co1_4: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wfill_sub_5: std_logic;
- signal wfill_sub_6: std_logic;
- signal co2_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wfill_sub_7: std_logic;
- signal wfill_sub_8: std_logic;
- signal co3_4: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wfill_sub_9: std_logic;
- signal wfill_sub_10: std_logic;
- signal co4_4: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wfill_sub_11: std_logic;
- signal wfill_sub_12: std_logic;
- signal co5_4: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wfill_sub_13: std_logic;
- signal wfill_sub_14: std_logic;
- signal co6_4: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wfill_sub_15: std_logic;
- signal co7_4: std_logic;
- signal wfill_sub_msb: std_logic;
- signal rfill_sub_0: std_logic;
- signal rptr_0: std_logic;
- signal scuba_vhi: std_logic;
- signal rfill_sub_1: std_logic;
- signal rfill_sub_2: std_logic;
- signal co0_5: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rfill_sub_3: std_logic;
- signal rfill_sub_4: std_logic;
- signal co1_5: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rfill_sub_5: std_logic;
- signal rfill_sub_6: std_logic;
- signal co2_5: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rfill_sub_7: std_logic;
- signal rfill_sub_8: std_logic;
- signal co3_5: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rfill_sub_9: std_logic;
- signal rfill_sub_10: std_logic;
- signal co4_5: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rfill_sub_11: std_logic;
- signal rfill_sub_12: std_logic;
- signal co5_5: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rfill_sub_13: std_logic;
- signal rfill_sub_14: std_logic;
- signal co6_5: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rfill_sub_15: std_logic;
- signal rfill_sub_16: std_logic;
- signal co7_5: std_logic;
- signal rptr_15: std_logic;
- signal rfill_sub_msb: std_logic;
- signal co8_2d: std_logic;
- signal co8_2: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_6: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_6: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_6: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_6: std_logic;
- signal wcount_r7: std_logic;
- signal wcount_r8: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_6: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_6: std_logic;
- signal wcount_r11: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_6: std_logic;
- signal wcount_r13: std_logic;
- signal wcount_r14: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_6: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_7: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_7: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_7: std_logic;
- signal rcount_w7: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_7: std_logic;
- signal rcount_w9: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_7: std_logic;
- signal rcount_w11: std_logic;
- signal rcount_w12: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w14: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_7: std_logic;
- signal rcount_w15: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_14: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal rcnt_reg_0: std_logic;
- signal rcnt_reg_1: std_logic;
- signal co0_8: std_logic;
- signal rcnt_reg_2: std_logic;
- signal rcnt_reg_3: std_logic;
- signal co1_8: std_logic;
- signal rcnt_reg_4: std_logic;
- signal rcnt_reg_5: std_logic;
- signal co2_8: std_logic;
- signal rcnt_reg_6: std_logic;
- signal rcnt_reg_7: std_logic;
- signal co3_8: std_logic;
- signal rcnt_reg_8: std_logic;
- signal rcnt_reg_9: std_logic;
- signal co4_8: std_logic;
- signal rcnt_reg_10: std_logic;
- signal rcnt_reg_11: std_logic;
- signal co5_8: std_logic;
- signal rcnt_reg_12: std_logic;
- signal rcnt_reg_13: std_logic;
- signal co6_8: std_logic;
- signal rcnt_reg_14: std_logic;
- signal rcnt_reg_15: std_logic;
- signal co7_7: std_logic;
- signal ae_clrsig: std_logic;
- signal ae_setsig: std_logic;
- signal ae_d: std_logic;
- signal ae_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_3: std_logic;
- signal wcnt_reg_0: std_logic;
- signal wcnt_reg_1: std_logic;
- signal co0_9: std_logic;
- signal wcnt_reg_2: std_logic;
- signal wcnt_reg_3: std_logic;
- signal co1_9: std_logic;
- signal wcnt_reg_4: std_logic;
- signal wcnt_reg_5: std_logic;
- signal co2_9: std_logic;
- signal wcnt_reg_6: std_logic;
- signal wcnt_reg_7: std_logic;
- signal co3_9: std_logic;
- signal wcnt_reg_8: std_logic;
- signal wcnt_reg_9: std_logic;
- signal co4_9: std_logic;
- signal wcnt_reg_10: std_logic;
- signal wcnt_reg_11: std_logic;
- signal co5_9: std_logic;
- signal wcnt_reg_12: std_logic;
- signal wcnt_reg_13: std_logic;
- signal co6_9: std_logic;
- signal wcnt_reg_14: std_logic;
- signal wcnt_reg_15: std_logic;
- signal af_d: std_logic;
- signal af_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX41
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
- Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is "";
- attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is "";
- attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is "";
- attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is "";
- attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is "";
- attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is "";
- attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is "";
- attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is "";
- attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is "";
- attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is "";
- attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is "";
- attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is "";
- attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is "";
- attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is "";
- attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is "";
- attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is "";
- attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is "";
- attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is "";
- attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is "";
- attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is "";
- attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is "";
- attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is "";
- attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is "";
- attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is "";
- attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is "";
- attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is "";
- attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is "";
- attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is "";
- attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is "";
- attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is "";
- attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is "";
- attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC";
- attribute GSR of FF_236 : label is "ENABLED";
- attribute GSR of FF_235 : label is "ENABLED";
- attribute GSR of FF_234 : label is "ENABLED";
- attribute GSR of FF_233 : label is "ENABLED";
- attribute GSR of FF_232 : label is "ENABLED";
- attribute GSR of FF_231 : label is "ENABLED";
- attribute GSR of FF_230 : label is "ENABLED";
- attribute GSR of FF_229 : label is "ENABLED";
- attribute GSR of FF_228 : label is "ENABLED";
- attribute GSR of FF_227 : label is "ENABLED";
- attribute GSR of FF_226 : label is "ENABLED";
- attribute GSR of FF_225 : label is "ENABLED";
- attribute GSR of FF_224 : label is "ENABLED";
- attribute GSR of FF_223 : label is "ENABLED";
- attribute GSR of FF_222 : label is "ENABLED";
- attribute GSR of FF_221 : label is "ENABLED";
- attribute GSR of FF_220 : label is "ENABLED";
- attribute GSR of FF_219 : label is "ENABLED";
- attribute GSR of FF_218 : label is "ENABLED";
- attribute GSR of FF_217 : label is "ENABLED";
- attribute GSR of FF_216 : label is "ENABLED";
- attribute GSR of FF_215 : label is "ENABLED";
- attribute GSR of FF_214 : label is "ENABLED";
- attribute GSR of FF_213 : label is "ENABLED";
- attribute GSR of FF_212 : label is "ENABLED";
- attribute GSR of FF_211 : label is "ENABLED";
- attribute GSR of FF_210 : label is "ENABLED";
- attribute GSR of FF_209 : label is "ENABLED";
- attribute GSR of FF_208 : label is "ENABLED";
- attribute GSR of FF_207 : label is "ENABLED";
- attribute GSR of FF_206 : label is "ENABLED";
- attribute GSR of FF_205 : label is "ENABLED";
- attribute GSR of FF_204 : label is "ENABLED";
- attribute GSR of FF_203 : label is "ENABLED";
- attribute GSR of FF_202 : label is "ENABLED";
- attribute GSR of FF_201 : label is "ENABLED";
- attribute GSR of FF_200 : label is "ENABLED";
- attribute GSR of FF_199 : label is "ENABLED";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t39: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_2: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t38: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_1: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t37: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t36: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t35: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t34: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t33: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t32: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t31: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t30: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t29: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t28: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t27: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t26: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t25: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t24: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t23: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t22: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t21: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t9: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t8: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t7: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t6: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r2);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r1);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- XOR2_t5: XOR2
- port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb);
-
- XOR2_t4: XOR2
- port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb);
-
- XOR2_t3: XOR2
- port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb);
-
- XOR2_t2: XOR2
- port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- INV_0: INV
- port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv);
-
- AND2_t1: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig);
-
- AND2_t0: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig);
-
- pdp_ram_0_0_31: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_30: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_2_29: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_3_28: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_4_27: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_5_26: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_6_25: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_7_24: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_23: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_1_22: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_2_21: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_3_20: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_4_19: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_5_18: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_6_17: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_7_16: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_15: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_1_14: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_2_13: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_3_12: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_4_11: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_5_10: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_6_9: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_7_8: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_7: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_1_6: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_2_5: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_3_4: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_4_3: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_5_2: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_6_1: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_7_0: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_236: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_235: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_234: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_233: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_232: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_231: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_230: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_229: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_228: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_227: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_226: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_225: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_224: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_223: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_222: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_221: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_220: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_219: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_218: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_217: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_216: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_215: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_214: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_213: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_212: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_211: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_210: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_209: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_208: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_207: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_206: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_205: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_204: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_203: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_202: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_201: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_200: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_199: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_198: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_197: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_196: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_195: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_194: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_193: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_192: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_191: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_190: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_189: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_188: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_187: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_186: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_185: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_184: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_183: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_182: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_181: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_180: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_179: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_178: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_177: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_176: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_175: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_174: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_173: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_172: FD1P3DX
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_171: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_170: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_169: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_168: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_167: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_166: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_165: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_164: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_163: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_162: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_161: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_160: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_159: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_158: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_157: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_156: FD1P3DX
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_155: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_154: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_153: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_152: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_151: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_150: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_149: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_148: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_147: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_146: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_145: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_144: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_143: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_142: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_141: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_140: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_139: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_138: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_137: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_136: FD1P3DX
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_135: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_134: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_133: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_132: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_131: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_130: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_129: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_128: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_127: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_126: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_125: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_124: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_123: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_122: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_121: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_120: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_119: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_118: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_117: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_116: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_115: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_114: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_113: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_112: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_111: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_110: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_109: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_108: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_107: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_106: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_105: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_104: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_103: FD1S3DX
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_102: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_101: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_100: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_99: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_98: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_97: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_96: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_95: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_94: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_93: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_92: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_91: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_90: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_89: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_88: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_87: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_86: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_85: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_84: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_83: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_82: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_81: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_80: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_79: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_78: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_77: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_76: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_75: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_74: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_73: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_72: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_71: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_70: FD1S3DX
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_69: FD1S3DX
- port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0);
-
- FF_68: FD1S3DX
- port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1);
-
- FF_67: FD1S3DX
- port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2);
-
- FF_66: FD1S3DX
- port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3);
-
- FF_65: FD1S3DX
- port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4);
-
- FF_64: FD1S3DX
- port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5);
-
- FF_63: FD1S3DX
- port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6);
-
- FF_62: FD1S3DX
- port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7);
-
- FF_61: FD1S3DX
- port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8);
-
- FF_60: FD1S3DX
- port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9);
-
- FF_59: FD1S3DX
- port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10);
-
- FF_58: FD1S3DX
- port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11);
-
- FF_57: FD1S3DX
- port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12);
-
- FF_56: FD1S3DX
- port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13);
-
- FF_55: FD1S3DX
- port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14);
-
- FF_54: FD1S3DX
- port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15);
-
- FF_53: FD1S3DX
- port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0);
-
- FF_52: FD1S3DX
- port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1);
-
- FF_51: FD1S3DX
- port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2);
-
- FF_50: FD1S3DX
- port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3);
-
- FF_49: FD1S3DX
- port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4);
-
- FF_48: FD1S3DX
- port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5);
-
- FF_47: FD1S3DX
- port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6);
-
- FF_46: FD1S3DX
- port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7);
-
- FF_45: FD1S3DX
- port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8);
-
- FF_44: FD1S3DX
- port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9);
-
- FF_43: FD1S3DX
- port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10);
-
- FF_42: FD1S3DX
- port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11);
-
- FF_41: FD1S3DX
- port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12);
-
- FF_40: FD1S3DX
- port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13);
-
- FF_39: FD1S3DX
- port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14);
-
- FF_38: FD1S3DX
- port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15);
-
- FF_37: FD1S3DX
- port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16);
-
- FF_36: FD1S3DX
- port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
-
- FF_35: FD1S3DX
- port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
-
- FF_34: FD1S3DX
- port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
-
- FF_33: FD1S3DX
- port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
-
- FF_32: FD1S3DX
- port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
-
- FF_31: FD1S3DX
- port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
-
- FF_30: FD1S3DX
- port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
-
- FF_29: FD1S3DX
- port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
-
- FF_28: FD1S3DX
- port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
-
- FF_27: FD1S3DX
- port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
-
- FF_26: FD1S3DX
- port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
-
- FF_25: FD1S3DX
- port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
-
- FF_24: FD1S3DX
- port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12));
-
- FF_23: FD1S3DX
- port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13));
-
- FF_22: FD1S3DX
- port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14));
-
- FF_21: FD1S3DX
- port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15));
-
- FF_20: FD1S3DX
- port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
-
- FF_19: FD1S3DX
- port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
-
- FF_18: FD1S3DX
- port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
-
- FF_17: FD1S3DX
- port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
-
- FF_16: FD1S3DX
- port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
-
- FF_15: FD1S3DX
- port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
-
- FF_14: FD1S3DX
- port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
-
- FF_13: FD1S3DX
- port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
-
- FF_12: FD1S3DX
- port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
-
- FF_11: FD1S3DX
- port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
-
- FF_10: FD1S3DX
- port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10));
-
- FF_9: FD1S3DX
- port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11));
-
- FF_8: FD1S3DX
- port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12));
-
- FF_7: FD1S3DX
- port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13));
-
- FF_6: FD1S3DX
- port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14));
-
- FF_5: FD1S3DX
- port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15));
-
- FF_4: FD1S3DX
- port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16));
-
- FF_3: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_2: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- FF_1: FD1S3BX
- port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
-
- FF_0: FD1S3DX
- port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>ircount_16, NC1=>open);
-
- mux_7: MUX41
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0));
-
- mux_6: MUX41
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1));
-
- mux_5: MUX41
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2));
-
- mux_4: MUX41
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3));
-
- mux_3: MUX41
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4));
-
- mux_2: MUX41
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5));
-
- mux_1: MUX41
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6));
-
- mux_0: MUX41
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7));
-
- wcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
- S1=>wcnt_sub_0);
-
- wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2,
- B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1,
- S1=>wcnt_sub_2);
-
- wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4,
- B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3,
- S1=>wcnt_sub_4);
-
- wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6,
- B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5,
- S1=>wcnt_sub_6);
-
- wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8,
- B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7,
- S1=>wcnt_sub_8);
-
- wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9,
- S1=>wcnt_sub_10);
-
- wcnt_6: FSUB2B
- port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2,
- S0=>wcnt_sub_11, S1=>wcnt_sub_12);
-
- wcnt_7: FSUB2B
- port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13,
- S1=>wcnt_sub_14);
-
- wcnt_8: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15,
- S1=>open);
-
- rcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open,
- S1=>rcnt_sub_0);
-
- rcnt_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1,
- B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1,
- S1=>rcnt_sub_2);
-
- rcnt_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3,
- B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3,
- S1=>rcnt_sub_4);
-
- rcnt_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5,
- B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5,
- S1=>rcnt_sub_6);
-
- rcnt_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7,
- B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7,
- S1=>rcnt_sub_8);
-
- rcnt_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9,
- B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9,
- S1=>rcnt_sub_10);
-
- rcnt_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11,
- B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11,
- S1=>rcnt_sub_12);
-
- rcnt_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13,
- B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13,
- S1=>rcnt_sub_14);
-
- rcnt_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15,
- B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15,
- S1=>rcnt_sub_16);
-
- rcntd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open);
-
- wfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open,
- S1=>wfill_sub_0);
-
- wfill_1: FSUB2B
- port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3,
- BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2);
-
- wfill_2: FSUB2B
- port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5,
- BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4);
-
- wfill_3: FSUB2B
- port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7,
- BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6);
-
- wfill_4: FSUB2B
- port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9,
- BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8);
-
- wfill_5: FSUB2B
- port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9,
- S1=>wfill_sub_10);
-
- wfill_6: FSUB2B
- port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4,
- S0=>wfill_sub_11, S1=>wfill_sub_12);
-
- wfill_7: FSUB2B
- port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13,
- S1=>wfill_sub_14);
-
- wfill_8: FSUB2B
- port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- rfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
- S1=>rfill_sub_0);
-
- rfill_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2,
- BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2);
-
- rfill_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4,
- BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4);
-
- rfill_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6,
- BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6);
-
- rfill_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8,
- BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8);
-
- rfill_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10,
- BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10);
-
- rfill_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11,
- B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11,
- S1=>rfill_sub_12);
-
- rfill_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13,
- B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13,
- S1=>rfill_sub_14);
-
- rfill_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15,
- B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15,
- S1=>rfill_sub_16);
-
- rfilld: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_6, GE=>co1_6);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_6, GE=>co2_6);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_6, GE=>co3_6);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
- B1=>wcount_r8, CI=>co3_6, GE=>co4_6);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co4_6, GE=>co5_6);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11,
- B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13,
- B1=>wcount_r14, CI=>co6_6, GE=>co7_6);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_7, GE=>co1_7);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_7, GE=>co2_7);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>rcount_w8, CI=>co2_7, GE=>co3_7);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
- B1=>rcount_w10, CI=>co3_7, GE=>co4_7);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11,
- B1=>rcount_w12, CI=>co4_7, GE=>co5_7);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w14, CI=>co5_7, GE=>co6_7);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15,
- B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- ae_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- ae_cmp_0: AGEB2
- port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
- B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8);
-
- ae_cmp_1: AGEB2
- port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
- B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8);
-
- ae_cmp_2: AGEB2
- port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
- B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8);
-
- ae_cmp_3: AGEB2
- port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
- B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8);
-
- ae_cmp_4: AGEB2
- port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9),
- B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8);
-
- ae_cmp_5: AGEB2
- port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11),
- B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8);
-
- ae_cmp_6: AGEB2
- port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13),
- B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8);
-
- ae_cmp_7: AGEB2
- port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15),
- B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7);
-
- ae_cmp_8: AGEB2
- port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig,
- B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
-
- af_d_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
-
- af_d_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
- B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9);
-
- af_d_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
- B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9);
-
- af_d_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
- B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9);
-
- af_d_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
- B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9);
-
- af_d_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
- B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9);
-
- af_d_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
- B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9);
-
- af_d_cmp_6: AGEB2
- port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
- B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9);
-
- af_d_cmp_7: AGEB2
- port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14),
- B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_32kx16x8_mb is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX41 use entity ecp3.MUX41(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_32kx16x8_mb2
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:22:54
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=32768
-Width=18
-RDepth=65536
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=1
-PeMode=Dynamic - Single Threshold
-PeAssert=16
-PeDeassert=12
-FullFlg=1
-PfMode=Dynamic - Single Threshold
-PfAssert=32752
-PfDeassert=506
-RDataCount=1
-WDataCount=1
-EnECC=0
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:22:54 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e
- Circuit name : fifo_32kx16x8_mb2
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]
- Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_32kx16x8_mb2.vhd
- VHDL template : fifo_32kx16x8_mb2_tmpl.vhd
- VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_32kx16x8_mb2.srp
- Element Usage :
- AGEB2 : 34
- AND2 : 4
- CU2 : 17
- FADD2B : 12
- FSUB2B : 36
- FD1P3BX : 2
- FD1P3DX : 102
- FD1S3BX : 2
- FD1S3DX : 134
- INV : 13
- MUX321 : 9
- OR2 : 1
- ROM16X1A : 181
- XOR2 : 35
- DP16KC : 32
- Estimated Resource Usage:
- LUT : 491
- EBR : 32
- Reg : 240
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e
-
--- Thu Sep 22 11:22:54 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_32kx16x8_mb2 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(8 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end fifo_32kx16x8_mb2;
-
-architecture Structure of fifo_32kx16x8_mb2 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal func_and_inet: std_logic;
- signal func_and_inet_1: std_logic;
- signal func_and_inet_2: std_logic;
- signal func_and_inet_3: std_logic;
- signal func_and_inet_4: std_logic;
- signal func_and_inet_5: std_logic;
- signal func_and_inet_6: std_logic;
- signal func_and_inet_7: std_logic;
- signal func_and_inet_8: std_logic;
- signal func_and_inet_9: std_logic;
- signal func_and_inet_10: std_logic;
- signal func_and_inet_11: std_logic;
- signal func_and_inet_12: std_logic;
- signal func_and_inet_13: std_logic;
- signal func_and_inet_14: std_logic;
- signal func_and_inet_15: std_logic;
- signal func_and_inet_16: std_logic;
- signal func_and_inet_17: std_logic;
- signal func_and_inet_18: std_logic;
- signal func_and_inet_19: std_logic;
- signal func_and_inet_20: std_logic;
- signal func_and_inet_21: std_logic;
- signal func_and_inet_22: std_logic;
- signal func_and_inet_23: std_logic;
- signal func_and_inet_24: std_logic;
- signal func_and_inet_25: std_logic;
- signal func_and_inet_26: std_logic;
- signal func_and_inet_27: std_logic;
- signal func_and_inet_28: std_logic;
- signal func_and_inet_29: std_logic;
- signal wptr_14_inv: std_logic;
- signal func_and_inet_30: std_logic;
- signal rptr_15_inv: std_logic;
- signal func_and_inet_31: std_logic;
- signal func_and_inet_32: std_logic;
- signal func_and_inet_33: std_logic;
- signal func_and_inet_34: std_logic;
- signal func_and_inet_35: std_logic;
- signal func_and_inet_36: std_logic;
- signal func_and_inet_37: std_logic;
- signal func_and_inet_38: std_logic;
- signal func_and_inet_39: std_logic;
- signal func_and_inet_40: std_logic;
- signal func_and_inet_41: std_logic;
- signal func_and_inet_42: std_logic;
- signal func_and_inet_43: std_logic;
- signal func_and_inet_44: std_logic;
- signal func_and_inet_45: std_logic;
- signal wptr_13_inv: std_logic;
- signal func_and_inet_46: std_logic;
- signal rptr_14_inv: std_logic;
- signal func_and_inet_47: std_logic;
- signal func_and_inet_48: std_logic;
- signal func_and_inet_49: std_logic;
- signal func_and_inet_50: std_logic;
- signal func_and_inet_51: std_logic;
- signal func_and_inet_52: std_logic;
- signal func_and_inet_53: std_logic;
- signal wptr_12_inv: std_logic;
- signal func_and_inet_54: std_logic;
- signal rptr_13_inv: std_logic;
- signal func_and_inet_55: std_logic;
- signal func_and_inet_56: std_logic;
- signal func_and_inet_57: std_logic;
- signal wptr_11_inv: std_logic;
- signal func_and_inet_58: std_logic;
- signal rptr_12_inv: std_logic;
- signal func_and_inet_59: std_logic;
- signal wptr_10_inv: std_logic;
- signal func_and_inet_60: std_logic;
- signal rptr_11_inv: std_logic;
- signal func_and_inet_61: std_logic;
- signal func_and_inet_62: std_logic;
- signal func_and_inet_63: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal rcount_w0: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal rcnt_reg_15_inv: std_logic;
- signal dec1_r10: std_logic;
- signal dec0_p00: std_logic;
- signal dec3_r11: std_logic;
- signal dec2_p01: std_logic;
- signal dec5_r12: std_logic;
- signal dec4_p02: std_logic;
- signal dec7_r13: std_logic;
- signal dec6_p03: std_logic;
- signal dec9_r14: std_logic;
- signal dec8_p04: std_logic;
- signal dec11_r15: std_logic;
- signal dec10_p05: std_logic;
- signal dec13_r16: std_logic;
- signal dec12_p06: std_logic;
- signal dec15_r17: std_logic;
- signal dec14_p07: std_logic;
- signal dec17_r18: std_logic;
- signal dec16_p08: std_logic;
- signal dec19_r19: std_logic;
- signal dec18_p09: std_logic;
- signal dec21_r110: std_logic;
- signal dec20_p010: std_logic;
- signal dec23_r111: std_logic;
- signal dec22_p011: std_logic;
- signal dec25_r112: std_logic;
- signal dec24_p012: std_logic;
- signal dec27_r113: std_logic;
- signal dec26_p013: std_logic;
- signal dec29_r114: std_logic;
- signal dec28_p014: std_logic;
- signal dec31_r115: std_logic;
- signal dec30_p015: std_logic;
- signal dec33_r116: std_logic;
- signal dec32_p016: std_logic;
- signal dec35_r117: std_logic;
- signal dec34_p017: std_logic;
- signal dec37_r118: std_logic;
- signal dec36_p018: std_logic;
- signal dec39_r119: std_logic;
- signal dec38_p019: std_logic;
- signal dec41_r120: std_logic;
- signal dec40_p020: std_logic;
- signal dec43_r121: std_logic;
- signal dec42_p021: std_logic;
- signal dec45_r122: std_logic;
- signal dec44_p022: std_logic;
- signal dec47_r123: std_logic;
- signal dec46_p023: std_logic;
- signal dec49_r124: std_logic;
- signal dec48_p024: std_logic;
- signal dec51_r125: std_logic;
- signal dec50_p025: std_logic;
- signal dec53_r126: std_logic;
- signal dec52_p026: std_logic;
- signal dec55_r127: std_logic;
- signal dec54_p027: std_logic;
- signal dec57_r128: std_logic;
- signal dec56_p028: std_logic;
- signal dec59_r129: std_logic;
- signal dec58_p029: std_logic;
- signal dec61_r130: std_logic;
- signal dec60_p030: std_logic;
- signal dec63_r131: std_logic;
- signal dec62_p031: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal wptr_15: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_16: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal rcnt_reg_16: std_logic;
- signal empty_i: std_logic;
- signal full_i: std_logic;
- signal rRst: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co7: std_logic;
- signal wcount_15: std_logic;
- signal co6: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_31_0: std_logic;
- signal mdout1_30_0: std_logic;
- signal mdout1_29_0: std_logic;
- signal mdout1_28_0: std_logic;
- signal mdout1_27_0: std_logic;
- signal mdout1_26_0: std_logic;
- signal mdout1_25_0: std_logic;
- signal mdout1_24_0: std_logic;
- signal mdout1_23_0: std_logic;
- signal mdout1_22_0: std_logic;
- signal mdout1_21_0: std_logic;
- signal mdout1_20_0: std_logic;
- signal mdout1_19_0: std_logic;
- signal mdout1_18_0: std_logic;
- signal mdout1_17_0: std_logic;
- signal mdout1_16_0: std_logic;
- signal mdout1_15_0: std_logic;
- signal mdout1_14_0: std_logic;
- signal mdout1_13_0: std_logic;
- signal mdout1_12_0: std_logic;
- signal mdout1_11_0: std_logic;
- signal mdout1_10_0: std_logic;
- signal mdout1_9_0: std_logic;
- signal mdout1_8_0: std_logic;
- signal mdout1_7_0: std_logic;
- signal mdout1_6_0: std_logic;
- signal mdout1_5_0: std_logic;
- signal mdout1_4_0: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_31_1: std_logic;
- signal mdout1_30_1: std_logic;
- signal mdout1_29_1: std_logic;
- signal mdout1_28_1: std_logic;
- signal mdout1_27_1: std_logic;
- signal mdout1_26_1: std_logic;
- signal mdout1_25_1: std_logic;
- signal mdout1_24_1: std_logic;
- signal mdout1_23_1: std_logic;
- signal mdout1_22_1: std_logic;
- signal mdout1_21_1: std_logic;
- signal mdout1_20_1: std_logic;
- signal mdout1_19_1: std_logic;
- signal mdout1_18_1: std_logic;
- signal mdout1_17_1: std_logic;
- signal mdout1_16_1: std_logic;
- signal mdout1_15_1: std_logic;
- signal mdout1_14_1: std_logic;
- signal mdout1_13_1: std_logic;
- signal mdout1_12_1: std_logic;
- signal mdout1_11_1: std_logic;
- signal mdout1_10_1: std_logic;
- signal mdout1_9_1: std_logic;
- signal mdout1_8_1: std_logic;
- signal mdout1_7_1: std_logic;
- signal mdout1_6_1: std_logic;
- signal mdout1_5_1: std_logic;
- signal mdout1_4_1: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_31_2: std_logic;
- signal mdout1_30_2: std_logic;
- signal mdout1_29_2: std_logic;
- signal mdout1_28_2: std_logic;
- signal mdout1_27_2: std_logic;
- signal mdout1_26_2: std_logic;
- signal mdout1_25_2: std_logic;
- signal mdout1_24_2: std_logic;
- signal mdout1_23_2: std_logic;
- signal mdout1_22_2: std_logic;
- signal mdout1_21_2: std_logic;
- signal mdout1_20_2: std_logic;
- signal mdout1_19_2: std_logic;
- signal mdout1_18_2: std_logic;
- signal mdout1_17_2: std_logic;
- signal mdout1_16_2: std_logic;
- signal mdout1_15_2: std_logic;
- signal mdout1_14_2: std_logic;
- signal mdout1_13_2: std_logic;
- signal mdout1_12_2: std_logic;
- signal mdout1_11_2: std_logic;
- signal mdout1_10_2: std_logic;
- signal mdout1_9_2: std_logic;
- signal mdout1_8_2: std_logic;
- signal mdout1_7_2: std_logic;
- signal mdout1_6_2: std_logic;
- signal mdout1_5_2: std_logic;
- signal mdout1_4_2: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_31_3: std_logic;
- signal mdout1_30_3: std_logic;
- signal mdout1_29_3: std_logic;
- signal mdout1_28_3: std_logic;
- signal mdout1_27_3: std_logic;
- signal mdout1_26_3: std_logic;
- signal mdout1_25_3: std_logic;
- signal mdout1_24_3: std_logic;
- signal mdout1_23_3: std_logic;
- signal mdout1_22_3: std_logic;
- signal mdout1_21_3: std_logic;
- signal mdout1_20_3: std_logic;
- signal mdout1_19_3: std_logic;
- signal mdout1_18_3: std_logic;
- signal mdout1_17_3: std_logic;
- signal mdout1_16_3: std_logic;
- signal mdout1_15_3: std_logic;
- signal mdout1_14_3: std_logic;
- signal mdout1_13_3: std_logic;
- signal mdout1_12_3: std_logic;
- signal mdout1_11_3: std_logic;
- signal mdout1_10_3: std_logic;
- signal mdout1_9_3: std_logic;
- signal mdout1_8_3: std_logic;
- signal mdout1_7_3: std_logic;
- signal mdout1_6_3: std_logic;
- signal mdout1_5_3: std_logic;
- signal mdout1_4_3: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_31_4: std_logic;
- signal mdout1_30_4: std_logic;
- signal mdout1_29_4: std_logic;
- signal mdout1_28_4: std_logic;
- signal mdout1_27_4: std_logic;
- signal mdout1_26_4: std_logic;
- signal mdout1_25_4: std_logic;
- signal mdout1_24_4: std_logic;
- signal mdout1_23_4: std_logic;
- signal mdout1_22_4: std_logic;
- signal mdout1_21_4: std_logic;
- signal mdout1_20_4: std_logic;
- signal mdout1_19_4: std_logic;
- signal mdout1_18_4: std_logic;
- signal mdout1_17_4: std_logic;
- signal mdout1_16_4: std_logic;
- signal mdout1_15_4: std_logic;
- signal mdout1_14_4: std_logic;
- signal mdout1_13_4: std_logic;
- signal mdout1_12_4: std_logic;
- signal mdout1_11_4: std_logic;
- signal mdout1_10_4: std_logic;
- signal mdout1_9_4: std_logic;
- signal mdout1_8_4: std_logic;
- signal mdout1_7_4: std_logic;
- signal mdout1_6_4: std_logic;
- signal mdout1_5_4: std_logic;
- signal mdout1_4_4: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_31_5: std_logic;
- signal mdout1_30_5: std_logic;
- signal mdout1_29_5: std_logic;
- signal mdout1_28_5: std_logic;
- signal mdout1_27_5: std_logic;
- signal mdout1_26_5: std_logic;
- signal mdout1_25_5: std_logic;
- signal mdout1_24_5: std_logic;
- signal mdout1_23_5: std_logic;
- signal mdout1_22_5: std_logic;
- signal mdout1_21_5: std_logic;
- signal mdout1_20_5: std_logic;
- signal mdout1_19_5: std_logic;
- signal mdout1_18_5: std_logic;
- signal mdout1_17_5: std_logic;
- signal mdout1_16_5: std_logic;
- signal mdout1_15_5: std_logic;
- signal mdout1_14_5: std_logic;
- signal mdout1_13_5: std_logic;
- signal mdout1_12_5: std_logic;
- signal mdout1_11_5: std_logic;
- signal mdout1_10_5: std_logic;
- signal mdout1_9_5: std_logic;
- signal mdout1_8_5: std_logic;
- signal mdout1_7_5: std_logic;
- signal mdout1_6_5: std_logic;
- signal mdout1_5_5: std_logic;
- signal mdout1_4_5: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_31_6: std_logic;
- signal mdout1_30_6: std_logic;
- signal mdout1_29_6: std_logic;
- signal mdout1_28_6: std_logic;
- signal mdout1_27_6: std_logic;
- signal mdout1_26_6: std_logic;
- signal mdout1_25_6: std_logic;
- signal mdout1_24_6: std_logic;
- signal mdout1_23_6: std_logic;
- signal mdout1_22_6: std_logic;
- signal mdout1_21_6: std_logic;
- signal mdout1_20_6: std_logic;
- signal mdout1_19_6: std_logic;
- signal mdout1_18_6: std_logic;
- signal mdout1_17_6: std_logic;
- signal mdout1_16_6: std_logic;
- signal mdout1_15_6: std_logic;
- signal mdout1_14_6: std_logic;
- signal mdout1_13_6: std_logic;
- signal mdout1_12_6: std_logic;
- signal mdout1_11_6: std_logic;
- signal mdout1_10_6: std_logic;
- signal mdout1_9_6: std_logic;
- signal mdout1_8_6: std_logic;
- signal mdout1_7_6: std_logic;
- signal mdout1_6_6: std_logic;
- signal mdout1_5_6: std_logic;
- signal mdout1_4_6: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_31_7: std_logic;
- signal mdout1_30_7: std_logic;
- signal mdout1_29_7: std_logic;
- signal mdout1_28_7: std_logic;
- signal mdout1_27_7: std_logic;
- signal mdout1_26_7: std_logic;
- signal mdout1_25_7: std_logic;
- signal mdout1_24_7: std_logic;
- signal mdout1_23_7: std_logic;
- signal mdout1_22_7: std_logic;
- signal mdout1_21_7: std_logic;
- signal mdout1_20_7: std_logic;
- signal mdout1_19_7: std_logic;
- signal mdout1_18_7: std_logic;
- signal mdout1_17_7: std_logic;
- signal mdout1_16_7: std_logic;
- signal mdout1_15_7: std_logic;
- signal mdout1_14_7: std_logic;
- signal mdout1_13_7: std_logic;
- signal mdout1_12_7: std_logic;
- signal mdout1_11_7: std_logic;
- signal mdout1_10_7: std_logic;
- signal mdout1_9_7: std_logic;
- signal mdout1_8_7: std_logic;
- signal mdout1_7_7: std_logic;
- signal mdout1_6_7: std_logic;
- signal mdout1_5_7: std_logic;
- signal mdout1_4_7: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal rptr_13_ff: std_logic;
- signal rptr_12_ff: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_31_8: std_logic;
- signal mdout1_30_8: std_logic;
- signal mdout1_29_8: std_logic;
- signal mdout1_28_8: std_logic;
- signal mdout1_27_8: std_logic;
- signal mdout1_26_8: std_logic;
- signal mdout1_25_8: std_logic;
- signal mdout1_24_8: std_logic;
- signal mdout1_23_8: std_logic;
- signal mdout1_22_8: std_logic;
- signal mdout1_21_8: std_logic;
- signal mdout1_20_8: std_logic;
- signal mdout1_19_8: std_logic;
- signal mdout1_18_8: std_logic;
- signal mdout1_17_8: std_logic;
- signal mdout1_16_8: std_logic;
- signal mdout1_15_8: std_logic;
- signal mdout1_14_8: std_logic;
- signal mdout1_13_8: std_logic;
- signal mdout1_12_8: std_logic;
- signal mdout1_11_8: std_logic;
- signal mdout1_10_8: std_logic;
- signal mdout1_9_8: std_logic;
- signal mdout1_8_8: std_logic;
- signal mdout1_7_8: std_logic;
- signal mdout1_6_8: std_logic;
- signal mdout1_5_8: std_logic;
- signal mdout1_4_8: std_logic;
- signal mdout1_3_8: std_logic;
- signal mdout1_2_8: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal wcnt_sub_0: std_logic;
- signal wcnt_sub_1: std_logic;
- signal wcnt_sub_2: std_logic;
- signal co0_2: std_logic;
- signal wcnt_sub_3: std_logic;
- signal wcnt_sub_4: std_logic;
- signal co1_2: std_logic;
- signal wcnt_sub_5: std_logic;
- signal wcnt_sub_6: std_logic;
- signal co2_2: std_logic;
- signal wcnt_sub_7: std_logic;
- signal wcnt_sub_8: std_logic;
- signal co3_2: std_logic;
- signal wcnt_sub_9: std_logic;
- signal wcnt_sub_10: std_logic;
- signal co4_2: std_logic;
- signal wcnt_sub_11: std_logic;
- signal wcnt_sub_12: std_logic;
- signal co5_2: std_logic;
- signal wcnt_sub_13: std_logic;
- signal wcnt_sub_14: std_logic;
- signal co6_2: std_logic;
- signal wcnt_sub_15: std_logic;
- signal co7_2: std_logic;
- signal wcnt_sub_msb: std_logic;
- signal rcnt_sub_0: std_logic;
- signal rcnt_sub_1: std_logic;
- signal rcnt_sub_2: std_logic;
- signal co0_3: std_logic;
- signal rcnt_sub_3: std_logic;
- signal rcnt_sub_4: std_logic;
- signal co1_3: std_logic;
- signal rcnt_sub_5: std_logic;
- signal rcnt_sub_6: std_logic;
- signal co2_3: std_logic;
- signal rcnt_sub_7: std_logic;
- signal rcnt_sub_8: std_logic;
- signal co3_3: std_logic;
- signal rcnt_sub_9: std_logic;
- signal rcnt_sub_10: std_logic;
- signal co4_3: std_logic;
- signal rcnt_sub_11: std_logic;
- signal rcnt_sub_12: std_logic;
- signal co5_3: std_logic;
- signal rcnt_sub_13: std_logic;
- signal rcnt_sub_14: std_logic;
- signal co6_3: std_logic;
- signal rcnt_sub_15: std_logic;
- signal rcnt_sub_16: std_logic;
- signal co7_3: std_logic;
- signal rcnt_sub_msb: std_logic;
- signal co8_1d: std_logic;
- signal co8_1: std_logic;
- signal wfill_sub_0: std_logic;
- signal wptr_0: std_logic;
- signal wfill_sub_1: std_logic;
- signal wfill_sub_2: std_logic;
- signal co0_4: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wfill_sub_3: std_logic;
- signal wfill_sub_4: std_logic;
- signal co1_4: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wfill_sub_5: std_logic;
- signal wfill_sub_6: std_logic;
- signal co2_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wfill_sub_7: std_logic;
- signal wfill_sub_8: std_logic;
- signal co3_4: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wfill_sub_9: std_logic;
- signal wfill_sub_10: std_logic;
- signal co4_4: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wfill_sub_11: std_logic;
- signal wfill_sub_12: std_logic;
- signal co5_4: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wfill_sub_13: std_logic;
- signal wfill_sub_14: std_logic;
- signal co6_4: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wfill_sub_15: std_logic;
- signal co7_4: std_logic;
- signal wfill_sub_msb: std_logic;
- signal rfill_sub_0: std_logic;
- signal rptr_0: std_logic;
- signal scuba_vhi: std_logic;
- signal rfill_sub_1: std_logic;
- signal rfill_sub_2: std_logic;
- signal co0_5: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rfill_sub_3: std_logic;
- signal rfill_sub_4: std_logic;
- signal co1_5: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rfill_sub_5: std_logic;
- signal rfill_sub_6: std_logic;
- signal co2_5: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rfill_sub_7: std_logic;
- signal rfill_sub_8: std_logic;
- signal co3_5: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rfill_sub_9: std_logic;
- signal rfill_sub_10: std_logic;
- signal co4_5: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rfill_sub_11: std_logic;
- signal rfill_sub_12: std_logic;
- signal co5_5: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rfill_sub_13: std_logic;
- signal rfill_sub_14: std_logic;
- signal co6_5: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rfill_sub_15: std_logic;
- signal rfill_sub_16: std_logic;
- signal co7_5: std_logic;
- signal rptr_15: std_logic;
- signal rfill_sub_msb: std_logic;
- signal co8_2d: std_logic;
- signal co8_2: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_6: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_6: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_6: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_6: std_logic;
- signal wcount_r7: std_logic;
- signal wcount_r8: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_6: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_6: std_logic;
- signal wcount_r11: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_6: std_logic;
- signal wcount_r13: std_logic;
- signal wcount_r14: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_6: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_7: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_7: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_7: std_logic;
- signal rcount_w7: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_7: std_logic;
- signal rcount_w9: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_7: std_logic;
- signal rcount_w11: std_logic;
- signal rcount_w12: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w14: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_7: std_logic;
- signal rcount_w15: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_14: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal rcnt_reg_0: std_logic;
- signal rcnt_reg_1: std_logic;
- signal co0_8: std_logic;
- signal rcnt_reg_2: std_logic;
- signal rcnt_reg_3: std_logic;
- signal co1_8: std_logic;
- signal rcnt_reg_4: std_logic;
- signal rcnt_reg_5: std_logic;
- signal co2_8: std_logic;
- signal rcnt_reg_6: std_logic;
- signal rcnt_reg_7: std_logic;
- signal co3_8: std_logic;
- signal rcnt_reg_8: std_logic;
- signal rcnt_reg_9: std_logic;
- signal co4_8: std_logic;
- signal rcnt_reg_10: std_logic;
- signal rcnt_reg_11: std_logic;
- signal co5_8: std_logic;
- signal rcnt_reg_12: std_logic;
- signal rcnt_reg_13: std_logic;
- signal co6_8: std_logic;
- signal rcnt_reg_14: std_logic;
- signal rcnt_reg_15: std_logic;
- signal co7_7: std_logic;
- signal ae_clrsig: std_logic;
- signal ae_setsig: std_logic;
- signal ae_d: std_logic;
- signal ae_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_3: std_logic;
- signal wcnt_reg_0: std_logic;
- signal wcnt_reg_1: std_logic;
- signal co0_9: std_logic;
- signal wcnt_reg_2: std_logic;
- signal wcnt_reg_3: std_logic;
- signal co1_9: std_logic;
- signal wcnt_reg_4: std_logic;
- signal wcnt_reg_5: std_logic;
- signal co2_9: std_logic;
- signal wcnt_reg_6: std_logic;
- signal wcnt_reg_7: std_logic;
- signal co3_9: std_logic;
- signal wcnt_reg_8: std_logic;
- signal wcnt_reg_9: std_logic;
- signal co4_9: std_logic;
- signal wcnt_reg_10: std_logic;
- signal wcnt_reg_11: std_logic;
- signal co5_9: std_logic;
- signal wcnt_reg_12: std_logic;
- signal wcnt_reg_13: std_logic;
- signal co6_9: std_logic;
- signal wcnt_reg_14: std_logic;
- signal wcnt_reg_15: std_logic;
- signal af_d: std_logic;
- signal af_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX321
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; D8: in std_logic;
- D9: in std_logic; D10: in std_logic; D11: in std_logic;
- D12: in std_logic; D13: in std_logic; D14: in std_logic;
- D15: in std_logic; D16: in std_logic; D17: in std_logic;
- D18: in std_logic; D19: in std_logic; D20: in std_logic;
- D21: in std_logic; D22: in std_logic; D23: in std_logic;
- D24: in std_logic; D25: in std_logic; D26: in std_logic;
- D27: in std_logic; D28: in std_logic; D29: in std_logic;
- D30: in std_logic; D31: in std_logic; SD1: in std_logic;
- SD2: in std_logic; SD3: in std_logic; SD4: in std_logic;
- SD5: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is "";
- attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is "";
- attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is "";
- attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is "";
- attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is "";
- attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is "";
- attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is "";
- attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is "";
- attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is "";
- attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is "";
- attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is "";
- attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is "";
- attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is "";
- attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is "";
- attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is "";
- attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is "";
- attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is "";
- attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is "";
- attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is "";
- attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is "";
- attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is "";
- attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is "";
- attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is "";
- attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is "";
- attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is "";
- attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is "";
- attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is "";
- attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is "";
- attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is "";
- attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is "";
- attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is "";
- attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC";
- attribute GSR of FF_239 : label is "ENABLED";
- attribute GSR of FF_238 : label is "ENABLED";
- attribute GSR of FF_237 : label is "ENABLED";
- attribute GSR of FF_236 : label is "ENABLED";
- attribute GSR of FF_235 : label is "ENABLED";
- attribute GSR of FF_234 : label is "ENABLED";
- attribute GSR of FF_233 : label is "ENABLED";
- attribute GSR of FF_232 : label is "ENABLED";
- attribute GSR of FF_231 : label is "ENABLED";
- attribute GSR of FF_230 : label is "ENABLED";
- attribute GSR of FF_229 : label is "ENABLED";
- attribute GSR of FF_228 : label is "ENABLED";
- attribute GSR of FF_227 : label is "ENABLED";
- attribute GSR of FF_226 : label is "ENABLED";
- attribute GSR of FF_225 : label is "ENABLED";
- attribute GSR of FF_224 : label is "ENABLED";
- attribute GSR of FF_223 : label is "ENABLED";
- attribute GSR of FF_222 : label is "ENABLED";
- attribute GSR of FF_221 : label is "ENABLED";
- attribute GSR of FF_220 : label is "ENABLED";
- attribute GSR of FF_219 : label is "ENABLED";
- attribute GSR of FF_218 : label is "ENABLED";
- attribute GSR of FF_217 : label is "ENABLED";
- attribute GSR of FF_216 : label is "ENABLED";
- attribute GSR of FF_215 : label is "ENABLED";
- attribute GSR of FF_214 : label is "ENABLED";
- attribute GSR of FF_213 : label is "ENABLED";
- attribute GSR of FF_212 : label is "ENABLED";
- attribute GSR of FF_211 : label is "ENABLED";
- attribute GSR of FF_210 : label is "ENABLED";
- attribute GSR of FF_209 : label is "ENABLED";
- attribute GSR of FF_208 : label is "ENABLED";
- attribute GSR of FF_207 : label is "ENABLED";
- attribute GSR of FF_206 : label is "ENABLED";
- attribute GSR of FF_205 : label is "ENABLED";
- attribute GSR of FF_204 : label is "ENABLED";
- attribute GSR of FF_203 : label is "ENABLED";
- attribute GSR of FF_202 : label is "ENABLED";
- attribute GSR of FF_201 : label is "ENABLED";
- attribute GSR of FF_200 : label is "ENABLED";
- attribute GSR of FF_199 : label is "ENABLED";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t39: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_12: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t38: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_11: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t37: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t36: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t35: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t34: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t33: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t32: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t31: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t30: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t29: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t28: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t27: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t26: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t25: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t24: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t23: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t22: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t21: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t9: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t8: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t7: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t6: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- INV_10: INV
- port map (A=>wptr_10, Z=>wptr_10_inv);
-
- INV_9: INV
- port map (A=>wptr_11, Z=>wptr_11_inv);
-
- INV_8: INV
- port map (A=>wptr_12, Z=>wptr_12_inv);
-
- INV_7: INV
- port map (A=>wptr_13, Z=>wptr_13_inv);
-
- INV_6: INV
- port map (A=>wptr_14, Z=>wptr_14_inv);
-
- LUT4_180: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet);
-
- LUT4_179: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_p00);
-
- INV_5: INV
- port map (A=>rptr_11, Z=>rptr_11_inv);
-
- INV_4: INV
- port map (A=>rptr_12, Z=>rptr_12_inv);
-
- INV_3: INV
- port map (A=>rptr_13, Z=>rptr_13_inv);
-
- INV_2: INV
- port map (A=>rptr_14, Z=>rptr_14_inv);
-
- INV_1: INV
- port map (A=>rptr_15, Z=>rptr_15_inv);
-
- LUT4_178: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_1);
-
- LUT4_177: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec1_r10);
-
- LUT4_176: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_2);
-
- LUT4_175: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec2_p01);
-
- LUT4_174: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_3);
-
- LUT4_173: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec3_r11);
-
- LUT4_172: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_4);
-
- LUT4_171: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec4_p02);
-
- LUT4_170: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_5);
-
- LUT4_169: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec5_r12);
-
- LUT4_168: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_6);
-
- LUT4_167: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec6_p03);
-
- LUT4_166: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_7);
-
- LUT4_165: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec7_r13);
-
- LUT4_164: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_8);
-
- LUT4_163: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec8_p04);
-
- LUT4_162: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_9);
-
- LUT4_161: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec9_r14);
-
- LUT4_160: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_10);
-
- LUT4_159: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05);
-
- LUT4_158: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_11);
-
- LUT4_157: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15);
-
- LUT4_156: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_12);
-
- LUT4_155: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06);
-
- LUT4_154: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_13);
-
- LUT4_153: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16);
-
- LUT4_152: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_14);
-
- LUT4_151: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07);
-
- LUT4_150: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_15);
-
- LUT4_149: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17);
-
- LUT4_148: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_16);
-
- LUT4_147: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08);
-
- LUT4_146: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_17);
-
- LUT4_145: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18);
-
- LUT4_144: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_18);
-
- LUT4_143: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09);
-
- LUT4_142: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_19);
-
- LUT4_141: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19);
-
- LUT4_140: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_20);
-
- LUT4_139: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010);
-
- LUT4_138: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_21);
-
- LUT4_137: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110);
-
- LUT4_136: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_22);
-
- LUT4_135: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011);
-
- LUT4_134: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_23);
-
- LUT4_133: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111);
-
- LUT4_132: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_24);
-
- LUT4_131: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012);
-
- LUT4_130: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_25);
-
- LUT4_129: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112);
-
- LUT4_128: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_26);
-
- LUT4_127: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013);
-
- LUT4_126: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_27);
-
- LUT4_125: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113);
-
- LUT4_124: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_28);
-
- LUT4_123: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014);
-
- LUT4_122: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_29);
-
- LUT4_121: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114);
-
- LUT4_120: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
- DO0=>func_and_inet_30);
-
- LUT4_119: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015);
-
- LUT4_118: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_31);
-
- LUT4_117: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115);
-
- LUT4_116: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_32);
-
- LUT4_115: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec32_p016);
-
- LUT4_114: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_33);
-
- LUT4_113: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec33_r116);
-
- LUT4_112: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_34);
-
- LUT4_111: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec34_p017);
-
- LUT4_110: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_35);
-
- LUT4_109: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec35_r117);
-
- LUT4_108: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_36);
-
- LUT4_107: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec36_p018);
-
- LUT4_106: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_37);
-
- LUT4_105: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec37_r118);
-
- LUT4_104: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_38);
-
- LUT4_103: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec38_p019);
-
- LUT4_102: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_39);
-
- LUT4_101: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec39_r119);
-
- LUT4_100: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_40);
-
- LUT4_99: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec40_p020);
-
- LUT4_98: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_41);
-
- LUT4_97: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec41_r120);
-
- LUT4_96: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_42);
-
- LUT4_95: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec42_p021);
-
- LUT4_94: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_43);
-
- LUT4_93: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec43_r121);
-
- LUT4_92: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_44);
-
- LUT4_91: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec44_p022);
-
- LUT4_90: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_45);
-
- LUT4_89: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec45_r122);
-
- LUT4_88: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_46);
-
- LUT4_87: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec46_p023);
-
- LUT4_86: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_47);
-
- LUT4_85: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec47_r123);
-
- LUT4_84: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_48);
-
- LUT4_83: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec48_p024);
-
- LUT4_82: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_49);
-
- LUT4_81: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec49_r124);
-
- LUT4_80: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_50);
-
- LUT4_79: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec50_p025);
-
- LUT4_78: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_51);
-
- LUT4_77: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec51_r125);
-
- LUT4_76: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_52);
-
- LUT4_75: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec52_p026);
-
- LUT4_74: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_53);
-
- LUT4_73: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec53_r126);
-
- LUT4_72: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_54);
-
- LUT4_71: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec54_p027);
-
- LUT4_70: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_55);
-
- LUT4_69: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec55_r127);
-
- LUT4_68: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_56);
-
- LUT4_67: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec56_p028);
-
- LUT4_66: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_57);
-
- LUT4_65: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec57_r128);
-
- LUT4_64: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_58);
-
- LUT4_63: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec58_p029);
-
- LUT4_62: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_59);
-
- LUT4_61: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec59_r129);
-
- LUT4_60: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_60);
-
- LUT4_59: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec60_p030);
-
- LUT4_58: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_61);
-
- LUT4_57: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec61_r130);
-
- LUT4_56: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
- DO0=>func_and_inet_62);
-
- LUT4_55: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec62_p031);
-
- LUT4_54: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_63);
-
- LUT4_53: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec63_r131);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r2);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r1);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- XOR2_t5: XOR2
- port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb);
-
- XOR2_t4: XOR2
- port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb);
-
- XOR2_t3: XOR2
- port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb);
-
- XOR2_t2: XOR2
- port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- INV_0: INV
- port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv);
-
- AND2_t1: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig);
-
- AND2_t0: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig);
-
- pdp_ram_0_0_31: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_30: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_29: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
- DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
- DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
- DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_28: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1,
- DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4,
- DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7,
- DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_4_0_27: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1,
- DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4,
- DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7,
- DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_5_0_26: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1,
- DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4,
- DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7,
- DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_6_0_25: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1,
- DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4,
- DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7,
- DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_7_0_24: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1,
- DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4,
- DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7,
- DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_8_0_23: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1,
- DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4,
- DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7,
- DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_9_0_22: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1,
- DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4,
- DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7,
- DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_10_0_21: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1,
- DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4,
- DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7,
- DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_11_0_20: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1,
- DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4,
- DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7,
- DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_12_0_19: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1,
- DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4,
- DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7,
- DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_13_0_18: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1,
- DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4,
- DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7,
- DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_14_0_17: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1,
- DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4,
- DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7,
- DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_15_0_16: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1,
- DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4,
- DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7,
- DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_16_0_15: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1,
- DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4,
- DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7,
- DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_17_0_14: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1,
- DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4,
- DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7,
- DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_18_0_13: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1,
- DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4,
- DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7,
- DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_19_0_12: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1,
- DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4,
- DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7,
- DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_20_0_11: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1,
- DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4,
- DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7,
- DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_21_0_10: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1,
- DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4,
- DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7,
- DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_22_0_9: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1,
- DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4,
- DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7,
- DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_23_0_8: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1,
- DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4,
- DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7,
- DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_24_0_7: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1,
- DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4,
- DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7,
- DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_25_0_6: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1,
- DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4,
- DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7,
- DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_26_0_5: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1,
- DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4,
- DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7,
- DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_27_0_4: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1,
- DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4,
- DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7,
- DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_28_0_3: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1,
- DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4,
- DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7,
- DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_29_0_2: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1,
- DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4,
- DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7,
- DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_30_0_1: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1,
- DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4,
- DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7,
- DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_31_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1,
- DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4,
- DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7,
- DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_239: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_238: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_237: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_236: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_235: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_234: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_233: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_232: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_231: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_230: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_229: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_228: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_227: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_226: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_225: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_224: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_223: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_222: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_221: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_220: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_219: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_218: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_217: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_216: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_215: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_214: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_213: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_212: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_211: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_210: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_209: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_208: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_207: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_206: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_205: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_204: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_203: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_202: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_201: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_200: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_199: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_198: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_197: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_196: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_195: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_194: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_193: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_192: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_191: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_190: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_189: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_188: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_187: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_186: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_185: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_184: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_183: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_182: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_181: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_180: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_179: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_178: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_177: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_176: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_175: FD1P3DX
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_174: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_173: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_172: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_171: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_170: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_169: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_168: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_167: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_166: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_165: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_164: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_163: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_162: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_161: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_160: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_159: FD1P3DX
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_158: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_157: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_156: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_155: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_154: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_153: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_152: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_151: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_150: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_149: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_148: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_147: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_146: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_145: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_144: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_143: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_142: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_141: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_140: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_139: FD1P3DX
- port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_12_ff);
-
- FF_138: FD1P3DX
- port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_13_ff);
-
- FF_137: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_136: FD1P3DX
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_135: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_134: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_133: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_132: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_131: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_130: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_129: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_128: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_127: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_126: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_125: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_124: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_123: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_122: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_121: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_120: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_119: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_118: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_117: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_116: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_115: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_114: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_113: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_112: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_111: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_110: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_109: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_108: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_107: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_106: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_105: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_104: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_103: FD1S3DX
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_102: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_101: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_100: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_99: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_98: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_97: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_96: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_95: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_94: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_93: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_92: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_91: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_90: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_89: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_88: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_87: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_86: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_85: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_84: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_83: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_82: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_81: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_80: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_79: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_78: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_77: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_76: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_75: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_74: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_73: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_72: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_71: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_70: FD1S3DX
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_69: FD1S3DX
- port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0);
-
- FF_68: FD1S3DX
- port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1);
-
- FF_67: FD1S3DX
- port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2);
-
- FF_66: FD1S3DX
- port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3);
-
- FF_65: FD1S3DX
- port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4);
-
- FF_64: FD1S3DX
- port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5);
-
- FF_63: FD1S3DX
- port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6);
-
- FF_62: FD1S3DX
- port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7);
-
- FF_61: FD1S3DX
- port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8);
-
- FF_60: FD1S3DX
- port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9);
-
- FF_59: FD1S3DX
- port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10);
-
- FF_58: FD1S3DX
- port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11);
-
- FF_57: FD1S3DX
- port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12);
-
- FF_56: FD1S3DX
- port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13);
-
- FF_55: FD1S3DX
- port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14);
-
- FF_54: FD1S3DX
- port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15);
-
- FF_53: FD1S3DX
- port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0);
-
- FF_52: FD1S3DX
- port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1);
-
- FF_51: FD1S3DX
- port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2);
-
- FF_50: FD1S3DX
- port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3);
-
- FF_49: FD1S3DX
- port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4);
-
- FF_48: FD1S3DX
- port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5);
-
- FF_47: FD1S3DX
- port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6);
-
- FF_46: FD1S3DX
- port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7);
-
- FF_45: FD1S3DX
- port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8);
-
- FF_44: FD1S3DX
- port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9);
-
- FF_43: FD1S3DX
- port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10);
-
- FF_42: FD1S3DX
- port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11);
-
- FF_41: FD1S3DX
- port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12);
-
- FF_40: FD1S3DX
- port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13);
-
- FF_39: FD1S3DX
- port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14);
-
- FF_38: FD1S3DX
- port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15);
-
- FF_37: FD1S3DX
- port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16);
-
- FF_36: FD1S3DX
- port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
-
- FF_35: FD1S3DX
- port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
-
- FF_34: FD1S3DX
- port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
-
- FF_33: FD1S3DX
- port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
-
- FF_32: FD1S3DX
- port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
-
- FF_31: FD1S3DX
- port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
-
- FF_30: FD1S3DX
- port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
-
- FF_29: FD1S3DX
- port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
-
- FF_28: FD1S3DX
- port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
-
- FF_27: FD1S3DX
- port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
-
- FF_26: FD1S3DX
- port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
-
- FF_25: FD1S3DX
- port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
-
- FF_24: FD1S3DX
- port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12));
-
- FF_23: FD1S3DX
- port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13));
-
- FF_22: FD1S3DX
- port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14));
-
- FF_21: FD1S3DX
- port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15));
-
- FF_20: FD1S3DX
- port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
-
- FF_19: FD1S3DX
- port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
-
- FF_18: FD1S3DX
- port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
-
- FF_17: FD1S3DX
- port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
-
- FF_16: FD1S3DX
- port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
-
- FF_15: FD1S3DX
- port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
-
- FF_14: FD1S3DX
- port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
-
- FF_13: FD1S3DX
- port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
-
- FF_12: FD1S3DX
- port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
-
- FF_11: FD1S3DX
- port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
-
- FF_10: FD1S3DX
- port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10));
-
- FF_9: FD1S3DX
- port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11));
-
- FF_8: FD1S3DX
- port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12));
-
- FF_7: FD1S3DX
- port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13));
-
- FF_6: FD1S3DX
- port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14));
-
- FF_5: FD1S3DX
- port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15));
-
- FF_4: FD1S3DX
- port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16));
-
- FF_3: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_2: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- FF_1: FD1S3BX
- port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
-
- FF_0: FD1S3DX
- port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>ircount_16, NC1=>open);
-
- mux_8: MUX321
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
- D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
- D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
- D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0,
- D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0,
- D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0,
- D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0,
- D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0,
- D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(0));
-
- mux_7: MUX321
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
- D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
- D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
- D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1,
- D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1,
- D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1,
- D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1,
- D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1,
- D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(1));
-
- mux_6: MUX321
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
- D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
- D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
- D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2,
- D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2,
- D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2,
- D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2,
- D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2,
- D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(2));
-
- mux_5: MUX321
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
- D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
- D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
- D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3,
- D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3,
- D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3,
- D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3,
- D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3,
- D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(3));
-
- mux_4: MUX321
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
- D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
- D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
- D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4,
- D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4,
- D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4,
- D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4,
- D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4,
- D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(4));
-
- mux_3: MUX321
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
- D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
- D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
- D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5,
- D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5,
- D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5,
- D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5,
- D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5,
- D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(5));
-
- mux_2: MUX321
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
- D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
- D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
- D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6,
- D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6,
- D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6,
- D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6,
- D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6,
- D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(6));
-
- mux_1: MUX321
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
- D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
- D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
- D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7,
- D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7,
- D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7,
- D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7,
- D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7,
- D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(7));
-
- mux_0: MUX321
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
- D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
- D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
- D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8,
- D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8,
- D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8,
- D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8,
- D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8,
- D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(8));
-
- wcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
- S1=>wcnt_sub_0);
-
- wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2,
- B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1,
- S1=>wcnt_sub_2);
-
- wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4,
- B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3,
- S1=>wcnt_sub_4);
-
- wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6,
- B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5,
- S1=>wcnt_sub_6);
-
- wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8,
- B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7,
- S1=>wcnt_sub_8);
-
- wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9,
- S1=>wcnt_sub_10);
-
- wcnt_6: FSUB2B
- port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2,
- S0=>wcnt_sub_11, S1=>wcnt_sub_12);
-
- wcnt_7: FSUB2B
- port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13,
- S1=>wcnt_sub_14);
-
- wcnt_8: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15,
- S1=>open);
-
- rcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open,
- S1=>rcnt_sub_0);
-
- rcnt_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1,
- B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1,
- S1=>rcnt_sub_2);
-
- rcnt_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3,
- B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3,
- S1=>rcnt_sub_4);
-
- rcnt_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5,
- B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5,
- S1=>rcnt_sub_6);
-
- rcnt_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7,
- B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7,
- S1=>rcnt_sub_8);
-
- rcnt_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9,
- B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9,
- S1=>rcnt_sub_10);
-
- rcnt_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11,
- B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11,
- S1=>rcnt_sub_12);
-
- rcnt_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13,
- B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13,
- S1=>rcnt_sub_14);
-
- rcnt_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15,
- B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15,
- S1=>rcnt_sub_16);
-
- rcntd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open);
-
- wfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open,
- S1=>wfill_sub_0);
-
- wfill_1: FSUB2B
- port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3,
- BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2);
-
- wfill_2: FSUB2B
- port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5,
- BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4);
-
- wfill_3: FSUB2B
- port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7,
- BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6);
-
- wfill_4: FSUB2B
- port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9,
- BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8);
-
- wfill_5: FSUB2B
- port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9,
- S1=>wfill_sub_10);
-
- wfill_6: FSUB2B
- port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4,
- S0=>wfill_sub_11, S1=>wfill_sub_12);
-
- wfill_7: FSUB2B
- port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13,
- S1=>wfill_sub_14);
-
- wfill_8: FSUB2B
- port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- rfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
- S1=>rfill_sub_0);
-
- rfill_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2,
- BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2);
-
- rfill_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4,
- BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4);
-
- rfill_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6,
- BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6);
-
- rfill_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8,
- BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8);
-
- rfill_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10,
- BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10);
-
- rfill_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11,
- B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11,
- S1=>rfill_sub_12);
-
- rfill_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13,
- B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13,
- S1=>rfill_sub_14);
-
- rfill_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15,
- B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15,
- S1=>rfill_sub_16);
-
- rfilld: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_6, GE=>co1_6);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_6, GE=>co2_6);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_6, GE=>co3_6);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
- B1=>wcount_r8, CI=>co3_6, GE=>co4_6);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co4_6, GE=>co5_6);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11,
- B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13,
- B1=>wcount_r14, CI=>co6_6, GE=>co7_6);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_7, GE=>co1_7);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_7, GE=>co2_7);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>rcount_w8, CI=>co2_7, GE=>co3_7);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
- B1=>rcount_w10, CI=>co3_7, GE=>co4_7);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11,
- B1=>rcount_w12, CI=>co4_7, GE=>co5_7);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w14, CI=>co5_7, GE=>co6_7);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15,
- B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- ae_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- ae_cmp_0: AGEB2
- port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
- B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8);
-
- ae_cmp_1: AGEB2
- port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
- B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8);
-
- ae_cmp_2: AGEB2
- port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
- B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8);
-
- ae_cmp_3: AGEB2
- port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
- B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8);
-
- ae_cmp_4: AGEB2
- port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9),
- B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8);
-
- ae_cmp_5: AGEB2
- port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11),
- B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8);
-
- ae_cmp_6: AGEB2
- port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13),
- B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8);
-
- ae_cmp_7: AGEB2
- port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15),
- B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7);
-
- ae_cmp_8: AGEB2
- port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig,
- B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
-
- af_d_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
-
- af_d_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
- B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9);
-
- af_d_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
- B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9);
-
- af_d_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
- B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9);
-
- af_d_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
- B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9);
-
- af_d_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
- B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9);
-
- af_d_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
- B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9);
-
- af_d_cmp_6: AGEB2
- port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
- B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9);
-
- af_d_cmp_7: AGEB2
- port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14),
- B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_32kx16x8_mb2 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX321 use entity ecp3.MUX321(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:22:54 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e
- Circuit name : fifo_32kx16x8_mb2
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]
- Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_32kx16x8_mb2.vhd
- VHDL template : fifo_32kx16x8_mb2_tmpl.vhd
- VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_32kx16x8_mb2.srp
- Estimated Resource Usage:
- LUT : 491
- EBR : 32
- Reg : 240
-
-END SCUBA Module Synthesis
-
-File: fifo_32kx16x8_mb2.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:22:54 2011
-
--- parameterized module component declaration
-component fifo_32kx16x8_mb2
- port (Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(8 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_32kx16x8_mb2
- port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__,
- AmFullThresh(14 downto 0)=>__, Q(8 downto 0)=>__, WCNT(15 downto 0)=>__,
- RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__,
- AlmostFull=>__);
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
-Fri Feb 05 16:48:12 2010\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_32kx16x8_mb -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 16 -num_words 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e \r
- Circuit name : fifo_32kx16x8_mb\r
- Module type : ebfifo\r
- Module Version : 5.3\r
- Ports : \r
- Inputs : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]\r
- Outputs : Q[7:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_32kx16x8_mb.vhd\r
- VHDL template : fifo_32kx16x8_mb_tmpl.vhd\r
- VHDL testbench : tb_fifo_32kx16x8_mb_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_32kx16x8_mb.srp\r
- Estimated Resource Usage:\r
- LUT : 299\r
- EBR : 32\r
- Reg : 237\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: .\ipexpress\fifo_32kx16x8_mb\fifo_32kx16x8_mb.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:22:35 2011
-
--- parameterized module component declaration
-component fifo_32kx16x8_mb
- port (Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(7 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_32kx16x8_mb
- port map (Data(15 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__,
- AmFullThresh(14 downto 0)=>__, Q(7 downto 0)=>__, WCNT(15 downto 0)=>__,
- RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__,
- AlmostFull=>__);
+++ /dev/null
-MODULE fifo_4096x32 DEFIN fifo_4096x32.vhd\r
- SUBMODULE FADD2B\r
- INSTANCE a1\r
- SUBMODULE VLO\r
- INSTANCE scuba_vlo_inst\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE full_cmp_ci_a\r
- SUBMODULE FADD2B\r
- INSTANCE a0\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE empty_cmp_ci_a\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_6\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_5\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_4\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_3\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_2\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_1\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_0\r
- SUBMODULE FADD2B\r
- INSTANCE r_gctr_cia\r
- SUBMODULE VHI\r
- INSTANCE scuba_vhi_inst\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_6\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_5\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_4\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_3\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_2\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_1\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_0\r
- SUBMODULE FADD2B\r
- INSTANCE w_gctr_cia\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_0\r
- SUBMODULE FD1S3BX\r
- INSTANCE FF_1\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_2\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_3\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_4\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_5\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_6\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_7\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_8\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_9\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_10\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_11\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_12\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_13\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_14\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_15\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_16\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_17\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_18\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_19\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_20\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_21\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_22\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_23\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_24\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_25\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_26\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_27\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_28\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_29\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_30\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_31\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_32\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_33\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_34\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_35\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_36\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_37\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_38\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_39\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_40\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_41\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_42\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_43\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_44\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_45\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_46\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_47\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_48\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_49\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_50\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_51\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_52\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_53\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_54\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_55\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_56\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_57\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_58\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_59\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_60\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_61\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_62\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_63\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_64\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_65\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_66\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_67\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_68\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_69\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_70\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_71\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_72\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_73\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_74\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_75\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_76\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_77\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_78\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_79\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_80\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_81\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_82\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_83\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_84\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_85\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_86\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_87\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_88\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_89\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_90\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_91\r
- SUBMODULE FD1P3BX\r
- INSTANCE FF_92\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_93\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_94\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_95\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_96\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_97\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_98\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_99\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_100\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_101\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_102\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_103\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_104\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_105\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_106\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_107\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_108\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_109\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_110\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_111\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_112\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_113\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_114\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_115\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_116\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_117\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_118\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_119\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_120\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_121\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_122\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_123\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_124\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_125\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_126\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_127\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_128\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_129\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_130\r
- SUBMODULE FD1P3BX\r
- INSTANCE FF_131\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_7_0\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_6_1\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_5_2\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_4_3\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_3_4\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_2_5\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_1_6\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_0_7\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_0\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_1\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_2\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_3\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_4\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_5\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_6\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_7\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_8\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_9\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_10\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_11\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_12\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_13\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_14\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_15\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_16\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_17\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_18\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_19\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_20\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_21\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_22\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_23\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_24\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_25\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_26\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_27\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_28\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_29\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_30\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_31\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_32\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_33\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t0\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t1\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t2\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t3\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t4\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t5\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t6\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t7\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t8\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t9\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t10\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t11\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t12\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t13\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t14\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t15\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t16\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t17\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t18\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t19\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t20\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t21\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t22\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t23\r
- SUBMODULE OR2\r
- INSTANCE OR2_t24\r
- SUBMODULE INV\r
- INSTANCE INV_0\r
- SUBMODULE AND2\r
- INSTANCE AND2_t25\r
- SUBMODULE INV\r
- INSTANCE INV_1\r
- SUBMODULE AND2\r
- INSTANCE AND2_t26\r
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_4096x32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:24:15
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=4096
-Width=32
-RDepth=4096
-RWidth=32
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[31] i\r
-Data[30] i\r
-Data[29] i\r
-Data[28] i\r
-Data[27] i\r
-Data[26] i\r
-Data[25] i\r
-Data[24] i\r
-Data[23] i\r
-Data[22] i\r
-Data[21] i\r
-Data[20] i\r
-Data[19] i\r
-Data[18] i\r
-Data[17] i\r
-Data[16] i\r
-Data[15] i\r
-Data[14] i\r
-Data[13] i\r
-Data[12] i\r
-Data[11] i\r
-Data[10] i\r
-Data[9] i\r
-Data[8] i\r
-Data[7] i\r
-Data[6] i\r
-Data[5] i\r
-Data[4] i\r
-Data[3] i\r
-Data[2] i\r
-Data[1] i\r
-Data[0] i\r
-WrClock i\r
-RdClock i\r
-WrEn i\r
-RdEn i\r
-Reset i\r
-RPReset i\r
-Q[31] o\r
-Q[30] o\r
-Q[29] o\r
-Q[28] o\r
-Q[27] o\r
-Q[26] o\r
-Q[25] o\r
-Q[24] o\r
-Q[23] o\r
-Q[22] o\r
-Q[21] o\r
-Q[20] o\r
-Q[19] o\r
-Q[18] o\r
-Q[17] o\r
-Q[16] o\r
-Q[15] o\r
-Q[14] o\r
-Q[13] o\r
-Q[12] o\r
-Q[11] o\r
-Q[10] o\r
-Q[9] o\r
-Q[8] o\r
-Q[7] o\r
-Q[6] o\r
-Q[5] o\r
-Q[4] o\r
-Q[3] o\r
-Q[2] o\r
-Q[1] o\r
-Q[0] o\r
-Empty o\r
-Full o\r
+++ /dev/null
-SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
-Fri Dec 18 03:02:30 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
- Issued command : /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n fifo_4096x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 12 -data_width 32 -num_words 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e \r
- Circuit name : fifo_4096x32\r
- Module type : ebfifo\r
- Module Version : 5.3\r
- Ports : \r
- Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
- Outputs : Q[31:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_4096x32.vhd\r
- VHDL template : fifo_4096x32_tmpl.vhd\r
- VHDL testbench : tb_fifo_4096x32_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_4096x32.srp\r
- Element Usage :\r
- AGEB2 : 14\r
- AND2 : 2\r
- CU2 : 14\r
- FADD2B : 6\r
- FD1P3BX : 2\r
- FD1P3DX : 76\r
- FD1S3BX : 1\r
- FD1S3DX : 53\r
- INV : 2\r
- OR2 : 1\r
- ROM16X1 : 34\r
- XOR2 : 24\r
- DP16KB : 8\r
- Estimated Resource Usage:\r
- LUT : 129\r
- EBR : 8\r
- Reg : 132\r
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:24:15 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_4096x32 is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_4096x32;
-
-architecture Structure of fifo_4096x32 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal co6: std_logic;
- signal wcount_12: std_logic;
- signal co5: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal co6_1: std_logic;
- signal rcount_12: std_logic;
- signal co5_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
- attribute RESETMODE of pdp_ram_0_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
- attribute RESETMODE of pdp_ram_0_1_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is "";
- attribute RESETMODE of pdp_ram_0_2_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is "";
- attribute RESETMODE of pdp_ram_0_3_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is "";
- attribute RESETMODE of pdp_ram_0_4_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is "";
- attribute RESETMODE of pdp_ram_0_5_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is "";
- attribute RESETMODE of pdp_ram_0_6_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is "";
- attribute RESETMODE of pdp_ram_0_7_0 : label is "SYNC";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t26: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t25: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t24: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t23: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t22: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t21: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t20: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t19: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t18: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t17: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t16: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t15: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t14: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t13: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t12: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t11: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t10: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t9: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t8: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t7: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t6: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t5: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t4: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t3: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t2: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t1: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t0: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r11);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w11);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_7: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_6: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6),
- DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4),
- DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_2_5: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10),
- DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8),
- DOB1=>Q(9), DOB2=>Q(10), DOB3=>Q(11), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_3_4: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14),
- DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(12),
- DOB1=>Q(13), DOB2=>Q(14), DOB3=>Q(15), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_4_3: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18),
- DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(16),
- DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_5_2: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22),
- DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(20),
- DOB1=>Q(21), DOB2=>Q(22), DOB3=>Q(23), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_6_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26),
- DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(24),
- DOB1=>Q(25), DOB2=>Q(26), DOB3=>Q(27), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_7_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30),
- DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(28),
- DOB1=>Q(29), DOB2=>Q(30), DOB3=>Q(31), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_131: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_130: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_129: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_128: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_127: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_126: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_125: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_124: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_123: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_122: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_121: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_119: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_118: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_117: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_116: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_115: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_114: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_113: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_112: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_111: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_110: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_107: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_106: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_105: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_104: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_103: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_102: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_101: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_100: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_99: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_98: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_97: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_96: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_95: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_94: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_93: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_92: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_91: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_90: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_89: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_88: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_87: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_86: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_85: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_84: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_83: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_82: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_81: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_80: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_79: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_78: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_77: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_76: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_75: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_74: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_67: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_66: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_65: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_64: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_63: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_62: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_61: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_60: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_59: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_58: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_57: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_56: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_55: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_54: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_52: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_51: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_50: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6,
- NC0=>iwcount_12, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1,
- NC0=>ircount_12, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_4096x32 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
-Fri Dec 18 03:02:30 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n fifo_4096x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 12 -data_width 32 -num_words 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e \r
- Circuit name : fifo_4096x32\r
- Module type : ebfifo\r
- Module Version : 5.3\r
- Ports : \r
- Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
- Outputs : Q[31:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_4096x32.vhd\r
- VHDL template : fifo_4096x32_tmpl.vhd\r
- VHDL testbench : tb_fifo_4096x32_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_4096x32.srp\r
- Estimated Resource Usage:\r
- LUT : 129\r
- EBR : 8\r
- Reg : 132\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: fifo_4096x32.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:24:15 2011
-
--- parameterized module component declaration
-component fifo_4096x32
- port (Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_4096x32
- port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-MODULE fifo_4096x9 DEFIN fifo_4096x9.vhd\r
- SUBMODULE FADD2B\r
- INSTANCE a1\r
- SUBMODULE VLO\r
- INSTANCE scuba_vlo_inst\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE full_cmp_ci_a\r
- SUBMODULE FADD2B\r
- INSTANCE a0\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE empty_cmp_ci_a\r
- SUBMODULE MUX21\r
- INSTANCE mux_0\r
- SUBMODULE MUX21\r
- INSTANCE mux_1\r
- SUBMODULE MUX21\r
- INSTANCE mux_2\r
- SUBMODULE MUX21\r
- INSTANCE mux_3\r
- SUBMODULE MUX21\r
- INSTANCE mux_4\r
- SUBMODULE MUX21\r
- INSTANCE mux_5\r
- SUBMODULE MUX21\r
- INSTANCE mux_6\r
- SUBMODULE MUX21\r
- INSTANCE mux_7\r
- SUBMODULE MUX21\r
- INSTANCE mux_8\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_6\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_5\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_4\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_3\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_2\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_1\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_0\r
- SUBMODULE FADD2B\r
- INSTANCE r_gctr_cia\r
- SUBMODULE VHI\r
- INSTANCE scuba_vhi_inst\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_6\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_5\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_4\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_3\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_2\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_1\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_0\r
- SUBMODULE FADD2B\r
- INSTANCE w_gctr_cia\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_0\r
- SUBMODULE FD1S3BX\r
- INSTANCE FF_1\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_2\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_3\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_4\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_5\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_6\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_7\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_8\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_9\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_10\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_11\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_12\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_13\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_14\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_15\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_16\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_17\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_18\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_19\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_20\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_21\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_22\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_23\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_24\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_25\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_26\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_27\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_28\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_29\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_30\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_31\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_32\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_33\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_34\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_35\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_36\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_37\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_38\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_39\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_40\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_41\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_42\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_43\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_44\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_45\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_46\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_47\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_48\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_49\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_50\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_51\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_52\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_53\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_54\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_55\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_56\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_57\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_58\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_59\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_60\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_61\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_62\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_63\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_64\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_65\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_66\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_67\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_68\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_69\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_70\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_71\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_72\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_73\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_74\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_75\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_76\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_77\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_78\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_79\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_80\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_81\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_82\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_83\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_84\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_85\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_86\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_87\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_88\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_89\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_90\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_91\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_92\r
- SUBMODULE FD1P3BX\r
- INSTANCE FF_93\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_94\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_95\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_96\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_97\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_98\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_99\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_100\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_101\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_102\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_103\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_104\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_105\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_106\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_107\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_108\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_109\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_110\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_111\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_112\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_113\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_114\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_115\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_116\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_117\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_118\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_119\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_120\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_121\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_122\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_123\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_124\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_125\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_126\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_127\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_128\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_129\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_130\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_131\r
- SUBMODULE FD1P3BX\r
- INSTANCE FF_132\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_0_0\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_0_1\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_0\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_1\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_2\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_3\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_4\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_5\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_6\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_7\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_8\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_9\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_10\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_11\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_12\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_13\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_14\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_15\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_16\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_17\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_18\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_19\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_20\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_21\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_22\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_23\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_24\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_25\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_26\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_27\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_28\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_29\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_30\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_31\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_32\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_33\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t0\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t1\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t2\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t3\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t4\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t5\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t6\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t7\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t8\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t9\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t10\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t11\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t12\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t13\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t14\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t15\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t16\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t17\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t18\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t19\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t20\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t21\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t22\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t23\r
- SUBMODULE OR2\r
- INSTANCE OR2_t24\r
- SUBMODULE INV\r
- INSTANCE INV_0\r
- SUBMODULE AND2\r
- INSTANCE AND2_t25\r
- SUBMODULE INV\r
- INSTANCE INV_1\r
- SUBMODULE AND2\r
- INSTANCE AND2_t26\r
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_4096x9
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:24:06
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=4096
-Width=9
-RDepth=4096
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[8] i\r
-Data[7] i\r
-Data[6] i\r
-Data[5] i\r
-Data[4] i\r
-Data[3] i\r
-Data[2] i\r
-Data[1] i\r
-Data[0] i\r
-WrClock i\r
-RdClock i\r
-WrEn i\r
-RdEn i\r
-Reset i\r
-RPReset i\r
-Q[8] o\r
-Q[7] o\r
-Q[6] o\r
-Q[5] o\r
-Q[4] o\r
-Q[3] o\r
-Q[2] o\r
-Q[1] o\r
-Q[0] o\r
-Empty o\r
-Full o\r
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Tue Jan 5 23:44:15 2010\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 12 -data_width 9 -num_words 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e \r
- Circuit name : fifo_4096x9\r
- Module type : ebfifo\r
- Module Version : 5.2\r
- Ports : \r
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
- Outputs : Q[8:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_4096x9.vhd\r
- VHDL template : fifo_4096x9_tmpl.vhd\r
- VHDL testbench : tb_fifo_4096x9_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_4096x9.srp\r
- Element Usage :\r
- AGEB2 : 14\r
- AND2 : 2\r
- CU2 : 14\r
- FADD2B : 6\r
- FD1P3BX : 2\r
- FD1P3DX : 77\r
- FD1S3BX : 1\r
- FD1S3DX : 53\r
- INV : 2\r
- MUX21 : 9\r
- OR2 : 1\r
- ROM16X1 : 34\r
- XOR2 : 24\r
- DP16KB : 2\r
- Estimated Resource Usage:\r
- LUT : 138\r
- EBR : 2\r
- Reg : 133\r
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:24:06 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_4096x9 is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_4096x9;
-
-architecture Structure of fifo_4096x9 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_12: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal co6: std_logic;
- signal wcount_12: std_logic;
- signal co5: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal co6_1: std_logic;
- signal rcount_12: std_logic;
- signal co5_1: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX21
- port (D0: in std_logic; D1: in std_logic; SD: in std_logic;
- Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is "";
- attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t26: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t25: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t24: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t23: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t22: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t21: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t20: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t19: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t18: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t17: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t16: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t15: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t14: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t13: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t12: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t11: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t10: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t9: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t8: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t7: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t6: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t5: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t4: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t3: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t2: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t1: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t0: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r11);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w11);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_132: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_131: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_130: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_129: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_128: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_127: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_126: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_125: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_124: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_123: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_122: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_121: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_119: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_118: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_117: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_116: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_115: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_114: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_113: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_112: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_111: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_110: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_107: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_106: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_105: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_104: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_103: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_102: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_101: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_100: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_99: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_98: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_97: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_96: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_95: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_94: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_93: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_92: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_91: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_90: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_89: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_88: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_87: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_86: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_85: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_84: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_83: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_82: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_81: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_80: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_79: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_78: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_77: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_76: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_75: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_74: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_68: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_67: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_66: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_65: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_64: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_63: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_62: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_61: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_60: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_59: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_58: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_57: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_56: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_55: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_54: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_52: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_51: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_50: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6,
- NC0=>iwcount_12, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1,
- NC0=>ircount_12, NC1=>open);
-
- mux_8: MUX21
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff,
- Z=>Q(0));
-
- mux_7: MUX21
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff,
- Z=>Q(1));
-
- mux_6: MUX21
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff,
- Z=>Q(2));
-
- mux_5: MUX21
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff,
- Z=>Q(3));
-
- mux_4: MUX21
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff,
- Z=>Q(4));
-
- mux_3: MUX21
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff,
- Z=>Q(5));
-
- mux_2: MUX21
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff,
- Z=>Q(6));
-
- mux_1: MUX21
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff,
- Z=>Q(7));
-
- mux_0: MUX21
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff,
- Z=>Q(8));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_4096x9 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX21 use entity ecp3.MUX21(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Tue Jan 5 23:44:15 2010\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 12 -data_width 9 -num_words 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e \r
- Circuit name : fifo_4096x9\r
- Module type : ebfifo\r
- Module Version : 5.2\r
- Ports : \r
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
- Outputs : Q[8:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_4096x9.vhd\r
- VHDL template : fifo_4096x9_tmpl.vhd\r
- VHDL testbench : tb_fifo_4096x9_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_4096x9.srp\r
- Estimated Resource Usage:\r
- LUT : 138\r
- EBR : 2\r
- Reg : 133\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: fifo_4096x9.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:24:06 2011
-
--- parameterized module component declaration
-component fifo_4096x9
- port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_4096x9
- port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-[Device]
-Family=latticeecp2m
-PartType=LFE2M100E
-PartName=LFE2M100E-5F900C
-SpeedGrade=5
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_512x32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=05/26/2011
-Time=17:17:59
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=512
-Width=32
-RDepth=512
-RWidth=32
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
--- Module Version: 5.4
---/opt/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e
-
--- Thu May 26 17:17:59 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity fifo_512x32 is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x32;
-
-architecture Structure of fifo_512x32 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KB
- -- synopsys translate_off
- generic (CSDECODE_R : in std_logic_vector(2 downto 0);
- CSDECODE_W : in std_logic_vector(2 downto 0);
- GSR : in String; RESETMODE : in String;
- REGMODE : in String; DATA_WIDTH_R : in Integer;
- DATA_WIDTH_W : in Integer);
- -- synopsys translate_on
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_R : string;
- attribute CSDECODE_W : string;
- attribute RESETMODE : string;
- attribute REGMODE : string;
- attribute DATA_WIDTH_R : string;
- attribute DATA_WIDTH_W : string;
- attribute GSR : string;
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000";
- attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
- attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
- attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG";
- attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
- attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: PDPW16KB
- -- synopsys translate_off
- generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
- DATA_WIDTH_W=> 36)
- -- synopsys translate_on
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
- ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7,
- ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open,
- DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4),
- DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9),
- DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13),
- DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
-
- FF_101: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of fifo_512x32 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-MODULE fifo_512x64 DEFIN fifo_512x64.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1P3DX
- INSTANCE FF_42
- SUBMODULE FD1P3DX
- INSTANCE FF_43
- SUBMODULE FD1P3DX
- INSTANCE FF_44
- SUBMODULE FD1P3DX
- INSTANCE FF_45
- SUBMODULE FD1P3DX
- INSTANCE FF_46
- SUBMODULE FD1P3DX
- INSTANCE FF_47
- SUBMODULE FD1P3DX
- INSTANCE FF_48
- SUBMODULE FD1P3DX
- INSTANCE FF_49
- SUBMODULE FD1P3DX
- INSTANCE FF_50
- SUBMODULE FD1P3DX
- INSTANCE FF_51
- SUBMODULE FD1P3DX
- INSTANCE FF_52
- SUBMODULE FD1P3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3BX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3BX
- INSTANCE FF_101
- SUBMODULE PDPW16KB
- INSTANCE pdp_ram_0_1_0
- SUBMODULE PDPW16KB
- INSTANCE pdp_ram_0_0_1
- SUBMODULE ROM16X1
- INSTANCE LUT4_0
- SUBMODULE ROM16X1
- INSTANCE LUT4_1
- SUBMODULE ROM16X1
- INSTANCE LUT4_2
- SUBMODULE ROM16X1
- INSTANCE LUT4_3
- SUBMODULE ROM16X1
- INSTANCE LUT4_4
- SUBMODULE ROM16X1
- INSTANCE LUT4_5
- SUBMODULE ROM16X1
- INSTANCE LUT4_6
- SUBMODULE ROM16X1
- INSTANCE LUT4_7
- SUBMODULE ROM16X1
- INSTANCE LUT4_8
- SUBMODULE ROM16X1
- INSTANCE LUT4_9
- SUBMODULE ROM16X1
- INSTANCE LUT4_10
- SUBMODULE ROM16X1
- INSTANCE LUT4_11
- SUBMODULE ROM16X1
- INSTANCE LUT4_12
- SUBMODULE ROM16X1
- INSTANCE LUT4_13
- SUBMODULE ROM16X1
- INSTANCE LUT4_14
- SUBMODULE ROM16X1
- INSTANCE LUT4_15
- SUBMODULE ROM16X1
- INSTANCE LUT4_16
- SUBMODULE ROM16X1
- INSTANCE LUT4_17
- SUBMODULE ROM16X1
- INSTANCE LUT4_18
- SUBMODULE ROM16X1
- INSTANCE LUT4_19
- SUBMODULE ROM16X1
- INSTANCE LUT4_20
- SUBMODULE ROM16X1
- INSTANCE LUT4_21
- SUBMODULE ROM16X1
- INSTANCE LUT4_22
- SUBMODULE ROM16X1
- INSTANCE LUT4_23
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE OR2
- INSTANCE OR2_t18
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t19
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t20
+++ /dev/null
-[Device]
-Family=latticeecp2m
-PartType=LFE2M100E
-PartName=LFE2M100E-5F900C
-SpeedGrade=-5
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_512x64
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=06/01/2011
-Time=17:13:21
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=512
-Width=72
-RDepth=512
-RWidth=72
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[71] i
-Data[70] i
-Data[69] i
-Data[68] i
-Data[67] i
-Data[66] i
-Data[65] i
-Data[64] i
-Data[63] i
-Data[62] i
-Data[61] i
-Data[60] i
-Data[59] i
-Data[58] i
-Data[57] i
-Data[56] i
-Data[55] i
-Data[54] i
-Data[53] i
-Data[52] i
-Data[51] i
-Data[50] i
-Data[49] i
-Data[48] i
-Data[47] i
-Data[46] i
-Data[45] i
-Data[44] i
-Data[43] i
-Data[42] i
-Data[41] i
-Data[40] i
-Data[39] i
-Data[38] i
-Data[37] i
-Data[36] i
-Data[35] i
-Data[34] i
-Data[33] i
-Data[32] i
-Data[31] i
-Data[30] i
-Data[29] i
-Data[28] i
-Data[27] i
-Data[26] i
-Data[25] i
-Data[24] i
-Data[23] i
-Data[22] i
-Data[21] i
-Data[20] i
-Data[19] i
-Data[18] i
-Data[17] i
-Data[16] i
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[71] o
-Q[70] o
-Q[69] o
-Q[68] o
-Q[67] o
-Q[66] o
-Q[65] o
-Q[64] o
-Q[63] o
-Q[62] o
-Q[61] o
-Q[60] o
-Q[59] o
-Q[58] o
-Q[57] o
-Q[56] o
-Q[55] o
-Q[54] o
-Q[53] o
-Q[52] o
-Q[51] o
-Q[50] o
-Q[49] o
-Q[48] o
-Q[47] o
-Q[46] o
-Q[45] o
-Q[44] o
-Q[43] o
-Q[42] o
-Q[41] o
-Q[40] o
-Q[39] o
-Q[38] o
-Q[37] o
-Q[36] o
-Q[35] o
-Q[34] o
-Q[33] o
-Q[32] o
-Q[31] o
-Q[30] o
-Q[29] o
-Q[28] o
-Q[27] o
-Q[26] o
-Q[25] o
-Q[24] o
-Q[23] o
-Q[22] o
-Q[21] o
-Q[20] o
-Q[19] o
-Q[18] o
-Q[17] o
-Q[16] o
-Q[15] o
-Q[14] o
-Q[13] o
-Q[12] o
-Q[11] o
-Q[10] o
-Q[9] o
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-SCUBA, Version ispLever_v8.1_PROD_Build (20)
-Wed Jun 1 17:13:21 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x64
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[71:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x64.vhd
- VHDL template : fifo_512x64_tmpl.vhd
- VHDL testbench : tb_fifo_512x64_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x64.srp
- Element Usage :
- AGEB2 : 10
- AND2 : 2
- CU2 : 10
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 58
- FD1S3BX : 1
- FD1S3DX : 41
- INV : 2
- OR2 : 1
- ROM16X1 : 24
- XOR2 : 18
- PDPW16KB : 2
- Estimated Resource Usage:
- LUT : 97
- EBR : 2
- Reg : 102
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20)
--- Module Version: 5.4
---/opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
-
--- Wed Jun 1 17:13:21 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity fifo_512x64 is
- port (
- Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x64;
-
-architecture Structure of fifo_512x64 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KB
- -- synopsys translate_off
- generic (CSDECODE_R : in std_logic_vector(2 downto 0);
- CSDECODE_W : in std_logic_vector(2 downto 0);
- GSR : in String; RESETMODE : in String;
- REGMODE : in String; DATA_WIDTH_R : in Integer;
- DATA_WIDTH_W : in Integer);
- -- synopsys translate_on
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_R : string;
- attribute CSDECODE_W : string;
- attribute RESETMODE : string;
- attribute REGMODE : string;
- attribute DATA_WIDTH_R : string;
- attribute DATA_WIDTH_W : string;
- attribute GSR : string;
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x64.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute CSDECODE_R of pdp_ram_0_0_1 : label is "0b000";
- attribute CSDECODE_W of pdp_ram_0_0_1 : label is "0b001";
- attribute GSR of pdp_ram_0_0_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";
- attribute REGMODE of pdp_ram_0_0_1 : label is "NOREG";
- attribute DATA_WIDTH_R of pdp_ram_0_0_1 : label is "36";
- attribute DATA_WIDTH_W of pdp_ram_0_0_1 : label is "36";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x64.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute CSDECODE_R of pdp_ram_0_1_0 : label is "0b000";
- attribute CSDECODE_W of pdp_ram_0_1_0 : label is "0b001";
- attribute GSR of pdp_ram_0_1_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC";
- attribute REGMODE of pdp_ram_0_1_0 : label is "NOREG";
- attribute DATA_WIDTH_R of pdp_ram_0_1_0 : label is "36";
- attribute DATA_WIDTH_W of pdp_ram_0_1_0 : label is "36";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: PDPW16KB
- -- synopsys translate_off
- generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
- DATA_WIDTH_W=> 36)
- -- synopsys translate_on
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
- ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
- DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
- pdp_ram_0_1_0: PDPW16KB
- -- synopsys translate_off
- generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
- DATA_WIDTH_W=> 36)
- -- synopsys translate_on
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
- DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
- DI14=>Data(50), DI15=>Data(51), DI16=>Data(52),
- DI17=>Data(53), DI18=>Data(54), DI19=>Data(55),
- DI20=>Data(56), DI21=>Data(57), DI22=>Data(58),
- DI23=>Data(59), DI24=>Data(60), DI25=>Data(61),
- DI26=>Data(62), DI27=>Data(63), DI28=>Data(64),
- DI29=>Data(65), DI30=>Data(66), DI31=>Data(67),
- DI32=>Data(68), DI33=>Data(69), DI34=>Data(70),
- DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
- ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
- ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi,
- BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock,
- CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
- ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
- ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
- ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5,
- ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55),
- DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60),
- DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65),
- DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69),
- DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37),
- DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
- DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45),
- DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49),
- DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53));
-
- FF_101: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of fifo_512x64 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process:
-
-SCUBA, Version ispLever_v8.1_PROD_Build (20)
-Wed Jun 1 17:13:21 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x64
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[71:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x64.vhd
- VHDL template : fifo_512x64_tmpl.vhd
- VHDL testbench : tb_fifo_512x64_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x64.srp
- Estimated Resource Usage:
- LUT : 97
- EBR : 2
- Reg : 102
-
-END SCUBA Module Synthesis
-
-File: fifo_512x64.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v8.1_PROD_Build (20)
--- Module Version: 5.4
--- Wed Jun 1 17:13:21 2011
-
--- parameterized module component declaration
-component fifo_512x64
- port (Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_512x64
- port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-MODULE fifo_512x72 DEFIN fifo_512x72.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1P3DX
- INSTANCE FF_42
- SUBMODULE FD1P3DX
- INSTANCE FF_43
- SUBMODULE FD1P3DX
- INSTANCE FF_44
- SUBMODULE FD1P3DX
- INSTANCE FF_45
- SUBMODULE FD1P3DX
- INSTANCE FF_46
- SUBMODULE FD1P3DX
- INSTANCE FF_47
- SUBMODULE FD1P3DX
- INSTANCE FF_48
- SUBMODULE FD1P3DX
- INSTANCE FF_49
- SUBMODULE FD1P3DX
- INSTANCE FF_50
- SUBMODULE FD1P3DX
- INSTANCE FF_51
- SUBMODULE FD1P3DX
- INSTANCE FF_52
- SUBMODULE FD1P3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3BX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3BX
- INSTANCE FF_101
- SUBMODULE PDPW16KB
- INSTANCE pdp_ram_0_1_0
- SUBMODULE PDPW16KB
- INSTANCE pdp_ram_0_0_1
- SUBMODULE ROM16X1
- INSTANCE LUT4_0
- SUBMODULE ROM16X1
- INSTANCE LUT4_1
- SUBMODULE ROM16X1
- INSTANCE LUT4_2
- SUBMODULE ROM16X1
- INSTANCE LUT4_3
- SUBMODULE ROM16X1
- INSTANCE LUT4_4
- SUBMODULE ROM16X1
- INSTANCE LUT4_5
- SUBMODULE ROM16X1
- INSTANCE LUT4_6
- SUBMODULE ROM16X1
- INSTANCE LUT4_7
- SUBMODULE ROM16X1
- INSTANCE LUT4_8
- SUBMODULE ROM16X1
- INSTANCE LUT4_9
- SUBMODULE ROM16X1
- INSTANCE LUT4_10
- SUBMODULE ROM16X1
- INSTANCE LUT4_11
- SUBMODULE ROM16X1
- INSTANCE LUT4_12
- SUBMODULE ROM16X1
- INSTANCE LUT4_13
- SUBMODULE ROM16X1
- INSTANCE LUT4_14
- SUBMODULE ROM16X1
- INSTANCE LUT4_15
- SUBMODULE ROM16X1
- INSTANCE LUT4_16
- SUBMODULE ROM16X1
- INSTANCE LUT4_17
- SUBMODULE ROM16X1
- INSTANCE LUT4_18
- SUBMODULE ROM16X1
- INSTANCE LUT4_19
- SUBMODULE ROM16X1
- INSTANCE LUT4_20
- SUBMODULE ROM16X1
- INSTANCE LUT4_21
- SUBMODULE ROM16X1
- INSTANCE LUT4_22
- SUBMODULE ROM16X1
- INSTANCE LUT4_23
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE OR2
- INSTANCE OR2_t18
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t19
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t20
+++ /dev/null
-[Device]
-Family=latticeecp2m
-PartType=LFE2M100E
-PartName=LFE2M100E-5F900C
-SpeedGrade=-5
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_512x72
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=06/01/2011
-Time=17:14:00
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=512
-Width=72
-RDepth=512
-RWidth=72
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[71] i
-Data[70] i
-Data[69] i
-Data[68] i
-Data[67] i
-Data[66] i
-Data[65] i
-Data[64] i
-Data[63] i
-Data[62] i
-Data[61] i
-Data[60] i
-Data[59] i
-Data[58] i
-Data[57] i
-Data[56] i
-Data[55] i
-Data[54] i
-Data[53] i
-Data[52] i
-Data[51] i
-Data[50] i
-Data[49] i
-Data[48] i
-Data[47] i
-Data[46] i
-Data[45] i
-Data[44] i
-Data[43] i
-Data[42] i
-Data[41] i
-Data[40] i
-Data[39] i
-Data[38] i
-Data[37] i
-Data[36] i
-Data[35] i
-Data[34] i
-Data[33] i
-Data[32] i
-Data[31] i
-Data[30] i
-Data[29] i
-Data[28] i
-Data[27] i
-Data[26] i
-Data[25] i
-Data[24] i
-Data[23] i
-Data[22] i
-Data[21] i
-Data[20] i
-Data[19] i
-Data[18] i
-Data[17] i
-Data[16] i
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[71] o
-Q[70] o
-Q[69] o
-Q[68] o
-Q[67] o
-Q[66] o
-Q[65] o
-Q[64] o
-Q[63] o
-Q[62] o
-Q[61] o
-Q[60] o
-Q[59] o
-Q[58] o
-Q[57] o
-Q[56] o
-Q[55] o
-Q[54] o
-Q[53] o
-Q[52] o
-Q[51] o
-Q[50] o
-Q[49] o
-Q[48] o
-Q[47] o
-Q[46] o
-Q[45] o
-Q[44] o
-Q[43] o
-Q[42] o
-Q[41] o
-Q[40] o
-Q[39] o
-Q[38] o
-Q[37] o
-Q[36] o
-Q[35] o
-Q[34] o
-Q[33] o
-Q[32] o
-Q[31] o
-Q[30] o
-Q[29] o
-Q[28] o
-Q[27] o
-Q[26] o
-Q[25] o
-Q[24] o
-Q[23] o
-Q[22] o
-Q[21] o
-Q[20] o
-Q[19] o
-Q[18] o
-Q[17] o
-Q[16] o
-Q[15] o
-Q[14] o
-Q[13] o
-Q[12] o
-Q[11] o
-Q[10] o
-Q[9] o
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-SCUBA, Version ispLever_v8.1_PROD_Build (20)
-Wed Jun 1 17:14:00 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x72
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[71:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x72.vhd
- VHDL template : fifo_512x72_tmpl.vhd
- VHDL testbench : tb_fifo_512x72_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x72.srp
- Element Usage :
- AGEB2 : 10
- AND2 : 2
- CU2 : 10
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 58
- FD1S3BX : 1
- FD1S3DX : 41
- INV : 2
- OR2 : 1
- ROM16X1 : 24
- XOR2 : 18
- PDPW16KB : 2
- Estimated Resource Usage:
- LUT : 97
- EBR : 2
- Reg : 102
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20)
--- Module Version: 5.4
---/opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
-
--- Wed Jun 1 17:14:00 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity fifo_512x72 is
- port (
- Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x72;
-
-architecture Structure of fifo_512x72 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KB
- -- synopsys translate_off
- generic (CSDECODE_R : in std_logic_vector(2 downto 0);
- CSDECODE_W : in std_logic_vector(2 downto 0);
- GSR : in String; RESETMODE : in String;
- REGMODE : in String; DATA_WIDTH_R : in Integer;
- DATA_WIDTH_W : in Integer);
- -- synopsys translate_on
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_R : string;
- attribute CSDECODE_W : string;
- attribute RESETMODE : string;
- attribute REGMODE : string;
- attribute DATA_WIDTH_R : string;
- attribute DATA_WIDTH_W : string;
- attribute GSR : string;
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x72.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute CSDECODE_R of pdp_ram_0_0_1 : label is "0b000";
- attribute CSDECODE_W of pdp_ram_0_0_1 : label is "0b001";
- attribute GSR of pdp_ram_0_0_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";
- attribute REGMODE of pdp_ram_0_0_1 : label is "NOREG";
- attribute DATA_WIDTH_R of pdp_ram_0_0_1 : label is "36";
- attribute DATA_WIDTH_W of pdp_ram_0_0_1 : label is "36";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x72.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute CSDECODE_R of pdp_ram_0_1_0 : label is "0b000";
- attribute CSDECODE_W of pdp_ram_0_1_0 : label is "0b001";
- attribute GSR of pdp_ram_0_1_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC";
- attribute REGMODE of pdp_ram_0_1_0 : label is "NOREG";
- attribute DATA_WIDTH_R of pdp_ram_0_1_0 : label is "36";
- attribute DATA_WIDTH_W of pdp_ram_0_1_0 : label is "36";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: PDPW16KB
- -- synopsys translate_off
- generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
- DATA_WIDTH_W=> 36)
- -- synopsys translate_on
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
- ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
- DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
- pdp_ram_0_1_0: PDPW16KB
- -- synopsys translate_off
- generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
- DATA_WIDTH_W=> 36)
- -- synopsys translate_on
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
- DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
- DI14=>Data(50), DI15=>Data(51), DI16=>Data(52),
- DI17=>Data(53), DI18=>Data(54), DI19=>Data(55),
- DI20=>Data(56), DI21=>Data(57), DI22=>Data(58),
- DI23=>Data(59), DI24=>Data(60), DI25=>Data(61),
- DI26=>Data(62), DI27=>Data(63), DI28=>Data(64),
- DI29=>Data(65), DI30=>Data(66), DI31=>Data(67),
- DI32=>Data(68), DI33=>Data(69), DI34=>Data(70),
- DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
- ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
- ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi,
- BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock,
- CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
- ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
- ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
- ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5,
- ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55),
- DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60),
- DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65),
- DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69),
- DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37),
- DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
- DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45),
- DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49),
- DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53));
-
- FF_101: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of fifo_512x72 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process:
-
-SCUBA, Version ispLever_v8.1_PROD_Build (20)
-Wed Jun 1 17:14:00 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x72
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[71:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x72.vhd
- VHDL template : fifo_512x72_tmpl.vhd
- VHDL testbench : tb_fifo_512x72_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x72.srp
- Estimated Resource Usage:
- LUT : 97
- EBR : 2
- Reg : 102
-
-END SCUBA Module Synthesis
-
-File: fifo_512x72.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v8.1_PROD_Build (20)
--- Module Version: 5.4
--- Wed Jun 1 17:14:00 2011
-
--- parameterized module component declaration
-component fifo_512x72
- port (Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_512x72
- port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-MODULE fifo_64kx8 DEFIN fifo_64kx8.vhd\r
- SUBMODULE FADD2B\r
- INSTANCE a1\r
- SUBMODULE VLO\r
- INSTANCE scuba_vlo_inst\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_8\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_7\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE full_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE full_cmp_ci_a\r
- SUBMODULE FADD2B\r
- INSTANCE a0\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_8\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_7\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_6\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_5\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_4\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_3\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_2\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_1\r
- SUBMODULE AGEB2\r
- INSTANCE empty_cmp_0\r
- SUBMODULE FADD2B\r
- INSTANCE empty_cmp_ci_a\r
- SUBMODULE MUX41\r
- INSTANCE mux_0\r
- SUBMODULE MUX41\r
- INSTANCE mux_1\r
- SUBMODULE MUX41\r
- INSTANCE mux_2\r
- SUBMODULE MUX41\r
- INSTANCE mux_3\r
- SUBMODULE MUX41\r
- INSTANCE mux_4\r
- SUBMODULE MUX41\r
- INSTANCE mux_5\r
- SUBMODULE MUX41\r
- INSTANCE mux_6\r
- SUBMODULE MUX41\r
- INSTANCE mux_7\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_8\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_7\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_6\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_5\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_4\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_3\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_2\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_1\r
- SUBMODULE CU2\r
- INSTANCE r_gctr_0\r
- SUBMODULE FADD2B\r
- INSTANCE r_gctr_cia\r
- SUBMODULE VHI\r
- INSTANCE scuba_vhi_inst\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_8\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_7\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_6\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_5\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_4\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_3\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_2\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_1\r
- SUBMODULE CU2\r
- INSTANCE w_gctr_0\r
- SUBMODULE FADD2B\r
- INSTANCE w_gctr_cia\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_0\r
- SUBMODULE FD1S3BX\r
- INSTANCE FF_1\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_2\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_3\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_4\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_5\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_6\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_7\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_8\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_9\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_10\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_11\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_12\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_13\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_14\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_15\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_16\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_17\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_18\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_19\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_20\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_21\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_22\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_23\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_24\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_25\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_26\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_27\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_28\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_29\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_30\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_31\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_32\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_33\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_34\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_35\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_36\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_37\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_38\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_39\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_40\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_41\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_42\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_43\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_44\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_45\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_46\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_47\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_48\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_49\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_50\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_51\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_52\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_53\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_54\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_55\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_56\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_57\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_58\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_59\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_60\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_61\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_62\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_63\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_64\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_65\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_66\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_67\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_68\r
- SUBMODULE FD1S3DX\r
- INSTANCE FF_69\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_70\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_71\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_72\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_73\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_74\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_75\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_76\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_77\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_78\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_79\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_80\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_81\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_82\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_83\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_84\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_85\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_86\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_87\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_88\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_89\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_90\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_91\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_92\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_93\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_94\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_95\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_96\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_97\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_98\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_99\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_100\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_101\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_102\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_103\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_104\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_105\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_106\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_107\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_108\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_109\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_110\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_111\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_112\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_113\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_114\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_115\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_116\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_117\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_118\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_119\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_120\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_121\r
- SUBMODULE FD1P3BX\r
- INSTANCE FF_122\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_123\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_124\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_125\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_126\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_127\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_128\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_129\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_130\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_131\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_132\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_133\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_134\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_135\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_136\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_137\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_138\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_139\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_140\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_141\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_142\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_143\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_144\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_145\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_146\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_147\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_148\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_149\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_150\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_151\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_152\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_153\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_154\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_155\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_156\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_157\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_158\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_159\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_160\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_161\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_162\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_163\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_164\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_165\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_166\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_167\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_168\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_169\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_170\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_171\r
- SUBMODULE FD1P3DX\r
- INSTANCE FF_172\r
- SUBMODULE FD1P3BX\r
- INSTANCE FF_173\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_7_0\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_6_1\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_5_2\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_4_3\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_3_4\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_2_5\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_1_6\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_3_0_7\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_7_8\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_6_9\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_5_10\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_4_11\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_3_12\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_2_13\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_1_14\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_2_0_15\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_7_16\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_6_17\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_5_18\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_4_19\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_3_20\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_2_21\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_1_22\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_1_0_23\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_7_24\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_6_25\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_5_26\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_4_27\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_3_28\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_2_29\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_1_30\r
- SUBMODULE DP16KB\r
- INSTANCE pdp_ram_0_0_31\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_0\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_1\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_2\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_3\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_4\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_5\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_6\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_7\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_8\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_9\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_10\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_11\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_12\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_13\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_14\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_15\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_16\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_17\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_18\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_19\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_20\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_21\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_22\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_23\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_24\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_25\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_26\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_27\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_28\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_29\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_30\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_31\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_32\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_33\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_34\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_35\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_36\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_37\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_38\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_39\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_40\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_41\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_42\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_43\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_44\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_45\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_46\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_47\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_48\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_49\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_50\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_51\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_52\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_53\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_54\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_55\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_56\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_57\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_58\r
- SUBMODULE ROM16X1\r
- INSTANCE LUT4_59\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t0\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t1\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t2\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t3\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t4\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t5\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t6\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t7\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t8\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t9\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t10\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t11\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t12\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t13\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t14\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t15\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t16\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t17\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t18\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t19\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t20\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t21\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t22\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t23\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t24\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t25\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t26\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t27\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t28\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t29\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t30\r
- SUBMODULE XOR2\r
- INSTANCE XOR2_t31\r
- SUBMODULE OR2\r
- INSTANCE OR2_t32\r
- SUBMODULE INV\r
- INSTANCE INV_0\r
- SUBMODULE AND2\r
- INSTANCE AND2_t33\r
- SUBMODULE INV\r
- INSTANCE INV_1\r
- SUBMODULE AND2\r
- INSTANCE AND2_t34\r
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_64kx8
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:23:03
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=65536
-Width=8
-RDepth=65536
-RWidth=8
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[7] i\r
-Data[6] i\r
-Data[5] i\r
-Data[4] i\r
-Data[3] i\r
-Data[2] i\r
-Data[1] i\r
-Data[0] i\r
-WrClock i\r
-RdClock i\r
-WrEn i\r
-RdEn i\r
-Reset i\r
-RPReset i\r
-Q[7] o\r
-Q[6] o\r
-Q[5] o\r
-Q[4] o\r
-Q[3] o\r
-Q[2] o\r
-Q[1] o\r
-Q[0] o\r
-Empty o\r
-Full o\r
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Sat Dec 26 00:12:05 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_64kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 8 -num_words 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e \r
- Circuit name : fifo_64kx8\r
- Module type : ebfifo\r
- Module Version : 5.2\r
- Ports : \r
- Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
- Outputs : Q[7:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_64kx8.vhd\r
- VHDL template : fifo_64kx8_tmpl.vhd\r
- VHDL testbench : tb_fifo_64kx8_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_64kx8.srp\r
- Element Usage :\r
- AGEB2 : 18\r
- AND2 : 2\r
- CU2 : 18\r
- FADD2B : 6\r
- FD1P3BX : 2\r
- FD1P3DX : 102\r
- FD1S3BX : 1\r
- FD1S3DX : 69\r
- INV : 2\r
- MUX41 : 8\r
- OR2 : 1\r
- ROM16X1 : 60\r
- XOR2 : 32\r
- DP16KB : 32\r
- Estimated Resource Usage:\r
- LUT : 187\r
- EBR : 32\r
- Reg : 174\r
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 8 -depth 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:23:03 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_64kx8 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_64kx8;
-
-architecture Structure of fifo_64kx8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_9: std_logic;
- signal func_xor_inet_8: std_logic;
- signal func_xor_inet_7: std_logic;
- signal func_xor_inet_6: std_logic;
- signal func_xor_inet_10: std_logic;
- signal func_xor_inet_11: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal w_gdata_15: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wptr_15: std_logic;
- signal wptr_16: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_16: std_logic;
- signal rptr_14: std_logic;
- signal rptr_15: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal w_gcount_16: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal w_gcount_r216: std_logic;
- signal w_gcount_r16: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co6: std_logic;
- signal iwcount_16: std_logic;
- signal co8: std_logic;
- signal wcount_16: std_logic;
- signal co7: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8_1: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal wcount_r12: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal wcount_r14: std_logic;
- signal wcount_r15: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal rcount_w12: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal rcount_w14: std_logic;
- signal rcount_w15: std_logic;
- signal wcount_14: std_logic;
- signal wcount_15: std_logic;
- signal co7_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX41
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
- Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is "";
- attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is "";
- attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is "";
- attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is "";
- attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is "";
- attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is "";
- attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is "";
- attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is "";
- attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is "";
- attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is "";
- attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is "";
- attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is "";
- attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is "";
- attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is "";
- attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is "";
- attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is "";
- attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is "";
- attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is "";
- attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is "";
- attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is "";
- attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is "";
- attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is "";
- attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is "";
- attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is "";
- attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is "";
- attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is "";
- attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is "";
- attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is "";
- attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is "";
- attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is "";
- attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is "";
- attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t34: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t33: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t32: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t31: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t30: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t29: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t28: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t27: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t26: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t25: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t24: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t23: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t22: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t21: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t20: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t19: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t18: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t17: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t16: XOR2
- port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15);
-
- XOR2_t15: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t14: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t13: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t12: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t11: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t10: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t9: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t8: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t7: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t6: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t5: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t4: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t3: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t2: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t1: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t0: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- LUT4_59: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>w_gcount_r216,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_58: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_57: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_56: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_55: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r15);
-
- LUT4_54: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215,
- AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_53: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0,
- DO0=>wcount_r10);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r3);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r2);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r1);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_10);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7,
- AD1=>func_xor_inet_8, AD0=>func_xor_inet_9,
- DO0=>func_xor_inet_11);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_31: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_30: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_2_29: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_3_28: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_4_27: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_5_26: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_6_25: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_7_24: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_23: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_1_22: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_2_21: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_3_20: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_4_19: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_5_18: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_6_17: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_7_16: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_15: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_1_14: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_2_13: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_3_12: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_4_11: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_5_10: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_6_9: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_7_8: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_7: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_1_6: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_2_5: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_3_4: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_4_3: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_5_2: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_6_1: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_7_0: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_173: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_172: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_171: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_170: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_169: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_168: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_167: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_166: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_165: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_164: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_163: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_162: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_161: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_160: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_159: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_158: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_157: FD1P3DX
- port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_16);
-
- FF_156: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_155: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_154: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_153: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_152: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_151: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_150: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_149: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_148: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_147: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_146: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_145: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_144: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_143: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_142: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_141: FD1P3DX
- port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_140: FD1P3DX
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_16);
-
- FF_139: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_138: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_137: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_136: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_135: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_134: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_133: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_132: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_131: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_130: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_129: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_128: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_127: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_126: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_125: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_124: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_123: FD1P3DX
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_16);
-
- FF_122: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_121: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_120: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_119: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_118: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_117: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_116: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_115: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_114: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_113: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_112: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_111: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_110: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_109: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_108: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_107: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_106: FD1P3DX
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_105: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_104: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_103: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_102: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_101: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_100: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_99: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_98: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_97: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_96: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_95: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_94: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_93: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_92: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_91: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_90: FD1P3DX
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_89: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_88: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_87: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_86: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_85: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_84: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_83: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_82: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_81: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_80: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_79: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_78: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_77: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_76: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_75: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_74: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_73: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_72: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_71: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_70: FD1P3DX
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_69: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_68: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_67: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_66: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_65: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_64: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_63: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_62: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_61: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_60: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_59: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_58: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_57: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_56: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_55: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_54: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r16);
-
- FF_52: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_51: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_50: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_49: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_48: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_47: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_46: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_45: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_44: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_43: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_42: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_41: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_31: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_30: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_29: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_28: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r216);
-
- FF_18: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_17: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_16: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_15: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- w_gctr_8: CU2
- port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>iwcount_16, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1,
- NC0=>ircount_16, NC1=>open);
-
- mux_7: MUX41
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0));
-
- mux_6: MUX41
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1));
-
- mux_5: MUX41
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2));
-
- mux_4: MUX41
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3));
-
- mux_3: MUX41
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4));
-
- mux_2: MUX41
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5));
-
- mux_1: MUX41
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6));
-
- mux_0: MUX41
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12,
- B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14,
- B1=>wcount_r15, CI=>co6_2, GE=>co7_2);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14,
- B1=>rcount_w15, CI=>co6_3, GE=>co7_3);
-
- full_cmp_8: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_64kx8 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX41 use entity ecp3.MUX41(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Sat Dec 26 00:12:05 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_64kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 8 -num_words 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e \r
- Circuit name : fifo_64kx8\r
- Module type : ebfifo\r
- Module Version : 5.2\r
- Ports : \r
- Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
- Outputs : Q[7:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_64kx8.vhd\r
- VHDL template : fifo_64kx8_tmpl.vhd\r
- VHDL testbench : tb_fifo_64kx8_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_64kx8.srp\r
- Estimated Resource Usage:\r
- LUT : 187\r
- EBR : 32\r
- Reg : 174\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: fifo_64kx8.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:23:03 2011
-
--- parameterized module component declaration
-component fifo_64kx8
- port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_64kx8
- port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_64kx9
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:23:21
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=65536
-Width=9
-RDepth=65536
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:21 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_64kx9
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_64kx9.vhd
- VHDL template : fifo_64kx9_tmpl.vhd
- VHDL testbench : tb_fifo_64kx9_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_64kx9.srp
- Element Usage :
- AGEB2 : 18
- AND2 : 2
- CU2 : 18
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 105
- FD1S3BX : 1
- FD1S3DX : 69
- INV : 12
- MUX321 : 9
- OR2 : 1
- ROM16X1A : 188
- XOR2 : 32
- DP16KC : 32
- Estimated Resource Usage:
- LUT : 379
- EBR : 32
- Reg : 177
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:23:21 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_64kx9 is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_64kx9;
-
-architecture Structure of fifo_64kx9 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal func_and_inet: std_logic;
- signal func_and_inet_1: std_logic;
- signal func_and_inet_2: std_logic;
- signal func_and_inet_3: std_logic;
- signal func_and_inet_4: std_logic;
- signal func_and_inet_5: std_logic;
- signal func_and_inet_6: std_logic;
- signal func_and_inet_7: std_logic;
- signal func_and_inet_8: std_logic;
- signal func_and_inet_9: std_logic;
- signal func_and_inet_10: std_logic;
- signal func_and_inet_11: std_logic;
- signal func_and_inet_12: std_logic;
- signal func_and_inet_13: std_logic;
- signal func_and_inet_14: std_logic;
- signal func_and_inet_15: std_logic;
- signal func_and_inet_16: std_logic;
- signal func_and_inet_17: std_logic;
- signal func_and_inet_18: std_logic;
- signal func_and_inet_19: std_logic;
- signal func_and_inet_20: std_logic;
- signal func_and_inet_21: std_logic;
- signal func_and_inet_22: std_logic;
- signal func_and_inet_23: std_logic;
- signal func_and_inet_24: std_logic;
- signal func_and_inet_25: std_logic;
- signal func_and_inet_26: std_logic;
- signal func_and_inet_27: std_logic;
- signal func_and_inet_28: std_logic;
- signal func_and_inet_29: std_logic;
- signal wptr_15_inv: std_logic;
- signal func_and_inet_30: std_logic;
- signal rptr_15_inv: std_logic;
- signal func_and_inet_31: std_logic;
- signal func_and_inet_32: std_logic;
- signal func_and_inet_33: std_logic;
- signal func_and_inet_34: std_logic;
- signal func_and_inet_35: std_logic;
- signal func_and_inet_36: std_logic;
- signal func_and_inet_37: std_logic;
- signal func_and_inet_38: std_logic;
- signal func_and_inet_39: std_logic;
- signal func_and_inet_40: std_logic;
- signal func_and_inet_41: std_logic;
- signal func_and_inet_42: std_logic;
- signal func_and_inet_43: std_logic;
- signal func_and_inet_44: std_logic;
- signal func_and_inet_45: std_logic;
- signal wptr_14_inv: std_logic;
- signal func_and_inet_46: std_logic;
- signal rptr_14_inv: std_logic;
- signal func_and_inet_47: std_logic;
- signal func_and_inet_48: std_logic;
- signal func_and_inet_49: std_logic;
- signal func_and_inet_50: std_logic;
- signal func_and_inet_51: std_logic;
- signal func_and_inet_52: std_logic;
- signal func_and_inet_53: std_logic;
- signal wptr_13_inv: std_logic;
- signal func_and_inet_54: std_logic;
- signal rptr_13_inv: std_logic;
- signal func_and_inet_55: std_logic;
- signal func_and_inet_56: std_logic;
- signal func_and_inet_57: std_logic;
- signal wptr_12_inv: std_logic;
- signal func_and_inet_58: std_logic;
- signal rptr_12_inv: std_logic;
- signal func_and_inet_59: std_logic;
- signal wptr_11_inv: std_logic;
- signal func_and_inet_60: std_logic;
- signal rptr_11_inv: std_logic;
- signal func_and_inet_61: std_logic;
- signal func_and_inet_62: std_logic;
- signal func_and_inet_63: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_9: std_logic;
- signal func_xor_inet_8: std_logic;
- signal func_xor_inet_7: std_logic;
- signal func_xor_inet_6: std_logic;
- signal func_xor_inet_10: std_logic;
- signal func_xor_inet_11: std_logic;
- signal dec1_r10: std_logic;
- signal dec0_p00: std_logic;
- signal dec3_r11: std_logic;
- signal dec2_p01: std_logic;
- signal dec5_r12: std_logic;
- signal dec4_p02: std_logic;
- signal dec7_r13: std_logic;
- signal dec6_p03: std_logic;
- signal dec9_r14: std_logic;
- signal dec8_p04: std_logic;
- signal dec11_r15: std_logic;
- signal dec10_p05: std_logic;
- signal dec13_r16: std_logic;
- signal dec12_p06: std_logic;
- signal dec15_r17: std_logic;
- signal dec14_p07: std_logic;
- signal dec17_r18: std_logic;
- signal dec16_p08: std_logic;
- signal dec19_r19: std_logic;
- signal dec18_p09: std_logic;
- signal dec21_r110: std_logic;
- signal dec20_p010: std_logic;
- signal dec23_r111: std_logic;
- signal dec22_p011: std_logic;
- signal dec25_r112: std_logic;
- signal dec24_p012: std_logic;
- signal dec27_r113: std_logic;
- signal dec26_p013: std_logic;
- signal dec29_r114: std_logic;
- signal dec28_p014: std_logic;
- signal dec31_r115: std_logic;
- signal dec30_p015: std_logic;
- signal dec33_r116: std_logic;
- signal dec32_p016: std_logic;
- signal dec35_r117: std_logic;
- signal dec34_p017: std_logic;
- signal dec37_r118: std_logic;
- signal dec36_p018: std_logic;
- signal dec39_r119: std_logic;
- signal dec38_p019: std_logic;
- signal dec41_r120: std_logic;
- signal dec40_p020: std_logic;
- signal dec43_r121: std_logic;
- signal dec42_p021: std_logic;
- signal dec45_r122: std_logic;
- signal dec44_p022: std_logic;
- signal dec47_r123: std_logic;
- signal dec46_p023: std_logic;
- signal dec49_r124: std_logic;
- signal dec48_p024: std_logic;
- signal dec51_r125: std_logic;
- signal dec50_p025: std_logic;
- signal dec53_r126: std_logic;
- signal dec52_p026: std_logic;
- signal dec55_r127: std_logic;
- signal dec54_p027: std_logic;
- signal dec57_r128: std_logic;
- signal dec56_p028: std_logic;
- signal dec59_r129: std_logic;
- signal dec58_p029: std_logic;
- signal dec61_r130: std_logic;
- signal dec60_p030: std_logic;
- signal dec63_r131: std_logic;
- signal dec62_p031: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal w_gdata_15: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wptr_15: std_logic;
- signal wptr_16: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_16: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rptr_15: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal w_gcount_16: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal w_gcount_r216: std_logic;
- signal w_gcount_r16: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co6: std_logic;
- signal iwcount_16: std_logic;
- signal co8: std_logic;
- signal wcount_16: std_logic;
- signal co7: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8_1: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_31_0: std_logic;
- signal mdout1_30_0: std_logic;
- signal mdout1_29_0: std_logic;
- signal mdout1_28_0: std_logic;
- signal mdout1_27_0: std_logic;
- signal mdout1_26_0: std_logic;
- signal mdout1_25_0: std_logic;
- signal mdout1_24_0: std_logic;
- signal mdout1_23_0: std_logic;
- signal mdout1_22_0: std_logic;
- signal mdout1_21_0: std_logic;
- signal mdout1_20_0: std_logic;
- signal mdout1_19_0: std_logic;
- signal mdout1_18_0: std_logic;
- signal mdout1_17_0: std_logic;
- signal mdout1_16_0: std_logic;
- signal mdout1_15_0: std_logic;
- signal mdout1_14_0: std_logic;
- signal mdout1_13_0: std_logic;
- signal mdout1_12_0: std_logic;
- signal mdout1_11_0: std_logic;
- signal mdout1_10_0: std_logic;
- signal mdout1_9_0: std_logic;
- signal mdout1_8_0: std_logic;
- signal mdout1_7_0: std_logic;
- signal mdout1_6_0: std_logic;
- signal mdout1_5_0: std_logic;
- signal mdout1_4_0: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_31_1: std_logic;
- signal mdout1_30_1: std_logic;
- signal mdout1_29_1: std_logic;
- signal mdout1_28_1: std_logic;
- signal mdout1_27_1: std_logic;
- signal mdout1_26_1: std_logic;
- signal mdout1_25_1: std_logic;
- signal mdout1_24_1: std_logic;
- signal mdout1_23_1: std_logic;
- signal mdout1_22_1: std_logic;
- signal mdout1_21_1: std_logic;
- signal mdout1_20_1: std_logic;
- signal mdout1_19_1: std_logic;
- signal mdout1_18_1: std_logic;
- signal mdout1_17_1: std_logic;
- signal mdout1_16_1: std_logic;
- signal mdout1_15_1: std_logic;
- signal mdout1_14_1: std_logic;
- signal mdout1_13_1: std_logic;
- signal mdout1_12_1: std_logic;
- signal mdout1_11_1: std_logic;
- signal mdout1_10_1: std_logic;
- signal mdout1_9_1: std_logic;
- signal mdout1_8_1: std_logic;
- signal mdout1_7_1: std_logic;
- signal mdout1_6_1: std_logic;
- signal mdout1_5_1: std_logic;
- signal mdout1_4_1: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_31_2: std_logic;
- signal mdout1_30_2: std_logic;
- signal mdout1_29_2: std_logic;
- signal mdout1_28_2: std_logic;
- signal mdout1_27_2: std_logic;
- signal mdout1_26_2: std_logic;
- signal mdout1_25_2: std_logic;
- signal mdout1_24_2: std_logic;
- signal mdout1_23_2: std_logic;
- signal mdout1_22_2: std_logic;
- signal mdout1_21_2: std_logic;
- signal mdout1_20_2: std_logic;
- signal mdout1_19_2: std_logic;
- signal mdout1_18_2: std_logic;
- signal mdout1_17_2: std_logic;
- signal mdout1_16_2: std_logic;
- signal mdout1_15_2: std_logic;
- signal mdout1_14_2: std_logic;
- signal mdout1_13_2: std_logic;
- signal mdout1_12_2: std_logic;
- signal mdout1_11_2: std_logic;
- signal mdout1_10_2: std_logic;
- signal mdout1_9_2: std_logic;
- signal mdout1_8_2: std_logic;
- signal mdout1_7_2: std_logic;
- signal mdout1_6_2: std_logic;
- signal mdout1_5_2: std_logic;
- signal mdout1_4_2: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_31_3: std_logic;
- signal mdout1_30_3: std_logic;
- signal mdout1_29_3: std_logic;
- signal mdout1_28_3: std_logic;
- signal mdout1_27_3: std_logic;
- signal mdout1_26_3: std_logic;
- signal mdout1_25_3: std_logic;
- signal mdout1_24_3: std_logic;
- signal mdout1_23_3: std_logic;
- signal mdout1_22_3: std_logic;
- signal mdout1_21_3: std_logic;
- signal mdout1_20_3: std_logic;
- signal mdout1_19_3: std_logic;
- signal mdout1_18_3: std_logic;
- signal mdout1_17_3: std_logic;
- signal mdout1_16_3: std_logic;
- signal mdout1_15_3: std_logic;
- signal mdout1_14_3: std_logic;
- signal mdout1_13_3: std_logic;
- signal mdout1_12_3: std_logic;
- signal mdout1_11_3: std_logic;
- signal mdout1_10_3: std_logic;
- signal mdout1_9_3: std_logic;
- signal mdout1_8_3: std_logic;
- signal mdout1_7_3: std_logic;
- signal mdout1_6_3: std_logic;
- signal mdout1_5_3: std_logic;
- signal mdout1_4_3: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_31_4: std_logic;
- signal mdout1_30_4: std_logic;
- signal mdout1_29_4: std_logic;
- signal mdout1_28_4: std_logic;
- signal mdout1_27_4: std_logic;
- signal mdout1_26_4: std_logic;
- signal mdout1_25_4: std_logic;
- signal mdout1_24_4: std_logic;
- signal mdout1_23_4: std_logic;
- signal mdout1_22_4: std_logic;
- signal mdout1_21_4: std_logic;
- signal mdout1_20_4: std_logic;
- signal mdout1_19_4: std_logic;
- signal mdout1_18_4: std_logic;
- signal mdout1_17_4: std_logic;
- signal mdout1_16_4: std_logic;
- signal mdout1_15_4: std_logic;
- signal mdout1_14_4: std_logic;
- signal mdout1_13_4: std_logic;
- signal mdout1_12_4: std_logic;
- signal mdout1_11_4: std_logic;
- signal mdout1_10_4: std_logic;
- signal mdout1_9_4: std_logic;
- signal mdout1_8_4: std_logic;
- signal mdout1_7_4: std_logic;
- signal mdout1_6_4: std_logic;
- signal mdout1_5_4: std_logic;
- signal mdout1_4_4: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_31_5: std_logic;
- signal mdout1_30_5: std_logic;
- signal mdout1_29_5: std_logic;
- signal mdout1_28_5: std_logic;
- signal mdout1_27_5: std_logic;
- signal mdout1_26_5: std_logic;
- signal mdout1_25_5: std_logic;
- signal mdout1_24_5: std_logic;
- signal mdout1_23_5: std_logic;
- signal mdout1_22_5: std_logic;
- signal mdout1_21_5: std_logic;
- signal mdout1_20_5: std_logic;
- signal mdout1_19_5: std_logic;
- signal mdout1_18_5: std_logic;
- signal mdout1_17_5: std_logic;
- signal mdout1_16_5: std_logic;
- signal mdout1_15_5: std_logic;
- signal mdout1_14_5: std_logic;
- signal mdout1_13_5: std_logic;
- signal mdout1_12_5: std_logic;
- signal mdout1_11_5: std_logic;
- signal mdout1_10_5: std_logic;
- signal mdout1_9_5: std_logic;
- signal mdout1_8_5: std_logic;
- signal mdout1_7_5: std_logic;
- signal mdout1_6_5: std_logic;
- signal mdout1_5_5: std_logic;
- signal mdout1_4_5: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_31_6: std_logic;
- signal mdout1_30_6: std_logic;
- signal mdout1_29_6: std_logic;
- signal mdout1_28_6: std_logic;
- signal mdout1_27_6: std_logic;
- signal mdout1_26_6: std_logic;
- signal mdout1_25_6: std_logic;
- signal mdout1_24_6: std_logic;
- signal mdout1_23_6: std_logic;
- signal mdout1_22_6: std_logic;
- signal mdout1_21_6: std_logic;
- signal mdout1_20_6: std_logic;
- signal mdout1_19_6: std_logic;
- signal mdout1_18_6: std_logic;
- signal mdout1_17_6: std_logic;
- signal mdout1_16_6: std_logic;
- signal mdout1_15_6: std_logic;
- signal mdout1_14_6: std_logic;
- signal mdout1_13_6: std_logic;
- signal mdout1_12_6: std_logic;
- signal mdout1_11_6: std_logic;
- signal mdout1_10_6: std_logic;
- signal mdout1_9_6: std_logic;
- signal mdout1_8_6: std_logic;
- signal mdout1_7_6: std_logic;
- signal mdout1_6_6: std_logic;
- signal mdout1_5_6: std_logic;
- signal mdout1_4_6: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_31_7: std_logic;
- signal mdout1_30_7: std_logic;
- signal mdout1_29_7: std_logic;
- signal mdout1_28_7: std_logic;
- signal mdout1_27_7: std_logic;
- signal mdout1_26_7: std_logic;
- signal mdout1_25_7: std_logic;
- signal mdout1_24_7: std_logic;
- signal mdout1_23_7: std_logic;
- signal mdout1_22_7: std_logic;
- signal mdout1_21_7: std_logic;
- signal mdout1_20_7: std_logic;
- signal mdout1_19_7: std_logic;
- signal mdout1_18_7: std_logic;
- signal mdout1_17_7: std_logic;
- signal mdout1_16_7: std_logic;
- signal mdout1_15_7: std_logic;
- signal mdout1_14_7: std_logic;
- signal mdout1_13_7: std_logic;
- signal mdout1_12_7: std_logic;
- signal mdout1_11_7: std_logic;
- signal mdout1_10_7: std_logic;
- signal mdout1_9_7: std_logic;
- signal mdout1_8_7: std_logic;
- signal mdout1_7_7: std_logic;
- signal mdout1_6_7: std_logic;
- signal mdout1_5_7: std_logic;
- signal mdout1_4_7: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal rptr_13_ff: std_logic;
- signal rptr_12_ff: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_31_8: std_logic;
- signal mdout1_30_8: std_logic;
- signal mdout1_29_8: std_logic;
- signal mdout1_28_8: std_logic;
- signal mdout1_27_8: std_logic;
- signal mdout1_26_8: std_logic;
- signal mdout1_25_8: std_logic;
- signal mdout1_24_8: std_logic;
- signal mdout1_23_8: std_logic;
- signal mdout1_22_8: std_logic;
- signal mdout1_21_8: std_logic;
- signal mdout1_20_8: std_logic;
- signal mdout1_19_8: std_logic;
- signal mdout1_18_8: std_logic;
- signal mdout1_17_8: std_logic;
- signal mdout1_16_8: std_logic;
- signal mdout1_15_8: std_logic;
- signal mdout1_14_8: std_logic;
- signal mdout1_13_8: std_logic;
- signal mdout1_12_8: std_logic;
- signal mdout1_11_8: std_logic;
- signal mdout1_10_8: std_logic;
- signal mdout1_9_8: std_logic;
- signal mdout1_8_8: std_logic;
- signal mdout1_7_8: std_logic;
- signal mdout1_6_8: std_logic;
- signal mdout1_5_8: std_logic;
- signal mdout1_4_8: std_logic;
- signal mdout1_3_8: std_logic;
- signal mdout1_2_8: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal wcount_r12: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal wcount_r14: std_logic;
- signal wcount_r15: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal rcount_w12: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal rcount_w14: std_logic;
- signal rcount_w15: std_logic;
- signal wcount_14: std_logic;
- signal wcount_15: std_logic;
- signal co7_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX321
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; D8: in std_logic;
- D9: in std_logic; D10: in std_logic; D11: in std_logic;
- D12: in std_logic; D13: in std_logic; D14: in std_logic;
- D15: in std_logic; D16: in std_logic; D17: in std_logic;
- D18: in std_logic; D19: in std_logic; D20: in std_logic;
- D21: in std_logic; D22: in std_logic; D23: in std_logic;
- D24: in std_logic; D25: in std_logic; D26: in std_logic;
- D27: in std_logic; D28: in std_logic; D29: in std_logic;
- D30: in std_logic; D31: in std_logic; SD1: in std_logic;
- SD2: in std_logic; SD3: in std_logic; SD4: in std_logic;
- SD5: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is "";
- attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is "";
- attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is "";
- attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is "";
- attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is "";
- attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is "";
- attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is "";
- attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is "";
- attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is "";
- attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is "";
- attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is "";
- attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is "";
- attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is "";
- attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is "";
- attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is "";
- attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is "";
- attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is "";
- attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is "";
- attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is "";
- attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is "";
- attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is "";
- attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is "";
- attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is "";
- attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is "";
- attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is "";
- attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is "";
- attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is "";
- attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is "";
- attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is "";
- attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is "";
- attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is "";
- attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t34: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_11: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t33: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_10: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t32: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t31: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t30: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t29: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t28: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t27: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t26: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t25: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t24: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t23: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t22: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t21: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t20: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t19: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t18: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t17: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t16: XOR2
- port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15);
-
- XOR2_t15: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t14: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t13: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t12: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t11: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t10: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t9: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t8: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t7: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t6: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t5: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t4: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t3: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t2: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t1: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t0: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- INV_9: INV
- port map (A=>wptr_11, Z=>wptr_11_inv);
-
- INV_8: INV
- port map (A=>wptr_12, Z=>wptr_12_inv);
-
- INV_7: INV
- port map (A=>wptr_13, Z=>wptr_13_inv);
-
- INV_6: INV
- port map (A=>wptr_14, Z=>wptr_14_inv);
-
- INV_5: INV
- port map (A=>wptr_15, Z=>wptr_15_inv);
-
- LUT4_187: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet);
-
- LUT4_186: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_p00);
-
- INV_4: INV
- port map (A=>rptr_11, Z=>rptr_11_inv);
-
- INV_3: INV
- port map (A=>rptr_12, Z=>rptr_12_inv);
-
- INV_2: INV
- port map (A=>rptr_13, Z=>rptr_13_inv);
-
- INV_1: INV
- port map (A=>rptr_14, Z=>rptr_14_inv);
-
- INV_0: INV
- port map (A=>rptr_15, Z=>rptr_15_inv);
-
- LUT4_185: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_1);
-
- LUT4_184: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec1_r10);
-
- LUT4_183: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_2);
-
- LUT4_182: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec2_p01);
-
- LUT4_181: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_3);
-
- LUT4_180: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec3_r11);
-
- LUT4_179: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_4);
-
- LUT4_178: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec4_p02);
-
- LUT4_177: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_5);
-
- LUT4_176: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec5_r12);
-
- LUT4_175: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_6);
-
- LUT4_174: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec6_p03);
-
- LUT4_173: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_7);
-
- LUT4_172: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec7_r13);
-
- LUT4_171: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_8);
-
- LUT4_170: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec8_p04);
-
- LUT4_169: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_9);
-
- LUT4_168: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec9_r14);
-
- LUT4_167: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_10);
-
- LUT4_166: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05);
-
- LUT4_165: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_11);
-
- LUT4_164: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15);
-
- LUT4_163: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_12);
-
- LUT4_162: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06);
-
- LUT4_161: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_13);
-
- LUT4_160: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16);
-
- LUT4_159: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_14);
-
- LUT4_158: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07);
-
- LUT4_157: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_15);
-
- LUT4_156: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17);
-
- LUT4_155: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_16);
-
- LUT4_154: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08);
-
- LUT4_153: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_17);
-
- LUT4_152: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18);
-
- LUT4_151: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_18);
-
- LUT4_150: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09);
-
- LUT4_149: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_19);
-
- LUT4_148: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19);
-
- LUT4_147: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_20);
-
- LUT4_146: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010);
-
- LUT4_145: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_21);
-
- LUT4_144: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110);
-
- LUT4_143: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_22);
-
- LUT4_142: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011);
-
- LUT4_141: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_23);
-
- LUT4_140: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111);
-
- LUT4_139: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_24);
-
- LUT4_138: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012);
-
- LUT4_137: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_25);
-
- LUT4_136: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112);
-
- LUT4_135: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_26);
-
- LUT4_134: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013);
-
- LUT4_133: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_27);
-
- LUT4_132: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113);
-
- LUT4_131: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_28);
-
- LUT4_130: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014);
-
- LUT4_129: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_29);
-
- LUT4_128: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114);
-
- LUT4_127: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
- DO0=>func_and_inet_30);
-
- LUT4_126: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015);
-
- LUT4_125: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_31);
-
- LUT4_124: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115);
-
- LUT4_123: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_32);
-
- LUT4_122: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec32_p016);
-
- LUT4_121: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_33);
-
- LUT4_120: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec33_r116);
-
- LUT4_119: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_34);
-
- LUT4_118: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec34_p017);
-
- LUT4_117: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_35);
-
- LUT4_116: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec35_r117);
-
- LUT4_115: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_36);
-
- LUT4_114: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec36_p018);
-
- LUT4_113: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_37);
-
- LUT4_112: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec37_r118);
-
- LUT4_111: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_38);
-
- LUT4_110: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec38_p019);
-
- LUT4_109: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_39);
-
- LUT4_108: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec39_r119);
-
- LUT4_107: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_40);
-
- LUT4_106: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec40_p020);
-
- LUT4_105: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_41);
-
- LUT4_104: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec41_r120);
-
- LUT4_103: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_42);
-
- LUT4_102: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec42_p021);
-
- LUT4_101: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_43);
-
- LUT4_100: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec43_r121);
-
- LUT4_99: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_44);
-
- LUT4_98: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec44_p022);
-
- LUT4_97: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_45);
-
- LUT4_96: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec45_r122);
-
- LUT4_95: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_46);
-
- LUT4_94: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec46_p023);
-
- LUT4_93: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_47);
-
- LUT4_92: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec47_r123);
-
- LUT4_91: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_48);
-
- LUT4_90: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec48_p024);
-
- LUT4_89: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_49);
-
- LUT4_88: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec49_r124);
-
- LUT4_87: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_50);
-
- LUT4_86: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec50_p025);
-
- LUT4_85: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_51);
-
- LUT4_84: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec51_r125);
-
- LUT4_83: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_52);
-
- LUT4_82: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec52_p026);
-
- LUT4_81: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_53);
-
- LUT4_80: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec53_r126);
-
- LUT4_79: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_54);
-
- LUT4_78: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec54_p027);
-
- LUT4_77: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_55);
-
- LUT4_76: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec55_r127);
-
- LUT4_75: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_56);
-
- LUT4_74: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec56_p028);
-
- LUT4_73: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_57);
-
- LUT4_72: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec57_r128);
-
- LUT4_71: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_58);
-
- LUT4_70: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec58_p029);
-
- LUT4_69: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_59);
-
- LUT4_68: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec59_r129);
-
- LUT4_67: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_60);
-
- LUT4_66: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec60_p030);
-
- LUT4_65: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_61);
-
- LUT4_64: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec61_r130);
-
- LUT4_63: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
- DO0=>func_and_inet_62);
-
- LUT4_62: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec62_p031);
-
- LUT4_61: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_63);
-
- LUT4_60: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec63_r131);
-
- LUT4_59: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>w_gcount_r216,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_58: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_57: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_56: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_55: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r15);
-
- LUT4_54: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215,
- AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_53: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0,
- DO0=>wcount_r10);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r3);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r2);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r1);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_10);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7,
- AD1=>func_xor_inet_8, AD0=>func_xor_inet_9,
- DO0=>func_xor_inet_11);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_31: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_30: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_29: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
- DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
- DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
- DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_28: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1,
- DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4,
- DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7,
- DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_4_0_27: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1,
- DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4,
- DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7,
- DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_5_0_26: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1,
- DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4,
- DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7,
- DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_6_0_25: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1,
- DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4,
- DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7,
- DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_7_0_24: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1,
- DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4,
- DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7,
- DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_8_0_23: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1,
- DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4,
- DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7,
- DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_9_0_22: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1,
- DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4,
- DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7,
- DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_10_0_21: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0,
- DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3,
- DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6,
- DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_11_0_20: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0,
- DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3,
- DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6,
- DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_12_0_19: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0,
- DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3,
- DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6,
- DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_13_0_18: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0,
- DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3,
- DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6,
- DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_14_0_17: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0,
- DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3,
- DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6,
- DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_15_0_16: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0,
- DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3,
- DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6,
- DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_16_0_15: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec32_p016, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec33_r116, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0,
- DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3,
- DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6,
- DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_17_0_14: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec34_p017, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec35_r117, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0,
- DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3,
- DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6,
- DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_18_0_13: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec36_p018, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec37_r118, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0,
- DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3,
- DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6,
- DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_19_0_12: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec38_p019, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec39_r119, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0,
- DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3,
- DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6,
- DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_20_0_11: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec40_p020, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec41_r120, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0,
- DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3,
- DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6,
- DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_21_0_10: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec42_p021, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec43_r121, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0,
- DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3,
- DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6,
- DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_22_0_9: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec44_p022, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec45_r122, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0,
- DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3,
- DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6,
- DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_23_0_8: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec46_p023, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec47_r123, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0,
- DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3,
- DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6,
- DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_24_0_7: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec48_p024, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec49_r124, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0,
- DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3,
- DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6,
- DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_25_0_6: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec50_p025, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec51_r125, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0,
- DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3,
- DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6,
- DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_26_0_5: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec52_p026, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec53_r126, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0,
- DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3,
- DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6,
- DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_27_0_4: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec54_p027, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec55_r127, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0,
- DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3,
- DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6,
- DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_28_0_3: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec56_p028, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec57_r128, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0,
- DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3,
- DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6,
- DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_29_0_2: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec58_p029, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec59_r129, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0,
- DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3,
- DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6,
- DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_30_0_1: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec60_p030, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec61_r130, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0,
- DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3,
- DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6,
- DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_31_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec62_p031, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec63_r131, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0,
- DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3,
- DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6,
- DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_176: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_175: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_174: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_173: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_172: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_171: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_170: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_169: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_168: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_167: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_166: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_165: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_164: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_163: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_162: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_161: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_160: FD1P3DX
- port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_16);
-
- FF_159: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_158: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_157: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_156: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_155: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_154: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_153: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_152: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_151: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_150: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_149: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_148: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_147: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_146: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_145: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_144: FD1P3DX
- port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_143: FD1P3DX
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_16);
-
- FF_142: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_141: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_140: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_139: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_138: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_137: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_136: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_135: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_134: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_133: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_132: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_131: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_130: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_129: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_128: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_127: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_126: FD1P3DX
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_16);
-
- FF_125: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_124: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_123: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_122: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_121: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_120: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_119: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_118: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_117: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_116: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_115: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_114: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_113: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_112: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_111: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_110: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_109: FD1P3DX
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_108: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_107: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_106: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_105: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_104: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_103: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_102: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_101: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_100: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_99: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_98: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_97: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_96: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_95: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_94: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_93: FD1P3DX
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_92: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_91: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_90: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_89: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_88: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_87: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_86: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_85: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_84: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_83: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_82: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_81: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_80: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_79: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_78: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_77: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_76: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_75: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_74: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_73: FD1P3DX
- port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_12_ff);
-
- FF_72: FD1P3DX
- port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_13_ff);
-
- FF_71: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_70: FD1P3DX
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_69: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_68: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_67: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_66: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_65: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_64: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_63: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_62: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_61: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_60: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_59: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_58: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_57: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_56: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_55: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_54: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r16);
-
- FF_52: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_51: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_50: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_49: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_48: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_47: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_46: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_45: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_44: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_43: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_42: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_41: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_31: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_30: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_29: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_28: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r216);
-
- FF_18: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_17: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_16: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_15: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- w_gctr_8: CU2
- port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>iwcount_16, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1,
- NC0=>ircount_16, NC1=>open);
-
- mux_8: MUX321
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
- D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
- D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
- D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0,
- D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0,
- D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0,
- D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0,
- D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0,
- D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(0));
-
- mux_7: MUX321
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
- D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
- D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
- D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1,
- D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1,
- D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1,
- D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1,
- D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1,
- D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(1));
-
- mux_6: MUX321
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
- D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
- D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
- D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2,
- D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2,
- D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2,
- D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2,
- D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2,
- D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(2));
-
- mux_5: MUX321
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
- D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
- D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
- D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3,
- D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3,
- D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3,
- D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3,
- D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3,
- D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(3));
-
- mux_4: MUX321
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
- D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
- D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
- D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4,
- D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4,
- D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4,
- D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4,
- D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4,
- D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(4));
-
- mux_3: MUX321
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
- D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
- D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
- D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5,
- D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5,
- D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5,
- D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5,
- D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5,
- D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(5));
-
- mux_2: MUX321
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
- D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
- D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
- D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6,
- D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6,
- D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6,
- D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6,
- D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6,
- D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(6));
-
- mux_1: MUX321
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
- D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
- D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
- D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7,
- D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7,
- D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7,
- D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7,
- D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7,
- D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(7));
-
- mux_0: MUX321
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
- D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
- D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
- D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8,
- D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8,
- D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8,
- D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8,
- D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8,
- D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(8));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12,
- B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14,
- B1=>wcount_r15, CI=>co6_2, GE=>co7_2);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14,
- B1=>rcount_w15, CI=>co6_3, GE=>co7_3);
-
- full_cmp_8: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_64kx9 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX321 use entity ecp3.MUX321(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:21 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_64kx9
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_64kx9.vhd
- VHDL template : fifo_64kx9_tmpl.vhd
- VHDL testbench : tb_fifo_64kx9_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_64kx9.srp
- Estimated Resource Usage:
- LUT : 379
- EBR : 32
- Reg : 177
-
-END SCUBA Module Synthesis
-
-File: fifo_64kx9.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:23:21 2011
-
--- parameterized module component declaration
-component fifo_64kx9
- port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_64kx9
- port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-MODULE ip_mem DEFIN ip_mem.vhd
- SUBMODULE DP16KB
- INSTANCE ip_mem_0_1_0
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE DP16KB
- INSTANCE ip_mem_0_0_1
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP_TRUE
-CoreRevision=7.1
-ModuleName=ip_mem
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:24:37
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-AAddress=256
-BAddress=256
-AData=32
-BData=32
-enByte=0
-ByteSize=9
-AadPipeline=0
-BadPipeline=0
-AinPipeline=0
-BinPipeline=0
-AoutPipeline=0
-BoutPipeline=1
-AMOR=0
-BMOR=0
-AInData=Registered
-BInData=Registered
-AAdControl=Registered
-BAdControl=Registered
-MemFile=ip_mem.mem
-MemFormat=orca
-Reset=Sync
-GSR=Enabled
-WriteA=Normal
-WriteB=Normal
-Pad=0
-EnECC=0
-Optimization=Speed
-Pipeline=0
-
-[FilesGenerated]
-ip_mem.mem=mem
+++ /dev/null
-#Format=Address-Hex\r
-#Depth=256\r
-#DataWidth=32\r
-#AddrRadix=3\r
-#DataRadix=3\r
-\r
-00: 214397e9\r
-01: 0000001b\r
-02: c0a80002\r
-03: 0000c350\r
-04: 023bdc00\r
-05: 00000013\r
-06: c0a80005\r
-07: 0000c350\r
-08: 00000578\r
-09: 00000000\r
-0a: 00000000\r
-0b: 00000000\r
-0c: 00000000\r
-0d: 00000000\r
-0e: 00000000\r
-0f: 00000000\r
-\r
-10: 214397e9\r
-11: 0000001b\r
-12: c0a80002\r
-13: 0000c351\r
-14: 023bdc01\r
-15: 00000013\r
-16: c0a80006\r
-17: 0000c350\r
-18: 00000578\r
-19: 00000000\r
-1a: 00000000\r
-1b: 00000000\r
-1c: 00000000\r
-1d: 00000000\r
-1e: 00000000\r
-1f: 00000000\r
-\r
-20: 214397e9\r
-21: 0000001b\r
-22: c0a80002\r
-23: 0000c352\r
-24: 023bdc02\r
-25: 00000013\r
-26: c0a80007\r
-27: 0000c350\r
-28: 00000578\r
-29: 00000000\r
-2a: 00000000\r
-2b: 00000000\r
-2c: 00000000\r
-2d: 00000000\r
-2e: 00000000\r
-2f: 00000000\r
-\r
-30: 214397e9\r
-31: 0000001b\r
-32: c0a80002\r
-33: 0000c353\r
-34: 023bdc03\r
-35: 00000013\r
-36: c0a80008\r
-37: 0000c350\r
-38: 00000578\r
-39: 00000000\r
-3a: 00000000\r
-3b: 00000000\r
-3c: 00000000\r
-3d: 00000000\r
-3e: 00000000\r
-3f: 00000000\r
-\r
-40: 00000000\r
-41: 00000000\r
-42: 00000000\r
-43: 00000000\r
-44: 00000000\r
-45: 00000000\r
-46: 00000000\r
-47: 00000000\r
-48: 00000578\r
-49: 00000000\r
-4a: 00000000\r
-4b: 00000000\r
-4c: 00000000\r
-4d: 00000000\r
-4e: 00000000\r
-4f: 00000000\r
-\r
-50: 00000000\r
-51: 00000000\r
-52: 00000000\r
-53: 00000000\r
-54: 00000000\r
-55: 00000000\r
-56: 00000000\r
-57: 00000000\r
-58: 00000578\r
-59: 00000000\r
-5a: 00000000\r
-5b: 00000000\r
-5c: 00000000\r
-5d: 00000000\r
-5e: 00000000\r
-5f: 00000000\r
-\r
-60: 00000000\r
-61: 00000000\r
-62: 00000000\r
-63: 00000000\r
-64: 00000000\r
-65: 00000000\r
-66: 00000000\r
-67: 00000000\r
-68: 00000578\r
-69: 00000000\r
-6a: 00000000\r
-6b: 00000000\r
-6c: 00000000\r
-6d: 00000000\r
-6e: 00000000\r
-6f: 00000000\r
-\r
-70: 00000000\r
-71: 00000000\r
-72: 00000000\r
-73: 00000000\r
-74: 00000000\r
-75: 00000000\r
-76: 00000000\r
-77: 00000000\r
-78: 00000578\r
-79: 00000000\r
-7a: 00000000\r
-7b: 00000000\r
-7c: 00000000\r
-7d: 00000000\r
-7e: 00000000\r
-7f: 00000000\r
-\r
-80: 00000000\r
-81: 00000000\r
-82: 00000000\r
-83: 00000000\r
-84: 00000000\r
-85: 00000000\r
-86: 00000000\r
-87: 00000000\r
-88: 00000578\r
-89: 00000000\r
-8a: 00000000\r
-8b: 00000000\r
-8c: 00000000\r
-8d: 00000000\r
-8e: 00000000\r
-8f: 00000000\r
-\r
-90: 00000000\r
-91: 00000000\r
-92: 00000000\r
-93: 00000000\r
-94: 00000000\r
-95: 00000000\r
-96: 00000000\r
-97: 00000000\r
-98: 00000578\r
-99: 00000000\r
-9a: 00000000\r
-9b: 00000000\r
-9c: 00000000\r
-9d: 00000000\r
-9e: 00000000\r
-9f: 00000000\r
-\r
-a0: 00000000\r
-a1: 00000000\r
-a2: 00000000\r
-a3: 00000000\r
-a4: 00000000\r
-a5: 00000000\r
-a6: 00000000\r
-a7: 00000000\r
-a8: 00000578\r
-a9: 00000000\r
-aa: 00000000\r
-ab: 00000000\r
-ac: 00000000\r
-ad: 00000000\r
-ae: 00000000\r
-af: 00000000\r
-\r
-b0: 00000000\r
-b1: 00000000\r
-b2: 00000000\r
-b3: 00000000\r
-b4: 00000000\r
-b5: 00000000\r
-b6: 00000000\r
-b7: 00000000\r
-b8: 00000578\r
-b9: 00000000\r
-ba: 00000000\r
-bb: 00000000\r
-bc: 00000000\r
-bd: 00000000\r
-be: 00000000\r
-bf: 00000000\r
-\r
-c0: 00000000\r
-c1: 00000000\r
-c2: 00000000\r
-c3: 00000000\r
-c4: 00000000\r
-c5: 00000000\r
-c6: 00000000\r
-c7: 00000000\r
-c8: 00000578\r
-c9: 00000000\r
-ca: 00000000\r
-cb: 00000000\r
-cc: 00000000\r
-cd: 00000000\r
-ce: 00000000\r
-cf: 00000000\r
-\r
-d0: 00000000\r
-d1: 00000000\r
-d2: 00000000\r
-d3: 00000000\r
-d4: 00000000\r
-d5: 00000000\r
-d6: 00000000\r
-d7: 00000000\r
-d8: 00000578\r
-d9: 00000000\r
-da: 00000000\r
-db: 00000000\r
-dc: 00000000\r
-dd: 00000000\r
-de: 00000000\r
-df: 00000000\r
-\r
-e0: 00000000\r
-e1: 00000000\r
-e2: 00000000\r
-e3: 00000000\r
-e4: 00000000\r
-e5: 00000000\r
-e6: 00000000\r
-e7: 00000000\r
-e8: 00000578\r
-e9: 00000000\r
-ea: 00000000\r
-eb: 00000000\r
-ec: 00000000\r
-ed: 00000000\r
-ee: 00000000\r
-ef: 00000000\r
-\r
-f0: 00000000\r
-f1: 00000000\r
-f2: 00000000\r
-f3: 00000000\r
-f4: 00000000\r
-f5: 00000000\r
-f6: 00000000\r
-f7: 00000000\r
-f8: 00000578\r
-f9: 00000000\r
-fa: 00000000\r
-fb: 00000000\r
-fc: 00000000\r
-fd: 00000000\r
-fe: 00000000\r
-ff: 00000000\r
+++ /dev/null
-#Format=Address-Hex\r
-#Depth=256\r
-#DataWidth=32\r
-#AddrRadix=3\r
-#DataRadix=3\r
-\r
-00: 00006cf0\r
-01: 4902d745\r
-02: c0a80002\r
-03: 0000c350\r
-04: 0000eeee\r
-05: eeeeeeee\r
-06: c0a80005\r
-07: 0000c350\r
-08: 00000578\r
-09: 00000000\r
-0a: 00000000\r
-0b: 00000000\r
-0c: 00000000\r
-0d: 00000000\r
-0e: 00000000\r
-0f: 00000000\r
-\r
-10: 00000000\r
-11: 00000000\r
-12: 00000000\r
-13: 00000000\r
-14: 00000000\r
-15: 00000000\r
-16: 00000000\r
-17: 00000000\r
-18: 00000578\r
-19: 00000000\r
-1a: 00000000\r
-1b: 00000000\r
-1c: 00000000\r
-1d: 00000000\r
-1e: 00000000\r
-1f: 00000000\r
-\r
-20: 00000000\r
-21: 00000000\r
-22: 00000000\r
-23: 00000000\r
-24: 00000000\r
-25: 00000000\r
-26: 00000000\r
-27: 00000000\r
-28: 00000578\r
-29: 00000000\r
-2a: 00000000\r
-2b: 00000000\r
-2c: 00000000\r
-2d: 00000000\r
-2e: 00000000\r
-2f: 00000000\r
-\r
-30: 00000000\r
-31: 00000000\r
-32: 00000000\r
-33: 00000000\r
-34: 00000000\r
-35: 00000000\r
-36: 00000000\r
-37: 00000000\r
-38: 00000578\r
-39: 00000000\r
-3a: 00000000\r
-3b: 00000000\r
-3c: 00000000\r
-3d: 00000000\r
-3e: 00000000\r
-3f: 00000000\r
-\r
-40: 00000000\r
-41: 00000000\r
-42: 00000000\r
-43: 00000000\r
-44: 00000000\r
-45: 00000000\r
-46: 00000000\r
-47: 00000000\r
-48: 00000578\r
-49: 00000000\r
-4a: 00000000\r
-4b: 00000000\r
-4c: 00000000\r
-4d: 00000000\r
-4e: 00000000\r
-4f: 00000000\r
-\r
-50: 00000000\r
-51: 00000000\r
-52: 00000000\r
-53: 00000000\r
-54: 00000000\r
-55: 00000000\r
-56: 00000000\r
-57: 00000000\r
-58: 00000578\r
-59: 00000000\r
-5a: 00000000\r
-5b: 00000000\r
-5c: 00000000\r
-5d: 00000000\r
-5e: 00000000\r
-5f: 00000000\r
-\r
-60: 00000000\r
-61: 00000000\r
-62: 00000000\r
-63: 00000000\r
-64: 00000000\r
-65: 00000000\r
-66: 00000000\r
-67: 00000000\r
-68: 00000578\r
-69: 00000000\r
-6a: 00000000\r
-6b: 00000000\r
-6c: 00000000\r
-6d: 00000000\r
-6e: 00000000\r
-6f: 00000000\r
-\r
-70: 00000000\r
-71: 00000000\r
-72: 00000000\r
-73: 00000000\r
-74: 00000000\r
-75: 00000000\r
-76: 00000000\r
-77: 00000000\r
-78: 00000578\r
-79: 00000000\r
-7a: 00000000\r
-7b: 00000000\r
-7c: 00000000\r
-7d: 00000000\r
-7e: 00000000\r
-7f: 00000000\r
-\r
-80: 00000000\r
-81: 00000000\r
-82: 00000000\r
-83: 00000000\r
-84: 00000000\r
-85: 00000000\r
-86: 00000000\r
-87: 00000000\r
-88: 00000578\r
-89: 00000000\r
-8a: 00000000\r
-8b: 00000000\r
-8c: 00000000\r
-8d: 00000000\r
-8e: 00000000\r
-8f: 00000000\r
-\r
-90: 00000000\r
-91: 00000000\r
-92: 00000000\r
-93: 00000000\r
-94: 00000000\r
-95: 00000000\r
-96: 00000000\r
-97: 00000000\r
-98: 00000578\r
-99: 00000000\r
-9a: 00000000\r
-9b: 00000000\r
-9c: 00000000\r
-9d: 00000000\r
-9e: 00000000\r
-9f: 00000000\r
-\r
-a0: 00000000\r
-a1: 00000000\r
-a2: 00000000\r
-a3: 00000000\r
-a4: 00000000\r
-a5: 00000000\r
-a6: 00000000\r
-a7: 00000000\r
-a8: 00000578\r
-a9: 00000000\r
-aa: 00000000\r
-ab: 00000000\r
-ac: 00000000\r
-ad: 00000000\r
-ae: 00000000\r
-af: 00000000\r
-\r
-b0: 00000000\r
-b1: 00000000\r
-b2: 00000000\r
-b3: 00000000\r
-b4: 00000000\r
-b5: 00000000\r
-b6: 00000000\r
-b7: 00000000\r
-b8: 00000578\r
-b9: 00000000\r
-ba: 00000000\r
-bb: 00000000\r
-bc: 00000000\r
-bd: 00000000\r
-be: 00000000\r
-bf: 00000000\r
-\r
-c0: 00000000\r
-c1: 00000000\r
-c2: 00000000\r
-c3: 00000000\r
-c4: 00000000\r
-c5: 00000000\r
-c6: 00000000\r
-c7: 00000000\r
-c8: 00000578\r
-c9: 00000000\r
-ca: 00000000\r
-cb: 00000000\r
-cc: 00000000\r
-cd: 00000000\r
-ce: 00000000\r
-cf: 00000000\r
-\r
-d0: 00000000\r
-d1: 00000000\r
-d2: 00000000\r
-d3: 00000000\r
-d4: 00000000\r
-d5: 00000000\r
-d6: 00000000\r
-d7: 00000000\r
-d8: 00000578\r
-d9: 00000000\r
-da: 00000000\r
-db: 00000000\r
-dc: 00000000\r
-dd: 00000000\r
-de: 00000000\r
-df: 00000000\r
-\r
-e0: 00000000\r
-e1: 00000000\r
-e2: 00000000\r
-e3: 00000000\r
-e4: 00000000\r
-e5: 00000000\r
-e6: 00000000\r
-e7: 00000000\r
-e8: 00000578\r
-e9: 00000000\r
-ea: 00000000\r
-eb: 00000000\r
-ec: 00000000\r
-ed: 00000000\r
-ee: 00000000\r
-ef: 00000000\r
-\r
-f0: 00000000\r
-f1: 00000000\r
-f2: 00000000\r
-f3: 00000000\r
-f4: 00000000\r
-f5: 00000000\r
-f6: 00000000\r
-f7: 00000000\r
-f8: 00000578\r
-f9: 00000000\r
-fa: 00000000\r
-fb: 00000000\r
-fc: 00000000\r
-fd: 00000000\r
-fe: 00000000\r
-ff: 00000000\r
+++ /dev/null
-DataInA[31] i
-DataInA[30] i
-DataInA[29] i
-DataInA[28] i
-DataInA[27] i
-DataInA[26] i
-DataInA[25] i
-DataInA[24] i
-DataInA[23] i
-DataInA[22] i
-DataInA[21] i
-DataInA[20] i
-DataInA[19] i
-DataInA[18] i
-DataInA[17] i
-DataInA[16] i
-DataInA[15] i
-DataInA[14] i
-DataInA[13] i
-DataInA[12] i
-DataInA[11] i
-DataInA[10] i
-DataInA[9] i
-DataInA[8] i
-DataInA[7] i
-DataInA[6] i
-DataInA[5] i
-DataInA[4] i
-DataInA[3] i
-DataInA[2] i
-DataInA[1] i
-DataInA[0] i
-DataInB[31] i
-DataInB[30] i
-DataInB[29] i
-DataInB[28] i
-DataInB[27] i
-DataInB[26] i
-DataInB[25] i
-DataInB[24] i
-DataInB[23] i
-DataInB[22] i
-DataInB[21] i
-DataInB[20] i
-DataInB[19] i
-DataInB[18] i
-DataInB[17] i
-DataInB[16] i
-DataInB[15] i
-DataInB[14] i
-DataInB[13] i
-DataInB[12] i
-DataInB[11] i
-DataInB[10] i
-DataInB[9] i
-DataInB[8] i
-DataInB[7] i
-DataInB[6] i
-DataInB[5] i
-DataInB[4] i
-DataInB[3] i
-DataInB[2] i
-DataInB[1] i
-DataInB[0] i
-AddressA[7] i
-AddressA[6] i
-AddressA[5] i
-AddressA[4] i
-AddressA[3] i
-AddressA[2] i
-AddressA[1] i
-AddressA[0] i
-AddressB[7] i
-AddressB[6] i
-AddressB[5] i
-AddressB[4] i
-AddressB[3] i
-AddressB[2] i
-AddressB[1] i
-AddressB[0] i
-ClockA i
-ClockB i
-ClockEnA i
-ClockEnB i
-WrA i
-WrB i
-ResetA i
-ResetB i
-QA[31] o
-QA[30] o
-QA[29] o
-QA[28] o
-QA[27] o
-QA[26] o
-QA[25] o
-QA[24] o
-QA[23] o
-QA[22] o
-QA[21] o
-QA[20] o
-QA[19] o
-QA[18] o
-QA[17] o
-QA[16] o
-QA[15] o
-QA[14] o
-QA[13] o
-QA[12] o
-QA[11] o
-QA[10] o
-QA[9] o
-QA[8] o
-QA[7] o
-QA[6] o
-QA[5] o
-QA[4] o
-QA[3] o
-QA[2] o
-QA[1] o
-QA[0] o
-QB[31] o
-QB[30] o
-QB[29] o
-QB[28] o
-QB[27] o
-QB[26] o
-QB[25] o
-QB[24] o
-QB[23] o
-QB[22] o
-QB[21] o
-QB[20] o
-QB[19] o
-QB[18] o
-QB[17] o
-QB[16] o
-QB[15] o
-QB[14] o
-QB[13] o
-QB[12] o
-QB[11] o
-QB[10] o
-QB[9] o
-QB[8] o
-QB[7] o
-QB[6] o
-QB[5] o
-QB[4] o
-QB[3] o
-QB[2] o
-QB[1] o
-QB[0] o
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Mon Mar 29 21:52:49 2010
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem -memformat orca -cascade -1 -e
- Circuit name : ip_mem
- Module type : RAM_DP_TRUE
- Module Version : 7.1
- Ports :
- Inputs : DataInA[31:0], DataInB[31:0], AddressA[7:0], AddressB[7:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
- Outputs : QA[31:0], QB[31:0]
- I/O buffer : not inserted
- Memory file : /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem
- EDIF output : suppressed
- VHDL output : ip_mem.vhd
- VHDL template : ip_mem_tmpl.vhd
- VHDL testbench : tb_ip_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : ip_mem.srp
- Element Usage :
- DP16KB : 2
- Estimated Resource Usage:
- EBR : 2
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 7.1
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e
-
--- Thu Sep 22 11:24:37 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity ip_mem is
- port (
- DataInA: in std_logic_vector(31 downto 0);
- DataInB: in std_logic_vector(31 downto 0);
- AddressA: in std_logic_vector(7 downto 0);
- AddressB: in std_logic_vector(7 downto 0);
- ClockA: in std_logic;
- ClockB: in std_logic;
- ClockEnA: in std_logic;
- ClockEnB: in std_logic;
- WrA: in std_logic;
- WrB: in std_logic;
- ResetA: in std_logic;
- ResetB: in std_logic;
- QA: out std_logic_vector(31 downto 0);
- QB: out std_logic_vector(31 downto 0));
-end ip_mem;
-
-architecture Structure of ip_mem is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KC
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc";
- attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem";
- attribute RESETMODE of ip_mem_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc";
- attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem";
- attribute RESETMODE of ip_mem_0_1_0 : label is "SYNC";
-
-begin
- -- component instantiation statements
- ip_mem_0_0_1: DP16KC
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9",
- INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9",
- INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9",
- INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9",
- CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG",
- REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
- port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
- DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
- DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
- DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
- DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
- DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
- ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
- ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
- ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
- ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA,
- CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA,
- DIB0=>DataInB(0), DIB1=>DataInB(1), DIB2=>DataInB(2),
- DIB3=>DataInB(3), DIB4=>DataInB(4), DIB5=>DataInB(5),
- DIB6=>DataInB(6), DIB7=>DataInB(7), DIB8=>DataInB(8),
- DIB9=>DataInB(9), DIB10=>DataInB(10), DIB11=>DataInB(11),
- DIB12=>DataInB(12), DIB13=>DataInB(13), DIB14=>DataInB(14),
- DIB15=>DataInB(15), DIB16=>DataInB(16), DIB17=>DataInB(17),
- ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo,
- ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1),
- ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4),
- ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7),
- ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB,
- CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(0),
- DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
- DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
- DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
- DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
- DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
- DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
- DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
- DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
- DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ip_mem_0_1_0: DP16KC
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG",
- REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
- port map (DIA0=>DataInA(18), DIA1=>DataInA(19),
- DIA2=>DataInA(20), DIA3=>DataInA(21), DIA4=>DataInA(22),
- DIA5=>DataInA(23), DIA6=>DataInA(24), DIA7=>DataInA(25),
- DIA8=>DataInA(26), DIA9=>DataInA(27), DIA10=>DataInA(28),
- DIA11=>DataInA(29), DIA12=>DataInA(30), DIA13=>DataInA(31),
- DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo,
- DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>AddressA(0),
- ADA5=>AddressA(1), ADA6=>AddressA(2), ADA7=>AddressA(3),
- ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6),
- ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo,
- CEA=>ClockEnA, CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>ResetA, DIB0=>DataInB(18), DIB1=>DataInB(19),
- DIB2=>DataInB(20), DIB3=>DataInB(21), DIB4=>DataInB(22),
- DIB5=>DataInB(23), DIB6=>DataInB(24), DIB7=>DataInB(25),
- DIB8=>DataInB(26), DIB9=>DataInB(27), DIB10=>DataInB(28),
- DIB11=>DataInB(29), DIB12=>DataInB(30), DIB13=>DataInB(31),
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vhi, ADB1=>scuba_vhi,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>AddressB(0),
- ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3),
- ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6),
- ADB11=>AddressB(7), ADB12=>scuba_vlo, ADB13=>scuba_vlo,
- CEB=>ClockEnB, CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19), DOA2=>QA(20),
- DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23), DOA6=>QA(24),
- DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27), DOA10=>QA(28),
- DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31), DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>QB(18),
- DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21), DOB4=>QB(22),
- DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25), DOB8=>QB(26),
- DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29), DOB12=>QB(30),
- DOB13=>QB(31), DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of ip_mem is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process:
-
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Mon Mar 29 21:52:49 2010
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem -memformat orca -cascade -1 -e
- Circuit name : ip_mem
- Module type : RAM_DP_TRUE
- Module Version : 7.1
- Ports :
- Inputs : DataInA[31:0], DataInB[31:0], AddressA[7:0], AddressB[7:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
- Outputs : QA[31:0], QB[31:0]
- I/O buffer : not inserted
- Memory file : /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem
- EDIF output : suppressed
- VHDL output : ip_mem.vhd
- VHDL template : ip_mem_tmpl.vhd
- VHDL testbench : tb_ip_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : ip_mem.srp
- Estimated Resource Usage:
- EBR : 2
-
-END SCUBA Module Synthesis
-
-File: ip_mem.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 7.1
--- Thu Sep 22 11:24:37 2011
-
--- parameterized module component declaration
-component ip_mem
- port (DataInA: in std_logic_vector(31 downto 0);
- DataInB: in std_logic_vector(31 downto 0);
- AddressA: in std_logic_vector(7 downto 0);
- AddressB: in std_logic_vector(7 downto 0);
- ClockA: in std_logic; ClockB: in std_logic;
- ClockEnA: in std_logic; ClockEnB: in std_logic;
- WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic;
- ResetB: in std_logic; QA: out std_logic_vector(31 downto 0);
- QB: out std_logic_vector(31 downto 0));
-end component;
-
--- parameterized module component instance
-__ : ip_mem
- port map (DataInA(31 downto 0)=>__, DataInB(31 downto 0)=>__,
- AddressA(7 downto 0)=>__, AddressB(7 downto 0)=>__, ClockA=>__,
- ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__,
- ResetB=>__, QA(31 downto 0)=>__, QB(31 downto 0)=>__);
+++ /dev/null
-#Format=Bin\r
-#Depth=54\r
-#Width=8\r
-#AddrRadix=3\r
-#DataRadix=3\r
-#Data\r
-00001111\r
-00001111\r
-10011001\r
-00000001\r
-11101110\r
-00000101\r
-00000000\r
-00000000\r
-00001100\r
-00000000\r
-00110100\r
-00010010\r
-01111000\r
-01010110\r
-10111100\r
-10011010\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-10000000\r
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=ROM
-CoreRevision=5.0
-ModuleName=mac_init_mem
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:24:53
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-Address=54
-Data=8
-adPipeline=0
-inPipeline=0
-outPipeline=1
-MOR=0
-InData=Registered
-AdControl=Registered
-MemFile=macInitDataInvWithMac.mem
-MemFormat=bin
-Reset=Sync
-Pad=0
-GSR=Enabled
-EnECC=0
-Optimization=Speed
-Pipeline=0
-
-[FilesGenerated]
-macInitDataInvWithMac.mem=mem
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Thu Aug 20 16:00:49 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n mac_init_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type romblk -device LFE2M100E -addr_width 6 -data_width 8 -num_words 54 -outdata REGISTERED -resetmode SYNC -memfile /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -memformat bin -cascade -1 -e \r
- Circuit name : mac_init_mem\r
- Module type : EBR_ROM\r
- Module Version : 5.0\r
- Ports : \r
- Inputs : Address[5:0], OutClock, OutClockEn, Reset\r
- Outputs : Q[7:0]\r
- I/O buffer : not inserted\r
- Memory file : /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem\r
- EDIF output : suppressed\r
- VHDL output : mac_init_mem.vhd\r
- VHDL template : mac_init_mem_tmpl.vhd\r
- VHDL testbench : tb_mac_init_mem_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : mac_init_mem.srp\r
- Element Usage :\r
- DP16KB : 1\r
- Estimated Resource Usage:\r
- EBR : 1\r
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.0
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e
-
--- Thu Sep 22 11:24:53 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity mac_init_mem is
- port (
- Address: in std_logic_vector(5 downto 0);
- OutClock: in std_logic;
- OutClockEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(7 downto 0));
-end mac_init_mem;
-
-architecture Structure of mac_init_mem is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KC
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc";
- attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem";
- attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC";
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- mac_init_mem_0_0_0: DP16KC
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000",
- INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F",
- CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG",
- REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2),
- ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5),
- ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo,
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn,
- CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo,
- ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo,
- ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo,
- ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo,
- CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1),
- DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6),
- DOA7=>Q(7), DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open,
- DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of mac_init_mem is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Thu Aug 20 16:00:49 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n mac_init_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type romblk -device LFE2M100E -addr_width 6 -data_width 8 -num_words 54 -outdata REGISTERED -resetmode SYNC -memfile /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -memformat bin -cascade -1 -e \r
- Circuit name : mac_init_mem\r
- Module type : EBR_ROM\r
- Module Version : 5.0\r
- Ports : \r
- Inputs : Address[5:0], OutClock, OutClockEn, Reset\r
- Outputs : Q[7:0]\r
- I/O buffer : not inserted\r
- Memory file : /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem\r
- EDIF output : suppressed\r
- VHDL output : mac_init_mem.vhd\r
- VHDL template : mac_init_mem_tmpl.vhd\r
- VHDL testbench : tb_mac_init_mem_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : mac_init_mem.srp\r
- Estimated Resource Usage:\r
- EBR : 1\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: mac_init_mem.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.0
--- Thu Sep 22 11:24:53 2011
-
--- parameterized module component declaration
-component mac_init_mem
- port (Address: in std_logic_vector(5 downto 0);
- OutClock: in std_logic; OutClockEn: in std_logic;
- Reset: in std_logic; Q: out std_logic_vector(7 downto 0));
-end component;
-
--- parameterized module component instance
-__ : mac_init_mem
- port map (Address(5 downto 0)=>__, OutClock=>__, OutClockEn=>__,
- Reset=>__, Q(7 downto 0)=>__);
+++ /dev/null
-SCUBA, Version ispLever_v8.1_PROD_Build (20)
-Wed Jun 1 17:14:00 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x72
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[71:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x72.vhd
- VHDL template : fifo_512x72_tmpl.vhd
- VHDL testbench : tb_fifo_512x72_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x72.srp
- Estimated Resource Usage:
- LUT : 97
- EBR : 2
- Reg : 102
-
-END SCUBA Module Synthesis
-
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_2048x8
- port (Data : in std_logic_vector(7 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(7 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_2048x8
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 2051 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_32kx16x8_mb
- port (Data : in std_logic_vector(15 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(7 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(15 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0');
- signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0');
- signal Q : std_logic_vector(7 downto 0);
- signal WCNT : std_logic_vector(15 downto 0);
- signal RCNT : std_logic_vector(16 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
- signal AlmostEmpty: std_logic;
- signal AlmostFull: std_logic;
-begin
- u1 : fifo_32kx16x8_mb
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh,
- Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full,
- AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 32771 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41)\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.std_logic_unsigned.all;\r
-\r
-entity tb is\r
-end entity tb;\r
-\r
-\r
-architecture test of tb is \r
-\r
- component fifo_32kx16x8\r
- port (Data : in std_logic_vector(15 downto 0); \r
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; \r
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; \r
- Q : out std_logic_vector(7 downto 0); \r
- WCNT : out std_logic_vector(15 downto 0); \r
- RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; \r
- Full: out std_logic\r
- );\r
- end component;\r
-\r
- signal Data : std_logic_vector(15 downto 0) := (others => '0');\r
- signal WrClock: std_logic := '0';\r
- signal RdClock: std_logic := '0';\r
- signal WrEn: std_logic := '0';\r
- signal RdEn: std_logic := '0';\r
- signal Reset: std_logic := '0';\r
- signal RPReset: std_logic := '0';\r
- signal Q : std_logic_vector(7 downto 0);\r
- signal WCNT : std_logic_vector(15 downto 0);\r
- signal RCNT : std_logic_vector(16 downto 0);\r
- signal Empty: std_logic;\r
- signal Full: std_logic;\r
-begin\r
- u1 : fifo_32kx16x8\r
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock, \r
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, \r
- Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full\r
- );\r
-\r
- process\r
-\r
- begin\r
- Data <= (others => '0') ;\r
- wait for 100 ns;\r
- wait until Reset = '0';\r
- for i in 0 to 32771 loop\r
- wait until WrClock'event and WrClock = '1';\r
- Data <= Data + '1' after 1 ns;\r
- end loop;\r
- wait;\r
- end process;\r
-\r
- WrClock <= not WrClock after 5.00 ns;\r
-\r
- RdClock <= not RdClock after 5.00 ns;\r
-\r
- process\r
-\r
- begin\r
- WrEn <= '0' ;\r
- wait for 100 ns;\r
- wait until Reset = '0';\r
- for i in 0 to 32771 loop\r
- wait until WrClock'event and WrClock = '1';\r
- WrEn <= '1' after 1 ns;\r
- end loop;\r
- WrEn <= '0' ;\r
- wait;\r
- end process;\r
-\r
- process\r
-\r
- begin\r
- RdEn <= '0' ;\r
- wait until Reset = '0';\r
- wait until WrEn = '1';\r
- wait until WrEn = '0';\r
- for i in 0 to 32771 loop\r
- wait until RdClock'event and RdClock = '1';\r
- RdEn <= '1' after 1 ns;\r
- end loop;\r
- RdEn <= '0' ;\r
- wait;\r
- end process;\r
-\r
- process\r
-\r
- begin\r
- Reset <= '1' ;\r
- wait for 100 ns;\r
- Reset <= '0' ;\r
- wait;\r
- end process;\r
-\r
- process\r
-\r
- begin\r
- RPReset <= '1' ;\r
- wait for 100 ns;\r
- RPReset <= '0' ;\r
- wait;\r
- end process;\r
-\r
-end architecture test;\r
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_4096x32
- port (Data : in std_logic_vector(31 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(31 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(31 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(31 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_4096x32
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 4099 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_4096x9
- port (Data : in std_logic_vector(8 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(8 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(8 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_4096x9
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 4099 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v8.1_PROD_Build (20)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_512x64
- port (Data : in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(71 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(71 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(71 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_512x64
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 515 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v8.1_PROD_Build (20)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_512x72
- port (Data : in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(71 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(71 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(71 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_512x72
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 515 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_64kx8
- port (Data : in std_logic_vector(7 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(7 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_64kx8
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 65539 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component ip_mem
- port (DataInA : in std_logic_vector(31 downto 0);
- DataInB : in std_logic_vector(31 downto 0);
- AddressA : in std_logic_vector(7 downto 0);
- AddressB : in std_logic_vector(7 downto 0); ClockA: in std_logic;
- ClockB: in std_logic; ClockEnA: in std_logic;
- ClockEnB: in std_logic; WrA: in std_logic; WrB: in std_logic;
- ResetA: in std_logic; ResetB: in std_logic;
- QA : out std_logic_vector(31 downto 0);
- QB : out std_logic_vector(31 downto 0)
- );
- end component;
-
- signal DataInA : std_logic_vector(31 downto 0) := (others => '0');
- signal DataInB : std_logic_vector(31 downto 0) := (others => '0');
- signal AddressA : std_logic_vector(7 downto 0) := (others => '0');
- signal AddressB : std_logic_vector(7 downto 0) := (others => '0');
- signal ClockA: std_logic := '0';
- signal ClockB: std_logic := '0';
- signal ClockEnA: std_logic := '0';
- signal ClockEnB: std_logic := '0';
- signal WrA: std_logic := '0';
- signal WrB: std_logic := '0';
- signal ResetA: std_logic := '0';
- signal ResetB: std_logic := '0';
- signal QA : std_logic_vector(31 downto 0);
- signal QB : std_logic_vector(31 downto 0);
-begin
- u1 : ip_mem
- port map (DataInA => DataInA, DataInB => DataInB, AddressA => AddressA,
- AddressB => AddressB, ClockA => ClockA, ClockB => ClockB,
- ClockEnA => ClockEnA, ClockEnB => ClockEnB, WrA => WrA, WrB => WrB,
- ResetA => ResetA, ResetB => ResetB, QA => QA, QB => QB
- );
-
- process
-
- begin
- DataInA <= (others => '0') ;
- wait for 100 ns;
- wait until ResetA = '0';
- for i in 0 to 259 loop
- wait until ClockA'event and ClockA = '1';
- DataInA <= DataInA + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- DataInB <= (others => '0') ;
- wait for 100 ns;
- wait until ResetB = '0';
- wait until WrB = '1';
- for i in 0 to 259 loop
- wait until ClockB'event and ClockB = '1';
- DataInB <= DataInB + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- AddressA <= (others => '0') ;
- wait for 100 ns;
- wait until ResetA = '0';
- for i in 0 to 518 loop
- wait until ClockA'event and ClockA = '1';
- AddressA <= AddressA + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- AddressB <= (others => '0') ;
- wait for 100 ns;
- wait until ResetB = '0';
- wait until WrB = '1';
- for i in 0 to 518 loop
- wait until ClockB'event and ClockB = '1';
- AddressB <= AddressB + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- ClockA <= not ClockA after 5.00 ns;
-
- ClockB <= not ClockB after 5.00 ns;
-
- process
-
- begin
- ClockEnA <= '0' ;
- wait for 100 ns;
- wait until ResetA = '0';
- ClockEnA <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- ClockEnB <= '0' ;
- wait for 100 ns;
- wait until ResetB = '0';
- ClockEnB <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- WrA <= '0' ;
- wait until ResetA = '0';
- for i in 0 to 259 loop
- wait until ClockA'event and ClockA = '1';
- WrA <= '1' after 1 ns;
- end loop;
- WrA <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- WrB <= '0' ;
- wait until ResetB = '0';
- wait until WrA = '1';
- wait until WrA = '0';
- for i in 0 to 259 loop
- wait until ClockA'event and ClockA = '1';
- end loop;
- for i in 0 to 259 loop
- wait until ClockB'event and ClockB = '1';
- WrB <= '1' after 1 ns;
- end loop;
- WrB <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- ResetA <= '1' ;
- wait for 100 ns;
- ResetA <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- ResetB <= '1' ;
- wait for 100 ns;
- ResetB <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component mac_init_mem
- port (Address : in std_logic_vector(5 downto 0);
- OutClock: in std_logic; OutClockEn: in std_logic;
- Reset: in std_logic; Q : out std_logic_vector(7 downto 0)
- );
- end component;
-
- signal Address : std_logic_vector(5 downto 0) := (others => '0');
- signal OutClock: std_logic := '0';
- signal OutClockEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
-begin
- u1 : mac_init_mem
- port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn,
- Reset => Reset, Q => Q
- );
-
- process
-
- begin
- Address <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 57 loop
- wait until OutClock'event and OutClock = '1';
- Address <= Address + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- OutClock <= not OutClock after 5.00 ns;
-
- process
-
- begin
- OutClockEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- OutClockEn <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 5.2
---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 16 -depth 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -e
-
--- Wed Jul 21 14:35:10 2010
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity debug_fifo_2kx16 is
- port (
- Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(15 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end debug_fifo_2kx16;
-
-architecture Structure of debug_fifo_2kx16 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5: std_logic;
- signal wcount_11: std_logic;
- signal co4: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5_1: std_logic;
- signal rcount_11: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_10: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_10: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
- attribute initval of LUT4_31 : label is "0x6996";
- attribute initval of LUT4_30 : label is "0x6996";
- attribute initval of LUT4_29 : label is "0x6996";
- attribute initval of LUT4_28 : label is "0x6996";
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "debug_fifo_2kx16.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL";
- attribute GSR of pdp_ram_0_0_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "debug_fifo_2kx16.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute CSDECODE_B of pdp_ram_0_1_0 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_1_0 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_1_0 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_1_0 : label is "NORMAL";
- attribute GSR of pdp_ram_0_1_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_1_0 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_1_0 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_1_0 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_0_1_0 : label is "9";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t24: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t23: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t22: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t21: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t9: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t8: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t7: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t6: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t5: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t4: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t3: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t2: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t1: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t0: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- LUT4_31: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5),
- DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(9),
- DOB1=>Q(10), DOB2=>Q(11), DOB3=>Q(12), DOB4=>Q(13),
- DOB5=>Q(14), DOB6=>Q(15), DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_121: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_120: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_119: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_118: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_117: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_116: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_115: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_114: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_113: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_112: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_111: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_110: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_109: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_108: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_107: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_106: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_105: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_104: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_103: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_102: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_101: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_85: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_71: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_61: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_60: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_59: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_58: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_57: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_56: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_55: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_54: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_53: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_52: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_51: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_50: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10,
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10,
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of debug_fifo_2kx16 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_1024x16x8" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 12 05 18:27:27.392" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="fifo_1024x16x8.lpc" type="lpc" modified="2011 12 05 18:27:25.000"/>
- <File name="fifo_1024x16x8.vhd" type="top_level_vhdl" modified="2011 12 05 18:27:25.000"/>
- <File name="fifo_1024x16x8_tmpl.vhd" type="template_vhdl" modified="2011 12 05 18:27:25.000"/>
- <File name="tb_fifo_1024x16x8_tmpl.vhd" type="testbench_vhdl" modified="2011 12 05 18:27:25.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_1024x16x8 DEFIN fifo_1024x16x8.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_5
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_5
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE CU2
- INSTANCE r_gctr_5
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_5
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1S3DX
- INSTANCE FF_42
- SUBMODULE FD1S3DX
- INSTANCE FF_43
- SUBMODULE FD1S3DX
- INSTANCE FF_44
- SUBMODULE FD1S3DX
- INSTANCE FF_45
- SUBMODULE FD1S3DX
- INSTANCE FF_46
- SUBMODULE FD1S3DX
- INSTANCE FF_47
- SUBMODULE FD1P3DX
- INSTANCE FF_48
- SUBMODULE FD1P3DX
- INSTANCE FF_49
- SUBMODULE FD1P3DX
- INSTANCE FF_50
- SUBMODULE FD1P3DX
- INSTANCE FF_51
- SUBMODULE FD1P3DX
- INSTANCE FF_52
- SUBMODULE FD1P3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3DX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3BX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3DX
- INSTANCE FF_101
- SUBMODULE FD1P3DX
- INSTANCE FF_102
- SUBMODULE FD1P3DX
- INSTANCE FF_103
- SUBMODULE FD1P3DX
- INSTANCE FF_104
- SUBMODULE FD1P3DX
- INSTANCE FF_105
- SUBMODULE FD1P3DX
- INSTANCE FF_106
- SUBMODULE FD1P3DX
- INSTANCE FF_107
- SUBMODULE FD1P3DX
- INSTANCE FF_108
- SUBMODULE FD1P3DX
- INSTANCE FF_109
- SUBMODULE FD1P3DX
- INSTANCE FF_110
- SUBMODULE FD1P3DX
- INSTANCE FF_111
- SUBMODULE FD1P3DX
- INSTANCE FF_112
- SUBMODULE FD1P3DX
- INSTANCE FF_113
- SUBMODULE FD1P3DX
- INSTANCE FF_114
- SUBMODULE FD1P3DX
- INSTANCE FF_115
- SUBMODULE FD1P3BX
- INSTANCE FF_116
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_0_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE ROM16X1A
- INSTANCE LUT4_24
- SUBMODULE ROM16X1A
- INSTANCE LUT4_25
- SUBMODULE ROM16X1A
- INSTANCE LUT4_26
- SUBMODULE ROM16X1A
- INSTANCE LUT4_27
- SUBMODULE ROM16X1A
- INSTANCE LUT4_28
- SUBMODULE ROM16X1A
- INSTANCE LUT4_29
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE XOR2
- INSTANCE XOR2_t18
- SUBMODULE XOR2
- INSTANCE XOR2_t19
- SUBMODULE XOR2
- INSTANCE XOR2_t20
- SUBMODULE OR2
- INSTANCE OR2_t21
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t22
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t23
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_1024x16x8
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/05/2011
-Time=18:27:25
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=1024
-Width=18
-RDepth=2048
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[17] i
-Data[16] i
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_1024x16x8.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Mon Dec 5 18:27:25 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_1024x16x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 10 -data_width 18 -num_words 1024 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_1024x16x8
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_1024x16x8.vhd
- VHDL template : fifo_1024x16x8_tmpl.vhd
- VHDL testbench : tb_fifo_1024x16x8_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_1024x16x8.srp
- Element Usage :
- AGEB2 : 12
- AND2 : 2
- CU2 : 12
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 67
- FD1S3BX : 1
- FD1S3DX : 47
- INV : 2
- OR2 : 1
- ROM16X1A : 30
- XOR2 : 21
- DP16KC : 1
- Estimated Resource Usage:
- LUT : 114
- EBR : 1
- Reg : 117
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 18 -depth 1024 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
-
--- Mon Dec 5 18:27:25 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_1024x16x8 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_1024x16x8;
-
-architecture Structure of fifo_1024x16x8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal rcount_w0: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal co5: std_logic;
- signal wcount_10: std_logic;
- signal co4: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5_1: std_logic;
- signal rcount_11: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r8: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r9: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_10: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w9: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_1024x16x8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t23: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t22: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t21: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t20: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t19: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t18: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t17: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t16: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t15: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t14: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t13: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t12: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t11: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t10: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t9: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t8: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t7: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t6: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t5: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t4: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t3: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t2: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t1: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t0: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>w_gcount_r210,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_gcount_r26,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r4);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>w_gcount_r22, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3),
- DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8),
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- FF_116: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_115: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_114: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_113: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_112: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_111: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_110: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_109: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_108: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_107: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_106: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_105: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_104: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_103: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_102: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_101: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_100: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_99: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_98: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_97: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_96: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_95: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_94: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_93: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_92: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_91: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_90: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_89: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_88: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_87: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_86: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_85: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_84: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_83: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_82: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_81: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_80: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_79: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_78: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_77: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_76: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_75: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_74: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_73: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_72: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_66: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_65: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_64: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_63: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_62: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_60: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_59: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_58: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_57: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_56: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_55: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_54: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_53: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_52: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_51: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_50: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_49: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_48: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5,
- NC0=>iwcount_10, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r8, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r9,
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>r_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
- B1=>rcount_w10, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_1024x16x8 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Mon Dec 5 18:27:25 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_1024x16x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 10 -data_width 18 -num_words 1024 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_1024x16x8
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_1024x16x8.vhd
- VHDL template : fifo_1024x16x8_tmpl.vhd
- VHDL testbench : tb_fifo_1024x16x8_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_1024x16x8.srp
- Estimated Resource Usage:
- LUT : 114
- EBR : 1
- Reg : 117
-
-END SCUBA Module Synthesis
-
-File: fifo_1024x16x8.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Mon Dec 5 18:27:25 2011
-
--- parameterized module component declaration
-component fifo_1024x16x8
- port (Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_1024x16x8
- port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
--- Module Version: 5.4
---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 8 -depth 16384 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Mon Dec 6 19:08:10 2010
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity fifo_16kx8 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_16kx8;
-
-architecture Structure of fifo_16kx8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal co7: std_logic;
- signal wcount_14: std_logic;
- signal co6: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal co7_1: std_logic;
- signal rcount_14: std_logic;
- signal co6_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal wcount_r12: std_logic;
- signal wcount_r13: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal rcount_w12: std_logic;
- signal rcount_w13: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
- attribute initval of LUT4_41 : label is "0x6996";
- attribute initval of LUT4_40 : label is "0x6996";
- attribute initval of LUT4_39 : label is "0x6996";
- attribute initval of LUT4_38 : label is "0x6996";
- attribute initval of LUT4_37 : label is "0x6996";
- attribute initval of LUT4_36 : label is "0x6996";
- attribute initval of LUT4_35 : label is "0x6996";
- attribute initval of LUT4_34 : label is "0x6996";
- attribute initval of LUT4_33 : label is "0x6996";
- attribute initval of LUT4_32 : label is "0x6996";
- attribute initval of LUT4_31 : label is "0x6996";
- attribute initval of LUT4_30 : label is "0x6996";
- attribute initval of LUT4_29 : label is "0x6996";
- attribute initval of LUT4_28 : label is "0x6996";
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
- attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL";
- attribute GSR of pdp_ram_0_0_7 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
- attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL";
- attribute GSR of pdp_ram_0_1_6 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is "";
- attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL";
- attribute GSR of pdp_ram_0_2_5 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is "";
- attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL";
- attribute GSR of pdp_ram_0_3_4 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is "";
- attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL";
- attribute GSR of pdp_ram_0_4_3 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is "";
- attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL";
- attribute GSR of pdp_ram_0_5_2 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is "";
- attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL";
- attribute GSR of pdp_ram_0_6_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is "";
- attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL";
- attribute GSR of pdp_ram_0_7_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "1";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t30: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t29: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t28: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t27: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t26: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t25: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t24: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t23: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t22: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t21: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t20: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t19: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t18: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t17: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t16: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t15: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t14: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t13: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t12: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t11: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t10: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t9: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t8: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t7: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t6: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t5: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t4: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t3: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t2: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t1: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t0: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- LUT4_41: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>w_gcount_r214,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_40: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>w_gcount_r210,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_39: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_gcount_r26,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_38: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_37: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>scuba_vlo, DO0=>wcount_r12);
-
- LUT4_36: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_35: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9);
-
- LUT4_34: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r8);
-
- LUT4_33: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_32: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r6);
-
- LUT4_31: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>wcount_r5);
-
- LUT4_30: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_29: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_28: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r22, DO0=>wcount_r2);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r1);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r0);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>r_gcount_w214,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>r_gcount_w210,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_gcount_w26,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w13);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>scuba_vlo, DO0=>rcount_w12);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w8);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w25, AD0=>r_gcount_w26, DO0=>rcount_w5);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w22, DO0=>rcount_w2);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_7: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(0), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_1_6: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(1), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_2_5: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(2), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_3_4: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(3), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_4_3: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(4), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_5_2: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(5), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_6_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(6), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_7_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(7), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- FF_151: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_150: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_149: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_148: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_147: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_146: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_145: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_144: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_143: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_142: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_141: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_140: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_139: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_138: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_137: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_136: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_135: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_134: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_133: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_132: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_131: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_130: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_129: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_128: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_127: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_126: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_125: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_124: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_123: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_122: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_121: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_120: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_119: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_118: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_117: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_116: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_115: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_114: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_113: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_112: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_111: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_110: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_109: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_108: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_107: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_106: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_105: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_104: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_103: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_102: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_101: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_85: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_71: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_61: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_60: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_59: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_58: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_57: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_56: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_55: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_54: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_53: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_52: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_51: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_50: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7,
- NC0=>iwcount_14, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_1,
- NC0=>ircount_14, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>w_g2b_xor_cluster_0, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12,
- B1=>wcount_r13, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co6_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>r_g2b_xor_cluster_0, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12,
- B1=>rcount_w13, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co6_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of fifo_16kx8 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_2048x8" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:24:00.079" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_2048x8.lpc" type="lpc" modified="2011 09 22 11:23:58.000"/>
- <File name="fifo_2048x8.vhd" type="top_level_vhdl" modified="2011 09 22 11:23:58.000"/>
- <File name="fifo_2048x8_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:23:58.000"/>
- <File name="tb_fifo_2048x8_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:23:58.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_2048x8 DEFIN fifo_2048x8.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_5
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_5
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE CU2
- INSTANCE r_gctr_5
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_5
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1S3DX
- INSTANCE FF_42
- SUBMODULE FD1S3DX
- INSTANCE FF_43
- SUBMODULE FD1S3DX
- INSTANCE FF_44
- SUBMODULE FD1S3DX
- INSTANCE FF_45
- SUBMODULE FD1S3DX
- INSTANCE FF_46
- SUBMODULE FD1S3DX
- INSTANCE FF_47
- SUBMODULE FD1S3DX
- INSTANCE FF_48
- SUBMODULE FD1S3DX
- INSTANCE FF_49
- SUBMODULE FD1P3DX
- INSTANCE FF_50
- SUBMODULE FD1P3DX
- INSTANCE FF_51
- SUBMODULE FD1P3DX
- INSTANCE FF_52
- SUBMODULE FD1P3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3DX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3BX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3DX
- INSTANCE FF_101
- SUBMODULE FD1P3DX
- INSTANCE FF_102
- SUBMODULE FD1P3DX
- INSTANCE FF_103
- SUBMODULE FD1P3DX
- INSTANCE FF_104
- SUBMODULE FD1P3DX
- INSTANCE FF_105
- SUBMODULE FD1P3DX
- INSTANCE FF_106
- SUBMODULE FD1P3DX
- INSTANCE FF_107
- SUBMODULE FD1P3DX
- INSTANCE FF_108
- SUBMODULE FD1P3DX
- INSTANCE FF_109
- SUBMODULE FD1P3DX
- INSTANCE FF_110
- SUBMODULE FD1P3DX
- INSTANCE FF_111
- SUBMODULE FD1P3DX
- INSTANCE FF_112
- SUBMODULE FD1P3DX
- INSTANCE FF_113
- SUBMODULE FD1P3DX
- INSTANCE FF_114
- SUBMODULE FD1P3DX
- INSTANCE FF_115
- SUBMODULE FD1P3DX
- INSTANCE FF_116
- SUBMODULE FD1P3DX
- INSTANCE FF_117
- SUBMODULE FD1P3DX
- INSTANCE FF_118
- SUBMODULE FD1P3DX
- INSTANCE FF_119
- SUBMODULE FD1P3DX
- INSTANCE FF_120
- SUBMODULE FD1P3BX
- INSTANCE FF_121
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_0_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE ROM16X1A
- INSTANCE LUT4_24
- SUBMODULE ROM16X1A
- INSTANCE LUT4_25
- SUBMODULE ROM16X1A
- INSTANCE LUT4_26
- SUBMODULE ROM16X1A
- INSTANCE LUT4_27
- SUBMODULE ROM16X1A
- INSTANCE LUT4_28
- SUBMODULE ROM16X1A
- INSTANCE LUT4_29
- SUBMODULE ROM16X1A
- INSTANCE LUT4_30
- SUBMODULE ROM16X1A
- INSTANCE LUT4_31
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE XOR2
- INSTANCE XOR2_t18
- SUBMODULE XOR2
- INSTANCE XOR2_t19
- SUBMODULE XOR2
- INSTANCE XOR2_t20
- SUBMODULE XOR2
- INSTANCE XOR2_t21
- SUBMODULE OR2
- INSTANCE OR2_t22
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t23
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t24
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_2048x8
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:23:58
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=2048
-Width=8
-RDepth=2048
-RWidth=8
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_2048x8.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:58 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_2048x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_2048x8
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[7:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_2048x8.vhd
- VHDL template : fifo_2048x8_tmpl.vhd
- VHDL testbench : tb_fifo_2048x8_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_2048x8.srp
- Element Usage :
- AGEB2 : 12
- AND2 : 2
- CU2 : 12
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 70
- FD1S3BX : 1
- FD1S3DX : 49
- INV : 2
- OR2 : 1
- ROM16X1A : 32
- XOR2 : 22
- DP16KC : 1
- Estimated Resource Usage:
- LUT : 117
- EBR : 1
- Reg : 122
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:23:58 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_2048x8 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_2048x8;
-
-architecture Structure of fifo_2048x8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5: std_logic;
- signal wcount_11: std_logic;
- signal co4: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5_1: std_logic;
- signal rcount_11: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_10: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_10: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t24: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t23: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t22: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t21: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t9: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t8: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t7: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t6: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t5: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t4: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t3: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t2: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t1: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t0: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2),
- DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7),
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_121: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_119: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_118: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_117: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_116: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_115: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_114: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_113: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_112: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_111: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_110: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_107: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_106: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_105: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_104: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_103: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_102: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_101: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_100: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_99: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_98: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_97: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_96: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_95: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_94: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_93: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_92: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_91: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_90: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_89: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_88: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_87: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_86: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_85: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_84: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_83: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_82: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_81: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_80: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_79: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_78: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_77: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_76: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_75: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_74: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_66: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_65: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_64: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_63: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_62: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_61: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_60: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_59: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_58: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_57: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_56: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_55: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_54: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_53: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_52: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_51: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_50: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10,
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10,
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_2048x8 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:58 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_2048x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_2048x8
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[7:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_2048x8.vhd
- VHDL template : fifo_2048x8_tmpl.vhd
- VHDL testbench : tb_fifo_2048x8_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_2048x8.srp
- Estimated Resource Usage:
- LUT : 117
- EBR : 1
- Reg : 122
-
-END SCUBA Module Synthesis
-
-File: fifo_2048x8.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:23:58 2011
-
--- parameterized module component declaration
-component fifo_2048x8
- port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_2048x8
- port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_2048x8x16" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 12 05 18:26:55.246" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="fifo_2048x8x16.lpc" type="lpc" modified="2011 12 05 18:26:53.000"/>
- <File name="fifo_2048x8x16.vhd" type="top_level_vhdl" modified="2011 12 05 18:26:53.000"/>
- <File name="fifo_2048x8x16_tmpl.vhd" type="template_vhdl" modified="2011 12 05 18:26:53.000"/>
- <File name="tb_fifo_2048x8x16_tmpl.vhd" type="testbench_vhdl" modified="2011 12 05 18:26:53.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_2048x8x16 DEFIN fifo_2048x8x16.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_5
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_5
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE CU2
- INSTANCE r_gctr_5
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_5
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1S3DX
- INSTANCE FF_42
- SUBMODULE FD1S3DX
- INSTANCE FF_43
- SUBMODULE FD1S3DX
- INSTANCE FF_44
- SUBMODULE FD1S3DX
- INSTANCE FF_45
- SUBMODULE FD1S3DX
- INSTANCE FF_46
- SUBMODULE FD1S3DX
- INSTANCE FF_47
- SUBMODULE FD1P3DX
- INSTANCE FF_48
- SUBMODULE FD1P3DX
- INSTANCE FF_49
- SUBMODULE FD1P3DX
- INSTANCE FF_50
- SUBMODULE FD1P3DX
- INSTANCE FF_51
- SUBMODULE FD1P3DX
- INSTANCE FF_52
- SUBMODULE FD1P3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3DX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3BX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3DX
- INSTANCE FF_101
- SUBMODULE FD1P3DX
- INSTANCE FF_102
- SUBMODULE FD1P3DX
- INSTANCE FF_103
- SUBMODULE FD1P3DX
- INSTANCE FF_104
- SUBMODULE FD1P3DX
- INSTANCE FF_105
- SUBMODULE FD1P3DX
- INSTANCE FF_106
- SUBMODULE FD1P3DX
- INSTANCE FF_107
- SUBMODULE FD1P3DX
- INSTANCE FF_108
- SUBMODULE FD1P3DX
- INSTANCE FF_109
- SUBMODULE FD1P3DX
- INSTANCE FF_110
- SUBMODULE FD1P3DX
- INSTANCE FF_111
- SUBMODULE FD1P3DX
- INSTANCE FF_112
- SUBMODULE FD1P3DX
- INSTANCE FF_113
- SUBMODULE FD1P3DX
- INSTANCE FF_114
- SUBMODULE FD1P3DX
- INSTANCE FF_115
- SUBMODULE FD1P3BX
- INSTANCE FF_116
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_0_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE ROM16X1A
- INSTANCE LUT4_24
- SUBMODULE ROM16X1A
- INSTANCE LUT4_25
- SUBMODULE ROM16X1A
- INSTANCE LUT4_26
- SUBMODULE ROM16X1A
- INSTANCE LUT4_27
- SUBMODULE ROM16X1A
- INSTANCE LUT4_28
- SUBMODULE ROM16X1A
- INSTANCE LUT4_29
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE XOR2
- INSTANCE XOR2_t18
- SUBMODULE XOR2
- INSTANCE XOR2_t19
- SUBMODULE XOR2
- INSTANCE XOR2_t20
- SUBMODULE OR2
- INSTANCE OR2_t21
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t22
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t23
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_2048x8x16
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/05/2011
-Time=18:26:53
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=2048
-Width=9
-RDepth=1024
-RWidth=18
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[17] o
-Q[16] o
-Q[15] o
-Q[14] o
-Q[13] o
-Q[12] o
-Q[11] o
-Q[10] o
-Q[9] o
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_2048x8x16.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Mon Dec 5 18:26:53 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_2048x8x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 9 -num_words 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_2048x8x16
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[17:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_2048x8x16.vhd
- VHDL template : fifo_2048x8x16_tmpl.vhd
- VHDL testbench : tb_fifo_2048x8x16_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_2048x8x16.srp
- Element Usage :
- AGEB2 : 12
- AND2 : 2
- CU2 : 12
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 67
- FD1S3BX : 1
- FD1S3DX : 47
- INV : 2
- OR2 : 1
- ROM16X1A : 30
- XOR2 : 21
- DP16KC : 1
- Estimated Resource Usage:
- LUT : 114
- EBR : 1
- Reg : 117
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 9 -depth 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -e
-
--- Mon Dec 5 18:26:53 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_2048x8x16 is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_2048x8x16;
-
-architecture Structure of fifo_2048x8x16 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal wcount_r0: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5: std_logic;
- signal wcount_11: std_logic;
- signal co4: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal co5_1: std_logic;
- signal rcount_10: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r7: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w9: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_10: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8x16.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t23: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t22: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t21: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t20: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t19: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t18: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t17: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t16: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t15: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t14: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t13: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t12: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t11: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t10: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t9: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t8: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t7: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t6: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t5: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t4: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t3: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t2: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t1: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t0: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>r_gcount_w210,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_gcount_w26,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
- ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3,
- ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, ADB11=>rptr_7,
- ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5),
- DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10),
- DOB11=>Q(11), DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14),
- DOB15=>Q(15), DOB16=>Q(16), DOB17=>Q(17));
-
- FF_116: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_115: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_114: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_113: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_112: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_111: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_110: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_109: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_108: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_107: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_106: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_105: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_104: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_103: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_102: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_101: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_100: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_99: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_98: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_97: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_96: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_95: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_94: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_93: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_92: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_91: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_90: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_89: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_88: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_87: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_86: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_85: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_84: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_83: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_82: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_81: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_80: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_79: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_78: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_77: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_76: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_75: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_74: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_73: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_72: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_71: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_70: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_66: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_65: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_64: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_63: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_62: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_59: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_58: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_57: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_56: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_55: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_54: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_53: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_52: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_51: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_50: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_49: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_48: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1,
- NC0=>ircount_10, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r1,
- B1=>wcount_r2, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r7,
- B1=>w_g2b_xor_cluster_0, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
- B1=>rcount_w0, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w1,
- B1=>rcount_w2, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w8, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w9,
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_2048x8x16 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Mon Dec 5 18:26:53 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_2048x8x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 9 -num_words 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_2048x8x16
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[17:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_2048x8x16.vhd
- VHDL template : fifo_2048x8x16_tmpl.vhd
- VHDL testbench : tb_fifo_2048x8x16_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_2048x8x16.srp
- Estimated Resource Usage:
- LUT : 114
- EBR : 1
- Reg : 117
-
-END SCUBA Module Synthesis
-
-File: fifo_2048x8x16.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Mon Dec 5 18:26:53 2011
-
--- parameterized module component declaration
-component fifo_2048x8x16
- port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_2048x8x16
- port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(17 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_32kx16x8_mb" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:22:37.333" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_32kx16x8_mb.lpc" type="lpc" modified="2011 09 22 11:22:35.000"/>
- <File name="fifo_32kx16x8_mb.vhd" type="top_level_vhdl" modified="2011 09 22 11:22:35.000"/>
- <File name="fifo_32kx16x8_mb_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:22:35.000"/>
- <File name="tb_fifo_32kx16x8_mb_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:22:35.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_32kx16x8_mb DEFIN fifo_32kx16x8_mb.vhd
- SUBMODULE FADD2B
- INSTANCE a3
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_7
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_6
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_5
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_4
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_3
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_2
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_1
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_0
- SUBMODULE FADD2B
- INSTANCE af_d_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a2
- SUBMODULE AGEB2
- INSTANCE ae_cmp_8
- SUBMODULE AGEB2
- INSTANCE ae_cmp_7
- SUBMODULE AGEB2
- INSTANCE ae_cmp_6
- SUBMODULE AGEB2
- INSTANCE ae_cmp_5
- SUBMODULE AGEB2
- INSTANCE ae_cmp_4
- SUBMODULE AGEB2
- INSTANCE ae_cmp_3
- SUBMODULE AGEB2
- INSTANCE ae_cmp_2
- SUBMODULE AGEB2
- INSTANCE ae_cmp_1
- SUBMODULE AGEB2
- INSTANCE ae_cmp_0
- SUBMODULE FADD2B
- INSTANCE ae_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE AGEB2
- INSTANCE full_cmp_7
- SUBMODULE AGEB2
- INSTANCE full_cmp_6
- SUBMODULE AGEB2
- INSTANCE full_cmp_5
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_8
- SUBMODULE AGEB2
- INSTANCE empty_cmp_7
- SUBMODULE AGEB2
- INSTANCE empty_cmp_6
- SUBMODULE AGEB2
- INSTANCE empty_cmp_5
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE rfilld
- SUBMODULE FSUB2B
- INSTANCE rfill_8
- SUBMODULE FSUB2B
- INSTANCE rfill_7
- SUBMODULE FSUB2B
- INSTANCE rfill_6
- SUBMODULE FSUB2B
- INSTANCE rfill_5
- SUBMODULE FSUB2B
- INSTANCE rfill_4
- SUBMODULE FSUB2B
- INSTANCE rfill_3
- SUBMODULE FSUB2B
- INSTANCE rfill_2
- SUBMODULE FSUB2B
- INSTANCE rfill_1
- SUBMODULE FSUB2B
- INSTANCE rfill_0
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE FSUB2B
- INSTANCE wfill_8
- SUBMODULE FSUB2B
- INSTANCE wfill_7
- SUBMODULE FSUB2B
- INSTANCE wfill_6
- SUBMODULE FSUB2B
- INSTANCE wfill_5
- SUBMODULE FSUB2B
- INSTANCE wfill_4
- SUBMODULE FSUB2B
- INSTANCE wfill_3
- SUBMODULE FSUB2B
- INSTANCE wfill_2
- SUBMODULE FSUB2B
- INSTANCE wfill_1
- SUBMODULE FSUB2B
- INSTANCE wfill_0
- SUBMODULE FADD2B
- INSTANCE rcntd
- SUBMODULE FSUB2B
- INSTANCE rcnt_8
- SUBMODULE FSUB2B
- INSTANCE rcnt_7
- SUBMODULE FSUB2B
- INSTANCE rcnt_6
- SUBMODULE FSUB2B
- INSTANCE rcnt_5
- SUBMODULE FSUB2B
- INSTANCE rcnt_4
- SUBMODULE FSUB2B
- INSTANCE rcnt_3
- SUBMODULE FSUB2B
- INSTANCE rcnt_2
- SUBMODULE FSUB2B
- INSTANCE rcnt_1
- SUBMODULE FSUB2B
- INSTANCE rcnt_0
- SUBMODULE FSUB2B
- INSTANCE wcnt_8
- SUBMODULE FSUB2B
- INSTANCE wcnt_7
- SUBMODULE FSUB2B
- INSTANCE wcnt_6
- SUBMODULE FSUB2B
- INSTANCE wcnt_5
- SUBMODULE FSUB2B
- INSTANCE wcnt_4
- SUBMODULE FSUB2B
- INSTANCE wcnt_3
- SUBMODULE FSUB2B
- INSTANCE wcnt_2
- SUBMODULE FSUB2B
- INSTANCE wcnt_1
- SUBMODULE FSUB2B
- INSTANCE wcnt_0
- SUBMODULE MUX41
- INSTANCE mux_0
- SUBMODULE MUX41
- INSTANCE mux_1
- SUBMODULE MUX41
- INSTANCE mux_2
- SUBMODULE MUX41
- INSTANCE mux_3
- SUBMODULE MUX41
- INSTANCE mux_4
- SUBMODULE MUX41
- INSTANCE mux_5
- SUBMODULE MUX41
- INSTANCE mux_6
- SUBMODULE MUX41
- INSTANCE mux_7
- SUBMODULE CU2
- INSTANCE r_gctr_8
- SUBMODULE CU2
- INSTANCE r_gctr_7
- SUBMODULE CU2
- INSTANCE r_gctr_6
- SUBMODULE CU2
- INSTANCE r_gctr_5
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE CU2
- INSTANCE w_gctr_7
- SUBMODULE CU2
- INSTANCE w_gctr_6
- SUBMODULE CU2
- INSTANCE w_gctr_5
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3BX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1S3DX
- INSTANCE FF_42
- SUBMODULE FD1S3DX
- INSTANCE FF_43
- SUBMODULE FD1S3DX
- INSTANCE FF_44
- SUBMODULE FD1S3DX
- INSTANCE FF_45
- SUBMODULE FD1S3DX
- INSTANCE FF_46
- SUBMODULE FD1S3DX
- INSTANCE FF_47
- SUBMODULE FD1S3DX
- INSTANCE FF_48
- SUBMODULE FD1S3DX
- INSTANCE FF_49
- SUBMODULE FD1S3DX
- INSTANCE FF_50
- SUBMODULE FD1S3DX
- INSTANCE FF_51
- SUBMODULE FD1S3DX
- INSTANCE FF_52
- SUBMODULE FD1S3DX
- INSTANCE FF_53
- SUBMODULE FD1S3DX
- INSTANCE FF_54
- SUBMODULE FD1S3DX
- INSTANCE FF_55
- SUBMODULE FD1S3DX
- INSTANCE FF_56
- SUBMODULE FD1S3DX
- INSTANCE FF_57
- SUBMODULE FD1S3DX
- INSTANCE FF_58
- SUBMODULE FD1S3DX
- INSTANCE FF_59
- SUBMODULE FD1S3DX
- INSTANCE FF_60
- SUBMODULE FD1S3DX
- INSTANCE FF_61
- SUBMODULE FD1S3DX
- INSTANCE FF_62
- SUBMODULE FD1S3DX
- INSTANCE FF_63
- SUBMODULE FD1S3DX
- INSTANCE FF_64
- SUBMODULE FD1S3DX
- INSTANCE FF_65
- SUBMODULE FD1S3DX
- INSTANCE FF_66
- SUBMODULE FD1S3DX
- INSTANCE FF_67
- SUBMODULE FD1S3DX
- INSTANCE FF_68
- SUBMODULE FD1S3DX
- INSTANCE FF_69
- SUBMODULE FD1S3DX
- INSTANCE FF_70
- SUBMODULE FD1S3DX
- INSTANCE FF_71
- SUBMODULE FD1S3DX
- INSTANCE FF_72
- SUBMODULE FD1S3DX
- INSTANCE FF_73
- SUBMODULE FD1S3DX
- INSTANCE FF_74
- SUBMODULE FD1S3DX
- INSTANCE FF_75
- SUBMODULE FD1S3DX
- INSTANCE FF_76
- SUBMODULE FD1S3DX
- INSTANCE FF_77
- SUBMODULE FD1S3DX
- INSTANCE FF_78
- SUBMODULE FD1S3DX
- INSTANCE FF_79
- SUBMODULE FD1S3DX
- INSTANCE FF_80
- SUBMODULE FD1S3DX
- INSTANCE FF_81
- SUBMODULE FD1S3DX
- INSTANCE FF_82
- SUBMODULE FD1S3DX
- INSTANCE FF_83
- SUBMODULE FD1S3DX
- INSTANCE FF_84
- SUBMODULE FD1S3DX
- INSTANCE FF_85
- SUBMODULE FD1S3DX
- INSTANCE FF_86
- SUBMODULE FD1S3DX
- INSTANCE FF_87
- SUBMODULE FD1S3DX
- INSTANCE FF_88
- SUBMODULE FD1S3DX
- INSTANCE FF_89
- SUBMODULE FD1S3DX
- INSTANCE FF_90
- SUBMODULE FD1S3DX
- INSTANCE FF_91
- SUBMODULE FD1S3DX
- INSTANCE FF_92
- SUBMODULE FD1S3DX
- INSTANCE FF_93
- SUBMODULE FD1S3DX
- INSTANCE FF_94
- SUBMODULE FD1S3DX
- INSTANCE FF_95
- SUBMODULE FD1S3DX
- INSTANCE FF_96
- SUBMODULE FD1S3DX
- INSTANCE FF_97
- SUBMODULE FD1S3DX
- INSTANCE FF_98
- SUBMODULE FD1S3DX
- INSTANCE FF_99
- SUBMODULE FD1S3DX
- INSTANCE FF_100
- SUBMODULE FD1S3DX
- INSTANCE FF_101
- SUBMODULE FD1S3DX
- INSTANCE FF_102
- SUBMODULE FD1S3DX
- INSTANCE FF_103
- SUBMODULE FD1S3DX
- INSTANCE FF_104
- SUBMODULE FD1S3DX
- INSTANCE FF_105
- SUBMODULE FD1S3DX
- INSTANCE FF_106
- SUBMODULE FD1S3DX
- INSTANCE FF_107
- SUBMODULE FD1S3DX
- INSTANCE FF_108
- SUBMODULE FD1S3DX
- INSTANCE FF_109
- SUBMODULE FD1S3DX
- INSTANCE FF_110
- SUBMODULE FD1S3DX
- INSTANCE FF_111
- SUBMODULE FD1S3DX
- INSTANCE FF_112
- SUBMODULE FD1S3DX
- INSTANCE FF_113
- SUBMODULE FD1S3DX
- INSTANCE FF_114
- SUBMODULE FD1S3DX
- INSTANCE FF_115
- SUBMODULE FD1S3DX
- INSTANCE FF_116
- SUBMODULE FD1S3DX
- INSTANCE FF_117
- SUBMODULE FD1S3DX
- INSTANCE FF_118
- SUBMODULE FD1S3DX
- INSTANCE FF_119
- SUBMODULE FD1S3DX
- INSTANCE FF_120
- SUBMODULE FD1S3DX
- INSTANCE FF_121
- SUBMODULE FD1S3DX
- INSTANCE FF_122
- SUBMODULE FD1S3DX
- INSTANCE FF_123
- SUBMODULE FD1S3DX
- INSTANCE FF_124
- SUBMODULE FD1S3DX
- INSTANCE FF_125
- SUBMODULE FD1S3DX
- INSTANCE FF_126
- SUBMODULE FD1S3DX
- INSTANCE FF_127
- SUBMODULE FD1S3DX
- INSTANCE FF_128
- SUBMODULE FD1S3DX
- INSTANCE FF_129
- SUBMODULE FD1S3DX
- INSTANCE FF_130
- SUBMODULE FD1S3DX
- INSTANCE FF_131
- SUBMODULE FD1S3DX
- INSTANCE FF_132
- SUBMODULE FD1S3DX
- INSTANCE FF_133
- SUBMODULE FD1S3DX
- INSTANCE FF_134
- SUBMODULE FD1S3DX
- INSTANCE FF_135
- SUBMODULE FD1P3DX
- INSTANCE FF_136
- SUBMODULE FD1P3DX
- INSTANCE FF_137
- SUBMODULE FD1P3DX
- INSTANCE FF_138
- SUBMODULE FD1P3DX
- INSTANCE FF_139
- SUBMODULE FD1P3DX
- INSTANCE FF_140
- SUBMODULE FD1P3DX
- INSTANCE FF_141
- SUBMODULE FD1P3DX
- INSTANCE FF_142
- SUBMODULE FD1P3DX
- INSTANCE FF_143
- SUBMODULE FD1P3DX
- INSTANCE FF_144
- SUBMODULE FD1P3DX
- INSTANCE FF_145
- SUBMODULE FD1P3DX
- INSTANCE FF_146
- SUBMODULE FD1P3DX
- INSTANCE FF_147
- SUBMODULE FD1P3DX
- INSTANCE FF_148
- SUBMODULE FD1P3DX
- INSTANCE FF_149
- SUBMODULE FD1P3DX
- INSTANCE FF_150
- SUBMODULE FD1P3DX
- INSTANCE FF_151
- SUBMODULE FD1P3DX
- INSTANCE FF_152
- SUBMODULE FD1P3DX
- INSTANCE FF_153
- SUBMODULE FD1P3DX
- INSTANCE FF_154
- SUBMODULE FD1P3DX
- INSTANCE FF_155
- SUBMODULE FD1P3DX
- INSTANCE FF_156
- SUBMODULE FD1P3DX
- INSTANCE FF_157
- SUBMODULE FD1P3DX
- INSTANCE FF_158
- SUBMODULE FD1P3DX
- INSTANCE FF_159
- SUBMODULE FD1P3DX
- INSTANCE FF_160
- SUBMODULE FD1P3DX
- INSTANCE FF_161
- SUBMODULE FD1P3DX
- INSTANCE FF_162
- SUBMODULE FD1P3DX
- INSTANCE FF_163
- SUBMODULE FD1P3DX
- INSTANCE FF_164
- SUBMODULE FD1P3DX
- INSTANCE FF_165
- SUBMODULE FD1P3DX
- INSTANCE FF_166
- SUBMODULE FD1P3DX
- INSTANCE FF_167
- SUBMODULE FD1P3DX
- INSTANCE FF_168
- SUBMODULE FD1P3DX
- INSTANCE FF_169
- SUBMODULE FD1P3DX
- INSTANCE FF_170
- SUBMODULE FD1P3DX
- INSTANCE FF_171
- SUBMODULE FD1P3DX
- INSTANCE FF_172
- SUBMODULE FD1P3DX
- INSTANCE FF_173
- SUBMODULE FD1P3DX
- INSTANCE FF_174
- SUBMODULE FD1P3DX
- INSTANCE FF_175
- SUBMODULE FD1P3DX
- INSTANCE FF_176
- SUBMODULE FD1P3DX
- INSTANCE FF_177
- SUBMODULE FD1P3DX
- INSTANCE FF_178
- SUBMODULE FD1P3DX
- INSTANCE FF_179
- SUBMODULE FD1P3DX
- INSTANCE FF_180
- SUBMODULE FD1P3DX
- INSTANCE FF_181
- SUBMODULE FD1P3DX
- INSTANCE FF_182
- SUBMODULE FD1P3DX
- INSTANCE FF_183
- SUBMODULE FD1P3DX
- INSTANCE FF_184
- SUBMODULE FD1P3DX
- INSTANCE FF_185
- SUBMODULE FD1P3DX
- INSTANCE FF_186
- SUBMODULE FD1P3DX
- INSTANCE FF_187
- SUBMODULE FD1P3BX
- INSTANCE FF_188
- SUBMODULE FD1P3DX
- INSTANCE FF_189
- SUBMODULE FD1P3DX
- INSTANCE FF_190
- SUBMODULE FD1P3DX
- INSTANCE FF_191
- SUBMODULE FD1P3DX
- INSTANCE FF_192
- SUBMODULE FD1P3DX
- INSTANCE FF_193
- SUBMODULE FD1P3DX
- INSTANCE FF_194
- SUBMODULE FD1P3DX
- INSTANCE FF_195
- SUBMODULE FD1P3DX
- INSTANCE FF_196
- SUBMODULE FD1P3DX
- INSTANCE FF_197
- SUBMODULE FD1P3DX
- INSTANCE FF_198
- SUBMODULE FD1P3DX
- INSTANCE FF_199
- SUBMODULE FD1P3DX
- INSTANCE FF_200
- SUBMODULE FD1P3DX
- INSTANCE FF_201
- SUBMODULE FD1P3DX
- INSTANCE FF_202
- SUBMODULE FD1P3DX
- INSTANCE FF_203
- SUBMODULE FD1P3DX
- INSTANCE FF_204
- SUBMODULE FD1P3DX
- INSTANCE FF_205
- SUBMODULE FD1P3DX
- INSTANCE FF_206
- SUBMODULE FD1P3DX
- INSTANCE FF_207
- SUBMODULE FD1P3DX
- INSTANCE FF_208
- SUBMODULE FD1P3DX
- INSTANCE FF_209
- SUBMODULE FD1P3DX
- INSTANCE FF_210
- SUBMODULE FD1P3DX
- INSTANCE FF_211
- SUBMODULE FD1P3DX
- INSTANCE FF_212
- SUBMODULE FD1P3DX
- INSTANCE FF_213
- SUBMODULE FD1P3DX
- INSTANCE FF_214
- SUBMODULE FD1P3DX
- INSTANCE FF_215
- SUBMODULE FD1P3DX
- INSTANCE FF_216
- SUBMODULE FD1P3DX
- INSTANCE FF_217
- SUBMODULE FD1P3DX
- INSTANCE FF_218
- SUBMODULE FD1P3DX
- INSTANCE FF_219
- SUBMODULE FD1P3DX
- INSTANCE FF_220
- SUBMODULE FD1P3DX
- INSTANCE FF_221
- SUBMODULE FD1P3DX
- INSTANCE FF_222
- SUBMODULE FD1P3DX
- INSTANCE FF_223
- SUBMODULE FD1P3DX
- INSTANCE FF_224
- SUBMODULE FD1P3DX
- INSTANCE FF_225
- SUBMODULE FD1P3DX
- INSTANCE FF_226
- SUBMODULE FD1P3DX
- INSTANCE FF_227
- SUBMODULE FD1P3DX
- INSTANCE FF_228
- SUBMODULE FD1P3DX
- INSTANCE FF_229
- SUBMODULE FD1P3DX
- INSTANCE FF_230
- SUBMODULE FD1P3DX
- INSTANCE FF_231
- SUBMODULE FD1P3DX
- INSTANCE FF_232
- SUBMODULE FD1P3DX
- INSTANCE FF_233
- SUBMODULE FD1P3DX
- INSTANCE FF_234
- SUBMODULE FD1P3DX
- INSTANCE FF_235
- SUBMODULE FD1P3BX
- INSTANCE FF_236
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_7_0
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_6_1
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_5_2
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_4_3
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_3_4
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_2_5
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_1_6
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_0_7
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_7_8
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_6_9
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_5_10
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_4_11
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_3_12
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_2_13
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_1_14
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_0_15
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_7_16
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_6_17
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_5_18
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_4_19
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_3_20
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_2_21
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_1_22
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_0_23
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_7_24
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_6_25
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_5_26
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_4_27
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_3_28
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_2_29
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_1_30
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_0_31
- SUBMODULE AND2
- INSTANCE AND2_t0
- SUBMODULE AND2
- INSTANCE AND2_t1
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE ROM16X1A
- INSTANCE LUT4_24
- SUBMODULE ROM16X1A
- INSTANCE LUT4_25
- SUBMODULE ROM16X1A
- INSTANCE LUT4_26
- SUBMODULE ROM16X1A
- INSTANCE LUT4_27
- SUBMODULE ROM16X1A
- INSTANCE LUT4_28
- SUBMODULE ROM16X1A
- INSTANCE LUT4_29
- SUBMODULE ROM16X1A
- INSTANCE LUT4_30
- SUBMODULE ROM16X1A
- INSTANCE LUT4_31
- SUBMODULE ROM16X1A
- INSTANCE LUT4_32
- SUBMODULE ROM16X1A
- INSTANCE LUT4_33
- SUBMODULE ROM16X1A
- INSTANCE LUT4_34
- SUBMODULE ROM16X1A
- INSTANCE LUT4_35
- SUBMODULE ROM16X1A
- INSTANCE LUT4_36
- SUBMODULE ROM16X1A
- INSTANCE LUT4_37
- SUBMODULE ROM16X1A
- INSTANCE LUT4_38
- SUBMODULE ROM16X1A
- INSTANCE LUT4_39
- SUBMODULE ROM16X1A
- INSTANCE LUT4_40
- SUBMODULE ROM16X1A
- INSTANCE LUT4_41
- SUBMODULE ROM16X1A
- INSTANCE LUT4_42
- SUBMODULE ROM16X1A
- INSTANCE LUT4_43
- SUBMODULE ROM16X1A
- INSTANCE LUT4_44
- SUBMODULE ROM16X1A
- INSTANCE LUT4_45
- SUBMODULE ROM16X1A
- INSTANCE LUT4_46
- SUBMODULE ROM16X1A
- INSTANCE LUT4_47
- SUBMODULE ROM16X1A
- INSTANCE LUT4_48
- SUBMODULE ROM16X1A
- INSTANCE LUT4_49
- SUBMODULE ROM16X1A
- INSTANCE LUT4_50
- SUBMODULE ROM16X1A
- INSTANCE LUT4_51
- SUBMODULE ROM16X1A
- INSTANCE LUT4_52
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE XOR2
- INSTANCE XOR2_t18
- SUBMODULE XOR2
- INSTANCE XOR2_t19
- SUBMODULE XOR2
- INSTANCE XOR2_t20
- SUBMODULE XOR2
- INSTANCE XOR2_t21
- SUBMODULE XOR2
- INSTANCE XOR2_t22
- SUBMODULE XOR2
- INSTANCE XOR2_t23
- SUBMODULE XOR2
- INSTANCE XOR2_t24
- SUBMODULE XOR2
- INSTANCE XOR2_t25
- SUBMODULE XOR2
- INSTANCE XOR2_t26
- SUBMODULE XOR2
- INSTANCE XOR2_t27
- SUBMODULE XOR2
- INSTANCE XOR2_t28
- SUBMODULE XOR2
- INSTANCE XOR2_t29
- SUBMODULE XOR2
- INSTANCE XOR2_t30
- SUBMODULE XOR2
- INSTANCE XOR2_t31
- SUBMODULE XOR2
- INSTANCE XOR2_t32
- SUBMODULE XOR2
- INSTANCE XOR2_t33
- SUBMODULE XOR2
- INSTANCE XOR2_t34
- SUBMODULE XOR2
- INSTANCE XOR2_t35
- SUBMODULE XOR2
- INSTANCE XOR2_t36
- SUBMODULE OR2
- INSTANCE OR2_t37
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t38
- SUBMODULE INV
- INSTANCE INV_2
- SUBMODULE AND2
- INSTANCE AND2_t39
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_32kx16x8_mb
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:22:35
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=32768
-Width=16
-RDepth=65536
-RWidth=8
-regout=0
-CtrlByRdEn=0
-EmpFlg=1
-PeMode=Dynamic - Single Threshold
-PeAssert=16
-PeDeassert=12
-FullFlg=1
-PfMode=Dynamic - Single Threshold
-PfAssert=32752
-PfDeassert=506
-RDataCount=1
-WDataCount=1
-EnECC=0
+++ /dev/null
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-AmEmptyThresh[15] i
-AmEmptyThresh[14] i
-AmEmptyThresh[13] i
-AmEmptyThresh[12] i
-AmEmptyThresh[11] i
-AmEmptyThresh[10] i
-AmEmptyThresh[9] i
-AmEmptyThresh[8] i
-AmEmptyThresh[7] i
-AmEmptyThresh[6] i
-AmEmptyThresh[5] i
-AmEmptyThresh[4] i
-AmEmptyThresh[3] i
-AmEmptyThresh[2] i
-AmEmptyThresh[1] i
-AmEmptyThresh[0] i
-AmFullThresh[14] i
-AmFullThresh[13] i
-AmFullThresh[12] i
-AmFullThresh[11] i
-AmFullThresh[10] i
-AmFullThresh[9] i
-AmFullThresh[8] i
-AmFullThresh[7] i
-AmFullThresh[6] i
-AmFullThresh[5] i
-AmFullThresh[4] i
-AmFullThresh[3] i
-AmFullThresh[2] i
-AmFullThresh[1] i
-AmFullThresh[0] i
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-WCNT[15] o
-WCNT[14] o
-WCNT[13] o
-WCNT[12] o
-WCNT[11] o
-WCNT[10] o
-WCNT[9] o
-WCNT[8] o
-WCNT[7] o
-WCNT[6] o
-WCNT[5] o
-WCNT[4] o
-WCNT[3] o
-WCNT[2] o
-WCNT[1] o
-WCNT[0] o
-RCNT[16] o
-RCNT[15] o
-RCNT[14] o
-RCNT[13] o
-RCNT[12] o
-RCNT[11] o
-RCNT[10] o
-RCNT[9] o
-RCNT[8] o
-RCNT[7] o
-RCNT[6] o
-RCNT[5] o
-RCNT[4] o
-RCNT[3] o
-RCNT[2] o
-RCNT[1] o
-RCNT[0] o
-Empty o
-Full o
-AlmostEmpty o
-AlmostFull o
+++ /dev/null
-fifo_32kx16x8_mb.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:22:35 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 16 -num_words 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e
- Circuit name : fifo_32kx16x8_mb
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]
- Outputs : Q[7:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_32kx16x8_mb.vhd
- VHDL template : fifo_32kx16x8_mb_tmpl.vhd
- VHDL testbench : tb_fifo_32kx16x8_mb_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_32kx16x8_mb.srp
- Element Usage :
- AGEB2 : 34
- AND2 : 4
- CU2 : 17
- FADD2B : 12
- FSUB2B : 36
- FD1P3BX : 2
- FD1P3DX : 99
- FD1S3BX : 2
- FD1S3DX : 134
- INV : 3
- MUX41 : 8
- OR2 : 1
- ROM16X1A : 53
- XOR2 : 35
- DP16KC : 32
- Estimated Resource Usage:
- LUT : 299
- EBR : 32
- Reg : 237
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e
-
--- Thu Sep 22 11:22:35 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_32kx16x8_mb is
- port (
- Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(7 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end fifo_32kx16x8_mb;
-
-architecture Structure of fifo_32kx16x8_mb is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal rcount_w0: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal rcnt_reg_15_inv: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal wptr_15: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_16: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal rcnt_reg_16: std_logic;
- signal empty_i: std_logic;
- signal full_i: std_logic;
- signal rRst: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co7: std_logic;
- signal wcount_15: std_logic;
- signal co6: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal wcnt_sub_0: std_logic;
- signal wcnt_sub_1: std_logic;
- signal wcnt_sub_2: std_logic;
- signal co0_2: std_logic;
- signal wcnt_sub_3: std_logic;
- signal wcnt_sub_4: std_logic;
- signal co1_2: std_logic;
- signal wcnt_sub_5: std_logic;
- signal wcnt_sub_6: std_logic;
- signal co2_2: std_logic;
- signal wcnt_sub_7: std_logic;
- signal wcnt_sub_8: std_logic;
- signal co3_2: std_logic;
- signal wcnt_sub_9: std_logic;
- signal wcnt_sub_10: std_logic;
- signal co4_2: std_logic;
- signal wcnt_sub_11: std_logic;
- signal wcnt_sub_12: std_logic;
- signal co5_2: std_logic;
- signal wcnt_sub_13: std_logic;
- signal wcnt_sub_14: std_logic;
- signal co6_2: std_logic;
- signal wcnt_sub_15: std_logic;
- signal co7_2: std_logic;
- signal wcnt_sub_msb: std_logic;
- signal rcnt_sub_0: std_logic;
- signal rcnt_sub_1: std_logic;
- signal rcnt_sub_2: std_logic;
- signal co0_3: std_logic;
- signal rcnt_sub_3: std_logic;
- signal rcnt_sub_4: std_logic;
- signal co1_3: std_logic;
- signal rcnt_sub_5: std_logic;
- signal rcnt_sub_6: std_logic;
- signal co2_3: std_logic;
- signal rcnt_sub_7: std_logic;
- signal rcnt_sub_8: std_logic;
- signal co3_3: std_logic;
- signal rcnt_sub_9: std_logic;
- signal rcnt_sub_10: std_logic;
- signal co4_3: std_logic;
- signal rcnt_sub_11: std_logic;
- signal rcnt_sub_12: std_logic;
- signal co5_3: std_logic;
- signal rcnt_sub_13: std_logic;
- signal rcnt_sub_14: std_logic;
- signal co6_3: std_logic;
- signal rcnt_sub_15: std_logic;
- signal rcnt_sub_16: std_logic;
- signal co7_3: std_logic;
- signal rcnt_sub_msb: std_logic;
- signal co8_1d: std_logic;
- signal co8_1: std_logic;
- signal wfill_sub_0: std_logic;
- signal wptr_0: std_logic;
- signal wfill_sub_1: std_logic;
- signal wfill_sub_2: std_logic;
- signal co0_4: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wfill_sub_3: std_logic;
- signal wfill_sub_4: std_logic;
- signal co1_4: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wfill_sub_5: std_logic;
- signal wfill_sub_6: std_logic;
- signal co2_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wfill_sub_7: std_logic;
- signal wfill_sub_8: std_logic;
- signal co3_4: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wfill_sub_9: std_logic;
- signal wfill_sub_10: std_logic;
- signal co4_4: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wfill_sub_11: std_logic;
- signal wfill_sub_12: std_logic;
- signal co5_4: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wfill_sub_13: std_logic;
- signal wfill_sub_14: std_logic;
- signal co6_4: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wfill_sub_15: std_logic;
- signal co7_4: std_logic;
- signal wfill_sub_msb: std_logic;
- signal rfill_sub_0: std_logic;
- signal rptr_0: std_logic;
- signal scuba_vhi: std_logic;
- signal rfill_sub_1: std_logic;
- signal rfill_sub_2: std_logic;
- signal co0_5: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rfill_sub_3: std_logic;
- signal rfill_sub_4: std_logic;
- signal co1_5: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rfill_sub_5: std_logic;
- signal rfill_sub_6: std_logic;
- signal co2_5: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rfill_sub_7: std_logic;
- signal rfill_sub_8: std_logic;
- signal co3_5: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rfill_sub_9: std_logic;
- signal rfill_sub_10: std_logic;
- signal co4_5: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rfill_sub_11: std_logic;
- signal rfill_sub_12: std_logic;
- signal co5_5: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rfill_sub_13: std_logic;
- signal rfill_sub_14: std_logic;
- signal co6_5: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rfill_sub_15: std_logic;
- signal rfill_sub_16: std_logic;
- signal co7_5: std_logic;
- signal rptr_15: std_logic;
- signal rfill_sub_msb: std_logic;
- signal co8_2d: std_logic;
- signal co8_2: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_6: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_6: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_6: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_6: std_logic;
- signal wcount_r7: std_logic;
- signal wcount_r8: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_6: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_6: std_logic;
- signal wcount_r11: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_6: std_logic;
- signal wcount_r13: std_logic;
- signal wcount_r14: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_6: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_7: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_7: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_7: std_logic;
- signal rcount_w7: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_7: std_logic;
- signal rcount_w9: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_7: std_logic;
- signal rcount_w11: std_logic;
- signal rcount_w12: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w14: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_7: std_logic;
- signal rcount_w15: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_14: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal rcnt_reg_0: std_logic;
- signal rcnt_reg_1: std_logic;
- signal co0_8: std_logic;
- signal rcnt_reg_2: std_logic;
- signal rcnt_reg_3: std_logic;
- signal co1_8: std_logic;
- signal rcnt_reg_4: std_logic;
- signal rcnt_reg_5: std_logic;
- signal co2_8: std_logic;
- signal rcnt_reg_6: std_logic;
- signal rcnt_reg_7: std_logic;
- signal co3_8: std_logic;
- signal rcnt_reg_8: std_logic;
- signal rcnt_reg_9: std_logic;
- signal co4_8: std_logic;
- signal rcnt_reg_10: std_logic;
- signal rcnt_reg_11: std_logic;
- signal co5_8: std_logic;
- signal rcnt_reg_12: std_logic;
- signal rcnt_reg_13: std_logic;
- signal co6_8: std_logic;
- signal rcnt_reg_14: std_logic;
- signal rcnt_reg_15: std_logic;
- signal co7_7: std_logic;
- signal ae_clrsig: std_logic;
- signal ae_setsig: std_logic;
- signal ae_d: std_logic;
- signal ae_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_3: std_logic;
- signal wcnt_reg_0: std_logic;
- signal wcnt_reg_1: std_logic;
- signal co0_9: std_logic;
- signal wcnt_reg_2: std_logic;
- signal wcnt_reg_3: std_logic;
- signal co1_9: std_logic;
- signal wcnt_reg_4: std_logic;
- signal wcnt_reg_5: std_logic;
- signal co2_9: std_logic;
- signal wcnt_reg_6: std_logic;
- signal wcnt_reg_7: std_logic;
- signal co3_9: std_logic;
- signal wcnt_reg_8: std_logic;
- signal wcnt_reg_9: std_logic;
- signal co4_9: std_logic;
- signal wcnt_reg_10: std_logic;
- signal wcnt_reg_11: std_logic;
- signal co5_9: std_logic;
- signal wcnt_reg_12: std_logic;
- signal wcnt_reg_13: std_logic;
- signal co6_9: std_logic;
- signal wcnt_reg_14: std_logic;
- signal wcnt_reg_15: std_logic;
- signal af_d: std_logic;
- signal af_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX41
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
- Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is "";
- attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is "";
- attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is "";
- attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is "";
- attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is "";
- attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is "";
- attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is "";
- attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is "";
- attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is "";
- attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is "";
- attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is "";
- attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is "";
- attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is "";
- attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is "";
- attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is "";
- attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is "";
- attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is "";
- attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is "";
- attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is "";
- attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is "";
- attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is "";
- attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is "";
- attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is "";
- attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is "";
- attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is "";
- attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is "";
- attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is "";
- attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is "";
- attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is "";
- attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is "";
- attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is "";
- attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC";
- attribute GSR of FF_236 : label is "ENABLED";
- attribute GSR of FF_235 : label is "ENABLED";
- attribute GSR of FF_234 : label is "ENABLED";
- attribute GSR of FF_233 : label is "ENABLED";
- attribute GSR of FF_232 : label is "ENABLED";
- attribute GSR of FF_231 : label is "ENABLED";
- attribute GSR of FF_230 : label is "ENABLED";
- attribute GSR of FF_229 : label is "ENABLED";
- attribute GSR of FF_228 : label is "ENABLED";
- attribute GSR of FF_227 : label is "ENABLED";
- attribute GSR of FF_226 : label is "ENABLED";
- attribute GSR of FF_225 : label is "ENABLED";
- attribute GSR of FF_224 : label is "ENABLED";
- attribute GSR of FF_223 : label is "ENABLED";
- attribute GSR of FF_222 : label is "ENABLED";
- attribute GSR of FF_221 : label is "ENABLED";
- attribute GSR of FF_220 : label is "ENABLED";
- attribute GSR of FF_219 : label is "ENABLED";
- attribute GSR of FF_218 : label is "ENABLED";
- attribute GSR of FF_217 : label is "ENABLED";
- attribute GSR of FF_216 : label is "ENABLED";
- attribute GSR of FF_215 : label is "ENABLED";
- attribute GSR of FF_214 : label is "ENABLED";
- attribute GSR of FF_213 : label is "ENABLED";
- attribute GSR of FF_212 : label is "ENABLED";
- attribute GSR of FF_211 : label is "ENABLED";
- attribute GSR of FF_210 : label is "ENABLED";
- attribute GSR of FF_209 : label is "ENABLED";
- attribute GSR of FF_208 : label is "ENABLED";
- attribute GSR of FF_207 : label is "ENABLED";
- attribute GSR of FF_206 : label is "ENABLED";
- attribute GSR of FF_205 : label is "ENABLED";
- attribute GSR of FF_204 : label is "ENABLED";
- attribute GSR of FF_203 : label is "ENABLED";
- attribute GSR of FF_202 : label is "ENABLED";
- attribute GSR of FF_201 : label is "ENABLED";
- attribute GSR of FF_200 : label is "ENABLED";
- attribute GSR of FF_199 : label is "ENABLED";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t39: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_2: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t38: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_1: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t37: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t36: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t35: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t34: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t33: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t32: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t31: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t30: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t29: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t28: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t27: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t26: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t25: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t24: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t23: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t22: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t21: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t9: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t8: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t7: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t6: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r2);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r1);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- XOR2_t5: XOR2
- port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb);
-
- XOR2_t4: XOR2
- port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb);
-
- XOR2_t3: XOR2
- port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb);
-
- XOR2_t2: XOR2
- port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- INV_0: INV
- port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv);
-
- AND2_t1: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig);
-
- AND2_t0: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig);
-
- pdp_ram_0_0_31: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_30: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_2_29: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_3_28: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_4_27: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_5_26: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_6_25: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_7_24: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_23: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_1_22: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_2_21: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_3_20: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_4_19: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_5_18: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_6_17: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_7_16: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_15: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_1_14: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_2_13: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_3_12: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_4_11: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_5_10: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_6_9: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_7_8: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_7: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_1_6: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_2_5: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_3_4: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_4_3: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_5_2: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_6_1: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_7_0: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_236: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_235: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_234: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_233: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_232: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_231: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_230: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_229: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_228: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_227: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_226: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_225: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_224: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_223: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_222: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_221: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_220: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_219: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_218: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_217: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_216: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_215: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_214: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_213: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_212: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_211: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_210: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_209: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_208: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_207: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_206: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_205: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_204: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_203: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_202: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_201: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_200: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_199: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_198: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_197: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_196: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_195: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_194: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_193: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_192: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_191: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_190: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_189: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_188: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_187: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_186: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_185: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_184: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_183: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_182: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_181: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_180: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_179: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_178: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_177: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_176: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_175: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_174: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_173: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_172: FD1P3DX
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_171: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_170: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_169: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_168: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_167: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_166: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_165: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_164: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_163: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_162: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_161: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_160: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_159: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_158: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_157: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_156: FD1P3DX
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_155: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_154: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_153: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_152: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_151: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_150: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_149: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_148: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_147: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_146: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_145: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_144: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_143: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_142: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_141: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_140: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_139: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_138: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_137: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_136: FD1P3DX
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_135: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_134: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_133: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_132: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_131: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_130: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_129: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_128: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_127: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_126: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_125: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_124: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_123: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_122: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_121: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_120: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_119: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_118: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_117: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_116: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_115: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_114: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_113: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_112: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_111: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_110: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_109: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_108: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_107: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_106: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_105: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_104: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_103: FD1S3DX
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_102: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_101: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_100: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_99: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_98: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_97: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_96: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_95: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_94: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_93: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_92: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_91: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_90: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_89: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_88: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_87: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_86: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_85: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_84: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_83: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_82: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_81: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_80: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_79: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_78: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_77: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_76: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_75: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_74: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_73: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_72: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_71: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_70: FD1S3DX
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_69: FD1S3DX
- port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0);
-
- FF_68: FD1S3DX
- port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1);
-
- FF_67: FD1S3DX
- port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2);
-
- FF_66: FD1S3DX
- port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3);
-
- FF_65: FD1S3DX
- port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4);
-
- FF_64: FD1S3DX
- port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5);
-
- FF_63: FD1S3DX
- port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6);
-
- FF_62: FD1S3DX
- port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7);
-
- FF_61: FD1S3DX
- port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8);
-
- FF_60: FD1S3DX
- port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9);
-
- FF_59: FD1S3DX
- port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10);
-
- FF_58: FD1S3DX
- port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11);
-
- FF_57: FD1S3DX
- port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12);
-
- FF_56: FD1S3DX
- port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13);
-
- FF_55: FD1S3DX
- port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14);
-
- FF_54: FD1S3DX
- port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15);
-
- FF_53: FD1S3DX
- port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0);
-
- FF_52: FD1S3DX
- port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1);
-
- FF_51: FD1S3DX
- port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2);
-
- FF_50: FD1S3DX
- port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3);
-
- FF_49: FD1S3DX
- port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4);
-
- FF_48: FD1S3DX
- port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5);
-
- FF_47: FD1S3DX
- port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6);
-
- FF_46: FD1S3DX
- port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7);
-
- FF_45: FD1S3DX
- port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8);
-
- FF_44: FD1S3DX
- port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9);
-
- FF_43: FD1S3DX
- port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10);
-
- FF_42: FD1S3DX
- port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11);
-
- FF_41: FD1S3DX
- port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12);
-
- FF_40: FD1S3DX
- port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13);
-
- FF_39: FD1S3DX
- port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14);
-
- FF_38: FD1S3DX
- port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15);
-
- FF_37: FD1S3DX
- port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16);
-
- FF_36: FD1S3DX
- port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
-
- FF_35: FD1S3DX
- port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
-
- FF_34: FD1S3DX
- port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
-
- FF_33: FD1S3DX
- port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
-
- FF_32: FD1S3DX
- port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
-
- FF_31: FD1S3DX
- port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
-
- FF_30: FD1S3DX
- port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
-
- FF_29: FD1S3DX
- port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
-
- FF_28: FD1S3DX
- port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
-
- FF_27: FD1S3DX
- port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
-
- FF_26: FD1S3DX
- port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
-
- FF_25: FD1S3DX
- port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
-
- FF_24: FD1S3DX
- port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12));
-
- FF_23: FD1S3DX
- port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13));
-
- FF_22: FD1S3DX
- port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14));
-
- FF_21: FD1S3DX
- port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15));
-
- FF_20: FD1S3DX
- port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
-
- FF_19: FD1S3DX
- port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
-
- FF_18: FD1S3DX
- port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
-
- FF_17: FD1S3DX
- port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
-
- FF_16: FD1S3DX
- port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
-
- FF_15: FD1S3DX
- port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
-
- FF_14: FD1S3DX
- port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
-
- FF_13: FD1S3DX
- port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
-
- FF_12: FD1S3DX
- port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
-
- FF_11: FD1S3DX
- port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
-
- FF_10: FD1S3DX
- port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10));
-
- FF_9: FD1S3DX
- port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11));
-
- FF_8: FD1S3DX
- port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12));
-
- FF_7: FD1S3DX
- port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13));
-
- FF_6: FD1S3DX
- port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14));
-
- FF_5: FD1S3DX
- port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15));
-
- FF_4: FD1S3DX
- port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16));
-
- FF_3: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_2: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- FF_1: FD1S3BX
- port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
-
- FF_0: FD1S3DX
- port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>ircount_16, NC1=>open);
-
- mux_7: MUX41
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0));
-
- mux_6: MUX41
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1));
-
- mux_5: MUX41
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2));
-
- mux_4: MUX41
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3));
-
- mux_3: MUX41
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4));
-
- mux_2: MUX41
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5));
-
- mux_1: MUX41
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6));
-
- mux_0: MUX41
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7));
-
- wcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
- S1=>wcnt_sub_0);
-
- wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2,
- B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1,
- S1=>wcnt_sub_2);
-
- wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4,
- B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3,
- S1=>wcnt_sub_4);
-
- wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6,
- B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5,
- S1=>wcnt_sub_6);
-
- wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8,
- B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7,
- S1=>wcnt_sub_8);
-
- wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9,
- S1=>wcnt_sub_10);
-
- wcnt_6: FSUB2B
- port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2,
- S0=>wcnt_sub_11, S1=>wcnt_sub_12);
-
- wcnt_7: FSUB2B
- port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13,
- S1=>wcnt_sub_14);
-
- wcnt_8: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15,
- S1=>open);
-
- rcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open,
- S1=>rcnt_sub_0);
-
- rcnt_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1,
- B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1,
- S1=>rcnt_sub_2);
-
- rcnt_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3,
- B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3,
- S1=>rcnt_sub_4);
-
- rcnt_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5,
- B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5,
- S1=>rcnt_sub_6);
-
- rcnt_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7,
- B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7,
- S1=>rcnt_sub_8);
-
- rcnt_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9,
- B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9,
- S1=>rcnt_sub_10);
-
- rcnt_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11,
- B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11,
- S1=>rcnt_sub_12);
-
- rcnt_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13,
- B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13,
- S1=>rcnt_sub_14);
-
- rcnt_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15,
- B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15,
- S1=>rcnt_sub_16);
-
- rcntd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open);
-
- wfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open,
- S1=>wfill_sub_0);
-
- wfill_1: FSUB2B
- port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3,
- BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2);
-
- wfill_2: FSUB2B
- port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5,
- BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4);
-
- wfill_3: FSUB2B
- port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7,
- BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6);
-
- wfill_4: FSUB2B
- port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9,
- BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8);
-
- wfill_5: FSUB2B
- port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9,
- S1=>wfill_sub_10);
-
- wfill_6: FSUB2B
- port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4,
- S0=>wfill_sub_11, S1=>wfill_sub_12);
-
- wfill_7: FSUB2B
- port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13,
- S1=>wfill_sub_14);
-
- wfill_8: FSUB2B
- port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- rfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
- S1=>rfill_sub_0);
-
- rfill_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2,
- BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2);
-
- rfill_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4,
- BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4);
-
- rfill_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6,
- BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6);
-
- rfill_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8,
- BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8);
-
- rfill_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10,
- BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10);
-
- rfill_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11,
- B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11,
- S1=>rfill_sub_12);
-
- rfill_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13,
- B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13,
- S1=>rfill_sub_14);
-
- rfill_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15,
- B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15,
- S1=>rfill_sub_16);
-
- rfilld: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_6, GE=>co1_6);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_6, GE=>co2_6);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_6, GE=>co3_6);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
- B1=>wcount_r8, CI=>co3_6, GE=>co4_6);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co4_6, GE=>co5_6);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11,
- B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13,
- B1=>wcount_r14, CI=>co6_6, GE=>co7_6);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_7, GE=>co1_7);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_7, GE=>co2_7);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>rcount_w8, CI=>co2_7, GE=>co3_7);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
- B1=>rcount_w10, CI=>co3_7, GE=>co4_7);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11,
- B1=>rcount_w12, CI=>co4_7, GE=>co5_7);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w14, CI=>co5_7, GE=>co6_7);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15,
- B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- ae_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- ae_cmp_0: AGEB2
- port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
- B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8);
-
- ae_cmp_1: AGEB2
- port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
- B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8);
-
- ae_cmp_2: AGEB2
- port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
- B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8);
-
- ae_cmp_3: AGEB2
- port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
- B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8);
-
- ae_cmp_4: AGEB2
- port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9),
- B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8);
-
- ae_cmp_5: AGEB2
- port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11),
- B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8);
-
- ae_cmp_6: AGEB2
- port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13),
- B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8);
-
- ae_cmp_7: AGEB2
- port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15),
- B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7);
-
- ae_cmp_8: AGEB2
- port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig,
- B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
-
- af_d_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
-
- af_d_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
- B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9);
-
- af_d_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
- B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9);
-
- af_d_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
- B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9);
-
- af_d_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
- B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9);
-
- af_d_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
- B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9);
-
- af_d_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
- B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9);
-
- af_d_cmp_6: AGEB2
- port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
- B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9);
-
- af_d_cmp_7: AGEB2
- port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14),
- B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_32kx16x8_mb is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX41 use entity ecp3.MUX41(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_32kx16x8_mb2" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:22:56.365" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_32kx16x8_mb2.lpc" type="lpc" modified="2011 09 22 11:22:54.000"/>
- <File name="fifo_32kx16x8_mb2.vhd" type="top_level_vhdl" modified="2011 09 22 11:22:54.000"/>
- <File name="fifo_32kx16x8_mb2_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:22:54.000"/>
- <File name="tb_fifo_32kx16x8_mb2_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:22:54.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_32kx16x8_mb2 DEFIN fifo_32kx16x8_mb2.vhd
- SUBMODULE FADD2B
- INSTANCE a3
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_7
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_6
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_5
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_4
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_3
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_2
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_1
- SUBMODULE AGEB2
- INSTANCE af_d_cmp_0
- SUBMODULE FADD2B
- INSTANCE af_d_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a2
- SUBMODULE AGEB2
- INSTANCE ae_cmp_8
- SUBMODULE AGEB2
- INSTANCE ae_cmp_7
- SUBMODULE AGEB2
- INSTANCE ae_cmp_6
- SUBMODULE AGEB2
- INSTANCE ae_cmp_5
- SUBMODULE AGEB2
- INSTANCE ae_cmp_4
- SUBMODULE AGEB2
- INSTANCE ae_cmp_3
- SUBMODULE AGEB2
- INSTANCE ae_cmp_2
- SUBMODULE AGEB2
- INSTANCE ae_cmp_1
- SUBMODULE AGEB2
- INSTANCE ae_cmp_0
- SUBMODULE FADD2B
- INSTANCE ae_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE AGEB2
- INSTANCE full_cmp_7
- SUBMODULE AGEB2
- INSTANCE full_cmp_6
- SUBMODULE AGEB2
- INSTANCE full_cmp_5
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_8
- SUBMODULE AGEB2
- INSTANCE empty_cmp_7
- SUBMODULE AGEB2
- INSTANCE empty_cmp_6
- SUBMODULE AGEB2
- INSTANCE empty_cmp_5
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE rfilld
- SUBMODULE FSUB2B
- INSTANCE rfill_8
- SUBMODULE FSUB2B
- INSTANCE rfill_7
- SUBMODULE FSUB2B
- INSTANCE rfill_6
- SUBMODULE FSUB2B
- INSTANCE rfill_5
- SUBMODULE FSUB2B
- INSTANCE rfill_4
- SUBMODULE FSUB2B
- INSTANCE rfill_3
- SUBMODULE FSUB2B
- INSTANCE rfill_2
- SUBMODULE FSUB2B
- INSTANCE rfill_1
- SUBMODULE FSUB2B
- INSTANCE rfill_0
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE FSUB2B
- INSTANCE wfill_8
- SUBMODULE FSUB2B
- INSTANCE wfill_7
- SUBMODULE FSUB2B
- INSTANCE wfill_6
- SUBMODULE FSUB2B
- INSTANCE wfill_5
- SUBMODULE FSUB2B
- INSTANCE wfill_4
- SUBMODULE FSUB2B
- INSTANCE wfill_3
- SUBMODULE FSUB2B
- INSTANCE wfill_2
- SUBMODULE FSUB2B
- INSTANCE wfill_1
- SUBMODULE FSUB2B
- INSTANCE wfill_0
- SUBMODULE FADD2B
- INSTANCE rcntd
- SUBMODULE FSUB2B
- INSTANCE rcnt_8
- SUBMODULE FSUB2B
- INSTANCE rcnt_7
- SUBMODULE FSUB2B
- INSTANCE rcnt_6
- SUBMODULE FSUB2B
- INSTANCE rcnt_5
- SUBMODULE FSUB2B
- INSTANCE rcnt_4
- SUBMODULE FSUB2B
- INSTANCE rcnt_3
- SUBMODULE FSUB2B
- INSTANCE rcnt_2
- SUBMODULE FSUB2B
- INSTANCE rcnt_1
- SUBMODULE FSUB2B
- INSTANCE rcnt_0
- SUBMODULE FSUB2B
- INSTANCE wcnt_8
- SUBMODULE FSUB2B
- INSTANCE wcnt_7
- SUBMODULE FSUB2B
- INSTANCE wcnt_6
- SUBMODULE FSUB2B
- INSTANCE wcnt_5
- SUBMODULE FSUB2B
- INSTANCE wcnt_4
- SUBMODULE FSUB2B
- INSTANCE wcnt_3
- SUBMODULE FSUB2B
- INSTANCE wcnt_2
- SUBMODULE FSUB2B
- INSTANCE wcnt_1
- SUBMODULE FSUB2B
- INSTANCE wcnt_0
- SUBMODULE MUX321
- INSTANCE mux_0
- SUBMODULE MUX321
- INSTANCE mux_1
- SUBMODULE MUX321
- INSTANCE mux_2
- SUBMODULE MUX321
- INSTANCE mux_3
- SUBMODULE MUX321
- INSTANCE mux_4
- SUBMODULE MUX321
- INSTANCE mux_5
- SUBMODULE MUX321
- INSTANCE mux_6
- SUBMODULE MUX321
- INSTANCE mux_7
- SUBMODULE MUX321
- INSTANCE mux_8
- SUBMODULE CU2
- INSTANCE r_gctr_8
- SUBMODULE CU2
- INSTANCE r_gctr_7
- SUBMODULE CU2
- INSTANCE r_gctr_6
- SUBMODULE CU2
- INSTANCE r_gctr_5
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE CU2
- INSTANCE w_gctr_7
- SUBMODULE CU2
- INSTANCE w_gctr_6
- SUBMODULE CU2
- INSTANCE w_gctr_5
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3BX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1S3DX
- INSTANCE FF_42
- SUBMODULE FD1S3DX
- INSTANCE FF_43
- SUBMODULE FD1S3DX
- INSTANCE FF_44
- SUBMODULE FD1S3DX
- INSTANCE FF_45
- SUBMODULE FD1S3DX
- INSTANCE FF_46
- SUBMODULE FD1S3DX
- INSTANCE FF_47
- SUBMODULE FD1S3DX
- INSTANCE FF_48
- SUBMODULE FD1S3DX
- INSTANCE FF_49
- SUBMODULE FD1S3DX
- INSTANCE FF_50
- SUBMODULE FD1S3DX
- INSTANCE FF_51
- SUBMODULE FD1S3DX
- INSTANCE FF_52
- SUBMODULE FD1S3DX
- INSTANCE FF_53
- SUBMODULE FD1S3DX
- INSTANCE FF_54
- SUBMODULE FD1S3DX
- INSTANCE FF_55
- SUBMODULE FD1S3DX
- INSTANCE FF_56
- SUBMODULE FD1S3DX
- INSTANCE FF_57
- SUBMODULE FD1S3DX
- INSTANCE FF_58
- SUBMODULE FD1S3DX
- INSTANCE FF_59
- SUBMODULE FD1S3DX
- INSTANCE FF_60
- SUBMODULE FD1S3DX
- INSTANCE FF_61
- SUBMODULE FD1S3DX
- INSTANCE FF_62
- SUBMODULE FD1S3DX
- INSTANCE FF_63
- SUBMODULE FD1S3DX
- INSTANCE FF_64
- SUBMODULE FD1S3DX
- INSTANCE FF_65
- SUBMODULE FD1S3DX
- INSTANCE FF_66
- SUBMODULE FD1S3DX
- INSTANCE FF_67
- SUBMODULE FD1S3DX
- INSTANCE FF_68
- SUBMODULE FD1S3DX
- INSTANCE FF_69
- SUBMODULE FD1S3DX
- INSTANCE FF_70
- SUBMODULE FD1S3DX
- INSTANCE FF_71
- SUBMODULE FD1S3DX
- INSTANCE FF_72
- SUBMODULE FD1S3DX
- INSTANCE FF_73
- SUBMODULE FD1S3DX
- INSTANCE FF_74
- SUBMODULE FD1S3DX
- INSTANCE FF_75
- SUBMODULE FD1S3DX
- INSTANCE FF_76
- SUBMODULE FD1S3DX
- INSTANCE FF_77
- SUBMODULE FD1S3DX
- INSTANCE FF_78
- SUBMODULE FD1S3DX
- INSTANCE FF_79
- SUBMODULE FD1S3DX
- INSTANCE FF_80
- SUBMODULE FD1S3DX
- INSTANCE FF_81
- SUBMODULE FD1S3DX
- INSTANCE FF_82
- SUBMODULE FD1S3DX
- INSTANCE FF_83
- SUBMODULE FD1S3DX
- INSTANCE FF_84
- SUBMODULE FD1S3DX
- INSTANCE FF_85
- SUBMODULE FD1S3DX
- INSTANCE FF_86
- SUBMODULE FD1S3DX
- INSTANCE FF_87
- SUBMODULE FD1S3DX
- INSTANCE FF_88
- SUBMODULE FD1S3DX
- INSTANCE FF_89
- SUBMODULE FD1S3DX
- INSTANCE FF_90
- SUBMODULE FD1S3DX
- INSTANCE FF_91
- SUBMODULE FD1S3DX
- INSTANCE FF_92
- SUBMODULE FD1S3DX
- INSTANCE FF_93
- SUBMODULE FD1S3DX
- INSTANCE FF_94
- SUBMODULE FD1S3DX
- INSTANCE FF_95
- SUBMODULE FD1S3DX
- INSTANCE FF_96
- SUBMODULE FD1S3DX
- INSTANCE FF_97
- SUBMODULE FD1S3DX
- INSTANCE FF_98
- SUBMODULE FD1S3DX
- INSTANCE FF_99
- SUBMODULE FD1S3DX
- INSTANCE FF_100
- SUBMODULE FD1S3DX
- INSTANCE FF_101
- SUBMODULE FD1S3DX
- INSTANCE FF_102
- SUBMODULE FD1S3DX
- INSTANCE FF_103
- SUBMODULE FD1S3DX
- INSTANCE FF_104
- SUBMODULE FD1S3DX
- INSTANCE FF_105
- SUBMODULE FD1S3DX
- INSTANCE FF_106
- SUBMODULE FD1S3DX
- INSTANCE FF_107
- SUBMODULE FD1S3DX
- INSTANCE FF_108
- SUBMODULE FD1S3DX
- INSTANCE FF_109
- SUBMODULE FD1S3DX
- INSTANCE FF_110
- SUBMODULE FD1S3DX
- INSTANCE FF_111
- SUBMODULE FD1S3DX
- INSTANCE FF_112
- SUBMODULE FD1S3DX
- INSTANCE FF_113
- SUBMODULE FD1S3DX
- INSTANCE FF_114
- SUBMODULE FD1S3DX
- INSTANCE FF_115
- SUBMODULE FD1S3DX
- INSTANCE FF_116
- SUBMODULE FD1S3DX
- INSTANCE FF_117
- SUBMODULE FD1S3DX
- INSTANCE FF_118
- SUBMODULE FD1S3DX
- INSTANCE FF_119
- SUBMODULE FD1S3DX
- INSTANCE FF_120
- SUBMODULE FD1S3DX
- INSTANCE FF_121
- SUBMODULE FD1S3DX
- INSTANCE FF_122
- SUBMODULE FD1S3DX
- INSTANCE FF_123
- SUBMODULE FD1S3DX
- INSTANCE FF_124
- SUBMODULE FD1S3DX
- INSTANCE FF_125
- SUBMODULE FD1S3DX
- INSTANCE FF_126
- SUBMODULE FD1S3DX
- INSTANCE FF_127
- SUBMODULE FD1S3DX
- INSTANCE FF_128
- SUBMODULE FD1S3DX
- INSTANCE FF_129
- SUBMODULE FD1S3DX
- INSTANCE FF_130
- SUBMODULE FD1S3DX
- INSTANCE FF_131
- SUBMODULE FD1S3DX
- INSTANCE FF_132
- SUBMODULE FD1S3DX
- INSTANCE FF_133
- SUBMODULE FD1S3DX
- INSTANCE FF_134
- SUBMODULE FD1S3DX
- INSTANCE FF_135
- SUBMODULE FD1P3DX
- INSTANCE FF_136
- SUBMODULE FD1P3DX
- INSTANCE FF_137
- SUBMODULE FD1P3DX
- INSTANCE FF_138
- SUBMODULE FD1P3DX
- INSTANCE FF_139
- SUBMODULE FD1P3DX
- INSTANCE FF_140
- SUBMODULE FD1P3DX
- INSTANCE FF_141
- SUBMODULE FD1P3DX
- INSTANCE FF_142
- SUBMODULE FD1P3DX
- INSTANCE FF_143
- SUBMODULE FD1P3DX
- INSTANCE FF_144
- SUBMODULE FD1P3DX
- INSTANCE FF_145
- SUBMODULE FD1P3DX
- INSTANCE FF_146
- SUBMODULE FD1P3DX
- INSTANCE FF_147
- SUBMODULE FD1P3DX
- INSTANCE FF_148
- SUBMODULE FD1P3DX
- INSTANCE FF_149
- SUBMODULE FD1P3DX
- INSTANCE FF_150
- SUBMODULE FD1P3DX
- INSTANCE FF_151
- SUBMODULE FD1P3DX
- INSTANCE FF_152
- SUBMODULE FD1P3DX
- INSTANCE FF_153
- SUBMODULE FD1P3DX
- INSTANCE FF_154
- SUBMODULE FD1P3DX
- INSTANCE FF_155
- SUBMODULE FD1P3DX
- INSTANCE FF_156
- SUBMODULE FD1P3DX
- INSTANCE FF_157
- SUBMODULE FD1P3DX
- INSTANCE FF_158
- SUBMODULE FD1P3DX
- INSTANCE FF_159
- SUBMODULE FD1P3DX
- INSTANCE FF_160
- SUBMODULE FD1P3DX
- INSTANCE FF_161
- SUBMODULE FD1P3DX
- INSTANCE FF_162
- SUBMODULE FD1P3DX
- INSTANCE FF_163
- SUBMODULE FD1P3DX
- INSTANCE FF_164
- SUBMODULE FD1P3DX
- INSTANCE FF_165
- SUBMODULE FD1P3DX
- INSTANCE FF_166
- SUBMODULE FD1P3DX
- INSTANCE FF_167
- SUBMODULE FD1P3DX
- INSTANCE FF_168
- SUBMODULE FD1P3DX
- INSTANCE FF_169
- SUBMODULE FD1P3DX
- INSTANCE FF_170
- SUBMODULE FD1P3DX
- INSTANCE FF_171
- SUBMODULE FD1P3DX
- INSTANCE FF_172
- SUBMODULE FD1P3DX
- INSTANCE FF_173
- SUBMODULE FD1P3DX
- INSTANCE FF_174
- SUBMODULE FD1P3DX
- INSTANCE FF_175
- SUBMODULE FD1P3DX
- INSTANCE FF_176
- SUBMODULE FD1P3DX
- INSTANCE FF_177
- SUBMODULE FD1P3DX
- INSTANCE FF_178
- SUBMODULE FD1P3DX
- INSTANCE FF_179
- SUBMODULE FD1P3DX
- INSTANCE FF_180
- SUBMODULE FD1P3DX
- INSTANCE FF_181
- SUBMODULE FD1P3DX
- INSTANCE FF_182
- SUBMODULE FD1P3DX
- INSTANCE FF_183
- SUBMODULE FD1P3DX
- INSTANCE FF_184
- SUBMODULE FD1P3DX
- INSTANCE FF_185
- SUBMODULE FD1P3DX
- INSTANCE FF_186
- SUBMODULE FD1P3DX
- INSTANCE FF_187
- SUBMODULE FD1P3DX
- INSTANCE FF_188
- SUBMODULE FD1P3DX
- INSTANCE FF_189
- SUBMODULE FD1P3DX
- INSTANCE FF_190
- SUBMODULE FD1P3BX
- INSTANCE FF_191
- SUBMODULE FD1P3DX
- INSTANCE FF_192
- SUBMODULE FD1P3DX
- INSTANCE FF_193
- SUBMODULE FD1P3DX
- INSTANCE FF_194
- SUBMODULE FD1P3DX
- INSTANCE FF_195
- SUBMODULE FD1P3DX
- INSTANCE FF_196
- SUBMODULE FD1P3DX
- INSTANCE FF_197
- SUBMODULE FD1P3DX
- INSTANCE FF_198
- SUBMODULE FD1P3DX
- INSTANCE FF_199
- SUBMODULE FD1P3DX
- INSTANCE FF_200
- SUBMODULE FD1P3DX
- INSTANCE FF_201
- SUBMODULE FD1P3DX
- INSTANCE FF_202
- SUBMODULE FD1P3DX
- INSTANCE FF_203
- SUBMODULE FD1P3DX
- INSTANCE FF_204
- SUBMODULE FD1P3DX
- INSTANCE FF_205
- SUBMODULE FD1P3DX
- INSTANCE FF_206
- SUBMODULE FD1P3DX
- INSTANCE FF_207
- SUBMODULE FD1P3DX
- INSTANCE FF_208
- SUBMODULE FD1P3DX
- INSTANCE FF_209
- SUBMODULE FD1P3DX
- INSTANCE FF_210
- SUBMODULE FD1P3DX
- INSTANCE FF_211
- SUBMODULE FD1P3DX
- INSTANCE FF_212
- SUBMODULE FD1P3DX
- INSTANCE FF_213
- SUBMODULE FD1P3DX
- INSTANCE FF_214
- SUBMODULE FD1P3DX
- INSTANCE FF_215
- SUBMODULE FD1P3DX
- INSTANCE FF_216
- SUBMODULE FD1P3DX
- INSTANCE FF_217
- SUBMODULE FD1P3DX
- INSTANCE FF_218
- SUBMODULE FD1P3DX
- INSTANCE FF_219
- SUBMODULE FD1P3DX
- INSTANCE FF_220
- SUBMODULE FD1P3DX
- INSTANCE FF_221
- SUBMODULE FD1P3DX
- INSTANCE FF_222
- SUBMODULE FD1P3DX
- INSTANCE FF_223
- SUBMODULE FD1P3DX
- INSTANCE FF_224
- SUBMODULE FD1P3DX
- INSTANCE FF_225
- SUBMODULE FD1P3DX
- INSTANCE FF_226
- SUBMODULE FD1P3DX
- INSTANCE FF_227
- SUBMODULE FD1P3DX
- INSTANCE FF_228
- SUBMODULE FD1P3DX
- INSTANCE FF_229
- SUBMODULE FD1P3DX
- INSTANCE FF_230
- SUBMODULE FD1P3DX
- INSTANCE FF_231
- SUBMODULE FD1P3DX
- INSTANCE FF_232
- SUBMODULE FD1P3DX
- INSTANCE FF_233
- SUBMODULE FD1P3DX
- INSTANCE FF_234
- SUBMODULE FD1P3DX
- INSTANCE FF_235
- SUBMODULE FD1P3DX
- INSTANCE FF_236
- SUBMODULE FD1P3DX
- INSTANCE FF_237
- SUBMODULE FD1P3DX
- INSTANCE FF_238
- SUBMODULE FD1P3BX
- INSTANCE FF_239
- SUBMODULE DP16KC
- INSTANCE pdp_ram_31_0_0
- SUBMODULE DP16KC
- INSTANCE pdp_ram_30_0_1
- SUBMODULE DP16KC
- INSTANCE pdp_ram_29_0_2
- SUBMODULE DP16KC
- INSTANCE pdp_ram_28_0_3
- SUBMODULE DP16KC
- INSTANCE pdp_ram_27_0_4
- SUBMODULE DP16KC
- INSTANCE pdp_ram_26_0_5
- SUBMODULE DP16KC
- INSTANCE pdp_ram_25_0_6
- SUBMODULE DP16KC
- INSTANCE pdp_ram_24_0_7
- SUBMODULE DP16KC
- INSTANCE pdp_ram_23_0_8
- SUBMODULE DP16KC
- INSTANCE pdp_ram_22_0_9
- SUBMODULE DP16KC
- INSTANCE pdp_ram_21_0_10
- SUBMODULE DP16KC
- INSTANCE pdp_ram_20_0_11
- SUBMODULE DP16KC
- INSTANCE pdp_ram_19_0_12
- SUBMODULE DP16KC
- INSTANCE pdp_ram_18_0_13
- SUBMODULE DP16KC
- INSTANCE pdp_ram_17_0_14
- SUBMODULE DP16KC
- INSTANCE pdp_ram_16_0_15
- SUBMODULE DP16KC
- INSTANCE pdp_ram_15_0_16
- SUBMODULE DP16KC
- INSTANCE pdp_ram_14_0_17
- SUBMODULE DP16KC
- INSTANCE pdp_ram_13_0_18
- SUBMODULE DP16KC
- INSTANCE pdp_ram_12_0_19
- SUBMODULE DP16KC
- INSTANCE pdp_ram_11_0_20
- SUBMODULE DP16KC
- INSTANCE pdp_ram_10_0_21
- SUBMODULE DP16KC
- INSTANCE pdp_ram_9_0_22
- SUBMODULE DP16KC
- INSTANCE pdp_ram_8_0_23
- SUBMODULE DP16KC
- INSTANCE pdp_ram_7_0_24
- SUBMODULE DP16KC
- INSTANCE pdp_ram_6_0_25
- SUBMODULE DP16KC
- INSTANCE pdp_ram_5_0_26
- SUBMODULE DP16KC
- INSTANCE pdp_ram_4_0_27
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_0_28
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_0_29
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_0_30
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_0_31
- SUBMODULE AND2
- INSTANCE AND2_t0
- SUBMODULE AND2
- INSTANCE AND2_t1
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE ROM16X1A
- INSTANCE LUT4_24
- SUBMODULE ROM16X1A
- INSTANCE LUT4_25
- SUBMODULE ROM16X1A
- INSTANCE LUT4_26
- SUBMODULE ROM16X1A
- INSTANCE LUT4_27
- SUBMODULE ROM16X1A
- INSTANCE LUT4_28
- SUBMODULE ROM16X1A
- INSTANCE LUT4_29
- SUBMODULE ROM16X1A
- INSTANCE LUT4_30
- SUBMODULE ROM16X1A
- INSTANCE LUT4_31
- SUBMODULE ROM16X1A
- INSTANCE LUT4_32
- SUBMODULE ROM16X1A
- INSTANCE LUT4_33
- SUBMODULE ROM16X1A
- INSTANCE LUT4_34
- SUBMODULE ROM16X1A
- INSTANCE LUT4_35
- SUBMODULE ROM16X1A
- INSTANCE LUT4_36
- SUBMODULE ROM16X1A
- INSTANCE LUT4_37
- SUBMODULE ROM16X1A
- INSTANCE LUT4_38
- SUBMODULE ROM16X1A
- INSTANCE LUT4_39
- SUBMODULE ROM16X1A
- INSTANCE LUT4_40
- SUBMODULE ROM16X1A
- INSTANCE LUT4_41
- SUBMODULE ROM16X1A
- INSTANCE LUT4_42
- SUBMODULE ROM16X1A
- INSTANCE LUT4_43
- SUBMODULE ROM16X1A
- INSTANCE LUT4_44
- SUBMODULE ROM16X1A
- INSTANCE LUT4_45
- SUBMODULE ROM16X1A
- INSTANCE LUT4_46
- SUBMODULE ROM16X1A
- INSTANCE LUT4_47
- SUBMODULE ROM16X1A
- INSTANCE LUT4_48
- SUBMODULE ROM16X1A
- INSTANCE LUT4_49
- SUBMODULE ROM16X1A
- INSTANCE LUT4_50
- SUBMODULE ROM16X1A
- INSTANCE LUT4_51
- SUBMODULE ROM16X1A
- INSTANCE LUT4_52
- SUBMODULE ROM16X1A
- INSTANCE LUT4_53
- SUBMODULE ROM16X1A
- INSTANCE LUT4_54
- SUBMODULE ROM16X1A
- INSTANCE LUT4_55
- SUBMODULE ROM16X1A
- INSTANCE LUT4_56
- SUBMODULE ROM16X1A
- INSTANCE LUT4_57
- SUBMODULE ROM16X1A
- INSTANCE LUT4_58
- SUBMODULE ROM16X1A
- INSTANCE LUT4_59
- SUBMODULE ROM16X1A
- INSTANCE LUT4_60
- SUBMODULE ROM16X1A
- INSTANCE LUT4_61
- SUBMODULE ROM16X1A
- INSTANCE LUT4_62
- SUBMODULE ROM16X1A
- INSTANCE LUT4_63
- SUBMODULE ROM16X1A
- INSTANCE LUT4_64
- SUBMODULE ROM16X1A
- INSTANCE LUT4_65
- SUBMODULE ROM16X1A
- INSTANCE LUT4_66
- SUBMODULE ROM16X1A
- INSTANCE LUT4_67
- SUBMODULE ROM16X1A
- INSTANCE LUT4_68
- SUBMODULE ROM16X1A
- INSTANCE LUT4_69
- SUBMODULE ROM16X1A
- INSTANCE LUT4_70
- SUBMODULE ROM16X1A
- INSTANCE LUT4_71
- SUBMODULE ROM16X1A
- INSTANCE LUT4_72
- SUBMODULE ROM16X1A
- INSTANCE LUT4_73
- SUBMODULE ROM16X1A
- INSTANCE LUT4_74
- SUBMODULE ROM16X1A
- INSTANCE LUT4_75
- SUBMODULE ROM16X1A
- INSTANCE LUT4_76
- SUBMODULE ROM16X1A
- INSTANCE LUT4_77
- SUBMODULE ROM16X1A
- INSTANCE LUT4_78
- SUBMODULE ROM16X1A
- INSTANCE LUT4_79
- SUBMODULE ROM16X1A
- INSTANCE LUT4_80
- SUBMODULE ROM16X1A
- INSTANCE LUT4_81
- SUBMODULE ROM16X1A
- INSTANCE LUT4_82
- SUBMODULE ROM16X1A
- INSTANCE LUT4_83
- SUBMODULE ROM16X1A
- INSTANCE LUT4_84
- SUBMODULE ROM16X1A
- INSTANCE LUT4_85
- SUBMODULE ROM16X1A
- INSTANCE LUT4_86
- SUBMODULE ROM16X1A
- INSTANCE LUT4_87
- SUBMODULE ROM16X1A
- INSTANCE LUT4_88
- SUBMODULE ROM16X1A
- INSTANCE LUT4_89
- SUBMODULE ROM16X1A
- INSTANCE LUT4_90
- SUBMODULE ROM16X1A
- INSTANCE LUT4_91
- SUBMODULE ROM16X1A
- INSTANCE LUT4_92
- SUBMODULE ROM16X1A
- INSTANCE LUT4_93
- SUBMODULE ROM16X1A
- INSTANCE LUT4_94
- SUBMODULE ROM16X1A
- INSTANCE LUT4_95
- SUBMODULE ROM16X1A
- INSTANCE LUT4_96
- SUBMODULE ROM16X1A
- INSTANCE LUT4_97
- SUBMODULE ROM16X1A
- INSTANCE LUT4_98
- SUBMODULE ROM16X1A
- INSTANCE LUT4_99
- SUBMODULE ROM16X1A
- INSTANCE LUT4_100
- SUBMODULE ROM16X1A
- INSTANCE LUT4_101
- SUBMODULE ROM16X1A
- INSTANCE LUT4_102
- SUBMODULE ROM16X1A
- INSTANCE LUT4_103
- SUBMODULE ROM16X1A
- INSTANCE LUT4_104
- SUBMODULE ROM16X1A
- INSTANCE LUT4_105
- SUBMODULE ROM16X1A
- INSTANCE LUT4_106
- SUBMODULE ROM16X1A
- INSTANCE LUT4_107
- SUBMODULE ROM16X1A
- INSTANCE LUT4_108
- SUBMODULE ROM16X1A
- INSTANCE LUT4_109
- SUBMODULE ROM16X1A
- INSTANCE LUT4_110
- SUBMODULE ROM16X1A
- INSTANCE LUT4_111
- SUBMODULE ROM16X1A
- INSTANCE LUT4_112
- SUBMODULE ROM16X1A
- INSTANCE LUT4_113
- SUBMODULE ROM16X1A
- INSTANCE LUT4_114
- SUBMODULE ROM16X1A
- INSTANCE LUT4_115
- SUBMODULE ROM16X1A
- INSTANCE LUT4_116
- SUBMODULE ROM16X1A
- INSTANCE LUT4_117
- SUBMODULE ROM16X1A
- INSTANCE LUT4_118
- SUBMODULE ROM16X1A
- INSTANCE LUT4_119
- SUBMODULE ROM16X1A
- INSTANCE LUT4_120
- SUBMODULE ROM16X1A
- INSTANCE LUT4_121
- SUBMODULE ROM16X1A
- INSTANCE LUT4_122
- SUBMODULE ROM16X1A
- INSTANCE LUT4_123
- SUBMODULE ROM16X1A
- INSTANCE LUT4_124
- SUBMODULE ROM16X1A
- INSTANCE LUT4_125
- SUBMODULE ROM16X1A
- INSTANCE LUT4_126
- SUBMODULE ROM16X1A
- INSTANCE LUT4_127
- SUBMODULE ROM16X1A
- INSTANCE LUT4_128
- SUBMODULE ROM16X1A
- INSTANCE LUT4_129
- SUBMODULE ROM16X1A
- INSTANCE LUT4_130
- SUBMODULE ROM16X1A
- INSTANCE LUT4_131
- SUBMODULE ROM16X1A
- INSTANCE LUT4_132
- SUBMODULE ROM16X1A
- INSTANCE LUT4_133
- SUBMODULE ROM16X1A
- INSTANCE LUT4_134
- SUBMODULE ROM16X1A
- INSTANCE LUT4_135
- SUBMODULE ROM16X1A
- INSTANCE LUT4_136
- SUBMODULE ROM16X1A
- INSTANCE LUT4_137
- SUBMODULE ROM16X1A
- INSTANCE LUT4_138
- SUBMODULE ROM16X1A
- INSTANCE LUT4_139
- SUBMODULE ROM16X1A
- INSTANCE LUT4_140
- SUBMODULE ROM16X1A
- INSTANCE LUT4_141
- SUBMODULE ROM16X1A
- INSTANCE LUT4_142
- SUBMODULE ROM16X1A
- INSTANCE LUT4_143
- SUBMODULE ROM16X1A
- INSTANCE LUT4_144
- SUBMODULE ROM16X1A
- INSTANCE LUT4_145
- SUBMODULE ROM16X1A
- INSTANCE LUT4_146
- SUBMODULE ROM16X1A
- INSTANCE LUT4_147
- SUBMODULE ROM16X1A
- INSTANCE LUT4_148
- SUBMODULE ROM16X1A
- INSTANCE LUT4_149
- SUBMODULE ROM16X1A
- INSTANCE LUT4_150
- SUBMODULE ROM16X1A
- INSTANCE LUT4_151
- SUBMODULE ROM16X1A
- INSTANCE LUT4_152
- SUBMODULE ROM16X1A
- INSTANCE LUT4_153
- SUBMODULE ROM16X1A
- INSTANCE LUT4_154
- SUBMODULE ROM16X1A
- INSTANCE LUT4_155
- SUBMODULE ROM16X1A
- INSTANCE LUT4_156
- SUBMODULE ROM16X1A
- INSTANCE LUT4_157
- SUBMODULE ROM16X1A
- INSTANCE LUT4_158
- SUBMODULE ROM16X1A
- INSTANCE LUT4_159
- SUBMODULE ROM16X1A
- INSTANCE LUT4_160
- SUBMODULE ROM16X1A
- INSTANCE LUT4_161
- SUBMODULE ROM16X1A
- INSTANCE LUT4_162
- SUBMODULE ROM16X1A
- INSTANCE LUT4_163
- SUBMODULE ROM16X1A
- INSTANCE LUT4_164
- SUBMODULE ROM16X1A
- INSTANCE LUT4_165
- SUBMODULE ROM16X1A
- INSTANCE LUT4_166
- SUBMODULE ROM16X1A
- INSTANCE LUT4_167
- SUBMODULE ROM16X1A
- INSTANCE LUT4_168
- SUBMODULE ROM16X1A
- INSTANCE LUT4_169
- SUBMODULE ROM16X1A
- INSTANCE LUT4_170
- SUBMODULE ROM16X1A
- INSTANCE LUT4_171
- SUBMODULE ROM16X1A
- INSTANCE LUT4_172
- SUBMODULE ROM16X1A
- INSTANCE LUT4_173
- SUBMODULE ROM16X1A
- INSTANCE LUT4_174
- SUBMODULE ROM16X1A
- INSTANCE LUT4_175
- SUBMODULE ROM16X1A
- INSTANCE LUT4_176
- SUBMODULE ROM16X1A
- INSTANCE LUT4_177
- SUBMODULE ROM16X1A
- INSTANCE LUT4_178
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE INV
- INSTANCE INV_2
- SUBMODULE INV
- INSTANCE INV_3
- SUBMODULE INV
- INSTANCE INV_4
- SUBMODULE INV
- INSTANCE INV_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_179
- SUBMODULE ROM16X1A
- INSTANCE LUT4_180
- SUBMODULE INV
- INSTANCE INV_6
- SUBMODULE INV
- INSTANCE INV_7
- SUBMODULE INV
- INSTANCE INV_8
- SUBMODULE INV
- INSTANCE INV_9
- SUBMODULE INV
- INSTANCE INV_10
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE XOR2
- INSTANCE XOR2_t18
- SUBMODULE XOR2
- INSTANCE XOR2_t19
- SUBMODULE XOR2
- INSTANCE XOR2_t20
- SUBMODULE XOR2
- INSTANCE XOR2_t21
- SUBMODULE XOR2
- INSTANCE XOR2_t22
- SUBMODULE XOR2
- INSTANCE XOR2_t23
- SUBMODULE XOR2
- INSTANCE XOR2_t24
- SUBMODULE XOR2
- INSTANCE XOR2_t25
- SUBMODULE XOR2
- INSTANCE XOR2_t26
- SUBMODULE XOR2
- INSTANCE XOR2_t27
- SUBMODULE XOR2
- INSTANCE XOR2_t28
- SUBMODULE XOR2
- INSTANCE XOR2_t29
- SUBMODULE XOR2
- INSTANCE XOR2_t30
- SUBMODULE XOR2
- INSTANCE XOR2_t31
- SUBMODULE XOR2
- INSTANCE XOR2_t32
- SUBMODULE XOR2
- INSTANCE XOR2_t33
- SUBMODULE XOR2
- INSTANCE XOR2_t34
- SUBMODULE XOR2
- INSTANCE XOR2_t35
- SUBMODULE XOR2
- INSTANCE XOR2_t36
- SUBMODULE OR2
- INSTANCE OR2_t37
- SUBMODULE INV
- INSTANCE INV_11
- SUBMODULE AND2
- INSTANCE AND2_t38
- SUBMODULE INV
- INSTANCE INV_12
- SUBMODULE AND2
- INSTANCE AND2_t39
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_32kx16x8_mb2
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:22:54
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=32768
-Width=18
-RDepth=65536
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=1
-PeMode=Dynamic - Single Threshold
-PeAssert=16
-PeDeassert=12
-FullFlg=1
-PfMode=Dynamic - Single Threshold
-PfAssert=32752
-PfDeassert=506
-RDataCount=1
-WDataCount=1
-EnECC=0
+++ /dev/null
-Data[17] i
-Data[16] i
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-AmEmptyThresh[15] i
-AmEmptyThresh[14] i
-AmEmptyThresh[13] i
-AmEmptyThresh[12] i
-AmEmptyThresh[11] i
-AmEmptyThresh[10] i
-AmEmptyThresh[9] i
-AmEmptyThresh[8] i
-AmEmptyThresh[7] i
-AmEmptyThresh[6] i
-AmEmptyThresh[5] i
-AmEmptyThresh[4] i
-AmEmptyThresh[3] i
-AmEmptyThresh[2] i
-AmEmptyThresh[1] i
-AmEmptyThresh[0] i
-AmFullThresh[14] i
-AmFullThresh[13] i
-AmFullThresh[12] i
-AmFullThresh[11] i
-AmFullThresh[10] i
-AmFullThresh[9] i
-AmFullThresh[8] i
-AmFullThresh[7] i
-AmFullThresh[6] i
-AmFullThresh[5] i
-AmFullThresh[4] i
-AmFullThresh[3] i
-AmFullThresh[2] i
-AmFullThresh[1] i
-AmFullThresh[0] i
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-WCNT[15] o
-WCNT[14] o
-WCNT[13] o
-WCNT[12] o
-WCNT[11] o
-WCNT[10] o
-WCNT[9] o
-WCNT[8] o
-WCNT[7] o
-WCNT[6] o
-WCNT[5] o
-WCNT[4] o
-WCNT[3] o
-WCNT[2] o
-WCNT[1] o
-WCNT[0] o
-RCNT[16] o
-RCNT[15] o
-RCNT[14] o
-RCNT[13] o
-RCNT[12] o
-RCNT[11] o
-RCNT[10] o
-RCNT[9] o
-RCNT[8] o
-RCNT[7] o
-RCNT[6] o
-RCNT[5] o
-RCNT[4] o
-RCNT[3] o
-RCNT[2] o
-RCNT[1] o
-RCNT[0] o
-Empty o
-Full o
-AlmostEmpty o
-AlmostFull o
+++ /dev/null
-fifo_32kx16x8_mb2.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:22:54 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e
- Circuit name : fifo_32kx16x8_mb2
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]
- Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_32kx16x8_mb2.vhd
- VHDL template : fifo_32kx16x8_mb2_tmpl.vhd
- VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_32kx16x8_mb2.srp
- Element Usage :
- AGEB2 : 34
- AND2 : 4
- CU2 : 17
- FADD2B : 12
- FSUB2B : 36
- FD1P3BX : 2
- FD1P3DX : 102
- FD1S3BX : 2
- FD1S3DX : 134
- INV : 13
- MUX321 : 9
- OR2 : 1
- ROM16X1A : 181
- XOR2 : 35
- DP16KC : 32
- Estimated Resource Usage:
- LUT : 491
- EBR : 32
- Reg : 240
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e
-
--- Thu Sep 22 11:22:54 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_32kx16x8_mb2 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(8 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end fifo_32kx16x8_mb2;
-
-architecture Structure of fifo_32kx16x8_mb2 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal func_and_inet: std_logic;
- signal func_and_inet_1: std_logic;
- signal func_and_inet_2: std_logic;
- signal func_and_inet_3: std_logic;
- signal func_and_inet_4: std_logic;
- signal func_and_inet_5: std_logic;
- signal func_and_inet_6: std_logic;
- signal func_and_inet_7: std_logic;
- signal func_and_inet_8: std_logic;
- signal func_and_inet_9: std_logic;
- signal func_and_inet_10: std_logic;
- signal func_and_inet_11: std_logic;
- signal func_and_inet_12: std_logic;
- signal func_and_inet_13: std_logic;
- signal func_and_inet_14: std_logic;
- signal func_and_inet_15: std_logic;
- signal func_and_inet_16: std_logic;
- signal func_and_inet_17: std_logic;
- signal func_and_inet_18: std_logic;
- signal func_and_inet_19: std_logic;
- signal func_and_inet_20: std_logic;
- signal func_and_inet_21: std_logic;
- signal func_and_inet_22: std_logic;
- signal func_and_inet_23: std_logic;
- signal func_and_inet_24: std_logic;
- signal func_and_inet_25: std_logic;
- signal func_and_inet_26: std_logic;
- signal func_and_inet_27: std_logic;
- signal func_and_inet_28: std_logic;
- signal func_and_inet_29: std_logic;
- signal wptr_14_inv: std_logic;
- signal func_and_inet_30: std_logic;
- signal rptr_15_inv: std_logic;
- signal func_and_inet_31: std_logic;
- signal func_and_inet_32: std_logic;
- signal func_and_inet_33: std_logic;
- signal func_and_inet_34: std_logic;
- signal func_and_inet_35: std_logic;
- signal func_and_inet_36: std_logic;
- signal func_and_inet_37: std_logic;
- signal func_and_inet_38: std_logic;
- signal func_and_inet_39: std_logic;
- signal func_and_inet_40: std_logic;
- signal func_and_inet_41: std_logic;
- signal func_and_inet_42: std_logic;
- signal func_and_inet_43: std_logic;
- signal func_and_inet_44: std_logic;
- signal func_and_inet_45: std_logic;
- signal wptr_13_inv: std_logic;
- signal func_and_inet_46: std_logic;
- signal rptr_14_inv: std_logic;
- signal func_and_inet_47: std_logic;
- signal func_and_inet_48: std_logic;
- signal func_and_inet_49: std_logic;
- signal func_and_inet_50: std_logic;
- signal func_and_inet_51: std_logic;
- signal func_and_inet_52: std_logic;
- signal func_and_inet_53: std_logic;
- signal wptr_12_inv: std_logic;
- signal func_and_inet_54: std_logic;
- signal rptr_13_inv: std_logic;
- signal func_and_inet_55: std_logic;
- signal func_and_inet_56: std_logic;
- signal func_and_inet_57: std_logic;
- signal wptr_11_inv: std_logic;
- signal func_and_inet_58: std_logic;
- signal rptr_12_inv: std_logic;
- signal func_and_inet_59: std_logic;
- signal wptr_10_inv: std_logic;
- signal func_and_inet_60: std_logic;
- signal rptr_11_inv: std_logic;
- signal func_and_inet_61: std_logic;
- signal func_and_inet_62: std_logic;
- signal func_and_inet_63: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal rcount_w0: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal rcnt_reg_15_inv: std_logic;
- signal dec1_r10: std_logic;
- signal dec0_p00: std_logic;
- signal dec3_r11: std_logic;
- signal dec2_p01: std_logic;
- signal dec5_r12: std_logic;
- signal dec4_p02: std_logic;
- signal dec7_r13: std_logic;
- signal dec6_p03: std_logic;
- signal dec9_r14: std_logic;
- signal dec8_p04: std_logic;
- signal dec11_r15: std_logic;
- signal dec10_p05: std_logic;
- signal dec13_r16: std_logic;
- signal dec12_p06: std_logic;
- signal dec15_r17: std_logic;
- signal dec14_p07: std_logic;
- signal dec17_r18: std_logic;
- signal dec16_p08: std_logic;
- signal dec19_r19: std_logic;
- signal dec18_p09: std_logic;
- signal dec21_r110: std_logic;
- signal dec20_p010: std_logic;
- signal dec23_r111: std_logic;
- signal dec22_p011: std_logic;
- signal dec25_r112: std_logic;
- signal dec24_p012: std_logic;
- signal dec27_r113: std_logic;
- signal dec26_p013: std_logic;
- signal dec29_r114: std_logic;
- signal dec28_p014: std_logic;
- signal dec31_r115: std_logic;
- signal dec30_p015: std_logic;
- signal dec33_r116: std_logic;
- signal dec32_p016: std_logic;
- signal dec35_r117: std_logic;
- signal dec34_p017: std_logic;
- signal dec37_r118: std_logic;
- signal dec36_p018: std_logic;
- signal dec39_r119: std_logic;
- signal dec38_p019: std_logic;
- signal dec41_r120: std_logic;
- signal dec40_p020: std_logic;
- signal dec43_r121: std_logic;
- signal dec42_p021: std_logic;
- signal dec45_r122: std_logic;
- signal dec44_p022: std_logic;
- signal dec47_r123: std_logic;
- signal dec46_p023: std_logic;
- signal dec49_r124: std_logic;
- signal dec48_p024: std_logic;
- signal dec51_r125: std_logic;
- signal dec50_p025: std_logic;
- signal dec53_r126: std_logic;
- signal dec52_p026: std_logic;
- signal dec55_r127: std_logic;
- signal dec54_p027: std_logic;
- signal dec57_r128: std_logic;
- signal dec56_p028: std_logic;
- signal dec59_r129: std_logic;
- signal dec58_p029: std_logic;
- signal dec61_r130: std_logic;
- signal dec60_p030: std_logic;
- signal dec63_r131: std_logic;
- signal dec62_p031: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal wptr_15: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_16: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal rcnt_reg_16: std_logic;
- signal empty_i: std_logic;
- signal full_i: std_logic;
- signal rRst: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co7: std_logic;
- signal wcount_15: std_logic;
- signal co6: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_31_0: std_logic;
- signal mdout1_30_0: std_logic;
- signal mdout1_29_0: std_logic;
- signal mdout1_28_0: std_logic;
- signal mdout1_27_0: std_logic;
- signal mdout1_26_0: std_logic;
- signal mdout1_25_0: std_logic;
- signal mdout1_24_0: std_logic;
- signal mdout1_23_0: std_logic;
- signal mdout1_22_0: std_logic;
- signal mdout1_21_0: std_logic;
- signal mdout1_20_0: std_logic;
- signal mdout1_19_0: std_logic;
- signal mdout1_18_0: std_logic;
- signal mdout1_17_0: std_logic;
- signal mdout1_16_0: std_logic;
- signal mdout1_15_0: std_logic;
- signal mdout1_14_0: std_logic;
- signal mdout1_13_0: std_logic;
- signal mdout1_12_0: std_logic;
- signal mdout1_11_0: std_logic;
- signal mdout1_10_0: std_logic;
- signal mdout1_9_0: std_logic;
- signal mdout1_8_0: std_logic;
- signal mdout1_7_0: std_logic;
- signal mdout1_6_0: std_logic;
- signal mdout1_5_0: std_logic;
- signal mdout1_4_0: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_31_1: std_logic;
- signal mdout1_30_1: std_logic;
- signal mdout1_29_1: std_logic;
- signal mdout1_28_1: std_logic;
- signal mdout1_27_1: std_logic;
- signal mdout1_26_1: std_logic;
- signal mdout1_25_1: std_logic;
- signal mdout1_24_1: std_logic;
- signal mdout1_23_1: std_logic;
- signal mdout1_22_1: std_logic;
- signal mdout1_21_1: std_logic;
- signal mdout1_20_1: std_logic;
- signal mdout1_19_1: std_logic;
- signal mdout1_18_1: std_logic;
- signal mdout1_17_1: std_logic;
- signal mdout1_16_1: std_logic;
- signal mdout1_15_1: std_logic;
- signal mdout1_14_1: std_logic;
- signal mdout1_13_1: std_logic;
- signal mdout1_12_1: std_logic;
- signal mdout1_11_1: std_logic;
- signal mdout1_10_1: std_logic;
- signal mdout1_9_1: std_logic;
- signal mdout1_8_1: std_logic;
- signal mdout1_7_1: std_logic;
- signal mdout1_6_1: std_logic;
- signal mdout1_5_1: std_logic;
- signal mdout1_4_1: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_31_2: std_logic;
- signal mdout1_30_2: std_logic;
- signal mdout1_29_2: std_logic;
- signal mdout1_28_2: std_logic;
- signal mdout1_27_2: std_logic;
- signal mdout1_26_2: std_logic;
- signal mdout1_25_2: std_logic;
- signal mdout1_24_2: std_logic;
- signal mdout1_23_2: std_logic;
- signal mdout1_22_2: std_logic;
- signal mdout1_21_2: std_logic;
- signal mdout1_20_2: std_logic;
- signal mdout1_19_2: std_logic;
- signal mdout1_18_2: std_logic;
- signal mdout1_17_2: std_logic;
- signal mdout1_16_2: std_logic;
- signal mdout1_15_2: std_logic;
- signal mdout1_14_2: std_logic;
- signal mdout1_13_2: std_logic;
- signal mdout1_12_2: std_logic;
- signal mdout1_11_2: std_logic;
- signal mdout1_10_2: std_logic;
- signal mdout1_9_2: std_logic;
- signal mdout1_8_2: std_logic;
- signal mdout1_7_2: std_logic;
- signal mdout1_6_2: std_logic;
- signal mdout1_5_2: std_logic;
- signal mdout1_4_2: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_31_3: std_logic;
- signal mdout1_30_3: std_logic;
- signal mdout1_29_3: std_logic;
- signal mdout1_28_3: std_logic;
- signal mdout1_27_3: std_logic;
- signal mdout1_26_3: std_logic;
- signal mdout1_25_3: std_logic;
- signal mdout1_24_3: std_logic;
- signal mdout1_23_3: std_logic;
- signal mdout1_22_3: std_logic;
- signal mdout1_21_3: std_logic;
- signal mdout1_20_3: std_logic;
- signal mdout1_19_3: std_logic;
- signal mdout1_18_3: std_logic;
- signal mdout1_17_3: std_logic;
- signal mdout1_16_3: std_logic;
- signal mdout1_15_3: std_logic;
- signal mdout1_14_3: std_logic;
- signal mdout1_13_3: std_logic;
- signal mdout1_12_3: std_logic;
- signal mdout1_11_3: std_logic;
- signal mdout1_10_3: std_logic;
- signal mdout1_9_3: std_logic;
- signal mdout1_8_3: std_logic;
- signal mdout1_7_3: std_logic;
- signal mdout1_6_3: std_logic;
- signal mdout1_5_3: std_logic;
- signal mdout1_4_3: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_31_4: std_logic;
- signal mdout1_30_4: std_logic;
- signal mdout1_29_4: std_logic;
- signal mdout1_28_4: std_logic;
- signal mdout1_27_4: std_logic;
- signal mdout1_26_4: std_logic;
- signal mdout1_25_4: std_logic;
- signal mdout1_24_4: std_logic;
- signal mdout1_23_4: std_logic;
- signal mdout1_22_4: std_logic;
- signal mdout1_21_4: std_logic;
- signal mdout1_20_4: std_logic;
- signal mdout1_19_4: std_logic;
- signal mdout1_18_4: std_logic;
- signal mdout1_17_4: std_logic;
- signal mdout1_16_4: std_logic;
- signal mdout1_15_4: std_logic;
- signal mdout1_14_4: std_logic;
- signal mdout1_13_4: std_logic;
- signal mdout1_12_4: std_logic;
- signal mdout1_11_4: std_logic;
- signal mdout1_10_4: std_logic;
- signal mdout1_9_4: std_logic;
- signal mdout1_8_4: std_logic;
- signal mdout1_7_4: std_logic;
- signal mdout1_6_4: std_logic;
- signal mdout1_5_4: std_logic;
- signal mdout1_4_4: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_31_5: std_logic;
- signal mdout1_30_5: std_logic;
- signal mdout1_29_5: std_logic;
- signal mdout1_28_5: std_logic;
- signal mdout1_27_5: std_logic;
- signal mdout1_26_5: std_logic;
- signal mdout1_25_5: std_logic;
- signal mdout1_24_5: std_logic;
- signal mdout1_23_5: std_logic;
- signal mdout1_22_5: std_logic;
- signal mdout1_21_5: std_logic;
- signal mdout1_20_5: std_logic;
- signal mdout1_19_5: std_logic;
- signal mdout1_18_5: std_logic;
- signal mdout1_17_5: std_logic;
- signal mdout1_16_5: std_logic;
- signal mdout1_15_5: std_logic;
- signal mdout1_14_5: std_logic;
- signal mdout1_13_5: std_logic;
- signal mdout1_12_5: std_logic;
- signal mdout1_11_5: std_logic;
- signal mdout1_10_5: std_logic;
- signal mdout1_9_5: std_logic;
- signal mdout1_8_5: std_logic;
- signal mdout1_7_5: std_logic;
- signal mdout1_6_5: std_logic;
- signal mdout1_5_5: std_logic;
- signal mdout1_4_5: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_31_6: std_logic;
- signal mdout1_30_6: std_logic;
- signal mdout1_29_6: std_logic;
- signal mdout1_28_6: std_logic;
- signal mdout1_27_6: std_logic;
- signal mdout1_26_6: std_logic;
- signal mdout1_25_6: std_logic;
- signal mdout1_24_6: std_logic;
- signal mdout1_23_6: std_logic;
- signal mdout1_22_6: std_logic;
- signal mdout1_21_6: std_logic;
- signal mdout1_20_6: std_logic;
- signal mdout1_19_6: std_logic;
- signal mdout1_18_6: std_logic;
- signal mdout1_17_6: std_logic;
- signal mdout1_16_6: std_logic;
- signal mdout1_15_6: std_logic;
- signal mdout1_14_6: std_logic;
- signal mdout1_13_6: std_logic;
- signal mdout1_12_6: std_logic;
- signal mdout1_11_6: std_logic;
- signal mdout1_10_6: std_logic;
- signal mdout1_9_6: std_logic;
- signal mdout1_8_6: std_logic;
- signal mdout1_7_6: std_logic;
- signal mdout1_6_6: std_logic;
- signal mdout1_5_6: std_logic;
- signal mdout1_4_6: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_31_7: std_logic;
- signal mdout1_30_7: std_logic;
- signal mdout1_29_7: std_logic;
- signal mdout1_28_7: std_logic;
- signal mdout1_27_7: std_logic;
- signal mdout1_26_7: std_logic;
- signal mdout1_25_7: std_logic;
- signal mdout1_24_7: std_logic;
- signal mdout1_23_7: std_logic;
- signal mdout1_22_7: std_logic;
- signal mdout1_21_7: std_logic;
- signal mdout1_20_7: std_logic;
- signal mdout1_19_7: std_logic;
- signal mdout1_18_7: std_logic;
- signal mdout1_17_7: std_logic;
- signal mdout1_16_7: std_logic;
- signal mdout1_15_7: std_logic;
- signal mdout1_14_7: std_logic;
- signal mdout1_13_7: std_logic;
- signal mdout1_12_7: std_logic;
- signal mdout1_11_7: std_logic;
- signal mdout1_10_7: std_logic;
- signal mdout1_9_7: std_logic;
- signal mdout1_8_7: std_logic;
- signal mdout1_7_7: std_logic;
- signal mdout1_6_7: std_logic;
- signal mdout1_5_7: std_logic;
- signal mdout1_4_7: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal rptr_13_ff: std_logic;
- signal rptr_12_ff: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_31_8: std_logic;
- signal mdout1_30_8: std_logic;
- signal mdout1_29_8: std_logic;
- signal mdout1_28_8: std_logic;
- signal mdout1_27_8: std_logic;
- signal mdout1_26_8: std_logic;
- signal mdout1_25_8: std_logic;
- signal mdout1_24_8: std_logic;
- signal mdout1_23_8: std_logic;
- signal mdout1_22_8: std_logic;
- signal mdout1_21_8: std_logic;
- signal mdout1_20_8: std_logic;
- signal mdout1_19_8: std_logic;
- signal mdout1_18_8: std_logic;
- signal mdout1_17_8: std_logic;
- signal mdout1_16_8: std_logic;
- signal mdout1_15_8: std_logic;
- signal mdout1_14_8: std_logic;
- signal mdout1_13_8: std_logic;
- signal mdout1_12_8: std_logic;
- signal mdout1_11_8: std_logic;
- signal mdout1_10_8: std_logic;
- signal mdout1_9_8: std_logic;
- signal mdout1_8_8: std_logic;
- signal mdout1_7_8: std_logic;
- signal mdout1_6_8: std_logic;
- signal mdout1_5_8: std_logic;
- signal mdout1_4_8: std_logic;
- signal mdout1_3_8: std_logic;
- signal mdout1_2_8: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal wcnt_sub_0: std_logic;
- signal wcnt_sub_1: std_logic;
- signal wcnt_sub_2: std_logic;
- signal co0_2: std_logic;
- signal wcnt_sub_3: std_logic;
- signal wcnt_sub_4: std_logic;
- signal co1_2: std_logic;
- signal wcnt_sub_5: std_logic;
- signal wcnt_sub_6: std_logic;
- signal co2_2: std_logic;
- signal wcnt_sub_7: std_logic;
- signal wcnt_sub_8: std_logic;
- signal co3_2: std_logic;
- signal wcnt_sub_9: std_logic;
- signal wcnt_sub_10: std_logic;
- signal co4_2: std_logic;
- signal wcnt_sub_11: std_logic;
- signal wcnt_sub_12: std_logic;
- signal co5_2: std_logic;
- signal wcnt_sub_13: std_logic;
- signal wcnt_sub_14: std_logic;
- signal co6_2: std_logic;
- signal wcnt_sub_15: std_logic;
- signal co7_2: std_logic;
- signal wcnt_sub_msb: std_logic;
- signal rcnt_sub_0: std_logic;
- signal rcnt_sub_1: std_logic;
- signal rcnt_sub_2: std_logic;
- signal co0_3: std_logic;
- signal rcnt_sub_3: std_logic;
- signal rcnt_sub_4: std_logic;
- signal co1_3: std_logic;
- signal rcnt_sub_5: std_logic;
- signal rcnt_sub_6: std_logic;
- signal co2_3: std_logic;
- signal rcnt_sub_7: std_logic;
- signal rcnt_sub_8: std_logic;
- signal co3_3: std_logic;
- signal rcnt_sub_9: std_logic;
- signal rcnt_sub_10: std_logic;
- signal co4_3: std_logic;
- signal rcnt_sub_11: std_logic;
- signal rcnt_sub_12: std_logic;
- signal co5_3: std_logic;
- signal rcnt_sub_13: std_logic;
- signal rcnt_sub_14: std_logic;
- signal co6_3: std_logic;
- signal rcnt_sub_15: std_logic;
- signal rcnt_sub_16: std_logic;
- signal co7_3: std_logic;
- signal rcnt_sub_msb: std_logic;
- signal co8_1d: std_logic;
- signal co8_1: std_logic;
- signal wfill_sub_0: std_logic;
- signal wptr_0: std_logic;
- signal wfill_sub_1: std_logic;
- signal wfill_sub_2: std_logic;
- signal co0_4: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wfill_sub_3: std_logic;
- signal wfill_sub_4: std_logic;
- signal co1_4: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wfill_sub_5: std_logic;
- signal wfill_sub_6: std_logic;
- signal co2_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wfill_sub_7: std_logic;
- signal wfill_sub_8: std_logic;
- signal co3_4: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wfill_sub_9: std_logic;
- signal wfill_sub_10: std_logic;
- signal co4_4: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wfill_sub_11: std_logic;
- signal wfill_sub_12: std_logic;
- signal co5_4: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wfill_sub_13: std_logic;
- signal wfill_sub_14: std_logic;
- signal co6_4: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wfill_sub_15: std_logic;
- signal co7_4: std_logic;
- signal wfill_sub_msb: std_logic;
- signal rfill_sub_0: std_logic;
- signal rptr_0: std_logic;
- signal scuba_vhi: std_logic;
- signal rfill_sub_1: std_logic;
- signal rfill_sub_2: std_logic;
- signal co0_5: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rfill_sub_3: std_logic;
- signal rfill_sub_4: std_logic;
- signal co1_5: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rfill_sub_5: std_logic;
- signal rfill_sub_6: std_logic;
- signal co2_5: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rfill_sub_7: std_logic;
- signal rfill_sub_8: std_logic;
- signal co3_5: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rfill_sub_9: std_logic;
- signal rfill_sub_10: std_logic;
- signal co4_5: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rfill_sub_11: std_logic;
- signal rfill_sub_12: std_logic;
- signal co5_5: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rfill_sub_13: std_logic;
- signal rfill_sub_14: std_logic;
- signal co6_5: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rfill_sub_15: std_logic;
- signal rfill_sub_16: std_logic;
- signal co7_5: std_logic;
- signal rptr_15: std_logic;
- signal rfill_sub_msb: std_logic;
- signal co8_2d: std_logic;
- signal co8_2: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_6: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_6: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_6: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_6: std_logic;
- signal wcount_r7: std_logic;
- signal wcount_r8: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_6: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_6: std_logic;
- signal wcount_r11: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_6: std_logic;
- signal wcount_r13: std_logic;
- signal wcount_r14: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_6: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_7: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_7: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_7: std_logic;
- signal rcount_w7: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_7: std_logic;
- signal rcount_w9: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_7: std_logic;
- signal rcount_w11: std_logic;
- signal rcount_w12: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w14: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_7: std_logic;
- signal rcount_w15: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_14: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal rcnt_reg_0: std_logic;
- signal rcnt_reg_1: std_logic;
- signal co0_8: std_logic;
- signal rcnt_reg_2: std_logic;
- signal rcnt_reg_3: std_logic;
- signal co1_8: std_logic;
- signal rcnt_reg_4: std_logic;
- signal rcnt_reg_5: std_logic;
- signal co2_8: std_logic;
- signal rcnt_reg_6: std_logic;
- signal rcnt_reg_7: std_logic;
- signal co3_8: std_logic;
- signal rcnt_reg_8: std_logic;
- signal rcnt_reg_9: std_logic;
- signal co4_8: std_logic;
- signal rcnt_reg_10: std_logic;
- signal rcnt_reg_11: std_logic;
- signal co5_8: std_logic;
- signal rcnt_reg_12: std_logic;
- signal rcnt_reg_13: std_logic;
- signal co6_8: std_logic;
- signal rcnt_reg_14: std_logic;
- signal rcnt_reg_15: std_logic;
- signal co7_7: std_logic;
- signal ae_clrsig: std_logic;
- signal ae_setsig: std_logic;
- signal ae_d: std_logic;
- signal ae_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_3: std_logic;
- signal wcnt_reg_0: std_logic;
- signal wcnt_reg_1: std_logic;
- signal co0_9: std_logic;
- signal wcnt_reg_2: std_logic;
- signal wcnt_reg_3: std_logic;
- signal co1_9: std_logic;
- signal wcnt_reg_4: std_logic;
- signal wcnt_reg_5: std_logic;
- signal co2_9: std_logic;
- signal wcnt_reg_6: std_logic;
- signal wcnt_reg_7: std_logic;
- signal co3_9: std_logic;
- signal wcnt_reg_8: std_logic;
- signal wcnt_reg_9: std_logic;
- signal co4_9: std_logic;
- signal wcnt_reg_10: std_logic;
- signal wcnt_reg_11: std_logic;
- signal co5_9: std_logic;
- signal wcnt_reg_12: std_logic;
- signal wcnt_reg_13: std_logic;
- signal co6_9: std_logic;
- signal wcnt_reg_14: std_logic;
- signal wcnt_reg_15: std_logic;
- signal af_d: std_logic;
- signal af_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX321
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; D8: in std_logic;
- D9: in std_logic; D10: in std_logic; D11: in std_logic;
- D12: in std_logic; D13: in std_logic; D14: in std_logic;
- D15: in std_logic; D16: in std_logic; D17: in std_logic;
- D18: in std_logic; D19: in std_logic; D20: in std_logic;
- D21: in std_logic; D22: in std_logic; D23: in std_logic;
- D24: in std_logic; D25: in std_logic; D26: in std_logic;
- D27: in std_logic; D28: in std_logic; D29: in std_logic;
- D30: in std_logic; D31: in std_logic; SD1: in std_logic;
- SD2: in std_logic; SD3: in std_logic; SD4: in std_logic;
- SD5: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is "";
- attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is "";
- attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is "";
- attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is "";
- attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is "";
- attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is "";
- attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is "";
- attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is "";
- attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is "";
- attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is "";
- attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is "";
- attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is "";
- attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is "";
- attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is "";
- attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is "";
- attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is "";
- attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is "";
- attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is "";
- attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is "";
- attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is "";
- attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is "";
- attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is "";
- attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is "";
- attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is "";
- attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is "";
- attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is "";
- attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is "";
- attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is "";
- attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is "";
- attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is "";
- attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is "";
- attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC";
- attribute GSR of FF_239 : label is "ENABLED";
- attribute GSR of FF_238 : label is "ENABLED";
- attribute GSR of FF_237 : label is "ENABLED";
- attribute GSR of FF_236 : label is "ENABLED";
- attribute GSR of FF_235 : label is "ENABLED";
- attribute GSR of FF_234 : label is "ENABLED";
- attribute GSR of FF_233 : label is "ENABLED";
- attribute GSR of FF_232 : label is "ENABLED";
- attribute GSR of FF_231 : label is "ENABLED";
- attribute GSR of FF_230 : label is "ENABLED";
- attribute GSR of FF_229 : label is "ENABLED";
- attribute GSR of FF_228 : label is "ENABLED";
- attribute GSR of FF_227 : label is "ENABLED";
- attribute GSR of FF_226 : label is "ENABLED";
- attribute GSR of FF_225 : label is "ENABLED";
- attribute GSR of FF_224 : label is "ENABLED";
- attribute GSR of FF_223 : label is "ENABLED";
- attribute GSR of FF_222 : label is "ENABLED";
- attribute GSR of FF_221 : label is "ENABLED";
- attribute GSR of FF_220 : label is "ENABLED";
- attribute GSR of FF_219 : label is "ENABLED";
- attribute GSR of FF_218 : label is "ENABLED";
- attribute GSR of FF_217 : label is "ENABLED";
- attribute GSR of FF_216 : label is "ENABLED";
- attribute GSR of FF_215 : label is "ENABLED";
- attribute GSR of FF_214 : label is "ENABLED";
- attribute GSR of FF_213 : label is "ENABLED";
- attribute GSR of FF_212 : label is "ENABLED";
- attribute GSR of FF_211 : label is "ENABLED";
- attribute GSR of FF_210 : label is "ENABLED";
- attribute GSR of FF_209 : label is "ENABLED";
- attribute GSR of FF_208 : label is "ENABLED";
- attribute GSR of FF_207 : label is "ENABLED";
- attribute GSR of FF_206 : label is "ENABLED";
- attribute GSR of FF_205 : label is "ENABLED";
- attribute GSR of FF_204 : label is "ENABLED";
- attribute GSR of FF_203 : label is "ENABLED";
- attribute GSR of FF_202 : label is "ENABLED";
- attribute GSR of FF_201 : label is "ENABLED";
- attribute GSR of FF_200 : label is "ENABLED";
- attribute GSR of FF_199 : label is "ENABLED";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t39: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_12: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t38: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_11: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t37: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t36: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t35: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t34: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t33: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t32: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t31: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t30: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t29: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t28: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t27: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t26: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t25: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t24: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t23: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t22: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t21: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t9: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t8: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t7: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t6: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- INV_10: INV
- port map (A=>wptr_10, Z=>wptr_10_inv);
-
- INV_9: INV
- port map (A=>wptr_11, Z=>wptr_11_inv);
-
- INV_8: INV
- port map (A=>wptr_12, Z=>wptr_12_inv);
-
- INV_7: INV
- port map (A=>wptr_13, Z=>wptr_13_inv);
-
- INV_6: INV
- port map (A=>wptr_14, Z=>wptr_14_inv);
-
- LUT4_180: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet);
-
- LUT4_179: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_p00);
-
- INV_5: INV
- port map (A=>rptr_11, Z=>rptr_11_inv);
-
- INV_4: INV
- port map (A=>rptr_12, Z=>rptr_12_inv);
-
- INV_3: INV
- port map (A=>rptr_13, Z=>rptr_13_inv);
-
- INV_2: INV
- port map (A=>rptr_14, Z=>rptr_14_inv);
-
- INV_1: INV
- port map (A=>rptr_15, Z=>rptr_15_inv);
-
- LUT4_178: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_1);
-
- LUT4_177: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec1_r10);
-
- LUT4_176: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_2);
-
- LUT4_175: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec2_p01);
-
- LUT4_174: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_3);
-
- LUT4_173: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec3_r11);
-
- LUT4_172: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_4);
-
- LUT4_171: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec4_p02);
-
- LUT4_170: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_5);
-
- LUT4_169: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec5_r12);
-
- LUT4_168: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_6);
-
- LUT4_167: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec6_p03);
-
- LUT4_166: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_7);
-
- LUT4_165: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec7_r13);
-
- LUT4_164: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_8);
-
- LUT4_163: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec8_p04);
-
- LUT4_162: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_9);
-
- LUT4_161: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec9_r14);
-
- LUT4_160: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_10);
-
- LUT4_159: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05);
-
- LUT4_158: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_11);
-
- LUT4_157: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15);
-
- LUT4_156: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_12);
-
- LUT4_155: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06);
-
- LUT4_154: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_13);
-
- LUT4_153: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16);
-
- LUT4_152: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_14);
-
- LUT4_151: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07);
-
- LUT4_150: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_15);
-
- LUT4_149: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17);
-
- LUT4_148: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_16);
-
- LUT4_147: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08);
-
- LUT4_146: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_17);
-
- LUT4_145: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18);
-
- LUT4_144: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_18);
-
- LUT4_143: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09);
-
- LUT4_142: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_19);
-
- LUT4_141: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19);
-
- LUT4_140: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_20);
-
- LUT4_139: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010);
-
- LUT4_138: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_21);
-
- LUT4_137: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110);
-
- LUT4_136: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_22);
-
- LUT4_135: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011);
-
- LUT4_134: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_23);
-
- LUT4_133: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111);
-
- LUT4_132: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_24);
-
- LUT4_131: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012);
-
- LUT4_130: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_25);
-
- LUT4_129: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112);
-
- LUT4_128: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_26);
-
- LUT4_127: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013);
-
- LUT4_126: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_27);
-
- LUT4_125: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113);
-
- LUT4_124: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_28);
-
- LUT4_123: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014);
-
- LUT4_122: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_29);
-
- LUT4_121: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114);
-
- LUT4_120: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
- DO0=>func_and_inet_30);
-
- LUT4_119: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015);
-
- LUT4_118: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_31);
-
- LUT4_117: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115);
-
- LUT4_116: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_32);
-
- LUT4_115: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec32_p016);
-
- LUT4_114: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_33);
-
- LUT4_113: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec33_r116);
-
- LUT4_112: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_34);
-
- LUT4_111: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec34_p017);
-
- LUT4_110: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_35);
-
- LUT4_109: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec35_r117);
-
- LUT4_108: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_36);
-
- LUT4_107: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec36_p018);
-
- LUT4_106: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_37);
-
- LUT4_105: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec37_r118);
-
- LUT4_104: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_38);
-
- LUT4_103: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec38_p019);
-
- LUT4_102: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_39);
-
- LUT4_101: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec39_r119);
-
- LUT4_100: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_40);
-
- LUT4_99: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec40_p020);
-
- LUT4_98: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_41);
-
- LUT4_97: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec41_r120);
-
- LUT4_96: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_42);
-
- LUT4_95: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec42_p021);
-
- LUT4_94: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_43);
-
- LUT4_93: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec43_r121);
-
- LUT4_92: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_44);
-
- LUT4_91: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec44_p022);
-
- LUT4_90: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_45);
-
- LUT4_89: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec45_r122);
-
- LUT4_88: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_46);
-
- LUT4_87: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec46_p023);
-
- LUT4_86: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_47);
-
- LUT4_85: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec47_r123);
-
- LUT4_84: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_48);
-
- LUT4_83: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec48_p024);
-
- LUT4_82: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_49);
-
- LUT4_81: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec49_r124);
-
- LUT4_80: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_50);
-
- LUT4_79: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec50_p025);
-
- LUT4_78: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_51);
-
- LUT4_77: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec51_r125);
-
- LUT4_76: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_52);
-
- LUT4_75: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec52_p026);
-
- LUT4_74: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_53);
-
- LUT4_73: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec53_r126);
-
- LUT4_72: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_54);
-
- LUT4_71: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec54_p027);
-
- LUT4_70: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_55);
-
- LUT4_69: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec55_r127);
-
- LUT4_68: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_56);
-
- LUT4_67: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec56_p028);
-
- LUT4_66: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_57);
-
- LUT4_65: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec57_r128);
-
- LUT4_64: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_58);
-
- LUT4_63: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec58_p029);
-
- LUT4_62: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_59);
-
- LUT4_61: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec59_r129);
-
- LUT4_60: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_60);
-
- LUT4_59: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec60_p030);
-
- LUT4_58: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_61);
-
- LUT4_57: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec61_r130);
-
- LUT4_56: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
- DO0=>func_and_inet_62);
-
- LUT4_55: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec62_p031);
-
- LUT4_54: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_63);
-
- LUT4_53: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec63_r131);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r2);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r1);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- XOR2_t5: XOR2
- port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb);
-
- XOR2_t4: XOR2
- port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb);
-
- XOR2_t3: XOR2
- port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb);
-
- XOR2_t2: XOR2
- port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- INV_0: INV
- port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv);
-
- AND2_t1: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig);
-
- AND2_t0: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig);
-
- pdp_ram_0_0_31: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_30: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_29: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
- DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
- DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
- DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_28: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1,
- DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4,
- DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7,
- DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_4_0_27: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1,
- DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4,
- DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7,
- DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_5_0_26: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1,
- DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4,
- DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7,
- DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_6_0_25: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1,
- DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4,
- DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7,
- DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_7_0_24: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1,
- DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4,
- DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7,
- DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_8_0_23: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1,
- DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4,
- DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7,
- DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_9_0_22: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1,
- DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4,
- DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7,
- DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_10_0_21: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1,
- DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4,
- DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7,
- DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_11_0_20: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1,
- DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4,
- DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7,
- DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_12_0_19: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1,
- DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4,
- DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7,
- DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_13_0_18: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1,
- DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4,
- DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7,
- DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_14_0_17: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1,
- DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4,
- DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7,
- DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_15_0_16: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1,
- DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4,
- DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7,
- DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_16_0_15: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1,
- DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4,
- DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7,
- DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_17_0_14: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1,
- DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4,
- DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7,
- DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_18_0_13: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1,
- DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4,
- DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7,
- DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_19_0_12: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1,
- DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4,
- DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7,
- DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_20_0_11: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1,
- DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4,
- DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7,
- DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_21_0_10: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1,
- DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4,
- DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7,
- DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_22_0_9: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1,
- DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4,
- DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7,
- DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_23_0_8: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1,
- DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4,
- DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7,
- DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_24_0_7: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1,
- DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4,
- DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7,
- DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_25_0_6: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1,
- DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4,
- DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7,
- DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_26_0_5: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1,
- DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4,
- DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7,
- DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_27_0_4: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1,
- DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4,
- DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7,
- DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_28_0_3: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1,
- DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4,
- DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7,
- DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_29_0_2: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1,
- DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4,
- DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7,
- DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_30_0_1: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1,
- DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4,
- DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7,
- DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_31_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1,
- DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4,
- DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7,
- DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_239: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_238: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_237: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_236: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_235: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_234: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_233: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_232: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_231: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_230: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_229: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_228: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_227: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_226: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_225: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_224: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_223: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_222: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_221: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_220: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_219: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_218: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_217: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_216: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_215: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_214: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_213: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_212: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_211: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_210: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_209: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_208: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_207: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_206: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_205: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_204: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_203: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_202: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_201: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_200: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_199: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_198: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_197: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_196: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_195: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_194: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_193: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_192: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_191: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_190: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_189: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_188: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_187: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_186: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_185: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_184: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_183: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_182: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_181: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_180: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_179: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_178: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_177: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_176: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_175: FD1P3DX
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_174: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_173: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_172: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_171: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_170: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_169: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_168: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_167: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_166: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_165: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_164: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_163: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_162: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_161: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_160: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_159: FD1P3DX
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_158: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_157: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_156: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_155: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_154: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_153: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_152: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_151: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_150: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_149: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_148: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_147: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_146: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_145: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_144: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_143: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_142: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_141: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_140: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_139: FD1P3DX
- port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_12_ff);
-
- FF_138: FD1P3DX
- port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_13_ff);
-
- FF_137: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_136: FD1P3DX
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_135: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_134: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_133: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_132: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_131: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_130: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_129: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_128: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_127: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_126: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_125: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_124: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_123: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_122: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_121: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_120: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_119: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_118: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_117: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_116: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_115: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_114: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_113: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_112: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_111: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_110: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_109: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_108: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_107: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_106: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_105: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_104: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_103: FD1S3DX
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_102: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_101: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_100: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_99: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_98: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_97: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_96: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_95: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_94: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_93: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_92: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_91: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_90: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_89: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_88: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_87: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_86: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_85: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_84: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_83: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_82: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_81: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_80: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_79: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_78: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_77: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_76: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_75: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_74: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_73: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_72: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_71: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_70: FD1S3DX
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_69: FD1S3DX
- port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0);
-
- FF_68: FD1S3DX
- port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1);
-
- FF_67: FD1S3DX
- port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2);
-
- FF_66: FD1S3DX
- port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3);
-
- FF_65: FD1S3DX
- port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4);
-
- FF_64: FD1S3DX
- port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5);
-
- FF_63: FD1S3DX
- port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6);
-
- FF_62: FD1S3DX
- port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7);
-
- FF_61: FD1S3DX
- port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8);
-
- FF_60: FD1S3DX
- port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9);
-
- FF_59: FD1S3DX
- port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10);
-
- FF_58: FD1S3DX
- port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11);
-
- FF_57: FD1S3DX
- port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12);
-
- FF_56: FD1S3DX
- port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13);
-
- FF_55: FD1S3DX
- port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14);
-
- FF_54: FD1S3DX
- port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15);
-
- FF_53: FD1S3DX
- port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0);
-
- FF_52: FD1S3DX
- port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1);
-
- FF_51: FD1S3DX
- port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2);
-
- FF_50: FD1S3DX
- port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3);
-
- FF_49: FD1S3DX
- port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4);
-
- FF_48: FD1S3DX
- port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5);
-
- FF_47: FD1S3DX
- port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6);
-
- FF_46: FD1S3DX
- port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7);
-
- FF_45: FD1S3DX
- port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8);
-
- FF_44: FD1S3DX
- port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9);
-
- FF_43: FD1S3DX
- port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10);
-
- FF_42: FD1S3DX
- port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11);
-
- FF_41: FD1S3DX
- port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12);
-
- FF_40: FD1S3DX
- port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13);
-
- FF_39: FD1S3DX
- port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14);
-
- FF_38: FD1S3DX
- port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15);
-
- FF_37: FD1S3DX
- port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16);
-
- FF_36: FD1S3DX
- port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
-
- FF_35: FD1S3DX
- port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
-
- FF_34: FD1S3DX
- port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
-
- FF_33: FD1S3DX
- port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
-
- FF_32: FD1S3DX
- port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
-
- FF_31: FD1S3DX
- port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
-
- FF_30: FD1S3DX
- port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
-
- FF_29: FD1S3DX
- port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
-
- FF_28: FD1S3DX
- port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
-
- FF_27: FD1S3DX
- port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
-
- FF_26: FD1S3DX
- port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
-
- FF_25: FD1S3DX
- port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
-
- FF_24: FD1S3DX
- port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12));
-
- FF_23: FD1S3DX
- port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13));
-
- FF_22: FD1S3DX
- port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14));
-
- FF_21: FD1S3DX
- port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15));
-
- FF_20: FD1S3DX
- port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
-
- FF_19: FD1S3DX
- port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
-
- FF_18: FD1S3DX
- port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
-
- FF_17: FD1S3DX
- port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
-
- FF_16: FD1S3DX
- port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
-
- FF_15: FD1S3DX
- port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
-
- FF_14: FD1S3DX
- port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
-
- FF_13: FD1S3DX
- port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
-
- FF_12: FD1S3DX
- port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
-
- FF_11: FD1S3DX
- port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
-
- FF_10: FD1S3DX
- port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10));
-
- FF_9: FD1S3DX
- port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11));
-
- FF_8: FD1S3DX
- port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12));
-
- FF_7: FD1S3DX
- port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13));
-
- FF_6: FD1S3DX
- port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14));
-
- FF_5: FD1S3DX
- port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15));
-
- FF_4: FD1S3DX
- port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16));
-
- FF_3: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_2: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- FF_1: FD1S3BX
- port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
-
- FF_0: FD1S3DX
- port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>ircount_16, NC1=>open);
-
- mux_8: MUX321
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
- D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
- D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
- D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0,
- D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0,
- D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0,
- D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0,
- D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0,
- D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(0));
-
- mux_7: MUX321
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
- D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
- D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
- D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1,
- D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1,
- D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1,
- D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1,
- D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1,
- D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(1));
-
- mux_6: MUX321
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
- D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
- D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
- D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2,
- D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2,
- D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2,
- D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2,
- D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2,
- D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(2));
-
- mux_5: MUX321
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
- D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
- D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
- D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3,
- D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3,
- D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3,
- D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3,
- D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3,
- D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(3));
-
- mux_4: MUX321
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
- D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
- D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
- D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4,
- D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4,
- D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4,
- D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4,
- D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4,
- D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(4));
-
- mux_3: MUX321
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
- D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
- D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
- D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5,
- D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5,
- D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5,
- D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5,
- D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5,
- D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(5));
-
- mux_2: MUX321
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
- D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
- D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
- D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6,
- D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6,
- D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6,
- D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6,
- D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6,
- D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(6));
-
- mux_1: MUX321
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
- D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
- D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
- D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7,
- D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7,
- D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7,
- D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7,
- D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7,
- D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(7));
-
- mux_0: MUX321
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
- D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
- D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
- D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8,
- D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8,
- D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8,
- D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8,
- D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8,
- D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(8));
-
- wcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
- S1=>wcnt_sub_0);
-
- wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2,
- B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1,
- S1=>wcnt_sub_2);
-
- wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4,
- B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3,
- S1=>wcnt_sub_4);
-
- wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6,
- B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5,
- S1=>wcnt_sub_6);
-
- wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8,
- B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7,
- S1=>wcnt_sub_8);
-
- wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9,
- S1=>wcnt_sub_10);
-
- wcnt_6: FSUB2B
- port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2,
- S0=>wcnt_sub_11, S1=>wcnt_sub_12);
-
- wcnt_7: FSUB2B
- port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13,
- S1=>wcnt_sub_14);
-
- wcnt_8: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15,
- S1=>open);
-
- rcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open,
- S1=>rcnt_sub_0);
-
- rcnt_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1,
- B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1,
- S1=>rcnt_sub_2);
-
- rcnt_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3,
- B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3,
- S1=>rcnt_sub_4);
-
- rcnt_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5,
- B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5,
- S1=>rcnt_sub_6);
-
- rcnt_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7,
- B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7,
- S1=>rcnt_sub_8);
-
- rcnt_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9,
- B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9,
- S1=>rcnt_sub_10);
-
- rcnt_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11,
- B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11,
- S1=>rcnt_sub_12);
-
- rcnt_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13,
- B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13,
- S1=>rcnt_sub_14);
-
- rcnt_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15,
- B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15,
- S1=>rcnt_sub_16);
-
- rcntd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open);
-
- wfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open,
- S1=>wfill_sub_0);
-
- wfill_1: FSUB2B
- port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3,
- BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2);
-
- wfill_2: FSUB2B
- port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5,
- BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4);
-
- wfill_3: FSUB2B
- port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7,
- BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6);
-
- wfill_4: FSUB2B
- port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9,
- BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8);
-
- wfill_5: FSUB2B
- port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9,
- S1=>wfill_sub_10);
-
- wfill_6: FSUB2B
- port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4,
- S0=>wfill_sub_11, S1=>wfill_sub_12);
-
- wfill_7: FSUB2B
- port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13,
- S1=>wfill_sub_14);
-
- wfill_8: FSUB2B
- port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- rfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
- S1=>rfill_sub_0);
-
- rfill_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2,
- BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2);
-
- rfill_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4,
- BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4);
-
- rfill_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6,
- BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6);
-
- rfill_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8,
- BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8);
-
- rfill_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10,
- BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10);
-
- rfill_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11,
- B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11,
- S1=>rfill_sub_12);
-
- rfill_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13,
- B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13,
- S1=>rfill_sub_14);
-
- rfill_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15,
- B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15,
- S1=>rfill_sub_16);
-
- rfilld: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_6, GE=>co1_6);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_6, GE=>co2_6);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_6, GE=>co3_6);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
- B1=>wcount_r8, CI=>co3_6, GE=>co4_6);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co4_6, GE=>co5_6);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11,
- B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13,
- B1=>wcount_r14, CI=>co6_6, GE=>co7_6);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_7, GE=>co1_7);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_7, GE=>co2_7);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>rcount_w8, CI=>co2_7, GE=>co3_7);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
- B1=>rcount_w10, CI=>co3_7, GE=>co4_7);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11,
- B1=>rcount_w12, CI=>co4_7, GE=>co5_7);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w14, CI=>co5_7, GE=>co6_7);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15,
- B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- ae_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- ae_cmp_0: AGEB2
- port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
- B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8);
-
- ae_cmp_1: AGEB2
- port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
- B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8);
-
- ae_cmp_2: AGEB2
- port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
- B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8);
-
- ae_cmp_3: AGEB2
- port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
- B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8);
-
- ae_cmp_4: AGEB2
- port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9),
- B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8);
-
- ae_cmp_5: AGEB2
- port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11),
- B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8);
-
- ae_cmp_6: AGEB2
- port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13),
- B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8);
-
- ae_cmp_7: AGEB2
- port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15),
- B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7);
-
- ae_cmp_8: AGEB2
- port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig,
- B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
-
- af_d_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
-
- af_d_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
- B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9);
-
- af_d_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
- B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9);
-
- af_d_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
- B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9);
-
- af_d_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
- B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9);
-
- af_d_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
- B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9);
-
- af_d_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
- B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9);
-
- af_d_cmp_6: AGEB2
- port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
- B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9);
-
- af_d_cmp_7: AGEB2
- port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14),
- B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_32kx16x8_mb2 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX321 use entity ecp3.MUX321(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:22:54 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e
- Circuit name : fifo_32kx16x8_mb2
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]
- Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_32kx16x8_mb2.vhd
- VHDL template : fifo_32kx16x8_mb2_tmpl.vhd
- VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_32kx16x8_mb2.srp
- Estimated Resource Usage:
- LUT : 491
- EBR : 32
- Reg : 240
-
-END SCUBA Module Synthesis
-
-File: fifo_32kx16x8_mb2.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:22:54 2011
-
--- parameterized module component declaration
-component fifo_32kx16x8_mb2
- port (Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(8 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_32kx16x8_mb2
- port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__,
- AmFullThresh(14 downto 0)=>__, Q(8 downto 0)=>__, WCNT(15 downto 0)=>__,
- RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__,
- AlmostFull=>__);
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:22:35 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 16 -num_words 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e
- Circuit name : fifo_32kx16x8_mb
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]
- Outputs : Q[7:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_32kx16x8_mb.vhd
- VHDL template : fifo_32kx16x8_mb_tmpl.vhd
- VHDL testbench : tb_fifo_32kx16x8_mb_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_32kx16x8_mb.srp
- Estimated Resource Usage:
- LUT : 299
- EBR : 32
- Reg : 237
-
-END SCUBA Module Synthesis
-
-File: fifo_32kx16x8_mb.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:22:35 2011
-
--- parameterized module component declaration
-component fifo_32kx16x8_mb
- port (Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(7 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_32kx16x8_mb
- port map (Data(15 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__,
- AmFullThresh(14 downto 0)=>__, Q(7 downto 0)=>__, WCNT(15 downto 0)=>__,
- RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__,
- AlmostFull=>__);
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
--- Module Version: 5.5
---/home/soft/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx9_flags -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 9 -depth 32768 -rdata_width 9 -no_enable -pe -1 -pf 30000 -pf2 29990 -e
-
--- Wed Nov 6 19:54:22 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_32kx9_flags is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostFull: out std_logic);
-end fifo_32kx9_flags;
-
-architecture Structure of fifo_32kx9_flags is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal wptr_14_inv: std_logic;
- signal rptr_14_inv: std_logic;
- signal wptr_13_inv: std_logic;
- signal rptr_13_inv: std_logic;
- signal wptr_12_inv: std_logic;
- signal rptr_12_inv: std_logic;
- signal wptr_11_inv: std_logic;
- signal rptr_11_inv: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal dec1_r10: std_logic;
- signal dec0_p00: std_logic;
- signal dec3_r11: std_logic;
- signal dec2_p01: std_logic;
- signal dec5_r12: std_logic;
- signal dec4_p02: std_logic;
- signal dec7_r13: std_logic;
- signal dec6_p03: std_logic;
- signal dec9_r14: std_logic;
- signal dec8_p04: std_logic;
- signal dec11_r15: std_logic;
- signal dec10_p05: std_logic;
- signal dec13_r16: std_logic;
- signal dec12_p06: std_logic;
- signal dec15_r17: std_logic;
- signal dec14_p07: std_logic;
- signal dec17_r18: std_logic;
- signal dec16_p08: std_logic;
- signal dec19_r19: std_logic;
- signal dec18_p09: std_logic;
- signal dec21_r110: std_logic;
- signal dec20_p010: std_logic;
- signal dec23_r111: std_logic;
- signal dec22_p011: std_logic;
- signal dec25_r112: std_logic;
- signal dec24_p012: std_logic;
- signal dec27_r113: std_logic;
- signal dec26_p013: std_logic;
- signal dec29_r114: std_logic;
- signal dec28_p014: std_logic;
- signal dec31_r115: std_logic;
- signal dec30_p015: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wptr_15: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_15: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal af: std_logic;
- signal af_d: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co7: std_logic;
- signal co6: std_logic;
- signal wcount_15: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co7_1: std_logic;
- signal co6_1: std_logic;
- signal rcount_15: std_logic;
- signal mdout1_15_0: std_logic;
- signal mdout1_14_0: std_logic;
- signal mdout1_13_0: std_logic;
- signal mdout1_12_0: std_logic;
- signal mdout1_11_0: std_logic;
- signal mdout1_10_0: std_logic;
- signal mdout1_9_0: std_logic;
- signal mdout1_8_0: std_logic;
- signal mdout1_7_0: std_logic;
- signal mdout1_6_0: std_logic;
- signal mdout1_5_0: std_logic;
- signal mdout1_4_0: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_15_1: std_logic;
- signal mdout1_14_1: std_logic;
- signal mdout1_13_1: std_logic;
- signal mdout1_12_1: std_logic;
- signal mdout1_11_1: std_logic;
- signal mdout1_10_1: std_logic;
- signal mdout1_9_1: std_logic;
- signal mdout1_8_1: std_logic;
- signal mdout1_7_1: std_logic;
- signal mdout1_6_1: std_logic;
- signal mdout1_5_1: std_logic;
- signal mdout1_4_1: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_15_2: std_logic;
- signal mdout1_14_2: std_logic;
- signal mdout1_13_2: std_logic;
- signal mdout1_12_2: std_logic;
- signal mdout1_11_2: std_logic;
- signal mdout1_10_2: std_logic;
- signal mdout1_9_2: std_logic;
- signal mdout1_8_2: std_logic;
- signal mdout1_7_2: std_logic;
- signal mdout1_6_2: std_logic;
- signal mdout1_5_2: std_logic;
- signal mdout1_4_2: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_15_3: std_logic;
- signal mdout1_14_3: std_logic;
- signal mdout1_13_3: std_logic;
- signal mdout1_12_3: std_logic;
- signal mdout1_11_3: std_logic;
- signal mdout1_10_3: std_logic;
- signal mdout1_9_3: std_logic;
- signal mdout1_8_3: std_logic;
- signal mdout1_7_3: std_logic;
- signal mdout1_6_3: std_logic;
- signal mdout1_5_3: std_logic;
- signal mdout1_4_3: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_15_4: std_logic;
- signal mdout1_14_4: std_logic;
- signal mdout1_13_4: std_logic;
- signal mdout1_12_4: std_logic;
- signal mdout1_11_4: std_logic;
- signal mdout1_10_4: std_logic;
- signal mdout1_9_4: std_logic;
- signal mdout1_8_4: std_logic;
- signal mdout1_7_4: std_logic;
- signal mdout1_6_4: std_logic;
- signal mdout1_5_4: std_logic;
- signal mdout1_4_4: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_15_5: std_logic;
- signal mdout1_14_5: std_logic;
- signal mdout1_13_5: std_logic;
- signal mdout1_12_5: std_logic;
- signal mdout1_11_5: std_logic;
- signal mdout1_10_5: std_logic;
- signal mdout1_9_5: std_logic;
- signal mdout1_8_5: std_logic;
- signal mdout1_7_5: std_logic;
- signal mdout1_6_5: std_logic;
- signal mdout1_5_5: std_logic;
- signal mdout1_4_5: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_15_6: std_logic;
- signal mdout1_14_6: std_logic;
- signal mdout1_13_6: std_logic;
- signal mdout1_12_6: std_logic;
- signal mdout1_11_6: std_logic;
- signal mdout1_10_6: std_logic;
- signal mdout1_9_6: std_logic;
- signal mdout1_8_6: std_logic;
- signal mdout1_7_6: std_logic;
- signal mdout1_6_6: std_logic;
- signal mdout1_5_6: std_logic;
- signal mdout1_4_6: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_15_7: std_logic;
- signal mdout1_14_7: std_logic;
- signal mdout1_13_7: std_logic;
- signal mdout1_12_7: std_logic;
- signal mdout1_11_7: std_logic;
- signal mdout1_10_7: std_logic;
- signal mdout1_9_7: std_logic;
- signal mdout1_8_7: std_logic;
- signal mdout1_7_7: std_logic;
- signal mdout1_6_7: std_logic;
- signal mdout1_5_7: std_logic;
- signal mdout1_4_7: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_14_ff: std_logic;
- signal rptr_13_ff: std_logic;
- signal rptr_12_ff: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_15_8: std_logic;
- signal mdout1_14_8: std_logic;
- signal mdout1_13_8: std_logic;
- signal mdout1_12_8: std_logic;
- signal mdout1_11_8: std_logic;
- signal mdout1_10_8: std_logic;
- signal mdout1_9_8: std_logic;
- signal mdout1_8_8: std_logic;
- signal mdout1_7_8: std_logic;
- signal mdout1_6_8: std_logic;
- signal mdout1_5_8: std_logic;
- signal mdout1_4_8: std_logic;
- signal mdout1_3_8: std_logic;
- signal mdout1_2_8: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r13: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal wcount_r14: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_14: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_14: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal iaf_setcount_0: std_logic;
- signal iaf_setcount_1: std_logic;
- signal af_set_ctr_ci: std_logic;
- signal iaf_setcount_2: std_logic;
- signal iaf_setcount_3: std_logic;
- signal co0_4: std_logic;
- signal iaf_setcount_4: std_logic;
- signal iaf_setcount_5: std_logic;
- signal co1_4: std_logic;
- signal iaf_setcount_6: std_logic;
- signal iaf_setcount_7: std_logic;
- signal co2_4: std_logic;
- signal iaf_setcount_8: std_logic;
- signal iaf_setcount_9: std_logic;
- signal co3_4: std_logic;
- signal iaf_setcount_10: std_logic;
- signal iaf_setcount_11: std_logic;
- signal co4_4: std_logic;
- signal iaf_setcount_12: std_logic;
- signal iaf_setcount_13: std_logic;
- signal co5_4: std_logic;
- signal iaf_setcount_14: std_logic;
- signal iaf_setcount_15: std_logic;
- signal co7_2: std_logic;
- signal co6_4: std_logic;
- signal af_setcount_15: std_logic;
- signal cmp_ci_2: std_logic;
- signal af_setcount_0: std_logic;
- signal af_setcount_1: std_logic;
- signal co0_5: std_logic;
- signal af_setcount_2: std_logic;
- signal af_setcount_3: std_logic;
- signal co1_5: std_logic;
- signal af_setcount_4: std_logic;
- signal af_setcount_5: std_logic;
- signal co2_5: std_logic;
- signal af_setcount_6: std_logic;
- signal af_setcount_7: std_logic;
- signal co3_5: std_logic;
- signal af_setcount_8: std_logic;
- signal af_setcount_9: std_logic;
- signal co4_5: std_logic;
- signal af_setcount_10: std_logic;
- signal af_setcount_11: std_logic;
- signal co5_5: std_logic;
- signal af_setcount_12: std_logic;
- signal af_setcount_13: std_logic;
- signal co6_5: std_logic;
- signal af_set_cmp_clr: std_logic;
- signal af_setcount_14: std_logic;
- signal af_set_cmp_set: std_logic;
- signal af_set: std_logic;
- signal af_set_c: std_logic;
- signal scuba_vhi: std_logic;
- signal iaf_clrcount_0: std_logic;
- signal iaf_clrcount_1: std_logic;
- signal af_clr_ctr_ci: std_logic;
- signal iaf_clrcount_2: std_logic;
- signal iaf_clrcount_3: std_logic;
- signal co0_6: std_logic;
- signal iaf_clrcount_4: std_logic;
- signal iaf_clrcount_5: std_logic;
- signal co1_6: std_logic;
- signal iaf_clrcount_6: std_logic;
- signal iaf_clrcount_7: std_logic;
- signal co2_6: std_logic;
- signal iaf_clrcount_8: std_logic;
- signal iaf_clrcount_9: std_logic;
- signal co3_6: std_logic;
- signal iaf_clrcount_10: std_logic;
- signal iaf_clrcount_11: std_logic;
- signal co4_6: std_logic;
- signal iaf_clrcount_12: std_logic;
- signal iaf_clrcount_13: std_logic;
- signal co5_6: std_logic;
- signal iaf_clrcount_14: std_logic;
- signal iaf_clrcount_15: std_logic;
- signal co7_3: std_logic;
- signal co6_6: std_logic;
- signal af_clrcount_15: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_3: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal af_clrcount_0: std_logic;
- signal af_clrcount_1: std_logic;
- signal co0_7: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal af_clrcount_2: std_logic;
- signal af_clrcount_3: std_logic;
- signal co1_7: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal af_clrcount_4: std_logic;
- signal af_clrcount_5: std_logic;
- signal co2_7: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal af_clrcount_6: std_logic;
- signal af_clrcount_7: std_logic;
- signal co3_7: std_logic;
- signal rcount_w8: std_logic;
- signal rcount_w9: std_logic;
- signal af_clrcount_8: std_logic;
- signal af_clrcount_9: std_logic;
- signal co4_7: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal af_clrcount_10: std_logic;
- signal af_clrcount_11: std_logic;
- signal co5_7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w13: std_logic;
- signal af_clrcount_12: std_logic;
- signal af_clrcount_13: std_logic;
- signal co6_7: std_logic;
- signal rcount_w14: std_logic;
- signal af_clr_cmp_clr: std_logic;
- signal af_clrcount_14: std_logic;
- signal af_clr_cmp_set: std_logic;
- signal af_clr: std_logic;
- signal af_clr_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX161
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; D8: in std_logic;
- D9: in std_logic; D10: in std_logic; D11: in std_logic;
- D12: in std_logic; D13: in std_logic; D14: in std_logic;
- D15: in std_logic; SD1: in std_logic; SD2: in std_logic;
- SD3: in std_logic; SD4: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_15 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_15 : label is "";
- attribute RESETMODE of pdp_ram_0_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_14 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_14 : label is "";
- attribute RESETMODE of pdp_ram_1_0_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_13 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_13 : label is "";
- attribute RESETMODE of pdp_ram_2_0_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_12 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_12 : label is "";
- attribute RESETMODE of pdp_ram_3_0_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_4_0_11 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_4_0_11 : label is "";
- attribute RESETMODE of pdp_ram_4_0_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_5_0_10 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_5_0_10 : label is "";
- attribute RESETMODE of pdp_ram_5_0_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_6_0_9 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_6_0_9 : label is "";
- attribute RESETMODE of pdp_ram_6_0_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_7_0_8 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_7_0_8 : label is "";
- attribute RESETMODE of pdp_ram_7_0_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_8_0_7 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_8_0_7 : label is "";
- attribute RESETMODE of pdp_ram_8_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_9_0_6 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_9_0_6 : label is "";
- attribute RESETMODE of pdp_ram_9_0_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_10_0_5 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_10_0_5 : label is "";
- attribute RESETMODE of pdp_ram_10_0_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_11_0_4 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_11_0_4 : label is "";
- attribute RESETMODE of pdp_ram_11_0_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_12_0_3 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_12_0_3 : label is "";
- attribute RESETMODE of pdp_ram_12_0_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_13_0_2 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_13_0_2 : label is "";
- attribute RESETMODE of pdp_ram_13_0_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_14_0_1 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_14_0_1 : label is "";
- attribute RESETMODE of pdp_ram_14_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_15_0_0 : label is "fifo_32kx9_flags.lpc";
- attribute MEM_INIT_FILE of pdp_ram_15_0_0 : label is "";
- attribute RESETMODE of pdp_ram_15_0_0 : label is "SYNC";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t32: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_9: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t31: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_8: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t30: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t29: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t28: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t27: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t26: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t25: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t24: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t23: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t22: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t21: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t20: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t19: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t18: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t17: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t16: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t15: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t14: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t13: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t12: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t11: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t10: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t9: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t8: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t7: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t6: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t5: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t4: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t3: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t2: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t1: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t0: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- INV_7: INV
- port map (A=>wptr_11, Z=>wptr_11_inv);
-
- INV_6: INV
- port map (A=>wptr_12, Z=>wptr_12_inv);
-
- INV_5: INV
- port map (A=>wptr_13, Z=>wptr_13_inv);
-
- INV_4: INV
- port map (A=>wptr_14, Z=>wptr_14_inv);
-
- LUT4_82: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>dec0_p00);
-
- INV_3: INV
- port map (A=>rptr_11, Z=>rptr_11_inv);
-
- INV_2: INV
- port map (A=>rptr_12, Z=>rptr_12_inv);
-
- INV_1: INV
- port map (A=>rptr_13, Z=>rptr_13_inv);
-
- INV_0: INV
- port map (A=>rptr_14, Z=>rptr_14_inv);
-
- LUT4_81: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>dec1_r10);
-
- LUT4_80: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>dec2_p01);
-
- LUT4_79: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>dec3_r11);
-
- LUT4_78: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>dec4_p02);
-
- LUT4_77: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>dec5_r12);
-
- LUT4_76: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>dec6_p03);
-
- LUT4_75: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>dec7_r13);
-
- LUT4_74: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>dec8_p04);
-
- LUT4_73: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>dec9_r14);
-
- LUT4_72: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>dec10_p05);
-
- LUT4_71: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>dec11_r15);
-
- LUT4_70: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>dec12_p06);
-
- LUT4_69: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>dec13_r16);
-
- LUT4_68: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>dec14_p07);
-
- LUT4_67: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>dec15_r17);
-
- LUT4_66: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>dec16_p08);
-
- LUT4_65: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>dec17_r18);
-
- LUT4_64: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>dec18_p09);
-
- LUT4_63: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>dec19_r19);
-
- LUT4_62: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>dec20_p010);
-
- LUT4_61: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>dec21_r110);
-
- LUT4_60: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>dec22_p011);
-
- LUT4_59: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>dec23_r111);
-
- LUT4_58: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>dec24_p012);
-
- LUT4_57: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>dec25_r112);
-
- LUT4_56: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>dec26_p013);
-
- LUT4_55: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>dec27_r113);
-
- LUT4_54: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>dec28_p014);
-
- LUT4_53: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>dec29_r114);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
- DO0=>dec30_p015);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>dec31_r115);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r2);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r1);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r0);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>scuba_vlo, DO0=>rcount_w13);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w9);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w23, DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w1);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w0);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_15, AD2=>rcount_15, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_15, AD2=>rcount_15, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w215,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w215,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"4c32")
- port map (AD3=>af_setcount_15, AD2=>wcount_15,
- AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_set_cmp_set);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"8001")
- port map (AD3=>af_setcount_15, AD2=>wcount_15,
- AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_set_cmp_clr);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"4c32")
- port map (AD3=>af_clrcount_15, AD2=>wcount_15,
- AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_clr_cmp_set);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"8001")
- port map (AD3=>af_clrcount_15, AD2=>wcount_15,
- AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_clr_cmp_clr);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4450")
- port map (AD3=>af, AD2=>af_set, AD1=>af_clr, AD0=>scuba_vlo,
- DO0=>af_d);
-
- pdp_ram_0_0_15: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_14: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_13: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
- DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
- DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
- DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_12: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1,
- DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4,
- DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7,
- DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_4_0_11: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1,
- DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4,
- DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7,
- DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_5_0_10: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1,
- DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4,
- DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7,
- DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_6_0_9: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1,
- DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4,
- DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7,
- DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_7_0_8: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1,
- DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4,
- DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7,
- DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_8_0_7: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1,
- DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4,
- DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7,
- DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_9_0_6: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1,
- DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4,
- DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7,
- DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_10_0_5: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0,
- DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3,
- DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6,
- DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_11_0_4: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0,
- DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3,
- DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6,
- DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_12_0_3: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0,
- DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3,
- DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6,
- DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_13_0_2: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0,
- DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3,
- DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6,
- DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_14_0_1: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0,
- DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3,
- DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6,
- DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_15_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0,
- DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3,
- DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6,
- DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_198: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_197: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_196: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_195: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_194: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_193: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_192: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_191: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_190: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_189: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_188: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_187: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_186: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_185: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_184: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_183: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_182: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_181: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_180: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_179: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_178: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_177: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_176: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_175: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_174: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_173: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_172: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_171: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_170: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_169: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_168: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_167: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_166: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_165: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_164: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_163: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_162: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_161: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_160: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_159: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_158: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_157: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_156: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_155: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_154: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_153: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_152: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_151: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_150: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_149: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_148: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_147: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_146: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_145: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_144: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_143: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_142: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_141: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_140: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_139: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_138: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_137: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_136: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_135: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_134: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_133: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_132: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_131: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_130: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_129: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_128: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_127: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_126: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_125: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_124: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_123: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_122: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_121: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_120: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_119: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_118: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_117: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_116: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_115: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_114: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_113: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_112: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_111: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_110: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_109: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_108: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_107: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_106: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_105: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_104: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_103: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_102: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_101: FD1P3DX
- port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_12_ff);
-
- FF_100: FD1P3DX
- port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_13_ff);
-
- FF_99: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_98: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_97: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_96: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_95: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_94: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_93: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_92: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_91: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_90: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_89: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_88: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_87: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_86: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_85: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_84: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_83: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_82: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_81: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_80: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_79: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_78: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_77: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_76: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_75: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_74: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_73: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_72: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_71: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_70: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_69: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_68: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_67: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_66: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_65: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_64: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_63: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_62: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_61: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_60: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_59: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_58: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_57: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_56: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_55: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_54: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_52: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_51: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_50: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_49: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_48: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_47: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_46: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_45: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_44: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_43: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_42: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_41: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_34: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_33: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- FF_32: FD1P3BX
- port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_0);
-
- FF_31: FD1P3DX
- port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_1);
-
- FF_30: FD1P3DX
- port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_2);
-
- FF_29: FD1P3DX
- port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_3);
-
- FF_28: FD1P3BX
- port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_4);
-
- FF_27: FD1P3DX
- port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_5);
-
- FF_26: FD1P3BX
- port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_6);
-
- FF_25: FD1P3BX
- port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_7);
-
- FF_24: FD1P3DX
- port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_8);
-
- FF_23: FD1P3BX
- port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_9);
-
- FF_22: FD1P3DX
- port map (D=>iaf_setcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_10);
-
- FF_21: FD1P3BX
- port map (D=>iaf_setcount_11, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_11);
-
- FF_20: FD1P3DX
- port map (D=>iaf_setcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_12);
-
- FF_19: FD1P3DX
- port map (D=>iaf_setcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_13);
-
- FF_18: FD1P3DX
- port map (D=>iaf_setcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_14);
-
- FF_17: FD1P3DX
- port map (D=>iaf_setcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_15);
-
- FF_16: FD1P3BX
- port map (D=>iaf_clrcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_clrcount_0);
-
- FF_15: FD1P3BX
- port map (D=>iaf_clrcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_clrcount_1);
-
- FF_14: FD1P3DX
- port map (D=>iaf_clrcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_clrcount_2);
-
- FF_13: FD1P3BX
- port map (D=>iaf_clrcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_clrcount_3);
-
- FF_12: FD1P3BX
- port map (D=>iaf_clrcount_4, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_clrcount_4);
-
- FF_11: FD1P3DX
- port map (D=>iaf_clrcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_clrcount_5);
-
- FF_10: FD1P3BX
- port map (D=>iaf_clrcount_6, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_clrcount_6);
-
- FF_9: FD1P3BX
- port map (D=>iaf_clrcount_7, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_clrcount_7);
-
- FF_8: FD1P3DX
- port map (D=>iaf_clrcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_clrcount_8);
-
- FF_7: FD1P3BX
- port map (D=>iaf_clrcount_9, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_clrcount_9);
-
- FF_6: FD1P3DX
- port map (D=>iaf_clrcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_clrcount_10);
-
- FF_5: FD1P3BX
- port map (D=>iaf_clrcount_11, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_clrcount_11);
-
- FF_4: FD1P3DX
- port map (D=>iaf_clrcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_clrcount_12);
-
- FF_3: FD1P3DX
- port map (D=>iaf_clrcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_clrcount_13);
-
- FF_2: FD1P3DX
- port map (D=>iaf_clrcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_clrcount_14);
-
- FF_1: FD1P3DX
- port map (D=>iaf_clrcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_clrcount_15);
-
- FF_0: FD1S3DX
- port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>af);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- mux_8: MUX161
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
- D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
- D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
- D15=>mdout1_15_0, SD1=>rptr_11_ff, SD2=>rptr_12_ff,
- SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(0));
-
- mux_7: MUX161
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
- D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
- D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
- D15=>mdout1_15_1, SD1=>rptr_11_ff, SD2=>rptr_12_ff,
- SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(1));
-
- mux_6: MUX161
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
- D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
- D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
- D15=>mdout1_15_2, SD1=>rptr_11_ff, SD2=>rptr_12_ff,
- SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(2));
-
- mux_5: MUX161
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
- D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
- D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
- D15=>mdout1_15_3, SD1=>rptr_11_ff, SD2=>rptr_12_ff,
- SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(3));
-
- mux_4: MUX161
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
- D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
- D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
- D15=>mdout1_15_4, SD1=>rptr_11_ff, SD2=>rptr_12_ff,
- SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(4));
-
- mux_3: MUX161
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
- D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
- D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
- D15=>mdout1_15_5, SD1=>rptr_11_ff, SD2=>rptr_12_ff,
- SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(5));
-
- mux_2: MUX161
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
- D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
- D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
- D15=>mdout1_15_6, SD1=>rptr_11_ff, SD2=>rptr_12_ff,
- SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(6));
-
- mux_1: MUX161
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
- D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
- D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
- D15=>mdout1_15_7, SD1=>rptr_11_ff, SD2=>rptr_12_ff,
- SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(7));
-
- mux_0: MUX161
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
- D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
- D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
- D15=>mdout1_15_8, SD1=>rptr_11_ff, SD2=>rptr_12_ff,
- SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(8));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r13, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>empty_cmp_set, B0=>wcount_r14,
- B1=>empty_cmp_clr, CI=>co6_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w13, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w14,
- B1=>full_cmp_clr, CI=>co6_3, GE=>full_d_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- af_set_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open,
- S1=>open);
-
- af_set_ctr_0: CU2
- port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0,
- PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0,
- NC1=>iaf_setcount_1);
-
- af_set_ctr_1: CU2
- port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3,
- CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3);
-
- af_set_ctr_2: CU2
- port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5,
- CO=>co2_4, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5);
-
- af_set_ctr_3: CU2
- port map (CI=>co2_4, PC0=>af_setcount_6, PC1=>af_setcount_7,
- CO=>co3_4, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7);
-
- af_set_ctr_4: CU2
- port map (CI=>co3_4, PC0=>af_setcount_8, PC1=>af_setcount_9,
- CO=>co4_4, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9);
-
- af_set_ctr_5: CU2
- port map (CI=>co4_4, PC0=>af_setcount_10, PC1=>af_setcount_11,
- CO=>co5_4, NC0=>iaf_setcount_10, NC1=>iaf_setcount_11);
-
- af_set_ctr_6: CU2
- port map (CI=>co5_4, PC0=>af_setcount_12, PC1=>af_setcount_13,
- CO=>co6_4, NC0=>iaf_setcount_12, NC1=>iaf_setcount_13);
-
- af_set_ctr_7: CU2
- port map (CI=>co6_4, PC0=>af_setcount_14, PC1=>af_setcount_15,
- CO=>co7_2, NC0=>iaf_setcount_14, NC1=>iaf_setcount_15);
-
- af_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- af_set_cmp_0: AGEB2
- port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5);
-
- af_set_cmp_1: AGEB2
- port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_5, GE=>co1_5);
-
- af_set_cmp_2: AGEB2
- port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_5, GE=>co2_5);
-
- af_set_cmp_3: AGEB2
- port map (A0=>af_setcount_6, A1=>af_setcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_5, GE=>co3_5);
-
- af_set_cmp_4: AGEB2
- port map (A0=>af_setcount_8, A1=>af_setcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_5, GE=>co4_5);
-
- af_set_cmp_5: AGEB2
- port map (A0=>af_setcount_10, A1=>af_setcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_5, GE=>co5_5);
-
- af_set_cmp_6: AGEB2
- port map (A0=>af_setcount_12, A1=>af_setcount_13,
- B0=>r_g2b_xor_cluster_0, B1=>rcount_w13, CI=>co5_5,
- GE=>co6_5);
-
- af_set_cmp_7: AGEB2
- port map (A0=>af_setcount_14, A1=>af_set_cmp_set, B0=>rcount_w14,
- B1=>af_set_cmp_clr, CI=>co6_5, GE=>af_set_c);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- af_clr_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_clr_ctr_ci, S0=>open,
- S1=>open);
-
- af_clr_ctr_0: CU2
- port map (CI=>af_clr_ctr_ci, PC0=>af_clrcount_0,
- PC1=>af_clrcount_1, CO=>co0_6, NC0=>iaf_clrcount_0,
- NC1=>iaf_clrcount_1);
-
- af_clr_ctr_1: CU2
- port map (CI=>co0_6, PC0=>af_clrcount_2, PC1=>af_clrcount_3,
- CO=>co1_6, NC0=>iaf_clrcount_2, NC1=>iaf_clrcount_3);
-
- af_clr_ctr_2: CU2
- port map (CI=>co1_6, PC0=>af_clrcount_4, PC1=>af_clrcount_5,
- CO=>co2_6, NC0=>iaf_clrcount_4, NC1=>iaf_clrcount_5);
-
- af_clr_ctr_3: CU2
- port map (CI=>co2_6, PC0=>af_clrcount_6, PC1=>af_clrcount_7,
- CO=>co3_6, NC0=>iaf_clrcount_6, NC1=>iaf_clrcount_7);
-
- af_clr_ctr_4: CU2
- port map (CI=>co3_6, PC0=>af_clrcount_8, PC1=>af_clrcount_9,
- CO=>co4_6, NC0=>iaf_clrcount_8, NC1=>iaf_clrcount_9);
-
- af_clr_ctr_5: CU2
- port map (CI=>co4_6, PC0=>af_clrcount_10, PC1=>af_clrcount_11,
- CO=>co5_6, NC0=>iaf_clrcount_10, NC1=>iaf_clrcount_11);
-
- af_clr_ctr_6: CU2
- port map (CI=>co5_6, PC0=>af_clrcount_12, PC1=>af_clrcount_13,
- CO=>co6_6, NC0=>iaf_clrcount_12, NC1=>iaf_clrcount_13);
-
- af_clr_ctr_7: CU2
- port map (CI=>co6_6, PC0=>af_clrcount_14, PC1=>af_clrcount_15,
- CO=>co7_3, NC0=>iaf_clrcount_14, NC1=>iaf_clrcount_15);
-
- af_clr_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
-
- af_clr_cmp_0: AGEB2
- port map (A0=>af_clrcount_0, A1=>af_clrcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_7);
-
- af_clr_cmp_1: AGEB2
- port map (A0=>af_clrcount_2, A1=>af_clrcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_7, GE=>co1_7);
-
- af_clr_cmp_2: AGEB2
- port map (A0=>af_clrcount_4, A1=>af_clrcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_7, GE=>co2_7);
-
- af_clr_cmp_3: AGEB2
- port map (A0=>af_clrcount_6, A1=>af_clrcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_7, GE=>co3_7);
-
- af_clr_cmp_4: AGEB2
- port map (A0=>af_clrcount_8, A1=>af_clrcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_7, GE=>co4_7);
-
- af_clr_cmp_5: AGEB2
- port map (A0=>af_clrcount_10, A1=>af_clrcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_7, GE=>co5_7);
-
- af_clr_cmp_6: AGEB2
- port map (A0=>af_clrcount_12, A1=>af_clrcount_13,
- B0=>r_g2b_xor_cluster_0, B1=>rcount_w13, CI=>co5_7,
- GE=>co6_7);
-
- af_clr_cmp_7: AGEB2
- port map (A0=>af_clrcount_14, A1=>af_clr_cmp_set, B0=>rcount_w14,
- B1=>af_clr_cmp_clr, CI=>co6_7, GE=>af_clr_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_clr_c, COUT=>open, S0=>af_clr,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
- AlmostFull <= af;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_32kx9_flags is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX161 use entity ecp3.MUX161(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_4096x32" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:24:17.331" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_4096x32.lpc" type="lpc" modified="2011 09 22 11:24:15.000"/>
- <File name="fifo_4096x32.vhd" type="top_level_vhdl" modified="2011 09 22 11:24:15.000"/>
- <File name="fifo_4096x32_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:24:15.000"/>
- <File name="tb_fifo_4096x32_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:24:15.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_4096x32 DEFIN fifo_4096x32.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_6
- SUBMODULE AGEB2
- INSTANCE full_cmp_5
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_6
- SUBMODULE AGEB2
- INSTANCE empty_cmp_5
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE CU2
- INSTANCE r_gctr_6
- SUBMODULE CU2
- INSTANCE r_gctr_5
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_6
- SUBMODULE CU2
- INSTANCE w_gctr_5
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1S3DX
- INSTANCE FF_42
- SUBMODULE FD1S3DX
- INSTANCE FF_43
- SUBMODULE FD1S3DX
- INSTANCE FF_44
- SUBMODULE FD1S3DX
- INSTANCE FF_45
- SUBMODULE FD1S3DX
- INSTANCE FF_46
- SUBMODULE FD1S3DX
- INSTANCE FF_47
- SUBMODULE FD1S3DX
- INSTANCE FF_48
- SUBMODULE FD1S3DX
- INSTANCE FF_49
- SUBMODULE FD1S3DX
- INSTANCE FF_50
- SUBMODULE FD1S3DX
- INSTANCE FF_51
- SUBMODULE FD1S3DX
- INSTANCE FF_52
- SUBMODULE FD1S3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3DX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3BX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3DX
- INSTANCE FF_101
- SUBMODULE FD1P3DX
- INSTANCE FF_102
- SUBMODULE FD1P3DX
- INSTANCE FF_103
- SUBMODULE FD1P3DX
- INSTANCE FF_104
- SUBMODULE FD1P3DX
- INSTANCE FF_105
- SUBMODULE FD1P3DX
- INSTANCE FF_106
- SUBMODULE FD1P3DX
- INSTANCE FF_107
- SUBMODULE FD1P3DX
- INSTANCE FF_108
- SUBMODULE FD1P3DX
- INSTANCE FF_109
- SUBMODULE FD1P3DX
- INSTANCE FF_110
- SUBMODULE FD1P3DX
- INSTANCE FF_111
- SUBMODULE FD1P3DX
- INSTANCE FF_112
- SUBMODULE FD1P3DX
- INSTANCE FF_113
- SUBMODULE FD1P3DX
- INSTANCE FF_114
- SUBMODULE FD1P3DX
- INSTANCE FF_115
- SUBMODULE FD1P3DX
- INSTANCE FF_116
- SUBMODULE FD1P3DX
- INSTANCE FF_117
- SUBMODULE FD1P3DX
- INSTANCE FF_118
- SUBMODULE FD1P3DX
- INSTANCE FF_119
- SUBMODULE FD1P3DX
- INSTANCE FF_120
- SUBMODULE FD1P3DX
- INSTANCE FF_121
- SUBMODULE FD1P3DX
- INSTANCE FF_122
- SUBMODULE FD1P3DX
- INSTANCE FF_123
- SUBMODULE FD1P3DX
- INSTANCE FF_124
- SUBMODULE FD1P3DX
- INSTANCE FF_125
- SUBMODULE FD1P3DX
- INSTANCE FF_126
- SUBMODULE FD1P3DX
- INSTANCE FF_127
- SUBMODULE FD1P3DX
- INSTANCE FF_128
- SUBMODULE FD1P3DX
- INSTANCE FF_129
- SUBMODULE FD1P3DX
- INSTANCE FF_130
- SUBMODULE FD1P3BX
- INSTANCE FF_131
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_7_0
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_6_1
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_5_2
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_4_3
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_3_4
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_2_5
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_1_6
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_0_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE ROM16X1A
- INSTANCE LUT4_24
- SUBMODULE ROM16X1A
- INSTANCE LUT4_25
- SUBMODULE ROM16X1A
- INSTANCE LUT4_26
- SUBMODULE ROM16X1A
- INSTANCE LUT4_27
- SUBMODULE ROM16X1A
- INSTANCE LUT4_28
- SUBMODULE ROM16X1A
- INSTANCE LUT4_29
- SUBMODULE ROM16X1A
- INSTANCE LUT4_30
- SUBMODULE ROM16X1A
- INSTANCE LUT4_31
- SUBMODULE ROM16X1A
- INSTANCE LUT4_32
- SUBMODULE ROM16X1A
- INSTANCE LUT4_33
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE XOR2
- INSTANCE XOR2_t18
- SUBMODULE XOR2
- INSTANCE XOR2_t19
- SUBMODULE XOR2
- INSTANCE XOR2_t20
- SUBMODULE XOR2
- INSTANCE XOR2_t21
- SUBMODULE XOR2
- INSTANCE XOR2_t22
- SUBMODULE XOR2
- INSTANCE XOR2_t23
- SUBMODULE OR2
- INSTANCE OR2_t24
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t25
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t26
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_4096x32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:24:15
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=4096
-Width=32
-RDepth=4096
-RWidth=32
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[31] i
-Data[30] i
-Data[29] i
-Data[28] i
-Data[27] i
-Data[26] i
-Data[25] i
-Data[24] i
-Data[23] i
-Data[22] i
-Data[21] i
-Data[20] i
-Data[19] i
-Data[18] i
-Data[17] i
-Data[16] i
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[31] o
-Q[30] o
-Q[29] o
-Q[28] o
-Q[27] o
-Q[26] o
-Q[25] o
-Q[24] o
-Q[23] o
-Q[22] o
-Q[21] o
-Q[20] o
-Q[19] o
-Q[18] o
-Q[17] o
-Q[16] o
-Q[15] o
-Q[14] o
-Q[13] o
-Q[12] o
-Q[11] o
-Q[10] o
-Q[9] o
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_4096x32.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:24:15 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_4096x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 32 -num_words 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_4096x32
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[31:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_4096x32.vhd
- VHDL template : fifo_4096x32_tmpl.vhd
- VHDL testbench : tb_fifo_4096x32_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_4096x32.srp
- Element Usage :
- AGEB2 : 14
- AND2 : 2
- CU2 : 14
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 76
- FD1S3BX : 1
- FD1S3DX : 53
- INV : 2
- OR2 : 1
- ROM16X1A : 34
- XOR2 : 24
- DP16KC : 8
- Estimated Resource Usage:
- LUT : 129
- EBR : 8
- Reg : 132
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:24:15 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_4096x32 is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_4096x32;
-
-architecture Structure of fifo_4096x32 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal co6: std_logic;
- signal wcount_12: std_logic;
- signal co5: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal co6_1: std_logic;
- signal rcount_12: std_logic;
- signal co5_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
- attribute RESETMODE of pdp_ram_0_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
- attribute RESETMODE of pdp_ram_0_1_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is "";
- attribute RESETMODE of pdp_ram_0_2_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is "";
- attribute RESETMODE of pdp_ram_0_3_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is "";
- attribute RESETMODE of pdp_ram_0_4_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is "";
- attribute RESETMODE of pdp_ram_0_5_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is "";
- attribute RESETMODE of pdp_ram_0_6_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is "";
- attribute RESETMODE of pdp_ram_0_7_0 : label is "SYNC";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t26: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t25: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t24: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t23: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t22: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t21: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t20: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t19: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t18: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t17: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t16: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t15: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t14: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t13: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t12: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t11: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t10: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t9: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t8: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t7: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t6: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t5: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t4: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t3: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t2: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t1: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t0: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r11);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w11);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_7: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_6: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6),
- DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4),
- DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_2_5: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10),
- DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8),
- DOB1=>Q(9), DOB2=>Q(10), DOB3=>Q(11), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_3_4: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14),
- DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(12),
- DOB1=>Q(13), DOB2=>Q(14), DOB3=>Q(15), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_4_3: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18),
- DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(16),
- DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_5_2: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22),
- DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(20),
- DOB1=>Q(21), DOB2=>Q(22), DOB3=>Q(23), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_6_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26),
- DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(24),
- DOB1=>Q(25), DOB2=>Q(26), DOB3=>Q(27), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_7_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30),
- DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(28),
- DOB1=>Q(29), DOB2=>Q(30), DOB3=>Q(31), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_131: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_130: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_129: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_128: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_127: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_126: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_125: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_124: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_123: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_122: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_121: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_119: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_118: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_117: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_116: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_115: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_114: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_113: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_112: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_111: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_110: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_107: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_106: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_105: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_104: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_103: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_102: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_101: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_100: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_99: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_98: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_97: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_96: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_95: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_94: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_93: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_92: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_91: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_90: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_89: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_88: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_87: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_86: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_85: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_84: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_83: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_82: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_81: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_80: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_79: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_78: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_77: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_76: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_75: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_74: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_67: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_66: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_65: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_64: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_63: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_62: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_61: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_60: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_59: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_58: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_57: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_56: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_55: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_54: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_52: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_51: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_50: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6,
- NC0=>iwcount_12, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1,
- NC0=>ircount_12, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_4096x32 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:24:15 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_4096x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 32 -num_words 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_4096x32
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[31:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_4096x32.vhd
- VHDL template : fifo_4096x32_tmpl.vhd
- VHDL testbench : tb_fifo_4096x32_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_4096x32.srp
- Estimated Resource Usage:
- LUT : 129
- EBR : 8
- Reg : 132
-
-END SCUBA Module Synthesis
-
-File: fifo_4096x32.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:24:15 2011
-
--- parameterized module component declaration
-component fifo_4096x32
- port (Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_4096x32
- port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_4096x9" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:24:07.957" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_4096x9.lpc" type="lpc" modified="2011 09 22 11:24:06.000"/>
- <File name="fifo_4096x9.vhd" type="top_level_vhdl" modified="2011 09 22 11:24:06.000"/>
- <File name="fifo_4096x9_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:24:06.000"/>
- <File name="tb_fifo_4096x9_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:24:06.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_4096x9 DEFIN fifo_4096x9.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_6
- SUBMODULE AGEB2
- INSTANCE full_cmp_5
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_6
- SUBMODULE AGEB2
- INSTANCE empty_cmp_5
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE MUX21
- INSTANCE mux_0
- SUBMODULE MUX21
- INSTANCE mux_1
- SUBMODULE MUX21
- INSTANCE mux_2
- SUBMODULE MUX21
- INSTANCE mux_3
- SUBMODULE MUX21
- INSTANCE mux_4
- SUBMODULE MUX21
- INSTANCE mux_5
- SUBMODULE MUX21
- INSTANCE mux_6
- SUBMODULE MUX21
- INSTANCE mux_7
- SUBMODULE MUX21
- INSTANCE mux_8
- SUBMODULE CU2
- INSTANCE r_gctr_6
- SUBMODULE CU2
- INSTANCE r_gctr_5
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_6
- SUBMODULE CU2
- INSTANCE w_gctr_5
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1S3DX
- INSTANCE FF_42
- SUBMODULE FD1S3DX
- INSTANCE FF_43
- SUBMODULE FD1S3DX
- INSTANCE FF_44
- SUBMODULE FD1S3DX
- INSTANCE FF_45
- SUBMODULE FD1S3DX
- INSTANCE FF_46
- SUBMODULE FD1S3DX
- INSTANCE FF_47
- SUBMODULE FD1S3DX
- INSTANCE FF_48
- SUBMODULE FD1S3DX
- INSTANCE FF_49
- SUBMODULE FD1S3DX
- INSTANCE FF_50
- SUBMODULE FD1S3DX
- INSTANCE FF_51
- SUBMODULE FD1S3DX
- INSTANCE FF_52
- SUBMODULE FD1S3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3DX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3BX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3DX
- INSTANCE FF_101
- SUBMODULE FD1P3DX
- INSTANCE FF_102
- SUBMODULE FD1P3DX
- INSTANCE FF_103
- SUBMODULE FD1P3DX
- INSTANCE FF_104
- SUBMODULE FD1P3DX
- INSTANCE FF_105
- SUBMODULE FD1P3DX
- INSTANCE FF_106
- SUBMODULE FD1P3DX
- INSTANCE FF_107
- SUBMODULE FD1P3DX
- INSTANCE FF_108
- SUBMODULE FD1P3DX
- INSTANCE FF_109
- SUBMODULE FD1P3DX
- INSTANCE FF_110
- SUBMODULE FD1P3DX
- INSTANCE FF_111
- SUBMODULE FD1P3DX
- INSTANCE FF_112
- SUBMODULE FD1P3DX
- INSTANCE FF_113
- SUBMODULE FD1P3DX
- INSTANCE FF_114
- SUBMODULE FD1P3DX
- INSTANCE FF_115
- SUBMODULE FD1P3DX
- INSTANCE FF_116
- SUBMODULE FD1P3DX
- INSTANCE FF_117
- SUBMODULE FD1P3DX
- INSTANCE FF_118
- SUBMODULE FD1P3DX
- INSTANCE FF_119
- SUBMODULE FD1P3DX
- INSTANCE FF_120
- SUBMODULE FD1P3DX
- INSTANCE FF_121
- SUBMODULE FD1P3DX
- INSTANCE FF_122
- SUBMODULE FD1P3DX
- INSTANCE FF_123
- SUBMODULE FD1P3DX
- INSTANCE FF_124
- SUBMODULE FD1P3DX
- INSTANCE FF_125
- SUBMODULE FD1P3DX
- INSTANCE FF_126
- SUBMODULE FD1P3DX
- INSTANCE FF_127
- SUBMODULE FD1P3DX
- INSTANCE FF_128
- SUBMODULE FD1P3DX
- INSTANCE FF_129
- SUBMODULE FD1P3DX
- INSTANCE FF_130
- SUBMODULE FD1P3DX
- INSTANCE FF_131
- SUBMODULE FD1P3BX
- INSTANCE FF_132
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_0_0
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_0_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE ROM16X1A
- INSTANCE LUT4_24
- SUBMODULE ROM16X1A
- INSTANCE LUT4_25
- SUBMODULE ROM16X1A
- INSTANCE LUT4_26
- SUBMODULE ROM16X1A
- INSTANCE LUT4_27
- SUBMODULE ROM16X1A
- INSTANCE LUT4_28
- SUBMODULE ROM16X1A
- INSTANCE LUT4_29
- SUBMODULE ROM16X1A
- INSTANCE LUT4_30
- SUBMODULE ROM16X1A
- INSTANCE LUT4_31
- SUBMODULE ROM16X1A
- INSTANCE LUT4_32
- SUBMODULE ROM16X1A
- INSTANCE LUT4_33
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE XOR2
- INSTANCE XOR2_t18
- SUBMODULE XOR2
- INSTANCE XOR2_t19
- SUBMODULE XOR2
- INSTANCE XOR2_t20
- SUBMODULE XOR2
- INSTANCE XOR2_t21
- SUBMODULE XOR2
- INSTANCE XOR2_t22
- SUBMODULE XOR2
- INSTANCE XOR2_t23
- SUBMODULE OR2
- INSTANCE OR2_t24
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t25
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t26
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_4096x9
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:24:06
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=4096
-Width=9
-RDepth=4096
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_4096x9.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:24:06 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 9 -num_words 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_4096x9
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_4096x9.vhd
- VHDL template : fifo_4096x9_tmpl.vhd
- VHDL testbench : tb_fifo_4096x9_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_4096x9.srp
- Element Usage :
- AGEB2 : 14
- AND2 : 2
- CU2 : 14
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 77
- FD1S3BX : 1
- FD1S3DX : 53
- INV : 2
- MUX21 : 9
- OR2 : 1
- ROM16X1A : 34
- XOR2 : 24
- DP16KC : 2
- Estimated Resource Usage:
- LUT : 138
- EBR : 2
- Reg : 133
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:24:06 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_4096x9 is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_4096x9;
-
-architecture Structure of fifo_4096x9 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_12: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal co6: std_logic;
- signal wcount_12: std_logic;
- signal co5: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal co6_1: std_logic;
- signal rcount_12: std_logic;
- signal co5_1: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX21
- port (D0: in std_logic; D1: in std_logic; SD: in std_logic;
- Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is "";
- attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t26: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t25: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t24: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t23: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t22: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t21: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t20: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t19: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t18: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t17: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t16: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t15: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t14: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t13: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t12: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t11: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t10: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t9: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t8: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t7: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t6: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t5: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t4: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t3: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t2: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t1: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t0: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r11);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w11);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_132: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_131: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_130: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_129: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_128: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_127: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_126: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_125: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_124: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_123: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_122: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_121: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_119: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_118: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_117: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_116: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_115: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_114: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_113: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_112: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_111: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_110: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_107: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_106: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_105: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_104: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_103: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_102: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_101: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_100: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_99: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_98: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_97: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_96: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_95: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_94: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_93: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_92: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_91: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_90: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_89: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_88: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_87: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_86: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_85: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_84: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_83: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_82: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_81: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_80: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_79: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_78: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_77: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_76: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_75: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_74: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_68: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_67: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_66: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_65: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_64: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_63: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_62: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_61: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_60: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_59: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_58: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_57: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_56: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_55: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_54: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_52: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_51: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_50: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6,
- NC0=>iwcount_12, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1,
- NC0=>ircount_12, NC1=>open);
-
- mux_8: MUX21
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff,
- Z=>Q(0));
-
- mux_7: MUX21
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff,
- Z=>Q(1));
-
- mux_6: MUX21
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff,
- Z=>Q(2));
-
- mux_5: MUX21
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff,
- Z=>Q(3));
-
- mux_4: MUX21
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff,
- Z=>Q(4));
-
- mux_3: MUX21
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff,
- Z=>Q(5));
-
- mux_2: MUX21
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff,
- Z=>Q(6));
-
- mux_1: MUX21
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff,
- Z=>Q(7));
-
- mux_0: MUX21
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff,
- Z=>Q(8));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_4096x9 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX21 use entity ecp3.MUX21(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:24:06 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 9 -num_words 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_4096x9
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_4096x9.vhd
- VHDL template : fifo_4096x9_tmpl.vhd
- VHDL testbench : tb_fifo_4096x9_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_4096x9.srp
- Estimated Resource Usage:
- LUT : 138
- EBR : 2
- Reg : 133
-
-END SCUBA Module Synthesis
-
-File: fifo_4096x9.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:24:06 2011
-
--- parameterized module component declaration
-component fifo_4096x9
- port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_4096x9
- port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
--- Module Version: 5.5
---/home/soft/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fifo_4kx18x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 18 -depth 2048 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
-
--- Wed Jun 26 14:33:30 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_4kx18x9 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_4kx18x9;
-
-architecture Structure of fifo_4kx18x9 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal rcount_w0: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_12: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5: std_logic;
- signal co4: std_logic;
- signal wcount_11: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal co6: std_logic;
- signal co5_1: std_logic;
- signal rcount_12: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r7: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w7: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w11: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_10: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX21
- port (D0: in std_logic; D1: in std_logic; SD: in std_logic;
- Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4kx18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4kx18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is "";
- attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t25: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t24: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t23: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t22: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t21: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t20: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t19: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t18: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t17: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t16: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t15: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t14: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t13: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t12: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t11: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t10: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t9: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t8: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t7: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t6: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t5: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t4: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t3: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t2: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t1: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t0: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w11);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0,
- DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3,
- DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6,
- DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0,
- DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3,
- DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6,
- DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_127: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_126: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_125: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_124: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_123: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_122: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_121: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_119: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_118: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_117: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_116: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_115: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_114: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_113: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_112: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_111: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_110: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_107: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_106: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_105: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_104: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_103: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_102: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_101: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_100: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_99: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_98: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_97: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_96: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_95: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_94: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_93: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_92: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_91: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_90: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_89: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_88: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_87: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_86: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_85: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_84: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_83: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_82: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_81: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_80: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_79: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_78: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_77: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_76: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_75: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_74: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_66: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_65: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_64: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_63: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_62: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_61: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_60: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_59: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_58: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_57: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_56: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_55: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_54: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_53: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_52: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_51: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_50: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6,
- NC0=>ircount_12, NC1=>open);
-
- mux_8: MUX21
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff,
- Z=>Q(0));
-
- mux_7: MUX21
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff,
- Z=>Q(1));
-
- mux_6: MUX21
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff,
- Z=>Q(2));
-
- mux_5: MUX21
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff,
- Z=>Q(3));
-
- mux_4: MUX21
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff,
- Z=>Q(4));
-
- mux_3: MUX21
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff,
- Z=>Q(5));
-
- mux_2: MUX21
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff,
- Z=>Q(6));
-
- mux_1: MUX21
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff,
- Z=>Q(7));
-
- mux_0: MUX21
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff,
- Z=>Q(8));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>rcount_w8, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w10, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w11,
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_4kx18x9 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX21 use entity ecp3.MUX21(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.4
---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 8 -depth 4096 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Tue Apr 23 14:34:09 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_4kx8_ecp3 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_4kx8_ecp3;
-
-architecture Structure of fifo_4kx8_ecp3 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal co6: std_logic;
- signal wcount_12: std_logic;
- signal co5: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal co6_1: std_logic;
- signal rcount_12: std_logic;
- signal co5_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4kx8_ecp3.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_4kx8_ecp3.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t26: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t25: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t24: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t23: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t22: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t21: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t20: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t19: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t18: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t17: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t16: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t15: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t14: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t13: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t12: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t11: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t10: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t9: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t8: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t7: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t6: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t5: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t4: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t3: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t2: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t1: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t0: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r11);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w11);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6),
- DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4),
- DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_131: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_130: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_129: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_128: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_127: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_126: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_125: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_124: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_123: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_122: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_121: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_119: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_118: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_117: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_116: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_115: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_114: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_113: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_112: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_111: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_110: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_107: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_106: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_105: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_104: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_103: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_102: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_101: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_100: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_99: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_98: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_97: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_96: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_95: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_94: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_93: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_92: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_91: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_90: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_89: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_88: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_87: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_86: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_85: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_84: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_83: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_82: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_81: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_80: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_79: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_78: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_77: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_76: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_75: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_74: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_67: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_66: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_65: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_64: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_63: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_62: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_61: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_60: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_59: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_58: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_57: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_56: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_55: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_54: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_52: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_51: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_50: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6,
- NC0=>iwcount_12, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1,
- NC0=>ircount_12, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_4kx8_ecp3 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_512x32" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:13:44.900" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="fifo_512x32.lpc" type="lpc" modified="2011 09 22 11:13:43.000"/>
- <File name="fifo_512x32.vhd" type="top_level_vhdl" modified="2011 09 22 11:13:43.000"/>
- <File name="fifo_512x32_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:13:43.000"/>
- <File name="tb_fifo_512x32_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:13:43.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_512x32 DEFIN fifo_512x32.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1P3DX
- INSTANCE FF_42
- SUBMODULE FD1P3DX
- INSTANCE FF_43
- SUBMODULE FD1P3DX
- INSTANCE FF_44
- SUBMODULE FD1P3DX
- INSTANCE FF_45
- SUBMODULE FD1P3DX
- INSTANCE FF_46
- SUBMODULE FD1P3DX
- INSTANCE FF_47
- SUBMODULE FD1P3DX
- INSTANCE FF_48
- SUBMODULE FD1P3DX
- INSTANCE FF_49
- SUBMODULE FD1P3DX
- INSTANCE FF_50
- SUBMODULE FD1P3DX
- INSTANCE FF_51
- SUBMODULE FD1P3DX
- INSTANCE FF_52
- SUBMODULE FD1P3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3BX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3BX
- INSTANCE FF_101
- SUBMODULE PDPW16KC
- INSTANCE pdp_ram_0_0_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE OR2
- INSTANCE OR2_t18
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t19
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t20
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_512x32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:13:43
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=512
-Width=32
-RDepth=512
-RWidth=32
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[31] i
-Data[30] i
-Data[29] i
-Data[28] i
-Data[27] i
-Data[26] i
-Data[25] i
-Data[24] i
-Data[23] i
-Data[22] i
-Data[21] i
-Data[20] i
-Data[19] i
-Data[18] i
-Data[17] i
-Data[16] i
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[31] o
-Q[30] o
-Q[29] o
-Q[28] o
-Q[27] o
-Q[26] o
-Q[25] o
-Q[24] o
-Q[23] o
-Q[22] o
-Q[21] o
-Q[20] o
-Q[19] o
-Q[18] o
-Q[17] o
-Q[16] o
-Q[15] o
-Q[14] o
-Q[13] o
-Q[12] o
-Q[11] o
-Q[10] o
-Q[9] o
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_512x32.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:13:43 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 32 -num_words 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x32
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[31:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x32.vhd
- VHDL template : fifo_512x32_tmpl.vhd
- VHDL testbench : tb_fifo_512x32_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x32.srp
- Element Usage :
- AGEB2 : 10
- AND2 : 2
- CU2 : 10
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 58
- FD1S3BX : 1
- FD1S3DX : 41
- INV : 2
- OR2 : 1
- ROM16X1A : 24
- XOR2 : 18
- PDPW16KC : 1
- Estimated Resource Usage:
- LUT : 97
- EBR : 1
- Reg : 102
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:13:43 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_512x32 is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x32;
-
-architecture Structure of fifo_512x32 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
- ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7,
- ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open,
- DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4),
- DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9),
- DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13),
- DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
-
- FF_101: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_512x32 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:13:43 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 32 -num_words 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x32
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[31:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x32.vhd
- VHDL template : fifo_512x32_tmpl.vhd
- VHDL testbench : tb_fifo_512x32_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x32.srp
- Estimated Resource Usage:
- LUT : 97
- EBR : 1
- Reg : 102
-
-END SCUBA Module Synthesis
-
-File: fifo_512x32.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:13:43 2011
-
--- parameterized module component declaration
-component fifo_512x32
- port (Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_512x32
- port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.4
---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Tue Jun 11 11:02:45 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_512x32x8 is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x32x8;
-
-architecture Structure of fifo_512x32x8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal rcount_w1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal rcount_w0: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5: std_logic;
- signal rcount_11: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_10: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w10: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32x8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t22: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t21: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t20: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t19: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t18: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t17: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t16: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t15: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t14: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t13: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t12: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t11: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t10: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t9: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t8: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t7: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t6: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t5: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t4: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t3: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t2: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t1: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t0: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>scuba_vlo, DI9=>Data(8), DI10=>Data(9), DI11=>Data(10),
- DI12=>Data(11), DI13=>Data(12), DI14=>Data(13),
- DI15=>Data(14), DI16=>Data(15), DI17=>scuba_vlo,
- DI18=>Data(16), DI19=>Data(17), DI20=>Data(18),
- DI21=>Data(19), DI22=>Data(20), DI23=>Data(21),
- DI24=>Data(22), DI25=>Data(23), DI26=>scuba_vlo,
- DI27=>Data(24), DI28=>Data(25), DI29=>Data(26),
- DI30=>Data(27), DI31=>Data(28), DI32=>Data(29),
- DI33=>Data(30), DI34=>Data(31), DI35=>scuba_vlo,
- ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
- ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7,
- ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
- ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
- ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
- ADR13=>rptr_10, CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo,
- CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0),
- DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), DO5=>Q(5),
- DO6=>Q(6), DO7=>Q(7), DO8=>open, DO9=>open, DO10=>open,
- DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
- DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
- DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
- DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
- DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
-
- FF_111: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_110: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_109: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_108: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_107: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_106: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_105: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_104: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_103: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_102: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_101: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_100: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_99: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_98: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_97: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_96: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_95: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_94: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_93: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_92: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_91: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_90: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_89: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_88: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_87: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_86: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_85: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_84: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_83: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_82: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_81: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_80: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_79: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_78: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_77: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_76: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_75: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_74: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_73: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_72: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_71: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_70: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_66: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_65: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_64: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_63: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_62: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_59: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_58: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_57: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_56: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_55: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_54: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_53: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_52: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_51: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_50: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_49: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_48: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_47: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_46: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_24: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5,
- NC0=>ircount_10, NC1=>ircount_11);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r0,
- B1=>wcount_r1, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w2,
- B1=>rcount_w3, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w9, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w10,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_512x32x8 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_512x64" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:23:41.995" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_512x64.lpc" type="lpc" modified="2011 09 22 11:23:40.000"/>
- <File name="fifo_512x64.vhd" type="top_level_vhdl" modified="2011 09 22 11:23:40.000"/>
- <File name="fifo_512x64_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:23:40.000"/>
- <File name="tb_fifo_512x64_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:23:40.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_512x64 DEFIN fifo_512x64.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1P3DX
- INSTANCE FF_42
- SUBMODULE FD1P3DX
- INSTANCE FF_43
- SUBMODULE FD1P3DX
- INSTANCE FF_44
- SUBMODULE FD1P3DX
- INSTANCE FF_45
- SUBMODULE FD1P3DX
- INSTANCE FF_46
- SUBMODULE FD1P3DX
- INSTANCE FF_47
- SUBMODULE FD1P3DX
- INSTANCE FF_48
- SUBMODULE FD1P3DX
- INSTANCE FF_49
- SUBMODULE FD1P3DX
- INSTANCE FF_50
- SUBMODULE FD1P3DX
- INSTANCE FF_51
- SUBMODULE FD1P3DX
- INSTANCE FF_52
- SUBMODULE FD1P3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3BX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3BX
- INSTANCE FF_101
- SUBMODULE PDPW16KC
- INSTANCE pdp_ram_0_1_0
- SUBMODULE PDPW16KC
- INSTANCE pdp_ram_0_0_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE OR2
- INSTANCE OR2_t18
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t19
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t20
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_512x64
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:23:40
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=512
-Width=72
-RDepth=512
-RWidth=72
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[71] i
-Data[70] i
-Data[69] i
-Data[68] i
-Data[67] i
-Data[66] i
-Data[65] i
-Data[64] i
-Data[63] i
-Data[62] i
-Data[61] i
-Data[60] i
-Data[59] i
-Data[58] i
-Data[57] i
-Data[56] i
-Data[55] i
-Data[54] i
-Data[53] i
-Data[52] i
-Data[51] i
-Data[50] i
-Data[49] i
-Data[48] i
-Data[47] i
-Data[46] i
-Data[45] i
-Data[44] i
-Data[43] i
-Data[42] i
-Data[41] i
-Data[40] i
-Data[39] i
-Data[38] i
-Data[37] i
-Data[36] i
-Data[35] i
-Data[34] i
-Data[33] i
-Data[32] i
-Data[31] i
-Data[30] i
-Data[29] i
-Data[28] i
-Data[27] i
-Data[26] i
-Data[25] i
-Data[24] i
-Data[23] i
-Data[22] i
-Data[21] i
-Data[20] i
-Data[19] i
-Data[18] i
-Data[17] i
-Data[16] i
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[71] o
-Q[70] o
-Q[69] o
-Q[68] o
-Q[67] o
-Q[66] o
-Q[65] o
-Q[64] o
-Q[63] o
-Q[62] o
-Q[61] o
-Q[60] o
-Q[59] o
-Q[58] o
-Q[57] o
-Q[56] o
-Q[55] o
-Q[54] o
-Q[53] o
-Q[52] o
-Q[51] o
-Q[50] o
-Q[49] o
-Q[48] o
-Q[47] o
-Q[46] o
-Q[45] o
-Q[44] o
-Q[43] o
-Q[42] o
-Q[41] o
-Q[40] o
-Q[39] o
-Q[38] o
-Q[37] o
-Q[36] o
-Q[35] o
-Q[34] o
-Q[33] o
-Q[32] o
-Q[31] o
-Q[30] o
-Q[29] o
-Q[28] o
-Q[27] o
-Q[26] o
-Q[25] o
-Q[24] o
-Q[23] o
-Q[22] o
-Q[21] o
-Q[20] o
-Q[19] o
-Q[18] o
-Q[17] o
-Q[16] o
-Q[15] o
-Q[14] o
-Q[13] o
-Q[12] o
-Q[11] o
-Q[10] o
-Q[9] o
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_512x64.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:40 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x64
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[71:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x64.vhd
- VHDL template : fifo_512x64_tmpl.vhd
- VHDL testbench : tb_fifo_512x64_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x64.srp
- Element Usage :
- AGEB2 : 10
- AND2 : 2
- CU2 : 10
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 58
- FD1S3BX : 1
- FD1S3DX : 41
- INV : 2
- OR2 : 1
- ROM16X1A : 24
- XOR2 : 18
- PDPW16KC : 2
- Estimated Resource Usage:
- LUT : 97
- EBR : 2
- Reg : 102
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:23:40 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_512x64 is
- port (
- Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x64;
-
-architecture Structure of fifo_512x64 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x64.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x64.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
- ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
- DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
- pdp_ram_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
- DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
- DI14=>Data(50), DI15=>Data(51), DI16=>Data(52),
- DI17=>Data(53), DI18=>Data(54), DI19=>Data(55),
- DI20=>Data(56), DI21=>Data(57), DI22=>Data(58),
- DI23=>Data(59), DI24=>Data(60), DI25=>Data(61),
- DI26=>Data(62), DI27=>Data(63), DI28=>Data(64),
- DI29=>Data(65), DI30=>Data(66), DI31=>Data(67),
- DI32=>Data(68), DI33=>Data(69), DI34=>Data(70),
- DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
- ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
- ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi,
- BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock,
- CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
- ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
- ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
- ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5,
- ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55),
- DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60),
- DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65),
- DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69),
- DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37),
- DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
- DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45),
- DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49),
- DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53));
-
- FF_101: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_512x64 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:40 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x64
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[71:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x64.vhd
- VHDL template : fifo_512x64_tmpl.vhd
- VHDL testbench : tb_fifo_512x64_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x64.srp
- Estimated Resource Usage:
- LUT : 97
- EBR : 2
- Reg : 102
-
-END SCUBA Module Synthesis
-
-File: fifo_512x64.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:23:40 2011
-
--- parameterized module component declaration
-component fifo_512x64
- port (Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_512x64
- port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_512x72" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:14:05.538" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="fifo_512x72.lpc" type="lpc" modified="2011 09 22 11:14:03.000"/>
- <File name="fifo_512x72.vhd" type="top_level_vhdl" modified="2011 09 22 11:14:04.000"/>
- <File name="fifo_512x72_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:14:04.000"/>
- <File name="tb_fifo_512x72_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:14:04.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_512x72 DEFIN fifo_512x72.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1P3DX
- INSTANCE FF_42
- SUBMODULE FD1P3DX
- INSTANCE FF_43
- SUBMODULE FD1P3DX
- INSTANCE FF_44
- SUBMODULE FD1P3DX
- INSTANCE FF_45
- SUBMODULE FD1P3DX
- INSTANCE FF_46
- SUBMODULE FD1P3DX
- INSTANCE FF_47
- SUBMODULE FD1P3DX
- INSTANCE FF_48
- SUBMODULE FD1P3DX
- INSTANCE FF_49
- SUBMODULE FD1P3DX
- INSTANCE FF_50
- SUBMODULE FD1P3DX
- INSTANCE FF_51
- SUBMODULE FD1P3DX
- INSTANCE FF_52
- SUBMODULE FD1P3DX
- INSTANCE FF_53
- SUBMODULE FD1P3DX
- INSTANCE FF_54
- SUBMODULE FD1P3DX
- INSTANCE FF_55
- SUBMODULE FD1P3DX
- INSTANCE FF_56
- SUBMODULE FD1P3DX
- INSTANCE FF_57
- SUBMODULE FD1P3DX
- INSTANCE FF_58
- SUBMODULE FD1P3DX
- INSTANCE FF_59
- SUBMODULE FD1P3DX
- INSTANCE FF_60
- SUBMODULE FD1P3DX
- INSTANCE FF_61
- SUBMODULE FD1P3DX
- INSTANCE FF_62
- SUBMODULE FD1P3DX
- INSTANCE FF_63
- SUBMODULE FD1P3DX
- INSTANCE FF_64
- SUBMODULE FD1P3DX
- INSTANCE FF_65
- SUBMODULE FD1P3DX
- INSTANCE FF_66
- SUBMODULE FD1P3DX
- INSTANCE FF_67
- SUBMODULE FD1P3DX
- INSTANCE FF_68
- SUBMODULE FD1P3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3BX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3BX
- INSTANCE FF_101
- SUBMODULE PDPW16KC
- INSTANCE pdp_ram_0_1_0
- SUBMODULE PDPW16KC
- INSTANCE pdp_ram_0_0_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE OR2
- INSTANCE OR2_t18
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t19
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t20
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_512x72
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:14:03
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=512
-Width=72
-RDepth=512
-RWidth=72
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[71] i
-Data[70] i
-Data[69] i
-Data[68] i
-Data[67] i
-Data[66] i
-Data[65] i
-Data[64] i
-Data[63] i
-Data[62] i
-Data[61] i
-Data[60] i
-Data[59] i
-Data[58] i
-Data[57] i
-Data[56] i
-Data[55] i
-Data[54] i
-Data[53] i
-Data[52] i
-Data[51] i
-Data[50] i
-Data[49] i
-Data[48] i
-Data[47] i
-Data[46] i
-Data[45] i
-Data[44] i
-Data[43] i
-Data[42] i
-Data[41] i
-Data[40] i
-Data[39] i
-Data[38] i
-Data[37] i
-Data[36] i
-Data[35] i
-Data[34] i
-Data[33] i
-Data[32] i
-Data[31] i
-Data[30] i
-Data[29] i
-Data[28] i
-Data[27] i
-Data[26] i
-Data[25] i
-Data[24] i
-Data[23] i
-Data[22] i
-Data[21] i
-Data[20] i
-Data[19] i
-Data[18] i
-Data[17] i
-Data[16] i
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[71] o
-Q[70] o
-Q[69] o
-Q[68] o
-Q[67] o
-Q[66] o
-Q[65] o
-Q[64] o
-Q[63] o
-Q[62] o
-Q[61] o
-Q[60] o
-Q[59] o
-Q[58] o
-Q[57] o
-Q[56] o
-Q[55] o
-Q[54] o
-Q[53] o
-Q[52] o
-Q[51] o
-Q[50] o
-Q[49] o
-Q[48] o
-Q[47] o
-Q[46] o
-Q[45] o
-Q[44] o
-Q[43] o
-Q[42] o
-Q[41] o
-Q[40] o
-Q[39] o
-Q[38] o
-Q[37] o
-Q[36] o
-Q[35] o
-Q[34] o
-Q[33] o
-Q[32] o
-Q[31] o
-Q[30] o
-Q[29] o
-Q[28] o
-Q[27] o
-Q[26] o
-Q[25] o
-Q[24] o
-Q[23] o
-Q[22] o
-Q[21] o
-Q[20] o
-Q[19] o
-Q[18] o
-Q[17] o
-Q[16] o
-Q[15] o
-Q[14] o
-Q[13] o
-Q[12] o
-Q[11] o
-Q[10] o
-Q[9] o
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_512x72.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:14:03 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x72
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[71:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x72.vhd
- VHDL template : fifo_512x72_tmpl.vhd
- VHDL testbench : tb_fifo_512x72_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x72.srp
- Element Usage :
- AGEB2 : 10
- AND2 : 2
- CU2 : 10
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 58
- FD1S3BX : 1
- FD1S3DX : 41
- INV : 2
- OR2 : 1
- ROM16X1A : 24
- XOR2 : 18
- PDPW16KC : 2
- Estimated Resource Usage:
- LUT : 97
- EBR : 2
- Reg : 102
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:14:04 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_512x72 is
- port (
- Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x72;
-
-architecture Structure of fifo_512x72 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x72.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x72.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
- ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
- DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
- pdp_ram_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
- DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
- DI14=>Data(50), DI15=>Data(51), DI16=>Data(52),
- DI17=>Data(53), DI18=>Data(54), DI19=>Data(55),
- DI20=>Data(56), DI21=>Data(57), DI22=>Data(58),
- DI23=>Data(59), DI24=>Data(60), DI25=>Data(61),
- DI26=>Data(62), DI27=>Data(63), DI28=>Data(64),
- DI29=>Data(65), DI30=>Data(66), DI31=>Data(67),
- DI32=>Data(68), DI33=>Data(69), DI34=>Data(70),
- DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
- ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
- ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi,
- BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock,
- CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
- ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
- ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
- ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5,
- ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55),
- DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60),
- DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65),
- DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69),
- DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37),
- DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
- DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45),
- DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49),
- DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53));
-
- FF_101: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_512x72 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:14:03 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_512x72
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[71:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_512x72.vhd
- VHDL template : fifo_512x72_tmpl.vhd
- VHDL testbench : tb_fifo_512x72_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_512x72.srp
- Estimated Resource Usage:
- LUT : 97
- EBR : 2
- Reg : 102
-
-END SCUBA Module Synthesis
-
-File: fifo_512x72.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:14:04 2011
-
--- parameterized module component declaration
-component fifo_512x72
- port (Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_512x72
- port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_64kx8" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:23:05.003" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_64kx8.lpc" type="lpc" modified="2011 09 22 11:23:03.000"/>
- <File name="fifo_64kx8.vhd" type="top_level_vhdl" modified="2011 09 22 11:23:03.000"/>
- <File name="fifo_64kx8_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:23:03.000"/>
- <File name="tb_fifo_64kx8_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:23:03.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_64kx8 DEFIN fifo_64kx8.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_8
- SUBMODULE AGEB2
- INSTANCE full_cmp_7
- SUBMODULE AGEB2
- INSTANCE full_cmp_6
- SUBMODULE AGEB2
- INSTANCE full_cmp_5
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_8
- SUBMODULE AGEB2
- INSTANCE empty_cmp_7
- SUBMODULE AGEB2
- INSTANCE empty_cmp_6
- SUBMODULE AGEB2
- INSTANCE empty_cmp_5
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE MUX41
- INSTANCE mux_0
- SUBMODULE MUX41
- INSTANCE mux_1
- SUBMODULE MUX41
- INSTANCE mux_2
- SUBMODULE MUX41
- INSTANCE mux_3
- SUBMODULE MUX41
- INSTANCE mux_4
- SUBMODULE MUX41
- INSTANCE mux_5
- SUBMODULE MUX41
- INSTANCE mux_6
- SUBMODULE MUX41
- INSTANCE mux_7
- SUBMODULE CU2
- INSTANCE r_gctr_8
- SUBMODULE CU2
- INSTANCE r_gctr_7
- SUBMODULE CU2
- INSTANCE r_gctr_6
- SUBMODULE CU2
- INSTANCE r_gctr_5
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_8
- SUBMODULE CU2
- INSTANCE w_gctr_7
- SUBMODULE CU2
- INSTANCE w_gctr_6
- SUBMODULE CU2
- INSTANCE w_gctr_5
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1S3DX
- INSTANCE FF_42
- SUBMODULE FD1S3DX
- INSTANCE FF_43
- SUBMODULE FD1S3DX
- INSTANCE FF_44
- SUBMODULE FD1S3DX
- INSTANCE FF_45
- SUBMODULE FD1S3DX
- INSTANCE FF_46
- SUBMODULE FD1S3DX
- INSTANCE FF_47
- SUBMODULE FD1S3DX
- INSTANCE FF_48
- SUBMODULE FD1S3DX
- INSTANCE FF_49
- SUBMODULE FD1S3DX
- INSTANCE FF_50
- SUBMODULE FD1S3DX
- INSTANCE FF_51
- SUBMODULE FD1S3DX
- INSTANCE FF_52
- SUBMODULE FD1S3DX
- INSTANCE FF_53
- SUBMODULE FD1S3DX
- INSTANCE FF_54
- SUBMODULE FD1S3DX
- INSTANCE FF_55
- SUBMODULE FD1S3DX
- INSTANCE FF_56
- SUBMODULE FD1S3DX
- INSTANCE FF_57
- SUBMODULE FD1S3DX
- INSTANCE FF_58
- SUBMODULE FD1S3DX
- INSTANCE FF_59
- SUBMODULE FD1S3DX
- INSTANCE FF_60
- SUBMODULE FD1S3DX
- INSTANCE FF_61
- SUBMODULE FD1S3DX
- INSTANCE FF_62
- SUBMODULE FD1S3DX
- INSTANCE FF_63
- SUBMODULE FD1S3DX
- INSTANCE FF_64
- SUBMODULE FD1S3DX
- INSTANCE FF_65
- SUBMODULE FD1S3DX
- INSTANCE FF_66
- SUBMODULE FD1S3DX
- INSTANCE FF_67
- SUBMODULE FD1S3DX
- INSTANCE FF_68
- SUBMODULE FD1S3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3DX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3DX
- INSTANCE FF_101
- SUBMODULE FD1P3DX
- INSTANCE FF_102
- SUBMODULE FD1P3DX
- INSTANCE FF_103
- SUBMODULE FD1P3DX
- INSTANCE FF_104
- SUBMODULE FD1P3DX
- INSTANCE FF_105
- SUBMODULE FD1P3DX
- INSTANCE FF_106
- SUBMODULE FD1P3DX
- INSTANCE FF_107
- SUBMODULE FD1P3DX
- INSTANCE FF_108
- SUBMODULE FD1P3DX
- INSTANCE FF_109
- SUBMODULE FD1P3DX
- INSTANCE FF_110
- SUBMODULE FD1P3DX
- INSTANCE FF_111
- SUBMODULE FD1P3DX
- INSTANCE FF_112
- SUBMODULE FD1P3DX
- INSTANCE FF_113
- SUBMODULE FD1P3DX
- INSTANCE FF_114
- SUBMODULE FD1P3DX
- INSTANCE FF_115
- SUBMODULE FD1P3DX
- INSTANCE FF_116
- SUBMODULE FD1P3DX
- INSTANCE FF_117
- SUBMODULE FD1P3DX
- INSTANCE FF_118
- SUBMODULE FD1P3DX
- INSTANCE FF_119
- SUBMODULE FD1P3DX
- INSTANCE FF_120
- SUBMODULE FD1P3DX
- INSTANCE FF_121
- SUBMODULE FD1P3BX
- INSTANCE FF_122
- SUBMODULE FD1P3DX
- INSTANCE FF_123
- SUBMODULE FD1P3DX
- INSTANCE FF_124
- SUBMODULE FD1P3DX
- INSTANCE FF_125
- SUBMODULE FD1P3DX
- INSTANCE FF_126
- SUBMODULE FD1P3DX
- INSTANCE FF_127
- SUBMODULE FD1P3DX
- INSTANCE FF_128
- SUBMODULE FD1P3DX
- INSTANCE FF_129
- SUBMODULE FD1P3DX
- INSTANCE FF_130
- SUBMODULE FD1P3DX
- INSTANCE FF_131
- SUBMODULE FD1P3DX
- INSTANCE FF_132
- SUBMODULE FD1P3DX
- INSTANCE FF_133
- SUBMODULE FD1P3DX
- INSTANCE FF_134
- SUBMODULE FD1P3DX
- INSTANCE FF_135
- SUBMODULE FD1P3DX
- INSTANCE FF_136
- SUBMODULE FD1P3DX
- INSTANCE FF_137
- SUBMODULE FD1P3DX
- INSTANCE FF_138
- SUBMODULE FD1P3DX
- INSTANCE FF_139
- SUBMODULE FD1P3DX
- INSTANCE FF_140
- SUBMODULE FD1P3DX
- INSTANCE FF_141
- SUBMODULE FD1P3DX
- INSTANCE FF_142
- SUBMODULE FD1P3DX
- INSTANCE FF_143
- SUBMODULE FD1P3DX
- INSTANCE FF_144
- SUBMODULE FD1P3DX
- INSTANCE FF_145
- SUBMODULE FD1P3DX
- INSTANCE FF_146
- SUBMODULE FD1P3DX
- INSTANCE FF_147
- SUBMODULE FD1P3DX
- INSTANCE FF_148
- SUBMODULE FD1P3DX
- INSTANCE FF_149
- SUBMODULE FD1P3DX
- INSTANCE FF_150
- SUBMODULE FD1P3DX
- INSTANCE FF_151
- SUBMODULE FD1P3DX
- INSTANCE FF_152
- SUBMODULE FD1P3DX
- INSTANCE FF_153
- SUBMODULE FD1P3DX
- INSTANCE FF_154
- SUBMODULE FD1P3DX
- INSTANCE FF_155
- SUBMODULE FD1P3DX
- INSTANCE FF_156
- SUBMODULE FD1P3DX
- INSTANCE FF_157
- SUBMODULE FD1P3DX
- INSTANCE FF_158
- SUBMODULE FD1P3DX
- INSTANCE FF_159
- SUBMODULE FD1P3DX
- INSTANCE FF_160
- SUBMODULE FD1P3DX
- INSTANCE FF_161
- SUBMODULE FD1P3DX
- INSTANCE FF_162
- SUBMODULE FD1P3DX
- INSTANCE FF_163
- SUBMODULE FD1P3DX
- INSTANCE FF_164
- SUBMODULE FD1P3DX
- INSTANCE FF_165
- SUBMODULE FD1P3DX
- INSTANCE FF_166
- SUBMODULE FD1P3DX
- INSTANCE FF_167
- SUBMODULE FD1P3DX
- INSTANCE FF_168
- SUBMODULE FD1P3DX
- INSTANCE FF_169
- SUBMODULE FD1P3DX
- INSTANCE FF_170
- SUBMODULE FD1P3DX
- INSTANCE FF_171
- SUBMODULE FD1P3DX
- INSTANCE FF_172
- SUBMODULE FD1P3BX
- INSTANCE FF_173
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_7_0
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_6_1
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_5_2
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_4_3
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_3_4
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_2_5
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_1_6
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_0_7
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_7_8
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_6_9
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_5_10
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_4_11
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_3_12
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_2_13
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_1_14
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_0_15
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_7_16
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_6_17
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_5_18
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_4_19
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_3_20
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_2_21
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_1_22
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_0_23
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_7_24
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_6_25
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_5_26
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_4_27
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_3_28
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_2_29
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_1_30
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_0_31
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE ROM16X1A
- INSTANCE LUT4_24
- SUBMODULE ROM16X1A
- INSTANCE LUT4_25
- SUBMODULE ROM16X1A
- INSTANCE LUT4_26
- SUBMODULE ROM16X1A
- INSTANCE LUT4_27
- SUBMODULE ROM16X1A
- INSTANCE LUT4_28
- SUBMODULE ROM16X1A
- INSTANCE LUT4_29
- SUBMODULE ROM16X1A
- INSTANCE LUT4_30
- SUBMODULE ROM16X1A
- INSTANCE LUT4_31
- SUBMODULE ROM16X1A
- INSTANCE LUT4_32
- SUBMODULE ROM16X1A
- INSTANCE LUT4_33
- SUBMODULE ROM16X1A
- INSTANCE LUT4_34
- SUBMODULE ROM16X1A
- INSTANCE LUT4_35
- SUBMODULE ROM16X1A
- INSTANCE LUT4_36
- SUBMODULE ROM16X1A
- INSTANCE LUT4_37
- SUBMODULE ROM16X1A
- INSTANCE LUT4_38
- SUBMODULE ROM16X1A
- INSTANCE LUT4_39
- SUBMODULE ROM16X1A
- INSTANCE LUT4_40
- SUBMODULE ROM16X1A
- INSTANCE LUT4_41
- SUBMODULE ROM16X1A
- INSTANCE LUT4_42
- SUBMODULE ROM16X1A
- INSTANCE LUT4_43
- SUBMODULE ROM16X1A
- INSTANCE LUT4_44
- SUBMODULE ROM16X1A
- INSTANCE LUT4_45
- SUBMODULE ROM16X1A
- INSTANCE LUT4_46
- SUBMODULE ROM16X1A
- INSTANCE LUT4_47
- SUBMODULE ROM16X1A
- INSTANCE LUT4_48
- SUBMODULE ROM16X1A
- INSTANCE LUT4_49
- SUBMODULE ROM16X1A
- INSTANCE LUT4_50
- SUBMODULE ROM16X1A
- INSTANCE LUT4_51
- SUBMODULE ROM16X1A
- INSTANCE LUT4_52
- SUBMODULE ROM16X1A
- INSTANCE LUT4_53
- SUBMODULE ROM16X1A
- INSTANCE LUT4_54
- SUBMODULE ROM16X1A
- INSTANCE LUT4_55
- SUBMODULE ROM16X1A
- INSTANCE LUT4_56
- SUBMODULE ROM16X1A
- INSTANCE LUT4_57
- SUBMODULE ROM16X1A
- INSTANCE LUT4_58
- SUBMODULE ROM16X1A
- INSTANCE LUT4_59
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE XOR2
- INSTANCE XOR2_t18
- SUBMODULE XOR2
- INSTANCE XOR2_t19
- SUBMODULE XOR2
- INSTANCE XOR2_t20
- SUBMODULE XOR2
- INSTANCE XOR2_t21
- SUBMODULE XOR2
- INSTANCE XOR2_t22
- SUBMODULE XOR2
- INSTANCE XOR2_t23
- SUBMODULE XOR2
- INSTANCE XOR2_t24
- SUBMODULE XOR2
- INSTANCE XOR2_t25
- SUBMODULE XOR2
- INSTANCE XOR2_t26
- SUBMODULE XOR2
- INSTANCE XOR2_t27
- SUBMODULE XOR2
- INSTANCE XOR2_t28
- SUBMODULE XOR2
- INSTANCE XOR2_t29
- SUBMODULE XOR2
- INSTANCE XOR2_t30
- SUBMODULE XOR2
- INSTANCE XOR2_t31
- SUBMODULE OR2
- INSTANCE OR2_t32
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE AND2
- INSTANCE AND2_t33
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE AND2
- INSTANCE AND2_t34
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_64kx8
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:23:03
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=65536
-Width=8
-RDepth=65536
-RWidth=8
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_64kx8.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:03 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 8 -num_words 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_64kx8
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[7:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_64kx8.vhd
- VHDL template : fifo_64kx8_tmpl.vhd
- VHDL testbench : tb_fifo_64kx8_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_64kx8.srp
- Element Usage :
- AGEB2 : 18
- AND2 : 2
- CU2 : 18
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 102
- FD1S3BX : 1
- FD1S3DX : 69
- INV : 2
- MUX41 : 8
- OR2 : 1
- ROM16X1A : 60
- XOR2 : 32
- DP16KC : 32
- Estimated Resource Usage:
- LUT : 187
- EBR : 32
- Reg : 174
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 8 -depth 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:23:03 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_64kx8 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_64kx8;
-
-architecture Structure of fifo_64kx8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_9: std_logic;
- signal func_xor_inet_8: std_logic;
- signal func_xor_inet_7: std_logic;
- signal func_xor_inet_6: std_logic;
- signal func_xor_inet_10: std_logic;
- signal func_xor_inet_11: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal w_gdata_15: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wptr_15: std_logic;
- signal wptr_16: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_16: std_logic;
- signal rptr_14: std_logic;
- signal rptr_15: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal w_gcount_16: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal w_gcount_r216: std_logic;
- signal w_gcount_r16: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co6: std_logic;
- signal iwcount_16: std_logic;
- signal co8: std_logic;
- signal wcount_16: std_logic;
- signal co7: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8_1: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal wcount_r12: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal wcount_r14: std_logic;
- signal wcount_r15: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal rcount_w12: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal rcount_w14: std_logic;
- signal rcount_w15: std_logic;
- signal wcount_14: std_logic;
- signal wcount_15: std_logic;
- signal co7_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX41
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
- Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is "";
- attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is "";
- attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is "";
- attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is "";
- attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is "";
- attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is "";
- attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is "";
- attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is "";
- attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is "";
- attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is "";
- attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is "";
- attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is "";
- attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is "";
- attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is "";
- attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is "";
- attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is "";
- attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is "";
- attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is "";
- attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is "";
- attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is "";
- attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is "";
- attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is "";
- attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is "";
- attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is "";
- attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is "";
- attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is "";
- attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is "";
- attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is "";
- attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is "";
- attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is "";
- attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_64kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is "";
- attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t34: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t33: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t32: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t31: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t30: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t29: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t28: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t27: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t26: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t25: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t24: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t23: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t22: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t21: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t20: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t19: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t18: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t17: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t16: XOR2
- port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15);
-
- XOR2_t15: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t14: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t13: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t12: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t11: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t10: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t9: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t8: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t7: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t6: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t5: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t4: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t3: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t2: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t1: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t0: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- LUT4_59: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>w_gcount_r216,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_58: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_57: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_56: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_55: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r15);
-
- LUT4_54: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215,
- AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_53: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0,
- DO0=>wcount_r10);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r3);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r2);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r1);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_10);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7,
- AD1=>func_xor_inet_8, AD0=>func_xor_inet_9,
- DO0=>func_xor_inet_11);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_31: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_30: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_2_29: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_3_28: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_4_27: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_5_26: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_6_25: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_7_24: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_23: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_1_22: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_2_21: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_3_20: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_4_19: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_5_18: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_6_17: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_7_16: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_15: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_1_14: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_2_13: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_3_12: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_4_11: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_5_10: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_6_9: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_7_8: DP16KC
- generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_7: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_1_6: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_2_5: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_3_4: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_4_3: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_5_2: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_6_1: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_7_0: DP16KC
- generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open,
- DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
- DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_173: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_172: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_171: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_170: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_169: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_168: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_167: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_166: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_165: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_164: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_163: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_162: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_161: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_160: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_159: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_158: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_157: FD1P3DX
- port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_16);
-
- FF_156: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_155: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_154: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_153: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_152: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_151: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_150: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_149: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_148: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_147: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_146: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_145: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_144: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_143: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_142: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_141: FD1P3DX
- port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_140: FD1P3DX
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_16);
-
- FF_139: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_138: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_137: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_136: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_135: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_134: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_133: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_132: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_131: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_130: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_129: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_128: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_127: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_126: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_125: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_124: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_123: FD1P3DX
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_16);
-
- FF_122: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_121: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_120: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_119: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_118: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_117: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_116: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_115: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_114: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_113: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_112: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_111: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_110: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_109: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_108: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_107: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_106: FD1P3DX
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_105: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_104: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_103: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_102: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_101: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_100: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_99: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_98: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_97: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_96: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_95: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_94: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_93: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_92: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_91: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_90: FD1P3DX
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_89: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_88: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_87: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_86: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_85: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_84: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_83: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_82: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_81: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_80: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_79: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_78: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_77: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_76: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_75: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_74: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_73: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_72: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_71: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_70: FD1P3DX
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_69: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_68: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_67: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_66: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_65: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_64: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_63: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_62: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_61: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_60: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_59: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_58: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_57: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_56: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_55: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_54: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r16);
-
- FF_52: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_51: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_50: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_49: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_48: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_47: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_46: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_45: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_44: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_43: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_42: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_41: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_31: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_30: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_29: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_28: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r216);
-
- FF_18: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_17: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_16: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_15: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- w_gctr_8: CU2
- port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>iwcount_16, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1,
- NC0=>ircount_16, NC1=>open);
-
- mux_7: MUX41
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0));
-
- mux_6: MUX41
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1));
-
- mux_5: MUX41
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2));
-
- mux_4: MUX41
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3));
-
- mux_3: MUX41
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4));
-
- mux_2: MUX41
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5));
-
- mux_1: MUX41
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6));
-
- mux_0: MUX41
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12,
- B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14,
- B1=>wcount_r15, CI=>co6_2, GE=>co7_2);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14,
- B1=>rcount_w15, CI=>co6_3, GE=>co7_3);
-
- full_cmp_8: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_64kx8 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX41 use entity ecp3.MUX41(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:03 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 8 -num_words 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_64kx8
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[7:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_64kx8.vhd
- VHDL template : fifo_64kx8_tmpl.vhd
- VHDL testbench : tb_fifo_64kx8_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_64kx8.srp
- Estimated Resource Usage:
- LUT : 187
- EBR : 32
- Reg : 174
-
-END SCUBA Module Synthesis
-
-File: fifo_64kx8.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:23:03 2011
-
--- parameterized module component declaration
-component fifo_64kx8
- port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_64kx8
- port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_64kx9" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:23:22.943" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_64kx9.lpc" type="lpc" modified="2011 09 22 11:23:21.000"/>
- <File name="fifo_64kx9.vhd" type="top_level_vhdl" modified="2011 09 22 11:23:21.000"/>
- <File name="fifo_64kx9_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:23:21.000"/>
- <File name="tb_fifo_64kx9_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:23:21.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE fifo_64kx9 DEFIN fifo_64kx9.vhd
- SUBMODULE FADD2B
- INSTANCE a1
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE AGEB2
- INSTANCE full_cmp_8
- SUBMODULE AGEB2
- INSTANCE full_cmp_7
- SUBMODULE AGEB2
- INSTANCE full_cmp_6
- SUBMODULE AGEB2
- INSTANCE full_cmp_5
- SUBMODULE AGEB2
- INSTANCE full_cmp_4
- SUBMODULE AGEB2
- INSTANCE full_cmp_3
- SUBMODULE AGEB2
- INSTANCE full_cmp_2
- SUBMODULE AGEB2
- INSTANCE full_cmp_1
- SUBMODULE AGEB2
- INSTANCE full_cmp_0
- SUBMODULE FADD2B
- INSTANCE full_cmp_ci_a
- SUBMODULE FADD2B
- INSTANCE a0
- SUBMODULE AGEB2
- INSTANCE empty_cmp_8
- SUBMODULE AGEB2
- INSTANCE empty_cmp_7
- SUBMODULE AGEB2
- INSTANCE empty_cmp_6
- SUBMODULE AGEB2
- INSTANCE empty_cmp_5
- SUBMODULE AGEB2
- INSTANCE empty_cmp_4
- SUBMODULE AGEB2
- INSTANCE empty_cmp_3
- SUBMODULE AGEB2
- INSTANCE empty_cmp_2
- SUBMODULE AGEB2
- INSTANCE empty_cmp_1
- SUBMODULE AGEB2
- INSTANCE empty_cmp_0
- SUBMODULE FADD2B
- INSTANCE empty_cmp_ci_a
- SUBMODULE MUX321
- INSTANCE mux_0
- SUBMODULE MUX321
- INSTANCE mux_1
- SUBMODULE MUX321
- INSTANCE mux_2
- SUBMODULE MUX321
- INSTANCE mux_3
- SUBMODULE MUX321
- INSTANCE mux_4
- SUBMODULE MUX321
- INSTANCE mux_5
- SUBMODULE MUX321
- INSTANCE mux_6
- SUBMODULE MUX321
- INSTANCE mux_7
- SUBMODULE MUX321
- INSTANCE mux_8
- SUBMODULE CU2
- INSTANCE r_gctr_8
- SUBMODULE CU2
- INSTANCE r_gctr_7
- SUBMODULE CU2
- INSTANCE r_gctr_6
- SUBMODULE CU2
- INSTANCE r_gctr_5
- SUBMODULE CU2
- INSTANCE r_gctr_4
- SUBMODULE CU2
- INSTANCE r_gctr_3
- SUBMODULE CU2
- INSTANCE r_gctr_2
- SUBMODULE CU2
- INSTANCE r_gctr_1
- SUBMODULE CU2
- INSTANCE r_gctr_0
- SUBMODULE FADD2B
- INSTANCE r_gctr_cia
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE CU2
- INSTANCE w_gctr_8
- SUBMODULE CU2
- INSTANCE w_gctr_7
- SUBMODULE CU2
- INSTANCE w_gctr_6
- SUBMODULE CU2
- INSTANCE w_gctr_5
- SUBMODULE CU2
- INSTANCE w_gctr_4
- SUBMODULE CU2
- INSTANCE w_gctr_3
- SUBMODULE CU2
- INSTANCE w_gctr_2
- SUBMODULE CU2
- INSTANCE w_gctr_1
- SUBMODULE CU2
- INSTANCE w_gctr_0
- SUBMODULE FADD2B
- INSTANCE w_gctr_cia
- SUBMODULE FD1S3DX
- INSTANCE FF_0
- SUBMODULE FD1S3BX
- INSTANCE FF_1
- SUBMODULE FD1S3DX
- INSTANCE FF_2
- SUBMODULE FD1S3DX
- INSTANCE FF_3
- SUBMODULE FD1S3DX
- INSTANCE FF_4
- SUBMODULE FD1S3DX
- INSTANCE FF_5
- SUBMODULE FD1S3DX
- INSTANCE FF_6
- SUBMODULE FD1S3DX
- INSTANCE FF_7
- SUBMODULE FD1S3DX
- INSTANCE FF_8
- SUBMODULE FD1S3DX
- INSTANCE FF_9
- SUBMODULE FD1S3DX
- INSTANCE FF_10
- SUBMODULE FD1S3DX
- INSTANCE FF_11
- SUBMODULE FD1S3DX
- INSTANCE FF_12
- SUBMODULE FD1S3DX
- INSTANCE FF_13
- SUBMODULE FD1S3DX
- INSTANCE FF_14
- SUBMODULE FD1S3DX
- INSTANCE FF_15
- SUBMODULE FD1S3DX
- INSTANCE FF_16
- SUBMODULE FD1S3DX
- INSTANCE FF_17
- SUBMODULE FD1S3DX
- INSTANCE FF_18
- SUBMODULE FD1S3DX
- INSTANCE FF_19
- SUBMODULE FD1S3DX
- INSTANCE FF_20
- SUBMODULE FD1S3DX
- INSTANCE FF_21
- SUBMODULE FD1S3DX
- INSTANCE FF_22
- SUBMODULE FD1S3DX
- INSTANCE FF_23
- SUBMODULE FD1S3DX
- INSTANCE FF_24
- SUBMODULE FD1S3DX
- INSTANCE FF_25
- SUBMODULE FD1S3DX
- INSTANCE FF_26
- SUBMODULE FD1S3DX
- INSTANCE FF_27
- SUBMODULE FD1S3DX
- INSTANCE FF_28
- SUBMODULE FD1S3DX
- INSTANCE FF_29
- SUBMODULE FD1S3DX
- INSTANCE FF_30
- SUBMODULE FD1S3DX
- INSTANCE FF_31
- SUBMODULE FD1S3DX
- INSTANCE FF_32
- SUBMODULE FD1S3DX
- INSTANCE FF_33
- SUBMODULE FD1S3DX
- INSTANCE FF_34
- SUBMODULE FD1S3DX
- INSTANCE FF_35
- SUBMODULE FD1S3DX
- INSTANCE FF_36
- SUBMODULE FD1S3DX
- INSTANCE FF_37
- SUBMODULE FD1S3DX
- INSTANCE FF_38
- SUBMODULE FD1S3DX
- INSTANCE FF_39
- SUBMODULE FD1S3DX
- INSTANCE FF_40
- SUBMODULE FD1S3DX
- INSTANCE FF_41
- SUBMODULE FD1S3DX
- INSTANCE FF_42
- SUBMODULE FD1S3DX
- INSTANCE FF_43
- SUBMODULE FD1S3DX
- INSTANCE FF_44
- SUBMODULE FD1S3DX
- INSTANCE FF_45
- SUBMODULE FD1S3DX
- INSTANCE FF_46
- SUBMODULE FD1S3DX
- INSTANCE FF_47
- SUBMODULE FD1S3DX
- INSTANCE FF_48
- SUBMODULE FD1S3DX
- INSTANCE FF_49
- SUBMODULE FD1S3DX
- INSTANCE FF_50
- SUBMODULE FD1S3DX
- INSTANCE FF_51
- SUBMODULE FD1S3DX
- INSTANCE FF_52
- SUBMODULE FD1S3DX
- INSTANCE FF_53
- SUBMODULE FD1S3DX
- INSTANCE FF_54
- SUBMODULE FD1S3DX
- INSTANCE FF_55
- SUBMODULE FD1S3DX
- INSTANCE FF_56
- SUBMODULE FD1S3DX
- INSTANCE FF_57
- SUBMODULE FD1S3DX
- INSTANCE FF_58
- SUBMODULE FD1S3DX
- INSTANCE FF_59
- SUBMODULE FD1S3DX
- INSTANCE FF_60
- SUBMODULE FD1S3DX
- INSTANCE FF_61
- SUBMODULE FD1S3DX
- INSTANCE FF_62
- SUBMODULE FD1S3DX
- INSTANCE FF_63
- SUBMODULE FD1S3DX
- INSTANCE FF_64
- SUBMODULE FD1S3DX
- INSTANCE FF_65
- SUBMODULE FD1S3DX
- INSTANCE FF_66
- SUBMODULE FD1S3DX
- INSTANCE FF_67
- SUBMODULE FD1S3DX
- INSTANCE FF_68
- SUBMODULE FD1S3DX
- INSTANCE FF_69
- SUBMODULE FD1P3DX
- INSTANCE FF_70
- SUBMODULE FD1P3DX
- INSTANCE FF_71
- SUBMODULE FD1P3DX
- INSTANCE FF_72
- SUBMODULE FD1P3DX
- INSTANCE FF_73
- SUBMODULE FD1P3DX
- INSTANCE FF_74
- SUBMODULE FD1P3DX
- INSTANCE FF_75
- SUBMODULE FD1P3DX
- INSTANCE FF_76
- SUBMODULE FD1P3DX
- INSTANCE FF_77
- SUBMODULE FD1P3DX
- INSTANCE FF_78
- SUBMODULE FD1P3DX
- INSTANCE FF_79
- SUBMODULE FD1P3DX
- INSTANCE FF_80
- SUBMODULE FD1P3DX
- INSTANCE FF_81
- SUBMODULE FD1P3DX
- INSTANCE FF_82
- SUBMODULE FD1P3DX
- INSTANCE FF_83
- SUBMODULE FD1P3DX
- INSTANCE FF_84
- SUBMODULE FD1P3DX
- INSTANCE FF_85
- SUBMODULE FD1P3DX
- INSTANCE FF_86
- SUBMODULE FD1P3DX
- INSTANCE FF_87
- SUBMODULE FD1P3DX
- INSTANCE FF_88
- SUBMODULE FD1P3DX
- INSTANCE FF_89
- SUBMODULE FD1P3DX
- INSTANCE FF_90
- SUBMODULE FD1P3DX
- INSTANCE FF_91
- SUBMODULE FD1P3DX
- INSTANCE FF_92
- SUBMODULE FD1P3DX
- INSTANCE FF_93
- SUBMODULE FD1P3DX
- INSTANCE FF_94
- SUBMODULE FD1P3DX
- INSTANCE FF_95
- SUBMODULE FD1P3DX
- INSTANCE FF_96
- SUBMODULE FD1P3DX
- INSTANCE FF_97
- SUBMODULE FD1P3DX
- INSTANCE FF_98
- SUBMODULE FD1P3DX
- INSTANCE FF_99
- SUBMODULE FD1P3DX
- INSTANCE FF_100
- SUBMODULE FD1P3DX
- INSTANCE FF_101
- SUBMODULE FD1P3DX
- INSTANCE FF_102
- SUBMODULE FD1P3DX
- INSTANCE FF_103
- SUBMODULE FD1P3DX
- INSTANCE FF_104
- SUBMODULE FD1P3DX
- INSTANCE FF_105
- SUBMODULE FD1P3DX
- INSTANCE FF_106
- SUBMODULE FD1P3DX
- INSTANCE FF_107
- SUBMODULE FD1P3DX
- INSTANCE FF_108
- SUBMODULE FD1P3DX
- INSTANCE FF_109
- SUBMODULE FD1P3DX
- INSTANCE FF_110
- SUBMODULE FD1P3DX
- INSTANCE FF_111
- SUBMODULE FD1P3DX
- INSTANCE FF_112
- SUBMODULE FD1P3DX
- INSTANCE FF_113
- SUBMODULE FD1P3DX
- INSTANCE FF_114
- SUBMODULE FD1P3DX
- INSTANCE FF_115
- SUBMODULE FD1P3DX
- INSTANCE FF_116
- SUBMODULE FD1P3DX
- INSTANCE FF_117
- SUBMODULE FD1P3DX
- INSTANCE FF_118
- SUBMODULE FD1P3DX
- INSTANCE FF_119
- SUBMODULE FD1P3DX
- INSTANCE FF_120
- SUBMODULE FD1P3DX
- INSTANCE FF_121
- SUBMODULE FD1P3DX
- INSTANCE FF_122
- SUBMODULE FD1P3DX
- INSTANCE FF_123
- SUBMODULE FD1P3DX
- INSTANCE FF_124
- SUBMODULE FD1P3BX
- INSTANCE FF_125
- SUBMODULE FD1P3DX
- INSTANCE FF_126
- SUBMODULE FD1P3DX
- INSTANCE FF_127
- SUBMODULE FD1P3DX
- INSTANCE FF_128
- SUBMODULE FD1P3DX
- INSTANCE FF_129
- SUBMODULE FD1P3DX
- INSTANCE FF_130
- SUBMODULE FD1P3DX
- INSTANCE FF_131
- SUBMODULE FD1P3DX
- INSTANCE FF_132
- SUBMODULE FD1P3DX
- INSTANCE FF_133
- SUBMODULE FD1P3DX
- INSTANCE FF_134
- SUBMODULE FD1P3DX
- INSTANCE FF_135
- SUBMODULE FD1P3DX
- INSTANCE FF_136
- SUBMODULE FD1P3DX
- INSTANCE FF_137
- SUBMODULE FD1P3DX
- INSTANCE FF_138
- SUBMODULE FD1P3DX
- INSTANCE FF_139
- SUBMODULE FD1P3DX
- INSTANCE FF_140
- SUBMODULE FD1P3DX
- INSTANCE FF_141
- SUBMODULE FD1P3DX
- INSTANCE FF_142
- SUBMODULE FD1P3DX
- INSTANCE FF_143
- SUBMODULE FD1P3DX
- INSTANCE FF_144
- SUBMODULE FD1P3DX
- INSTANCE FF_145
- SUBMODULE FD1P3DX
- INSTANCE FF_146
- SUBMODULE FD1P3DX
- INSTANCE FF_147
- SUBMODULE FD1P3DX
- INSTANCE FF_148
- SUBMODULE FD1P3DX
- INSTANCE FF_149
- SUBMODULE FD1P3DX
- INSTANCE FF_150
- SUBMODULE FD1P3DX
- INSTANCE FF_151
- SUBMODULE FD1P3DX
- INSTANCE FF_152
- SUBMODULE FD1P3DX
- INSTANCE FF_153
- SUBMODULE FD1P3DX
- INSTANCE FF_154
- SUBMODULE FD1P3DX
- INSTANCE FF_155
- SUBMODULE FD1P3DX
- INSTANCE FF_156
- SUBMODULE FD1P3DX
- INSTANCE FF_157
- SUBMODULE FD1P3DX
- INSTANCE FF_158
- SUBMODULE FD1P3DX
- INSTANCE FF_159
- SUBMODULE FD1P3DX
- INSTANCE FF_160
- SUBMODULE FD1P3DX
- INSTANCE FF_161
- SUBMODULE FD1P3DX
- INSTANCE FF_162
- SUBMODULE FD1P3DX
- INSTANCE FF_163
- SUBMODULE FD1P3DX
- INSTANCE FF_164
- SUBMODULE FD1P3DX
- INSTANCE FF_165
- SUBMODULE FD1P3DX
- INSTANCE FF_166
- SUBMODULE FD1P3DX
- INSTANCE FF_167
- SUBMODULE FD1P3DX
- INSTANCE FF_168
- SUBMODULE FD1P3DX
- INSTANCE FF_169
- SUBMODULE FD1P3DX
- INSTANCE FF_170
- SUBMODULE FD1P3DX
- INSTANCE FF_171
- SUBMODULE FD1P3DX
- INSTANCE FF_172
- SUBMODULE FD1P3DX
- INSTANCE FF_173
- SUBMODULE FD1P3DX
- INSTANCE FF_174
- SUBMODULE FD1P3DX
- INSTANCE FF_175
- SUBMODULE FD1P3BX
- INSTANCE FF_176
- SUBMODULE DP16KC
- INSTANCE pdp_ram_31_0_0
- SUBMODULE DP16KC
- INSTANCE pdp_ram_30_0_1
- SUBMODULE DP16KC
- INSTANCE pdp_ram_29_0_2
- SUBMODULE DP16KC
- INSTANCE pdp_ram_28_0_3
- SUBMODULE DP16KC
- INSTANCE pdp_ram_27_0_4
- SUBMODULE DP16KC
- INSTANCE pdp_ram_26_0_5
- SUBMODULE DP16KC
- INSTANCE pdp_ram_25_0_6
- SUBMODULE DP16KC
- INSTANCE pdp_ram_24_0_7
- SUBMODULE DP16KC
- INSTANCE pdp_ram_23_0_8
- SUBMODULE DP16KC
- INSTANCE pdp_ram_22_0_9
- SUBMODULE DP16KC
- INSTANCE pdp_ram_21_0_10
- SUBMODULE DP16KC
- INSTANCE pdp_ram_20_0_11
- SUBMODULE DP16KC
- INSTANCE pdp_ram_19_0_12
- SUBMODULE DP16KC
- INSTANCE pdp_ram_18_0_13
- SUBMODULE DP16KC
- INSTANCE pdp_ram_17_0_14
- SUBMODULE DP16KC
- INSTANCE pdp_ram_16_0_15
- SUBMODULE DP16KC
- INSTANCE pdp_ram_15_0_16
- SUBMODULE DP16KC
- INSTANCE pdp_ram_14_0_17
- SUBMODULE DP16KC
- INSTANCE pdp_ram_13_0_18
- SUBMODULE DP16KC
- INSTANCE pdp_ram_12_0_19
- SUBMODULE DP16KC
- INSTANCE pdp_ram_11_0_20
- SUBMODULE DP16KC
- INSTANCE pdp_ram_10_0_21
- SUBMODULE DP16KC
- INSTANCE pdp_ram_9_0_22
- SUBMODULE DP16KC
- INSTANCE pdp_ram_8_0_23
- SUBMODULE DP16KC
- INSTANCE pdp_ram_7_0_24
- SUBMODULE DP16KC
- INSTANCE pdp_ram_6_0_25
- SUBMODULE DP16KC
- INSTANCE pdp_ram_5_0_26
- SUBMODULE DP16KC
- INSTANCE pdp_ram_4_0_27
- SUBMODULE DP16KC
- INSTANCE pdp_ram_3_0_28
- SUBMODULE DP16KC
- INSTANCE pdp_ram_2_0_29
- SUBMODULE DP16KC
- INSTANCE pdp_ram_1_0_30
- SUBMODULE DP16KC
- INSTANCE pdp_ram_0_0_31
- SUBMODULE ROM16X1A
- INSTANCE LUT4_0
- SUBMODULE ROM16X1A
- INSTANCE LUT4_1
- SUBMODULE ROM16X1A
- INSTANCE LUT4_2
- SUBMODULE ROM16X1A
- INSTANCE LUT4_3
- SUBMODULE ROM16X1A
- INSTANCE LUT4_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_5
- SUBMODULE ROM16X1A
- INSTANCE LUT4_6
- SUBMODULE ROM16X1A
- INSTANCE LUT4_7
- SUBMODULE ROM16X1A
- INSTANCE LUT4_8
- SUBMODULE ROM16X1A
- INSTANCE LUT4_9
- SUBMODULE ROM16X1A
- INSTANCE LUT4_10
- SUBMODULE ROM16X1A
- INSTANCE LUT4_11
- SUBMODULE ROM16X1A
- INSTANCE LUT4_12
- SUBMODULE ROM16X1A
- INSTANCE LUT4_13
- SUBMODULE ROM16X1A
- INSTANCE LUT4_14
- SUBMODULE ROM16X1A
- INSTANCE LUT4_15
- SUBMODULE ROM16X1A
- INSTANCE LUT4_16
- SUBMODULE ROM16X1A
- INSTANCE LUT4_17
- SUBMODULE ROM16X1A
- INSTANCE LUT4_18
- SUBMODULE ROM16X1A
- INSTANCE LUT4_19
- SUBMODULE ROM16X1A
- INSTANCE LUT4_20
- SUBMODULE ROM16X1A
- INSTANCE LUT4_21
- SUBMODULE ROM16X1A
- INSTANCE LUT4_22
- SUBMODULE ROM16X1A
- INSTANCE LUT4_23
- SUBMODULE ROM16X1A
- INSTANCE LUT4_24
- SUBMODULE ROM16X1A
- INSTANCE LUT4_25
- SUBMODULE ROM16X1A
- INSTANCE LUT4_26
- SUBMODULE ROM16X1A
- INSTANCE LUT4_27
- SUBMODULE ROM16X1A
- INSTANCE LUT4_28
- SUBMODULE ROM16X1A
- INSTANCE LUT4_29
- SUBMODULE ROM16X1A
- INSTANCE LUT4_30
- SUBMODULE ROM16X1A
- INSTANCE LUT4_31
- SUBMODULE ROM16X1A
- INSTANCE LUT4_32
- SUBMODULE ROM16X1A
- INSTANCE LUT4_33
- SUBMODULE ROM16X1A
- INSTANCE LUT4_34
- SUBMODULE ROM16X1A
- INSTANCE LUT4_35
- SUBMODULE ROM16X1A
- INSTANCE LUT4_36
- SUBMODULE ROM16X1A
- INSTANCE LUT4_37
- SUBMODULE ROM16X1A
- INSTANCE LUT4_38
- SUBMODULE ROM16X1A
- INSTANCE LUT4_39
- SUBMODULE ROM16X1A
- INSTANCE LUT4_40
- SUBMODULE ROM16X1A
- INSTANCE LUT4_41
- SUBMODULE ROM16X1A
- INSTANCE LUT4_42
- SUBMODULE ROM16X1A
- INSTANCE LUT4_43
- SUBMODULE ROM16X1A
- INSTANCE LUT4_44
- SUBMODULE ROM16X1A
- INSTANCE LUT4_45
- SUBMODULE ROM16X1A
- INSTANCE LUT4_46
- SUBMODULE ROM16X1A
- INSTANCE LUT4_47
- SUBMODULE ROM16X1A
- INSTANCE LUT4_48
- SUBMODULE ROM16X1A
- INSTANCE LUT4_49
- SUBMODULE ROM16X1A
- INSTANCE LUT4_50
- SUBMODULE ROM16X1A
- INSTANCE LUT4_51
- SUBMODULE ROM16X1A
- INSTANCE LUT4_52
- SUBMODULE ROM16X1A
- INSTANCE LUT4_53
- SUBMODULE ROM16X1A
- INSTANCE LUT4_54
- SUBMODULE ROM16X1A
- INSTANCE LUT4_55
- SUBMODULE ROM16X1A
- INSTANCE LUT4_56
- SUBMODULE ROM16X1A
- INSTANCE LUT4_57
- SUBMODULE ROM16X1A
- INSTANCE LUT4_58
- SUBMODULE ROM16X1A
- INSTANCE LUT4_59
- SUBMODULE ROM16X1A
- INSTANCE LUT4_60
- SUBMODULE ROM16X1A
- INSTANCE LUT4_61
- SUBMODULE ROM16X1A
- INSTANCE LUT4_62
- SUBMODULE ROM16X1A
- INSTANCE LUT4_63
- SUBMODULE ROM16X1A
- INSTANCE LUT4_64
- SUBMODULE ROM16X1A
- INSTANCE LUT4_65
- SUBMODULE ROM16X1A
- INSTANCE LUT4_66
- SUBMODULE ROM16X1A
- INSTANCE LUT4_67
- SUBMODULE ROM16X1A
- INSTANCE LUT4_68
- SUBMODULE ROM16X1A
- INSTANCE LUT4_69
- SUBMODULE ROM16X1A
- INSTANCE LUT4_70
- SUBMODULE ROM16X1A
- INSTANCE LUT4_71
- SUBMODULE ROM16X1A
- INSTANCE LUT4_72
- SUBMODULE ROM16X1A
- INSTANCE LUT4_73
- SUBMODULE ROM16X1A
- INSTANCE LUT4_74
- SUBMODULE ROM16X1A
- INSTANCE LUT4_75
- SUBMODULE ROM16X1A
- INSTANCE LUT4_76
- SUBMODULE ROM16X1A
- INSTANCE LUT4_77
- SUBMODULE ROM16X1A
- INSTANCE LUT4_78
- SUBMODULE ROM16X1A
- INSTANCE LUT4_79
- SUBMODULE ROM16X1A
- INSTANCE LUT4_80
- SUBMODULE ROM16X1A
- INSTANCE LUT4_81
- SUBMODULE ROM16X1A
- INSTANCE LUT4_82
- SUBMODULE ROM16X1A
- INSTANCE LUT4_83
- SUBMODULE ROM16X1A
- INSTANCE LUT4_84
- SUBMODULE ROM16X1A
- INSTANCE LUT4_85
- SUBMODULE ROM16X1A
- INSTANCE LUT4_86
- SUBMODULE ROM16X1A
- INSTANCE LUT4_87
- SUBMODULE ROM16X1A
- INSTANCE LUT4_88
- SUBMODULE ROM16X1A
- INSTANCE LUT4_89
- SUBMODULE ROM16X1A
- INSTANCE LUT4_90
- SUBMODULE ROM16X1A
- INSTANCE LUT4_91
- SUBMODULE ROM16X1A
- INSTANCE LUT4_92
- SUBMODULE ROM16X1A
- INSTANCE LUT4_93
- SUBMODULE ROM16X1A
- INSTANCE LUT4_94
- SUBMODULE ROM16X1A
- INSTANCE LUT4_95
- SUBMODULE ROM16X1A
- INSTANCE LUT4_96
- SUBMODULE ROM16X1A
- INSTANCE LUT4_97
- SUBMODULE ROM16X1A
- INSTANCE LUT4_98
- SUBMODULE ROM16X1A
- INSTANCE LUT4_99
- SUBMODULE ROM16X1A
- INSTANCE LUT4_100
- SUBMODULE ROM16X1A
- INSTANCE LUT4_101
- SUBMODULE ROM16X1A
- INSTANCE LUT4_102
- SUBMODULE ROM16X1A
- INSTANCE LUT4_103
- SUBMODULE ROM16X1A
- INSTANCE LUT4_104
- SUBMODULE ROM16X1A
- INSTANCE LUT4_105
- SUBMODULE ROM16X1A
- INSTANCE LUT4_106
- SUBMODULE ROM16X1A
- INSTANCE LUT4_107
- SUBMODULE ROM16X1A
- INSTANCE LUT4_108
- SUBMODULE ROM16X1A
- INSTANCE LUT4_109
- SUBMODULE ROM16X1A
- INSTANCE LUT4_110
- SUBMODULE ROM16X1A
- INSTANCE LUT4_111
- SUBMODULE ROM16X1A
- INSTANCE LUT4_112
- SUBMODULE ROM16X1A
- INSTANCE LUT4_113
- SUBMODULE ROM16X1A
- INSTANCE LUT4_114
- SUBMODULE ROM16X1A
- INSTANCE LUT4_115
- SUBMODULE ROM16X1A
- INSTANCE LUT4_116
- SUBMODULE ROM16X1A
- INSTANCE LUT4_117
- SUBMODULE ROM16X1A
- INSTANCE LUT4_118
- SUBMODULE ROM16X1A
- INSTANCE LUT4_119
- SUBMODULE ROM16X1A
- INSTANCE LUT4_120
- SUBMODULE ROM16X1A
- INSTANCE LUT4_121
- SUBMODULE ROM16X1A
- INSTANCE LUT4_122
- SUBMODULE ROM16X1A
- INSTANCE LUT4_123
- SUBMODULE ROM16X1A
- INSTANCE LUT4_124
- SUBMODULE ROM16X1A
- INSTANCE LUT4_125
- SUBMODULE ROM16X1A
- INSTANCE LUT4_126
- SUBMODULE ROM16X1A
- INSTANCE LUT4_127
- SUBMODULE ROM16X1A
- INSTANCE LUT4_128
- SUBMODULE ROM16X1A
- INSTANCE LUT4_129
- SUBMODULE ROM16X1A
- INSTANCE LUT4_130
- SUBMODULE ROM16X1A
- INSTANCE LUT4_131
- SUBMODULE ROM16X1A
- INSTANCE LUT4_132
- SUBMODULE ROM16X1A
- INSTANCE LUT4_133
- SUBMODULE ROM16X1A
- INSTANCE LUT4_134
- SUBMODULE ROM16X1A
- INSTANCE LUT4_135
- SUBMODULE ROM16X1A
- INSTANCE LUT4_136
- SUBMODULE ROM16X1A
- INSTANCE LUT4_137
- SUBMODULE ROM16X1A
- INSTANCE LUT4_138
- SUBMODULE ROM16X1A
- INSTANCE LUT4_139
- SUBMODULE ROM16X1A
- INSTANCE LUT4_140
- SUBMODULE ROM16X1A
- INSTANCE LUT4_141
- SUBMODULE ROM16X1A
- INSTANCE LUT4_142
- SUBMODULE ROM16X1A
- INSTANCE LUT4_143
- SUBMODULE ROM16X1A
- INSTANCE LUT4_144
- SUBMODULE ROM16X1A
- INSTANCE LUT4_145
- SUBMODULE ROM16X1A
- INSTANCE LUT4_146
- SUBMODULE ROM16X1A
- INSTANCE LUT4_147
- SUBMODULE ROM16X1A
- INSTANCE LUT4_148
- SUBMODULE ROM16X1A
- INSTANCE LUT4_149
- SUBMODULE ROM16X1A
- INSTANCE LUT4_150
- SUBMODULE ROM16X1A
- INSTANCE LUT4_151
- SUBMODULE ROM16X1A
- INSTANCE LUT4_152
- SUBMODULE ROM16X1A
- INSTANCE LUT4_153
- SUBMODULE ROM16X1A
- INSTANCE LUT4_154
- SUBMODULE ROM16X1A
- INSTANCE LUT4_155
- SUBMODULE ROM16X1A
- INSTANCE LUT4_156
- SUBMODULE ROM16X1A
- INSTANCE LUT4_157
- SUBMODULE ROM16X1A
- INSTANCE LUT4_158
- SUBMODULE ROM16X1A
- INSTANCE LUT4_159
- SUBMODULE ROM16X1A
- INSTANCE LUT4_160
- SUBMODULE ROM16X1A
- INSTANCE LUT4_161
- SUBMODULE ROM16X1A
- INSTANCE LUT4_162
- SUBMODULE ROM16X1A
- INSTANCE LUT4_163
- SUBMODULE ROM16X1A
- INSTANCE LUT4_164
- SUBMODULE ROM16X1A
- INSTANCE LUT4_165
- SUBMODULE ROM16X1A
- INSTANCE LUT4_166
- SUBMODULE ROM16X1A
- INSTANCE LUT4_167
- SUBMODULE ROM16X1A
- INSTANCE LUT4_168
- SUBMODULE ROM16X1A
- INSTANCE LUT4_169
- SUBMODULE ROM16X1A
- INSTANCE LUT4_170
- SUBMODULE ROM16X1A
- INSTANCE LUT4_171
- SUBMODULE ROM16X1A
- INSTANCE LUT4_172
- SUBMODULE ROM16X1A
- INSTANCE LUT4_173
- SUBMODULE ROM16X1A
- INSTANCE LUT4_174
- SUBMODULE ROM16X1A
- INSTANCE LUT4_175
- SUBMODULE ROM16X1A
- INSTANCE LUT4_176
- SUBMODULE ROM16X1A
- INSTANCE LUT4_177
- SUBMODULE ROM16X1A
- INSTANCE LUT4_178
- SUBMODULE ROM16X1A
- INSTANCE LUT4_179
- SUBMODULE ROM16X1A
- INSTANCE LUT4_180
- SUBMODULE ROM16X1A
- INSTANCE LUT4_181
- SUBMODULE ROM16X1A
- INSTANCE LUT4_182
- SUBMODULE ROM16X1A
- INSTANCE LUT4_183
- SUBMODULE ROM16X1A
- INSTANCE LUT4_184
- SUBMODULE ROM16X1A
- INSTANCE LUT4_185
- SUBMODULE INV
- INSTANCE INV_0
- SUBMODULE INV
- INSTANCE INV_1
- SUBMODULE INV
- INSTANCE INV_2
- SUBMODULE INV
- INSTANCE INV_3
- SUBMODULE INV
- INSTANCE INV_4
- SUBMODULE ROM16X1A
- INSTANCE LUT4_186
- SUBMODULE ROM16X1A
- INSTANCE LUT4_187
- SUBMODULE INV
- INSTANCE INV_5
- SUBMODULE INV
- INSTANCE INV_6
- SUBMODULE INV
- INSTANCE INV_7
- SUBMODULE INV
- INSTANCE INV_8
- SUBMODULE INV
- INSTANCE INV_9
- SUBMODULE XOR2
- INSTANCE XOR2_t0
- SUBMODULE XOR2
- INSTANCE XOR2_t1
- SUBMODULE XOR2
- INSTANCE XOR2_t2
- SUBMODULE XOR2
- INSTANCE XOR2_t3
- SUBMODULE XOR2
- INSTANCE XOR2_t4
- SUBMODULE XOR2
- INSTANCE XOR2_t5
- SUBMODULE XOR2
- INSTANCE XOR2_t6
- SUBMODULE XOR2
- INSTANCE XOR2_t7
- SUBMODULE XOR2
- INSTANCE XOR2_t8
- SUBMODULE XOR2
- INSTANCE XOR2_t9
- SUBMODULE XOR2
- INSTANCE XOR2_t10
- SUBMODULE XOR2
- INSTANCE XOR2_t11
- SUBMODULE XOR2
- INSTANCE XOR2_t12
- SUBMODULE XOR2
- INSTANCE XOR2_t13
- SUBMODULE XOR2
- INSTANCE XOR2_t14
- SUBMODULE XOR2
- INSTANCE XOR2_t15
- SUBMODULE XOR2
- INSTANCE XOR2_t16
- SUBMODULE XOR2
- INSTANCE XOR2_t17
- SUBMODULE XOR2
- INSTANCE XOR2_t18
- SUBMODULE XOR2
- INSTANCE XOR2_t19
- SUBMODULE XOR2
- INSTANCE XOR2_t20
- SUBMODULE XOR2
- INSTANCE XOR2_t21
- SUBMODULE XOR2
- INSTANCE XOR2_t22
- SUBMODULE XOR2
- INSTANCE XOR2_t23
- SUBMODULE XOR2
- INSTANCE XOR2_t24
- SUBMODULE XOR2
- INSTANCE XOR2_t25
- SUBMODULE XOR2
- INSTANCE XOR2_t26
- SUBMODULE XOR2
- INSTANCE XOR2_t27
- SUBMODULE XOR2
- INSTANCE XOR2_t28
- SUBMODULE XOR2
- INSTANCE XOR2_t29
- SUBMODULE XOR2
- INSTANCE XOR2_t30
- SUBMODULE XOR2
- INSTANCE XOR2_t31
- SUBMODULE OR2
- INSTANCE OR2_t32
- SUBMODULE INV
- INSTANCE INV_10
- SUBMODULE AND2
- INSTANCE AND2_t33
- SUBMODULE INV
- INSTANCE INV_11
- SUBMODULE AND2
- INSTANCE AND2_t34
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_64kx9
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:23:21
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=65536
-Width=9
-RDepth=65536
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WrClock i
-RdClock i
-WrEn i
-RdEn i
-Reset i
-RPReset i
-Q[8] o
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
-Empty o
-Full o
+++ /dev/null
-fifo_64kx9.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:21 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_64kx9
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_64kx9.vhd
- VHDL template : fifo_64kx9_tmpl.vhd
- VHDL testbench : tb_fifo_64kx9_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_64kx9.srp
- Element Usage :
- AGEB2 : 18
- AND2 : 2
- CU2 : 18
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 105
- FD1S3BX : 1
- FD1S3DX : 69
- INV : 12
- MUX321 : 9
- OR2 : 1
- ROM16X1A : 188
- XOR2 : 32
- DP16KC : 32
- Estimated Resource Usage:
- LUT : 379
- EBR : 32
- Reg : 177
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:23:21 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_64kx9 is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_64kx9;
-
-architecture Structure of fifo_64kx9 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal func_and_inet: std_logic;
- signal func_and_inet_1: std_logic;
- signal func_and_inet_2: std_logic;
- signal func_and_inet_3: std_logic;
- signal func_and_inet_4: std_logic;
- signal func_and_inet_5: std_logic;
- signal func_and_inet_6: std_logic;
- signal func_and_inet_7: std_logic;
- signal func_and_inet_8: std_logic;
- signal func_and_inet_9: std_logic;
- signal func_and_inet_10: std_logic;
- signal func_and_inet_11: std_logic;
- signal func_and_inet_12: std_logic;
- signal func_and_inet_13: std_logic;
- signal func_and_inet_14: std_logic;
- signal func_and_inet_15: std_logic;
- signal func_and_inet_16: std_logic;
- signal func_and_inet_17: std_logic;
- signal func_and_inet_18: std_logic;
- signal func_and_inet_19: std_logic;
- signal func_and_inet_20: std_logic;
- signal func_and_inet_21: std_logic;
- signal func_and_inet_22: std_logic;
- signal func_and_inet_23: std_logic;
- signal func_and_inet_24: std_logic;
- signal func_and_inet_25: std_logic;
- signal func_and_inet_26: std_logic;
- signal func_and_inet_27: std_logic;
- signal func_and_inet_28: std_logic;
- signal func_and_inet_29: std_logic;
- signal wptr_15_inv: std_logic;
- signal func_and_inet_30: std_logic;
- signal rptr_15_inv: std_logic;
- signal func_and_inet_31: std_logic;
- signal func_and_inet_32: std_logic;
- signal func_and_inet_33: std_logic;
- signal func_and_inet_34: std_logic;
- signal func_and_inet_35: std_logic;
- signal func_and_inet_36: std_logic;
- signal func_and_inet_37: std_logic;
- signal func_and_inet_38: std_logic;
- signal func_and_inet_39: std_logic;
- signal func_and_inet_40: std_logic;
- signal func_and_inet_41: std_logic;
- signal func_and_inet_42: std_logic;
- signal func_and_inet_43: std_logic;
- signal func_and_inet_44: std_logic;
- signal func_and_inet_45: std_logic;
- signal wptr_14_inv: std_logic;
- signal func_and_inet_46: std_logic;
- signal rptr_14_inv: std_logic;
- signal func_and_inet_47: std_logic;
- signal func_and_inet_48: std_logic;
- signal func_and_inet_49: std_logic;
- signal func_and_inet_50: std_logic;
- signal func_and_inet_51: std_logic;
- signal func_and_inet_52: std_logic;
- signal func_and_inet_53: std_logic;
- signal wptr_13_inv: std_logic;
- signal func_and_inet_54: std_logic;
- signal rptr_13_inv: std_logic;
- signal func_and_inet_55: std_logic;
- signal func_and_inet_56: std_logic;
- signal func_and_inet_57: std_logic;
- signal wptr_12_inv: std_logic;
- signal func_and_inet_58: std_logic;
- signal rptr_12_inv: std_logic;
- signal func_and_inet_59: std_logic;
- signal wptr_11_inv: std_logic;
- signal func_and_inet_60: std_logic;
- signal rptr_11_inv: std_logic;
- signal func_and_inet_61: std_logic;
- signal func_and_inet_62: std_logic;
- signal func_and_inet_63: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_9: std_logic;
- signal func_xor_inet_8: std_logic;
- signal func_xor_inet_7: std_logic;
- signal func_xor_inet_6: std_logic;
- signal func_xor_inet_10: std_logic;
- signal func_xor_inet_11: std_logic;
- signal dec1_r10: std_logic;
- signal dec0_p00: std_logic;
- signal dec3_r11: std_logic;
- signal dec2_p01: std_logic;
- signal dec5_r12: std_logic;
- signal dec4_p02: std_logic;
- signal dec7_r13: std_logic;
- signal dec6_p03: std_logic;
- signal dec9_r14: std_logic;
- signal dec8_p04: std_logic;
- signal dec11_r15: std_logic;
- signal dec10_p05: std_logic;
- signal dec13_r16: std_logic;
- signal dec12_p06: std_logic;
- signal dec15_r17: std_logic;
- signal dec14_p07: std_logic;
- signal dec17_r18: std_logic;
- signal dec16_p08: std_logic;
- signal dec19_r19: std_logic;
- signal dec18_p09: std_logic;
- signal dec21_r110: std_logic;
- signal dec20_p010: std_logic;
- signal dec23_r111: std_logic;
- signal dec22_p011: std_logic;
- signal dec25_r112: std_logic;
- signal dec24_p012: std_logic;
- signal dec27_r113: std_logic;
- signal dec26_p013: std_logic;
- signal dec29_r114: std_logic;
- signal dec28_p014: std_logic;
- signal dec31_r115: std_logic;
- signal dec30_p015: std_logic;
- signal dec33_r116: std_logic;
- signal dec32_p016: std_logic;
- signal dec35_r117: std_logic;
- signal dec34_p017: std_logic;
- signal dec37_r118: std_logic;
- signal dec36_p018: std_logic;
- signal dec39_r119: std_logic;
- signal dec38_p019: std_logic;
- signal dec41_r120: std_logic;
- signal dec40_p020: std_logic;
- signal dec43_r121: std_logic;
- signal dec42_p021: std_logic;
- signal dec45_r122: std_logic;
- signal dec44_p022: std_logic;
- signal dec47_r123: std_logic;
- signal dec46_p023: std_logic;
- signal dec49_r124: std_logic;
- signal dec48_p024: std_logic;
- signal dec51_r125: std_logic;
- signal dec50_p025: std_logic;
- signal dec53_r126: std_logic;
- signal dec52_p026: std_logic;
- signal dec55_r127: std_logic;
- signal dec54_p027: std_logic;
- signal dec57_r128: std_logic;
- signal dec56_p028: std_logic;
- signal dec59_r129: std_logic;
- signal dec58_p029: std_logic;
- signal dec61_r130: std_logic;
- signal dec60_p030: std_logic;
- signal dec63_r131: std_logic;
- signal dec62_p031: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal w_gdata_15: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wptr_15: std_logic;
- signal wptr_16: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_16: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rptr_15: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal w_gcount_16: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal w_gcount_r216: std_logic;
- signal w_gcount_r16: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co6: std_logic;
- signal iwcount_16: std_logic;
- signal co8: std_logic;
- signal wcount_16: std_logic;
- signal co7: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8_1: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_31_0: std_logic;
- signal mdout1_30_0: std_logic;
- signal mdout1_29_0: std_logic;
- signal mdout1_28_0: std_logic;
- signal mdout1_27_0: std_logic;
- signal mdout1_26_0: std_logic;
- signal mdout1_25_0: std_logic;
- signal mdout1_24_0: std_logic;
- signal mdout1_23_0: std_logic;
- signal mdout1_22_0: std_logic;
- signal mdout1_21_0: std_logic;
- signal mdout1_20_0: std_logic;
- signal mdout1_19_0: std_logic;
- signal mdout1_18_0: std_logic;
- signal mdout1_17_0: std_logic;
- signal mdout1_16_0: std_logic;
- signal mdout1_15_0: std_logic;
- signal mdout1_14_0: std_logic;
- signal mdout1_13_0: std_logic;
- signal mdout1_12_0: std_logic;
- signal mdout1_11_0: std_logic;
- signal mdout1_10_0: std_logic;
- signal mdout1_9_0: std_logic;
- signal mdout1_8_0: std_logic;
- signal mdout1_7_0: std_logic;
- signal mdout1_6_0: std_logic;
- signal mdout1_5_0: std_logic;
- signal mdout1_4_0: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_31_1: std_logic;
- signal mdout1_30_1: std_logic;
- signal mdout1_29_1: std_logic;
- signal mdout1_28_1: std_logic;
- signal mdout1_27_1: std_logic;
- signal mdout1_26_1: std_logic;
- signal mdout1_25_1: std_logic;
- signal mdout1_24_1: std_logic;
- signal mdout1_23_1: std_logic;
- signal mdout1_22_1: std_logic;
- signal mdout1_21_1: std_logic;
- signal mdout1_20_1: std_logic;
- signal mdout1_19_1: std_logic;
- signal mdout1_18_1: std_logic;
- signal mdout1_17_1: std_logic;
- signal mdout1_16_1: std_logic;
- signal mdout1_15_1: std_logic;
- signal mdout1_14_1: std_logic;
- signal mdout1_13_1: std_logic;
- signal mdout1_12_1: std_logic;
- signal mdout1_11_1: std_logic;
- signal mdout1_10_1: std_logic;
- signal mdout1_9_1: std_logic;
- signal mdout1_8_1: std_logic;
- signal mdout1_7_1: std_logic;
- signal mdout1_6_1: std_logic;
- signal mdout1_5_1: std_logic;
- signal mdout1_4_1: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_31_2: std_logic;
- signal mdout1_30_2: std_logic;
- signal mdout1_29_2: std_logic;
- signal mdout1_28_2: std_logic;
- signal mdout1_27_2: std_logic;
- signal mdout1_26_2: std_logic;
- signal mdout1_25_2: std_logic;
- signal mdout1_24_2: std_logic;
- signal mdout1_23_2: std_logic;
- signal mdout1_22_2: std_logic;
- signal mdout1_21_2: std_logic;
- signal mdout1_20_2: std_logic;
- signal mdout1_19_2: std_logic;
- signal mdout1_18_2: std_logic;
- signal mdout1_17_2: std_logic;
- signal mdout1_16_2: std_logic;
- signal mdout1_15_2: std_logic;
- signal mdout1_14_2: std_logic;
- signal mdout1_13_2: std_logic;
- signal mdout1_12_2: std_logic;
- signal mdout1_11_2: std_logic;
- signal mdout1_10_2: std_logic;
- signal mdout1_9_2: std_logic;
- signal mdout1_8_2: std_logic;
- signal mdout1_7_2: std_logic;
- signal mdout1_6_2: std_logic;
- signal mdout1_5_2: std_logic;
- signal mdout1_4_2: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_31_3: std_logic;
- signal mdout1_30_3: std_logic;
- signal mdout1_29_3: std_logic;
- signal mdout1_28_3: std_logic;
- signal mdout1_27_3: std_logic;
- signal mdout1_26_3: std_logic;
- signal mdout1_25_3: std_logic;
- signal mdout1_24_3: std_logic;
- signal mdout1_23_3: std_logic;
- signal mdout1_22_3: std_logic;
- signal mdout1_21_3: std_logic;
- signal mdout1_20_3: std_logic;
- signal mdout1_19_3: std_logic;
- signal mdout1_18_3: std_logic;
- signal mdout1_17_3: std_logic;
- signal mdout1_16_3: std_logic;
- signal mdout1_15_3: std_logic;
- signal mdout1_14_3: std_logic;
- signal mdout1_13_3: std_logic;
- signal mdout1_12_3: std_logic;
- signal mdout1_11_3: std_logic;
- signal mdout1_10_3: std_logic;
- signal mdout1_9_3: std_logic;
- signal mdout1_8_3: std_logic;
- signal mdout1_7_3: std_logic;
- signal mdout1_6_3: std_logic;
- signal mdout1_5_3: std_logic;
- signal mdout1_4_3: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_31_4: std_logic;
- signal mdout1_30_4: std_logic;
- signal mdout1_29_4: std_logic;
- signal mdout1_28_4: std_logic;
- signal mdout1_27_4: std_logic;
- signal mdout1_26_4: std_logic;
- signal mdout1_25_4: std_logic;
- signal mdout1_24_4: std_logic;
- signal mdout1_23_4: std_logic;
- signal mdout1_22_4: std_logic;
- signal mdout1_21_4: std_logic;
- signal mdout1_20_4: std_logic;
- signal mdout1_19_4: std_logic;
- signal mdout1_18_4: std_logic;
- signal mdout1_17_4: std_logic;
- signal mdout1_16_4: std_logic;
- signal mdout1_15_4: std_logic;
- signal mdout1_14_4: std_logic;
- signal mdout1_13_4: std_logic;
- signal mdout1_12_4: std_logic;
- signal mdout1_11_4: std_logic;
- signal mdout1_10_4: std_logic;
- signal mdout1_9_4: std_logic;
- signal mdout1_8_4: std_logic;
- signal mdout1_7_4: std_logic;
- signal mdout1_6_4: std_logic;
- signal mdout1_5_4: std_logic;
- signal mdout1_4_4: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_31_5: std_logic;
- signal mdout1_30_5: std_logic;
- signal mdout1_29_5: std_logic;
- signal mdout1_28_5: std_logic;
- signal mdout1_27_5: std_logic;
- signal mdout1_26_5: std_logic;
- signal mdout1_25_5: std_logic;
- signal mdout1_24_5: std_logic;
- signal mdout1_23_5: std_logic;
- signal mdout1_22_5: std_logic;
- signal mdout1_21_5: std_logic;
- signal mdout1_20_5: std_logic;
- signal mdout1_19_5: std_logic;
- signal mdout1_18_5: std_logic;
- signal mdout1_17_5: std_logic;
- signal mdout1_16_5: std_logic;
- signal mdout1_15_5: std_logic;
- signal mdout1_14_5: std_logic;
- signal mdout1_13_5: std_logic;
- signal mdout1_12_5: std_logic;
- signal mdout1_11_5: std_logic;
- signal mdout1_10_5: std_logic;
- signal mdout1_9_5: std_logic;
- signal mdout1_8_5: std_logic;
- signal mdout1_7_5: std_logic;
- signal mdout1_6_5: std_logic;
- signal mdout1_5_5: std_logic;
- signal mdout1_4_5: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_31_6: std_logic;
- signal mdout1_30_6: std_logic;
- signal mdout1_29_6: std_logic;
- signal mdout1_28_6: std_logic;
- signal mdout1_27_6: std_logic;
- signal mdout1_26_6: std_logic;
- signal mdout1_25_6: std_logic;
- signal mdout1_24_6: std_logic;
- signal mdout1_23_6: std_logic;
- signal mdout1_22_6: std_logic;
- signal mdout1_21_6: std_logic;
- signal mdout1_20_6: std_logic;
- signal mdout1_19_6: std_logic;
- signal mdout1_18_6: std_logic;
- signal mdout1_17_6: std_logic;
- signal mdout1_16_6: std_logic;
- signal mdout1_15_6: std_logic;
- signal mdout1_14_6: std_logic;
- signal mdout1_13_6: std_logic;
- signal mdout1_12_6: std_logic;
- signal mdout1_11_6: std_logic;
- signal mdout1_10_6: std_logic;
- signal mdout1_9_6: std_logic;
- signal mdout1_8_6: std_logic;
- signal mdout1_7_6: std_logic;
- signal mdout1_6_6: std_logic;
- signal mdout1_5_6: std_logic;
- signal mdout1_4_6: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_31_7: std_logic;
- signal mdout1_30_7: std_logic;
- signal mdout1_29_7: std_logic;
- signal mdout1_28_7: std_logic;
- signal mdout1_27_7: std_logic;
- signal mdout1_26_7: std_logic;
- signal mdout1_25_7: std_logic;
- signal mdout1_24_7: std_logic;
- signal mdout1_23_7: std_logic;
- signal mdout1_22_7: std_logic;
- signal mdout1_21_7: std_logic;
- signal mdout1_20_7: std_logic;
- signal mdout1_19_7: std_logic;
- signal mdout1_18_7: std_logic;
- signal mdout1_17_7: std_logic;
- signal mdout1_16_7: std_logic;
- signal mdout1_15_7: std_logic;
- signal mdout1_14_7: std_logic;
- signal mdout1_13_7: std_logic;
- signal mdout1_12_7: std_logic;
- signal mdout1_11_7: std_logic;
- signal mdout1_10_7: std_logic;
- signal mdout1_9_7: std_logic;
- signal mdout1_8_7: std_logic;
- signal mdout1_7_7: std_logic;
- signal mdout1_6_7: std_logic;
- signal mdout1_5_7: std_logic;
- signal mdout1_4_7: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal rptr_13_ff: std_logic;
- signal rptr_12_ff: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_31_8: std_logic;
- signal mdout1_30_8: std_logic;
- signal mdout1_29_8: std_logic;
- signal mdout1_28_8: std_logic;
- signal mdout1_27_8: std_logic;
- signal mdout1_26_8: std_logic;
- signal mdout1_25_8: std_logic;
- signal mdout1_24_8: std_logic;
- signal mdout1_23_8: std_logic;
- signal mdout1_22_8: std_logic;
- signal mdout1_21_8: std_logic;
- signal mdout1_20_8: std_logic;
- signal mdout1_19_8: std_logic;
- signal mdout1_18_8: std_logic;
- signal mdout1_17_8: std_logic;
- signal mdout1_16_8: std_logic;
- signal mdout1_15_8: std_logic;
- signal mdout1_14_8: std_logic;
- signal mdout1_13_8: std_logic;
- signal mdout1_12_8: std_logic;
- signal mdout1_11_8: std_logic;
- signal mdout1_10_8: std_logic;
- signal mdout1_9_8: std_logic;
- signal mdout1_8_8: std_logic;
- signal mdout1_7_8: std_logic;
- signal mdout1_6_8: std_logic;
- signal mdout1_5_8: std_logic;
- signal mdout1_4_8: std_logic;
- signal mdout1_3_8: std_logic;
- signal mdout1_2_8: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal wcount_r12: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal wcount_r14: std_logic;
- signal wcount_r15: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal rcount_w12: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal rcount_w14: std_logic;
- signal rcount_w15: std_logic;
- signal wcount_14: std_logic;
- signal wcount_15: std_logic;
- signal co7_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX321
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; D8: in std_logic;
- D9: in std_logic; D10: in std_logic; D11: in std_logic;
- D12: in std_logic; D13: in std_logic; D14: in std_logic;
- D15: in std_logic; D16: in std_logic; D17: in std_logic;
- D18: in std_logic; D19: in std_logic; D20: in std_logic;
- D21: in std_logic; D22: in std_logic; D23: in std_logic;
- D24: in std_logic; D25: in std_logic; D26: in std_logic;
- D27: in std_logic; D28: in std_logic; D29: in std_logic;
- D30: in std_logic; D31: in std_logic; SD1: in std_logic;
- SD2: in std_logic; SD3: in std_logic; SD4: in std_logic;
- SD5: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is "";
- attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is "";
- attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is "";
- attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is "";
- attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is "";
- attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is "";
- attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is "";
- attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is "";
- attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is "";
- attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is "";
- attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is "";
- attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is "";
- attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is "";
- attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is "";
- attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is "";
- attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is "";
- attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is "";
- attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is "";
- attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is "";
- attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is "";
- attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is "";
- attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is "";
- attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is "";
- attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is "";
- attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is "";
- attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is "";
- attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is "";
- attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is "";
- attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is "";
- attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is "";
- attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is "";
- attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t34: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_11: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t33: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_10: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t32: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t31: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t30: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t29: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t28: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t27: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t26: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t25: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t24: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t23: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t22: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t21: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t20: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t19: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t18: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t17: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t16: XOR2
- port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15);
-
- XOR2_t15: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t14: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t13: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t12: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t11: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t10: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t9: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t8: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t7: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t6: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t5: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t4: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t3: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t2: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t1: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t0: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- INV_9: INV
- port map (A=>wptr_11, Z=>wptr_11_inv);
-
- INV_8: INV
- port map (A=>wptr_12, Z=>wptr_12_inv);
-
- INV_7: INV
- port map (A=>wptr_13, Z=>wptr_13_inv);
-
- INV_6: INV
- port map (A=>wptr_14, Z=>wptr_14_inv);
-
- INV_5: INV
- port map (A=>wptr_15, Z=>wptr_15_inv);
-
- LUT4_187: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet);
-
- LUT4_186: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_p00);
-
- INV_4: INV
- port map (A=>rptr_11, Z=>rptr_11_inv);
-
- INV_3: INV
- port map (A=>rptr_12, Z=>rptr_12_inv);
-
- INV_2: INV
- port map (A=>rptr_13, Z=>rptr_13_inv);
-
- INV_1: INV
- port map (A=>rptr_14, Z=>rptr_14_inv);
-
- INV_0: INV
- port map (A=>rptr_15, Z=>rptr_15_inv);
-
- LUT4_185: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_1);
-
- LUT4_184: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec1_r10);
-
- LUT4_183: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_2);
-
- LUT4_182: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec2_p01);
-
- LUT4_181: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_3);
-
- LUT4_180: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec3_r11);
-
- LUT4_179: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_4);
-
- LUT4_178: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec4_p02);
-
- LUT4_177: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_5);
-
- LUT4_176: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec5_r12);
-
- LUT4_175: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_6);
-
- LUT4_174: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec6_p03);
-
- LUT4_173: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_7);
-
- LUT4_172: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec7_r13);
-
- LUT4_171: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_8);
-
- LUT4_170: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec8_p04);
-
- LUT4_169: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_9);
-
- LUT4_168: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec9_r14);
-
- LUT4_167: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_10);
-
- LUT4_166: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05);
-
- LUT4_165: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_11);
-
- LUT4_164: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15);
-
- LUT4_163: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_12);
-
- LUT4_162: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06);
-
- LUT4_161: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_13);
-
- LUT4_160: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16);
-
- LUT4_159: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_14);
-
- LUT4_158: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07);
-
- LUT4_157: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_15);
-
- LUT4_156: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17);
-
- LUT4_155: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_16);
-
- LUT4_154: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08);
-
- LUT4_153: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_17);
-
- LUT4_152: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18);
-
- LUT4_151: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_18);
-
- LUT4_150: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09);
-
- LUT4_149: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_19);
-
- LUT4_148: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19);
-
- LUT4_147: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_20);
-
- LUT4_146: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010);
-
- LUT4_145: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_21);
-
- LUT4_144: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110);
-
- LUT4_143: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_22);
-
- LUT4_142: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011);
-
- LUT4_141: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_23);
-
- LUT4_140: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111);
-
- LUT4_139: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_24);
-
- LUT4_138: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012);
-
- LUT4_137: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_25);
-
- LUT4_136: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112);
-
- LUT4_135: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_26);
-
- LUT4_134: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013);
-
- LUT4_133: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_27);
-
- LUT4_132: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113);
-
- LUT4_131: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_28);
-
- LUT4_130: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014);
-
- LUT4_129: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_29);
-
- LUT4_128: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114);
-
- LUT4_127: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
- DO0=>func_and_inet_30);
-
- LUT4_126: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015);
-
- LUT4_125: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_31);
-
- LUT4_124: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115);
-
- LUT4_123: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_32);
-
- LUT4_122: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec32_p016);
-
- LUT4_121: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_33);
-
- LUT4_120: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec33_r116);
-
- LUT4_119: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_34);
-
- LUT4_118: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec34_p017);
-
- LUT4_117: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_35);
-
- LUT4_116: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec35_r117);
-
- LUT4_115: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_36);
-
- LUT4_114: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec36_p018);
-
- LUT4_113: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_37);
-
- LUT4_112: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec37_r118);
-
- LUT4_111: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_38);
-
- LUT4_110: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec38_p019);
-
- LUT4_109: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_39);
-
- LUT4_108: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec39_r119);
-
- LUT4_107: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_40);
-
- LUT4_106: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec40_p020);
-
- LUT4_105: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_41);
-
- LUT4_104: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec41_r120);
-
- LUT4_103: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_42);
-
- LUT4_102: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec42_p021);
-
- LUT4_101: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_43);
-
- LUT4_100: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec43_r121);
-
- LUT4_99: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_44);
-
- LUT4_98: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec44_p022);
-
- LUT4_97: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_45);
-
- LUT4_96: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec45_r122);
-
- LUT4_95: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_46);
-
- LUT4_94: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec46_p023);
-
- LUT4_93: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_47);
-
- LUT4_92: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec47_r123);
-
- LUT4_91: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_48);
-
- LUT4_90: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec48_p024);
-
- LUT4_89: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_49);
-
- LUT4_88: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec49_r124);
-
- LUT4_87: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_50);
-
- LUT4_86: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec50_p025);
-
- LUT4_85: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_51);
-
- LUT4_84: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec51_r125);
-
- LUT4_83: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_52);
-
- LUT4_82: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec52_p026);
-
- LUT4_81: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_53);
-
- LUT4_80: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec53_r126);
-
- LUT4_79: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_54);
-
- LUT4_78: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec54_p027);
-
- LUT4_77: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_55);
-
- LUT4_76: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec55_r127);
-
- LUT4_75: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_56);
-
- LUT4_74: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec56_p028);
-
- LUT4_73: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_57);
-
- LUT4_72: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec57_r128);
-
- LUT4_71: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_58);
-
- LUT4_70: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec58_p029);
-
- LUT4_69: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_59);
-
- LUT4_68: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec59_r129);
-
- LUT4_67: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_60);
-
- LUT4_66: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec60_p030);
-
- LUT4_65: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_61);
-
- LUT4_64: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec61_r130);
-
- LUT4_63: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
- DO0=>func_and_inet_62);
-
- LUT4_62: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec62_p031);
-
- LUT4_61: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_63);
-
- LUT4_60: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec63_r131);
-
- LUT4_59: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>w_gcount_r216,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_58: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_57: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_56: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_55: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r15);
-
- LUT4_54: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215,
- AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_53: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0,
- DO0=>wcount_r10);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r3);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r2);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r1);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_10);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7,
- AD1=>func_xor_inet_8, AD0=>func_xor_inet_9,
- DO0=>func_xor_inet_11);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_31: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_30: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_29: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
- DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
- DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
- DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_28: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1,
- DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4,
- DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7,
- DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_4_0_27: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1,
- DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4,
- DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7,
- DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_5_0_26: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1,
- DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4,
- DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7,
- DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_6_0_25: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1,
- DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4,
- DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7,
- DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_7_0_24: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1,
- DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4,
- DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7,
- DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_8_0_23: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1,
- DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4,
- DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7,
- DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_9_0_22: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1,
- DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4,
- DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7,
- DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_10_0_21: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0,
- DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3,
- DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6,
- DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_11_0_20: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0,
- DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3,
- DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6,
- DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_12_0_19: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0,
- DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3,
- DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6,
- DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_13_0_18: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0,
- DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3,
- DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6,
- DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_14_0_17: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0,
- DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3,
- DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6,
- DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_15_0_16: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0,
- DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3,
- DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6,
- DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_16_0_15: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec32_p016, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec33_r116, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0,
- DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3,
- DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6,
- DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_17_0_14: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec34_p017, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec35_r117, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0,
- DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3,
- DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6,
- DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_18_0_13: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec36_p018, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec37_r118, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0,
- DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3,
- DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6,
- DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_19_0_12: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec38_p019, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec39_r119, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0,
- DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3,
- DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6,
- DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_20_0_11: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec40_p020, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec41_r120, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0,
- DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3,
- DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6,
- DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_21_0_10: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec42_p021, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec43_r121, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0,
- DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3,
- DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6,
- DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_22_0_9: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec44_p022, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec45_r122, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0,
- DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3,
- DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6,
- DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_23_0_8: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec46_p023, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec47_r123, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0,
- DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3,
- DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6,
- DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_24_0_7: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec48_p024, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec49_r124, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0,
- DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3,
- DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6,
- DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_25_0_6: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec50_p025, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec51_r125, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0,
- DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3,
- DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6,
- DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_26_0_5: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec52_p026, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec53_r126, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0,
- DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3,
- DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6,
- DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_27_0_4: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec54_p027, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec55_r127, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0,
- DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3,
- DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6,
- DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_28_0_3: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec56_p028, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec57_r128, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0,
- DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3,
- DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6,
- DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_29_0_2: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec58_p029, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec59_r129, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0,
- DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3,
- DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6,
- DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_30_0_1: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec60_p030, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec61_r130, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0,
- DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3,
- DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6,
- DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_31_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>dec62_p031, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i,
- WEB=>scuba_vlo, CSB0=>dec63_r131, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0,
- DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3,
- DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6,
- DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_176: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_175: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_174: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_173: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_172: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_171: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_170: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_169: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_168: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_167: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_166: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_165: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_164: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_163: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_162: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_161: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_160: FD1P3DX
- port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_16);
-
- FF_159: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_158: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_157: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_156: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_155: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_154: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_153: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_152: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_151: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_150: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_149: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_148: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_147: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_146: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_145: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_144: FD1P3DX
- port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_143: FD1P3DX
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_16);
-
- FF_142: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_141: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_140: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_139: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_138: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_137: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_136: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_135: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_134: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_133: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_132: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_131: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_130: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_129: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_128: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_127: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_126: FD1P3DX
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_16);
-
- FF_125: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_124: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_123: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_122: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_121: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_120: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_119: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_118: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_117: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_116: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_115: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_114: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_113: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_112: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_111: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_110: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_109: FD1P3DX
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_108: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_107: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_106: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_105: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_104: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_103: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_102: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_101: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_100: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_99: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_98: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_97: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_96: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_95: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_94: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_93: FD1P3DX
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_92: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_91: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_90: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_89: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_88: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_87: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_86: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_85: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_84: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_83: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_82: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_81: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_80: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_79: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_78: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_77: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_76: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_75: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_74: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_73: FD1P3DX
- port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_12_ff);
-
- FF_72: FD1P3DX
- port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_13_ff);
-
- FF_71: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_70: FD1P3DX
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_69: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_68: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_67: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_66: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_65: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_64: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_63: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_62: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_61: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_60: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_59: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_58: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_57: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_56: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_55: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_54: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r16);
-
- FF_52: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_51: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_50: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_49: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_48: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_47: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_46: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_45: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_44: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_43: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_42: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_41: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_31: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_30: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_29: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_28: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r216);
-
- FF_18: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_17: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_16: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_15: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- w_gctr_8: CU2
- port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>iwcount_16, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1,
- NC0=>ircount_16, NC1=>open);
-
- mux_8: MUX321
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
- D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
- D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
- D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0,
- D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0,
- D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0,
- D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0,
- D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0,
- D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(0));
-
- mux_7: MUX321
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
- D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
- D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
- D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1,
- D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1,
- D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1,
- D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1,
- D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1,
- D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(1));
-
- mux_6: MUX321
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
- D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
- D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
- D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2,
- D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2,
- D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2,
- D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2,
- D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2,
- D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(2));
-
- mux_5: MUX321
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
- D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
- D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
- D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3,
- D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3,
- D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3,
- D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3,
- D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3,
- D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(3));
-
- mux_4: MUX321
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
- D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
- D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
- D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4,
- D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4,
- D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4,
- D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4,
- D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4,
- D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(4));
-
- mux_3: MUX321
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
- D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
- D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
- D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5,
- D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5,
- D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5,
- D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5,
- D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5,
- D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(5));
-
- mux_2: MUX321
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
- D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
- D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
- D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6,
- D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6,
- D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6,
- D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6,
- D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6,
- D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(6));
-
- mux_1: MUX321
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
- D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
- D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
- D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7,
- D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7,
- D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7,
- D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7,
- D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7,
- D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(7));
-
- mux_0: MUX321
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
- D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
- D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
- D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8,
- D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8,
- D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8,
- D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8,
- D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8,
- D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(8));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12,
- B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14,
- B1=>wcount_r15, CI=>co6_2, GE=>co7_2);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14,
- B1=>rcount_w15, CI=>co6_3, GE=>co7_3);
-
- full_cmp_8: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_64kx9 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX321 use entity ecp3.MUX321(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:23:21 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_64kx9
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_64kx9.vhd
- VHDL template : fifo_64kx9_tmpl.vhd
- VHDL testbench : tb_fifo_64kx9_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_64kx9.srp
- Estimated Resource Usage:
- LUT : 379
- EBR : 32
- Reg : 177
-
-END SCUBA Module Synthesis
-
-File: fifo_64kx9.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:23:21 2011
-
--- parameterized module component declaration
-component fifo_64kx9
- port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_64kx9
- port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_65536x18x9
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=05/19/2012
-Time=15:06:37
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=32768
-Width=18
-RDepth=65536
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.4_Production (87)
--- Module Version: 5.4
---/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
-
--- Sat May 19 15:06:38 2012
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_65536x18x9 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_65536x18x9;
-
-architecture Structure of fifo_65536x18x9 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal func_and_inet: std_logic;
- signal func_and_inet_1: std_logic;
- signal func_and_inet_2: std_logic;
- signal func_and_inet_3: std_logic;
- signal func_and_inet_4: std_logic;
- signal func_and_inet_5: std_logic;
- signal func_and_inet_6: std_logic;
- signal func_and_inet_7: std_logic;
- signal func_and_inet_8: std_logic;
- signal func_and_inet_9: std_logic;
- signal func_and_inet_10: std_logic;
- signal func_and_inet_11: std_logic;
- signal func_and_inet_12: std_logic;
- signal func_and_inet_13: std_logic;
- signal func_and_inet_14: std_logic;
- signal func_and_inet_15: std_logic;
- signal func_and_inet_16: std_logic;
- signal func_and_inet_17: std_logic;
- signal func_and_inet_18: std_logic;
- signal func_and_inet_19: std_logic;
- signal func_and_inet_20: std_logic;
- signal func_and_inet_21: std_logic;
- signal func_and_inet_22: std_logic;
- signal func_and_inet_23: std_logic;
- signal func_and_inet_24: std_logic;
- signal func_and_inet_25: std_logic;
- signal func_and_inet_26: std_logic;
- signal func_and_inet_27: std_logic;
- signal func_and_inet_28: std_logic;
- signal func_and_inet_29: std_logic;
- signal wptr_14_inv: std_logic;
- signal func_and_inet_30: std_logic;
- signal rptr_15_inv: std_logic;
- signal func_and_inet_31: std_logic;
- signal func_and_inet_32: std_logic;
- signal func_and_inet_33: std_logic;
- signal func_and_inet_34: std_logic;
- signal func_and_inet_35: std_logic;
- signal func_and_inet_36: std_logic;
- signal func_and_inet_37: std_logic;
- signal func_and_inet_38: std_logic;
- signal func_and_inet_39: std_logic;
- signal func_and_inet_40: std_logic;
- signal func_and_inet_41: std_logic;
- signal func_and_inet_42: std_logic;
- signal func_and_inet_43: std_logic;
- signal func_and_inet_44: std_logic;
- signal func_and_inet_45: std_logic;
- signal wptr_13_inv: std_logic;
- signal func_and_inet_46: std_logic;
- signal rptr_14_inv: std_logic;
- signal func_and_inet_47: std_logic;
- signal func_and_inet_48: std_logic;
- signal func_and_inet_49: std_logic;
- signal func_and_inet_50: std_logic;
- signal func_and_inet_51: std_logic;
- signal func_and_inet_52: std_logic;
- signal func_and_inet_53: std_logic;
- signal wptr_12_inv: std_logic;
- signal func_and_inet_54: std_logic;
- signal rptr_13_inv: std_logic;
- signal func_and_inet_55: std_logic;
- signal func_and_inet_56: std_logic;
- signal func_and_inet_57: std_logic;
- signal wptr_11_inv: std_logic;
- signal func_and_inet_58: std_logic;
- signal rptr_12_inv: std_logic;
- signal func_and_inet_59: std_logic;
- signal wptr_10_inv: std_logic;
- signal func_and_inet_60: std_logic;
- signal rptr_11_inv: std_logic;
- signal func_and_inet_61: std_logic;
- signal func_and_inet_62: std_logic;
- signal func_and_inet_63: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal rcount_w0: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal dec1_r10: std_logic;
- signal dec0_p00: std_logic;
- signal dec3_r11: std_logic;
- signal dec2_p01: std_logic;
- signal dec5_r12: std_logic;
- signal dec4_p02: std_logic;
- signal dec7_r13: std_logic;
- signal dec6_p03: std_logic;
- signal dec9_r14: std_logic;
- signal dec8_p04: std_logic;
- signal dec11_r15: std_logic;
- signal dec10_p05: std_logic;
- signal dec13_r16: std_logic;
- signal dec12_p06: std_logic;
- signal dec15_r17: std_logic;
- signal dec14_p07: std_logic;
- signal dec17_r18: std_logic;
- signal dec16_p08: std_logic;
- signal dec19_r19: std_logic;
- signal dec18_p09: std_logic;
- signal dec21_r110: std_logic;
- signal dec20_p010: std_logic;
- signal dec23_r111: std_logic;
- signal dec22_p011: std_logic;
- signal dec25_r112: std_logic;
- signal dec24_p012: std_logic;
- signal dec27_r113: std_logic;
- signal dec26_p013: std_logic;
- signal dec29_r114: std_logic;
- signal dec28_p014: std_logic;
- signal dec31_r115: std_logic;
- signal dec30_p015: std_logic;
- signal dec33_r116: std_logic;
- signal dec32_p016: std_logic;
- signal dec35_r117: std_logic;
- signal dec34_p017: std_logic;
- signal dec37_r118: std_logic;
- signal dec36_p018: std_logic;
- signal dec39_r119: std_logic;
- signal dec38_p019: std_logic;
- signal dec41_r120: std_logic;
- signal dec40_p020: std_logic;
- signal dec43_r121: std_logic;
- signal dec42_p021: std_logic;
- signal dec45_r122: std_logic;
- signal dec44_p022: std_logic;
- signal dec47_r123: std_logic;
- signal dec46_p023: std_logic;
- signal dec49_r124: std_logic;
- signal dec48_p024: std_logic;
- signal dec51_r125: std_logic;
- signal dec50_p025: std_logic;
- signal dec53_r126: std_logic;
- signal dec52_p026: std_logic;
- signal dec55_r127: std_logic;
- signal dec54_p027: std_logic;
- signal dec57_r128: std_logic;
- signal dec56_p028: std_logic;
- signal dec59_r129: std_logic;
- signal dec58_p029: std_logic;
- signal dec61_r130: std_logic;
- signal dec60_p030: std_logic;
- signal dec63_r131: std_logic;
- signal dec62_p031: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wptr_15: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_16: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rptr_15: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co7: std_logic;
- signal wcount_15: std_logic;
- signal co6: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_31_0: std_logic;
- signal mdout1_30_0: std_logic;
- signal mdout1_29_0: std_logic;
- signal mdout1_28_0: std_logic;
- signal mdout1_27_0: std_logic;
- signal mdout1_26_0: std_logic;
- signal mdout1_25_0: std_logic;
- signal mdout1_24_0: std_logic;
- signal mdout1_23_0: std_logic;
- signal mdout1_22_0: std_logic;
- signal mdout1_21_0: std_logic;
- signal mdout1_20_0: std_logic;
- signal mdout1_19_0: std_logic;
- signal mdout1_18_0: std_logic;
- signal mdout1_17_0: std_logic;
- signal mdout1_16_0: std_logic;
- signal mdout1_15_0: std_logic;
- signal mdout1_14_0: std_logic;
- signal mdout1_13_0: std_logic;
- signal mdout1_12_0: std_logic;
- signal mdout1_11_0: std_logic;
- signal mdout1_10_0: std_logic;
- signal mdout1_9_0: std_logic;
- signal mdout1_8_0: std_logic;
- signal mdout1_7_0: std_logic;
- signal mdout1_6_0: std_logic;
- signal mdout1_5_0: std_logic;
- signal mdout1_4_0: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_31_1: std_logic;
- signal mdout1_30_1: std_logic;
- signal mdout1_29_1: std_logic;
- signal mdout1_28_1: std_logic;
- signal mdout1_27_1: std_logic;
- signal mdout1_26_1: std_logic;
- signal mdout1_25_1: std_logic;
- signal mdout1_24_1: std_logic;
- signal mdout1_23_1: std_logic;
- signal mdout1_22_1: std_logic;
- signal mdout1_21_1: std_logic;
- signal mdout1_20_1: std_logic;
- signal mdout1_19_1: std_logic;
- signal mdout1_18_1: std_logic;
- signal mdout1_17_1: std_logic;
- signal mdout1_16_1: std_logic;
- signal mdout1_15_1: std_logic;
- signal mdout1_14_1: std_logic;
- signal mdout1_13_1: std_logic;
- signal mdout1_12_1: std_logic;
- signal mdout1_11_1: std_logic;
- signal mdout1_10_1: std_logic;
- signal mdout1_9_1: std_logic;
- signal mdout1_8_1: std_logic;
- signal mdout1_7_1: std_logic;
- signal mdout1_6_1: std_logic;
- signal mdout1_5_1: std_logic;
- signal mdout1_4_1: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_31_2: std_logic;
- signal mdout1_30_2: std_logic;
- signal mdout1_29_2: std_logic;
- signal mdout1_28_2: std_logic;
- signal mdout1_27_2: std_logic;
- signal mdout1_26_2: std_logic;
- signal mdout1_25_2: std_logic;
- signal mdout1_24_2: std_logic;
- signal mdout1_23_2: std_logic;
- signal mdout1_22_2: std_logic;
- signal mdout1_21_2: std_logic;
- signal mdout1_20_2: std_logic;
- signal mdout1_19_2: std_logic;
- signal mdout1_18_2: std_logic;
- signal mdout1_17_2: std_logic;
- signal mdout1_16_2: std_logic;
- signal mdout1_15_2: std_logic;
- signal mdout1_14_2: std_logic;
- signal mdout1_13_2: std_logic;
- signal mdout1_12_2: std_logic;
- signal mdout1_11_2: std_logic;
- signal mdout1_10_2: std_logic;
- signal mdout1_9_2: std_logic;
- signal mdout1_8_2: std_logic;
- signal mdout1_7_2: std_logic;
- signal mdout1_6_2: std_logic;
- signal mdout1_5_2: std_logic;
- signal mdout1_4_2: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_31_3: std_logic;
- signal mdout1_30_3: std_logic;
- signal mdout1_29_3: std_logic;
- signal mdout1_28_3: std_logic;
- signal mdout1_27_3: std_logic;
- signal mdout1_26_3: std_logic;
- signal mdout1_25_3: std_logic;
- signal mdout1_24_3: std_logic;
- signal mdout1_23_3: std_logic;
- signal mdout1_22_3: std_logic;
- signal mdout1_21_3: std_logic;
- signal mdout1_20_3: std_logic;
- signal mdout1_19_3: std_logic;
- signal mdout1_18_3: std_logic;
- signal mdout1_17_3: std_logic;
- signal mdout1_16_3: std_logic;
- signal mdout1_15_3: std_logic;
- signal mdout1_14_3: std_logic;
- signal mdout1_13_3: std_logic;
- signal mdout1_12_3: std_logic;
- signal mdout1_11_3: std_logic;
- signal mdout1_10_3: std_logic;
- signal mdout1_9_3: std_logic;
- signal mdout1_8_3: std_logic;
- signal mdout1_7_3: std_logic;
- signal mdout1_6_3: std_logic;
- signal mdout1_5_3: std_logic;
- signal mdout1_4_3: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_31_4: std_logic;
- signal mdout1_30_4: std_logic;
- signal mdout1_29_4: std_logic;
- signal mdout1_28_4: std_logic;
- signal mdout1_27_4: std_logic;
- signal mdout1_26_4: std_logic;
- signal mdout1_25_4: std_logic;
- signal mdout1_24_4: std_logic;
- signal mdout1_23_4: std_logic;
- signal mdout1_22_4: std_logic;
- signal mdout1_21_4: std_logic;
- signal mdout1_20_4: std_logic;
- signal mdout1_19_4: std_logic;
- signal mdout1_18_4: std_logic;
- signal mdout1_17_4: std_logic;
- signal mdout1_16_4: std_logic;
- signal mdout1_15_4: std_logic;
- signal mdout1_14_4: std_logic;
- signal mdout1_13_4: std_logic;
- signal mdout1_12_4: std_logic;
- signal mdout1_11_4: std_logic;
- signal mdout1_10_4: std_logic;
- signal mdout1_9_4: std_logic;
- signal mdout1_8_4: std_logic;
- signal mdout1_7_4: std_logic;
- signal mdout1_6_4: std_logic;
- signal mdout1_5_4: std_logic;
- signal mdout1_4_4: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_31_5: std_logic;
- signal mdout1_30_5: std_logic;
- signal mdout1_29_5: std_logic;
- signal mdout1_28_5: std_logic;
- signal mdout1_27_5: std_logic;
- signal mdout1_26_5: std_logic;
- signal mdout1_25_5: std_logic;
- signal mdout1_24_5: std_logic;
- signal mdout1_23_5: std_logic;
- signal mdout1_22_5: std_logic;
- signal mdout1_21_5: std_logic;
- signal mdout1_20_5: std_logic;
- signal mdout1_19_5: std_logic;
- signal mdout1_18_5: std_logic;
- signal mdout1_17_5: std_logic;
- signal mdout1_16_5: std_logic;
- signal mdout1_15_5: std_logic;
- signal mdout1_14_5: std_logic;
- signal mdout1_13_5: std_logic;
- signal mdout1_12_5: std_logic;
- signal mdout1_11_5: std_logic;
- signal mdout1_10_5: std_logic;
- signal mdout1_9_5: std_logic;
- signal mdout1_8_5: std_logic;
- signal mdout1_7_5: std_logic;
- signal mdout1_6_5: std_logic;
- signal mdout1_5_5: std_logic;
- signal mdout1_4_5: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_31_6: std_logic;
- signal mdout1_30_6: std_logic;
- signal mdout1_29_6: std_logic;
- signal mdout1_28_6: std_logic;
- signal mdout1_27_6: std_logic;
- signal mdout1_26_6: std_logic;
- signal mdout1_25_6: std_logic;
- signal mdout1_24_6: std_logic;
- signal mdout1_23_6: std_logic;
- signal mdout1_22_6: std_logic;
- signal mdout1_21_6: std_logic;
- signal mdout1_20_6: std_logic;
- signal mdout1_19_6: std_logic;
- signal mdout1_18_6: std_logic;
- signal mdout1_17_6: std_logic;
- signal mdout1_16_6: std_logic;
- signal mdout1_15_6: std_logic;
- signal mdout1_14_6: std_logic;
- signal mdout1_13_6: std_logic;
- signal mdout1_12_6: std_logic;
- signal mdout1_11_6: std_logic;
- signal mdout1_10_6: std_logic;
- signal mdout1_9_6: std_logic;
- signal mdout1_8_6: std_logic;
- signal mdout1_7_6: std_logic;
- signal mdout1_6_6: std_logic;
- signal mdout1_5_6: std_logic;
- signal mdout1_4_6: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_31_7: std_logic;
- signal mdout1_30_7: std_logic;
- signal mdout1_29_7: std_logic;
- signal mdout1_28_7: std_logic;
- signal mdout1_27_7: std_logic;
- signal mdout1_26_7: std_logic;
- signal mdout1_25_7: std_logic;
- signal mdout1_24_7: std_logic;
- signal mdout1_23_7: std_logic;
- signal mdout1_22_7: std_logic;
- signal mdout1_21_7: std_logic;
- signal mdout1_20_7: std_logic;
- signal mdout1_19_7: std_logic;
- signal mdout1_18_7: std_logic;
- signal mdout1_17_7: std_logic;
- signal mdout1_16_7: std_logic;
- signal mdout1_15_7: std_logic;
- signal mdout1_14_7: std_logic;
- signal mdout1_13_7: std_logic;
- signal mdout1_12_7: std_logic;
- signal mdout1_11_7: std_logic;
- signal mdout1_10_7: std_logic;
- signal mdout1_9_7: std_logic;
- signal mdout1_8_7: std_logic;
- signal mdout1_7_7: std_logic;
- signal mdout1_6_7: std_logic;
- signal mdout1_5_7: std_logic;
- signal mdout1_4_7: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal rptr_13_ff: std_logic;
- signal rptr_12_ff: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_31_8: std_logic;
- signal mdout1_30_8: std_logic;
- signal mdout1_29_8: std_logic;
- signal mdout1_28_8: std_logic;
- signal mdout1_27_8: std_logic;
- signal mdout1_26_8: std_logic;
- signal mdout1_25_8: std_logic;
- signal mdout1_24_8: std_logic;
- signal mdout1_23_8: std_logic;
- signal mdout1_22_8: std_logic;
- signal mdout1_21_8: std_logic;
- signal mdout1_20_8: std_logic;
- signal mdout1_19_8: std_logic;
- signal mdout1_18_8: std_logic;
- signal mdout1_17_8: std_logic;
- signal mdout1_16_8: std_logic;
- signal mdout1_15_8: std_logic;
- signal mdout1_14_8: std_logic;
- signal mdout1_13_8: std_logic;
- signal mdout1_12_8: std_logic;
- signal mdout1_11_8: std_logic;
- signal mdout1_10_8: std_logic;
- signal mdout1_9_8: std_logic;
- signal mdout1_8_8: std_logic;
- signal mdout1_7_8: std_logic;
- signal mdout1_6_8: std_logic;
- signal mdout1_5_8: std_logic;
- signal mdout1_4_8: std_logic;
- signal mdout1_3_8: std_logic;
- signal mdout1_2_8: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r7: std_logic;
- signal wcount_r8: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal wcount_r11: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal wcount_r13: std_logic;
- signal wcount_r14: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w7: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w9: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w11: std_logic;
- signal rcount_w12: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w14: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal rcount_w15: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_14: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX321
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; D8: in std_logic;
- D9: in std_logic; D10: in std_logic; D11: in std_logic;
- D12: in std_logic; D13: in std_logic; D14: in std_logic;
- D15: in std_logic; D16: in std_logic; D17: in std_logic;
- D18: in std_logic; D19: in std_logic; D20: in std_logic;
- D21: in std_logic; D22: in std_logic; D23: in std_logic;
- D24: in std_logic; D25: in std_logic; D26: in std_logic;
- D27: in std_logic; D28: in std_logic; D29: in std_logic;
- D30: in std_logic; D31: in std_logic; SD1: in std_logic;
- SD2: in std_logic; SD3: in std_logic; SD4: in std_logic;
- SD5: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is "";
- attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is "";
- attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is "";
- attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is "";
- attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is "";
- attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is "";
- attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is "";
- attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is "";
- attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is "";
- attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is "";
- attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is "";
- attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is "";
- attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is "";
- attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is "";
- attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is "";
- attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is "";
- attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is "";
- attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is "";
- attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is "";
- attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is "";
- attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is "";
- attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is "";
- attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is "";
- attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is "";
- attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is "";
- attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is "";
- attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is "";
- attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is "";
- attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is "";
- attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is "";
- attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_65536x18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is "";
- attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t33: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_11: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t32: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_10: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t31: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t30: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t29: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t28: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t27: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t26: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t25: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t24: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t23: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t22: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t21: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t20: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t19: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t18: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t17: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t16: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t15: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t14: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t13: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t12: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t11: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t10: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t9: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t8: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t7: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t6: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t5: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t4: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t3: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t2: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t1: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t0: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- INV_9: INV
- port map (A=>wptr_10, Z=>wptr_10_inv);
-
- INV_8: INV
- port map (A=>wptr_11, Z=>wptr_11_inv);
-
- INV_7: INV
- port map (A=>wptr_12, Z=>wptr_12_inv);
-
- INV_6: INV
- port map (A=>wptr_13, Z=>wptr_13_inv);
-
- INV_5: INV
- port map (A=>wptr_14, Z=>wptr_14_inv);
-
- LUT4_180: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet);
-
- LUT4_179: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_p00);
-
- INV_4: INV
- port map (A=>rptr_11, Z=>rptr_11_inv);
-
- INV_3: INV
- port map (A=>rptr_12, Z=>rptr_12_inv);
-
- INV_2: INV
- port map (A=>rptr_13, Z=>rptr_13_inv);
-
- INV_1: INV
- port map (A=>rptr_14, Z=>rptr_14_inv);
-
- INV_0: INV
- port map (A=>rptr_15, Z=>rptr_15_inv);
-
- LUT4_178: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_1);
-
- LUT4_177: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec1_r10);
-
- LUT4_176: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_2);
-
- LUT4_175: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec2_p01);
-
- LUT4_174: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_3);
-
- LUT4_173: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec3_r11);
-
- LUT4_172: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_4);
-
- LUT4_171: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec4_p02);
-
- LUT4_170: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_5);
-
- LUT4_169: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec5_r12);
-
- LUT4_168: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_6);
-
- LUT4_167: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec6_p03);
-
- LUT4_166: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_7);
-
- LUT4_165: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec7_r13);
-
- LUT4_164: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_8);
-
- LUT4_163: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec8_p04);
-
- LUT4_162: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_9);
-
- LUT4_161: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec9_r14);
-
- LUT4_160: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_10);
-
- LUT4_159: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05);
-
- LUT4_158: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_11);
-
- LUT4_157: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15);
-
- LUT4_156: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_12);
-
- LUT4_155: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06);
-
- LUT4_154: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_13);
-
- LUT4_153: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16);
-
- LUT4_152: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_14);
-
- LUT4_151: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07);
-
- LUT4_150: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_15);
-
- LUT4_149: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17);
-
- LUT4_148: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_16);
-
- LUT4_147: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08);
-
- LUT4_146: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_17);
-
- LUT4_145: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18);
-
- LUT4_144: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_18);
-
- LUT4_143: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09);
-
- LUT4_142: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_19);
-
- LUT4_141: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19);
-
- LUT4_140: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_20);
-
- LUT4_139: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010);
-
- LUT4_138: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_21);
-
- LUT4_137: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110);
-
- LUT4_136: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_22);
-
- LUT4_135: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011);
-
- LUT4_134: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_23);
-
- LUT4_133: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111);
-
- LUT4_132: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_24);
-
- LUT4_131: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012);
-
- LUT4_130: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_25);
-
- LUT4_129: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112);
-
- LUT4_128: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_26);
-
- LUT4_127: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013);
-
- LUT4_126: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_27);
-
- LUT4_125: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113);
-
- LUT4_124: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_28);
-
- LUT4_123: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014);
-
- LUT4_122: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_29);
-
- LUT4_121: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114);
-
- LUT4_120: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
- DO0=>func_and_inet_30);
-
- LUT4_119: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015);
-
- LUT4_118: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_31);
-
- LUT4_117: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115);
-
- LUT4_116: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_32);
-
- LUT4_115: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec32_p016);
-
- LUT4_114: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_33);
-
- LUT4_113: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec33_r116);
-
- LUT4_112: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_34);
-
- LUT4_111: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec34_p017);
-
- LUT4_110: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_35);
-
- LUT4_109: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec35_r117);
-
- LUT4_108: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_36);
-
- LUT4_107: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec36_p018);
-
- LUT4_106: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_37);
-
- LUT4_105: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec37_r118);
-
- LUT4_104: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_38);
-
- LUT4_103: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec38_p019);
-
- LUT4_102: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_39);
-
- LUT4_101: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec39_r119);
-
- LUT4_100: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_40);
-
- LUT4_99: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec40_p020);
-
- LUT4_98: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_41);
-
- LUT4_97: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec41_r120);
-
- LUT4_96: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_42);
-
- LUT4_95: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec42_p021);
-
- LUT4_94: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_43);
-
- LUT4_93: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec43_r121);
-
- LUT4_92: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_44);
-
- LUT4_91: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec44_p022);
-
- LUT4_90: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_45);
-
- LUT4_89: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec45_r122);
-
- LUT4_88: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_46);
-
- LUT4_87: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec46_p023);
-
- LUT4_86: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_47);
-
- LUT4_85: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec47_r123);
-
- LUT4_84: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_48);
-
- LUT4_83: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec48_p024);
-
- LUT4_82: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_49);
-
- LUT4_81: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec49_r124);
-
- LUT4_80: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_50);
-
- LUT4_79: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec50_p025);
-
- LUT4_78: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_51);
-
- LUT4_77: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec51_r125);
-
- LUT4_76: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_52);
-
- LUT4_75: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec52_p026);
-
- LUT4_74: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_53);
-
- LUT4_73: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec53_r126);
-
- LUT4_72: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_54);
-
- LUT4_71: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec54_p027);
-
- LUT4_70: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_55);
-
- LUT4_69: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec55_r127);
-
- LUT4_68: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_56);
-
- LUT4_67: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec56_p028);
-
- LUT4_66: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_57);
-
- LUT4_65: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec57_r128);
-
- LUT4_64: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_58);
-
- LUT4_63: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec58_p029);
-
- LUT4_62: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_59);
-
- LUT4_61: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec59_r129);
-
- LUT4_60: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_60);
-
- LUT4_59: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec60_p030);
-
- LUT4_58: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_61);
-
- LUT4_57: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec61_r130);
-
- LUT4_56: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
- DO0=>func_and_inet_62);
-
- LUT4_55: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec62_p031);
-
- LUT4_54: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_63);
-
- LUT4_53: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec63_r131);
-
- LUT4_52: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_51: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_50: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_49: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_48: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_47: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_46: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_45: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_44: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9);
-
- LUT4_43: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_42: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_41: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6);
-
- LUT4_40: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_39: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_38: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_37: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3);
-
- LUT4_36: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_35: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r2);
-
- LUT4_34: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r1);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_31: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_30: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_29: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
- DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
- DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
- DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_28: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1,
- DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4,
- DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7,
- DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_4_0_27: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1,
- DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4,
- DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7,
- DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_5_0_26: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1,
- DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4,
- DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7,
- DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_6_0_25: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1,
- DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4,
- DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7,
- DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_7_0_24: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1,
- DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4,
- DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7,
- DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_8_0_23: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1,
- DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4,
- DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7,
- DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_9_0_22: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1,
- DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4,
- DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7,
- DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_10_0_21: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1,
- DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4,
- DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7,
- DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_11_0_20: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1,
- DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4,
- DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7,
- DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_12_0_19: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1,
- DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4,
- DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7,
- DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_13_0_18: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1,
- DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4,
- DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7,
- DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_14_0_17: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1,
- DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4,
- DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7,
- DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_15_0_16: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1,
- DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4,
- DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7,
- DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_16_0_15: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1,
- DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4,
- DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7,
- DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_17_0_14: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1,
- DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4,
- DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7,
- DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_18_0_13: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1,
- DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4,
- DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7,
- DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_19_0_12: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1,
- DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4,
- DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7,
- DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_20_0_11: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1,
- DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4,
- DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7,
- DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_21_0_10: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1,
- DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4,
- DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7,
- DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_22_0_9: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1,
- DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4,
- DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7,
- DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_23_0_8: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1,
- DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4,
- DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7,
- DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_24_0_7: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1,
- DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4,
- DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7,
- DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_25_0_6: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1,
- DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4,
- DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7,
- DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_26_0_5: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1,
- DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4,
- DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7,
- DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_27_0_4: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1,
- DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4,
- DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7,
- DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_28_0_3: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1,
- DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4,
- DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7,
- DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_29_0_2: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1,
- DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4,
- DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7,
- DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_30_0_1: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1,
- DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4,
- DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7,
- DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_31_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1,
- DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4,
- DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7,
- DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_171: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_170: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_169: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_168: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_167: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_166: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_165: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_164: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_163: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_162: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_161: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_160: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_159: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_158: FD1P3DX
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_157: FD1P3DX
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_156: FD1P3DX
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_155: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_154: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_153: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_152: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_151: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_150: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_149: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_148: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_147: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_146: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_145: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_144: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_143: FD1P3DX
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_142: FD1P3DX
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_141: FD1P3DX
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_140: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_139: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_138: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_137: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_136: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_135: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_134: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_133: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_132: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_131: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_130: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_129: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_128: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_127: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_126: FD1P3DX
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_125: FD1P3DX
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_124: FD1P3DX
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_123: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_122: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_121: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_120: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_119: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_118: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_117: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_116: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_115: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_114: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_113: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_112: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_111: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_110: FD1P3DX
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_109: FD1P3DX
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_108: FD1P3DX
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_107: FD1P3DX
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_106: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_105: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_104: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_103: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_102: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_101: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_100: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_99: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_98: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_97: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_96: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_95: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_94: FD1P3DX
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_93: FD1P3DX
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_92: FD1P3DX
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_91: FD1P3DX
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_90: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_89: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_88: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_87: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_86: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_85: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_84: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_83: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_82: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_81: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_80: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_79: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_78: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_77: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_76: FD1P3DX
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_75: FD1P3DX
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_74: FD1P3DX
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_73: FD1P3DX
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_72: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_71: FD1P3DX
- port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_12_ff);
-
- FF_70: FD1P3DX
- port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_13_ff);
-
- FF_69: FD1P3DX
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_68: FD1P3DX
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_67: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_66: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_65: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_64: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_63: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_62: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_61: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_60: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_59: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_58: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_57: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_56: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_55: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_54: FD1S3DX
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_52: FD1S3DX
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_51: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_50: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_49: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_48: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_47: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_46: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_45: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_44: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_43: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_42: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_41: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_31: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_30: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_29: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_28: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_18: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_17: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_16: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_15: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>ircount_16, NC1=>open);
-
- mux_8: MUX321
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
- D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
- D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
- D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0,
- D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0,
- D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0,
- D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0,
- D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0,
- D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(0));
-
- mux_7: MUX321
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
- D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
- D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
- D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1,
- D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1,
- D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1,
- D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1,
- D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1,
- D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(1));
-
- mux_6: MUX321
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
- D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
- D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
- D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2,
- D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2,
- D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2,
- D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2,
- D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2,
- D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(2));
-
- mux_5: MUX321
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
- D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
- D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
- D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3,
- D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3,
- D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3,
- D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3,
- D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3,
- D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(3));
-
- mux_4: MUX321
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
- D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
- D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
- D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4,
- D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4,
- D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4,
- D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4,
- D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4,
- D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(4));
-
- mux_3: MUX321
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
- D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
- D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
- D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5,
- D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5,
- D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5,
- D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5,
- D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5,
- D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(5));
-
- mux_2: MUX321
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
- D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
- D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
- D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6,
- D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6,
- D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6,
- D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6,
- D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6,
- D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(6));
-
- mux_1: MUX321
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
- D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
- D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
- D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7,
- D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7,
- D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7,
- D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7,
- D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7,
- D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(7));
-
- mux_0: MUX321
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
- D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
- D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
- D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8,
- D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8,
- D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8,
- D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8,
- D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8,
- D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(8));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
- B1=>wcount_r8, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11,
- B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13,
- B1=>wcount_r14, CI=>co6_2, GE=>co7_2);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>rcount_w8, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
- B1=>rcount_w10, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11,
- B1=>rcount_w12, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w14, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15,
- B1=>full_cmp_clr, CI=>co6_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_65536x18x9 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX321 use entity ecp3.MUX321(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="ip_mem" module="RAM_DP_TRUE" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:24:38.281" version="7.1" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="ip_mem.lpc" type="lpc" modified="2011 09 22 11:24:37.000"/>
- <File name="ip_mem.mem" type="mem" modified="2011 09 22 11:21:25.000"/>
- <File name="ip_mem.vhd" type="top_level_vhdl" modified="2011 09 22 11:24:37.000"/>
- <File name="ip_mem_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:24:37.000"/>
- <File name="tb_ip_mem_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:24:37.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE ip_mem DEFIN ip_mem.vhd
- SUBMODULE DP16KC
- INSTANCE ip_mem_0_1_0
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
- SUBMODULE DP16KC
- INSTANCE ip_mem_0_0_1
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP_TRUE
-CoreRevision=7.1
-ModuleName=ip_mem
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:24:37
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-AAddress=256
-BAddress=256
-AData=32
-BData=32
-enByte=0
-ByteSize=9
-AadPipeline=0
-BadPipeline=0
-AinPipeline=0
-BinPipeline=0
-AoutPipeline=0
-BoutPipeline=1
-AMOR=0
-BMOR=0
-AInData=Registered
-BInData=Registered
-AAdControl=Registered
-BAdControl=Registered
-MemFile=ip_mem.mem
-MemFormat=orca
-Reset=Sync
-GSR=Enabled
-WriteA=Normal
-WriteB=Normal
-Pad=0
-EnECC=0
-Optimization=Speed
-Pipeline=0
-
-[FilesGenerated]
-ip_mem.mem=mem
+++ /dev/null
-#Format=Address-Hex\r
-#Depth=256\r
-#DataWidth=32\r
-#AddrRadix=3\r
-#DataRadix=3\r
-\r
-00: 214397e9\r
-01: 0000001b\r
-02: c0a80002\r
-03: 0000c350\r
-04: 023bdc00\r
-05: 00000013\r
-06: c0a80005\r
-07: 0000c350\r
-08: 00000578\r
-09: 00000000\r
-0a: 00000000\r
-0b: 00000000\r
-0c: 00000000\r
-0d: 00000000\r
-0e: 00000000\r
-0f: 00000000\r
-\r
-10: 214397e9\r
-11: 0000001b\r
-12: c0a80002\r
-13: 0000c351\r
-14: 023bdc01\r
-15: 00000013\r
-16: c0a80006\r
-17: 0000c350\r
-18: 00000578\r
-19: 00000000\r
-1a: 00000000\r
-1b: 00000000\r
-1c: 00000000\r
-1d: 00000000\r
-1e: 00000000\r
-1f: 00000000\r
-\r
-20: 214397e9\r
-21: 0000001b\r
-22: c0a80002\r
-23: 0000c352\r
-24: 023bdc02\r
-25: 00000013\r
-26: c0a80007\r
-27: 0000c350\r
-28: 00000578\r
-29: 00000000\r
-2a: 00000000\r
-2b: 00000000\r
-2c: 00000000\r
-2d: 00000000\r
-2e: 00000000\r
-2f: 00000000\r
-\r
-30: 214397e9\r
-31: 0000001b\r
-32: c0a80002\r
-33: 0000c353\r
-34: 023bdc03\r
-35: 00000013\r
-36: c0a80008\r
-37: 0000c350\r
-38: 00000578\r
-39: 00000000\r
-3a: 00000000\r
-3b: 00000000\r
-3c: 00000000\r
-3d: 00000000\r
-3e: 00000000\r
-3f: 00000000\r
-\r
-40: 00000000\r
-41: 00000000\r
-42: 00000000\r
-43: 00000000\r
-44: 00000000\r
-45: 00000000\r
-46: 00000000\r
-47: 00000000\r
-48: 00000578\r
-49: 00000000\r
-4a: 00000000\r
-4b: 00000000\r
-4c: 00000000\r
-4d: 00000000\r
-4e: 00000000\r
-4f: 00000000\r
-\r
-50: 00000000\r
-51: 00000000\r
-52: 00000000\r
-53: 00000000\r
-54: 00000000\r
-55: 00000000\r
-56: 00000000\r
-57: 00000000\r
-58: 00000578\r
-59: 00000000\r
-5a: 00000000\r
-5b: 00000000\r
-5c: 00000000\r
-5d: 00000000\r
-5e: 00000000\r
-5f: 00000000\r
-\r
-60: 00000000\r
-61: 00000000\r
-62: 00000000\r
-63: 00000000\r
-64: 00000000\r
-65: 00000000\r
-66: 00000000\r
-67: 00000000\r
-68: 00000578\r
-69: 00000000\r
-6a: 00000000\r
-6b: 00000000\r
-6c: 00000000\r
-6d: 00000000\r
-6e: 00000000\r
-6f: 00000000\r
-\r
-70: 00000000\r
-71: 00000000\r
-72: 00000000\r
-73: 00000000\r
-74: 00000000\r
-75: 00000000\r
-76: 00000000\r
-77: 00000000\r
-78: 00000578\r
-79: 00000000\r
-7a: 00000000\r
-7b: 00000000\r
-7c: 00000000\r
-7d: 00000000\r
-7e: 00000000\r
-7f: 00000000\r
-\r
-80: 00000000\r
-81: 00000000\r
-82: 00000000\r
-83: 00000000\r
-84: 00000000\r
-85: 00000000\r
-86: 00000000\r
-87: 00000000\r
-88: 00000578\r
-89: 00000000\r
-8a: 00000000\r
-8b: 00000000\r
-8c: 00000000\r
-8d: 00000000\r
-8e: 00000000\r
-8f: 00000000\r
-\r
-90: 00000000\r
-91: 00000000\r
-92: 00000000\r
-93: 00000000\r
-94: 00000000\r
-95: 00000000\r
-96: 00000000\r
-97: 00000000\r
-98: 00000578\r
-99: 00000000\r
-9a: 00000000\r
-9b: 00000000\r
-9c: 00000000\r
-9d: 00000000\r
-9e: 00000000\r
-9f: 00000000\r
-\r
-a0: 00000000\r
-a1: 00000000\r
-a2: 00000000\r
-a3: 00000000\r
-a4: 00000000\r
-a5: 00000000\r
-a6: 00000000\r
-a7: 00000000\r
-a8: 00000578\r
-a9: 00000000\r
-aa: 00000000\r
-ab: 00000000\r
-ac: 00000000\r
-ad: 00000000\r
-ae: 00000000\r
-af: 00000000\r
-\r
-b0: 00000000\r
-b1: 00000000\r
-b2: 00000000\r
-b3: 00000000\r
-b4: 00000000\r
-b5: 00000000\r
-b6: 00000000\r
-b7: 00000000\r
-b8: 00000578\r
-b9: 00000000\r
-ba: 00000000\r
-bb: 00000000\r
-bc: 00000000\r
-bd: 00000000\r
-be: 00000000\r
-bf: 00000000\r
-\r
-c0: 00000000\r
-c1: 00000000\r
-c2: 00000000\r
-c3: 00000000\r
-c4: 00000000\r
-c5: 00000000\r
-c6: 00000000\r
-c7: 00000000\r
-c8: 00000578\r
-c9: 00000000\r
-ca: 00000000\r
-cb: 00000000\r
-cc: 00000000\r
-cd: 00000000\r
-ce: 00000000\r
-cf: 00000000\r
-\r
-d0: 00000000\r
-d1: 00000000\r
-d2: 00000000\r
-d3: 00000000\r
-d4: 00000000\r
-d5: 00000000\r
-d6: 00000000\r
-d7: 00000000\r
-d8: 00000578\r
-d9: 00000000\r
-da: 00000000\r
-db: 00000000\r
-dc: 00000000\r
-dd: 00000000\r
-de: 00000000\r
-df: 00000000\r
-\r
-e0: 00000000\r
-e1: 00000000\r
-e2: 00000000\r
-e3: 00000000\r
-e4: 00000000\r
-e5: 00000000\r
-e6: 00000000\r
-e7: 00000000\r
-e8: 00000578\r
-e9: 00000000\r
-ea: 00000000\r
-eb: 00000000\r
-ec: 00000000\r
-ed: 00000000\r
-ee: 00000000\r
-ef: 00000000\r
-\r
-f0: 00000000\r
-f1: 00000000\r
-f2: 00000000\r
-f3: 00000000\r
-f4: 00000000\r
-f5: 00000000\r
-f6: 00000000\r
-f7: 00000000\r
-f8: 00000578\r
-f9: 00000000\r
-fa: 00000000\r
-fb: 00000000\r
-fc: 00000000\r
-fd: 00000000\r
-fe: 00000000\r
-ff: 00000000\r
+++ /dev/null
-#Format=Address-Hex\r
-#Depth=256\r
-#DataWidth=32\r
-#AddrRadix=3\r
-#DataRadix=3\r
-\r
-00: 00006cf0\r
-01: 4902d745\r
-02: c0a80002\r
-03: 0000c350\r
-04: 0000eeee\r
-05: eeeeeeee\r
-06: c0a80005\r
-07: 0000c350\r
-08: 00000578\r
-09: 00000000\r
-0a: 00000000\r
-0b: 00000000\r
-0c: 00000000\r
-0d: 00000000\r
-0e: 00000000\r
-0f: 00000000\r
-\r
-10: 00000000\r
-11: 00000000\r
-12: 00000000\r
-13: 00000000\r
-14: 00000000\r
-15: 00000000\r
-16: 00000000\r
-17: 00000000\r
-18: 00000578\r
-19: 00000000\r
-1a: 00000000\r
-1b: 00000000\r
-1c: 00000000\r
-1d: 00000000\r
-1e: 00000000\r
-1f: 00000000\r
-\r
-20: 00000000\r
-21: 00000000\r
-22: 00000000\r
-23: 00000000\r
-24: 00000000\r
-25: 00000000\r
-26: 00000000\r
-27: 00000000\r
-28: 00000578\r
-29: 00000000\r
-2a: 00000000\r
-2b: 00000000\r
-2c: 00000000\r
-2d: 00000000\r
-2e: 00000000\r
-2f: 00000000\r
-\r
-30: 00000000\r
-31: 00000000\r
-32: 00000000\r
-33: 00000000\r
-34: 00000000\r
-35: 00000000\r
-36: 00000000\r
-37: 00000000\r
-38: 00000578\r
-39: 00000000\r
-3a: 00000000\r
-3b: 00000000\r
-3c: 00000000\r
-3d: 00000000\r
-3e: 00000000\r
-3f: 00000000\r
-\r
-40: 00000000\r
-41: 00000000\r
-42: 00000000\r
-43: 00000000\r
-44: 00000000\r
-45: 00000000\r
-46: 00000000\r
-47: 00000000\r
-48: 00000578\r
-49: 00000000\r
-4a: 00000000\r
-4b: 00000000\r
-4c: 00000000\r
-4d: 00000000\r
-4e: 00000000\r
-4f: 00000000\r
-\r
-50: 00000000\r
-51: 00000000\r
-52: 00000000\r
-53: 00000000\r
-54: 00000000\r
-55: 00000000\r
-56: 00000000\r
-57: 00000000\r
-58: 00000578\r
-59: 00000000\r
-5a: 00000000\r
-5b: 00000000\r
-5c: 00000000\r
-5d: 00000000\r
-5e: 00000000\r
-5f: 00000000\r
-\r
-60: 00000000\r
-61: 00000000\r
-62: 00000000\r
-63: 00000000\r
-64: 00000000\r
-65: 00000000\r
-66: 00000000\r
-67: 00000000\r
-68: 00000578\r
-69: 00000000\r
-6a: 00000000\r
-6b: 00000000\r
-6c: 00000000\r
-6d: 00000000\r
-6e: 00000000\r
-6f: 00000000\r
-\r
-70: 00000000\r
-71: 00000000\r
-72: 00000000\r
-73: 00000000\r
-74: 00000000\r
-75: 00000000\r
-76: 00000000\r
-77: 00000000\r
-78: 00000578\r
-79: 00000000\r
-7a: 00000000\r
-7b: 00000000\r
-7c: 00000000\r
-7d: 00000000\r
-7e: 00000000\r
-7f: 00000000\r
-\r
-80: 00000000\r
-81: 00000000\r
-82: 00000000\r
-83: 00000000\r
-84: 00000000\r
-85: 00000000\r
-86: 00000000\r
-87: 00000000\r
-88: 00000578\r
-89: 00000000\r
-8a: 00000000\r
-8b: 00000000\r
-8c: 00000000\r
-8d: 00000000\r
-8e: 00000000\r
-8f: 00000000\r
-\r
-90: 00000000\r
-91: 00000000\r
-92: 00000000\r
-93: 00000000\r
-94: 00000000\r
-95: 00000000\r
-96: 00000000\r
-97: 00000000\r
-98: 00000578\r
-99: 00000000\r
-9a: 00000000\r
-9b: 00000000\r
-9c: 00000000\r
-9d: 00000000\r
-9e: 00000000\r
-9f: 00000000\r
-\r
-a0: 00000000\r
-a1: 00000000\r
-a2: 00000000\r
-a3: 00000000\r
-a4: 00000000\r
-a5: 00000000\r
-a6: 00000000\r
-a7: 00000000\r
-a8: 00000578\r
-a9: 00000000\r
-aa: 00000000\r
-ab: 00000000\r
-ac: 00000000\r
-ad: 00000000\r
-ae: 00000000\r
-af: 00000000\r
-\r
-b0: 00000000\r
-b1: 00000000\r
-b2: 00000000\r
-b3: 00000000\r
-b4: 00000000\r
-b5: 00000000\r
-b6: 00000000\r
-b7: 00000000\r
-b8: 00000578\r
-b9: 00000000\r
-ba: 00000000\r
-bb: 00000000\r
-bc: 00000000\r
-bd: 00000000\r
-be: 00000000\r
-bf: 00000000\r
-\r
-c0: 00000000\r
-c1: 00000000\r
-c2: 00000000\r
-c3: 00000000\r
-c4: 00000000\r
-c5: 00000000\r
-c6: 00000000\r
-c7: 00000000\r
-c8: 00000578\r
-c9: 00000000\r
-ca: 00000000\r
-cb: 00000000\r
-cc: 00000000\r
-cd: 00000000\r
-ce: 00000000\r
-cf: 00000000\r
-\r
-d0: 00000000\r
-d1: 00000000\r
-d2: 00000000\r
-d3: 00000000\r
-d4: 00000000\r
-d5: 00000000\r
-d6: 00000000\r
-d7: 00000000\r
-d8: 00000578\r
-d9: 00000000\r
-da: 00000000\r
-db: 00000000\r
-dc: 00000000\r
-dd: 00000000\r
-de: 00000000\r
-df: 00000000\r
-\r
-e0: 00000000\r
-e1: 00000000\r
-e2: 00000000\r
-e3: 00000000\r
-e4: 00000000\r
-e5: 00000000\r
-e6: 00000000\r
-e7: 00000000\r
-e8: 00000578\r
-e9: 00000000\r
-ea: 00000000\r
-eb: 00000000\r
-ec: 00000000\r
-ed: 00000000\r
-ee: 00000000\r
-ef: 00000000\r
-\r
-f0: 00000000\r
-f1: 00000000\r
-f2: 00000000\r
-f3: 00000000\r
-f4: 00000000\r
-f5: 00000000\r
-f6: 00000000\r
-f7: 00000000\r
-f8: 00000578\r
-f9: 00000000\r
-fa: 00000000\r
-fb: 00000000\r
-fc: 00000000\r
-fd: 00000000\r
-fe: 00000000\r
-ff: 00000000\r
+++ /dev/null
-DataInA[31] i
-DataInA[30] i
-DataInA[29] i
-DataInA[28] i
-DataInA[27] i
-DataInA[26] i
-DataInA[25] i
-DataInA[24] i
-DataInA[23] i
-DataInA[22] i
-DataInA[21] i
-DataInA[20] i
-DataInA[19] i
-DataInA[18] i
-DataInA[17] i
-DataInA[16] i
-DataInA[15] i
-DataInA[14] i
-DataInA[13] i
-DataInA[12] i
-DataInA[11] i
-DataInA[10] i
-DataInA[9] i
-DataInA[8] i
-DataInA[7] i
-DataInA[6] i
-DataInA[5] i
-DataInA[4] i
-DataInA[3] i
-DataInA[2] i
-DataInA[1] i
-DataInA[0] i
-DataInB[31] i
-DataInB[30] i
-DataInB[29] i
-DataInB[28] i
-DataInB[27] i
-DataInB[26] i
-DataInB[25] i
-DataInB[24] i
-DataInB[23] i
-DataInB[22] i
-DataInB[21] i
-DataInB[20] i
-DataInB[19] i
-DataInB[18] i
-DataInB[17] i
-DataInB[16] i
-DataInB[15] i
-DataInB[14] i
-DataInB[13] i
-DataInB[12] i
-DataInB[11] i
-DataInB[10] i
-DataInB[9] i
-DataInB[8] i
-DataInB[7] i
-DataInB[6] i
-DataInB[5] i
-DataInB[4] i
-DataInB[3] i
-DataInB[2] i
-DataInB[1] i
-DataInB[0] i
-AddressA[7] i
-AddressA[6] i
-AddressA[5] i
-AddressA[4] i
-AddressA[3] i
-AddressA[2] i
-AddressA[1] i
-AddressA[0] i
-AddressB[7] i
-AddressB[6] i
-AddressB[5] i
-AddressB[4] i
-AddressB[3] i
-AddressB[2] i
-AddressB[1] i
-AddressB[0] i
-ClockA i
-ClockB i
-ClockEnA i
-ClockEnB i
-WrA i
-WrB i
-ResetA i
-ResetB i
-QA[31] o
-QA[30] o
-QA[29] o
-QA[28] o
-QA[27] o
-QA[26] o
-QA[25] o
-QA[24] o
-QA[23] o
-QA[22] o
-QA[21] o
-QA[20] o
-QA[19] o
-QA[18] o
-QA[17] o
-QA[16] o
-QA[15] o
-QA[14] o
-QA[13] o
-QA[12] o
-QA[11] o
-QA[10] o
-QA[9] o
-QA[8] o
-QA[7] o
-QA[6] o
-QA[5] o
-QA[4] o
-QA[3] o
-QA[2] o
-QA[1] o
-QA[0] o
-QB[31] o
-QB[30] o
-QB[29] o
-QB[28] o
-QB[27] o
-QB[26] o
-QB[25] o
-QB[24] o
-QB[23] o
-QB[22] o
-QB[21] o
-QB[20] o
-QB[19] o
-QB[18] o
-QB[17] o
-QB[16] o
-QB[15] o
-QB[14] o
-QB[13] o
-QB[12] o
-QB[11] o
-QB[10] o
-QB[9] o
-QB[8] o
-QB[7] o
-QB[6] o
-QB[5] o
-QB[4] o
-QB[3] o
-QB[2] o
-QB[1] o
-QB[0] o
+++ /dev/null
-ip_mem.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:24:37 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ramdp -device LFE3-150EA -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e
- Circuit name : ip_mem
- Module type : RAM_DP_TRUE
- Module Version : 7.1
- Ports :
- Inputs : DataInA[31:0], DataInB[31:0], AddressA[7:0], AddressB[7:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
- Outputs : QA[31:0], QB[31:0]
- I/O buffer : not inserted
- Memory file : ip_mem.mem
- EDIF output : suppressed
- VHDL output : ip_mem.vhd
- VHDL template : ip_mem_tmpl.vhd
- VHDL testbench : tb_ip_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : ip_mem.srp
- Element Usage :
- DP16KC : 2
- Estimated Resource Usage:
- EBR : 2
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 7.1
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e
-
--- Thu Sep 22 11:24:37 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity ip_mem is
- port (
- DataInA: in std_logic_vector(31 downto 0);
- DataInB: in std_logic_vector(31 downto 0);
- AddressA: in std_logic_vector(7 downto 0);
- AddressB: in std_logic_vector(7 downto 0);
- ClockA: in std_logic;
- ClockB: in std_logic;
- ClockEnA: in std_logic;
- ClockEnB: in std_logic;
- WrA: in std_logic;
- WrB: in std_logic;
- ResetA: in std_logic;
- ResetB: in std_logic;
- QA: out std_logic_vector(31 downto 0);
- QB: out std_logic_vector(31 downto 0));
-end ip_mem;
-
-architecture Structure of ip_mem is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KC
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc";
- attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem";
- attribute RESETMODE of ip_mem_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc";
- attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem";
- attribute RESETMODE of ip_mem_0_1_0 : label is "SYNC";
-
-begin
- -- component instantiation statements
- ip_mem_0_0_1: DP16KC
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9",
- INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9",
- INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9",
- INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9",
- CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG",
- REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
- port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
- DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
- DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
- DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
- DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
- DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
- ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
- ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
- ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
- ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA,
- CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA,
- DIB0=>DataInB(0), DIB1=>DataInB(1), DIB2=>DataInB(2),
- DIB3=>DataInB(3), DIB4=>DataInB(4), DIB5=>DataInB(5),
- DIB6=>DataInB(6), DIB7=>DataInB(7), DIB8=>DataInB(8),
- DIB9=>DataInB(9), DIB10=>DataInB(10), DIB11=>DataInB(11),
- DIB12=>DataInB(12), DIB13=>DataInB(13), DIB14=>DataInB(14),
- DIB15=>DataInB(15), DIB16=>DataInB(16), DIB17=>DataInB(17),
- ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo,
- ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1),
- ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4),
- ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7),
- ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB,
- CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(0),
- DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
- DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
- DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
- DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
- DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
- DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
- DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
- DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
- DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ip_mem_0_1_0: DP16KC
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG",
- REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
- port map (DIA0=>DataInA(18), DIA1=>DataInA(19),
- DIA2=>DataInA(20), DIA3=>DataInA(21), DIA4=>DataInA(22),
- DIA5=>DataInA(23), DIA6=>DataInA(24), DIA7=>DataInA(25),
- DIA8=>DataInA(26), DIA9=>DataInA(27), DIA10=>DataInA(28),
- DIA11=>DataInA(29), DIA12=>DataInA(30), DIA13=>DataInA(31),
- DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo,
- DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>AddressA(0),
- ADA5=>AddressA(1), ADA6=>AddressA(2), ADA7=>AddressA(3),
- ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6),
- ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo,
- CEA=>ClockEnA, CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>ResetA, DIB0=>DataInB(18), DIB1=>DataInB(19),
- DIB2=>DataInB(20), DIB3=>DataInB(21), DIB4=>DataInB(22),
- DIB5=>DataInB(23), DIB6=>DataInB(24), DIB7=>DataInB(25),
- DIB8=>DataInB(26), DIB9=>DataInB(27), DIB10=>DataInB(28),
- DIB11=>DataInB(29), DIB12=>DataInB(30), DIB13=>DataInB(31),
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vhi, ADB1=>scuba_vhi,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>AddressB(0),
- ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3),
- ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6),
- ADB11=>AddressB(7), ADB12=>scuba_vlo, ADB13=>scuba_vlo,
- CEB=>ClockEnB, CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19), DOA2=>QA(20),
- DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23), DOA6=>QA(24),
- DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27), DOA10=>QA(28),
- DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31), DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>QB(18),
- DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21), DOB4=>QB(22),
- DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25), DOB8=>QB(26),
- DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29), DOB12=>QB(30),
- DOB13=>QB(31), DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of ip_mem is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: Module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:24:37 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ramdp -device LFE3-150EA -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e
- Circuit name : ip_mem
- Module type : RAM_DP_TRUE
- Module Version : 7.1
- Ports :
- Inputs : DataInA[31:0], DataInB[31:0], AddressA[7:0], AddressB[7:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
- Outputs : QA[31:0], QB[31:0]
- I/O buffer : not inserted
- Memory file : ip_mem.mem
- EDIF output : suppressed
- VHDL output : ip_mem.vhd
- VHDL template : ip_mem_tmpl.vhd
- VHDL testbench : tb_ip_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : ip_mem.srp
- Estimated Resource Usage:
- EBR : 2
-
-END SCUBA Module Synthesis
-
-File: ip_mem.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 7.1
--- Thu Sep 22 11:24:37 2011
-
--- parameterized module component declaration
-component ip_mem
- port (DataInA: in std_logic_vector(31 downto 0);
- DataInB: in std_logic_vector(31 downto 0);
- AddressA: in std_logic_vector(7 downto 0);
- AddressB: in std_logic_vector(7 downto 0);
- ClockA: in std_logic; ClockB: in std_logic;
- ClockEnA: in std_logic; ClockEnB: in std_logic;
- WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic;
- ResetB: in std_logic; QA: out std_logic_vector(31 downto 0);
- QB: out std_logic_vector(31 downto 0));
-end component;
-
--- parameterized module component instance
-__ : ip_mem
- port map (DataInA(31 downto 0)=>__, DataInB(31 downto 0)=>__,
- AddressA(7 downto 0)=>__, AddressB(7 downto 0)=>__, ClockA=>__,
- ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__,
- ResetB=>__, QA(31 downto 0)=>__, QB(31 downto 0)=>__);
+++ /dev/null
-#Format=Bin\r
-#Depth=54\r
-#Width=8\r
-#AddrRadix=3\r
-#DataRadix=3\r
-#Data\r
-00001111\r
-00001111\r
-10011001\r
-00000001\r
-11101110\r
-00000101\r
-00000000\r
-00000000\r
-00001100\r
-00000000\r
-00110100\r
-00010010\r
-01111000\r
-01010110\r
-10111100\r
-10011010\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-10000000\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="mac_init_mem" module="ROM" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 22 11:24:55.177" version="5.0" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="macInitDataInvWithMac.mem" type="mem" modified="2011 09 22 11:21:25.000"/>
- <File name="mac_init_mem.lpc" type="lpc" modified="2011 09 22 11:24:53.000"/>
- <File name="mac_init_mem.vhd" type="top_level_vhdl" modified="2011 09 22 11:24:53.000"/>
- <File name="mac_init_mem_tmpl.vhd" type="template_vhdl" modified="2011 09 22 11:24:53.000"/>
- <File name="tb_mac_init_mem_tmpl.vhd" type="testbench_vhdl" modified="2011 09 22 11:24:53.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE mac_init_mem DEFIN mac_init_mem.vhd
- SUBMODULE DP16KC
- INSTANCE mac_init_mem_0_0_0
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=ROM
-CoreRevision=5.0
-ModuleName=mac_init_mem
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:24:53
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-Address=54
-Data=8
-adPipeline=0
-inPipeline=0
-outPipeline=1
-MOR=0
-InData=Registered
-AdControl=Registered
-MemFile=macInitDataInvWithMac.mem
-MemFormat=bin
-Reset=Sync
-Pad=0
-GSR=Enabled
-EnECC=0
-Optimization=Speed
-Pipeline=0
-
-[FilesGenerated]
-macInitDataInvWithMac.mem=mem
+++ /dev/null
-Address[5] i
-Address[4] i
-Address[3] i
-Address[2] i
-Address[1] i
-Address[0] i
-OutClock i
-OutClockEn i
-Reset i
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
+++ /dev/null
-mac_init_mem.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:24:53 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n mac_init_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type romblk -device LFE3-150EA -addr_width 6 -data_width 8 -num_words 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e
- Circuit name : mac_init_mem
- Module type : EBR_ROM
- Module Version : 5.0
- Ports :
- Inputs : Address[5:0], OutClock, OutClockEn, Reset
- Outputs : Q[7:0]
- I/O buffer : not inserted
- Memory file : macInitDataInvWithMac.mem
- EDIF output : suppressed
- VHDL output : mac_init_mem.vhd
- VHDL template : mac_init_mem_tmpl.vhd
- VHDL testbench : tb_mac_init_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : mac_init_mem.srp
- Element Usage :
- DP16KC : 1
- Estimated Resource Usage:
- EBR : 1
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.0
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e
-
--- Thu Sep 22 11:24:53 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity mac_init_mem is
- port (
- Address: in std_logic_vector(5 downto 0);
- OutClock: in std_logic;
- OutClockEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(7 downto 0));
-end mac_init_mem;
-
-architecture Structure of mac_init_mem is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KC
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc";
- attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem";
- attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC";
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- mac_init_mem_0_0_0: DP16KC
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000",
- INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F",
- CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG",
- REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2),
- ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5),
- ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo,
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn,
- CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo,
- ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo,
- ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo,
- ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo,
- CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1),
- DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6),
- DOA7=>Q(7), DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open,
- DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of mac_init_mem is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: Module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Thu Sep 22 11:24:53 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n mac_init_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type romblk -device LFE3-150EA -addr_width 6 -data_width 8 -num_words 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e
- Circuit name : mac_init_mem
- Module type : EBR_ROM
- Module Version : 5.0
- Ports :
- Inputs : Address[5:0], OutClock, OutClockEn, Reset
- Outputs : Q[7:0]
- I/O buffer : not inserted
- Memory file : macInitDataInvWithMac.mem
- EDIF output : suppressed
- VHDL output : mac_init_mem.vhd
- VHDL template : mac_init_mem_tmpl.vhd
- VHDL testbench : tb_mac_init_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : mac_init_mem.srp
- Estimated Resource Usage:
- EBR : 1
-
-END SCUBA Module Synthesis
-
-File: mac_init_mem.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.0
--- Thu Sep 22 11:24:53 2011
-
--- parameterized module component declaration
-component mac_init_mem
- port (Address: in std_logic_vector(5 downto 0);
- OutClock: in std_logic; OutClockEn: in std_logic;
- Reset: in std_logic; Q: out std_logic_vector(7 downto 0));
-end component;
-
--- parameterized module component instance
-__ : mac_init_mem
- port map (Address(5 downto 0)=>__, OutClock=>__, OutClockEn=>__,
- Reset=>__, Q(7 downto 0)=>__);
+++ /dev/null
-SCUBA, Version Diamond_1.4_Production (87)
-Sat May 19 15:06:38 2012
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -n fifo_65536x18x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
- Circuit name : fifo_65536x18x9
- Module type : ebfifo
- Module Version : 5.4
- Ports :
- Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : fifo_65536x18x9.vhd
- VHDL template : fifo_65536x18x9_tmpl.vhd
- VHDL testbench : tb_fifo_65536x18x9_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_65536x18x9.srp
- Estimated Resource Usage:
- LUT : 367
- EBR : 32
- Reg : 172
-
-END SCUBA Module Synthesis
-
+++ /dev/null
- Module Name: serdes_gbe_0_extclock_8b\r
- Core Name: PCS\r
- LPC file : serdes_gbe_0_extclock_8b.lpc\r
- Parameter File : serdes_gbe_0_extclock_8b.pp\r
- Command line: /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_extclock_8b.pp\r
- Return Value:\r
- \r
- \r
- Module PCS has been generated in /home/greg/NewHub2/hub2/ipexpress/serdes successfully!\r
-\r
-/home/greg/.isplever_lin1/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_extclock_8b -ext readme -out serdes_gbe_0_extclock_8b -tpl serdes_gbe_0_extclock_8b.tft serdes_gbe_0_extclock_8b.vhd\r
-\r
-Done successfully!\r
+++ /dev/null
-MODULE serdes_gbe_0_extclock_8b DEFIN serdes_gbe_0_extclock_8b.vhd\r
- SUBMODULE PCSC\r
- INSTANCE PCSC_INST\r
- SUBMODULE VLO\r
- INSTANCE vlo_inst\r
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-6F900C\r
-SpeedGrade=-6\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=PCS\r
-CoreRevision=7.0\r
-ModuleName=serdes_gbe_0_extclock_8b\r
-SourceFormat=Schematic/VHDL\r
-ParameterFileVersion=1.0\r
-Date=08/20/2009\r
-Time=11:50:53\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-Protocol=Quad\r
-mode=Gigabit Ethernet\r
-Channel0=SINGLE\r
-Channel1=DISABLE\r
-Channel2=DISABLE\r
-Channel3=DISABLE\r
-Rate0=None\r
-Rate1=None\r
-Rate2=None\r
-Rate3=None\r
-TxRefClk=REFCLK\r
-RxRefClk=REFCLK\r
-ClkRate=1.25\r
-ClkMult=10X\r
-CalClkRate=125.0\r
-DataWidth=8\r
-FPGAClkRate=125.0\r
-TxRefClkCM=REFCLK\r
-RxRefClk0CM=REFCLK\r
-RxRefClk1CM=REFCLK\r
-RxRefClk2CM=REFCLK\r
-RxRefClk3CM=REFCLK\r
-ClkRateH=0.625\r
-ClkMultH=10XH\r
-CalClkRateH=125.0\r
-DataWidthH=8\r
-FPGAClkRateH=62.5\r
-VCh0=0\r
-VCh1=0\r
-VCh2=0\r
-VCh3=0\r
-PreCh0=DISABLE\r
-PreCh1=DISABLE\r
-PreCh2=DISABLE\r
-PreCh3=DISABLE\r
-TxCh0=50\r
-TxCh1=50\r
-TxCh2=50\r
-TxCh3=50\r
-EqCh0=DISABLE\r
-EqCh1=DISABLE\r
-EqCh2=DISABLE\r
-EqCh3=DISABLE\r
-RxTermCh0=50\r
-RxTermCh1=50\r
-RxTermCh2=50\r
-RxTermCh3=50\r
-RxCoupCh0=AC\r
-RxCoupCh1=AC\r
-RxCoupCh2=AC\r
-RxCoupCh3=AC\r
-Loss=0\r
-CDRLoss=0\r
-TxTerm=50\r
-TxCoup=AC\r
-TxPllLoss=0\r
-TxInvCh0=NORMAL\r
-TxInvCh1=NORMAL\r
-TxInvCh2=NORMAL\r
-TxInvCh3=NORMAL\r
-RxInvCh0=NORMAL\r
-RxInvCh1=NORMAL\r
-RxInvCh2=NORMAL\r
-RxInvCh3=NORMAL\r
-RxModeCh0=NORMAL\r
-RxModeCh1=NORMAL\r
-RxModeCh2=NORMAL\r
-RxModeCh3=NORMAL\r
-Plus=1100000101\r
-Minus=0011111010\r
-Mask=1111111111\r
-Align=AUTO\r
-CTCCh0=NORMAL\r
-CTCCh1=NORMAL\r
-CTCCh2=NORMAL\r
-CTCCh3=NORMAL\r
-CC_MATCH1=0000000000\r
-CC_MATCH2=0000000000\r
-CC_MATCH3=0110111100\r
-CC_MATCH4=0001010000\r
-MinIPG=3\r
-High=9\r
-Low=7\r
-CC_MATCH_MODE=MATCH_3_4\r
-RxDataCh0=FALSE\r
-RxDataCh1=FALSE\r
-RxDataCh2=FALSE\r
-RxDataCh3=FALSE\r
-AlignerCh0=FALSE\r
-AlignerCh1=FALSE\r
-AlignerCh2=FALSE\r
-AlignerCh3=FALSE\r
-DetectCh0=FALSE\r
-DetectCh1=FALSE\r
-DetectCh2=FALSE\r
-DetectCh3=FALSE\r
-ELSMCh0=FALSE\r
-ELSMCh1=FALSE\r
-ELSMCh2=FALSE\r
-ELSMCh3=FALSE\r
-_teidleCh0=FALSE\r
-_teidleCh1=FALSE\r
-_teidleCh2=FALSE\r
-_teidleCh3=FALSE\r
-Ports0=FALSE\r
-rdoPorts0=Serial Loopback\r
-Ports1=FALSE\r
-Ports2=TRUE\r
-Ports3=FALSE\r
-Ports3_1=FALSE\r
-Ports4=FALSE\r
+++ /dev/null
-refclkp i\r
-refclkn i\r
-hdinp0 i\r
-hdinn0 i\r
-hdoutp0 o\r
-hdoutn0 o\r
-ff_rxiclk_ch0 i\r
-ff_txiclk_ch0 i\r
-ff_ebrd_clk_0 i\r
-ff_txdata_ch0[7] i\r
-ff_txdata_ch0[6] i\r
-ff_txdata_ch0[5] i\r
-ff_txdata_ch0[4] i\r
-ff_txdata_ch0[3] i\r
-ff_txdata_ch0[2] i\r
-ff_txdata_ch0[1] i\r
-ff_txdata_ch0[0] i\r
-ff_rxdata_ch0[7] o\r
-ff_rxdata_ch0[6] o\r
-ff_rxdata_ch0[5] o\r
-ff_rxdata_ch0[4] o\r
-ff_rxdata_ch0[3] o\r
-ff_rxdata_ch0[2] o\r
-ff_rxdata_ch0[1] o\r
-ff_rxdata_ch0[0] o\r
-ff_tx_k_cntrl_ch0 i\r
-ff_rx_k_cntrl_ch0 o\r
-ff_rxfullclk_ch0 o\r
-ff_xmit_ch0 i\r
-ff_correct_disp_ch0 i\r
-ff_disp_err_ch0 o\r
-ff_cv_ch0 o\r
-ff_rx_even_ch0 o\r
-ffc_rrst_ch0 i\r
-ffc_lane_tx_rst_ch0 i\r
-ffc_lane_rx_rst_ch0 i\r
-ffc_txpwdnb_ch0 i\r
-ffc_rxpwdnb_ch0 i\r
-ffs_rlos_lo_ch0 o\r
-ffs_ls_sync_status_ch0 o\r
-ffs_rlol_ch0 o\r
-oob_out_ch0 o\r
-ffc_macro_rst i\r
-ffc_quad_rst i\r
-ffc_trst i\r
-ff_txfullclk o\r
-ff_txhalfclk o\r
-refck2core o\r
-ffs_plol o\r
+++ /dev/null
-#define _device_name "LFE2M100E"\r
-#define _protocol_mode "Quad Based Protocol Mode"\r
-#define _protocol "GIGE" \r
-#define _ch0_mode "SINGLE" \r
-#define _ch1_mode "DISABLE" \r
-#define _ch2_mode "DISABLE" \r
-#define _ch3_mode "DISABLE" \r
-#define _pll_txsrc "REFCLK" \r
-#define _pll_rxsrc "REFCLK" \r
-#define _datarange "MED" \r
-#define _refclk_mult "10X" \r
-#define _refclk_rate 125.0\r
-#define _data_width "8" \r
-#define _fpgaintclk_rate 125.0\r
-#define _ch0_tdrv_amp "0" \r
-#define _ch1_tdrv_amp "0" \r
-#define _ch2_tdrv_amp "0" \r
-#define _ch3_tdrv_amp "0" \r
-#define _ch0_tx_pre "DISABLE" \r
-#define _ch1_tx_pre "DISABLE" \r
-#define _ch2_tx_pre "DISABLE" \r
-#define _ch3_tx_pre "DISABLE" \r
-#define _ch0_rterm_tx "50" \r
-#define _ch1_rterm_tx "50" \r
-#define _ch2_rterm_tx "50" \r
-#define _ch3_rterm_tx "50" \r
-#define _ch0_rx_eq "DISABLE" \r
-#define _ch1_rx_eq "DISABLE" \r
-#define _ch2_rx_eq "DISABLE" \r
-#define _ch3_rx_eq "DISABLE" \r
-#define _ch0_rterm_rx "50" \r
-#define _ch1_rterm_rx "50" \r
-#define _ch2_rterm_rx "50" \r
-#define _ch3_rterm_rx "50" \r
-#define _ch0_rx_dcc "AC" \r
-#define _ch1_rx_dcc "AC" \r
-#define _ch2_rx_dcc "AC" \r
-#define _ch3_rx_dcc "AC" \r
-#define _los_threshold "0" \r
-#define _pll_term "50" \r
-#define _pll_dcc "AC" \r
-#define _pll_lol_set "0" \r
-#define _ch0_tx_sb "NORMAL" \r
-#define _ch1_tx_sb "NORMAL" \r
-#define _ch2_tx_sb "NORMAL" \r
-#define _ch3_tx_sb "NORMAL" \r
-#define _ch0_rx_sb "NORMAL" \r
-#define _ch1_rx_sb "NORMAL" \r
-#define _ch2_rx_sb "NORMAL" \r
-#define _ch3_rx_sb "NORMAL" \r
-#define _ch0_8b10b "NORMAL" \r
-#define _ch1_8b10b "NORMAL" \r
-#define _ch2_8b10b "NORMAL" \r
-#define _ch3_8b10b "NORMAL" \r
-#define _comma_a "1100000101" \r
-#define _comma_b "0011111010" \r
-#define _comma_m "1111111111" \r
-#define _comma_align "AUTO" \r
-#define _ch0_ctc_byp "NORMAL" \r
-#define _ch1_ctc_byp "NORMAL" \r
-#define _ch2_ctc_byp "NORMAL" \r
-#define _ch3_ctc_byp "NORMAL" \r
-#define _cc_match1 "0000000000" \r
-#define _cc_match2 "0000000000" \r
-#define _cc_match3 "0110111100" \r
-#define _cc_match4 "0001010000" \r
-#define _cc_match_mode "MATCH_3_4" \r
-#define _cc_min_ipg "3" \r
-#define _cchmark "9" \r
-#define _cclmark "7" \r
-#define _ch0_ird "FALSE" \r
-#define _ch1_ird "FALSE" \r
-#define _ch2_ird "FALSE" \r
-#define _ch3_ird "FALSE" \r
-#define _ch0_elsm "FALSE" \r
-#define _ch1_elsm "FALSE" \r
-#define _ch2_elsm "FALSE" \r
-#define _ch3_elsm "FALSE" \r
-#define _ch0_teidle "FALSE"\r
-#define _ch1_teidle "FALSE"\r
-#define _ch2_teidle "FALSE"\r
-#define _ch3_teidle "FALSE"\r
-#define _loopback "FALSE" \r
-#define _lbtype "Serial Loopback"\r
-#define _refck2core "TRUE" \r
-#define _pllqclkports "FALSE"\r
-#define _sci_ports "FALSE" \r
-#define _sci_int_port "FALSE" \r
-#define _errsports "FALSE" \r
-\r
-#define _circuit_name serdes_gbe_0_extclock_8b\r
-#define _lang vhdl\r
-\r
-#include <pcs/PCSC.vhd>\r
-#include <pcs/pcsc_cfg.txt>\r
+++ /dev/null
-\r
- TOOL: orcapp \r
- DATE: 19-MAR-2008 13:11:51 \r
- TITLE: Lattice Semiconductor Corporation\r
- MODULE: serdes_gbe_0_extclock_8b\r
- DESIGN: serdes_gbe_0_extclock_8b\r
- FILENAME: serdes_gbe_0_extclock_8b.readme\r
- PROJECT: Unknown\r
- VERSION: 2.0\r
- This file is auto generated by the ispLEVER\r
-\r
-\r
-NOTE: This readme file has been provided to instantiate the interface\r
-netlist. Since this template contains synthesis attributes for precision that\r
-are crucial to the design flow, we recommend that you use this\r
-template in your FPGA design.\r
-entity chip is\r
-port (\r
-\r
--- Add your FPGA design top level I/Os here\r
-\r
-\r
--- ASIC side pins for PCSA. These pins must exist for the\r
--- PCS core.\r
- refclkp : in std_logic;\r
- refclkn : in std_logic;\r
- hdinp0 : in std_logic;\r
- hdinn0 : in std_logic;\r
- hdinp1 : in std_logic;\r
- hdinn1 : in std_logic;\r
- hdinp2 : in std_logic;\r
- hdinn2 : in std_logic;\r
- hdinp3 : in std_logic;\r
- hdinn3 : in std_logic;\r
-\r
- hdoutp0 : out std_logic;\r
- hdoutn0 : out std_logic;\r
- hdoutp1 : out std_logic;\r
- hdoutn1 : out std_logic;\r
- hdoutp2 : out std_logic;\r
- hdoutn2 : out std_logic;\r
- hdoutp3 : out std_logic;\r
- hdoutn3 : out std_logic;\r
-\r
-\r
-);\r
-end chip;\r
-\r
-architecture chip_arch of chip is\r
-\r
--- This defines all the high-speed ports. You may have to remove\r
--- some of them depending on your design.\r
-attribute nopad : string;\r
-attribute nopad of\r
- refclkp, refclkn,\r
- hdinp0, hdinn0, hdinp1, hdinn1,\r
- hdinp2, hdinn2, hdinp3, hdinn3,\r
- hdoutp0, hdoutn0, hdoutp1, hdoutn1,\r
- hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";\r
-\r
- COMPONENT serdes_gbe_0_extclock_8b\r
- PORT(\r
- refclkp : IN std_logic;\r
- refclkn : IN std_logic;\r
- hdinp0 : IN std_logic;\r
- hdinn0 : IN std_logic;\r
- ff_rxiclk_ch0 : IN std_logic;\r
- ff_txiclk_ch0 : IN std_logic;\r
- ff_ebrd_clk_0 : IN std_logic;\r
- ff_txdata_ch0 : IN std_logic_vector(7 downto 0);\r
- ff_tx_k_cntrl_ch0 : IN std_logic;\r
- ff_xmit_ch0 : IN std_logic;\r
- ff_correct_disp_ch0 : IN std_logic;\r
- ffc_rrst_ch0 : IN std_logic;\r
- ffc_lane_tx_rst_ch0 : IN std_logic;\r
- ffc_lane_rx_rst_ch0 : IN std_logic;\r
- ffc_txpwdnb_ch0 : IN std_logic;\r
- ffc_rxpwdnb_ch0 : IN std_logic;\r
- ffc_macro_rst : IN std_logic;\r
- ffc_quad_rst : IN std_logic;\r
- ffc_trst : IN std_logic; \r
- hdoutp0 : OUT std_logic;\r
- hdoutn0 : OUT std_logic;\r
- ff_rxdata_ch0 : OUT std_logic_vector(7 downto 0);\r
- ff_rx_k_cntrl_ch0 : OUT std_logic;\r
- ff_rxfullclk_ch0 : OUT std_logic;\r
- ff_disp_err_ch0 : OUT std_logic;\r
- ff_cv_ch0 : OUT std_logic;\r
- ff_rx_even_ch0 : OUT std_logic;\r
- ffs_rlos_lo_ch0 : OUT std_logic;\r
- ffs_ls_sync_status_ch0 : OUT std_logic;\r
- ffs_rlol_ch0 : OUT std_logic;\r
- oob_out_ch0 : OUT std_logic;\r
- ff_txfullclk : OUT std_logic;\r
- ff_txhalfclk : OUT std_logic;\r
- refck2core : OUT std_logic;\r
- ffs_plol : OUT std_logic\r
- );\r
- END COMPONENT;\r
-\r
-\r
-\r
- uut: serdes_gbe_0_extclock_8b PORT MAP(\r
- refclkp => refclkp,\r
- refclkn => refclkn,\r
- hdinp0 => hdinp0,\r
- hdinn0 => hdinn0,\r
- hdoutp0 => hdoutp0,\r
- hdoutn0 => hdoutn0,\r
- ff_rxiclk_ch0 => ff_rxiclk_ch0,\r
- ff_txiclk_ch0 => ff_txiclk_ch0,\r
- ff_ebrd_clk_0 => ff_ebrd_clk_0,\r
- ff_txdata_ch0 => ff_txdata_ch0,\r
- ff_rxdata_ch0 => ff_rxdata_ch0,\r
- ff_tx_k_cntrl_ch0 => ff_tx_k_cntrl_ch0,\r
- ff_rx_k_cntrl_ch0 => ff_rx_k_cntrl_ch0,\r
- ff_rxfullclk_ch0 => ff_rxfullclk_ch0,\r
- ff_xmit_ch0 => ff_xmit_ch0,\r
- ff_correct_disp_ch0 => ff_correct_disp_ch0,\r
- ff_disp_err_ch0 => ff_disp_err_ch0,\r
- ff_cv_ch0 => ff_cv_ch0,\r
- ff_rx_even_ch0 => ff_rx_even_ch0,\r
- ffc_rrst_ch0 => ffc_rrst_ch0,\r
- ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst_ch0,\r
- ffc_lane_rx_rst_ch0 => ffc_lane_rx_rst_ch0,\r
- ffc_txpwdnb_ch0 => ffc_txpwdnb_ch0,\r
- ffc_rxpwdnb_ch0 => ffc_rxpwdnb_ch0,\r
- ffs_rlos_lo_ch0 => ffs_rlos_lo_ch0,\r
- ffs_ls_sync_status_ch0 => ffs_ls_sync_status_ch0,\r
- ffs_rlol_ch0 => ffs_rlol_ch0,\r
- oob_out_ch0 => oob_out_ch0,\r
- ffc_macro_rst => ffc_macro_rst,\r
- ffc_quad_rst => ffc_quad_rst,\r
- ffc_trst => ffc_trst,\r
- ff_txfullclk => ff_txfullclk,\r
- ff_txhalfclk => ff_txhalfclk,\r
- refck2core => refck2core,\r
- ffs_plol => ffs_plol\r
- );\r
-\r
-\r
+++ /dev/null
-@set suppresnewline=on@\r
-\r
-@comment --------------------------------------------------------------------- @\r
-@comment Template-drive TFI generator @\r
-@comment Template for TFI generation. @\r
-@comment --------------------------------------------------------------------- @\r
-\r
-@set suppresnewline=off@\r
- TOOL: orcapp \r
- DATE: 19-MAR-2008 13:11:51 \r
- TITLE: %title%\r
- MODULE: %module%\r
- DESIGN: %module%\r
- FILENAME: %filename%\r
- PROJECT: %project%\r
- VERSION: %ver%\r
- This file is auto generated by the ispLEVER\r
-@set suppresnewline=on@\r
-\r
-@cr@\r
-@cr@\r
-\r
-@set sigdelim=@\r
-\r
-NOTE: This readme file has been provided to instantiate the interface@cr@\r
-netlist. Since this template contains synthesis attributes for precision that@cr@\r
-are crucial to the design flow, we recommend that you use this@cr@\r
-template in your FPGA design.@cr@\r
-entity chip is@cr@\r
-port (@cr@\r
-@cr@\r
--- Add your FPGA design top level I/Os here@cr@\r
-@cr@\r
-@cr@\r
--- ASIC side pins for PCSA. These pins must exist for the@cr@\r
--- PCS core.@cr@\r
- refclkp : in std_logic;@cr@\r
- refclkn : in std_logic;@cr@\r
- hdinp0 : in std_logic;@cr@\r
- hdinn0 : in std_logic;@cr@\r
- hdinp1 : in std_logic;@cr@\r
- hdinn1 : in std_logic;@cr@\r
- hdinp2 : in std_logic;@cr@\r
- hdinn2 : in std_logic;@cr@\r
- hdinp3 : in std_logic;@cr@\r
- hdinn3 : in std_logic;@cr@\r
-@cr@\r
- hdoutp0 : out std_logic;@cr@\r
- hdoutn0 : out std_logic;@cr@\r
- hdoutp1 : out std_logic;@cr@\r
- hdoutn1 : out std_logic;@cr@\r
- hdoutp2 : out std_logic;@cr@\r
- hdoutn2 : out std_logic;@cr@\r
- hdoutp3 : out std_logic;@cr@\r
- hdoutn3 : out std_logic;@cr@\r
-@cr@\r
-@cr@\r
-);@cr@\r
-end chip;@cr@\r
-@cr@\r
-architecture chip_arch of chip is@cr@\r
-@cr@\r
--- This defines all the high-speed ports. You may have to remove@cr@\r
--- some of them depending on your design.@cr@\r
-attribute nopad : string;@cr@\r
-attribute nopad of@cr@\r
- refclkp, refclkn,@cr@\r
- hdinp0, hdinn0, hdinp1, hdinn1,@cr@\r
- hdinp2, hdinn2, hdinp3, hdinn3,@cr@\r
- hdoutp0, hdoutn0, hdoutp1, hdoutn1,@cr@\r
- hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";@cr@\r
-\r
-@cr@\r
-@tab@COMPONENT %module%\r
-@set sigdelim=@\r
-@cr@@tab@PORT(\r
-@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@\r
-@ifhas oport=*@ @comment if the design has any output ports... @\r
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@\r
- @set sigdelim=;@\r
- @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@\r
-@endif@\r
-@ifnhas oport=*@ @comment we need an "else in this language! @\r
- @set sigdelim=;@\r
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@\r
-@endif@\r
-@cr@@tab@@tab@);@cr@\r
-@tab@END COMPONENT;@cr@@cr@\r
-@comment Now do a signal declaration for each port @\r
-\r
-@cr@@cr@\r
-@comment do the component instantiation @\r
-@set sigdelim=,@\r
-@tab@uut: %module% PORT MAP(\r
-@iterate@%port%\r
-@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@\r
-@cr@@tab@);@cr@@cr@\r
-@set suppresnewline=off@\r
+++ /dev/null
-\r
-# This file is used by the simulation model as well as the ispLEVER bitstream\r
-# generation process to automatically initialize the PCSC quad to the mode\r
-# selected in the IPexpress. This file is expected to be modified by the\r
-# end user to adjust the PCSC quad to the final design requirements.\r
-\r
-DEVICE_NAME "LFE2M100E"\r
-PROTOCOL "GIGE" \r
-CH0_MODE "SINGLE" \r
-CH1_MODE "DISABLE" \r
-CH2_MODE "DISABLE" \r
-CH3_MODE "DISABLE" \r
-PLL_SRC "REFCLK" \r
-DATARANGE "MED" \r
-CH0_CDR_SRC "REFCLK" \r
-CH0_DATA_WIDTH "8" \r
-CH0_REFCK_MULT "10X" \r
-#REFCLK_RATE 125.0\r
-#FPGAINTCLK_RATE 125.0\r
-CH0_TDRV_AMP "0" \r
-CH0_TX_PRE "DISABLE" \r
-CH0_RTERM_TX "50" \r
-CH0_RX_EQ "DISABLE" \r
-CH0_RTERM_RX "50" \r
-CH0_RX_DCC "AC" \r
-LOS_THRESHOLD "0" \r
-PLL_TERM "50" \r
-PLL_DCC "AC" \r
-PLL_LOL_SET "0" \r
-CH0_TX_SB "NORMAL" \r
-CH0_RX_SB "NORMAL" \r
-CH0_8B10B "NORMAL" \r
-COMMA_A "1100000101" \r
-COMMA_B "0011111010" \r
-COMMA_M "1111111111" \r
-CH0_COMMA_ALIGN "AUTO" \r
-CH0_CTC_BYP "BYPASS" \r
-CC_MATCH1 "0000000000" \r
-CC_MATCH2 "0000000000" \r
-CC_MATCH3 "0110111100" \r
-CC_MATCH4 "0001010000" \r
-CC_MATCH_MODE "MATCH_3_4" \r
-CC_MIN_IPG "3" \r
-CCHMARK "9" \r
-CCLMARK "7" \r
-OS_REFCK2CORE "1"\r
-OS_PLLQCLKPORTS "0"\r
-OS_INT_ALL "0"\r
-\r
+++ /dev/null
-\r
-\r
---synopsys translate_off\r
-\r
-library pcsc_work;\r
-use pcsc_work.all;\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity PCSC is\r
-GENERIC(\r
- CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"\r
- );\r
-port (\r
- HDINN0 : in std_logic;\r
- HDINN1 : in std_logic;\r
- HDINN2 : in std_logic;\r
- HDINN3 : in std_logic;\r
- HDINP0 : in std_logic;\r
- HDINP1 : in std_logic;\r
- HDINP2 : in std_logic;\r
- HDINP3 : in std_logic;\r
- REFCLKN : in std_logic;\r
- REFCLKP : in std_logic;\r
- CIN0 : in std_logic;\r
- CIN1 : in std_logic;\r
- CIN2 : in std_logic;\r
- CIN3 : in std_logic;\r
- CIN4 : in std_logic;\r
- CIN5 : in std_logic;\r
- CIN6 : in std_logic;\r
- CIN7 : in std_logic;\r
- CIN8 : in std_logic;\r
- CIN9 : in std_logic;\r
- CIN10 : in std_logic;\r
- CIN11 : in std_logic;\r
- CYAWSTN : in std_logic;\r
- FF_EBRD_CLK_0 : in std_logic;\r
- FF_EBRD_CLK_1 : in std_logic;\r
- FF_EBRD_CLK_2 : in std_logic;\r
- FF_EBRD_CLK_3 : in std_logic;\r
- FF_RXI_CLK_0 : in std_logic;\r
- FF_RXI_CLK_1 : in std_logic;\r
- FF_RXI_CLK_2 : in std_logic;\r
- FF_RXI_CLK_3 : in std_logic;\r
- FF_TX_D_0_0 : in std_logic;\r
- FF_TX_D_0_1 : in std_logic;\r
- FF_TX_D_0_2 : in std_logic;\r
- FF_TX_D_0_3 : in std_logic;\r
- FF_TX_D_0_4 : in std_logic;\r
- FF_TX_D_0_5 : in std_logic;\r
- FF_TX_D_0_6 : in std_logic;\r
- FF_TX_D_0_7 : in std_logic;\r
- FF_TX_D_0_8 : in std_logic;\r
- FF_TX_D_0_9 : in std_logic;\r
- FF_TX_D_0_10 : in std_logic;\r
- FF_TX_D_0_11 : in std_logic;\r
- FF_TX_D_0_12 : in std_logic;\r
- FF_TX_D_0_13 : in std_logic;\r
- FF_TX_D_0_14 : in std_logic;\r
- FF_TX_D_0_15 : in std_logic;\r
- FF_TX_D_0_16 : in std_logic;\r
- FF_TX_D_0_17 : in std_logic;\r
- FF_TX_D_0_18 : in std_logic;\r
- FF_TX_D_0_19 : in std_logic;\r
- FF_TX_D_0_20 : in std_logic;\r
- FF_TX_D_0_21 : in std_logic;\r
- FF_TX_D_0_22 : in std_logic;\r
- FF_TX_D_0_23 : in std_logic;\r
- FF_TX_D_1_0 : in std_logic;\r
- FF_TX_D_1_1 : in std_logic;\r
- FF_TX_D_1_2 : in std_logic;\r
- FF_TX_D_1_3 : in std_logic;\r
- FF_TX_D_1_4 : in std_logic;\r
- FF_TX_D_1_5 : in std_logic;\r
- FF_TX_D_1_6 : in std_logic;\r
- FF_TX_D_1_7 : in std_logic;\r
- FF_TX_D_1_8 : in std_logic;\r
- FF_TX_D_1_9 : in std_logic;\r
- FF_TX_D_1_10 : in std_logic;\r
- FF_TX_D_1_11 : in std_logic;\r
- FF_TX_D_1_12 : in std_logic;\r
- FF_TX_D_1_13 : in std_logic;\r
- FF_TX_D_1_14 : in std_logic;\r
- FF_TX_D_1_15 : in std_logic;\r
- FF_TX_D_1_16 : in std_logic;\r
- FF_TX_D_1_17 : in std_logic;\r
- FF_TX_D_1_18 : in std_logic;\r
- FF_TX_D_1_19 : in std_logic;\r
- FF_TX_D_1_20 : in std_logic;\r
- FF_TX_D_1_21 : in std_logic;\r
- FF_TX_D_1_22 : in std_logic;\r
- FF_TX_D_1_23 : in std_logic;\r
- FF_TX_D_2_0 : in std_logic;\r
- FF_TX_D_2_1 : in std_logic;\r
- FF_TX_D_2_2 : in std_logic;\r
- FF_TX_D_2_3 : in std_logic;\r
- FF_TX_D_2_4 : in std_logic;\r
- FF_TX_D_2_5 : in std_logic;\r
- FF_TX_D_2_6 : in std_logic;\r
- FF_TX_D_2_7 : in std_logic;\r
- FF_TX_D_2_8 : in std_logic;\r
- FF_TX_D_2_9 : in std_logic;\r
- FF_TX_D_2_10 : in std_logic;\r
- FF_TX_D_2_11 : in std_logic;\r
- FF_TX_D_2_12 : in std_logic;\r
- FF_TX_D_2_13 : in std_logic;\r
- FF_TX_D_2_14 : in std_logic;\r
- FF_TX_D_2_15 : in std_logic;\r
- FF_TX_D_2_16 : in std_logic;\r
- FF_TX_D_2_17 : in std_logic;\r
- FF_TX_D_2_18 : in std_logic;\r
- FF_TX_D_2_19 : in std_logic;\r
- FF_TX_D_2_20 : in std_logic;\r
- FF_TX_D_2_21 : in std_logic;\r
- FF_TX_D_2_22 : in std_logic;\r
- FF_TX_D_2_23 : in std_logic;\r
- FF_TX_D_3_0 : in std_logic;\r
- FF_TX_D_3_1 : in std_logic;\r
- FF_TX_D_3_2 : in std_logic;\r
- FF_TX_D_3_3 : in std_logic;\r
- FF_TX_D_3_4 : in std_logic;\r
- FF_TX_D_3_5 : in std_logic;\r
- FF_TX_D_3_6 : in std_logic;\r
- FF_TX_D_3_7 : in std_logic;\r
- FF_TX_D_3_8 : in std_logic;\r
- FF_TX_D_3_9 : in std_logic;\r
- FF_TX_D_3_10 : in std_logic;\r
- FF_TX_D_3_11 : in std_logic;\r
- FF_TX_D_3_12 : in std_logic;\r
- FF_TX_D_3_13 : in std_logic;\r
- FF_TX_D_3_14 : in std_logic;\r
- FF_TX_D_3_15 : in std_logic;\r
- FF_TX_D_3_16 : in std_logic;\r
- FF_TX_D_3_17 : in std_logic;\r
- FF_TX_D_3_18 : in std_logic;\r
- FF_TX_D_3_19 : in std_logic;\r
- FF_TX_D_3_20 : in std_logic;\r
- FF_TX_D_3_21 : in std_logic;\r
- FF_TX_D_3_22 : in std_logic;\r
- FF_TX_D_3_23 : in std_logic;\r
- FF_TXI_CLK_0 : in std_logic;\r
- FF_TXI_CLK_1 : in std_logic;\r
- FF_TXI_CLK_2 : in std_logic;\r
- FF_TXI_CLK_3 : in std_logic;\r
- FFC_CK_CORE_RX : in std_logic;\r
- FFC_CK_CORE_TX : in std_logic;\r
- FFC_EI_EN_0 : in std_logic;\r
- FFC_EI_EN_1 : in std_logic;\r
- FFC_EI_EN_2 : in std_logic;\r
- FFC_EI_EN_3 : in std_logic;\r
- FFC_ENABLE_CGALIGN_0 : in std_logic;\r
- FFC_ENABLE_CGALIGN_1 : in std_logic;\r
- FFC_ENABLE_CGALIGN_2 : in std_logic;\r
- FFC_ENABLE_CGALIGN_3 : in std_logic;\r
- FFC_FB_LOOPBACK_0 : in std_logic;\r
- FFC_FB_LOOPBACK_1 : in std_logic;\r
- FFC_FB_LOOPBACK_2 : in std_logic;\r
- FFC_FB_LOOPBACK_3 : in std_logic;\r
- FFC_LANE_RX_RST_0 : in std_logic;\r
- FFC_LANE_RX_RST_1 : in std_logic;\r
- FFC_LANE_RX_RST_2 : in std_logic;\r
- FFC_LANE_RX_RST_3 : in std_logic;\r
- FFC_LANE_TX_RST_0 : in std_logic;\r
- FFC_LANE_TX_RST_1 : in std_logic;\r
- FFC_LANE_TX_RST_2 : in std_logic;\r
- FFC_LANE_TX_RST_3 : in std_logic;\r
- FFC_MACRO_RST : in std_logic;\r
- FFC_PCI_DET_EN_0 : in std_logic;\r
- FFC_PCI_DET_EN_1 : in std_logic;\r
- FFC_PCI_DET_EN_2 : in std_logic;\r
- FFC_PCI_DET_EN_3 : in std_logic;\r
- FFC_PCIE_CT_0 : in std_logic;\r
- FFC_PCIE_CT_1 : in std_logic;\r
- FFC_PCIE_CT_2 : in std_logic;\r
- FFC_PCIE_CT_3 : in std_logic;\r
- FFC_PFIFO_CLR_0 : in std_logic;\r
- FFC_PFIFO_CLR_1 : in std_logic;\r
- FFC_PFIFO_CLR_2 : in std_logic;\r
- FFC_PFIFO_CLR_3 : in std_logic;\r
- FFC_QUAD_RST : in std_logic;\r
- FFC_RRST_0 : in std_logic;\r
- FFC_RRST_1 : in std_logic;\r
- FFC_RRST_2 : in std_logic;\r
- FFC_RRST_3 : in std_logic;\r
- FFC_RXPWDNB_0 : in std_logic;\r
- FFC_RXPWDNB_1 : in std_logic;\r
- FFC_RXPWDNB_2 : in std_logic;\r
- FFC_RXPWDNB_3 : in std_logic;\r
- FFC_SB_INV_RX_0 : in std_logic;\r
- FFC_SB_INV_RX_1 : in std_logic;\r
- FFC_SB_INV_RX_2 : in std_logic;\r
- FFC_SB_INV_RX_3 : in std_logic;\r
- FFC_SB_PFIFO_LP_0 : in std_logic;\r
- FFC_SB_PFIFO_LP_1 : in std_logic;\r
- FFC_SB_PFIFO_LP_2 : in std_logic;\r
- FFC_SB_PFIFO_LP_3 : in std_logic;\r
- FFC_SIGNAL_DETECT_0 : in std_logic;\r
- FFC_SIGNAL_DETECT_1 : in std_logic;\r
- FFC_SIGNAL_DETECT_2 : in std_logic;\r
- FFC_SIGNAL_DETECT_3 : in std_logic;\r
- FFC_TRST : in std_logic;\r
- FFC_TXPWDNB_0 : in std_logic;\r
- FFC_TXPWDNB_1 : in std_logic;\r
- FFC_TXPWDNB_2 : in std_logic;\r
- FFC_TXPWDNB_3 : in std_logic;\r
- SCIADDR0 : in std_logic;\r
- SCIADDR1 : in std_logic;\r
- SCIADDR2 : in std_logic;\r
- SCIADDR3 : in std_logic;\r
- SCIADDR4 : in std_logic;\r
- SCIADDR5 : in std_logic;\r
- SCIENAUX : in std_logic;\r
- SCIENCH0 : in std_logic;\r
- SCIENCH1 : in std_logic;\r
- SCIENCH2 : in std_logic;\r
- SCIENCH3 : in std_logic;\r
- SCIRD : in std_logic;\r
- SCISELAUX : in std_logic;\r
- SCISELCH0 : in std_logic;\r
- SCISELCH1 : in std_logic;\r
- SCISELCH2 : in std_logic;\r
- SCISELCH3 : in std_logic;\r
- SCIWDATA0 : in std_logic;\r
- SCIWDATA1 : in std_logic;\r
- SCIWDATA2 : in std_logic;\r
- SCIWDATA3 : in std_logic;\r
- SCIWDATA4 : in std_logic;\r
- SCIWDATA5 : in std_logic;\r
- SCIWDATA6 : in std_logic;\r
- SCIWDATA7 : in std_logic;\r
- SCIWSTN : in std_logic;\r
- HDOUTN0 : out std_logic;\r
- HDOUTN1 : out std_logic;\r
- HDOUTN2 : out std_logic;\r
- HDOUTN3 : out std_logic;\r
- HDOUTP0 : out std_logic;\r
- HDOUTP1 : out std_logic;\r
- HDOUTP2 : out std_logic;\r
- HDOUTP3 : out std_logic;\r
- COUT0 : out std_logic;\r
- COUT1 : out std_logic;\r
- COUT2 : out std_logic;\r
- COUT3 : out std_logic;\r
- COUT4 : out std_logic;\r
- COUT5 : out std_logic;\r
- COUT6 : out std_logic;\r
- COUT7 : out std_logic;\r
- COUT8 : out std_logic;\r
- COUT9 : out std_logic;\r
- COUT10 : out std_logic;\r
- COUT11 : out std_logic;\r
- COUT12 : out std_logic;\r
- COUT13 : out std_logic;\r
- COUT14 : out std_logic;\r
- COUT15 : out std_logic;\r
- COUT16 : out std_logic;\r
- COUT17 : out std_logic;\r
- COUT18 : out std_logic;\r
- COUT19 : out std_logic;\r
- FF_RX_D_0_0 : out std_logic;\r
- FF_RX_D_0_1 : out std_logic;\r
- FF_RX_D_0_2 : out std_logic;\r
- FF_RX_D_0_3 : out std_logic;\r
- FF_RX_D_0_4 : out std_logic;\r
- FF_RX_D_0_5 : out std_logic;\r
- FF_RX_D_0_6 : out std_logic;\r
- FF_RX_D_0_7 : out std_logic;\r
- FF_RX_D_0_8 : out std_logic;\r
- FF_RX_D_0_9 : out std_logic;\r
- FF_RX_D_0_10 : out std_logic;\r
- FF_RX_D_0_11 : out std_logic;\r
- FF_RX_D_0_12 : out std_logic;\r
- FF_RX_D_0_13 : out std_logic;\r
- FF_RX_D_0_14 : out std_logic;\r
- FF_RX_D_0_15 : out std_logic;\r
- FF_RX_D_0_16 : out std_logic;\r
- FF_RX_D_0_17 : out std_logic;\r
- FF_RX_D_0_18 : out std_logic;\r
- FF_RX_D_0_19 : out std_logic;\r
- FF_RX_D_0_20 : out std_logic;\r
- FF_RX_D_0_21 : out std_logic;\r
- FF_RX_D_0_22 : out std_logic;\r
- FF_RX_D_0_23 : out std_logic;\r
- FF_RX_D_1_0 : out std_logic;\r
- FF_RX_D_1_1 : out std_logic;\r
- FF_RX_D_1_2 : out std_logic;\r
- FF_RX_D_1_3 : out std_logic;\r
- FF_RX_D_1_4 : out std_logic;\r
- FF_RX_D_1_5 : out std_logic;\r
- FF_RX_D_1_6 : out std_logic;\r
- FF_RX_D_1_7 : out std_logic;\r
- FF_RX_D_1_8 : out std_logic;\r
- FF_RX_D_1_9 : out std_logic;\r
- FF_RX_D_1_10 : out std_logic;\r
- FF_RX_D_1_11 : out std_logic;\r
- FF_RX_D_1_12 : out std_logic;\r
- FF_RX_D_1_13 : out std_logic;\r
- FF_RX_D_1_14 : out std_logic;\r
- FF_RX_D_1_15 : out std_logic;\r
- FF_RX_D_1_16 : out std_logic;\r
- FF_RX_D_1_17 : out std_logic;\r
- FF_RX_D_1_18 : out std_logic;\r
- FF_RX_D_1_19 : out std_logic;\r
- FF_RX_D_1_20 : out std_logic;\r
- FF_RX_D_1_21 : out std_logic;\r
- FF_RX_D_1_22 : out std_logic;\r
- FF_RX_D_1_23 : out std_logic;\r
- FF_RX_D_2_0 : out std_logic;\r
- FF_RX_D_2_1 : out std_logic;\r
- FF_RX_D_2_2 : out std_logic;\r
- FF_RX_D_2_3 : out std_logic;\r
- FF_RX_D_2_4 : out std_logic;\r
- FF_RX_D_2_5 : out std_logic;\r
- FF_RX_D_2_6 : out std_logic;\r
- FF_RX_D_2_7 : out std_logic;\r
- FF_RX_D_2_8 : out std_logic;\r
- FF_RX_D_2_9 : out std_logic;\r
- FF_RX_D_2_10 : out std_logic;\r
- FF_RX_D_2_11 : out std_logic;\r
- FF_RX_D_2_12 : out std_logic;\r
- FF_RX_D_2_13 : out std_logic;\r
- FF_RX_D_2_14 : out std_logic;\r
- FF_RX_D_2_15 : out std_logic;\r
- FF_RX_D_2_16 : out std_logic;\r
- FF_RX_D_2_17 : out std_logic;\r
- FF_RX_D_2_18 : out std_logic;\r
- FF_RX_D_2_19 : out std_logic;\r
- FF_RX_D_2_20 : out std_logic;\r
- FF_RX_D_2_21 : out std_logic;\r
- FF_RX_D_2_22 : out std_logic;\r
- FF_RX_D_2_23 : out std_logic;\r
- FF_RX_D_3_0 : out std_logic;\r
- FF_RX_D_3_1 : out std_logic;\r
- FF_RX_D_3_2 : out std_logic;\r
- FF_RX_D_3_3 : out std_logic;\r
- FF_RX_D_3_4 : out std_logic;\r
- FF_RX_D_3_5 : out std_logic;\r
- FF_RX_D_3_6 : out std_logic;\r
- FF_RX_D_3_7 : out std_logic;\r
- FF_RX_D_3_8 : out std_logic;\r
- FF_RX_D_3_9 : out std_logic;\r
- FF_RX_D_3_10 : out std_logic;\r
- FF_RX_D_3_11 : out std_logic;\r
- FF_RX_D_3_12 : out std_logic;\r
- FF_RX_D_3_13 : out std_logic;\r
- FF_RX_D_3_14 : out std_logic;\r
- FF_RX_D_3_15 : out std_logic;\r
- FF_RX_D_3_16 : out std_logic;\r
- FF_RX_D_3_17 : out std_logic;\r
- FF_RX_D_3_18 : out std_logic;\r
- FF_RX_D_3_19 : out std_logic;\r
- FF_RX_D_3_20 : out std_logic;\r
- FF_RX_D_3_21 : out std_logic;\r
- FF_RX_D_3_22 : out std_logic;\r
- FF_RX_D_3_23 : out std_logic;\r
- FF_RX_F_CLK_0 : out std_logic;\r
- FF_RX_F_CLK_1 : out std_logic;\r
- FF_RX_F_CLK_2 : out std_logic;\r
- FF_RX_F_CLK_3 : out std_logic;\r
- FF_RX_H_CLK_0 : out std_logic;\r
- FF_RX_H_CLK_1 : out std_logic;\r
- FF_RX_H_CLK_2 : out std_logic;\r
- FF_RX_H_CLK_3 : out std_logic;\r
- FF_RX_Q_CLK_0 : out std_logic;\r
- FF_RX_Q_CLK_1 : out std_logic;\r
- FF_RX_Q_CLK_2 : out std_logic;\r
- FF_RX_Q_CLK_3 : out std_logic;\r
- FF_TX_F_CLK : out std_logic;\r
- FF_TX_H_CLK : out std_logic;\r
- FF_TX_Q_CLK : out std_logic;\r
- FFS_CC_OVERRUN_0 : out std_logic;\r
- FFS_CC_OVERRUN_1 : out std_logic;\r
- FFS_CC_OVERRUN_2 : out std_logic;\r
- FFS_CC_OVERRUN_3 : out std_logic;\r
- FFS_CC_UNDERRUN_0 : out std_logic;\r
- FFS_CC_UNDERRUN_1 : out std_logic;\r
- FFS_CC_UNDERRUN_2 : out std_logic;\r
- FFS_CC_UNDERRUN_3 : out std_logic;\r
- FFS_LS_SYNC_STATUS_0 : out std_logic;\r
- FFS_LS_SYNC_STATUS_1 : out std_logic;\r
- FFS_LS_SYNC_STATUS_2 : out std_logic;\r
- FFS_LS_SYNC_STATUS_3 : out std_logic;\r
- FFS_PCIE_CON_0 : out std_logic;\r
- FFS_PCIE_CON_1 : out std_logic;\r
- FFS_PCIE_CON_2 : out std_logic;\r
- FFS_PCIE_CON_3 : out std_logic;\r
- FFS_PCIE_DONE_0 : out std_logic;\r
- FFS_PCIE_DONE_1 : out std_logic;\r
- FFS_PCIE_DONE_2 : out std_logic;\r
- FFS_PCIE_DONE_3 : out std_logic;\r
- FFS_RLOS_LO_0 : out std_logic;\r
- FFS_RLOS_LO_1 : out std_logic;\r
- FFS_RLOS_LO_2 : out std_logic;\r
- FFS_RLOS_LO_3 : out std_logic;\r
- OOB_OUT_0 : out std_logic;\r
- OOB_OUT_1 : out std_logic;\r
- OOB_OUT_2 : out std_logic;\r
- OOB_OUT_3 : out std_logic;\r
- REFCK2CORE : out std_logic;\r
- SCIINT : out std_logic;\r
- SCIRDATA0 : out std_logic;\r
- SCIRDATA1 : out std_logic;\r
- SCIRDATA2 : out std_logic;\r
- SCIRDATA3 : out std_logic;\r
- SCIRDATA4 : out std_logic;\r
- SCIRDATA5 : out std_logic;\r
- SCIRDATA6 : out std_logic;\r
- SCIRDATA7 : out std_logic;\r
- FFS_PLOL : out std_logic;\r
- FFS_RLOL_0 : out std_logic;\r
- FFS_RLOL_1 : out std_logic;\r
- FFS_RLOL_2 : out std_logic;\r
- FFS_RLOL_3 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_3 : out std_logic\r
-);\r
-\r
-end PCSC;\r
-\r
-architecture PCSC_arch of PCSC is\r
-\r
-component PCSC_sim\r
-GENERIC(\r
- CONFIG_FILE : String\r
- );\r
-port (\r
- HDINN0 : in std_logic;\r
- HDINN1 : in std_logic;\r
- HDINN2 : in std_logic;\r
- HDINN3 : in std_logic;\r
- HDINP0 : in std_logic;\r
- HDINP1 : in std_logic;\r
- HDINP2 : in std_logic;\r
- HDINP3 : in std_logic;\r
- REFCLKN : in std_logic;\r
- REFCLKP : in std_logic;\r
- CIN0 : in std_logic;\r
- CIN1 : in std_logic;\r
- CIN2 : in std_logic;\r
- CIN3 : in std_logic;\r
- CIN4 : in std_logic;\r
- CIN5 : in std_logic;\r
- CIN6 : in std_logic;\r
- CIN7 : in std_logic;\r
- CIN8 : in std_logic;\r
- CIN9 : in std_logic;\r
- CIN10 : in std_logic;\r
- CIN11 : in std_logic;\r
- CYAWSTN : in std_logic;\r
- FF_EBRD_CLK_0 : in std_logic;\r
- FF_EBRD_CLK_1 : in std_logic;\r
- FF_EBRD_CLK_2 : in std_logic;\r
- FF_EBRD_CLK_3 : in std_logic;\r
- FF_RXI_CLK_0 : in std_logic;\r
- FF_RXI_CLK_1 : in std_logic;\r
- FF_RXI_CLK_2 : in std_logic;\r
- FF_RXI_CLK_3 : in std_logic;\r
- FF_TX_D_0_0 : in std_logic;\r
- FF_TX_D_0_1 : in std_logic;\r
- FF_TX_D_0_2 : in std_logic;\r
- FF_TX_D_0_3 : in std_logic;\r
- FF_TX_D_0_4 : in std_logic;\r
- FF_TX_D_0_5 : in std_logic;\r
- FF_TX_D_0_6 : in std_logic;\r
- FF_TX_D_0_7 : in std_logic;\r
- FF_TX_D_0_8 : in std_logic;\r
- FF_TX_D_0_9 : in std_logic;\r
- FF_TX_D_0_10 : in std_logic;\r
- FF_TX_D_0_11 : in std_logic;\r
- FF_TX_D_0_12 : in std_logic;\r
- FF_TX_D_0_13 : in std_logic;\r
- FF_TX_D_0_14 : in std_logic;\r
- FF_TX_D_0_15 : in std_logic;\r
- FF_TX_D_0_16 : in std_logic;\r
- FF_TX_D_0_17 : in std_logic;\r
- FF_TX_D_0_18 : in std_logic;\r
- FF_TX_D_0_19 : in std_logic;\r
- FF_TX_D_0_20 : in std_logic;\r
- FF_TX_D_0_21 : in std_logic;\r
- FF_TX_D_0_22 : in std_logic;\r
- FF_TX_D_0_23 : in std_logic;\r
- FF_TX_D_1_0 : in std_logic;\r
- FF_TX_D_1_1 : in std_logic;\r
- FF_TX_D_1_2 : in std_logic;\r
- FF_TX_D_1_3 : in std_logic;\r
- FF_TX_D_1_4 : in std_logic;\r
- FF_TX_D_1_5 : in std_logic;\r
- FF_TX_D_1_6 : in std_logic;\r
- FF_TX_D_1_7 : in std_logic;\r
- FF_TX_D_1_8 : in std_logic;\r
- FF_TX_D_1_9 : in std_logic;\r
- FF_TX_D_1_10 : in std_logic;\r
- FF_TX_D_1_11 : in std_logic;\r
- FF_TX_D_1_12 : in std_logic;\r
- FF_TX_D_1_13 : in std_logic;\r
- FF_TX_D_1_14 : in std_logic;\r
- FF_TX_D_1_15 : in std_logic;\r
- FF_TX_D_1_16 : in std_logic;\r
- FF_TX_D_1_17 : in std_logic;\r
- FF_TX_D_1_18 : in std_logic;\r
- FF_TX_D_1_19 : in std_logic;\r
- FF_TX_D_1_20 : in std_logic;\r
- FF_TX_D_1_21 : in std_logic;\r
- FF_TX_D_1_22 : in std_logic;\r
- FF_TX_D_1_23 : in std_logic;\r
- FF_TX_D_2_0 : in std_logic;\r
- FF_TX_D_2_1 : in std_logic;\r
- FF_TX_D_2_2 : in std_logic;\r
- FF_TX_D_2_3 : in std_logic;\r
- FF_TX_D_2_4 : in std_logic;\r
- FF_TX_D_2_5 : in std_logic;\r
- FF_TX_D_2_6 : in std_logic;\r
- FF_TX_D_2_7 : in std_logic;\r
- FF_TX_D_2_8 : in std_logic;\r
- FF_TX_D_2_9 : in std_logic;\r
- FF_TX_D_2_10 : in std_logic;\r
- FF_TX_D_2_11 : in std_logic;\r
- FF_TX_D_2_12 : in std_logic;\r
- FF_TX_D_2_13 : in std_logic;\r
- FF_TX_D_2_14 : in std_logic;\r
- FF_TX_D_2_15 : in std_logic;\r
- FF_TX_D_2_16 : in std_logic;\r
- FF_TX_D_2_17 : in std_logic;\r
- FF_TX_D_2_18 : in std_logic;\r
- FF_TX_D_2_19 : in std_logic;\r
- FF_TX_D_2_20 : in std_logic;\r
- FF_TX_D_2_21 : in std_logic;\r
- FF_TX_D_2_22 : in std_logic;\r
- FF_TX_D_2_23 : in std_logic;\r
- FF_TX_D_3_0 : in std_logic;\r
- FF_TX_D_3_1 : in std_logic;\r
- FF_TX_D_3_2 : in std_logic;\r
- FF_TX_D_3_3 : in std_logic;\r
- FF_TX_D_3_4 : in std_logic;\r
- FF_TX_D_3_5 : in std_logic;\r
- FF_TX_D_3_6 : in std_logic;\r
- FF_TX_D_3_7 : in std_logic;\r
- FF_TX_D_3_8 : in std_logic;\r
- FF_TX_D_3_9 : in std_logic;\r
- FF_TX_D_3_10 : in std_logic;\r
- FF_TX_D_3_11 : in std_logic;\r
- FF_TX_D_3_12 : in std_logic;\r
- FF_TX_D_3_13 : in std_logic;\r
- FF_TX_D_3_14 : in std_logic;\r
- FF_TX_D_3_15 : in std_logic;\r
- FF_TX_D_3_16 : in std_logic;\r
- FF_TX_D_3_17 : in std_logic;\r
- FF_TX_D_3_18 : in std_logic;\r
- FF_TX_D_3_19 : in std_logic;\r
- FF_TX_D_3_20 : in std_logic;\r
- FF_TX_D_3_21 : in std_logic;\r
- FF_TX_D_3_22 : in std_logic;\r
- FF_TX_D_3_23 : in std_logic;\r
- FF_TXI_CLK_0 : in std_logic;\r
- FF_TXI_CLK_1 : in std_logic;\r
- FF_TXI_CLK_2 : in std_logic;\r
- FF_TXI_CLK_3 : in std_logic;\r
- FFC_CK_CORE_RX : in std_logic;\r
- FFC_CK_CORE_TX : in std_logic;\r
- FFC_EI_EN_0 : in std_logic;\r
- FFC_EI_EN_1 : in std_logic;\r
- FFC_EI_EN_2 : in std_logic;\r
- FFC_EI_EN_3 : in std_logic;\r
- FFC_ENABLE_CGALIGN_0 : in std_logic;\r
- FFC_ENABLE_CGALIGN_1 : in std_logic;\r
- FFC_ENABLE_CGALIGN_2 : in std_logic;\r
- FFC_ENABLE_CGALIGN_3 : in std_logic;\r
- FFC_FB_LOOPBACK_0 : in std_logic;\r
- FFC_FB_LOOPBACK_1 : in std_logic;\r
- FFC_FB_LOOPBACK_2 : in std_logic;\r
- FFC_FB_LOOPBACK_3 : in std_logic;\r
- FFC_LANE_RX_RST_0 : in std_logic;\r
- FFC_LANE_RX_RST_1 : in std_logic;\r
- FFC_LANE_RX_RST_2 : in std_logic;\r
- FFC_LANE_RX_RST_3 : in std_logic;\r
- FFC_LANE_TX_RST_0 : in std_logic;\r
- FFC_LANE_TX_RST_1 : in std_logic;\r
- FFC_LANE_TX_RST_2 : in std_logic;\r
- FFC_LANE_TX_RST_3 : in std_logic;\r
- FFC_MACRO_RST : in std_logic;\r
- FFC_PCI_DET_EN_0 : in std_logic;\r
- FFC_PCI_DET_EN_1 : in std_logic;\r
- FFC_PCI_DET_EN_2 : in std_logic;\r
- FFC_PCI_DET_EN_3 : in std_logic;\r
- FFC_PCIE_CT_0 : in std_logic;\r
- FFC_PCIE_CT_1 : in std_logic;\r
- FFC_PCIE_CT_2 : in std_logic;\r
- FFC_PCIE_CT_3 : in std_logic;\r
- FFC_PFIFO_CLR_0 : in std_logic;\r
- FFC_PFIFO_CLR_1 : in std_logic;\r
- FFC_PFIFO_CLR_2 : in std_logic;\r
- FFC_PFIFO_CLR_3 : in std_logic;\r
- FFC_QUAD_RST : in std_logic;\r
- FFC_RRST_0 : in std_logic;\r
- FFC_RRST_1 : in std_logic;\r
- FFC_RRST_2 : in std_logic;\r
- FFC_RRST_3 : in std_logic;\r
- FFC_RXPWDNB_0 : in std_logic;\r
- FFC_RXPWDNB_1 : in std_logic;\r
- FFC_RXPWDNB_2 : in std_logic;\r
- FFC_RXPWDNB_3 : in std_logic;\r
- FFC_SB_INV_RX_0 : in std_logic;\r
- FFC_SB_INV_RX_1 : in std_logic;\r
- FFC_SB_INV_RX_2 : in std_logic;\r
- FFC_SB_INV_RX_3 : in std_logic;\r
- FFC_SB_PFIFO_LP_0 : in std_logic;\r
- FFC_SB_PFIFO_LP_1 : in std_logic;\r
- FFC_SB_PFIFO_LP_2 : in std_logic;\r
- FFC_SB_PFIFO_LP_3 : in std_logic;\r
- FFC_SIGNAL_DETECT_0 : in std_logic;\r
- FFC_SIGNAL_DETECT_1 : in std_logic;\r
- FFC_SIGNAL_DETECT_2 : in std_logic;\r
- FFC_SIGNAL_DETECT_3 : in std_logic;\r
- FFC_TRST : in std_logic;\r
- FFC_TXPWDNB_0 : in std_logic;\r
- FFC_TXPWDNB_1 : in std_logic;\r
- FFC_TXPWDNB_2 : in std_logic;\r
- FFC_TXPWDNB_3 : in std_logic;\r
- SCIADDR0 : in std_logic;\r
- SCIADDR1 : in std_logic;\r
- SCIADDR2 : in std_logic;\r
- SCIADDR3 : in std_logic;\r
- SCIADDR4 : in std_logic;\r
- SCIADDR5 : in std_logic;\r
- SCIENAUX : in std_logic;\r
- SCIENCH0 : in std_logic;\r
- SCIENCH1 : in std_logic;\r
- SCIENCH2 : in std_logic;\r
- SCIENCH3 : in std_logic;\r
- SCIRD : in std_logic;\r
- SCISELAUX : in std_logic;\r
- SCISELCH0 : in std_logic;\r
- SCISELCH1 : in std_logic;\r
- SCISELCH2 : in std_logic;\r
- SCISELCH3 : in std_logic;\r
- SCIWDATA0 : in std_logic;\r
- SCIWDATA1 : in std_logic;\r
- SCIWDATA2 : in std_logic;\r
- SCIWDATA3 : in std_logic;\r
- SCIWDATA4 : in std_logic;\r
- SCIWDATA5 : in std_logic;\r
- SCIWDATA6 : in std_logic;\r
- SCIWDATA7 : in std_logic;\r
- SCIWSTN : in std_logic;\r
- HDOUTN0 : out std_logic;\r
- HDOUTN1 : out std_logic;\r
- HDOUTN2 : out std_logic;\r
- HDOUTN3 : out std_logic;\r
- HDOUTP0 : out std_logic;\r
- HDOUTP1 : out std_logic;\r
- HDOUTP2 : out std_logic;\r
- HDOUTP3 : out std_logic;\r
- COUT0 : out std_logic;\r
- COUT1 : out std_logic;\r
- COUT2 : out std_logic;\r
- COUT3 : out std_logic;\r
- COUT4 : out std_logic;\r
- COUT5 : out std_logic;\r
- COUT6 : out std_logic;\r
- COUT7 : out std_logic;\r
- COUT8 : out std_logic;\r
- COUT9 : out std_logic;\r
- COUT10 : out std_logic;\r
- COUT11 : out std_logic;\r
- COUT12 : out std_logic;\r
- COUT13 : out std_logic;\r
- COUT14 : out std_logic;\r
- COUT15 : out std_logic;\r
- COUT16 : out std_logic;\r
- COUT17 : out std_logic;\r
- COUT18 : out std_logic;\r
- COUT19 : out std_logic;\r
- FF_RX_D_0_0 : out std_logic;\r
- FF_RX_D_0_1 : out std_logic;\r
- FF_RX_D_0_2 : out std_logic;\r
- FF_RX_D_0_3 : out std_logic;\r
- FF_RX_D_0_4 : out std_logic;\r
- FF_RX_D_0_5 : out std_logic;\r
- FF_RX_D_0_6 : out std_logic;\r
- FF_RX_D_0_7 : out std_logic;\r
- FF_RX_D_0_8 : out std_logic;\r
- FF_RX_D_0_9 : out std_logic;\r
- FF_RX_D_0_10 : out std_logic;\r
- FF_RX_D_0_11 : out std_logic;\r
- FF_RX_D_0_12 : out std_logic;\r
- FF_RX_D_0_13 : out std_logic;\r
- FF_RX_D_0_14 : out std_logic;\r
- FF_RX_D_0_15 : out std_logic;\r
- FF_RX_D_0_16 : out std_logic;\r
- FF_RX_D_0_17 : out std_logic;\r
- FF_RX_D_0_18 : out std_logic;\r
- FF_RX_D_0_19 : out std_logic;\r
- FF_RX_D_0_20 : out std_logic;\r
- FF_RX_D_0_21 : out std_logic;\r
- FF_RX_D_0_22 : out std_logic;\r
- FF_RX_D_0_23 : out std_logic;\r
- FF_RX_D_1_0 : out std_logic;\r
- FF_RX_D_1_1 : out std_logic;\r
- FF_RX_D_1_2 : out std_logic;\r
- FF_RX_D_1_3 : out std_logic;\r
- FF_RX_D_1_4 : out std_logic;\r
- FF_RX_D_1_5 : out std_logic;\r
- FF_RX_D_1_6 : out std_logic;\r
- FF_RX_D_1_7 : out std_logic;\r
- FF_RX_D_1_8 : out std_logic;\r
- FF_RX_D_1_9 : out std_logic;\r
- FF_RX_D_1_10 : out std_logic;\r
- FF_RX_D_1_11 : out std_logic;\r
- FF_RX_D_1_12 : out std_logic;\r
- FF_RX_D_1_13 : out std_logic;\r
- FF_RX_D_1_14 : out std_logic;\r
- FF_RX_D_1_15 : out std_logic;\r
- FF_RX_D_1_16 : out std_logic;\r
- FF_RX_D_1_17 : out std_logic;\r
- FF_RX_D_1_18 : out std_logic;\r
- FF_RX_D_1_19 : out std_logic;\r
- FF_RX_D_1_20 : out std_logic;\r
- FF_RX_D_1_21 : out std_logic;\r
- FF_RX_D_1_22 : out std_logic;\r
- FF_RX_D_1_23 : out std_logic;\r
- FF_RX_D_2_0 : out std_logic;\r
- FF_RX_D_2_1 : out std_logic;\r
- FF_RX_D_2_2 : out std_logic;\r
- FF_RX_D_2_3 : out std_logic;\r
- FF_RX_D_2_4 : out std_logic;\r
- FF_RX_D_2_5 : out std_logic;\r
- FF_RX_D_2_6 : out std_logic;\r
- FF_RX_D_2_7 : out std_logic;\r
- FF_RX_D_2_8 : out std_logic;\r
- FF_RX_D_2_9 : out std_logic;\r
- FF_RX_D_2_10 : out std_logic;\r
- FF_RX_D_2_11 : out std_logic;\r
- FF_RX_D_2_12 : out std_logic;\r
- FF_RX_D_2_13 : out std_logic;\r
- FF_RX_D_2_14 : out std_logic;\r
- FF_RX_D_2_15 : out std_logic;\r
- FF_RX_D_2_16 : out std_logic;\r
- FF_RX_D_2_17 : out std_logic;\r
- FF_RX_D_2_18 : out std_logic;\r
- FF_RX_D_2_19 : out std_logic;\r
- FF_RX_D_2_20 : out std_logic;\r
- FF_RX_D_2_21 : out std_logic;\r
- FF_RX_D_2_22 : out std_logic;\r
- FF_RX_D_2_23 : out std_logic;\r
- FF_RX_D_3_0 : out std_logic;\r
- FF_RX_D_3_1 : out std_logic;\r
- FF_RX_D_3_2 : out std_logic;\r
- FF_RX_D_3_3 : out std_logic;\r
- FF_RX_D_3_4 : out std_logic;\r
- FF_RX_D_3_5 : out std_logic;\r
- FF_RX_D_3_6 : out std_logic;\r
- FF_RX_D_3_7 : out std_logic;\r
- FF_RX_D_3_8 : out std_logic;\r
- FF_RX_D_3_9 : out std_logic;\r
- FF_RX_D_3_10 : out std_logic;\r
- FF_RX_D_3_11 : out std_logic;\r
- FF_RX_D_3_12 : out std_logic;\r
- FF_RX_D_3_13 : out std_logic;\r
- FF_RX_D_3_14 : out std_logic;\r
- FF_RX_D_3_15 : out std_logic;\r
- FF_RX_D_3_16 : out std_logic;\r
- FF_RX_D_3_17 : out std_logic;\r
- FF_RX_D_3_18 : out std_logic;\r
- FF_RX_D_3_19 : out std_logic;\r
- FF_RX_D_3_20 : out std_logic;\r
- FF_RX_D_3_21 : out std_logic;\r
- FF_RX_D_3_22 : out std_logic;\r
- FF_RX_D_3_23 : out std_logic;\r
- FF_RX_F_CLK_0 : out std_logic;\r
- FF_RX_F_CLK_1 : out std_logic;\r
- FF_RX_F_CLK_2 : out std_logic;\r
- FF_RX_F_CLK_3 : out std_logic;\r
- FF_RX_H_CLK_0 : out std_logic;\r
- FF_RX_H_CLK_1 : out std_logic;\r
- FF_RX_H_CLK_2 : out std_logic;\r
- FF_RX_H_CLK_3 : out std_logic;\r
- FF_RX_Q_CLK_0 : out std_logic;\r
- FF_RX_Q_CLK_1 : out std_logic;\r
- FF_RX_Q_CLK_2 : out std_logic;\r
- FF_RX_Q_CLK_3 : out std_logic;\r
- FF_TX_F_CLK : out std_logic;\r
- FF_TX_H_CLK : out std_logic;\r
- FF_TX_Q_CLK : out std_logic;\r
- FFS_CC_OVERRUN_0 : out std_logic;\r
- FFS_CC_OVERRUN_1 : out std_logic;\r
- FFS_CC_OVERRUN_2 : out std_logic;\r
- FFS_CC_OVERRUN_3 : out std_logic;\r
- FFS_CC_UNDERRUN_0 : out std_logic;\r
- FFS_CC_UNDERRUN_1 : out std_logic;\r
- FFS_CC_UNDERRUN_2 : out std_logic;\r
- FFS_CC_UNDERRUN_3 : out std_logic;\r
- FFS_LS_SYNC_STATUS_0 : out std_logic;\r
- FFS_LS_SYNC_STATUS_1 : out std_logic;\r
- FFS_LS_SYNC_STATUS_2 : out std_logic;\r
- FFS_LS_SYNC_STATUS_3 : out std_logic;\r
- FFS_PCIE_CON_0 : out std_logic;\r
- FFS_PCIE_CON_1 : out std_logic;\r
- FFS_PCIE_CON_2 : out std_logic;\r
- FFS_PCIE_CON_3 : out std_logic;\r
- FFS_PCIE_DONE_0 : out std_logic;\r
- FFS_PCIE_DONE_1 : out std_logic;\r
- FFS_PCIE_DONE_2 : out std_logic;\r
- FFS_PCIE_DONE_3 : out std_logic;\r
- FFS_RLOS_LO_0 : out std_logic;\r
- FFS_RLOS_LO_1 : out std_logic;\r
- FFS_RLOS_LO_2 : out std_logic;\r
- FFS_RLOS_LO_3 : out std_logic;\r
- OOB_OUT_0 : out std_logic;\r
- OOB_OUT_1 : out std_logic;\r
- OOB_OUT_2 : out std_logic;\r
- OOB_OUT_3 : out std_logic;\r
- REFCK2CORE : out std_logic;\r
- SCIINT : out std_logic;\r
- SCIRDATA0 : out std_logic;\r
- SCIRDATA1 : out std_logic;\r
- SCIRDATA2 : out std_logic;\r
- SCIRDATA3 : out std_logic;\r
- SCIRDATA4 : out std_logic;\r
- SCIRDATA5 : out std_logic;\r
- SCIRDATA6 : out std_logic;\r
- SCIRDATA7 : out std_logic;\r
- FFS_PLOL : out std_logic;\r
- FFS_RLOL_0 : out std_logic;\r
- FFS_RLOL_1 : out std_logic;\r
- FFS_RLOL_2 : out std_logic;\r
- FFS_RLOL_3 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_3 : out std_logic\r
-);\r
-end component;\r
-\r
-begin\r
-\r
-PCSC_sim_inst : PCSC_sim\r
-generic map (\r
- CONFIG_FILE => CONFIG_FILE)\r
-port map (\r
- HDINN0 => HDINN0,\r
- HDINN1 => HDINN1,\r
- HDINN2 => HDINN2,\r
- HDINN3 => HDINN3,\r
- HDINP0 => HDINP0,\r
- HDINP1 => HDINP1,\r
- HDINP2 => HDINP2,\r
- HDINP3 => HDINP3,\r
- REFCLKN => REFCLKN,\r
- REFCLKP => REFCLKP,\r
- CIN11 => CIN11,\r
- CIN10 => CIN10,\r
- CIN9 => CIN9,\r
- CIN8 => CIN8,\r
- CIN7 => CIN7,\r
- CIN6 => CIN6,\r
- CIN5 => CIN5,\r
- CIN4 => CIN4,\r
- CIN3 => CIN3,\r
- CIN2 => CIN2,\r
- CIN1 => CIN1,\r
- CIN0 => CIN0,\r
- CYAWSTN => CYAWSTN,\r
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,\r
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,\r
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,\r
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,\r
- FF_RXI_CLK_3 => FF_RXI_CLK_3,\r
- FF_RXI_CLK_2 => FF_RXI_CLK_2,\r
- FF_RXI_CLK_1 => FF_RXI_CLK_1,\r
- FF_RXI_CLK_0 => FF_RXI_CLK_0,\r
-\r
- FF_TX_D_0_0 => FF_TX_D_0_0,\r
- FF_TX_D_0_1 => FF_TX_D_0_1,\r
- FF_TX_D_0_2 => FF_TX_D_0_2,\r
- FF_TX_D_0_3 => FF_TX_D_0_3,\r
- FF_TX_D_0_4 => FF_TX_D_0_4,\r
- FF_TX_D_0_5 => FF_TX_D_0_5,\r
- FF_TX_D_0_6 => FF_TX_D_0_6,\r
- FF_TX_D_0_7 => FF_TX_D_0_7,\r
- FF_TX_D_0_8 => FF_TX_D_0_8,\r
- FF_TX_D_0_9 => FF_TX_D_0_9,\r
- FF_TX_D_0_10 => FF_TX_D_0_10,\r
- FF_TX_D_0_11 => FF_TX_D_0_11,\r
- FF_TX_D_0_12 => FF_TX_D_0_12,\r
- FF_TX_D_0_13 => FF_TX_D_0_13,\r
- FF_TX_D_0_14 => FF_TX_D_0_14,\r
- FF_TX_D_0_15 => FF_TX_D_0_15,\r
- FF_TX_D_0_16 => FF_TX_D_0_16,\r
- FF_TX_D_0_17 => FF_TX_D_0_17,\r
- FF_TX_D_0_18 => FF_TX_D_0_18,\r
- FF_TX_D_0_19 => FF_TX_D_0_19,\r
- FF_TX_D_0_20 => FF_TX_D_0_20,\r
- FF_TX_D_0_21 => FF_TX_D_0_21,\r
- FF_TX_D_0_22 => FF_TX_D_0_22,\r
- FF_TX_D_0_23 => FF_TX_D_0_23,\r
- FF_TX_D_1_0 => FF_TX_D_1_0,\r
- FF_TX_D_1_1 => FF_TX_D_1_1,\r
- FF_TX_D_1_2 => FF_TX_D_1_2,\r
- FF_TX_D_1_3 => FF_TX_D_1_3,\r
- FF_TX_D_1_4 => FF_TX_D_1_4,\r
- FF_TX_D_1_5 => FF_TX_D_1_5,\r
- FF_TX_D_1_6 => FF_TX_D_1_6,\r
- FF_TX_D_1_7 => FF_TX_D_1_7,\r
- FF_TX_D_1_8 => FF_TX_D_1_8,\r
- FF_TX_D_1_9 => FF_TX_D_1_9,\r
- FF_TX_D_1_10 => FF_TX_D_1_10,\r
- FF_TX_D_1_11 => FF_TX_D_1_11,\r
- FF_TX_D_1_12 => FF_TX_D_1_12,\r
- FF_TX_D_1_13 => FF_TX_D_1_13,\r
- FF_TX_D_1_14 => FF_TX_D_1_14,\r
- FF_TX_D_1_15 => FF_TX_D_1_15,\r
- FF_TX_D_1_16 => FF_TX_D_1_16,\r
- FF_TX_D_1_17 => FF_TX_D_1_17,\r
- FF_TX_D_1_18 => FF_TX_D_1_18,\r
- FF_TX_D_1_19 => FF_TX_D_1_19,\r
- FF_TX_D_1_20 => FF_TX_D_1_20,\r
- FF_TX_D_1_21 => FF_TX_D_1_21,\r
- FF_TX_D_1_22 => FF_TX_D_1_22,\r
- FF_TX_D_1_23 => FF_TX_D_1_23,\r
- FF_TX_D_2_0 => FF_TX_D_2_0,\r
- FF_TX_D_2_1 => FF_TX_D_2_1,\r
- FF_TX_D_2_2 => FF_TX_D_2_2,\r
- FF_TX_D_2_3 => FF_TX_D_2_3,\r
- FF_TX_D_2_4 => FF_TX_D_2_4,\r
- FF_TX_D_2_5 => FF_TX_D_2_5,\r
- FF_TX_D_2_6 => FF_TX_D_2_6,\r
- FF_TX_D_2_7 => FF_TX_D_2_7,\r
- FF_TX_D_2_8 => FF_TX_D_2_8,\r
- FF_TX_D_2_9 => FF_TX_D_2_9,\r
- FF_TX_D_2_10 => FF_TX_D_2_10,\r
- FF_TX_D_2_11 => FF_TX_D_2_11,\r
- FF_TX_D_2_12 => FF_TX_D_2_12,\r
- FF_TX_D_2_13 => FF_TX_D_2_13,\r
- FF_TX_D_2_14 => FF_TX_D_2_14,\r
- FF_TX_D_2_15 => FF_TX_D_2_15,\r
- FF_TX_D_2_16 => FF_TX_D_2_16,\r
- FF_TX_D_2_17 => FF_TX_D_2_17,\r
- FF_TX_D_2_18 => FF_TX_D_2_18,\r
- FF_TX_D_2_19 => FF_TX_D_2_19,\r
- FF_TX_D_2_20 => FF_TX_D_2_20,\r
- FF_TX_D_2_21 => FF_TX_D_2_21,\r
- FF_TX_D_2_22 => FF_TX_D_2_22,\r
- FF_TX_D_2_23 => FF_TX_D_2_23,\r
- FF_TX_D_3_0 => FF_TX_D_3_0,\r
- FF_TX_D_3_1 => FF_TX_D_3_1,\r
- FF_TX_D_3_2 => FF_TX_D_3_2,\r
- FF_TX_D_3_3 => FF_TX_D_3_3,\r
- FF_TX_D_3_4 => FF_TX_D_3_4,\r
- FF_TX_D_3_5 => FF_TX_D_3_5,\r
- FF_TX_D_3_6 => FF_TX_D_3_6,\r
- FF_TX_D_3_7 => FF_TX_D_3_7,\r
- FF_TX_D_3_8 => FF_TX_D_3_8,\r
- FF_TX_D_3_9 => FF_TX_D_3_9,\r
- FF_TX_D_3_10 => FF_TX_D_3_10,\r
- FF_TX_D_3_11 => FF_TX_D_3_11,\r
- FF_TX_D_3_12 => FF_TX_D_3_12,\r
- FF_TX_D_3_13 => FF_TX_D_3_13,\r
- FF_TX_D_3_14 => FF_TX_D_3_14,\r
- FF_TX_D_3_15 => FF_TX_D_3_15,\r
- FF_TX_D_3_16 => FF_TX_D_3_16,\r
- FF_TX_D_3_17 => FF_TX_D_3_17,\r
- FF_TX_D_3_18 => FF_TX_D_3_18,\r
- FF_TX_D_3_19 => FF_TX_D_3_19,\r
- FF_TX_D_3_20 => FF_TX_D_3_20,\r
- FF_TX_D_3_21 => FF_TX_D_3_21,\r
- FF_TX_D_3_22 => FF_TX_D_3_22,\r
- FF_TX_D_3_23 => FF_TX_D_3_23,\r
- FF_TXI_CLK_0 => FF_TXI_CLK_0,\r
- FF_TXI_CLK_1 => FF_TXI_CLK_1,\r
- FF_TXI_CLK_2 => FF_TXI_CLK_2,\r
- FF_TXI_CLK_3 => FF_TXI_CLK_3,\r
- FFC_CK_CORE_RX => FFC_CK_CORE_RX,\r
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,\r
- FFC_EI_EN_0 => FFC_EI_EN_0,\r
- FFC_EI_EN_1 => FFC_EI_EN_1,\r
- FFC_EI_EN_2 => FFC_EI_EN_2,\r
- FFC_EI_EN_3 => FFC_EI_EN_3,\r
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,\r
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,\r
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,\r
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,\r
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,\r
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,\r
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,\r
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,\r
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,\r
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,\r
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,\r
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,\r
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,\r
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,\r
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,\r
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,\r
- FFC_MACRO_RST => FFC_MACRO_RST,\r
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,\r
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,\r
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,\r
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,\r
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,\r
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,\r
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,\r
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,\r
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,\r
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,\r
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,\r
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,\r
- FFC_QUAD_RST => FFC_QUAD_RST,\r
- FFC_RRST_0 => FFC_RRST_0,\r
- FFC_RRST_1 => FFC_RRST_1,\r
- FFC_RRST_2 => FFC_RRST_2,\r
- FFC_RRST_3 => FFC_RRST_3,\r
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,\r
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,\r
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,\r
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,\r
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,\r
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,\r
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,\r
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,\r
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,\r
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,\r
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,\r
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,\r
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,\r
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,\r
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,\r
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,\r
- FFC_TRST => FFC_TRST,\r
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,\r
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,\r
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,\r
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,\r
- SCIADDR0 => SCIADDR0,\r
- SCIADDR1 => SCIADDR1,\r
- SCIADDR2 => SCIADDR2,\r
- SCIADDR3 => SCIADDR3,\r
- SCIADDR4 => SCIADDR4,\r
- SCIADDR5 => SCIADDR5,\r
- SCIENAUX => SCIENAUX,\r
- SCIENCH0 => SCIENCH0,\r
- SCIENCH1 => SCIENCH1,\r
- SCIENCH2 => SCIENCH2,\r
- SCIENCH3 => SCIENCH3,\r
- SCIRD => SCIRD,\r
- SCISELAUX => SCISELAUX,\r
- SCISELCH0 => SCISELCH0,\r
- SCISELCH1 => SCISELCH1,\r
- SCISELCH2 => SCISELCH2,\r
- SCISELCH3 => SCISELCH3,\r
- SCIWDATA0 => SCIWDATA0,\r
- SCIWDATA1 => SCIWDATA1,\r
- SCIWDATA2 => SCIWDATA2,\r
- SCIWDATA3 => SCIWDATA3,\r
- SCIWDATA4 => SCIWDATA4,\r
- SCIWDATA5 => SCIWDATA5,\r
- SCIWDATA6 => SCIWDATA6,\r
- SCIWDATA7 => SCIWDATA7,\r
- SCIWSTN => SCIWSTN,\r
- HDOUTN0 => HDOUTN0,\r
- HDOUTN1 => HDOUTN1,\r
- HDOUTN2 => HDOUTN2,\r
- HDOUTN3 => HDOUTN3,\r
- HDOUTP0 => HDOUTP0,\r
- HDOUTP1 => HDOUTP1,\r
- HDOUTP2 => HDOUTP2,\r
- HDOUTP3 => HDOUTP3,\r
- COUT19 => COUT19,\r
- COUT18 => COUT18,\r
- COUT17 => COUT17,\r
- COUT16 => COUT16,\r
- COUT15 => COUT15,\r
- COUT14 => COUT14,\r
- COUT13 => COUT13,\r
- COUT12 => COUT12,\r
- COUT11 => COUT11,\r
- COUT10 => COUT10,\r
- COUT9 => COUT9,\r
- COUT8 => COUT8,\r
- COUT7 => COUT7,\r
- COUT6 => COUT6,\r
- COUT5 => COUT5,\r
- COUT4 => COUT4,\r
- COUT3 => COUT3,\r
- COUT2 => COUT2,\r
- COUT1 => COUT1,\r
- COUT0 => COUT0,\r
- FF_RX_D_0_0 => FF_RX_D_0_0,\r
- FF_RX_D_0_1 => FF_RX_D_0_1,\r
- FF_RX_D_0_2 => FF_RX_D_0_2,\r
- FF_RX_D_0_3 => FF_RX_D_0_3,\r
- FF_RX_D_0_4 => FF_RX_D_0_4,\r
- FF_RX_D_0_5 => FF_RX_D_0_5,\r
- FF_RX_D_0_6 => FF_RX_D_0_6,\r
- FF_RX_D_0_7 => FF_RX_D_0_7,\r
- FF_RX_D_0_8 => FF_RX_D_0_8,\r
- FF_RX_D_0_9 => FF_RX_D_0_9,\r
- FF_RX_D_0_10 => FF_RX_D_0_10,\r
- FF_RX_D_0_11 => FF_RX_D_0_11,\r
- FF_RX_D_0_12 => FF_RX_D_0_12,\r
- FF_RX_D_0_13 => FF_RX_D_0_13,\r
- FF_RX_D_0_14 => FF_RX_D_0_14,\r
- FF_RX_D_0_15 => FF_RX_D_0_15,\r
- FF_RX_D_0_16 => FF_RX_D_0_16,\r
- FF_RX_D_0_17 => FF_RX_D_0_17,\r
- FF_RX_D_0_18 => FF_RX_D_0_18,\r
- FF_RX_D_0_19 => FF_RX_D_0_19,\r
- FF_RX_D_0_20 => FF_RX_D_0_20,\r
- FF_RX_D_0_21 => FF_RX_D_0_21,\r
- FF_RX_D_0_22 => FF_RX_D_0_22,\r
- FF_RX_D_0_23 => FF_RX_D_0_23,\r
- FF_RX_D_1_0 => FF_RX_D_1_0,\r
- FF_RX_D_1_1 => FF_RX_D_1_1,\r
- FF_RX_D_1_2 => FF_RX_D_1_2,\r
- FF_RX_D_1_3 => FF_RX_D_1_3,\r
- FF_RX_D_1_4 => FF_RX_D_1_4,\r
- FF_RX_D_1_5 => FF_RX_D_1_5,\r
- FF_RX_D_1_6 => FF_RX_D_1_6,\r
- FF_RX_D_1_7 => FF_RX_D_1_7,\r
- FF_RX_D_1_8 => FF_RX_D_1_8,\r
- FF_RX_D_1_9 => FF_RX_D_1_9,\r
- FF_RX_D_1_10 => FF_RX_D_1_10,\r
- FF_RX_D_1_11 => FF_RX_D_1_11,\r
- FF_RX_D_1_12 => FF_RX_D_1_12,\r
- FF_RX_D_1_13 => FF_RX_D_1_13,\r
- FF_RX_D_1_14 => FF_RX_D_1_14,\r
- FF_RX_D_1_15 => FF_RX_D_1_15,\r
- FF_RX_D_1_16 => FF_RX_D_1_16,\r
- FF_RX_D_1_17 => FF_RX_D_1_17,\r
- FF_RX_D_1_18 => FF_RX_D_1_18,\r
- FF_RX_D_1_19 => FF_RX_D_1_19,\r
- FF_RX_D_1_20 => FF_RX_D_1_20,\r
- FF_RX_D_1_21 => FF_RX_D_1_21,\r
- FF_RX_D_1_22 => FF_RX_D_1_22,\r
- FF_RX_D_1_23 => FF_RX_D_1_23,\r
- FF_RX_D_2_0 => FF_RX_D_2_0,\r
- FF_RX_D_2_1 => FF_RX_D_2_1,\r
- FF_RX_D_2_2 => FF_RX_D_2_2,\r
- FF_RX_D_2_3 => FF_RX_D_2_3,\r
- FF_RX_D_2_4 => FF_RX_D_2_4,\r
- FF_RX_D_2_5 => FF_RX_D_2_5,\r
- FF_RX_D_2_6 => FF_RX_D_2_6,\r
- FF_RX_D_2_7 => FF_RX_D_2_7,\r
- FF_RX_D_2_8 => FF_RX_D_2_8,\r
- FF_RX_D_2_9 => FF_RX_D_2_9,\r
- FF_RX_D_2_10 => FF_RX_D_2_10,\r
- FF_RX_D_2_11 => FF_RX_D_2_11,\r
- FF_RX_D_2_12 => FF_RX_D_2_12,\r
- FF_RX_D_2_13 => FF_RX_D_2_13,\r
- FF_RX_D_2_14 => FF_RX_D_2_14,\r
- FF_RX_D_2_15 => FF_RX_D_2_15,\r
- FF_RX_D_2_16 => FF_RX_D_2_16,\r
- FF_RX_D_2_17 => FF_RX_D_2_17,\r
- FF_RX_D_2_18 => FF_RX_D_2_18,\r
- FF_RX_D_2_19 => FF_RX_D_2_19,\r
- FF_RX_D_2_20 => FF_RX_D_2_20,\r
- FF_RX_D_2_21 => FF_RX_D_2_21,\r
- FF_RX_D_2_22 => FF_RX_D_2_22,\r
- FF_RX_D_2_23 => FF_RX_D_2_23,\r
- FF_RX_D_3_0 => FF_RX_D_3_0,\r
- FF_RX_D_3_1 => FF_RX_D_3_1,\r
- FF_RX_D_3_2 => FF_RX_D_3_2,\r
- FF_RX_D_3_3 => FF_RX_D_3_3,\r
- FF_RX_D_3_4 => FF_RX_D_3_4,\r
- FF_RX_D_3_5 => FF_RX_D_3_5,\r
- FF_RX_D_3_6 => FF_RX_D_3_6,\r
- FF_RX_D_3_7 => FF_RX_D_3_7,\r
- FF_RX_D_3_8 => FF_RX_D_3_8,\r
- FF_RX_D_3_9 => FF_RX_D_3_9,\r
- FF_RX_D_3_10 => FF_RX_D_3_10,\r
- FF_RX_D_3_11 => FF_RX_D_3_11,\r
- FF_RX_D_3_12 => FF_RX_D_3_12,\r
- FF_RX_D_3_13 => FF_RX_D_3_13,\r
- FF_RX_D_3_14 => FF_RX_D_3_14,\r
- FF_RX_D_3_15 => FF_RX_D_3_15,\r
- FF_RX_D_3_16 => FF_RX_D_3_16,\r
- FF_RX_D_3_17 => FF_RX_D_3_17,\r
- FF_RX_D_3_18 => FF_RX_D_3_18,\r
- FF_RX_D_3_19 => FF_RX_D_3_19,\r
- FF_RX_D_3_20 => FF_RX_D_3_20,\r
- FF_RX_D_3_21 => FF_RX_D_3_21,\r
- FF_RX_D_3_22 => FF_RX_D_3_22,\r
- FF_RX_D_3_23 => FF_RX_D_3_23,\r
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,\r
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,\r
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,\r
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,\r
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,\r
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,\r
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,\r
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,\r
- FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,\r
- FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,\r
- FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,\r
- FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,\r
- FF_TX_F_CLK => FF_TX_F_CLK,\r
- FF_TX_H_CLK => FF_TX_H_CLK,\r
- FF_TX_Q_CLK => FF_TX_Q_CLK,\r
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,\r
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,\r
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,\r
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,\r
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,\r
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,\r
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,\r
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,\r
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,\r
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,\r
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,\r
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,\r
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,\r
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,\r
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,\r
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,\r
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,\r
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,\r
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,\r
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,\r
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,\r
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,\r
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,\r
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,\r
- FFS_PLOL => FFS_PLOL,\r
- FFS_RLOL_0 => FFS_RLOL_0,\r
- FFS_RLOL_1 => FFS_RLOL_1,\r
- FFS_RLOL_2 => FFS_RLOL_2,\r
- FFS_RLOL_3 => FFS_RLOL_3,\r
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,\r
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,\r
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,\r
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,\r
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,\r
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,\r
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,\r
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,\r
- OOB_OUT_0 => OOB_OUT_0,\r
- OOB_OUT_1 => OOB_OUT_1,\r
- OOB_OUT_2 => OOB_OUT_2,\r
- OOB_OUT_3 => OOB_OUT_3,\r
- REFCK2CORE => REFCK2CORE,\r
- SCIINT => SCIINT,\r
- SCIRDATA0 => SCIRDATA0,\r
- SCIRDATA1 => SCIRDATA1,\r
- SCIRDATA2 => SCIRDATA2,\r
- SCIRDATA3 => SCIRDATA3,\r
- SCIRDATA4 => SCIRDATA4,\r
- SCIRDATA5 => SCIRDATA5,\r
- SCIRDATA6 => SCIRDATA6,\r
- SCIRDATA7 => SCIRDATA7\r
- );\r
-\r
-end PCSC_arch;\r
-\r
---synopsys translate_on\r
-\r
---synopsys translate_off\r
-library ECP2;\r
-use ECP2.components.all;\r
---synopsys translate_on\r
-\r
-library IEEE, STD;\r
-use IEEE.std_logic_1164.all;\r
-use STD.TEXTIO.all;\r
-\r
-entity serdes_gbe_0_extclock_8b is\r
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt");\r
- port (\r
- refclkp, refclkn : in std_logic;\r
- hdinp0, hdinn0 : in std_logic;\r
- hdoutp0, hdoutn0 : out std_logic;\r
- ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;\r
- ff_txdata_ch0 : in std_logic_vector (7 downto 0);\r
- ff_rxdata_ch0 : out std_logic_vector (7 downto 0);\r
- ff_tx_k_cntrl_ch0 : in std_logic;\r
- ff_rx_k_cntrl_ch0 : out std_logic;\r
- ff_rxfullclk_ch0 : out std_logic;\r
- ff_xmit_ch0 : in std_logic;\r
- ff_correct_disp_ch0 : in std_logic;\r
- ff_disp_err_ch0, ff_cv_ch0 : out std_logic;\r
- ff_rx_even_ch0 : out std_logic;\r
- ffc_rrst_ch0 : in std_logic;\r
- ffc_lane_tx_rst_ch0 : in std_logic;\r
- ffc_lane_rx_rst_ch0 : in std_logic;\r
- ffc_txpwdnb_ch0 : in std_logic;\r
- ffc_rxpwdnb_ch0 : in std_logic;\r
- ffs_rlos_lo_ch0 : out std_logic;\r
- ffs_ls_sync_status_ch0 : out std_logic;\r
- ffs_rlol_ch0 : out std_logic;\r
- oob_out_ch0 : out std_logic;\r
- ffc_macro_rst : in std_logic;\r
- ffc_quad_rst : in std_logic;\r
- ffc_trst : in std_logic;\r
- ff_txfullclk : out std_logic;\r
- ff_txhalfclk : out std_logic;\r
- refck2core : out std_logic;\r
- ffs_plol : out std_logic);\r
-\r
-end serdes_gbe_0_extclock_8b;\r
-\r
-architecture serdes_gbe_0_extclock_8b_arch of serdes_gbe_0_extclock_8b is\r
-\r
-component VLO\r
-port (\r
- Z : out std_logic);\r
-end component;\r
-\r
-component VHI\r
-port (\r
- Z : out std_logic);\r
-end component;\r
-component PCSC\r
---synopsys translate_off\r
-GENERIC(\r
- CONFIG_FILE : String\r
- );\r
---synopsys translate_on\r
-port (\r
- HDINN0 : in std_logic;\r
- HDINN1 : in std_logic;\r
- HDINN2 : in std_logic;\r
- HDINN3 : in std_logic;\r
- HDINP0 : in std_logic;\r
- HDINP1 : in std_logic;\r
- HDINP2 : in std_logic;\r
- HDINP3 : in std_logic;\r
- REFCLKN : in std_logic;\r
- REFCLKP : in std_logic;\r
- CIN0 : in std_logic;\r
- CIN1 : in std_logic;\r
- CIN2 : in std_logic;\r
- CIN3 : in std_logic;\r
- CIN4 : in std_logic;\r
- CIN5 : in std_logic;\r
- CIN6 : in std_logic;\r
- CIN7 : in std_logic;\r
- CIN8 : in std_logic;\r
- CIN9 : in std_logic;\r
- CIN10 : in std_logic;\r
- CIN11 : in std_logic;\r
- CYAWSTN : in std_logic;\r
- FF_EBRD_CLK_0 : in std_logic;\r
- FF_EBRD_CLK_1 : in std_logic;\r
- FF_EBRD_CLK_2 : in std_logic;\r
- FF_EBRD_CLK_3 : in std_logic;\r
- FF_RXI_CLK_0 : in std_logic;\r
- FF_RXI_CLK_1 : in std_logic;\r
- FF_RXI_CLK_2 : in std_logic;\r
- FF_RXI_CLK_3 : in std_logic;\r
- FF_TX_D_0_0 : in std_logic;\r
- FF_TX_D_0_1 : in std_logic;\r
- FF_TX_D_0_2 : in std_logic;\r
- FF_TX_D_0_3 : in std_logic;\r
- FF_TX_D_0_4 : in std_logic;\r
- FF_TX_D_0_5 : in std_logic;\r
- FF_TX_D_0_6 : in std_logic;\r
- FF_TX_D_0_7 : in std_logic;\r
- FF_TX_D_0_8 : in std_logic;\r
- FF_TX_D_0_9 : in std_logic;\r
- FF_TX_D_0_10 : in std_logic;\r
- FF_TX_D_0_11 : in std_logic;\r
- FF_TX_D_0_12 : in std_logic;\r
- FF_TX_D_0_13 : in std_logic;\r
- FF_TX_D_0_14 : in std_logic;\r
- FF_TX_D_0_15 : in std_logic;\r
- FF_TX_D_0_16 : in std_logic;\r
- FF_TX_D_0_17 : in std_logic;\r
- FF_TX_D_0_18 : in std_logic;\r
- FF_TX_D_0_19 : in std_logic;\r
- FF_TX_D_0_20 : in std_logic;\r
- FF_TX_D_0_21 : in std_logic;\r
- FF_TX_D_0_22 : in std_logic;\r
- FF_TX_D_0_23 : in std_logic;\r
- FF_TX_D_1_0 : in std_logic;\r
- FF_TX_D_1_1 : in std_logic;\r
- FF_TX_D_1_2 : in std_logic;\r
- FF_TX_D_1_3 : in std_logic;\r
- FF_TX_D_1_4 : in std_logic;\r
- FF_TX_D_1_5 : in std_logic;\r
- FF_TX_D_1_6 : in std_logic;\r
- FF_TX_D_1_7 : in std_logic;\r
- FF_TX_D_1_8 : in std_logic;\r
- FF_TX_D_1_9 : in std_logic;\r
- FF_TX_D_1_10 : in std_logic;\r
- FF_TX_D_1_11 : in std_logic;\r
- FF_TX_D_1_12 : in std_logic;\r
- FF_TX_D_1_13 : in std_logic;\r
- FF_TX_D_1_14 : in std_logic;\r
- FF_TX_D_1_15 : in std_logic;\r
- FF_TX_D_1_16 : in std_logic;\r
- FF_TX_D_1_17 : in std_logic;\r
- FF_TX_D_1_18 : in std_logic;\r
- FF_TX_D_1_19 : in std_logic;\r
- FF_TX_D_1_20 : in std_logic;\r
- FF_TX_D_1_21 : in std_logic;\r
- FF_TX_D_1_22 : in std_logic;\r
- FF_TX_D_1_23 : in std_logic;\r
- FF_TX_D_2_0 : in std_logic;\r
- FF_TX_D_2_1 : in std_logic;\r
- FF_TX_D_2_2 : in std_logic;\r
- FF_TX_D_2_3 : in std_logic;\r
- FF_TX_D_2_4 : in std_logic;\r
- FF_TX_D_2_5 : in std_logic;\r
- FF_TX_D_2_6 : in std_logic;\r
- FF_TX_D_2_7 : in std_logic;\r
- FF_TX_D_2_8 : in std_logic;\r
- FF_TX_D_2_9 : in std_logic;\r
- FF_TX_D_2_10 : in std_logic;\r
- FF_TX_D_2_11 : in std_logic;\r
- FF_TX_D_2_12 : in std_logic;\r
- FF_TX_D_2_13 : in std_logic;\r
- FF_TX_D_2_14 : in std_logic;\r
- FF_TX_D_2_15 : in std_logic;\r
- FF_TX_D_2_16 : in std_logic;\r
- FF_TX_D_2_17 : in std_logic;\r
- FF_TX_D_2_18 : in std_logic;\r
- FF_TX_D_2_19 : in std_logic;\r
- FF_TX_D_2_20 : in std_logic;\r
- FF_TX_D_2_21 : in std_logic;\r
- FF_TX_D_2_22 : in std_logic;\r
- FF_TX_D_2_23 : in std_logic;\r
- FF_TX_D_3_0 : in std_logic;\r
- FF_TX_D_3_1 : in std_logic;\r
- FF_TX_D_3_2 : in std_logic;\r
- FF_TX_D_3_3 : in std_logic;\r
- FF_TX_D_3_4 : in std_logic;\r
- FF_TX_D_3_5 : in std_logic;\r
- FF_TX_D_3_6 : in std_logic;\r
- FF_TX_D_3_7 : in std_logic;\r
- FF_TX_D_3_8 : in std_logic;\r
- FF_TX_D_3_9 : in std_logic;\r
- FF_TX_D_3_10 : in std_logic;\r
- FF_TX_D_3_11 : in std_logic;\r
- FF_TX_D_3_12 : in std_logic;\r
- FF_TX_D_3_13 : in std_logic;\r
- FF_TX_D_3_14 : in std_logic;\r
- FF_TX_D_3_15 : in std_logic;\r
- FF_TX_D_3_16 : in std_logic;\r
- FF_TX_D_3_17 : in std_logic;\r
- FF_TX_D_3_18 : in std_logic;\r
- FF_TX_D_3_19 : in std_logic;\r
- FF_TX_D_3_20 : in std_logic;\r
- FF_TX_D_3_21 : in std_logic;\r
- FF_TX_D_3_22 : in std_logic;\r
- FF_TX_D_3_23 : in std_logic;\r
- FF_TXI_CLK_0 : in std_logic;\r
- FF_TXI_CLK_1 : in std_logic;\r
- FF_TXI_CLK_2 : in std_logic;\r
- FF_TXI_CLK_3 : in std_logic;\r
- FFC_CK_CORE_RX : in std_logic;\r
- FFC_CK_CORE_TX : in std_logic;\r
- FFC_EI_EN_0 : in std_logic;\r
- FFC_EI_EN_1 : in std_logic;\r
- FFC_EI_EN_2 : in std_logic;\r
- FFC_EI_EN_3 : in std_logic;\r
- FFC_ENABLE_CGALIGN_0 : in std_logic;\r
- FFC_ENABLE_CGALIGN_1 : in std_logic;\r
- FFC_ENABLE_CGALIGN_2 : in std_logic;\r
- FFC_ENABLE_CGALIGN_3 : in std_logic;\r
- FFC_FB_LOOPBACK_0 : in std_logic;\r
- FFC_FB_LOOPBACK_1 : in std_logic;\r
- FFC_FB_LOOPBACK_2 : in std_logic;\r
- FFC_FB_LOOPBACK_3 : in std_logic;\r
- FFC_LANE_RX_RST_0 : in std_logic;\r
- FFC_LANE_RX_RST_1 : in std_logic;\r
- FFC_LANE_RX_RST_2 : in std_logic;\r
- FFC_LANE_RX_RST_3 : in std_logic;\r
- FFC_LANE_TX_RST_0 : in std_logic;\r
- FFC_LANE_TX_RST_1 : in std_logic;\r
- FFC_LANE_TX_RST_2 : in std_logic;\r
- FFC_LANE_TX_RST_3 : in std_logic;\r
- FFC_MACRO_RST : in std_logic;\r
- FFC_PCI_DET_EN_0 : in std_logic;\r
- FFC_PCI_DET_EN_1 : in std_logic;\r
- FFC_PCI_DET_EN_2 : in std_logic;\r
- FFC_PCI_DET_EN_3 : in std_logic;\r
- FFC_PCIE_CT_0 : in std_logic;\r
- FFC_PCIE_CT_1 : in std_logic;\r
- FFC_PCIE_CT_2 : in std_logic;\r
- FFC_PCIE_CT_3 : in std_logic;\r
- FFC_PFIFO_CLR_0 : in std_logic;\r
- FFC_PFIFO_CLR_1 : in std_logic;\r
- FFC_PFIFO_CLR_2 : in std_logic;\r
- FFC_PFIFO_CLR_3 : in std_logic;\r
- FFC_QUAD_RST : in std_logic;\r
- FFC_RRST_0 : in std_logic;\r
- FFC_RRST_1 : in std_logic;\r
- FFC_RRST_2 : in std_logic;\r
- FFC_RRST_3 : in std_logic;\r
- FFC_RXPWDNB_0 : in std_logic;\r
- FFC_RXPWDNB_1 : in std_logic;\r
- FFC_RXPWDNB_2 : in std_logic;\r
- FFC_RXPWDNB_3 : in std_logic;\r
- FFC_SB_INV_RX_0 : in std_logic;\r
- FFC_SB_INV_RX_1 : in std_logic;\r
- FFC_SB_INV_RX_2 : in std_logic;\r
- FFC_SB_INV_RX_3 : in std_logic;\r
- FFC_SB_PFIFO_LP_0 : in std_logic;\r
- FFC_SB_PFIFO_LP_1 : in std_logic;\r
- FFC_SB_PFIFO_LP_2 : in std_logic;\r
- FFC_SB_PFIFO_LP_3 : in std_logic;\r
- FFC_SIGNAL_DETECT_0 : in std_logic;\r
- FFC_SIGNAL_DETECT_1 : in std_logic;\r
- FFC_SIGNAL_DETECT_2 : in std_logic;\r
- FFC_SIGNAL_DETECT_3 : in std_logic;\r
- FFC_TRST : in std_logic;\r
- FFC_TXPWDNB_0 : in std_logic;\r
- FFC_TXPWDNB_1 : in std_logic;\r
- FFC_TXPWDNB_2 : in std_logic;\r
- FFC_TXPWDNB_3 : in std_logic;\r
- SCIADDR0 : in std_logic;\r
- SCIADDR1 : in std_logic;\r
- SCIADDR2 : in std_logic;\r
- SCIADDR3 : in std_logic;\r
- SCIADDR4 : in std_logic;\r
- SCIADDR5 : in std_logic;\r
- SCIENAUX : in std_logic;\r
- SCIENCH0 : in std_logic;\r
- SCIENCH1 : in std_logic;\r
- SCIENCH2 : in std_logic;\r
- SCIENCH3 : in std_logic;\r
- SCIRD : in std_logic;\r
- SCISELAUX : in std_logic;\r
- SCISELCH0 : in std_logic;\r
- SCISELCH1 : in std_logic;\r
- SCISELCH2 : in std_logic;\r
- SCISELCH3 : in std_logic;\r
- SCIWDATA0 : in std_logic;\r
- SCIWDATA1 : in std_logic;\r
- SCIWDATA2 : in std_logic;\r
- SCIWDATA3 : in std_logic;\r
- SCIWDATA4 : in std_logic;\r
- SCIWDATA5 : in std_logic;\r
- SCIWDATA6 : in std_logic;\r
- SCIWDATA7 : in std_logic;\r
- SCIWSTN : in std_logic;\r
- HDOUTN0 : out std_logic;\r
- HDOUTN1 : out std_logic;\r
- HDOUTN2 : out std_logic;\r
- HDOUTN3 : out std_logic;\r
- HDOUTP0 : out std_logic;\r
- HDOUTP1 : out std_logic;\r
- HDOUTP2 : out std_logic;\r
- HDOUTP3 : out std_logic;\r
- COUT0 : out std_logic;\r
- COUT1 : out std_logic;\r
- COUT2 : out std_logic;\r
- COUT3 : out std_logic;\r
- COUT4 : out std_logic;\r
- COUT5 : out std_logic;\r
- COUT6 : out std_logic;\r
- COUT7 : out std_logic;\r
- COUT8 : out std_logic;\r
- COUT9 : out std_logic;\r
- COUT10 : out std_logic;\r
- COUT11 : out std_logic;\r
- COUT12 : out std_logic;\r
- COUT13 : out std_logic;\r
- COUT14 : out std_logic;\r
- COUT15 : out std_logic;\r
- COUT16 : out std_logic;\r
- COUT17 : out std_logic;\r
- COUT18 : out std_logic;\r
- COUT19 : out std_logic;\r
- FF_RX_D_0_0 : out std_logic;\r
- FF_RX_D_0_1 : out std_logic;\r
- FF_RX_D_0_2 : out std_logic;\r
- FF_RX_D_0_3 : out std_logic;\r
- FF_RX_D_0_4 : out std_logic;\r
- FF_RX_D_0_5 : out std_logic;\r
- FF_RX_D_0_6 : out std_logic;\r
- FF_RX_D_0_7 : out std_logic;\r
- FF_RX_D_0_8 : out std_logic;\r
- FF_RX_D_0_9 : out std_logic;\r
- FF_RX_D_0_10 : out std_logic;\r
- FF_RX_D_0_11 : out std_logic;\r
- FF_RX_D_0_12 : out std_logic;\r
- FF_RX_D_0_13 : out std_logic;\r
- FF_RX_D_0_14 : out std_logic;\r
- FF_RX_D_0_15 : out std_logic;\r
- FF_RX_D_0_16 : out std_logic;\r
- FF_RX_D_0_17 : out std_logic;\r
- FF_RX_D_0_18 : out std_logic;\r
- FF_RX_D_0_19 : out std_logic;\r
- FF_RX_D_0_20 : out std_logic;\r
- FF_RX_D_0_21 : out std_logic;\r
- FF_RX_D_0_22 : out std_logic;\r
- FF_RX_D_0_23 : out std_logic;\r
- FF_RX_D_1_0 : out std_logic;\r
- FF_RX_D_1_1 : out std_logic;\r
- FF_RX_D_1_2 : out std_logic;\r
- FF_RX_D_1_3 : out std_logic;\r
- FF_RX_D_1_4 : out std_logic;\r
- FF_RX_D_1_5 : out std_logic;\r
- FF_RX_D_1_6 : out std_logic;\r
- FF_RX_D_1_7 : out std_logic;\r
- FF_RX_D_1_8 : out std_logic;\r
- FF_RX_D_1_9 : out std_logic;\r
- FF_RX_D_1_10 : out std_logic;\r
- FF_RX_D_1_11 : out std_logic;\r
- FF_RX_D_1_12 : out std_logic;\r
- FF_RX_D_1_13 : out std_logic;\r
- FF_RX_D_1_14 : out std_logic;\r
- FF_RX_D_1_15 : out std_logic;\r
- FF_RX_D_1_16 : out std_logic;\r
- FF_RX_D_1_17 : out std_logic;\r
- FF_RX_D_1_18 : out std_logic;\r
- FF_RX_D_1_19 : out std_logic;\r
- FF_RX_D_1_20 : out std_logic;\r
- FF_RX_D_1_21 : out std_logic;\r
- FF_RX_D_1_22 : out std_logic;\r
- FF_RX_D_1_23 : out std_logic;\r
- FF_RX_D_2_0 : out std_logic;\r
- FF_RX_D_2_1 : out std_logic;\r
- FF_RX_D_2_2 : out std_logic;\r
- FF_RX_D_2_3 : out std_logic;\r
- FF_RX_D_2_4 : out std_logic;\r
- FF_RX_D_2_5 : out std_logic;\r
- FF_RX_D_2_6 : out std_logic;\r
- FF_RX_D_2_7 : out std_logic;\r
- FF_RX_D_2_8 : out std_logic;\r
- FF_RX_D_2_9 : out std_logic;\r
- FF_RX_D_2_10 : out std_logic;\r
- FF_RX_D_2_11 : out std_logic;\r
- FF_RX_D_2_12 : out std_logic;\r
- FF_RX_D_2_13 : out std_logic;\r
- FF_RX_D_2_14 : out std_logic;\r
- FF_RX_D_2_15 : out std_logic;\r
- FF_RX_D_2_16 : out std_logic;\r
- FF_RX_D_2_17 : out std_logic;\r
- FF_RX_D_2_18 : out std_logic;\r
- FF_RX_D_2_19 : out std_logic;\r
- FF_RX_D_2_20 : out std_logic;\r
- FF_RX_D_2_21 : out std_logic;\r
- FF_RX_D_2_22 : out std_logic;\r
- FF_RX_D_2_23 : out std_logic;\r
- FF_RX_D_3_0 : out std_logic;\r
- FF_RX_D_3_1 : out std_logic;\r
- FF_RX_D_3_2 : out std_logic;\r
- FF_RX_D_3_3 : out std_logic;\r
- FF_RX_D_3_4 : out std_logic;\r
- FF_RX_D_3_5 : out std_logic;\r
- FF_RX_D_3_6 : out std_logic;\r
- FF_RX_D_3_7 : out std_logic;\r
- FF_RX_D_3_8 : out std_logic;\r
- FF_RX_D_3_9 : out std_logic;\r
- FF_RX_D_3_10 : out std_logic;\r
- FF_RX_D_3_11 : out std_logic;\r
- FF_RX_D_3_12 : out std_logic;\r
- FF_RX_D_3_13 : out std_logic;\r
- FF_RX_D_3_14 : out std_logic;\r
- FF_RX_D_3_15 : out std_logic;\r
- FF_RX_D_3_16 : out std_logic;\r
- FF_RX_D_3_17 : out std_logic;\r
- FF_RX_D_3_18 : out std_logic;\r
- FF_RX_D_3_19 : out std_logic;\r
- FF_RX_D_3_20 : out std_logic;\r
- FF_RX_D_3_21 : out std_logic;\r
- FF_RX_D_3_22 : out std_logic;\r
- FF_RX_D_3_23 : out std_logic;\r
- FF_RX_F_CLK_0 : out std_logic;\r
- FF_RX_F_CLK_1 : out std_logic;\r
- FF_RX_F_CLK_2 : out std_logic;\r
- FF_RX_F_CLK_3 : out std_logic;\r
- FF_RX_H_CLK_0 : out std_logic;\r
- FF_RX_H_CLK_1 : out std_logic;\r
- FF_RX_H_CLK_2 : out std_logic;\r
- FF_RX_H_CLK_3 : out std_logic;\r
- FF_RX_Q_CLK_0 : out std_logic;\r
- FF_RX_Q_CLK_1 : out std_logic;\r
- FF_RX_Q_CLK_2 : out std_logic;\r
- FF_RX_Q_CLK_3 : out std_logic;\r
- FF_TX_F_CLK : out std_logic;\r
- FF_TX_H_CLK : out std_logic;\r
- FF_TX_Q_CLK : out std_logic;\r
- FFS_CC_OVERRUN_0 : out std_logic;\r
- FFS_CC_OVERRUN_1 : out std_logic;\r
- FFS_CC_OVERRUN_2 : out std_logic;\r
- FFS_CC_OVERRUN_3 : out std_logic;\r
- FFS_CC_UNDERRUN_0 : out std_logic;\r
- FFS_CC_UNDERRUN_1 : out std_logic;\r
- FFS_CC_UNDERRUN_2 : out std_logic;\r
- FFS_CC_UNDERRUN_3 : out std_logic;\r
- FFS_LS_SYNC_STATUS_0 : out std_logic;\r
- FFS_LS_SYNC_STATUS_1 : out std_logic;\r
- FFS_LS_SYNC_STATUS_2 : out std_logic;\r
- FFS_LS_SYNC_STATUS_3 : out std_logic;\r
- FFS_PCIE_CON_0 : out std_logic;\r
- FFS_PCIE_CON_1 : out std_logic;\r
- FFS_PCIE_CON_2 : out std_logic;\r
- FFS_PCIE_CON_3 : out std_logic;\r
- FFS_PCIE_DONE_0 : out std_logic;\r
- FFS_PCIE_DONE_1 : out std_logic;\r
- FFS_PCIE_DONE_2 : out std_logic;\r
- FFS_PCIE_DONE_3 : out std_logic;\r
- FFS_RLOS_LO_0 : out std_logic;\r
- FFS_RLOS_LO_1 : out std_logic;\r
- FFS_RLOS_LO_2 : out std_logic;\r
- FFS_RLOS_LO_3 : out std_logic;\r
- OOB_OUT_0 : out std_logic;\r
- OOB_OUT_1 : out std_logic;\r
- OOB_OUT_2 : out std_logic;\r
- OOB_OUT_3 : out std_logic;\r
- REFCK2CORE : out std_logic;\r
- SCIINT : out std_logic;\r
- SCIRDATA0 : out std_logic;\r
- SCIRDATA1 : out std_logic;\r
- SCIRDATA2 : out std_logic;\r
- SCIRDATA3 : out std_logic;\r
- SCIRDATA4 : out std_logic;\r
- SCIRDATA5 : out std_logic;\r
- SCIRDATA6 : out std_logic;\r
- SCIRDATA7 : out std_logic;\r
- FFS_PLOL : out std_logic;\r
- FFS_RLOL_0 : out std_logic;\r
- FFS_RLOL_1 : out std_logic;\r
- FFS_RLOL_2 : out std_logic;\r
- FFS_RLOL_3 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_3 : out std_logic\r
-);\r
-end component;\r
- attribute IS_ASB: string;\r
- attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";\r
- attribute CONFIG_FILE: string;\r
- attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;\r
- attribute black_box_pad_pin: string;\r
- attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";\r
-\r
-signal fpsc_vlo : std_logic := '0';\r
-signal cin : std_logic_vector (11 downto 0) := "000000000000";\r
-signal cout : std_logic_vector (19 downto 0);\r
-\r
-begin\r
-\r
-vlo_inst : VLO port map(Z => fpsc_vlo);\r
-\r
--- pcs_quad instance\r
-PCSC_INST : PCSC\r
---synopsys translate_off\r
- generic map (CONFIG_FILE => USER_CONFIG_FILE)\r
---synopsys translate_on\r
-port map (\r
- FFC_CK_CORE_TX => fpsc_vlo,\r
- FFC_CK_CORE_RX => fpsc_vlo,\r
- REFCLKP => refclkp,\r
- REFCLKN => refclkn,\r
- HDINP0 => hdinp0,\r
- HDINN0 => hdinn0,\r
- HDOUTP0 => hdoutp0,\r
- HDOUTN0 => hdoutn0,\r
- SCISELCH0 => fpsc_vlo,\r
- SCIENCH0 => fpsc_vlo,\r
- FF_RXI_CLK_0 => ff_rxiclk_ch0,\r
- FF_TXI_CLK_0 => ff_txiclk_ch0,\r
- FF_EBRD_CLK_0 => ff_ebrd_clk_0,\r
- FF_RX_F_CLK_0 => ff_rxfullclk_ch0,\r
- FF_RX_H_CLK_0 => open,\r
- FF_RX_Q_CLK_0 => open,\r
- FF_TX_D_0_0 => ff_txdata_ch0(0),\r
- FF_TX_D_0_1 => ff_txdata_ch0(1),\r
- FF_TX_D_0_2 => ff_txdata_ch0(2),\r
- FF_TX_D_0_3 => ff_txdata_ch0(3),\r
- FF_TX_D_0_4 => ff_txdata_ch0(4),\r
- FF_TX_D_0_5 => ff_txdata_ch0(5),\r
- FF_TX_D_0_6 => ff_txdata_ch0(6),\r
- FF_TX_D_0_7 => ff_txdata_ch0(7),\r
- FF_TX_D_0_8 => ff_tx_k_cntrl_ch0,\r
- FF_TX_D_0_9 => fpsc_vlo,\r
- FF_TX_D_0_10 => ff_xmit_ch0,\r
- FF_TX_D_0_11 => ff_correct_disp_ch0,\r
- FF_TX_D_0_12 => fpsc_vlo,\r
- FF_TX_D_0_13 => fpsc_vlo,\r
- FF_TX_D_0_14 => fpsc_vlo,\r
- FF_TX_D_0_15 => fpsc_vlo,\r
- FF_TX_D_0_16 => fpsc_vlo,\r
- FF_TX_D_0_17 => fpsc_vlo,\r
- FF_TX_D_0_18 => fpsc_vlo,\r
- FF_TX_D_0_19 => fpsc_vlo,\r
- FF_TX_D_0_20 => fpsc_vlo,\r
- FF_TX_D_0_21 => fpsc_vlo,\r
- FF_TX_D_0_22 => fpsc_vlo,\r
- FF_TX_D_0_23 => fpsc_vlo,\r
- FF_RX_D_0_0 => ff_rxdata_ch0(0),\r
- FF_RX_D_0_1 => ff_rxdata_ch0(1),\r
- FF_RX_D_0_2 => ff_rxdata_ch0(2),\r
- FF_RX_D_0_3 => ff_rxdata_ch0(3),\r
- FF_RX_D_0_4 => ff_rxdata_ch0(4),\r
- FF_RX_D_0_5 => ff_rxdata_ch0(5),\r
- FF_RX_D_0_6 => ff_rxdata_ch0(6),\r
- FF_RX_D_0_7 => ff_rxdata_ch0(7),\r
- FF_RX_D_0_8 => ff_rx_k_cntrl_ch0,\r
- FF_RX_D_0_9 => ff_disp_err_ch0,\r
- FF_RX_D_0_10 => ff_cv_ch0,\r
- FF_RX_D_0_11 => ff_rx_even_ch0,\r
- FF_RX_D_0_12 => open,\r
- FF_RX_D_0_13 => open,\r
- FF_RX_D_0_14 => open,\r
- FF_RX_D_0_15 => open,\r
- FF_RX_D_0_16 => open,\r
- FF_RX_D_0_17 => open,\r
- FF_RX_D_0_18 => open,\r
- FF_RX_D_0_19 => open,\r
- FF_RX_D_0_20 => open,\r
- FF_RX_D_0_21 => open,\r
- FF_RX_D_0_22 => open,\r
- FF_RX_D_0_23 => open,\r
- FFC_RRST_0 => ffc_rrst_ch0,\r
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,\r
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,\r
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,\r
- FFC_PFIFO_CLR_0 => fpsc_vlo,\r
- FFC_FB_LOOPBACK_0 => fpsc_vlo,\r
- FFC_SB_INV_RX_0 => fpsc_vlo,\r
- FFC_PCIE_CT_0 => fpsc_vlo,\r
- FFC_PCI_DET_EN_0 => fpsc_vlo,\r
- FFS_PCIE_DONE_0 => open,\r
- FFS_PCIE_CON_0 => open,\r
- FFC_EI_EN_0 => fpsc_vlo,\r
- FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0,\r
- FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0,\r
- FFC_TXPWDNB_0 => ffc_txpwdnb_ch0,\r
- FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0,\r
- FFS_RLOS_LO_0 => ffs_rlos_lo_ch0,\r
- FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0,\r
- FFS_CC_UNDERRUN_0 => open,\r
- FFS_CC_OVERRUN_0 => open,\r
- FFS_RXFBFIFO_ERROR_0 => open,\r
- FFS_TXFBFIFO_ERROR_0 => open,\r
- FFS_RLOL_0 => ffs_rlol_ch0,\r
- OOB_OUT_0 => oob_out_ch0,\r
- HDINP1 => fpsc_vlo,\r
- HDINN1 => fpsc_vlo,\r
- HDOUTP1 => open,\r
- HDOUTN1 => open,\r
- SCISELCH1 => fpsc_vlo,\r
- SCIENCH1 => fpsc_vlo,\r
- FF_RXI_CLK_1 => fpsc_vlo,\r
- FF_TXI_CLK_1 => fpsc_vlo,\r
- FF_EBRD_CLK_1 => fpsc_vlo,\r
- FF_RX_F_CLK_1 => open,\r
- FF_RX_H_CLK_1 => open,\r
- FF_RX_Q_CLK_1 => open,\r
- FF_TX_D_1_0 => fpsc_vlo,\r
- FF_TX_D_1_1 => fpsc_vlo,\r
- FF_TX_D_1_2 => fpsc_vlo,\r
- FF_TX_D_1_3 => fpsc_vlo,\r
- FF_TX_D_1_4 => fpsc_vlo,\r
- FF_TX_D_1_5 => fpsc_vlo,\r
- FF_TX_D_1_6 => fpsc_vlo,\r
- FF_TX_D_1_7 => fpsc_vlo,\r
- FF_TX_D_1_8 => fpsc_vlo,\r
- FF_TX_D_1_9 => fpsc_vlo,\r
- FF_TX_D_1_10 => fpsc_vlo,\r
- FF_TX_D_1_11 => fpsc_vlo,\r
- FF_TX_D_1_12 => fpsc_vlo,\r
- FF_TX_D_1_13 => fpsc_vlo,\r
- FF_TX_D_1_14 => fpsc_vlo,\r
- FF_TX_D_1_15 => fpsc_vlo,\r
- FF_TX_D_1_16 => fpsc_vlo,\r
- FF_TX_D_1_17 => fpsc_vlo,\r
- FF_TX_D_1_18 => fpsc_vlo,\r
- FF_TX_D_1_19 => fpsc_vlo,\r
- FF_TX_D_1_20 => fpsc_vlo,\r
- FF_TX_D_1_21 => fpsc_vlo,\r
- FF_TX_D_1_22 => fpsc_vlo,\r
- FF_TX_D_1_23 => fpsc_vlo,\r
- FF_RX_D_1_0 => open,\r
- FF_RX_D_1_1 => open,\r
- FF_RX_D_1_2 => open,\r
- FF_RX_D_1_3 => open,\r
- FF_RX_D_1_4 => open,\r
- FF_RX_D_1_5 => open,\r
- FF_RX_D_1_6 => open,\r
- FF_RX_D_1_7 => open,\r
- FF_RX_D_1_8 => open,\r
- FF_RX_D_1_9 => open,\r
- FF_RX_D_1_10 => open,\r
- FF_RX_D_1_11 => open,\r
- FF_RX_D_1_12 => open,\r
- FF_RX_D_1_13 => open,\r
- FF_RX_D_1_14 => open,\r
- FF_RX_D_1_15 => open,\r
- FF_RX_D_1_16 => open,\r
- FF_RX_D_1_17 => open,\r
- FF_RX_D_1_18 => open,\r
- FF_RX_D_1_19 => open,\r
- FF_RX_D_1_20 => open,\r
- FF_RX_D_1_21 => open,\r
- FF_RX_D_1_22 => open,\r
- FF_RX_D_1_23 => open,\r
- FFC_RRST_1 => fpsc_vlo,\r
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,\r
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,\r
- FFC_SB_INV_RX_1 => fpsc_vlo,\r
- FFC_PFIFO_CLR_1 => fpsc_vlo,\r
- FFC_PCIE_CT_1 => fpsc_vlo,\r
- FFC_PCI_DET_EN_1 => fpsc_vlo,\r
- FFC_FB_LOOPBACK_1 => fpsc_vlo,\r
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,\r
- FFC_EI_EN_1 => fpsc_vlo,\r
- FFC_LANE_TX_RST_1 => fpsc_vlo,\r
- FFC_LANE_RX_RST_1 => fpsc_vlo,\r
- FFC_TXPWDNB_1 => fpsc_vlo,\r
- FFC_RXPWDNB_1 => fpsc_vlo,\r
- FFS_RLOS_LO_1 => open,\r
- FFS_PCIE_DONE_1 => open,\r
- FFS_PCIE_CON_1 => open,\r
- FFS_LS_SYNC_STATUS_1 => open,\r
- FFS_CC_UNDERRUN_1 => open,\r
- FFS_CC_OVERRUN_1 => open,\r
- FFS_RLOL_1 => open,\r
- FFS_RXFBFIFO_ERROR_1 => open,\r
- FFS_TXFBFIFO_ERROR_1 => open,\r
- OOB_OUT_1 => open,\r
- HDINP2 => fpsc_vlo,\r
- HDINN2 => fpsc_vlo,\r
- HDOUTP2 => open,\r
- HDOUTN2 => open,\r
- SCISELCH2 => fpsc_vlo,\r
- SCIENCH2 => fpsc_vlo,\r
- FF_RXI_CLK_2 => fpsc_vlo,\r
- FF_TXI_CLK_2 => fpsc_vlo,\r
- FF_EBRD_CLK_2 => fpsc_vlo,\r
- FF_RX_F_CLK_2 => open,\r
- FF_RX_H_CLK_2 => open,\r
- FF_RX_Q_CLK_2 => open,\r
- FF_TX_D_2_0 => fpsc_vlo,\r
- FF_TX_D_2_1 => fpsc_vlo,\r
- FF_TX_D_2_2 => fpsc_vlo,\r
- FF_TX_D_2_3 => fpsc_vlo,\r
- FF_TX_D_2_4 => fpsc_vlo,\r
- FF_TX_D_2_5 => fpsc_vlo,\r
- FF_TX_D_2_6 => fpsc_vlo,\r
- FF_TX_D_2_7 => fpsc_vlo,\r
- FF_TX_D_2_8 => fpsc_vlo,\r
- FF_TX_D_2_9 => fpsc_vlo,\r
- FF_TX_D_2_10 => fpsc_vlo,\r
- FF_TX_D_2_11 => fpsc_vlo,\r
- FF_TX_D_2_12 => fpsc_vlo,\r
- FF_TX_D_2_13 => fpsc_vlo,\r
- FF_TX_D_2_14 => fpsc_vlo,\r
- FF_TX_D_2_15 => fpsc_vlo,\r
- FF_TX_D_2_16 => fpsc_vlo,\r
- FF_TX_D_2_17 => fpsc_vlo,\r
- FF_TX_D_2_18 => fpsc_vlo,\r
- FF_TX_D_2_19 => fpsc_vlo,\r
- FF_TX_D_2_20 => fpsc_vlo,\r
- FF_TX_D_2_21 => fpsc_vlo,\r
- FF_TX_D_2_22 => fpsc_vlo,\r
- FF_TX_D_2_23 => fpsc_vlo,\r
- FF_RX_D_2_0 => open,\r
- FF_RX_D_2_1 => open,\r
- FF_RX_D_2_2 => open,\r
- FF_RX_D_2_3 => open,\r
- FF_RX_D_2_4 => open,\r
- FF_RX_D_2_5 => open,\r
- FF_RX_D_2_6 => open,\r
- FF_RX_D_2_7 => open,\r
- FF_RX_D_2_8 => open,\r
- FF_RX_D_2_9 => open,\r
- FF_RX_D_2_10 => open,\r
- FF_RX_D_2_11 => open,\r
- FF_RX_D_2_12 => open,\r
- FF_RX_D_2_13 => open,\r
- FF_RX_D_2_14 => open,\r
- FF_RX_D_2_15 => open,\r
- FF_RX_D_2_16 => open,\r
- FF_RX_D_2_17 => open,\r
- FF_RX_D_2_18 => open,\r
- FF_RX_D_2_19 => open,\r
- FF_RX_D_2_20 => open,\r
- FF_RX_D_2_21 => open,\r
- FF_RX_D_2_22 => open,\r
- FF_RX_D_2_23 => open,\r
- FFC_RRST_2 => fpsc_vlo,\r
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,\r
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,\r
- FFC_SB_INV_RX_2 => fpsc_vlo,\r
- FFC_PFIFO_CLR_2 => fpsc_vlo,\r
- FFC_PCIE_CT_2 => fpsc_vlo,\r
- FFC_PCI_DET_EN_2 => fpsc_vlo,\r
- FFC_FB_LOOPBACK_2 => fpsc_vlo,\r
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,\r
- FFC_EI_EN_2 => fpsc_vlo,\r
- FFC_LANE_TX_RST_2 => fpsc_vlo,\r
- FFC_LANE_RX_RST_2 => fpsc_vlo,\r
- FFC_TXPWDNB_2 => fpsc_vlo,\r
- FFC_RXPWDNB_2 => fpsc_vlo,\r
- FFS_RLOS_LO_2 => open,\r
- FFS_PCIE_DONE_2 => open,\r
- FFS_PCIE_CON_2 => open,\r
- FFS_LS_SYNC_STATUS_2 => open,\r
- FFS_CC_UNDERRUN_2 => open,\r
- FFS_CC_OVERRUN_2 => open,\r
- FFS_RLOL_2 => open,\r
- FFS_RXFBFIFO_ERROR_2 => open,\r
- FFS_TXFBFIFO_ERROR_2 => open,\r
- OOB_OUT_2 => open,\r
- HDINP3 => fpsc_vlo,\r
- HDINN3 => fpsc_vlo,\r
- HDOUTP3 => open,\r
- HDOUTN3 => open,\r
- SCISELCH3 => fpsc_vlo,\r
- SCIENCH3 => fpsc_vlo,\r
- FF_RXI_CLK_3 => fpsc_vlo,\r
- FF_TXI_CLK_3 => fpsc_vlo,\r
- FF_EBRD_CLK_3 => fpsc_vlo,\r
- FF_RX_F_CLK_3 => open,\r
- FF_RX_H_CLK_3 => open,\r
- FF_RX_Q_CLK_3 => open,\r
- FF_TX_D_3_0 => fpsc_vlo,\r
- FF_TX_D_3_1 => fpsc_vlo,\r
- FF_TX_D_3_2 => fpsc_vlo,\r
- FF_TX_D_3_3 => fpsc_vlo,\r
- FF_TX_D_3_4 => fpsc_vlo,\r
- FF_TX_D_3_5 => fpsc_vlo,\r
- FF_TX_D_3_6 => fpsc_vlo,\r
- FF_TX_D_3_7 => fpsc_vlo,\r
- FF_TX_D_3_8 => fpsc_vlo,\r
- FF_TX_D_3_9 => fpsc_vlo,\r
- FF_TX_D_3_10 => fpsc_vlo,\r
- FF_TX_D_3_11 => fpsc_vlo,\r
- FF_TX_D_3_12 => fpsc_vlo,\r
- FF_TX_D_3_13 => fpsc_vlo,\r
- FF_TX_D_3_14 => fpsc_vlo,\r
- FF_TX_D_3_15 => fpsc_vlo,\r
- FF_TX_D_3_16 => fpsc_vlo,\r
- FF_TX_D_3_17 => fpsc_vlo,\r
- FF_TX_D_3_18 => fpsc_vlo,\r
- FF_TX_D_3_19 => fpsc_vlo,\r
- FF_TX_D_3_20 => fpsc_vlo,\r
- FF_TX_D_3_21 => fpsc_vlo,\r
- FF_TX_D_3_22 => fpsc_vlo,\r
- FF_TX_D_3_23 => fpsc_vlo,\r
- FF_RX_D_3_0 => open,\r
- FF_RX_D_3_1 => open,\r
- FF_RX_D_3_2 => open,\r
- FF_RX_D_3_3 => open,\r
- FF_RX_D_3_4 => open,\r
- FF_RX_D_3_5 => open,\r
- FF_RX_D_3_6 => open,\r
- FF_RX_D_3_7 => open,\r
- FF_RX_D_3_8 => open,\r
- FF_RX_D_3_9 => open,\r
- FF_RX_D_3_10 => open,\r
- FF_RX_D_3_11 => open,\r
- FF_RX_D_3_12 => open,\r
- FF_RX_D_3_13 => open,\r
- FF_RX_D_3_14 => open,\r
- FF_RX_D_3_15 => open,\r
- FF_RX_D_3_16 => open,\r
- FF_RX_D_3_17 => open,\r
- FF_RX_D_3_18 => open,\r
- FF_RX_D_3_19 => open,\r
- FF_RX_D_3_20 => open,\r
- FF_RX_D_3_21 => open,\r
- FF_RX_D_3_22 => open,\r
- FF_RX_D_3_23 => open,\r
- FFC_RRST_3 => fpsc_vlo,\r
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,\r
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,\r
- FFC_SB_INV_RX_3 => fpsc_vlo,\r
- FFC_PFIFO_CLR_3 => fpsc_vlo,\r
- FFC_PCIE_CT_3 => fpsc_vlo,\r
- FFC_PCI_DET_EN_3 => fpsc_vlo,\r
- FFC_FB_LOOPBACK_3 => fpsc_vlo,\r
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,\r
- FFC_EI_EN_3 => fpsc_vlo,\r
- FFC_LANE_TX_RST_3 => fpsc_vlo,\r
- FFC_LANE_RX_RST_3 => fpsc_vlo,\r
- FFC_TXPWDNB_3 => fpsc_vlo,\r
- FFC_RXPWDNB_3 => fpsc_vlo,\r
- FFS_RLOS_LO_3 => open,\r
- FFS_PCIE_DONE_3 => open,\r
- FFS_PCIE_CON_3 => open,\r
- FFS_LS_SYNC_STATUS_3 => open,\r
- FFS_CC_UNDERRUN_3 => open,\r
- FFS_CC_OVERRUN_3 => open,\r
- FFS_RLOL_3 => open,\r
- FFS_RXFBFIFO_ERROR_3 => open,\r
- FFS_TXFBFIFO_ERROR_3 => open,\r
- OOB_OUT_3 => open,\r
- SCIWDATA0 => fpsc_vlo,\r
- SCIWDATA1 => fpsc_vlo,\r
- SCIWDATA2 => fpsc_vlo,\r
- SCIWDATA3 => fpsc_vlo,\r
- SCIWDATA4 => fpsc_vlo,\r
- SCIWDATA5 => fpsc_vlo,\r
- SCIWDATA6 => fpsc_vlo,\r
- SCIWDATA7 => fpsc_vlo,\r
- SCIADDR0 => fpsc_vlo,\r
- SCIADDR1 => fpsc_vlo,\r
- SCIADDR2 => fpsc_vlo,\r
- SCIADDR3 => fpsc_vlo,\r
- SCIADDR4 => fpsc_vlo,\r
- SCIADDR5 => fpsc_vlo,\r
- SCIRDATA0 => open,\r
- SCIRDATA1 => open,\r
- SCIRDATA2 => open,\r
- SCIRDATA3 => open,\r
- SCIRDATA4 => open,\r
- SCIRDATA5 => open,\r
- SCIRDATA6 => open,\r
- SCIRDATA7 => open,\r
- SCIENAUX => fpsc_vlo,\r
- SCISELAUX => fpsc_vlo,\r
- SCIRD => fpsc_vlo,\r
- SCIWSTN => fpsc_vlo,\r
- CYAWSTN => fpsc_vlo,\r
- SCIINT => open,\r
- FFC_MACRO_RST => ffc_macro_rst,\r
- FFC_QUAD_RST => ffc_quad_rst,\r
- FFC_TRST => ffc_trst,\r
- FF_TX_F_CLK => ff_txfullclk,\r
- FF_TX_H_CLK => ff_txhalfclk,\r
- FF_TX_Q_CLK => open,\r
- REFCK2CORE => refck2core,\r
- CIN0 => cin(0),\r
- CIN1 => cin(1),\r
- CIN2 => cin(2),\r
- CIN3 => cin(3),\r
- CIN4 => cin(4),\r
- CIN5 => cin(5),\r
- CIN6 => cin(6),\r
- CIN7 => cin(7),\r
- CIN8 => cin(8),\r
- CIN9 => cin(9),\r
- CIN10 => cin(10),\r
- CIN11 => cin(11),\r
- COUT0 => cout(0),\r
- COUT1 => cout(1),\r
- COUT2 => cout(2),\r
- COUT3 => cout(3),\r
- COUT4 => cout(4),\r
- COUT5 => cout(5),\r
- COUT6 => cout(6),\r
- COUT7 => cout(7),\r
- COUT8 => cout(8),\r
- COUT9 => cout(9),\r
- COUT10 => cout(10),\r
- COUT11 => cout(11),\r
- COUT12 => cout(12),\r
- COUT13 => cout(13),\r
- COUT14 => cout(14),\r
- COUT15 => cout(15),\r
- COUT16 => cout(16),\r
- COUT17 => cout(17),\r
- COUT18 => cout(18),\r
- COUT19 => cout(19),\r
- FFS_PLOL => ffs_plol);\r
-\r
---synopsys translate_off\r
-file_read : PROCESS\r
-VARIABLE open_status : file_open_status;\r
-FILE config : text;\r
-BEGIN\r
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);\r
- IF (open_status = name_error) THEN\r
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"\r
- severity ERROR;\r
- END IF;\r
- wait;\r
-END PROCESS;\r
---synopsys translate_on\r
-\r
-end serdes_gbe_0_extclock_8b_arch ;\r
+++ /dev/null
-Starting process: \r
-\r
- Module Name: serdes_gbe_0_extclock_8b\r
- Core Name: PCS\r
- LPC file : serdes_gbe_0_extclock_8b.lpc\r
- Parameter File : serdes_gbe_0_extclock_8b.pp\r
- Command line: /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_extclock_8b.pp\r
- Return Value:\r
-\r
-\r
- Module PCS has been generated in /home/greg/NewHub2/hub2/ipexpress/serdes successfully!\r
-\r
-/home/greg/.isplever_lin1/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_extclock_8b -ext readme -out serdes_gbe_0_extclock_8b -tpl serdes_gbe_0_extclock_8b.tft serdes_gbe_0_extclock_8b.vhd\r
-\r
-Done successfully!\r
-File: serdes_gbe_0_extclock_8b.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_ch4" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 04 04 20:33:50.582" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_ch4.lpc" type="lpc" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.pp" type="pp" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.sym" type="sym" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.tft" type="tft" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.txt" type="pcs_module" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.vhd" type="top_level_vhdl" modified="2012 04 04 20:33:49.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE serdes_ch4 DEFIN serdes_ch4.vhd
- SUBMODULE PCSD
- INSTANCE PCSD_INST
- SUBMODULE VHI
- INSTANCE vhi_inst
- SUBMODULE VLO
- INSTANCE vlo_inst
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_ch4
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/04/2012
-Time=20:33:49
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=RXTX
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=GIGE
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=1.25
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=125.0
-_tx_protocol0=DISABLED
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=GIGE
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=125.0
-_tx_ficlk_rate1=125.0
-_tx_ficlk_rate2=125.0
-_tx_ficlk_rate3=125.0
-_pll_rxsrc0=EXTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2.5
-_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=1.25
-_rx_protocol0=DISABLED
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=GIGE
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=250.0
-_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=125.0
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
-_rx_ficlk_rate0=250.0
-_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=125.0
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=AC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=AC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P5
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111111
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=2
-_k00=00
-_k01=00
-_k02=00
-_k03=01
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=00
-_byten00=00000000
-_byten01=00000000
-_byten02=00000000
-_byten03=10111100
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=01010000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=10111100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=01010000
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=DISABLED
-_sci_int_port=DISABLED
-_refck2core=DISABLED
-Regen=auto
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_ch4.pp=pp
-serdes_ch4.tft=tft
-serdes_ch4.txt=pcs_module
-serdes_ch4.sym=sym
+++ /dev/null
-hdinp_ch3 i
-hdinn_ch3 i
-hdoutp_ch3 o
-hdoutn_ch3 o
-rxiclk_ch3 i
-txiclk_ch3 i
-rx_full_clk_ch3 o
-rx_half_clk_ch3 o
-tx_full_clk_ch3 o
-tx_half_clk_ch3 o
-fpga_rxrefclk_ch3 i
-txdata_ch3[7] i
-txdata_ch3[6] i
-txdata_ch3[5] i
-txdata_ch3[4] i
-txdata_ch3[3] i
-txdata_ch3[2] i
-txdata_ch3[1] i
-txdata_ch3[0] i
-tx_k_ch3 i
-xmit_ch3 i
-tx_disp_correct_ch3 i
-rxdata_ch3[7] o
-rxdata_ch3[6] o
-rxdata_ch3[5] o
-rxdata_ch3[4] o
-rxdata_ch3[3] o
-rxdata_ch3[2] o
-rxdata_ch3[1] o
-rxdata_ch3[0] o
-rx_k_ch3 o
-rx_disp_err_ch3 o
-rx_cv_err_ch3 o
-rx_serdes_rst_ch3_c i
-sb_felb_ch3_c i
-sb_felb_rst_ch3_c i
-tx_pcs_rst_ch3_c i
-tx_pwrup_ch3_c i
-rx_pcs_rst_ch3_c i
-rx_pwrup_ch3_c i
-rx_los_low_ch3_s o
-lsm_status_ch3_s o
-rx_cdr_lol_ch3_s o
-fpga_txrefclk i
-tx_serdes_rst_c i
-tx_pll_lol_qd_s o
-rst_qd_c i
-serdes_rst_qd_c i
+++ /dev/null
-#define _device_name "LFE3-150EA"
-#define _ch0_pll_rxsrc "REFCLK_EXT"
-#define _ch0_mode "DISABLED"
-#define _ch0_protocol "G8B10B"
-#define _ch0_ldr "DISABLED"
-#define _ch0_tx_data_rate "FULL"
-#define _ch0_tx_data_width "8"
-#define _ch0_tx_fifo "ENABLED"
-#define _ch0_tx_ficlk_rate 125.0
-#define _ch0_rx_datarange "MEDHIGH"
-#define _ch0_rx_data_rate "FULL"
-#define _ch0_rxrefclk_rate "250.0"
-#define _ch0_rx_data_width "8"
-#define _ch0_rx_fifo "ENABLED"
-#define _ch0_rx_ficlk_rate 250.0
-#define _ch0_tdrv "0"
-#define _ch0_tx_pre "DISABLED"
-#define _ch0_rterm_tx "50"
-#define _ch0_rx_eq "DISABLED"
-#define _ch0_rterm_rx "50"
-#define _ch0_rx_dcc "AC"
-#define _los_threshold_lo0 "2"
-#define _ch0_tx_sb "DISABLED"
-#define _ch0_tx_8b10b "ENABLED"
-#define _ch0_rx_sb "DISABLED"
-#define _ch0_ird "DISABLED"
-#define _ch0_rx_8b10b "ENABLED"
-#define _ch0_rxwa "ENABLED"
-#define _ch0_ilsm "ENABLED"
-#define _ch0_scomma "K28P157"
-#define _ch0_comma_a "1100000101"
-#define _ch0_comma_b "0011111010"
-#define _ch0_comma_m "1111111100"
-#define _ch0_ctc "DISABLED"
-#define _ch0_cc_match_mode "1"
-#define _ch0_byten "0000000000"
-#define _ch0_byten1 "0000000000"
-#define _ch0_byten2 "0100011100"
-#define _ch0_byten3 "0100011100"
-#define _ch0_cc_min_ipg "3"
-#define _ch0_lbtype "DISABLED"
-#define _ch0_teidle "DISABLED"
-#define _ch0_rx_lol_port "INTERNAL"
-
-#define _ch1_pll_rxsrc "REFCLK_EXT"
-#define _ch1_mode "DISABLED"
-#define _ch1_protocol "G8B10B"
-#define _ch1_ldr "DISABLED"
-#define _ch1_tx_data_rate "FULL"
-#define _ch1_tx_data_width "8"
-#define _ch1_tx_fifo "ENABLED"
-#define _ch1_tx_ficlk_rate 125.0
-#define _ch1_rx_datarange "MEDHIGH"
-#define _ch1_rx_data_rate "FULL"
-#define _ch1_rxrefclk_rate "250.0"
-#define _ch1_rx_data_width "8"
-#define _ch1_rx_fifo "ENABLED"
-#define _ch1_rx_ficlk_rate 250.0
-#define _ch1_tdrv "0"
-#define _ch1_tx_pre "DISABLED"
-#define _ch1_rterm_tx "50"
-#define _ch1_rx_eq "DISABLED"
-#define _ch1_rterm_rx "50"
-#define _ch1_rx_dcc "AC"
-#define _los_threshold_lo1 "2"
-#define _ch1_tx_sb "DISABLED"
-#define _ch1_tx_8b10b "ENABLED"
-#define _ch1_rx_sb "DISABLED"
-#define _ch1_ird "DISABLED"
-#define _ch1_rx_8b10b "ENABLED"
-#define _ch1_rxwa "ENABLED"
-#define _ch1_ilsm "ENABLED"
-#define _ch1_scomma "K28P157"
-#define _ch1_comma_a "1100000101"
-#define _ch1_comma_b "0011111010"
-#define _ch1_comma_m "1111111100"
-#define _ch1_ctc "DISABLED"
-#define _ch1_cc_match_mode "1"
-#define _ch1_byten "0000000000"
-#define _ch1_byten1 "0000000000"
-#define _ch1_byten2 "0100011100"
-#define _ch1_byten3 "0100011100"
-#define _ch1_cc_min_ipg "3"
-#define _ch1_lbtype "DISABLED"
-#define _ch1_teidle "DISABLED"
-#define _ch1_rx_lol_port "INTERNAL"
-
-#define _ch2_pll_rxsrc "REFCLK_EXT"
-#define _ch2_mode "DISABLED"
-#define _ch2_protocol "G8B10B"
-#define _ch2_ldr "DISABLED"
-#define _ch2_tx_data_rate "FULL"
-#define _ch2_tx_data_width "8"
-#define _ch2_tx_fifo "ENABLED"
-#define _ch2_tx_ficlk_rate 125.0
-#define _ch2_rx_datarange "MEDHIGH"
-#define _ch2_rx_data_rate "FULL"
-#define _ch2_rxrefclk_rate "250.0"
-#define _ch2_rx_data_width "8"
-#define _ch2_rx_fifo "ENABLED"
-#define _ch2_rx_ficlk_rate 250.0
-#define _ch2_tdrv "0"
-#define _ch2_tx_pre "DISABLED"
-#define _ch2_rterm_tx "50"
-#define _ch2_rx_eq "DISABLED"
-#define _ch2_rterm_rx "50"
-#define _ch2_rx_dcc "AC"
-#define _los_threshold_lo2 "2"
-#define _ch2_tx_sb "DISABLED"
-#define _ch2_tx_8b10b "ENABLED"
-#define _ch2_rx_sb "DISABLED"
-#define _ch2_ird "DISABLED"
-#define _ch2_rx_8b10b "ENABLED"
-#define _ch2_rxwa "ENABLED"
-#define _ch2_ilsm "ENABLED"
-#define _ch2_scomma "K28P157"
-#define _ch2_comma_a "1100000101"
-#define _ch2_comma_b "0011111010"
-#define _ch2_comma_m "1111111100"
-#define _ch2_ctc "DISABLED"
-#define _ch2_cc_match_mode "1"
-#define _ch2_byten "0000000000"
-#define _ch2_byten1 "0000000000"
-#define _ch2_byten2 "0100011100"
-#define _ch2_byten3 "0100011100"
-#define _ch2_cc_min_ipg "3"
-#define _ch2_lbtype "DISABLED"
-#define _ch2_teidle "DISABLED"
-#define _ch2_rx_lol_port "INTERNAL"
-
-#define _ch3_pll_rxsrc "REFCLK_CORE"
-#define _ch3_mode "RXTX"
-#define _ch3_protocol "GIGE"
-#define _ch3_ldr "DISABLED"
-#define _ch3_tx_data_rate "FULL"
-#define _ch3_tx_data_width "8"
-#define _ch3_tx_fifo "ENABLED"
-#define _ch3_tx_ficlk_rate 125.0
-#define _ch3_rx_datarange "MED"
-#define _ch3_rx_data_rate "FULL"
-#define _ch3_rxrefclk_rate "125.0"
-#define _ch3_rx_data_width "8"
-#define _ch3_rx_fifo "ENABLED"
-#define _ch3_rx_ficlk_rate 125.0
-#define _ch3_tdrv "0"
-#define _ch3_tx_pre "DISABLED"
-#define _ch3_rterm_tx "50"
-#define _ch3_rx_eq "DISABLED"
-#define _ch3_rterm_rx "50"
-#define _ch3_rx_dcc "AC"
-#define _los_threshold_lo3 "2"
-#define _ch3_tx_sb "DISABLED"
-#define _ch3_tx_8b10b "ENABLED"
-#define _ch3_rx_sb "DISABLED"
-#define _ch3_ird "DISABLED"
-#define _ch3_rx_8b10b "ENABLED"
-#define _ch3_rxwa "ENABLED"
-#define _ch3_ilsm "ENABLED"
-#define _ch3_scomma "K28P5"
-#define _ch3_comma_a "1100000101"
-#define _ch3_comma_b "0011111010"
-#define _ch3_comma_m "1111111111"
-#define _ch3_ctc "DISABLED"
-#define _ch3_cc_match_mode "2"
-#define _ch3_byten "0110111100"
-#define _ch3_byten1 "0001010000"
-#define _ch3_byten2 "0110111100"
-#define _ch3_byten3 "0001010000"
-#define _ch3_cc_min_ipg "3"
-#define _ch3_lbtype "DISABLED"
-#define _ch3_teidle "DISABLED"
-#define _ch3_rx_lol_port "INTERNAL"
-
-#define _datarange "MED"
-#define _pll_txsrc "REFCLK_CORE"
-#define _refclk_mult "10X"
-#define _refclk_rate 125.0
-#define _pll_term "50"
-#define _pll_dcc "AC"
-#define _pll_lol_set "0"
-#define _cchmark "9"
-#define _cclmark "7"
-#define _rst_gen "DISABLED"
-#define _sci_ports "DISABLED"
-#define _sci_int_port "DISABLED"
-#define _refck2core "DISABLED"
-#define _circuit_name serdes_ch4
-#define _lang vhdl
-
-#include <pcs/PCSD.vhd>
-#include <pcs/pcsd_cfg.txt>
+++ /dev/null
-
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: Lattice Semiconductor Corporation
- MODULE: serdes_ch4
- DESIGN: serdes_ch4
- FILENAME: serdes_ch4.readme
- PROJECT: Unknown
- VERSION: 2.0
- This file is auto generated by the ispLEVER
-
-
-NOTE: This readme file has been provided to instantiate the interface
-netlist. Since this template contains synthesis attributes for precision that
-are crucial to the design flow, we recommend that you use this
-template in your FPGA design.
-entity chip is
-port (
-
--- Add your FPGA design top level I/Os here
-
-
--- ASIC side pins for PCSD. These pins must exist for the
--- PCS core.
- refclkp : in std_logic;
- refclkn : in std_logic;
- hdinp_ch0 : in std_logic;
- hdinn_ch0 : in std_logic;
- hdinp_ch1 : in std_logic;
- hdinn_ch1 : in std_logic;
- hdinp_ch2 : in std_logic;
- hdinn_ch2 : in std_logic;
- hdinp_ch3 : in std_logic;
- hdinn_ch3 : in std_logic;
-
- hdoutp_ch0 : out std_logic;
- hdoutn_ch0 : out std_logic;
- hdoutp_ch1 : out std_logic;
- hdoutn_ch1 : out std_logic;
- hdoutp_ch2 : out std_logic;
- hdoutn_ch2 : out std_logic;
- hdoutp_ch3 : out std_logic;
- hdoutn_ch3 : out std_logic;
-
-
-);
-end chip;
-
-architecture chip_arch of chip is
-
--- This defines all the high-speed ports. You may have to remove
--- some of them depending on your design.
-attribute nopad : string;
-attribute nopad of
- refclkp, refclkn,
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
-
- COMPONENT serdes_ch4
- PORT(
- hdinp_ch3 : IN std_logic;
- hdinn_ch3 : IN std_logic;
- rxiclk_ch3 : IN std_logic;
- txiclk_ch3 : IN std_logic;
- fpga_rxrefclk_ch3 : IN std_logic;
- txdata_ch3 : IN std_logic_vector(7 downto 0);
- tx_k_ch3 : IN std_logic;
- xmit_ch3 : IN std_logic;
- tx_disp_correct_ch3 : IN std_logic;
- rx_serdes_rst_ch3_c : IN std_logic;
- sb_felb_ch3_c : IN std_logic;
- sb_felb_rst_ch3_c : IN std_logic;
- tx_pcs_rst_ch3_c : IN std_logic;
- tx_pwrup_ch3_c : IN std_logic;
- rx_pcs_rst_ch3_c : IN std_logic;
- rx_pwrup_ch3_c : IN std_logic;
- fpga_txrefclk : IN std_logic;
- tx_serdes_rst_c : IN std_logic;
- rst_qd_c : IN std_logic;
- serdes_rst_qd_c : IN std_logic;
- hdoutp_ch3 : OUT std_logic;
- hdoutn_ch3 : OUT std_logic;
- rx_full_clk_ch3 : OUT std_logic;
- rx_half_clk_ch3 : OUT std_logic;
- tx_full_clk_ch3 : OUT std_logic;
- tx_half_clk_ch3 : OUT std_logic;
- rxdata_ch3 : OUT std_logic_vector(7 downto 0);
- rx_k_ch3 : OUT std_logic;
- rx_disp_err_ch3 : OUT std_logic;
- rx_cv_err_ch3 : OUT std_logic;
- rx_los_low_ch3_s : OUT std_logic;
- lsm_status_ch3_s : OUT std_logic;
- rx_cdr_lol_ch3_s : OUT std_logic;
- tx_pll_lol_qd_s : OUT std_logic
- );
- END COMPONENT;
-
-
-
- uut: serdes_ch4 PORT MAP(
- hdinp_ch3 => hdinp_ch3,
- hdinn_ch3 => hdinn_ch3,
- hdoutp_ch3 => hdoutp_ch3,
- hdoutn_ch3 => hdoutn_ch3,
- rxiclk_ch3 => rxiclk_ch3,
- txiclk_ch3 => txiclk_ch3,
- rx_full_clk_ch3 => rx_full_clk_ch3,
- rx_half_clk_ch3 => rx_half_clk_ch3,
- tx_full_clk_ch3 => tx_full_clk_ch3,
- tx_half_clk_ch3 => tx_half_clk_ch3,
- fpga_rxrefclk_ch3 => fpga_rxrefclk_ch3,
- txdata_ch3 => txdata_ch3,
- tx_k_ch3 => tx_k_ch3,
- xmit_ch3 => xmit_ch3,
- tx_disp_correct_ch3 => tx_disp_correct_ch3,
- rxdata_ch3 => rxdata_ch3,
- rx_k_ch3 => rx_k_ch3,
- rx_disp_err_ch3 => rx_disp_err_ch3,
- rx_cv_err_ch3 => rx_cv_err_ch3,
- rx_serdes_rst_ch3_c => rx_serdes_rst_ch3_c,
- sb_felb_ch3_c => sb_felb_ch3_c,
- sb_felb_rst_ch3_c => sb_felb_rst_ch3_c,
- tx_pcs_rst_ch3_c => tx_pcs_rst_ch3_c,
- tx_pwrup_ch3_c => tx_pwrup_ch3_c,
- rx_pcs_rst_ch3_c => rx_pcs_rst_ch3_c,
- rx_pwrup_ch3_c => rx_pwrup_ch3_c,
- rx_los_low_ch3_s => rx_los_low_ch3_s,
- lsm_status_ch3_s => lsm_status_ch3_s,
- rx_cdr_lol_ch3_s => rx_cdr_lol_ch3_s,
- fpga_txrefclk => fpga_txrefclk,
- tx_serdes_rst_c => tx_serdes_rst_c,
- tx_pll_lol_qd_s => tx_pll_lol_qd_s,
- rst_qd_c => rst_qd_c,
- serdes_rst_qd_c => serdes_rst_qd_c
- );
-
-
-
-
+++ /dev/null
-serdes_ch4.vhd
+++ /dev/null
-@set suppresnewline=on@
-
-@comment --------------------------------------------------------------------- @
-@comment Template-drive TFI generator @
-@comment Template for TFI generation. @
-@comment --------------------------------------------------------------------- @
-
-@set suppresnewline=off@
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: %title%
- MODULE: %module%
- DESIGN: %module%
- FILENAME: %filename%
- PROJECT: %project%
- VERSION: %ver%
- This file is auto generated by the ispLEVER
-@set suppresnewline=on@
-
-@cr@
-@cr@
-
-@set sigdelim=@
-
-NOTE: This readme file has been provided to instantiate the interface@cr@
-netlist. Since this template contains synthesis attributes for precision that@cr@
-are crucial to the design flow, we recommend that you use this@cr@
-template in your FPGA design.@cr@
-entity chip is@cr@
-port (@cr@
-@cr@
--- Add your FPGA design top level I/Os here@cr@
-@cr@
-@cr@
--- ASIC side pins for PCSD. These pins must exist for the@cr@
--- PCS core.@cr@
- refclkp : in std_logic;@cr@
- refclkn : in std_logic;@cr@
- hdinp_ch0 : in std_logic;@cr@
- hdinn_ch0 : in std_logic;@cr@
- hdinp_ch1 : in std_logic;@cr@
- hdinn_ch1 : in std_logic;@cr@
- hdinp_ch2 : in std_logic;@cr@
- hdinn_ch2 : in std_logic;@cr@
- hdinp_ch3 : in std_logic;@cr@
- hdinn_ch3 : in std_logic;@cr@
-@cr@
- hdoutp_ch0 : out std_logic;@cr@
- hdoutn_ch0 : out std_logic;@cr@
- hdoutp_ch1 : out std_logic;@cr@
- hdoutn_ch1 : out std_logic;@cr@
- hdoutp_ch2 : out std_logic;@cr@
- hdoutn_ch2 : out std_logic;@cr@
- hdoutp_ch3 : out std_logic;@cr@
- hdoutn_ch3 : out std_logic;@cr@
-@cr@
-@cr@
-);@cr@
-end chip;@cr@
-@cr@
-architecture chip_arch of chip is@cr@
-@cr@
--- This defines all the high-speed ports. You may have to remove@cr@
--- some of them depending on your design.@cr@
-attribute nopad : string;@cr@
-attribute nopad of@cr@
- refclkp, refclkn,@cr@
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
-
-@cr@
-@tab@COMPONENT %module%
-@set sigdelim=@
-@cr@@tab@PORT(
-@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
-@ifhas oport=*@ @comment if the design has any output ports... @
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
- @set sigdelim=;@
- @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
-@endif@
-@ifnhas oport=*@ @comment we need an "else in this language! @
- @set sigdelim=;@
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
-@endif@
-@cr@@tab@@tab@);@cr@
-@tab@END COMPONENT;@cr@@cr@
-@comment Now do a signal declaration for each port @
-
-@cr@@cr@
-@comment do the component instantiation @
-@set sigdelim=,@
-@tab@uut: %module% PORT MAP(
-@iterate@%port%
-@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
-@cr@@tab@);@cr@@cr@
-@set suppresnewline=off@
-
-
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH3_PROTOCOL "GIGE"
-CH0_MODE "DISABLED"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "RXTX"
-CH3_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MED"
-CH3_RX_DATARATE_RANGE "MED"
-REFCK_MULT "10X"
-#REFCLK_RATE 125.0
-CH3_RX_DATA_RATE "FULL"
-CH3_TX_DATA_RATE "FULL"
-CH3_TX_DATA_WIDTH "8"
-CH3_RX_DATA_WIDTH "8"
-CH3_TX_FIFO "ENABLED"
-CH3_RX_FIFO "ENABLED"
-CH3_TDRV "0"
-#CH3_TX_FICLK_RATE 125.0
-#CH3_RXREFCLK_RATE "125.0"
-#CH3_RX_FICLK_RATE 125.0
-CH3_TX_PRE "DISABLED"
-CH3_RTERM_TX "50"
-CH3_RX_EQ "DISABLED"
-CH3_RTERM_RX "50"
-CH3_RX_DCC "AC"
-CH3_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH3_TX_SB "DISABLED"
-CH3_RX_SB "DISABLED"
-CH3_TX_8B10B "ENABLED"
-CH3_RX_8B10B "ENABLED"
-CH3_COMMA_A "1100000101"
-CH3_COMMA_B "0011111010"
-CH3_COMMA_M "1111111111"
-CH3_RXWA "ENABLED"
-CH3_ILSM "ENABLED"
-CH3_CTC "DISABLED"
-CH3_CC_MATCH3 "0110111100"
-CH3_CC_MATCH4 "0001010000"
-CH3_CC_MATCH_MODE "2"
-CH3_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH3_SSLB "DISABLED"
-CH3_SPLBPORTS "DISABLED"
-CH3_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "DISABLED"
-
-
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "serdes_ch4.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_EXT";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_CORE";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_ch4 is
- GENERIC (USER_CONFIG_FILE : String := "serdes_ch4.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
--- CH2 --
--- CH3 --
- hdinp_ch3, hdinn_ch3 : in std_logic;
- hdoutp_ch3, hdoutn_ch3 : out std_logic;
- rxiclk_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- txdata_ch3 : in std_logic_vector (7 downto 0);
- tx_k_ch3 : in std_logic;
- xmit_ch3 : in std_logic;
- tx_disp_correct_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- rx_serdes_rst_ch3_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
- tx_pcs_rst_ch3_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pcs_rst_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
----- Miscillaneous ports
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- rst_qd_c : in std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end serdes_ch4;
-
-
-architecture serdes_ch4_arch of serdes_ch4 is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH3_CDR_SRC: string;
- attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch3_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- rx_los_low_ch3_s <= rx_los_low_ch3_sig;
- rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH3_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => open,
- HDOUTN0 => open,
- HDINP0 => fpsc_vlo,
- HDINN0 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => fpsc_vlo,
- FF_TXI_CLK_0 => fpsc_vlo,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => open,
- FF_RX_H_CLK_0 => open,
- FF_TX_F_CLK_0 => open,
- FF_TX_H_CLK_0 => open,
- FFC_CK_CORE_RX_0 => fpsc_vlo,
- FF_TX_D_0_0 => fpsc_vlo,
- FF_TX_D_0_1 => fpsc_vlo,
- FF_TX_D_0_2 => fpsc_vlo,
- FF_TX_D_0_3 => fpsc_vlo,
- FF_TX_D_0_4 => fpsc_vlo,
- FF_TX_D_0_5 => fpsc_vlo,
- FF_TX_D_0_6 => fpsc_vlo,
- FF_TX_D_0_7 => fpsc_vlo,
- FF_TX_D_0_8 => fpsc_vlo,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => fpsc_vlo,
- FF_TX_D_0_11 => fpsc_vlo,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => open,
- FF_RX_D_0_1 => open,
- FF_RX_D_0_2 => open,
- FF_RX_D_0_3 => open,
- FF_RX_D_0_4 => open,
- FF_RX_D_0_5 => open,
- FF_RX_D_0_6 => open,
- FF_RX_D_0_7 => open,
- FF_RX_D_0_8 => open,
- FF_RX_D_0_9 => open,
- FF_RX_D_0_10 => open,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => fpsc_vlo,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => fpsc_vlo,
- FFC_TXPWDNB_0 => fpsc_vlo,
- FFC_LANE_RX_RST_0 => fpsc_vlo,
- FFC_RXPWDNB_0 => fpsc_vlo,
- FFS_RLOS_LO_0 => open,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => open,
- HDOUTN1 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_TX_F_CLK_1 => open,
- FF_TX_H_CLK_1 => open,
- FFC_CK_CORE_RX_1 => fpsc_vlo,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => fpsc_vlo,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => hdoutp_ch3,
- HDOUTN3 => hdoutn_ch3,
- HDINP3 => hdinp_ch3,
- HDINN3 => hdinn_ch3,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => rxiclk_ch3,
- FF_TXI_CLK_3 => txiclk_ch3,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => rx_full_clk_ch3,
- FF_RX_H_CLK_3 => rx_half_clk_ch3,
- FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
- FF_TX_H_CLK_3 => tx_half_clk_ch3,
- FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
- FF_TX_D_3_0 => txdata_ch3(0),
- FF_TX_D_3_1 => txdata_ch3(1),
- FF_TX_D_3_2 => txdata_ch3(2),
- FF_TX_D_3_3 => txdata_ch3(3),
- FF_TX_D_3_4 => txdata_ch3(4),
- FF_TX_D_3_5 => txdata_ch3(5),
- FF_TX_D_3_6 => txdata_ch3(6),
- FF_TX_D_3_7 => txdata_ch3(7),
- FF_TX_D_3_8 => tx_k_ch3,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => xmit_ch3,
- FF_TX_D_3_11 => tx_disp_correct_ch3,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => rxdata_ch3(0),
- FF_RX_D_3_1 => rxdata_ch3(1),
- FF_RX_D_3_2 => rxdata_ch3(2),
- FF_RX_D_3_3 => rxdata_ch3(3),
- FF_RX_D_3_4 => rxdata_ch3(4),
- FF_RX_D_3_5 => rxdata_ch3(5),
- FF_RX_D_3_6 => rxdata_ch3(6),
- FF_RX_D_3_7 => rxdata_ch3(7),
- FF_RX_D_3_8 => rx_k_ch3,
- FF_RX_D_3_9 => rx_disp_err_ch3,
- FF_RX_D_3_10 => rx_cv_err_ch3,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => rx_serdes_rst_ch3_c,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
- FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
- FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
- FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
- FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
- FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
- SCIWDATA7 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA0 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIRDATA7 => open,
- SCIRDATA6 => open,
- SCIRDATA5 => open,
- SCIRDATA4 => open,
- SCIRDATA3 => open,
- SCIRDATA2 => open,
- SCIRDATA1 => open,
- SCIRDATA0 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
-
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end serdes_ch4_arch ;
+++ /dev/null
-Starting process: Module
-
-Starting process:
-
- Module Name: serdes_ch4
- Core Name: PCS
- LPC file : serdes_ch4.lpc
- Parameter File : serdes_ch4.pp
- Command line: /opt/lattice/diamond/1.4/ispfpga/bin/lin/orcapp -Fmaco serdes_ch4.pp
- Return Value:
-
-
-
- Module PCS has been generated in /home/greg/projects/trb3/trb3_gbe/. successfully!
-
-/opt/lattice/diamond/1.4/bin/lin/hdl2jhd -tfi -mod serdes_ch4 -ext readme -out serdes_ch4 -tpl serdes_ch4.tft serdes_ch4.vhd
-
-Done successfully!
-File: serdes_ch4.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
-dummy_sym.vhd
+++ /dev/null
- Module Name: serdes_gbe_0ch
- Core Name: PCS
- LPC file : serdes_gbe_0ch.lpc
- Parameter File : serdes_gbe_0ch.pp
- Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0ch.pp
- Return Value:
-
-
-
- Module PCS has been generated in /home/greg/projects/trb3/trb3_gbe/simple_test/ipcores/serdes_gbe_0ch/. successfully!
-
-/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0ch -ext readme -out serdes_gbe_0ch -tpl serdes_gbe_0ch.tft serdes_gbe_0ch.vhd
-
-Done successfully!
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_gbe_0ch" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 11 30 14:02:48.322" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_gbe_0ch.lpc" type="lpc" modified="2011 11 30 14:02:46.000"/>
- <File name="serdes_gbe_0ch.pp" type="pp" modified="2011 11 30 14:02:46.000"/>
- <File name="serdes_gbe_0ch.sym" type="sym" modified="2011 11 30 14:02:46.000"/>
- <File name="serdes_gbe_0ch.tft" type="tft" modified="2011 11 30 14:02:46.000"/>
- <File name="serdes_gbe_0ch.txt" type="pcs_module" modified="2011 11 30 14:02:46.000"/>
- <File name="serdes_gbe_0ch.vhd" type="top_level_vhdl" modified="2011 11 30 14:02:46.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE serdes_gbe_0ch DEFIN serdes_gbe_0ch.vhd
- SUBMODULE PCSD
- INSTANCE PCSD_INST
- SUBMODULE VHI
- INSTANCE vhi_inst
- SUBMODULE VLO
- INSTANCE vlo_inst
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-6FN1156C
-SpeedGrade=6
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_gbe_0ch
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=11/30/2011
-Time=14:02:46
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=RXTX
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=GIGE
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=1.25
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=125.0
-_tx_protocol0=GIGE
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=125.0
-_tx_ficlk_rate1=125.0
-_tx_ficlk_rate2=125.0
-_tx_ficlk_rate3=125.0
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=1.25
-_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=2.5
-_rx_protocol0=GIGE
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=125.0
-_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=250.0
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
-_rx_ficlk_rate0=125.0
-_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=250.0
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=AC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=AC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P5
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111111
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=2
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=00
-_k02=00
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=00
-_k31=01
-_k32=01
-_k33=01
-_byten00=10111100
-_byten01=00000000
-_byten02=00000000
-_byten03=00000000
-_byten10=01010000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=10111100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=01010000
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=DISABLED
-_sci_int_port=DISABLED
-_refck2core=DISABLED
-Regen=auto
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_gbe_0ch.pp=pp
-serdes_gbe_0ch.tft=tft
-serdes_gbe_0ch.txt=pcs_module
-serdes_gbe_0ch.sym=sym
+++ /dev/null
-hdinp_ch0 i
-hdinn_ch0 i
-hdoutp_ch0 o
-hdoutn_ch0 o
-rxiclk_ch0 i
-txiclk_ch0 i
-rx_full_clk_ch0 o
-rx_half_clk_ch0 o
-tx_full_clk_ch0 o
-tx_half_clk_ch0 o
-fpga_rxrefclk_ch0 i
-txdata_ch0[7] i
-txdata_ch0[6] i
-txdata_ch0[5] i
-txdata_ch0[4] i
-txdata_ch0[3] i
-txdata_ch0[2] i
-txdata_ch0[1] i
-txdata_ch0[0] i
-tx_k_ch0 i
-xmit_ch0 i
-tx_disp_correct_ch0 i
-rxdata_ch0[7] o
-rxdata_ch0[6] o
-rxdata_ch0[5] o
-rxdata_ch0[4] o
-rxdata_ch0[3] o
-rxdata_ch0[2] o
-rxdata_ch0[1] o
-rxdata_ch0[0] o
-rx_k_ch0 o
-rx_disp_err_ch0 o
-rx_cv_err_ch0 o
-rx_serdes_rst_ch0_c i
-sb_felb_ch0_c i
-sb_felb_rst_ch0_c i
-tx_pcs_rst_ch0_c i
-tx_pwrup_ch0_c i
-rx_pcs_rst_ch0_c i
-rx_pwrup_ch0_c i
-rx_los_low_ch0_s o
-lsm_status_ch0_s o
-rx_cdr_lol_ch0_s o
-fpga_txrefclk i
-tx_serdes_rst_c i
-tx_pll_lol_qd_s o
-rst_qd_c i
-serdes_rst_qd_c i
+++ /dev/null
-#define _device_name "LFE3-150EA"
-#define _ch0_pll_rxsrc "REFCLK_CORE"
-#define _ch0_mode "RXTX"
-#define _ch0_protocol "GIGE"
-#define _ch0_ldr "DISABLED"
-#define _ch0_tx_data_rate "FULL"
-#define _ch0_tx_data_width "8"
-#define _ch0_tx_fifo "ENABLED"
-#define _ch0_tx_ficlk_rate 125.0
-#define _ch0_rx_datarange "MED"
-#define _ch0_rx_data_rate "FULL"
-#define _ch0_rxrefclk_rate "125.0"
-#define _ch0_rx_data_width "8"
-#define _ch0_rx_fifo "ENABLED"
-#define _ch0_rx_ficlk_rate 125.0
-#define _ch0_tdrv "0"
-#define _ch0_tx_pre "DISABLED"
-#define _ch0_rterm_tx "50"
-#define _ch0_rx_eq "DISABLED"
-#define _ch0_rterm_rx "50"
-#define _ch0_rx_dcc "AC"
-#define _los_threshold_mode0 "LOS_E"
-#define _los_threshold_lo0 "2"
-#define _ch0_tx_sb "DISABLED"
-#define _ch0_tx_8b10b "ENABLED"
-#define _ch0_rx_sb "DISABLED"
-#define _ch0_ird "DISABLED"
-#define _ch0_rx_8b10b "ENABLED"
-#define _ch0_rxwa "ENABLED"
-#define _ch0_ilsm "ENABLED"
-#define _ch0_scomma "K28P5"
-#define _ch0_comma_a "1100000101"
-#define _ch0_comma_b "0011111010"
-#define _ch0_comma_m "1111111111"
-#define _ch0_ctc "DISABLED"
-#define _ch0_cc_match_mode "2"
-#define _ch0_byten "0110111100"
-#define _ch0_byten1 "0001010000"
-#define _ch0_byten2 "0110111100"
-#define _ch0_byten3 "0001010000"
-#define _ch0_cc_min_ipg "3"
-#define _ch0_lbtype "DISABLED"
-#define _ch0_teidle "DISABLED"
-#define _ch0_rx_lol_port "INTERNAL"
-
-#define _ch1_pll_rxsrc "REFCLK_EXT"
-#define _ch1_mode "DISABLED"
-#define _ch1_protocol "G8B10B"
-#define _ch1_ldr "DISABLED"
-#define _ch1_tx_data_rate "FULL"
-#define _ch1_tx_data_width "8"
-#define _ch1_tx_fifo "ENABLED"
-#define _ch1_tx_ficlk_rate 125.0
-#define _ch1_rx_datarange "MEDHIGH"
-#define _ch1_rx_data_rate "FULL"
-#define _ch1_rxrefclk_rate "250.0"
-#define _ch1_rx_data_width "8"
-#define _ch1_rx_fifo "ENABLED"
-#define _ch1_rx_ficlk_rate 250.0
-#define _ch1_tdrv "0"
-#define _ch1_tx_pre "DISABLED"
-#define _ch1_rterm_tx "50"
-#define _ch1_rx_eq "DISABLED"
-#define _ch1_rterm_rx "50"
-#define _ch1_rx_dcc "AC"
-#define _los_threshold_mode1 "LOS_E"
-#define _los_threshold_lo1 "2"
-#define _ch1_tx_sb "DISABLED"
-#define _ch1_tx_8b10b "ENABLED"
-#define _ch1_rx_sb "DISABLED"
-#define _ch1_ird "DISABLED"
-#define _ch1_rx_8b10b "ENABLED"
-#define _ch1_rxwa "ENABLED"
-#define _ch1_ilsm "ENABLED"
-#define _ch1_scomma "K28P157"
-#define _ch1_comma_a "1100000101"
-#define _ch1_comma_b "0011111010"
-#define _ch1_comma_m "1111111100"
-#define _ch1_ctc "DISABLED"
-#define _ch1_cc_match_mode "1"
-#define _ch1_byten "0000000000"
-#define _ch1_byten1 "0000000000"
-#define _ch1_byten2 "0100011100"
-#define _ch1_byten3 "0100011100"
-#define _ch1_cc_min_ipg "3"
-#define _ch1_lbtype "DISABLED"
-#define _ch1_teidle "DISABLED"
-#define _ch1_rx_lol_port "INTERNAL"
-
-#define _ch2_pll_rxsrc "REFCLK_EXT"
-#define _ch2_mode "DISABLED"
-#define _ch2_protocol "G8B10B"
-#define _ch2_ldr "DISABLED"
-#define _ch2_tx_data_rate "FULL"
-#define _ch2_tx_data_width "8"
-#define _ch2_tx_fifo "ENABLED"
-#define _ch2_tx_ficlk_rate 125.0
-#define _ch2_rx_datarange "MEDHIGH"
-#define _ch2_rx_data_rate "FULL"
-#define _ch2_rxrefclk_rate "250.0"
-#define _ch2_rx_data_width "8"
-#define _ch2_rx_fifo "ENABLED"
-#define _ch2_rx_ficlk_rate 250.0
-#define _ch2_tdrv "0"
-#define _ch2_tx_pre "DISABLED"
-#define _ch2_rterm_tx "50"
-#define _ch2_rx_eq "DISABLED"
-#define _ch2_rterm_rx "50"
-#define _ch2_rx_dcc "AC"
-#define _los_threshold_mode2 "LOS_E"
-#define _los_threshold_lo2 "2"
-#define _ch2_tx_sb "DISABLED"
-#define _ch2_tx_8b10b "ENABLED"
-#define _ch2_rx_sb "DISABLED"
-#define _ch2_ird "DISABLED"
-#define _ch2_rx_8b10b "ENABLED"
-#define _ch2_rxwa "ENABLED"
-#define _ch2_ilsm "ENABLED"
-#define _ch2_scomma "K28P157"
-#define _ch2_comma_a "1100000101"
-#define _ch2_comma_b "0011111010"
-#define _ch2_comma_m "1111111100"
-#define _ch2_ctc "DISABLED"
-#define _ch2_cc_match_mode "1"
-#define _ch2_byten "0000000000"
-#define _ch2_byten1 "0000000000"
-#define _ch2_byten2 "0100011100"
-#define _ch2_byten3 "0100011100"
-#define _ch2_cc_min_ipg "3"
-#define _ch2_lbtype "DISABLED"
-#define _ch2_teidle "DISABLED"
-#define _ch2_rx_lol_port "INTERNAL"
-
-#define _ch3_pll_rxsrc "REFCLK_EXT"
-#define _ch3_mode "DISABLED"
-#define _ch3_protocol "G8B10B"
-#define _ch3_ldr "DISABLED"
-#define _ch3_tx_data_rate "FULL"
-#define _ch3_tx_data_width "8"
-#define _ch3_tx_fifo "ENABLED"
-#define _ch3_tx_ficlk_rate 125.0
-#define _ch3_rx_datarange "MEDHIGH"
-#define _ch3_rx_data_rate "FULL"
-#define _ch3_rxrefclk_rate "250.0"
-#define _ch3_rx_data_width "8"
-#define _ch3_rx_fifo "ENABLED"
-#define _ch3_rx_ficlk_rate 250.0
-#define _ch3_tdrv "0"
-#define _ch3_tx_pre "DISABLED"
-#define _ch3_rterm_tx "50"
-#define _ch3_rx_eq "DISABLED"
-#define _ch3_rterm_rx "50"
-#define _ch3_rx_dcc "AC"
-#define _los_threshold_mode3 "LOS_E"
-#define _los_threshold_lo3 "2"
-#define _ch3_tx_sb "DISABLED"
-#define _ch3_tx_8b10b "ENABLED"
-#define _ch3_rx_sb "DISABLED"
-#define _ch3_ird "DISABLED"
-#define _ch3_rx_8b10b "ENABLED"
-#define _ch3_rxwa "ENABLED"
-#define _ch3_ilsm "ENABLED"
-#define _ch3_scomma "K28P157"
-#define _ch3_comma_a "1100000101"
-#define _ch3_comma_b "0011111010"
-#define _ch3_comma_m "1111111100"
-#define _ch3_ctc "DISABLED"
-#define _ch3_cc_match_mode "1"
-#define _ch3_byten "0000000000"
-#define _ch3_byten1 "0000000000"
-#define _ch3_byten2 "0100011100"
-#define _ch3_byten3 "0100011100"
-#define _ch3_cc_min_ipg "3"
-#define _ch3_lbtype "DISABLED"
-#define _ch3_teidle "DISABLED"
-#define _ch3_rx_lol_port "INTERNAL"
-
-#define _datarange "MED"
-#define _pll_txsrc "REFCLK_CORE"
-#define _refclk_mult "10X"
-#define _refclk_rate 125.0
-#define _pll_term "50"
-#define _pll_dcc "AC"
-#define _pll_lol_set "0"
-#define _cchmark "9"
-#define _cclmark "7"
-#define _rst_gen "DISABLED"
-#define _sci_ports "DISABLED"
-#define _sci_int_port "DISABLED"
-#define _refck2core "DISABLED"
-#define _circuit_name serdes_gbe_0ch
-#define _lang vhdl
-
-#include <pcs/PCSD.vhd>
-#include <pcs/pcsd_cfg.txt>
+++ /dev/null
-
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: Lattice Semiconductor Corporation
- MODULE: serdes_gbe_0ch
- DESIGN: serdes_gbe_0ch
- FILENAME: serdes_gbe_0ch.readme
- PROJECT: Unknown
- VERSION: 2.0
- This file is auto generated by the ispLEVER
-
-
-NOTE: This readme file has been provided to instantiate the interface
-netlist. Since this template contains synthesis attributes for precision that
-are crucial to the design flow, we recommend that you use this
-template in your FPGA design.
-entity chip is
-port (
-
--- Add your FPGA design top level I/Os here
-
-
--- ASIC side pins for PCSD. These pins must exist for the
--- PCS core.
- refclkp : in std_logic;
- refclkn : in std_logic;
- hdinp_ch0 : in std_logic;
- hdinn_ch0 : in std_logic;
- hdinp_ch1 : in std_logic;
- hdinn_ch1 : in std_logic;
- hdinp_ch2 : in std_logic;
- hdinn_ch2 : in std_logic;
- hdinp_ch3 : in std_logic;
- hdinn_ch3 : in std_logic;
-
- hdoutp_ch0 : out std_logic;
- hdoutn_ch0 : out std_logic;
- hdoutp_ch1 : out std_logic;
- hdoutn_ch1 : out std_logic;
- hdoutp_ch2 : out std_logic;
- hdoutn_ch2 : out std_logic;
- hdoutp_ch3 : out std_logic;
- hdoutn_ch3 : out std_logic;
-
-
-);
-end chip;
-
-architecture chip_arch of chip is
-
--- This defines all the high-speed ports. You may have to remove
--- some of them depending on your design.
-attribute nopad : string;
-attribute nopad of
- refclkp, refclkn,
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
-
- COMPONENT serdes_gbe_0ch
- PORT(
- hdinp_ch0 : IN std_logic;
- hdinn_ch0 : IN std_logic;
- rxiclk_ch0 : IN std_logic;
- txiclk_ch0 : IN std_logic;
- fpga_rxrefclk_ch0 : IN std_logic;
- txdata_ch0 : IN std_logic_vector(7 downto 0);
- tx_k_ch0 : IN std_logic;
- xmit_ch0 : IN std_logic;
- tx_disp_correct_ch0 : IN std_logic;
- rx_serdes_rst_ch0_c : IN std_logic;
- sb_felb_ch0_c : IN std_logic;
- sb_felb_rst_ch0_c : IN std_logic;
- tx_pcs_rst_ch0_c : IN std_logic;
- tx_pwrup_ch0_c : IN std_logic;
- rx_pcs_rst_ch0_c : IN std_logic;
- rx_pwrup_ch0_c : IN std_logic;
- fpga_txrefclk : IN std_logic;
- tx_serdes_rst_c : IN std_logic;
- rst_qd_c : IN std_logic;
- serdes_rst_qd_c : IN std_logic;
- hdoutp_ch0 : OUT std_logic;
- hdoutn_ch0 : OUT std_logic;
- rx_full_clk_ch0 : OUT std_logic;
- rx_half_clk_ch0 : OUT std_logic;
- tx_full_clk_ch0 : OUT std_logic;
- tx_half_clk_ch0 : OUT std_logic;
- rxdata_ch0 : OUT std_logic_vector(7 downto 0);
- rx_k_ch0 : OUT std_logic;
- rx_disp_err_ch0 : OUT std_logic;
- rx_cv_err_ch0 : OUT std_logic;
- rx_los_low_ch0_s : OUT std_logic;
- lsm_status_ch0_s : OUT std_logic;
- rx_cdr_lol_ch0_s : OUT std_logic;
- tx_pll_lol_qd_s : OUT std_logic
- );
- END COMPONENT;
-
-
-
- uut: serdes_gbe_0ch PORT MAP(
- hdinp_ch0 => hdinp_ch0,
- hdinn_ch0 => hdinn_ch0,
- hdoutp_ch0 => hdoutp_ch0,
- hdoutn_ch0 => hdoutn_ch0,
- rxiclk_ch0 => rxiclk_ch0,
- txiclk_ch0 => txiclk_ch0,
- rx_full_clk_ch0 => rx_full_clk_ch0,
- rx_half_clk_ch0 => rx_half_clk_ch0,
- tx_full_clk_ch0 => tx_full_clk_ch0,
- tx_half_clk_ch0 => tx_half_clk_ch0,
- fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0,
- txdata_ch0 => txdata_ch0,
- tx_k_ch0 => tx_k_ch0,
- xmit_ch0 => xmit_ch0,
- tx_disp_correct_ch0 => tx_disp_correct_ch0,
- rxdata_ch0 => rxdata_ch0,
- rx_k_ch0 => rx_k_ch0,
- rx_disp_err_ch0 => rx_disp_err_ch0,
- rx_cv_err_ch0 => rx_cv_err_ch0,
- rx_serdes_rst_ch0_c => rx_serdes_rst_ch0_c,
- sb_felb_ch0_c => sb_felb_ch0_c,
- sb_felb_rst_ch0_c => sb_felb_rst_ch0_c,
- tx_pcs_rst_ch0_c => tx_pcs_rst_ch0_c,
- tx_pwrup_ch0_c => tx_pwrup_ch0_c,
- rx_pcs_rst_ch0_c => rx_pcs_rst_ch0_c,
- rx_pwrup_ch0_c => rx_pwrup_ch0_c,
- rx_los_low_ch0_s => rx_los_low_ch0_s,
- lsm_status_ch0_s => lsm_status_ch0_s,
- rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s,
- fpga_txrefclk => fpga_txrefclk,
- tx_serdes_rst_c => tx_serdes_rst_c,
- tx_pll_lol_qd_s => tx_pll_lol_qd_s,
- rst_qd_c => rst_qd_c,
- serdes_rst_qd_c => serdes_rst_qd_c
- );
-
-
-
-
+++ /dev/null
-serdes_gbe_0ch.vhd
+++ /dev/null
-@set suppresnewline=on@
-
-@comment --------------------------------------------------------------------- @
-@comment Template-drive TFI generator @
-@comment Template for TFI generation. @
-@comment --------------------------------------------------------------------- @
-
-@set suppresnewline=off@
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: %title%
- MODULE: %module%
- DESIGN: %module%
- FILENAME: %filename%
- PROJECT: %project%
- VERSION: %ver%
- This file is auto generated by the ispLEVER
-@set suppresnewline=on@
-
-@cr@
-@cr@
-
-@set sigdelim=@
-
-NOTE: This readme file has been provided to instantiate the interface@cr@
-netlist. Since this template contains synthesis attributes for precision that@cr@
-are crucial to the design flow, we recommend that you use this@cr@
-template in your FPGA design.@cr@
-entity chip is@cr@
-port (@cr@
-@cr@
--- Add your FPGA design top level I/Os here@cr@
-@cr@
-@cr@
--- ASIC side pins for PCSD. These pins must exist for the@cr@
--- PCS core.@cr@
- refclkp : in std_logic;@cr@
- refclkn : in std_logic;@cr@
- hdinp_ch0 : in std_logic;@cr@
- hdinn_ch0 : in std_logic;@cr@
- hdinp_ch1 : in std_logic;@cr@
- hdinn_ch1 : in std_logic;@cr@
- hdinp_ch2 : in std_logic;@cr@
- hdinn_ch2 : in std_logic;@cr@
- hdinp_ch3 : in std_logic;@cr@
- hdinn_ch3 : in std_logic;@cr@
-@cr@
- hdoutp_ch0 : out std_logic;@cr@
- hdoutn_ch0 : out std_logic;@cr@
- hdoutp_ch1 : out std_logic;@cr@
- hdoutn_ch1 : out std_logic;@cr@
- hdoutp_ch2 : out std_logic;@cr@
- hdoutn_ch2 : out std_logic;@cr@
- hdoutp_ch3 : out std_logic;@cr@
- hdoutn_ch3 : out std_logic;@cr@
-@cr@
-@cr@
-);@cr@
-end chip;@cr@
-@cr@
-architecture chip_arch of chip is@cr@
-@cr@
--- This defines all the high-speed ports. You may have to remove@cr@
--- some of them depending on your design.@cr@
-attribute nopad : string;@cr@
-attribute nopad of@cr@
- refclkp, refclkn,@cr@
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
-
-@cr@
-@tab@COMPONENT %module%
-@set sigdelim=@
-@cr@@tab@PORT(
-@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
-@ifhas oport=*@ @comment if the design has any output ports... @
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
- @set sigdelim=;@
- @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
-@endif@
-@ifnhas oport=*@ @comment we need an "else in this language! @
- @set sigdelim=;@
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
-@endif@
-@cr@@tab@@tab@);@cr@
-@tab@END COMPONENT;@cr@@cr@
-@comment Now do a signal declaration for each port @
-
-@cr@@cr@
-@comment do the component instantiation @
-@set sigdelim=,@
-@tab@uut: %module% PORT MAP(
-@iterate@%port%
-@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
-@cr@@tab@);@cr@@cr@
-@set suppresnewline=off@
-
-
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL "GIGE"
-CH0_MODE "RXTX"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH0_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MED"
-CH0_RX_DATARATE_RANGE "MED"
-REFCK_MULT "10X"
-#REFCLK_RATE 125.0
-CH0_RX_DATA_RATE "FULL"
-CH0_TX_DATA_RATE "FULL"
-CH0_TX_DATA_WIDTH "8"
-CH0_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "ENABLED"
-CH0_RX_FIFO "ENABLED"
-CH0_TDRV "0"
-#CH0_TX_FICLK_RATE 125.0
-#CH0_RXREFCLK_RATE "125.0"
-#CH0_RX_FICLK_RATE 125.0
-CH0_TX_PRE "DISABLED"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLED"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "AC"
-CH0_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "DISABLED"
-CH0_RX_SB "DISABLED"
-CH0_TX_8B10B "ENABLED"
-CH0_RX_8B10B "ENABLED"
-CH0_COMMA_A "1100000101"
-CH0_COMMA_B "0011111010"
-CH0_COMMA_M "1111111111"
-CH0_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH0_CTC "DISABLED"
-CH0_CC_MATCH3 "0110111100"
-CH0_CC_MATCH4 "0001010000"
-CH0_CC_MATCH_MODE "2"
-CH0_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH0_SSLB "DISABLED"
-CH0_SPLBPORTS "DISABLED"
-CH0_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "DISABLED"
-
-
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "serdes_gbe_0ch.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_gbe_0ch is
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0ch.txt");
- port (
-------------------
--- CH0 --
- hdinp_ch0, hdinn_ch0 : in std_logic;
- hdoutp_ch0, hdoutn_ch0 : out std_logic;
- rxiclk_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- txdata_ch0 : in std_logic_vector (7 downto 0);
- tx_k_ch0 : in std_logic;
- xmit_ch0 : in std_logic;
- tx_disp_correct_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- rx_serdes_rst_ch0_c : in std_logic;
- sb_felb_ch0_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- tx_pcs_rst_ch0_c : in std_logic;
- tx_pwrup_ch0_c : in std_logic;
- rx_pcs_rst_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
--- CH1 --
--- CH2 --
--- CH3 --
----- Miscillaneous ports
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- rst_qd_c : in std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end serdes_gbe_0ch;
-
-
-architecture serdes_gbe_0ch_arch of serdes_gbe_0ch is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH0_CDR_SRC: string;
- attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch0_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- rx_los_low_ch0_s <= rx_los_low_ch0_sig;
- rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH0_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => hdoutp_ch0,
- HDOUTN0 => hdoutn_ch0,
- HDINP0 => hdinp_ch0,
- HDINN0 => hdinn_ch0,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => rxiclk_ch0,
- FF_TXI_CLK_0 => txiclk_ch0,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => rx_full_clk_ch0,
- FF_RX_H_CLK_0 => rx_half_clk_ch0,
- FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
- FF_TX_H_CLK_0 => tx_half_clk_ch0,
- FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
- FF_TX_D_0_0 => txdata_ch0(0),
- FF_TX_D_0_1 => txdata_ch0(1),
- FF_TX_D_0_2 => txdata_ch0(2),
- FF_TX_D_0_3 => txdata_ch0(3),
- FF_TX_D_0_4 => txdata_ch0(4),
- FF_TX_D_0_5 => txdata_ch0(5),
- FF_TX_D_0_6 => txdata_ch0(6),
- FF_TX_D_0_7 => txdata_ch0(7),
- FF_TX_D_0_8 => tx_k_ch0,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => xmit_ch0,
- FF_TX_D_0_11 => tx_disp_correct_ch0,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => rxdata_ch0(0),
- FF_RX_D_0_1 => rxdata_ch0(1),
- FF_RX_D_0_2 => rxdata_ch0(2),
- FF_RX_D_0_3 => rxdata_ch0(3),
- FF_RX_D_0_4 => rxdata_ch0(4),
- FF_RX_D_0_5 => rxdata_ch0(5),
- FF_RX_D_0_6 => rxdata_ch0(6),
- FF_RX_D_0_7 => rxdata_ch0(7),
- FF_RX_D_0_8 => rx_k_ch0,
- FF_RX_D_0_9 => rx_disp_err_ch0,
- FF_RX_D_0_10 => rx_cv_err_ch0,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => rx_serdes_rst_ch0_c,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
- FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
- FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
- FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
- FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
- FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => open,
- HDOUTN1 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_TX_F_CLK_1 => open,
- FF_TX_H_CLK_1 => open,
- FFC_CK_CORE_RX_1 => fpsc_vlo,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => fpsc_vlo,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => open,
- HDOUTN3 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_TX_F_CLK_3 => open,
- FF_TX_H_CLK_3 => open,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
- SCIWDATA7 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA0 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIRDATA7 => open,
- SCIRDATA6 => open,
- SCIRDATA5 => open,
- SCIRDATA4 => open,
- SCIRDATA3 => open,
- SCIRDATA2 => open,
- SCIRDATA1 => open,
- SCIRDATA0 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
-
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end serdes_gbe_0ch_arch ;
+++ /dev/null
-Starting process: Module
-
-Starting process:
-
- Module Name: serdes_gbe_0ch
- Core Name: PCS
- LPC file : serdes_gbe_0ch.lpc
- Parameter File : serdes_gbe_0ch.pp
- Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0ch.pp
- Return Value:
-
-
-
- Module PCS has been generated in /home/greg/projects/trb3/trb3_gbe/simple_test/ipcores/serdes_gbe_0ch/. successfully!
-
-/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0ch -ext readme -out serdes_gbe_0ch -tpl serdes_gbe_0ch.tft serdes_gbe_0ch.vhd
-
-Done successfully!
-File: serdes_gbe_0ch.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
-dummy_sym.vhd
+++ /dev/null
- Module Name: serdes_gbe_0_intclock_8b_ecp3
- Core Name: PCS
- LPC file : serdes_gbe_0_intclock_8b_ecp3.lpc
- Parameter File : serdes_gbe_0_intclock_8b_ecp3.pp
- Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b_ecp3.pp
- Return Value:
-
-
-
- Module PCS has been generated in /home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/. successfully!
-
-/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b_ecp3 -ext readme -out serdes_gbe_0_intclock_8b_ecp3 -tpl serdes_gbe_0_intclock_8b_ecp3.tft serdes_gbe_0_intclock_8b_ecp3.vhd
-
-Done successfully!
+++ /dev/null
-rst_n i
-refclkdiv2 i
-tx_pll_lol_qd_s i
-rx_serdes_rst_ch_c o
-rx_cdr_lol_ch_s i
-rx_los_low_ch_s i
-rx_pcs_rst_ch_c o
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_gbe_0_intclock_8b" module="serdes_gbe_0_intclock_8b" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 25 14:19:34.543" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_gbe_0_intclock_8b.lpc" type="lpc" modified="2011 09 25 14:19:31.000"/>
- <File name="serdes_gbe_0_intclock_8b.pp" type="pp" modified="2011 09 25 14:19:32.000"/>
- <File name="serdes_gbe_0_intclock_8b.sym" type="sym" modified="2011 09 25 14:19:32.000"/>
- <File name="serdes_gbe_0_intclock_8b.tft" type="tft" modified="2011 09 25 14:19:32.000"/>
- <File name="serdes_gbe_0_intclock_8b.txt" type="pcs_module" modified="2011 09 25 14:19:32.000"/>
- <File name="serdes_gbe_0_intclock_8b.vhd" type="top_level_vhdl" modified="2011 09 25 14:19:32.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE serdes_gbe_0_intclock_8b DEFIN serdes_gbe_0_intclock_8b.vhd
- SUBMODULE PCSD
- INSTANCE PCSD_INST
- SUBMODULE VHI
- INSTANCE vhi_inst
- SUBMODULE VLO
- INSTANCE vlo_inst
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_gbe_0_intclock_8b
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/25/2011
-Time=14:19:31
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=RXTX
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=GIGE
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=1.25
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=125.0
-_tx_protocol0=GIGE
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=125.0
-_tx_ficlk_rate1=125.0
-_tx_ficlk_rate2=125.0
-_tx_ficlk_rate3=125.0
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=1.25
-_rx_datarange1=1.25
-_rx_datarange2=1.25
-_rx_datarange3=1.25
-_rx_protocol0=GIGE
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=125.0
-_rxrefclk_rate1=125.0
-_rxrefclk_rate2=125.0
-_rxrefclk_rate3=125.0
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
-_rx_ficlk_rate0=125.0
-_rx_ficlk_rate1=125.0
-_rx_ficlk_rate2=125.0
-_rx_ficlk_rate3=125.0
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=AC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=AC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P5
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111111
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=2
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=00
-_k02=00
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=00
-_k31=01
-_k32=01
-_k33=01
-_byten00=10111100
-_byten01=00000000
-_byten02=00000000
-_byten03=00000000
-_byten10=01010000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=10111100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=01010000
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=DISABLED
-_sci_int_port=DISABLED
-_refck2core=DISABLED
-Regen=auto
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_gbe_0_intclock_8b.pp=pp
-serdes_gbe_0_intclock_8b.tft=tft
-serdes_gbe_0_intclock_8b.txt=pcs_module
-serdes_gbe_0_intclock_8b.sym=sym
+++ /dev/null
-hdinp_ch0 i
-hdinn_ch0 i
-hdoutp_ch0 o
-hdoutn_ch0 o
-rxiclk_ch0 i
-txiclk_ch0 i
-rx_full_clk_ch0 o
-rx_half_clk_ch0 o
-tx_full_clk_ch0 o
-tx_half_clk_ch0 o
-fpga_rxrefclk_ch0 i
-txdata_ch0[7] i
-txdata_ch0[6] i
-txdata_ch0[5] i
-txdata_ch0[4] i
-txdata_ch0[3] i
-txdata_ch0[2] i
-txdata_ch0[1] i
-txdata_ch0[0] i
-tx_k_ch0 i
-xmit_ch0 i
-tx_disp_correct_ch0 i
-rxdata_ch0[7] o
-rxdata_ch0[6] o
-rxdata_ch0[5] o
-rxdata_ch0[4] o
-rxdata_ch0[3] o
-rxdata_ch0[2] o
-rxdata_ch0[1] o
-rxdata_ch0[0] o
-rx_k_ch0 o
-rx_disp_err_ch0 o
-rx_cv_err_ch0 o
-rx_serdes_rst_ch0_c i
-sb_felb_ch0_c i
-sb_felb_rst_ch0_c i
-tx_pcs_rst_ch0_c i
-tx_pwrup_ch0_c i
-rx_pcs_rst_ch0_c i
-rx_pwrup_ch0_c i
-rx_los_low_ch0_s o
-lsm_status_ch0_s o
-rx_cdr_lol_ch0_s o
-fpga_txrefclk i
-tx_serdes_rst_c i
-tx_pll_lol_qd_s o
-rst_qd_c i
-serdes_rst_qd_c i
+++ /dev/null
-#define _device_name "LFE3-150EA"
-#define _ch0_pll_rxsrc "REFCLK_CORE"
-#define _ch0_mode "RXTX"
-#define _ch0_protocol "GIGE"
-#define _ch0_ldr "DISABLED"
-#define _ch0_tx_data_rate "FULL"
-#define _ch0_tx_data_width "8"
-#define _ch0_tx_fifo "ENABLED"
-#define _ch0_tx_ficlk_rate 125.0
-#define _ch0_rx_datarange "MED"
-#define _ch0_rx_data_rate "FULL"
-#define _ch0_rxrefclk_rate "125.0"
-#define _ch0_rx_data_width "8"
-#define _ch0_rx_fifo "ENABLED"
-#define _ch0_rx_ficlk_rate 125.0
-#define _ch0_tdrv "0"
-#define _ch0_tx_pre "DISABLED"
-#define _ch0_rterm_tx "50"
-#define _ch0_rx_eq "DISABLED"
-#define _ch0_rterm_rx "50"
-#define _ch0_rx_dcc "AC"
-#define _los_threshold_mode0 "LOS_E"
-#define _los_threshold_lo0 "2"
-#define _ch0_tx_sb "DISABLED"
-#define _ch0_tx_8b10b "ENABLED"
-#define _ch0_rx_sb "DISABLED"
-#define _ch0_ird "DISABLED"
-#define _ch0_rx_8b10b "ENABLED"
-#define _ch0_rxwa "ENABLED"
-#define _ch0_ilsm "ENABLED"
-#define _ch0_scomma "K28P5"
-#define _ch0_comma_a "1100000101"
-#define _ch0_comma_b "0011111010"
-#define _ch0_comma_m "1111111111"
-#define _ch0_ctc "DISABLED"
-#define _ch0_cc_match_mode "2"
-#define _ch0_byten "0110111100"
-#define _ch0_byten1 "0001010000"
-#define _ch0_byten2 "0110111100"
-#define _ch0_byten3 "0001010000"
-#define _ch0_cc_min_ipg "3"
-#define _ch0_lbtype "DISABLED"
-#define _ch0_teidle "DISABLED"
-#define _ch0_rx_lol_port "INTERNAL"
-
-#define _ch1_pll_rxsrc "REFCLK_EXT"
-#define _ch1_mode "DISABLED"
-#define _ch1_protocol "G8B10B"
-#define _ch1_ldr "DISABLED"
-#define _ch1_tx_data_rate "FULL"
-#define _ch1_tx_data_width "8"
-#define _ch1_tx_fifo "ENABLED"
-#define _ch1_tx_ficlk_rate 125.0
-#define _ch1_rx_datarange "MED"
-#define _ch1_rx_data_rate "FULL"
-#define _ch1_rxrefclk_rate "125.0"
-#define _ch1_rx_data_width "8"
-#define _ch1_rx_fifo "ENABLED"
-#define _ch1_rx_ficlk_rate 125.0
-#define _ch1_tdrv "0"
-#define _ch1_tx_pre "DISABLED"
-#define _ch1_rterm_tx "50"
-#define _ch1_rx_eq "DISABLED"
-#define _ch1_rterm_rx "50"
-#define _ch1_rx_dcc "AC"
-#define _los_threshold_mode1 "LOS_E"
-#define _los_threshold_lo1 "2"
-#define _ch1_tx_sb "DISABLED"
-#define _ch1_tx_8b10b "ENABLED"
-#define _ch1_rx_sb "DISABLED"
-#define _ch1_ird "DISABLED"
-#define _ch1_rx_8b10b "ENABLED"
-#define _ch1_rxwa "ENABLED"
-#define _ch1_ilsm "ENABLED"
-#define _ch1_scomma "K28P157"
-#define _ch1_comma_a "1100000101"
-#define _ch1_comma_b "0011111010"
-#define _ch1_comma_m "1111111100"
-#define _ch1_ctc "DISABLED"
-#define _ch1_cc_match_mode "1"
-#define _ch1_byten "0000000000"
-#define _ch1_byten1 "0000000000"
-#define _ch1_byten2 "0100011100"
-#define _ch1_byten3 "0100011100"
-#define _ch1_cc_min_ipg "3"
-#define _ch1_lbtype "DISABLED"
-#define _ch1_teidle "DISABLED"
-#define _ch1_rx_lol_port "INTERNAL"
-
-#define _ch2_pll_rxsrc "REFCLK_EXT"
-#define _ch2_mode "DISABLED"
-#define _ch2_protocol "G8B10B"
-#define _ch2_ldr "DISABLED"
-#define _ch2_tx_data_rate "FULL"
-#define _ch2_tx_data_width "8"
-#define _ch2_tx_fifo "ENABLED"
-#define _ch2_tx_ficlk_rate 125.0
-#define _ch2_rx_datarange "MED"
-#define _ch2_rx_data_rate "FULL"
-#define _ch2_rxrefclk_rate "125.0"
-#define _ch2_rx_data_width "8"
-#define _ch2_rx_fifo "ENABLED"
-#define _ch2_rx_ficlk_rate 125.0
-#define _ch2_tdrv "0"
-#define _ch2_tx_pre "DISABLED"
-#define _ch2_rterm_tx "50"
-#define _ch2_rx_eq "DISABLED"
-#define _ch2_rterm_rx "50"
-#define _ch2_rx_dcc "AC"
-#define _los_threshold_mode2 "LOS_E"
-#define _los_threshold_lo2 "2"
-#define _ch2_tx_sb "DISABLED"
-#define _ch2_tx_8b10b "ENABLED"
-#define _ch2_rx_sb "DISABLED"
-#define _ch2_ird "DISABLED"
-#define _ch2_rx_8b10b "ENABLED"
-#define _ch2_rxwa "ENABLED"
-#define _ch2_ilsm "ENABLED"
-#define _ch2_scomma "K28P157"
-#define _ch2_comma_a "1100000101"
-#define _ch2_comma_b "0011111010"
-#define _ch2_comma_m "1111111100"
-#define _ch2_ctc "DISABLED"
-#define _ch2_cc_match_mode "1"
-#define _ch2_byten "0000000000"
-#define _ch2_byten1 "0000000000"
-#define _ch2_byten2 "0100011100"
-#define _ch2_byten3 "0100011100"
-#define _ch2_cc_min_ipg "3"
-#define _ch2_lbtype "DISABLED"
-#define _ch2_teidle "DISABLED"
-#define _ch2_rx_lol_port "INTERNAL"
-
-#define _ch3_pll_rxsrc "REFCLK_EXT"
-#define _ch3_mode "DISABLED"
-#define _ch3_protocol "G8B10B"
-#define _ch3_ldr "DISABLED"
-#define _ch3_tx_data_rate "FULL"
-#define _ch3_tx_data_width "8"
-#define _ch3_tx_fifo "ENABLED"
-#define _ch3_tx_ficlk_rate 125.0
-#define _ch3_rx_datarange "MED"
-#define _ch3_rx_data_rate "FULL"
-#define _ch3_rxrefclk_rate "125.0"
-#define _ch3_rx_data_width "8"
-#define _ch3_rx_fifo "ENABLED"
-#define _ch3_rx_ficlk_rate 125.0
-#define _ch3_tdrv "0"
-#define _ch3_tx_pre "DISABLED"
-#define _ch3_rterm_tx "50"
-#define _ch3_rx_eq "DISABLED"
-#define _ch3_rterm_rx "50"
-#define _ch3_rx_dcc "AC"
-#define _los_threshold_mode3 "LOS_E"
-#define _los_threshold_lo3 "2"
-#define _ch3_tx_sb "DISABLED"
-#define _ch3_tx_8b10b "ENABLED"
-#define _ch3_rx_sb "DISABLED"
-#define _ch3_ird "DISABLED"
-#define _ch3_rx_8b10b "ENABLED"
-#define _ch3_rxwa "ENABLED"
-#define _ch3_ilsm "ENABLED"
-#define _ch3_scomma "K28P157"
-#define _ch3_comma_a "1100000101"
-#define _ch3_comma_b "0011111010"
-#define _ch3_comma_m "1111111100"
-#define _ch3_ctc "DISABLED"
-#define _ch3_cc_match_mode "1"
-#define _ch3_byten "0000000000"
-#define _ch3_byten1 "0000000000"
-#define _ch3_byten2 "0100011100"
-#define _ch3_byten3 "0100011100"
-#define _ch3_cc_min_ipg "3"
-#define _ch3_lbtype "DISABLED"
-#define _ch3_teidle "DISABLED"
-#define _ch3_rx_lol_port "INTERNAL"
-
-#define _datarange "MED"
-#define _pll_txsrc "REFCLK_CORE"
-#define _refclk_mult "10X"
-#define _refclk_rate 125.0
-#define _pll_term "50"
-#define _pll_dcc "AC"
-#define _pll_lol_set "0"
-#define _cchmark "9"
-#define _cclmark "7"
-#define _rst_gen "DISABLED"
-#define _sci_ports "DISABLED"
-#define _sci_int_port "DISABLED"
-#define _refck2core "DISABLED"
-#define _circuit_name serdes_gbe_0_intclock_8b
-#define _lang vhdl
-
-#include <pcs/PCSD.vhd>
-#include <pcs/pcsd_cfg.txt>
+++ /dev/null
-
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: Lattice Semiconductor Corporation
- MODULE: serdes_gbe_0_intclock_8b
- DESIGN: serdes_gbe_0_intclock_8b
- FILENAME: serdes_gbe_0_intclock_8b.readme
- PROJECT: Unknown
- VERSION: 2.0
- This file is auto generated by the ispLEVER
-
-
-NOTE: This readme file has been provided to instantiate the interface
-netlist. Since this template contains synthesis attributes for precision that
-are crucial to the design flow, we recommend that you use this
-template in your FPGA design.
-entity chip is
-port (
-
--- Add your FPGA design top level I/Os here
-
-
--- ASIC side pins for PCSD. These pins must exist for the
--- PCS core.
- refclkp : in std_logic;
- refclkn : in std_logic;
- hdinp_ch0 : in std_logic;
- hdinn_ch0 : in std_logic;
- hdinp_ch1 : in std_logic;
- hdinn_ch1 : in std_logic;
- hdinp_ch2 : in std_logic;
- hdinn_ch2 : in std_logic;
- hdinp_ch3 : in std_logic;
- hdinn_ch3 : in std_logic;
-
- hdoutp_ch0 : out std_logic;
- hdoutn_ch0 : out std_logic;
- hdoutp_ch1 : out std_logic;
- hdoutn_ch1 : out std_logic;
- hdoutp_ch2 : out std_logic;
- hdoutn_ch2 : out std_logic;
- hdoutp_ch3 : out std_logic;
- hdoutn_ch3 : out std_logic;
-
-
-);
-end chip;
-
-architecture chip_arch of chip is
-
--- This defines all the high-speed ports. You may have to remove
--- some of them depending on your design.
-attribute nopad : string;
-attribute nopad of
- refclkp, refclkn,
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
-
- COMPONENT serdes_gbe_0_intclock_8b
- PORT(
- hdinp_ch0 : IN std_logic;
- hdinn_ch0 : IN std_logic;
- rxiclk_ch0 : IN std_logic;
- txiclk_ch0 : IN std_logic;
- fpga_rxrefclk_ch0 : IN std_logic;
- txdata_ch0 : IN std_logic_vector(7 downto 0);
- tx_k_ch0 : IN std_logic;
- xmit_ch0 : IN std_logic;
- tx_disp_correct_ch0 : IN std_logic;
- rx_serdes_rst_ch0_c : IN std_logic;
- sb_felb_ch0_c : IN std_logic;
- sb_felb_rst_ch0_c : IN std_logic;
- tx_pcs_rst_ch0_c : IN std_logic;
- tx_pwrup_ch0_c : IN std_logic;
- rx_pcs_rst_ch0_c : IN std_logic;
- rx_pwrup_ch0_c : IN std_logic;
- fpga_txrefclk : IN std_logic;
- tx_serdes_rst_c : IN std_logic;
- rst_qd_c : IN std_logic;
- serdes_rst_qd_c : IN std_logic;
- hdoutp_ch0 : OUT std_logic;
- hdoutn_ch0 : OUT std_logic;
- rx_full_clk_ch0 : OUT std_logic;
- rx_half_clk_ch0 : OUT std_logic;
- tx_full_clk_ch0 : OUT std_logic;
- tx_half_clk_ch0 : OUT std_logic;
- rxdata_ch0 : OUT std_logic_vector(7 downto 0);
- rx_k_ch0 : OUT std_logic;
- rx_disp_err_ch0 : OUT std_logic;
- rx_cv_err_ch0 : OUT std_logic;
- rx_los_low_ch0_s : OUT std_logic;
- lsm_status_ch0_s : OUT std_logic;
- rx_cdr_lol_ch0_s : OUT std_logic;
- tx_pll_lol_qd_s : OUT std_logic
- );
- END COMPONENT;
-
-
-
- uut: serdes_gbe_0_intclock_8b PORT MAP(
- hdinp_ch0 => hdinp_ch0,
- hdinn_ch0 => hdinn_ch0,
- hdoutp_ch0 => hdoutp_ch0,
- hdoutn_ch0 => hdoutn_ch0,
- rxiclk_ch0 => rxiclk_ch0,
- txiclk_ch0 => txiclk_ch0,
- rx_full_clk_ch0 => rx_full_clk_ch0,
- rx_half_clk_ch0 => rx_half_clk_ch0,
- tx_full_clk_ch0 => tx_full_clk_ch0,
- tx_half_clk_ch0 => tx_half_clk_ch0,
- fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0,
- txdata_ch0 => txdata_ch0,
- tx_k_ch0 => tx_k_ch0,
- xmit_ch0 => xmit_ch0,
- tx_disp_correct_ch0 => tx_disp_correct_ch0,
- rxdata_ch0 => rxdata_ch0,
- rx_k_ch0 => rx_k_ch0,
- rx_disp_err_ch0 => rx_disp_err_ch0,
- rx_cv_err_ch0 => rx_cv_err_ch0,
- rx_serdes_rst_ch0_c => rx_serdes_rst_ch0_c,
- sb_felb_ch0_c => sb_felb_ch0_c,
- sb_felb_rst_ch0_c => sb_felb_rst_ch0_c,
- tx_pcs_rst_ch0_c => tx_pcs_rst_ch0_c,
- tx_pwrup_ch0_c => tx_pwrup_ch0_c,
- rx_pcs_rst_ch0_c => rx_pcs_rst_ch0_c,
- rx_pwrup_ch0_c => rx_pwrup_ch0_c,
- rx_los_low_ch0_s => rx_los_low_ch0_s,
- lsm_status_ch0_s => lsm_status_ch0_s,
- rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s,
- fpga_txrefclk => fpga_txrefclk,
- tx_serdes_rst_c => tx_serdes_rst_c,
- tx_pll_lol_qd_s => tx_pll_lol_qd_s,
- rst_qd_c => rst_qd_c,
- serdes_rst_qd_c => serdes_rst_qd_c
- );
-
-
-
-
+++ /dev/null
-serdes_gbe_0_intclock_8b.vhd
+++ /dev/null
-@set suppresnewline=on@
-
-@comment --------------------------------------------------------------------- @
-@comment Template-drive TFI generator @
-@comment Template for TFI generation. @
-@comment --------------------------------------------------------------------- @
-
-@set suppresnewline=off@
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: %title%
- MODULE: %module%
- DESIGN: %module%
- FILENAME: %filename%
- PROJECT: %project%
- VERSION: %ver%
- This file is auto generated by the ispLEVER
-@set suppresnewline=on@
-
-@cr@
-@cr@
-
-@set sigdelim=@
-
-NOTE: This readme file has been provided to instantiate the interface@cr@
-netlist. Since this template contains synthesis attributes for precision that@cr@
-are crucial to the design flow, we recommend that you use this@cr@
-template in your FPGA design.@cr@
-entity chip is@cr@
-port (@cr@
-@cr@
--- Add your FPGA design top level I/Os here@cr@
-@cr@
-@cr@
--- ASIC side pins for PCSD. These pins must exist for the@cr@
--- PCS core.@cr@
- refclkp : in std_logic;@cr@
- refclkn : in std_logic;@cr@
- hdinp_ch0 : in std_logic;@cr@
- hdinn_ch0 : in std_logic;@cr@
- hdinp_ch1 : in std_logic;@cr@
- hdinn_ch1 : in std_logic;@cr@
- hdinp_ch2 : in std_logic;@cr@
- hdinn_ch2 : in std_logic;@cr@
- hdinp_ch3 : in std_logic;@cr@
- hdinn_ch3 : in std_logic;@cr@
-@cr@
- hdoutp_ch0 : out std_logic;@cr@
- hdoutn_ch0 : out std_logic;@cr@
- hdoutp_ch1 : out std_logic;@cr@
- hdoutn_ch1 : out std_logic;@cr@
- hdoutp_ch2 : out std_logic;@cr@
- hdoutn_ch2 : out std_logic;@cr@
- hdoutp_ch3 : out std_logic;@cr@
- hdoutn_ch3 : out std_logic;@cr@
-@cr@
-@cr@
-);@cr@
-end chip;@cr@
-@cr@
-architecture chip_arch of chip is@cr@
-@cr@
--- This defines all the high-speed ports. You may have to remove@cr@
--- some of them depending on your design.@cr@
-attribute nopad : string;@cr@
-attribute nopad of@cr@
- refclkp, refclkn,@cr@
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
-
-@cr@
-@tab@COMPONENT %module%
-@set sigdelim=@
-@cr@@tab@PORT(
-@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
-@ifhas oport=*@ @comment if the design has any output ports... @
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
- @set sigdelim=;@
- @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
-@endif@
-@ifnhas oport=*@ @comment we need an "else in this language! @
- @set sigdelim=;@
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
-@endif@
-@cr@@tab@@tab@);@cr@
-@tab@END COMPONENT;@cr@@cr@
-@comment Now do a signal declaration for each port @
-
-@cr@@cr@
-@comment do the component instantiation @
-@set sigdelim=,@
-@tab@uut: %module% PORT MAP(
-@iterate@%port%
-@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
-@cr@@tab@);@cr@@cr@
-@set suppresnewline=off@
-
-
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL "GIGE"
-CH0_MODE "RXTX"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH0_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MED"
-CH0_RX_DATARATE_RANGE "MED"
-REFCK_MULT "10X"
-#REFCLK_RATE 125.0
-CH0_RX_DATA_RATE "FULL"
-CH0_TX_DATA_RATE "FULL"
-CH0_TX_DATA_WIDTH "8"
-CH0_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "ENABLED"
-CH0_RX_FIFO "ENABLED"
-CH0_TDRV "0"
-#CH0_TX_FICLK_RATE 125.0
-#CH0_RXREFCLK_RATE "125.0"
-#CH0_RX_FICLK_RATE 125.0
-CH0_TX_PRE "DISABLED"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLED"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "AC"
-CH0_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "DISABLED"
-CH0_RX_SB "DISABLED"
-CH0_TX_8B10B "ENABLED"
-CH0_RX_8B10B "ENABLED"
-CH0_COMMA_A "1100000101"
-CH0_COMMA_B "0011111010"
-CH0_COMMA_M "1111111111"
-CH0_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH0_CTC "DISABLED"
-CH0_CC_MATCH3 "0110111100"
-CH0_CC_MATCH4 "0001010000"
-CH0_CC_MATCH_MODE "2"
-CH0_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH0_SSLB "DISABLED"
-CH0_SPLBPORTS "DISABLED"
-CH0_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "DISABLED"
-
-
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_gbe_0_intclock_8b is
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt");
- port (
-------------------
--- CH0 --
- hdinp_ch0, hdinn_ch0 : in std_logic;
- hdoutp_ch0, hdoutn_ch0 : out std_logic;
- rxiclk_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- txdata_ch0 : in std_logic_vector (7 downto 0);
- tx_k_ch0 : in std_logic;
- xmit_ch0 : in std_logic;
- tx_disp_correct_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- rx_serdes_rst_ch0_c : in std_logic;
- sb_felb_ch0_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- tx_pcs_rst_ch0_c : in std_logic;
- tx_pwrup_ch0_c : in std_logic;
- rx_pcs_rst_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
--- CH1 --
--- CH2 --
--- CH3 --
----- Miscillaneous ports
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- rst_qd_c : in std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end serdes_gbe_0_intclock_8b;
-
-
-architecture serdes_gbe_0_intclock_8b_arch of serdes_gbe_0_intclock_8b is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH0_CDR_SRC: string;
- attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch0_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- rx_los_low_ch0_s <= rx_los_low_ch0_sig;
- rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH0_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => hdoutp_ch0,
- HDOUTN0 => hdoutn_ch0,
- HDINP0 => hdinp_ch0,
- HDINN0 => hdinn_ch0,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => rxiclk_ch0,
- FF_TXI_CLK_0 => txiclk_ch0,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => rx_full_clk_ch0,
- FF_RX_H_CLK_0 => rx_half_clk_ch0,
- FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
- FF_TX_H_CLK_0 => tx_half_clk_ch0,
- FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
- FF_TX_D_0_0 => txdata_ch0(0),
- FF_TX_D_0_1 => txdata_ch0(1),
- FF_TX_D_0_2 => txdata_ch0(2),
- FF_TX_D_0_3 => txdata_ch0(3),
- FF_TX_D_0_4 => txdata_ch0(4),
- FF_TX_D_0_5 => txdata_ch0(5),
- FF_TX_D_0_6 => txdata_ch0(6),
- FF_TX_D_0_7 => txdata_ch0(7),
- FF_TX_D_0_8 => tx_k_ch0,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => xmit_ch0,
- FF_TX_D_0_11 => tx_disp_correct_ch0,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => rxdata_ch0(0),
- FF_RX_D_0_1 => rxdata_ch0(1),
- FF_RX_D_0_2 => rxdata_ch0(2),
- FF_RX_D_0_3 => rxdata_ch0(3),
- FF_RX_D_0_4 => rxdata_ch0(4),
- FF_RX_D_0_5 => rxdata_ch0(5),
- FF_RX_D_0_6 => rxdata_ch0(6),
- FF_RX_D_0_7 => rxdata_ch0(7),
- FF_RX_D_0_8 => rx_k_ch0,
- FF_RX_D_0_9 => rx_disp_err_ch0,
- FF_RX_D_0_10 => rx_cv_err_ch0,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => rx_serdes_rst_ch0_c,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
- FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
- FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
- FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
- FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
- FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => open,
- HDOUTN1 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_TX_F_CLK_1 => open,
- FF_TX_H_CLK_1 => open,
- FFC_CK_CORE_RX_1 => fpsc_vlo,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => fpsc_vlo,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => open,
- HDOUTN3 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_TX_F_CLK_3 => open,
- FF_TX_H_CLK_3 => open,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
- SCIWDATA7 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA0 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIRDATA7 => open,
- SCIRDATA6 => open,
- SCIRDATA5 => open,
- SCIRDATA4 => open,
- SCIRDATA3 => open,
- SCIRDATA2 => open,
- SCIRDATA1 => open,
- SCIRDATA0 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
-
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end serdes_gbe_0_intclock_8b_arch ;
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_gbe_0_intclock_8b_ecp3" module="serdes_gbe_0_intclock_8b_ecp3" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 10 05 15:38:10.991" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_gbe_0_intclock_8b_ecp3.lpc" type="lpc" modified="2011 10 05 15:38:09.000"/>
- <File name="serdes_gbe_0_intclock_8b_ecp3.pp" type="pp" modified="2011 10 05 15:38:09.000"/>
- <File name="serdes_gbe_0_intclock_8b_ecp3.sym" type="sym" modified="2011 10 05 15:38:09.000"/>
- <File name="serdes_gbe_0_intclock_8b_ecp3.tft" type="tft" modified="2011 10 05 15:38:09.000"/>
- <File name="serdes_gbe_0_intclock_8b_ecp3.txt" type="pcs_module" modified="2011 10 05 15:38:09.000"/>
- <File name="serdes_gbe_0_intclock_8b_ecp3.vhd" type="top_level_vhdl" modified="2011 10 05 15:38:09.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE rx_reset_sm DEFIN serdes_gbe_0_intclock_8b_ecp3.vhd
-MODULE tx_reset_sm DEFIN serdes_gbe_0_intclock_8b_ecp3.vhd
-MODULE serdes_gbe_0_intclock_8b_ecp3 DEFIN serdes_gbe_0_intclock_8b_ecp3.vhd
- SUBMODULE tx_reset_sm
- INSTANCE tx_reset_sm_ch
- SUBMODULE rx_reset_sm
- INSTANCE rx_reset_sm_ch0
- SUBMODULE PCSD
- INSTANCE PCSD_INST
- SUBMODULE VHI
- INSTANCE vhi_inst
- SUBMODULE VLO
- INSTANCE vlo_inst
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_gbe_0_intclock_8b_ecp3
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=10/05/2011
-Time=15:38:09
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=RXTX
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=GIGE
-_protocol1=GIGE
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=1.25
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=125.0
-_tx_protocol0=GIGE
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=125.0
-_tx_ficlk_rate1=125.0
-_tx_ficlk_rate2=125.0
-_tx_ficlk_rate3=125.0
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=1.25
-_rx_datarange1=1.25
-_rx_datarange2=1.25
-_rx_datarange3=1.25
-_rx_protocol0=GIGE
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=DIV2
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=125.0
-_rxrefclk_rate1=125.0
-_rxrefclk_rate2=125.0
-_rxrefclk_rate3=125.0
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
-_rx_ficlk_rate0=125.0
-_rx_ficlk_rate1=62.5
-_rx_ficlk_rate2=125.0
-_rx_ficlk_rate3=125.0
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=AC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=AC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P5
-_scomma1=K28P5
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111111
-_comma_m1=1111111111
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=2
-_cc_match_mode1=2
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=00
-_k02=01
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=00
-_k31=00
-_k32=01
-_k33=01
-_byten00=10111100
-_byten01=00000000
-_byten02=00011100
-_byten03=00000000
-_byten10=01010000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=10111100
-_byten21=10111100
-_byten22=00011100
-_byten23=00011100
-_byten30=01010000
-_byten31=01010000
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=ENABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=DISABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=auto
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_gbe_0_intclock_8b_ecp3.pp=pp
-serdes_gbe_0_intclock_8b_ecp3.tft=tft
-serdes_gbe_0_intclock_8b_ecp3.txt=pcs_module
-serdes_gbe_0_intclock_8b_ecp3.sym=sym
+++ /dev/null
-hdinp_ch0 i
-hdinn_ch0 i
-hdoutp_ch0 o
-hdoutn_ch0 o
-rxiclk_ch0 i
-txiclk_ch0 i
-rx_full_clk_ch0 o
-rx_half_clk_ch0 o
-tx_full_clk_ch0 o
-tx_half_clk_ch0 o
-fpga_rxrefclk_ch0 i
-txdata_ch0[7] i
-txdata_ch0[6] i
-txdata_ch0[5] i
-txdata_ch0[4] i
-txdata_ch0[3] i
-txdata_ch0[2] i
-txdata_ch0[1] i
-txdata_ch0[0] i
-tx_k_ch0 i
-xmit_ch0 i
-tx_disp_correct_ch0 i
-rxdata_ch0[7] o
-rxdata_ch0[6] o
-rxdata_ch0[5] o
-rxdata_ch0[4] o
-rxdata_ch0[3] o
-rxdata_ch0[2] o
-rxdata_ch0[1] o
-rxdata_ch0[0] o
-rx_k_ch0 o
-rx_disp_err_ch0 o
-rx_cv_err_ch0 o
-sb_felb_ch0_c i
-sb_felb_rst_ch0_c i
-tx_pwrup_ch0_c i
-rx_pwrup_ch0_c i
-rx_los_low_ch0_s o
-lsm_status_ch0_s o
-rx_cdr_lol_ch0_s o
-fpga_txrefclk i
-tx_serdes_rst_c i
-tx_pll_lol_qd_s o
-refclk2fpga o
-rst_n i
-serdes_rst_qd_c i
+++ /dev/null
-#define _device_name "LFE3-150EA"
-#define _ch0_pll_rxsrc "REFCLK_CORE"
-#define _ch0_mode "RXTX"
-#define _ch0_protocol "GIGE"
-#define _ch0_ldr "DISABLED"
-#define _ch0_tx_data_rate "FULL"
-#define _ch0_tx_data_width "8"
-#define _ch0_tx_fifo "ENABLED"
-#define _ch0_tx_ficlk_rate 125.0
-#define _ch0_rx_datarange "MED"
-#define _ch0_rx_data_rate "FULL"
-#define _ch0_rxrefclk_rate "125.0"
-#define _ch0_rx_data_width "8"
-#define _ch0_rx_fifo "ENABLED"
-#define _ch0_rx_ficlk_rate 125.0
-#define _ch0_tdrv "0"
-#define _ch0_tx_pre "DISABLED"
-#define _ch0_rterm_tx "50"
-#define _ch0_rx_eq "DISABLED"
-#define _ch0_rterm_rx "50"
-#define _ch0_rx_dcc "AC"
-#define _los_threshold_mode0 "LOS_E"
-#define _los_threshold_lo0 "2"
-#define _ch0_tx_sb "DISABLED"
-#define _ch0_tx_8b10b "ENABLED"
-#define _ch0_rx_sb "DISABLED"
-#define _ch0_ird "DISABLED"
-#define _ch0_rx_8b10b "ENABLED"
-#define _ch0_rxwa "ENABLED"
-#define _ch0_ilsm "ENABLED"
-#define _ch0_scomma "K28P5"
-#define _ch0_comma_a "1100000101"
-#define _ch0_comma_b "0011111010"
-#define _ch0_comma_m "1111111111"
-#define _ch0_ctc "DISABLED"
-#define _ch0_cc_match_mode "2"
-#define _ch0_byten "0110111100"
-#define _ch0_byten1 "0001010000"
-#define _ch0_byten2 "0110111100"
-#define _ch0_byten3 "0001010000"
-#define _ch0_cc_min_ipg "3"
-#define _ch0_lbtype "DISABLED"
-#define _ch0_teidle "DISABLED"
-#define _ch0_rx_lol_port "INTERNAL"
-
-#define _ch1_pll_rxsrc "REFCLK_EXT"
-#define _ch1_mode "DISABLED"
-#define _ch1_protocol "GIGE"
-#define _ch1_ldr "DISABLED"
-#define _ch1_tx_data_rate "FULL"
-#define _ch1_tx_data_width "8"
-#define _ch1_tx_fifo "ENABLED"
-#define _ch1_tx_ficlk_rate 125.0
-#define _ch1_rx_datarange "MED"
-#define _ch1_rx_data_rate "DIV2"
-#define _ch1_rxrefclk_rate "125.0"
-#define _ch1_rx_data_width "8"
-#define _ch1_rx_fifo "ENABLED"
-#define _ch1_rx_ficlk_rate 62.5
-#define _ch1_tdrv "0"
-#define _ch1_tx_pre "DISABLED"
-#define _ch1_rterm_tx "50"
-#define _ch1_rx_eq "DISABLED"
-#define _ch1_rterm_rx "50"
-#define _ch1_rx_dcc "AC"
-#define _los_threshold_mode1 "LOS_E"
-#define _los_threshold_lo1 "2"
-#define _ch1_tx_sb "DISABLED"
-#define _ch1_tx_8b10b "ENABLED"
-#define _ch1_rx_sb "DISABLED"
-#define _ch1_ird "DISABLED"
-#define _ch1_rx_8b10b "ENABLED"
-#define _ch1_rxwa "ENABLED"
-#define _ch1_ilsm "ENABLED"
-#define _ch1_scomma "K28P5"
-#define _ch1_comma_a "1100000101"
-#define _ch1_comma_b "0011111010"
-#define _ch1_comma_m "1111111111"
-#define _ch1_ctc "DISABLED"
-#define _ch1_cc_match_mode "2"
-#define _ch1_byten "0000000000"
-#define _ch1_byten1 "0000000000"
-#define _ch1_byten2 "0110111100"
-#define _ch1_byten3 "0001010000"
-#define _ch1_cc_min_ipg "3"
-#define _ch1_lbtype "DISABLED"
-#define _ch1_teidle "DISABLED"
-#define _ch1_rx_lol_port "INTERNAL"
-
-#define _ch2_pll_rxsrc "REFCLK_EXT"
-#define _ch2_mode "DISABLED"
-#define _ch2_protocol "G8B10B"
-#define _ch2_ldr "DISABLED"
-#define _ch2_tx_data_rate "FULL"
-#define _ch2_tx_data_width "8"
-#define _ch2_tx_fifo "ENABLED"
-#define _ch2_tx_ficlk_rate 125.0
-#define _ch2_rx_datarange "MED"
-#define _ch2_rx_data_rate "FULL"
-#define _ch2_rxrefclk_rate "125.0"
-#define _ch2_rx_data_width "8"
-#define _ch2_rx_fifo "ENABLED"
-#define _ch2_rx_ficlk_rate 125.0
-#define _ch2_tdrv "0"
-#define _ch2_tx_pre "DISABLED"
-#define _ch2_rterm_tx "50"
-#define _ch2_rx_eq "DISABLED"
-#define _ch2_rterm_rx "50"
-#define _ch2_rx_dcc "AC"
-#define _los_threshold_mode2 "LOS_E"
-#define _los_threshold_lo2 "2"
-#define _ch2_tx_sb "DISABLED"
-#define _ch2_tx_8b10b "ENABLED"
-#define _ch2_rx_sb "DISABLED"
-#define _ch2_ird "DISABLED"
-#define _ch2_rx_8b10b "ENABLED"
-#define _ch2_rxwa "ENABLED"
-#define _ch2_ilsm "ENABLED"
-#define _ch2_scomma "K28P157"
-#define _ch2_comma_a "1100000101"
-#define _ch2_comma_b "0011111010"
-#define _ch2_comma_m "1111111100"
-#define _ch2_ctc "DISABLED"
-#define _ch2_cc_match_mode "1"
-#define _ch2_byten "0100011100"
-#define _ch2_byten1 "0000000000"
-#define _ch2_byten2 "0100011100"
-#define _ch2_byten3 "0100011100"
-#define _ch2_cc_min_ipg "3"
-#define _ch2_lbtype "DISABLED"
-#define _ch2_teidle "DISABLED"
-#define _ch2_rx_lol_port "INTERNAL"
-
-#define _ch3_pll_rxsrc "REFCLK_EXT"
-#define _ch3_mode "DISABLED"
-#define _ch3_protocol "G8B10B"
-#define _ch3_ldr "DISABLED"
-#define _ch3_tx_data_rate "FULL"
-#define _ch3_tx_data_width "8"
-#define _ch3_tx_fifo "ENABLED"
-#define _ch3_tx_ficlk_rate 125.0
-#define _ch3_rx_datarange "MED"
-#define _ch3_rx_data_rate "FULL"
-#define _ch3_rxrefclk_rate "125.0"
-#define _ch3_rx_data_width "8"
-#define _ch3_rx_fifo "ENABLED"
-#define _ch3_rx_ficlk_rate 125.0
-#define _ch3_tdrv "0"
-#define _ch3_tx_pre "DISABLED"
-#define _ch3_rterm_tx "50"
-#define _ch3_rx_eq "DISABLED"
-#define _ch3_rterm_rx "50"
-#define _ch3_rx_dcc "AC"
-#define _los_threshold_mode3 "LOS_E"
-#define _los_threshold_lo3 "2"
-#define _ch3_tx_sb "DISABLED"
-#define _ch3_tx_8b10b "ENABLED"
-#define _ch3_rx_sb "DISABLED"
-#define _ch3_ird "DISABLED"
-#define _ch3_rx_8b10b "ENABLED"
-#define _ch3_rxwa "ENABLED"
-#define _ch3_ilsm "ENABLED"
-#define _ch3_scomma "K28P157"
-#define _ch3_comma_a "1100000101"
-#define _ch3_comma_b "0011111010"
-#define _ch3_comma_m "1111111100"
-#define _ch3_ctc "DISABLED"
-#define _ch3_cc_match_mode "1"
-#define _ch3_byten "0000000000"
-#define _ch3_byten1 "0000000000"
-#define _ch3_byten2 "0100011100"
-#define _ch3_byten3 "0100011100"
-#define _ch3_cc_min_ipg "3"
-#define _ch3_lbtype "DISABLED"
-#define _ch3_teidle "DISABLED"
-#define _ch3_rx_lol_port "INTERNAL"
-
-#define _datarange "MED"
-#define _pll_txsrc "REFCLK_CORE"
-#define _refclk_mult "10X"
-#define _refclk_rate 125.0
-#define _pll_term "50"
-#define _pll_dcc "AC"
-#define _pll_lol_set "0"
-#define _cchmark "9"
-#define _cclmark "7"
-#define _rst_gen "ENABLED"
-#define _sci_ports "DISABLED"
-#define _sci_int_port "DISABLED"
-#define _refck2core "ENABLED"
-#define _circuit_name serdes_gbe_0_intclock_8b_ecp3
-#define _lang vhdl
-
-#include <pcs/PCSD.vhd>
-#include <pcs/pcsd_cfg.txt>
+++ /dev/null
-
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: Lattice Semiconductor Corporation
- MODULE: serdes_gbe_0_intclock_8b_ecp3
- DESIGN: serdes_gbe_0_intclock_8b_ecp3
- FILENAME: serdes_gbe_0_intclock_8b_ecp3.readme
- PROJECT: Unknown
- VERSION: 2.0
- This file is auto generated by the ispLEVER
-
-
-NOTE: This readme file has been provided to instantiate the interface
-netlist. Since this template contains synthesis attributes for precision that
-are crucial to the design flow, we recommend that you use this
-template in your FPGA design.
-entity chip is
-port (
-
--- Add your FPGA design top level I/Os here
-
-
--- ASIC side pins for PCSD. These pins must exist for the
--- PCS core.
- refclkp : in std_logic;
- refclkn : in std_logic;
- hdinp_ch0 : in std_logic;
- hdinn_ch0 : in std_logic;
- hdinp_ch1 : in std_logic;
- hdinn_ch1 : in std_logic;
- hdinp_ch2 : in std_logic;
- hdinn_ch2 : in std_logic;
- hdinp_ch3 : in std_logic;
- hdinn_ch3 : in std_logic;
-
- hdoutp_ch0 : out std_logic;
- hdoutn_ch0 : out std_logic;
- hdoutp_ch1 : out std_logic;
- hdoutn_ch1 : out std_logic;
- hdoutp_ch2 : out std_logic;
- hdoutn_ch2 : out std_logic;
- hdoutp_ch3 : out std_logic;
- hdoutn_ch3 : out std_logic;
-
-
-);
-end chip;
-
-architecture chip_arch of chip is
-
--- This defines all the high-speed ports. You may have to remove
--- some of them depending on your design.
-attribute nopad : string;
-attribute nopad of
- refclkp, refclkn,
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
-
- COMPONENT serdes_gbe_0_intclock_8b_ecp3
- PORT(
- hdinp_ch0 : IN std_logic;
- hdinn_ch0 : IN std_logic;
- rxiclk_ch0 : IN std_logic;
- txiclk_ch0 : IN std_logic;
- fpga_rxrefclk_ch0 : IN std_logic;
- txdata_ch0 : IN std_logic_vector(7 downto 0);
- tx_k_ch0 : IN std_logic;
- xmit_ch0 : IN std_logic;
- tx_disp_correct_ch0 : IN std_logic;
- sb_felb_ch0_c : IN std_logic;
- sb_felb_rst_ch0_c : IN std_logic;
- tx_pwrup_ch0_c : IN std_logic;
- rx_pwrup_ch0_c : IN std_logic;
- fpga_txrefclk : IN std_logic;
- tx_serdes_rst_c : IN std_logic;
- rst_n : IN std_logic;
- serdes_rst_qd_c : IN std_logic;
- hdoutp_ch0 : OUT std_logic;
- hdoutn_ch0 : OUT std_logic;
- rx_full_clk_ch0 : OUT std_logic;
- rx_half_clk_ch0 : OUT std_logic;
- tx_full_clk_ch0 : OUT std_logic;
- tx_half_clk_ch0 : OUT std_logic;
- rxdata_ch0 : OUT std_logic_vector(7 downto 0);
- rx_k_ch0 : OUT std_logic;
- rx_disp_err_ch0 : OUT std_logic;
- rx_cv_err_ch0 : OUT std_logic;
- rx_los_low_ch0_s : OUT std_logic;
- lsm_status_ch0_s : OUT std_logic;
- rx_cdr_lol_ch0_s : OUT std_logic;
- tx_pll_lol_qd_s : OUT std_logic;
- refclk2fpga : OUT std_logic
- );
- END COMPONENT;
-
-
-
- uut: serdes_gbe_0_intclock_8b_ecp3 PORT MAP(
- hdinp_ch0 => hdinp_ch0,
- hdinn_ch0 => hdinn_ch0,
- hdoutp_ch0 => hdoutp_ch0,
- hdoutn_ch0 => hdoutn_ch0,
- rxiclk_ch0 => rxiclk_ch0,
- txiclk_ch0 => txiclk_ch0,
- rx_full_clk_ch0 => rx_full_clk_ch0,
- rx_half_clk_ch0 => rx_half_clk_ch0,
- tx_full_clk_ch0 => tx_full_clk_ch0,
- tx_half_clk_ch0 => tx_half_clk_ch0,
- fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0,
- txdata_ch0 => txdata_ch0,
- tx_k_ch0 => tx_k_ch0,
- xmit_ch0 => xmit_ch0,
- tx_disp_correct_ch0 => tx_disp_correct_ch0,
- rxdata_ch0 => rxdata_ch0,
- rx_k_ch0 => rx_k_ch0,
- rx_disp_err_ch0 => rx_disp_err_ch0,
- rx_cv_err_ch0 => rx_cv_err_ch0,
- sb_felb_ch0_c => sb_felb_ch0_c,
- sb_felb_rst_ch0_c => sb_felb_rst_ch0_c,
- tx_pwrup_ch0_c => tx_pwrup_ch0_c,
- rx_pwrup_ch0_c => rx_pwrup_ch0_c,
- rx_los_low_ch0_s => rx_los_low_ch0_s,
- lsm_status_ch0_s => lsm_status_ch0_s,
- rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s,
- fpga_txrefclk => fpga_txrefclk,
- tx_serdes_rst_c => tx_serdes_rst_c,
- tx_pll_lol_qd_s => tx_pll_lol_qd_s,
- refclk2fpga => refclk2fpga,
- rst_n => rst_n,
- serdes_rst_qd_c => serdes_rst_qd_c
- );
-
-
-
-
+++ /dev/null
-serdes_gbe_0_intclock_8b_ecp3.vhd
+++ /dev/null
-@set suppresnewline=on@
-
-@comment --------------------------------------------------------------------- @
-@comment Template-drive TFI generator @
-@comment Template for TFI generation. @
-@comment --------------------------------------------------------------------- @
-
-@set suppresnewline=off@
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: %title%
- MODULE: %module%
- DESIGN: %module%
- FILENAME: %filename%
- PROJECT: %project%
- VERSION: %ver%
- This file is auto generated by the ispLEVER
-@set suppresnewline=on@
-
-@cr@
-@cr@
-
-@set sigdelim=@
-
-NOTE: This readme file has been provided to instantiate the interface@cr@
-netlist. Since this template contains synthesis attributes for precision that@cr@
-are crucial to the design flow, we recommend that you use this@cr@
-template in your FPGA design.@cr@
-entity chip is@cr@
-port (@cr@
-@cr@
--- Add your FPGA design top level I/Os here@cr@
-@cr@
-@cr@
--- ASIC side pins for PCSD. These pins must exist for the@cr@
--- PCS core.@cr@
- refclkp : in std_logic;@cr@
- refclkn : in std_logic;@cr@
- hdinp_ch0 : in std_logic;@cr@
- hdinn_ch0 : in std_logic;@cr@
- hdinp_ch1 : in std_logic;@cr@
- hdinn_ch1 : in std_logic;@cr@
- hdinp_ch2 : in std_logic;@cr@
- hdinn_ch2 : in std_logic;@cr@
- hdinp_ch3 : in std_logic;@cr@
- hdinn_ch3 : in std_logic;@cr@
-@cr@
- hdoutp_ch0 : out std_logic;@cr@
- hdoutn_ch0 : out std_logic;@cr@
- hdoutp_ch1 : out std_logic;@cr@
- hdoutn_ch1 : out std_logic;@cr@
- hdoutp_ch2 : out std_logic;@cr@
- hdoutn_ch2 : out std_logic;@cr@
- hdoutp_ch3 : out std_logic;@cr@
- hdoutn_ch3 : out std_logic;@cr@
-@cr@
-@cr@
-);@cr@
-end chip;@cr@
-@cr@
-architecture chip_arch of chip is@cr@
-@cr@
--- This defines all the high-speed ports. You may have to remove@cr@
--- some of them depending on your design.@cr@
-attribute nopad : string;@cr@
-attribute nopad of@cr@
- refclkp, refclkn,@cr@
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
-
-@cr@
-@tab@COMPONENT %module%
-@set sigdelim=@
-@cr@@tab@PORT(
-@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
-@ifhas oport=*@ @comment if the design has any output ports... @
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
- @set sigdelim=;@
- @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
-@endif@
-@ifnhas oport=*@ @comment we need an "else in this language! @
- @set sigdelim=;@
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
-@endif@
-@cr@@tab@@tab@);@cr@
-@tab@END COMPONENT;@cr@@cr@
-@comment Now do a signal declaration for each port @
-
-@cr@@cr@
-@comment do the component instantiation @
-@set sigdelim=,@
-@tab@uut: %module% PORT MAP(
-@iterate@%port%
-@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
-@cr@@tab@);@cr@@cr@
-@set suppresnewline=off@
-
-
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL "GIGE"
-CH0_MODE "RXTX"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH0_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MED"
-CH0_RX_DATARATE_RANGE "MED"
-REFCK_MULT "10X"
-#REFCLK_RATE 125.0
-CH0_RX_DATA_RATE "FULL"
-CH0_TX_DATA_RATE "FULL"
-CH0_TX_DATA_WIDTH "8"
-CH0_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "ENABLED"
-CH0_RX_FIFO "ENABLED"
-CH0_TDRV "0"
-#CH0_TX_FICLK_RATE 125.0
-#CH0_RXREFCLK_RATE "125.0"
-#CH0_RX_FICLK_RATE 125.0
-CH0_TX_PRE "DISABLED"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLED"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "AC"
-CH0_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "DISABLED"
-CH0_RX_SB "DISABLED"
-CH0_TX_8B10B "ENABLED"
-CH0_RX_8B10B "ENABLED"
-CH0_COMMA_A "1100000101"
-CH0_COMMA_B "0011111010"
-CH0_COMMA_M "1111111111"
-CH0_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH0_CTC "DISABLED"
-CH0_CC_MATCH3 "0110111100"
-CH0_CC_MATCH4 "0001010000"
-CH0_CC_MATCH_MODE "2"
-CH0_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH0_SSLB "DISABLED"
-CH0_SPLBPORTS "DISABLED"
-CH0_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "serdes_gbe_0_intclock_8b_ecp3.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
---THIS MODULE IS INSTANTIATED PER RX CHANNEL
---Reset Sequence Generator
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity rx_reset_sm is
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rx_serdes_rst_ch_c: out std_logic;
- rx_cdr_lol_ch_s : in std_logic;
- rx_los_low_ch_s : in std_logic;
- rx_pcs_rst_ch_c : out std_logic
-);
-end rx_reset_sm ;
-
-architecture rx_reset_sm_arch of rx_reset_sm is
-
-type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
-
-signal cs: statetype; -- current state of lsm
-signal ns: statetype; -- next state of lsm
-
-signal tx_pll_lol_qd_s_int: std_logic;
-signal rx_los_low_int: std_logic;
-signal plol_los_int: std_logic;
-signal rx_lol_los : std_logic;
-signal rx_lol_los_int: std_logic;
-signal rx_lol_los_del: std_logic;
-signal rx_pcs_rst_ch_c_int: std_logic;
-signal rx_serdes_rst_ch_c_int: std_logic;
-
-signal reset_timer1: std_logic;
-signal reset_timer2: std_logic;
-
-signal counter1: std_logic_vector(1 downto 0);
-signal TIMER1: std_logic;
-
-signal counter2: std_logic_vector(18 downto 0);
-signal TIMER2 : std_logic;
-
-begin
-
-rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
-
-process(refclkdiv2,rst_n)
-begin
- if rising_edge(refclkdiv2) then
- if rst_n = '0' then
- cs <= WAIT_FOR_PLOL;
- rx_lol_los_int <= '1';
- rx_lol_los_del <= '1';
- tx_pll_lol_qd_s_int <= '1';
- rx_pcs_rst_ch_c <= '1';
- rx_serdes_rst_ch_c <= '0';
- rx_los_low_int <= '1';
- else
- cs <= ns;
- rx_lol_los_del <= rx_lol_los;
- rx_lol_los_int <= rx_lol_los_del;
- tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
- rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
- rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
- rx_los_low_int <= rx_los_low_ch_s;
- end if;
- end if;
-end process;
-
---TIMER1 = 3NS;
---Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
---A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
-
-process(refclkdiv2, reset_timer1)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer1 = '1' then
- counter1 <= "00";
- TIMER1 <= '0';
- else
- if counter1(1) = '1' then
- TIMER1 <='1';
- else
- TIMER1 <='0';
- counter1 <= counter1 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
---TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
---An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-
-process(refclkdiv2, reset_timer2)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer2 = '1' then
- counter2 <= "0000000000000000000";
- TIMER2 <= '0';
- else
- if counter2(count_index) = '1' then
- TIMER2 <='1';
- else
- TIMER2 <='0';
- counter2 <= counter2 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-
-process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
-begin
- reset_timer1 <= '0';
- reset_timer2 <= '0';
-
- case cs is
- when WAIT_FOR_PLOL =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal
- ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next
- else
- ns <= RX_SERDES_RESET;
- end if;
-
- when RX_SERDES_RESET =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '1';
- reset_timer1 <= '1';
- ns <= WAIT_FOR_TIMER1;
-
-
- when WAIT_FOR_TIMER1 =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '1';
- if TIMER1 = '1' then
- ns <= CHECK_LOL_LOS;
- else
- ns <= WAIT_FOR_TIMER1;
- end if;
-
- when CHECK_LOL_LOS =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- reset_timer2 <= '1';
- ns <= WAIT_FOR_TIMER2;
-
- when WAIT_FOR_TIMER2 =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES
- if TIMER2 = '1' then
- if rx_lol_los_int = '1' then
- ns <= WAIT_FOR_PLOL;
- else
- ns <= NORMAL;
- end if;
- else
- ns <= WAIT_FOR_TIMER2;
- end if;
- else
- ns <= CHECK_LOL_LOS; --RESET TIMER2
- end if;
-
- when NORMAL =>
- rx_pcs_rst_ch_c_int <= '0';
- rx_serdes_rst_ch_c_int <= '0';
- if rx_lol_los_int = '1' then
- ns <= WAIT_FOR_PLOL;
- else
- ns <= NORMAL;
- end if;
-
- when others =>
- ns <= WAIT_FOR_PLOL;
-
- end case;
-
-end process;
-
-
-end rx_reset_sm_arch;
-
---THIS MODULE IS INSTANTIATED PER TX QUAD
---TX Reset Sequence state machine--
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity tx_reset_sm is
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rst_qd_c : out std_logic;
- tx_pcs_rst_ch_c : out std_logic
- );
-end tx_reset_sm;
-
-architecture tx_reset_sm_arch of tx_reset_sm is
-
-type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
-
-signal cs: statetype; -- current state of lsm
-signal ns: statetype; -- next state of lsm
-
-signal tx_pll_lol_qd_s_int : std_logic;
-signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0);
-signal rst_qd_c_int : std_logic;
-
-signal reset_timer1: std_logic;
-signal reset_timer2: std_logic;
-
-signal counter1: std_logic_vector(2 downto 0);
-signal TIMER1: std_logic;
-
-signal counter2: std_logic_vector(18 downto 0);
-signal TIMER2: std_logic;
-
-begin
-
-process (refclkdiv2, rst_n)
-begin
- if rst_n = '0' then
- cs <= QUAD_RESET;
- tx_pll_lol_qd_s_int <= '1';
- tx_pcs_rst_ch_c <= '1';
- rst_qd_c <= '1';
- else if rising_edge(refclkdiv2) then
- cs <= ns;
- tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
- tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
- rst_qd_c <= rst_qd_c_int;
- end if;
- end if;
-end process;
---TIMER1 = 20ns;
---Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
--- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
-
-
-process (refclkdiv2, reset_timer1)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer1 = '1' then
- counter1 <= "000";
- TIMER1 <= '0';
- else
- if counter1(2) = '1' then
- TIMER1 <= '1';
- else
- TIMER1 <='0';
- counter1 <= counter1 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-
---TIMER2 = 1,400,000 UI;
---WORST CASE CYCLES is with smallest multipier factor.
--- This would be with X8 clock multiplier in DIV2 mode
--- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
--- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
--- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-
-
-process(refclkdiv2, reset_timer2)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer2 = '1' then
- counter2 <= "0000000000000000000";
- TIMER2 <= '0';
- else
- if counter2(count_index) = '1' then
- TIMER2 <='1';
- else
- TIMER2 <='0';
- counter2 <= counter2 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
-begin
-
- reset_timer1 <= '0';
- reset_timer2 <= '0';
-
- case cs is
-
- when QUAD_RESET =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '1';
- reset_timer1 <= '1';
- ns <= WAIT_FOR_TIMER1;
-
- when WAIT_FOR_TIMER1 =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '1';
- if TIMER1 = '1' then
- ns <= CHECK_PLOL;
- else
- ns <= WAIT_FOR_TIMER1;
- end if;
-
- when CHECK_PLOL =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '0';
- reset_timer2 <= '1';
- ns <= WAIT_FOR_TIMER2;
-
- when WAIT_FOR_TIMER2 =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '0';
- if TIMER2 = '1' then
- if tx_pll_lol_qd_s_int = '1' then
- ns <= QUAD_RESET;
- else
- ns <= NORMAL;
- end if;
- else
- ns <= WAIT_FOR_TIMER2;
- end if;
-
- when NORMAL =>
- tx_pcs_rst_ch_c_int <= "0000";
- rst_qd_c_int <= '0';
- if tx_pll_lol_qd_s_int = '1' then
- ns <= QUAD_RESET;
- else
- ns <= NORMAL;
- end if;
-
- when others =>
- ns <= QUAD_RESET;
-
- end case;
-
-end process;
-
-end tx_reset_sm_arch;
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_gbe_0_intclock_8b_ecp3 is
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b_ecp3.txt");
- port (
-------------------
--- CH0 --
- hdinp_ch0, hdinn_ch0 : in std_logic;
- hdoutp_ch0, hdoutn_ch0 : out std_logic;
- rxiclk_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- txdata_ch0 : in std_logic_vector (7 downto 0);
- tx_k_ch0 : in std_logic;
- xmit_ch0 : in std_logic;
- tx_disp_correct_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- sb_felb_ch0_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- tx_pwrup_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
--- CH1 --
--- CH2 --
--- CH3 --
----- Miscillaneous ports
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- refclk2fpga : out std_logic;
- rst_n : in std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end serdes_gbe_0_intclock_8b_ecp3;
-
-
-architecture serdes_gbe_0_intclock_8b_ecp3_arch of serdes_gbe_0_intclock_8b_ecp3 is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-component rx_reset_sm
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rx_serdes_rst_ch_c: out std_logic;
- rx_cdr_lol_ch_s : in std_logic;
- rx_los_low_ch_s : in std_logic;
- rx_pcs_rst_ch_c : out std_logic
-);
-end component ;
-
-component tx_reset_sm
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rst_qd_c : out std_logic;
- tx_pcs_rst_ch_c : out std_logic
- );
-end component;
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH0_CDR_SRC: string;
- attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "31.2500";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "125.0";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch0_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-signal rx_serdes_rst_ch0_c : std_logic;
-signal rx_pcs_rst_ch0_c : std_logic;
-
--- reset sequence for rx
-signal refclkdiv2_rx_ch0 : std_logic;
-
-signal refclkdiv2_tx_ch : std_logic;
-signal tx_pcs_rst_ch_c : std_logic;
-signal rst_qd_c : std_logic;
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- refclk2fpga <= refclk2fpga_sig;
- rx_los_low_ch0_s <= rx_los_low_ch0_sig;
- rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH0_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => hdoutp_ch0,
- HDOUTN0 => hdoutn_ch0,
- HDINP0 => hdinp_ch0,
- HDINN0 => hdinn_ch0,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => rxiclk_ch0,
- FF_TXI_CLK_0 => txiclk_ch0,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => rx_full_clk_ch0,
- FF_RX_H_CLK_0 => rx_half_clk_ch0,
- FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
- FF_TX_H_CLK_0 => tx_half_clk_ch0,
- FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
- FF_TX_D_0_0 => txdata_ch0(0),
- FF_TX_D_0_1 => txdata_ch0(1),
- FF_TX_D_0_2 => txdata_ch0(2),
- FF_TX_D_0_3 => txdata_ch0(3),
- FF_TX_D_0_4 => txdata_ch0(4),
- FF_TX_D_0_5 => txdata_ch0(5),
- FF_TX_D_0_6 => txdata_ch0(6),
- FF_TX_D_0_7 => txdata_ch0(7),
- FF_TX_D_0_8 => tx_k_ch0,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => xmit_ch0,
- FF_TX_D_0_11 => tx_disp_correct_ch0,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => rxdata_ch0(0),
- FF_RX_D_0_1 => rxdata_ch0(1),
- FF_RX_D_0_2 => rxdata_ch0(2),
- FF_RX_D_0_3 => rxdata_ch0(3),
- FF_RX_D_0_4 => rxdata_ch0(4),
- FF_RX_D_0_5 => rxdata_ch0(5),
- FF_RX_D_0_6 => rxdata_ch0(6),
- FF_RX_D_0_7 => rxdata_ch0(7),
- FF_RX_D_0_8 => rx_k_ch0,
- FF_RX_D_0_9 => rx_disp_err_ch0,
- FF_RX_D_0_10 => rx_cv_err_ch0,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => rx_serdes_rst_ch0_c,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
- FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => tx_pcs_rst_ch_c,
- FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
- FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
- FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
- FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => open,
- HDOUTN1 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_TX_F_CLK_1 => open,
- FF_TX_H_CLK_1 => open,
- FFC_CK_CORE_RX_1 => fpsc_vlo,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => fpsc_vlo,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => open,
- HDOUTN3 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_TX_F_CLK_3 => open,
- FF_TX_H_CLK_3 => open,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
- SCIWDATA7 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA0 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIRDATA7 => open,
- SCIRDATA6 => open,
- SCIRDATA5 => open,
- SCIRDATA4 => open,
- SCIRDATA3 => open,
- SCIRDATA2 => open,
- SCIRDATA1 => open,
- SCIRDATA0 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
--- reset sequence for rx
-
- P1 : PROCESS(fpga_rxrefclk_ch0, rst_n)
- BEGIN
- IF (rst_n = '0') THEN
- refclkdiv2_rx_ch0 <= '0';
- ELSIF (fpga_rxrefclk_ch0'event and fpga_rxrefclk_ch0 = '1') THEN
- refclkdiv2_rx_ch0 <= not refclkdiv2_rx_ch0;
- END IF;
- END PROCESS;
-
-rx_reset_sm_ch0 : rx_reset_sm
---synopsys translate_off
- generic map (count_index => 4)
---synopsys translate_on
-port map (
- refclkdiv2 => refclkdiv2_rx_ch0,
- rst_n => rst_n,
- rx_cdr_lol_ch_s => rx_cdr_lol_ch0_sig,
- rx_los_low_ch_s => rx_los_low_ch0_sig,
- tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
- rx_pcs_rst_ch_c => rx_pcs_rst_ch0_c,
- rx_serdes_rst_ch_c => rx_serdes_rst_ch0_c);
-
-
-
-
-
- P5 : PROCESS(fpga_txrefclk, rst_n)
- BEGIN
- IF (rst_n = '0') THEN
- refclkdiv2_tx_ch <= '0';
- ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
- refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
- END IF;
- END PROCESS;
-
--- reset sequence for tx
-tx_reset_sm_ch : tx_reset_sm
---synopsys translate_off
- generic map (count_index => 4)
---synopsys translate_on
-port map (
- rst_n => rst_n,
- refclkdiv2 => refclkdiv2_tx_ch,
- tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
- rst_qd_c => rst_qd_c,
- tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
- );
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end serdes_gbe_0_intclock_8b_ecp3_arch ;
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "serdes_gbe_0_intclock_8b_ecp3.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
---THIS MODULE IS INSTANTIATED PER RX CHANNEL
---Reset Sequence Generator
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity rx_reset_sm is
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rx_serdes_rst_ch_c: out std_logic;
- rx_cdr_lol_ch_s : in std_logic;
- rx_los_low_ch_s : in std_logic;
- rx_pcs_rst_ch_c : out std_logic
-);
-end rx_reset_sm ;
-
-architecture rx_reset_sm_arch of rx_reset_sm is
-
-type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
-
-signal cs: statetype; -- current state of lsm
-signal ns: statetype; -- next state of lsm
-
-signal tx_pll_lol_qd_s_int: std_logic;
-signal rx_los_low_int: std_logic;
-signal plol_los_int: std_logic;
-signal rx_lol_los : std_logic;
-signal rx_lol_los_int: std_logic;
-signal rx_lol_los_del: std_logic;
-signal rx_pcs_rst_ch_c_int: std_logic;
-signal rx_serdes_rst_ch_c_int: std_logic;
-
-signal reset_timer1: std_logic;
-signal reset_timer2: std_logic;
-
-signal counter1: std_logic_vector(1 downto 0);
-signal TIMER1: std_logic;
-
-signal counter2: std_logic_vector(18 downto 0);
-signal TIMER2 : std_logic;
-
-begin
-
-rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
-
-process(refclkdiv2,rst_n)
-begin
- if rising_edge(refclkdiv2) then
- if rst_n = '0' then
- cs <= WAIT_FOR_PLOL;
- rx_lol_los_int <= '1';
- rx_lol_los_del <= '1';
- tx_pll_lol_qd_s_int <= '1';
- rx_pcs_rst_ch_c <= '1';
- rx_serdes_rst_ch_c <= '0';
- rx_los_low_int <= '1';
- else
- cs <= ns;
- rx_lol_los_del <= rx_lol_los;
- rx_lol_los_int <= rx_lol_los_del;
- tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
- rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
- rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
- rx_los_low_int <= rx_los_low_ch_s;
- end if;
- end if;
-end process;
-
---TIMER1 = 3NS;
---Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
---A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
-
-process(refclkdiv2, reset_timer1)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer1 = '1' then
- counter1 <= "00";
- TIMER1 <= '0';
- else
- if counter1(1) = '1' then
- TIMER1 <='1';
- else
- TIMER1 <='0';
- counter1 <= counter1 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
---TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
---An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-
-process(refclkdiv2, reset_timer2)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer2 = '1' then
- counter2 <= "0000000000000000000";
- TIMER2 <= '0';
- else
- if counter2(count_index) = '1' then
- TIMER2 <='1';
- else
- TIMER2 <='0';
- counter2 <= counter2 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-
-process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
-begin
- reset_timer1 <= '0';
- reset_timer2 <= '0';
-
- case cs is
- when WAIT_FOR_PLOL =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal
- ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next
- else
- ns <= RX_SERDES_RESET;
- end if;
-
- when RX_SERDES_RESET =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '1';
- reset_timer1 <= '1';
- ns <= WAIT_FOR_TIMER1;
-
-
- when WAIT_FOR_TIMER1 =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '1';
- if TIMER1 = '1' then
- ns <= CHECK_LOL_LOS;
- else
- ns <= WAIT_FOR_TIMER1;
- end if;
-
- when CHECK_LOL_LOS =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- reset_timer2 <= '1';
- ns <= WAIT_FOR_TIMER2;
-
- when WAIT_FOR_TIMER2 =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES
- if TIMER2 = '1' then
- if rx_lol_los_int = '1' then
- ns <= WAIT_FOR_PLOL;
- else
- ns <= NORMAL;
- end if;
- else
- ns <= WAIT_FOR_TIMER2;
- end if;
- else
- ns <= CHECK_LOL_LOS; --RESET TIMER2
- end if;
-
- when NORMAL =>
- rx_pcs_rst_ch_c_int <= '0';
- rx_serdes_rst_ch_c_int <= '0';
- if rx_lol_los_int = '1' then
- ns <= WAIT_FOR_PLOL;
- else
- ns <= NORMAL;
- end if;
-
- when others =>
- ns <= WAIT_FOR_PLOL;
-
- end case;
-
-end process;
-
-
-end rx_reset_sm_arch;
-
---THIS MODULE IS INSTANTIATED PER TX QUAD
---TX Reset Sequence state machine--
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity tx_reset_sm is
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rst_qd_c : out std_logic;
- tx_pcs_rst_ch_c : out std_logic
- );
-end tx_reset_sm;
-
-architecture tx_reset_sm_arch of tx_reset_sm is
-
-type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
-
-signal cs: statetype; -- current state of lsm
-signal ns: statetype; -- next state of lsm
-
-signal tx_pll_lol_qd_s_int : std_logic;
-signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0);
-signal rst_qd_c_int : std_logic;
-
-signal reset_timer1: std_logic;
-signal reset_timer2: std_logic;
-
-signal counter1: std_logic_vector(2 downto 0);
-signal TIMER1: std_logic;
-
-signal counter2: std_logic_vector(18 downto 0);
-signal TIMER2: std_logic;
-
-begin
-
-process (refclkdiv2, rst_n)
-begin
- if rst_n = '0' then
- cs <= QUAD_RESET;
- tx_pll_lol_qd_s_int <= '1';
- tx_pcs_rst_ch_c <= '1';
- rst_qd_c <= '1';
- else if rising_edge(refclkdiv2) then
- cs <= ns;
- tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
- tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
- rst_qd_c <= rst_qd_c_int;
- end if;
- end if;
-end process;
---TIMER1 = 20ns;
---Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
--- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
-
-
-process (refclkdiv2, reset_timer1)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer1 = '1' then
- counter1 <= "000";
- TIMER1 <= '0';
- else
- if counter1(2) = '1' then
- TIMER1 <= '1';
- else
- TIMER1 <='0';
- counter1 <= counter1 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-
---TIMER2 = 1,400,000 UI;
---WORST CASE CYCLES is with smallest multipier factor.
--- This would be with X8 clock multiplier in DIV2 mode
--- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
--- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
--- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-
-
-process(refclkdiv2, reset_timer2)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer2 = '1' then
- counter2 <= "0000000000000000000";
- TIMER2 <= '0';
- else
- if counter2(count_index) = '1' then
- TIMER2 <='1';
- else
- TIMER2 <='0';
- counter2 <= counter2 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
-begin
-
- reset_timer1 <= '0';
- reset_timer2 <= '0';
-
- case cs is
-
- when QUAD_RESET =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '1';
- reset_timer1 <= '1';
- ns <= WAIT_FOR_TIMER1;
-
- when WAIT_FOR_TIMER1 =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '1';
- if TIMER1 = '1' then
- ns <= CHECK_PLOL;
- else
- ns <= WAIT_FOR_TIMER1;
- end if;
-
- when CHECK_PLOL =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '0';
- reset_timer2 <= '1';
- ns <= WAIT_FOR_TIMER2;
-
- when WAIT_FOR_TIMER2 =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '0';
- if TIMER2 = '1' then
- if tx_pll_lol_qd_s_int = '1' then
- ns <= QUAD_RESET;
- else
- ns <= NORMAL;
- end if;
- else
- ns <= WAIT_FOR_TIMER2;
- end if;
-
- when NORMAL =>
- tx_pcs_rst_ch_c_int <= "0000";
- rst_qd_c_int <= '0';
- if tx_pll_lol_qd_s_int = '1' then
- ns <= QUAD_RESET;
- else
- ns <= NORMAL;
- end if;
-
- when others =>
- ns <= QUAD_RESET;
-
- end case;
-
-end process;
-
-end tx_reset_sm_arch;
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_gbe_0_intclock_8b_ecp3 is
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b_ecp3.txt");
- port (
-------------------
--- CH0 --
- hdinp_ch0, hdinn_ch0 : in std_logic;
- hdoutp_ch0, hdoutn_ch0 : out std_logic;
- rxiclk_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- txdata_ch0 : in std_logic_vector (7 downto 0);
- tx_k_ch0 : in std_logic;
- xmit_ch0 : in std_logic;
- tx_disp_correct_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- sb_felb_ch0_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- tx_pwrup_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
--- CH1 --
--- CH2 --
--- CH3 --
----- Miscillaneous ports
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- rst_n : in std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end serdes_gbe_0_intclock_8b_ecp3;
-
-
-architecture serdes_gbe_0_intclock_8b_ecp3_arch of serdes_gbe_0_intclock_8b_ecp3 is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-component rx_reset_sm
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rx_serdes_rst_ch_c: out std_logic;
- rx_cdr_lol_ch_s : in std_logic;
- rx_los_low_ch_s : in std_logic;
- rx_pcs_rst_ch_c : out std_logic
-);
-end component ;
-
-component tx_reset_sm
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rst_qd_c : out std_logic;
- tx_pcs_rst_ch_c : out std_logic
- );
-end component;
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH0_CDR_SRC: string;
- attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch0_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-signal rx_serdes_rst_ch0_c : std_logic;
-signal rx_pcs_rst_ch0_c : std_logic;
-
--- reset sequence for rx
-signal refclkdiv2_rx_ch0 : std_logic;
-
-signal refclkdiv2_tx_ch : std_logic;
-signal tx_pcs_rst_ch_c : std_logic;
-signal rst_qd_c : std_logic;
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- rx_los_low_ch0_s <= rx_los_low_ch0_sig;
- rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH0_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => hdoutp_ch0,
- HDOUTN0 => hdoutn_ch0,
- HDINP0 => hdinp_ch0,
- HDINN0 => hdinn_ch0,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => rxiclk_ch0,
- FF_TXI_CLK_0 => txiclk_ch0,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => rx_full_clk_ch0,
- FF_RX_H_CLK_0 => rx_half_clk_ch0,
- FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
- FF_TX_H_CLK_0 => tx_half_clk_ch0,
- FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
- FF_TX_D_0_0 => txdata_ch0(0),
- FF_TX_D_0_1 => txdata_ch0(1),
- FF_TX_D_0_2 => txdata_ch0(2),
- FF_TX_D_0_3 => txdata_ch0(3),
- FF_TX_D_0_4 => txdata_ch0(4),
- FF_TX_D_0_5 => txdata_ch0(5),
- FF_TX_D_0_6 => txdata_ch0(6),
- FF_TX_D_0_7 => txdata_ch0(7),
- FF_TX_D_0_8 => tx_k_ch0,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => xmit_ch0,
- FF_TX_D_0_11 => tx_disp_correct_ch0,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => rxdata_ch0(0),
- FF_RX_D_0_1 => rxdata_ch0(1),
- FF_RX_D_0_2 => rxdata_ch0(2),
- FF_RX_D_0_3 => rxdata_ch0(3),
- FF_RX_D_0_4 => rxdata_ch0(4),
- FF_RX_D_0_5 => rxdata_ch0(5),
- FF_RX_D_0_6 => rxdata_ch0(6),
- FF_RX_D_0_7 => rxdata_ch0(7),
- FF_RX_D_0_8 => rx_k_ch0,
- FF_RX_D_0_9 => rx_disp_err_ch0,
- FF_RX_D_0_10 => rx_cv_err_ch0,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => rx_serdes_rst_ch0_c,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
- FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => tx_pcs_rst_ch_c,
- FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
- FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
- FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
- FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => open,
- HDOUTN1 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_TX_F_CLK_1 => open,
- FF_TX_H_CLK_1 => open,
- FFC_CK_CORE_RX_1 => fpsc_vlo,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => fpsc_vlo,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => open,
- HDOUTN3 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_TX_F_CLK_3 => open,
- FF_TX_H_CLK_3 => open,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
- SCIWDATA7 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA0 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIRDATA7 => open,
- SCIRDATA6 => open,
- SCIRDATA5 => open,
- SCIRDATA4 => open,
- SCIRDATA3 => open,
- SCIRDATA2 => open,
- SCIRDATA1 => open,
- SCIRDATA0 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
--- reset sequence for rx
-
- P1 : PROCESS(fpga_rxrefclk_ch0, rst_n)
- BEGIN
- IF (rst_n = '0') THEN
- refclkdiv2_rx_ch0 <= '0';
- ELSIF (fpga_rxrefclk_ch0'event and fpga_rxrefclk_ch0 = '1') THEN
- refclkdiv2_rx_ch0 <= not refclkdiv2_rx_ch0;
- END IF;
- END PROCESS;
-
-rx_reset_sm_ch0 : rx_reset_sm
---synopsys translate_off
- generic map (count_index => 4)
---synopsys translate_on
-port map (
- refclkdiv2 => refclkdiv2_rx_ch0,
- rst_n => rst_n,
- rx_cdr_lol_ch_s => rx_cdr_lol_ch0_sig,
- rx_los_low_ch_s => rx_los_low_ch0_sig,
- tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
- rx_pcs_rst_ch_c => rx_pcs_rst_ch0_c,
- rx_serdes_rst_ch_c => rx_serdes_rst_ch0_c);
-
-
-
-
-
- P5 : PROCESS(fpga_txrefclk, rst_n)
- BEGIN
- IF (rst_n = '0') THEN
- refclkdiv2_tx_ch <= '0';
- ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
- refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
- END IF;
- END PROCESS;
-
--- reset sequence for tx
-tx_reset_sm_ch : tx_reset_sm
---synopsys translate_off
- generic map (count_index => 4)
---synopsys translate_on
-port map (
- rst_n => rst_n,
- refclkdiv2 => refclkdiv2_tx_ch,
- tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
- rst_qd_c => rst_qd_c,
- tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
- );
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end serdes_gbe_0_intclock_8b_ecp3_arch ;
+++ /dev/null
-Starting process: Module
-
-Starting process:
-
- Module Name: serdes_gbe_0_intclock_8b_ecp3
- Core Name: PCS
- LPC file : serdes_gbe_0_intclock_8b_ecp3.lpc
- Parameter File : serdes_gbe_0_intclock_8b_ecp3.pp
- Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b_ecp3.pp
- Return Value:
-
-
-
- Module PCS has been generated in /home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/. successfully!
-
-/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b_ecp3 -ext readme -out serdes_gbe_0_intclock_8b_ecp3 -tpl serdes_gbe_0_intclock_8b_ecp3.tft serdes_gbe_0_intclock_8b_ecp3.vhd
-
-Done successfully!
-File: serdes_gbe_0_intclock_8b_ecp3.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
-Starting process: Module
-
-Starting process:
-
- Module Name: serdes_gbe_0_intclock_8b
- Core Name: PCS
- LPC file : serdes_gbe_0_intclock_8b.lpc
- Parameter File : serdes_gbe_0_intclock_8b.pp
- Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b.pp
- Return Value:
-
-
-
- Module PCS has been generated in /home/greg/projects/trbnet/gbe2_ecp2m/ipcores_ecp3/serdes_intclk/. successfully!
-
-/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b -ext readme -out serdes_gbe_0_intclock_8b -tpl serdes_gbe_0_intclock_8b.tft serdes_gbe_0_intclock_8b.vhd
-
-Done successfully!
-File: serdes_gbe_0_intclock_8b.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
-rst_n i
-refclkdiv2 i
-tx_pll_lol_qd_s i
-rst_qd_c o
-tx_pcs_rst_ch_c o
+++ /dev/null
- Module Name: serdes_gbe_0_intclock_8b
- Core Name: PCS
- LPC file : serdes_gbe_0_intclock_8b.lpc
- Parameter File : serdes_gbe_0_intclock_8b.pp
- Command line: /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b.pp
- Return Value:
-
-
-
- Module PCS has been generated in /home/greg/projects/trbnet/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50 successfully!
-
-/home/greg/.isplever_lin/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b -ext readme -out serdes_gbe_0_intclock_8b -tpl serdes_gbe_0_intclock_8b.tft serdes_gbe_0_intclock_8b.vhd
-
-Done successfully!
+++ /dev/null
-MODULE serdes_gbe_0_intclock_8b DEFIN serdes_gbe_0_intclock_8b.vhd
- SUBMODULE PCSC
- INSTANCE PCSC_INST
- SUBMODULE VLO
- INSTANCE vlo_inst
+++ /dev/null
-[Device]
-Family=latticeecp2m
-PartType=LFE2M50E
-PartName=LFE2M50E-5F900C
-SpeedGrade=-5
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_gbe_0_intclock_8b
-SourceFormat=Schematic/VHDL
-ParameterFileVersion=1.0
-Date=07/31/2010
-Time=18:08:44
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-Protocol=Quad
-mode=Gigabit Ethernet
-Channel0=SINGLE
-Channel1=DISABLE
-Channel2=DISABLE
-Channel3=DISABLE
-Rate0=None
-Rate1=None
-Rate2=None
-Rate3=None
-TxRefClk=CORE_TXREFCLK
-RxRefClk=CORE_RXREFCLK
-ClkRate=1.25
-ClkMult=10X
-CalClkRate=125.0
-DataWidth=8
-FPGAClkRate=125.0
-TxRefClkCM=REFCLK
-RxRefClk0CM=REFCLK
-RxRefClk1CM=REFCLK
-RxRefClk2CM=REFCLK
-RxRefClk3CM=REFCLK
-ClkRateH=0.625
-ClkMultH=10XH
-CalClkRateH=125.0
-DataWidthH=8
-FPGAClkRateH=62.5
-VCh0=0
-VCh1=0
-VCh2=0
-VCh3=0
-PreCh0=DISABLE
-PreCh1=DISABLE
-PreCh2=DISABLE
-PreCh3=DISABLE
-TxCh0=50
-TxCh1=50
-TxCh2=50
-TxCh3=50
-EqCh0=DISABLE
-EqCh1=DISABLE
-EqCh2=DISABLE
-EqCh3=DISABLE
-RxTermCh0=50
-RxTermCh1=50
-RxTermCh2=50
-RxTermCh3=50
-RxCoupCh0=AC
-RxCoupCh1=AC
-RxCoupCh2=AC
-RxCoupCh3=AC
-Loss=0
-CDRLoss=0
-TxTerm=50
-TxCoup=AC
-TxPllLoss=0
-TxInvCh0=NORMAL
-TxInvCh1=NORMAL
-TxInvCh2=NORMAL
-TxInvCh3=NORMAL
-RxInvCh0=NORMAL
-RxInvCh1=NORMAL
-RxInvCh2=NORMAL
-RxInvCh3=NORMAL
-RxModeCh0=NORMAL
-RxModeCh1=NORMAL
-RxModeCh2=NORMAL
-RxModeCh3=NORMAL
-Plus=1100000101
-Minus=0011111010
-Mask=1111111111
-Align=AUTO
-CTCCh0=NORMAL
-CTCCh1=NORMAL
-CTCCh2=NORMAL
-CTCCh3=NORMAL
-CC_MATCH1=0000000000
-CC_MATCH2=0000000000
-CC_MATCH3=0110111100
-CC_MATCH4=0001010000
-MinIPG=3
-High=9
-Low=7
-CC_MATCH_MODE=MATCH_3_4
-RxDataCh0=FALSE
-RxDataCh1=FALSE
-RxDataCh2=FALSE
-RxDataCh3=FALSE
-AlignerCh0=FALSE
-AlignerCh1=FALSE
-AlignerCh2=FALSE
-AlignerCh3=FALSE
-DetectCh0=FALSE
-DetectCh1=FALSE
-DetectCh2=FALSE
-DetectCh3=FALSE
-ELSMCh0=FALSE
-ELSMCh1=FALSE
-ELSMCh2=FALSE
-ELSMCh3=FALSE
-_teidleCh0=FALSE
-_teidleCh1=FALSE
-_teidleCh2=FALSE
-_teidleCh3=FALSE
-Ports0=FALSE
-rdoPorts0=Serial Loopback
-Ports1=FALSE
-Ports2=FALSE
-Ports3=FALSE
-Ports3_1=FALSE
-Ports4=FALSE
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
+++ /dev/null
-core_txrefclk i
-core_rxrefclk i
-hdinp0 i
-hdinn0 i
-hdoutp0 o
-hdoutn0 o
-ff_rxiclk_ch0 i
-ff_txiclk_ch0 i
-ff_ebrd_clk_0 i
-ff_txdata_ch0[7] i
-ff_txdata_ch0[6] i
-ff_txdata_ch0[5] i
-ff_txdata_ch0[4] i
-ff_txdata_ch0[3] i
-ff_txdata_ch0[2] i
-ff_txdata_ch0[1] i
-ff_txdata_ch0[0] i
-ff_rxdata_ch0[7] o
-ff_rxdata_ch0[6] o
-ff_rxdata_ch0[5] o
-ff_rxdata_ch0[4] o
-ff_rxdata_ch0[3] o
-ff_rxdata_ch0[2] o
-ff_rxdata_ch0[1] o
-ff_rxdata_ch0[0] o
-ff_tx_k_cntrl_ch0 i
-ff_rx_k_cntrl_ch0 o
-ff_rxfullclk_ch0 o
-ff_xmit_ch0 i
-ff_correct_disp_ch0 i
-ff_disp_err_ch0 o
-ff_cv_ch0 o
-ff_rx_even_ch0 o
-ffc_rrst_ch0 i
-ffc_lane_tx_rst_ch0 i
-ffc_lane_rx_rst_ch0 i
-ffc_txpwdnb_ch0 i
-ffc_rxpwdnb_ch0 i
-ffs_rlos_lo_ch0 o
-ffs_ls_sync_status_ch0 o
-ffs_rlol_ch0 o
-oob_out_ch0 o
-ffc_macro_rst i
-ffc_quad_rst i
-ffc_trst i
-ff_txfullclk o
-ff_txhalfclk o
-ffs_plol o
+++ /dev/null
-#define _device_name "LFE2M50E"
-#define _protocol_mode "Quad Based Protocol Mode"
-#define _protocol "GIGE"
-#define _ch0_mode "SINGLE"
-#define _ch1_mode "DISABLE"
-#define _ch2_mode "DISABLE"
-#define _ch3_mode "DISABLE"
-#define _pll_txsrc "CORE_TXREFCLK"
-#define _pll_rxsrc "CORE_RXREFCLK"
-#define _datarange "MED"
-#define _refclk_mult "10X"
-#define _refclk_rate 125.0
-#define _data_width "8"
-#define _fpgaintclk_rate 125.0
-#define _ch0_tdrv_amp "0"
-#define _ch1_tdrv_amp "0"
-#define _ch2_tdrv_amp "0"
-#define _ch3_tdrv_amp "0"
-#define _ch0_tx_pre "DISABLE"
-#define _ch1_tx_pre "DISABLE"
-#define _ch2_tx_pre "DISABLE"
-#define _ch3_tx_pre "DISABLE"
-#define _ch0_rterm_tx "50"
-#define _ch1_rterm_tx "50"
-#define _ch2_rterm_tx "50"
-#define _ch3_rterm_tx "50"
-#define _ch0_rx_eq "DISABLE"
-#define _ch1_rx_eq "DISABLE"
-#define _ch2_rx_eq "DISABLE"
-#define _ch3_rx_eq "DISABLE"
-#define _ch0_rterm_rx "50"
-#define _ch1_rterm_rx "50"
-#define _ch2_rterm_rx "50"
-#define _ch3_rterm_rx "50"
-#define _ch0_rx_dcc "AC"
-#define _ch1_rx_dcc "AC"
-#define _ch2_rx_dcc "AC"
-#define _ch3_rx_dcc "AC"
-#define _los_threshold "0"
-#define _pll_term "50"
-#define _pll_dcc "AC"
-#define _pll_lol_set "0"
-#define _ch0_tx_sb "NORMAL"
-#define _ch1_tx_sb "NORMAL"
-#define _ch2_tx_sb "NORMAL"
-#define _ch3_tx_sb "NORMAL"
-#define _ch0_rx_sb "NORMAL"
-#define _ch1_rx_sb "NORMAL"
-#define _ch2_rx_sb "NORMAL"
-#define _ch3_rx_sb "NORMAL"
-#define _ch0_8b10b "NORMAL"
-#define _ch1_8b10b "NORMAL"
-#define _ch2_8b10b "NORMAL"
-#define _ch3_8b10b "NORMAL"
-#define _comma_a "1100000101"
-#define _comma_b "0011111010"
-#define _comma_m "1111111111"
-#define _comma_align "AUTO"
-#define _ch0_ctc_byp "NORMAL"
-#define _ch1_ctc_byp "NORMAL"
-#define _ch2_ctc_byp "NORMAL"
-#define _ch3_ctc_byp "NORMAL"
-#define _cc_match1 "0000000000"
-#define _cc_match2 "0000000000"
-#define _cc_match3 "0110111100"
-#define _cc_match4 "0001010000"
-#define _cc_match_mode "MATCH_3_4"
-#define _cc_min_ipg "3"
-#define _cchmark "9"
-#define _cclmark "7"
-#define _ch0_ird "FALSE"
-#define _ch1_ird "FALSE"
-#define _ch2_ird "FALSE"
-#define _ch3_ird "FALSE"
-#define _ch0_elsm "FALSE"
-#define _ch1_elsm "FALSE"
-#define _ch2_elsm "FALSE"
-#define _ch3_elsm "FALSE"
-#define _ch0_teidle "FALSE"
-#define _ch1_teidle "FALSE"
-#define _ch2_teidle "FALSE"
-#define _ch3_teidle "FALSE"
-#define _loopback "FALSE"
-#define _lbtype "Serial Loopback"
-#define _refck2core "FALSE"
-#define _pllqclkports "FALSE"
-#define _sci_ports "FALSE"
-#define _sci_int_port "FALSE"
-#define _errsports "FALSE"
-#define _rst_gen "DISABLED"
-#define _rx_los_port0 "Internal"
-#define _rx_los_port1 "Internal"
-#define _rx_los_port2 "Internal"
-#define _rx_los_port3 "Internal"
-
-#define _ch0_rx_ficlk_rate 125.0
-#define _ch1_rx_ficlk_rate 125.0
-#define _ch2_rx_ficlk_rate 125.0
-#define _ch3_rx_ficlk_rate 125.0
-
-#define _ch0_rx_hiclk_rate 62.5
-#define _ch1_rx_hiclk_rate 62.5
-#define _ch2_rx_hiclk_rate 62.5
-#define _ch3_rx_hiclk_rate 62.5
-
-#define _ch0_rx_qiclk_rate 31.25
-#define _ch1_rx_qiclk_rate 31.25
-#define _ch2_rx_qiclk_rate 31.25
-#define _ch3_rx_qiclk_rate 31.25
-
-#define _tx_ficlk_rate 125.0
-#define _tx_hiclk_rate 62.5
-#define _tx_qiclk_rate 31.25
-
-#define _circuit_name serdes_gbe_0_intclock_8b
-#define _lang vhdl
-
-#include <pcs/PCSC.vhd>
-#include <pcs/pcsc_cfg.txt>
+++ /dev/null
-
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:51
- TITLE: Lattice Semiconductor Corporation
- MODULE: serdes_gbe_0_intclock_8b
- DESIGN: serdes_gbe_0_intclock_8b
- FILENAME: serdes_gbe_0_intclock_8b.readme
- PROJECT: Unknown
- VERSION: 2.0
- This file is auto generated by the ispLEVER
-
-
-NOTE: This readme file has been provided to instantiate the interface
-netlist. Since this template contains synthesis attributes for precision that
-are crucial to the design flow, we recommend that you use this
-template in your FPGA design.
-entity chip is
-port (
-
--- Add your FPGA design top level I/Os here
-
-
--- ASIC side pins for PCSA. These pins must exist for the
--- PCS core.
- refclkp : in std_logic;
- refclkn : in std_logic;
- hdinp0 : in std_logic;
- hdinn0 : in std_logic;
- hdinp1 : in std_logic;
- hdinn1 : in std_logic;
- hdinp2 : in std_logic;
- hdinn2 : in std_logic;
- hdinp3 : in std_logic;
- hdinn3 : in std_logic;
-
- hdoutp0 : out std_logic;
- hdoutn0 : out std_logic;
- hdoutp1 : out std_logic;
- hdoutn1 : out std_logic;
- hdoutp2 : out std_logic;
- hdoutn2 : out std_logic;
- hdoutp3 : out std_logic;
- hdoutn3 : out std_logic;
-
-
-);
-end chip;
-
-architecture chip_arch of chip is
-
--- This defines all the high-speed ports. You may have to remove
--- some of them depending on your design.
-attribute nopad : string;
-attribute nopad of
- refclkp, refclkn,
- hdinp0, hdinn0, hdinp1, hdinn1,
- hdinp2, hdinn2, hdinp3, hdinn3,
- hdoutp0, hdoutn0, hdoutp1, hdoutn1,
- hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";
-
- COMPONENT serdes_gbe_0_intclock_8b
- PORT(
- core_txrefclk : IN std_logic;
- core_rxrefclk : IN std_logic;
- hdinp0 : IN std_logic;
- hdinn0 : IN std_logic;
- ff_rxiclk_ch0 : IN std_logic;
- ff_txiclk_ch0 : IN std_logic;
- ff_ebrd_clk_0 : IN std_logic;
- ff_txdata_ch0 : IN std_logic_vector(7 downto 0);
- ff_tx_k_cntrl_ch0 : IN std_logic;
- ff_xmit_ch0 : IN std_logic;
- ff_correct_disp_ch0 : IN std_logic;
- ffc_rrst_ch0 : IN std_logic;
- ffc_lane_tx_rst_ch0 : IN std_logic;
- ffc_lane_rx_rst_ch0 : IN std_logic;
- ffc_txpwdnb_ch0 : IN std_logic;
- ffc_rxpwdnb_ch0 : IN std_logic;
- ffc_macro_rst : IN std_logic;
- ffc_quad_rst : IN std_logic;
- ffc_trst : IN std_logic;
- hdoutp0 : OUT std_logic;
- hdoutn0 : OUT std_logic;
- ff_rxdata_ch0 : OUT std_logic_vector(7 downto 0);
- ff_rx_k_cntrl_ch0 : OUT std_logic;
- ff_rxfullclk_ch0 : OUT std_logic;
- ff_disp_err_ch0 : OUT std_logic;
- ff_cv_ch0 : OUT std_logic;
- ff_rx_even_ch0 : OUT std_logic;
- ffs_rlos_lo_ch0 : OUT std_logic;
- ffs_ls_sync_status_ch0 : OUT std_logic;
- ffs_rlol_ch0 : OUT std_logic;
- oob_out_ch0 : OUT std_logic;
- ff_txfullclk : OUT std_logic;
- ff_txhalfclk : OUT std_logic;
- ffs_plol : OUT std_logic
- );
- END COMPONENT;
-
-
-
- uut: serdes_gbe_0_intclock_8b PORT MAP(
- core_txrefclk => core_txrefclk,
- core_rxrefclk => core_rxrefclk,
- hdinp0 => hdinp0,
- hdinn0 => hdinn0,
- hdoutp0 => hdoutp0,
- hdoutn0 => hdoutn0,
- ff_rxiclk_ch0 => ff_rxiclk_ch0,
- ff_txiclk_ch0 => ff_txiclk_ch0,
- ff_ebrd_clk_0 => ff_ebrd_clk_0,
- ff_txdata_ch0 => ff_txdata_ch0,
- ff_rxdata_ch0 => ff_rxdata_ch0,
- ff_tx_k_cntrl_ch0 => ff_tx_k_cntrl_ch0,
- ff_rx_k_cntrl_ch0 => ff_rx_k_cntrl_ch0,
- ff_rxfullclk_ch0 => ff_rxfullclk_ch0,
- ff_xmit_ch0 => ff_xmit_ch0,
- ff_correct_disp_ch0 => ff_correct_disp_ch0,
- ff_disp_err_ch0 => ff_disp_err_ch0,
- ff_cv_ch0 => ff_cv_ch0,
- ff_rx_even_ch0 => ff_rx_even_ch0,
- ffc_rrst_ch0 => ffc_rrst_ch0,
- ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst_ch0,
- ffc_lane_rx_rst_ch0 => ffc_lane_rx_rst_ch0,
- ffc_txpwdnb_ch0 => ffc_txpwdnb_ch0,
- ffc_rxpwdnb_ch0 => ffc_rxpwdnb_ch0,
- ffs_rlos_lo_ch0 => ffs_rlos_lo_ch0,
- ffs_ls_sync_status_ch0 => ffs_ls_sync_status_ch0,
- ffs_rlol_ch0 => ffs_rlol_ch0,
- oob_out_ch0 => oob_out_ch0,
- ffc_macro_rst => ffc_macro_rst,
- ffc_quad_rst => ffc_quad_rst,
- ffc_trst => ffc_trst,
- ff_txfullclk => ff_txfullclk,
- ff_txhalfclk => ff_txhalfclk,
- ffs_plol => ffs_plol
- );
-
-
+++ /dev/null
-@set suppresnewline=on@
-
-@comment --------------------------------------------------------------------- @
-@comment Template-drive TFI generator @
-@comment Template for TFI generation. @
-@comment --------------------------------------------------------------------- @
-
-@set suppresnewline=off@
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:51
- TITLE: %title%
- MODULE: %module%
- DESIGN: %module%
- FILENAME: %filename%
- PROJECT: %project%
- VERSION: %ver%
- This file is auto generated by the ispLEVER
-@set suppresnewline=on@
-
-@cr@
-@cr@
-
-@set sigdelim=@
-
-NOTE: This readme file has been provided to instantiate the interface@cr@
-netlist. Since this template contains synthesis attributes for precision that@cr@
-are crucial to the design flow, we recommend that you use this@cr@
-template in your FPGA design.@cr@
-entity chip is@cr@
-port (@cr@
-@cr@
--- Add your FPGA design top level I/Os here@cr@
-@cr@
-@cr@
--- ASIC side pins for PCSA. These pins must exist for the@cr@
--- PCS core.@cr@
- refclkp : in std_logic;@cr@
- refclkn : in std_logic;@cr@
- hdinp0 : in std_logic;@cr@
- hdinn0 : in std_logic;@cr@
- hdinp1 : in std_logic;@cr@
- hdinn1 : in std_logic;@cr@
- hdinp2 : in std_logic;@cr@
- hdinn2 : in std_logic;@cr@
- hdinp3 : in std_logic;@cr@
- hdinn3 : in std_logic;@cr@
-@cr@
- hdoutp0 : out std_logic;@cr@
- hdoutn0 : out std_logic;@cr@
- hdoutp1 : out std_logic;@cr@
- hdoutn1 : out std_logic;@cr@
- hdoutp2 : out std_logic;@cr@
- hdoutn2 : out std_logic;@cr@
- hdoutp3 : out std_logic;@cr@
- hdoutn3 : out std_logic;@cr@
-@cr@
-@cr@
-);@cr@
-end chip;@cr@
-@cr@
-architecture chip_arch of chip is@cr@
-@cr@
--- This defines all the high-speed ports. You may have to remove@cr@
--- some of them depending on your design.@cr@
-attribute nopad : string;@cr@
-attribute nopad of@cr@
- refclkp, refclkn,@cr@
- hdinp0, hdinn0, hdinp1, hdinn1,@cr@
- hdinp2, hdinn2, hdinp3, hdinn3,@cr@
- hdoutp0, hdoutn0, hdoutp1, hdoutn1,@cr@
- hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";@cr@
-
-@cr@
-@tab@COMPONENT %module%
-@set sigdelim=@
-@cr@@tab@PORT(
-@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
-@ifhas oport=*@ @comment if the design has any output ports... @
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
- @set sigdelim=;@
- @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
-@endif@
-@ifnhas oport=*@ @comment we need an "else in this language! @
- @set sigdelim=;@
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
-@endif@
-@cr@@tab@@tab@);@cr@
-@tab@END COMPONENT;@cr@@cr@
-@comment Now do a signal declaration for each port @
-
-@cr@@cr@
-@comment do the component instantiation @
-@set sigdelim=,@
-@tab@uut: %module% PORT MAP(
-@iterate@%port%
-@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
-@cr@@tab@);@cr@@cr@
-@set suppresnewline=off@
+++ /dev/null
-
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSC quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSC quad to the final design requirements.
-
-DEVICE_NAME "LFE2M50E"
-PROTOCOL "GIGE"
-CH0_MODE "SINGLE"
-CH1_MODE "DISABLE"
-CH2_MODE "DISABLE"
-CH3_MODE "DISABLE"
-PLL_SRC "CORE_TXREFCLK"
-DATARANGE "MED"
-CH0_CDR_SRC "CORE_RXREFCLK"
-CH0_DATA_WIDTH "8"
-CH0_REFCK_MULT "10X"
-#REFCLK_RATE 125.0
-#FPGAINTCLK_RATE 125.0
-CH0_TDRV_AMP "0"
-CH0_TX_PRE "DISABLE"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLE"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "AC"
-LOS_THRESHOLD "0"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "NORMAL"
-CH0_RX_SB "NORMAL"
-CH0_8B10B "NORMAL"
-COMMA_A "1100000101"
-COMMA_B "0011111010"
-COMMA_M "1111111111"
-CH0_COMMA_ALIGN "AUTO"
-CH0_CTC_BYP "BYPASS"
-CC_MATCH1 "0000000000"
-CC_MATCH2 "0000000000"
-CC_MATCH3 "0110111100"
-CC_MATCH4 "0001010000"
-CC_MATCH_MODE "MATCH_3_4"
-CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-OS_REFCK2CORE "0"
-OS_PLLQCLKPORTS "0"
-OS_INT_ALL "0"
-
+++ /dev/null
-
-
---synopsys translate_off
-
-library pcsc_work;
-use pcsc_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSC is
-GENERIC(
- CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-
-end PCSC;
-
-architecture PCSC_arch of PCSC is
-
-component PCSC_sim
-GENERIC(
- CONFIG_FILE : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-end component;
-
-begin
-
-PCSC_sim_inst : PCSC_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE)
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
-
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX => FFC_CK_CORE_RX,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,
- FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,
- FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,
- FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,
- FF_TX_F_CLK => FF_TX_F_CLK,
- FF_TX_H_CLK => FF_TX_H_CLK,
- FF_TX_Q_CLK => FF_TX_Q_CLK,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- OOB_OUT_0 => OOB_OUT_0,
- OOB_OUT_1 => OOB_OUT_1,
- OOB_OUT_2 => OOB_OUT_2,
- OOB_OUT_3 => OOB_OUT_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7
- );
-
-end PCSC_arch;
-
---synopsys translate_on
-
---synopsys translate_off
-library ECP2;
-use ECP2.components.all;
---synopsys translate_on
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_gbe_0_intclock_8b is
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt");
- port (
- core_txrefclk : in std_logic;
- core_rxrefclk : in std_logic;
- hdinp0, hdinn0 : in std_logic;
- hdoutp0, hdoutn0 : out std_logic;
- ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;
- ff_txdata_ch0 : in std_logic_vector (7 downto 0);
- ff_rxdata_ch0 : out std_logic_vector (7 downto 0);
- ff_tx_k_cntrl_ch0 : in std_logic;
- ff_rx_k_cntrl_ch0 : out std_logic;
- ff_rxfullclk_ch0 : out std_logic;
- ff_xmit_ch0 : in std_logic;
- ff_correct_disp_ch0 : in std_logic;
- ff_disp_err_ch0, ff_cv_ch0 : out std_logic;
- ff_rx_even_ch0 : out std_logic;
- ffc_rrst_ch0 : in std_logic;
- ffc_lane_tx_rst_ch0 : in std_logic;
- ffc_lane_rx_rst_ch0 : in std_logic;
- ffc_txpwdnb_ch0 : in std_logic;
- ffc_rxpwdnb_ch0 : in std_logic;
- ffs_rlos_lo_ch0 : out std_logic;
- ffs_ls_sync_status_ch0 : out std_logic;
- ffs_rlol_ch0 : out std_logic;
- oob_out_ch0 : out std_logic;
- ffc_macro_rst : in std_logic;
- ffc_quad_rst : in std_logic;
- ffc_trst : in std_logic;
- ff_txfullclk : out std_logic;
- ff_txhalfclk : out std_logic;
- ffs_plol : out std_logic);
-
-end serdes_gbe_0_intclock_8b;
-
-architecture serdes_gbe_0_intclock_8b_arch of serdes_gbe_0_intclock_8b is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-component PCSC
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-end component;
- attribute IS_ASB: string;
- attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSC_INST : label is "62.5";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSC_INST : label is "62.5";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSC_INST : label is "62.5";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSC_INST : label is "62.5";
- attribute FREQUENCY_PIN_FF_TX_F_CLK: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_TX_H_CLK: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK of PCSC_INST : label is "62.5";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal fpsc_vlo : std_logic := '0';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-
--- pcs_quad instance
-PCSC_INST : PCSC
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE)
---synopsys translate_on
-port map (
- FFC_CK_CORE_TX => core_txrefclk,
- FFC_CK_CORE_RX => core_rxrefclk,
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
- HDINP0 => hdinp0,
- HDINN0 => hdinn0,
- HDOUTP0 => hdoutp0,
- HDOUTN0 => hdoutn0,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => ff_rxiclk_ch0,
- FF_TXI_CLK_0 => ff_txiclk_ch0,
- FF_EBRD_CLK_0 => ff_ebrd_clk_0,
- FF_RX_F_CLK_0 => ff_rxfullclk_ch0,
- FF_RX_H_CLK_0 => open,
- FF_RX_Q_CLK_0 => open,
- FF_TX_D_0_0 => ff_txdata_ch0(0),
- FF_TX_D_0_1 => ff_txdata_ch0(1),
- FF_TX_D_0_2 => ff_txdata_ch0(2),
- FF_TX_D_0_3 => ff_txdata_ch0(3),
- FF_TX_D_0_4 => ff_txdata_ch0(4),
- FF_TX_D_0_5 => ff_txdata_ch0(5),
- FF_TX_D_0_6 => ff_txdata_ch0(6),
- FF_TX_D_0_7 => ff_txdata_ch0(7),
- FF_TX_D_0_8 => ff_tx_k_cntrl_ch0,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => ff_xmit_ch0,
- FF_TX_D_0_11 => ff_correct_disp_ch0,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => ff_rxdata_ch0(0),
- FF_RX_D_0_1 => ff_rxdata_ch0(1),
- FF_RX_D_0_2 => ff_rxdata_ch0(2),
- FF_RX_D_0_3 => ff_rxdata_ch0(3),
- FF_RX_D_0_4 => ff_rxdata_ch0(4),
- FF_RX_D_0_5 => ff_rxdata_ch0(5),
- FF_RX_D_0_6 => ff_rxdata_ch0(6),
- FF_RX_D_0_7 => ff_rxdata_ch0(7),
- FF_RX_D_0_8 => ff_rx_k_cntrl_ch0,
- FF_RX_D_0_9 => ff_disp_err_ch0,
- FF_RX_D_0_10 => ff_cv_ch0,
- FF_RX_D_0_11 => ff_rx_even_ch0,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
- FFC_RRST_0 => ffc_rrst_ch0,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFS_PCIE_DONE_0 => open,
- FFS_PCIE_CON_0 => open,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0,
- FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0,
- FFC_TXPWDNB_0 => ffc_txpwdnb_ch0,
- FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0,
- FFS_RLOS_LO_0 => ffs_rlos_lo_ch0,
- FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0,
- FFS_CC_UNDERRUN_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- FFS_RLOL_0 => ffs_rlol_ch0,
- OOB_OUT_0 => oob_out_ch0,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- HDOUTP1 => open,
- HDOUTN1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_RX_Q_CLK_1 => open,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- OOB_OUT_1 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- HDOUTP2 => open,
- HDOUTN2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_RX_Q_CLK_2 => open,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- OOB_OUT_2 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- HDOUTP3 => open,
- HDOUTN3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_RX_Q_CLK_3 => open,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- OOB_OUT_3 => open,
- SCIWDATA0 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA7 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIRDATA0 => open,
- SCIRDATA1 => open,
- SCIRDATA2 => open,
- SCIRDATA3 => open,
- SCIRDATA4 => open,
- SCIRDATA5 => open,
- SCIRDATA6 => open,
- SCIRDATA7 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_MACRO_RST => ffc_macro_rst,
- FFC_QUAD_RST => ffc_quad_rst,
- FFC_TRST => ffc_trst,
- FF_TX_F_CLK => ff_txfullclk,
- FF_TX_H_CLK => ff_txhalfclk,
- FF_TX_Q_CLK => open,
- REFCK2CORE => open,
- CIN0 => cin(0),
- CIN1 => cin(1),
- CIN2 => cin(2),
- CIN3 => cin(3),
- CIN4 => cin(4),
- CIN5 => cin(5),
- CIN6 => cin(6),
- CIN7 => cin(7),
- CIN8 => cin(8),
- CIN9 => cin(9),
- CIN10 => cin(10),
- CIN11 => cin(11),
- COUT0 => cout(0),
- COUT1 => cout(1),
- COUT2 => cout(2),
- COUT3 => cout(3),
- COUT4 => cout(4),
- COUT5 => cout(5),
- COUT6 => cout(6),
- COUT7 => cout(7),
- COUT8 => cout(8),
- COUT9 => cout(9),
- COUT10 => cout(10),
- COUT11 => cout(11),
- COUT12 => cout(12),
- COUT13 => cout(13),
- COUT14 => cout(14),
- COUT15 => cout(15),
- COUT16 => cout(16),
- COUT17 => cout(17),
- COUT18 => cout(18),
- COUT19 => cout(19),
- FFS_PLOL => ffs_plol);
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-
-end serdes_gbe_0_intclock_8b_arch ;
+++ /dev/null
-Starting process:
-
- Module Name: serdes_gbe_0_intclock_8b
- Core Name: PCS
- LPC file : serdes_gbe_0_intclock_8b.lpc
- Parameter File : serdes_gbe_0_intclock_8b.pp
- Command line: /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b.pp
- Return Value:
-
-
-
- Module PCS has been generated in /home/greg/projects/trbnet/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50 successfully!
-
-/home/greg/.isplever_lin/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b -ext readme -out serdes_gbe_0_intclock_8b -tpl serdes_gbe_0_intclock_8b.tft serdes_gbe_0_intclock_8b.vhd
-
-Done successfully!
-File: serdes_gbe_0_intclock_8b.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
-//**************************************************************************\r
-// *************************************************************************\r
-// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
-// * PROPRIETARY NOTE *\r
-// * *\r
-// * This software contains information confidential and proprietary *\r
-// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
-// * in whole or in part, or transferred to other documents, or disclosed *\r
-// * to third parties, or used for any purpose other than that for which *\r
-// * it was obtained, without the prior written consent of Lattice *\r
-// * Semiconductor Corporation. All rights reserved. *\r
-// * *\r
-// *************************************************************************\r
-//**************************************************************************\r
-\r
-`timescale 1ns/100ps\r
-\r
-module rate_resolution (\r
- gbe_mode,\r
- sgmii_mode,\r
- an_enable,\r
- advertised_rate,\r
- link_partner_rate,\r
- non_an_rate,\r
-\r
- operational_rate\r
-);\r
-\r
-input gbe_mode;\r
-input sgmii_mode;\r
-input an_enable;\r
-input [1:0] advertised_rate; // 00=10Mbps 01=100Mbps 10=1Gbps\r
-input [1:0] link_partner_rate;\r
-input [1:0] non_an_rate;\r
-\r
-output [1:0] operational_rate;\r
-reg [1:0] operational_rate;\r
-\r
-\r
-\r
-always @(gbe_mode or sgmii_mode or an_enable or advertised_rate or link_partner_rate or non_an_rate) begin\r
- if (gbe_mode) begin\r
- operational_rate <= 2'b10; // 1Gbps\r
- end\r
- else begin\r
- if (an_enable) begin\r
- if (sgmii_mode) begin\r
- // PHY Mode\r
- operational_rate <= advertised_rate;\r
- end\r
- else begin\r
- // MAC Mode\r
- operational_rate <= link_partner_rate;\r
- end\r
- end\r
- else begin\r
- // If auto-negotiation disabled, then this becomes active rate\r
- operational_rate <= non_an_rate;\r
- end\r
- end\r
-end\r
-\r
-\r
-\r
-endmodule\r
-\r
+++ /dev/null
-//**************************************************************************\r
-// *************************************************************************\r
-// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
-// * PROPRIETARY NOTE *\r
-// * *\r
-// * This software contains information confidential and proprietary *\r
-// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
-// * in whole or in part, or transferred to other documents, or disclosed *\r
-// * to third parties, or used for any purpose other than that for which *\r
-// * it was obtained, without the prior written consent of Lattice *\r
-// * Semiconductor Corporation. All rights reserved. *\r
-// * *\r
-// *************************************************************************\r
-//**************************************************************************\r
-\r
-`timescale 1ns/100ps\r
-\r
-module register_interface_hb (\r
-\r
- // Control Signals\r
- rst_n,\r
- hclk,\r
- gbe_mode,\r
- sgmii_mode,\r
-\r
- // Host Bus\r
- hcs_n,\r
- hwrite_n,\r
- haddr,\r
- hdatain,\r
-\r
- hdataout,\r
- hready_n,\r
-\r
- // Register Inputs\r
- mr_an_enable,\r
- mr_restart_an,\r
- mr_adv_ability,\r
-\r
- // Register Outputs\r
- mr_main_reset,\r
- mr_an_complete,\r
- mr_page_rx,\r
- mr_lp_adv_ability\r
- );\r
-\r
-\r
-input rst_n ;\r
-input hclk ;\r
-input gbe_mode ;\r
-input sgmii_mode ;\r
-\r
-input hcs_n;\r
-input hwrite_n;\r
-input [3:0] haddr;\r
-input [7:0] hdatain;\r
-\r
-output [7:0] hdataout;\r
-output hready_n;\r
-\r
-input mr_an_complete;\r
-input mr_page_rx;\r
-input [15:0] mr_lp_adv_ability;\r
-\r
-output mr_an_enable;\r
-output mr_restart_an;\r
-output [15:0] mr_adv_ability;\r
-output mr_main_reset;\r
-\r
-regs_hb regs (\r
- .rst_n (rst_n),\r
- .hclk (hclk),\r
-\r
- .gbe_mode (gbe_mode),\r
- .sgmii_mode (sgmii_mode),\r
-\r
- .hcs_n (hcs_n),\r
- .hwrite_n (hwrite_n),\r
- .haddr (haddr),\r
- .hdatain (hdatain),\r
-\r
- .hdataout (hdataout),\r
- .hready_n (hready_n),\r
-\r
- .mr_an_complete (mr_an_complete),\r
- .mr_page_rx (mr_page_rx),\r
- .mr_lp_adv_ability (mr_lp_adv_ability),\r
-\r
- .mr_main_reset (mr_main_reset),\r
- .mr_an_enable (mr_an_enable),\r
- .mr_restart_an (mr_restart_an),\r
- .mr_adv_ability (mr_adv_ability)\r
-);\r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-module register_0_hb (\r
- rst_n,\r
- clk, \r
- cs_0,\r
- cs_1,\r
- write,\r
- ready,\r
- data_in,\r
-\r
- data_out,\r
- mr_main_reset,\r
- mr_an_enable,\r
- mr_restart_an\r
-);\r
-\r
-input rst_n;\r
-input clk;\r
-input cs_0;\r
-input cs_1;\r
-input write;\r
-input ready;\r
-input [15:0] data_in;\r
-\r
-output [15:0] data_out;\r
-output mr_main_reset; // bit D15 // R/W // Self Clearing\r
-output mr_an_enable; // bit D12 // R/W\r
-output mr_restart_an; // bit D09 // R/W // Self Clearing\r
-\r
-reg [15:0] data_out;\r
-reg mr_main_reset;\r
-reg mr_an_enable;\r
-reg mr_restart_an;\r
-reg m_m_r;\r
-reg m_r_a;\r
-\r
-\r
-// Write Operations\r
-\r
- // Low Portion of Register[D7:D0] has no\r
- // implemented bits. Therefore, no write\r
- // operations here.\r
-\r
- // High Portion of Register[D15:D8]\r
- always @(posedge clk or negedge rst_n) begin\r
- if (rst_n == 1'b0) begin\r
- mr_main_reset <= 0; // default value\r
- mr_an_enable <= 1; // default value\r
- mr_restart_an <= 0; // default value\r
- m_m_r <= 0;\r
- m_r_a <= 0;\r
- end\r
- else begin\r
-\r
- // Do the Writes\r
- if (cs_1 && ready && write) begin\r
- mr_main_reset <= data_in[15];\r
- mr_an_enable <= data_in[12];\r
- mr_restart_an <= data_in[9];\r
- end\r
-\r
- // Delay the Self Clearing Register Bits\r
- m_m_r <= mr_main_reset;\r
- m_r_a <= mr_restart_an;\r
-\r
- // Do the Self Clearing\r
- if (m_m_r)\r
- mr_main_reset <= 0;\r
-\r
- if (m_r_a)\r
- mr_restart_an <= 0;\r
- end\r
- end\r
-\r
-\r
-\r
-\r
-\r
-// Read Operations\r
- always @(*) begin\r
- data_out[7:0] = 8'b00000000;\r
- data_out[15] = mr_main_reset;\r
- data_out[14] = 0;\r
- data_out[13] = 0;\r
- data_out[12] = mr_an_enable;\r
- data_out[11] = 0;\r
- data_out[10] = 0;\r
- data_out[9] = mr_restart_an;\r
- data_out[8] = 0;\r
- end\r
-endmodule\r
-\r
-module register_1_hb (\r
- rst_n,\r
- cs_0,\r
- cs_1,\r
- mr_an_complete,\r
-\r
- data_out\r
-);\r
-\r
-input rst_n;\r
-input cs_0;\r
-input cs_1;\r
-input mr_an_complete; // bit D5 // Read-Only\r
-\r
-output [15:0] data_out;\r
-\r
-reg [15:0] data_out;\r
-\r
-\r
-// Read Operations\r
-\r
- always @(*) begin\r
- data_out[7] <= 0;\r
- data_out[6] <= 0;\r
- data_out[5] <= mr_an_complete;\r
- data_out[4] <= 0;\r
- data_out[3] <= 0;\r
- data_out[2] <= 0;\r
- data_out[1] <= 0;\r
- data_out[0] <= 0;\r
- data_out[15:8] <= 8'b00000000;\r
- end\r
-endmodule\r
-\r
-module register_4_hb (\r
- rst_n,\r
- clk, \r
- gbe_mode,\r
- sgmii_mode,\r
- cs_0,\r
- cs_1,\r
- write,\r
- ready,\r
- data_in,\r
-\r
- data_out,\r
- mr_adv_ability\r
-);\r
-\r
-parameter [15:0] initval_gbe = 16'h0020;\r
-parameter [15:0] initval_phy = 16'hd801;\r
-parameter [15:0] initval_mac = 16'h4001;\r
-\r
-input rst_n;\r
-input clk;\r
-input gbe_mode;\r
-input sgmii_mode;\r
-input cs_0;\r
-input cs_1;\r
-input write;\r
-input ready;\r
-input [15:0] data_in;\r
-\r
-output [15:0] data_out;\r
-output [15:0] mr_adv_ability; // When sgmii_mode == 1 == PHY\r
- // all bits D15-D0 are R/W,\r
- ///////////////////////////////////\r
- // D15 = Link Status (1=up, 0=down)\r
- // D14 = Can be written but has no effect\r
- // on autonegotiation. Instead\r
- // the autonegotiation state machine\r
- // controls the utilization of this bit.\r
- // D12 = Duplex Mode (1=full, 0=half)\r
- // D11:10 = Speed (11=reserved)\r
- // (10=1000Mbps)\r
- // (01=100 Mbps)\r
- // (00=10 Mbps)\r
- // D0 = 1\r
- // all other bits = 0\r
- ///////////////////////////////////\r
- //When sgmii_mode == 0 = MAC\r
- // all bits D15-D0 are R/W,\r
- // D14 = Can be written but has no effect\r
- // on autonegotiation. Instead\r
- // the autonegotiation state machine\r
- // controls the utilization of this bit.\r
- // D0 = 1\r
- // all other bits = 0\r
- ///////////////////////////////////\r
-\r
-\r
-reg [15:0] data_out;\r
-reg [15:0] mr_adv_ability;\r
-reg rst_d1;\r
-reg rst_d2;\r
-reg rst_d3;\r
-reg rst_d4;\r
-reg rst_d5;\r
-reg rst_d6;\r
-reg rst_d7;\r
-reg rst_d8;\r
-reg sync_reset;\r
-reg sgmii_mode_d1;\r
-reg sgmii_mode_d2;\r
-reg sgmii_mode_d3;\r
-reg sgmii_mode_d4;\r
-reg sgmii_mode_change;\r
-reg gbe_mode_d1;\r
-reg gbe_mode_d2;\r
-reg gbe_mode_d3;\r
-reg gbe_mode_d4;\r
-reg gbe_mode_change;\r
-\r
-// generate a synchronous reset signal\r
-// note: this method is used so that\r
-// an initval can be applied during\r
-// device run-time, instead of at compile time\r
-always @(posedge clk or negedge rst_n) begin\r
- if (rst_n == 1'b0) begin\r
- rst_d1 <= 0;\r
- rst_d2 <= 0;\r
- rst_d3 <= 0;\r
- rst_d4 <= 0;\r
- rst_d5 <= 0;\r
- rst_d6 <= 0;\r
- rst_d7 <= 0;\r
- rst_d8 <= 0;\r
- sync_reset <= 0;\r
- end\r
- else begin\r
- rst_d1 <= 1;\r
- rst_d2 <= rst_d1;\r
- rst_d3 <= rst_d2;\r
- rst_d4 <= rst_d3;\r
- rst_d5 <= rst_d4;\r
- rst_d6 <= rst_d5;\r
- rst_d7 <= rst_d6;\r
- rst_d8 <= rst_d7;\r
-\r
- // asserts on rising edge of rst_d8\r
- sync_reset <= !rst_d8 & rst_d7; \r
- end\r
-end\r
-\r
-\r
-// Detect change in sgmii_mode\r
-always @(posedge clk or negedge rst_n) begin\r
- if (rst_n == 1'b0) begin\r
- sgmii_mode_d1 <= 0;\r
- sgmii_mode_d2 <= 0;\r
- sgmii_mode_d3 <= 0;\r
- sgmii_mode_d4 <= 0;\r
- sgmii_mode_change <= 0;\r
- end\r
- else begin\r
-\r
- // deboggle\r
- sgmii_mode_d1 <= sgmii_mode;\r
- sgmii_mode_d2 <= sgmii_mode_d1;\r
-\r
- // delay \r
- sgmii_mode_d3 <= sgmii_mode_d2;\r
- sgmii_mode_d4 <= sgmii_mode_d3;\r
-\r
- // detect change\r
- if (sgmii_mode_d3 != sgmii_mode_d4)\r
- sgmii_mode_change <= 1;\r
- else\r
- sgmii_mode_change <= 0;\r
- end\r
-end\r
-\r
-\r
-// Detect change in gbe_mode\r
-always @(posedge clk or negedge rst_n) begin\r
- if (rst_n == 1'b0) begin\r
- gbe_mode_d1 <= 0;\r
- gbe_mode_d2 <= 0;\r
- gbe_mode_d3 <= 0;\r
- gbe_mode_d4 <= 0;\r
- gbe_mode_change <= 0;\r
- end\r
- else begin\r
-\r
- // deboggle\r
- gbe_mode_d1 <= gbe_mode;\r
- gbe_mode_d2 <= gbe_mode_d1;\r
-\r
- // delay \r
- gbe_mode_d3 <= gbe_mode_d2;\r
- gbe_mode_d4 <= gbe_mode_d3;\r
-\r
- // detect change\r
- if (gbe_mode_d3 != gbe_mode_d4)\r
- gbe_mode_change <= 1;\r
- else\r
- gbe_mode_change <= 0;\r
- end\r
-end\r
-\r
-\r
-// Write Operations\r
- // Low Portion of Register[D7:D0]\r
- always @(posedge clk or negedge rst_n) begin\r
- if (rst_n == 1'b0) begin\r
- mr_adv_ability[7:0] <= 8'h01;\r
- end\r
- else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin\r
- if (gbe_mode_d4)\r
- mr_adv_ability[7:0] <= initval_gbe[7:0];\r
- else if (sgmii_mode)\r
- mr_adv_ability[7:0] <= initval_phy[7:0];\r
- else\r
- mr_adv_ability[7:0] <= initval_mac[7:0];\r
- end\r
- else begin\r
- if (cs_0 && ready && write && (sgmii_mode || gbe_mode)) begin\r
- mr_adv_ability[7:0] <= data_in[7:0];\r
- end\r
- end\r
- end\r
-\r
-\r
- // High Portion of Register[D15:D8]\r
- always @(posedge clk or negedge rst_n) begin\r
- if (rst_n == 1'b0) begin\r
- mr_adv_ability[15:8] <= 8'h40; // default\r
- end\r
- else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin\r
- if (gbe_mode_d4)\r
- mr_adv_ability[15:8] <= initval_gbe[15:8];\r
- else if (sgmii_mode)\r
- mr_adv_ability[15:8] <= initval_phy[15:8];\r
- else\r
- mr_adv_ability[15:8] <= initval_mac[15:8];\r
- end\r
- else begin\r
- if (cs_1 && ready && write && (sgmii_mode || gbe_mode)) begin\r
- mr_adv_ability[15:8] <= data_in[15:8];\r
- end\r
- end\r
- end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-// Read Operations\r
-\r
- always @(*) begin\r
- data_out[7:0] <= mr_adv_ability[7:0];\r
- data_out[15:8] <= mr_adv_ability[15:8];\r
- end\r
-\r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-module register_5_hb (\r
- rst_n,\r
- mr_lp_adv_ability,\r
- cs_0,\r
- cs_1,\r
- ready,\r
-\r
- data_out\r
-);\r
-\r
-input rst_n;\r
-input cs_0;\r
-input cs_1;\r
-input ready;\r
-input [15:0] mr_lp_adv_ability;\r
- // This entire register is read-only\r
- ///////////////////////////////////\r
- // When sgmii_mode == 0 == MAC\r
- ///////////////////////////////////\r
- // D15 = PHY Link Status (1=up, 0=down)\r
- // D14 = PHY Autonegotiation Handshake\r
- // D12 = PHY Duplex Mode (1=full, 0=half)\r
- // D11:10 = PHY Speed (11=reserved)\r
- // (10=1000Mbps)\r
- // (01=100 Mbps)\r
- // (00=10 Mbps)\r
- // D0 = 1\r
- // all other bits = 0\r
- ///////////////////////////////////\r
- //When sgmii_mode == 1 = PHY\r
- // D14 = MAC Autonegotiation Handshake\r
- // D0 = 1\r
- // all other bits = 0\r
- ///////////////////////////////////\r
-output [15:0] data_out;\r
-\r
-reg [15:0] data_out;\r
-\r
-// Read Operations\r
-\r
- always @(*) begin\r
- data_out[7:0] <= mr_lp_adv_ability[7:0];\r
- data_out[15:8] <= mr_lp_adv_ability[15:8];\r
- end\r
-endmodule\r
-\r
-module register_6_hb (\r
- rst_n,\r
- clk,\r
- mr_page_rx,\r
- cs_0,\r
- cs_1,\r
- write,\r
- ready,\r
-\r
- data_out\r
-);\r
-\r
-input rst_n;\r
-input clk;\r
-input cs_0;\r
-input cs_1;\r
-input write;\r
-input ready;\r
-input mr_page_rx;\r
-output [15:0] data_out;\r
-\r
-reg [15:0] data_out;\r
-reg mr_page_rx_latched;\r
-reg clear_on_read;\r
-reg read_detect;\r
-reg rd_d1;\r
-reg rd_d2;\r
-\r
-// generate clear-on-read signal\r
- always @(posedge clk or negedge rst_n) begin\r
- if (rst_n == 1'b0) begin\r
- clear_on_read <= 0;\r
- read_detect <= 0;\r
- rd_d1 <= 0;\r
- rd_d2 <= 0;\r
- end\r
- else begin\r
- if (!write && ready && cs_0)\r
- read_detect <= 1;\r
- else \r
- read_detect <= 0;\r
-\r
- rd_d1 <= read_detect;\r
- rd_d2 <= rd_d1;\r
-\r
- // assert on falling edge of rd_d2\r
- clear_on_read <= !rd_d1 & rd_d2;\r
- end\r
- end\r
-\r
-\r
-// Latch and Clear\r
- always @(posedge clk or negedge rst_n) begin\r
- if (rst_n == 1'b0) begin\r
- mr_page_rx_latched <= 0;\r
- end\r
- else begin\r
- if (clear_on_read)\r
- mr_page_rx_latched <= 0;\r
- else if (mr_page_rx)\r
- mr_page_rx_latched <= 1;\r
- end\r
- end\r
-\r
-\r
-// Read Operations\r
-\r
- always @(*) begin\r
- data_out[15:2] <= 14'd0;\r
- data_out[1] <= mr_page_rx_latched;\r
- data_out[0] <= 0;\r
- end\r
-endmodule\r
-\r
-\r
-module regs_hb (\r
- rst_n,\r
- hclk,\r
- gbe_mode,\r
- sgmii_mode,\r
- hcs_n,\r
- hwrite_n,\r
- haddr,\r
- hdatain,\r
-\r
- hdataout,\r
- hready_n,\r
-\r
- mr_an_complete,\r
- mr_page_rx,\r
- mr_lp_adv_ability,\r
-\r
- mr_main_reset,\r
- mr_an_enable,\r
- mr_restart_an,\r
- mr_adv_ability\r
-);\r
-\r
-input rst_n;\r
-input hclk;\r
-input gbe_mode;\r
-input sgmii_mode;\r
-input hcs_n;\r
-input hwrite_n;\r
-input [3:0] haddr;\r
-input [7:0] hdatain;\r
-\r
-output [7:0] hdataout;\r
-output hready_n;\r
-\r
-input mr_an_complete;\r
-input mr_page_rx;\r
-input [15:0] mr_lp_adv_ability;\r
-\r
-output mr_main_reset;\r
-output mr_an_enable;\r
-output mr_restart_an;\r
-output [15:0] mr_adv_ability;\r
-\r
-///////////////////////////////////\r
-\r
-\r
-\r
-reg [7:0] hdataout;\r
-reg hr;\r
-reg hready_n;\r
-\r
-reg hcs_n_delayed;\r
-\r
-wire reg0_cs_0;\r
-wire reg0_cs_1;\r
-\r
-wire reg1_cs_0;\r
-wire reg1_cs_1;\r
-\r
-wire reg4_cs_0;\r
-wire reg4_cs_1;\r
-\r
-wire reg5_cs_0;\r
-wire reg5_cs_1;\r
-\r
-wire reg6_cs_0;\r
-wire reg6_cs_1;\r
-\r
-wire [15:0] data_out_reg_0;\r
-wire [15:0] data_out_reg_1;\r
-wire [15:0] data_out_reg_4;\r
-wire [15:0] data_out_reg_5;\r
-wire [15:0] data_out_reg_6;\r
-\r
-\r
-\r
-register_addr_decoder ad_dec (\r
- .rst_n(rst_n),\r
- .addr(haddr),\r
- .cs_in(~hcs_n),\r
-\r
- .reg0_cs_0 (reg0_cs_0),\r
- .reg0_cs_1 (reg0_cs_1),\r
- .reg1_cs_0 (reg1_cs_0),\r
- .reg1_cs_1 (reg1_cs_1),\r
- .reg4_cs_0 (reg4_cs_0),\r
- .reg4_cs_1 (reg4_cs_1),\r
- .reg5_cs_0 (reg5_cs_0),\r
- .reg5_cs_1 (reg5_cs_1),\r
- .reg6_cs_0 (reg6_cs_0),\r
- .reg6_cs_1 (reg6_cs_1)\r
-);\r
-\r
-\r
-register_0_hb register_0 (\r
- .rst_n (rst_n),\r
- .clk (hclk), \r
- .cs_0 (reg0_cs_0),\r
- .cs_1 (reg0_cs_1),\r
- .write (~hwrite_n),\r
- .ready (1'b1),\r
- .data_in ({hdatain, hdatain}),\r
-\r
- .data_out (data_out_reg_0),\r
- .mr_main_reset (mr_main_reset),\r
- .mr_an_enable (mr_an_enable),\r
- .mr_restart_an (mr_restart_an)\r
-);\r
-\r
-\r
-register_1_hb register_1 (\r
- .rst_n (rst_n),\r
- .cs_0 (reg1_cs_0),\r
- .cs_1 (reg1_cs_1),\r
- .mr_an_complete (mr_an_complete),\r
-\r
- .data_out (data_out_reg_1)\r
-);\r
-\r
-\r
-register_4_hb register_4 (\r
- .rst_n (rst_n),\r
- .clk (hclk), \r
- .gbe_mode (gbe_mode),\r
- .sgmii_mode (sgmii_mode),\r
- .cs_0 (reg4_cs_0),\r
- .cs_1 (reg4_cs_1),\r
- .write (~hwrite_n),\r
- .ready (1'b1),\r
- .data_in ({hdatain, hdatain}),\r
-\r
- .data_out (data_out_reg_4),\r
- .mr_adv_ability (mr_adv_ability)\r
-);\r
-\r
-\r
-register_5_hb register_5 (\r
- .rst_n (rst_n),\r
- .mr_lp_adv_ability (mr_lp_adv_ability),\r
- .cs_0 (reg5_cs_0),\r
- .cs_1 (reg5_cs_1),\r
- .ready (1'b1),\r
-\r
- .data_out (data_out_reg_5)\r
-);\r
-\r
-\r
-register_6_hb register_6 (\r
- .rst_n (rst_n),\r
- .clk (hclk), \r
- .mr_page_rx (mr_page_rx),\r
- .cs_0 (reg6_cs_0),\r
- .cs_1 (reg6_cs_1),\r
- .write (~hwrite_n),\r
- .ready (1'b1),\r
-\r
- .data_out (data_out_reg_6)\r
-);\r
-\r
-\r
-\r
-// generate an ack\r
-always @(posedge hclk or negedge rst_n) begin\r
- if (rst_n == 1'b0) begin\r
- hcs_n_delayed <= 1'b1;\r
- hr <= 1'b1;\r
- hready_n <= 1'b1;\r
- end\r
- else begin\r
- hcs_n_delayed <= hcs_n;\r
-\r
- //assert on falling edge of delayed chip select\r
- hr <= ~hcs_n & hcs_n_delayed;\r
- hready_n <= ~hr;\r
- end\r
-end\r
-\r
-\r
-\r
-// Mux Register Read-Data Outputs\r
-always @(posedge hclk or negedge rst_n)\r
-begin\r
- if (rst_n == 1'b0) begin\r
- hdataout <= 8'd0;\r
- end\r
- else begin\r
- case (haddr[3:0])\r
-\r
- 4'd0:\r
- begin\r
- hdataout <= data_out_reg_0[7:0];\r
- end\r
-\r
-\r
- 4'd1:\r
- begin\r
- hdataout <= data_out_reg_0[15:8];\r
- end\r
-\r
- /////////////////////////////////////////////\r
-\r
- 4'd2:\r
- begin\r
- hdataout <= data_out_reg_1[7:0];\r
- end\r
-\r
-\r
- 4'd3:\r
- begin\r
- hdataout <= data_out_reg_1[15:8];\r
- end\r
-\r
- /////////////////////////////////////////////\r
-\r
- 4'd8:\r
- begin\r
- hdataout <= data_out_reg_4[7:0];\r
- end\r
-\r
-\r
- 4'd9:\r
- begin\r
- hdataout <= data_out_reg_4[15:8];\r
- end\r
-\r
- /////////////////////////////////////////////\r
-\r
- 4'd10:\r
- begin\r
- hdataout <= data_out_reg_5[7:0];\r
- end\r
-\r
-\r
- 4'd11:\r
- begin\r
- hdataout <= data_out_reg_5[15:8];\r
- end\r
-\r
- /////////////////////////////////////////////\r
-\r
- 4'd12:\r
- begin\r
- hdataout <= data_out_reg_6[7:0];\r
- end\r
-\r
-\r
- 4'd13:\r
- begin\r
- hdataout <= data_out_reg_6[15:8];\r
- end\r
-\r
- /////////////////////////////////////////////\r
-\r
- default:\r
- begin\r
- hdataout <= 8'd0;\r
- end\r
- endcase\r
- end\r
-end\r
-\r
-endmodule\r
-\r
-module register_addr_decoder (\r
- rst_n,\r
- addr,\r
- cs_in,\r
-\r
- reg0_cs_0,\r
- reg0_cs_1,\r
-\r
- reg1_cs_0,\r
- reg1_cs_1,\r
-\r
- reg4_cs_0,\r
- reg4_cs_1,\r
-\r
- reg5_cs_0,\r
- reg5_cs_1,\r
-\r
- reg6_cs_0,\r
- reg6_cs_1\r
-);\r
-\r
-input rst_n;\r
-input cs_in;\r
-input [3:0] addr;\r
-\r
-output reg0_cs_0;\r
-output reg0_cs_1;\r
-\r
-output reg1_cs_0;\r
-output reg1_cs_1;\r
-\r
-output reg4_cs_0;\r
-output reg4_cs_1;\r
-\r
-output reg5_cs_0;\r
-output reg5_cs_1;\r
-\r
-output reg6_cs_0;\r
-output reg6_cs_1;\r
-\r
-//////////////////////////\r
-\r
-wire reg0_cs_0;\r
-wire reg0_cs_1;\r
-\r
-wire reg1_cs_0;\r
-wire reg1_cs_1;\r
-\r
-wire reg4_cs_0;\r
-wire reg4_cs_1;\r
-\r
-wire reg5_cs_0;\r
-wire reg5_cs_1;\r
-\r
-wire reg6_cs_0;\r
-wire reg6_cs_1;\r
-\r
-//////////////////////////\r
-\r
-assign reg0_cs_0 = (addr == 4'h0) ? cs_in : 1'b0;\r
-assign reg0_cs_1 = (addr == 4'h1) ? cs_in : 1'b0;\r
-\r
-assign reg1_cs_0 = (addr == 4'h2) ? cs_in : 1'b0;\r
-assign reg1_cs_1 = (addr == 4'h3) ? cs_in : 1'b0;\r
-\r
-assign reg4_cs_0 = (addr == 4'h8) ? cs_in : 1'b0;\r
-assign reg4_cs_1 = (addr == 4'h9) ? cs_in : 1'b0;\r
-\r
-assign reg5_cs_0 = (addr == 4'ha) ? cs_in : 1'b0;\r
-assign reg5_cs_1 = (addr == 4'hb) ? cs_in : 1'b0;\r
-\r
-assign reg6_cs_0 = (addr == 4'hc) ? cs_in : 1'b0;\r
-assign reg6_cs_1 = (addr == 4'hd) ? cs_in : 1'b0;\r
-\r
-\r
-endmodule\r
-\r
+++ /dev/null
-//**************************************************************************\r
-// *************************************************************************\r
-// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
-// * PROPRIETARY NOTE *\r
-// * *\r
-// * This software contains information confidential and proprietary *\r
-// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
-// * in whole or in part, or transferred to other documents, or disclosed *\r
-// * to third parties, or used for any purpose other than that for which *\r
-// * it was obtained, without the prior written consent of Lattice *\r
-// * Semiconductor Corporation. All rights reserved. *\r
-// * *\r
-// *************************************************************************\r
-//**************************************************************************\r
-\r
-////////////////////////////////////////////////////////////////////////\r
-// This module forces a RESET to the SERDES CDR\r
-// when the CDR either loses lock or loses signal\r
-////////////////////////////////////////////////////////////////////////\r
-\r
-`timescale 1ns/100ps\r
-\r
-module reset_controller_cdr (\r
-\r
- rst_n,\r
- clk,\r
-\r
- cdr_lol,\r
-\r
- cdr_rst_out\r
- );\r
-\r
-input rst_n;\r
-input clk; // 125Mhz clock\r
-\r
-input cdr_lol;\r
-\r
-output cdr_rst_out;\r
-\r
-\r
-///////////////////////////////////////\r
-\r
-reg cdr_rst_out;\r
-\r
-reg cdr_lol_mstb_1;\r
-reg cdr_lol_mstb_2;\r
-\r
-\r
-reg sht_mx;\r
-reg [5:0] sht_count;\r
-\r
-reg lng_mx;\r
-reg [22:0] lng_count;\r
-\r
-reg cnt_rst;\r
-parameter\r
- ASSRT_RST = 3'd0,\r
- WAIT_SHORT = 3'd1,\r
- DSSRT_RST = 3'd2,\r
- WAIT_LONG = 3'd3,\r
- SEEK_CDR_ERR = 3'd4,\r
- SEEK_SIGNAL_RESTORE = 3'd5;\r
-reg[2:0] fsm;\r
-\r
-//////////////////////////////////////\r
-// Mestastability Filter\r
-//////////////////////////////////////\r
-always @(posedge clk or negedge rst_n)\r
-begin\r
- if (rst_n == 1'b0) begin\r
- cdr_lol_mstb_1 <= 1'b1;\r
- cdr_lol_mstb_2 <= 1'b1;\r
-\r
-\r
- end\r
- else begin\r
- cdr_lol_mstb_1 <= cdr_lol;\r
- cdr_lol_mstb_2 <= cdr_lol_mstb_1;\r
-\r
- end\r
-end \r
-\r
-\r
-\r
-///////////////////////////////////////\r
-// Operate Short Timer (256 nsec)\r
-///////////////////////////////////////\r
-always @(posedge clk or negedge rst_n)\r
-begin\r
- if (rst_n == 1'b0) begin\r
- sht_mx <= 1'b0;\r
- sht_count <= 6'd0;\r
- end\r
- else begin\r
-\r
- // define max count\r
- if (sht_count[5] && (!cnt_rst)) begin\r
- sht_mx <= 1'b1;\r
- end\r
- else begin\r
- sht_mx <= 1'b0;\r
- end\r
-\r
- // operate counter\r
- if (cnt_rst) begin\r
- sht_count <= 6'd0; //clear\r
- end\r
- else if (sht_mx) begin\r
- sht_count <= sht_count; //hold\r
- end\r
- else begin\r
- sht_count <= sht_count + 1; //count\r
- end\r
- end\r
-end \r
-\r
-\r
-/////////////////////////////////////\r
-// Operate Long Timer (33 msec)\r
-/////////////////////////////////////\r
-always @(posedge clk or negedge rst_n)\r
-begin\r
- if (rst_n == 1'b0) begin\r
- lng_mx <= 1'b0;\r
- lng_count <= 23'd0;\r
- end\r
- else begin\r
-\r
- // define max count\r
- if (lng_count[22] && (!cnt_rst)) begin\r
- lng_mx <= 1'b1;\r
- end\r
- else begin\r
- lng_mx <= 1'b0;\r
- end\r
-\r
- // operate counter\r
- if (cnt_rst) begin\r
- lng_count <= 6'd0; //clear\r
- end\r
- else if (lng_mx) begin\r
- lng_count <= lng_count; //hold\r
- end\r
- else begin\r
- lng_count <= lng_count + 1; //count\r
- end\r
- end\r
-end \r
-\r
-\r
-/////////////////////////////////////\r
-// State Machine\r
-/////////////////////////////////////\r
-always @(posedge clk or negedge rst_n)\r
-begin\r
- if (rst_n == 1'b0) begin\r
- cdr_rst_out <= 1'b1;\r
- cnt_rst <= 1'b1;\r
- fsm <= ASSRT_RST;\r
- end\r
- else begin\r
-\r
- // defaults\r
- cnt_rst <= 1'b0;\r
-\r
- case (fsm)\r
- ASSRT_RST: begin\r
- cdr_rst_out <= 1'b1; // assert\r
- cnt_rst <= 1'b1;\r
- fsm <= WAIT_SHORT;\r
- end\r
-\r
- WAIT_SHORT: begin\r
- // wait for 256 nsec\r
- if (sht_mx && (!cnt_rst)) begin\r
- fsm <= DSSRT_RST;\r
- end\r
- end\r
-\r
- DSSRT_RST: begin\r
- cdr_rst_out <= 1'b0; // de-assert\r
- fsm <= WAIT_LONG;\r
- end\r
-\r
- WAIT_LONG: begin\r
- // wait for 33 msec\r
- if (lng_mx && (!cnt_rst)) begin\r
- fsm <= SEEK_CDR_ERR;\r
- end\r
- end\r
-\r
- SEEK_CDR_ERR: begin\r
-\r
- cnt_rst <= 1'b1;\r
-\r
-\r
- // Wait for CDR to fail\r
- if (cdr_lol_mstb_2) begin\r
- fsm <= ASSRT_RST;\r
- end\r
- else begin\r
- fsm <= SEEK_CDR_ERR;\r
- end\r
- end\r
-\r
-\r
-\r
- default: begin\r
- fsm <= ASSRT_RST;\r
- end\r
- endcase\r
-\r
- end\r
-end \r
-\r
-\r
-\r
-endmodule\r
-\r
+++ /dev/null
-//**************************************************************************\r
-// *************************************************************************\r
-// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
-// * PROPRIETARY NOTE *\r
-// * *\r
-// * This software contains information confidential and proprietary *\r
-// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
-// * in whole or in part, or transferred to other documents, or disclosed *\r
-// * to third parties, or used for any purpose other than that for which *\r
-// * it was obtained, without the prior written consent of Lattice *\r
-// * Semiconductor Corporation. All rights reserved. *\r
-// * *\r
-// *************************************************************************\r
-//**************************************************************************\r
-\r
-////////////////////////////////////////////////////////////////////////\r
-// This module implements the SERDES/PCS reset sequence as specified\r
-// in Figure 47 of Lattice Technical Note TN1176\r
-////////////////////////////////////////////////////////////////////////\r
-\r
-`timescale 1ns/100ps\r
-\r
-module reset_controller_pcs (\r
-\r
- rst_n,\r
- clk,\r
-\r
- tx_plol,\r
- rx_cdr_lol,\r
-\r
- quad_rst_out,\r
- tx_pcs_rst_out,\r
- rx_pcs_rst_out\r
- );\r
-\r
-input rst_n;\r
-input clk; // 125Mhz clock\r
-\r
-input tx_plol;\r
-input rx_cdr_lol;\r
-\r
-output quad_rst_out;\r
-output tx_pcs_rst_out;\r
-output rx_pcs_rst_out;\r
-\r
-\r
-///////////////////////////////////////\r
-\r
-reg quad_rst_out;\r
-reg tx_pcs_rst_out;\r
-reg rx_pcs_rst_out;\r
-\r
-reg q_mx;\r
-reg [3:0] q_count;\r
-\r
-reg rx_cdr_lol_mstb_1;\r
-reg rx_cdr_lol_mstb_2;\r
-\r
-reg wd_mx;\r
-reg wd_mx_d1;\r
-reg wd_mx_re;\r
-reg [22:0] wd_count;\r
-reg watchdog_flag;\r
-\r
-////////////////////////////////////////////////////////\r
-// Assert Quad RST For 8 Clocks After Device Hard Reset\r
-////////////////////////////////////////////////////////\r
-always @(posedge clk or negedge rst_n)\r
-begin\r
- if (rst_n == 1'b0) begin\r
- q_mx <= 1'b0;\r
- q_count <= 4'd0;\r
- quad_rst_out <= 1'b1; // assert\r
- end\r
- else begin\r
-\r
- // define max count\r
- if (q_count[3]) begin\r
- q_mx <= 1'b1;\r
- end\r
- else begin\r
- q_mx <= 1'b0;\r
- end\r
-\r
- // operate counter\r
- if (q_mx) begin\r
- q_count <= q_count; //hold\r
- end\r
- else begin\r
- q_count <= q_count + 1; //count\r
- end\r
-\r
- // operate quad reset\r
- if (q_mx) begin\r
- quad_rst_out <= 1'b0; //de-assert on max-count\r
- end\r
- else begin\r
- quad_rst_out <= 1'b1; //assert otherwise\r
- end\r
- end\r
-end \r
-\r
-\r
-////////////////////////////////////////////////////////////////////\r
-// Watchdog Timer -- In Case PLLs Don't Acquire Lock Within 33msec\r
-////////////////////////////////////////////////////////////////////\r
-always @(posedge clk or negedge rst_n)\r
-begin\r
- if (rst_n == 1'b0) begin\r
- wd_mx <= 1'b0;\r
- wd_mx_d1 <= 1'b0;\r
- wd_mx_re <= 1'b0;\r
- wd_count <= 23'd0;\r
- watchdog_flag <= 1'b0;\r
- end\r
- else begin\r
-\r
- // define max count\r
- if (wd_count[22]) begin\r
- wd_mx <= 1'b1;\r
- end\r
- else begin\r
- wd_mx <= 1'b0;\r
- end\r
-\r
- // operate counter\r
- if (quad_rst_out) begin\r
- wd_count <= 23'd0; //clear\r
- end\r
- else if (wd_mx) begin\r
- wd_count <= wd_count; //hold\r
- end\r
- else begin\r
- wd_count <= wd_count + 1; //count\r
- end\r
-\r
- // detect rising edge of max_count flag\r
- wd_mx_d1 <= wd_mx;\r
-\r
- wd_mx_re <= wd_mx & (!wd_mx_d1);\r
-\r
- // generate watchdog flag\r
- watchdog_flag <= wd_mx_re;\r
- end\r
-end \r
-\r
-\r
-\r
-\r
-////////////////////////////////////////////////\r
-// De-Assert TX PCS After TX PLL Acquires Lock\r
-////////////////////////////////////////////////\r
-always @(posedge clk or negedge rst_n)\r
-begin\r
- if (rst_n == 1'b0) begin\r
- tx_pcs_rst_out <= 1'b1; // assert\r
- end\r
- else begin\r
-\r
- case (tx_pcs_rst_out)\r
- 1'b1: begin\r
- // if asserted, wait for PLL to acquire lock\r
- if ((!quad_rst_out && (!tx_plol)) || watchdog_flag) begin\r
- tx_pcs_rst_out <= 1'b0; // deassert\r
- end\r
- end\r
-\r
- 1'b0: begin\r
- // if de-asserted, stay that way\r
- tx_pcs_rst_out <= 1'b0; // deassert\r
- end\r
-\r
- default: begin\r
- tx_pcs_rst_out <= 1'b1; // assert\r
- end\r
- endcase\r
-\r
- end\r
-end \r
-\r
-\r
-\r
-\r
-\r
-///////////////////////////////////////////////////////\r
-// De-Assert RX PCS-Chan-0 After RX CDR Acquires Lock\r
-///////////////////////////////////////////////////////\r
-always @(posedge clk or negedge rst_n)\r
-begin\r
- if (rst_n == 1'b0) begin\r
- rx_pcs_rst_out <= 1'b1; // assert\r
- rx_cdr_lol_mstb_1 <= 1'b1;\r
- rx_cdr_lol_mstb_2 <= 1'b1;\r
- end\r
- else begin\r
-\r
- // metastability - filter\r
- rx_cdr_lol_mstb_1 <= rx_cdr_lol;\r
- rx_cdr_lol_mstb_2 <= rx_cdr_lol_mstb_1;\r
-\r
- case (rx_pcs_rst_out)\r
- 1'b1: begin\r
- // if asserted, wait for CDR to acquire lock\r
- if ((!quad_rst_out && (!rx_cdr_lol_mstb_2)) || watchdog_flag) begin\r
- rx_pcs_rst_out <= 1'b0; // deassert\r
- end\r
- end\r
-\r
- 1'b0: begin\r
- // if de-asserted, stay that way\r
- rx_pcs_rst_out <= 1'b0; // deassert\r
- end\r
-\r
- default: begin\r
- rx_pcs_rst_out <= 1'b1; // assert\r
- end\r
- endcase\r
-\r
- end\r
-end \r
-\r
-\r
-\r
-\r
-endmodule\r
-\r
+++ /dev/null
-//**************************************************************************\r
-// *************************************************************************\r
-// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
-// * PROPRIETARY NOTE *\r
-// * *\r
-// * This software contains information confidential and proprietary *\r
-// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
-// * in whole or in part, or transferred to other documents, or disclosed *\r
-// * to third parties, or used for any purpose other than that for which *\r
-// * it was obtained, without the prior written consent of Lattice *\r
-// * Semiconductor Corporation. All rights reserved. *\r
-// * *\r
-// *************************************************************************\r
-//**************************************************************************\r
-\r
-`timescale 1ns/100ps\r
-\r
-module sgmii_channel_smi (\r
-\r
- // Control Interface\r
- rst_n,\r
- gbe_mode,\r
- sgmii_mode,\r
- signal_detect,\r
- debug_link_timer_short,\r
- rx_compensation_err,\r
- non_an_rate,\r
-\r
- // G/MII Interface\r
- in_clk_gmii,\r
- in_clk_mii,\r
- data_in_mii,\r
- en_in_mii,\r
- err_in_mii,\r
-\r
- out_clk_gmii,\r
- out_clk_mii,\r
- data_out_mii,\r
- dv_out_mii,\r
- err_out_mii,\r
- col_out_mii,\r
- crs_out_mii,\r
-\r
- // 8-bit Interface\r
- data_out_8bi,\r
- kcntl_out_8bi,\r
- disparity_cntl_out_8bi,\r
-\r
- serdes_recovered_clk,\r
- data_in_8bi,\r
- kcntl_in_8bi,\r
- even_in_8bi,\r
- disp_err_in_8bi,\r
- cv_err_in_8bi,\r
- err_decode_mode_8bi,\r
-\r
- // MDIO Port\r
- mdc,\r
- mdio,\r
- port_id\r
- );\r
-\r
-\r
-\r
-// I/O Declarations\r
-input rst_n ; // System Reset, Active Low\r
-input signal_detect ;\r
-input gbe_mode ; // GBE Mode (0=SGMII 1=GBE)\r
-input sgmii_mode ; // SGMII PCS Mode (0=MAC 1=PHY)\r
-input debug_link_timer_short ; // (0=NORMAL 1=SHORT)\r
-output rx_compensation_err; // Active high pulse indicating RX_CTC_FIFO either underflowed or overflowed\r
-input [1:0] non_an_rate ; // MII Rate Used When Autonegotiation is Disabled (00=10Mbps; 01=100Mbps; 10=1Gbps)\r
-\r
-input in_clk_mii ; // G/MII Transmit clock 2.5Mhz/25Mhz/125Mhz \r
-input [7:0] data_in_mii ; // G/MII Tx data\r
-input en_in_mii ; // G/MII data valid\r
-input err_in_mii ; // G/MII Tx error\r
-\r
-input out_clk_mii ; // G/MII Receice clock 2.5Mhz/25Mhz/125MHz \r
-output [7:0] data_out_mii ; // G/MII Rx data\r
-output dv_out_mii ; // G/MII Rx data valid\r
-output err_out_mii ; // G/MII Rx error\r
-output col_out_mii ; // G/MII collision detect \r
-output crs_out_mii ; // G/MII carrier sense detect \r
-\r
-output [7:0] data_out_8bi ; // 8BI Tx Data\r
-output kcntl_out_8bi ; // 8BI Tx Kcntl\r
-output disparity_cntl_out_8bi ; // 8BI Tx Kcntl\r
-\r
-input serdes_recovered_clk ;\r
-input [7:0] data_in_8bi ; // 8BI Rx Data\r
-input kcntl_in_8bi ; // 8BI Rx Kcntl\r
-input even_in_8bi ; // 8BI Rx Even\r
-input disp_err_in_8bi ; // 8BI Rx Disparity Error\r
-input cv_err_in_8bi ; // 8BI Rx Coding Violation Error\r
-input err_decode_mode_8bi ; // 8BI Error Decode Mode (0=NORMAL, 1=DECODE_MODE)\r
-\r
-input in_clk_gmii ; // GMII Transmit clock 125Mhz\r
-input out_clk_gmii ; // GMII Receive clock 125Mhz\r
-\r
-input mdc;\r
-inout mdio;\r
-input [4:0] port_id;\r
-\r
-\r
-wire mdin;\r
-wire mdout;\r
-wire mdout_en;\r
-\r
-// Internal Signals \r
-\r
-wire mr_an_complete;\r
-wire mr_page_rx;\r
-wire [15:0] mr_lp_adv_ability;\r
-\r
-wire mr_main_reset;\r
-wire mr_an_enable;\r
-wire mr_restart_an;\r
-wire [15:0] mr_adv_ability;\r
-\r
-wire [1:0] operational_rate;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-// SGMII PCS\r
-sgmii33 sgmii33_U (\r
- // Clock and Reset\r
- .rst_n (rst_n ),\r
- .signal_detect (signal_detect),\r
- .gbe_mode (gbe_mode),\r
- .sgmii_mode (sgmii_mode),\r
- .debug_link_timer_short (debug_link_timer_short), \r
- .operational_rate (operational_rate),\r
- .rx_compensation_err (rx_compensation_err),\r
- .tx_clk_125 (in_clk_gmii),\r
- .serdes_recovered_clk (serdes_recovered_clk),\r
- .rx_clk_125 (out_clk_gmii),\r
-\r
- // Control\r
-\r
-\r
- // (G)MII TX Port\r
- .tx_clk_mii (in_clk_mii),\r
- .tx_d (data_in_mii),\r
- .tx_en (err_in_mii),\r
- .tx_er (en_in_mii),\r
-\r
- // (G)MII RX Port\r
- .rx_clk_mii (out_clk_mii),\r
- .rx_d (data_out_mii),\r
- .rx_dv (dv_out_mii),\r
- .rx_er (err_out_mii),\r
- .col (col_out_mii),\r
- .crs (crs_out_mii),\r
- \r
- // 8BI TX Port\r
- .tx_data (data_out_8bi),\r
- .tx_kcntl (kcntl_out_8bi),\r
- .tx_disparity_cntl (disparity_cntl_out_8bi),\r
-\r
- // 8BI RX Port\r
- .rx_data (data_in_8bi),\r
- .rx_kcntl (kcntl_in_8bi),\r
- .rx_even (even_in_8bi),\r
- .rx_disp_err (disp_err_in_8bi),\r
- .rx_cv_err (cv_err_in_8bi),\r
- .rx_err_decode_mode (err_decode_mode_8bi),\r
-\r
- // Management Interface I/O\r
- .mr_adv_ability (mr_adv_ability),\r
- .mr_an_enable (mr_an_enable), \r
- .mr_main_reset (mr_main_reset), \r
- .mr_restart_an (mr_restart_an), \r
-\r
- .mr_an_complete (mr_an_complete), \r
- .mr_lp_adv_ability (mr_lp_adv_ability), \r
- .mr_page_rx (mr_page_rx)\r
- );\r
-\r
-\r
-\r
-// SMI Register Interface for SGMII IP Core\r
-register_interface_smi ri (\r
-\r
- // Control Signals\r
- .rst_n (rst_n),\r
- .gbe_mode (gbe_mode),\r
- .sgmii_mode (sgmii_mode),\r
-\r
- // MDIO Port\r
- .mdc (mdc),\r
- .mdin (mdin),\r
- .mdout (mdout),\r
- .mdout_en (mdout_en),\r
- .port_id (port_id),\r
-\r
- // Register Outputs\r
- .mr_an_enable (mr_an_enable),\r
- .mr_restart_an (mr_restart_an),\r
- .mr_main_reset (mr_main_reset),\r
- .mr_adv_ability (mr_adv_ability),\r
-\r
- // Register Inputs\r
- .mr_an_complete (mr_an_complete),\r
- .mr_page_rx (mr_page_rx),\r
- .mr_lp_adv_ability (mr_lp_adv_ability)\r
- );\r
-\r
-\r
-\r
-// (G)MII Rate Resolution for SGMII IP Core\r
-rate_resolution rate_resolution (\r
- .gbe_mode (gbe_mode),\r
- .sgmii_mode (sgmii_mode),\r
- .an_enable (mr_an_enable),\r
- .advertised_rate (mr_adv_ability[11:10]),\r
- .link_partner_rate (mr_lp_adv_ability[11:10]),\r
- .non_an_rate (non_an_rate),\r
-\r
- .operational_rate (operational_rate)\r
-);\r
-\r
-\r
-\r
-\r
-\r
-// Bidirectional Assignments\r
-assign mdio = mdout_en ? mdout : 1'bz; // MDIO Output\r
-assign mdin = mdio; // MDIO Input\r
-\r
-endmodule\r
-\r
+++ /dev/null
-
-#!/usr/local/bin/wish
-
-set Para(cmd) ""
-if ![catch {set temp $argc} result] {
- if {$argc > 0} {
- for {set i 0} {$i < $argc} {incr i 2} {
- set temp [lindex $argv $i]
- set temp [string range $temp 1 end]
- lappend argv_list $temp
- lappend value_list [lindex $argv [expr $i+1]]
- }
- foreach argument $argv_list value $value_list {
- switch $argument {
- "cmd" {set Para(cmd) $value;}
- }
- }
- }
-}
-
-set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/sgmii_gbe_pcs32"
-set Para(ModuleName) "sgmii_gbe_pcs32"
-set Para(lib) "/home/greg/sgmii_gbepcs_v3.4/lib"
-set Para(CoreName) "SGMII/Gb Ethernet PCS"
-set Para(family) "latticeecp2m"
-set Para(Family) "ep5m00"
-set Para(design) "VHDL"
-
-lappend auto_path "/home/greg/sgmii_gbepcs_v3.4/gui"
-
-lappend auto_path "/home/greg/sgmii_gbepcs_v3.4/script"
-package require Core_Generate
-
-lappend auto_path "/opt/lattice/ispLEVER8.1/isptools/ispcpld/tcltk/lib/ipwidgets/ispipbuilder/../runproc"
-package require runcmd
-
-set Para(install_dir) "/opt/lattice/ispLEVER8.1/isptools/ispcpld/tcltk/lib/ipwidgets/ispipbuilder/../../../../.."
-
-set Para(result) [GenerateCore]
+++ /dev/null
-PROJECT: sgmii_gbe_pcs32
- working_path: "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/sgmii_gbe_pcs32/syn_results"
- module: sgmii_gbe_pcs32
-
- verilog_file_list: "/opt/lattice/ispLEVER8.1/isptools/ispcpld/tcltk/lib/ipwidgets/ispipbuilder/../../../../../cae_library/synthesis/verilog/ecp2m.v" "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32_wrapper.v" "/home/greg/sgmii_gbepcs_v3.4/lib/../sgmii_pcs_eval/username/src/ertl/ertl.v"
-
- suffix_name: edi
- output_file_name: sgmii_gbe_pcs32
- write_prf: false
- vlog_std_v2001: true
- disable_io_insertion: true
- STYFILENAME: dummy.sty
-
-force_gsr: false
+++ /dev/null
-[Device]
-Family=ep5m00
-PartType=LFE2M100E
-PartName=LFE2M100E-5F900C
-SpeedGrade=-5
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=IPCFG
-CoreStatus=Demo
-CoreName=SGMII/Gb Ethernet PCS
-CoreRevision=3.2
-ModuleName=sgmii_gbe_pcs32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=06/17/2011
-Time=11:34:20
-
-[Parameters]
-RX_CTC=2
-RX_CTC_LOW=16
-RX_CTC_HIGH=32
-EasyConnect=1
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress 12/10/2009 15:57:55 \r
-// Filename: sgmii_gbe_pcs32_bb.v \r
-// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-//---------------------------------------------------------------\r
-// sgmii_gbe_pcs32 synthesis black box definition \r
-//---------------------------------------------------------------\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
-\r
- \r
-\r
- \r
-\r
-\r
-module sgmii_gbe_pcs32 (\r
- // Control Interface\r
- rst_n,\r
- signal_detect,\r
- gbe_mode,\r
- sgmii_mode,\r
- operational_rate,\r
- debug_link_timer_short,\r
- rx_compensation_err,\r
- \r
- // G/MII Interface\r
- tx_clock_enable_sink ,\r
- tx_clock_enable_source ,\r
- tx_clk_125,\r
- tx_d,\r
- tx_en,\r
- tx_er,\r
-\r
- rx_clock_enable_sink ,\r
- rx_clock_enable_source ,\r
- rx_clk_125,\r
- rx_d,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
-\r
- // 8-bit Interface\r
- tx_data,\r
- tx_kcntl,\r
- tx_disparity_cntl,\r
-\r
- serdes_recovered_clk,\r
- rx_data,\r
- rx_kcntl,\r
- rx_even ,\r
- rx_disp_err ,\r
- rx_cv_err ,\r
- rx_err_decode_mode ,\r
- \r
- // Managment Control Outputs\r
- mr_an_complete,\r
- mr_page_rx,\r
- mr_lp_adv_ability,\r
-\r
- // Managment Control Inputs\r
- mr_main_reset,\r
- mr_an_enable,\r
- mr_restart_an,\r
- mr_adv_ability\r
- );\r
-\r
-\r
-\r
-// Control Interface\r
-input rst_n ;\r
-input signal_detect ;\r
-input gbe_mode ;\r
-input sgmii_mode ;\r
-input [1:0] operational_rate ;\r
-input debug_link_timer_short ;\r
-output rx_compensation_err ;\r
-\r
-// G/MII Interface\r
-input tx_clock_enable_sink;\r
-output tx_clock_enable_source;\r
-input tx_clk_125 ;\r
-input [7:0] tx_d ;\r
-input tx_en ;\r
-input tx_er ;\r
-\r
-input rx_clock_enable_sink;\r
-output rx_clock_enable_source;\r
-input rx_clk_125 ;\r
-output [7:0] rx_d ;\r
-output rx_dv ;\r
-output rx_er ;\r
-output col ;\r
-output crs ;\r
-\r
-// 8-bit Interface\r
-output [7:0] tx_data ;\r
-output tx_kcntl;\r
-output tx_disparity_cntl;\r
-\r
-input serdes_recovered_clk ;\r
-input [7:0] rx_data ;\r
-input rx_even ;\r
-input rx_kcntl;\r
-input rx_disp_err ;\r
-input rx_cv_err ;\r
-input rx_err_decode_mode ;\r
-\r
-// Managment Control Outputs\r
-output mr_an_complete;\r
-output mr_page_rx;\r
-output [15:0] mr_lp_adv_ability;\r
-\r
-// Managment Control Inputs\r
-input mr_main_reset;\r
-input mr_an_enable;\r
-input mr_restart_an;\r
-input [15:0] mr_adv_ability;\r
-\r
-\r
-\r
-endmodule\r
-\r
+++ /dev/null
-// sgmii_pcs_core_beh_pp.v generated by Lattice IP Model Creator version 1\r
-// created on Wed Mar 11 09:41:50 CST 2009\r
-// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved\r
-// obfuscator_exe version 1.mar0807\r
-\r
-// top\r
-\r
-\r
-`define SGMII_NO_ENC\r
-\r
-`define SGMII_YES_CTC_DYNAMIC\r
-\r
-`define SGMII_FIFO_FAMILY_ECP2M\r
-\r
-`define SGMII_YES_SINGLE_CLOCK\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module xwfb762 (icdbb13, fndd899, dzec4ce, ww62677, nt133b8, je99dc6, \r
- gocee32, ay77190, dob8c81, gbc640b, db3205d, cb902ef, fp8177d, \r
- pubbee);\r
-input [17:0] icdbb13;\r
-input fndd899;\r
-input dzec4ce;\r
-input ww62677;\r
-input nt133b8;\r
-input je99dc6;\r
-input gocee32;\r
-input [9:0] ay77190;\r
-input [9:0] dob8c81;\r
-output [17:0] gbc640b;\r
-output db3205d;\r
-output cb902ef;\r
-output fp8177d;\r
-output pubbee;\r
-reg [17 : 0] hqbd2d7;\r
-reg jpe96ba;\r
-reg uv4b5d7;\r
-reg pf5aebd;\r
-reg jpd75ef;\r
-reg fpbaf7e;\r
-reg thd7bf6;\r
-reg [9 : 0] jebdfb7;\r
-reg [9 : 0] ayefdbb;\r
-reg [2047:0] bl7edd9;\r
-wire [8:0] nrf6ece;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam zmb7676 = 9,wlbb3b3 = 32'hfdfff40b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-AND2 ofe7218 (.A(ww62677), .B(fnc8624), .Z(su43126)); INV ux18931 (.A(qgc498c), .Z(fnc8624)); AND2 ir26308 (.A(nt133b8), .B(tw8c221), .Z(dz6110a)); INV ux8857 (.A(of442bd), .Z(tw8c221)); OR2 gqaf61 (.A(je99dc6), .B(gocee32), .Z(vvec21b)); XOR2 nr610df (.A(wl86ff), .B(yk437fc), .Z(pu1bfe1)); XOR2 hodff0b (.A(yk437fc), .B(jpfc2d8), .Z(xwe16c6)); XOR2 xyb633 (.A(jpfc2d8), .B(hbd8cdc), .Z(shc66e6)); XOR2 ux33735 (.A(hbd8cdc), .B(mrdcd6f), .Z(hbe6b7c)); XOR2 zm35be7 (.A(mrdcd6f), .B(ip6f9da), .Z(lq7ced5)); XOR2 she76ab (.A(ip6f9da), .B(nedaae1), .Z(rgd570b)); XOR2 uxab85b (.A(nedaae1), .B(hoe16e9), .Z(zmb74b)); XOR2 cz5ba5b (.A(hoe16e9), .B(nre96ef), .Z(al4b77f)); XOR2 kd5bbfd (.A(nre96ef), .B(ykeff6e), .Z(kd7fb71)); XOR2 gbfdb8c (.A(ykeff6e), .B(dz6e32c), .Z(vv71966)); XOR2 pu8cb37 (.A(al659bb), .B(sj2cddc), .Z(jc66ee4)); XOR2 rv37723 (.A(sj2cddc), .B(gbdc8fc), .Z(jce47e4)); XOR2 qv23f23 (.A(gbdc8fc), .B(hbfc8e9), .Z(lqe474f)); XOR2 gd23a7b (.A(hbfc8e9), .B(hbe9eed), .Z(bl4f76e)); XOR2 th7bb77 (.A(hbe9eed), .B(wjeddf6), .Z(rt6efb4)); XOR2 ea77da7 (.A(wjeddf6), .B(blf69c4), .Z(irb4e26)); XOR2 pua7135 (.A(blf69c4), .B(ayc4d57), .Z(gd26ab9)); XOR2 ri355cd (.A(ayc4d57), .B(dm57357), .Z(gqb9aba)); XOR2 fncd5d1 (.A(dm57357), .B(dm57475), .Z(jrba3aa)); XOR2 ayd1d57 (.A(dm57475), .B(qt755c6), .Z(zzaae34)); defparam rg571a7.initval = 16'h6996 ; ROM16X1 rg571a7 (.AD3(yxc69d3), .AD2(ks34e9c), .AD1(fca74e1), .AD0(fc3a70a), .DO0(wjd3853)) ; defparam hq9c29d.initval = 16'h6996 ; ROM16X1 hq9c29d (.AD3(gqa75b), .AD2(ea53ad9), .AD1(sw9d6c9), .AD0(faeb649), .DO0(kd5b24a)) ; defparam qtd9254.initval = 16'h6996 ; ROM16X1 qtd9254 (.AD3(fca74e1), .AD2(fc3a70a), .AD1(ip54b06), .AD0(ip54b06), .DO0(ux2c1a6)) ; defparam en60d35.initval = 16'h6996 ; ROM16X1 en60d35 (.AD3(ks34e9c), .AD2(fca74e1), .AD1(fc3a70a), .AD0(ip54b06), .DO0(fa66258)) ; defparam ec312c2.initval = 16'h6996 ; ROM16X1 ec312c2 (.AD3(faeb649), .AD2(yxc69d3), .AD1(ks34e9c), .AD0(ux2c1a6), .DO0(mg82af9)) ; defparam sw157c8.initval = 16'h6996 ; ROM16X1 sw157c8 (.AD3(sw9d6c9), .AD2(faeb649), .AD1(yxc69d3), .AD0(fa66258), .DO0(yzddb5)) ; defparam vv6edad.initval = 16'h6996 ; ROM16X1 vv6edad (.AD3(ea53ad9), .AD2(sw9d6c9), .AD1(faeb649), .AD0(wjd3853), .DO0(al7a1d4)) ; defparam hod0ea5.initval = 16'h6996 ; ROM16X1 hod0ea5 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(ip54b06), .AD0(ip54b06), .DO0(en5143a)) ; defparam ux8a1d5.initval = 16'h6996 ; ROM16X1 ux8a1d5 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(tud5b8a), .AD0(ip54b06), .DO0(ld6e292)) ; defparam hb71496.initval = 16'h6996 ; ROM16X1 hb71496 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(xy96d51), .AD0(tud5b8a), .DO0(jrb5458)) ; defparam vxaa2c6.initval = 16'h6996 ; ROM16X1 vxaa2c6 (.AD3(bn8b1b5), .AD2(xy96d51), .AD1(tud5b8a), .AD0(ip54b06), .DO0(xlb5ea4)) ; defparam hdaf527.initval = 16'h6996 ; ROM16X1 hdaf527 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(xlb5ea4), .AD0(ip54b06), .DO0(byf4138)) ; defparam jra09c2.initval = 16'h6996 ; ROM16X1 jra09c2 (.AD3(rv270b3), .AD2(zz3859e), .AD1(xjc2cf6), .AD0(fp167b6), .DO0(wyb3db6)) ; defparam vx9edb0.initval = 16'h6996 ; ROM16X1 vx9edb0 (.AD3(mgb6c3e), .AD2(qib61f0), .AD1(dbb0f81), .AD0(aa87c0f), .DO0(aa3e078)) ; defparam gof03c1.initval = 16'h6996 ; ROM16X1 gof03c1 (.AD3(xjc2cf6), .AD2(fp167b6), .AD1(ip54b06), .AD0(ip54b06), .DO0(rg47205)) ; defparam mt3902b.initval = 16'h6996 ; ROM16X1 mt3902b (.AD3(zz3859e), .AD2(xjc2cf6), .AD1(fp167b6), .AD0(ip54b06), .DO0(pfe6e08)) ; defparam nt37047.initval = 16'h6996 ; ROM16X1 nt37047 (.AD3(aa87c0f), .AD2(rv270b3), .AD1(zz3859e), .AD0(rg47205), .DO0(cmfa153)) ; defparam xwd0a99.initval = 16'h6996 ; ROM16X1 xwd0a99 (.AD3(dbb0f81), .AD2(aa87c0f), .AD1(rv270b3), .AD0(pfe6e08), .DO0(sh5441a)) ; defparam baa20d5.initval = 16'h6996 ; ROM16X1 baa20d5 (.AD3(qib61f0), .AD2(dbb0f81), .AD1(aa87c0f), .AD0(wyb3db6), .DO0(mr5165e)) ; defparam hd8b2f5.initval = 16'h6996 ; ROM16X1 hd8b2f5 (.AD3(wyb3db6), .AD2(aa3e078), .AD1(ip54b06), .AD0(ip54b06), .DO0(fa7914e)) ; defparam thc8a72.initval = 16'h6996 ; ROM16X1 thc8a72 (.AD3(wyb3db6), .AD2(aa3e078), .AD1(ww72fa5), .AD0(ip54b06), .DO0(cbbe941)) ; defparam tuf4a0c.initval = 16'h6996 ; ROM16X1 tuf4a0c (.AD3(wyb3db6), .AD2(aa3e078), .AD1(phc7fd), .AD0(ww72fa5), .DO0(gq1ff73)) ; defparam meffb99.initval = 16'h6996 ; ROM16X1 meffb99 (.AD3(byee645), .AD2(phc7fd), .AD1(ww72fa5), .AD0(ip54b06), .DO0(th454df)) ; defparam xy2a6fe.initval = 16'h6996 ; ROM16X1 xy2a6fe (.AD3(wyb3db6), .AD2(aa3e078), .AD1(th454df), .AD0(ip54b06), .DO0(yz90edd)) ; XOR2 sw876ec (.A(dz6e32c), .B(fp167b6), .Z(xjdd849)); XOR2 rtec24e (.A(fc3a70a), .B(qt755c6), .Z(me49dfe)); defparam cz4eff1.initval = 16'h0410 ; ROM16X1 cz4eff1 (.AD3(fpbfc60), .AD2(qt755c6), .AD1(fc3a70a), .AD0(ip54b06), .DO0(en60cda)) ; defparam zz66d4.initval = 16'h1004 ; ROM16X1 zz66d4 (.AD3(fpbfc60), .AD2(qt755c6), .AD1(fc3a70a), .AD0(ip54b06), .DO0(db3dcc3)) ; defparam faee61f.initval = 16'h0140 ; ROM16X1 faee61f (.AD3(wy987d3), .AD2(dz6e32c), .AD1(fp167b6), .AD0(ip54b06), .DO0(ipd3301)) ; defparam vk9980c.initval = 16'h4001 ; ROM16X1 vk9980c (.AD3(wy987d3), .AD2(dz6e32c), .AD1(fp167b6), .AD0(ip54b06), .DO0(ba14af1)) ; INV tja578a (.A(qi2bc57), .Z(yx5e2b9)); AND2 xwf15cc (.A(cb8ae62), .B(yx5e2b9), .Z(ukb98a2)); AND2 mrcc511 (.A(cb8ae62), .B(qi2bc57), .Z(doa230b)); defparam pu1185a.CSDECODE_R = 3'b000 ; defparam pu1185a.CSDECODE_W = 3'b000 ; defparam pu1185a.GSR = "ENABLED" ; defparam pu1185a.RESETMODE = "ASYNC" ; defparam pu1185a.REGMODE = "NOREG" ; defparam pu1185a.DATA_WIDTH_R = 18 ; defparam pu1185a.DATA_WIDTH_W = 18 ; PDP16KA pu1185a (.DI0(icdbb13[0]), .DI1(icdbb13[1]), .DI2(icdbb13[2]), .DI3(icdbb13[3]), .DI4(icdbb13[4]), .DI5(icdbb13[5]), .DI6(icdbb13[6]), .DI7(icdbb13[7]), .DI8(icdbb13[8]), .DI9(icdbb13[9]), .DI10(icdbb13[10]), .DI11(icdbb13[11]), .DI12(icdbb13[12]), .DI13(icdbb13[13]), .DI14(icdbb13[14]), .DI15(icdbb13[15]), .DI16(icdbb13[16]), .DI17(icdbb13[17]), .DI18(icdbb13[0]), .DI19(icdbb13[1]), .DI20(icdbb13[2]), .DI21(icdbb13[3]), .DI22(icdbb13[4]), .DI23(icdbb13[5]), .DI24(icdbb13[6]), .DI25(icdbb13[7]), .DI26(icdbb13[8]), .DI27(icdbb13[9]), .DI28(icdbb13[10]), .DI29(icdbb13[11]), .DI30(icdbb13[12]), .DI31(icdbb13[13]), .DI32(icdbb13[14]), .DI33(icdbb13[15]), .DI34(icdbb13[16]), .DI35(icdbb13[17]), .ADW0(vve93e5), .ADW1(vve93e5), .ADW2(ip54b06), .ADW3(ip54b06), .ADW4(uie5e73), .ADW5(vk2f398), .ADW6(ho79cc2), .ADW7(kqce613), .ADW8(lq73099), .ADW9(mg984cb), .ADW10(ldc2659), .ADW11(rv132cf), .ADW12(pu9967e), .ADW13(gocb3f3), .CEW(su43126), .CLKW(fndd899), .WE(vve93e5), .CSW0(ip54b06), .CSW1(ip54b06), .CSW2(ip54b06), .ADR0(ip54b06), .ADR1(ip54b06), .ADR2(ip54b06), .ADR3(ip54b06), .ADR4(icde57a), .ADR5(alf2bd0), .ADR6(an95e84), .ADR7(lfaf424), .ADR8(gb7a126), .ADR9(dmd0935), .ADR10(jr849aa), .ADR11(ym24d57), .ADR12(cb26ab8), .ADR13(ls355c5), .CER(dz6110a), .CLKR(dzec4ce), .CSR0(ip54b06), .CSR1(ip54b06), .CSR2(ip54b06), .RST(je99dc6), .DO0(gbc640b[0]), .DO1(gbc640b[1]), .DO2(gbc640b[2]), .DO3(gbc640b[3]), .DO4(gbc640b[4]), .DO5(gbc640b[5]), .\r
-DO6(gbc640b[6]), .DO7(gbc640b[7]), .DO8(gbc640b[8]), .DO9(gbc640b[9]), .DO10(gbc640b[10]), .DO11(gbc640b[11]), .DO12(gbc640b[12]), .DO13(gbc640b[13]), .DO14(gbc640b[14]), .DO15(gbc640b[15]), .DO16(gbc640b[16]), .DO17(gbc640b[17]), .DO18(), .DO19(), .DO20(), .DO21(), .DO22(), .DO23(), .DO24(), .DO25(), .DO26(), .DO27(), .DO28(), .DO29(), .DO30(), .DO31(), .DO32(), .DO33(), .DO34(), .DO35()) ; defparam mt9f303.GSR = "ENABLED" ; FD1P3BX mt9f303 (.D(mrcc0e7), .SP(su43126), .CK(fndd899), .PD(je99dc6), .Q(wl86ff)) ; defparam kf3cbb5.GSR = "ENABLED" ; FD1P3DX kf3cbb5 (.D(co2ed68), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(yk437fc)) ; defparam of415d9.GSR = "ENABLED" ; FD1P3DX of415d9 (.D(rg57660), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(jpfc2d8)) ; defparam ir2b25.GSR = "ENABLED" ; FD1P3DX ir2b25 (.D(aaac960), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hbd8cdc)) ; defparam gqcad.GSR = "ENABLED" ; FD1P3DX gqcad (.D(fp32b4f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(mrdcd6f)) ; defparam rt7e8d6.GSR = "ENABLED" ; FD1P3DX rt7e8d6 (.D(swa35b2), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ip6f9da)) ; defparam gd9034b.GSR = "ENABLED" ; FD1P3DX gd9034b (.D(qvd2ef), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(nedaae1)) ; defparam ps7c711.GSR = "ENABLED" ; FD1P3DX ps7c711 (.D(jr1c457), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hoe16e9)) ; defparam vxbf8e3.GSR = "ENABLED" ; FD1P3DX vxbf8e3 (.D(lde38f6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(nre96ef)) ; defparam lsb7fde.GSR = "ENABLED" ; FD1P3DX lsb7fde (.D(meff796), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ykeff6e)) ; defparam kfb1422.GSR = "ENABLED" ; FD1P3DX kfb1422 (.D(bl508a5), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(dz6e32c)) ; defparam aa2edd6.GSR = "ENABLED" ; FD1P3DX aa2edd6 (.D(pu1bfe1), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(oh8a7a4)) ; defparam qg53d25.GSR = "ENABLED" ; FD1P3DX qg53d25 (.D(xwe16c6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ld4f71c)) ; defparam vv7b8e7.GSR = "ENABLED" ; FD1P3DX vv7b8e7 (.D(shc66e6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(uif5fa8)) ; defparam jrafd41.GSR = "ENABLED" ; FD1P3DX jrafd41 (.D(hbe6b7c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(jp7e0e8)) ; defparam ayf0747.GSR = "ENABLED" ; FD1P3DX ayf0747 (.D(lq7ced5), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hbc2b1e)) ; defparam ec158f6.GSR = "ENABLED" ; FD1P3DX ec158f6 (.D(rgd570b), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(rv816fe)) ; defparam hqb7f6.GSR = "ENABLED" ; FD1P3DX hqb7f6 (.D(zmb74b), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(co9d6b8)) ; defparam hoeb5c1.GSR = "ENABLED" ; FD1P3DX hoeb5c1 (.D(al4b77f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(xw57c80)) ; defparam qvbe403.GSR = "ENABLED" ; FD1P3DX qvbe403 (.D(kd7fb71), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(gbedb34)) ; defparam qg6d9a4.GSR = "ENABLED" ; FD1P3DX qg6d9a4 (.D(vv71966), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ep266b)) ; defparam nt1335d.GSR = "ENABLED" ; FD1P3DX nt1335d (.D(dz6e32c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ay72dd2)) ; defparam zm96e90.GSR = "ENABLED" ; FD1P3DX zm96e90 (.D(wl86ff), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(uie5e73)) ; defparam vidfd5b.GSR = "ENABLED" ; FD1P3DX vidfd5b (.D(yk437fc), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(vk2f398)) ; defparam hod0902.GSR = "ENABLED" ; FD1P3DX hod0902 (.D(jpfc2d8), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ho79cc2)) ; defparam mgb9768.GSR = "ENABLED" ; FD1P3DX mgb9768 (.D(hbd8cdc), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(kqce613)) ; defparam mt2a70.GSR = "ENABLED" ; FD1P3DX mt2a70 (.D(mrdcd6f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(lq73099)) ; defparam yz8b71.GSR = "ENABLED" ; FD1P3DX yz8b71 (.D(ip6f9da), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(mg984cb)) ; defparam fn7edcd.GSR = "ENABLED" ; FD1P3DX fn7edcd (.D(nedaae1), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ldc2659)) ; defparam qib33fb.GSR = "ENABLED" ; FD1P3DX qib33fb (.D(hoe16e9), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(rv132cf)) ; defparam vi52aeb.GSR = "ENABLED" ; FD1P3DX vi52aeb (.D(nre96ef), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(pu9967e)) ; defparam czed6ae.GSR = "ENABLED" ; FD1P3DX czed6ae (.D(ykeff6e), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(gocb3f3)) ; defparam ea7756d.GSR = "ENABLED" ; FD1P3DX ea7756d (.D(dz6e32c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(wy987d3)) ; defparam ic72455.GSR = "ENABLED" ; FD1P3BX ic72455 (.D(tj91548), .SP(dz6110a), .CK(dzec4ce), .PD(vvec21b), .Q(al659bb)) ; defparam vi479cb.GSR = "ENABLED" ; FD1P3DX vi479cb (.D(qte72d5), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(sj2cddc)) ; defparam qiac87a.GSR = "ENABLED" ; FD1P3DX qiac87a (.D(gq21e87), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gbdc8fc)) ; defparam jr38351.GSR = "ENABLED" ; FD1P3DX jr38351 (.D(and471), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(hbfc8e9)) ; defparam ba8c93f.GSR = "ENABLED" ; FD1P3DX ba8c93f (.D(mg24fde), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(hbe9eed)) ; defparam uif0ed0.GSR = "ENABLED" ; FD1P3DX uif0ed0 (.D(aa3b409), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(wjeddf6)) ; defparam ui494f6.GSR = "ENABLED" ; FD1P3DX ui494f6 (.D(su53d87), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(blf69c4)) ; defparam yz39ff9.GSR = "ENABLED" ; FD1P3DX yz39ff9 (.D(mr7fe6a), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ayc4d57)) ; defparam al543f5.GSR = "ENABLED" ; FD1P3DX al543f5 (.D(ymfd6c), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dm57357)) ; defparam kd60c53.GSR = "ENABLED" ; FD1P3DX kd60c53 (.D(qi314e7), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dm57475)) ; defparam nt38a54.GSR = "ENABLED" ; FD1P3DX nt38a54 (.D(gd2953a), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(qt755c6)) ; defparam byd5d12.GSR = "ENABLED" ; FD1P3DX byd5d12 (.D(jc66ee4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(sj95ca1)) ; defparam yzae50c.GSR = "ENABLED" ; FD1P3DX yzae50c (.D(jce47e4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ls20f3f)) ; defparam cb79fa.GSR = "ENABLED" ; FD1P3DX cb79fa (.D(lqe474f), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(fpa5ac0)) ; defparam hd2d606.GSR = "ENABLED" ; FD1P3DX hd2d606 (.D(bl4f76e), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(uxbe6f6)) ; defparam nrf37b5.GSR = "ENABLED" ; FD1P3DX nrf37b5 (.D(rt6efb4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ip7f3bf)) ; defparam vvf9dfd.GSR = "ENABLED" ; FD1P3DX vvf9dfd (.D(irb4e26), \r
-.SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ww781a8)) ; defparam xwc0d40.GSR = "ENABLED" ; FD1P3DX xwc0d40 (.D(gd26ab9), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ba1e4f6)) ; defparam wjf27b2.GSR = "ENABLED" ; FD1P3DX wjf27b2 (.D(gqb9aba), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gdabfd5)) ; defparam xj5fead.GSR = "ENABLED" ; FD1P3DX xj5fead (.D(jrba3aa), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ps79094)) ; defparam vvc84a2.GSR = "ENABLED" ; FD1P3DX vvc84a2 (.D(zzaae34), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gqb3bde)) ; defparam uk9def0.GSR = "ENABLED" ; FD1P3DX uk9def0 (.D(qt755c6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gqc04)) ; defparam db6021.GSR = "ENABLED" ; FD1P3DX db6021 (.D(al659bb), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(icde57a)) ; defparam rgd540c.GSR = "ENABLED" ; FD1P3DX rgd540c (.D(sj2cddc), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(alf2bd0)) ; defparam enf7f9b.GSR = "ENABLED" ; FD1P3DX enf7f9b (.D(gbdc8fc), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(an95e84)) ; defparam cb33fe6.GSR = "ENABLED" ; FD1P3DX cb33fe6 (.D(hbfc8e9), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(lfaf424)) ; defparam xl28fcf.GSR = "ENABLED" ; FD1P3DX xl28fcf (.D(hbe9eed), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gb7a126)) ; defparam ls93ebd.GSR = "ENABLED" ; FD1P3DX ls93ebd (.D(wjeddf6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dmd0935)) ; defparam wwe0e99.GSR = "ENABLED" ; FD1P3DX wwe0e99 (.D(blf69c4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(jr849aa)) ; defparam uk2b8fe.GSR = "ENABLED" ; FD1P3DX uk2b8fe (.D(ayc4d57), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ym24d57)) ; defparam rt4f2d3.GSR = "ENABLED" ; FD1P3DX rt4f2d3 (.D(dm57357), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(cb26ab8)) ; defparam osd1d61.GSR = "ENABLED" ; FD1P3DX osd1d61 (.D(dm57475), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ls355c5)) ; defparam ba353e8.GSR = "ENABLED" ; FD1P3DX ba353e8 (.D(qt755c6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(fpbfc60)) ; defparam xy86158.GSR = "ENABLED" ; FD1S3DX xy86158 (.D(oh8a7a4), .CK(dzec4ce), .CD(je99dc6), .Q(shc3703)) ; defparam tw1b81d.GSR = "ENABLED" ; FD1S3DX tw1b81d (.D(ld4f71c), .CK(dzec4ce), .CD(je99dc6), .Q(neeba75)) ; defparam zk5d3ab.GSR = "ENABLED" ; FD1S3DX zk5d3ab (.D(uif5fa8), .CK(dzec4ce), .CD(je99dc6), .Q(uv5bd24)) ; defparam uide925.GSR = "ENABLED" ; FD1S3DX uide925 (.D(jp7e0e8), .CK(dzec4ce), .CD(je99dc6), .Q(oh29703)) ; defparam ip4b81d.GSR = "ENABLED" ; FD1S3DX ip4b81d (.D(hbc2b1e), .CK(dzec4ce), .CD(je99dc6), .Q(nrec274)) ; defparam bl613a7.GSR = "ENABLED" ; FD1S3DX bl613a7 (.D(rv816fe), .CK(dzec4ce), .CD(je99dc6), .Q(pu3ff3b)) ; defparam suff9da.GSR = "ENABLED" ; FD1S3DX suff9da (.D(co9d6b8), .CK(dzec4ce), .CD(je99dc6), .Q(vid0f0a)) ; defparam uk87852.GSR = "ENABLED" ; FD1S3DX uk87852 (.D(xw57c80), .CK(dzec4ce), .CD(je99dc6), .Q(sj908ca)) ; defparam zz84654.GSR = "ENABLED" ; FD1S3DX zz84654 (.D(gbedb34), .CK(dzec4ce), .CD(je99dc6), .Q(yma69d4)) ; defparam ec34ea1.GSR = "ENABLED" ; FD1S3DX ec34ea1 (.D(ep266b), .CK(dzec4ce), .CD(je99dc6), .Q(tj948d)) ; defparam dz4a46e.GSR = "ENABLED" ; FD1S3DX dz4a46e (.D(ay72dd2), .CK(dzec4ce), .CD(je99dc6), .Q(kq7758f)) ; defparam hdbac79.GSR = "ENABLED" ; FD1S3DX hdbac79 (.D(sj95ca1), .CK(fndd899), .CD(vvec21b), .Q(cmce96b)) ; defparam xj74b58.GSR = "ENABLED" ; FD1S3DX xj74b58 (.D(ls20f3f), .CK(fndd899), .CD(vvec21b), .Q(ldc7df2)) ; defparam ks3ef96.GSR = "ENABLED" ; FD1S3DX ks3ef96 (.D(fpa5ac0), .CK(fndd899), .CD(vvec21b), .Q(bnb0962)) ; defparam nt84b17.GSR = "ENABLED" ; FD1S3DX nt84b17 (.D(uxbe6f6), .CK(fndd899), .CD(vvec21b), .Q(phbf54d)) ; defparam wwfaa6f.GSR = "ENABLED" ; FD1S3DX wwfaa6f (.D(ip7f3bf), .CK(fndd899), .CD(vvec21b), .Q(go7861c)) ; defparam alc30e0.GSR = "ENABLED" ; FD1S3DX alc30e0 (.D(ww781a8), .CK(fndd899), .CD(vvec21b), .Q(qi5b38)) ; defparam fp2d9c1.GSR = "ENABLED" ; FD1S3DX fp2d9c1 (.D(ba1e4f6), .CK(fndd899), .CD(vvec21b), .Q(hqe431)) ; defparam me7218b.GSR = "ENABLED" ; FD1S3DX me7218b (.D(gdabfd5), .CK(fndd899), .CD(vvec21b), .Q(os598c7)) ; defparam wjcc638.GSR = "ENABLED" ; FD1S3DX wjcc638 (.D(ps79094), .CK(fndd899), .CD(vvec21b), .Q(goc453f)) ; defparam zz229f8.GSR = "ENABLED" ; FD1S3DX zz229f8 (.D(gqb3bde), .CK(fndd899), .CD(vvec21b), .Q(thc74dd)) ; defparam ba3a6ef.GSR = "ENABLED" ; FD1S3DX ba3a6ef (.D(gqc04), .CK(fndd899), .CD(vvec21b), .Q(pf7b9f0)) ; defparam uvdcf86.GSR = "ENABLED" ; FD1S3DX uvdcf86 (.D(shc3703), .CK(dzec4ce), .CD(je99dc6), .Q(bn8b1b5)) ; defparam bna5251.GSR = "ENABLED" ; FD1S3DX bna5251 (.D(neeba75), .CK(dzec4ce), .CD(je99dc6), .Q(xy96d51)) ; defparam ww7d1e4.GSR = "ENABLED" ; FD1S3DX ww7d1e4 (.D(uv5bd24), .CK(dzec4ce), .CD(je99dc6), .Q(tud5b8a)) ; defparam ls455a.GSR = "ENABLED" ; FD1S3DX ls455a (.D(oh29703), .CK(dzec4ce), .CD(je99dc6), .Q(gqa75b)) ; defparam ec97337.GSR = "ENABLED" ; FD1S3DX ec97337 (.D(nrec274), .CK(dzec4ce), .CD(je99dc6), .Q(ea53ad9)) ; defparam mec1afa.GSR = "ENABLED" ; FD1S3DX mec1afa (.D(pu3ff3b), .CK(dzec4ce), .CD(je99dc6), .Q(sw9d6c9)) ; defparam pu8cf88.GSR = "ENABLED" ; FD1S3DX pu8cf88 (.D(vid0f0a), .CK(dzec4ce), .CD(je99dc6), .Q(faeb649)) ; defparam ph19281.GSR = "ENABLED" ; FD1S3DX ph19281 (.D(sj908ca), .CK(dzec4ce), .CD(je99dc6), .Q(yxc69d3)) ; defparam fa7cff8.GSR = "ENABLED" ; FD1S3DX fa7cff8 (.D(yma69d4), .CK(dzec4ce), .CD(je99dc6), .Q(ks34e9c)) ; defparam mt1d464.GSR = "ENABLED" ; FD1S3DX mt1d464 (.D(tj948d), .CK(dzec4ce), .CD(je99dc6), .Q(fca74e1)) ; defparam tj288f3.GSR = "ENABLED" ; FD1S3DX tj288f3 (.D(kq7758f), .CK(dzec4ce), .CD(je99dc6), .Q(fc3a70a)) ; defparam byf4ab7.GSR = "ENABLED" ; FD1S3DX byf4ab7 (.D(cmce96b), .CK(fndd899), .CD(vvec21b), .Q(byee645)) ; defparam hodf65c.GSR = "ENABLED" ; FD1S3DX hodf65c (.D(ldc7df2), .CK(fndd899), .CD(vvec21b), .Q(phc7fd)) ; defparam tj13a0c.GSR = "ENABLED" ; FD1S3DX tj13a0c (.D(bnb0962), .CK(fndd899), .CD(vvec21b), .Q(ww72fa5)) ; defparam oh39b78.GSR = "ENABLED" ; FD1S3DX oh39b78 (.D(phbf54d), .CK(fndd899), .CD(vvec21b), .Q(mgb6c3e)) ; defparam je2f10b.GSR = "ENABLED" ; FD1S3DX je2f10b (.D(go7861c), .CK(fndd899), .CD(vvec21b), .Q(qib61f0)) ; defparam cmd105e.GSR = "ENABLED" ; FD1S3DX cmd105e (.D(qi5b38), .CK(fndd899), .CD(vvec21b), .Q(dbb0f81)) ; defparam gq888a2.GSR = "ENABLED" ; FD1S3DX gq888a2 (.D(hqe431), .CK(fndd899), .CD(vvec21b), .Q(aa87c0f)) ; defparam pu8ced2.GSR = "ENABLED" ; FD1S3DX pu8ced2 (.D(os598c7), .CK(fndd899), .CD(vvec21b), .Q(rv270b3)) ; defparam wy982b2.GSR = "ENABLED" ; FD1S3DX wy982b2 (.D(goc453f), .CK(fndd899), .CD(vvec21b), .Q(zz3859e)) ; defparam aa8801f.GSR = "ENABLED" ; FD1S3DX aa8801f (.D(thc74dd), .CK(fndd899), .\r
-CD(vvec21b), .Q(xjc2cf6)) ; defparam wjc6185.GSR = "ENABLED" ; FD1S3DX wjc6185 (.D(pf7b9f0), .CK(fndd899), .CD(vvec21b), .Q(fp167b6)) ; defparam vv6b6ef.GSR = "ENABLED" ; FD1S3BX vv6b6ef (.D(ykdbbf4), .CK(dzec4ce), .PD(vvec21b), .Q(of442bd)) ; defparam byf438e.GSR = "ENABLED" ; FD1S3DX byf438e (.D(doe394), .CK(fndd899), .CD(je99dc6), .Q(qgc498c)) ; defparam bn947f8.GSR = "ENABLED" ; FD1S3BX bn947f8 (.D(ym1fe39), .CK(dzec4ce), .PD(vvec21b), .Q(fp8177d)) ; defparam sj3926f.GSR = "ENABLED" ; FD1S3DX sj3926f (.D(su49be4), .CK(fndd899), .CD(je99dc6), .Q(pubbee)) ; CU2 nee42eb (.CI(vve93e5), .PC1(yk437fc), .PC0(wl86ff), .CO(tueb653), .NC1(co2ed68), .NC0(mrcc0e7)); CU2 hoca6a5 (.CI(tueb653), .PC1(hbd8cdc), .PC0(jpfc2d8), .CO(hda5628), .NC1(aaac960), .NC0(rg57660)); CU2 byc51c2 (.CI(hda5628), .PC1(ip6f9da), .PC0(mrdcd6f), .CO(rtc259e), .NC1(swa35b2), .NC0(fp32b4f)); CU2 wyb3dea (.CI(rtc259e), .PC1(hoe16e9), .PC0(nedaae1), .CO(qgea1e2), .NC1(jr1c457), .NC0(qvd2ef)); CU2 gd3c430 (.CI(qgea1e2), .PC1(ykeff6e), .PC0(nre96ef), .CO(je30903), .NC1(meff796), .NC0(lde38f6)); CU2 pu206f9 (.CI(je30903), .PC1(ip54b06), .PC0(dz6e32c), .CO(dzf97da), .NC1(), .NC0(bl508a5)); CU2 hb5f6b0 (.CI(vve93e5), .PC1(sj2cddc), .PC0(al659bb), .CO(zzb0cdc), .NC1(qte72d5), .NC0(tj91548)); CU2 tj9b9dd (.CI(zzb0cdc), .PC1(hbfc8e9), .PC0(gbdc8fc), .CO(hbddf20), .NC1(and471), .NC0(gq21e87)); CU2 jce418b (.CI(hbddf20), .PC1(wjeddf6), .PC0(hbe9eed), .CO(lf8b6b8), .NC1(aa3b409), .NC0(mg24fde)); CU2 zxd71e3 (.CI(lf8b6b8), .PC1(ayc4d57), .PC0(blf69c4), .CO(rte3cf4), .NC1(mr7fe6a), .NC0(su53d87)); CU2 db9e9d6 (.CI(rte3cf4), .PC1(dm57475), .PC0(dm57357), .CO(end6ed2), .NC1(qi314e7), .NC0(ymfd6c)); CU2 hoda55d (.CI(end6ed2), .PC1(ip54b06), .PC0(qt755c6), .CO(xw5d5ed), .NC1(), .NC0(gd2953a)); FSUB2 ne57b59 (.A1(yk437fc), .A0(wl86ff), .B1(gq1ff73), .B0(yz90edd), .BI(vve93e5), .BOUT1(of5bb89), .BOUT0(), .S1(blddc4d), .S0(viee26e)); FSUB2 jp71372 (.A1(hbd8cdc), .A0(jpfc2d8), .B1(fa7914e), .B0(cbbe941), .BI(of5bb89), .BOUT1(oub3782), .BOUT0(), .S1(nt9bc11), .S0(qgde08f)); FSUB2 kqf0478 (.A1(ip6f9da), .A0(mrdcd6f), .B1(sh5441a), .B0(mr5165e), .BI(oub3782), .BOUT1(hq1542), .BOUT0(), .S1(ecaa12), .S0(nr55090)); FSUB2 nga8487 (.A1(hoe16e9), .A0(nedaae1), .B1(wyb3db6), .B0(cmfa153), .BI(hq1542), .BOUT1(aydb909), .BOUT0(), .S1(shdc849), .S0(bye424c)); FSUB2 co21263 (.A1(ykeff6e), .A0(nre96ef), .B1(rg47205), .B0(pfe6e08), .BI(aydb909), .BOUT1(icce216), .BOUT0(), .S1(xj710b1), .S0(aa8858e)); FSUB2 fa42c70 (.A1(ip54b06), .A0(xjdd849), .B1(ip54b06), .B0(ip54b06), .BI(icce216), .BOUT1(), .BOUT0(), .S1(), .S0(fp16be0)); VHI dbb5f07 (.Z(vve93e5)); FSUB2 xw7c1ff (.A1(jrb5458), .A0(byf4138), .B1(sj2cddc), .B0(al659bb), .BI(vve93e5), .BOUT1(rgd0889), .BOUT0(), .S1(rv8444a), .S0(jr22256)); FSUB2 ls112b6 (.A1(en5143a), .A0(ld6e292), .B1(hbfc8e9), .B0(gbdc8fc), .BI(rgd0889), .BOUT1(yz9ac49), .BOUT0(), .S1(czd624d), .S0(anb126c)); FSUB2 zm89364 (.A1(yzddb5), .A0(al7a1d4), .B1(wjeddf6), .B0(hbe9eed), .BI(yz9ac49), .BOUT1(fc116be), .BOUT0(), .S1(db8b5f3), .S0(jp5af9f)); FSUB2 nrd7cff (.A1(wjd3853), .A0(mg82af9), .B1(ayc4d57), .B0(blf69c4), .BI(fc116be), .BOUT1(ipfdd40), .BOUT0(), .S1(tueea05), .S0(wj7502b)); FSUB2 twa815c (.A1(ux2c1a6), .A0(fa66258), .B1(dm57475), .B0(dm57357), .BI(ipfdd40), .BOUT1(ym1f04f), .BOUT0(), .S1(qi2bc57), .S0(mec13c4)); FSUB2 vx9e20 (.A1(ip54b06), .A0(me49dfe), .B1(ip54b06), .B0(ip54b06), .BI(ym1f04f), .BOUT1(), .BOUT0(), .S1(), .S0(cb8ae62)); AGEB2 zxf90a3 (.A1(sj2cddc), .A0(al659bb), .B1(jrb5458), .B0(byf4138), .CI(dz6110a), .GE(fnf64cb)); AGEB2 rib265f (.A1(hbfc8e9), .A0(gbdc8fc), .B1(en5143a), .B0(ld6e292), .CI(fnf64cb), .GE(fada633)); AGEB2 czd319a (.A1(wjeddf6), .A0(hbe9eed), .B1(yzddb5), .B0(al7a1d4), .CI(fada633), .GE(lfa0b69)); AGEB2 aa5b4e (.A1(ayc4d57), .A0(blf69c4), .B1(wjd3853), .B0(mg82af9), .CI(lfa0b69), .GE(zz8e2af)); AGEB2 dz7157f (.A1(dm57475), .A0(dm57357), .B1(ux2c1a6), .B0(fa66258), .CI(zz8e2af), .GE(vif4de2)); AGEB2 oua6f13 (.A1(ip54b06), .A0(en60cda), .B1(ip54b06), .B0(db3dcc3), .CI(vif4de2), .GE(goce132)); FADD2 gb70991 (.A1(ip54b06), .A0(ip54b06), .B1(ip54b06), .B0(ip54b06), .CI(goce132), .COUT1(), .COUT0(), .S1(), .S0(ykdbbf4)); AGEB2 tu7cf8d (.A1(yk437fc), .A0(wl86ff), .B1(gq1ff73), .B0(yz90edd), .CI(su43126), .GE(xw5d2c7)); AGEB2 vve963b (.A1(hbd8cdc), .A0(jpfc2d8), .B1(fa7914e), .B0(cbbe941), .CI(xw5d2c7), .GE(kdfd5c3)); AGEB2 eaeae1c (.A1(ip6f9da), .A0(mrdcd6f), .B1(sh5441a), .B0(mr5165e), .CI(kdfd5c3), .GE(oua53b)); AGEB2 rg529d9 (.A1(hoe16e9), .A0(nedaae1), .B1(wyb3db6), .B0(cmfa153), .CI(oua53b), .GE(gb5e468)); AGEB2 kdf2344 (.A1(ykeff6e), .A0(nre96ef), .B1(rg47205), .B0(pfe6e08), .CI(gb5e468), .GE(ou2e02a)); AGEB2 en70150 (.A1(ip54b06), .A0(ipd3301), .B1(ip54b06), .B0(ba14af1), .CI(ou2e02a), .GE(xy250b7)); FADD2 zz285bb (.A1(ip54b06), .A0(ip54b06), .B1(ip54b06), .B0(ip54b06), .CI(xy250b7), .COUT1(), .COUT0(), .S1(), .S0(doe394)); AGEB2 vvd7710 (.A1(ay77190[1]), .A0(ay77190[0]), .B1(rv8444a), .B0(jr22256), .CI(dz6110a), .GE(ou34b02)); AGEB2 nta5811 (.A1(ay77190[3]), .A0(ay77190[2]), .B1(czd624d), .B0(anb126c), .CI(ou34b02), .GE(sh75b56)); AGEB2 riadab5 (.A1(ay77190[5]), .A0(ay77190[4]), .B1(db8b5f3), .B0(jp5af9f), .CI(sh75b56), .GE(sh51a76)); AGEB2 wy8d3b4 (.A1(ay77190[7]), .A0(ay77190[6]), .B1(tueea05), .B0(wj7502b), .CI(sh51a76), .GE(ep28a7)); AGEB2 hq1453c (.A1(ay77190[9]), .A0(ay77190[8]), .B1(qi2bc57), .B0(mec13c4), .CI(ep28a7), .GE(do1b4e6)); AGEB2 lqda732 (.A1(ip54b06), .A0(doa230b), .B1(ip54b06), .B0(ukb98a2), .CI(do1b4e6), .GE(sj955b9)); FADD2 dbaadcd (.A1(ip54b06), .A0(ip54b06), .B1(ip54b06), .B0(ip54b06), .CI(sj955b9), .COUT1(), .COUT0(), .S1(), .S0(ym1fe39)); AGEB2 qgcb3e2 (.A1(blddc4d), .A0(viee26e), .B1(dob8c81[1]), .B0(dob8c81[0]), .CI(su43126), .GE(wy884a3)); AGEB2 zk42518 (.A1(nt9bc11), .A0(qgde08f), .B1(dob8c81[3]), .B0(dob8c81[2]), .CI(wy884a3), .GE(sj1de2c)); AGEB2 ayef164 (.A1(ecaa12), .A0(nr55090), .B1(dob8c81[5]), .B0(dob8c81[4]), .CI(sj1de2c), .GE(zm173b)); AGEB2 twb9da (.A1(shdc849), .A0(bye424c), .B1(dob8c81[7]), .B0(dob8c81[6]), .CI(zm173b), .GE(wl90856)); AGEB2 fp842b4 (.A1(xj710b1), .A0(aa8858e), .B1(dob8c81[9]), .B0(dob8c81[8]), .CI(wl90856), .GE(ou31068)); AGEB2 gq88340 (.A1(ip54b06), .A0(fp16be0), .B1(ip54b06), .B0(ip54b06), .CI(ou31068), .GE(gq5871)); VLO cb2c389 (.Z(ip54b06)); FADD2 xye26e (.A1(ip54b06), .A0(ip54b06), .B1(ip54b06), .B0(ip54b06), .CI(gq5871), .COUT1(), .COUT0(), .S1(), .S0(su49be4)); assign db3205d = of442bd; assign cb902ef = qgc498c;\r
- \r
-always@* begin hqbd2d7<={icdbb13>>1,nrf6ece[0]};jpe96ba<=nrf6ece[1];uv4b5d7<=nrf6ece[2];pf5aebd<=nrf6ece[3];jpd75ef<=nrf6ece[4];fpbaf7e<=nrf6ece[5];thd7bf6<=nrf6ece[6];jebdfb7<={ay77190>>1,nrf6ece[7]};ayefdbb<={dob8c81>>1,nrf6ece[8]};end\r
-always@* begin bl7edd9[2047]<=fndd899;bl7edd9[2046]<=dzec4ce;bl7edd9[2044]<=ww62677;bl7edd9[2040]<=nt133b8;bl7edd9[2032]<=je99dc6;bl7edd9[2016]<=gocee32;bl7edd9[1984]<=ay77190[0];bl7edd9[1920]<=dob8c81[0];bl7edd9[1023]<=icdbb13[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module rg69299 (icdbb13, fndd899, dzec4ce, ww62677, nt133b8, je99dc6, \r
- gocee32, ay77190, dob8c81, gbc640b, db3205d, cb902ef, fp8177d, \r
- pubbee);\r
-input [17:0] icdbb13;\r
-input fndd899;\r
-input dzec4ce;\r
-input ww62677;\r
-input nt133b8;\r
-input je99dc6;\r
-input gocee32;\r
-input [9:0] ay77190;\r
-input [9:0] dob8c81;\r
-output [17:0] gbc640b;\r
-output db3205d;\r
-output cb902ef;\r
-output fp8177d;\r
-output pubbee;\r
-reg [17 : 0] hqbd2d7;\r
-reg jpe96ba;\r
-reg uv4b5d7;\r
-reg pf5aebd;\r
-reg jpd75ef;\r
-reg fpbaf7e;\r
-reg thd7bf6;\r
-reg [9 : 0] jebdfb7;\r
-reg [9 : 0] ayefdbb;\r
-reg [2047:0] bl7edd9;\r
-wire [8:0] nrf6ece;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam zmb7676 = 9,wlbb3b3 = 32'hfdffc68b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-AND2 ofe7218 (.A(ww62677), .B(fnc8624), .Z(su43126)); INV ux18931 (.A(qgc498c), .Z(fnc8624)); AND2 ir26308 (.A(nt133b8), .B(tw8c221), .Z(dz6110a)); INV ux8857 (.A(of442bd), .Z(tw8c221)); OR2 gqaf61 (.A(je99dc6), .B(gocee32), .Z(vvec21b)); XOR2 nr610df (.A(wl86ff), .B(yk437fc), .Z(pu1bfe1)); XOR2 hodff0b (.A(yk437fc), .B(jpfc2d8), .Z(xwe16c6)); XOR2 xyb633 (.A(jpfc2d8), .B(hbd8cdc), .Z(shc66e6)); XOR2 ux33735 (.A(hbd8cdc), .B(mrdcd6f), .Z(hbe6b7c)); XOR2 zm35be7 (.A(mrdcd6f), .B(ip6f9da), .Z(lq7ced5)); XOR2 she76ab (.A(ip6f9da), .B(nedaae1), .Z(rgd570b)); XOR2 uxab85b (.A(nedaae1), .B(hoe16e9), .Z(zmb74b)); XOR2 cz5ba5b (.A(hoe16e9), .B(nre96ef), .Z(al4b77f)); XOR2 kd5bbfd (.A(nre96ef), .B(ykeff6e), .Z(kd7fb71)); XOR2 gbfdb8c (.A(ykeff6e), .B(dz6e32c), .Z(vv71966)); XOR2 pu8cb37 (.A(al659bb), .B(sj2cddc), .Z(jc66ee4)); XOR2 rv37723 (.A(sj2cddc), .B(gbdc8fc), .Z(jce47e4)); XOR2 qv23f23 (.A(gbdc8fc), .B(hbfc8e9), .Z(lqe474f)); XOR2 gd23a7b (.A(hbfc8e9), .B(hbe9eed), .Z(bl4f76e)); XOR2 th7bb77 (.A(hbe9eed), .B(wjeddf6), .Z(rt6efb4)); XOR2 ea77da7 (.A(wjeddf6), .B(blf69c4), .Z(irb4e26)); XOR2 pua7135 (.A(blf69c4), .B(ayc4d57), .Z(gd26ab9)); XOR2 ri355cd (.A(ayc4d57), .B(dm57357), .Z(gqb9aba)); XOR2 fncd5d1 (.A(dm57357), .B(dm57475), .Z(jrba3aa)); XOR2 ayd1d57 (.A(dm57475), .B(qt755c6), .Z(zzaae34)); defparam rg571a7.initval = 16'h6996 ; ROM16X1 rg571a7 (.AD3(yxc69d3), .AD2(ks34e9c), .AD1(fca74e1), .AD0(fc3a70a), .DO0(wjd3853)) ; defparam hq9c29d.initval = 16'h6996 ; ROM16X1 hq9c29d (.AD3(gqa75b), .AD2(ea53ad9), .AD1(sw9d6c9), .AD0(faeb649), .DO0(kd5b24a)) ; defparam qtd9254.initval = 16'h6996 ; ROM16X1 qtd9254 (.AD3(fca74e1), .AD2(fc3a70a), .AD1(ip54b06), .AD0(ip54b06), .DO0(ux2c1a6)) ; defparam en60d35.initval = 16'h6996 ; ROM16X1 en60d35 (.AD3(ks34e9c), .AD2(fca74e1), .AD1(fc3a70a), .AD0(ip54b06), .DO0(fa66258)) ; defparam ec312c2.initval = 16'h6996 ; ROM16X1 ec312c2 (.AD3(faeb649), .AD2(yxc69d3), .AD1(ks34e9c), .AD0(ux2c1a6), .DO0(mg82af9)) ; defparam sw157c8.initval = 16'h6996 ; ROM16X1 sw157c8 (.AD3(sw9d6c9), .AD2(faeb649), .AD1(yxc69d3), .AD0(fa66258), .DO0(yzddb5)) ; defparam vv6edad.initval = 16'h6996 ; ROM16X1 vv6edad (.AD3(ea53ad9), .AD2(sw9d6c9), .AD1(faeb649), .AD0(wjd3853), .DO0(al7a1d4)) ; defparam hod0ea5.initval = 16'h6996 ; ROM16X1 hod0ea5 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(ip54b06), .AD0(ip54b06), .DO0(en5143a)) ; defparam ux8a1d5.initval = 16'h6996 ; ROM16X1 ux8a1d5 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(tud5b8a), .AD0(ip54b06), .DO0(ld6e292)) ; defparam hb71496.initval = 16'h6996 ; ROM16X1 hb71496 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(xy96d51), .AD0(tud5b8a), .DO0(jrb5458)) ; defparam vxaa2c6.initval = 16'h6996 ; ROM16X1 vxaa2c6 (.AD3(bn8b1b5), .AD2(xy96d51), .AD1(tud5b8a), .AD0(ip54b06), .DO0(xlb5ea4)) ; defparam hdaf527.initval = 16'h6996 ; ROM16X1 hdaf527 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(xlb5ea4), .AD0(ip54b06), .DO0(byf4138)) ; defparam jra09c2.initval = 16'h6996 ; ROM16X1 jra09c2 (.AD3(rv270b3), .AD2(zz3859e), .AD1(xjc2cf6), .AD0(fp167b6), .DO0(wyb3db6)) ; defparam vx9edb0.initval = 16'h6996 ; ROM16X1 vx9edb0 (.AD3(mgb6c3e), .AD2(qib61f0), .AD1(dbb0f81), .AD0(aa87c0f), .DO0(aa3e078)) ; defparam gof03c1.initval = 16'h6996 ; ROM16X1 gof03c1 (.AD3(xjc2cf6), .AD2(fp167b6), .AD1(ip54b06), .AD0(ip54b06), .DO0(rg47205)) ; defparam mt3902b.initval = 16'h6996 ; ROM16X1 mt3902b (.AD3(zz3859e), .AD2(xjc2cf6), .AD1(fp167b6), .AD0(ip54b06), .DO0(pfe6e08)) ; defparam nt37047.initval = 16'h6996 ; ROM16X1 nt37047 (.AD3(aa87c0f), .AD2(rv270b3), .AD1(zz3859e), .AD0(rg47205), .DO0(cmfa153)) ; defparam xwd0a99.initval = 16'h6996 ; ROM16X1 xwd0a99 (.AD3(dbb0f81), .AD2(aa87c0f), .AD1(rv270b3), .AD0(pfe6e08), .DO0(sh5441a)) ; defparam baa20d5.initval = 16'h6996 ; ROM16X1 baa20d5 (.AD3(qib61f0), .AD2(dbb0f81), .AD1(aa87c0f), .AD0(wyb3db6), .DO0(mr5165e)) ; defparam hd8b2f5.initval = 16'h6996 ; ROM16X1 hd8b2f5 (.AD3(wyb3db6), .AD2(aa3e078), .AD1(ip54b06), .AD0(ip54b06), .DO0(fa7914e)) ; defparam thc8a72.initval = 16'h6996 ; ROM16X1 thc8a72 (.AD3(wyb3db6), .AD2(aa3e078), .AD1(ww72fa5), .AD0(ip54b06), .DO0(cbbe941)) ; defparam tuf4a0c.initval = 16'h6996 ; ROM16X1 tuf4a0c (.AD3(wyb3db6), .AD2(aa3e078), .AD1(phc7fd), .AD0(ww72fa5), .DO0(gq1ff73)) ; defparam meffb99.initval = 16'h6996 ; ROM16X1 meffb99 (.AD3(byee645), .AD2(phc7fd), .AD1(ww72fa5), .AD0(ip54b06), .DO0(th454df)) ; defparam xy2a6fe.initval = 16'h6996 ; ROM16X1 xy2a6fe (.AD3(wyb3db6), .AD2(aa3e078), .AD1(th454df), .AD0(ip54b06), .DO0(yz90edd)) ; XOR2 sw876ec (.A(dz6e32c), .B(fp167b6), .Z(xjdd849)); XOR2 rtec24e (.A(fc3a70a), .B(qt755c6), .Z(me49dfe)); defparam cz4eff1.initval = 16'h0410 ; ROM16X1 cz4eff1 (.AD3(fpbfc60), .AD2(qt755c6), .AD1(fc3a70a), .AD0(ip54b06), .DO0(en60cda)) ; defparam zz66d4.initval = 16'h1004 ; ROM16X1 zz66d4 (.AD3(fpbfc60), .AD2(qt755c6), .AD1(fc3a70a), .AD0(ip54b06), .DO0(db3dcc3)) ; defparam faee61f.initval = 16'h0140 ; ROM16X1 faee61f (.AD3(wy987d3), .AD2(dz6e32c), .AD1(fp167b6), .AD0(ip54b06), .DO0(ipd3301)) ; defparam vk9980c.initval = 16'h4001 ; ROM16X1 vk9980c (.AD3(wy987d3), .AD2(dz6e32c), .AD1(fp167b6), .AD0(ip54b06), .DO0(ba14af1)) ; INV tja578a (.A(qi2bc57), .Z(yx5e2b9)); AND2 xwf15cc (.A(cb8ae62), .B(yx5e2b9), .Z(ukb98a2)); AND2 mrcc511 (.A(cb8ae62), .B(qi2bc57), .Z(doa230b)); defparam pu1185a.CSDECODE_B = 3'b000 ; defparam pu1185a.CSDECODE_A = 3'b000 ; defparam pu1185a.WRITEMODE_B = "NORMAL" ; defparam pu1185a.WRITEMODE_A = "NORMAL" ; defparam pu1185a.GSR = "ENABLED" ; defparam pu1185a.RESETMODE = "ASYNC" ; defparam pu1185a.REGMODE_B = "NOREG" ; defparam pu1185a.REGMODE_A = "NOREG" ; defparam pu1185a.DATA_WIDTH_B = 18 ; defparam pu1185a.DATA_WIDTH_A = 18 ; DP16KB pu1185a (.DIA0(icdbb13[0]), .DIA1(icdbb13[1]), .DIA2(icdbb13[2]), .DIA3(icdbb13[3]), .DIA4(icdbb13[4]), .DIA5(icdbb13[5]), .DIA6(icdbb13[6]), .DIA7(icdbb13[7]), .DIA8(icdbb13[8]), .DIA9(icdbb13[9]), .DIA10(icdbb13[10]), .DIA11(icdbb13[11]), .DIA12(icdbb13[12]), .DIA13(icdbb13[13]), .DIA14(icdbb13[14]), .DIA15(icdbb13[15]), .DIA16(icdbb13[16]), .DIA17(icdbb13[17]), .ADA0(vve93e5), .ADA1(vve93e5), .ADA2(ip54b06), .ADA3(ip54b06), .ADA4(uie5e73), .ADA5(vk2f398), .ADA6(ho79cc2), .ADA7(kqce613), .ADA8(lq73099), .ADA9(mg984cb), .ADA10(ldc2659), .ADA11(rv132cf), .ADA12(pu9967e), .ADA13(gocb3f3), .CEA(su43126), .CLKA(fndd899), .WEA(vve93e5), .CSA0(ip54b06), .CSA1(ip54b06), .CSA2(ip54b06), .RSTA(je99dc6), .DIB0(ip54b06), .DIB1(ip54b06), .DIB2(ip54b06), .DIB3(ip54b06), .DIB4(ip54b06), .DIB5(ip54b06), .DIB6(ip54b06), .DIB7(ip54b06), .DIB8(ip54b06), .DIB9(ip54b06), .DIB10(ip54b06), .DIB11(ip54b06), .DIB12(ip54b06), .DIB13(ip54b06), .DIB14(ip54b06), .DIB15(ip54b06), .DIB16(ip54b06), .DIB17(ip54b06), .ADB0(ip54b06), .ADB1(ip54b06), .ADB2(ip54b06), .ADB3(ip54b06), .ADB4(icde57a), .ADB5(alf2bd0), .ADB6(an95e84), .ADB7(lfaf424), .ADB8(gb7a126), .ADB9(dmd0935), .ADB10(jr849aa), .ADB11(ym24d57), .ADB12(cb26ab8), .ADB13(ls355c5), .CEB(dz6110a), .CLKB(dzec4ce), .WEB(ip54b06), .CSB0(ip54b06), .CSB1(ip54b06), .CSB2(ip54b06), .\r
-RSTB(je99dc6), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOA9(), .DOA10(), .DOA11(), .DOA12(), .DOA13(), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(gbc640b[0]), .DOB1(gbc640b[1]), .DOB2(gbc640b[2]), .DOB3(gbc640b[3]), .DOB4(gbc640b[4]), .DOB5(gbc640b[5]), .DOB6(gbc640b[6]), .DOB7(gbc640b[7]), .DOB8(gbc640b[8]), .DOB9(gbc640b[9]), .DOB10(gbc640b[10]), .DOB11(gbc640b[11]), .DOB12(gbc640b[12]), .DOB13(gbc640b[13]), .DOB14(gbc640b[14]), .DOB15(gbc640b[15]), .DOB16(gbc640b[16]), .DOB17(gbc640b[17])) ; defparam mt9f303.GSR = "ENABLED" ; FD1P3BX mt9f303 (.D(mrcc0e7), .SP(su43126), .CK(fndd899), .PD(je99dc6), .Q(wl86ff)) ; defparam kf3cbb5.GSR = "ENABLED" ; FD1P3DX kf3cbb5 (.D(co2ed68), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(yk437fc)) ; defparam of415d9.GSR = "ENABLED" ; FD1P3DX of415d9 (.D(rg57660), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(jpfc2d8)) ; defparam ir2b25.GSR = "ENABLED" ; FD1P3DX ir2b25 (.D(aaac960), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hbd8cdc)) ; defparam gqcad.GSR = "ENABLED" ; FD1P3DX gqcad (.D(fp32b4f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(mrdcd6f)) ; defparam rt7e8d6.GSR = "ENABLED" ; FD1P3DX rt7e8d6 (.D(swa35b2), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ip6f9da)) ; defparam gd9034b.GSR = "ENABLED" ; FD1P3DX gd9034b (.D(qvd2ef), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(nedaae1)) ; defparam ps7c711.GSR = "ENABLED" ; FD1P3DX ps7c711 (.D(jr1c457), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hoe16e9)) ; defparam vxbf8e3.GSR = "ENABLED" ; FD1P3DX vxbf8e3 (.D(lde38f6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(nre96ef)) ; defparam lsb7fde.GSR = "ENABLED" ; FD1P3DX lsb7fde (.D(meff796), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ykeff6e)) ; defparam kfb1422.GSR = "ENABLED" ; FD1P3DX kfb1422 (.D(bl508a5), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(dz6e32c)) ; defparam aa2edd6.GSR = "ENABLED" ; FD1P3DX aa2edd6 (.D(pu1bfe1), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(oh8a7a4)) ; defparam qg53d25.GSR = "ENABLED" ; FD1P3DX qg53d25 (.D(xwe16c6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ld4f71c)) ; defparam vv7b8e7.GSR = "ENABLED" ; FD1P3DX vv7b8e7 (.D(shc66e6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(uif5fa8)) ; defparam jrafd41.GSR = "ENABLED" ; FD1P3DX jrafd41 (.D(hbe6b7c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(jp7e0e8)) ; defparam ayf0747.GSR = "ENABLED" ; FD1P3DX ayf0747 (.D(lq7ced5), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hbc2b1e)) ; defparam ec158f6.GSR = "ENABLED" ; FD1P3DX ec158f6 (.D(rgd570b), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(rv816fe)) ; defparam hqb7f6.GSR = "ENABLED" ; FD1P3DX hqb7f6 (.D(zmb74b), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(co9d6b8)) ; defparam hoeb5c1.GSR = "ENABLED" ; FD1P3DX hoeb5c1 (.D(al4b77f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(xw57c80)) ; defparam qvbe403.GSR = "ENABLED" ; FD1P3DX qvbe403 (.D(kd7fb71), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(gbedb34)) ; defparam qg6d9a4.GSR = "ENABLED" ; FD1P3DX qg6d9a4 (.D(vv71966), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ep266b)) ; defparam nt1335d.GSR = "ENABLED" ; FD1P3DX nt1335d (.D(dz6e32c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ay72dd2)) ; defparam zm96e90.GSR = "ENABLED" ; FD1P3DX zm96e90 (.D(wl86ff), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(uie5e73)) ; defparam vidfd5b.GSR = "ENABLED" ; FD1P3DX vidfd5b (.D(yk437fc), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(vk2f398)) ; defparam hod0902.GSR = "ENABLED" ; FD1P3DX hod0902 (.D(jpfc2d8), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ho79cc2)) ; defparam mgb9768.GSR = "ENABLED" ; FD1P3DX mgb9768 (.D(hbd8cdc), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(kqce613)) ; defparam mt2a70.GSR = "ENABLED" ; FD1P3DX mt2a70 (.D(mrdcd6f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(lq73099)) ; defparam yz8b71.GSR = "ENABLED" ; FD1P3DX yz8b71 (.D(ip6f9da), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(mg984cb)) ; defparam fn7edcd.GSR = "ENABLED" ; FD1P3DX fn7edcd (.D(nedaae1), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ldc2659)) ; defparam qib33fb.GSR = "ENABLED" ; FD1P3DX qib33fb (.D(hoe16e9), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(rv132cf)) ; defparam vi52aeb.GSR = "ENABLED" ; FD1P3DX vi52aeb (.D(nre96ef), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(pu9967e)) ; defparam czed6ae.GSR = "ENABLED" ; FD1P3DX czed6ae (.D(ykeff6e), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(gocb3f3)) ; defparam ea7756d.GSR = "ENABLED" ; FD1P3DX ea7756d (.D(dz6e32c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(wy987d3)) ; defparam ic72455.GSR = "ENABLED" ; FD1P3BX ic72455 (.D(tj91548), .SP(dz6110a), .CK(dzec4ce), .PD(vvec21b), .Q(al659bb)) ; defparam vi479cb.GSR = "ENABLED" ; FD1P3DX vi479cb (.D(qte72d5), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(sj2cddc)) ; defparam qiac87a.GSR = "ENABLED" ; FD1P3DX qiac87a (.D(gq21e87), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gbdc8fc)) ; defparam jr38351.GSR = "ENABLED" ; FD1P3DX jr38351 (.D(and471), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(hbfc8e9)) ; defparam ba8c93f.GSR = "ENABLED" ; FD1P3DX ba8c93f (.D(mg24fde), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(hbe9eed)) ; defparam uif0ed0.GSR = "ENABLED" ; FD1P3DX uif0ed0 (.D(aa3b409), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(wjeddf6)) ; defparam ui494f6.GSR = "ENABLED" ; FD1P3DX ui494f6 (.D(su53d87), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(blf69c4)) ; defparam yz39ff9.GSR = "ENABLED" ; FD1P3DX yz39ff9 (.D(mr7fe6a), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ayc4d57)) ; defparam al543f5.GSR = "ENABLED" ; FD1P3DX al543f5 (.D(ymfd6c), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dm57357)) ; defparam kd60c53.GSR = "ENABLED" ; FD1P3DX kd60c53 (.D(qi314e7), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dm57475)) ; defparam nt38a54.GSR = "ENABLED" ; FD1P3DX nt38a54 (.D(gd2953a), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(qt755c6)) ; defparam byd5d12.GSR = "ENABLED" ; FD1P3DX byd5d12 (.D(jc66ee4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(sj95ca1)) ; defparam yzae50c.GSR = "ENABLED" ; FD1P3DX yzae50c (.D(jce47e4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ls20f3f)) ; defparam cb79fa.GSR = "ENABLED" ; FD1P3DX cb79fa (.D(lqe474f), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(fpa5ac0)) ; defparam hd2d606.GSR = "ENABLED" ; FD1P3DX hd2d606 (.D(bl4f76e), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(uxbe6f6)) ; defparam nrf37b5.GSR = \r
-"ENABLED" ; FD1P3DX nrf37b5 (.D(rt6efb4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ip7f3bf)) ; defparam vvf9dfd.GSR = "ENABLED" ; FD1P3DX vvf9dfd (.D(irb4e26), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ww781a8)) ; defparam xwc0d40.GSR = "ENABLED" ; FD1P3DX xwc0d40 (.D(gd26ab9), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ba1e4f6)) ; defparam wjf27b2.GSR = "ENABLED" ; FD1P3DX wjf27b2 (.D(gqb9aba), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gdabfd5)) ; defparam xj5fead.GSR = "ENABLED" ; FD1P3DX xj5fead (.D(jrba3aa), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ps79094)) ; defparam vvc84a2.GSR = "ENABLED" ; FD1P3DX vvc84a2 (.D(zzaae34), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gqb3bde)) ; defparam uk9def0.GSR = "ENABLED" ; FD1P3DX uk9def0 (.D(qt755c6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gqc04)) ; defparam db6021.GSR = "ENABLED" ; FD1P3DX db6021 (.D(al659bb), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(icde57a)) ; defparam rgd540c.GSR = "ENABLED" ; FD1P3DX rgd540c (.D(sj2cddc), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(alf2bd0)) ; defparam enf7f9b.GSR = "ENABLED" ; FD1P3DX enf7f9b (.D(gbdc8fc), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(an95e84)) ; defparam cb33fe6.GSR = "ENABLED" ; FD1P3DX cb33fe6 (.D(hbfc8e9), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(lfaf424)) ; defparam xl28fcf.GSR = "ENABLED" ; FD1P3DX xl28fcf (.D(hbe9eed), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gb7a126)) ; defparam ls93ebd.GSR = "ENABLED" ; FD1P3DX ls93ebd (.D(wjeddf6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dmd0935)) ; defparam wwe0e99.GSR = "ENABLED" ; FD1P3DX wwe0e99 (.D(blf69c4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(jr849aa)) ; defparam uk2b8fe.GSR = "ENABLED" ; FD1P3DX uk2b8fe (.D(ayc4d57), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ym24d57)) ; defparam rt4f2d3.GSR = "ENABLED" ; FD1P3DX rt4f2d3 (.D(dm57357), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(cb26ab8)) ; defparam osd1d61.GSR = "ENABLED" ; FD1P3DX osd1d61 (.D(dm57475), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ls355c5)) ; defparam ba353e8.GSR = "ENABLED" ; FD1P3DX ba353e8 (.D(qt755c6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(fpbfc60)) ; defparam xy86158.GSR = "ENABLED" ; FD1S3DX xy86158 (.D(oh8a7a4), .CK(dzec4ce), .CD(je99dc6), .Q(shc3703)) ; defparam tw1b81d.GSR = "ENABLED" ; FD1S3DX tw1b81d (.D(ld4f71c), .CK(dzec4ce), .CD(je99dc6), .Q(neeba75)) ; defparam zk5d3ab.GSR = "ENABLED" ; FD1S3DX zk5d3ab (.D(uif5fa8), .CK(dzec4ce), .CD(je99dc6), .Q(uv5bd24)) ; defparam uide925.GSR = "ENABLED" ; FD1S3DX uide925 (.D(jp7e0e8), .CK(dzec4ce), .CD(je99dc6), .Q(oh29703)) ; defparam ip4b81d.GSR = "ENABLED" ; FD1S3DX ip4b81d (.D(hbc2b1e), .CK(dzec4ce), .CD(je99dc6), .Q(nrec274)) ; defparam bl613a7.GSR = "ENABLED" ; FD1S3DX bl613a7 (.D(rv816fe), .CK(dzec4ce), .CD(je99dc6), .Q(pu3ff3b)) ; defparam suff9da.GSR = "ENABLED" ; FD1S3DX suff9da (.D(co9d6b8), .CK(dzec4ce), .CD(je99dc6), .Q(vid0f0a)) ; defparam uk87852.GSR = "ENABLED" ; FD1S3DX uk87852 (.D(xw57c80), .CK(dzec4ce), .CD(je99dc6), .Q(sj908ca)) ; defparam zz84654.GSR = "ENABLED" ; FD1S3DX zz84654 (.D(gbedb34), .CK(dzec4ce), .CD(je99dc6), .Q(yma69d4)) ; defparam ec34ea1.GSR = "ENABLED" ; FD1S3DX ec34ea1 (.D(ep266b), .CK(dzec4ce), .CD(je99dc6), .Q(tj948d)) ; defparam dz4a46e.GSR = "ENABLED" ; FD1S3DX dz4a46e (.D(ay72dd2), .CK(dzec4ce), .CD(je99dc6), .Q(kq7758f)) ; defparam hdbac79.GSR = "ENABLED" ; FD1S3DX hdbac79 (.D(sj95ca1), .CK(fndd899), .CD(vvec21b), .Q(cmce96b)) ; defparam xj74b58.GSR = "ENABLED" ; FD1S3DX xj74b58 (.D(ls20f3f), .CK(fndd899), .CD(vvec21b), .Q(ldc7df2)) ; defparam ks3ef96.GSR = "ENABLED" ; FD1S3DX ks3ef96 (.D(fpa5ac0), .CK(fndd899), .CD(vvec21b), .Q(bnb0962)) ; defparam nt84b17.GSR = "ENABLED" ; FD1S3DX nt84b17 (.D(uxbe6f6), .CK(fndd899), .CD(vvec21b), .Q(phbf54d)) ; defparam wwfaa6f.GSR = "ENABLED" ; FD1S3DX wwfaa6f (.D(ip7f3bf), .CK(fndd899), .CD(vvec21b), .Q(go7861c)) ; defparam alc30e0.GSR = "ENABLED" ; FD1S3DX alc30e0 (.D(ww781a8), .CK(fndd899), .CD(vvec21b), .Q(qi5b38)) ; defparam fp2d9c1.GSR = "ENABLED" ; FD1S3DX fp2d9c1 (.D(ba1e4f6), .CK(fndd899), .CD(vvec21b), .Q(hqe431)) ; defparam me7218b.GSR = "ENABLED" ; FD1S3DX me7218b (.D(gdabfd5), .CK(fndd899), .CD(vvec21b), .Q(os598c7)) ; defparam wjcc638.GSR = "ENABLED" ; FD1S3DX wjcc638 (.D(ps79094), .CK(fndd899), .CD(vvec21b), .Q(goc453f)) ; defparam zz229f8.GSR = "ENABLED" ; FD1S3DX zz229f8 (.D(gqb3bde), .CK(fndd899), .CD(vvec21b), .Q(thc74dd)) ; defparam ba3a6ef.GSR = "ENABLED" ; FD1S3DX ba3a6ef (.D(gqc04), .CK(fndd899), .CD(vvec21b), .Q(pf7b9f0)) ; defparam uvdcf86.GSR = "ENABLED" ; FD1S3DX uvdcf86 (.D(shc3703), .CK(dzec4ce), .CD(je99dc6), .Q(bn8b1b5)) ; defparam bna5251.GSR = "ENABLED" ; FD1S3DX bna5251 (.D(neeba75), .CK(dzec4ce), .CD(je99dc6), .Q(xy96d51)) ; defparam ww7d1e4.GSR = "ENABLED" ; FD1S3DX ww7d1e4 (.D(uv5bd24), .CK(dzec4ce), .CD(je99dc6), .Q(tud5b8a)) ; defparam ls455a.GSR = "ENABLED" ; FD1S3DX ls455a (.D(oh29703), .CK(dzec4ce), .CD(je99dc6), .Q(gqa75b)) ; defparam ec97337.GSR = "ENABLED" ; FD1S3DX ec97337 (.D(nrec274), .CK(dzec4ce), .CD(je99dc6), .Q(ea53ad9)) ; defparam mec1afa.GSR = "ENABLED" ; FD1S3DX mec1afa (.D(pu3ff3b), .CK(dzec4ce), .CD(je99dc6), .Q(sw9d6c9)) ; defparam pu8cf88.GSR = "ENABLED" ; FD1S3DX pu8cf88 (.D(vid0f0a), .CK(dzec4ce), .CD(je99dc6), .Q(faeb649)) ; defparam ph19281.GSR = "ENABLED" ; FD1S3DX ph19281 (.D(sj908ca), .CK(dzec4ce), .CD(je99dc6), .Q(yxc69d3)) ; defparam fa7cff8.GSR = "ENABLED" ; FD1S3DX fa7cff8 (.D(yma69d4), .CK(dzec4ce), .CD(je99dc6), .Q(ks34e9c)) ; defparam mt1d464.GSR = "ENABLED" ; FD1S3DX mt1d464 (.D(tj948d), .CK(dzec4ce), .CD(je99dc6), .Q(fca74e1)) ; defparam tj288f3.GSR = "ENABLED" ; FD1S3DX tj288f3 (.D(kq7758f), .CK(dzec4ce), .CD(je99dc6), .Q(fc3a70a)) ; defparam byf4ab7.GSR = "ENABLED" ; FD1S3DX byf4ab7 (.D(cmce96b), .CK(fndd899), .CD(vvec21b), .Q(byee645)) ; defparam hodf65c.GSR = "ENABLED" ; FD1S3DX hodf65c (.D(ldc7df2), .CK(fndd899), .CD(vvec21b), .Q(phc7fd)) ; defparam tj13a0c.GSR = "ENABLED" ; FD1S3DX tj13a0c (.D(bnb0962), .CK(fndd899), .CD(vvec21b), .Q(ww72fa5)) ; defparam oh39b78.GSR = "ENABLED" ; FD1S3DX oh39b78 (.D(phbf54d), .CK(fndd899), .CD(vvec21b), .Q(mgb6c3e)) ; defparam je2f10b.GSR = "ENABLED" ; FD1S3DX je2f10b (.D(go7861c), .CK(fndd899), .CD(vvec21b), .Q(qib61f0)) ; defparam cmd105e.GSR = "ENABLED" ; FD1S3DX cmd105e (.D(qi5b38), .CK(fndd899), .CD(vvec21b), .Q(dbb0f81)) ; defparam gq888a2.GSR = "ENABLED" ; FD1S3DX gq888a2 (.D(hqe431), .CK(fndd899), .CD(vvec21b), .Q(aa87c0f)) ; defparam pu8ced2.GSR = "ENABLED" ; FD1S3DX pu8ced2 (.D(os598c7), .CK(fndd899), .CD(vvec21b), .Q(rv270b3)) ; defparam wy982b2.\r
-GSR = "ENABLED" ; FD1S3DX wy982b2 (.D(goc453f), .CK(fndd899), .CD(vvec21b), .Q(zz3859e)) ; defparam aa8801f.GSR = "ENABLED" ; FD1S3DX aa8801f (.D(thc74dd), .CK(fndd899), .CD(vvec21b), .Q(xjc2cf6)) ; defparam wjc6185.GSR = "ENABLED" ; FD1S3DX wjc6185 (.D(pf7b9f0), .CK(fndd899), .CD(vvec21b), .Q(fp167b6)) ; defparam vv6b6ef.GSR = "ENABLED" ; FD1S3BX vv6b6ef (.D(ykdbbf4), .CK(dzec4ce), .PD(vvec21b), .Q(of442bd)) ; defparam byf438e.GSR = "ENABLED" ; FD1S3DX byf438e (.D(doe394), .CK(fndd899), .CD(je99dc6), .Q(qgc498c)) ; defparam bn947f8.GSR = "ENABLED" ; FD1S3BX bn947f8 (.D(ym1fe39), .CK(dzec4ce), .PD(vvec21b), .Q(fp8177d)) ; defparam sj3926f.GSR = "ENABLED" ; FD1S3DX sj3926f (.D(su49be4), .CK(fndd899), .CD(je99dc6), .Q(pubbee)) ; FADD2B wje7c42 (.A0(ip54b06), .A1(vve93e5), .B0(ip54b06), .B1(vve93e5), .CI(ip54b06), .COUT(mga9411), .S0(), .S1()); CU2 nee42eb (.CI(mga9411), .PC0(wl86ff), .PC1(yk437fc), .CO(tueb653), .NC0(mrcc0e7), .NC1(co2ed68)); CU2 hoca6a5 (.CI(tueb653), .PC0(jpfc2d8), .PC1(hbd8cdc), .CO(hda5628), .NC0(rg57660), .NC1(aaac960)); CU2 byc51c2 (.CI(hda5628), .PC0(mrdcd6f), .PC1(ip6f9da), .CO(rtc259e), .NC0(fp32b4f), .NC1(swa35b2)); CU2 wyb3dea (.CI(rtc259e), .PC0(nedaae1), .PC1(hoe16e9), .CO(qgea1e2), .NC0(qvd2ef), .NC1(jr1c457)); CU2 gd3c430 (.CI(qgea1e2), .PC0(nre96ef), .PC1(ykeff6e), .CO(je30903), .NC0(lde38f6), .NC1(meff796)); CU2 pu206f9 (.CI(je30903), .PC0(dz6e32c), .PC1(ip54b06), .CO(dzf97da), .NC0(bl508a5), .NC1()); FADD2B rtcd253 (.A0(ip54b06), .A1(vve93e5), .B0(ip54b06), .B1(vve93e5), .CI(ip54b06), .COUT(blf31ce), .S0(), .S1()); CU2 hb5f6b0 (.CI(blf31ce), .PC0(al659bb), .PC1(sj2cddc), .CO(zzb0cdc), .NC0(tj91548), .NC1(qte72d5)); CU2 tj9b9dd (.CI(zzb0cdc), .PC0(gbdc8fc), .PC1(hbfc8e9), .CO(hbddf20), .NC0(gq21e87), .NC1(and471)); CU2 jce418b (.CI(hbddf20), .PC0(hbe9eed), .PC1(wjeddf6), .CO(lf8b6b8), .NC0(mg24fde), .NC1(aa3b409)); CU2 zxd71e3 (.CI(lf8b6b8), .PC0(blf69c4), .PC1(ayc4d57), .CO(rte3cf4), .NC0(su53d87), .NC1(mr7fe6a)); CU2 db9e9d6 (.CI(rte3cf4), .PC0(dm57357), .PC1(dm57475), .CO(end6ed2), .NC0(ymfd6c), .NC1(qi314e7)); CU2 hoda55d (.CI(end6ed2), .PC0(qt755c6), .PC1(ip54b06), .CO(xw5d5ed), .NC0(gd2953a), .NC1()); FSUB2B ne57b59 (.A0(vve93e5), .A1(wl86ff), .B0(ip54b06), .B1(yz90edd), .BI(ip54b06), .BOUT(of5bb89), .S0(), .S1(viee26e)); FSUB2B jp71372 (.A0(yk437fc), .A1(jpfc2d8), .B0(gq1ff73), .B1(cbbe941), .BI(of5bb89), .BOUT(oub3782), .S0(blddc4d), .S1(qgde08f)); FSUB2B kqf0478 (.A0(hbd8cdc), .A1(mrdcd6f), .B0(fa7914e), .B1(mr5165e), .BI(oub3782), .BOUT(hq1542), .S0(nt9bc11), .S1(nr55090)); FSUB2B nga8487 (.A0(ip6f9da), .A1(nedaae1), .B0(sh5441a), .B1(cmfa153), .BI(hq1542), .BOUT(aydb909), .S0(ecaa12), .S1(bye424c)); FSUB2B co21263 (.A0(hoe16e9), .A1(nre96ef), .B0(wyb3db6), .B1(pfe6e08), .BI(aydb909), .BOUT(icce216), .S0(shdc849), .S1(aa8858e)); FSUB2B fa42c70 (.A0(ykeff6e), .A1(xjdd849), .B0(rg47205), .B1(ip54b06), .BI(icce216), .BOUT(), .S0(xj710b1), .S1(fp16be0)); VHI dbb5f07 (.Z(vve93e5)); FSUB2B xw7c1ff (.A0(vve93e5), .A1(byf4138), .B0(ip54b06), .B1(al659bb), .BI(ip54b06), .BOUT(rgd0889), .S0(), .S1(jr22256)); FSUB2B ls112b6 (.A0(jrb5458), .A1(ld6e292), .B0(sj2cddc), .B1(gbdc8fc), .BI(rgd0889), .BOUT(yz9ac49), .S0(rv8444a), .S1(anb126c)); FSUB2B zm89364 (.A0(en5143a), .A1(al7a1d4), .B0(hbfc8e9), .B1(hbe9eed), .BI(yz9ac49), .BOUT(fc116be), .S0(czd624d), .S1(jp5af9f)); FSUB2B nrd7cff (.A0(yzddb5), .A1(mg82af9), .B0(wjeddf6), .B1(blf69c4), .BI(fc116be), .BOUT(ipfdd40), .S0(db8b5f3), .S1(wj7502b)); FSUB2B twa815c (.A0(wjd3853), .A1(fa66258), .B0(ayc4d57), .B1(dm57357), .BI(ipfdd40), .BOUT(ym1f04f), .S0(tueea05), .S1(mec13c4)); FSUB2B vx9e20 (.A0(ux2c1a6), .A1(me49dfe), .B0(dm57475), .B1(ip54b06), .BI(ym1f04f), .BOUT(), .S0(qi2bc57), .S1(cb8ae62)); FADD2B xy30e89 (.A0(ip54b06), .A1(dz6110a), .B0(ip54b06), .B1(dz6110a), .CI(ip54b06), .COUT(go59655), .S0(), .S1()); AGEB2 zxf90a3 (.A0(al659bb), .A1(sj2cddc), .B0(byf4138), .B1(jrb5458), .CI(go59655), .GE(fnf64cb)); AGEB2 rib265f (.A0(gbdc8fc), .A1(hbfc8e9), .B0(ld6e292), .B1(en5143a), .CI(fnf64cb), .GE(fada633)); AGEB2 czd319a (.A0(hbe9eed), .A1(wjeddf6), .B0(al7a1d4), .B1(yzddb5), .CI(fada633), .GE(lfa0b69)); AGEB2 aa5b4e (.A0(blf69c4), .A1(ayc4d57), .B0(mg82af9), .B1(wjd3853), .CI(lfa0b69), .GE(zz8e2af)); AGEB2 dz7157f (.A0(dm57357), .A1(dm57475), .B0(fa66258), .B1(ux2c1a6), .CI(zz8e2af), .GE(vif4de2)); AGEB2 oua6f13 (.A0(en60cda), .A1(ip54b06), .B0(db3dcc3), .B1(ip54b06), .CI(vif4de2), .GE(goce132)); FADD2B gb70991 (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(goce132), .COUT(), .S0(ykdbbf4), .S1()); FADD2B cmef57b (.A0(ip54b06), .A1(su43126), .B0(ip54b06), .B1(su43126), .CI(ip54b06), .COUT(uic45be), .S0(), .S1()); AGEB2 tu7cf8d (.A0(wl86ff), .A1(yk437fc), .B0(yz90edd), .B1(gq1ff73), .CI(uic45be), .GE(xw5d2c7)); AGEB2 vve963b (.A0(jpfc2d8), .A1(hbd8cdc), .B0(cbbe941), .B1(fa7914e), .CI(xw5d2c7), .GE(kdfd5c3)); AGEB2 eaeae1c (.A0(mrdcd6f), .A1(ip6f9da), .B0(mr5165e), .B1(sh5441a), .CI(kdfd5c3), .GE(oua53b)); AGEB2 rg529d9 (.A0(nedaae1), .A1(hoe16e9), .B0(cmfa153), .B1(wyb3db6), .CI(oua53b), .GE(gb5e468)); AGEB2 kdf2344 (.A0(nre96ef), .A1(ykeff6e), .B0(pfe6e08), .B1(rg47205), .CI(gb5e468), .GE(ou2e02a)); AGEB2 en70150 (.A0(ipd3301), .A1(ip54b06), .B0(ba14af1), .B1(ip54b06), .CI(ou2e02a), .GE(xy250b7)); FADD2B zz285bb (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(xy250b7), .COUT(), .S0(doe394), .S1()); FADD2B vx943c6 (.A0(ip54b06), .A1(dz6110a), .B0(ip54b06), .B1(dz6110a), .CI(ip54b06), .COUT(swbc266), .S0(), .S1()); AGEB2 vvd7710 (.A0(ay77190[0]), .A1(ay77190[1]), .B0(jr22256), .B1(rv8444a), .CI(swbc266), .GE(ou34b02)); AGEB2 nta5811 (.A0(ay77190[2]), .A1(ay77190[3]), .B0(anb126c), .B1(czd624d), .CI(ou34b02), .GE(sh75b56)); AGEB2 riadab5 (.A0(ay77190[4]), .A1(ay77190[5]), .B0(jp5af9f), .B1(db8b5f3), .CI(sh75b56), .GE(sh51a76)); AGEB2 wy8d3b4 (.A0(ay77190[6]), .A1(ay77190[7]), .B0(wj7502b), .B1(tueea05), .CI(sh51a76), .GE(ep28a7)); AGEB2 hq1453c (.A0(ay77190[8]), .A1(ay77190[9]), .B0(mec13c4), .B1(qi2bc57), .CI(ep28a7), .GE(do1b4e6)); AGEB2 lqda732 (.A0(doa230b), .A1(ip54b06), .B0(ukb98a2), .B1(ip54b06), .CI(do1b4e6), .GE(sj955b9)); FADD2B dbaadcd (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(sj955b9), .COUT(), .S0(ym1fe39), .S1()); FADD2B ks2e00f (.A0(ip54b06), .A1(su43126), .B0(ip54b06), .B1(su43126), .CI(ip54b06), .COUT(qgc48c9), .S0(), .S1()); AGEB2 qgcb3e2 (.A0(viee26e), .A1(blddc4d), .B0(dob8c81[0]), .B1(dob8c81[1]), .CI(qgc48c9), .GE(wy884a3)); AGEB2 zk42518 (.A0(qgde08f), .A1(nt9bc11), .B0(dob8c81[2]), .B1(dob8c81[3]), .CI(wy884a3), .GE(sj1de2c)); AGEB2 ayef164 (.A0(nr55090), .A1(ecaa12), .B0(dob8c81[4]), .B1(dob8c81[5]), .CI(sj1de2c), .GE(zm173b)); AGEB2 twb9da (.A0(bye424c), .A1(shdc849), .B0(dob8c81[6]), .B1(dob8c81[7]), .CI(zm173b), .GE(wl90856)); AGEB2 fp842b4 (.A0(aa8858e), .A1(xj710b1), .B0(dob8c81[8]), .B1(dob8c81[9]), .CI(wl90856), .GE(ou31068)); AGEB2 gq88340 (.A0(fp16be0), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(ou31068), .GE(gq5871)); VLO cb2c389 (.Z(ip54b06)); FADD2B xye26e (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(gq5871), .COUT(), .S0(su49be4), .S1()); assign db3205d = of442bd; assign cb902ef = qgc498c;\r
- \r
-always@* begin hqbd2d7<={icdbb13>>1,nrf6ece[0]};jpe96ba<=nrf6ece[1];uv4b5d7<=nrf6ece[2];pf5aebd<=nrf6ece[3];jpd75ef<=nrf6ece[4];fpbaf7e<=nrf6ece[5];thd7bf6<=nrf6ece[6];jebdfb7<={ay77190>>1,nrf6ece[7]};ayefdbb<={dob8c81>>1,nrf6ece[8]};end\r
-always@* begin bl7edd9[2047]<=fndd899;bl7edd9[2046]<=dzec4ce;bl7edd9[2044]<=ww62677;bl7edd9[2040]<=nt133b8;bl7edd9[2032]<=je99dc6;bl7edd9[2017]<=gocee32;bl7edd9[1987]<=ay77190[0];bl7edd9[1926]<=dob8c81[0];bl7edd9[1023]<=icdbb13[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ba4f04 (icdbb13, fndd899, dzec4ce, ww62677, nt133b8, je99dc6, \r
- gocee32, ay77190, dob8c81, gbc640b, db3205d, cb902ef, fp8177d, \r
- pubbee);\r
-input wire [17:0] icdbb13;\r
-input wire fndd899;\r
-input wire dzec4ce;\r
-input wire ww62677;\r
-input wire nt133b8;\r
-input wire je99dc6;\r
-input wire gocee32;\r
-input wire [9:0] ay77190;\r
-input wire [9:0] dob8c81;\r
-output wire [17:0] gbc640b;\r
-output wire db3205d;\r
-output wire cb902ef;\r
-output wire fp8177d;\r
-output wire pubbee;\r
-wire fnc8624;\r
-wire tw8c221;\r
-wire xlb5ea4;\r
-wire kd5b24a;\r
-wire th454df;\r
-wire aa3e078;\r
-wire gd1d5e2;\r
-wire pu1bfe1;\r
-wire xwe16c6;\r
-wire shc66e6;\r
-wire hbe6b7c;\r
-wire lq7ced5;\r
-wire rgd570b;\r
-wire zmb74b;\r
-wire al4b77f;\r
-wire kd7fb71;\r
-wire vv71966;\r
-wire uie5e73;\r
-wire vk2f398;\r
-wire ho79cc2;\r
-wire kqce613;\r
-wire lq73099;\r
-wire mg984cb;\r
-wire ldc2659;\r
-wire rv132cf;\r
-wire pu9967e;\r
-wire gocb3f3;\r
-wire wy987d3;\r
-wire jc66ee4;\r
-wire jce47e4;\r
-wire lqe474f;\r
-wire bl4f76e;\r
-wire rt6efb4;\r
-wire irb4e26;\r
-wire gd26ab9;\r
-wire gqb9aba;\r
-wire jrba3aa;\r
-wire zzaae34;\r
-wire icde57a;\r
-wire alf2bd0;\r
-wire an95e84;\r
-wire lfaf424;\r
-wire gb7a126;\r
-wire dmd0935;\r
-wire jr849aa;\r
-wire ym24d57;\r
-wire cb26ab8;\r
-wire ls355c5;\r
-wire fpbfc60;\r
-wire oh8a7a4;\r
-wire ld4f71c;\r
-wire uif5fa8;\r
-wire jp7e0e8;\r
-wire hbc2b1e;\r
-wire rv816fe;\r
-wire co9d6b8;\r
-wire xw57c80;\r
-wire gbedb34;\r
-wire ep266b;\r
-wire ay72dd2;\r
-wire sj95ca1;\r
-wire ls20f3f;\r
-wire fpa5ac0;\r
-wire uxbe6f6;\r
-wire ip7f3bf;\r
-wire ww781a8;\r
-wire ba1e4f6;\r
-wire gdabfd5;\r
-wire ps79094;\r
-wire gqb3bde;\r
-wire gqc04;\r
-wire bn8b1b5;\r
-wire shc3703;\r
-wire xy96d51;\r
-wire neeba75;\r
-wire tud5b8a;\r
-wire uv5bd24;\r
-wire gqa75b;\r
-wire oh29703;\r
-wire ea53ad9;\r
-wire nrec274;\r
-wire sw9d6c9;\r
-wire pu3ff3b;\r
-wire faeb649;\r
-wire vid0f0a;\r
-wire yxc69d3;\r
-wire sj908ca;\r
-wire ks34e9c;\r
-wire yma69d4;\r
-wire fca74e1;\r
-wire tj948d;\r
-wire fc3a70a;\r
-wire kq7758f;\r
-wire byee645;\r
-wire cmce96b;\r
-wire phc7fd;\r
-wire ldc7df2;\r
-wire ww72fa5;\r
-wire bnb0962;\r
-wire mgb6c3e;\r
-wire phbf54d;\r
-wire qib61f0;\r
-wire go7861c;\r
-wire dbb0f81;\r
-wire qi5b38;\r
-wire aa87c0f;\r
-wire hqe431;\r
-wire rv270b3;\r
-wire os598c7;\r
-wire zz3859e;\r
-wire goc453f;\r
-wire xjc2cf6;\r
-wire thc74dd;\r
-wire fp167b6;\r
-wire pf7b9f0;\r
-wire oh8012e;\r
-wire of442bd;\r
-wire qgc498c;\r
-wire vvec21b;\r
-wire mrcc0e7;\r
-wire co2ed68;\r
-wire mga9411;\r
-wire rg57660;\r
-wire aaac960;\r
-wire tueb653;\r
-wire fp32b4f;\r
-wire swa35b2;\r
-wire hda5628;\r
-wire qvd2ef;\r
-wire jr1c457;\r
-wire rtc259e;\r
-wire lde38f6;\r
-wire meff796;\r
-wire qgea1e2;\r
-wire bl508a5;\r
-wire dzf97da;\r
-wire dz6e32c;\r
-wire je30903;\r
-wire tj91548;\r
-wire qte72d5;\r
-wire blf31ce;\r
-wire gq21e87;\r
-wire and471;\r
-wire zzb0cdc;\r
-wire mg24fde;\r
-wire aa3b409;\r
-wire hbddf20;\r
-wire su53d87;\r
-wire mr7fe6a;\r
-wire lf8b6b8;\r
-wire ymfd6c;\r
-wire qi314e7;\r
-wire rte3cf4;\r
-wire gd2953a;\r
-wire xw5d5ed;\r
-wire qt755c6;\r
-wire end6ed2;\r
-wire viee26e;\r
-wire blddc4d;\r
-wire qgde08f;\r
-wire of5bb89;\r
-wire nt9bc11;\r
-wire nr55090;\r
-wire oub3782;\r
-wire ecaa12;\r
-wire bye424c;\r
-wire hq1542;\r
-wire shdc849;\r
-wire aa8858e;\r
-wire aydb909;\r
-wire xj710b1;\r
-wire fp16be0;\r
-wire icce216;\r
-wire xjdd849;\r
-wire fn4afe2;\r
-wire tu57f16;\r
-wire jr22256;\r
-wire vve93e5;\r
-wire rv8444a;\r
-wire anb126c;\r
-wire rgd0889;\r
-wire czd624d;\r
-wire jp5af9f;\r
-wire yz9ac49;\r
-wire db8b5f3;\r
-wire wj7502b;\r
-wire fc116be;\r
-wire tueea05;\r
-wire mec13c4;\r
-wire ipfdd40;\r
-wire qi2bc57;\r
-wire cb8ae62;\r
-wire ym1f04f;\r
-wire me49dfe;\r
-wire sw213fa;\r
-wire lf9fd1;\r
-wire go59655;\r
-wire byf4138;\r
-wire jrb5458;\r
-wire al659bb;\r
-wire sj2cddc;\r
-wire fnf64cb;\r
-wire ld6e292;\r
-wire en5143a;\r
-wire gbdc8fc;\r
-wire hbfc8e9;\r
-wire fada633;\r
-wire al7a1d4;\r
-wire yzddb5;\r
-wire hbe9eed;\r
-wire wjeddf6;\r
-wire lfa0b69;\r
-wire mg82af9;\r
-wire wjd3853;\r
-wire blf69c4;\r
-wire ayc4d57;\r
-wire zz8e2af;\r
-wire fa66258;\r
-wire ux2c1a6;\r
-wire dm57357;\r
-wire dm57475;\r
-wire vif4de2;\r
-wire db3dcc3;\r
-wire en60cda;\r
-wire ykdbbf4;\r
-wire goce132;\r
-wire uic45be;\r
-wire yz90edd;\r
-wire gq1ff73;\r
-wire wl86ff;\r
-wire yk437fc;\r
-wire xw5d2c7;\r
-wire cbbe941;\r
-wire fa7914e;\r
-wire jpfc2d8;\r
-wire hbd8cdc;\r
-wire kdfd5c3;\r
-wire mr5165e;\r
-wire sh5441a;\r
-wire mrdcd6f;\r
-wire ip6f9da;\r
-wire oua53b;\r
-wire cmfa153;\r
-wire wyb3db6;\r
-wire nedaae1;\r
-wire hoe16e9;\r
-wire gb5e468;\r
-wire pfe6e08;\r
-wire rg47205;\r
-wire nre96ef;\r
-wire ykeff6e;\r
-wire ou2e02a;\r
-wire ba14af1;\r
-wire ipd3301;\r
-wire doe394;\r
-wire xy250b7;\r
-wire dz6110a;\r
-wire swbc266;\r
-wire jr3e16;\r
-wire uk1f0b6;\r
-wire ou34b02;\r
-wire thc2d84;\r
-wire zz16c26;\r
-wire sh75b56;\r
-wire lfb09b9;\r
-wire ph84dcf;\r
-wire sh51a76;\r
-wire rv373fd;\r
-wire ieb9fef;\r
-wire ep28a7;\r
-wire cz7fbca;\r
-wire uvfde54;\r
-wire do1b4e6;\r
-wire ukb98a2;\r
-wire doa230b;\r
-wire ym1fe39;\r
-wire sj955b9;\r
-wire su43126;\r
-wire qgc48c9;\r
-wire yz129fb;\r
-wire zz94fdd;\r
-wire wy884a3;\r
-wire do3f773;\r
-wire fafbb9b;\r
-wire sj1de2c;\r
-wire jcee6d6;\r
-wire ps736b2;\r
-wire zm173b;\r
-wire zkdac9e;\r
-wire kdd64f3;\r
-wire wl90856;\r
-wire ng93ce3;\r
-wire ph9e71b;\r
-wire ou31068;\r
-wire ng9c6f6;\r
-wire su49be4;\r
-wire gq5871;\r
-wire ip54b06;\r
-reg [17 : 0] hqbd2d7;\r
-reg jpe96ba;\r
-reg uv4b5d7;\r
-reg pf5aebd;\r
-reg jpd75ef;\r
-reg fpbaf7e;\r
-reg thd7bf6;\r
-reg [9 : 0] jebdfb7;\r
-reg [9 : 0] ayefdbb;\r
-reg fpba667;\r
-reg wjd333f;\r
-reg do999fc;\r
-reg mrccfe2;\r
-reg ay67f15;\r
-reg vk3f8a9;\r
-reg rtfc54a;\r
-reg kde2a56;\r
-reg wy152b5;\r
-reg gqa95a9;\r
-reg xj4ad49;\r
-reg go56a4e;\r
-reg lfb5271;\r
-reg iea938e;\r
-reg kq49c71;\r
-reg mr4e389;\r
-reg dz71c4d;\r
-reg db8e26f;\r
-reg jp7137f;\r
-reg tw89bfe;\r
-reg fa4dff3;\r
-reg yx6ff9b;\r
-reg kd7fcdd;\r
-reg fafe6ec;\r
-reg xjf3763;\r
-reg hd9bb1f;\r
-reg xjdd8ff;\r
-reg rtec7fe;\r
-reg fa63ff7;\r
-reg ie1ffbb;\r
-reg cmffdd9;\r
-reg tufeec8;\r
-reg alf7642;\r
-reg epbb215;\r
-reg ofd90ad;\r
-reg blc856d;\r
-reg ne42b6e;\r
-reg aa15b72;\r
-reg jeadb90;\r
-reg os6dc82;\r
-reg fn6e410;\r
-reg ic72086;\r
-reg qv90431;\r
-reg ks8218d;\r
-reg gq10c69;\r
-reg fc86348;\r
-reg sw31a43;\r
-reg qi8d219;\r
-reg dm690c8;\r
-reg xw48643;\r
-reg go4321a;\r
-reg db190d1;\r
-reg rtc868f;\r
-reg kq4347e;\r
-reg gq1a3f1;\r
-reg icd1f88;\r
-reg wl8fc40;\r
-reg bl7e204;\r
-reg psf1027;\r
-reg ou8813a;\r
-reg pf409d0;\r
-reg vk4e87;\r
-reg tj2743b;\r
-reg ng3a1de;\r
-reg hod0ef3;\r
-reg mg8779a;\r
-reg wy3bcd1;\r
-reg wwde688;\r
-reg jpf3440;\r
-reg yz9a207;\r
-reg wwd103c;\r
-reg gq881e1;\r
-reg dz40f08;\r
-reg ep7847;\r
-reg ir3c23c;\r
-reg pse11e4;\r
-reg mt8f23;\r
-reg by4791d;\r
-reg kf3c8ea;\r
-reg jce4755;\r
-reg qv23aab;\r
-reg ux1d55d;\r
-reg uieaaed;\r
-reg fn55769;\r
-reg cbabb4f;\r
-reg ps5da7d;\r
-reg ened3ea;\r
-reg fa69f55;\r
-reg ld4faaa;\r
-reg os7d556;\r
-reg kqeaab0;\r
-reg dz55581;\r
-reg ntaac0f;\r
-reg yk5607f;\r
-reg vxb03f8;\r
-reg nt81fc6;\r
-reg ecfe37;\r
-reg mr7f1b8;\r
-reg alf8dc5;\r
-reg ipc6e2d;\r
-reg ph3716c;\r
-reg twb8b67;\r
-reg dmc5b3b;\r
-reg fp2d9db;\r
-reg jc6cede;\r
-reg os676f2;\r
-reg ym3b790;\r
-reg qgdbc81;\r
-reg osde409;\r
-reg wjf2048;\r
-reg yz90245;\r
-reg zz8122d;\r
-reg vx916e;\r
-reg rg48b76;\r
-reg rt45bb3;\r
-reg nt2dd9f;\r
-reg xj6ecfe;\r
-reg by767f7;\r
-reg ksb3fbb;\r
-reg cb9fdd8;\r
-reg hofeec5;\r
-reg ipf762a;\r
-reg qvbb155;\r
-reg hbd8aad;\r
-reg rgc556e;\r
-reg hq2ab72;\r
-reg fn55b93;\r
-reg xyadc9e;\r
-reg zx6e4f2;\r
-reg me72796;\r
-reg vk93cb1;\r
-reg bn9e58b;\r
-reg wjf2c5e;\r
-reg tw962f4;\r
-reg gdb17a2;\r
-reg xl8bd14;\r
-reg ip5e8a6;\r
-reg dmf4535;\r
-reg xya29aa;\r
-reg xy14d53;\r
-reg ksa6a9a;\r
-reg xy354d1;\r
-reg dbaa68a;\r
-reg su53456;\r
-reg yz9a2b0;\r
-reg wwd1584;\r
-reg ir8ac21;\r
-reg qg5610c;\r
-reg jrb0860;\r
-reg zz84307;\r
-reg sw2183e;\r
-reg hdc1f0;\r
-reg kd60f86;\r
-reg ux7c34;\r
-reg ec3e1a4;\r
-reg mef0d21;\r
-reg vk86909;\r
-reg mg3484a;\r
-reg wla4251;\r
-reg ou2128d;\r
-reg fp9469;\r
-reg vv4a34e;\r
-reg wj51a77;\r
-reg co8d3bc;\r
-reg vi69de0;\r
-reg ip4ef02;\r
-reg qg77814;\r
-reg wybc0a0;\r
-reg wwe0500;\r
-reg qv2801;\r
-reg zm1400c;\r
-reg hda0063;\r
-reg ym31f;\r
-reg ls18f8;\r
-reg rvc7c3;\r
-reg lq63e1e;\r
-reg ec1f0f3;\r
-reg uvf8798;\r
-reg ipc3cc4;\r
-reg ng1e624;\r
-reg pff3122;\r
-reg sw98917;\r
-reg ayc48b8;\r
-reg ec245c1;\r
-reg db22e09;\r
-reg ux1704f;\r
-reg ngb827c;\r
-reg cmc13e2;\r
-reg tj9f10;\r
-reg hb4f887;\r
-reg jc7c43e;\r
-reg yxe21f2;\r
-reg aa10f94;\r
-reg ie87ca0;\r
-reg mg3e500;\r
-reg alf2801;\r
-reg bn9400c;\r
-reg xla0067;\r
-reg wy33f;\r
-reg vk19f8;\r
-reg tjcfc3;\r
-reg ea67e1f;\r
-reg ba3f0f9;\r
-reg qtf87cb;\r
-reg czc3e5c;\r
-reg qi1f2e4;\r
-reg nrf9720;\r
-reg cmcb906;\r
-reg ui5c830;\r
-reg rge4180;\r
-reg ba20c03;\r
-reg bn601a;\r
-reg ng300d7;\r
-reg an806ba;\r
-reg db35d4;\r
-reg co1aea7;\r
-reg jpd7539;\r
-reg fpba9ce;\r
-reg qgd4e76;\r
-reg hqa73b0;\r
-reg wl39d82;\r
-reg aycec15;\r
-reg fa760a8;\r
-reg tjb0543;\r
-reg uk82a1e;\r
-reg ec150f0;\r
-reg twa8781;\r
-reg ui43c0b;\r
-reg fc1e058;\r
-reg ayf02c2;\r
-reg bn81610;\r
-reg jeb086;\r
-reg dm58433;\r
-reg rtc219b;\r
-reg ks10cdf;\r
-reg ls866f8;\r
-reg qv337c3;\r
-reg db9be1d;\r
-reg psdf0ef;\r
-reg enf877a;\r
-reg kdc3bd4;\r
-reg ep1dea4;\r
-reg suef524;\r
-reg kd7a920;\r
-reg ead4904;\r
-reg qva4820;\r
-reg ou24104;\r
-reg do20821;\r
-reg pu410a;\r
-reg ri20852;\r
-reg xy4292;\r
-reg co21492;\r
-reg ksa491;\r
-reg lq52489;\r
-reg sw9244a;\r
-reg wy92250;\r
-reg fp91280;\r
-reg ba89407;\r
-reg pf4a03a;\r
-reg bl501d7;\r
-reg wl80ebf;\r
-reg an75fd;\r
-reg fc3afed;\r
-reg thd7f6a;\r
-reg lfbfb57;\r
-reg offdabe;\r
-reg qted5f5;\r
-reg yx6afad;\r
-reg jc57d6d;\r
-reg irbeb6b;\r
-reg osf5b5c;\r
-reg lsadae1;\r
-reg ea6d70a;\r
-reg hb6b851;\r
-reg cm5c28f;\r
-reg hoe1479;\r
-reg yma3cb;\r
-reg uv51e59;\r
-reg oh8f2cc;\r
-reg rg79665;\r
-reg iccb32a;\r
-reg ui59951;\r
-reg shcca88;\r
-reg yx65445;\r
-reg fc2a22d;\r
-reg kd5116a;\r
-reg ou88b55;\r
-reg th45aa9;\r
-reg db2d54f;\r
-reg yx6aa7f;\r
-reg ld553fd;\r
-reg wya9fef;\r
-reg rt4ff78;\r
-reg mr7fbc6;\r
-reg wjfde34;\r
-reg ayef1a5;\r
-reg ui78d28;\r
-reg mrc6941;\r
-reg [2047:0] bl7edd9;\r
-wire [306:0] nrf6ece;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam zmb7676 = 307,wlbb3b3 = 32'hfdffc68b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-AND2 ofe7218 (.A(ww62677), .B(fnc8624), .Z(su43126)); INV ux18931 (.A(qgc498c), .Z(fnc8624)); AND2 ir26308 (.A(nt133b8), .B(tw8c221), .Z(dz6110a)); INV ux8857 (.A(of442bd), .Z(tw8c221)); OR2 gqaf61 (.A(je99dc6), .B(gocee32), .Z(vvec21b)); XOR2 nr610df (.A(wl86ff), .B(yk437fc), .Z(pu1bfe1)); XOR2 hodff0b (.A(yk437fc), .B(jpfc2d8), .Z(xwe16c6)); XOR2 xyb633 (.A(jpfc2d8), .B(hbd8cdc), .Z(shc66e6)); XOR2 ux33735 (.A(hbd8cdc), .B(mrdcd6f), .Z(hbe6b7c)); XOR2 zm35be7 (.A(mrdcd6f), .B(ip6f9da), .Z(lq7ced5)); XOR2 she76ab (.A(ip6f9da), .B(nedaae1), .Z(rgd570b)); XOR2 uxab85b (.A(nedaae1), .B(hoe16e9), .Z(zmb74b)); XOR2 cz5ba5b (.A(hoe16e9), .B(nre96ef), .Z(al4b77f)); XOR2 kd5bbfd (.A(nre96ef), .B(ykeff6e), .Z(kd7fb71)); XOR2 gbfdb8c (.A(ykeff6e), .B(dz6e32c), .Z(vv71966)); XOR2 pu8cb37 (.A(al659bb), .B(sj2cddc), .Z(jc66ee4)); XOR2 rv37723 (.A(sj2cddc), .B(gbdc8fc), .Z(jce47e4)); XOR2 qv23f23 (.A(gbdc8fc), .B(hbfc8e9), .Z(lqe474f)); XOR2 gd23a7b (.A(hbfc8e9), .B(hbe9eed), .Z(bl4f76e)); XOR2 th7bb77 (.A(hbe9eed), .B(wjeddf6), .Z(rt6efb4)); XOR2 ea77da7 (.A(wjeddf6), .B(blf69c4), .Z(irb4e26)); XOR2 pua7135 (.A(blf69c4), .B(ayc4d57), .Z(gd26ab9)); XOR2 ri355cd (.A(ayc4d57), .B(dm57357), .Z(gqb9aba)); XOR2 fncd5d1 (.A(dm57357), .B(dm57475), .Z(jrba3aa)); XOR2 ayd1d57 (.A(dm57475), .B(qt755c6), .Z(zzaae34)); defparam rg571a7.initval = 16'h6996 ; ROM16X1A rg571a7 (.AD3(yxc69d3), .AD2(ks34e9c), .AD1(fca74e1), .AD0(fc3a70a), .DO0(wjd3853)); defparam hq9c29d.initval = 16'h6996 ; ROM16X1A hq9c29d (.AD3(gqa75b), .AD2(ea53ad9), .AD1(sw9d6c9), .AD0(faeb649), .DO0(kd5b24a)); defparam qtd9254.initval = 16'h6996 ; ROM16X1A qtd9254 (.AD3(fca74e1), .AD2(fc3a70a), .AD1(ip54b06), .AD0(ip54b06), .DO0(ux2c1a6)); defparam en60d35.initval = 16'h6996 ; ROM16X1A en60d35 (.AD3(ks34e9c), .AD2(fca74e1), .AD1(fc3a70a), .AD0(ip54b06), .DO0(fa66258)); defparam ec312c2.initval = 16'h6996 ; ROM16X1A ec312c2 (.AD3(faeb649), .AD2(yxc69d3), .AD1(ks34e9c), .AD0(ux2c1a6), .DO0(mg82af9)); defparam sw157c8.initval = 16'h6996 ; ROM16X1A sw157c8 (.AD3(sw9d6c9), .AD2(faeb649), .AD1(yxc69d3), .AD0(fa66258), .DO0(yzddb5)); defparam vv6edad.initval = 16'h6996 ; ROM16X1A vv6edad (.AD3(ea53ad9), .AD2(sw9d6c9), .AD1(faeb649), .AD0(wjd3853), .DO0(al7a1d4)); defparam hod0ea5.initval = 16'h6996 ; ROM16X1A hod0ea5 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(ip54b06), .AD0(ip54b06), .DO0(en5143a)); defparam ux8a1d5.initval = 16'h6996 ; ROM16X1A ux8a1d5 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(tud5b8a), .AD0(ip54b06), .DO0(ld6e292)); defparam hb71496.initval = 16'h6996 ; ROM16X1A hb71496 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(xy96d51), .AD0(tud5b8a), .DO0(jrb5458)); defparam vxaa2c6.initval = 16'h6996 ; ROM16X1A vxaa2c6 (.AD3(bn8b1b5), .AD2(xy96d51), .AD1(tud5b8a), .AD0(ip54b06), .DO0(xlb5ea4)); defparam hdaf527.initval = 16'h6996 ; ROM16X1A hdaf527 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(xlb5ea4), .AD0(ip54b06), .DO0(byf4138)); defparam jra09c2.initval = 16'h6996 ; ROM16X1A jra09c2 (.AD3(rv270b3), .AD2(zz3859e), .AD1(xjc2cf6), .AD0(fp167b6), .DO0(wyb3db6)); defparam vx9edb0.initval = 16'h6996 ; ROM16X1A vx9edb0 (.AD3(mgb6c3e), .AD2(qib61f0), .AD1(dbb0f81), .AD0(aa87c0f), .DO0(aa3e078)); defparam gof03c1.initval = 16'h6996 ; ROM16X1A gof03c1 (.AD3(xjc2cf6), .AD2(fp167b6), .AD1(ip54b06), .AD0(ip54b06), .DO0(rg47205)); defparam mt3902b.initval = 16'h6996 ; ROM16X1A mt3902b (.AD3(zz3859e), .AD2(xjc2cf6), .AD1(fp167b6), .AD0(ip54b06), .DO0(pfe6e08)); defparam nt37047.initval = 16'h6996 ; ROM16X1A nt37047 (.AD3(aa87c0f), .AD2(rv270b3), .AD1(zz3859e), .AD0(rg47205), .DO0(cmfa153)); defparam xwd0a99.initval = 16'h6996 ; ROM16X1A xwd0a99 (.AD3(dbb0f81), .AD2(aa87c0f), .AD1(rv270b3), .AD0(pfe6e08), .DO0(sh5441a)); defparam baa20d5.initval = 16'h6996 ; ROM16X1A baa20d5 (.AD3(qib61f0), .AD2(dbb0f81), .AD1(aa87c0f), .AD0(wyb3db6), .DO0(mr5165e)); defparam hd8b2f5.initval = 16'h6996 ; ROM16X1A hd8b2f5 (.AD3(wyb3db6), .AD2(aa3e078), .AD1(ip54b06), .AD0(ip54b06), .DO0(fa7914e)); defparam thc8a72.initval = 16'h6996 ; ROM16X1A thc8a72 (.AD3(wyb3db6), .AD2(aa3e078), .AD1(ww72fa5), .AD0(ip54b06), .DO0(cbbe941)); defparam tuf4a0c.initval = 16'h6996 ; ROM16X1A tuf4a0c (.AD3(wyb3db6), .AD2(aa3e078), .AD1(phc7fd), .AD0(ww72fa5), .DO0(gq1ff73)); defparam meffb99.initval = 16'h6996 ; ROM16X1A meffb99 (.AD3(byee645), .AD2(phc7fd), .AD1(ww72fa5), .AD0(ip54b06), .DO0(th454df)); defparam xy2a6fe.initval = 16'h6996 ; ROM16X1A xy2a6fe (.AD3(wyb3db6), .AD2(aa3e078), .AD1(th454df), .AD0(ip54b06), .DO0(yz90edd)); XOR2 sw876ec (.A(dz6e32c), .B(fp167b6), .Z(xjdd849)); XOR2 rtec24e (.A(fc3a70a), .B(qt755c6), .Z(me49dfe)); defparam cz4eff1.initval = 16'h0410 ; ROM16X1A cz4eff1 (.AD3(fpbfc60), .AD2(qt755c6), .AD1(fc3a70a), .AD0(ip54b06), .DO0(en60cda)); defparam zz66d4.initval = 16'h1004 ; ROM16X1A zz66d4 (.AD3(fpbfc60), .AD2(qt755c6), .AD1(fc3a70a), .AD0(ip54b06), .DO0(db3dcc3)); defparam faee61f.initval = 16'h0140 ; ROM16X1A faee61f (.AD3(wy987d3), .AD2(dz6e32c), .AD1(fp167b6), .AD0(ip54b06), .DO0(ipd3301)); defparam vk9980c.initval = 16'h4001 ; ROM16X1A vk9980c (.AD3(wy987d3), .AD2(dz6e32c), .AD1(fp167b6), .AD0(ip54b06), .DO0(ba14af1)); INV tja578a (.A(uvfde54), .Z(gd1d5e2)); AND2 xwf15cc (.A(oh8012e), .B(gd1d5e2), .Z(ukb98a2)); AND2 mrcc511 (.A(oh8012e), .B(uvfde54), .Z(doa230b)); defparam pu1185a.CSDECODE_B = "0b000" ; defparam pu1185a.CSDECODE_A = "0b000" ; defparam pu1185a.WRITEMODE_B = "NORMAL" ; defparam pu1185a.WRITEMODE_A = "NORMAL" ; defparam pu1185a.GSR = "ENABLED" ; defparam pu1185a.REGMODE_B = "NOREG" ; defparam pu1185a.REGMODE_A = "NOREG" ; defparam pu1185a.DATA_WIDTH_B = 18 ; defparam pu1185a.DATA_WIDTH_A = 18 ; DP16KC pu1185a (.DIA0(icdbb13[0]), .DIA1(icdbb13[1]), .DIA2(icdbb13[2]), .DIA3(icdbb13[3]), .DIA4(icdbb13[4]), .DIA5(icdbb13[5]), .DIA6(icdbb13[6]), .DIA7(icdbb13[7]), .DIA8(icdbb13[8]), .DIA9(icdbb13[9]), .DIA10(icdbb13[10]), .DIA11(icdbb13[11]), .DIA12(icdbb13[12]), .DIA13(icdbb13[13]), .DIA14(icdbb13[14]), .DIA15(icdbb13[15]), .DIA16(icdbb13[16]), .DIA17(icdbb13[17]), .ADA0(vve93e5), .ADA1(vve93e5), .ADA2(ip54b06), .ADA3(ip54b06), .ADA4(uie5e73), .ADA5(vk2f398), .ADA6(ho79cc2), .ADA7(kqce613), .ADA8(lq73099), .ADA9(mg984cb), .ADA10(ldc2659), .ADA11(rv132cf), .ADA12(pu9967e), .ADA13(gocb3f3), .CEA(su43126), .CLKA(fndd899), .OCEA(su43126), .WEA(vve93e5), .CSA0(ip54b06), .CSA1(ip54b06), .CSA2(ip54b06), .RSTA(je99dc6), .DIB0(ip54b06), .DIB1(ip54b06), .DIB2(ip54b06), .DIB3(ip54b06), .DIB4(ip54b06), .DIB5(ip54b06), .DIB6(ip54b06), .DIB7(ip54b06), .DIB8(ip54b06), .DIB9(ip54b06), .DIB10(ip54b06), .DIB11(ip54b06), .DIB12(ip54b06), .DIB13(ip54b06), .DIB14(ip54b06), .DIB15(ip54b06), .DIB16(ip54b06), .DIB17(ip54b06), .ADB0(ip54b06), .ADB1(ip54b06), .ADB2(ip54b06), .ADB3(ip54b06), .ADB4(icde57a), .ADB5(alf2bd0), .ADB6(an95e84), .ADB7(lfaf424), .ADB8(gb7a126), .ADB9(dmd0935), .ADB10(jr849aa), .ADB11(ym24d57), .ADB12(cb26ab8), .ADB13(ls355c5), .CEB(dz6110a), .CLKB(dzec4ce), .OCEB(dz6110a), .WEB(ip54b06), .CSB0(ip54b06), .CSB1(ip54b06), .CSB2(ip54b06), .RSTB(je99dc6), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOA9(), .DOA10(), .DOA11(), .DOA12(), .DOA13(), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(gbc640b[0]), .DOB1(gbc640b[1]), .DOB2(gbc640b[2]), .DOB3(gbc640b[3]), .DOB4(gbc640b[4]), .DOB5(gbc640b[5]), .DOB6(gbc640b[6]), .DOB7(gbc640b[7]), .DOB8(gbc640b[8]), .DOB9(gbc640b[9]), .DOB10(gbc640b[10]), .DOB11(gbc640b[11]), .DOB12(gbc640b[12]), .DOB13(gbc640b[13]), .DOB14(gbc640b[14]), .DOB15(gbc640b[15]), .DOB16(gbc640b[16]), .DOB17(gbc640b[17\r
-])) ; FD1P3BX fn7e468 (.D(mrcc0e7), .SP(su43126), .CK(fndd899), .PD(je99dc6), .Q(wl86ff)) ; FD1P3DX lf3dc02 (.D(co2ed68), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(yk437fc)) ; FD1P3DX bnba924 (.D(rg57660), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(jpfc2d8)) ; FD1P3DX do30804 (.D(aaac960), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hbd8cdc)) ; FD1P3DX ba1e655 (.D(fp32b4f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(mrdcd6f)) ; FD1P3DX ho576bf (.D(swa35b2), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ip6f9da)) ; FD1P3DX dmd57f8 (.D(qvd2ef), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(nedaae1)) ; FD1P3DX ir1de64 (.D(jr1c457), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hoe16e9)) ; FD1P3DX ba20771 (.D(lde38f6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(nre96ef)) ; FD1P3DX uv5e8b6 (.D(meff796), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ykeff6e)) ; FD1P3DX tjaa7c6 (.D(bl508a5), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(dz6e32c)) ; FD1P3DX qvb1965 (.D(pu1bfe1), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(oh8a7a4)) ; FD1P3DX fn6b927 (.D(xwe16c6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ld4f71c)) ; FD1P3DX ipf843b (.D(shc66e6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(uif5fa8)) ; FD1P3DX ofe7044 (.D(hbe6b7c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(jp7e0e8)) ; FD1P3DX ir26168 (.D(lq7ced5), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hbc2b1e)) ; FD1P3DX wl23bc4 (.D(rgd570b), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(rv816fe)) ; FD1P3DX gd2c04a (.D(zmb74b), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(co9d6b8)) ; FD1P3DX xyad5b6 (.D(al4b77f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(xw57c80)) ; FD1P3DX mg9d208 (.D(kd7fb71), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(gbedb34)) ; FD1P3DX ymf525 (.D(vv71966), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ep266b)) ; FD1P3DX os4c11c (.D(dz6e32c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ay72dd2)) ; FD1P3DX mt9f303 (.D(wl86ff), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(uie5e73)) ; FD1P3DX kf3cbb5 (.D(yk437fc), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(vk2f398)) ; FD1P3DX of415d9 (.D(jpfc2d8), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ho79cc2)) ; FD1P3DX ir2b25 (.D(hbd8cdc), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(kqce613)) ; FD1P3DX gqcad (.D(mrdcd6f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(lq73099)) ; FD1P3DX rt7e8d6 (.D(ip6f9da), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(mg984cb)) ; FD1P3DX gd9034b (.D(nedaae1), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ldc2659)) ; FD1P3DX ps7c711 (.D(hoe16e9), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(rv132cf)) ; FD1P3DX vxbf8e3 (.D(nre96ef), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(pu9967e)) ; FD1P3DX lsb7fde (.D(ykeff6e), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(gocb3f3)) ; FD1P3DX kfb1422 (.D(dz6e32c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(wy987d3)) ; FD1P3BX aa2edd6 (.D(tj91548), .SP(dz6110a), .CK(dzec4ce), .PD(vvec21b), .Q(al659bb)) ; FD1P3DX qg53d25 (.D(qte72d5), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(sj2cddc)) ; FD1P3DX vv7b8e7 (.D(gq21e87), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gbdc8fc)) ; FD1P3DX jrafd41 (.D(and471), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(hbfc8e9)) ; FD1P3DX ayf0747 (.D(mg24fde), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(hbe9eed)) ; FD1P3DX ec158f6 (.D(aa3b409), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(wjeddf6)) ; FD1P3DX hqb7f6 (.D(su53d87), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(blf69c4)) ; FD1P3DX hoeb5c1 (.D(mr7fe6a), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ayc4d57)) ; FD1P3DX qvbe403 (.D(ymfd6c), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dm57357)) ; FD1P3DX qg6d9a4 (.D(qi314e7), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dm57475)) ; FD1P3DX nt1335d (.D(gd2953a), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(qt755c6)) ; FD1P3DX zm96e90 (.D(jc66ee4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(sj95ca1)) ; FD1P3DX vidfd5b (.D(jce47e4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ls20f3f)) ; FD1P3DX hod0902 (.D(lqe474f), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(fpa5ac0)) ; FD1P3DX mgb9768 (.D(bl4f76e), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(uxbe6f6)) ; FD1P3DX mt2a70 (.D(rt6efb4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ip7f3bf)) ; FD1P3DX yz8b71 (.D(irb4e26), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ww781a8)) ; FD1P3DX fn7edcd (.D(gd26ab9), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ba1e4f6)) ; FD1P3DX qib33fb (.D(gqb9aba), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gdabfd5)) ; FD1P3DX vi52aeb (.D(jrba3aa), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ps79094)) ; FD1P3DX czed6ae (.D(zzaae34), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gqb3bde)) ; FD1P3DX ea7756d (.D(qt755c6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gqc04)) ; FD1P3DX ic72455 (.D(al659bb), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(icde57a)) ; FD1P3DX vi479cb (.D(sj2cddc), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(alf2bd0)) ; FD1P3DX qiac87a (.D(gbdc8fc), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(an95e84)) ; FD1P3DX jr38351 (.D(hbfc8e9), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(lfaf424)) ; FD1P3DX ba8c93f (.D(hbe9eed), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gb7a126)) ; FD1P3DX uif0ed0 (.D(wjeddf6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dmd0935)) ; FD1P3DX ui494f6 (.D(blf69c4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(jr849aa)) ; FD1P3DX yz39ff9 (.D(ayc4d57), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ym24d57)) ; FD1P3DX al543f5 (.D(dm57357), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(cb26ab8)) ; FD1P3DX kd60c53 (.D(dm57475), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ls355c5)) ; FD1P3DX nt38a54 (.D(qt755c6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(fpbfc60)) ; FD1S3DX byd5d12 (.D(oh8a7a4), .CK(dzec4ce), .CD(je99dc6), .Q(shc3703)) ; FD1S3DX yzae50c (.D(ld4f71c), .CK(dzec4ce), .CD(je99dc6), .Q(neeba75)) ; FD1S3DX cb79fa (.D(uif5fa8), .CK(dzec4ce), .CD(je99dc6), .Q(uv5bd24)) ; FD1S3DX hd2d606 (.D(jp7e0e8), .CK(dzec4ce), .CD(je99dc6), .Q(oh29703)) ; FD1S3DX nrf37b5 (.D(hbc2b1e), .CK(dzec4ce), .CD(je99dc6), .Q(nrec274)) ; FD1S3DX vvf9dfd (.D(rv816fe), .CK(dzec4ce), .CD(je99dc6), .Q(pu3ff3b)) ; FD1S3DX xwc0d40 (.D(co9d6b8), .CK(dzec4ce), .CD(je99dc6), .Q(vid0f0a)) ; FD1S3DX wjf27b2 (.D(xw57c80), .CK(dzec4ce), .CD(je99dc6), .Q(sj908ca)) ; FD1S3DX xj5fead (.D(gbedb34), .CK(dzec4ce), .CD(je99dc6), .Q(yma69d4)) ; FD1S3DX vvc84a2 (.D(ep266b), .CK(dzec4ce), .CD(je99dc6), .Q(tj948d)) ; FD1S3DX uk9def0 (.D(ay72dd2), .CK(dzec4ce), .CD(je99dc6), .Q(kq7758f)) ; FD1S3DX db6021 (.D(sj95ca1), .CK(fndd899), .CD(vvec21b), .Q(cmce96b))\r
- ; FD1S3DX rgd540c (.D(ls20f3f), .CK(fndd899), .CD(vvec21b), .Q(ldc7df2)) ; FD1S3DX enf7f9b (.D(fpa5ac0), .CK(fndd899), .CD(vvec21b), .Q(bnb0962)) ; FD1S3DX cb33fe6 (.D(uxbe6f6), .CK(fndd899), .CD(vvec21b), .Q(phbf54d)) ; FD1S3DX xl28fcf (.D(ip7f3bf), .CK(fndd899), .CD(vvec21b), .Q(go7861c)) ; FD1S3DX ls93ebd (.D(ww781a8), .CK(fndd899), .CD(vvec21b), .Q(qi5b38)) ; FD1S3DX wwe0e99 (.D(ba1e4f6), .CK(fndd899), .CD(vvec21b), .Q(hqe431)) ; FD1S3DX uk2b8fe (.D(gdabfd5), .CK(fndd899), .CD(vvec21b), .Q(os598c7)) ; FD1S3DX rt4f2d3 (.D(ps79094), .CK(fndd899), .CD(vvec21b), .Q(goc453f)) ; FD1S3DX osd1d61 (.D(gqb3bde), .CK(fndd899), .CD(vvec21b), .Q(thc74dd)) ; FD1S3DX ba353e8 (.D(gqc04), .CK(fndd899), .CD(vvec21b), .Q(pf7b9f0)) ; FD1S3DX xy86158 (.D(shc3703), .CK(dzec4ce), .CD(je99dc6), .Q(bn8b1b5)) ; FD1S3DX tw1b81d (.D(neeba75), .CK(dzec4ce), .CD(je99dc6), .Q(xy96d51)) ; FD1S3DX zk5d3ab (.D(uv5bd24), .CK(dzec4ce), .CD(je99dc6), .Q(tud5b8a)) ; FD1S3DX uide925 (.D(oh29703), .CK(dzec4ce), .CD(je99dc6), .Q(gqa75b)) ; FD1S3DX ip4b81d (.D(nrec274), .CK(dzec4ce), .CD(je99dc6), .Q(ea53ad9)) ; FD1S3DX bl613a7 (.D(pu3ff3b), .CK(dzec4ce), .CD(je99dc6), .Q(sw9d6c9)) ; FD1S3DX suff9da (.D(vid0f0a), .CK(dzec4ce), .CD(je99dc6), .Q(faeb649)) ; FD1S3DX uk87852 (.D(sj908ca), .CK(dzec4ce), .CD(je99dc6), .Q(yxc69d3)) ; FD1S3DX zz84654 (.D(yma69d4), .CK(dzec4ce), .CD(je99dc6), .Q(ks34e9c)) ; FD1S3DX ec34ea1 (.D(tj948d), .CK(dzec4ce), .CD(je99dc6), .Q(fca74e1)) ; FD1S3DX dz4a46e (.D(kq7758f), .CK(dzec4ce), .CD(je99dc6), .Q(fc3a70a)) ; FD1S3DX hdbac79 (.D(cmce96b), .CK(fndd899), .CD(vvec21b), .Q(byee645)) ; FD1S3DX xj74b58 (.D(ldc7df2), .CK(fndd899), .CD(vvec21b), .Q(phc7fd)) ; FD1S3DX ks3ef96 (.D(bnb0962), .CK(fndd899), .CD(vvec21b), .Q(ww72fa5)) ; FD1S3DX nt84b17 (.D(phbf54d), .CK(fndd899), .CD(vvec21b), .Q(mgb6c3e)) ; FD1S3DX wwfaa6f (.D(go7861c), .CK(fndd899), .CD(vvec21b), .Q(qib61f0)) ; FD1S3DX alc30e0 (.D(qi5b38), .CK(fndd899), .CD(vvec21b), .Q(dbb0f81)) ; FD1S3DX fp2d9c1 (.D(hqe431), .CK(fndd899), .CD(vvec21b), .Q(aa87c0f)) ; FD1S3DX me7218b (.D(os598c7), .CK(fndd899), .CD(vvec21b), .Q(rv270b3)) ; FD1S3DX wjcc638 (.D(goc453f), .CK(fndd899), .CD(vvec21b), .Q(zz3859e)) ; FD1S3DX zz229f8 (.D(thc74dd), .CK(fndd899), .CD(vvec21b), .Q(xjc2cf6)) ; FD1S3DX ba3a6ef (.D(pf7b9f0), .CK(fndd899), .CD(vvec21b), .Q(fp167b6)) ; FD1S3DX uvdcf86 (.D(viee26e), .CK(fndd899), .CD(je99dc6), .Q(yz129fb)) ; FD1S3DX bna5251 (.D(blddc4d), .CK(fndd899), .CD(je99dc6), .Q(zz94fdd)) ; FD1S3DX ww7d1e4 (.D(qgde08f), .CK(fndd899), .CD(je99dc6), .Q(do3f773)) ; FD1S3DX ls455a (.D(nt9bc11), .CK(fndd899), .CD(je99dc6), .Q(fafbb9b)) ; FD1S3DX ec97337 (.D(nr55090), .CK(fndd899), .CD(je99dc6), .Q(jcee6d6)) ; FD1S3DX mec1afa (.D(ecaa12), .CK(fndd899), .CD(je99dc6), .Q(ps736b2)) ; FD1S3DX pu8cf88 (.D(bye424c), .CK(fndd899), .CD(je99dc6), .Q(zkdac9e)) ; FD1S3DX ph19281 (.D(shdc849), .CK(fndd899), .CD(je99dc6), .Q(kdd64f3)) ; FD1S3DX fa7cff8 (.D(aa8858e), .CK(fndd899), .CD(je99dc6), .Q(ng93ce3)) ; FD1S3DX mt1d464 (.D(xj710b1), .CK(fndd899), .CD(je99dc6), .Q(ph9e71b)) ; FD1S3DX tj288f3 (.D(fp16be0), .CK(fndd899), .CD(je99dc6), .Q(ng9c6f6)) ; FD1S3DX byf4ab7 (.D(jr22256), .CK(dzec4ce), .CD(vvec21b), .Q(jr3e16)) ; FD1S3DX hodf65c (.D(rv8444a), .CK(dzec4ce), .CD(vvec21b), .Q(uk1f0b6)) ; FD1S3DX tj13a0c (.D(anb126c), .CK(dzec4ce), .CD(vvec21b), .Q(thc2d84)) ; FD1S3DX oh39b78 (.D(czd624d), .CK(dzec4ce), .CD(vvec21b), .Q(zz16c26)) ; FD1S3DX je2f10b (.D(jp5af9f), .CK(dzec4ce), .CD(vvec21b), .Q(lfb09b9)) ; FD1S3DX cmd105e (.D(db8b5f3), .CK(dzec4ce), .CD(vvec21b), .Q(ph84dcf)) ; FD1S3DX gq888a2 (.D(wj7502b), .CK(dzec4ce), .CD(vvec21b), .Q(rv373fd)) ; FD1S3DX pu8ced2 (.D(tueea05), .CK(dzec4ce), .CD(vvec21b), .Q(ieb9fef)) ; FD1S3DX wy982b2 (.D(mec13c4), .CK(dzec4ce), .CD(vvec21b), .Q(cz7fbca)) ; FD1S3DX aa8801f (.D(qi2bc57), .CK(dzec4ce), .CD(vvec21b), .Q(uvfde54)) ; FD1S3DX wjc6185 (.D(cb8ae62), .CK(dzec4ce), .CD(vvec21b), .Q(oh8012e)) ; FD1S3BX vv6b6ef (.D(ykdbbf4), .CK(dzec4ce), .PD(vvec21b), .Q(of442bd)) ; FD1S3DX byf438e (.D(doe394), .CK(fndd899), .CD(je99dc6), .Q(qgc498c)) ; FD1S3BX bn947f8 (.D(ym1fe39), .CK(dzec4ce), .PD(vvec21b), .Q(fp8177d)) ; FD1S3DX sj3926f (.D(su49be4), .CK(fndd899), .CD(je99dc6), .Q(pubbee)) ; FADD2B wje7c42 (.A0(ip54b06), .A1(vve93e5), .B0(ip54b06), .B1(vve93e5), .CI(ip54b06), .COUT(mga9411), .S0(), .S1()); CU2 nee42eb (.CI(mga9411), .PC0(wl86ff), .PC1(yk437fc), .CO(tueb653), .NC0(mrcc0e7), .NC1(co2ed68)); CU2 hoca6a5 (.CI(tueb653), .PC0(jpfc2d8), .PC1(hbd8cdc), .CO(hda5628), .NC0(rg57660), .NC1(aaac960)); CU2 byc51c2 (.CI(hda5628), .PC0(mrdcd6f), .PC1(ip6f9da), .CO(rtc259e), .NC0(fp32b4f), .NC1(swa35b2)); CU2 wyb3dea (.CI(rtc259e), .PC0(nedaae1), .PC1(hoe16e9), .CO(qgea1e2), .NC0(qvd2ef), .NC1(jr1c457)); CU2 gd3c430 (.CI(qgea1e2), .PC0(nre96ef), .PC1(ykeff6e), .CO(je30903), .NC0(lde38f6), .NC1(meff796)); CU2 pu206f9 (.CI(je30903), .PC0(dz6e32c), .PC1(ip54b06), .CO(dzf97da), .NC0(bl508a5), .NC1()); FADD2B rtcd253 (.A0(ip54b06), .A1(vve93e5), .B0(ip54b06), .B1(vve93e5), .CI(ip54b06), .COUT(blf31ce), .S0(), .S1()); CU2 hb5f6b0 (.CI(blf31ce), .PC0(al659bb), .PC1(sj2cddc), .CO(zzb0cdc), .NC0(tj91548), .NC1(qte72d5)); CU2 tj9b9dd (.CI(zzb0cdc), .PC0(gbdc8fc), .PC1(hbfc8e9), .CO(hbddf20), .NC0(gq21e87), .NC1(and471)); CU2 jce418b (.CI(hbddf20), .PC0(hbe9eed), .PC1(wjeddf6), .CO(lf8b6b8), .NC0(mg24fde), .NC1(aa3b409)); CU2 zxd71e3 (.CI(lf8b6b8), .PC0(blf69c4), .PC1(ayc4d57), .CO(rte3cf4), .NC0(su53d87), .NC1(mr7fe6a)); CU2 db9e9d6 (.CI(rte3cf4), .PC0(dm57357), .PC1(dm57475), .CO(end6ed2), .NC0(ymfd6c), .NC1(qi314e7)); CU2 hoda55d (.CI(end6ed2), .PC0(qt755c6), .PC1(ip54b06), .CO(xw5d5ed), .NC0(gd2953a), .NC1()); FSUB2B ne57b59 (.A0(vve93e5), .A1(wl86ff), .B0(ip54b06), .B1(yz90edd), .BI(ip54b06), .BOUT(of5bb89), .S0(), .S1(viee26e)); FSUB2B jp71372 (.A0(yk437fc), .A1(jpfc2d8), .B0(gq1ff73), .B1(cbbe941), .BI(of5bb89), .BOUT(oub3782), .S0(blddc4d), .S1(qgde08f)); FSUB2B kqf0478 (.A0(hbd8cdc), .A1(mrdcd6f), .B0(fa7914e), .B1(mr5165e), .BI(oub3782), .BOUT(hq1542), .S0(nt9bc11), .S1(nr55090)); FSUB2B nga8487 (.A0(ip6f9da), .A1(nedaae1), .B0(sh5441a), .B1(cmfa153), .BI(hq1542), .BOUT(aydb909), .S0(ecaa12), .S1(bye424c)); FSUB2B co21263 (.A0(hoe16e9), .A1(nre96ef), .B0(wyb3db6), .B1(pfe6e08), .BI(aydb909), .BOUT(icce216), .S0(shdc849), .S1(aa8858e)); FSUB2B fa42c70 (.A0(ykeff6e), .A1(xjdd849), .B0(rg47205), .B1(ip54b06), .BI(icce216), .BOUT(tu57f16), .S0(xj710b1), .S1(fp16be0)); FADD2B ic72f67 (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(tu57f16), .COUT(), .S0(fn4afe2), .S1()); VHI dbb5f07 (.Z(vve93e5)); FSUB2B xw7c1ff (.A0(vve93e5), .A1(byf4138), .B0(ip54b06), .B1(al659bb), .BI(ip54b06), .BOUT(rgd0889), .S0(), .S1(jr22256)); FSUB2B ls112b6 (.A0(jrb5458), .A1(ld6e292), .B0(sj2cddc), .B1(gbdc8fc), .BI(rgd0889), .BOUT(yz9ac49), .S0(rv8444a), .S1(anb126c)); FSUB2B zm89364 (.A0(en5143a), .A1(al7a1d4), .B0(hbfc8e9), .B1(hbe9eed), .BI(yz9ac49), .BOUT(fc116be), .S0(czd624d), .S1(jp5af9f)); FSUB2B nrd7cff (.A0(yzddb5), .A1(mg82af9), .B0(wjeddf6), .B1(blf69c4), .BI(fc116be), .\r
-BOUT(ipfdd40), .S0(db8b5f3), .S1(wj7502b)); FSUB2B twa815c (.A0(wjd3853), .A1(fa66258), .B0(ayc4d57), .B1(dm57357), .BI(ipfdd40), .BOUT(ym1f04f), .S0(tueea05), .S1(mec13c4)); FSUB2B vx9e20 (.A0(ux2c1a6), .A1(me49dfe), .B0(dm57475), .B1(ip54b06), .BI(ym1f04f), .BOUT(lf9fd1), .S0(qi2bc57), .S1(cb8ae62)); FADD2B cm77fdc (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(lf9fd1), .COUT(), .S0(sw213fa), .S1()); FADD2B xy30e89 (.A0(ip54b06), .A1(dz6110a), .B0(ip54b06), .B1(dz6110a), .CI(ip54b06), .COUT(go59655), .S0(), .S1()); AGEB2 zxf90a3 (.A0(al659bb), .A1(sj2cddc), .B0(byf4138), .B1(jrb5458), .CI(go59655), .GE(fnf64cb)); AGEB2 rib265f (.A0(gbdc8fc), .A1(hbfc8e9), .B0(ld6e292), .B1(en5143a), .CI(fnf64cb), .GE(fada633)); AGEB2 czd319a (.A0(hbe9eed), .A1(wjeddf6), .B0(al7a1d4), .B1(yzddb5), .CI(fada633), .GE(lfa0b69)); AGEB2 aa5b4e (.A0(blf69c4), .A1(ayc4d57), .B0(mg82af9), .B1(wjd3853), .CI(lfa0b69), .GE(zz8e2af)); AGEB2 dz7157f (.A0(dm57357), .A1(dm57475), .B0(fa66258), .B1(ux2c1a6), .CI(zz8e2af), .GE(vif4de2)); AGEB2 oua6f13 (.A0(en60cda), .A1(ip54b06), .B0(db3dcc3), .B1(ip54b06), .CI(vif4de2), .GE(goce132)); FADD2B gb70991 (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(goce132), .COUT(), .S0(ykdbbf4), .S1()); FADD2B cmef57b (.A0(ip54b06), .A1(su43126), .B0(ip54b06), .B1(su43126), .CI(ip54b06), .COUT(uic45be), .S0(), .S1()); AGEB2 tu7cf8d (.A0(wl86ff), .A1(yk437fc), .B0(yz90edd), .B1(gq1ff73), .CI(uic45be), .GE(xw5d2c7)); AGEB2 vve963b (.A0(jpfc2d8), .A1(hbd8cdc), .B0(cbbe941), .B1(fa7914e), .CI(xw5d2c7), .GE(kdfd5c3)); AGEB2 eaeae1c (.A0(mrdcd6f), .A1(ip6f9da), .B0(mr5165e), .B1(sh5441a), .CI(kdfd5c3), .GE(oua53b)); AGEB2 rg529d9 (.A0(nedaae1), .A1(hoe16e9), .B0(cmfa153), .B1(wyb3db6), .CI(oua53b), .GE(gb5e468)); AGEB2 kdf2344 (.A0(nre96ef), .A1(ykeff6e), .B0(pfe6e08), .B1(rg47205), .CI(gb5e468), .GE(ou2e02a)); AGEB2 en70150 (.A0(ipd3301), .A1(ip54b06), .B0(ba14af1), .B1(ip54b06), .CI(ou2e02a), .GE(xy250b7)); FADD2B zz285bb (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(xy250b7), .COUT(), .S0(doe394), .S1()); FADD2B vx943c6 (.A0(ip54b06), .A1(dz6110a), .B0(ip54b06), .B1(dz6110a), .CI(ip54b06), .COUT(swbc266), .S0(), .S1()); AGEB2 vvd7710 (.A0(ay77190[0]), .A1(ay77190[1]), .B0(jr3e16), .B1(uk1f0b6), .CI(swbc266), .GE(ou34b02)); AGEB2 nta5811 (.A0(ay77190[2]), .A1(ay77190[3]), .B0(thc2d84), .B1(zz16c26), .CI(ou34b02), .GE(sh75b56)); AGEB2 riadab5 (.A0(ay77190[4]), .A1(ay77190[5]), .B0(lfb09b9), .B1(ph84dcf), .CI(sh75b56), .GE(sh51a76)); AGEB2 wy8d3b4 (.A0(ay77190[6]), .A1(ay77190[7]), .B0(rv373fd), .B1(ieb9fef), .CI(sh51a76), .GE(ep28a7)); AGEB2 hq1453c (.A0(ay77190[8]), .A1(ay77190[9]), .B0(cz7fbca), .B1(uvfde54), .CI(ep28a7), .GE(do1b4e6)); AGEB2 lqda732 (.A0(doa230b), .A1(ip54b06), .B0(ukb98a2), .B1(ip54b06), .CI(do1b4e6), .GE(sj955b9)); FADD2B dbaadcd (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(sj955b9), .COUT(), .S0(ym1fe39), .S1()); FADD2B ks2e00f (.A0(ip54b06), .A1(su43126), .B0(ip54b06), .B1(su43126), .CI(ip54b06), .COUT(qgc48c9), .S0(), .S1()); AGEB2 qgcb3e2 (.A0(yz129fb), .A1(zz94fdd), .B0(dob8c81[0]), .B1(dob8c81[1]), .CI(qgc48c9), .GE(wy884a3)); AGEB2 zk42518 (.A0(do3f773), .A1(fafbb9b), .B0(dob8c81[2]), .B1(dob8c81[3]), .CI(wy884a3), .GE(sj1de2c)); AGEB2 ayef164 (.A0(jcee6d6), .A1(ps736b2), .B0(dob8c81[4]), .B1(dob8c81[5]), .CI(sj1de2c), .GE(zm173b)); AGEB2 twb9da (.A0(zkdac9e), .A1(kdd64f3), .B0(dob8c81[6]), .B1(dob8c81[7]), .CI(zm173b), .GE(wl90856)); AGEB2 fp842b4 (.A0(ng93ce3), .A1(ph9e71b), .B0(dob8c81[8]), .B1(dob8c81[9]), .CI(wl90856), .GE(ou31068)); AGEB2 gq88340 (.A0(ng9c6f6), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(ou31068), .GE(gq5871)); VLO cb2c389 (.Z(ip54b06)); FADD2B xye26e (.A0(ip54b06), .A1(ip54b06), .B0(ip54b06), .B1(ip54b06), .CI(gq5871), .COUT(), .S0(su49be4), .S1()); assign db3205d = xj6ecfe; assign cb902ef = by767f7;\r
- \r
-always@* begin hqbd2d7<={icdbb13>>1,nrf6ece[0]};jpe96ba<=nrf6ece[1];uv4b5d7<=nrf6ece[2];pf5aebd<=nrf6ece[3];jpd75ef<=nrf6ece[4];fpbaf7e<=nrf6ece[5];thd7bf6<=nrf6ece[6];jebdfb7<={ay77190>>1,nrf6ece[7]};ayefdbb<={dob8c81>>1,nrf6ece[8]};fpba667<=nrf6ece[9];wjd333f<=nrf6ece[10];do999fc<=nrf6ece[11];mrccfe2<=nrf6ece[12];ay67f15<=nrf6ece[13];vk3f8a9<=nrf6ece[14];rtfc54a<=nrf6ece[15];kde2a56<=nrf6ece[16];wy152b5<=nrf6ece[17];gqa95a9<=nrf6ece[18];xj4ad49<=nrf6ece[19];go56a4e<=nrf6ece[20];lfb5271<=nrf6ece[21];iea938e<=nrf6ece[22];kq49c71<=nrf6ece[23];mr4e389<=nrf6ece[24];dz71c4d<=nrf6ece[25];db8e26f<=nrf6ece[26];jp7137f<=nrf6ece[27];tw89bfe<=nrf6ece[28];fa4dff3<=nrf6ece[29];yx6ff9b<=nrf6ece[30];kd7fcdd<=nrf6ece[31];fafe6ec<=nrf6ece[32];xjf3763<=nrf6ece[33];hd9bb1f<=nrf6ece[34];xjdd8ff<=nrf6ece[35];rtec7fe<=nrf6ece[36];fa63ff7<=nrf6ece[37];ie1ffbb<=nrf6ece[38];cmffdd9<=nrf6ece[39];tufeec8<=nrf6ece[40];alf7642<=nrf6ece[41];epbb215<=nrf6ece[42];ofd90ad<=nrf6ece[43];blc856d<=nrf6ece[44];ne42b6e<=nrf6ece[45];aa15b72<=nrf6ece[46];jeadb90<=nrf6ece[47];os6dc82<=nrf6ece[48];fn6e410<=nrf6ece[49];ic72086<=nrf6ece[50];qv90431<=nrf6ece[51];ks8218d<=nrf6ece[52];gq10c69<=nrf6ece[53];fc86348<=nrf6ece[54];sw31a43<=nrf6ece[55];qi8d219<=nrf6ece[56];dm690c8<=nrf6ece[57];xw48643<=nrf6ece[58];go4321a<=nrf6ece[59];db190d1<=nrf6ece[60];rtc868f<=nrf6ece[61];kq4347e<=nrf6ece[62];gq1a3f1<=nrf6ece[63];icd1f88<=nrf6ece[64];wl8fc40<=nrf6ece[65];bl7e204<=nrf6ece[66];psf1027<=nrf6ece[67];ou8813a<=nrf6ece[68];pf409d0<=nrf6ece[69];vk4e87<=nrf6ece[70];tj2743b<=nrf6ece[71];ng3a1de<=nrf6ece[72];hod0ef3<=nrf6ece[73];mg8779a<=nrf6ece[74];wy3bcd1<=nrf6ece[75];wwde688<=nrf6ece[76];jpf3440<=nrf6ece[77];yz9a207<=nrf6ece[78];wwd103c<=nrf6ece[79];gq881e1<=nrf6ece[80];dz40f08<=nrf6ece[81];ep7847<=nrf6ece[82];ir3c23c<=nrf6ece[83];pse11e4<=nrf6ece[84];mt8f23<=nrf6ece[85];by4791d<=nrf6ece[86];kf3c8ea<=nrf6ece[87];jce4755<=nrf6ece[88];qv23aab<=nrf6ece[89];ux1d55d<=nrf6ece[90];uieaaed<=nrf6ece[91];fn55769<=nrf6ece[92];cbabb4f<=nrf6ece[93];ps5da7d<=nrf6ece[94];ened3ea<=nrf6ece[95];fa69f55<=nrf6ece[96];ld4faaa<=nrf6ece[97];os7d556<=nrf6ece[98];kqeaab0<=nrf6ece[99];dz55581<=nrf6ece[100];ntaac0f<=nrf6ece[101];yk5607f<=nrf6ece[102];vxb03f8<=nrf6ece[103];nt81fc6<=nrf6ece[104];ecfe37<=nrf6ece[105];mr7f1b8<=nrf6ece[106];alf8dc5<=nrf6ece[107];ipc6e2d<=nrf6ece[108];ph3716c<=nrf6ece[109];twb8b67<=nrf6ece[110];dmc5b3b<=nrf6ece[111];fp2d9db<=nrf6ece[112];jc6cede<=nrf6ece[113];os676f2<=nrf6ece[114];ym3b790<=nrf6ece[115];qgdbc81<=nrf6ece[116];osde409<=nrf6ece[117];wjf2048<=nrf6ece[118];yz90245<=nrf6ece[119];zz8122d<=nrf6ece[120];vx916e<=nrf6ece[121];rg48b76<=nrf6ece[122];rt45bb3<=nrf6ece[123];nt2dd9f<=nrf6ece[124];xj6ecfe<=nrf6ece[125];by767f7<=nrf6ece[126];ksb3fbb<=nrf6ece[127];cb9fdd8<=nrf6ece[128];hofeec5<=nrf6ece[129];ipf762a<=nrf6ece[130];qvbb155<=nrf6ece[131];hbd8aad<=nrf6ece[132];rgc556e<=nrf6ece[133];hq2ab72<=nrf6ece[134];fn55b93<=nrf6ece[135];xyadc9e<=nrf6ece[136];zx6e4f2<=nrf6ece[137];me72796<=nrf6ece[138];vk93cb1<=nrf6ece[139];bn9e58b<=nrf6ece[140];wjf2c5e<=nrf6ece[141];tw962f4<=nrf6ece[142];gdb17a2<=nrf6ece[143];xl8bd14<=nrf6ece[144];ip5e8a6<=nrf6ece[145];dmf4535<=nrf6ece[146];xya29aa<=nrf6ece[147];xy14d53<=nrf6ece[148];ksa6a9a<=nrf6ece[149];xy354d1<=nrf6ece[150];dbaa68a<=nrf6ece[151];su53456<=nrf6ece[152];yz9a2b0<=nrf6ece[153];wwd1584<=nrf6ece[154];ir8ac21<=nrf6ece[155];qg5610c<=nrf6ece[156];jrb0860<=nrf6ece[157];zz84307<=nrf6ece[158];sw2183e<=nrf6ece[159];hdc1f0<=nrf6ece[160];kd60f86<=nrf6ece[161];ux7c34<=nrf6ece[162];ec3e1a4<=nrf6ece[163];mef0d21<=nrf6ece[164];vk86909<=nrf6ece[165];mg3484a<=nrf6ece[166];wla4251<=nrf6ece[167];ou2128d<=nrf6ece[168];fp9469<=nrf6ece[169];vv4a34e<=nrf6ece[170];wj51a77<=nrf6ece[171];co8d3bc<=nrf6ece[172];vi69de0<=nrf6ece[173];ip4ef02<=nrf6ece[174];qg77814<=nrf6ece[175];wybc0a0<=nrf6ece[176];wwe0500<=nrf6ece[177];qv2801<=nrf6ece[178];zm1400c<=nrf6ece[179];hda0063<=nrf6ece[180];ym31f<=nrf6ece[181];ls18f8<=nrf6ece[182];rvc7c3<=nrf6ece[183];lq63e1e<=nrf6ece[184];ec1f0f3<=nrf6ece[185];uvf8798<=nrf6ece[186];ipc3cc4<=nrf6ece[187];ng1e624<=nrf6ece[188];pff3122<=nrf6ece[189];sw98917<=nrf6ece[190];ayc48b8<=nrf6ece[191];ec245c1<=nrf6ece[192];db22e09<=nrf6ece[193];ux1704f<=nrf6ece[194];ngb827c<=nrf6ece[195];cmc13e2<=nrf6ece[196];tj9f10<=nrf6ece[197];hb4f887<=nrf6ece[198];jc7c43e<=nrf6ece[199];yxe21f2<=nrf6ece[200];aa10f94<=nrf6ece[201];ie87ca0<=nrf6ece[202];mg3e500<=nrf6ece[203];alf2801<=nrf6ece[204];bn9400c<=nrf6ece[205];xla0067<=nrf6ece[206];wy33f<=nrf6ece[207];vk19f8<=nrf6ece[208];tjcfc3<=nrf6ece[209];ea67e1f<=nrf6ece[210];ba3f0f9<=nrf6ece[211];qtf87cb<=nrf6ece[212];czc3e5c<=nrf6ece[213];qi1f2e4<=nrf6ece[214];nrf9720<=nrf6ece[215];cmcb906<=nrf6ece[216];ui5c830<=nrf6ece[217];rge4180<=nrf6ece[218];ba20c03<=nrf6ece[219];bn601a<=nrf6ece[220];ng300d7<=nrf6ece[221];an806ba<=nrf6ece[222];db35d4<=nrf6ece[223];co1aea7<=nrf6ece[224];jpd7539<=nrf6ece[225];fpba9ce<=nrf6ece[226];qgd4e76<=nrf6ece[227];hqa73b0<=nrf6ece[228];wl39d82<=nrf6ece[229];aycec15<=nrf6ece[230];fa760a8<=nrf6ece[231];tjb0543<=nrf6ece[232];uk82a1e<=nrf6ece[233];ec150f0<=nrf6ece[234];twa8781<=nrf6ece[235];ui43c0b<=nrf6ece[236];fc1e058<=nrf6ece[237];ayf02c2<=nrf6ece[238];bn81610<=nrf6ece[239];jeb086<=nrf6ece[240];dm58433<=nrf6ece[241];rtc219b<=\r
-nrf6ece[242];ks10cdf<=nrf6ece[243];ls866f8<=nrf6ece[244];qv337c3<=nrf6ece[245];db9be1d<=nrf6ece[246];psdf0ef<=nrf6ece[247];enf877a<=nrf6ece[248];kdc3bd4<=nrf6ece[249];ep1dea4<=nrf6ece[250];suef524<=nrf6ece[251];kd7a920<=nrf6ece[252];ead4904<=nrf6ece[253];qva4820<=nrf6ece[254];ou24104<=nrf6ece[255];do20821<=nrf6ece[256];pu410a<=nrf6ece[257];ri20852<=nrf6ece[258];xy4292<=nrf6ece[259];co21492<=nrf6ece[260];ksa491<=nrf6ece[261];lq52489<=nrf6ece[262];sw9244a<=nrf6ece[263];wy92250<=nrf6ece[264];fp91280<=nrf6ece[265];ba89407<=nrf6ece[266];pf4a03a<=nrf6ece[267];bl501d7<=nrf6ece[268];wl80ebf<=nrf6ece[269];an75fd<=nrf6ece[270];fc3afed<=nrf6ece[271];thd7f6a<=nrf6ece[272];lfbfb57<=nrf6ece[273];offdabe<=nrf6ece[274];qted5f5<=nrf6ece[275];yx6afad<=nrf6ece[276];jc57d6d<=nrf6ece[277];irbeb6b<=nrf6ece[278];osf5b5c<=nrf6ece[279];lsadae1<=nrf6ece[280];ea6d70a<=nrf6ece[281];hb6b851<=nrf6ece[282];cm5c28f<=nrf6ece[283];hoe1479<=nrf6ece[284];yma3cb<=nrf6ece[285];uv51e59<=nrf6ece[286];oh8f2cc<=nrf6ece[287];rg79665<=nrf6ece[288];iccb32a<=nrf6ece[289];ui59951<=nrf6ece[290];shcca88<=nrf6ece[291];yx65445<=nrf6ece[292];fc2a22d<=nrf6ece[293];kd5116a<=nrf6ece[294];ou88b55<=nrf6ece[295];th45aa9<=nrf6ece[296];db2d54f<=nrf6ece[297];yx6aa7f<=nrf6ece[298];ld553fd<=nrf6ece[299];wya9fef<=nrf6ece[300];rt4ff78<=nrf6ece[301];mr7fbc6<=nrf6ece[302];wjfde34<=nrf6ece[303];ayef1a5<=nrf6ece[304];ui78d28<=nrf6ece[305];mrc6941<=nrf6ece[306];end\r
-always@* begin bl7edd9[2047]<=fndd899;bl7edd9[2046]<=dzec4ce;bl7edd9[2044]<=ww62677;bl7edd9[2043]<=tu57f16;bl7edd9[2040]<=nt133b8;bl7edd9[2038]<=jr22256;bl7edd9[2032]<=je99dc6;bl7edd9[2029]<=vve93e5;bl7edd9[2017]<=gocee32;bl7edd9[2013]<=go7861c;bl7edd9[2010]<=rv8444a;bl7edd9[2003]<=sj955b9;bl7edd9[1990]<=tueb653;bl7edd9[1987]<=ay77190[0];bl7edd9[1982]<=uvfde54;bl7edd9[1980]<=an95e84;bl7edd9[1979]<=dbb0f81;bl7edd9[1973]<=anb126c;bl7edd9[1963]<=rv132cf;bl7edd9[1958]<=su43126;bl7edd9[1957]<=thc74dd;bl7edd9[1953]<=cbbe941;bl7edd9[1942]<=ym24d57;bl7edd9[1932]<=fp32b4f;bl7edd9[1929]<=blddc4d;bl7edd9[1926]<=dob8c81[0];bl7edd9[1923]<=lf8b6b8;bl7edd9[1921]<=al4b77f;bl7edd9[1917]<=do1b4e6;bl7edd9[1914]<=os598c7;bl7edd9[1913]<=lfaf424;bl7edd9[1911]<=qi5b38;bl7edd9[1903]<=irb4e26;bl7edd9[1898]<=rgd0889;bl7edd9[1879]<=pu9967e;bl7edd9[1876]<=nrec274;bl7edd9[1872]<=xw57c80;bl7edd9[1868]<=qgc48c9;bl7edd9[1866]<=fp167b6;bl7edd9[1863]<=ou2e02a;bl7edd9[1858]<=fa7914e;bl7edd9[1837]<=cb26ab8;bl7edd9[1816]<=swa35b2;bl7edd9[1810]<=qgde08f;bl7edd9[1805]<=fnc8624;bl7edd9[1802]<=uk1f0b6;bl7edd9[1799]<=ymfd6c;bl7edd9[1795]<=kd7fb71;bl7edd9[1786]<=ukb98a2;bl7edd9[1783]<=zzaae34;bl7edd9[1780]<=zz3859e;bl7edd9[1778]<=gb7a126;bl7edd9[1775]<=aa87c0f;bl7edd9[1770]<=hbc2b1e;bl7edd9[1758]<=gd26ab9;bl7edd9[1748]<=czd624d;bl7edd9[1710]<=gocb3f3;bl7edd9[1704]<=sw9d6c9;bl7edd9[1701]<=ux2c1a6;bl7edd9[1699]<=db8b5f3;bl7edd9[1696]<=gbedb34;bl7edd9[1689]<=yz129fb;bl7edd9[1685]<=pf7b9f0;bl7edd9[1679]<=pu1bfe1;bl7edd9[1678]<=ba14af1;bl7edd9[1668]<=jpfc2d8;bl7edd9[1627]<=ls355c5;bl7edd9[1624]<=me49dfe;bl7edd9[1605]<=jcee6d6;bl7edd9[1589]<=wjd3853;bl7edd9[1584]<=hda5628;bl7edd9[1573]<=of5bb89;bl7edd9[1572]<=al659bb;bl7edd9[1567]<=ldc7df2;bl7edd9[1562]<=tw8c221;bl7edd9[1557]<=qte72d5;bl7edd9[1556]<=ou34b02;bl7edd9[1551]<=qi314e7;bl7edd9[1548]<=meff796;bl7edd9[1543]<=vv71966;bl7edd9[1524]<=doa230b;bl7edd9[1521]<=rg57660;bl7edd9[1519]<=icde57a;bl7edd9[1513]<=goc453f;bl7edd9[1512]<=yk437fc;bl7edd9[1509]<=dmd0935;bl7edd9[1504]<=su53d87;bl7edd9[1502]<=hqe431;bl7edd9[1499]<=bl4f76e;bl7edd9[1493]<=oh29703;bl7edd9[1492]<=rv816fe;bl7edd9[1469]<=gqb9aba;bl7edd9[1466]<=uif5fa8;bl7edd9[1448]<=jp5af9f;bl7edd9[1421]<=lfa0b69;bl7edd9[1417]<=byf4138;bl7edd9[1415]<=cmce96b;bl7edd9[1404]<=co2ed68;bl7edd9[1402]<=gq1ff73;bl7edd9[1400]<=aa3b409;bl7edd9[1398]<=jce47e4;bl7edd9[1377]<=kq7758f;bl7edd9[1374]<=uic45be;bl7edd9[1373]<=wy987d3;bl7edd9[1361]<=pu3ff3b;bl7edd9[1359]<=aa8858e;bl7edd9[1355]<=bn8b1b5;bl7edd9[1354]<=dm57357;bl7edd9[1350]<=wj7502b;bl7edd9[1349]<=vid0f0a;bl7edd9[1344]<=ep266b;bl7edd9[1343]<=xj710b1;bl7edd9[1341]<=sh51a76;bl7edd9[1330]<=zz94fdd;bl7edd9[1326]<=xy96d51;bl7edd9[1323]<=oh8012e;bl7edd9[1322]<=vif4de2;bl7edd9[1310]<=xwe16c6;bl7edd9[1308]<=ipd3301;bl7edd9[1305]<=tueea05;bl7edd9[1301]<=sj908ca;bl7edd9[1289]<=hbd8cdc;bl7edd9[1286]<=ou31068;bl7edd9[1280]<=sj95ca1;bl7edd9[1279]<=icce216;bl7edd9[1271]<=ieb9fef;bl7edd9[1224]<=do3f773;bl7edd9[1210]<=tud5b8a;bl7edd9[1207]<=fpbfc60;bl7edd9[1201]<=sw213fa;bl7edd9[1199]<=qgc498c;bl7edd9[1195]<=en60cda;bl7edd9[1193]<=bye424c;bl7edd9[1163]<=gbdc8fc;bl7edd9[1162]<=ps736b2;bl7edd9[1155]<=cmfa153;bl7edd9[1144]<=hbe6b7c;bl7edd9[1136]<=xy250b7;bl7edd9[1130]<=blf69c4;bl7edd9[1125]<=ipfdd40;bl7edd9[1120]<=qvd2ef;bl7edd9[1112]<=al7a1d4;bl7edd9[1110]<=yma69d4;bl7edd9[1104]<=kdd64f3;bl7edd9[1098]<=nt9bc11;bl7edd9[1096]<=sj2cddc;bl7edd9[1086]<=ww72fa5;bl7edd9[1076]<=xlb5ea4;bl7edd9[1067]<=blf31ce;bl7edd9[1065]<=thc2d84;bl7edd9[1060]<=mr5165e;bl7edd9[1054]<=rte3cf4;bl7edd9[1053]<=hoe16e9;bl7edd9[1051]<=su49be4;bl7edd9[1048]<=qgea1e2;bl7edd9[1039]<=uie5e73;bl7edd9[1026]<=fpa5ac0;bl7edd9[1023]<=icdbb13[0];bl7edd9[1021]<=fn4afe2;bl7edd9[1006]<=qib61f0;bl7edd9[1001]<=ym1fe39;bl7edd9[995]<=aaac960;bl7edd9[991]<=cz7fbca;bl7edd9[990]<=alf2bd0;bl7edd9[981]<=ldc2659;bl7edd9[978]<=xjc2cf6;bl7edd9[976]<=xw5d2c7;bl7edd9[971]<=jr849aa;bl7edd9[964]<=viee26e;bl7edd9[961]<=mr7fe6a;bl7edd9[960]<=zmb74b;bl7edd9[957]<=rv270b3;bl7edd9[951]<=rt6efb4;bl7edd9[938]<=ea53ad9;bl7edd9[936]<=co9d6b8;bl7edd9[931]<=ykeff6e;bl7edd9[901]<=jr3e16;bl7edd9[891]<=jrba3aa;bl7edd9[885]<=jp7e0e8;bl7edd9[850]<=fa66258;bl7edd9[849]<=yz9ac49;bl7edd9[839]<=gd1d5e2;bl7edd9[812]<=ym1f04f;bl7edd9[802]<=sj1de2c;bl7edd9[794]<=mg82af9;bl7edd9[786]<=jrb5458;bl7edd9[783]<=phc7fd;bl7edd9[778]<=tj91548;bl7edd9[774]<=lde38f6;bl7edd9[760]<=mga9411;bl7edd9[756]<=wl86ff;bl7edd9[752]<=hbddf20;bl7edd9[749]<=lqe474f;bl7edd9[746]<=gqa75b;bl7edd9[733]<=ld4f71c;bl7edd9[710]<=wjeddf6;bl7edd9[708]<=go59655;bl7edd9[707]<=byee645;bl7edd9[702]<=mrcc0e7;bl7edd9[701]<=yz90edd;bl7edd9[700]<=mg24fde;bl7edd9[699]<=jc66ee4;bl7edd9[688]<=fc3a70a;bl7edd9[687]<=goce132;bl7edd9[679]<=shdc849;bl7edd9[677]<=gqc04;bl7edd9[674]<=faeb649;bl7edd9[671]<=aydb909;bl7edd9[670]<=ph84dcf;bl7edd9[663]<=shc3703;bl7edd9[661]<=dm57475;bl7edd9[652]<=fc116be;bl7edd9[650]<=yxc69d3;bl7edd9[643]<=ph9e71b;bl7edd9[640]<=ay72dd2;bl7edd9[639]<=fp16be0;bl7edd9[635]<=rv373fd;bl7edd9[612]<=wy884a3;bl7edd9[605]<=neeba75;bl7edd9[599]<=of442bd;bl7edd9[597]<=db3dcc3;bl7edd9[596]<=ecaa12;bl7edd9[581]<=en5143a;bl7edd9[577]<=oua53b;bl7edd9[572]<=shc66e6;bl7edd9[568]<=doe394;bl7edd9[562]<=mec13c4;bl7edd9[556]<=fada633;bl7edd9[555]<=ks34e9c;bl7edd9[552]<=zkdac9e;bl7edd9[530]<=kdfd5c3;bl7edd9[526]<=nedaae1;bl7edd9[525]<=ng9c6f6;bl7edd9[513]<=ls20f3f;bl7edd9[510]<=xjdd849;bl7edd9[503]<=phbf54d;bl7edd9[495]<=ep28a7;bl7edd9[490]<=mg984cb;bl7edd9[482]<=end6ed2;bl7edd9[480]<=rgd570b;bl7edd9[465]<=nre96ef;bl7edd9[450]<=swbc266;bl7edd9[425]<=zz8e2af;bl7edd9[419]<=aa3e078;bl7edd9[406]<=cb8ae62;bl7edd9[401]<=fafbb9b;bl7edd9[389]<=je30903;bl7edd9[387]<=rtc259e;bl7edd9[373]<=uv5bd24;bl7edd9[366]<=oh8a7a4;bl7edd9[355]<=hbe9eed;bl7edd9[354]<=lf9fd1;bl7edd9[351]<=vvec21b;bl7edd9[350]<=zzb0cdc;bl7edd9[344]<=tj948d;bl7edd9[343]<=ykdbbf4;bl7edd9[339]<=hq1542;bl7edd9[338]<=gqb3bde;bl7edd9[335]<=lfb09b9;bl7edd9[321]<=ng93ce3;bl7edd9[298]<=oub3782;bl7edd9[290]<=ld6e292;bl7edd9[288]<=ip6f9da;bl7edd9[278]<=hbfc8e9;bl7edd9[276]<=zm173b;bl7edd9[263]<=wyb3db6;bl7edd9[251]<=mgb6c3e;bl7edd9[245]<=lq73099;bl7edd9[241]<=qt755c6;bl7edd9[240]<=lq7ced5;bl7edd9[232]<=rg47205;bl7edd9[225]<=dz6110a;bl7edd9[212]<=ayc4d57;bl7edd9[209]<=th454df;bl7edd9[203]<=qi2bc57;bl7edd9[194]<=dz6e32c;bl7edd9[193]<=jr1c457;bl7edd9[177]<=yzddb5;bl7edd9[175]<=and471;bl7edd9[172]<=fca74e1;bl7edd9[169]<=ps79094;bl7edd9[167]<=sh75b56;bl7edd9[160]<=wl90856;bl7edd9[149]<=nr55090;bl7edd9[145]<=fnf64cb;bl7edd9[144]<=mrdcd6f;bl7edd9[125]<=bnb0962;bl7edd9[122]<=kqce613;bl7edd9[120]<=xw5d5ed;bl7edd9[116]<=pfe6e08;bl7edd9[109]<=ip54b06;bl7edd9[104]<=kd5b24a;bl7edd9[97]<=dzf97da;bl7edd9[87]<=gq21e87;bl7edd9[84]<=gdabfd5;bl7edd9[83]<=zz16c26;bl7edd9[72]<=sh5441a;bl7edd9[61]<=ho79cc2;bl7edd9[60]<=gd2953a;\r
-bl7edd9[58]<=gb5e468;bl7edd9[54]<=gq5871;bl7edd9[48]<=bl508a5;bl7edd9[42]<=ba1e4f6;bl7edd9[30]<=vk2f398;bl7edd9[21]<=ww781a8;bl7edd9[10]<=ip7f3bf;bl7edd9[5]<=uxbe6f6;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module oh39ef9 (rst_n,\r
- gbe_mode,\r
- lqdf35e,\r
-\r
- zxf9af2,\r
-\r
- blcd797,\r
- pf6bcbe,\r
- qt5e5f7,\r
-\r
- mrf2fbc,\r
- qi97de4,\r
- mtbef21,\r
- wjf790c\r
- );\r
-input rst_n;\r
-input gbe_mode;\r
-input lqdf35e;\r
-input [1:0] zxf9af2;\r
-input [7:0] blcd797;\r
-input pf6bcbe;\r
-input qt5e5f7;\r
-input mrf2fbc;\r
-output [7:0] qi97de4;\r
-output mtbef21;\r
-output wjf790c;\r
-reg [7:0] qi97de4;\r
-reg mtbef21;\r
-reg wjf790c;\r
-reg [1:0] oub3c7c;\r
-reg [1:0] jr9e3e0;\r
-reg [1:0] hof1f06;\r
-reg [1:0] ir8f833;\r
-reg [1:0] rg7c19c;\r
-reg [1:0] ice0ce2;\r
-reg fp6710;\r
-reg ux33887;\r
-reg do9c43c;\r
-reg qte21e3;\r
-reg [7:0] ou10f1c;\r
-reg qi878e0;\r
-reg an3c700;\r
-reg [7:0] fne3804;\r
-reg lf1c027;\r
-reg aye013f;\r
-reg [7:0] uk9f9;\r
-reg je4fc9;\r
-reg bn27e4b;\r
-reg do3f25f;\r
-wire hbf92fb;\r
-wire ipc97de;\r
-wire [7:0] sh4bef4;\r
-wire vv5f7a4;\r
-reg zkfbd26;\r
-reg uide932;\r
-reg vif4991;\r
-reg qva4c8b;\r
-reg qv2645c;\r
-reg rv322e4;\r
-reg lf91727;\r
-reg zz8b93f;\r
-reg [6:0] ww5c9fe;\r
-reg hoe4ff0;\r
-reg xl27f82;\r
-reg xy3fc17;\r
-reg fafe0ba;\r
-reg uif05d3;\r
-reg co82e98;\r
-reg sj174c0;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-`endif\r
-reg zzba604;\r
-reg [1 : 0] ald3027;\r
-reg [7 : 0] ie9813c;\r
-reg dmc09e1;\r
-reg do4f0b;\r
-reg [1 : 0] fp2785b;\r
-reg [1 : 0] kf3c2df;\r
-reg [1 : 0] fae16fc;\r
-reg [1 : 0] jeb7e3;\r
-reg [1 : 0] en5bf1b;\r
-reg [1 : 0] xwdf8dd;\r
-reg vvfc6eb;\r
-reg rte375e;\r
-reg xy1baf6;\r
-reg vvdd7b3;\r
-reg [7 : 0] dmebd9f;\r
-reg yx5ecfb;\r
-reg dzf67dd;\r
-reg [7 : 0] aab3eef;\r
-reg an9f778;\r
-reg nefbbc4;\r
-reg [7 : 0] fndde22;\r
-reg ayef116;\r
-reg ui788b0;\r
-reg kqc4581;\r
-reg fp22c08;\r
-reg lf16047;\r
-reg [7 : 0] vxb023e;\r
-reg nt811f6;\r
-reg cb8fb6;\r
-reg zk47db5;\r
-reg sw3edaa;\r
-reg thf6d50;\r
-reg ukb6a86;\r
-reg fpb5430;\r
-reg phaa186;\r
-reg nr50c36;\r
-reg [6 : 0] je861b6;\r
-reg zm30db3;\r
-reg vk86d9b;\r
-reg oh36cda;\r
-reg gqb66d4;\r
-reg ymb36a1;\r
-reg ph9b509;\r
-reg dmda84e;\r
-reg [2047:0] bl7edd9;\r
-wire [44:0] nrf6ece;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-localparam zmb7676 = 45,wlbb3b3 = 32'hfdffca8b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-\r
-always @(posedge lqdf35e or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vif4991 <= 1'd1; qva4c8b <= 1'd1; end else begin vif4991 <= zk47db5; qva4c8b <= sw3edaa; end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge lqdf35e or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qv2645c <= 1'd1; rv322e4 <= 1'd1; end else begin qv2645c <= rte375e; rv322e4 <= ukb6a86; end\r
-end\r
-\r
-\r
-always @(posedge lqdf35e or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qi878e0 <= 1'b0; an3c700 <= 1'b0; ou10f1c <= 8'd0; lf1c027 <= 1'b0; aye013f <= 1'b0; fne3804 <= 8'd0; je4fc9 <= 1'b0; bn27e4b <= 1'b0; uk9f9 <= 8'd0; do3f25f <= 1'b0; end else begin ou10f1c <= ie9813c; an3c700 <= do4f0b; qi878e0 <= dmc09e1; fne3804 <= dmebd9f; aye013f <= dzf67dd; lf1c027 <= yx5ecfb;\r
- if (thf6d50) begin do3f25f <= 1'b0; end else if (((dzf67dd==1'd1) && (nefbbc4==1'd0)) || (fpb5430 ==1'd1)) do3f25f <= 1'b1; else do3f25f <= (~kqc4581); if (kqc4581) begin uk9f9[3:0] <= aab3eef[3:0]; bn27e4b <= nefbbc4; je4fc9 <= an9f778; if (fpb5430) begin uk9f9[7:4] <= aab3eef[7:4]; end else begin uk9f9[7:4] <= dmebd9f[3:0]; end end end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) ead4aa4 ( .Reset(qva4c8b), .RPReset(qva4c8b), .WrClock(lqdf35e), .WrEn(do3f25f), .Data({je4fc9, bn27e4b, uk9f9}),\r
- .RdClock(mrf2fbc), .RdEn(zkfbd26), .Q({hbf92fb, ipc97de, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) ead4aa4 ( .Reset(qva4c8b), .RPReset(qva4c8b), .WrClock(lqdf35e), .WrEn(do3f25f), .Data({je4fc9, bn27e4b, uk9f9}),\r
- .RdClock(mrf2fbc), .RdEn(zkfbd26), .Q({hbf92fb, ipc97de, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) ead4aa4 ( .Reset(qva4c8b), .RPReset(qva4c8b), .WrClock(lqdf35e), .WrEn(do3f25f), .Data({je4fc9, bn27e4b, uk9f9}),\r
- .RdClock(mrf2fbc), .RdEn(zkfbd26), .Q({hbf92fb, ipc97de, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-\r
-`endif\r
-\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin xl27f82 <= 1'b0; xy3fc17 <= 1'b0; fafe0ba <= 1'b0; uif05d3 <= 1'b0; co82e98 <= 1'b0; sj174c0 <= 1'b0; end else begin xl27f82 <= zzba604; xy3fc17 <= vk86d9b;\r
- fafe0ba <= oh36cda; uif05d3 <= oh36cda & (~gqb66d4); co82e98 <= ~oh36cda & (gqb66d4); sj174c0 <= ymb36a1 || ph9b509; end\r
-end\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin oub3c7c <= 2'd0; jr9e3e0 <= 2'd0; hof1f06 <= 2'd0; ir8f833 <= 2'd0; rg7c19c <= 2'd0; ice0ce2 <= 2'd0; fp6710 <= 1'b0; ux33887 <= 1'b0; do9c43c <= 1'b0; qte21e3 <= 1'b0; end else begin oub3c7c <= ald3027; jr9e3e0 <= fp2785b; hof1f06 <= kf3c2df; ir8f833 <= fae16fc; if ((kf3c2df==fae16fc) && (kf3c2df==jeb7e3)) rg7c19c <= jeb7e3; ice0ce2 <= en5bf1b; if (dmda84e) fp6710 <= 1'b1; else if (en5bf1b != xwdf8dd) fp6710 <= 1'b1; else fp6710 <= 1'b0; if (gqb66d4) begin ux33887 <= 1'b1; do9c43c <= 1'b0; qte21e3 <= 1'b0; end else begin ux33887 <= en5bf1b[1]; do9c43c <= !en5bf1b[1] & ( en5bf1b[0]); qte21e3 <= !en5bf1b[1] & (!en5bf1b[0]); end\r
- case (phaa186) 1'd0: begin if (vvfc6eb) begin uide932 <= 1'b1; lf91727 <= 1'd1; end else begin uide932 <= 1'b0; lf91727 <= 1'd0; end end 1'd1: begin uide932 <= 1'b1; if (nr50c36) begin lf91727 <= 1'd0; end else begin lf91727 <= 1'd1; end end default: begin lf91727 <= 1'd0; end endcase\r
- end\r
-end\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ww5c9fe <= 7'd0; hoe4ff0 <= 1'b0; end else begin if (vvfc6eb || zm30db3) begin ww5c9fe <= 7'd0; end else begin ww5c9fe <= je861b6 + 1; end\r
- if (vvfc6eb) begin hoe4ff0 <= 1'b0; end else if (xy1baf6) begin if (je861b6 == 7'd8) begin hoe4ff0 <= 1'b1; end else begin hoe4ff0 <= 1'b0; end end else if (vvdd7b3) begin if (je861b6 == 7'd98) begin hoe4ff0 <= 1'b1; end else begin hoe4ff0 <= 1'b0; end end else begin hoe4ff0 <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin zz8b93f <= 1'b0; end else begin if (vvfc6eb) begin zz8b93f <= 1'b0; end else if (xy1baf6) begin if (je861b6 == 7'd3) begin zz8b93f <= 1'b1; end else begin zz8b93f <= 1'b0; end end else if (vvdd7b3) begin if (je861b6 == 7'd49) begin zz8b93f <= 1'b1; end else begin zz8b93f <= 1'b0; end end else begin zz8b93f <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin zkfbd26 <= 1'b0; end else begin if (zk47db5) begin zkfbd26 <= 1'b0; end else if (!nt811f6 && nr50c36) begin zkfbd26 <= 1'b1; end else begin zkfbd26 <= 1'b0; end end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qi97de4 <= 8'd0; mtbef21 <= 1'd0; wjf790c <= 1'd0; end else begin qi97de4 <= vxb023e; mtbef21 <= fp22c08; wjf790c <= lf16047; end\r
-end\r
-\r
-always@* begin zzba604<=nrf6ece[0];ald3027<={zxf9af2>>1,nrf6ece[1]};ie9813c<={blcd797>>1,nrf6ece[2]};dmc09e1<=nrf6ece[3];do4f0b<=nrf6ece[4];fp2785b<={oub3c7c>>1,nrf6ece[5]};kf3c2df<={jr9e3e0>>1,nrf6ece[6]};fae16fc<={hof1f06>>1,nrf6ece[7]};jeb7e3<={ir8f833>>1,nrf6ece[8]};en5bf1b<={rg7c19c>>1,nrf6ece[9]};xwdf8dd<={ice0ce2>>1,nrf6ece[10]};vvfc6eb<=nrf6ece[11];rte375e<=nrf6ece[12];xy1baf6<=nrf6ece[13];vvdd7b3<=nrf6ece[14];dmebd9f<={ou10f1c>>1,nrf6ece[15]};yx5ecfb<=nrf6ece[16];dzf67dd<=nrf6ece[17];aab3eef<={fne3804>>1,nrf6ece[18]};an9f778<=nrf6ece[19];nefbbc4<=nrf6ece[20];fndde22<={uk9f9>>1,nrf6ece[21]};ayef116<=nrf6ece[22];ui788b0<=nrf6ece[23];kqc4581<=nrf6ece[24];fp22c08<=nrf6ece[25];lf16047<=nrf6ece[26];vxb023e<={sh4bef4>>1,nrf6ece[27]};nt811f6<=nrf6ece[28];cb8fb6<=nrf6ece[29];zk47db5<=nrf6ece[30];sw3edaa<=nrf6ece[31];thf6d50<=nrf6ece[32];ukb6a86<=nrf6ece[33];fpb5430<=nrf6ece[34];phaa186<=nrf6ece[35];nr50c36<=nrf6ece[36];je861b6<={ww5c9fe>>1,nrf6ece[37]};zm30db3<=nrf6ece[38];vk86d9b<=nrf6ece[39];oh36cda<=nrf6ece[40];gqb66d4<=nrf6ece[41];ymb36a1<=nrf6ece[42];ph9b509<=nrf6ece[43];dmda84e<=nrf6ece[44];end\r
-always@* begin bl7edd9[2047]<=zxf9af2[0];bl7edd9[2046]<=blcd797[0];bl7edd9[2044]<=pf6bcbe;bl7edd9[2040]<=qt5e5f7;bl7edd9[2032]<=oub3c7c[0];bl7edd9[2017]<=jr9e3e0[0];bl7edd9[1987]<=hof1f06[0];bl7edd9[1926]<=ir8f833[0];bl7edd9[1805]<=lf91727;bl7edd9[1804]<=rg7c19c[0];bl7edd9[1803]<=bn27e4b;bl7edd9[1761]<=qva4c8b;bl7edd9[1668]<=uif05d3;bl7edd9[1562]<=zz8b93f;bl7edd9[1560]<=ice0ce2[0];bl7edd9[1558]<=do3f25f;bl7edd9[1550]<=qi878e0;bl7edd9[1475]<=qv2645c;bl7edd9[1464]<=uide932;bl7edd9[1288]<=co82e98;bl7edd9[1076]<=ww5c9fe[0];bl7edd9[1072]<=fp6710;bl7edd9[1069]<=hbf92fb;bl7edd9[1052]<=an3c700;bl7edd9[1023]<=gbe_mode;bl7edd9[902]<=rv322e4;bl7edd9[901]<=je4fc9;bl7edd9[880]<=vif4991;bl7edd9[834]<=fafe0ba;bl7edd9[775]<=ou10f1c[0];bl7edd9[732]<=zkfbd26;bl7edd9[528]<=sj174c0;bl7edd9[450]<=uk9f9[0];bl7edd9[417]<=xy3fc17;bl7edd9[387]<=qte21e3;bl7edd9[366]<=vv5f7a4;bl7edd9[225]<=aye013f;bl7edd9[208]<=xl27f82;bl7edd9[193]<=do9c43c;bl7edd9[183]<=sh4bef4[0];bl7edd9[112]<=lf1c027;bl7edd9[104]<=hoe4ff0;bl7edd9[96]<=ux33887;bl7edd9[91]<=ipc97de;bl7edd9[56]<=fne3804[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module vx9b22c (rst_n,\r
- gbe_mode,\r
- lqdf35e,\r
-\r
- blcd797,\r
- pf6bcbe,\r
- qt5e5f7,\r
- hdaff1b,\r
- en7f8df,\r
-\r
- mrf2fbc,\r
- pfe37e6,\r
- qi97de4,\r
- mtbef21,\r
- wjf790c,\r
- xje6cdf,\r
- yz366ff\r
- );\r
-input rst_n;\r
-input gbe_mode;\r
-input lqdf35e;\r
-input [7:0] blcd797;\r
-input pf6bcbe;\r
-input qt5e5f7;\r
-input hdaff1b;\r
-input en7f8df;\r
-input mrf2fbc;\r
-input [1:0] pfe37e6;\r
-output [7:0] qi97de4;\r
-output mtbef21;\r
-output wjf790c;\r
-output xje6cdf;\r
-output yz366ff;\r
-reg [7:0] qi97de4;\r
-reg mtbef21;\r
-reg wjf790c;\r
-reg xje6cdf;\r
-reg yz366ff;\r
-reg [1:0] oub3c7c;\r
-reg [1:0] jr9e3e0;\r
-reg [1:0] hof1f06;\r
-reg [1:0] ir8f833;\r
-reg [1:0] rg7c19c;\r
-reg [1:0] ice0ce2;\r
-reg fp6710;\r
-reg ux33887;\r
-reg do9c43c;\r
-reg qte21e3;\r
-reg uide932;\r
-reg vif4991;\r
-reg ri89c38;\r
-reg zz8b93f;\r
-reg [6:0] ww5c9fe;\r
-reg hoe4ff0;\r
-reg ph38769;\r
-reg uvc3b4e;\r
-reg zkfbd26;\r
-reg [7:0] ou10f1c;\r
-reg an3c700;\r
-reg qi878e0;\r
-reg nr74954;\r
-reg epa4aa7;\r
-wire [7:0] sh4bef4;\r
-wire ipc97de;\r
-wire hbf92fb;\r
-wire zma78dc;\r
-wire oh3c6e3;\r
-reg [7:0] nre371c;\r
-reg ri1b8e6;\r
-reg yxdc733;\r
-reg dze399d;\r
-reg vx1ccef;\r
-reg lf91727;\r
-reg qv2645c;\r
-reg ym9dfb4;\r
-reg xl27f82;\r
-reg xy3fc17;\r
-reg fafe0ba;\r
-reg uif05d3;\r
-reg co82e98;\r
-reg sj174c0;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-`endif\r
-reg zzba604;\r
-reg [7 : 0] ie9813c;\r
-reg dmc09e1;\r
-reg do4f0b;\r
-reg uk3b4aa;\r
-reg lqda551;\r
-reg [1 : 0] zxd2a8a;\r
-reg [1 : 0] fp2785b;\r
-reg [1 : 0] kf3c2df;\r
-reg [1 : 0] fae16fc;\r
-reg [1 : 0] jeb7e3;\r
-reg [1 : 0] en5bf1b;\r
-reg [1 : 0] xwdf8dd;\r
-reg vvfc6eb;\r
-reg rte375e;\r
-reg xy1baf6;\r
-reg vvdd7b3;\r
-reg zk47db5;\r
-reg sw3edaa;\r
-reg rtdd291;\r
-reg nr50c36;\r
-reg [6 : 0] je861b6;\r
-reg zm30db3;\r
-reg zz91ffa;\r
-reg cb8ffd6;\r
-reg cb8fb6;\r
-reg [7 : 0] dmebd9f;\r
-reg dzf67dd;\r
-reg yx5ecfb;\r
-reg uxb4845;\r
-reg ira422d;\r
-reg [7 : 0] vxb023e;\r
-reg lf16047;\r
-reg fp22c08;\r
-reg zz2da6f;\r
-reg me6d37e;\r
-reg [7 : 0] rg69bf1;\r
-reg by4df8a;\r
-reg sh6fc53;\r
-reg pf7e29d;\r
-reg xwf14ef;\r
-reg phaa186;\r
-reg ukb6a86;\r
-reg wy9dea9;\r
-reg vk86d9b;\r
-reg oh36cda;\r
-reg gqb66d4;\r
-reg ymb36a1;\r
-reg ph9b509;\r
-reg dmda84e;\r
-reg [2047:0] bl7edd9;\r
-wire [49:0] nrf6ece;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-localparam zmb7676 = 50,wlbb3b3 = 32'hfdffe06b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-\r
-always @(posedge lqdf35e or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin xl27f82 <= 1'b0; xy3fc17 <= 1'b0; fafe0ba <= 1'b0; uif05d3 <= 1'b0; co82e98 <= 1'b0; sj174c0 <= 1'b0; end else begin xl27f82 <= zzba604; xy3fc17 <= vk86d9b;\r
- fafe0ba <= oh36cda; uif05d3 <= oh36cda & (~gqb66d4); co82e98 <= ~oh36cda & (gqb66d4); sj174c0 <= ymb36a1 || ph9b509; end\r
-end\r
-\r
-\r
-always @(posedge lqdf35e or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin oub3c7c <= 2'd0; jr9e3e0 <= 2'd0; hof1f06 <= 2'd0; ir8f833 <= 2'd0; rg7c19c <= 2'd0; ice0ce2 <= 2'd0; fp6710 <= 1'b1; ux33887 <= 1'b0; do9c43c <= 1'b0; qte21e3 <= 1'b0; end else begin oub3c7c <= zxd2a8a; jr9e3e0 <= fp2785b; hof1f06 <= kf3c2df; ir8f833 <= fae16fc; if ((kf3c2df==fae16fc) && (kf3c2df==jeb7e3)) rg7c19c <= jeb7e3; ice0ce2 <= en5bf1b; if (dmda84e) fp6710 <= 1'b1; else if (en5bf1b != xwdf8dd) fp6710 <= 1'b1; else fp6710 <= 1'b0; if (gqb66d4) begin ux33887 <= 1'b1; do9c43c <= 1'b0; qte21e3 <= 1'b0; end else begin ux33887 <= en5bf1b[1]; do9c43c <= !en5bf1b[1] & ( en5bf1b[0]); qte21e3 <= !en5bf1b[1] & (!en5bf1b[0]); end case (phaa186) 1'd0: begin if (vvfc6eb) begin uide932 <= 1'b1; lf91727 <= 1'd1; end else begin uide932 <= 1'b0; lf91727 <= 1'd0; end end 1'd1: begin uide932 <= 1'b1; if (nr50c36) begin lf91727 <= 1'd0; end else begin lf91727 <= 1'd1; end end default: begin lf91727 <= 1'd0; end endcase end\r
-end\r
-\r
-\r
-always @(posedge lqdf35e or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ww5c9fe <= 7'd0; hoe4ff0 <= 1'b0; end else begin if (vvfc6eb || zm30db3) begin ww5c9fe <= 7'd0; end else begin ww5c9fe <= je861b6 + 1; end\r
- if (vvfc6eb) begin hoe4ff0 <= 1'b0; end else if (xy1baf6) begin if (je861b6 == 7'd8) begin hoe4ff0 <= 1'b1; end else begin hoe4ff0 <= 1'b0; end end else if (vvdd7b3) begin if (je861b6 == 7'd98) begin hoe4ff0 <= 1'b1; end else begin hoe4ff0 <= 1'b0; end end else begin hoe4ff0 <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-always @(posedge lqdf35e or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin zz8b93f <= 1'b0; end else begin if (vvfc6eb) begin zz8b93f <= 1'b0; end else if (xy1baf6) begin if (je861b6 == 7'd3) begin zz8b93f <= 1'b1; end else begin zz8b93f <= 1'b0; end end else if (vvdd7b3) begin if (je861b6 == 7'd49) begin zz8b93f <= 1'b1; end else begin zz8b93f <= 1'b0; end end else begin zz8b93f <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-always @(posedge lqdf35e or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qi878e0 <= 0; an3c700 <= 0; nr74954 <= 0; epa4aa7 <= 0; ou10f1c <= 8'd0; end else begin ou10f1c <= ie9813c; an3c700 <= do4f0b; qi878e0 <= dmc09e1; nr74954 <= uk3b4aa; epa4aa7 <= lqda551; end\r
-end\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(12), .pmi_data_width_r(12), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) vx9e54 ( .Reset(ri89c38), .RPReset(ri89c38), .WrClock(lqdf35e), .WrEn(zz8b93f), .Data({epa4aa7, nr74954, qi878e0, an3c700, ou10f1c}),\r
- .RdClock(mrf2fbc), .RdEn(zkfbd26), .Q({oh3c6e3, zma78dc, hbf92fb, ipc97de, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(12), .pmi_data_width_r(12), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) vx9e54 ( .Reset(ri89c38), .RPReset(ri89c38), .WrClock(lqdf35e), .WrEn(zz8b93f), .Data({epa4aa7, nr74954, qi878e0, an3c700, ou10f1c}),\r
- .RdClock(mrf2fbc), .RdEn(zkfbd26), .Q({oh3c6e3, zma78dc, hbf92fb, ipc97de, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(12), .pmi_data_width_r(12), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) vx9e54 ( .Reset(ri89c38), .RPReset(ri89c38), .WrClock(lqdf35e), .WrEn(zz8b93f), .Data({epa4aa7, nr74954, qi878e0, an3c700, ou10f1c}),\r
- .RdClock(mrf2fbc), .RdEn(zkfbd26), .Q({oh3c6e3, zma78dc, hbf92fb, ipc97de, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-\r
-`endif\r
-\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vif4991 <= 1'd1; ri89c38 <= 1'd1; end else begin vif4991 <= zk47db5; ri89c38 <= sw3edaa; end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qv2645c <= 1'd1; ym9dfb4 <= 1'd1; end else begin qv2645c <= rte375e; ym9dfb4 <= ukb6a86; end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ph38769 <= 1'b0; uvc3b4e <= 1'b0; end else begin if (rtdd291) begin ph38769 <= 1'b0; end else begin if (wy9dea9) begin ph38769 <= 1'b1; end else begin ph38769 <= ~zz91ffa; end end\r
- uvc3b4e <= zz91ffa;\r
- end\r
-end\r
-\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin zkfbd26 <= 1'b0; end else begin if (rtdd291) begin zkfbd26 <= 1'b0; end else begin if (!vv5f7a4 && zz91ffa) begin zkfbd26 <= 1'b1; end else begin zkfbd26 <= 1'b0; end end end\r
-end\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin yxdc733 <= 0; ri1b8e6 <= 0; dze399d <= 0; vx1ccef <= 0; nre371c <= 8'd0; end else begin if (zz91ffa) begin ri1b8e6 <= lf16047; dze399d <= zz2da6f; vx1ccef <= me6d37e; if ((!wy9dea9) && fp22c08 && (vxb023e == 8'h0F) && (!lf16047) && by4df8a) begin yxdc733 <= 1'b0; nre371c <= 8'h00; end else begin yxdc733 <= fp22c08; nre371c <= vxb023e; end end\r
- end\r
-end\r
-\r
-\r
-\r
-always @(posedge mrf2fbc or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin mtbef21 <= 0; wjf790c <= 0; xje6cdf <= 0; yz366ff <= 0; qi97de4 <= 8'd0; end else begin if (cb8ffd6) begin qi97de4[3:0] <= rg69bf1[3:0]; end else begin qi97de4[3:0] <= rg69bf1[7:4]; end qi97de4[7:4] <= rg69bf1[7:4]; wjf790c <= by4df8a; mtbef21 <= sh6fc53; xje6cdf <= pf7e29d; yz366ff <= xwf14ef; end\r
-end\r
-\r
-\r
-\r
-always@* begin zzba604<=nrf6ece[0];ie9813c<={blcd797>>1,nrf6ece[1]};dmc09e1<=nrf6ece[2];do4f0b<=nrf6ece[3];uk3b4aa<=nrf6ece[4];lqda551<=nrf6ece[5];zxd2a8a<={pfe37e6>>1,nrf6ece[6]};fp2785b<={oub3c7c>>1,nrf6ece[7]};kf3c2df<={jr9e3e0>>1,nrf6ece[8]};fae16fc<={hof1f06>>1,nrf6ece[9]};jeb7e3<={ir8f833>>1,nrf6ece[10]};en5bf1b<={rg7c19c>>1,nrf6ece[11]};xwdf8dd<={ice0ce2>>1,nrf6ece[12]};vvfc6eb<=nrf6ece[13];rte375e<=nrf6ece[14];xy1baf6<=nrf6ece[15];vvdd7b3<=nrf6ece[16];zk47db5<=nrf6ece[17];sw3edaa<=nrf6ece[18];rtdd291<=nrf6ece[19];nr50c36<=nrf6ece[20];je861b6<={ww5c9fe>>1,nrf6ece[21]};zm30db3<=nrf6ece[22];zz91ffa<=nrf6ece[23];cb8ffd6<=nrf6ece[24];cb8fb6<=nrf6ece[25];dmebd9f<={ou10f1c>>1,nrf6ece[26]};dzf67dd<=nrf6ece[27];yx5ecfb<=nrf6ece[28];uxb4845<=nrf6ece[29];ira422d<=nrf6ece[30];vxb023e<={sh4bef4>>1,nrf6ece[31]};lf16047<=nrf6ece[32];fp22c08<=nrf6ece[33];zz2da6f<=nrf6ece[34];me6d37e<=nrf6ece[35];rg69bf1<={nre371c>>1,nrf6ece[36]};by4df8a<=nrf6ece[37];sh6fc53<=nrf6ece[38];pf7e29d<=nrf6ece[39];xwf14ef<=nrf6ece[40];phaa186<=nrf6ece[41];ukb6a86<=nrf6ece[42];wy9dea9<=nrf6ece[43];vk86d9b<=nrf6ece[44];oh36cda<=nrf6ece[45];gqb66d4<=nrf6ece[46];ymb36a1<=nrf6ece[47];ph9b509<=nrf6ece[48];dmda84e<=nrf6ece[49];end\r
-always@* begin bl7edd9[2047]<=blcd797[0];bl7edd9[2046]<=pf6bcbe;bl7edd9[2044]<=qt5e5f7;bl7edd9[2041]<=hdaff1b;bl7edd9[2034]<=en7f8df;bl7edd9[2021]<=pfe37e6[0];bl7edd9[2017]<=ww5c9fe[0];bl7edd9[1995]<=oub3c7c[0];bl7edd9[1986]<=hoe4ff0;bl7edd9[1943]<=jr9e3e0[0];bl7edd9[1925]<=ph38769;bl7edd9[1908]<=hbf92fb;bl7edd9[1864]<=ri1b8e6;bl7edd9[1855]<=qte21e3;bl7edd9[1838]<=hof1f06[0];bl7edd9[1803]<=uvc3b4e;bl7edd9[1769]<=zma78dc;bl7edd9[1680]<=yxdc733;bl7edd9[1662]<=uide932;bl7edd9[1628]<=ir8f833[0];bl7edd9[1559]<=zkfbd26;bl7edd9[1501]<=sh4bef4[0];bl7edd9[1490]<=oh3c6e3;bl7edd9[1487]<=ux33887;bl7edd9[1312]<=dze399d;bl7edd9[1276]<=vif4991;bl7edd9[1209]<=rg7c19c[0];bl7edd9[1155]<=lf91727;bl7edd9[1070]<=ou10f1c[0];bl7edd9[1048]<=xl27f82;bl7edd9[1023]<=gbe_mode;bl7edd9[1008]<=zz8b93f;bl7edd9[954]<=ipc97de;bl7edd9[932]<=nre371c[0];bl7edd9[927]<=do9c43c;bl7edd9[791]<=sj174c0;bl7edd9[750]<=epa4aa7;bl7edd9[743]<=fp6710;bl7edd9[577]<=vx1ccef;bl7edd9[524]<=ym9dfb4;bl7edd9[504]<=ri89c38;bl7edd9[395]<=co82e98;bl7edd9[375]<=nr74954;bl7edd9[371]<=ice0ce2[0];bl7edd9[262]<=qv2645c;bl7edd9[197]<=uif05d3;bl7edd9[187]<=qi878e0;bl7edd9[98]<=fafe0ba;bl7edd9[93]<=an3c700;bl7edd9[49]<=xy3fc17;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module hq25f53 (rst_n,\r
- gbe_mode,\r
- eaea698,\r
- ay534c0,\r
- zz8b93f,\r
-\r
- blcd797,\r
- pf6bcbe,\r
- qt5e5f7,\r
-\r
- aa90a,\r
- qi97de4,\r
- mtbef21,\r
- wjf790c\r
- );\r
-input rst_n;\r
-input gbe_mode;\r
-input eaea698;\r
-input ay534c0;\r
-output zz8b93f;\r
-input [7:0] blcd797;\r
-input pf6bcbe;\r
-input qt5e5f7;\r
-input [1:0] aa90a;\r
-output [7:0] qi97de4;\r
-output mtbef21;\r
-output wjf790c;\r
-reg [7:0] qi97de4;\r
-reg mtbef21;\r
-reg wjf790c;\r
-reg [1:0] oub3c7c;\r
-reg [1:0] jr9e3e0;\r
-reg [1:0] hof1f06;\r
-reg [1:0] ir8f833;\r
-reg [1:0] rg7c19c;\r
-reg [1:0] ice0ce2;\r
-reg fp6710;\r
-reg ux33887;\r
-reg do9c43c;\r
-reg qte21e3;\r
-reg zz8b93f;\r
-reg [6:0] ww5c9fe;\r
-reg hoe4ff0;\r
-reg ph38769;\r
-reg zkfbd26;\r
-reg [7:0] ou10f1c;\r
-reg an3c700;\r
-reg qi878e0;\r
-reg xl27f82;\r
-reg xy3fc17;\r
-reg fafe0ba;\r
-reg uif05d3;\r
-reg co82e98;\r
-reg sj174c0;\r
-reg zzba604;\r
-reg pfcdf9a;\r
-reg [7 : 0] ie9813c;\r
-reg dmc09e1;\r
-reg do4f0b;\r
-reg [1 : 0] kf9af7f;\r
-reg [1 : 0] fp2785b;\r
-reg [1 : 0] kf3c2df;\r
-reg [1 : 0] fae16fc;\r
-reg [1 : 0] jeb7e3;\r
-reg [1 : 0] en5bf1b;\r
-reg [1 : 0] xwdf8dd;\r
-reg vvfc6eb;\r
-reg rte375e;\r
-reg xy1baf6;\r
-reg vvdd7b3;\r
-reg [6 : 0] je861b6;\r
-reg zm30db3;\r
-reg zz91ffa;\r
-reg cb8fb6;\r
-reg [7 : 0] dmebd9f;\r
-reg dzf67dd;\r
-reg yx5ecfb;\r
-reg vk86d9b;\r
-reg oh36cda;\r
-reg gqb66d4;\r
-reg ymb36a1;\r
-reg ph9b509;\r
-reg dmda84e;\r
-reg [2047:0] bl7edd9;\r
-wire [28:0] nrf6ece;\r
-\r
-localparam zmb7676 = 29,wlbb3b3 = 32'hfdffca8b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin xl27f82 <= 1'b0; xy3fc17 <= 1'b0; fafe0ba <= 1'b0; uif05d3 <= 1'b0; co82e98 <= 1'b0; sj174c0 <= 1'b0; end else begin xl27f82 <= zzba604; xy3fc17 <= vk86d9b;\r
- fafe0ba <= oh36cda; uif05d3 <= oh36cda & (~gqb66d4); co82e98 <= ~oh36cda & (gqb66d4); sj174c0 <= ymb36a1 || ph9b509; end\r
-end\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin oub3c7c <= 2'd0; jr9e3e0 <= 2'd0; hof1f06 <= 2'd0; ir8f833 <= 2'd0; rg7c19c <= 2'd0; ice0ce2 <= 2'd0; fp6710 <= 1'b1; ux33887 <= 1'b0; do9c43c <= 1'b0; qte21e3 <= 1'b0; end else begin oub3c7c <= kf9af7f; jr9e3e0 <= fp2785b; hof1f06 <= kf3c2df; ir8f833 <= fae16fc; if ((kf3c2df==fae16fc) && (kf3c2df==jeb7e3)) rg7c19c <= jeb7e3; ice0ce2 <= en5bf1b; if (dmda84e) fp6710 <= 1'b1; else if (en5bf1b != xwdf8dd) fp6710 <= 1'b1; else fp6710 <= 1'b0; if (gqb66d4) begin ux33887 <= 1'b1; do9c43c <= 1'b0; qte21e3 <= 1'b0; end else begin ux33887 <= en5bf1b[1]; do9c43c <= !en5bf1b[1] & ( en5bf1b[0]); qte21e3 <= !en5bf1b[1] & (!en5bf1b[0]); end end\r
-end\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ww5c9fe <= 7'd0; hoe4ff0 <= 1'b0; end else begin if (vvfc6eb || zm30db3) begin ww5c9fe <= 7'd0; end else begin ww5c9fe <= je861b6 + 1; end\r
- if (vvfc6eb) begin hoe4ff0 <= 1'b0; end else if (xy1baf6) begin if (je861b6 == 7'd8) begin hoe4ff0 <= 1'b1; end else begin hoe4ff0 <= 1'b0; end end else if (vvdd7b3) begin if (je861b6 == 7'd98) begin hoe4ff0 <= 1'b1; end else begin hoe4ff0 <= 1'b0; end end else begin hoe4ff0 <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin zz8b93f <= 1'b0; end else begin if (vvfc6eb) begin zz8b93f <= 1'b0; end else if (xy1baf6) begin if (je861b6 == 7'd3) begin zz8b93f <= 1'b1; end else begin zz8b93f <= 1'b0; end end else if (vvdd7b3) begin if (je861b6 == 7'd49) begin zz8b93f <= 1'b1; end else begin zz8b93f <= 1'b0; end end else begin zz8b93f <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qi878e0 <= 0; an3c700 <= 0; ou10f1c <= 8'd0; end else begin if (pfcdf9a) begin ou10f1c <= ie9813c; an3c700 <= do4f0b; qi878e0 <= dmc09e1; end end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin mtbef21 <= 0; wjf790c <= 0; qi97de4 <= 8'd0; end else begin if (pfcdf9a) begin wjf790c <= dzf67dd; mtbef21 <= yx5ecfb; qi97de4 <= dmebd9f; end end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-always@* begin zzba604<=nrf6ece[0];pfcdf9a<=nrf6ece[1];ie9813c<={blcd797>>1,nrf6ece[2]};dmc09e1<=nrf6ece[3];do4f0b<=nrf6ece[4];kf9af7f<={aa90a>>1,nrf6ece[5]};fp2785b<={oub3c7c>>1,nrf6ece[6]};kf3c2df<={jr9e3e0>>1,nrf6ece[7]};fae16fc<={hof1f06>>1,nrf6ece[8]};jeb7e3<={ir8f833>>1,nrf6ece[9]};en5bf1b<={rg7c19c>>1,nrf6ece[10]};xwdf8dd<={ice0ce2>>1,nrf6ece[11]};vvfc6eb<=nrf6ece[12];rte375e<=nrf6ece[13];xy1baf6<=nrf6ece[14];vvdd7b3<=nrf6ece[15];je861b6<={ww5c9fe>>1,nrf6ece[16]};zm30db3<=nrf6ece[17];zz91ffa<=nrf6ece[18];cb8fb6<=nrf6ece[19];dmebd9f<={ou10f1c>>1,nrf6ece[20]};dzf67dd<=nrf6ece[21];yx5ecfb<=nrf6ece[22];vk86d9b<=nrf6ece[23];oh36cda<=nrf6ece[24];gqb66d4<=nrf6ece[25];ymb36a1<=nrf6ece[26];ph9b509<=nrf6ece[27];dmda84e<=nrf6ece[28];end\r
-always@* begin bl7edd9[2047]<=ay534c0;bl7edd9[2046]<=blcd797[0];bl7edd9[2044]<=pf6bcbe;bl7edd9[2040]<=qt5e5f7;bl7edd9[2032]<=aa90a[0];bl7edd9[2017]<=oub3c7c[0];bl7edd9[1987]<=jr9e3e0[0];bl7edd9[1926]<=hof1f06[0];bl7edd9[1804]<=ir8f833[0];bl7edd9[1803]<=xl27f82;bl7edd9[1560]<=rg7c19c[0];bl7edd9[1558]<=xy3fc17;bl7edd9[1550]<=ww5c9fe[0];bl7edd9[1072]<=ice0ce2[0];bl7edd9[1069]<=fafe0ba;bl7edd9[1052]<=hoe4ff0;bl7edd9[1023]<=gbe_mode;bl7edd9[901]<=qi878e0;bl7edd9[775]<=qte21e3;bl7edd9[450]<=an3c700;bl7edd9[387]<=do9c43c;bl7edd9[366]<=sj174c0;bl7edd9[225]<=ou10f1c[0];bl7edd9[193]<=ux33887;bl7edd9[183]<=co82e98;bl7edd9[112]<=zkfbd26;bl7edd9[96]<=fp6710;bl7edd9[91]<=uif05d3;bl7edd9[56]<=ph38769;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module yx5b9d8 (rst_n,\r
- gbe_mode,\r
- eaea698,\r
- ay534c0,\r
- zz8b93f,\r
-\r
- blcd797,\r
- pf6bcbe,\r
- qt5e5f7,\r
- hdaff1b,\r
- en7f8df,\r
-\r
- aa90a,\r
- qi97de4,\r
- mtbef21,\r
- wjf790c,\r
- xje6cdf,\r
- yz366ff\r
- );\r
-input rst_n;\r
-input gbe_mode;\r
-input eaea698;\r
-input ay534c0;\r
-output zz8b93f;\r
-input [7:0] blcd797;\r
-input pf6bcbe;\r
-input qt5e5f7;\r
-input hdaff1b;\r
-input en7f8df;\r
-input [1:0] aa90a;\r
-output [7:0] qi97de4;\r
-output mtbef21;\r
-output wjf790c;\r
-output xje6cdf;\r
-output yz366ff;\r
-reg [7:0] qi97de4;\r
-reg mtbef21;\r
-reg wjf790c;\r
-reg xje6cdf;\r
-reg yz366ff;\r
-reg [1:0] oub3c7c;\r
-reg [1:0] jr9e3e0;\r
-reg [1:0] hof1f06;\r
-reg [1:0] ir8f833;\r
-reg [1:0] rg7c19c;\r
-reg [1:0] ice0ce2;\r
-reg fp6710;\r
-reg ux33887;\r
-reg do9c43c;\r
-reg qte21e3;\r
-reg zz8b93f;\r
-reg [6:0] ww5c9fe;\r
-reg hoe4ff0;\r
-reg ph38769;\r
-reg zkfbd26;\r
-reg [7:0] ou10f1c;\r
-reg an3c700;\r
-reg qi878e0;\r
-reg nr74954;\r
-reg epa4aa7;\r
-reg xl27f82;\r
-reg xy3fc17;\r
-reg fafe0ba;\r
-reg uif05d3;\r
-reg co82e98;\r
-reg sj174c0;\r
-reg zzba604;\r
-reg pfcdf9a;\r
-reg [7 : 0] ie9813c;\r
-reg dmc09e1;\r
-reg do4f0b;\r
-reg uk3b4aa;\r
-reg lqda551;\r
-reg [1 : 0] kf9af7f;\r
-reg [1 : 0] fp2785b;\r
-reg [1 : 0] kf3c2df;\r
-reg [1 : 0] fae16fc;\r
-reg [1 : 0] jeb7e3;\r
-reg [1 : 0] en5bf1b;\r
-reg [1 : 0] xwdf8dd;\r
-reg vvfc6eb;\r
-reg rte375e;\r
-reg xy1baf6;\r
-reg vvdd7b3;\r
-reg [6 : 0] je861b6;\r
-reg zm30db3;\r
-reg zz91ffa;\r
-reg cb8fb6;\r
-reg [7 : 0] dmebd9f;\r
-reg dzf67dd;\r
-reg yx5ecfb;\r
-reg uxb4845;\r
-reg ira422d;\r
-reg vk86d9b;\r
-reg oh36cda;\r
-reg gqb66d4;\r
-reg ymb36a1;\r
-reg ph9b509;\r
-reg dmda84e;\r
-reg [2047:0] bl7edd9;\r
-wire [32:0] nrf6ece;\r
-\r
-localparam zmb7676 = 33,wlbb3b3 = 32'hfdffd42b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin xl27f82 <= 1'b0; xy3fc17 <= 1'b0; fafe0ba <= 1'b0; uif05d3 <= 1'b0; co82e98 <= 1'b0; sj174c0 <= 1'b0; end else begin xl27f82 <= zzba604; xy3fc17 <= vk86d9b;\r
- fafe0ba <= oh36cda; uif05d3 <= oh36cda & (~gqb66d4); co82e98 <= ~oh36cda & (gqb66d4); sj174c0 <= ymb36a1 || ph9b509; end\r
-end\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin oub3c7c <= 2'd0; jr9e3e0 <= 2'd0; hof1f06 <= 2'd0; ir8f833 <= 2'd0; rg7c19c <= 2'd0; ice0ce2 <= 2'd0; fp6710 <= 1'b1; ux33887 <= 1'b0; do9c43c <= 1'b0; qte21e3 <= 1'b0; end else begin oub3c7c <= kf9af7f; jr9e3e0 <= fp2785b; hof1f06 <= kf3c2df; ir8f833 <= fae16fc; if ((kf3c2df==fae16fc) && (kf3c2df==jeb7e3)) rg7c19c <= jeb7e3; ice0ce2 <= en5bf1b; if (dmda84e) fp6710 <= 1'b1; else if (en5bf1b != xwdf8dd) fp6710 <= 1'b1; else fp6710 <= 1'b0; if (gqb66d4) begin ux33887 <= 1'b1; do9c43c <= 1'b0; qte21e3 <= 1'b0; end else begin ux33887 <= en5bf1b[1]; do9c43c <= !en5bf1b[1] & ( en5bf1b[0]); qte21e3 <= !en5bf1b[1] & (!en5bf1b[0]); end end\r
-end\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ww5c9fe <= 7'd0; hoe4ff0 <= 1'b0; end else begin if (vvfc6eb || zm30db3) begin ww5c9fe <= 7'd0; end else begin ww5c9fe <= je861b6 + 1; end\r
- if (vvfc6eb) begin hoe4ff0 <= 1'b0; end else if (xy1baf6) begin if (je861b6 == 7'd8) begin hoe4ff0 <= 1'b1; end else begin hoe4ff0 <= 1'b0; end end else if (vvdd7b3) begin if (je861b6 == 7'd98) begin hoe4ff0 <= 1'b1; end else begin hoe4ff0 <= 1'b0; end end else begin hoe4ff0 <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin zz8b93f <= 1'b0; end else begin if (vvfc6eb) begin zz8b93f <= 1'b0; end else if (xy1baf6) begin if (je861b6 == 7'd3) begin zz8b93f <= 1'b1; end else begin zz8b93f <= 1'b0; end end else if (vvdd7b3) begin if (je861b6 == 7'd49) begin zz8b93f <= 1'b1; end else begin zz8b93f <= 1'b0; end end else begin zz8b93f <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qi878e0 <= 0; an3c700 <= 0; nr74954 <= 0; epa4aa7 <= 0; ou10f1c <= 8'd0; end else begin if (pfcdf9a) begin ou10f1c <= ie9813c; an3c700 <= do4f0b; qi878e0 <= dmc09e1; nr74954 <= uk3b4aa; epa4aa7 <= lqda551; end end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin mtbef21 <= 0; wjf790c <= 0; xje6cdf <= 0; yz366ff <= 0; qi97de4 <= 8'd0; end else begin if (pfcdf9a) begin wjf790c <= dzf67dd; xje6cdf <= uxb4845; yz366ff <= ira422d; if ((!rte375e) && yx5ecfb && (dmebd9f == 8'h0F) && (!dzf67dd) && wjf790c) begin mtbef21 <= 1'b0; qi97de4 <= 8'h00; end else begin mtbef21 <= yx5ecfb; qi97de4 <= dmebd9f; end end\r
- end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-always@* begin zzba604<=nrf6ece[0];pfcdf9a<=nrf6ece[1];ie9813c<={blcd797>>1,nrf6ece[2]};dmc09e1<=nrf6ece[3];do4f0b<=nrf6ece[4];uk3b4aa<=nrf6ece[5];lqda551<=nrf6ece[6];kf9af7f<={aa90a>>1,nrf6ece[7]};fp2785b<={oub3c7c>>1,nrf6ece[8]};kf3c2df<={jr9e3e0>>1,nrf6ece[9]};fae16fc<={hof1f06>>1,nrf6ece[10]};jeb7e3<={ir8f833>>1,nrf6ece[11]};en5bf1b<={rg7c19c>>1,nrf6ece[12]};xwdf8dd<={ice0ce2>>1,nrf6ece[13]};vvfc6eb<=nrf6ece[14];rte375e<=nrf6ece[15];xy1baf6<=nrf6ece[16];vvdd7b3<=nrf6ece[17];je861b6<={ww5c9fe>>1,nrf6ece[18]};zm30db3<=nrf6ece[19];zz91ffa<=nrf6ece[20];cb8fb6<=nrf6ece[21];dmebd9f<={ou10f1c>>1,nrf6ece[22]};dzf67dd<=nrf6ece[23];yx5ecfb<=nrf6ece[24];uxb4845<=nrf6ece[25];ira422d<=nrf6ece[26];vk86d9b<=nrf6ece[27];oh36cda<=nrf6ece[28];gqb66d4<=nrf6ece[29];ymb36a1<=nrf6ece[30];ph9b509<=nrf6ece[31];dmda84e<=nrf6ece[32];end\r
-always@* begin bl7edd9[2047]<=ay534c0;bl7edd9[2046]<=blcd797[0];bl7edd9[2044]<=pf6bcbe;bl7edd9[2041]<=qt5e5f7;bl7edd9[2035]<=hdaff1b;bl7edd9[2022]<=en7f8df;bl7edd9[1996]<=aa90a[0];bl7edd9[1945]<=oub3c7c[0];bl7edd9[1922]<=nr74954;bl7edd9[1842]<=jr9e3e0[0];bl7edd9[1797]<=epa4aa7;bl7edd9[1776]<=ou10f1c[0];bl7edd9[1637]<=hof1f06[0];bl7edd9[1622]<=fp6710;bl7edd9[1546]<=xl27f82;bl7edd9[1504]<=an3c700;bl7edd9[1468]<=ph38769;bl7edd9[1391]<=ww5c9fe[0];bl7edd9[1226]<=ir8f833[0];bl7edd9[1197]<=ux33887;bl7edd9[1044]<=xy3fc17;bl7edd9[1023]<=gbe_mode;bl7edd9[961]<=qi878e0;bl7edd9[888]<=zkfbd26;bl7edd9[811]<=ice0ce2[0];bl7edd9[734]<=hoe4ff0;bl7edd9[695]<=qte21e3;bl7edd9[405]<=rg7c19c[0];bl7edd9[347]<=do9c43c;bl7edd9[328]<=sj174c0;bl7edd9[164]<=co82e98;bl7edd9[82]<=uif05d3;bl7edd9[41]<=fafe0ba;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module hq11045 ( eaea698,\r
- rst_n,\r
-\r
- gbe_mode,\r
- sgmii_mode,\r
-\r
- mr_main_reset,\r
- mr_restart_an,\r
- mr_an_enable,\r
- mr_adv_ability,\r
- mr_lp_adv_ability,\r
- ip70450, \r
- mr_page_rx,\r
- mr_an_complete,\r
- \r
- sj8a10b,\r
- \r
- zx5085d,\r
- db842ee,\r
- ym21776,\r
- \r
- fcbbb1,\r
- tu5dd8a,\r
- jceec52,\r
- tu76293\r
- );\r
-input eaea698;\r
-input rst_n;\r
-input gbe_mode;\r
-input sgmii_mode;\r
-input mr_main_reset;\r
-input mr_restart_an;\r
-input mr_an_enable;\r
-input [16:1] mr_adv_ability;\r
-output [16:1] mr_lp_adv_ability;\r
-input ip70450;\r
-output mr_page_rx;\r
-output mr_an_complete;\r
-input sj8a10b;\r
-input zx5085d;\r
-input db842ee;\r
-input ym21776;\r
-input [15:0] fcbbb1;\r
-output [15:0] tu5dd8a;\r
-output [1:0] jceec52;\r
-output tu76293;\r
-reg [16:1] mr_lp_adv_ability;\r
-reg mr_page_rx;\r
-reg mr_an_complete;\r
-reg [15:0] tu5dd8a;\r
-reg [1:0] jceec52;\r
-reg [15:0] qi82738;\r
-reg [15:0] fp139c1;\r
-reg [15:0] ba9ce0f;\r
-reg [15:0] wje707a;\r
-reg [15:0] nt383d4;\r
-reg cmc1ea6;\r
-localparam ukf531 = 2'b00, of7a989 = 2'b01, kqd4c4c = 2'b10;\r
-localparam ksa6260 = 4'b0000, sw31300 = 4'b0001, ng89800 = 4'b0010, ic4c003 = 4'b0011, sh60018 = 4'b0100, iec5 = 4'b0101, mg628 = 4'b0111, vx3140 = 4'b1000;\r
-parameter sj18a07 = 21'h1cf2bf, byc503c = 21'h0ced2f, LINK_TIMER_SH = 21'h1fff01;\r
-reg ld40f17;\r
-reg qv78bf;\r
-reg an3c5fc;\r
-reg ene2fe4;\r
-reg cb17f25;\r
-reg [20:0] fpbf92d;\r
-reg thfc96e;\r
-reg [20:0] dme4b77;\r
-reg pu25bba;\r
-reg [3:0] jr2ddd2, rt6ee96, ea774b7;\r
-wire [15:0] fcbbb1;\r
-reg [15:0] thd2dcf;\r
-reg [15:0] je96e7f;\r
-reg [15:0] hqb73fb;\r
-reg [ 1:0] gqb9fdb;\r
-reg [ 1:0] dmcfed9;\r
-reg [ 1:0] en7f6ca;\r
-wire ym21776;\r
-reg godb2ab;\r
-wire db842ee;\r
-reg tucaac5;\r
-reg dz5562a;\r
-reg mtab157;\r
-reg ne58abc;\r
-reg nec55e2;\r
-reg ba2af12;\r
-reg ho57893;\r
-reg qibc49b;\r
-reg cze24d8;\r
-reg ir126c4;\r
-reg vk93624;\r
-reg xl9b122;\r
-reg [16:1] rtd8916;\r
-reg suc48b6;\r
-reg sw245b1;\r
-reg lf22d89;\r
-reg hd16c4f;\r
-reg qib627f;\r
-reg[15:0] cbb13f9;\r
-reg pu89fcc;\r
-reg bl4fe63;\r
-reg of7f31e;\r
-reg rtf98f5;\r
-reg [16:1] ofcc7af;\r
-reg ne63d7c;\r
-reg vk1ebe3;\r
-reg cmf5f1b;\r
-reg vxaf8d9;\r
-reg lq7c6cf;\r
-reg[15:0] pfe367a;\r
-reg hq1b3d6;\r
-reg shd9eb2;\r
-wire bycf594 ;\r
-reg [(22*8):1] sh7aca3;\r
-reg zzba604;\r
-reg xyb28e4;\r
-reg db94722;\r
-reg ksa3917;\r
-reg zz1c8b9;\r
-reg [16 : 1] fae45ce;\r
-reg lf22e73;\r
-reg gd1739f;\r
-reg ecb9cfc;\r
-reg mece7e1;\r
-reg by73f09;\r
-reg [15 : 0] ir9f84a;\r
-reg [15 : 0] fnfc255;\r
-reg [15 : 0] rge12ae;\r
-reg [15 : 0] db9573;\r
-reg [15 : 0] fn4ab9e;\r
-reg vv55cf6;\r
-reg wlae7b6;\r
-reg ps73db4;\r
-reg rv9eda2;\r
-reg zxf6d17;\r
-reg qib68be;\r
-reg [20 : 0] yzb45f0;\r
-reg jea2f84;\r
-reg [20 : 0] qv17c23;\r
-reg mtbe11d;\r
-reg [3 : 0] ykf08ed;\r
-reg [3 : 0] ph84769;\r
-reg [3 : 0] sj23b4e;\r
-reg [15 : 0] kf1da75;\r
-reg [15 : 0] qted3ac;\r
-reg [15 : 0] xw69d65;\r
-reg [1 : 0] yx4eb2a;\r
-reg [1 : 0] qt75954;\r
-reg [1 : 0] aaacaa5;\r
-reg wj65528;\r
-reg pu2a945;\r
-reg qt54a2b;\r
-reg jra515c;\r
-reg rv28ae7;\r
-reg dz4573e;\r
-reg ym2b9f6;\r
-reg ic5cfb1;\r
-reg ale7d88;\r
-reg uk3ec45;\r
-reg jpf6228;\r
-reg yzb1147;\r
-reg ie88a3c;\r
-reg [16 : 1] xj451e1;\r
-reg fp28f0e;\r
-reg jc47876;\r
-reg wl3c3b2;\r
-reg xwe1d94;\r
-reg tweca2;\r
-reg [15 : 0] by76512;\r
-reg lsb2893;\r
-reg lf9449a;\r
-reg xya24d7;\r
-reg ux126ba;\r
-reg [16 : 1] ng935d4;\r
-reg kf9aea2;\r
-reg vvd7515;\r
-reg xlba8ae;\r
-reg ead4576;\r
-reg twa2bb1;\r
-reg [15 : 0] qi15d8b;\r
-reg iraec58;\r
-reg lq762c5;\r
-reg [(22 * 8) : 1] ohb162b;\r
-reg [2047:0] bl7edd9;\r
-wire [68:0] nrf6ece;\r
-\r
-localparam zmb7676 = 69,wlbb3b3 = 32'hfdffd84b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
-\r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if(!rst_n) begin hq1b3d6 <= 1'b1; shd9eb2 <= 1'b1; end else begin hq1b3d6 <= db94722; shd9eb2 <= iraec58; end\r
-end\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin if(!rst_n) begin cze24d8 <= 1'b0; ir126c4 <= 1'b0; vk93624 <= 1'b0; xl9b122 <= 1'b0; rtd8916 <= 16'd0; suc48b6 <= 1'b0; sw245b1 <= 1'b0; lf22d89 <= 1'b0; hd16c4f <= 1'b0; qib627f <= 1'b0; cbb13f9 <= 16'b0; pu89fcc <= 1'b0; bl4fe63 <= 1'b0; of7f31e <= 1'b0; rtf98f5 <= 1'b0; ofcc7af <= 16'b0; ne63d7c <= 1'b0; vk1ebe3 <= 1'b0; cmf5f1b <= 1'b0; vxaf8d9 <= 1'b0; lq7c6cf <= 1'b0; pfe367a <= 16'b0; end else begin cze24d8 <= zzba604; ir126c4 <= xyb28e4; vk93624 <= ksa3917; xl9b122 <= zz1c8b9; rtd8916 <= fae45ce; suc48b6 <= lf22e73; sw245b1 <= gd1739f; lf22d89 <= ecb9cfc; hd16c4f <= mece7e1; qib627f <= by73f09; cbb13f9 <= fcbbb1; pu89fcc <= uk3ec45; bl4fe63 <= jpf6228; of7f31e <= yzb1147; rtf98f5 <= ie88a3c; ofcc7af <= xj451e1; ne63d7c <= fp28f0e; vk1ebe3 <= jc47876; cmf5f1b <= wl3c3b2; vxaf8d9 <= xwe1d94; lq7c6cf <= tweca2; pfe367a <= by76512; end\r
-end\r
-\r
-\r
-\r
-assign bycf594 = (qi15d8b[15] == qted3ac[15]) & (qi15d8b[13:0] == qted3ac[13:0]);\r
-\r
-always @(posedge eaea698 or negedge rst_n or posedge shd9eb2) begin : gb51f46 if(!rst_n || shd9eb2) begin tucaac5 <= 1'b0; dz5562a <= 1'b0; mtab157 <= 1'b0; ne58abc <= 1'b0; nec55e2 <= 1'b0; ba2af12 <= 1'b0; ho57893 <= 1'b0; qibc49b <= 1'b0; end else begin tucaac5 <= (wlae7b6 != ux126ba); dz5562a <= lq762c5 ; mtab157 <= lq762c5 & qi15d8b[14] & qted3ac[14]; ne58abc <= (yx4eb2a == 2'b10) & wj65528; nec55e2 <= (qt75954 == 2'b10) & wj65528; ba2af12 <= (aaacaa5 == 2'b11); ho57893 <= (yx4eb2a == 2'b10) & wj65528 & lq762c5 ; qibc49b <= (sj23b4e != ph84769); end\r
-end\r
-\r
-always @(posedge eaea698 or negedge rst_n or posedge shd9eb2) begin : tue4626 if(!rst_n || shd9eb2) begin rt6ee96 <= ksa6260; end else begin if(xya24d7 || !mtbe11d || pu2a945 || xlba8ae || vv55cf6) begin rt6ee96 <= ksa6260; end else begin rt6ee96 <= ykf08ed; end end\r
-end\r
-always @(posedge eaea698 or negedge rst_n or posedge shd9eb2) begin if(!rst_n || shd9eb2) begin ea774b7 <= ksa6260; ld40f17 <= 1'b0; godb2ab <= 1'b0; thd2dcf <= 16'h0000; end else begin ea774b7 <= ph84769; ld40f17 <= ux126ba; godb2ab <= twa2bb1; thd2dcf <= qi15d8b; end\r
-end\r
-\r
-always @( ph84769 or ux126ba or jea2f84 or rv28ae7 or kf1da75 or dz4573e or ic5cfb1 or ym2b9f6) begin : rtc8cce case (ph84769) ksa6260 : begin if(ux126ba) jr2ddd2 = sw31300; else jr2ddd2 = ng89800; end\r
- sw31300 : begin if(jea2f84) jr2ddd2 = ic4c003; else jr2ddd2 = sw31300; end\r
- ic4c003 : begin if(rv28ae7 && kf1da75 != 16'd0) jr2ddd2 = sh60018; else jr2ddd2 = ic4c003; end\r
- sh60018 : begin if((dz4573e && !ic5cfb1) || (rv28ae7 && kf1da75 == 16'h0000)) jr2ddd2 = ksa6260; else if(dz4573e && ic5cfb1) jr2ddd2 = iec5; else jr2ddd2 = sh60018; end\r
- iec5 : begin if(rv28ae7 && kf1da75 == 16'h0000) jr2ddd2 = ksa6260; else if((jea2f84) && (!rv28ae7 || kf1da75 != 16'h0000)) jr2ddd2 = mg628; else jr2ddd2 = iec5; end\r
- mg628 : begin if (rv28ae7 && kf1da75 == 16'h0000) jr2ddd2 = ksa6260; else if (ym2b9f6 && jea2f84) jr2ddd2 = vx3140; else jr2ddd2 = mg628; end\r
- vx3140 : begin if (rv28ae7) jr2ddd2 = ksa6260; else jr2ddd2 = vx3140; end\r
- ng89800 : jr2ddd2 = ng89800;\r
- default : begin jr2ddd2 = ksa6260; end\r
- endcase\r
-end \r
-\r
-always @(posedge eaea698 or negedge rst_n) begin if(!rst_n) begin mr_page_rx <= 1'b0; end else begin if (ph84769 == iec5) begin mr_page_rx <= 1'b1; end else begin mr_page_rx <= 1'b0; end end\r
-end\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin if(!rst_n ) begin mr_lp_adv_ability <= 16'h0000; end else begin if ((ph84769 == ksa6260) || (ph84769 == ic4c003)) begin mr_lp_adv_ability <= 16'h0000; end else if (ph84769 == iec5) begin mr_lp_adv_ability <= qi15d8b; end else begin mr_lp_adv_ability <= mr_lp_adv_ability; end end\r
-end\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin : os5347c if(!rst_n ) begin mr_an_complete <= 1'b0; end else begin if (ph84769 == ksa6260) begin mr_an_complete <= 1'b0; end else if (ph84769 == vx3140) begin mr_an_complete <= 1'b1; end else begin mr_an_complete <= mr_an_complete; end end\r
-end\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin : co92c4c if(!rst_n ) begin tu5dd8a <= 16'd0; end else begin if ((ph84769 == ksa6260 && ux126ba) || ph84769 == sw31300) begin tu5dd8a <= 16'd0; end else if (ph84769 == ic4c003) begin tu5dd8a <= {ng935d4[16],1'b0,ng935d4[14:1]}; end else if (ph84769 == sh60018) begin tu5dd8a <= (tu5dd8a | 16'h4000); end else begin tu5dd8a <= tu5dd8a; end end\r
-end\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin : bld8bf7 if(!rst_n ) begin jceec52 <= ukf531; end else begin if (((ph84769 == ksa6260) && ux126ba) || (ph84769 == sw31300)) begin jceec52 <= of7a989; end else if (((ph84769 == ksa6260) && !ux126ba) || (ph84769 == mg628)) begin jceec52 <= ukf531; end else if ((ph84769 == ng89800) || (ph84769 == vx3140)) begin jceec52 <= kqd4c4c; end else begin jceec52 <= jceec52; end end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin if(!rst_n ) begin an3c5fc <= 1'b0; ene2fe4 <= 1'b0; cb17f25 <= 1'b0; qv78bf <= 1'b0; end else begin if ((ph84769 == sw31300) && (sj23b4e == ksa6260)) an3c5fc <= 1'b1; else an3c5fc <= 1'b0; if ((ph84769 == iec5) && (sj23b4e == sh60018)) ene2fe4 <= 1'b1; else ene2fe4 <= 1'b0; if ((ph84769 == mg628) && (sj23b4e == iec5)) cb17f25 <= 1'b1; else cb17f25 <= 1'b0; if (rv9eda2 || zxf6d17 || qib68be) qv78bf <= 1'b1; else qv78bf <= 1'b0; end\r
-end\r
-always @(posedge eaea698 or negedge rst_n) begin : lq47793 if(!rst_n ) begin fpbf92d <= sj18a07; end else if (ps73db4) begin if (kf9aea2) begin fpbf92d <= LINK_TIMER_SH; end else if (lsb2893) begin fpbf92d <= byc503c; end else begin fpbf92d <= sj18a07; end end else if (!jea2f84) begin fpbf92d <= yzb45f0 + 'd1; end else begin fpbf92d <= yzb45f0; end\r
-end\r
-always @(posedge eaea698 or negedge rst_n) begin : icef089 if(!rst_n ) begin thfc96e <= 1'b0; end else begin if (yzb45f0 == 'd0 && !ps73db4) begin thfc96e <= 1'b1; end else begin thfc96e <= 1'b0; end end\r
-end\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin : vida5e9 if(!rst_n ) begin dme4b77 <= 21'd0; end else if (vvd7515) begin if (kf9aea2) begin dme4b77 <= LINK_TIMER_SH; end else if (lsb2893) begin dme4b77 <= byc503c; end else begin dme4b77 <= sj18a07; end end else begin dme4b77 <= qv17c23 + 'd1; end\r
-end\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin : ipeda78 if(!rst_n ) begin pu25bba <= 1'b0; end else begin case(mtbe11d) 1'b0: begin if (vvd7515) begin pu25bba <= 1'b1; end end 1'b1: begin if(qv17c23 == 21'd0) begin pu25bba <= 1'b0; end end default: begin pu25bba <= 1'b0; end endcase end\r
-end\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin : wj41086 if(!rst_n ) je96e7f <= 16'h0000; else if(ale7d88) je96e7f <= 16'h0000; else if(twa2bb1) je96e7f <= qi15d8b; else je96e7f <= qted3ac;\r
-end\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin : fa6cbd1 if(!rst_n ) begin hqb73fb <= 16'h0000; end else begin if(rv28ae7) begin hqb73fb <= qi15d8b; end else begin hqb73fb <= xw69d65; end end\r
-end\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin : me4cac8 if(!rst_n ) gqb9fdb <= 2'b00; else if(ale7d88 || ead4576) gqb9fdb <= 2'b00; else if(twa2bb1 && qt54a2b && (yx4eb2a != 2'b10)) gqb9fdb <= yx4eb2a + 2'b01; else gqb9fdb <= yx4eb2a;\r
-end\r
-always @(posedge eaea698 or negedge rst_n) begin : xj553a5 if(!rst_n ) dmcfed9 <= 2'b00; else if(ale7d88 || ead4576) dmcfed9 <= 2'b00; else if(twa2bb1 && jra515c && (qt75954 != 2'b10)) dmcfed9 <= qt75954 + 2'b01; else dmcfed9 <= qt75954;\r
-end\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin : dzcdefb if(!rst_n ) en7f6ca <= 2'b00; else if(ale7d88) en7f6ca <= 2'b00; else if(ead4576 && !ym2b9f6) en7f6ca <= aaacaa5 + 2'b01; else en7f6ca <= aaacaa5;\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin if(!rst_n) begin qi82738 <= 16'd0; fp139c1 <= 16'd0; ba9ce0f <= 16'd0; wje707a <= 16'd0; nt383d4 <= 16'd0; cmc1ea6 <= 1'b0; end else begin qi82738[15:0] <= ng935d4[16:1]; fp139c1 <= ir9f84a; ba9ce0f <= fnfc255; if ((ir9f84a == fnfc255) && (ir9f84a == rge12ae)) nt383d4 <= rge12ae; else nt383d4 <= fn4ab9e; wje707a <= fn4ab9e; if ((lf9449a==1'b1) && (lsb2893==1'b0)) begin if (fn4ab9e != db9573) begin cmc1ea6 <= 1'b1; end else begin cmc1ea6 <= 1'b0; end end else begin cmc1ea6 <= 1'b0; end end\r
-end\r
-assign tu76293 = ((ph84769==vx3140) || (ph84769==ng89800)) ? 1'b1 : 1'b0;\r
-\r
-\r
-\r
-\r
-always @(ph84769) begin case (ph84769) ksa6260 : sh7aca3 = "AN_ENABLE"; sw31300 : sh7aca3 = "AN_RESTART"; ng89800 : sh7aca3 = "AN_DISABLE_LINK_OK"; ic4c003 : sh7aca3 = "ABILITY_DETECT"; sh60018 : sh7aca3 = "ACKNOWLEDGE_DETECT"; iec5 : sh7aca3 = "COMPLETE_ACKNOWLEDGE"; mg628 : sh7aca3 = "IDLE_DETECT"; vx3140 : sh7aca3 = "LINK_OK";\r
- default : sh7aca3 = "***ERROR***"; endcase\r
-end\r
-\r
-always@* begin zzba604<=nrf6ece[0];xyb28e4<=nrf6ece[1];db94722<=nrf6ece[2];ksa3917<=nrf6ece[3];zz1c8b9<=nrf6ece[4];fae45ce<={mr_adv_ability>>1,nrf6ece[5]};lf22e73<=nrf6ece[6];gd1739f<=nrf6ece[7];ecb9cfc<=nrf6ece[8];mece7e1<=nrf6ece[9];by73f09<=nrf6ece[10];ir9f84a<={qi82738>>1,nrf6ece[11]};fnfc255<={fp139c1>>1,nrf6ece[12]};rge12ae<={ba9ce0f>>1,nrf6ece[13]};db9573<={wje707a>>1,nrf6ece[14]};fn4ab9e<={nt383d4>>1,nrf6ece[15]};vv55cf6<=nrf6ece[16];wlae7b6<=nrf6ece[17];ps73db4<=nrf6ece[18];rv9eda2<=nrf6ece[19];zxf6d17<=nrf6ece[20];qib68be<=nrf6ece[21];yzb45f0<={fpbf92d>>1,nrf6ece[22]};jea2f84<=nrf6ece[23];qv17c23<={dme4b77>>1,nrf6ece[24]};mtbe11d<=nrf6ece[25];ykf08ed<={jr2ddd2>>1,nrf6ece[26]};ph84769<={rt6ee96>>1,nrf6ece[27]};sj23b4e<={ea774b7>>1,nrf6ece[28]};kf1da75<={thd2dcf>>1,nrf6ece[29]};qted3ac<={je96e7f>>1,nrf6ece[30]};xw69d65<={hqb73fb>>1,nrf6ece[31]};yx4eb2a<={gqb9fdb>>1,nrf6ece[32]};qt75954<={dmcfed9>>1,nrf6ece[33]};aaacaa5<={en7f6ca>>1,nrf6ece[34]};wj65528<=nrf6ece[35];pu2a945<=nrf6ece[36];qt54a2b<=nrf6ece[37];jra515c<=nrf6ece[38];rv28ae7<=nrf6ece[39];dz4573e<=nrf6ece[40];ym2b9f6<=nrf6ece[41];ic5cfb1<=nrf6ece[42];ale7d88<=nrf6ece[43];uk3ec45<=nrf6ece[44];jpf6228<=nrf6ece[45];yzb1147<=nrf6ece[46];ie88a3c<=nrf6ece[47];xj451e1<={rtd8916>>1,nrf6ece[48]};fp28f0e<=nrf6ece[49];jc47876<=nrf6ece[50];wl3c3b2<=nrf6ece[51];xwe1d94<=nrf6ece[52];tweca2<=nrf6ece[53];by76512<={cbb13f9>>1,nrf6ece[54]};lsb2893<=nrf6ece[55];lf9449a<=nrf6ece[56];xya24d7<=nrf6ece[57];ux126ba<=nrf6ece[58];ng935d4<={ofcc7af>>1,nrf6ece[59]};kf9aea2<=nrf6ece[60];vvd7515<=nrf6ece[61];xlba8ae<=nrf6ece[62];ead4576<=nrf6ece[63];twa2bb1<=nrf6ece[64];qi15d8b<={pfe367a>>1,nrf6ece[65]};iraec58<=nrf6ece[66];lq762c5<=nrf6ece[67];ohb162b<={sh7aca3>>1,nrf6ece[68]};end\r
-always@* begin bl7edd9[2047]<=sgmii_mode;bl7edd9[2046]<=mr_main_reset;bl7edd9[2044]<=mr_restart_an;bl7edd9[2040]<=mr_an_enable;bl7edd9[2033]<=mr_adv_ability[1];bl7edd9[2019]<=ip70450;bl7edd9[1999]<=godb2ab;bl7edd9[1991]<=sj8a10b;bl7edd9[1981]<=lf22d89;bl7edd9[1958]<=bl4fe63;bl7edd9[1950]<=tucaac5;bl7edd9[1947]<=ho57893;bl7edd9[1934]<=zx5085d;bl7edd9[1914]<=hd16c4f;bl7edd9[1892]<=ene2fe4;bl7edd9[1868]<=of7f31e;bl7edd9[1852]<=dz5562a;bl7edd9[1851]<=nt383d4[0];bl7edd9[1847]<=qibc49b;bl7edd9[1820]<=db842ee;bl7edd9[1783]<=rtd8916[1];bl7edd9[1780]<=qib627f;bl7edd9[1737]<=cb17f25;bl7edd9[1689]<=rtf98f5;bl7edd9[1657]<=mtab157;bl7edd9[1654]<=cmc1ea6;bl7edd9[1647]<=cze24d8;bl7edd9[1610]<=dme4b77[0];bl7edd9[1608]<=lq7c6cf;bl7edd9[1593]<=ym21776;bl7edd9[1523]<=dmcfed9[0];bl7edd9[1519]<=suc48b6;bl7edd9[1513]<=cbb13f9[0];bl7edd9[1426]<=fpbf92d[0];bl7edd9[1404]<=hqb73fb[0];bl7edd9[1330]<=ofcc7af[1];bl7edd9[1267]<=ne58abc;bl7edd9[1260]<=ld40f17;bl7edd9[1246]<=ir126c4;bl7edd9[1225]<=vk1ebe3;bl7edd9[1199]<=ea774b7[0];bl7edd9[1173]<=pu25bba;bl7edd9[1169]<=pfe367a[0];bl7edd9[1163]<=sh7aca3[1];bl7edd9[1139]<=qi82738[0];bl7edd9[1023]<=gbe_mode;bl7edd9[999]<=en7f6ca[0];bl7edd9[990]<=sw245b1;bl7edd9[979]<=pu89fcc;bl7edd9[973]<=ba2af12;bl7edd9[946]<=an3c5fc;bl7edd9[925]<=wje707a[0];bl7edd9[891]<=xl9b122;bl7edd9[805]<=thfc96e;bl7edd9[804]<=vxaf8d9;bl7edd9[761]<=gqb9fdb[0];bl7edd9[702]<=je96e7f[0];bl7edd9[612]<=ne63d7c;bl7edd9[599]<=rt6ee96[0];bl7edd9[581]<=bycf594;bl7edd9[486]<=nec55e2;bl7edd9[473]<=qv78bf;bl7edd9[462]<=ba9ce0f[0];bl7edd9[445]<=vk93624;bl7edd9[402]<=cmf5f1b;bl7edd9[351]<=thd2dcf[0];bl7edd9[299]<=jr2ddd2[0];bl7edd9[290]<=hq1b3d6;bl7edd9[231]<=fp139c1[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module kf95b26 (\r
- \r
- lsad934 ,\r
- rst_n ,\r
- mr_main_reset ,\r
- \r
- \r
- rx_data ,\r
- rx_kcntl ,\r
- baa25a8 ,\r
- \r
- sj8a10b ,\r
- rx_even ,\r
- jceec52 ,\r
- \r
- \r
- fcbbb1 ,\r
- ps42af3 ,\r
- qi1579a ,\r
- mtabcd1 ,\r
-\r
- sh5e68d ,\r
- dzf346c ,\r
- cb9a367 \r
- );\r
-input lsad934;\r
-input rst_n;\r
-input mr_main_reset;\r
-input [7:0] rx_data;\r
-input rx_kcntl;\r
-input baa25a8;\r
-input sj8a10b;\r
-input rx_even;\r
-input [1:0] jceec52;\r
-output [15:0] fcbbb1;\r
-output ps42af3;\r
-output qi1579a;\r
-output mtabcd1;\r
-output [7:0] sh5e68d;\r
-output dzf346c;\r
-output cb9a367;\r
-localparam ksb988c = 8'hBC , kdcc461 = 8'hFE , go6230c = 8'hFB , ng11860 = 8'hFD , je8c302 = 8'hF7 , bl61812 = 8'hB5 , bnc096 = 8'h42 , of604b6 = 8'hC5 , ep25b5 = 8'h50 , mt12dad = 8'h00 , fc96d6d = 8'hFC , aab6b6b = 8'h3C ;\r
-localparam bnb5b58 = 5'd0 , lsadac7 = 5'd1 , ea6d63a = 5'd2 , hb6b1d1 = 5'd3 , zk58e8e = 5'd4 , hbc7472 = 5'd5 , je3a397 = 5'd6 , ayd1cbb = 5'd7 , lf8e5d8 = 5'd8 , su72ec7 = 5'd9 , mg97638 = 5'd10 , cbbb1c0 = 5'd11 , zxd8e05 = 5'd12 , hbc702e = 5'd13 , lf38177 = 5'd14 , nec0bbe = 5'd15 , ec5df3 = 5'd16 , ks2ef99 = 5'd17 ;\r
-reg cb9a367;\r
-reg dzf346c;\r
-reg [7:0] sh5e68d;\r
-reg xy9922f;\r
-reg [15:0] fcbbb1;\r
-reg ps42af3;\r
-reg qi1579a;\r
-reg mtabcd1;\r
-reg [7:0] th7b8fa ;\r
-reg [7:0] aldc7d6 ;\r
-reg [7:0] the3eb5 ;\r
-reg [7:0] qi1f5af ;\r
-reg [7:0] kqfad78 ;\r
-reg gbd6bc0 ;\r
-reg lfb5e05 ;\r
-reg phaf02f ;\r
-reg kq7817e ;\r
-reg fac0bf0 ;\r
-reg sw5f83 ;\r
-reg tw2fc19 ;\r
-reg xj7e0cb ;\r
-reg icf065f ;\r
-reg ls832f8 ;\r
-reg rv197c3 ;\r
-reg wwcbe1f ;\r
-reg bl5f0f8 ;\r
-reg wjf87c6 ;\r
-reg yxc3e34 ;\r
-reg ks1f1a4 ;\r
-reg qtf8d20 ;\r
-reg gbc6905 ;\r
-reg wy3482c ;\r
-reg yza4161 ;\r
-reg fc20b0d ;\r
-reg ec586a ;\r
-reg mt2c351 ;\r
-reg th61a8d ;\r
-reg [4:0] ohd46e ;\r
-reg [4:0] of6a374 ;\r
-wire en51ba4 ;\r
-wire ou8dd24 ;\r
-wire th6e921 ;\r
-wire xj7490f ;\r
-wire gda487f ;\r
-wire mg243fc ;\r
-wire mg21fe1 ;\r
-wire ieff08 ;\r
-wire sh7f840 ;\r
-wire thfc204 ;\r
-wire zke1026 ;\r
-wire oh8133 ;\r
-wire pf4099c ;\r
-wire vk4ce7 ;\r
-reg [1:0] sj2673b;\r
-reg [1:0] gd339dc;\r
-reg [(20*8):1] vk9cee4;\r
-reg db94722;\r
-reg [7 : 0] qi3b914;\r
-reg czdc8a0;\r
-reg dme4504;\r
-reg gd1739f;\r
-reg hq1411f;\r
-reg [1 : 0] tja08fb;\r
-reg ng47de;\r
-reg [7 : 0] cb23ef2;\r
-reg [7 : 0] ks1f795;\r
-reg [7 : 0] psfbca8;\r
-reg [7 : 0] sude542;\r
-reg [7 : 0] czf2a10;\r
-reg qv95084;\r
-reg lsa8425;\r
-reg jc4212b;\r
-reg ym1095b;\r
-reg vx84ad8;\r
-reg ri256c7;\r
-reg aa2b63b;\r
-reg wj5b1d8;\r
-reg jpd8ec4;\r
-reg jpc7626;\r
-reg ym3b137;\r
-reg thd89b9;\r
-reg icc4dce;\r
-reg sj26e71;\r
-reg lf3738d;\r
-reg mgb9c6f;\r
-reg ykce379;\r
-reg vv71bc9;\r
-reg ou8de4f;\r
-reg sh6f279;\r
-reg jc793cc;\r
-reg yxc9e62;\r
-reg vv4f315;\r
-reg vi798af;\r
-reg [4 : 0] uvcc57b;\r
-reg [4 : 0] ic62bdc;\r
-reg gq15ee1;\r
-reg hdaf708;\r
-reg bl7b846;\r
-reg mrdc236;\r
-reg jce11b5;\r
-reg qv8dab;\r
-reg go46d5d;\r
-reg yz36ae8;\r
-reg lfb5744;\r
-reg kfaba26;\r
-reg by5d135;\r
-reg ale89ab;\r
-reg wj44d5c;\r
-reg an26ae5;\r
-reg [1 : 0] vk3572d;\r
-reg [1 : 0] mtab96a;\r
-reg [(20 * 8) : 1] qg5cb55;\r
-reg [2047:0] bl7edd9;\r
-wire [55:0] nrf6ece;\r
-\r
-localparam zmb7676 = 56,wlbb3b3 = 32'hfdffc70b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if (!rst_n) begin th7b8fa <= 8'h00 ; aldc7d6 <= 8'h00 ; the3eb5 <= 8'h00 ; qi1f5af <= 8'h00 ; kqfad78 <= 8'h00 ; gbd6bc0 <= 1'b0 ; lfb5e05 <= 1'b0 ; phaf02f <= 1'b0 ; kq7817e <= 1'b0 ; fac0bf0 <= 1'b0 ; sw5f83 <= 1'b0 ; tw2fc19 <= 1'b0 ; xj7e0cb <= 1'b0 ; icf065f <= 1'b0 ; ls832f8 <= 1'b0 ; rv197c3 <= 1'b0 ; wwcbe1f <= 1'b0 ; end else begin th7b8fa <= qi3b914 ; aldc7d6 <= cb23ef2 ; the3eb5 <= ks1f795 ; qi1f5af <= psfbca8 ; kqfad78 <= sude542 ; gbd6bc0 <= czdc8a0 ; lfb5e05 <= qv95084 ; phaf02f <= lsa8425 ; kq7817e <= jc4212b ; fac0bf0 <= dme4504 ; sw5f83 <= vx84ad8 ; tw2fc19 <= ri256c7 ; xj7e0cb <= aa2b63b ; ls832f8 <= hq1411f ; rv197c3 <= jpc7626 ; wwcbe1f <= ym3b137 ; end\r
-end\r
-\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if (!rst_n) begin sj2673b <= 2'd0 ; gd339dc <= 2'd0 ; end else begin sj2673b <= tja08fb ; gd339dc <= vk3572d ; end\r
-end\r
-\r
-assign en51ba4 = ((psfbca8 == ksb988c) & jc4212b) ;\r
-assign ou8dd24 = ((psfbca8 == go6230c) & jc4212b) ;\r
-assign th6e921 = ((psfbca8 == bl61812) & ~jc4212b) ;\r
-assign xj7490f = ((psfbca8 == bnc096) & ~jc4212b) ;\r
-assign gda487f = ~((psfbca8 == ksb988c) & jc4212b) ;\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if (!rst_n) begin bl5f0f8 <= 1'b0 ; wjf87c6 <= 1'b0 ; yxc3e34 <= 1'b0 ; ks1f1a4 <= 1'b0 ; qtf8d20 <= 1'b0 ; end else begin bl5f0f8 <= gq15ee1 ; wjf87c6 <= hdaf708 ; yxc3e34 <= bl7b846 ; ks1f1a4 <= mrdc236 ; qtf8d20 <= jce11b5 ; end\r
-end\r
-\r
-\r
-assign mg243fc = (((psfbca8 == ksb988c) & jc4212b ) & ( ~lsa8425 ) & ((cb23ef2 == ksb988c) & qv95084 ) ) ;\r
-\r
-\r
-assign mg21fe1 = (((psfbca8 == ksb988c) & jc4212b ) & (((ks1f795 == bl61812) | (ks1f795 == bnc096)) & ~lsa8425 ) & ((cb23ef2 == mt12dad) & ~qv95084 ) ) ;\r
-\r
-\r
-assign ieff08 = (((psfbca8 == ng11860) & jc4212b ) & ((ks1f795 == je8c302) & lsa8425 ) & ((cb23ef2 == ksb988c) & qv95084 ) ) ;\r
-\r
-\r
-assign sh7f840 = (((psfbca8 == ng11860) & jc4212b ) & ((ks1f795 == je8c302) & lsa8425 ) & ((cb23ef2 == je8c302) & qv95084 ) ) ;\r
-\r
-\r
-assign thfc204 = (((psfbca8 == je8c302) & jc4212b ) & ((ks1f795 == je8c302) & lsa8425 ) & ((cb23ef2 == je8c302) & qv95084 ) ) ;\r
-\r
-\r
-assign zke1026 = (((psfbca8 == je8c302) & jc4212b ) & ((ks1f795 == je8c302) & lsa8425 ) & ((cb23ef2 == ksb988c) & qv95084 ) ) ;\r
-\r
-\r
-assign oh8133 = (((psfbca8 == je8c302) & jc4212b ) & ((ks1f795 == je8c302) & lsa8425 ) & ((cb23ef2 == go6230c) & qv95084 ) ) ;\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if (!rst_n) begin gbc6905 <= 1'b0 ; wy3482c <= 1'b0 ; yza4161 <= 1'b0 ; fc20b0d <= 1'b0 ; ec586a <= 1'b0 ; mt2c351 <= 1'b0 ; th61a8d <= 1'b0 ; end else begin gbc6905 <= qv8dab ; wy3482c <= go46d5d ; yza4161 <= yz36ae8 ; fc20b0d <= lfb5744 ; ec586a <= kfaba26 ; mt2c351 <= by5d135 ; th61a8d <= ale89ab ; end\r
-end\r
-\r
- assign pf4099c = (mtab96a == 2'b01) ; assign vk4ce7 = (mtab96a == 2'b10) ;\r
-\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if (!rst_n) ohd46e <= lsadac7 ; else if (db94722) ohd46e <= lsadac7 ; else if (!gd1739f) ohd46e <= bnb5b58 ; else ohd46e <= ic62bdc ;\r
-end\r
-\r
-\r
-always @(uvcc57b or ym3b137 or an26ae5 or wj44d5c or ym1095b or wj5b1d8 or vv71bc9 or ou8de4f or sh6f279 or jc793cc or yxc9e62 or vv4f315 or vi798af or icc4dce or sj26e71 or lf3738d or mgb9c6f or ykce379 ) begin case (uvcc57b) bnb5b58 : of6a374 = lsadac7 ; lsadac7 : if (icc4dce && ym3b137) of6a374 = ea6d63a ; else of6a374 = lsadac7 ; ea6d63a : if (lf3738d || mgb9c6f) of6a374 = hb6b1d1 ; else if (!an26ae5 && (ym1095b || wj5b1d8)) of6a374 = je3a397 ; else if ((!an26ae5 && (!ym1095b && !wj5b1d8) && !lf3738d && !mgb9c6f) || (an26ae5 && !lf3738d && !mgb9c6f)) of6a374 = ayd1cbb ; else of6a374 = ea6d63a ; hb6b1d1 : if (!ym1095b && !wj5b1d8) of6a374 = zk58e8e ; else of6a374 = je3a397 ; zk58e8e : if (!ym1095b && !wj5b1d8) of6a374 = hbc7472 ; else of6a374 = je3a397 ; hbc7472 : if (icc4dce && ym3b137) of6a374 = ea6d63a ; else if (!icc4dce || !ym3b137) of6a374 = je3a397 ; else of6a374 = hbc7472 ; je3a397 : if (icc4dce && ym3b137) of6a374 = ea6d63a; else if (!icc4dce && ym3b137) of6a374 = lsadac7; else of6a374 = je3a397; ayd1cbb : if (!icc4dce && !an26ae5) of6a374 = je3a397; else if (an26ae5 && ykce379) if (!sj26e71) of6a374 = lf8e5d8; else of6a374 = su72ec7; else if ((an26ae5 && !ykce379) || icc4dce) of6a374 = ea6d63a; else of6a374 = ayd1cbb; lf8e5d8 : if (icc4dce && ym3b137) of6a374 = ea6d63a; else of6a374 = lf8e5d8; su72ec7 : if ((vv71bc9 || ou8de4f) && ym3b137) of6a374 = mg97638; else if (sh6f279 && ym3b137) of6a374 = cbbb1c0; else if (jc793cc) of6a374 = zxd8e05; else if (yxc9e62) of6a374 = nec0bbe; else if (!ym1095b && !wj5b1d8) of6a374 = lf38177; else of6a374 = hbc702e; mg97638 : if (!lf3738d && !mgb9c6f) of6a374 = ayd1cbb; else of6a374 = hb6b1d1; cbbb1c0 : if (icc4dce) of6a374 = ea6d63a; else of6a374 = cbbb1c0; zxd8e05 : if (yxc9e62) of6a374 = zxd8e05; else if (vv4f315 && ym3b137) of6a374 = cbbb1c0; else if (vi798af) of6a374 = ec5df3; else of6a374 = ks2ef99; hbc702e : if ((vv71bc9 || ou8de4f) && ym3b137) of6a374 = mg97638; else if (sh6f279 && ym3b137) of6a374 = cbbb1c0; else if (jc793cc) of6a374 = zxd8e05; else if (yxc9e62) of6a374 = nec0bbe; else if (!ym1095b && !wj5b1d8) of6a374 = lf38177; else of6a374 = hbc702e; lf38177 : if ((vv71bc9 || ou8de4f) && ym3b137) of6a374 = mg97638; else if (sh6f279 && ym3b137) of6a374 = cbbb1c0; else if (jc793cc) of6a374 = zxd8e05; else if (yxc9e62) of6a374 = nec0bbe; else if (!ym1095b && !wj5b1d8) of6a374 = lf38177; else of6a374 = hbc702e; nec0bbe : if (yxc9e62) of6a374 = zxd8e05; else if (vv4f315 && ym3b137) of6a374 = cbbb1c0; else if (vi798af) of6a374 = ec5df3; else of6a374 = ks2ef99; ec5df3 : if (sj26e71) of6a374 = su72ec7; else of6a374 = ec5df3; ks2ef99 : if (sj26e71) of6a374 = su72ec7; else if (icc4dce && ym3b137) of6a374 = ea6d63a; else if (!sj26e71 && !icc4dce && ym3b137) if (yxc9e62) of6a374 = zxd8e05; else if (vv4f315 && ym3b137) of6a374 = cbbb1c0; else if (vi798af) of6a374 = ec5df3; else of6a374 = ks2ef99; else of6a374 = ks2ef99; default : of6a374 = lsadac7; endcase\r
-end\r
-\r
-\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if(!rst_n) cb9a367 <= 1'b0; else if (uvcc57b == lf8e5d8 || uvcc57b == mg97638 || uvcc57b == hbc702e || uvcc57b == nec0bbe || uvcc57b == zxd8e05 || (uvcc57b == bnb5b58 && ng47de)) cb9a367 <= 1'b1; else if (uvcc57b == zk58e8e || uvcc57b == hbc7472 || uvcc57b == je3a397 || uvcc57b == ks2ef99 || uvcc57b == ec5df3) cb9a367 <= cb9a367; else cb9a367 <= 1'b0;\r
-end\r
-\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if(!rst_n) dzf346c <= 1'b0; else if (uvcc57b == su72ec7) dzf346c <= 1'b1; else if (uvcc57b == zk58e8e || uvcc57b == hbc7472 || uvcc57b == je3a397 || uvcc57b == lf8e5d8 || (uvcc57b == bnb5b58 && ng47de == 1'b1) || uvcc57b == mg97638 || uvcc57b == hbc702e || uvcc57b == lf38177 || uvcc57b == nec0bbe) dzf346c <= dzf346c; else dzf346c <= 1'b0;\r
-end\r
-\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if(!rst_n) sh5e68d <= 8'b00000000; else if (uvcc57b == su72ec7) sh5e68d <= 8'b01010101; else if (uvcc57b == ec5df3 || uvcc57b == zxd8e05) sh5e68d <= 8'b00001111; else if (uvcc57b == ks2ef99) sh5e68d <= 8'b00011111; else if (uvcc57b == lf8e5d8) sh5e68d <= 8'b00001110; else if (uvcc57b == lf38177) sh5e68d <= czf2a10; else sh5e68d <= 8'b00000000;\r
-end\r
-\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if(!rst_n) xy9922f <= 1'b0; else if (uvcc57b == ayd1cbb && an26ae5 && ykce379) xy9922f <= 1'b1; else if (uvcc57b == cbbb1c0 || (uvcc57b == bnb5b58 && ng47de) || uvcc57b == lsadac7 || uvcc57b == ea6d63a || uvcc57b == hb6b1d1 || uvcc57b == ayd1cbb) xy9922f <= 1'b0; else xy9922f <= ng47de;\r
-end always @(posedge lsad934 or negedge rst_n) begin if(!rst_n) fcbbb1 <= 16'h0000; else if(uvcc57b == zk58e8e) begin fcbbb1[7:0] <= czf2a10; fcbbb1[15:8] <= fcbbb1[15:8]; end else if(uvcc57b == hbc7472) begin fcbbb1[ 7:0] <= fcbbb1[7:0]; fcbbb1[15:8] <= czf2a10; end else fcbbb1 <= fcbbb1; end\r
- always @(posedge lsad934 or negedge rst_n) begin if(!rst_n) ps42af3 <= 1'b0; else if(uvcc57b == hbc7472) ps42af3 <= 1'b1; else ps42af3 <= 1'b0; end always @(posedge lsad934 or negedge rst_n) begin if(!rst_n) qi1579a <= 1'b0; else if(uvcc57b == ayd1cbb) qi1579a <= 1'b1; else qi1579a <= 1'b0; end always @(posedge lsad934 or negedge rst_n) begin if(!rst_n) mtabcd1 <= 1'b0; else if((uvcc57b == je3a397 && wj44d5c) || (uvcc57b == bnb5b58 && !an26ae5)) mtabcd1 <= 1'b1; else mtabcd1 <= 1'b0; end\r
-\r
-\r
-\r
-\r
-\r
-always @(uvcc57b)\r
-begin case (uvcc57b) bnb5b58 : vk9cee4 = "LNK_FAIL"; lsadac7 : vk9cee4 = "WAIT_K"; ea6d63a : vk9cee4 = "RX_K"; hb6b1d1 : vk9cee4 = "RX_CB"; zk58e8e : vk9cee4 = "RX_CC"; hbc7472 : vk9cee4 = "RX_CD"; je3a397 : vk9cee4 = "RX_INV"; ayd1cbb : vk9cee4 = "IDL_D"; lf8e5d8 : vk9cee4 = "FLS_CARR"; su72ec7 : vk9cee4 = "SOP"; mg97638 : vk9cee4 = "ERLY_END"; cbbb1c0 : vk9cee4 = "TRI_RRI"; zxd8e05 : vk9cee4 = "TRR_EXT"; hbc702e : vk9cee4 = "RXD_ERR"; lf38177 : vk9cee4 = "RX_D"; nec0bbe : vk9cee4 = "EEND_EXT"; ec5df3 : vk9cee4 = "PKT_BRRS"; ks2ef99 : vk9cee4 = "EXT_ERR"; default : vk9cee4 = " ERROR "; endcase\r
-end\r
-\r
-\r
-always@* begin db94722<=nrf6ece[0];qi3b914<={rx_data>>1,nrf6ece[1]};czdc8a0<=nrf6ece[2];dme4504<=nrf6ece[3];gd1739f<=nrf6ece[4];hq1411f<=nrf6ece[5];tja08fb<={jceec52>>1,nrf6ece[6]};ng47de<=nrf6ece[7];cb23ef2<={th7b8fa>>1,nrf6ece[8]};ks1f795<={aldc7d6>>1,nrf6ece[9]};psfbca8<={the3eb5>>1,nrf6ece[10]};sude542<={qi1f5af>>1,nrf6ece[11]};czf2a10<={kqfad78>>1,nrf6ece[12]};qv95084<=nrf6ece[13];lsa8425<=nrf6ece[14];jc4212b<=nrf6ece[15];ym1095b<=nrf6ece[16];vx84ad8<=nrf6ece[17];ri256c7<=nrf6ece[18];aa2b63b<=nrf6ece[19];wj5b1d8<=nrf6ece[20];jpd8ec4<=nrf6ece[21];jpc7626<=nrf6ece[22];ym3b137<=nrf6ece[23];thd89b9<=nrf6ece[24];icc4dce<=nrf6ece[25];sj26e71<=nrf6ece[26];lf3738d<=nrf6ece[27];mgb9c6f<=nrf6ece[28];ykce379<=nrf6ece[29];vv71bc9<=nrf6ece[30];ou8de4f<=nrf6ece[31];sh6f279<=nrf6ece[32];jc793cc<=nrf6ece[33];yxc9e62<=nrf6ece[34];vv4f315<=nrf6ece[35];vi798af<=nrf6ece[36];uvcc57b<={ohd46e>>1,nrf6ece[37]};ic62bdc<={of6a374>>1,nrf6ece[38]};gq15ee1<=nrf6ece[39];hdaf708<=nrf6ece[40];bl7b846<=nrf6ece[41];mrdc236<=nrf6ece[42];jce11b5<=nrf6ece[43];qv8dab<=nrf6ece[44];go46d5d<=nrf6ece[45];yz36ae8<=nrf6ece[46];lfb5744<=nrf6ece[47];kfaba26<=nrf6ece[48];by5d135<=nrf6ece[49];ale89ab<=nrf6ece[50];wj44d5c<=nrf6ece[51];an26ae5<=nrf6ece[52];vk3572d<={sj2673b>>1,nrf6ece[53]};mtab96a<={gd339dc>>1,nrf6ece[54]};qg5cb55<={vk9cee4>>1,nrf6ece[55]};end\r
-always@* begin bl7edd9[2047]<=rx_data[0];bl7edd9[2046]<=rx_kcntl;bl7edd9[2044]<=baa25a8;bl7edd9[2040]<=sj8a10b;bl7edd9[2032]<=rx_even;bl7edd9[2016]<=jceec52[0];bl7edd9[1985]<=xy9922f;bl7edd9[1922]<=th7b8fa[0];bl7edd9[1867]<=tw2fc19;bl7edd9[1804]<=sh7f840;bl7edd9[1797]<=aldc7d6[0];bl7edd9[1761]<=mg243fc;bl7edd9[1686]<=xj7e0cb;bl7edd9[1623]<=gd339dc[0];bl7edd9[1561]<=thfc204;bl7edd9[1558]<=ks1f1a4;bl7edd9[1547]<=the3eb5[0];bl7edd9[1542]<=th61a8d;bl7edd9[1490]<=fac0bf0;bl7edd9[1475]<=mg21fe1;bl7edd9[1413]<=wjf87c6;bl7edd9[1409]<=ec586a;bl7edd9[1324]<=icf065f;bl7edd9[1200]<=rv197c3;bl7edd9[1199]<=vk9cee4[1];bl7edd9[1074]<=zke1026;bl7edd9[1068]<=qtf8d20;bl7edd9[1047]<=qi1f5af[0];bl7edd9[1037]<=ohd46e[0];bl7edd9[1023]<=mr_main_reset;bl7edd9[933]<=sw5f83;bl7edd9[902]<=ieff08;bl7edd9[880]<=gda487f;bl7edd9[811]<=sj2673b[0];bl7edd9[779]<=yxc3e34;bl7edd9[771]<=mt2c351;bl7edd9[745]<=kq7817e;bl7edd9[706]<=bl5f0f8;bl7edd9[704]<=fc20b0d;bl7edd9[600]<=ls832f8;bl7edd9[440]<=xj7490f;bl7edd9[405]<=vk4ce7;bl7edd9[372]<=phaf02f;bl7edd9[353]<=wwcbe1f;bl7edd9[352]<=yza4161;bl7edd9[220]<=th6e921;bl7edd9[202]<=pf4099c;bl7edd9[186]<=lfb5e05;bl7edd9[176]<=wy3482c;bl7edd9[110]<=ou8dd24;bl7edd9[101]<=oh8133;bl7edd9[93]<=gbd6bc0;bl7edd9[88]<=gbc6905;bl7edd9[55]<=en51ba4;bl7edd9[46]<=kqfad78[0];bl7edd9[27]<=of6a374[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module fp8bd4a (\r
- lsad934 ,\r
- rst_n ,\r
- mr_main_reset ,\r
- \r
- signal_detect ,\r
- rx_data ,\r
- rx_kcntl ,\r
- baa25a8 ,\r
- \r
- sj8a10b ,\r
- rx_even \r
- );\r
-input lsad934 ;\r
-input rst_n ;\r
-input mr_main_reset ;\r
-input signal_detect ;\r
-input [7:0] rx_data ;\r
-input rx_kcntl ;\r
-input baa25a8 ;\r
-output sj8a10b ;\r
-output rx_even ;\r
-localparam lf8be49 = 4'b0000 , rt5f24e = 4'b0001 , vvf9276 = 4'b0010 , qtc93b6 = 4'b0011 , cm49db4 = 4'b0100 , al4eda1 = 4'b0101 , fa76d0c = 4'b0110 , mgb6862 = 4'b0111 , sjb4310 = 4'b1000 , oha1884 = 4'b1001 , bnc424 = 4'b1010 , me62126 = 4'b1011 , ie10930 = 4'b1100 ;\r
-reg sj8a10b ;\r
-reg rx_even ;\r
-reg [3:0] oh26038 ;\r
-reg [3:0] zm301c4 ;\r
-reg [1:0] sj80e22 ;\r
-reg ux7115 ;\r
-reg lf388ad ;\r
-reg qgc456f ;\r
-reg bn22b78 ;\r
-reg co15bc7 ;\r
-wire zmade38 ;\r
-reg of6f1c2 ;\r
-reg cm78e14 ;\r
-reg zxc70a1 ;\r
-reg [(20*8):1] zz3850f;\r
-reg db94722;\r
-reg do143f6;\r
-reg [7 : 0] qi3b914;\r
-reg czdc8a0;\r
-reg dme4504;\r
-reg [3 : 0] blf6706;\r
-reg [3 : 0] ksb3837;\r
-reg [1 : 0] ba9c1b8;\r
-reg yke0dc3;\r
-reg db6e18;\r
-reg bn370c6;\r
-reg lsb8637;\r
-reg ofc31ba;\r
-reg oh18dd5;\r
-reg wjc6eac;\r
-reg xl37564;\r
-reg hdbab27;\r
-reg [(20 * 8) : 1] hod593e;\r
-reg [2047:0] bl7edd9;\r
-wire [17:0] nrf6ece;\r
-\r
-localparam zmb7676 = 18,wlbb3b3 = 32'hfdffe0cb;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign zmade38 = ( czdc8a0 & (qi3b914[5:0] == 6'b111100) & ((qi3b914[7:6] == 2'b00) | (qi3b914[7:6] == 2'b10) | (qi3b914[7:6] == 2'b11)));\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if (!rst_n) begin zxc70a1 <= 1'b0 ; of6f1c2 <= 1'b0 ; cm78e14 <= 1'b0 ; end else begin zxc70a1 <= oh18dd5 & ~dme4504; of6f1c2 <= (dme4504 | (oh18dd5 & ofc31ba)); cm78e14 <= ~czdc8a0 & ~wjc6eac ; end\r
-end\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if (!rst_n) begin ux7115 <= 1'b0 ; lf388ad <= 1'b0 ; qgc456f <= 1'b0 ; bn22b78 <= 1'b0 ; co15bc7 <= 1'b0 ; end else begin ux7115 <= do143f6 ; lf388ad <= yke0dc3 ; qgc456f <= db6e18 ; bn22b78 <= (db6e18 ^ bn370c6) ; co15bc7 <= rx_even ; end\r
-end\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if(!rst_n) oh26038 <= lf8be49 ; else if (db94722 || lsb8637) oh26038 <= lf8be49 ; else oh26038 <= ksb3837 ;\r
-end\r
-\r
-\r
-always @(blf6706 or hdbab27 or xl37564 or ba9c1b8 or rx_even or wjc6eac) begin case (blf6706) lf8be49 : if (hdbab27 && bn370c6) zm301c4 = rt5f24e ; else zm301c4 = lf8be49 ; rt5f24e : if (xl37564) zm301c4 = vvf9276 ; else zm301c4 = lf8be49 ; vvf9276 : if (!rx_even && hdbab27) zm301c4 = qtc93b6 ; else if (wjc6eac) zm301c4 = lf8be49 ; else zm301c4 = vvf9276 ; qtc93b6 : if (xl37564) zm301c4 = cm49db4 ; else zm301c4 = lf8be49 ; cm49db4 : if (!rx_even && hdbab27) zm301c4 = al4eda1 ; else if (wjc6eac) zm301c4 = lf8be49 ; else zm301c4 = cm49db4 ; al4eda1: if (xl37564) zm301c4 = fa76d0c; else zm301c4 = lf8be49; fa76d0c: if (wjc6eac) zm301c4 = mgb6862; else zm301c4 = fa76d0c; mgb6862: if (wjc6eac) zm301c4 = oha1884; else zm301c4 = sjb4310; sjb4310: if (wjc6eac) zm301c4 = oha1884; else if (ba9c1b8 == 2'b11) zm301c4 = fa76d0c; else zm301c4 = sjb4310; oha1884: if (wjc6eac) zm301c4 = me62126; else zm301c4 = bnc424; bnc424: if (wjc6eac) zm301c4 = me62126; else if (ba9c1b8 == 2'b11) zm301c4 = mgb6862; else zm301c4 = bnc424; me62126: if (wjc6eac) zm301c4 = lf8be49; else zm301c4 = ie10930; ie10930: if (wjc6eac) zm301c4 = lf8be49; else if (ba9c1b8 == 2'b11) zm301c4 = oha1884; else zm301c4 = ie10930; default: zm301c4 = lf8be49; endcase\r
-end\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if (!rst_n) sj80e22 <= 2'b00; else if ((blf6706 == sjb4310) || (blf6706 == bnc424) || (blf6706 == ie10930)) sj80e22 <= ba9c1b8 + 1'b1; else sj80e22 <= 2'b00;\r
-end\r
-\r
-\r
-always @(posedge lsad934 or negedge rst_n) begin if (!rst_n) sj8a10b <= 1'b0; else if (blf6706 == lf8be49) sj8a10b <= 1'b0; else if (blf6706 == fa76d0c) sj8a10b <= 1'b1; else sj8a10b <= sj8a10b ;\r
-end\r
-always @(blf6706 or ofc31ba) begin case (blf6706) rt5f24e, qtc93b6, al4eda1 : rx_even = 1'b1 ; lf8be49, vvf9276, cm49db4, fa76d0c, mgb6862, oha1884, me62126, sjb4310, bnc424, ie10930 : rx_even = ~ofc31ba ; default : rx_even = 1'b0; endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-always @(blf6706)\r
-begin case (blf6706) lf8be49 : zz3850f = "LOS"; rt5f24e : zz3850f = "COM_DET1"; vvf9276 : zz3850f = "AQR_SYNC1"; qtc93b6 : zz3850f = "COM_DET2"; cm49db4 : zz3850f = "AQR_SYNC2"; al4eda1 : zz3850f = "COM_DET3"; fa76d0c : zz3850f = "SYNC_AQRD1"; mgb6862 : zz3850f = "SYNC_AQRD2"; sjb4310 : zz3850f = "SYNC_AQRD2A"; oha1884 : zz3850f = "SYNC_AQRD3"; bnc424 : zz3850f = "SYNC_AQRD3A"; me62126 : zz3850f = "SYNC_AQRD4"; ie10930 : zz3850f = "SYNC_AQRD4A"; default : zz3850f = " ERROR "; endcase\r
-end\r
-\r
-\r
-always@* begin db94722<=nrf6ece[0];do143f6<=nrf6ece[1];qi3b914<={rx_data>>1,nrf6ece[2]};czdc8a0<=nrf6ece[3];dme4504<=nrf6ece[4];blf6706<={oh26038>>1,nrf6ece[5]};ksb3837<={zm301c4>>1,nrf6ece[6]};ba9c1b8<={sj80e22>>1,nrf6ece[7]};yke0dc3<=nrf6ece[8];db6e18<=nrf6ece[9];bn370c6<=nrf6ece[10];lsb8637<=nrf6ece[11];ofc31ba<=nrf6ece[12];oh18dd5<=nrf6ece[13];wjc6eac<=nrf6ece[14];xl37564<=nrf6ece[15];hdbab27<=nrf6ece[16];hod593e<={zz3850f>>1,nrf6ece[17]};end\r
-always@* begin bl7edd9[2047]<=signal_detect;bl7edd9[2046]<=rx_data[0];bl7edd9[2044]<=rx_kcntl;bl7edd9[2040]<=baa25a8;bl7edd9[2033]<=oh26038[0];bl7edd9[2018]<=zm301c4[0];bl7edd9[1988]<=sj80e22[0];bl7edd9[1929]<=ux7115;bl7edd9[1811]<=lf388ad;bl7edd9[1574]<=qgc456f;bl7edd9[1247]<=cm78e14;bl7edd9[1101]<=bn22b78;bl7edd9[1023]<=mr_main_reset;bl7edd9[894]<=zz3850f[1];bl7edd9[623]<=of6f1c2;bl7edd9[447]<=zxc70a1;bl7edd9[311]<=zmade38;bl7edd9[155]<=co15bc7;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ieac3e6 (\r
- nr61f31,\r
- qif98e,\r
- tu76293,\r
- hbe6383,\r
-\r
- gbe_mode,\r
- operational_rate,\r
-\r
- en7078f,\r
- fc83c7c,\r
- pu1e3e2,\r
- dmf1f12,\r
-\r
- cb8f893,\r
- vi7c49c,\r
- qte24e2,\r
- qv12714,\r
- hq938a4\r
-);\r
-input nr61f31;\r
-input qif98e;\r
-input tu76293;\r
-input hbe6383;\r
-input gbe_mode;\r
-input [1:0] operational_rate;\r
-input en7078f;\r
-input [7:0] fc83c7c;\r
-input pu1e3e2;\r
-input dmf1f12;\r
-input cb8f893;\r
-output [7:0] vi7c49c;\r
-output qte24e2;\r
-output qv12714;\r
-output hq938a4;\r
-parameter DYNAMIC_LT_10MBPS = 340;\r
-parameter DYNAMIC_HT_10MBPS = 680;\r
-parameter DYNAMIC_LT_100MBPS = 34;\r
-parameter DYNAMIC_HT_100MBPS = 68;\r
-parameter DYNAMIC_LT_1000MBPS = 16;\r
-parameter DYNAMIC_HT_1000MBPS = 32;\r
-localparam vxbaf41 = 2'd0, rtd7a0e = 2'd1, twbd077 = 2'd2, ale83ba = 2'd3;\r
-reg[1:0] al41dd5;\r
-localparam fceead = 3'd0, su7756a = 3'd1, tjbab51 = 3'd2, zkd5a8e = 3'd3, baad472 = 3'd4, ip6a393 = 3'd5;\r
-reg [2:0] ip51c9c;\r
-reg [7:0] xl8e4e4;\r
-reg kq72727;\r
-reg fc93939;\r
-reg [7:0] ba9c9cb;\r
-reg vie4e5a;\r
-reg fp272d2;\r
-reg [7:0] gd39696;\r
-reg ykcb4b4;\r
-reg vv5a5a1;\r
-reg bld2d0e;\r
-reg vk96877;\r
-reg anb43bb;\r
-reg ana1ddc;\r
-reg rieee4;\r
-reg kq77722;\r
-reg gdbb911;\r
-reg zkfbd26;\r
-reg [7:0] vi7c49c;\r
-reg qte24e2;\r
-reg qv12714;\r
-wire [7:0] sh4bef4;\r
-wire zx64793;\r
-wire hbf92fb;\r
-wire do1e4fd;\r
-wire mrf27ea;\r
-wire vk93f55;\r
-reg an9faab;\r
-wire vv5f7a4;\r
-reg qgeaaec;\r
-reg zx55761;\r
-reg gdabb0f;\r
-reg vi5d87d;\r
-reg blec3ea;\r
-reg jp61f57;\r
-reg ksfabe;\r
-wire hq938a4;\r
-wire [7:0] ykeaf80;\r
-reg [1:0] jr9e3e0;\r
-reg [1:0] hof1f06;\r
-reg [1:0] suf005d;\r
-reg [1:0] oh802e8;\r
-reg je1744;\r
-reg vkba22;\r
-reg rg5d112;\r
-reg yxe8893;\r
-reg fp6710;\r
-reg zz224e4;\r
-reg kf12726;\r
-reg ls93934;\r
-reg xy9c9a3;\r
-reg pse4d1a;\r
-reg ir268d2;\r
-reg [9:0] gq34695;\r
-reg [9:0] uka34a8;\r
-reg xl27f82;\r
-reg xy3fc17;\r
-reg [1:0] kf95007;\r
-reg [1:0] pua803d;\r
-reg rt401eb;\r
-reg gqf5e;\r
-reg cb7af1;\r
-reg tj3d78c;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-`endif\r
-reg [(22*8):1] zkebc66;\r
-reg [(22*8):1] sh5e333;\r
-reg byf199c;\r
-reg ls8cce3;\r
-reg zzba604;\r
-reg [1 : 0] oh338da;\r
-reg [7 : 0] hq9c6d4;\r
-reg xje36a3;\r
-reg tw1b51e;\r
-reg [1 : 0] jcda8f2;\r
-reg [2 : 0] kqd4793;\r
-reg [7 : 0] oua3c99;\r
-reg do1e4c9;\r
-reg mrf264a;\r
-reg [7 : 0] vk93255;\r
-reg vk992aa;\r
-reg enc9553;\r
-reg [7 : 0] nr4aa9c;\r
-reg hb554e6;\r
-reg tjaa737;\r
-reg qg539be;\r
-reg ls9cdf1;\r
-reg zxe6f8a;\r
-reg ph37c57;\r
-reg qvbe2be;\r
-reg faf15f5;\r
-reg oh8afaa;\r
-reg cb8fb6;\r
-reg [7 : 0] vxb023e;\r
-reg kqf551c;\r
-reg fp22c08;\r
-reg yx54707;\r
-reg wya383d;\r
-reg rv1c1e9;\r
-reg wwe0f4f;\r
-reg nt811f6;\r
-reg vx3d3c4;\r
-reg rte9e26;\r
-reg dz4f136;\r
-reg go789b7;\r
-reg cmc4db9;\r
-reg wl26dc9;\r
-reg qv36e4d;\r
-reg [7 : 0] xyb726c;\r
-reg [1 : 0] kf3c2df;\r
-reg [1 : 0] fae16fc;\r
-reg [1 : 0] lq4d8c5;\r
-reg [1 : 0] tu6c62b;\r
-reg vi6315b;\r
-reg ep18ada;\r
-reg tuc56d4;\r
-reg wy2b6a2;\r
-reg vvfc6eb;\r
-reg lqda884;\r
-reg ayd4423;\r
-reg nga2119;\r
-reg qi108ca;\r
-reg jr84650;\r
-reg wl23286;\r
-reg [9 : 0] nt19434;\r
-reg [9 : 0] rgca1a7;\r
-reg vk86d9b;\r
-reg oh36cda;\r
-reg [1 : 0] qi34ef2;\r
-reg [1 : 0] baa7791;\r
-reg ym3bc8a;\r
-reg mede450;\r
-reg gbf2280;\r
-reg bn91405;\r
-reg [(22 * 8) : 1] wl8a02f;\r
-reg [(22 * 8) : 1] fn5017d;\r
-reg [2047:0] bl7edd9;\r
-wire [68:0] nrf6ece;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-localparam zmb7676 = 69,wlbb3b3 = 32'hfdffd48b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin xl27f82 <= 1'b0; xy3fc17 <= 1'b0; end else begin xl27f82 <= zzba604; xy3fc17 <= vk86d9b; end\r
-end\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin kf95007 <= 2'b10; pua803d <= 2'b10; end else begin kf95007 <= oh338da; pua803d <= qi34ef2; end\r
-end\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin rt401eb <= 1'b0; gqf5e <= 1'b0; cb7af1 <= 1'b1; tj3d78c <= 1'b1; end else begin rt401eb <= byf199c; gqf5e <= ym3bc8a; cb7af1 <= ls8cce3; tj3d78c <= gbf2280; end\r
-end\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin jr9e3e0 <= 2'b10; hof1f06 <= 2'b10; je1744 <= 1'b1; vkba22 <= 1'b1; rg5d112 <= 1'b1; yxe8893 <= 1'b1; fp6710 <= 1'b1; end else begin if (oh36cda) begin jr9e3e0 <= 2'b10; end else if (mede450 || (!bn91405)) begin jr9e3e0 <= baa7791; end else begin jr9e3e0 <= 2'b10; end hof1f06 <= kf3c2df; je1744 <= kf3c2df != fae16fc; vkba22 <= vi6315b; rg5d112 <= ep18ada; yxe8893 <= tuc56d4; fp6710 <= vi6315b | ep18ada | tuc56d4 | wy2b6a2; end\r
-end\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin suf005d <= 2'b10; oh802e8 <= 2'b10; end else begin suf005d <= kf3c2df; oh802e8 <= lq4d8c5; end\r
-end\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin zz224e4 <= 1'b0; kf12726 <= 1'b0; ls93934 <= 1'b1; end else begin zz224e4 <= vvfc6eb; kf12726 <= lqda884; ls93934 <= ayd4423; end\r
-end\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin xy9c9a3 <= 1'b0; pse4d1a <= 1'b0; ir268d2 <= 1'b1; end else begin xy9c9a3 <= vvfc6eb; pse4d1a <= qi108ca; ir268d2 <= jr84650; end\r
-end\r
-\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin gq34695 <= 10'd16; end else begin case (fae16fc) 2'd0: begin gq34695 <= DYNAMIC_LT_10MBPS; end 2'd1: begin gq34695 <= DYNAMIC_LT_100MBPS; end 2'd2: begin gq34695 <= DYNAMIC_LT_1000MBPS; end 2'd3: begin gq34695 <= DYNAMIC_LT_1000MBPS; end default: begin gq34695 <= nt19434; end endcase end\r
-end\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin uka34a8 <= 10'd32; end else begin case (tu6c62b) 2'd0: begin uka34a8 <= DYNAMIC_HT_10MBPS; end 2'd1: begin uka34a8 <= DYNAMIC_HT_100MBPS; end 2'd2: begin uka34a8 <= DYNAMIC_HT_1000MBPS; end 2'd3: begin uka34a8 <= DYNAMIC_HT_1000MBPS; end default: begin uka34a8 <= rgca1a7; end endcase end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin xl8e4e4 <= 1'd0; kq72727 <= 1'd0; fc93939 <= 8'd0; ba9c9cb <= 1'd0; vie4e5a <= 1'd0; fp272d2 <= 8'd0; gd39696 <= 1'd0; ykcb4b4 <= 1'd0; vv5a5a1 <= 8'd0; end else begin xl8e4e4 <= hq9c6d4; kq72727 <= xje36a3; fc93939 <= tw1b51e; ba9c9cb <= oua3c99; vie4e5a <= do1e4c9; fp272d2 <= mrf264a; gd39696 <= vk93255; ykcb4b4 <= vk992aa; vv5a5a1 <= enc9553; end\r
-end\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin bld2d0e <= 1'b0; vk96877 <= 1'b0; anb43bb <= 1'b0; ana1ddc <= 1'b0; rieee4 <= 1'b0; kq77722 <= 1'b0; end else begin if ((do1e4c9 == 1'b1) && (oua3c99 == 8'hBC)) begin bld2d0e <= 1'b1; end else begin bld2d0e <= 1'b0; end\r
- if ((xje36a3 == 1'b0) && (hq9c6d4 == 8'hC5)) begin vk96877 <= 1'b1; end else begin vk96877 <= 1'b0; end if ((xje36a3 == 1'b0) && (hq9c6d4 == 8'h50)) begin anb43bb <= 1'b1; end else begin anb43bb <= 1'b0; end if ((xje36a3 == 1'b0) && (hq9c6d4 == 8'h42)) begin ana1ddc <= 1'b1; end else begin ana1ddc <= 1'b0; end if ((xje36a3 == 1'b0) && (hq9c6d4 == 8'hB5)) begin rieee4 <= 1'b1; end else begin rieee4 <= 1'b0; end if (qg539be && (ph37c57 || qvbe2be)) begin kq77722 <= 1'b1; end else begin kq77722 <= 1'b0; end end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin al41dd5 <= vxbaf41; gdbb911 <= 1'b0; end else begin if (nga2119) begin al41dd5 <= vxbaf41; gdbb911 <= 1'b0; end else begin case (jcda8f2) vxbaf41: begin if (wya383d) begin if (qg539be && (zxe6f8a || ph37c57 || qvbe2be)) begin gdbb911 <= 1'b0; al41dd5 <= rtd7a0e; end end else begin gdbb911 <= 1'b1; al41dd5 <= vxbaf41; end end rtd7a0e: begin gdbb911 <= 1'b0; if (faf15f5) begin al41dd5 <= twbd077; end else begin al41dd5 <= vxbaf41; end end twbd077: begin gdbb911 <= 1'b0; al41dd5 <= ale83ba; end ale83ba: begin gdbb911 <= 1'b0; al41dd5 <= vxbaf41; end\r
- default: begin al41dd5 <= vxbaf41; end endcase end end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin ip51c9c <= fceead; vi7c49c <= 8'd0; qte24e2 <= 1'b0; qv12714 <= 1'b0; zkfbd26 <= 1'b0; end else begin if (wl23286) begin vi7c49c <= vxb023e; qte24e2 <= kqf551c; qv12714 <= fp22c08; zkfbd26 <= 1'b0; ip51c9c <= fceead; end else begin vi7c49c <= vxb023e; qte24e2 <= kqf551c; qv12714 <= fp22c08; zkfbd26 <= 1'b0; case (kqd4793) fceead: begin qte24e2 <= 1'b1; qv12714 <= 1'b0; vi7c49c <= 8'hBC; if (yx54707) begin ip51c9c <= ip6a393; end else begin zkfbd26 <= 1'b1; ip51c9c <= su7756a; end end su7756a: begin qte24e2 <= 1'b0; qv12714 <= 1'b0; vi7c49c <= 8'h50; zkfbd26 <= 1'b1; ip51c9c <= baad472; end tjbab51: begin qte24e2 <= 1'b1; qv12714 <= 1'b0; vi7c49c <= 8'hBC; if (yx54707) begin ip51c9c <= ip6a393; end else begin zkfbd26 <= 1'b1; ip51c9c <= zkd5a8e; end end\r
- zkd5a8e: begin zkfbd26 <= 1'b1; ip51c9c <= baad472; end\r
-\r
- baad472: begin if (yx54707 && kqf551c && (vxb023e == 8'hBC)) begin qte24e2 <= 1'b1; qv12714 <= 1'b0; vi7c49c <= 8'hBC; ip51c9c <= ip6a393; end else begin zkfbd26 <= 1'b1; ip51c9c <= baad472; end end ip6a393: begin qte24e2 <= 1'b0; qv12714 <= 1'b0; vi7c49c <= 8'h50; ip51c9c <= tjbab51; end default: begin ip51c9c <= fceead; end endcase\r
- end end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin zx55761 <= 1'd0; gdabb0f <= 1'd0; vi5d87d <= 1'd0; an9faab <= 1'd0; end else begin if (nga2119) begin zx55761 <= 1'd0; gdabb0f <= 1'd0; vi5d87d <= 1'd0; an9faab <= 1'd0; end else begin an9faab <= rv1c1e9; if (wwe0f4f && oh8afaa) begin zx55761 <= 1'd1; end else begin zx55761 <= 1'd0; end gdabb0f <= rte9e26; vi5d87d <= rte9e26 | dz4f136; end end\r
-end\r
-\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin blec3ea <= 1'd0; jp61f57 <= 1'd0; ksfabe <= 1'd0; qgeaaec <= 1'd1; end else begin if (wl23286) begin blec3ea <= 1'd0; jp61f57 <= 1'd0; ksfabe <= 1'd0; qgeaaec <= 1'd1; end else begin qgeaaec <= nt811f6; if (vx3d3c4 && cb8fb6) begin blec3ea <= 1'd1; end else begin blec3ea <= 1'd0; end jp61f57 <= cmc4db9; ksfabe <= cmc4db9 | wl26dc9; end end\r
-end\r
-\r
-\r
-assign hq938a4 = go789b7 | qv36e4d;\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- xwfb762 sj8d30 ( .je99dc6(nga2119), .fndd899(en7078f), .ww62677(oh8afaa), .dob8c81(rgca1a7), .icdbb13({8'd0, tjaa737, hb554e6, nr4aa9c}),\r
- .gocee32(wl23286), .dzec4ce(cb8f893), .nt133b8(cb8fb6), .ay77190(nt19434), .gbc640b({ykeaf80, hbf92fb, zx64793, sh4bef4}),\r
- .db3205d(vv5f7a4), .cb902ef(vk93f55), .fp8177d(do1e4fd), .pubbee(mrf27ea) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- rg69299 sj8d30 ( .je99dc6(nga2119), .fndd899(en7078f), .ww62677(oh8afaa), .dob8c81(rgca1a7), .icdbb13({8'd0, tjaa737, hb554e6, nr4aa9c}),\r
- .gocee32(wl23286), .dzec4ce(cb8f893), .nt133b8(cb8fb6), .ay77190(nt19434), .gbc640b({ykeaf80, hbf92fb, zx64793, sh4bef4}),\r
- .db3205d(vv5f7a4), .cb902ef(vk93f55), .fp8177d(do1e4fd), .pubbee(mrf27ea) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- ba4f04 sj8d30 ( .je99dc6(nga2119), .fndd899(en7078f), .ww62677(oh8afaa), .dob8c81(rgca1a7), .icdbb13({8'd0, tjaa737, hb554e6, nr4aa9c}),\r
- .gocee32(wl23286), .dzec4ce(cb8f893), .nt133b8(cb8fb6), .ay77190(nt19434), .gbc640b({ykeaf80, hbf92fb, zx64793, sh4bef4}),\r
- .db3205d(vv5f7a4), .cb902ef(vk93f55), .fp8177d(do1e4fd), .pubbee(mrf27ea) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(jcda8f2) begin case (jcda8f2) vxbaf41 : zkebc66 = "SEEK_IDLE_START"; rtd7a0e : zkebc66 = "DISABLE_WRITES"; twbd077 : zkebc66 = "DISABLE_W3"; ale83ba : zkebc66 = "DISABLE_W4"; default : zkebc66 = "***ERROR***"; endcase\r
-end\r
-\r
-always @(kqd4793) begin case (kqd4793) fceead : sh5e333 = "SEEK_BEGIN_THRESH"; su7756a : sh5e333 = "DELAY_BEGIN"; tjbab51 : sh5e333 = "SEEK_START_THRESH"; zkd5a8e : sh5e333 = "DELAY"; baad472 : sh5e333 = "SEEK_STOP_THRESH"; ip6a393 : sh5e333 = "INSERT_IDLE"; default : sh5e333 = "***ERROR***"; endcase\r
-end\r
-\r
-\r
-\r
-\r
-always@* begin byf199c<=nrf6ece[0];ls8cce3<=nrf6ece[1];zzba604<=nrf6ece[2];oh338da<={operational_rate>>1,nrf6ece[3]};hq9c6d4<={fc83c7c>>1,nrf6ece[4]};xje36a3<=nrf6ece[5];tw1b51e<=nrf6ece[6];jcda8f2<={al41dd5>>1,nrf6ece[7]};kqd4793<={ip51c9c>>1,nrf6ece[8]};oua3c99<={xl8e4e4>>1,nrf6ece[9]};do1e4c9<=nrf6ece[10];mrf264a<=nrf6ece[11];vk93255<={ba9c9cb>>1,nrf6ece[12]};vk992aa<=nrf6ece[13];enc9553<=nrf6ece[14];nr4aa9c<={gd39696>>1,nrf6ece[15]};hb554e6<=nrf6ece[16];tjaa737<=nrf6ece[17];qg539be<=nrf6ece[18];ls9cdf1<=nrf6ece[19];zxe6f8a<=nrf6ece[20];ph37c57<=nrf6ece[21];qvbe2be<=nrf6ece[22];faf15f5<=nrf6ece[23];oh8afaa<=nrf6ece[24];cb8fb6<=nrf6ece[25];vxb023e<={sh4bef4>>1,nrf6ece[26]};kqf551c<=nrf6ece[27];fp22c08<=nrf6ece[28];yx54707<=nrf6ece[29];wya383d<=nrf6ece[30];rv1c1e9<=nrf6ece[31];wwe0f4f<=nrf6ece[32];nt811f6<=nrf6ece[33];vx3d3c4<=nrf6ece[34];rte9e26<=nrf6ece[35];dz4f136<=nrf6ece[36];go789b7<=nrf6ece[37];cmc4db9<=nrf6ece[38];wl26dc9<=nrf6ece[39];qv36e4d<=nrf6ece[40];xyb726c<={ykeaf80>>1,nrf6ece[41]};kf3c2df<={jr9e3e0>>1,nrf6ece[42]};fae16fc<={hof1f06>>1,nrf6ece[43]};lq4d8c5<={suf005d>>1,nrf6ece[44]};tu6c62b<={oh802e8>>1,nrf6ece[45]};vi6315b<=nrf6ece[46];ep18ada<=nrf6ece[47];tuc56d4<=nrf6ece[48];wy2b6a2<=nrf6ece[49];vvfc6eb<=nrf6ece[50];lqda884<=nrf6ece[51];ayd4423<=nrf6ece[52];nga2119<=nrf6ece[53];qi108ca<=nrf6ece[54];jr84650<=nrf6ece[55];wl23286<=nrf6ece[56];nt19434<={gq34695>>1,nrf6ece[57]};rgca1a7<={uka34a8>>1,nrf6ece[58]};vk86d9b<=nrf6ece[59];oh36cda<=nrf6ece[60];qi34ef2<={kf95007>>1,nrf6ece[61]};baa7791<={pua803d>>1,nrf6ece[62]};ym3bc8a<=nrf6ece[63];mede450<=nrf6ece[64];gbf2280<=nrf6ece[65];bn91405<=nrf6ece[66];wl8a02f<={zkebc66>>1,nrf6ece[67]};fn5017d<={sh5e333>>1,nrf6ece[68]};end\r
-always@* begin bl7edd9[2047]<=hbe6383;bl7edd9[2046]<=gbe_mode;bl7edd9[2044]<=operational_rate[0];bl7edd9[2040]<=fc83c7c[0];bl7edd9[2032]<=pu1e3e2;bl7edd9[2018]<=jr9e3e0[0];bl7edd9[2017]<=dmf1f12;bl7edd9[1989]<=hof1f06[0];bl7edd9[1987]<=al41dd5[0];bl7edd9[1931]<=suf005d[0];bl7edd9[1927]<=ip51c9c[0];bl7edd9[1865]<=ykcb4b4;bl7edd9[1859]<=vv5f7a4;bl7edd9[1844]<=ls93934;bl7edd9[1815]<=oh802e8[0];bl7edd9[1806]<=xl8e4e4[0];bl7edd9[1682]<=vv5a5a1;bl7edd9[1674]<=uka34a8[0];bl7edd9[1671]<=qgeaaec;bl7edd9[1640]<=xy9c9a3;bl7edd9[1582]<=je1744;bl7edd9[1565]<=kq72727;bl7edd9[1488]<=vk93f55;bl7edd9[1485]<=zz224e4;bl7edd9[1326]<=sh4bef4[0];bl7edd9[1317]<=bld2d0e;bl7edd9[1300]<=xl27f82;bl7edd9[1297]<=cb7af1;bl7edd9[1295]<=zx55761;bl7edd9[1233]<=pse4d1a;bl7edd9[1210]<=hbf92fb;bl7edd9[1189]<=kq77722;bl7edd9[1172]<=anb43bb;bl7edd9[1116]<=vkba22;bl7edd9[1105]<=kf95007[0];bl7edd9[1092]<=zkebc66[1];bl7edd9[1087]<=vi5d87d;bl7edd9[1082]<=fc93939;bl7edd9[1023]<=tu76293;bl7edd9[1009]<=ykeaf80[0];bl7edd9[932]<=gd39696[0];bl7edd9[929]<=an9faab;bl7edd9[922]<=kf12726;bl7edd9[837]<=gq34695[0];bl7edd9[744]<=mrf27ea;bl7edd9[742]<=fp6710;bl7edd9[663]<=zkfbd26;bl7edd9[648]<=gqf5e;bl7edd9[605]<=zx64793;bl7edd9[594]<=rieee4;bl7edd9[586]<=vk96877;bl7edd9[552]<=xy3fc17;bl7edd9[546]<=tj3d78c;bl7edd9[543]<=gdabb0f;bl7edd9[504]<=ksfabe;bl7edd9[466]<=fp272d2;bl7edd9[418]<=ir268d2;bl7edd9[372]<=do1e4fd;bl7edd9[371]<=yxe8893;bl7edd9[331]<=gdbb911;bl7edd9[324]<=rt401eb;bl7edd9[297]<=ana1ddc;bl7edd9[252]<=jp61f57;bl7edd9[233]<=vie4e5a;bl7edd9[185]<=rg5d112;bl7edd9[162]<=pua803d[0];bl7edd9[136]<=sh5e333[1];bl7edd9[126]<=blec3ea;bl7edd9[116]<=ba9c9cb[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module fadf356 (\r
- nr61f31,\r
- qif98e,\r
-\r
- en7078f,\r
- fc83c7c,\r
- pu1e3e2,\r
- dmf1f12,\r
-\r
- cb8f893,\r
- vi7c49c,\r
- qte24e2,\r
- qv12714,\r
- hq938a4\r
-);\r
-input nr61f31;\r
-input qif98e;\r
-input en7078f;\r
-input [7:0] fc83c7c;\r
-input pu1e3e2;\r
-input dmf1f12;\r
-input cb8f893;\r
-output [7:0] vi7c49c;\r
-output qte24e2;\r
-output qv12714;\r
-output hq938a4;\r
-parameter STATIC_HI_THRESH = 32;\r
-parameter STATIC_LO_THRESH = 16;\r
-localparam vxbaf41 = 2'd0, rtd7a0e = 2'd1, twbd077 = 2'd2, ale83ba = 2'd3;\r
-reg[1:0] al41dd5;\r
-localparam fceead = 3'd0, su7756a = 3'd1, tjbab51 = 3'd2, zkd5a8e = 3'd3, baad472 = 3'd4, ip6a393 = 3'd5;\r
-reg [2:0] ip51c9c;\r
-reg [7:0] xl8e4e4;\r
-reg kq72727;\r
-reg fc93939;\r
-reg [7:0] ba9c9cb;\r
-reg vie4e5a;\r
-reg fp272d2;\r
-reg [7:0] gd39696;\r
-reg ykcb4b4;\r
-reg vv5a5a1;\r
-reg bld2d0e;\r
-reg vk96877;\r
-reg anb43bb;\r
-reg ana1ddc;\r
-reg rieee4;\r
-reg kq77722;\r
-reg gdbb911;\r
-reg zkfbd26;\r
-reg [7:0] vi7c49c;\r
-reg qte24e2;\r
-reg qv12714;\r
-wire [7:0] sh4bef4;\r
-wire zx64793;\r
-wire hbf92fb;\r
-wire do1e4fd;\r
-wire mrf27ea;\r
-wire vk93f55;\r
-reg an9faab;\r
-wire vv5f7a4;\r
-reg qgeaaec;\r
-reg zx55761;\r
-reg gdabb0f;\r
-reg vi5d87d;\r
-reg blec3ea;\r
-reg jp61f57;\r
-reg ksfabe;\r
-wire hq938a4;\r
-wire [7:0] ykeaf80;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-`endif\r
-reg [(22*8):1] zkebc66;\r
-reg [(22*8):1] sh5e333;\r
-reg [7 : 0] hq9c6d4;\r
-reg xje36a3;\r
-reg tw1b51e;\r
-reg [1 : 0] jcda8f2;\r
-reg [2 : 0] kqd4793;\r
-reg [7 : 0] oua3c99;\r
-reg do1e4c9;\r
-reg mrf264a;\r
-reg [7 : 0] vk93255;\r
-reg vk992aa;\r
-reg enc9553;\r
-reg [7 : 0] nr4aa9c;\r
-reg hb554e6;\r
-reg tjaa737;\r
-reg qg539be;\r
-reg ls9cdf1;\r
-reg zxe6f8a;\r
-reg ph37c57;\r
-reg qvbe2be;\r
-reg faf15f5;\r
-reg oh8afaa;\r
-reg cb8fb6;\r
-reg [7 : 0] vxb023e;\r
-reg kqf551c;\r
-reg fp22c08;\r
-reg yx54707;\r
-reg wya383d;\r
-reg rv1c1e9;\r
-reg wwe0f4f;\r
-reg nt811f6;\r
-reg vx3d3c4;\r
-reg rte9e26;\r
-reg dz4f136;\r
-reg go789b7;\r
-reg cmc4db9;\r
-reg wl26dc9;\r
-reg qv36e4d;\r
-reg [7 : 0] xyb726c;\r
-reg [(22 * 8) : 1] wl8a02f;\r
-reg [(22 * 8) : 1] fn5017d;\r
-reg [2047:0] bl7edd9;\r
-wire [39:0] nrf6ece;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-localparam zmb7676 = 40,wlbb3b3 = 32'hfdffe44b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin xl8e4e4 <= 1'd0; kq72727 <= 1'd0; fc93939 <= 8'd0; ba9c9cb <= 1'd0; vie4e5a <= 1'd0; fp272d2 <= 8'd0; gd39696 <= 1'd0; ykcb4b4 <= 1'd0; vv5a5a1 <= 8'd0; end else begin xl8e4e4 <= hq9c6d4; kq72727 <= xje36a3; fc93939 <= tw1b51e; ba9c9cb <= oua3c99; vie4e5a <= do1e4c9; fp272d2 <= mrf264a; gd39696 <= vk93255; ykcb4b4 <= vk992aa; vv5a5a1 <= enc9553; end\r
-end\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin bld2d0e <= 1'b0; vk96877 <= 1'b0; anb43bb <= 1'b0; ana1ddc <= 1'b0; rieee4 <= 1'b0; kq77722 <= 1'b0; end else begin if ((do1e4c9 == 1'b1) && (oua3c99 == 8'hBC)) begin bld2d0e <= 1'b1; end else begin bld2d0e <= 1'b0; end\r
- if ((xje36a3 == 1'b0) && (hq9c6d4 == 8'hC5)) begin vk96877 <= 1'b1; end else begin vk96877 <= 1'b0; end if ((xje36a3 == 1'b0) && (hq9c6d4 == 8'h50)) begin anb43bb <= 1'b1; end else begin anb43bb <= 1'b0; end if ((xje36a3 == 1'b0) && (hq9c6d4 == 8'h42)) begin ana1ddc <= 1'b1; end else begin ana1ddc <= 1'b0; end if ((xje36a3 == 1'b0) && (hq9c6d4 == 8'hB5)) begin rieee4 <= 1'b1; end else begin rieee4 <= 1'b0; end if (qg539be && (ph37c57 || qvbe2be)) begin kq77722 <= 1'b1; end else begin kq77722 <= 1'b0; end end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin al41dd5 <= vxbaf41; gdbb911 <= 1'b0; end else begin case (jcda8f2) vxbaf41: begin if (wya383d) begin if (qg539be && (zxe6f8a || ph37c57 || qvbe2be)) begin gdbb911 <= 1'b0; al41dd5 <= rtd7a0e; end end else begin gdbb911 <= 1'b1; al41dd5 <= vxbaf41; end end rtd7a0e: begin gdbb911 <= 1'b0; if (faf15f5) begin al41dd5 <= twbd077; end else begin al41dd5 <= vxbaf41; end end twbd077: begin gdbb911 <= 1'b0; al41dd5 <= ale83ba; end ale83ba: begin gdbb911 <= 1'b0; al41dd5 <= vxbaf41; end\r
- default: begin al41dd5 <= vxbaf41; end endcase end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin ip51c9c <= fceead; vi7c49c <= 8'd0; qte24e2 <= 1'b0; qv12714 <= 1'b0; zkfbd26 <= 1'b0; end else begin vi7c49c <= vxb023e; qte24e2 <= kqf551c; qv12714 <= fp22c08; zkfbd26 <= 1'b0; case (kqd4793) fceead: begin qte24e2 <= 1'b1; qv12714 <= 1'b0; vi7c49c <= 8'hBC; if (yx54707) begin ip51c9c <= ip6a393; end else begin zkfbd26 <= 1'b1; ip51c9c <= su7756a; end end su7756a: begin qte24e2 <= 1'b0; qv12714 <= 1'b0; vi7c49c <= 8'h50; zkfbd26 <= 1'b1; ip51c9c <= baad472; end tjbab51: begin qte24e2 <= 1'b1; qv12714 <= 1'b0; vi7c49c <= 8'hBC; if (yx54707) begin ip51c9c <= ip6a393; end else begin zkfbd26 <= 1'b1; ip51c9c <= zkd5a8e; end end\r
- zkd5a8e: begin zkfbd26 <= 1'b1; ip51c9c <= baad472; end\r
-\r
- baad472: begin if (yx54707 && kqf551c && (vxb023e == 8'hBC)) begin qte24e2 <= 1'b1; qv12714 <= 1'b0; vi7c49c <= 8'hBC; ip51c9c <= ip6a393; end else begin zkfbd26 <= 1'b1; ip51c9c <= baad472; end end ip6a393: begin qte24e2 <= 1'b0; qv12714 <= 1'b0; vi7c49c <= 8'h50; ip51c9c <= tjbab51; end default: begin ip51c9c <= fceead; end endcase end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin zx55761 <= 1'd0; gdabb0f <= 1'd0; vi5d87d <= 1'd0; an9faab <= 1'd0; end else begin an9faab <= rv1c1e9; if (wwe0f4f && oh8afaa) begin zx55761 <= 1'd1; end else begin zx55761 <= 1'd0; end gdabb0f <= rte9e26; vi5d87d <= rte9e26 | dz4f136; end\r
-end\r
-\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin blec3ea <= 1'd0; jp61f57 <= 1'd0; ksfabe <= 1'd0; qgeaaec <= 1'd1; end else begin qgeaaec <= nt811f6; if (vx3d3c4 && cb8fb6) begin blec3ea <= 1'd1; end else begin blec3ea <= 1'd0; end jp61f57 <= cmc4db9; ksfabe <= cmc4db9 | wl26dc9; end\r
-end\r
-\r
-\r
-assign hq938a4 = go789b7 | qv36e4d;\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(18), .pmi_data_width_r(18), .pmi_data_depth_w(1024), .pmi_data_depth_r(1024), .pmi_full_flag(1024), .pmi_empty_flag(0), .pmi_almost_full_flag(STATIC_HI_THRESH), .pmi_almost_empty_flag(STATIC_LO_THRESH), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("EBR")) sj8d30 ( .Reset(~nr61f31), .RPReset(~qif98e), .WrClock(en7078f), .WrEn(gdbb911), .Data({8'd0, vv5a5a1, ykcb4b4, gd39696}),\r
- .RdClock(cb8f893), .RdEn(zkfbd26), .Q({ykeaf80, hbf92fb, zx64793, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(vk93f55), .AlmostEmpty(do1e4fd), .AlmostFull(mrf27ea) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(18), .pmi_data_width_r(18), .pmi_data_depth_w(1024), .pmi_data_depth_r(1024), .pmi_full_flag(1024), .pmi_empty_flag(0), .pmi_almost_full_flag(STATIC_HI_THRESH), .pmi_almost_empty_flag(STATIC_LO_THRESH), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("EBR")) sj8d30 ( .Reset(~nr61f31), .RPReset(~qif98e), .WrClock(en7078f), .WrEn(gdbb911), .Data({8'd0, vv5a5a1, ykcb4b4, gd39696}),\r
- .RdClock(cb8f893), .RdEn(zkfbd26), .Q({ykeaf80, hbf92fb, zx64793, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(vk93f55), .AlmostEmpty(do1e4fd), .AlmostFull(mrf27ea) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(18), .pmi_data_width_r(18), .pmi_data_depth_w(1024), .pmi_data_depth_r(1024), .pmi_full_flag(1024), .pmi_empty_flag(0), .pmi_almost_full_flag(STATIC_HI_THRESH), .pmi_almost_empty_flag(STATIC_LO_THRESH), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("EBR")) sj8d30 ( .Reset(~nr61f31), .RPReset(~qif98e), .WrClock(en7078f), .WrEn(gdbb911), .Data({8'd0, vv5a5a1, ykcb4b4, gd39696}),\r
- .RdClock(cb8f893), .RdEn(zkfbd26), .Q({ykeaf80, hbf92fb, zx64793, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(vk93f55), .AlmostEmpty(do1e4fd), .AlmostFull(mrf27ea) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(jcda8f2) begin case (jcda8f2) vxbaf41 : zkebc66 = "SEEK_IDLE_START"; rtd7a0e : zkebc66 = "DISABLE_WRITES"; twbd077 : zkebc66 = "DISABLE_W3"; ale83ba : zkebc66 = "DISABLE_W4"; default : zkebc66 = "***ERROR***"; endcase\r
-end\r
-\r
-always @(kqd4793) begin case (kqd4793) fceead : sh5e333 = "SEEK_BEGIN_THRESH"; su7756a : sh5e333 = "DELAY_BEGIN"; tjbab51 : sh5e333 = "SEEK_START_THRESH"; zkd5a8e : sh5e333 = "DELAY"; baad472 : sh5e333 = "SEEK_STOP_THRESH"; ip6a393 : sh5e333 = "INSERT_IDLE"; default : sh5e333 = "***ERROR***"; endcase\r
-end\r
-\r
-\r
-\r
-\r
-always@* begin hq9c6d4<={fc83c7c>>1,nrf6ece[0]};xje36a3<=nrf6ece[1];tw1b51e<=nrf6ece[2];jcda8f2<={al41dd5>>1,nrf6ece[3]};kqd4793<={ip51c9c>>1,nrf6ece[4]};oua3c99<={xl8e4e4>>1,nrf6ece[5]};do1e4c9<=nrf6ece[6];mrf264a<=nrf6ece[7];vk93255<={ba9c9cb>>1,nrf6ece[8]};vk992aa<=nrf6ece[9];enc9553<=nrf6ece[10];nr4aa9c<={gd39696>>1,nrf6ece[11]};hb554e6<=nrf6ece[12];tjaa737<=nrf6ece[13];qg539be<=nrf6ece[14];ls9cdf1<=nrf6ece[15];zxe6f8a<=nrf6ece[16];ph37c57<=nrf6ece[17];qvbe2be<=nrf6ece[18];faf15f5<=nrf6ece[19];oh8afaa<=nrf6ece[20];cb8fb6<=nrf6ece[21];vxb023e<={sh4bef4>>1,nrf6ece[22]};kqf551c<=nrf6ece[23];fp22c08<=nrf6ece[24];yx54707<=nrf6ece[25];wya383d<=nrf6ece[26];rv1c1e9<=nrf6ece[27];wwe0f4f<=nrf6ece[28];nt811f6<=nrf6ece[29];vx3d3c4<=nrf6ece[30];rte9e26<=nrf6ece[31];dz4f136<=nrf6ece[32];go789b7<=nrf6ece[33];cmc4db9<=nrf6ece[34];wl26dc9<=nrf6ece[35];qv36e4d<=nrf6ece[36];xyb726c<={ykeaf80>>1,nrf6ece[37]};wl8a02f<={zkebc66>>1,nrf6ece[38]};fn5017d<={sh5e333>>1,nrf6ece[39]};end\r
-always@* begin bl7edd9[2047]<=pu1e3e2;bl7edd9[2046]<=dmf1f12;bl7edd9[2044]<=al41dd5[0];bl7edd9[2040]<=ip51c9c[0];bl7edd9[2033]<=xl8e4e4[0];bl7edd9[2019]<=kq72727;bl7edd9[1991]<=fc93939;bl7edd9[1934]<=ba9c9cb[0];bl7edd9[1898]<=vk96877;bl7edd9[1821]<=vie4e5a;bl7edd9[1749]<=anb43bb;bl7edd9[1707]<=kq77722;bl7edd9[1666]<=an9faab;bl7edd9[1595]<=fp272d2;bl7edd9[1450]<=ana1ddc;bl7edd9[1440]<=mrf27ea;bl7edd9[1384]<=hbf92fb;bl7edd9[1370]<=sh4bef4[0];bl7edd9[1366]<=gdbb911;bl7edd9[1284]<=vv5f7a4;bl7edd9[1142]<=gd39696[0];bl7edd9[1125]<=ykeaf80[0];bl7edd9[1041]<=zx55761;bl7edd9[1023]<=fc83c7c[0];bl7edd9[949]<=bld2d0e;bl7edd9[853]<=rieee4;bl7edd9[833]<=vk93f55;bl7edd9[720]<=do1e4fd;bl7edd9[692]<=zx64793;bl7edd9[685]<=zkfbd26;bl7edd9[562]<=ksfabe;bl7edd9[520]<=qgeaaec;bl7edd9[474]<=vv5a5a1;bl7edd9[407]<=sh5e333[1];bl7edd9[281]<=jp61f57;bl7edd9[237]<=ykcb4b4;bl7edd9[203]<=zkebc66[1];bl7edd9[140]<=blec3ea;bl7edd9[70]<=vi5d87d;bl7edd9[35]<=gdabb0f;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module eac16a7 (\r
- nr61f31,\r
- qif98e,\r
-\r
- en7078f,\r
- fc83c7c,\r
- pu1e3e2,\r
- dmf1f12,\r
-\r
- cb8f893,\r
- vi7c49c,\r
- qte24e2,\r
- qv12714,\r
- hq938a4\r
-);\r
-input nr61f31;\r
-input qif98e;\r
-input en7078f;\r
-input [7:0] fc83c7c;\r
-input pu1e3e2;\r
-input dmf1f12;\r
-input cb8f893;\r
-output [7:0] vi7c49c;\r
-output qte24e2;\r
-output qv12714;\r
-output hq938a4;\r
-reg [7:0] xl8e4e4;\r
-reg kq72727;\r
-reg fc93939;\r
-reg gdbb911;\r
-reg zkfbd26;\r
-reg [7:0] vi7c49c;\r
-reg qte24e2;\r
-reg qv12714;\r
-wire [7:0] sh4bef4;\r
-wire zx64793;\r
-wire hbf92fb;\r
-wire do1e4fd;\r
-wire mrf27ea;\r
-wire vk93f55;\r
-wire vv5f7a4;\r
-reg zx55761;\r
-reg gdabb0f;\r
-reg vi5d87d;\r
-reg blec3ea;\r
-reg jp61f57;\r
-reg ksfabe;\r
-wire hq938a4;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-`endif\r
-reg [7 : 0] hq9c6d4;\r
-reg xje36a3;\r
-reg tw1b51e;\r
-reg [7 : 0] oua3c99;\r
-reg do1e4c9;\r
-reg mrf264a;\r
-reg oh8afaa;\r
-reg cb8fb6;\r
-reg [7 : 0] vxb023e;\r
-reg kqf551c;\r
-reg fp22c08;\r
-reg yx54707;\r
-reg wya383d;\r
-reg rv1c1e9;\r
-reg nt811f6;\r
-reg rte9e26;\r
-reg dz4f136;\r
-reg go789b7;\r
-reg cmc4db9;\r
-reg wl26dc9;\r
-reg qv36e4d;\r
-reg [2047:0] bl7edd9;\r
-wire [20:0] nrf6ece;\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-localparam zmb7676 = 21,wlbb3b3 = 32'hfdffd14b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-\r
-\r
-`endif\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin xl8e4e4 <= 1'd0; kq72727 <= 1'd0; fc93939 <= 8'd0; end else begin xl8e4e4 <= hq9c6d4; kq72727 <= xje36a3; fc93939 <= tw1b51e; end\r
-end\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin vi7c49c <= 8'd0; qte24e2 <= 1'b0; qv12714 <= 1'b0; end else begin vi7c49c <= vxb023e; qte24e2 <= kqf551c; qv12714 <= fp22c08; end\r
-end\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin gdbb911 <= 1'b0; end else begin if (rv1c1e9) begin gdbb911 <= 1'b0; end else begin gdbb911 <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin zkfbd26 <= 1'b0; end else begin if (nt811f6) begin zkfbd26 <= 1'b0; end else if (yx54707) begin zkfbd26 <= 1'b0; end else begin zkfbd26 <= 1'b1; end end\r
-end\r
-\r
-\r
-\r
-\r
-always @(posedge en7078f or negedge nr61f31)\r
-begin if (nr61f31 == 1'b0) begin zx55761 <= 1'd0; gdabb0f <= 1'd0; vi5d87d <= 1'd0; end else begin if (rv1c1e9 && oh8afaa) begin zx55761 <= 1'd1; end else begin zx55761 <= 1'd0; end gdabb0f <= rte9e26; vi5d87d <= rte9e26 | dz4f136; end\r
-end\r
-\r
-\r
-\r
-always @(posedge cb8f893 or negedge qif98e)\r
-begin if (qif98e == 1'b0) begin blec3ea <= 1'd0; jp61f57 <= 1'd0; ksfabe <= 1'd0; end else begin if (nt811f6 && cb8fb6) begin blec3ea <= 1'd1; end else begin blec3ea <= 1'd0; end jp61f57 <= cmc4db9; ksfabe <= cmc4db9 | wl26dc9; end\r
-end\r
-\r
-\r
-assign hq938a4 = go789b7 | qv36e4d;\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(16), .pmi_data_depth_r(16), .pmi_full_flag(16), .pmi_empty_flag(0), .pmi_almost_full_flag(13), .pmi_almost_empty_flag(7), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) sj8d30 ( .Reset(~nr61f31), .RPReset(~qif98e), .WrClock(en7078f), .WrEn(gdbb911), .Data({fc93939, kq72727, xl8e4e4}),\r
- .RdClock(cb8f893), .RdEn(zkfbd26), .Q({hbf92fb, zx64793, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(vk93f55), .AlmostEmpty(do1e4fd), .AlmostFull(mrf27ea) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(16), .pmi_data_depth_r(16), .pmi_full_flag(16), .pmi_empty_flag(0), .pmi_almost_full_flag(13), .pmi_almost_empty_flag(7), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) sj8d30 ( .Reset(~nr61f31), .RPReset(~qif98e), .WrClock(en7078f), .WrEn(gdbb911), .Data({fc93939, kq72727, xl8e4e4}),\r
- .RdClock(cb8f893), .RdEn(zkfbd26), .Q({hbf92fb, zx64793, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(vk93f55), .AlmostEmpty(do1e4fd), .AlmostFull(mrf27ea) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(16), .pmi_data_depth_r(16), .pmi_full_flag(16), .pmi_empty_flag(0), .pmi_almost_full_flag(13), .pmi_almost_empty_flag(7), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) sj8d30 ( .Reset(~nr61f31), .RPReset(~qif98e), .WrClock(en7078f), .WrEn(gdbb911), .Data({fc93939, kq72727, xl8e4e4}),\r
- .RdClock(cb8f893), .RdEn(zkfbd26), .Q({hbf92fb, zx64793, sh4bef4}),\r
- .Empty(vv5f7a4), .Full(vk93f55), .AlmostEmpty(do1e4fd), .AlmostFull(mrf27ea) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-always@* begin hq9c6d4<={fc83c7c>>1,nrf6ece[0]};xje36a3<=nrf6ece[1];tw1b51e<=nrf6ece[2];oua3c99<={xl8e4e4>>1,nrf6ece[3]};do1e4c9<=nrf6ece[4];mrf264a<=nrf6ece[5];oh8afaa<=nrf6ece[6];cb8fb6<=nrf6ece[7];vxb023e<={sh4bef4>>1,nrf6ece[8]};kqf551c<=nrf6ece[9];fp22c08<=nrf6ece[10];yx54707<=nrf6ece[11];wya383d<=nrf6ece[12];rv1c1e9<=nrf6ece[13];nt811f6<=nrf6ece[14];rte9e26<=nrf6ece[15];dz4f136<=nrf6ece[16];go789b7<=nrf6ece[17];cmc4db9<=nrf6ece[18];wl26dc9<=nrf6ece[19];qv36e4d<=nrf6ece[20];end\r
-always@* begin bl7edd9[2047]<=pu1e3e2;bl7edd9[2046]<=dmf1f12;bl7edd9[2044]<=xl8e4e4[0];bl7edd9[2040]<=kq72727;bl7edd9[2033]<=fc93939;bl7edd9[2019]<=gdbb911;bl7edd9[1990]<=zkfbd26;bl7edd9[1939]<=blec3ea;bl7edd9[1933]<=sh4bef4[0];bl7edd9[1831]<=jp61f57;bl7edd9[1819]<=zx64793;bl7edd9[1778]<=zx55761;bl7edd9[1615]<=ksfabe;bl7edd9[1591]<=hbf92fb;bl7edd9[1508]<=gdabb0f;bl7edd9[1135]<=do1e4fd;bl7edd9[1023]<=fc83c7c[0];bl7edd9[969]<=vi5d87d;bl7edd9[889]<=vv5f7a4;bl7edd9[444]<=vk93f55;bl7edd9[222]<=mrf27ea;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module an2c1c8 ( eaea698,\r
- rst_n,\r
- mr_main_reset,\r
- jceec52,\r
- fn45967,\r
- tx_en,\r
- tx_er,\r
- tu5dd8a,\r
- ic67f24,\r
- hq3f921,\r
- jpfc90a\r
- );\r
-parameter ksb988c = 8'hbc, kdcc461 = 8'hfe, go6230c = 8'hfb, ng11860 = 8'hfd, je8c302 = 8'hf7, bl61812 = 8'hb5, bnc096 = 8'h42, of604b6 = 8'hc5, ep25b5 = 8'h50;\r
-parameter ukf531 = 2'b00, of7a989 = 2'b01, kqd4c4c = 2'b10;\r
-parameter tuca4a0 = 4'h0, fa52503 = 4'h1, wy9281a = 4'h2, jr940d1 = 4'h3, jra068f = 4'h4, rv347f = 4'h5, ks1a3ff = 4'h6, osd1ff8 = 4'h7, sj8ffc0 = 4'h8, uv7fe04 = 4'h9, goff024 = 4'hA, enf8121 = 4'hB, jcc090c = 4'hC, zm4863 = 4'hD, wy2431b = 4'hE, ou218d9 = 4'hF;\r
-input eaea698;\r
-input rst_n;\r
-input mr_main_reset;\r
-input [1:0] jceec52;\r
-input [7:0] fn45967;\r
-input tx_en;\r
-input tx_er;\r
-input [15:0] tu5dd8a;\r
-output [7:0] ic67f24;\r
-output hq3f921;\r
-output jpfc90a;\r
-wire eaea698;\r
-wire rst_n;\r
-wire [1:0] jceec52;\r
-wire [7:0] fn45967;\r
-wire tx_en;\r
-wire tx_er;\r
-wire [15:0] tu5dd8a;\r
-reg [7:0] ic67f24;\r
-reg [7:0] sueab8f;\r
-reg [7:0] pf55c79;\r
-reg anae3ce;\r
-reg hq3f921;\r
-reg gd8f3a7;\r
-reg jpfc90a;\r
-reg [7:0] uice9eb;\r
-reg ld74f58;\r
-reg nga7ac7;\r
-reg [3:0] rt6ee96;\r
-reg [3:0] ea774b7;\r
-reg [3:0] jr2ddd2;\r
-reg jpc7792;\r
-reg ym3bc97;\r
-reg mede4b8;\r
-reg [1:0] gbf25c0;\r
-reg ym92e05;\r
-wire wy97029 = ((jceec52 != gbf25c0) && !ym3bc97) || ym92e05;\r
-reg dm484c5;\r
-reg [(20*8):1] sh7aca3;\r
-reg db94722;\r
-reg wy98a9e;\r
-reg hoc54f0;\r
-reg [7 : 0] fc2a782;\r
-reg [7 : 0] ic53c12;\r
-reg bn9e091;\r
-reg uif048e;\r
-reg [7 : 0] co82470;\r
-reg wl12381;\r
-reg fp91c0c;\r
-reg [3 : 0] ph84769;\r
-reg [3 : 0] sj23b4e;\r
-reg [3 : 0] ykf08ed;\r
-reg ntcde7;\r
-reg jc66f3f;\r
-reg rv379fb;\r
-reg [1 : 0] ecbcfde;\r
-reg ofe7ef1;\r
-reg do3f78d;\r
-reg fafbc6b;\r
-reg [(20 * 8) : 1] ohb162b;\r
-reg [2047:0] bl7edd9;\r
-wire [20:0] nrf6ece;\r
-\r
-localparam zmb7676 = 21,wlbb3b3 = 32'hfdffd48b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-function [7:0] vve653a;\r
-input [7:0] fp329d6;\r
-input ph94eb6;\r
-input zma75b6;\r
-input [7:0] je3adb2;\r
-\r
-begin if(ph94eb6 == 1'b0 && zma75b6 == 1'b1 && je3adb2 != 8'b00001111) vve653a = kdcc461; else if(ph94eb6 == 1'b1 && zma75b6 == 1'b1) vve653a = kdcc461; else vve653a = fp329d6;\r
-end\r
-endfunction\r
-function hb6b8c6;\r
-input [7:0] fp329d6;\r
-input ph94eb6;\r
-input zma75b6;\r
-input [7:0] je3adb2;\r
-\r
-begin if(ph94eb6 == 1'b0 && zma75b6 == 1'b1 && je3adb2 != 8'b00001111) hb6b8c6 = 1'b1; else if(ph94eb6 == 1'b1 && zma75b6 == 1'b1) hb6b8c6 = 1'b1; else hb6b8c6 = fp329d6;\r
-end\r
-endfunction\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin : ie34eaf\r
-if(!rst_n) begin uice9eb <= 8'd0; nga7ac7 <= 1'd0; ld74f58 <= 1'd0; end\r
-else begin uice9eb <= fn45967; nga7ac7 <= wy98a9e; ld74f58 <= hoc54f0; end\r
-end\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin : uid14d4\r
-if(!rst_n) begin gbf25c0 <= 1'd0; ym92e05 <= 1'd0; end\r
-else begin gbf25c0 <= jceec52; ym92e05 <= (jceec52 != ecbcfde) && jc66f3f; end\r
-end\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin : hq20d0f if(!rst_n) jpc7792 <= 1'b0; else begin if(ph84769 == rv347f) jpc7792 <= ~ntcde7; else jpc7792 <= ntcde7; end\r
-end\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin : fn64f87\r
-if(!rst_n) mede4b8 <= 1'd0;\r
-else mede4b8 <= jc66f3f;\r
-end\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin : ieb9205 if (!rst_n) begin rt6ee96 <= tuca4a0; ea774b7 <= tuca4a0; dm484c5 <= 1'b0; end else if (db94722) begin rt6ee96 <= tuca4a0; ea774b7 <= tuca4a0; dm484c5 <= 1'b0; end else begin ea774b7 <= ph84769; if (do3f78d) begin rt6ee96 <= tuca4a0; dm484c5 <= 1'b0; end else begin rt6ee96 <= ykf08ed; case(fafbc6b) 0: begin if (ph84769 == fa52503) begin dm484c5 <= 1'b1; end end 1: begin if ( (ph84769 != tuca4a0) && (ph84769 != fa52503) ) begin dm484c5 <= 1'b0; end end default: begin dm484c5 <= fafbc6b; end endcase\r
- end end\r
-end\r
-\r
-\r
-\r
-\r
-always @(ph84769 or jceec52 or wy98a9e or hoc54f0 or jc66f3f)\r
-begin : rtc8cce case (ph84769) tuca4a0 : jr2ddd2 = fa52503; fa52503 : begin if (jceec52 == of7a989) jr2ddd2 = wy9281a;\r
-\r
- else if (jceec52 == ukf531) jr2ddd2 = tuca4a0; else if (jceec52 == kqd4c4c) begin if (wy98a9e) begin if(hoc54f0 == 1'b0) jr2ddd2 = ks1a3ff; else jr2ddd2 = wy2431b; end else jr2ddd2 = tuca4a0; end else jr2ddd2 = tuca4a0; end wy9281a : jr2ddd2 = jr940d1; jr940d1 : jr2ddd2 = jra068f; jra068f : jr2ddd2 = rv347f; rv347f : jr2ddd2 = wy9281a; ks1a3ff : begin if (wy98a9e == 1'b1) jr2ddd2 = osd1ff8; else begin if (hoc54f0 == 1'b0) jr2ddd2 = sj8ffc0; else jr2ddd2 = enf8121; end end osd1ff8 : begin if (wy98a9e == 1'b1) jr2ddd2 = osd1ff8; else begin if (hoc54f0 == 1'b0) jr2ddd2 = sj8ffc0; else jr2ddd2 = enf8121; end end sj8ffc0 : jr2ddd2 = uv7fe04; uv7fe04 : begin if (jc66f3f == 1'b0) jr2ddd2 = tuca4a0; else jr2ddd2 = goff024; end goff024 : jr2ddd2 = tuca4a0; enf8121 : begin if (hoc54f0 == 1'b0) jr2ddd2 = jcc090c; else jr2ddd2 = zm4863; end jcc090c : jr2ddd2 = uv7fe04; zm4863 : begin if (wy98a9e == 1'b0 && hoc54f0 == 1'b0) jr2ddd2 = jcc090c; else if (wy98a9e == 1'b1 && hoc54f0 == 1'b1) jr2ddd2 = wy2431b; else if (wy98a9e == 1'b1 && hoc54f0 == 1'b0) jr2ddd2 = ks1a3ff; else jr2ddd2 = zm4863; end wy2431b : jr2ddd2 = ou218d9; ou218d9 : begin if (wy98a9e == 1'b1) jr2ddd2 = osd1ff8; else begin if (hoc54f0 == 1'b0) jr2ddd2 = sj8ffc0; else jr2ddd2 = enf8121; end end default : jr2ddd2 = tuca4a0; endcase\r
-end \r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n)\r
-begin : ir33f6c\r
-if(!rst_n) begin ic67f24 <= ksb988c; sueab8f <= ksb988c; pf55c79 <= ksb988c; hq3f921 <= 1'b1; anae3ce <= 1'b1; jpfc90a <= 1'b0; gd8f3a7 <= 1'b0; end\r
-else begin if(sj23b4e < 7) ic67f24 <= fc2a782; else ic67f24 <= ic53c12;\r
- hq3f921 <= bn9e091; jpfc90a <= uif048e; gd8f3a7 <= 1'b0;\r
- case(ph84769) tuca4a0 : begin sueab8f <= ksb988c; anae3ce <= 1'b1; end fa52503 : begin sueab8f <= ep25b5; anae3ce <= 1'b0; gd8f3a7 <= ~fafbc6b; end wy9281a : begin sueab8f <= ksb988c; anae3ce <= 1'b1; end jr940d1 : begin sueab8f <= ntcde7 ? bnc096 : bl61812; anae3ce <= 1'b0; end jra068f : begin sueab8f <= tu5dd8a[7:0]; anae3ce <= 1'b0; end rv347f : begin sueab8f <= tu5dd8a[15:8]; anae3ce <= 1'b0; end ks1a3ff : begin sueab8f <= go6230c; anae3ce <= 1'b1; end wy2431b : begin pf55c79 <= go6230c; anae3ce <= 1'b1; end osd1ff8 : begin pf55c79 <= vve653a(co82470, fp91c0c, wl12381, co82470); anae3ce <= hb6b8c6(1'b0, fp91c0c, wl12381, co82470); end sj8ffc0 : begin pf55c79 <= ng11860; anae3ce <= 1'b1; end uv7fe04, goff024, jcc090c : begin pf55c79 <= je8c302; anae3ce <= 1'b1; end enf8121 : begin pf55c79 <= vve653a(ng11860, fp91c0c, wl12381, co82470); anae3ce <= 1'b1; end zm4863 : begin pf55c79 <= vve653a(je8c302, fp91c0c, wl12381, co82470); anae3ce <= 1'b1; end ou218d9 : begin pf55c79 <= kdcc461; anae3ce <= 1'b1; end default : begin pf55c79 <= ksb988c; anae3ce <= 1'b1; end endcase\r
-end\r
-end \r
-always @(ph84769 or rv379fb)\r
-begin : su6206b case(ph84769) tuca4a0 : ym3bc97 = 1'b1; fa52503 : ym3bc97 = 1'b0; wy9281a : ym3bc97 = 1'b1; jr940d1 : ym3bc97 = 1'b0; jra068f : ym3bc97 = 1'b1; rv347f : ym3bc97 = 1'b0; ks1a3ff : ym3bc97 = ~rv379fb; wy2431b : ym3bc97 = ~rv379fb; osd1ff8 : ym3bc97 = ~rv379fb; sj8ffc0 : ym3bc97 = ~rv379fb; uv7fe04 : ym3bc97 = ~rv379fb; goff024 : ym3bc97 = ~rv379fb; jcc090c : ym3bc97 = ~rv379fb; enf8121 : ym3bc97 = ~rv379fb; zm4863 : ym3bc97 = ~rv379fb; ou218d9 : ym3bc97 = ~rv379fb; default : ym3bc97 = 1'b1; endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-always @(ph84769)\r
-begin case (ph84769) tuca4a0 : sh7aca3 = "IDLE_A"; fa52503 : sh7aca3 = "IDLE_B"; wy9281a : sh7aca3 = "CFG_A"; jr940d1 : sh7aca3 = "CFG_B"; jra068f : sh7aca3 = "CFG_C"; rv347f : sh7aca3 = "CFG_D"; ks1a3ff : sh7aca3 = "START_OF_PACKET"; osd1ff8 : sh7aca3 = "TX_DATA"; sj8ffc0 : sh7aca3 = "END_OF_PACKET_NOEXT"; uv7fe04 : sh7aca3 = "EPD2_NOEXT"; goff024 : sh7aca3 = "EPD3"; enf8121 : sh7aca3 = "END_OF_PACKET_EXT"; jcc090c : sh7aca3 = "EXTEND_BY_1"; zm4863 : sh7aca3 = "CARRIER_EXTEND"; wy2431b : sh7aca3 = "START_ERROR"; ou218d9 : sh7aca3 = "TX_DATA_ERROR"; default : sh7aca3 = " ERROR "; endcase\r
-end\r
-\r
-always@* begin db94722<=nrf6ece[0];wy98a9e<=nrf6ece[1];hoc54f0<=nrf6ece[2];fc2a782<={sueab8f>>1,nrf6ece[3]};ic53c12<={pf55c79>>1,nrf6ece[4]};bn9e091<=nrf6ece[5];uif048e<=nrf6ece[6];co82470<={uice9eb>>1,nrf6ece[7]};wl12381<=nrf6ece[8];fp91c0c<=nrf6ece[9];ph84769<={rt6ee96>>1,nrf6ece[10]};sj23b4e<={ea774b7>>1,nrf6ece[11]};ykf08ed<={jr2ddd2>>1,nrf6ece[12]};ntcde7<=nrf6ece[13];jc66f3f<=nrf6ece[14];rv379fb<=nrf6ece[15];ecbcfde<={gbf25c0>>1,nrf6ece[16]};ofe7ef1<=nrf6ece[17];do3f78d<=nrf6ece[18];fafbc6b<=nrf6ece[19];ohb162b<={sh7aca3>>1,nrf6ece[20]};end\r
-always@* begin bl7edd9[2047]<=tx_en;bl7edd9[2046]<=tx_er;bl7edd9[2044]<=sueab8f[0];bl7edd9[2040]<=pf55c79[0];bl7edd9[2032]<=anae3ce;bl7edd9[2017]<=gd8f3a7;bl7edd9[1987]<=uice9eb[0];bl7edd9[1927]<=ld74f58;bl7edd9[1865]<=gbf25c0[0];bl7edd9[1806]<=nga7ac7;bl7edd9[1682]<=ym92e05;bl7edd9[1565]<=rt6ee96[0];bl7edd9[1317]<=wy97029;bl7edd9[1172]<=sh7aca3[1];bl7edd9[1082]<=ea774b7[0];bl7edd9[1023]<=mr_main_reset;bl7edd9[932]<=mede4b8;bl7edd9[586]<=dm484c5;bl7edd9[466]<=ym3bc97;bl7edd9[233]<=jpc7792;bl7edd9[116]<=jr2ddd2[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module shd3a74 ( eaea698,\r
- rst_n,\r
- hq3f921,\r
- vv74a74,\r
- rva53a7,\r
- cb29d3f,\r
- mr4e9fc,\r
- zx74fe4,\r
- jpfc90a,\r
- hq3f93b );\r
-input eaea698;\r
-input rst_n;\r
-input hq3f921;\r
-input [7:0] vv74a74;\r
-input rva53a7;\r
-input cb29d3f;\r
-input mr4e9fc;\r
-input zx74fe4;\r
-input jpfc90a;\r
-output [9:0] hq3f93b;\r
-reg [9:0] hq3f93b;\r
-reg [7:0] blf6935;\r
-reg irb49ae;\r
-wire qva4d75;\r
-reg [9:6] qv26bac;\r
-reg [5:0] tw35d65;\r
-reg [9:6] anaeb2b;\r
-reg [5:0] al7595d;\r
-reg coacaed, mr65768, mg2bb45, rg5da29, uved14a;\r
-reg cm68a55, nr452a8, cb29546, rt4aa35, nr551ae;\r
-reg nga8d77;\r
-reg [7 : 0] ui46bba;\r
-reg fc35dd0;\r
-reg sjaee83;\r
-reg me7741d;\r
-reg xlba0e9;\r
-reg jcd074f;\r
-reg [7 : 0] hq83a7b;\r
-reg gd1d3da;\r
-reg pfe9ed5;\r
-reg [9 : 6] nr4f6ae;\r
-reg [5 : 0] ld7b577;\r
-reg [9 : 6] rgdabbf;\r
-reg [5 : 0] xwd5dfb;\r
-reg mtaefda;\r
-reg qg77ed5;\r
-reg zzbf6a8;\r
-reg zkfb547;\r
-reg zkdaa3b;\r
-reg jcd51db;\r
-reg hqa8edb;\r
-reg zk476da;\r
-reg wy3b6d3;\r
-reg aydb699;\r
-reg [2047:0] bl7edd9;\r
-wire [23:0] nrf6ece;\r
-\r
-localparam zmb7676 = 24,wlbb3b3 = 32'hfdffd30b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin if (rst_n == 1'b0) irb49ae <= 1'b0; else irb49ae <= aydb699; end\r
-\r
-\r
-assign qva4d75 = fc35dd0 ? sjaee83 : gd1d3da;\r
-\r
-\r
-\r
-always @(posedge eaea698 or negedge rst_n) begin if (rst_n == 1'b0) hq3f93b <= 10'b00_0000_0000; else hq3f93b <= {rgdabbf[9:6], xwd5dfb[5:0]}; end\r
-\r
-\r
-\r
-\r
-always @(ui46bba or me7741d or xlba0e9 or pfe9ed5 or jcd074f)\r
-begin if(jcd074f && !pfe9ed5) begin if (me7741d) blf6935 = {ui46bba[7:6], 1'b1, ui46bba[4:0]}; if (xlba0e9) blf6935 = 8'b110_00101; else blf6935 = ui46bba; end else blf6935 = ui46bba;\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always@(hq83a7b or nga8d77)\r
-begin: ene282c\r
-case (hq83a7b[3:0]) 4'b0000 : begin tw35d65[0] = hq83a7b[0]; tw35d65[1] = 1; tw35d65[2] = 1; tw35d65[3] = hq83a7b[3]; tw35d65[4] = hq83a7b[4]; tw35d65[5] = hq83a7b[4]; coacaed = hq83a7b[4]; mr65768 = !hq83a7b[4]; mg2bb45 = !hq83a7b[4]; rg5da29 = hq83a7b[4]; end 4'b1000 , 4'b0100 , 4'b0010 , 4'b0001 : begin if (hq83a7b[4] == 0) begin tw35d65[0] = hq83a7b[0]; tw35d65[1] = hq83a7b[1]; tw35d65[2] = hq83a7b[2]; tw35d65[3] = hq83a7b[3]; tw35d65[4] = 1; tw35d65[5] = 0; coacaed = hq83a7b[4]; mr65768 = !hq83a7b[4]; mg2bb45 = !hq83a7b[4]; rg5da29 = hq83a7b[4]; end else if (hq83a7b[3] == 0) begin tw35d65[0] = hq83a7b[0]; tw35d65[1] = hq83a7b[1]; tw35d65[2] = hq83a7b[2]; tw35d65[3] = hq83a7b[3]; tw35d65[4] = hq83a7b[4]; tw35d65[5] = 1; coacaed = 0; mr65768 = 0; mg2bb45 = 0; rg5da29 = 0; end else begin tw35d65[0] = hq83a7b[0]; tw35d65[1] = hq83a7b[1]; tw35d65[2] = 1; tw35d65[3] = hq83a7b[3]; tw35d65[4] = 0; tw35d65[5] = 0; coacaed = 0; mr65768 = 1; mg2bb45 = 1; rg5da29 = 0; end end 4'b1100 : begin tw35d65[0] = hq83a7b[0]; tw35d65[1] = hq83a7b[1]; tw35d65[2] = hq83a7b[2]; tw35d65[3] = hq83a7b[3]; tw35d65[4] = hq83a7b[4]; if (nga8d77 == 1 && hq83a7b[4] == 1) begin coacaed = nga8d77; mr65768 = !nga8d77; mg2bb45 = 0; rg5da29 = 1; tw35d65[5] = 1; end else begin coacaed = 0; mr65768 = 0; mg2bb45 = 0; rg5da29 = 0; if (hq83a7b[4] == 0) tw35d65[5] = 1; else tw35d65[5] = 0; end end 4'b0011 , 4'b1010 , 4'b0101 , 4'b1001 , 4'b0110 : begin tw35d65[0] = hq83a7b[0]; tw35d65[1] = hq83a7b[1]; tw35d65[2] = hq83a7b[2]; tw35d65[3] = hq83a7b[3]; tw35d65[4] = hq83a7b[4]; coacaed = 0; mr65768 = 0; mg2bb45 = 0; rg5da29 = 0; if (hq83a7b[4] == 0) tw35d65[5] = 1; else tw35d65[5] = 0; end 4'b1111: begin tw35d65[0] = hq83a7b[0]; tw35d65[1] = 0; tw35d65[2] = hq83a7b[2]; tw35d65[3] = 0; tw35d65[4] = hq83a7b[4]; tw35d65[5] = hq83a7b[4]; coacaed = hq83a7b[4]; mr65768 = !hq83a7b[4]; mg2bb45 = !hq83a7b[4]; rg5da29 = hq83a7b[4]; end 4'b0111 : begin tw35d65[0] = hq83a7b[0]; tw35d65[1] = hq83a7b[1]; tw35d65[2] = hq83a7b[2]; tw35d65[3] = hq83a7b[3]; tw35d65[4] = hq83a7b[4]; tw35d65[5] = 0; mr65768 = 0; coacaed = hq83a7b[4]; mg2bb45 = 0; rg5da29 = 1; end 4'b1101 , 4'b1011 , 4'b1110 : begin tw35d65[0] = hq83a7b[0]; tw35d65[1] = hq83a7b[1]; tw35d65[2] = hq83a7b[2]; tw35d65[3] = hq83a7b[3]; tw35d65[4] = hq83a7b[4]; tw35d65[5] = 0; mr65768 = 0; coacaed = hq83a7b[4]; mg2bb45 = 0; rg5da29 = hq83a7b[4]; end default : begin tw35d65[5:0] = 0; coacaed = 0; mr65768 = 0; mg2bb45 = 0; rg5da29 = 0; end\r
-endcase\r
-end\r
-\r
-\r
-\r
-\r
-always@(mtaefda or qg77ed5 or zzbf6a8 or zkfb547 or pfe9ed5 or ld7b577)\r
-begin: xy2aed0\r
-if ((zzbf6a8 && pfe9ed5) || (zkfb547 && !pfe9ed5) || (!zzbf6a8 && !zkfb547)) begin al7595d[5:0] = ld7b577[5:0]; if (!mtaefda && !qg77ed5) uved14a = pfe9ed5; else uved14a = mtaefda;\r
-end\r
-else begin al7595d[0] = !ld7b577[0]; al7595d[1] = !ld7b577[1]; al7595d[2] = !ld7b577[2]; al7595d[3] = !ld7b577[3]; al7595d[4] = !ld7b577[4]; al7595d[5] = !ld7b577[5]; if (!mtaefda && !qg77ed5) uved14a = pfe9ed5; else uved14a = !mtaefda;\r
-end\r
-end\r
-\r
-\r
-\r
-always@(hq83a7b or nga8d77 or xwd5dfb or zkdaa3b)\r
-begin: mec165b\r
-case (hq83a7b[7:5]) 3'b000 : begin qv26bac[6] = hq83a7b[5]; qv26bac[7] = !hq83a7b[6]; qv26bac[8] = hq83a7b[7]; qv26bac[9] = 0; cb29546 = 1; rt4aa35 = 0; cm68a55 = 0; nr452a8 = 1; end 3'b001 , 3'b010 , 3'b101 , 3'b110 : begin qv26bac[6] = hq83a7b[5]; qv26bac[7] = hq83a7b[6]; qv26bac[8] = hq83a7b[7]; qv26bac[9] = !hq83a7b[7]; if (nga8d77 == 1) cb29546 = 1; else cb29546 = 0; rt4aa35 = 0; cm68a55 = 0; nr452a8 = 0; end 3'b011 : begin qv26bac[6] = hq83a7b[5]; qv26bac[7] = hq83a7b[6]; qv26bac[8] = hq83a7b[7]; qv26bac[9] = 0; cb29546 = 0; rt4aa35 = 1; cm68a55 = 0; nr452a8 = 0; end 3'b100 : begin qv26bac[6] = hq83a7b[5]; qv26bac[7] = hq83a7b[6]; qv26bac[8] = hq83a7b[7]; qv26bac[9] = 0; cb29546 = 1; rt4aa35 = 0; cm68a55 = 0; nr452a8 = 1; end 3'b111 : begin if ((xwd5dfb[4] == 1 && xwd5dfb[5] == 1 && zkdaa3b == 0) || (xwd5dfb[4] == 0 && xwd5dfb[5] == 0 && zkdaa3b == 1) || (nga8d77 == 1)) begin qv26bac[6] = 0; qv26bac[7] = hq83a7b[6]; qv26bac[8] = hq83a7b[7]; qv26bac[9] = 1; cb29546 = 0; rt4aa35 = 1; cm68a55 = 1; nr452a8 = 0; end else begin qv26bac[6] = hq83a7b[5]; qv26bac[7] = hq83a7b[6]; qv26bac[8] = hq83a7b[7]; qv26bac[9] = 0; cb29546 = 0; rt4aa35 = 1; cm68a55 = 1; nr452a8 = 0; end end default : begin qv26bac[6] = hq83a7b[5]; qv26bac[7] = hq83a7b[6]; qv26bac[8] = hq83a7b[7]; qv26bac[9] = 0; cb29546 = 0; rt4aa35 = 0; cm68a55 = 0; nr452a8 = 0; end\r
-endcase\r
-end\r
-\r
-\r
-\r
-always@(jcd51db or hqa8edb or zk476da or wy3b6d3 or zkdaa3b or nr4f6ae)\r
-begin: ux1d29f\r
-if ((zk476da && zkdaa3b) || (wy3b6d3 && !zkdaa3b) || (!zk476da && !wy3b6d3)) begin anaeb2b[9:6] = nr4f6ae[9:6]; if (!jcd51db && !hqa8edb) nr551ae = zkdaa3b; else nr551ae = jcd51db;\r
-end\r
-else begin anaeb2b[6] = !nr4f6ae[6]; anaeb2b[7] = !nr4f6ae[7]; anaeb2b[8] = !nr4f6ae[8]; anaeb2b[9] = !nr4f6ae[9]; if (!jcd51db && !hqa8edb) nr551ae = zkdaa3b; else nr551ae = !jcd51db;\r
-end\r
-end\r
-\r
-always@* begin nga8d77<=nrf6ece[0];ui46bba<={vv74a74>>1,nrf6ece[1]};fc35dd0<=nrf6ece[2];sjaee83<=nrf6ece[3];me7741d<=nrf6ece[4];xlba0e9<=nrf6ece[5];jcd074f<=nrf6ece[6];hq83a7b<={blf6935>>1,nrf6ece[7]};gd1d3da<=nrf6ece[8];pfe9ed5<=nrf6ece[9];nr4f6ae<={qv26bac>>1,nrf6ece[10]};ld7b577<={tw35d65>>1,nrf6ece[11]};rgdabbf<={anaeb2b>>1,nrf6ece[12]};xwd5dfb<={al7595d>>1,nrf6ece[13]};mtaefda<=nrf6ece[14];qg77ed5<=nrf6ece[15];zzbf6a8<=nrf6ece[16];zkfb547<=nrf6ece[17];zkdaa3b<=nrf6ece[18];jcd51db<=nrf6ece[19];hqa8edb<=nrf6ece[20];zk476da<=nrf6ece[21];wy3b6d3<=nrf6ece[22];aydb699<=nrf6ece[23];end\r
-always@* begin bl7edd9[2047]<=vv74a74[0];bl7edd9[2046]<=rva53a7;bl7edd9[2044]<=cb29d3f;bl7edd9[2040]<=mr4e9fc;bl7edd9[2032]<=zx74fe4;bl7edd9[2016]<=jpfc90a;bl7edd9[1985]<=blf6935[0];bl7edd9[1922]<=irb49ae;bl7edd9[1796]<=qva4d75;bl7edd9[1544]<=qv26bac[6];bl7edd9[1302]<=cb29546;bl7edd9[1115]<=nr551ae;bl7edd9[1105]<=rg5da29;bl7edd9[1041]<=tw35d65[0];bl7edd9[1023]<=hq3f921;bl7edd9[651]<=nr452a8;bl7edd9[557]<=rt4aa35;bl7edd9[552]<=mg2bb45;bl7edd9[325]<=cm68a55;bl7edd9[276]<=mr65768;bl7edd9[162]<=uved14a;bl7edd9[138]<=coacaed;bl7edd9[69]<=al7595d[0];bl7edd9[34]<=anaeb2b[6];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module sgmii_gbe_pcs32 (\r
- \r
- tx_clk_125 ,\r
- serdes_recovered_clk ,\r
- rx_clk_125 ,\r
- rst_n ,\r
- gbe_mode ,\r
- sgmii_mode ,\r
- signal_detect ,\r
- debug_link_timer_short,\r
- operational_rate,\r
- rx_compensation_err,\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
- tx_clock_enable_sink ,\r
- tx_clock_enable_source ,\r
-\r
- rx_clock_enable_sink ,\r
- rx_clock_enable_source ,\r
-`else\r
- tx_clk_mii ,\r
- rx_clk_mii ,\r
-`endif\r
- \r
- \r
- \r
- rx_data ,\r
- rx_kcntl ,\r
- rx_even ,\r
- rx_disp_err ,\r
- rx_cv_err ,\r
- rx_err_decode_mode ,\r
-\r
- \r
- tx_d ,\r
- tx_en ,\r
- tx_er ,\r
-\r
- \r
- mr_adv_ability ,\r
- mr_an_enable , \r
- mr_main_reset , \r
- mr_restart_an , \r
-\r
- mr_an_complete , \r
- mr_lp_adv_ability , \r
- mr_page_rx , \r
- \r
- \r
- \r
- rx_d ,\r
- rx_dv ,\r
- rx_er ,\r
- col ,\r
- crs ,\r
- \r
- \r
- tx_data,\r
- tx_kcntl,\r
- tx_disparity_cntl\r
- ) ;\r
-input tx_clk_125 ;\r
-input serdes_recovered_clk ;\r
-input rx_clk_125 ;\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-input tx_clock_enable_sink;\r
-output tx_clock_enable_source;\r
-input rx_clock_enable_sink;\r
-output rx_clock_enable_source;\r
-\r
-`else\r
-input tx_clk_mii;\r
-input rx_clk_mii;\r
-\r
-`endif\r
-input rst_n ;\r
-input signal_detect ;\r
-input gbe_mode ;\r
-input sgmii_mode ;\r
-input debug_link_timer_short ;\r
-input [1:0] operational_rate;\r
-output rx_compensation_err;\r
-input [7:0] rx_data ;\r
-input rx_kcntl ;\r
-input rx_even ;\r
-input rx_disp_err ;\r
-input rx_cv_err ;\r
-input rx_err_decode_mode ;\r
-input [7:0] tx_d ;\r
-input tx_en ;\r
-input tx_er ;\r
-input [15:0] mr_adv_ability;\r
-input mr_an_enable;\r
-input mr_main_reset;\r
-input mr_restart_an;\r
-output mr_an_complete;\r
-output [15:0] mr_lp_adv_ability;\r
-output mr_page_rx;\r
-output [7:0] rx_d ;\r
-output rx_dv ;\r
-output rx_er ;\r
-output col ;\r
-output crs ;\r
-output [7:0] tx_data ;\r
-output tx_kcntl ;\r
-output tx_disparity_cntl ;\r
-\r
-`ifdef SGMII_YES_ENC\r
-wire [7:0] xy1e251 ;\r
-wire psf128a ;\r
-wire gd8f3a7 ;\r
-\r
-`endif\r
-wire [1:0] jceec52 ;\r
-wire [15:0] fcbbb1 ;\r
-wire [15:0] tu5dd8a ;\r
-wire [15:0] mr_adv_ability ;\r
-wire [15:0] mr_lp_adv_ability ;\r
-wire baa25a8;\r
-wire [7:0] jebda89;\r
-wire czed44b;\r
-wire qt6a25d;\r
-wire rx_compensation_err;\r
-wire ri89765;\r
-wire mr4bb2a;\r
-wire xw5d954;\r
-wire rtecaa2;\r
-wire cz65516;\r
-wire tu76293;\r
-reg xl27f82;\r
-reg xy3fc17;\r
-reg fafe0ba;\r
-reg uif05d3;\r
-reg co82e98;\r
-reg sj174c0;\r
-reg tuebfab;\r
-reg xj5fd5b;\r
-reg tufeadf;\r
-reg ykf56fa;\r
-reg kfab7d0;\r
-reg yx5be84;\r
-reg bydf425;\r
-reg uifa12a;\r
-reg lqd0951;\r
-reg vx84a8a;\r
-reg ri25457;\r
-wire [7:0] ba2a2bb;\r
-wire en515da;\r
-wire ux8aed5;\r
-wire [7:0] jc576ac;\r
-wire epbb562;\r
-wire nedab15;\r
-wire rgd58ab;\r
-wire ouac55a;\r
-reg go62ad1;\r
-reg qi15689;\r
-reg mtab449;\r
-\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-reg pf5a24c;\r
-reg cmd1266;\r
-\r
-`endif\r
-parameter DYNAMIC_LT_10MBPS = 340;\r
-parameter DYNAMIC_HT_10MBPS = 680;\r
-parameter DYNAMIC_LT_100MBPS = 34;\r
-parameter DYNAMIC_HT_100MBPS = 68;\r
-parameter DYNAMIC_LT_1000MBPS = 16;\r
-parameter DYNAMIC_HT_1000MBPS = 32;\r
-parameter STATIC_LO_THRESH = 16;\r
-parameter STATIC_HI_THRESH = 32;\r
-parameter LINK_TIMER_SH = 21'h1fff01;\r
-\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-\r
-`endif\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-\r
-`else\r
-\r
-`endif\r
-\r
-`ifdef SGMII_YES_CTC_DYNAMIC\r
-\r
-`endif\r
-\r
-`ifdef SGMII_YES_CTC_STATIC\r
-\r
-`endif\r
-\r
-`ifdef SGMII_NO_CTC\r
-\r
-`endif\r
-\r
-`ifdef SGMII_YES_ENC\r
-\r
-`else\r
-\r
-`endif\r
-reg zzba604;\r
-reg xyb28e4;\r
-reg do143f6;\r
-reg gb6afaf;\r
-reg [1 : 0] oh338da;\r
-reg [7 : 0] qi3b914;\r
-reg czdc8a0;\r
-reg hq1411f;\r
-reg kq7d70f;\r
-reg faeb878;\r
-reg me5c3c3;\r
-reg [7 : 0] jce1e19;\r
-reg wy98a9e;\r
-reg hoc54f0;\r
-reg zz1c8b9;\r
-reg db94722;\r
-reg ksa3917;\r
-reg [1 : 0] tja08fb;\r
-reg [15 : 0] mg88bdd;\r
-reg [15 : 0] dz45ee9;\r
-reg dme4504;\r
-reg [7 : 0] vv7ba7a;\r
-reg rtdd3d6;\r
-reg zxe9eb7;\r
-reg pf4f5be;\r
-reg al7adf7;\r
-reg end6fbc;\r
-reg twb7de5;\r
-reg wlbef2a;\r
-reg byf199c;\r
-reg vk86d9b;\r
-reg oh36cda;\r
-reg gqb66d4;\r
-reg ymb36a1;\r
-reg ph9b509;\r
-reg dmda84e;\r
-reg nt9729;\r
-reg gb4b94e;\r
-reg ay5ca74;\r
-reg mee53a0;\r
-reg oh29d01;\r
-reg en4e80c;\r
-reg nr74064;\r
-reg bna0326;\r
-reg do1937;\r
-reg fpc9bb;\r
-reg zx64ddf;\r
-reg [7 : 0] kf26efe;\r
-reg zz377f5;\r
-reg wlbbfaf;\r
-reg [7 : 0] xwdfd7c;\r
-reg tufebe3;\r
-reg ykf5f1a;\r
-reg phaf8d1;\r
-reg ps7c68f;\r
-reg vve347a;\r
-reg co1a3d6;\r
-reg cmd1eb0;\r
-reg [2047:0] bl7edd9;\r
-wire [57:0] nrf6ece;\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-\r
-`else\r
-\r
-`endif\r
-\r
-`ifdef SGMII_YES_ENC\r
-\r
-`endif\r
-\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-\r
-`endif\r
-\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-\r
-`endif\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-\r
-\r
-\r
-`else\r
-\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_YES_CTC_DYNAMIC\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_YES_CTC_STATIC\r
-\r
-\r
-`endif\r
-\r
-`ifdef SGMII_NO_CTC\r
-\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_YES_ENC\r
-\r
-\r
-\r
-`else\r
-\r
-\r
-`endif\r
-\r
-localparam zmb7676 = 58,wlbb3b3 = 32'hfdffca8b;\r
-localparam [31:0] czd9d9d = wlbb3b3;\r
-localparam vi76760 = wlbb3b3 & 4'hf;\r
-localparam [11:0] gq9d818 = 'h7ff;\r
-wire [(1 << vi76760) -1:0] kd60607;\r
-reg [zmb7676-1:0] yz181ef;\r
-reg [vi76760-1:0] oh7beb [0:1];\r
-reg [vi76760-1:0] qgefae7;\r
-reg ww7d739;\r
-integer xweb9c8;\r
-integer ay5ce43;\r
-\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-\r
-\r
-`else\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_YES_ENC\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-\r
-\r
-`else\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_YES_CTC_DYNAMIC\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_YES_CTC_STATIC\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_NO_CTC\r
-\r
-\r
-`endif\r
-\r
-\r
-`ifdef SGMII_YES_ENC\r
-\r
-\r
-`else\r
-\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-\r
-\r
-\r
-`else\r
-\r
-\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_YES_ENC\r
-\r
-\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-\r
-\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-assign mr4bb2a = ({hq1411f, faeb878, kq7d70f} == 3'b100) ? 1'b1 : 1'b0;\r
-assign xw5d954 = ({hq1411f, faeb878, kq7d70f} == 3'b111) ? 1'b1 : 1'b0;\r
-assign rtecaa2 = al7adf7 | end6fbc;\r
-\r
-assign cz65516 = faeb878 | kq7d70f;\r
-\r
-assign baa25a8 = (me5c3c3) ? twb7de5 : wlbef2a;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge tx_clk_125 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin go62ad1 <= 1'b0; end else begin go62ad1 <= ~vve347a; end\r
-end\r
-always @(posedge rx_clk_125 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qi15689 <= 1'b0; end else begin qi15689 <= ~co1a3d6; end\r
-end\r
-always @(posedge serdes_recovered_clk or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin mtab449 <= 1'b0; end else begin mtab449 <= ~cmd1eb0; end\r
-end\r
-\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
- always @(posedge tx_clk_mii or negedge rst_n) begin if (rst_n == 1'b0) begin pf5a24c <= 1'b0; end else begin pf5a24c <= ~pf5a24c; end end always @(posedge rx_clk_mii or negedge rst_n) begin if (rst_n == 1'b0) begin cmd1266 <= 1'b0; end else begin cmd1266 <= ~cmd1266; end end\r
-\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
- hq25f53 dz64746 ( .rst_n ( nr74064 ) , .gbe_mode ( zzba604 ) , .eaea698 ( tx_clk_125 ) , .ay534c0 ( tx_clock_enable_sink ) , .zz8b93f ( tx_clock_enable_source ) , .aa90a ( oh338da ) , .blcd797 ( jce1e19 ) , .pf6bcbe ( hoc54f0 ) , .qt5e5f7 ( wy98a9e ) ,\r
- .qi97de4 ( ba2a2bb ) , .mtbef21 ( en515da ) , .wjf790c ( ux8aed5 ) ); yx5b9d8 co8811d ( .rst_n ( do1937 ) , .gbe_mode ( zzba604 ) , .eaea698 ( rx_clk_125 ) , .ay534c0 ( rx_clock_enable_sink ) , .zz8b93f ( rx_clock_enable_source ) , .aa90a ( oh338da ) , .blcd797 ( xwdfd7c ) , .pf6bcbe ( tufebe3 ) , .qt5e5f7 ( ykf5f1a ) , .hdaff1b ( phaf8d1 ) , .en7f8df ( ps7c68f ) ,\r
- .qi97de4 ( rx_d ) , .mtbef21 ( rx_er ) , .wjf790c ( rx_dv ), .xje6cdf ( col ) , .yz366ff ( crs ) );\r
-\r
-`else\r
- oh39ef9 dz64746 ( .rst_n ( nr74064 ) , .gbe_mode ( zzba604 ) , .lqdf35e ( tx_clk_mii ) , .zxf9af2 ( oh338da ) , .blcd797 ( jce1e19 ) , .pf6bcbe ( hoc54f0 ) , .qt5e5f7 ( wy98a9e ) ,\r
- .mrf2fbc ( tx_clk_125 ) , .qi97de4 ( ba2a2bb ) , .mtbef21 ( en515da ) , .wjf790c ( ux8aed5 ) ); vx9b22c co8811d ( .rst_n ( nr74064 ) , .gbe_mode ( zzba604 ) , .lqdf35e ( rx_clk_125 ) , .blcd797 ( xwdfd7c ) , .pf6bcbe ( tufebe3 ) , .qt5e5f7 ( ykf5f1a ) , .hdaff1b ( phaf8d1 ) , .en7f8df ( ps7c68f ) ,\r
- .mrf2fbc ( rx_clk_mii ) , .pfe37e6 ( oh338da ) , .qi97de4 ( rx_d ) , .mtbef21 ( rx_er ) , .wjf790c ( rx_dv ), .xje6cdf ( col ) , .yz366ff ( crs ) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-\r
-`ifdef SGMII_YES_CTC_DYNAMIC\r
- ieac3e6 # (.DYNAMIC_HT_1000MBPS(DYNAMIC_HT_1000MBPS), .DYNAMIC_LT_1000MBPS(DYNAMIC_LT_1000MBPS), .DYNAMIC_HT_100MBPS (DYNAMIC_HT_100MBPS), .DYNAMIC_LT_100MBPS (DYNAMIC_LT_100MBPS), .DYNAMIC_HT_10MBPS (DYNAMIC_HT_10MBPS), .DYNAMIC_LT_10MBPS (DYNAMIC_LT_10MBPS)) co244ea ( .nr61f31 (zx64ddf), .qif98e (do1937), .tu76293 (byf199c), .hbe6383 (zz1c8b9), .gbe_mode (zzba604), .operational_rate (oh338da), .en7078f (serdes_recovered_clk), .fc83c7c (qi3b914), .pu1e3e2 (czdc8a0), .dmf1f12 (dme4504), .cb8f893 (rx_clk_125), .vi7c49c (jebda89), .qte24e2 (czed44b), .qv12714 (qt6a25d), .hq938a4 (rx_compensation_err) );\r
-\r
-`endif\r
-\r
-\r
-\r
-`ifdef SGMII_YES_CTC_STATIC\r
- fadf356 # (.STATIC_HI_THRESH(STATIC_HI_THRESH), .STATIC_LO_THRESH(STATIC_LO_THRESH)) co244ea ( .nr61f31 (zx64ddf), .qif98e (do1937), .en7078f (serdes_recovered_clk), .fc83c7c (qi3b914), .pu1e3e2 (czdc8a0), .dmf1f12 (dme4504), .cb8f893 (rx_clk_125), .vi7c49c (jebda89), .qte24e2 (czed44b), .qv12714 (qt6a25d), .hq938a4 (rx_compensation_err) );\r
-\r
-`endif\r
-\r
-\r
-\r
-`ifdef SGMII_NO_CTC\r
- eac16a7 co244ea ( .nr61f31 (zx64ddf), .qif98e (do1937), .en7078f (serdes_recovered_clk), .fc83c7c (qi3b914), .pu1e3e2 (czdc8a0), .dmf1f12 (dme4504), .cb8f893 (rx_clk_125), .vi7c49c (jebda89), .qte24e2 (czed44b), .qv12714 (qt6a25d), .hq938a4 (rx_compensation_err) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-\r
-\r
-fp8bd4a fp8bd4a ( .lsad934 ( rx_clk_125 ) , .rst_n ( do1937 ) , .mr_main_reset ( 1'b0 ) ,\r
- .signal_detect ( do143f6 ) , .rx_data ( vv7ba7a ) , .rx_kcntl ( rtdd3d6 ) , .baa25a8 ( zxe9eb7 ) ,\r
- .sj8a10b ( sj8a10b ) , .rx_even ( ri89765 ) );\r
-\r
-\r
-\r
-\r
-\r
-\r
-kf95b26 kf95b26 ( .lsad934 ( rx_clk_125 ) , .rst_n ( do1937 ) , .mr_main_reset ( 1'b0 ) ,\r
- .rx_data ( vv7ba7a ) , .rx_kcntl ( rtdd3d6 ) , .baa25a8 ( zxe9eb7 ) ,\r
- .sj8a10b ( sj8a10b ) , .rx_even ( pf4f5be ) , .jceec52 ( tja08fb ) ,\r
- .fcbbb1( fcbbb1 ) , .ps42af3 ( ps42af3 ) , .qi1579a ( qi1579a ) , .mtabcd1 ( mtabcd1 ) , .sh5e68d ( jc576ac ) , .dzf346c ( nedab15 ) , .cb9a367 ( epbb562 ) );\r
-\r
-\r
-\r
-\r
- hq11045 # (.LINK_TIMER_SH(LINK_TIMER_SH)) hq11045 ( .eaea698 ( tx_clk_125 ) , .rst_n ( nr74064 ) , .gbe_mode ( zzba604 ) , .sgmii_mode ( xyb28e4 ) , .mr_main_reset ( 1'b0 ) , .mr_restart_an ( ksa3917 ) , .mr_an_enable ( zz1c8b9 ) , .mr_adv_ability ( mr_adv_ability ) , .mr_lp_adv_ability ( mr_lp_adv_ability ) , .mr_page_rx ( mr_page_rx ) , .mr_an_complete ( mr_an_complete ) , .ip70450 ( gb6afaf ) ,\r
- .sj8a10b ( sj8a10b ) ,\r
- .zx5085d ( mtabcd1 ) , .db842ee ( qi1579a ) , .ym21776 ( ps42af3 ) ,\r
- .fcbbb1 ( mg88bdd ) , .tu5dd8a ( tu5dd8a ) , .jceec52 ( jceec52 ), .tu76293 ( tu76293 ) );\r
-\r
-\r
-`ifdef SGMII_YES_ENC\r
- an2c1c8 an2c1c8 ( .eaea698 ( tx_clk_125 ) , .rst_n ( nr74064 ) , .mr_main_reset ( 1'b0 ), .fn45967 ( kf26efe ) , .tx_en ( wlbbfaf ) , .tx_er ( zz377f5 ) , .jceec52 ( tja08fb ) , .tu5dd8a ( dz45ee9 ) , .ic67f24 ( xy1e251 ) , .hq3f921 ( psf128a ), .jpfc90a ( gd8f3a7 ) );\r
- shd3a74 shd3a74 ( .eaea698 (tx_clk_125), .rst_n (nr74064), .hq3f921 (psf128a), .vv74a74 (xy1e251), .rva53a7 (1'b0), .cb29d3f (1'b0), .mr4e9fc (1'b0), .zx74fe4 (1'b1), .jpfc90a (gd8f3a7), .hq3f93b ({tx_disparity_cntl, tx_kcntl, tx_data}) );\r
-\r
-`else\r
- an2c1c8 an2c1c8 ( .eaea698 ( tx_clk_125 ) , .rst_n ( nr74064 ) , .mr_main_reset ( 1'b0 ), .fn45967 ( kf26efe ) , .tx_en ( wlbbfaf ) , .tx_er ( zz377f5 ) , .jceec52 ( tja08fb ) , .tu5dd8a ( dz45ee9 ) , .ic67f24 ( tx_data ) , .hq3f921 ( tx_kcntl ), .jpfc90a ( tx_disparity_cntl ) );\r
-\r
-`endif\r
-\r
-\r
-\r
-\r
-\r
-assign rgd58ab = rx_dv & wy98a9e;\r
-assign ouac55a = rx_dv;\r
-\r
-\r
-always @(posedge tx_clk_125 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin xl27f82 <= 1'b0; xy3fc17 <= 1'b0; fafe0ba <= 1'b0; uif05d3 <= 1'b0; co82e98 <= 1'b0; sj174c0 <= 1'b0; tuebfab <= 1'b0; xj5fd5b <= 1'b0; tufeadf <= 1'b0; ykf56fa <= 1'b0; kfab7d0 <= 1'b1; yx5be84 <= 1'b1; bydf425 <= 1'b0; end else begin xl27f82 <= zzba604; xy3fc17 <= vk86d9b; kfab7d0 <= db94722; yx5be84 <= oh29d01;\r
- fafe0ba <= oh36cda; uif05d3 <= oh36cda & (~gqb66d4); co82e98 <= ~oh36cda & (gqb66d4); sj174c0 <= ymb36a1 || ph9b509; tuebfab <= dmda84e; xj5fd5b <= nt9729; tufeadf <= gb4b94e; ykf56fa <= dmda84e | nt9729 | gb4b94e | ay5ca74; bydf425 <= ~(en4e80c | mee53a0); end\r
-end\r
-\r
-\r
-always @(posedge rx_clk_125 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin uifa12a <= 1'b0; lqd0951 <= 1'b0; end else begin uifa12a <= nr74064; lqd0951 <= bna0326; end\r
-end\r
-always @(posedge serdes_recovered_clk or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vx84a8a <= 1'b0; ri25457 <= 1'b0; end else begin vx84a8a <= nr74064; ri25457 <= fpc9bb; end\r
-end\r
-\r
-\r
-\r
-always@* begin zzba604<=nrf6ece[0];xyb28e4<=nrf6ece[1];do143f6<=nrf6ece[2];gb6afaf<=nrf6ece[3];oh338da<={operational_rate>>1,nrf6ece[4]};qi3b914<={rx_data>>1,nrf6ece[5]};czdc8a0<=nrf6ece[6];hq1411f<=nrf6ece[7];kq7d70f<=nrf6ece[8];faeb878<=nrf6ece[9];me5c3c3<=nrf6ece[10];jce1e19<={tx_d>>1,nrf6ece[11]};wy98a9e<=nrf6ece[12];hoc54f0<=nrf6ece[13];zz1c8b9<=nrf6ece[14];db94722<=nrf6ece[15];ksa3917<=nrf6ece[16];tja08fb<={jceec52>>1,nrf6ece[17]};mg88bdd<={fcbbb1>>1,nrf6ece[18]};dz45ee9<={tu5dd8a>>1,nrf6ece[19]};dme4504<=nrf6ece[20];vv7ba7a<={jebda89>>1,nrf6ece[21]};rtdd3d6<=nrf6ece[22];zxe9eb7<=nrf6ece[23];pf4f5be<=nrf6ece[24];al7adf7<=nrf6ece[25];end6fbc<=nrf6ece[26];twb7de5<=nrf6ece[27];wlbef2a<=nrf6ece[28];byf199c<=nrf6ece[29];vk86d9b<=nrf6ece[30];oh36cda<=nrf6ece[31];gqb66d4<=nrf6ece[32];ymb36a1<=nrf6ece[33];ph9b509<=nrf6ece[34];dmda84e<=nrf6ece[35];nt9729<=nrf6ece[36];gb4b94e<=nrf6ece[37];ay5ca74<=nrf6ece[38];mee53a0<=nrf6ece[39];oh29d01<=nrf6ece[40];en4e80c<=nrf6ece[41];nr74064<=nrf6ece[42];bna0326<=nrf6ece[43];do1937<=nrf6ece[44];fpc9bb<=nrf6ece[45];zx64ddf<=nrf6ece[46];kf26efe<={ba2a2bb>>1,nrf6ece[47]};zz377f5<=nrf6ece[48];wlbbfaf<=nrf6ece[49];xwdfd7c<={jc576ac>>1,nrf6ece[50]};tufebe3<=nrf6ece[51];ykf5f1a<=nrf6ece[52];phaf8d1<=nrf6ece[53];ps7c68f<=nrf6ece[54];vve347a<=nrf6ece[55];co1a3d6<=nrf6ece[56];cmd1eb0<=nrf6ece[57];end\r
-always@* begin bl7edd9[2047]<=sgmii_mode;bl7edd9[2046]<=signal_detect;bl7edd9[2044]<=debug_link_timer_short;bl7edd9[2040]<=operational_rate[0];bl7edd9[2032]<=rx_data[0];bl7edd9[2017]<=rx_kcntl;bl7edd9[1987]<=rx_even;bl7edd9[1926]<=rx_disp_err;bl7edd9[1805]<=sj174c0;bl7edd9[1804]<=rx_cv_err;bl7edd9[1803]<=qt6a25d;bl7edd9[1761]<=fafe0ba;bl7edd9[1668]<=bydf425;bl7edd9[1562]<=tuebfab;bl7edd9[1560]<=rx_err_decode_mode;bl7edd9[1558]<=ri89765;bl7edd9[1550]<=mr_restart_an;bl7edd9[1475]<=uif05d3;bl7edd9[1464]<=xl27f82;bl7edd9[1288]<=uifa12a;bl7edd9[1076]<=xj5fd5b;bl7edd9[1072]<=tx_d[0];bl7edd9[1069]<=mr4bb2a;bl7edd9[1056]<=vx84a8a;bl7edd9[1052]<=jceec52[0];bl7edd9[1028]<=jc576ac[0];bl7edd9[1023]<=gbe_mode;bl7edd9[902]<=co82e98;bl7edd9[901]<=czed44b;bl7edd9[880]<=xy3fc17;bl7edd9[834]<=yx5be84;bl7edd9[775]<=mr_main_reset;bl7edd9[732]<=tu76293;bl7edd9[621]<=mtab449;bl7edd9[528]<=lqd0951;bl7edd9[514]<=ux8aed5;bl7edd9[450]<=jebda89[0];bl7edd9[417]<=kfab7d0;bl7edd9[387]<=mr_an_enable;bl7edd9[366]<=cz65516;bl7edd9[310]<=qi15689;bl7edd9[257]<=en515da;bl7edd9[225]<=baa25a8;bl7edd9[208]<=ykf56fa;bl7edd9[193]<=tx_er;bl7edd9[183]<=rtecaa2;bl7edd9[155]<=go62ad1;bl7edd9[128]<=ba2a2bb[0];bl7edd9[112]<=tu5dd8a[0];bl7edd9[104]<=tufeadf;bl7edd9[96]<=tx_en;bl7edd9[91]<=xw5d954;bl7edd9[77]<=ouac55a;bl7edd9[64]<=ri25457;bl7edd9[56]<=fcbbb1[0];bl7edd9[38]<=rgd58ab;bl7edd9[19]<=nedab15;bl7edd9[9]<=epbb562;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43<zmb7676; ay5ce43=ay5ce43+1) begin yz181ef[ay5ce43] = kd60607[qgefae7]; ww7d739 = ^(qgefae7 & oh7beb[0]); qgefae7 = {qgefae7, ww7d739}; end end \r
-endmodule\r
-\r
-\r
+++ /dev/null
-Parameters loaded ok.
-No optional files required.
-Running parameter check.
-Parameter values ok.
+++ /dev/null
-GenerateCore within package Core_Generate 1.0.0 in file LatticeIP_generate.tcl
-can't read "env(SYNPLIFY)": no such variable
-
-Total Warnings: 0
-
-
-Total Errors: 0
-
-
-
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress 12/10/2009 15:57:55 \r
-// Filename: sgmii_gbe_pcs32_inst.v \r
-// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
-\r
-//---------------------------------------------------------------\r
-// sgmii_gbe_pcs32 module instantiation template \r
-//---------------------------------------------------------------\r
- \r
-\r
- \r
-\r
-sgmii_gbe_pcs32 sgmii_gbe_pcs32_U (\r
-\r
- // Control Interface\r
- .rst_n ( rst_n ) ,\r
- .signal_detect ( signal_detect ) ,\r
- .gbe_mode ( gbe_mode ) ,\r
- .sgmii_mode ( sgmii_mode ) ,\r
- .operational_rate ( operational_rate ) ,\r
- .debug_link_timer_short ( debug_link_timer_short ) ,\r
- .rx_compensation_err ( rx_compensation_err ) ,\r
-\r
- // (G)MII Interface\r
- .tx_clock_enable_sink ( tx_clock_enable_sink ),\r
- .tx_clock_enable_source ( tx_clock_enable_source ),\r
- .tx_clk_125 ( tx_clk_125 ) ,\r
- .tx_d ( tx_d ) ,\r
- .tx_en ( tx_en ) ,\r
- .tx_er ( tx_er ) ,\r
-\r
- .rx_clock_enable_sink ( rx_clock_enable_sink ),\r
- .rx_clock_enable_source ( rx_clock_enable_source ),\r
- .rx_clk_125 ( rx_clk_125 ) ,\r
- .rx_d ( rx_d ) ,\r
- .rx_dv ( rx_dv ) ,\r
- .rx_er ( rx_er ) ,\r
- .col ( col ) ,\r
- .crs ( crs ) ,\r
- \r
- // 8BI Interface\r
- .tx_data ( tx_data ) ,\r
- .tx_kcntl ( tx_kcntl ) ,\r
- .tx_disparity_cntl ( tx_disparity_cntl ) ,\r
-\r
- .serdes_recovered_clk ( serdes_recovered_clk ) ,\r
- .rx_data ( rx_data ) ,\r
- .rx_kcntl ( rx_kcntl) ,\r
- .rx_even ( rx_even ) ,\r
- .rx_disp_err ( rx_disp_err ) ,\r
- .rx_cv_err ( rx_cv_err ) ,\r
- .rx_err_decode_mode ( rx_err_decode_mode ) ,\r
-\r
- // Management Interface\r
- .mr_adv_ability ( mr_adv_ability ),\r
- .mr_an_enable ( mr_an_enable ), \r
- .mr_main_reset ( mr_main_reset ), \r
- .mr_restart_an ( mr_restart_an ), \r
-\r
- .mr_an_complete ( mr_an_complete ), \r
- .mr_lp_adv_ability ( mr_lp_adv_ability ), \r
- .mr_page_rx ( mr_page_rx ) \r
-);\r
-\r
+++ /dev/null
-//**************************************************************************\r
-// *************************************************************************\r
-// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
-// * PROPRIETARY NOTE *\r
-// * *\r
-// * This software contains information confidential and proprietary *\r
-// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
-// * in whole or in part, or transferred to other documents, or disclosed *\r
-// * to third parties, or used for any purpose other than that for which *\r
-// * it was obtained, without the prior written consent of Lattice *\r
-// * Semiconductor Corporation. All rights reserved. *\r
-// * *\r
-// *************************************************************************\r
-//**************************************************************************\r
-\r
-`define SGMII_NO_ENC\r
-`define SGMII_YES_CTC_DYNAMIC\r
-`define SGMII_FIFO_FAMILY_ECP2M\r
-`define SGMII_YES_SINGLE_CLOCK\r
-\r
-module sgmii_gbe_pcs32 (\r
-\r
- // Control Interface\r
- rst_n,\r
- signal_detect,\r
- gbe_mode,\r
- sgmii_mode,\r
- operational_rate,\r
- debug_link_timer_short,\r
- force_isolate,\r
- force_loopback,\r
- force_unidir,\r
-\r
- rx_compensation_err,\r
- ctc_drop_flag,\r
- ctc_add_flag,\r
- an_link_ok,\r
-\r
- // G/MII Interface\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
- tx_clock_enable_sink ,\r
- tx_clock_enable_source ,\r
-\r
- rx_clock_enable_sink ,\r
- rx_clock_enable_source ,\r
-`else\r
- tx_clk_mii ,\r
- rx_clk_mii ,\r
-`endif\r
- tx_clk_125,\r
- tx_d,\r
- tx_en,\r
- tx_er,\r
-\r
- rx_clk_125,\r
- rx_d,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
-\r
- // 8-bit Interface\r
- tx_data,\r
- tx_kcntl,\r
- tx_disparity_cntl,\r
- xmit_autoneg,\r
-\r
- serdes_recovered_clk,\r
- rx_data,\r
- rx_kcntl,\r
- rx_even ,\r
- rx_disp_err ,\r
- rx_cv_err ,\r
- rx_err_decode_mode ,\r
-\r
- // Managment Control Outputs\r
- mr_an_complete,\r
- mr_page_rx,\r
- mr_lp_adv_ability,\r
-\r
- // Managment Control Inputs\r
- mr_main_reset,\r
- mr_an_enable,\r
- mr_restart_an,\r
- mr_adv_ability\r
- );\r
-\r
-\r
-\r
-// Control Interface\r
-input rst_n ;\r
-input signal_detect ;\r
-input gbe_mode ;\r
-input sgmii_mode ;\r
-input [1:0] operational_rate ;\r
-input debug_link_timer_short ;\r
-input force_isolate ;\r
-input force_loopback ;\r
-input force_unidir ;\r
-\r
-output rx_compensation_err ;\r
-output ctc_drop_flag ;\r
-output ctc_add_flag ;\r
-output an_link_ok ;\r
-\r
-// G/MII Interface\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
- input tx_clock_enable_sink;\r
- output tx_clock_enable_source;\r
-\r
- input rx_clock_enable_sink;\r
- output rx_clock_enable_source;\r
-`else\r
- input tx_clk_mii;\r
- input rx_clk_mii;\r
-`endif\r
-\r
-input tx_clk_125 ;\r
-input [7:0] tx_d ;\r
-input tx_en ;\r
-input tx_er ;\r
-\r
-input rx_clk_125 ;\r
-output [7:0] rx_d ;\r
-output rx_dv ;\r
-output rx_er ;\r
-output col ;\r
-output crs ;\r
-\r
-// 8-bit Interface\r
-output [7:0] tx_data ;\r
-output tx_kcntl;\r
-output tx_disparity_cntl;\r
-output xmit_autoneg;\r
-\r
-input serdes_recovered_clk ;\r
-input [7:0] rx_data ;\r
-input rx_even ;\r
-input rx_kcntl;\r
-input rx_disp_err ; // Displarity error on "rx_data".\r
-input rx_cv_err ; // Code error on "rx_data".\r
-input rx_err_decode_mode ;\r
-\r
-// Managment Control Outputs\r
-output mr_an_complete;\r
-output mr_page_rx;\r
-output [15:0] mr_lp_adv_ability;\r
-\r
-// Managment Control Inputs\r
-input mr_main_reset;\r
-input mr_an_enable;\r
-input mr_restart_an;\r
-input [15:0] mr_adv_ability;\r
-\r
-\r
-parameter STATIC_HI_THRESH = 32;\r
-parameter STATIC_LO_THRESH = 16;\r
-parameter LINK_TIMER_SH = 21'h1fff01;\r
-\r
- \r
-\r
-// SGMII PCS\r
-sgmii_pcs_gda_001 # (.STATIC_HI_THRESH(STATIC_HI_THRESH), .STATIC_LO_THRESH(STATIC_LO_THRESH), .LINK_TIMER_SH(LINK_TIMER_SH)) sgmii_pcs_gda_001 (\r
- // Clock and Reset\r
- .rst_n ( rst_n ) ,\r
- .signal_detect ( signal_detect ) ,\r
- .gbe_mode ( gbe_mode ) ,\r
- .sgmii_mode ( sgmii_mode ) ,\r
- .operational_rate ( operational_rate ) ,\r
- .debug_link_timer_short ( debug_link_timer_short ) ,\r
- .force_isolate ( force_isolate ) ,\r
- .force_loopback ( force_loopback ) ,\r
- .force_unidir ( force_unidir ) ,\r
-\r
- .rx_compensation_err ( rx_compensation_err ) ,\r
- .ctc_drop_flag ( ctc_drop_flag ) ,\r
- .ctc_add_flag ( ctc_add_flag ) ,\r
- .an_link_ok ( an_link_ok ) ,\r
-\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
- .tx_clock_enable_sink ( tx_clock_enable_sink ),\r
- .tx_clock_enable_source ( tx_clock_enable_source ),\r
-\r
- .rx_clock_enable_sink ( rx_clock_enable_sink ),\r
- .rx_clock_enable_source ( rx_clock_enable_source ),\r
-`else\r
- .tx_clk_mii ( tx_clk_mii ),\r
- .rx_clk_mii ( rx_clk_mii ),\r
-`endif\r
-\r
- // GMII TX Inputs\r
- .tx_clk_125 ( tx_clk_125 ) ,\r
- .tx_d ( tx_d) ,\r
- .tx_en ( tx_en) ,\r
- .tx_er ( tx_er) ,\r
-\r
- // GMII RX Outputs\r
- // To GMII/MAC interface\r
- .rx_clk_125 ( rx_clk_125 ) ,\r
- .rx_d ( rx_d ) ,\r
- .rx_dv ( rx_dv ) ,\r
- .rx_er ( rx_er ) ,\r
- .col ( col ) ,\r
- .crs ( crs ) ,\r
- \r
- // 8BI TX Outputs\r
- .tx_data ( tx_data) ,\r
- .tx_kcntl ( tx_kcntl) ,\r
- .tx_disparity_cntl ( tx_disparity_cntl) ,\r
- .xmit_autoneg ( xmit_autoneg) ,\r
-\r
- // 8BI RX Inputs\r
- .serdes_recovered_clk ( serdes_recovered_clk ) ,\r
- .rx_data ( rx_data ) ,\r
- .rx_kcntl ( rx_kcntl ) ,\r
- .rx_even ( rx_even ) ,\r
- .rx_disp_err ( rx_disp_err ) ,\r
- .rx_cv_err ( rx_cv_err ) ,\r
- .rx_err_decode_mode ( rx_err_decode_mode ) ,\r
-\r
- // Management Interface I/O\r
- .mr_adv_ability (mr_adv_ability),\r
- .mr_an_enable (mr_an_enable), \r
- .mr_main_reset (mr_main_reset), \r
- .mr_restart_an (mr_restart_an), \r
-\r
- .mr_an_complete (mr_an_complete), \r
- .mr_lp_adv_ability (mr_lp_adv_ability), \r
- .mr_page_rx (mr_page_rx)\r
- );\r
-\r
-\r
-endmodule\r
+++ /dev/null
-Running in Lattice mode\r
-\r
-\r
-Starting: /opt/synplify/syn96L3/synplify_linux/linux/mbin/synbatch\r
-Install: /opt/synplify/syn96L3/synplify_linux\r
-Date: Thu Dec 10 15:57:42 2009\r
-Version: 9.6L3\r
-\r
-\r
-Arguments: -product synplify -batch /home/greg/NewHub2/hub2/ipexpress/sgmii_gbe_pcs32/syn_results/sgmii_gbe_pcs32.prj\r
-ProductType: synplify\r
-\r
-\r
-\r
-\r
-\r
-Running synthesis on sgmii_gbe_pcs32:syn_results\r
-\r
-log file: "/home/greg/NewHub2/hub2/ipexpress/sgmii_gbe_pcs32/syn_results/sgmii_gbe_pcs32.srf"\r
-\r
-\r
-Running Verilog Compiler...\r
-\r
-Verilog Compiler Completed\r
-Return Code: 0\r
-\r
-\r
-Running lattice-ecp2m Mapper...\r
-\r
-Option not allowed with current settings and will be ignored: fixgatedclocks\r
-Option not allowed with current settings and will be ignored: fixgeneratedclocks\r
-\r
-Option not allowed with current settings and will be ignored: fixgatedclocks\r
-Option not allowed with current settings and will be ignored: fixgeneratedclocks\r
-\r
-lattice-ecp2m Mapper Completed with warnings\r
-Return Code: 1\r
-\r
-\r
-exit status=0\r
-\r
-\r
+++ /dev/null
-
-#!/usr/local/bin/wish
-
-set Para(cmd) ""
-if ![catch {set temp $argc} result] {
- if {$argc > 0} {
- for {set i 0} {$i < $argc} {incr i 2} {
- set temp [lindex $argv $i]
- set temp [string range $temp 1 end]
- lappend argv_list $temp
- lappend value_list [lindex $argv [expr $i+1]]
- }
- foreach argument $argv_list value $value_list {
- switch $argument {
- "cmd" {set Para(cmd) $value;}
- }
- }
- }
-}
-
-set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/sgmii_gbe_pcs34"
-set Para(ModuleName) "sgmii_gbe_pcs34"
-set Para(lib) "/home/greg/sgmii_gbepcs_v3.4/lib"
-set Para(CoreName) "SGMII/Gb Ethernet PCS"
-set Para(arch) "ep5m00"
-set Para(family) "latticeecp2m"
-set Para(Family) "latticeecp2m"
-set Para(design) "VHDL"
-set Para(install_dir) "/opt/lattice/diamond/1.1/bin/lin/../.."
-set Para(Bin) "/opt/lattice/diamond/1.1/bin/lin"
-set Para(SpeedGrade) "Para(spd)"
-set Para(FPGAPath) "/opt/lattice/diamond/1.1/bin/lin/../../ispfpga/bin/sol"
-
-lappend auto_path "/home/greg/sgmii_gbepcs_v3.4/gui"
-
-lappend auto_path "/home/greg/sgmii_gbepcs_v3.4/script"
-package require Core_Generate
-
-lappend auto_path "/opt/lattice/diamond/1.1/tcltk/lib/ipwidgets/ispipbuilder/../runproc"
-package require runcmd
-
-
-set Para(result) [GenerateCore]
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="sgmii_gbe_pcs34" module="SGMII/Gb Ethernet PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 10 04 13:50:40.319" version="3.4" type="IP" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="sgmii_gbe_pcs34.lpc" type="lpc" modified="2011 10 04 13:50:08.000"/>
- <File name="sgmii_gbe_pcs34.ngo" type="database" modified="2011 10 04 13:50:20.000"/>
- <File name="sgmii_gbe_pcs34_bb.v" type="black_box_verilog" modified="2011 10 04 13:50:20.000"/>
- <File name="sgmii_gbe_pcs34_beh.v" type="behavioral_verilog" modified="2011 10 04 13:50:20.000"/>
- <File name="sgmii_gbe_pcs34_inst.v" type="instantiation_verilog" modified="2011 10 04 13:50:20.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=ep5c00
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=IPCFG
-CoreStatus=Demo
-CoreName=SGMII/Gb Ethernet PCS
-CoreRevision=3.4
-ModuleName=sgmii_gbe_pcs34
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=10/04/2011
-Time=13:50:08
-
-[Parameters]
-RX_CTC=2
-RX_CTC_LOW=16
-RX_CTC_HIGH=32
-EasyConnect=1
+++ /dev/null
-//=============================================================================
-// Verilog module generated by IPExpress 10/04/2011 13:50:20
-// Filename: sgmii_gbe_pcs34_bb.v
-// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-//=============================================================================
-
-//---------------------------------------------------------------
-// sgmii_gbe_pcs34 synthesis black box definition
-//---------------------------------------------------------------
-
-/* WARNING - Changes to this file should be performed by re-running IPexpress
-or modifying the .LPC file and regenerating the core. Other changes may lead
-to inconsistent simulation and/or implemenation results */
-
-
-
- \r
-\r
-\r
-module sgmii_gbe_pcs34 (\r
- // Control Interface\r
- rst_n,\r
- signal_detect,\r
- gbe_mode,\r
- sgmii_mode,\r
- operational_rate,\r
- debug_link_timer_short,\r
- force_isolate,\r
- force_loopback,\r
- force_unidir,\r
-\r
- rx_compensation_err,\r
- ctc_drop_flag,\r
- ctc_add_flag,\r
- an_link_ok,\r
- \r
- // G/MII Interface\r
- tx_clock_enable_sink ,\r
- tx_clock_enable_source ,\r
- tx_clk_125,\r
- tx_d,\r
- tx_en,\r
- tx_er,\r
-\r
- rx_clock_enable_sink ,\r
- rx_clock_enable_source ,\r
- rx_clk_125,\r
- rx_d,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
-\r
- // 8-bit Interface\r
- tx_data,\r
- tx_kcntl,\r
- tx_disparity_cntl,\r
- xmit_autoneg,\r
-\r
- serdes_recovered_clk,\r
- rx_data,\r
- rx_kcntl,\r
- rx_even ,\r
- rx_disp_err ,\r
- rx_cv_err ,\r
- rx_err_decode_mode ,\r
- \r
- // Managment Control Outputs\r
- mr_an_complete,\r
- mr_page_rx,\r
- mr_lp_adv_ability,\r
-\r
- // Managment Control Inputs\r
- mr_main_reset,\r
- mr_an_enable,\r
- mr_restart_an,\r
- mr_adv_ability\r
- );\r
-\r
-\r
-\r
-// Control Interface\r
-input rst_n ;\r
-input signal_detect ;\r
-input gbe_mode ;\r
-input sgmii_mode ;\r
-input [1:0] operational_rate ;\r
-input debug_link_timer_short ;\r
-input force_isolate ;\r
-input force_loopback ;\r
-input force_unidir ;\r
-\r
-output rx_compensation_err ;\r
-output ctc_drop_flag ;\r
-output ctc_add_flag ;\r
-output an_link_ok ;\r
-\r
-// G/MII Interface\r
-input tx_clock_enable_sink;\r
-output tx_clock_enable_source;\r
-input tx_clk_125 ;\r
-input [7:0] tx_d ;\r
-input tx_en ;\r
-input tx_er ;\r
-\r
-input rx_clock_enable_sink;\r
-output rx_clock_enable_source;\r
-input rx_clk_125 ;\r
-output [7:0] rx_d ;\r
-output rx_dv ;\r
-output rx_er ;\r
-output col ;\r
-output crs ;\r
-\r
-// 8-bit Interface\r
-output [7:0] tx_data ;\r
-output tx_kcntl;\r
-output tx_disparity_cntl;\r
-output xmit_autoneg;\r
-\r
-input serdes_recovered_clk ;\r
-input [7:0] rx_data ;\r
-input rx_even ;\r
-input rx_kcntl;\r
-input rx_disp_err ;\r
-input rx_cv_err ;\r
-input rx_err_decode_mode ;\r
-\r
-// Managment Control Outputs\r
-output mr_an_complete;\r
-output mr_page_rx;\r
-output [15:0] mr_lp_adv_ability;\r
-\r
-// Managment Control Inputs\r
-input mr_main_reset;\r
-input mr_an_enable;\r
-input mr_restart_an;\r
-input [15:0] mr_adv_ability;\r
-\r
-\r
-\r
-endmodule\r
-\r
+++ /dev/null
-// sgmii_pcs_core_beh_pp.v generated by Lattice IP Model Creator version 1
-// created on Wed Feb 23 18:52:49 CST 2011
-// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved
-// obfuscator_exe version 1.mar0807
-
-// top
-
-
-`define SGMII_NO_ENC\r
-
-`define SGMII_YES_CTC_DYNAMIC\r
-
-`define SGMII_FIFO_FAMILY_ECP3\r
-
-`define SGMII_YES_SINGLE_CLOCK\r
-
-
-
-
-`timescale 1 ns / 100 ps
-module tjb57bb (wlabdde, uv5eef5, wjf77ad, yzbbd6d, medeb6c, icf5b61,
- puadb09, kq6d84a, xw6c250, dz61283, vx941f, th4a0fe, hb507f7,
- ri83fbf);
-input [17:0] wlabdde;
-input uv5eef5;
-input wjf77ad;
-input yzbbd6d;
-input medeb6c;
-input icf5b61;
-input puadb09;
-input [9:0] kq6d84a;
-input [9:0] xw6c250;
-output [17:0] dz61283;
-output vx941f;
-output th4a0fe;
-output hb507f7;
-output ri83fbf;
-reg [17 : 0] ng14a7f;
-reg lfa53fa;
-reg gd29fd7;
-reg th4febc;
-reg cz7f5e6;
-reg wwfaf35;
-reg zxd79a8;
-reg [9 : 0] ecbcd47;
-reg [9 : 0] pfe6a39;
-reg [2047:0] ls351cf;
-wire [8:0] jea8e7a;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-localparam ps473d2 = 9,wl39e93 = 32'hfdfff40b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-AND2 mececb4 (.A(yzbbd6d), .B(fcb2d03), .Z(ng9681a)); INV ohb40d3 (.A(jra069c), .Z(fcb2d03)); AND2 ks1a73f (.A(medeb6c), .B(ls9cfc5), .Z(yxe7e2a)); INV fc3f155 (.A(wjf8aab), .Z(ls9cfc5)); OR2 je2aaea (.A(icf5b61), .B(puadb09), .Z(zk5d4fd)); XOR2 icea7eb (.A(go53f58), .B(kf9fac1), .Z(uvfd60d)); XOR2 hoeb06c (.A(kf9fac1), .B(icc1b13), .Z(sjd899)); XOR2 xw6c4cd (.A(icc1b13), .B(tj13358), .Z(fc99ac6)); XOR2 dzcd632 (.A(tj13358), .B(jc58cb6), .Z(ipc65b2)); XOR2 tj32d95 (.A(jc58cb6), .B(ymb6573), .Z(ngb2b99)); XOR2 an95cca (.A(ymb6573), .B(xw732a4), .Z(fc99523)); XOR2 faca91b (.A(xw732a4), .B(oha46d4), .Z(ep236a5)); XOR2 xy1b52c (.A(oha46d4), .B(god4b13), .Z(hda5898)); XOR2 wl2c4c6 (.A(god4b13), .B(hd131a8), .Z(mg98d46)); XOR2 gbc6a30 (.A(hd131a8), .B(baa8c22), .Z(cm46112)); XOR2 vk30891 (.A(rv8448b), .B(jr2245e), .Z(mt122f6)); XOR2 db917b4 (.A(jr2245e), .B(gb5ed3e), .Z(pff69f5)); XOR2 qvb4fae (.A(gb5ed3e), .B(co3ebab), .Z(suf5d58)); XOR2 sjaeac1 (.A(co3ebab), .B(irab06c), .Z(ho58364)); XOR2 uic1b23 (.A(irab06c), .B(lq6c8cd), .Z(hb6466a)); XOR2 an23357 (.A(lq6c8cd), .B(ldcd5e6), .Z(qt6af36)); XOR2 xw579b5 (.A(ldcd5e6), .B(rte6d59), .Z(cb36acf)); XOR2 rvb567c (.A(rte6d59), .B(qg59f34), .Z(lqcf9a0)); XOR2 ps7cd02 (.A(qg59f34), .B(mg3409f), .Z(tja04f8)); XOR2 sj27c7 (.A(mg3409f), .B(an9f1ef), .Z(off8f7c)); defparam rtc7be5.initval = 16'h6996 ; ROM16X1 rtc7be5 (.AD3(ayef977), .AD2(zk7cbb9), .AD1(yke5dcb), .AD0(aa2ee58), .DO0(yk772c1)) ; defparam mgb9609.initval = 16'h6996 ; ROM16X1 mgb9609 (.AD3(ne58241), .AD2(qgc120b), .AD1(bn9058), .AD0(ne482c6), .DO0(gb41632)) ; defparam xyb194.initval = 16'h6996 ; ROM16X1 xyb194 (.AD3(yke5dcb), .AD2(aa2ee58), .AD1(hd946ae), .AD0(hd946ae), .DO0(ou1abb8)) ; defparam zkd5dc1.initval = 16'h6996 ; ROM16X1 zkd5dc1 (.AD3(zk7cbb9), .AD2(yke5dcb), .AD1(aa2ee58), .AD0(hd946ae), .DO0(vv55280)) ; defparam yma9407.initval = 16'h6996 ; ROM16X1 yma9407 (.AD3(ne482c6), .AD2(ayef977), .AD1(zk7cbb9), .AD0(ou1abb8), .DO0(xwcff6d)) ; defparam ip7fb6a.initval = 16'h6996 ; ROM16X1 ip7fb6a (.AD3(bn9058), .AD2(ne482c6), .AD1(ayef977), .AD0(vv55280), .DO0(nta586c)) ; defparam sj2c366.initval = 16'h6996 ; ROM16X1 sj2c366 (.AD3(qgc120b), .AD2(bn9058), .AD1(ne482c6), .AD0(yk772c1), .DO0(wlaea9b)) ; defparam uv754dd.initval = 16'h6996 ; ROM16X1 uv754dd (.AD3(yk772c1), .AD2(gb41632), .AD1(hd946ae), .AD0(hd946ae), .DO0(dm661f6)) ; defparam pu30fb2.initval = 16'h6996 ; ROM16X1 pu30fb2 (.AD3(yk772c1), .AD2(gb41632), .AD1(dob2607), .AD0(hd946ae), .DO0(qi981da)) ; defparam psc0ed1.initval = 16'h6996 ; ROM16X1 psc0ed1 (.AD3(yk772c1), .AD2(gb41632), .AD1(sud174a), .AD0(dob2607), .DO0(dm5d28e)) ; defparam rte9473.initval = 16'h6996 ; ROM16X1 rte9473 (.AD3(of51cff), .AD2(sud174a), .AD1(dob2607), .AD0(hd946ae), .DO0(ykff9d5)) ; defparam pffcea8.initval = 16'h6996 ; ROM16X1 pffcea8 (.AD3(yk772c1), .AD2(gb41632), .AD1(ykff9d5), .AD0(hd946ae), .DO0(ep3c4d2)) ; defparam kde2694.initval = 16'h6996 ; ROM16X1 kde2694 (.AD3(wl9a526), .AD2(jpd2934), .AD1(jr949a7), .AD0(epa4d3e), .DO0(yz269f4)) ; defparam ec34fa5.initval = 16'h6996 ; ROM16X1 ec34fa5 (.AD3(ou3e94b), .AD2(lqf4a58), .AD1(pha52c3), .AD0(mt2961f), .DO0(sh4b0fd)) ; defparam xw587ed.initval = 16'h6996 ; ROM16X1 xw587ed (.AD3(jr949a7), .AD2(epa4d3e), .AD1(hd946ae), .AD0(hd946ae), .DO0(os5c36f)) ; defparam zke1b79.initval = 16'h6996 ; ROM16X1 zke1b79 (.AD3(jpd2934), .AD2(jr949a7), .AD1(epa4d3e), .AD0(hd946ae), .DO0(nr55112)) ; defparam nga8897.initval = 16'h6996 ; ROM16X1 nga8897 (.AD3(mt2961f), .AD2(wl9a526), .AD1(jpd2934), .AD0(os5c36f), .DO0(wwd4d46)) ; defparam coa6a30.initval = 16'h6996 ; ROM16X1 coa6a30 (.AD3(pha52c3), .AD2(mt2961f), .AD1(wl9a526), .AD0(nr55112), .DO0(iea456)) ; defparam vi522b1.initval = 16'h6996 ; ROM16X1 vi522b1 (.AD3(lqf4a58), .AD2(pha52c3), .AD1(mt2961f), .AD0(yz269f4), .DO0(fa57824)) ; defparam aabc123.initval = 16'h6996 ; ROM16X1 aabc123 (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(hd946ae), .AD0(hd946ae), .DO0(xwc0665)) ; defparam fp332a.initval = 16'h6996 ; ROM16X1 fp332a (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(xy2afad), .AD0(hd946ae), .DO0(wlbeb5b)) ; defparam wwf5adc.initval = 16'h6996 ; ROM16X1 wwf5adc (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(wjdc2f5), .AD0(xy2afad), .DO0(fcbd6b)) ; defparam uv5eb5a.initval = 16'h6996 ; ROM16X1 uv5eb5a (.AD3(hqad6a9), .AD2(wjdc2f5), .AD1(xy2afad), .AD0(hd946ae), .DO0(uka97bb)) ; defparam en4bdd9.initval = 16'h6996 ; ROM16X1 en4bdd9 (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(uka97bb), .AD0(hd946ae), .DO0(of65b65)) ; XOR2 bn2db2c (.A(baa8c22), .B(epa4d3e), .Z(gb65982)); XOR2 oh2cc14 (.A(aa2ee58), .B(an9f1ef), .Z(ou82912)); defparam je14890.initval = 16'h0410 ; ROM16X1 je14890 (.AD3(db22415), .AD2(an9f1ef), .AD1(aa2ee58), .AD0(hd946ae), .DO0(ks15d28)) ; defparam mtae940.initval = 16'h1004 ; ROM16X1 mtae940 (.AD3(db22415), .AD2(an9f1ef), .AD1(aa2ee58), .AD0(hd946ae), .DO0(je2fff9)) ; defparam uv7ffcb.initval = 16'h0140 ; ROM16X1 uv7ffcb (.AD3(ykff2e0), .AD2(baa8c22), .AD1(epa4d3e), .AD0(hd946ae), .DO0(yke0381)) ; defparam fc1c09.initval = 16'h4001 ; ROM16X1 fc1c09 (.AD3(ykff2e0), .AD2(baa8c22), .AD1(epa4d3e), .AD0(hd946ae), .DO0(of5b9b5)) ; INV aldcdad (.A(pfe6d6c), .Z(mt36b67)); AND2 tjb5b3c (.A(zmad9e7), .B(mt36b67), .Z(ui679d2)); AND2 an3ce91 (.A(zmad9e7), .B(pfe6d6c), .Z(hbd2363)); defparam ph91b1e.CSDECODE_R = 3'b000 ; defparam ph91b1e.CSDECODE_W = 3'b000 ; defparam ph91b1e.GSR = "ENABLED" ; defparam ph91b1e.RESETMODE = "ASYNC" ; defparam ph91b1e.REGMODE = "NOREG" ; defparam ph91b1e.DATA_WIDTH_R = 18 ; defparam ph91b1e.DATA_WIDTH_W = 18 ; PDP16KA ph91b1e (.DI0(wlabdde[0]), .DI1(wlabdde[1]), .DI2(wlabdde[2]), .DI3(wlabdde[3]), .DI4(wlabdde[4]), .DI5(wlabdde[5]), .DI6(wlabdde[6]), .DI7(wlabdde[7]), .DI8(wlabdde[8]), .DI9(wlabdde[9]), .DI10(wlabdde[10]), .DI11(wlabdde[11]), .DI12(wlabdde[12]), .DI13(wlabdde[13]), .DI14(wlabdde[14]), .DI15(wlabdde[15]), .DI16(wlabdde[16]), .DI17(wlabdde[17]), .DI18(wlabdde[0]), .DI19(wlabdde[1]), .DI20(wlabdde[2]), .DI21(wlabdde[3]), .DI22(wlabdde[4]), .DI23(wlabdde[5]), .DI24(wlabdde[6]), .DI25(wlabdde[7]), .DI26(wlabdde[8]), .DI27(wlabdde[9]), .DI28(wlabdde[10]), .DI29(wlabdde[11]), .DI30(wlabdde[12]), .DI31(wlabdde[13]), .DI32(wlabdde[14]), .DI33(wlabdde[15]), .DI34(wlabdde[16]), .DI35(wlabdde[17]), .ADW0(ba1ecef), .ADW1(ba1ecef), .ADW2(hd946ae), .ADW3(hd946ae), .ADW4(meef7c0), .ADW5(pf7be00), .ADW6(tudf006), .ADW7(kdf8032), .ADW8(fac0194), .ADW9(ouca2), .ADW10(ph6511), .ADW11(xl3288f), .ADW12(db9447e), .ADW13(lsa23f7), .CEW(ng9681a), .CLKW(uv5eef5), .WE(ba1ecef), .CSW0(hd946ae), .CSW1(hd946ae), .CSW2(hd946ae), .ADR0(hd946ae), .ADR1(hd946ae), .ADR2(hd946ae), .ADR3(hd946ae), .ADR4(al7fc5f), .ADR5(dmfe2fc), .ADR6(faf17e3), .ADR7(ph8bf1a), .ADR8(xj5f8d6), .ADR9(vvfc6b7), .ADR10(rte35be), .ADR11(wy1adf6), .ADR12(mrd6fb1), .ADR13(fcb7d8d), .CER(yxe7e2a), .CLKR(wjf77ad), .CSR0(hd946ae), .CSR1(hd946ae), .CSR2(hd946ae), .RST(icf5b61), .DO0(dz61283[0]), .DO1(dz61283[1]), .DO2(dz61283[2]), .DO3(dz61283[3]), .DO4(dz61283[4]), .DO5(dz61283[5]), .DO6(
-dz61283[6]), .DO7(dz61283[7]), .DO8(dz61283[8]), .DO9(dz61283[9]), .DO10(dz61283[10]), .DO11(dz61283[11]), .DO12(dz61283[12]), .DO13(dz61283[13]), .DO14(dz61283[14]), .DO15(dz61283[15]), .DO16(dz61283[16]), .DO17(dz61283[17]), .DO18(), .DO19(), .DO20(), .DO21(), .DO22(), .DO23(), .DO24(), .DO25(), .DO26(), .DO27(), .DO28(), .DO29(), .DO30(), .DO31(), .DO32(), .DO33(), .DO34(), .DO35()) ; defparam hq113f.GSR = "ENABLED" ; FD1P3BX hq113f (.D(gb44fd5), .SP(ng9681a), .CK(uv5eef5), .PD(icf5b61), .Q(go53f58)) ; defparam fcadec2.GSR = "ENABLED" ; FD1P3DX fcadec2 (.D(zx7b094), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(kf9fac1)) ; defparam lsa7fee.GSR = "ENABLED" ; FD1P3DX lsa7fee (.D(qgffb9a), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(icc1b13)) ; defparam jcd0a9c.GSR = "ENABLED" ; FD1P3DX jcd0a9c (.D(hq2a714), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tj13358)) ; defparam fca22eb.GSR = "ENABLED" ; FD1P3DX fca22eb (.D(db8bad3), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(jc58cb6)) ; defparam xl9e6b5.GSR = "ENABLED" ; FD1P3DX xl9e6b5 (.D(kf9ad77), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ymb6573)) ; defparam jebdbe8.GSR = "ENABLED" ; FD1P3DX jebdbe8 (.D(mr6fa1c), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(xw732a4)) ; defparam wwe5146.GSR = "ENABLED" ; FD1P3DX wwe5146 (.D(dz4518e), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(oha46d4)) ; defparam zk76c4e.GSR = "ENABLED" ; FD1P3DX zk76c4e (.D(cbb1391), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(god4b13)) ; defparam pu8c74e.GSR = "ENABLED" ; FD1P3DX pu8c74e (.D(ir1d393), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(hd131a8)) ; defparam aa9dd4b.GSR = "ENABLED" ; FD1P3DX aa9dd4b (.D(al752c3), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(baa8c22)) ; defparam tj1c35c.GSR = "ENABLED" ; FD1P3DX tj1c35c (.D(uvfd60d), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(pu3a9c4)) ; defparam sud4e22.GSR = "ENABLED" ; FD1P3DX sud4e22 (.D(sjd899), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(gq82e31)) ; defparam yz17188.GSR = "ENABLED" ; FD1P3DX yz17188 (.D(fc99ac6), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ep23a0c)) ; defparam cb1d065.GSR = "ENABLED" ; FD1P3DX cb1d065 (.D(ipc65b2), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(os6dbe6)) ; defparam cm6df30.GSR = "ENABLED" ; FD1P3DX cm6df30 (.D(ngb2b99), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ks5795)) ; defparam co2bca8.GSR = "ENABLED" ; FD1P3DX co2bca8 (.D(fc99523), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tjc95d)) ; defparam hb64aef.GSR = "ENABLED" ; FD1P3DX hb64aef (.D(ep236a5), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(thf328f)) ; defparam zm9947f.GSR = "ENABLED" ; FD1P3DX zm9947f (.D(hda5898), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(godb92b)) ; defparam ofdc959.GSR = "ENABLED" ; FD1P3DX ofdc959 (.D(mg98d46), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ea62604)) ; defparam zz13020.GSR = "ENABLED" ; FD1P3DX zz13020 (.D(cm46112), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(co31697)) ; defparam rv8b4b8.GSR = "ENABLED" ; FD1P3DX rv8b4b8 (.D(baa8c22), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ou3ee1e)) ; defparam mrf70f0.GSR = "ENABLED" ; FD1P3DX mrf70f0 (.D(go53f58), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(meef7c0)) ; defparam yx54463.GSR = "ENABLED" ; FD1P3DX yx54463 (.D(kf9fac1), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(pf7be00)) ; defparam by524e8.GSR = "ENABLED" ; FD1P3DX by524e8 (.D(icc1b13), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tudf006)) ; defparam je83359.GSR = "ENABLED" ; FD1P3DX je83359 (.D(tj13358), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(kdf8032)) ; defparam rtf6c45.GSR = "ENABLED" ; FD1P3DX rtf6c45 (.D(jc58cb6), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(fac0194)) ; defparam ri8c3c7.GSR = "ENABLED" ; FD1P3DX ri8c3c7 (.D(ymb6573), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ouca2)) ; defparam kfb13d4.GSR = "ENABLED" ; FD1P3DX kfb13d4 (.D(xw732a4), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ph6511)) ; defparam uk1f82d.GSR = "ENABLED" ; FD1P3DX uk1f82d (.D(oha46d4), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(xl3288f)) ; defparam kd703d5.GSR = "ENABLED" ; FD1P3DX kd703d5 (.D(god4b13), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(db9447e)) ; defparam qv39880.GSR = "ENABLED" ; FD1P3DX qv39880 (.D(hd131a8), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(lsa23f7)) ; defparam al6034d.GSR = "ENABLED" ; FD1P3DX al6034d (.D(baa8c22), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ykff2e0)) ; defparam su5c4cf.GSR = "ENABLED" ; FD1P3BX su5c4cf (.D(ph133cc), .SP(yxe7e2a), .CK(wjf77ad), .PD(zk5d4fd), .Q(rv8448b)) ; defparam lq664dd.GSR = "ENABLED" ; FD1P3DX lq664dd (.D(ba93757), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(jr2245e)) ; defparam xlbafca.GSR = "ENABLED" ; FD1P3DX xlbafca (.D(tjbf2b7), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(gb5ed3e)) ; defparam rvbfc8a.GSR = "ENABLED" ; FD1P3DX rvbfc8a (.D(czf22b3), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(co3ebab)) ; defparam gq9df00.GSR = "ENABLED" ; FD1P3DX gq9df00 (.D(lq7c001), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(irab06c)) ; defparam qia202.GSR = "ENABLED" ; FD1P3DX qia202 (.D(ym8808d), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(lq6c8cd)) ; defparam me68d50.GSR = "ENABLED" ; FD1P3DX me68d50 (.D(tw35400), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ldcd5e6)) ; defparam wl2de0.GSR = "ENABLED" ; FD1P3DX wl2de0 (.D(pub7827), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(rte6d59)) ; defparam pu3a01e.GSR = "ENABLED" ; FD1P3DX pu3a01e (.D(qv8079b), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qg59f34)) ; defparam kddccbf.GSR = "ENABLED" ; FD1P3DX kddccbf (.D(zz32fe6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(mg3409f)) ; defparam yz363bf.GSR = "ENABLED" ; FD1P3DX yz363bf (.D(nt8efed), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(an9f1ef)) ; defparam bl6e1ac.GSR = "ENABLED" ; FD1P3DX bl6e1ac (.D(mt122f6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(tw354c3)) ; defparam xlaa61a.GSR = "ENABLED" ; FD1P3DX xlaa61a (.D(pff69f5), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(jrb034c)) ; defparam vx81a66.GSR = "ENABLED" ; FD1P3DX vx81a66 (.D(suf5d58), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(gqbc45e)) ; defparam ale22f0.GSR = "ENABLED" ; FD1P3DX ale22f0 (.D(ho58364), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qv23d0e)) ; defparam tw1e875.GSR = "ENABLED" ; FD1P3DX tw1e875 (.D(hb6466a), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ld5a8a4)) ; defparam ayd4527.GSR = "ENABLED" ; FD1P3DX ayd4527 (.D(
-qt6af36), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qgcb534)) ; defparam jp5a9a1.GSR = "ENABLED" ; FD1P3DX jp5a9a1 (.D(cb36acf), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(me78221)) ; defparam uic1108.GSR = "ENABLED" ; FD1P3DX uic1108 (.D(lqcf9a0), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(sw5867)) ; defparam ux2c339.GSR = "ENABLED" ; FD1P3DX ux2c339 (.D(tja04f8), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(vv6ee2f)) ; defparam kq7717f.GSR = "ENABLED" ; FD1P3DX kq7717f (.D(off8f7c), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qgcb6ee)) ; defparam ip5b771.GSR = "ENABLED" ; FD1P3DX ip5b771 (.D(an9f1ef), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ld61cba)) ; defparam bae5d6.GSR = "ENABLED" ; FD1P3DX bae5d6 (.D(rv8448b), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(al7fc5f)) ; defparam lqc0d09.GSR = "ENABLED" ; FD1P3DX lqc0d09 (.D(jr2245e), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(dmfe2fc)) ; defparam wwf0ba4.GSR = "ENABLED" ; FD1P3DX wwf0ba4 (.D(gb5ed3e), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(faf17e3)) ; defparam ps69f44.GSR = "ENABLED" ; FD1P3DX ps69f44 (.D(co3ebab), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ph8bf1a)) ; defparam ntb093e.GSR = "ENABLED" ; FD1P3DX ntb093e (.D(irab06c), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(xj5f8d6)) ; defparam czf8e27.GSR = "ENABLED" ; FD1P3DX czf8e27 (.D(lq6c8cd), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(vvfc6b7)) ; defparam gb7f3f9.GSR = "ENABLED" ; FD1P3DX gb7f3f9 (.D(ldcd5e6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(rte35be)) ; defparam al7abfc.GSR = "ENABLED" ; FD1P3DX al7abfc (.D(rte6d59), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(wy1adf6)) ; defparam kf179df.GSR = "ENABLED" ; FD1P3DX kf179df (.D(qg59f34), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(mrd6fb1)) ; defparam go4c0e6.GSR = "ENABLED" ; FD1P3DX go4c0e6 (.D(mg3409f), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(fcb7d8d)) ; defparam gq2ed9d.GSR = "ENABLED" ; FD1P3DX gq2ed9d (.D(an9f1ef), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(db22415)) ; defparam gb5107f.GSR = "ENABLED" ; FD1S3DX gb5107f (.D(pu3a9c4), .CK(wjf77ad), .CD(icf5b61), .Q(ipfd144)) ; defparam qte8a24.GSR = "ENABLED" ; FD1S3DX qte8a24 (.D(gq82e31), .CK(wjf77ad), .CD(icf5b61), .Q(ks24da8)) ; defparam ux26d40.GSR = "ENABLED" ; FD1S3DX ux26d40 (.D(ep23a0c), .CK(wjf77ad), .CD(icf5b61), .Q(sw599f)) ; defparam ux2ccf9.GSR = "ENABLED" ; FD1S3DX ux2ccf9 (.D(os6dbe6), .CK(wjf77ad), .CD(icf5b61), .Q(wjcc527)) ; defparam yk6293c.GSR = "ENABLED" ; FD1S3DX yk6293c (.D(ks5795), .CK(wjf77ad), .CD(icf5b61), .Q(hoe153c)) ; defparam yma9e3.GSR = "ENABLED" ; FD1S3DX yma9e3 (.D(tjc95d), .CK(wjf77ad), .CD(icf5b61), .Q(gd188e6)) ; defparam icc4734.GSR = "ENABLED" ; FD1S3DX icc4734 (.D(thf328f), .CK(wjf77ad), .CD(icf5b61), .Q(pha0bb8)) ; defparam gq5dc6.GSR = "ENABLED" ; FD1S3DX gq5dc6 (.D(godb92b), .CK(wjf77ad), .CD(icf5b61), .Q(qi3125d)) ; defparam xy892e8.GSR = "ENABLED" ; FD1S3DX xy892e8 (.D(ea62604), .CK(wjf77ad), .CD(icf5b61), .Q(fa4211d)) ; defparam sw108eb.GSR = "ENABLED" ; FD1S3DX sw108eb (.D(co31697), .CK(wjf77ad), .CD(icf5b61), .Q(by58d6a)) ; defparam wjc6b52.GSR = "ENABLED" ; FD1S3DX wjc6b52 (.D(ou3ee1e), .CK(wjf77ad), .CD(icf5b61), .Q(lf946e3)) ; defparam wya371f.GSR = "ENABLED" ; FD1S3DX wya371f (.D(tw354c3), .CK(uv5eef5), .CD(zk5d4fd), .Q(wjf8778)) ; defparam yxc3bc4.GSR = "ENABLED" ; FD1S3DX yxc3bc4 (.D(jrb034c), .CK(uv5eef5), .CD(zk5d4fd), .Q(aa24809)) ; defparam qi24048.GSR = "ENABLED" ; FD1S3DX qi24048 (.D(gqbc45e), .CK(uv5eef5), .CD(zk5d4fd), .Q(yx416b2)) ; defparam lsb594.GSR = "ENABLED" ; FD1S3DX lsb594 (.D(qv23d0e), .CK(uv5eef5), .CD(zk5d4fd), .Q(swa3f17)) ; defparam ie1f8b9.GSR = "ENABLED" ; FD1S3DX ie1f8b9 (.D(ld5a8a4), .CK(uv5eef5), .CD(zk5d4fd), .Q(gbc9d60)) ; defparam gb4eb05.GSR = "ENABLED" ; FD1S3DX gb4eb05 (.D(qgcb534), .CK(uv5eef5), .CD(zk5d4fd), .Q(qv2ca61)) ; defparam uv6530c.GSR = "ENABLED" ; FD1S3DX uv6530c (.D(me78221), .CK(uv5eef5), .CD(zk5d4fd), .Q(ip65837)) ; defparam ep2c1bc.GSR = "ENABLED" ; FD1S3DX ep2c1bc (.D(sw5867), .CK(uv5eef5), .CD(zk5d4fd), .Q(kqe59b1)) ; defparam ux2cd88.GSR = "ENABLED" ; FD1S3DX ux2cd88 (.D(vv6ee2f), .CK(uv5eef5), .CD(zk5d4fd), .Q(ip44761)) ; defparam oh23b0c.GSR = "ENABLED" ; FD1S3DX oh23b0c (.D(qgcb6ee), .CK(uv5eef5), .CD(zk5d4fd), .Q(gb659f7)) ; defparam oh2cfbc.GSR = "ENABLED" ; FD1S3DX oh2cfbc (.D(ld61cba), .CK(uv5eef5), .CD(zk5d4fd), .Q(lqe4221)) ; defparam ec2110b.GSR = "ENABLED" ; FD1S3DX ec2110b (.D(ipfd144), .CK(wjf77ad), .CD(icf5b61), .Q(of51cff)) ; defparam thcd858.GSR = "ENABLED" ; FD1S3DX thcd858 (.D(ks24da8), .CK(wjf77ad), .CD(icf5b61), .Q(sud174a)) ; defparam ou3bed7.GSR = "ENABLED" ; FD1S3DX ou3bed7 (.D(sw599f), .CK(wjf77ad), .CD(icf5b61), .Q(dob2607)) ; defparam zxc26f2.GSR = "ENABLED" ; FD1S3DX zxc26f2 (.D(wjcc527), .CK(wjf77ad), .CD(icf5b61), .Q(ne58241)) ; defparam cbbee21.GSR = "ENABLED" ; FD1S3DX cbbee21 (.D(hoe153c), .CK(wjf77ad), .CD(icf5b61), .Q(qgc120b)) ; defparam en65607.GSR = "ENABLED" ; FD1S3DX en65607 (.D(gd188e6), .CK(wjf77ad), .CD(icf5b61), .Q(bn9058)) ; defparam yxe86e6.GSR = "ENABLED" ; FD1S3DX yxe86e6 (.D(pha0bb8), .CK(wjf77ad), .CD(icf5b61), .Q(ne482c6)) ; defparam yma973a.GSR = "ENABLED" ; FD1S3DX yma973a (.D(qi3125d), .CK(wjf77ad), .CD(icf5b61), .Q(ayef977)) ; defparam zm8c118.GSR = "ENABLED" ; FD1S3DX zm8c118 (.D(fa4211d), .CK(wjf77ad), .CD(icf5b61), .Q(zk7cbb9)) ; defparam do1452e.GSR = "ENABLED" ; FD1S3DX do1452e (.D(by58d6a), .CK(wjf77ad), .CD(icf5b61), .Q(yke5dcb)) ; defparam jr9b583.GSR = "ENABLED" ; FD1S3DX jr9b583 (.D(lf946e3), .CK(wjf77ad), .CD(icf5b61), .Q(aa2ee58)) ; defparam xjf3992.GSR = "ENABLED" ; FD1S3DX xjf3992 (.D(wjf8778), .CK(uv5eef5), .CD(zk5d4fd), .Q(hqad6a9)) ; defparam vkb2dca.GSR = "ENABLED" ; FD1S3DX vkb2dca (.D(aa24809), .CK(uv5eef5), .CD(zk5d4fd), .Q(wjdc2f5)) ; defparam hq9361a.GSR = "ENABLED" ; FD1S3DX hq9361a (.D(yx416b2), .CK(uv5eef5), .CD(zk5d4fd), .Q(xy2afad)) ; defparam do96f47.GSR = "ENABLED" ; FD1S3DX do96f47 (.D(swa3f17), .CK(uv5eef5), .CD(zk5d4fd), .Q(ou3e94b)) ; defparam vida519.GSR = "ENABLED" ; FD1S3DX vida519 (.D(gbc9d60), .CK(uv5eef5), .CD(zk5d4fd), .Q(lqf4a58)) ; defparam xw57e3a.GSR = "ENABLED" ; FD1S3DX xw57e3a (.D(qv2ca61), .CK(uv5eef5), .CD(zk5d4fd), .Q(pha52c3)) ; defparam cb9fbdd.GSR = "ENABLED" ; FD1S3DX cb9fbdd (.D(ip65837), .CK(uv5eef5), .CD(zk5d4fd), .Q(mt2961f)) ; defparam ay6d1b4.GSR = "ENABLED" ; FD1S3DX ay6d1b4 (.D(kqe59b1), .CK(uv5eef5), .CD(zk5d4fd), .Q(wl9a526)) ; defparam kf8125.GSR = "ENABLED" ; FD1S3DX kf8125 (.D(ip44761), .CK(uv5eef5), .CD(zk5d4fd), .Q(jpd2934)) ; defparam kq67614.GSR = "ENABLED" ; FD1S3DX kq67614 (.D(gb659f7), .CK(
-uv5eef5), .CD(zk5d4fd), .Q(jr949a7)) ; defparam ls1f9f.GSR = "ENABLED" ; FD1S3DX ls1f9f (.D(lqe4221), .CK(uv5eef5), .CD(zk5d4fd), .Q(epa4d3e)) ; defparam rtd8fa3.GSR = "ENABLED" ; FD1S3BX rtd8fa3 (.D(mg3e8f6), .CK(wjf77ad), .PD(zk5d4fd), .Q(wjf8aab)) ; defparam vvf608b.GSR = "ENABLED" ; FD1S3DX vvf608b (.D(ec822fe), .CK(uv5eef5), .CD(icf5b61), .Q(jra069c)) ; defparam jcfe2f7.GSR = "ENABLED" ; FD1S3BX jcfe2f7 (.D(jr8bdda), .CK(wjf77ad), .PD(zk5d4fd), .Q(hb507f7)) ; defparam vidad6d.GSR = "ENABLED" ; FD1S3DX vidad6d (.D(vxb5b5d), .CK(uv5eef5), .CD(icf5b61), .Q(ri83fbf)) ; CU2 xw5de8f (.CI(ba1ecef), .PC1(kf9fac1), .PC0(go53f58), .CO(cb8f428), .NC1(zx7b094), .NC0(gb44fd5)); CU2 oh8516a (.CI(cb8f428), .PC1(tj13358), .PC0(icc1b13), .CO(kd6a9bf), .NC1(hq2a714), .NC0(qgffb9a)); CU2 hd37f61 (.CI(kd6a9bf), .PC1(ymb6573), .PC0(jc58cb6), .CO(dz61daf), .NC1(kf9ad77), .NC0(db8bad3)); CU2 ntb5f92 (.CI(dz61daf), .PC1(oha46d4), .PC0(xw732a4), .CO(mg92ffd), .NC1(dz4518e), .NC0(mr6fa1c)); CU2 osffa4e (.CI(mg92ffd), .PC1(hd131a8), .PC0(god4b13), .CO(kd4e139), .NC1(ir1d393), .NC0(cbb1391)); CU2 jr2736f (.CI(kd4e139), .PC1(hd946ae), .PC0(baa8c22), .CO(uv6fd78), .NC1(), .NC0(al752c3)); CU2 qgf5e2e (.CI(ba1ecef), .PC1(jr2245e), .PC0(rv8448b), .CO(qi2e38b), .NC1(ba93757), .NC0(ph133cc)); CU2 rt7163f (.CI(qi2e38b), .PC1(co3ebab), .PC0(gb5ed3e), .CO(ri3fdd6), .NC1(czf22b3), .NC0(tjbf2b7)); CU2 phbac95 (.CI(ri3fdd6), .PC1(lq6c8cd), .PC0(irab06c), .CO(ep95d19), .NC1(ym8808d), .NC0(lq7c001)); CU2 qia332e (.CI(ep95d19), .PC1(rte6d59), .PC0(ldcd5e6), .CO(ym2e1ac), .NC1(pub7827), .NC0(tw35400)); CU2 tw3582a (.CI(ym2e1ac), .PC1(mg3409f), .PC0(qg59f34), .CO(pu2a660), .NC1(zz32fe6), .NC0(qv8079b)); CU2 yxcc082 (.CI(pu2a660), .PC1(hd946ae), .PC0(an9f1ef), .CO(ym82969), .NC1(), .NC0(nt8efed)); FSUB2 vxa5a42 (.A1(kf9fac1), .A0(go53f58), .B1(fcbd6b), .B0(of65b65), .BI(ba1ecef), .BOUT1(bab7697), .BOUT0(), .S1(mtbb4bb), .S0(zkda5dd)); FSUB2 hbd2eea (.A1(tj13358), .A0(icc1b13), .B1(xwc0665), .B0(wlbeb5b), .BI(bab7697), .BOUT1(fcb89ca), .BOUT0(), .S1(uic4e53), .S0(lf27299)); FSUB2 cb394ce (.A1(ymb6573), .A0(jc58cb6), .B1(iea456), .B0(fa57824), .BI(fcb89ca), .BOUT1(aaa3086), .BOUT0(), .S1(sj18430), .S0(hbc2185)); FSUB2 ie10c2f (.A1(oha46d4), .A0(xw732a4), .B1(yz269f4), .B0(wwd4d46), .BI(aaa3086), .BOUT1(ofc3750), .BOUT0(), .S1(ng1ba85), .S0(thdd42b)); FSUB2 meea15f (.A1(hd131a8), .A0(god4b13), .B1(os5c36f), .B0(nr55112), .BI(ofc3750), .BOUT1(czc6875), .BOUT0(), .S1(qi343ac), .S0(yza1d60)); FSUB2 baeb04 (.A1(hd946ae), .A0(gb65982), .B1(hd946ae), .B0(hd946ae), .BI(czc6875), .BOUT1(), .BOUT0(), .S1(), .S0(ym15317)); VHI wya98b9 (.Z(ba1ecef)); FSUB2 me62e40 (.A1(dm5d28e), .A0(ep3c4d2), .B1(jr2245e), .B0(rv8448b), .BI(ba1ecef), .BOUT1(xlc1b3), .BOUT0(), .S1(ip60d9e), .S0(fp6cf4)); FSUB2 qv367a6 (.A1(dm661f6), .A0(qi981da), .B1(co3ebab), .B0(gb5ed3e), .BI(xlc1b3), .BOUT1(ria8eca), .BOUT0(), .S1(by47652), .S0(mg3b293)); FSUB2 ald9499 (.A1(nta586c), .A0(wlaea9b), .B1(lq6c8cd), .B0(irab06c), .BI(ria8eca), .BOUT1(jp6b496), .BOUT0(), .S1(rt5a4b6), .S0(vvd25b6)); FSUB2 uk92db6 (.A1(yk772c1), .A0(xwcff6d), .B1(rte6d59), .B0(ldcd5e6), .BI(jp6b496), .BOUT1(rv8b00c), .BOUT0(), .S1(ps58067), .S0(hoc033b)); FSUB2 fc19da (.A1(ou1abb8), .A0(vv55280), .B1(mg3409f), .B0(qg59f34), .BI(rv8b00c), .BOUT1(yz9f055), .BOUT0(), .S1(pfe6d6c), .S0(mec1564)); FSUB2 swab20 (.A1(hd946ae), .A0(ou82912), .B1(hd946ae), .B0(hd946ae), .BI(yz9f055), .BOUT1(), .BOUT0(), .S1(), .S0(zmad9e7)); AGEB2 ri30ecf (.A1(jr2245e), .A0(rv8448b), .B1(dm5d28e), .B0(ep3c4d2), .CI(yxe7e2a), .GE(wjd931f)); AGEB2 mrc98fd (.A1(co3ebab), .A0(gb5ed3e), .B1(dm661f6), .B0(qi981da), .CI(wjd931f), .GE(go6866d)); AGEB2 ui43369 (.A1(lq6c8cd), .A0(irab06c), .B1(nta586c), .B0(wlaea9b), .CI(go6866d), .GE(ip4ee59)); AGEB2 qg772cc (.A1(rte6d59), .A0(ldcd5e6), .B1(yk772c1), .B0(xwcff6d), .CI(ip4ee59), .GE(cb8227)); AGEB2 wj4113c (.A1(mg3409f), .A0(qg59f34), .B1(ou1abb8), .B0(vv55280), .CI(cb8227), .GE(zm25bea)); AGEB2 lf2df52 (.A1(hd946ae), .A0(ks15d28), .B1(hd946ae), .B0(je2fff9), .CI(zm25bea), .GE(lfb501b)); FADD2 jea80de (.A1(hd946ae), .A0(hd946ae), .B1(hd946ae), .B0(hd946ae), .CI(lfb501b), .COUT1(), .COUT0(), .S1(), .S0(mg3e8f6)); AGEB2 ipf7637 (.A1(kf9fac1), .A0(go53f58), .B1(fcbd6b), .B0(of65b65), .CI(ng9681a), .GE(wjedd33)); AGEB2 rt6e99c (.A1(tj13358), .A0(icc1b13), .B1(xwc0665), .B0(wlbeb5b), .CI(wjedd33), .GE(je3f115)); AGEB2 czf88ab (.A1(ymb6573), .A0(jc58cb6), .B1(iea456), .B0(fa57824), .CI(je3f115), .GE(cze8e6b)); AGEB2 lq4735c (.A1(oha46d4), .A0(xw732a4), .B1(yz269f4), .B0(wwd4d46), .CI(cze8e6b), .GE(kf1ddcf)); AGEB2 pseee7c (.A1(hd131a8), .A0(god4b13), .B1(os5c36f), .B0(nr55112), .CI(kf1ddcf), .GE(vx19296)); AGEB2 enc94b7 (.A1(hd946ae), .A0(yke0381), .B1(hd946ae), .B0(of5b9b5), .CI(vx19296), .GE(ofe76d1)); FADD2 ym3b68c (.A1(hd946ae), .A0(hd946ae), .B1(hd946ae), .B0(hd946ae), .CI(ofe76d1), .COUT1(), .COUT0(), .S1(), .S0(ec822fe)); AGEB2 ho420bc (.A1(kq6d84a[1]), .A0(kq6d84a[0]), .B1(ip60d9e), .B0(fp6cf4), .CI(yxe7e2a), .GE(db19146)); AGEB2 rtc8a37 (.A1(kq6d84a[3]), .A0(kq6d84a[2]), .B1(by47652), .B0(mg3b293), .CI(db19146), .GE(nefec36)); AGEB2 fnf61b2 (.A1(kq6d84a[5]), .A0(kq6d84a[4]), .B1(rt5a4b6), .B0(vvd25b6), .CI(nefec36), .GE(fpbf551)); AGEB2 uifaa8f (.A1(kq6d84a[7]), .A0(kq6d84a[6]), .B1(ps58067), .B0(hoc033b), .CI(fpbf551), .GE(shc3d28)); AGEB2 pu1e944 (.A1(kq6d84a[9]), .A0(kq6d84a[8]), .B1(pfe6d6c), .B0(mec1564), .CI(shc3d28), .GE(fc1bfa4)); AGEB2 fadfd23 (.A1(hd946ae), .A0(hbd2363), .B1(hd946ae), .B0(ui679d2), .CI(fc1bfa4), .GE(vida762)); FADD2 ald3b12 (.A1(hd946ae), .A0(hd946ae), .B1(hd946ae), .B0(hd946ae), .CI(vida762), .COUT1(), .COUT0(), .S1(), .S0(jr8bdda)); AGEB2 vi4716a (.A1(mtbb4bb), .A0(zkda5dd), .B1(xw6c250[1]), .B0(xw6c250[0]), .CI(ng9681a), .GE(ep9f7e1)); AGEB2 tufbf0c (.A1(uic4e53), .A0(lf27299), .B1(xw6c250[3]), .B0(xw6c250[2]), .CI(ep9f7e1), .GE(tj13cb0)); AGEB2 lf9e587 (.A1(sj18430), .A0(hbc2185), .B1(xw6c250[5]), .B0(xw6c250[4]), .CI(tj13cb0), .GE(nef45c0)); AGEB2 zma2e02 (.A1(ng1ba85), .A0(thdd42b), .B1(xw6c250[7]), .B0(xw6c250[6]), .CI(nef45c0), .GE(vk9c4af)); AGEB2 ene257b (.A1(qi343ac), .A0(yza1d60), .B1(xw6c250[9]), .B0(xw6c250[8]), .CI(vk9c4af), .GE(wwe59b4)); AGEB2 mt2cda0 (.A1(hd946ae), .A0(ym15317), .B1(hd946ae), .B0(hd946ae), .CI(wwe59b4), .GE(qv23932)); VLO vx1c995 (.Z(hd946ae)); FADD2 kf26572 (.A1(hd946ae), .A0(hd946ae), .B1(hd946ae), .B0(hd946ae), .CI(qv23932), .COUT1(), .COUT0(), .S1(), .S0(vxb5b5d)); assign vx941f = wjf8aab; assign th4a0fe = jra069c;
-
-always@* begin ng14a7f<={wlabdde>>1,jea8e7a[0]};lfa53fa<=jea8e7a[1];gd29fd7<=jea8e7a[2];th4febc<=jea8e7a[3];cz7f5e6<=jea8e7a[4];wwfaf35<=jea8e7a[5];zxd79a8<=jea8e7a[6];ecbcd47<={kq6d84a>>1,jea8e7a[7]};pfe6a39<={xw6c250>>1,jea8e7a[8]};end
-always@* begin ls351cf[2047]<=uv5eef5;ls351cf[2046]<=wjf77ad;ls351cf[2044]<=yzbbd6d;ls351cf[2040]<=medeb6c;ls351cf[2032]<=icf5b61;ls351cf[2016]<=puadb09;ls351cf[1984]<=kq6d84a[0];ls351cf[1920]<=xw6c250[0];ls351cf[1023]<=wlabdde[0];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-`timescale 1 ns / 100 ps
-module zm209c0 (wlabdde, uv5eef5, wjf77ad, yzbbd6d, medeb6c, icf5b61,
- puadb09, kq6d84a, xw6c250, dz61283, vx941f, th4a0fe, hb507f7,
- ri83fbf);
-input [17:0] wlabdde;
-input uv5eef5;
-input wjf77ad;
-input yzbbd6d;
-input medeb6c;
-input icf5b61;
-input puadb09;
-input [9:0] kq6d84a;
-input [9:0] xw6c250;
-output [17:0] dz61283;
-output vx941f;
-output th4a0fe;
-output hb507f7;
-output ri83fbf;
-reg [17 : 0] ng14a7f;
-reg lfa53fa;
-reg gd29fd7;
-reg th4febc;
-reg cz7f5e6;
-reg wwfaf35;
-reg zxd79a8;
-reg [9 : 0] ecbcd47;
-reg [9 : 0] pfe6a39;
-reg [2047:0] ls351cf;
-wire [8:0] jea8e7a;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-localparam ps473d2 = 9,wl39e93 = 32'hfdffc68b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-AND2 mececb4 (.A(yzbbd6d), .B(fcb2d03), .Z(ng9681a)); INV ohb40d3 (.A(jra069c), .Z(fcb2d03)); AND2 ks1a73f (.A(medeb6c), .B(ls9cfc5), .Z(yxe7e2a)); INV fc3f155 (.A(wjf8aab), .Z(ls9cfc5)); OR2 je2aaea (.A(icf5b61), .B(puadb09), .Z(zk5d4fd)); XOR2 icea7eb (.A(go53f58), .B(kf9fac1), .Z(uvfd60d)); XOR2 hoeb06c (.A(kf9fac1), .B(icc1b13), .Z(sjd899)); XOR2 xw6c4cd (.A(icc1b13), .B(tj13358), .Z(fc99ac6)); XOR2 dzcd632 (.A(tj13358), .B(jc58cb6), .Z(ipc65b2)); XOR2 tj32d95 (.A(jc58cb6), .B(ymb6573), .Z(ngb2b99)); XOR2 an95cca (.A(ymb6573), .B(xw732a4), .Z(fc99523)); XOR2 faca91b (.A(xw732a4), .B(oha46d4), .Z(ep236a5)); XOR2 xy1b52c (.A(oha46d4), .B(god4b13), .Z(hda5898)); XOR2 wl2c4c6 (.A(god4b13), .B(hd131a8), .Z(mg98d46)); XOR2 gbc6a30 (.A(hd131a8), .B(baa8c22), .Z(cm46112)); XOR2 vk30891 (.A(rv8448b), .B(jr2245e), .Z(mt122f6)); XOR2 db917b4 (.A(jr2245e), .B(gb5ed3e), .Z(pff69f5)); XOR2 qvb4fae (.A(gb5ed3e), .B(co3ebab), .Z(suf5d58)); XOR2 sjaeac1 (.A(co3ebab), .B(irab06c), .Z(ho58364)); XOR2 uic1b23 (.A(irab06c), .B(lq6c8cd), .Z(hb6466a)); XOR2 an23357 (.A(lq6c8cd), .B(ldcd5e6), .Z(qt6af36)); XOR2 xw579b5 (.A(ldcd5e6), .B(rte6d59), .Z(cb36acf)); XOR2 rvb567c (.A(rte6d59), .B(qg59f34), .Z(lqcf9a0)); XOR2 ps7cd02 (.A(qg59f34), .B(mg3409f), .Z(tja04f8)); XOR2 sj27c7 (.A(mg3409f), .B(an9f1ef), .Z(off8f7c)); defparam rtc7be5.initval = 16'h6996 ; ROM16X1 rtc7be5 (.AD3(ayef977), .AD2(zk7cbb9), .AD1(yke5dcb), .AD0(aa2ee58), .DO0(yk772c1)) ; defparam mgb9609.initval = 16'h6996 ; ROM16X1 mgb9609 (.AD3(ne58241), .AD2(qgc120b), .AD1(bn9058), .AD0(ne482c6), .DO0(gb41632)) ; defparam xyb194.initval = 16'h6996 ; ROM16X1 xyb194 (.AD3(yke5dcb), .AD2(aa2ee58), .AD1(hd946ae), .AD0(hd946ae), .DO0(ou1abb8)) ; defparam zkd5dc1.initval = 16'h6996 ; ROM16X1 zkd5dc1 (.AD3(zk7cbb9), .AD2(yke5dcb), .AD1(aa2ee58), .AD0(hd946ae), .DO0(vv55280)) ; defparam yma9407.initval = 16'h6996 ; ROM16X1 yma9407 (.AD3(ne482c6), .AD2(ayef977), .AD1(zk7cbb9), .AD0(ou1abb8), .DO0(xwcff6d)) ; defparam ip7fb6a.initval = 16'h6996 ; ROM16X1 ip7fb6a (.AD3(bn9058), .AD2(ne482c6), .AD1(ayef977), .AD0(vv55280), .DO0(nta586c)) ; defparam sj2c366.initval = 16'h6996 ; ROM16X1 sj2c366 (.AD3(qgc120b), .AD2(bn9058), .AD1(ne482c6), .AD0(yk772c1), .DO0(wlaea9b)) ; defparam uv754dd.initval = 16'h6996 ; ROM16X1 uv754dd (.AD3(yk772c1), .AD2(gb41632), .AD1(hd946ae), .AD0(hd946ae), .DO0(dm661f6)) ; defparam pu30fb2.initval = 16'h6996 ; ROM16X1 pu30fb2 (.AD3(yk772c1), .AD2(gb41632), .AD1(dob2607), .AD0(hd946ae), .DO0(qi981da)) ; defparam psc0ed1.initval = 16'h6996 ; ROM16X1 psc0ed1 (.AD3(yk772c1), .AD2(gb41632), .AD1(sud174a), .AD0(dob2607), .DO0(dm5d28e)) ; defparam rte9473.initval = 16'h6996 ; ROM16X1 rte9473 (.AD3(of51cff), .AD2(sud174a), .AD1(dob2607), .AD0(hd946ae), .DO0(ykff9d5)) ; defparam pffcea8.initval = 16'h6996 ; ROM16X1 pffcea8 (.AD3(yk772c1), .AD2(gb41632), .AD1(ykff9d5), .AD0(hd946ae), .DO0(ep3c4d2)) ; defparam kde2694.initval = 16'h6996 ; ROM16X1 kde2694 (.AD3(wl9a526), .AD2(jpd2934), .AD1(jr949a7), .AD0(epa4d3e), .DO0(yz269f4)) ; defparam ec34fa5.initval = 16'h6996 ; ROM16X1 ec34fa5 (.AD3(ou3e94b), .AD2(lqf4a58), .AD1(pha52c3), .AD0(mt2961f), .DO0(sh4b0fd)) ; defparam xw587ed.initval = 16'h6996 ; ROM16X1 xw587ed (.AD3(jr949a7), .AD2(epa4d3e), .AD1(hd946ae), .AD0(hd946ae), .DO0(os5c36f)) ; defparam zke1b79.initval = 16'h6996 ; ROM16X1 zke1b79 (.AD3(jpd2934), .AD2(jr949a7), .AD1(epa4d3e), .AD0(hd946ae), .DO0(nr55112)) ; defparam nga8897.initval = 16'h6996 ; ROM16X1 nga8897 (.AD3(mt2961f), .AD2(wl9a526), .AD1(jpd2934), .AD0(os5c36f), .DO0(wwd4d46)) ; defparam coa6a30.initval = 16'h6996 ; ROM16X1 coa6a30 (.AD3(pha52c3), .AD2(mt2961f), .AD1(wl9a526), .AD0(nr55112), .DO0(iea456)) ; defparam vi522b1.initval = 16'h6996 ; ROM16X1 vi522b1 (.AD3(lqf4a58), .AD2(pha52c3), .AD1(mt2961f), .AD0(yz269f4), .DO0(fa57824)) ; defparam aabc123.initval = 16'h6996 ; ROM16X1 aabc123 (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(hd946ae), .AD0(hd946ae), .DO0(xwc0665)) ; defparam fp332a.initval = 16'h6996 ; ROM16X1 fp332a (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(xy2afad), .AD0(hd946ae), .DO0(wlbeb5b)) ; defparam wwf5adc.initval = 16'h6996 ; ROM16X1 wwf5adc (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(wjdc2f5), .AD0(xy2afad), .DO0(fcbd6b)) ; defparam uv5eb5a.initval = 16'h6996 ; ROM16X1 uv5eb5a (.AD3(hqad6a9), .AD2(wjdc2f5), .AD1(xy2afad), .AD0(hd946ae), .DO0(uka97bb)) ; defparam en4bdd9.initval = 16'h6996 ; ROM16X1 en4bdd9 (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(uka97bb), .AD0(hd946ae), .DO0(of65b65)) ; XOR2 bn2db2c (.A(baa8c22), .B(epa4d3e), .Z(gb65982)); XOR2 oh2cc14 (.A(aa2ee58), .B(an9f1ef), .Z(ou82912)); defparam je14890.initval = 16'h0410 ; ROM16X1 je14890 (.AD3(db22415), .AD2(an9f1ef), .AD1(aa2ee58), .AD0(hd946ae), .DO0(ks15d28)) ; defparam mtae940.initval = 16'h1004 ; ROM16X1 mtae940 (.AD3(db22415), .AD2(an9f1ef), .AD1(aa2ee58), .AD0(hd946ae), .DO0(je2fff9)) ; defparam uv7ffcb.initval = 16'h0140 ; ROM16X1 uv7ffcb (.AD3(ykff2e0), .AD2(baa8c22), .AD1(epa4d3e), .AD0(hd946ae), .DO0(yke0381)) ; defparam fc1c09.initval = 16'h4001 ; ROM16X1 fc1c09 (.AD3(ykff2e0), .AD2(baa8c22), .AD1(epa4d3e), .AD0(hd946ae), .DO0(of5b9b5)) ; INV aldcdad (.A(pfe6d6c), .Z(mt36b67)); AND2 tjb5b3c (.A(zmad9e7), .B(mt36b67), .Z(ui679d2)); AND2 an3ce91 (.A(zmad9e7), .B(pfe6d6c), .Z(hbd2363)); defparam ph91b1e.CSDECODE_B = 3'b000 ; defparam ph91b1e.CSDECODE_A = 3'b000 ; defparam ph91b1e.WRITEMODE_B = "NORMAL" ; defparam ph91b1e.WRITEMODE_A = "NORMAL" ; defparam ph91b1e.GSR = "ENABLED" ; defparam ph91b1e.RESETMODE = "ASYNC" ; defparam ph91b1e.REGMODE_B = "NOREG" ; defparam ph91b1e.REGMODE_A = "NOREG" ; defparam ph91b1e.DATA_WIDTH_B = 18 ; defparam ph91b1e.DATA_WIDTH_A = 18 ; DP16KB ph91b1e (.DIA0(wlabdde[0]), .DIA1(wlabdde[1]), .DIA2(wlabdde[2]), .DIA3(wlabdde[3]), .DIA4(wlabdde[4]), .DIA5(wlabdde[5]), .DIA6(wlabdde[6]), .DIA7(wlabdde[7]), .DIA8(wlabdde[8]), .DIA9(wlabdde[9]), .DIA10(wlabdde[10]), .DIA11(wlabdde[11]), .DIA12(wlabdde[12]), .DIA13(wlabdde[13]), .DIA14(wlabdde[14]), .DIA15(wlabdde[15]), .DIA16(wlabdde[16]), .DIA17(wlabdde[17]), .ADA0(ba1ecef), .ADA1(ba1ecef), .ADA2(hd946ae), .ADA3(hd946ae), .ADA4(meef7c0), .ADA5(pf7be00), .ADA6(tudf006), .ADA7(kdf8032), .ADA8(fac0194), .ADA9(ouca2), .ADA10(ph6511), .ADA11(xl3288f), .ADA12(db9447e), .ADA13(lsa23f7), .CEA(ng9681a), .CLKA(uv5eef5), .WEA(ba1ecef), .CSA0(hd946ae), .CSA1(hd946ae), .CSA2(hd946ae), .RSTA(icf5b61), .DIB0(hd946ae), .DIB1(hd946ae), .DIB2(hd946ae), .DIB3(hd946ae), .DIB4(hd946ae), .DIB5(hd946ae), .DIB6(hd946ae), .DIB7(hd946ae), .DIB8(hd946ae), .DIB9(hd946ae), .DIB10(hd946ae), .DIB11(hd946ae), .DIB12(hd946ae), .DIB13(hd946ae), .DIB14(hd946ae), .DIB15(hd946ae), .DIB16(hd946ae), .DIB17(hd946ae), .ADB0(hd946ae), .ADB1(hd946ae), .ADB2(hd946ae), .ADB3(hd946ae), .ADB4(al7fc5f), .ADB5(dmfe2fc), .ADB6(faf17e3), .ADB7(ph8bf1a), .ADB8(xj5f8d6), .ADB9(vvfc6b7), .ADB10(rte35be), .ADB11(wy1adf6), .ADB12(mrd6fb1), .ADB13(fcb7d8d), .CEB(yxe7e2a), .CLKB(wjf77ad), .WEB(hd946ae), .CSB0(hd946ae), .CSB1(hd946ae), .CSB2(hd946ae), .RSTB(
-icf5b61), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOA9(), .DOA10(), .DOA11(), .DOA12(), .DOA13(), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(dz61283[0]), .DOB1(dz61283[1]), .DOB2(dz61283[2]), .DOB3(dz61283[3]), .DOB4(dz61283[4]), .DOB5(dz61283[5]), .DOB6(dz61283[6]), .DOB7(dz61283[7]), .DOB8(dz61283[8]), .DOB9(dz61283[9]), .DOB10(dz61283[10]), .DOB11(dz61283[11]), .DOB12(dz61283[12]), .DOB13(dz61283[13]), .DOB14(dz61283[14]), .DOB15(dz61283[15]), .DOB16(dz61283[16]), .DOB17(dz61283[17])) ; defparam hq113f.GSR = "ENABLED" ; FD1P3BX hq113f (.D(gb44fd5), .SP(ng9681a), .CK(uv5eef5), .PD(icf5b61), .Q(go53f58)) ; defparam fcadec2.GSR = "ENABLED" ; FD1P3DX fcadec2 (.D(zx7b094), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(kf9fac1)) ; defparam lsa7fee.GSR = "ENABLED" ; FD1P3DX lsa7fee (.D(qgffb9a), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(icc1b13)) ; defparam jcd0a9c.GSR = "ENABLED" ; FD1P3DX jcd0a9c (.D(hq2a714), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tj13358)) ; defparam fca22eb.GSR = "ENABLED" ; FD1P3DX fca22eb (.D(db8bad3), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(jc58cb6)) ; defparam xl9e6b5.GSR = "ENABLED" ; FD1P3DX xl9e6b5 (.D(kf9ad77), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ymb6573)) ; defparam jebdbe8.GSR = "ENABLED" ; FD1P3DX jebdbe8 (.D(mr6fa1c), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(xw732a4)) ; defparam wwe5146.GSR = "ENABLED" ; FD1P3DX wwe5146 (.D(dz4518e), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(oha46d4)) ; defparam zk76c4e.GSR = "ENABLED" ; FD1P3DX zk76c4e (.D(cbb1391), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(god4b13)) ; defparam pu8c74e.GSR = "ENABLED" ; FD1P3DX pu8c74e (.D(ir1d393), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(hd131a8)) ; defparam aa9dd4b.GSR = "ENABLED" ; FD1P3DX aa9dd4b (.D(al752c3), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(baa8c22)) ; defparam tj1c35c.GSR = "ENABLED" ; FD1P3DX tj1c35c (.D(uvfd60d), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(pu3a9c4)) ; defparam sud4e22.GSR = "ENABLED" ; FD1P3DX sud4e22 (.D(sjd899), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(gq82e31)) ; defparam yz17188.GSR = "ENABLED" ; FD1P3DX yz17188 (.D(fc99ac6), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ep23a0c)) ; defparam cb1d065.GSR = "ENABLED" ; FD1P3DX cb1d065 (.D(ipc65b2), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(os6dbe6)) ; defparam cm6df30.GSR = "ENABLED" ; FD1P3DX cm6df30 (.D(ngb2b99), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ks5795)) ; defparam co2bca8.GSR = "ENABLED" ; FD1P3DX co2bca8 (.D(fc99523), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tjc95d)) ; defparam hb64aef.GSR = "ENABLED" ; FD1P3DX hb64aef (.D(ep236a5), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(thf328f)) ; defparam zm9947f.GSR = "ENABLED" ; FD1P3DX zm9947f (.D(hda5898), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(godb92b)) ; defparam ofdc959.GSR = "ENABLED" ; FD1P3DX ofdc959 (.D(mg98d46), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ea62604)) ; defparam zz13020.GSR = "ENABLED" ; FD1P3DX zz13020 (.D(cm46112), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(co31697)) ; defparam rv8b4b8.GSR = "ENABLED" ; FD1P3DX rv8b4b8 (.D(baa8c22), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ou3ee1e)) ; defparam mrf70f0.GSR = "ENABLED" ; FD1P3DX mrf70f0 (.D(go53f58), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(meef7c0)) ; defparam yx54463.GSR = "ENABLED" ; FD1P3DX yx54463 (.D(kf9fac1), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(pf7be00)) ; defparam by524e8.GSR = "ENABLED" ; FD1P3DX by524e8 (.D(icc1b13), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tudf006)) ; defparam je83359.GSR = "ENABLED" ; FD1P3DX je83359 (.D(tj13358), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(kdf8032)) ; defparam rtf6c45.GSR = "ENABLED" ; FD1P3DX rtf6c45 (.D(jc58cb6), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(fac0194)) ; defparam ri8c3c7.GSR = "ENABLED" ; FD1P3DX ri8c3c7 (.D(ymb6573), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ouca2)) ; defparam kfb13d4.GSR = "ENABLED" ; FD1P3DX kfb13d4 (.D(xw732a4), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ph6511)) ; defparam uk1f82d.GSR = "ENABLED" ; FD1P3DX uk1f82d (.D(oha46d4), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(xl3288f)) ; defparam kd703d5.GSR = "ENABLED" ; FD1P3DX kd703d5 (.D(god4b13), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(db9447e)) ; defparam qv39880.GSR = "ENABLED" ; FD1P3DX qv39880 (.D(hd131a8), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(lsa23f7)) ; defparam al6034d.GSR = "ENABLED" ; FD1P3DX al6034d (.D(baa8c22), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ykff2e0)) ; defparam su5c4cf.GSR = "ENABLED" ; FD1P3BX su5c4cf (.D(ph133cc), .SP(yxe7e2a), .CK(wjf77ad), .PD(zk5d4fd), .Q(rv8448b)) ; defparam lq664dd.GSR = "ENABLED" ; FD1P3DX lq664dd (.D(ba93757), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(jr2245e)) ; defparam xlbafca.GSR = "ENABLED" ; FD1P3DX xlbafca (.D(tjbf2b7), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(gb5ed3e)) ; defparam rvbfc8a.GSR = "ENABLED" ; FD1P3DX rvbfc8a (.D(czf22b3), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(co3ebab)) ; defparam gq9df00.GSR = "ENABLED" ; FD1P3DX gq9df00 (.D(lq7c001), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(irab06c)) ; defparam qia202.GSR = "ENABLED" ; FD1P3DX qia202 (.D(ym8808d), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(lq6c8cd)) ; defparam me68d50.GSR = "ENABLED" ; FD1P3DX me68d50 (.D(tw35400), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ldcd5e6)) ; defparam wl2de0.GSR = "ENABLED" ; FD1P3DX wl2de0 (.D(pub7827), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(rte6d59)) ; defparam pu3a01e.GSR = "ENABLED" ; FD1P3DX pu3a01e (.D(qv8079b), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qg59f34)) ; defparam kddccbf.GSR = "ENABLED" ; FD1P3DX kddccbf (.D(zz32fe6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(mg3409f)) ; defparam yz363bf.GSR = "ENABLED" ; FD1P3DX yz363bf (.D(nt8efed), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(an9f1ef)) ; defparam bl6e1ac.GSR = "ENABLED" ; FD1P3DX bl6e1ac (.D(mt122f6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(tw354c3)) ; defparam xlaa61a.GSR = "ENABLED" ; FD1P3DX xlaa61a (.D(pff69f5), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(jrb034c)) ; defparam vx81a66.GSR = "ENABLED" ; FD1P3DX vx81a66 (.D(suf5d58), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(gqbc45e)) ; defparam ale22f0.GSR = "ENABLED" ; FD1P3DX ale22f0 (.D(ho58364), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qv23d0e)) ; defparam tw1e875.GSR
- = "ENABLED" ; FD1P3DX tw1e875 (.D(hb6466a), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ld5a8a4)) ; defparam ayd4527.GSR = "ENABLED" ; FD1P3DX ayd4527 (.D(qt6af36), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qgcb534)) ; defparam jp5a9a1.GSR = "ENABLED" ; FD1P3DX jp5a9a1 (.D(cb36acf), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(me78221)) ; defparam uic1108.GSR = "ENABLED" ; FD1P3DX uic1108 (.D(lqcf9a0), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(sw5867)) ; defparam ux2c339.GSR = "ENABLED" ; FD1P3DX ux2c339 (.D(tja04f8), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(vv6ee2f)) ; defparam kq7717f.GSR = "ENABLED" ; FD1P3DX kq7717f (.D(off8f7c), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qgcb6ee)) ; defparam ip5b771.GSR = "ENABLED" ; FD1P3DX ip5b771 (.D(an9f1ef), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ld61cba)) ; defparam bae5d6.GSR = "ENABLED" ; FD1P3DX bae5d6 (.D(rv8448b), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(al7fc5f)) ; defparam lqc0d09.GSR = "ENABLED" ; FD1P3DX lqc0d09 (.D(jr2245e), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(dmfe2fc)) ; defparam wwf0ba4.GSR = "ENABLED" ; FD1P3DX wwf0ba4 (.D(gb5ed3e), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(faf17e3)) ; defparam ps69f44.GSR = "ENABLED" ; FD1P3DX ps69f44 (.D(co3ebab), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ph8bf1a)) ; defparam ntb093e.GSR = "ENABLED" ; FD1P3DX ntb093e (.D(irab06c), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(xj5f8d6)) ; defparam czf8e27.GSR = "ENABLED" ; FD1P3DX czf8e27 (.D(lq6c8cd), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(vvfc6b7)) ; defparam gb7f3f9.GSR = "ENABLED" ; FD1P3DX gb7f3f9 (.D(ldcd5e6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(rte35be)) ; defparam al7abfc.GSR = "ENABLED" ; FD1P3DX al7abfc (.D(rte6d59), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(wy1adf6)) ; defparam kf179df.GSR = "ENABLED" ; FD1P3DX kf179df (.D(qg59f34), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(mrd6fb1)) ; defparam go4c0e6.GSR = "ENABLED" ; FD1P3DX go4c0e6 (.D(mg3409f), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(fcb7d8d)) ; defparam gq2ed9d.GSR = "ENABLED" ; FD1P3DX gq2ed9d (.D(an9f1ef), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(db22415)) ; defparam gb5107f.GSR = "ENABLED" ; FD1S3DX gb5107f (.D(pu3a9c4), .CK(wjf77ad), .CD(icf5b61), .Q(ipfd144)) ; defparam qte8a24.GSR = "ENABLED" ; FD1S3DX qte8a24 (.D(gq82e31), .CK(wjf77ad), .CD(icf5b61), .Q(ks24da8)) ; defparam ux26d40.GSR = "ENABLED" ; FD1S3DX ux26d40 (.D(ep23a0c), .CK(wjf77ad), .CD(icf5b61), .Q(sw599f)) ; defparam ux2ccf9.GSR = "ENABLED" ; FD1S3DX ux2ccf9 (.D(os6dbe6), .CK(wjf77ad), .CD(icf5b61), .Q(wjcc527)) ; defparam yk6293c.GSR = "ENABLED" ; FD1S3DX yk6293c (.D(ks5795), .CK(wjf77ad), .CD(icf5b61), .Q(hoe153c)) ; defparam yma9e3.GSR = "ENABLED" ; FD1S3DX yma9e3 (.D(tjc95d), .CK(wjf77ad), .CD(icf5b61), .Q(gd188e6)) ; defparam icc4734.GSR = "ENABLED" ; FD1S3DX icc4734 (.D(thf328f), .CK(wjf77ad), .CD(icf5b61), .Q(pha0bb8)) ; defparam gq5dc6.GSR = "ENABLED" ; FD1S3DX gq5dc6 (.D(godb92b), .CK(wjf77ad), .CD(icf5b61), .Q(qi3125d)) ; defparam xy892e8.GSR = "ENABLED" ; FD1S3DX xy892e8 (.D(ea62604), .CK(wjf77ad), .CD(icf5b61), .Q(fa4211d)) ; defparam sw108eb.GSR = "ENABLED" ; FD1S3DX sw108eb (.D(co31697), .CK(wjf77ad), .CD(icf5b61), .Q(by58d6a)) ; defparam wjc6b52.GSR = "ENABLED" ; FD1S3DX wjc6b52 (.D(ou3ee1e), .CK(wjf77ad), .CD(icf5b61), .Q(lf946e3)) ; defparam wya371f.GSR = "ENABLED" ; FD1S3DX wya371f (.D(tw354c3), .CK(uv5eef5), .CD(zk5d4fd), .Q(wjf8778)) ; defparam yxc3bc4.GSR = "ENABLED" ; FD1S3DX yxc3bc4 (.D(jrb034c), .CK(uv5eef5), .CD(zk5d4fd), .Q(aa24809)) ; defparam qi24048.GSR = "ENABLED" ; FD1S3DX qi24048 (.D(gqbc45e), .CK(uv5eef5), .CD(zk5d4fd), .Q(yx416b2)) ; defparam lsb594.GSR = "ENABLED" ; FD1S3DX lsb594 (.D(qv23d0e), .CK(uv5eef5), .CD(zk5d4fd), .Q(swa3f17)) ; defparam ie1f8b9.GSR = "ENABLED" ; FD1S3DX ie1f8b9 (.D(ld5a8a4), .CK(uv5eef5), .CD(zk5d4fd), .Q(gbc9d60)) ; defparam gb4eb05.GSR = "ENABLED" ; FD1S3DX gb4eb05 (.D(qgcb534), .CK(uv5eef5), .CD(zk5d4fd), .Q(qv2ca61)) ; defparam uv6530c.GSR = "ENABLED" ; FD1S3DX uv6530c (.D(me78221), .CK(uv5eef5), .CD(zk5d4fd), .Q(ip65837)) ; defparam ep2c1bc.GSR = "ENABLED" ; FD1S3DX ep2c1bc (.D(sw5867), .CK(uv5eef5), .CD(zk5d4fd), .Q(kqe59b1)) ; defparam ux2cd88.GSR = "ENABLED" ; FD1S3DX ux2cd88 (.D(vv6ee2f), .CK(uv5eef5), .CD(zk5d4fd), .Q(ip44761)) ; defparam oh23b0c.GSR = "ENABLED" ; FD1S3DX oh23b0c (.D(qgcb6ee), .CK(uv5eef5), .CD(zk5d4fd), .Q(gb659f7)) ; defparam oh2cfbc.GSR = "ENABLED" ; FD1S3DX oh2cfbc (.D(ld61cba), .CK(uv5eef5), .CD(zk5d4fd), .Q(lqe4221)) ; defparam ec2110b.GSR = "ENABLED" ; FD1S3DX ec2110b (.D(ipfd144), .CK(wjf77ad), .CD(icf5b61), .Q(of51cff)) ; defparam thcd858.GSR = "ENABLED" ; FD1S3DX thcd858 (.D(ks24da8), .CK(wjf77ad), .CD(icf5b61), .Q(sud174a)) ; defparam ou3bed7.GSR = "ENABLED" ; FD1S3DX ou3bed7 (.D(sw599f), .CK(wjf77ad), .CD(icf5b61), .Q(dob2607)) ; defparam zxc26f2.GSR = "ENABLED" ; FD1S3DX zxc26f2 (.D(wjcc527), .CK(wjf77ad), .CD(icf5b61), .Q(ne58241)) ; defparam cbbee21.GSR = "ENABLED" ; FD1S3DX cbbee21 (.D(hoe153c), .CK(wjf77ad), .CD(icf5b61), .Q(qgc120b)) ; defparam en65607.GSR = "ENABLED" ; FD1S3DX en65607 (.D(gd188e6), .CK(wjf77ad), .CD(icf5b61), .Q(bn9058)) ; defparam yxe86e6.GSR = "ENABLED" ; FD1S3DX yxe86e6 (.D(pha0bb8), .CK(wjf77ad), .CD(icf5b61), .Q(ne482c6)) ; defparam yma973a.GSR = "ENABLED" ; FD1S3DX yma973a (.D(qi3125d), .CK(wjf77ad), .CD(icf5b61), .Q(ayef977)) ; defparam zm8c118.GSR = "ENABLED" ; FD1S3DX zm8c118 (.D(fa4211d), .CK(wjf77ad), .CD(icf5b61), .Q(zk7cbb9)) ; defparam do1452e.GSR = "ENABLED" ; FD1S3DX do1452e (.D(by58d6a), .CK(wjf77ad), .CD(icf5b61), .Q(yke5dcb)) ; defparam jr9b583.GSR = "ENABLED" ; FD1S3DX jr9b583 (.D(lf946e3), .CK(wjf77ad), .CD(icf5b61), .Q(aa2ee58)) ; defparam xjf3992.GSR = "ENABLED" ; FD1S3DX xjf3992 (.D(wjf8778), .CK(uv5eef5), .CD(zk5d4fd), .Q(hqad6a9)) ; defparam vkb2dca.GSR = "ENABLED" ; FD1S3DX vkb2dca (.D(aa24809), .CK(uv5eef5), .CD(zk5d4fd), .Q(wjdc2f5)) ; defparam hq9361a.GSR = "ENABLED" ; FD1S3DX hq9361a (.D(yx416b2), .CK(uv5eef5), .CD(zk5d4fd), .Q(xy2afad)) ; defparam do96f47.GSR = "ENABLED" ; FD1S3DX do96f47 (.D(swa3f17), .CK(uv5eef5), .CD(zk5d4fd), .Q(ou3e94b)) ; defparam vida519.GSR = "ENABLED" ; FD1S3DX vida519 (.D(gbc9d60), .CK(uv5eef5), .CD(zk5d4fd), .Q(lqf4a58)) ; defparam xw57e3a.GSR = "ENABLED" ; FD1S3DX xw57e3a (.D(qv2ca61), .CK(uv5eef5), .CD(zk5d4fd), .Q(pha52c3)) ; defparam cb9fbdd.GSR = "ENABLED" ; FD1S3DX cb9fbdd (.D(ip65837), .CK(uv5eef5), .CD(zk5d4fd), .Q(mt2961f)) ; defparam ay6d1b4.GSR = "ENABLED" ; FD1S3DX ay6d1b4 (.D(kqe59b1), .CK(uv5eef5), .CD(zk5d4fd), .Q(wl9a526)) ; defparam
-kf8125.GSR = "ENABLED" ; FD1S3DX kf8125 (.D(ip44761), .CK(uv5eef5), .CD(zk5d4fd), .Q(jpd2934)) ; defparam kq67614.GSR = "ENABLED" ; FD1S3DX kq67614 (.D(gb659f7), .CK(uv5eef5), .CD(zk5d4fd), .Q(jr949a7)) ; defparam ls1f9f.GSR = "ENABLED" ; FD1S3DX ls1f9f (.D(lqe4221), .CK(uv5eef5), .CD(zk5d4fd), .Q(epa4d3e)) ; defparam rtd8fa3.GSR = "ENABLED" ; FD1S3BX rtd8fa3 (.D(mg3e8f6), .CK(wjf77ad), .PD(zk5d4fd), .Q(wjf8aab)) ; defparam vvf608b.GSR = "ENABLED" ; FD1S3DX vvf608b (.D(ec822fe), .CK(uv5eef5), .CD(icf5b61), .Q(jra069c)) ; defparam jcfe2f7.GSR = "ENABLED" ; FD1S3BX jcfe2f7 (.D(jr8bdda), .CK(wjf77ad), .PD(zk5d4fd), .Q(hb507f7)) ; defparam vidad6d.GSR = "ENABLED" ; FD1S3DX vidad6d (.D(vxb5b5d), .CK(uv5eef5), .CD(icf5b61), .Q(ri83fbf)) ; FADD2B me530f4 (.A0(hd946ae), .A1(ba1ecef), .B0(hd946ae), .B1(ba1ecef), .CI(hd946ae), .COUT(je18d7), .S0(), .S1()); CU2 xw5de8f (.CI(je18d7), .PC0(go53f58), .PC1(kf9fac1), .CO(cb8f428), .NC0(gb44fd5), .NC1(zx7b094)); CU2 oh8516a (.CI(cb8f428), .PC0(icc1b13), .PC1(tj13358), .CO(kd6a9bf), .NC0(qgffb9a), .NC1(hq2a714)); CU2 hd37f61 (.CI(kd6a9bf), .PC0(jc58cb6), .PC1(ymb6573), .CO(dz61daf), .NC0(db8bad3), .NC1(kf9ad77)); CU2 ntb5f92 (.CI(dz61daf), .PC0(xw732a4), .PC1(oha46d4), .CO(mg92ffd), .NC0(mr6fa1c), .NC1(dz4518e)); CU2 osffa4e (.CI(mg92ffd), .PC0(god4b13), .PC1(hd131a8), .CO(kd4e139), .NC0(cbb1391), .NC1(ir1d393)); CU2 jr2736f (.CI(kd4e139), .PC0(baa8c22), .PC1(hd946ae), .CO(uv6fd78), .NC0(al752c3), .NC1()); FADD2B ng30277 (.A0(hd946ae), .A1(ba1ecef), .B0(hd946ae), .B1(ba1ecef), .CI(hd946ae), .COUT(kdd6f0e), .S0(), .S1()); CU2 qgf5e2e (.CI(kdd6f0e), .PC0(rv8448b), .PC1(jr2245e), .CO(qi2e38b), .NC0(ph133cc), .NC1(ba93757)); CU2 rt7163f (.CI(qi2e38b), .PC0(gb5ed3e), .PC1(co3ebab), .CO(ri3fdd6), .NC0(tjbf2b7), .NC1(czf22b3)); CU2 phbac95 (.CI(ri3fdd6), .PC0(irab06c), .PC1(lq6c8cd), .CO(ep95d19), .NC0(lq7c001), .NC1(ym8808d)); CU2 qia332e (.CI(ep95d19), .PC0(ldcd5e6), .PC1(rte6d59), .CO(ym2e1ac), .NC0(tw35400), .NC1(pub7827)); CU2 tw3582a (.CI(ym2e1ac), .PC0(qg59f34), .PC1(mg3409f), .CO(pu2a660), .NC0(qv8079b), .NC1(zz32fe6)); CU2 yxcc082 (.CI(pu2a660), .PC0(an9f1ef), .PC1(hd946ae), .CO(ym82969), .NC0(nt8efed), .NC1()); FSUB2B vxa5a42 (.A0(ba1ecef), .A1(go53f58), .B0(hd946ae), .B1(of65b65), .BI(hd946ae), .BOUT(bab7697), .S0(), .S1(zkda5dd)); FSUB2B hbd2eea (.A0(kf9fac1), .A1(icc1b13), .B0(fcbd6b), .B1(wlbeb5b), .BI(bab7697), .BOUT(fcb89ca), .S0(mtbb4bb), .S1(lf27299)); FSUB2B cb394ce (.A0(tj13358), .A1(jc58cb6), .B0(xwc0665), .B1(fa57824), .BI(fcb89ca), .BOUT(aaa3086), .S0(uic4e53), .S1(hbc2185)); FSUB2B ie10c2f (.A0(ymb6573), .A1(xw732a4), .B0(iea456), .B1(wwd4d46), .BI(aaa3086), .BOUT(ofc3750), .S0(sj18430), .S1(thdd42b)); FSUB2B meea15f (.A0(oha46d4), .A1(god4b13), .B0(yz269f4), .B1(nr55112), .BI(ofc3750), .BOUT(czc6875), .S0(ng1ba85), .S1(yza1d60)); FSUB2B baeb04 (.A0(hd131a8), .A1(gb65982), .B0(os5c36f), .B1(hd946ae), .BI(czc6875), .BOUT(), .S0(qi343ac), .S1(ym15317)); VHI wya98b9 (.Z(ba1ecef)); FSUB2B me62e40 (.A0(ba1ecef), .A1(ep3c4d2), .B0(hd946ae), .B1(rv8448b), .BI(hd946ae), .BOUT(xlc1b3), .S0(), .S1(fp6cf4)); FSUB2B qv367a6 (.A0(dm5d28e), .A1(qi981da), .B0(jr2245e), .B1(gb5ed3e), .BI(xlc1b3), .BOUT(ria8eca), .S0(ip60d9e), .S1(mg3b293)); FSUB2B ald9499 (.A0(dm661f6), .A1(wlaea9b), .B0(co3ebab), .B1(irab06c), .BI(ria8eca), .BOUT(jp6b496), .S0(by47652), .S1(vvd25b6)); FSUB2B uk92db6 (.A0(nta586c), .A1(xwcff6d), .B0(lq6c8cd), .B1(ldcd5e6), .BI(jp6b496), .BOUT(rv8b00c), .S0(rt5a4b6), .S1(hoc033b)); FSUB2B fc19da (.A0(yk772c1), .A1(vv55280), .B0(rte6d59), .B1(qg59f34), .BI(rv8b00c), .BOUT(yz9f055), .S0(ps58067), .S1(mec1564)); FSUB2B swab20 (.A0(ou1abb8), .A1(ou82912), .B0(mg3409f), .B1(hd946ae), .BI(yz9f055), .BOUT(), .S0(pfe6d6c), .S1(zmad9e7)); FADD2B aa5bd (.A0(hd946ae), .A1(yxe7e2a), .B0(hd946ae), .B1(yxe7e2a), .CI(hd946ae), .COUT(wj44e94), .S0(), .S1()); AGEB2 ri30ecf (.A0(rv8448b), .A1(jr2245e), .B0(ep3c4d2), .B1(dm5d28e), .CI(wj44e94), .GE(wjd931f)); AGEB2 mrc98fd (.A0(gb5ed3e), .A1(co3ebab), .B0(qi981da), .B1(dm661f6), .CI(wjd931f), .GE(go6866d)); AGEB2 ui43369 (.A0(irab06c), .A1(lq6c8cd), .B0(wlaea9b), .B1(nta586c), .CI(go6866d), .GE(ip4ee59)); AGEB2 qg772cc (.A0(ldcd5e6), .A1(rte6d59), .B0(xwcff6d), .B1(yk772c1), .CI(ip4ee59), .GE(cb8227)); AGEB2 wj4113c (.A0(qg59f34), .A1(mg3409f), .B0(vv55280), .B1(ou1abb8), .CI(cb8227), .GE(zm25bea)); AGEB2 lf2df52 (.A0(ks15d28), .A1(hd946ae), .B0(je2fff9), .B1(hd946ae), .CI(zm25bea), .GE(lfb501b)); FADD2B jea80de (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(lfb501b), .COUT(), .S0(mg3e8f6), .S1()); FADD2B ic67b2e (.A0(hd946ae), .A1(ng9681a), .B0(hd946ae), .B1(ng9681a), .CI(hd946ae), .COUT(mt8fd07), .S0(), .S1()); AGEB2 ipf7637 (.A0(go53f58), .A1(kf9fac1), .B0(of65b65), .B1(fcbd6b), .CI(mt8fd07), .GE(wjedd33)); AGEB2 rt6e99c (.A0(icc1b13), .A1(tj13358), .B0(wlbeb5b), .B1(xwc0665), .CI(wjedd33), .GE(je3f115)); AGEB2 czf88ab (.A0(jc58cb6), .A1(ymb6573), .B0(fa57824), .B1(iea456), .CI(je3f115), .GE(cze8e6b)); AGEB2 lq4735c (.A0(xw732a4), .A1(oha46d4), .B0(wwd4d46), .B1(yz269f4), .CI(cze8e6b), .GE(kf1ddcf)); AGEB2 pseee7c (.A0(god4b13), .A1(hd131a8), .B0(nr55112), .B1(os5c36f), .CI(kf1ddcf), .GE(vx19296)); AGEB2 enc94b7 (.A0(yke0381), .A1(hd946ae), .B0(of5b9b5), .B1(hd946ae), .CI(vx19296), .GE(ofe76d1)); FADD2B ym3b68c (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(ofe76d1), .COUT(), .S0(ec822fe), .S1()); FADD2B shed6e6 (.A0(hd946ae), .A1(yxe7e2a), .B0(hd946ae), .B1(yxe7e2a), .CI(hd946ae), .COUT(mtaeb3b), .S0(), .S1()); AGEB2 ho420bc (.A0(kq6d84a[0]), .A1(kq6d84a[1]), .B0(fp6cf4), .B1(ip60d9e), .CI(mtaeb3b), .GE(db19146)); AGEB2 rtc8a37 (.A0(kq6d84a[2]), .A1(kq6d84a[3]), .B0(mg3b293), .B1(by47652), .CI(db19146), .GE(nefec36)); AGEB2 fnf61b2 (.A0(kq6d84a[4]), .A1(kq6d84a[5]), .B0(vvd25b6), .B1(rt5a4b6), .CI(nefec36), .GE(fpbf551)); AGEB2 uifaa8f (.A0(kq6d84a[6]), .A1(kq6d84a[7]), .B0(hoc033b), .B1(ps58067), .CI(fpbf551), .GE(shc3d28)); AGEB2 pu1e944 (.A0(kq6d84a[8]), .A1(kq6d84a[9]), .B0(mec1564), .B1(pfe6d6c), .CI(shc3d28), .GE(fc1bfa4)); AGEB2 fadfd23 (.A0(hbd2363), .A1(hd946ae), .B0(ui679d2), .B1(hd946ae), .CI(fc1bfa4), .GE(vida762)); FADD2B ald3b12 (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(vida762), .COUT(), .S0(jr8bdda), .S1()); FADD2B qg72dd6 (.A0(hd946ae), .A1(ng9681a), .B0(hd946ae), .B1(ng9681a), .CI(hd946ae), .COUT(tw837a6), .S0(), .S1()); AGEB2 vi4716a (.A0(zkda5dd), .A1(mtbb4bb), .B0(xw6c250[0]), .B1(xw6c250[1]), .CI(tw837a6), .GE(ep9f7e1)); AGEB2 tufbf0c (.A0(lf27299), .A1(uic4e53), .B0(xw6c250[2]), .B1(xw6c250[3]), .CI(ep9f7e1), .GE(tj13cb0)); AGEB2 lf9e587 (.A0(hbc2185), .A1(sj18430), .B0(xw6c250[4]), .B1(xw6c250[5]), .CI(tj13cb0), .GE(nef45c0)); AGEB2 zma2e02 (.A0(thdd42b), .A1(ng1ba85), .B0(xw6c250[6]), .B1(xw6c250[7]), .CI(nef45c0), .GE(vk9c4af)); AGEB2 ene257b (.A0(yza1d60), .A1(qi343ac), .B0(xw6c250[8]), .B1(xw6c250[9]), .CI(vk9c4af), .GE(wwe59b4)); AGEB2 mt2cda0 (.A0(ym15317), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(wwe59b4), .GE(qv23932)); VLO vx1c995 (.Z(hd946ae)); FADD2B kf26572 (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(qv23932), .COUT(), .S0(vxb5b5d), .S1()); assign vx941f = wjf8aab; assign th4a0fe = jra069c;
-
-always@* begin ng14a7f<={wlabdde>>1,jea8e7a[0]};lfa53fa<=jea8e7a[1];gd29fd7<=jea8e7a[2];th4febc<=jea8e7a[3];cz7f5e6<=jea8e7a[4];wwfaf35<=jea8e7a[5];zxd79a8<=jea8e7a[6];ecbcd47<={kq6d84a>>1,jea8e7a[7]};pfe6a39<={xw6c250>>1,jea8e7a[8]};end
-always@* begin ls351cf[2047]<=uv5eef5;ls351cf[2046]<=wjf77ad;ls351cf[2044]<=yzbbd6d;ls351cf[2040]<=medeb6c;ls351cf[2032]<=icf5b61;ls351cf[2017]<=puadb09;ls351cf[1987]<=kq6d84a[0];ls351cf[1926]<=xw6c250[0];ls351cf[1023]<=wlabdde[0];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-`timescale 1 ns / 100 ps
-module jr8178b (wlabdde, uv5eef5, wjf77ad, yzbbd6d, medeb6c, icf5b61,
- puadb09, kq6d84a, xw6c250, dz61283, vx941f, th4a0fe, hb507f7,
- ri83fbf);
-input wire [17:0] wlabdde;
-input wire uv5eef5;
-input wire wjf77ad;
-input wire yzbbd6d;
-input wire medeb6c;
-input wire icf5b61;
-input wire puadb09;
-input wire [9:0] kq6d84a;
-input wire [9:0] xw6c250;
-output wire [17:0] dz61283;
-output wire vx941f;
-output wire th4a0fe;
-output wire hb507f7;
-output wire ri83fbf;
-wire fcb2d03;
-wire ls9cfc5;
-wire ykff9d5;
-wire gb41632;
-wire uka97bb;
-wire sh4b0fd;
-wire yz29b02;
-wire uvfd60d;
-wire sjd899;
-wire fc99ac6;
-wire ipc65b2;
-wire ngb2b99;
-wire fc99523;
-wire ep236a5;
-wire hda5898;
-wire mg98d46;
-wire cm46112;
-wire meef7c0;
-wire pf7be00;
-wire tudf006;
-wire kdf8032;
-wire fac0194;
-wire ouca2;
-wire ph6511;
-wire xl3288f;
-wire db9447e;
-wire lsa23f7;
-wire ykff2e0;
-wire mt122f6;
-wire pff69f5;
-wire suf5d58;
-wire ho58364;
-wire hb6466a;
-wire qt6af36;
-wire cb36acf;
-wire lqcf9a0;
-wire tja04f8;
-wire off8f7c;
-wire al7fc5f;
-wire dmfe2fc;
-wire faf17e3;
-wire ph8bf1a;
-wire xj5f8d6;
-wire vvfc6b7;
-wire rte35be;
-wire wy1adf6;
-wire mrd6fb1;
-wire fcb7d8d;
-wire db22415;
-wire pu3a9c4;
-wire gq82e31;
-wire ep23a0c;
-wire os6dbe6;
-wire ks5795;
-wire tjc95d;
-wire thf328f;
-wire godb92b;
-wire ea62604;
-wire co31697;
-wire ou3ee1e;
-wire tw354c3;
-wire jrb034c;
-wire gqbc45e;
-wire qv23d0e;
-wire ld5a8a4;
-wire qgcb534;
-wire me78221;
-wire sw5867;
-wire vv6ee2f;
-wire qgcb6ee;
-wire ld61cba;
-wire of51cff;
-wire ipfd144;
-wire sud174a;
-wire ks24da8;
-wire dob2607;
-wire sw599f;
-wire ne58241;
-wire wjcc527;
-wire qgc120b;
-wire hoe153c;
-wire bn9058;
-wire gd188e6;
-wire ne482c6;
-wire pha0bb8;
-wire ayef977;
-wire qi3125d;
-wire zk7cbb9;
-wire fa4211d;
-wire yke5dcb;
-wire by58d6a;
-wire aa2ee58;
-wire lf946e3;
-wire hqad6a9;
-wire wjf8778;
-wire wjdc2f5;
-wire aa24809;
-wire xy2afad;
-wire yx416b2;
-wire ou3e94b;
-wire swa3f17;
-wire lqf4a58;
-wire gbc9d60;
-wire pha52c3;
-wire qv2ca61;
-wire mt2961f;
-wire ip65837;
-wire wl9a526;
-wire kqe59b1;
-wire jpd2934;
-wire ip44761;
-wire jr949a7;
-wire gb659f7;
-wire epa4d3e;
-wire lqe4221;
-wire tuee7bc;
-wire wjf8aab;
-wire jra069c;
-wire zk5d4fd;
-wire gb44fd5;
-wire zx7b094;
-wire je18d7;
-wire qgffb9a;
-wire hq2a714;
-wire cb8f428;
-wire db8bad3;
-wire kf9ad77;
-wire kd6a9bf;
-wire mr6fa1c;
-wire dz4518e;
-wire dz61daf;
-wire cbb1391;
-wire ir1d393;
-wire mg92ffd;
-wire al752c3;
-wire uv6fd78;
-wire baa8c22;
-wire kd4e139;
-wire ph133cc;
-wire ba93757;
-wire kdd6f0e;
-wire tjbf2b7;
-wire czf22b3;
-wire qi2e38b;
-wire lq7c001;
-wire ym8808d;
-wire ri3fdd6;
-wire tw35400;
-wire pub7827;
-wire ep95d19;
-wire qv8079b;
-wire zz32fe6;
-wire ym2e1ac;
-wire nt8efed;
-wire ym82969;
-wire an9f1ef;
-wire pu2a660;
-wire zkda5dd;
-wire mtbb4bb;
-wire lf27299;
-wire bab7697;
-wire uic4e53;
-wire hbc2185;
-wire fcb89ca;
-wire sj18430;
-wire thdd42b;
-wire aaa3086;
-wire ng1ba85;
-wire yza1d60;
-wire ofc3750;
-wire qi343ac;
-wire ym15317;
-wire czc6875;
-wire gb65982;
-wire an29990;
-wire ui4cc84;
-wire fp6cf4;
-wire ba1ecef;
-wire ip60d9e;
-wire mg3b293;
-wire xlc1b3;
-wire by47652;
-wire vvd25b6;
-wire ria8eca;
-wire rt5a4b6;
-wire hoc033b;
-wire jp6b496;
-wire ps58067;
-wire mec1564;
-wire rv8b00c;
-wire pfe6d6c;
-wire zmad9e7;
-wire yz9f055;
-wire ou82912;
-wire hb7191b;
-wire hq8c8df;
-wire wj44e94;
-wire ep3c4d2;
-wire dm5d28e;
-wire rv8448b;
-wire jr2245e;
-wire wjd931f;
-wire qi981da;
-wire dm661f6;
-wire gb5ed3e;
-wire co3ebab;
-wire go6866d;
-wire wlaea9b;
-wire nta586c;
-wire irab06c;
-wire lq6c8cd;
-wire ip4ee59;
-wire xwcff6d;
-wire yk772c1;
-wire ldcd5e6;
-wire rte6d59;
-wire cb8227;
-wire vv55280;
-wire ou1abb8;
-wire qg59f34;
-wire mg3409f;
-wire zm25bea;
-wire je2fff9;
-wire ks15d28;
-wire mg3e8f6;
-wire lfb501b;
-wire mt8fd07;
-wire of65b65;
-wire fcbd6b;
-wire go53f58;
-wire kf9fac1;
-wire wjedd33;
-wire wlbeb5b;
-wire xwc0665;
-wire icc1b13;
-wire tj13358;
-wire je3f115;
-wire fa57824;
-wire iea456;
-wire jc58cb6;
-wire ymb6573;
-wire cze8e6b;
-wire wwd4d46;
-wire yz269f4;
-wire xw732a4;
-wire oha46d4;
-wire kf1ddcf;
-wire nr55112;
-wire os5c36f;
-wire god4b13;
-wire hd131a8;
-wire vx19296;
-wire of5b9b5;
-wire yke0381;
-wire ec822fe;
-wire ofe76d1;
-wire yxe7e2a;
-wire mtaeb3b;
-wire ba898cd;
-wire qg4c66b;
-wire db19146;
-wire rv19ac2;
-wire vvcd616;
-wire nefec36;
-wire rg585b6;
-wire zxc2db3;
-wire fpbf551;
-wire ymb6cf7;
-wire ieb67b8;
-wire shc3d28;
-wire jr9ee08;
-wire mrf7047;
-wire fc1bfa4;
-wire ui679d2;
-wire hbd2363;
-wire jr8bdda;
-wire vida762;
-wire ng9681a;
-wire tw837a6;
-wire kf85586;
-wire do2ac34;
-wire ep9f7e1;
-wire fpb0d18;
-wire ri868c7;
-wire tj13cb0;
-wire uka31d0;
-wire wl18e80;
-wire nef45c0;
-wire zm3a027;
-wire zkd013b;
-wire vk9c4af;
-wire ba4edd;
-wire ph276eb;
-wire wwe59b4;
-wire cmdbaf1;
-wire vxb5b5d;
-wire qv23932;
-wire hd946ae;
-reg [17 : 0] ng14a7f;
-reg lfa53fa;
-reg gd29fd7;
-reg th4febc;
-reg cz7f5e6;
-reg wwfaf35;
-reg zxd79a8;
-reg [9 : 0] ecbcd47;
-reg [9 : 0] pfe6a39;
-reg qgf59ea;
-reg aaacf51;
-reg ui67a88;
-reg bn3d441;
-reg kqea20e;
-reg yx51070;
-reg wy88385;
-reg al41c28;
-reg fce145;
-reg yx70a2b;
-reg oh8515d;
-reg lf28aec;
-reg hb45766;
-reg ec2bb36;
-reg fa5d9b1;
-reg dzecd8a;
-reg tu66c56;
-reg sj362b3;
-reg sjb159d;
-reg oh8acec;
-reg me56764;
-reg aab3b20;
-reg ym9d900;
-reg zxec800;
-reg pf64006;
-reg ls20037;
-reg ec1bb;
-reg gqdd8;
-reg db6ec1;
-reg bn3760e;
-reg mtbb077;
-reg bld83bd;
-reg ykc1def;
-reg puef79;
-reg ui77bca;
-reg dobde50;
-reg eaef283;
-reg by79418;
-reg lqca0c2;
-reg vv50613;
-reg zm8309f;
-reg yz184fb;
-reg dzc27dd;
-reg fp13eef;
-reg cb9f77f;
-reg dmfbbfc;
-reg dzddfe2;
-reg kqeff16;
-reg cz7f8b1;
-reg vvfc58c;
-reg qte2c66;
-reg vx16335;
-reg wlb19ae;
-reg xy8cd75;
-reg lq66bab;
-reg fc35d5b;
-reg sjaeadb;
-reg of756dd;
-reg irab6ec;
-reg ip5b764;
-reg ykdbb24;
-reg dzdd921;
-reg nrec90e;
-reg xj64876;
-reg sw243b6;
-reg ie21db1;
-reg doed88;
-reg dm76c42;
-reg wyb6212;
-reg yzb1091;
-reg ie8848c;
-reg rg42460;
-reg mt12303;
-reg db9181c;
-reg hq8c0e6;
-reg kd60732;
-reg zz3995;
-reg vx1ccae;
-reg ble6576;
-reg bn32bb6;
-reg ir95db6;
-reg wlaedb4;
-reg tu76da5;
-reg ukb6d2a;
-reg cob6950;
-reg qvb4a80;
-reg dba5405;
-reg tw2a02f;
-reg th5017a;
-reg kf80bd7;
-reg gq5ebd;
-reg ba2f5e9;
-reg en7af4a;
-reg ldd7a54;
-reg xybd2a7;
-reg hbe953a;
-reg fn4a9d7;
-reg uv54ebe;
-reg nga75f4;
-reg ri3afa2;
-reg ldd7d12;
-reg yzbe897;
-reg nef44bc;
-reg zma25e2;
-reg kf12f12;
-reg ou97895;
-reg ukbc4a9;
-reg ipe2548;
-reg ep12a44;
-reg ux95225;
-reg qia912d;
-reg xw48969;
-reg mr44b4b;
-reg xy25a5d;
-reg vx2d2ea;
-reg lq69757;
-reg kd4babb;
-reg ho5d5dc;
-reg uieaee3;
-reg dm57719;
-reg irbb8ca;
-reg qtdc654;
-reg rte32a5;
-reg zz1952e;
-reg jcca977;
-reg al54bba;
-reg lfa5dd4;
-reg aa2eea6;
-reg yk77531;
-reg phba989;
-reg sud4c4e;
-reg wya6270;
-reg ks31380;
-reg ba89c00;
-reg sh4e003;
-reg yx7001d;
-reg kf800ec;
-reg co764;
-reg tj3b20;
-reg yz1d906;
-reg zxec834;
-reg pf641a6;
-reg ls20d37;
-reg db69ba;
-reg ym34dd6;
-reg mga6eb1;
-reg ph37589;
-reg vxbac4f;
-reg qtd627e;
-reg irb13f4;
-reg ls89fa4;
-reg vv4fd23;
-reg th7e91e;
-reg zkf48f6;
-reg wla47b3;
-reg qv23d9d;
-reg tw1eced;
-reg pff676b;
-reg swb3b5f;
-reg mg9daf8;
-reg gbed7c0;
-reg xj6be05;
-reg dz5f02f;
-reg mrf817e;
-reg vic0bf4;
-reg qi5fa3;
-reg do2fd19;
-reg zx7e8cb;
-reg vif465e;
-reg ksa32f2;
-reg vx19790;
-reg cmcbc87;
-reg wj5e438;
-reg ipf21c4;
-reg qv90e25;
-reg gq8712c;
-reg db38961;
-reg eac4b0f;
-reg ls25879;
-reg cb2c3ca;
-reg rt61e55;
-reg wyf2ae;
-reg dm79571;
-reg bycab8a;
-reg pf55c52;
-reg anae296;
-reg xj714b4;
-reg cb8a5a6;
-reg zk52d35;
-reg fc969ab;
-reg cbb4d5b;
-reg swa6add;
-reg je356e9;
-reg uxab74a;
-reg al5ba54;
-reg thdd2a5;
-reg pfe952f;
-reg rt4a97f;
-reg mr54bfe;
-reg dba5ff4;
-reg pu2ffa6;
-reg qt7fd33;
-reg byfe99c;
-reg lqf4ce2;
-reg mga6713;
-reg kf33898;
-reg ba9c4c4;
-reg ale2623;
-reg tj1311c;
-reg ec988e6;
-reg suc4730;
-reg qv23980;
-reg vx1cc05;
-reg ble602e;
-reg zm30176;
-reg sj80bb2;
-reg sw5d95;
-reg sw2eca9;
-reg ne76549;
-reg dob2a4b;
-reg yz9525a;
-reg wya92d5;
-reg su496a9;
-reg uv4b548;
-reg pf5aa45;
-reg hod522f;
-reg qia917b;
-reg xw48bd9;
-reg nr45ecb;
-reg fc2f65f;
-reg ld7b2fa;
-reg shd97d7;
-reg eacbebd;
-reg nr5f5e8;
-reg mefaf46;
-reg xjd7a30;
-reg pubd187;
-reg uve8c3a;
-reg yk461d4;
-reg pu30ea1;
-reg sw8750b;
-reg tw3a859;
-reg ykd42ca;
-reg yza1651;
-reg fcb28d;
-reg ww5946b;
-reg lqca359;
-reg uv51acb;
-reg mg8d65c;
-reg zx6b2e0;
-reg me59706;
-reg iccb831;
-reg qg5c188;
-reg ose0c41;
-reg bn6208;
-reg mg31047;
-reg qi88238;
-reg en411c0;
-reg ir8e04;
-reg vi47025;
-reg tj3812b;
-reg zkc095e;
-reg xy4af3;
-reg hq2579b;
-reg ym2bcdb;
-reg kd5e6d9;
-reg rtf36cc;
-reg lf9b667;
-reg wwdb33e;
-reg ipd99f0;
-reg alccf84;
-reg ic67c25;
-reg gq3e129;
-reg cmf0949;
-reg vx84a49;
-reg ri2524f;
-reg cb2927b;
-reg os493dd;
-reg me49ee8;
-reg dz4f741;
-reg jp7ba0f;
-reg zxdd07e;
-reg kde83f7;
-reg cz41fbd;
-reg ukfded;
-reg ld7ef68;
-reg off7b46;
-reg hqbda34;
-reg mred1a3;
-reg qg68d1d;
-reg su468e8;
-reg ou34740;
-reg gqa3a00;
-reg sj1d001;
-reg gbe800d;
-reg xj4006d;
-reg co36e;
-reg ri1b70;
-reg [2047:0] ls351cf;
-wire [306:0] jea8e7a;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-localparam ps473d2 = 307,wl39e93 = 32'hfdffc68b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-AND2 mececb4 (.A(yzbbd6d), .B(fcb2d03), .Z(ng9681a)); INV ohb40d3 (.A(jra069c), .Z(fcb2d03)); AND2 ks1a73f (.A(medeb6c), .B(ls9cfc5), .Z(yxe7e2a)); INV fc3f155 (.A(wjf8aab), .Z(ls9cfc5)); OR2 je2aaea (.A(icf5b61), .B(puadb09), .Z(zk5d4fd)); XOR2 icea7eb (.A(go53f58), .B(kf9fac1), .Z(uvfd60d)); XOR2 hoeb06c (.A(kf9fac1), .B(icc1b13), .Z(sjd899)); XOR2 xw6c4cd (.A(icc1b13), .B(tj13358), .Z(fc99ac6)); XOR2 dzcd632 (.A(tj13358), .B(jc58cb6), .Z(ipc65b2)); XOR2 tj32d95 (.A(jc58cb6), .B(ymb6573), .Z(ngb2b99)); XOR2 an95cca (.A(ymb6573), .B(xw732a4), .Z(fc99523)); XOR2 faca91b (.A(xw732a4), .B(oha46d4), .Z(ep236a5)); XOR2 xy1b52c (.A(oha46d4), .B(god4b13), .Z(hda5898)); XOR2 wl2c4c6 (.A(god4b13), .B(hd131a8), .Z(mg98d46)); XOR2 gbc6a30 (.A(hd131a8), .B(baa8c22), .Z(cm46112)); XOR2 vk30891 (.A(rv8448b), .B(jr2245e), .Z(mt122f6)); XOR2 db917b4 (.A(jr2245e), .B(gb5ed3e), .Z(pff69f5)); XOR2 qvb4fae (.A(gb5ed3e), .B(co3ebab), .Z(suf5d58)); XOR2 sjaeac1 (.A(co3ebab), .B(irab06c), .Z(ho58364)); XOR2 uic1b23 (.A(irab06c), .B(lq6c8cd), .Z(hb6466a)); XOR2 an23357 (.A(lq6c8cd), .B(ldcd5e6), .Z(qt6af36)); XOR2 xw579b5 (.A(ldcd5e6), .B(rte6d59), .Z(cb36acf)); XOR2 rvb567c (.A(rte6d59), .B(qg59f34), .Z(lqcf9a0)); XOR2 ps7cd02 (.A(qg59f34), .B(mg3409f), .Z(tja04f8)); XOR2 sj27c7 (.A(mg3409f), .B(an9f1ef), .Z(off8f7c)); defparam rtc7be5.initval = 16'h6996 ; ROM16X1A rtc7be5 (.AD3(ayef977), .AD2(zk7cbb9), .AD1(yke5dcb), .AD0(aa2ee58), .DO0(yk772c1)); defparam mgb9609.initval = 16'h6996 ; ROM16X1A mgb9609 (.AD3(ne58241), .AD2(qgc120b), .AD1(bn9058), .AD0(ne482c6), .DO0(gb41632)); defparam xyb194.initval = 16'h6996 ; ROM16X1A xyb194 (.AD3(yke5dcb), .AD2(aa2ee58), .AD1(hd946ae), .AD0(hd946ae), .DO0(ou1abb8)); defparam zkd5dc1.initval = 16'h6996 ; ROM16X1A zkd5dc1 (.AD3(zk7cbb9), .AD2(yke5dcb), .AD1(aa2ee58), .AD0(hd946ae), .DO0(vv55280)); defparam yma9407.initval = 16'h6996 ; ROM16X1A yma9407 (.AD3(ne482c6), .AD2(ayef977), .AD1(zk7cbb9), .AD0(ou1abb8), .DO0(xwcff6d)); defparam ip7fb6a.initval = 16'h6996 ; ROM16X1A ip7fb6a (.AD3(bn9058), .AD2(ne482c6), .AD1(ayef977), .AD0(vv55280), .DO0(nta586c)); defparam sj2c366.initval = 16'h6996 ; ROM16X1A sj2c366 (.AD3(qgc120b), .AD2(bn9058), .AD1(ne482c6), .AD0(yk772c1), .DO0(wlaea9b)); defparam uv754dd.initval = 16'h6996 ; ROM16X1A uv754dd (.AD3(yk772c1), .AD2(gb41632), .AD1(hd946ae), .AD0(hd946ae), .DO0(dm661f6)); defparam pu30fb2.initval = 16'h6996 ; ROM16X1A pu30fb2 (.AD3(yk772c1), .AD2(gb41632), .AD1(dob2607), .AD0(hd946ae), .DO0(qi981da)); defparam psc0ed1.initval = 16'h6996 ; ROM16X1A psc0ed1 (.AD3(yk772c1), .AD2(gb41632), .AD1(sud174a), .AD0(dob2607), .DO0(dm5d28e)); defparam rte9473.initval = 16'h6996 ; ROM16X1A rte9473 (.AD3(of51cff), .AD2(sud174a), .AD1(dob2607), .AD0(hd946ae), .DO0(ykff9d5)); defparam pffcea8.initval = 16'h6996 ; ROM16X1A pffcea8 (.AD3(yk772c1), .AD2(gb41632), .AD1(ykff9d5), .AD0(hd946ae), .DO0(ep3c4d2)); defparam kde2694.initval = 16'h6996 ; ROM16X1A kde2694 (.AD3(wl9a526), .AD2(jpd2934), .AD1(jr949a7), .AD0(epa4d3e), .DO0(yz269f4)); defparam ec34fa5.initval = 16'h6996 ; ROM16X1A ec34fa5 (.AD3(ou3e94b), .AD2(lqf4a58), .AD1(pha52c3), .AD0(mt2961f), .DO0(sh4b0fd)); defparam xw587ed.initval = 16'h6996 ; ROM16X1A xw587ed (.AD3(jr949a7), .AD2(epa4d3e), .AD1(hd946ae), .AD0(hd946ae), .DO0(os5c36f)); defparam zke1b79.initval = 16'h6996 ; ROM16X1A zke1b79 (.AD3(jpd2934), .AD2(jr949a7), .AD1(epa4d3e), .AD0(hd946ae), .DO0(nr55112)); defparam nga8897.initval = 16'h6996 ; ROM16X1A nga8897 (.AD3(mt2961f), .AD2(wl9a526), .AD1(jpd2934), .AD0(os5c36f), .DO0(wwd4d46)); defparam coa6a30.initval = 16'h6996 ; ROM16X1A coa6a30 (.AD3(pha52c3), .AD2(mt2961f), .AD1(wl9a526), .AD0(nr55112), .DO0(iea456)); defparam vi522b1.initval = 16'h6996 ; ROM16X1A vi522b1 (.AD3(lqf4a58), .AD2(pha52c3), .AD1(mt2961f), .AD0(yz269f4), .DO0(fa57824)); defparam aabc123.initval = 16'h6996 ; ROM16X1A aabc123 (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(hd946ae), .AD0(hd946ae), .DO0(xwc0665)); defparam fp332a.initval = 16'h6996 ; ROM16X1A fp332a (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(xy2afad), .AD0(hd946ae), .DO0(wlbeb5b)); defparam wwf5adc.initval = 16'h6996 ; ROM16X1A wwf5adc (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(wjdc2f5), .AD0(xy2afad), .DO0(fcbd6b)); defparam uv5eb5a.initval = 16'h6996 ; ROM16X1A uv5eb5a (.AD3(hqad6a9), .AD2(wjdc2f5), .AD1(xy2afad), .AD0(hd946ae), .DO0(uka97bb)); defparam en4bdd9.initval = 16'h6996 ; ROM16X1A en4bdd9 (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(uka97bb), .AD0(hd946ae), .DO0(of65b65)); XOR2 bn2db2c (.A(baa8c22), .B(epa4d3e), .Z(gb65982)); XOR2 oh2cc14 (.A(aa2ee58), .B(an9f1ef), .Z(ou82912)); defparam je14890.initval = 16'h0410 ; ROM16X1A je14890 (.AD3(db22415), .AD2(an9f1ef), .AD1(aa2ee58), .AD0(hd946ae), .DO0(ks15d28)); defparam mtae940.initval = 16'h1004 ; ROM16X1A mtae940 (.AD3(db22415), .AD2(an9f1ef), .AD1(aa2ee58), .AD0(hd946ae), .DO0(je2fff9)); defparam uv7ffcb.initval = 16'h0140 ; ROM16X1A uv7ffcb (.AD3(ykff2e0), .AD2(baa8c22), .AD1(epa4d3e), .AD0(hd946ae), .DO0(yke0381)); defparam fc1c09.initval = 16'h4001 ; ROM16X1A fc1c09 (.AD3(ykff2e0), .AD2(baa8c22), .AD1(epa4d3e), .AD0(hd946ae), .DO0(of5b9b5)); INV aldcdad (.A(mrf7047), .Z(yz29b02)); AND2 tjb5b3c (.A(tuee7bc), .B(yz29b02), .Z(ui679d2)); AND2 an3ce91 (.A(tuee7bc), .B(mrf7047), .Z(hbd2363)); defparam ph91b1e.CSDECODE_B = "0b000" ; defparam ph91b1e.CSDECODE_A = "0b000" ; defparam ph91b1e.WRITEMODE_B = "NORMAL" ; defparam ph91b1e.WRITEMODE_A = "NORMAL" ; defparam ph91b1e.GSR = "ENABLED" ; defparam ph91b1e.REGMODE_B = "NOREG" ; defparam ph91b1e.REGMODE_A = "NOREG" ; defparam ph91b1e.DATA_WIDTH_B = 18 ; defparam ph91b1e.DATA_WIDTH_A = 18 ; DP16KC ph91b1e (.DIA0(wlabdde[0]), .DIA1(wlabdde[1]), .DIA2(wlabdde[2]), .DIA3(wlabdde[3]), .DIA4(wlabdde[4]), .DIA5(wlabdde[5]), .DIA6(wlabdde[6]), .DIA7(wlabdde[7]), .DIA8(wlabdde[8]), .DIA9(wlabdde[9]), .DIA10(wlabdde[10]), .DIA11(wlabdde[11]), .DIA12(wlabdde[12]), .DIA13(wlabdde[13]), .DIA14(wlabdde[14]), .DIA15(wlabdde[15]), .DIA16(wlabdde[16]), .DIA17(wlabdde[17]), .ADA0(ba1ecef), .ADA1(ba1ecef), .ADA2(hd946ae), .ADA3(hd946ae), .ADA4(meef7c0), .ADA5(pf7be00), .ADA6(tudf006), .ADA7(kdf8032), .ADA8(fac0194), .ADA9(ouca2), .ADA10(ph6511), .ADA11(xl3288f), .ADA12(db9447e), .ADA13(lsa23f7), .CEA(ng9681a), .CLKA(uv5eef5), .OCEA(ng9681a), .WEA(ba1ecef), .CSA0(hd946ae), .CSA1(hd946ae), .CSA2(hd946ae), .RSTA(icf5b61), .DIB0(hd946ae), .DIB1(hd946ae), .DIB2(hd946ae), .DIB3(hd946ae), .DIB4(hd946ae), .DIB5(hd946ae), .DIB6(hd946ae), .DIB7(hd946ae), .DIB8(hd946ae), .DIB9(hd946ae), .DIB10(hd946ae), .DIB11(hd946ae), .DIB12(hd946ae), .DIB13(hd946ae), .DIB14(hd946ae), .DIB15(hd946ae), .DIB16(hd946ae), .DIB17(hd946ae), .ADB0(hd946ae), .ADB1(hd946ae), .ADB2(hd946ae), .ADB3(hd946ae), .ADB4(al7fc5f), .ADB5(dmfe2fc), .ADB6(faf17e3), .ADB7(ph8bf1a), .ADB8(xj5f8d6), .ADB9(vvfc6b7), .ADB10(rte35be), .ADB11(wy1adf6), .ADB12(mrd6fb1), .ADB13(fcb7d8d), .CEB(yxe7e2a), .CLKB(wjf77ad), .OCEB(yxe7e2a), .WEB(hd946ae), .CSB0(hd946ae), .CSB1(hd946ae), .CSB2(hd946ae), .RSTB(icf5b61), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOA9(), .DOA10(), .DOA11(), .DOA12(), .DOA13(), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(dz61283[0]), .DOB1(dz61283[1]), .DOB2(dz61283[2]), .DOB3(dz61283[3]), .DOB4(dz61283[4]), .DOB5(dz61283[5]), .DOB6(dz61283[6]), .DOB7(dz61283[7]), .DOB8(dz61283[8]), .DOB9(dz61283[9]), .DOB10(dz61283[10]), .DOB11(dz61283[11]), .DOB12(dz61283[12]), .DOB13(dz61283[13]), .DOB14(dz61283[14]), .DOB15(dz61283[15]), .DOB16(dz61283[16]), .DOB17(dz61283[17]))
- ; FD1P3BX hd19c3f (.D(gb44fd5), .SP(ng9681a), .CK(uv5eef5), .PD(icf5b61), .Q(go53f58)) ; FD1P3DX jcf1a13 (.D(zx7b094), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(kf9fac1)) ; FD1P3DX ldd82f6 (.D(qgffb9a), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(icc1b13)) ; FD1P3DX hqb8573 (.D(hq2a714), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tj13358)) ; FD1P3DX ipd611d (.D(db8bad3), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(jc58cb6)) ; FD1P3DX su67d66 (.D(kf9ad77), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ymb6573)) ; FD1P3DX mg88210 (.D(mr6fa1c), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(xw732a4)) ; FD1P3DX hq48cd (.D(dz4518e), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(oha46d4)) ; FD1P3DX ic599b6 (.D(cbb1391), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(god4b13)) ; FD1P3DX wl8570f (.D(ir1d393), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(hd131a8)) ; FD1P3DX xwe1282 (.D(al752c3), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(baa8c22)) ; FD1P3DX jr9efcf (.D(uvfd60d), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(pu3a9c4)) ; FD1P3DX thfcfd4 (.D(sjd899), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(gq82e31)) ; FD1P3DX hd3d603 (.D(fc99ac6), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ep23a0c)) ; FD1P3DX mrf26b2 (.D(ipc65b2), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(os6dbe6)) ; FD1P3DX bnaab15 (.D(ngb2b99), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ks5795)) ; FD1P3DX jp7e247 (.D(fc99523), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tjc95d)) ; FD1P3DX ykfa4d3 (.D(ep236a5), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(thf328f)) ; FD1P3DX icce522 (.D(hda5898), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(godb92b)) ; FD1P3DX ym88d73 (.D(mg98d46), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ea62604)) ; FD1P3DX fnc871b (.D(cm46112), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(co31697)) ; FD1P3DX osf0f98 (.D(baa8c22), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ou3ee1e)) ; FD1P3DX hq113f (.D(go53f58), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(meef7c0)) ; FD1P3DX fcadec2 (.D(kf9fac1), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(pf7be00)) ; FD1P3DX lsa7fee (.D(icc1b13), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tudf006)) ; FD1P3DX jcd0a9c (.D(tj13358), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(kdf8032)) ; FD1P3DX fca22eb (.D(jc58cb6), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(fac0194)) ; FD1P3DX xl9e6b5 (.D(ymb6573), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ouca2)) ; FD1P3DX jebdbe8 (.D(xw732a4), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ph6511)) ; FD1P3DX wwe5146 (.D(oha46d4), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(xl3288f)) ; FD1P3DX zk76c4e (.D(god4b13), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(db9447e)) ; FD1P3DX pu8c74e (.D(hd131a8), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(lsa23f7)) ; FD1P3DX aa9dd4b (.D(baa8c22), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ykff2e0)) ; FD1P3BX tj1c35c (.D(ph133cc), .SP(yxe7e2a), .CK(wjf77ad), .PD(zk5d4fd), .Q(rv8448b)) ; FD1P3DX sud4e22 (.D(ba93757), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(jr2245e)) ; FD1P3DX yz17188 (.D(tjbf2b7), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(gb5ed3e)) ; FD1P3DX cb1d065 (.D(czf22b3), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(co3ebab)) ; FD1P3DX cm6df30 (.D(lq7c001), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(irab06c)) ; FD1P3DX co2bca8 (.D(ym8808d), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(lq6c8cd)) ; FD1P3DX hb64aef (.D(tw35400), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ldcd5e6)) ; FD1P3DX zm9947f (.D(pub7827), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(rte6d59)) ; FD1P3DX ofdc959 (.D(qv8079b), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qg59f34)) ; FD1P3DX zz13020 (.D(zz32fe6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(mg3409f)) ; FD1P3DX rv8b4b8 (.D(nt8efed), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(an9f1ef)) ; FD1P3DX mrf70f0 (.D(mt122f6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(tw354c3)) ; FD1P3DX yx54463 (.D(pff69f5), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(jrb034c)) ; FD1P3DX by524e8 (.D(suf5d58), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(gqbc45e)) ; FD1P3DX je83359 (.D(ho58364), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qv23d0e)) ; FD1P3DX rtf6c45 (.D(hb6466a), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ld5a8a4)) ; FD1P3DX ri8c3c7 (.D(qt6af36), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qgcb534)) ; FD1P3DX kfb13d4 (.D(cb36acf), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(me78221)) ; FD1P3DX uk1f82d (.D(lqcf9a0), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(sw5867)) ; FD1P3DX kd703d5 (.D(tja04f8), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(vv6ee2f)) ; FD1P3DX qv39880 (.D(off8f7c), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qgcb6ee)) ; FD1P3DX al6034d (.D(an9f1ef), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ld61cba)) ; FD1P3DX su5c4cf (.D(rv8448b), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(al7fc5f)) ; FD1P3DX lq664dd (.D(jr2245e), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(dmfe2fc)) ; FD1P3DX xlbafca (.D(gb5ed3e), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(faf17e3)) ; FD1P3DX rvbfc8a (.D(co3ebab), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ph8bf1a)) ; FD1P3DX gq9df00 (.D(irab06c), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(xj5f8d6)) ; FD1P3DX qia202 (.D(lq6c8cd), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(vvfc6b7)) ; FD1P3DX me68d50 (.D(ldcd5e6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(rte35be)) ; FD1P3DX wl2de0 (.D(rte6d59), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(wy1adf6)) ; FD1P3DX pu3a01e (.D(qg59f34), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(mrd6fb1)) ; FD1P3DX kddccbf (.D(mg3409f), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(fcb7d8d)) ; FD1P3DX yz363bf (.D(an9f1ef), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(db22415)) ; FD1S3DX bl6e1ac (.D(pu3a9c4), .CK(wjf77ad), .CD(icf5b61), .Q(ipfd144)) ; FD1S3DX xlaa61a (.D(gq82e31), .CK(wjf77ad), .CD(icf5b61), .Q(ks24da8)) ; FD1S3DX vx81a66 (.D(ep23a0c), .CK(wjf77ad), .CD(icf5b61), .Q(sw599f)) ; FD1S3DX ale22f0 (.D(os6dbe6), .CK(wjf77ad), .CD(icf5b61), .Q(wjcc527)) ; FD1S3DX tw1e875 (.D(ks5795), .CK(wjf77ad), .CD(icf5b61), .Q(hoe153c)) ; FD1S3DX ayd4527 (.D(tjc95d), .CK(wjf77ad), .CD(icf5b61), .Q(gd188e6)) ; FD1S3DX jp5a9a1 (.D(thf328f), .CK(wjf77ad), .CD(icf5b61), .Q(pha0bb8)) ; FD1S3DX uic1108 (.D(godb92b), .CK(wjf77ad), .CD(icf5b61), .Q(qi3125d)) ; FD1S3DX ux2c339 (.D(ea62604), .CK(wjf77ad), .CD(icf5b61), .Q(fa4211d)) ; FD1S3DX kq7717f (.D(co31697), .CK(wjf77ad), .CD(icf5b61), .Q(by58d6a)) ; FD1S3DX ip5b771 (.D(ou3ee1e), .CK(wjf77ad), .CD(icf5b61), .Q(lf946e3)) ; FD1S3DX bae5d6 (.D(tw354c3), .CK(uv5eef5), .CD(zk5d4fd), .Q(wjf8778))
- ; FD1S3DX lqc0d09 (.D(jrb034c), .CK(uv5eef5), .CD(zk5d4fd), .Q(aa24809)) ; FD1S3DX wwf0ba4 (.D(gqbc45e), .CK(uv5eef5), .CD(zk5d4fd), .Q(yx416b2)) ; FD1S3DX ps69f44 (.D(qv23d0e), .CK(uv5eef5), .CD(zk5d4fd), .Q(swa3f17)) ; FD1S3DX ntb093e (.D(ld5a8a4), .CK(uv5eef5), .CD(zk5d4fd), .Q(gbc9d60)) ; FD1S3DX czf8e27 (.D(qgcb534), .CK(uv5eef5), .CD(zk5d4fd), .Q(qv2ca61)) ; FD1S3DX gb7f3f9 (.D(me78221), .CK(uv5eef5), .CD(zk5d4fd), .Q(ip65837)) ; FD1S3DX al7abfc (.D(sw5867), .CK(uv5eef5), .CD(zk5d4fd), .Q(kqe59b1)) ; FD1S3DX kf179df (.D(vv6ee2f), .CK(uv5eef5), .CD(zk5d4fd), .Q(ip44761)) ; FD1S3DX go4c0e6 (.D(qgcb6ee), .CK(uv5eef5), .CD(zk5d4fd), .Q(gb659f7)) ; FD1S3DX gq2ed9d (.D(ld61cba), .CK(uv5eef5), .CD(zk5d4fd), .Q(lqe4221)) ; FD1S3DX gb5107f (.D(ipfd144), .CK(wjf77ad), .CD(icf5b61), .Q(of51cff)) ; FD1S3DX qte8a24 (.D(ks24da8), .CK(wjf77ad), .CD(icf5b61), .Q(sud174a)) ; FD1S3DX ux26d40 (.D(sw599f), .CK(wjf77ad), .CD(icf5b61), .Q(dob2607)) ; FD1S3DX ux2ccf9 (.D(wjcc527), .CK(wjf77ad), .CD(icf5b61), .Q(ne58241)) ; FD1S3DX yk6293c (.D(hoe153c), .CK(wjf77ad), .CD(icf5b61), .Q(qgc120b)) ; FD1S3DX yma9e3 (.D(gd188e6), .CK(wjf77ad), .CD(icf5b61), .Q(bn9058)) ; FD1S3DX icc4734 (.D(pha0bb8), .CK(wjf77ad), .CD(icf5b61), .Q(ne482c6)) ; FD1S3DX gq5dc6 (.D(qi3125d), .CK(wjf77ad), .CD(icf5b61), .Q(ayef977)) ; FD1S3DX xy892e8 (.D(fa4211d), .CK(wjf77ad), .CD(icf5b61), .Q(zk7cbb9)) ; FD1S3DX sw108eb (.D(by58d6a), .CK(wjf77ad), .CD(icf5b61), .Q(yke5dcb)) ; FD1S3DX wjc6b52 (.D(lf946e3), .CK(wjf77ad), .CD(icf5b61), .Q(aa2ee58)) ; FD1S3DX wya371f (.D(wjf8778), .CK(uv5eef5), .CD(zk5d4fd), .Q(hqad6a9)) ; FD1S3DX yxc3bc4 (.D(aa24809), .CK(uv5eef5), .CD(zk5d4fd), .Q(wjdc2f5)) ; FD1S3DX qi24048 (.D(yx416b2), .CK(uv5eef5), .CD(zk5d4fd), .Q(xy2afad)) ; FD1S3DX lsb594 (.D(swa3f17), .CK(uv5eef5), .CD(zk5d4fd), .Q(ou3e94b)) ; FD1S3DX ie1f8b9 (.D(gbc9d60), .CK(uv5eef5), .CD(zk5d4fd), .Q(lqf4a58)) ; FD1S3DX gb4eb05 (.D(qv2ca61), .CK(uv5eef5), .CD(zk5d4fd), .Q(pha52c3)) ; FD1S3DX uv6530c (.D(ip65837), .CK(uv5eef5), .CD(zk5d4fd), .Q(mt2961f)) ; FD1S3DX ep2c1bc (.D(kqe59b1), .CK(uv5eef5), .CD(zk5d4fd), .Q(wl9a526)) ; FD1S3DX ux2cd88 (.D(ip44761), .CK(uv5eef5), .CD(zk5d4fd), .Q(jpd2934)) ; FD1S3DX oh23b0c (.D(gb659f7), .CK(uv5eef5), .CD(zk5d4fd), .Q(jr949a7)) ; FD1S3DX oh2cfbc (.D(lqe4221), .CK(uv5eef5), .CD(zk5d4fd), .Q(epa4d3e)) ; FD1S3DX ec2110b (.D(zkda5dd), .CK(uv5eef5), .CD(icf5b61), .Q(kf85586)) ; FD1S3DX thcd858 (.D(mtbb4bb), .CK(uv5eef5), .CD(icf5b61), .Q(do2ac34)) ; FD1S3DX ou3bed7 (.D(lf27299), .CK(uv5eef5), .CD(icf5b61), .Q(fpb0d18)) ; FD1S3DX zxc26f2 (.D(uic4e53), .CK(uv5eef5), .CD(icf5b61), .Q(ri868c7)) ; FD1S3DX cbbee21 (.D(hbc2185), .CK(uv5eef5), .CD(icf5b61), .Q(uka31d0)) ; FD1S3DX en65607 (.D(sj18430), .CK(uv5eef5), .CD(icf5b61), .Q(wl18e80)) ; FD1S3DX yxe86e6 (.D(thdd42b), .CK(uv5eef5), .CD(icf5b61), .Q(zm3a027)) ; FD1S3DX yma973a (.D(ng1ba85), .CK(uv5eef5), .CD(icf5b61), .Q(zkd013b)) ; FD1S3DX zm8c118 (.D(yza1d60), .CK(uv5eef5), .CD(icf5b61), .Q(ba4edd)) ; FD1S3DX do1452e (.D(qi343ac), .CK(uv5eef5), .CD(icf5b61), .Q(ph276eb)) ; FD1S3DX jr9b583 (.D(ym15317), .CK(uv5eef5), .CD(icf5b61), .Q(cmdbaf1)) ; FD1S3DX xjf3992 (.D(fp6cf4), .CK(wjf77ad), .CD(zk5d4fd), .Q(ba898cd)) ; FD1S3DX vkb2dca (.D(ip60d9e), .CK(wjf77ad), .CD(zk5d4fd), .Q(qg4c66b)) ; FD1S3DX hq9361a (.D(mg3b293), .CK(wjf77ad), .CD(zk5d4fd), .Q(rv19ac2)) ; FD1S3DX do96f47 (.D(by47652), .CK(wjf77ad), .CD(zk5d4fd), .Q(vvcd616)) ; FD1S3DX vida519 (.D(vvd25b6), .CK(wjf77ad), .CD(zk5d4fd), .Q(rg585b6)) ; FD1S3DX xw57e3a (.D(rt5a4b6), .CK(wjf77ad), .CD(zk5d4fd), .Q(zxc2db3)) ; FD1S3DX cb9fbdd (.D(hoc033b), .CK(wjf77ad), .CD(zk5d4fd), .Q(ymb6cf7)) ; FD1S3DX ay6d1b4 (.D(ps58067), .CK(wjf77ad), .CD(zk5d4fd), .Q(ieb67b8)) ; FD1S3DX kf8125 (.D(mec1564), .CK(wjf77ad), .CD(zk5d4fd), .Q(jr9ee08)) ; FD1S3DX kq67614 (.D(pfe6d6c), .CK(wjf77ad), .CD(zk5d4fd), .Q(mrf7047)) ; FD1S3DX ls1f9f (.D(zmad9e7), .CK(wjf77ad), .CD(zk5d4fd), .Q(tuee7bc)) ; FD1S3BX rtd8fa3 (.D(mg3e8f6), .CK(wjf77ad), .PD(zk5d4fd), .Q(wjf8aab)) ; FD1S3DX vvf608b (.D(ec822fe), .CK(uv5eef5), .CD(icf5b61), .Q(jra069c)) ; FD1S3BX jcfe2f7 (.D(jr8bdda), .CK(wjf77ad), .PD(zk5d4fd), .Q(hb507f7)) ; FD1S3DX vidad6d (.D(vxb5b5d), .CK(uv5eef5), .CD(icf5b61), .Q(ri83fbf)) ; FADD2B me530f4 (.A0(hd946ae), .A1(ba1ecef), .B0(hd946ae), .B1(ba1ecef), .CI(hd946ae), .COUT(je18d7), .S0(), .S1()); CU2 xw5de8f (.CI(je18d7), .PC0(go53f58), .PC1(kf9fac1), .CO(cb8f428), .NC0(gb44fd5), .NC1(zx7b094)); CU2 oh8516a (.CI(cb8f428), .PC0(icc1b13), .PC1(tj13358), .CO(kd6a9bf), .NC0(qgffb9a), .NC1(hq2a714)); CU2 hd37f61 (.CI(kd6a9bf), .PC0(jc58cb6), .PC1(ymb6573), .CO(dz61daf), .NC0(db8bad3), .NC1(kf9ad77)); CU2 ntb5f92 (.CI(dz61daf), .PC0(xw732a4), .PC1(oha46d4), .CO(mg92ffd), .NC0(mr6fa1c), .NC1(dz4518e)); CU2 osffa4e (.CI(mg92ffd), .PC0(god4b13), .PC1(hd131a8), .CO(kd4e139), .NC0(cbb1391), .NC1(ir1d393)); CU2 jr2736f (.CI(kd4e139), .PC0(baa8c22), .PC1(hd946ae), .CO(uv6fd78), .NC0(al752c3), .NC1()); FADD2B ng30277 (.A0(hd946ae), .A1(ba1ecef), .B0(hd946ae), .B1(ba1ecef), .CI(hd946ae), .COUT(kdd6f0e), .S0(), .S1()); CU2 qgf5e2e (.CI(kdd6f0e), .PC0(rv8448b), .PC1(jr2245e), .CO(qi2e38b), .NC0(ph133cc), .NC1(ba93757)); CU2 rt7163f (.CI(qi2e38b), .PC0(gb5ed3e), .PC1(co3ebab), .CO(ri3fdd6), .NC0(tjbf2b7), .NC1(czf22b3)); CU2 phbac95 (.CI(ri3fdd6), .PC0(irab06c), .PC1(lq6c8cd), .CO(ep95d19), .NC0(lq7c001), .NC1(ym8808d)); CU2 qia332e (.CI(ep95d19), .PC0(ldcd5e6), .PC1(rte6d59), .CO(ym2e1ac), .NC0(tw35400), .NC1(pub7827)); CU2 tw3582a (.CI(ym2e1ac), .PC0(qg59f34), .PC1(mg3409f), .CO(pu2a660), .NC0(qv8079b), .NC1(zz32fe6)); CU2 yxcc082 (.CI(pu2a660), .PC0(an9f1ef), .PC1(hd946ae), .CO(ym82969), .NC0(nt8efed), .NC1()); FSUB2B vxa5a42 (.A0(ba1ecef), .A1(go53f58), .B0(hd946ae), .B1(of65b65), .BI(hd946ae), .BOUT(bab7697), .S0(), .S1(zkda5dd)); FSUB2B hbd2eea (.A0(kf9fac1), .A1(icc1b13), .B0(fcbd6b), .B1(wlbeb5b), .BI(bab7697), .BOUT(fcb89ca), .S0(mtbb4bb), .S1(lf27299)); FSUB2B cb394ce (.A0(tj13358), .A1(jc58cb6), .B0(xwc0665), .B1(fa57824), .BI(fcb89ca), .BOUT(aaa3086), .S0(uic4e53), .S1(hbc2185)); FSUB2B ie10c2f (.A0(ymb6573), .A1(xw732a4), .B0(iea456), .B1(wwd4d46), .BI(aaa3086), .BOUT(ofc3750), .S0(sj18430), .S1(thdd42b)); FSUB2B meea15f (.A0(oha46d4), .A1(god4b13), .B0(yz269f4), .B1(nr55112), .BI(ofc3750), .BOUT(czc6875), .S0(ng1ba85), .S1(yza1d60)); FSUB2B baeb04 (.A0(hd131a8), .A1(gb65982), .B0(os5c36f), .B1(hd946ae), .BI(czc6875), .BOUT(ui4cc84), .S0(qi343ac), .S1(ym15317)); FADD2B icd45c5 (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(ui4cc84), .COUT(), .S0(an29990), .S1()); VHI wya98b9 (.Z(ba1ecef)); FSUB2B me62e40 (.A0(ba1ecef), .A1(ep3c4d2), .B0(hd946ae), .B1(rv8448b), .BI(hd946ae), .BOUT(xlc1b3), .S0(), .S1(fp6cf4)); FSUB2B qv367a6 (.A0(dm5d28e), .A1(qi981da), .B0(jr2245e), .B1(gb5ed3e), .BI(xlc1b3), .BOUT(ria8eca), .S0(ip60d9e), .S1(mg3b293)); FSUB2B ald9499 (.A0(dm661f6), .A1(wlaea9b), .B0(co3ebab), .B1(irab06c), .BI(ria8eca), .BOUT(jp6b496), .S0(by47652), .S1(vvd25b6)); FSUB2B uk92db6 (.A0(nta586c), .A1(xwcff6d), .B0(lq6c8cd), .B1(ldcd5e6), .BI(jp6b496),
- .BOUT(rv8b00c), .S0(rt5a4b6), .S1(hoc033b)); FSUB2B fc19da (.A0(yk772c1), .A1(vv55280), .B0(rte6d59), .B1(qg59f34), .BI(rv8b00c), .BOUT(yz9f055), .S0(ps58067), .S1(mec1564)); FSUB2B swab20 (.A0(ou1abb8), .A1(ou82912), .B0(mg3409f), .B1(hd946ae), .BI(yz9f055), .BOUT(hq8c8df), .S0(pfe6d6c), .S1(zmad9e7)); FADD2B epb4ced (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(hq8c8df), .COUT(), .S0(hb7191b), .S1()); FADD2B aa5bd (.A0(hd946ae), .A1(yxe7e2a), .B0(hd946ae), .B1(yxe7e2a), .CI(hd946ae), .COUT(wj44e94), .S0(), .S1()); AGEB2 ri30ecf (.A0(rv8448b), .A1(jr2245e), .B0(ep3c4d2), .B1(dm5d28e), .CI(wj44e94), .GE(wjd931f)); AGEB2 mrc98fd (.A0(gb5ed3e), .A1(co3ebab), .B0(qi981da), .B1(dm661f6), .CI(wjd931f), .GE(go6866d)); AGEB2 ui43369 (.A0(irab06c), .A1(lq6c8cd), .B0(wlaea9b), .B1(nta586c), .CI(go6866d), .GE(ip4ee59)); AGEB2 qg772cc (.A0(ldcd5e6), .A1(rte6d59), .B0(xwcff6d), .B1(yk772c1), .CI(ip4ee59), .GE(cb8227)); AGEB2 wj4113c (.A0(qg59f34), .A1(mg3409f), .B0(vv55280), .B1(ou1abb8), .CI(cb8227), .GE(zm25bea)); AGEB2 lf2df52 (.A0(ks15d28), .A1(hd946ae), .B0(je2fff9), .B1(hd946ae), .CI(zm25bea), .GE(lfb501b)); FADD2B jea80de (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(lfb501b), .COUT(), .S0(mg3e8f6), .S1()); FADD2B ic67b2e (.A0(hd946ae), .A1(ng9681a), .B0(hd946ae), .B1(ng9681a), .CI(hd946ae), .COUT(mt8fd07), .S0(), .S1()); AGEB2 ipf7637 (.A0(go53f58), .A1(kf9fac1), .B0(of65b65), .B1(fcbd6b), .CI(mt8fd07), .GE(wjedd33)); AGEB2 rt6e99c (.A0(icc1b13), .A1(tj13358), .B0(wlbeb5b), .B1(xwc0665), .CI(wjedd33), .GE(je3f115)); AGEB2 czf88ab (.A0(jc58cb6), .A1(ymb6573), .B0(fa57824), .B1(iea456), .CI(je3f115), .GE(cze8e6b)); AGEB2 lq4735c (.A0(xw732a4), .A1(oha46d4), .B0(wwd4d46), .B1(yz269f4), .CI(cze8e6b), .GE(kf1ddcf)); AGEB2 pseee7c (.A0(god4b13), .A1(hd131a8), .B0(nr55112), .B1(os5c36f), .CI(kf1ddcf), .GE(vx19296)); AGEB2 enc94b7 (.A0(yke0381), .A1(hd946ae), .B0(of5b9b5), .B1(hd946ae), .CI(vx19296), .GE(ofe76d1)); FADD2B ym3b68c (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(ofe76d1), .COUT(), .S0(ec822fe), .S1()); FADD2B shed6e6 (.A0(hd946ae), .A1(yxe7e2a), .B0(hd946ae), .B1(yxe7e2a), .CI(hd946ae), .COUT(mtaeb3b), .S0(), .S1()); AGEB2 ho420bc (.A0(kq6d84a[0]), .A1(kq6d84a[1]), .B0(ba898cd), .B1(qg4c66b), .CI(mtaeb3b), .GE(db19146)); AGEB2 rtc8a37 (.A0(kq6d84a[2]), .A1(kq6d84a[3]), .B0(rv19ac2), .B1(vvcd616), .CI(db19146), .GE(nefec36)); AGEB2 fnf61b2 (.A0(kq6d84a[4]), .A1(kq6d84a[5]), .B0(rg585b6), .B1(zxc2db3), .CI(nefec36), .GE(fpbf551)); AGEB2 uifaa8f (.A0(kq6d84a[6]), .A1(kq6d84a[7]), .B0(ymb6cf7), .B1(ieb67b8), .CI(fpbf551), .GE(shc3d28)); AGEB2 pu1e944 (.A0(kq6d84a[8]), .A1(kq6d84a[9]), .B0(jr9ee08), .B1(mrf7047), .CI(shc3d28), .GE(fc1bfa4)); AGEB2 fadfd23 (.A0(hbd2363), .A1(hd946ae), .B0(ui679d2), .B1(hd946ae), .CI(fc1bfa4), .GE(vida762)); FADD2B ald3b12 (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(vida762), .COUT(), .S0(jr8bdda), .S1()); FADD2B qg72dd6 (.A0(hd946ae), .A1(ng9681a), .B0(hd946ae), .B1(ng9681a), .CI(hd946ae), .COUT(tw837a6), .S0(), .S1()); AGEB2 vi4716a (.A0(kf85586), .A1(do2ac34), .B0(xw6c250[0]), .B1(xw6c250[1]), .CI(tw837a6), .GE(ep9f7e1)); AGEB2 tufbf0c (.A0(fpb0d18), .A1(ri868c7), .B0(xw6c250[2]), .B1(xw6c250[3]), .CI(ep9f7e1), .GE(tj13cb0)); AGEB2 lf9e587 (.A0(uka31d0), .A1(wl18e80), .B0(xw6c250[4]), .B1(xw6c250[5]), .CI(tj13cb0), .GE(nef45c0)); AGEB2 zma2e02 (.A0(zm3a027), .A1(zkd013b), .B0(xw6c250[6]), .B1(xw6c250[7]), .CI(nef45c0), .GE(vk9c4af)); AGEB2 ene257b (.A0(ba4edd), .A1(ph276eb), .B0(xw6c250[8]), .B1(xw6c250[9]), .CI(vk9c4af), .GE(wwe59b4)); AGEB2 mt2cda0 (.A0(cmdbaf1), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(wwe59b4), .GE(qv23932)); VLO vx1c995 (.Z(hd946ae)); FADD2B kf26572 (.A0(hd946ae), .A1(hd946ae), .B0(hd946ae), .B1(hd946ae), .CI(qv23932), .COUT(), .S0(vxb5b5d), .S1()); assign vx941f = kd4babb; assign th4a0fe = ho5d5dc;
-
-always@* begin ng14a7f<={wlabdde>>1,jea8e7a[0]};lfa53fa<=jea8e7a[1];gd29fd7<=jea8e7a[2];th4febc<=jea8e7a[3];cz7f5e6<=jea8e7a[4];wwfaf35<=jea8e7a[5];zxd79a8<=jea8e7a[6];ecbcd47<={kq6d84a>>1,jea8e7a[7]};pfe6a39<={xw6c250>>1,jea8e7a[8]};qgf59ea<=jea8e7a[9];aaacf51<=jea8e7a[10];ui67a88<=jea8e7a[11];bn3d441<=jea8e7a[12];kqea20e<=jea8e7a[13];yx51070<=jea8e7a[14];wy88385<=jea8e7a[15];al41c28<=jea8e7a[16];fce145<=jea8e7a[17];yx70a2b<=jea8e7a[18];oh8515d<=jea8e7a[19];lf28aec<=jea8e7a[20];hb45766<=jea8e7a[21];ec2bb36<=jea8e7a[22];fa5d9b1<=jea8e7a[23];dzecd8a<=jea8e7a[24];tu66c56<=jea8e7a[25];sj362b3<=jea8e7a[26];sjb159d<=jea8e7a[27];oh8acec<=jea8e7a[28];me56764<=jea8e7a[29];aab3b20<=jea8e7a[30];ym9d900<=jea8e7a[31];zxec800<=jea8e7a[32];pf64006<=jea8e7a[33];ls20037<=jea8e7a[34];ec1bb<=jea8e7a[35];gqdd8<=jea8e7a[36];db6ec1<=jea8e7a[37];bn3760e<=jea8e7a[38];mtbb077<=jea8e7a[39];bld83bd<=jea8e7a[40];ykc1def<=jea8e7a[41];puef79<=jea8e7a[42];ui77bca<=jea8e7a[43];dobde50<=jea8e7a[44];eaef283<=jea8e7a[45];by79418<=jea8e7a[46];lqca0c2<=jea8e7a[47];vv50613<=jea8e7a[48];zm8309f<=jea8e7a[49];yz184fb<=jea8e7a[50];dzc27dd<=jea8e7a[51];fp13eef<=jea8e7a[52];cb9f77f<=jea8e7a[53];dmfbbfc<=jea8e7a[54];dzddfe2<=jea8e7a[55];kqeff16<=jea8e7a[56];cz7f8b1<=jea8e7a[57];vvfc58c<=jea8e7a[58];qte2c66<=jea8e7a[59];vx16335<=jea8e7a[60];wlb19ae<=jea8e7a[61];xy8cd75<=jea8e7a[62];lq66bab<=jea8e7a[63];fc35d5b<=jea8e7a[64];sjaeadb<=jea8e7a[65];of756dd<=jea8e7a[66];irab6ec<=jea8e7a[67];ip5b764<=jea8e7a[68];ykdbb24<=jea8e7a[69];dzdd921<=jea8e7a[70];nrec90e<=jea8e7a[71];xj64876<=jea8e7a[72];sw243b6<=jea8e7a[73];ie21db1<=jea8e7a[74];doed88<=jea8e7a[75];dm76c42<=jea8e7a[76];wyb6212<=jea8e7a[77];yzb1091<=jea8e7a[78];ie8848c<=jea8e7a[79];rg42460<=jea8e7a[80];mt12303<=jea8e7a[81];db9181c<=jea8e7a[82];hq8c0e6<=jea8e7a[83];kd60732<=jea8e7a[84];zz3995<=jea8e7a[85];vx1ccae<=jea8e7a[86];ble6576<=jea8e7a[87];bn32bb6<=jea8e7a[88];ir95db6<=jea8e7a[89];wlaedb4<=jea8e7a[90];tu76da5<=jea8e7a[91];ukb6d2a<=jea8e7a[92];cob6950<=jea8e7a[93];qvb4a80<=jea8e7a[94];dba5405<=jea8e7a[95];tw2a02f<=jea8e7a[96];th5017a<=jea8e7a[97];kf80bd7<=jea8e7a[98];gq5ebd<=jea8e7a[99];ba2f5e9<=jea8e7a[100];en7af4a<=jea8e7a[101];ldd7a54<=jea8e7a[102];xybd2a7<=jea8e7a[103];hbe953a<=jea8e7a[104];fn4a9d7<=jea8e7a[105];uv54ebe<=jea8e7a[106];nga75f4<=jea8e7a[107];ri3afa2<=jea8e7a[108];ldd7d12<=jea8e7a[109];yzbe897<=jea8e7a[110];nef44bc<=jea8e7a[111];zma25e2<=jea8e7a[112];kf12f12<=jea8e7a[113];ou97895<=jea8e7a[114];ukbc4a9<=jea8e7a[115];ipe2548<=jea8e7a[116];ep12a44<=jea8e7a[117];ux95225<=jea8e7a[118];qia912d<=jea8e7a[119];xw48969<=jea8e7a[120];mr44b4b<=jea8e7a[121];xy25a5d<=jea8e7a[122];vx2d2ea<=jea8e7a[123];lq69757<=jea8e7a[124];kd4babb<=jea8e7a[125];ho5d5dc<=jea8e7a[126];uieaee3<=jea8e7a[127];dm57719<=jea8e7a[128];irbb8ca<=jea8e7a[129];qtdc654<=jea8e7a[130];rte32a5<=jea8e7a[131];zz1952e<=jea8e7a[132];jcca977<=jea8e7a[133];al54bba<=jea8e7a[134];lfa5dd4<=jea8e7a[135];aa2eea6<=jea8e7a[136];yk77531<=jea8e7a[137];phba989<=jea8e7a[138];sud4c4e<=jea8e7a[139];wya6270<=jea8e7a[140];ks31380<=jea8e7a[141];ba89c00<=jea8e7a[142];sh4e003<=jea8e7a[143];yx7001d<=jea8e7a[144];kf800ec<=jea8e7a[145];co764<=jea8e7a[146];tj3b20<=jea8e7a[147];yz1d906<=jea8e7a[148];zxec834<=jea8e7a[149];pf641a6<=jea8e7a[150];ls20d37<=jea8e7a[151];db69ba<=jea8e7a[152];ym34dd6<=jea8e7a[153];mga6eb1<=jea8e7a[154];ph37589<=jea8e7a[155];vxbac4f<=jea8e7a[156];qtd627e<=jea8e7a[157];irb13f4<=jea8e7a[158];ls89fa4<=jea8e7a[159];vv4fd23<=jea8e7a[160];th7e91e<=jea8e7a[161];zkf48f6<=jea8e7a[162];wla47b3<=jea8e7a[163];qv23d9d<=jea8e7a[164];tw1eced<=jea8e7a[165];pff676b<=jea8e7a[166];swb3b5f<=jea8e7a[167];mg9daf8<=jea8e7a[168];gbed7c0<=jea8e7a[169];xj6be05<=jea8e7a[170];dz5f02f<=jea8e7a[171];mrf817e<=jea8e7a[172];vic0bf4<=jea8e7a[173];qi5fa3<=jea8e7a[174];do2fd19<=jea8e7a[175];zx7e8cb<=jea8e7a[176];vif465e<=jea8e7a[177];ksa32f2<=jea8e7a[178];vx19790<=jea8e7a[179];cmcbc87<=jea8e7a[180];wj5e438<=jea8e7a[181];ipf21c4<=jea8e7a[182];qv90e25<=jea8e7a[183];gq8712c<=jea8e7a[184];db38961<=jea8e7a[185];eac4b0f<=jea8e7a[186];ls25879<=jea8e7a[187];cb2c3ca<=jea8e7a[188];rt61e55<=jea8e7a[189];wyf2ae<=jea8e7a[190];dm79571<=jea8e7a[191];bycab8a<=jea8e7a[192];pf55c52<=jea8e7a[193];anae296<=jea8e7a[194];xj714b4<=jea8e7a[195];cb8a5a6<=jea8e7a[196];zk52d35<=jea8e7a[197];fc969ab<=jea8e7a[198];cbb4d5b<=jea8e7a[199];swa6add<=jea8e7a[200];je356e9<=jea8e7a[201];uxab74a<=jea8e7a[202];al5ba54<=jea8e7a[203];thdd2a5<=jea8e7a[204];pfe952f<=jea8e7a[205];rt4a97f<=jea8e7a[206];mr54bfe<=jea8e7a[207];dba5ff4<=jea8e7a[208];pu2ffa6<=jea8e7a[209];qt7fd33<=jea8e7a[210];byfe99c<=jea8e7a[211];lqf4ce2<=jea8e7a[212];mga6713<=jea8e7a[213];kf33898<=jea8e7a[214];ba9c4c4<=jea8e7a[215];ale2623<=jea8e7a[216];tj1311c<=jea8e7a[217];ec988e6<=jea8e7a[218];suc4730<=jea8e7a[219];qv23980<=jea8e7a[220];vx1cc05<=jea8e7a[221];ble602e<=jea8e7a[222];zm30176<=jea8e7a[223];sj80bb2<=jea8e7a[224];sw5d95<=jea8e7a[225];sw2eca9<=jea8e7a[226];ne76549<=jea8e7a[227];dob2a4b<=jea8e7a[228];yz9525a<=jea8e7a[229];wya92d5<=jea8e7a[230];su496a9<=jea8e7a[231];uv4b548<=jea8e7a[232];pf5aa45<=jea8e7a[233];hod522f<=jea8e7a[234];qia917b<=jea8e7a[235];xw48bd9<=jea8e7a[236];nr45ecb<=jea8e7a[237];fc2f65f<=jea8e7a[238];ld7b2fa<=jea8e7a[239];shd97d7<=jea8e7a[240];eacbebd<=jea8e7a[241];nr5f5e8<=
-jea8e7a[242];mefaf46<=jea8e7a[243];xjd7a30<=jea8e7a[244];pubd187<=jea8e7a[245];uve8c3a<=jea8e7a[246];yk461d4<=jea8e7a[247];pu30ea1<=jea8e7a[248];sw8750b<=jea8e7a[249];tw3a859<=jea8e7a[250];ykd42ca<=jea8e7a[251];yza1651<=jea8e7a[252];fcb28d<=jea8e7a[253];ww5946b<=jea8e7a[254];lqca359<=jea8e7a[255];uv51acb<=jea8e7a[256];mg8d65c<=jea8e7a[257];zx6b2e0<=jea8e7a[258];me59706<=jea8e7a[259];iccb831<=jea8e7a[260];qg5c188<=jea8e7a[261];ose0c41<=jea8e7a[262];bn6208<=jea8e7a[263];mg31047<=jea8e7a[264];qi88238<=jea8e7a[265];en411c0<=jea8e7a[266];ir8e04<=jea8e7a[267];vi47025<=jea8e7a[268];tj3812b<=jea8e7a[269];zkc095e<=jea8e7a[270];xy4af3<=jea8e7a[271];hq2579b<=jea8e7a[272];ym2bcdb<=jea8e7a[273];kd5e6d9<=jea8e7a[274];rtf36cc<=jea8e7a[275];lf9b667<=jea8e7a[276];wwdb33e<=jea8e7a[277];ipd99f0<=jea8e7a[278];alccf84<=jea8e7a[279];ic67c25<=jea8e7a[280];gq3e129<=jea8e7a[281];cmf0949<=jea8e7a[282];vx84a49<=jea8e7a[283];ri2524f<=jea8e7a[284];cb2927b<=jea8e7a[285];os493dd<=jea8e7a[286];me49ee8<=jea8e7a[287];dz4f741<=jea8e7a[288];jp7ba0f<=jea8e7a[289];zxdd07e<=jea8e7a[290];kde83f7<=jea8e7a[291];cz41fbd<=jea8e7a[292];ukfded<=jea8e7a[293];ld7ef68<=jea8e7a[294];off7b46<=jea8e7a[295];hqbda34<=jea8e7a[296];mred1a3<=jea8e7a[297];qg68d1d<=jea8e7a[298];su468e8<=jea8e7a[299];ou34740<=jea8e7a[300];gqa3a00<=jea8e7a[301];sj1d001<=jea8e7a[302];gbe800d<=jea8e7a[303];xj4006d<=jea8e7a[304];co36e<=jea8e7a[305];ri1b70<=jea8e7a[306];end
-always@* begin ls351cf[2047]<=uv5eef5;ls351cf[2046]<=wjf77ad;ls351cf[2044]<=yzbbd6d;ls351cf[2043]<=ui4cc84;ls351cf[2040]<=medeb6c;ls351cf[2038]<=fp6cf4;ls351cf[2032]<=icf5b61;ls351cf[2029]<=ba1ecef;ls351cf[2017]<=puadb09;ls351cf[2013]<=gbc9d60;ls351cf[2010]<=ip60d9e;ls351cf[2003]<=vida762;ls351cf[1990]<=cb8f428;ls351cf[1987]<=kq6d84a[0];ls351cf[1982]<=mrf7047;ls351cf[1980]<=faf17e3;ls351cf[1979]<=pha52c3;ls351cf[1973]<=mg3b293;ls351cf[1963]<=xl3288f;ls351cf[1958]<=ng9681a;ls351cf[1957]<=gb659f7;ls351cf[1953]<=wlbeb5b;ls351cf[1942]<=wy1adf6;ls351cf[1932]<=db8bad3;ls351cf[1929]<=mtbb4bb;ls351cf[1926]<=xw6c250[0];ls351cf[1923]<=ep95d19;ls351cf[1921]<=hda5898;ls351cf[1917]<=fc1bfa4;ls351cf[1914]<=kqe59b1;ls351cf[1913]<=ph8bf1a;ls351cf[1911]<=qv2ca61;ls351cf[1903]<=qt6af36;ls351cf[1898]<=xlc1b3;ls351cf[1879]<=db9447e;ls351cf[1876]<=hoe153c;ls351cf[1872]<=godb92b;ls351cf[1868]<=tw837a6;ls351cf[1866]<=epa4d3e;ls351cf[1863]<=vx19296;ls351cf[1858]<=xwc0665;ls351cf[1837]<=mrd6fb1;ls351cf[1816]<=kf9ad77;ls351cf[1810]<=lf27299;ls351cf[1805]<=fcb2d03;ls351cf[1802]<=qg4c66b;ls351cf[1799]<=qv8079b;ls351cf[1795]<=mg98d46;ls351cf[1786]<=ui679d2;ls351cf[1783]<=off8f7c;ls351cf[1780]<=jpd2934;ls351cf[1778]<=xj5f8d6;ls351cf[1775]<=mt2961f;ls351cf[1770]<=ks5795;ls351cf[1758]<=cb36acf;ls351cf[1748]<=by47652;ls351cf[1710]<=lsa23f7;ls351cf[1704]<=bn9058;ls351cf[1701]<=ou1abb8;ls351cf[1699]<=rt5a4b6;ls351cf[1696]<=ea62604;ls351cf[1689]<=kf85586;ls351cf[1685]<=lqe4221;ls351cf[1679]<=uvfd60d;ls351cf[1678]<=of5b9b5;ls351cf[1668]<=icc1b13;ls351cf[1627]<=fcb7d8d;ls351cf[1624]<=ou82912;ls351cf[1605]<=uka31d0;ls351cf[1589]<=yk772c1;ls351cf[1584]<=kd6a9bf;ls351cf[1573]<=bab7697;ls351cf[1572]<=rv8448b;ls351cf[1567]<=aa24809;ls351cf[1562]<=ls9cfc5;ls351cf[1557]<=ba93757;ls351cf[1556]<=db19146;ls351cf[1551]<=zz32fe6;ls351cf[1548]<=ir1d393;ls351cf[1543]<=cm46112;ls351cf[1524]<=hbd2363;ls351cf[1521]<=qgffb9a;ls351cf[1519]<=al7fc5f;ls351cf[1513]<=ip44761;ls351cf[1512]<=kf9fac1;ls351cf[1509]<=vvfc6b7;ls351cf[1504]<=tw35400;ls351cf[1502]<=ip65837;ls351cf[1499]<=ho58364;ls351cf[1493]<=wjcc527;ls351cf[1492]<=tjc95d;ls351cf[1469]<=lqcf9a0;ls351cf[1466]<=ep23a0c;ls351cf[1448]<=vvd25b6;ls351cf[1421]<=ip4ee59;ls351cf[1417]<=ep3c4d2;ls351cf[1415]<=wjf8778;ls351cf[1404]<=zx7b094;ls351cf[1402]<=fcbd6b;ls351cf[1400]<=ym8808d;ls351cf[1398]<=pff69f5;ls351cf[1377]<=lf946e3;ls351cf[1374]<=mt8fd07;ls351cf[1373]<=ykff2e0;ls351cf[1361]<=gd188e6;ls351cf[1359]<=yza1d60;ls351cf[1355]<=of51cff;ls351cf[1354]<=qg59f34;ls351cf[1350]<=hoc033b;ls351cf[1349]<=pha0bb8;ls351cf[1344]<=co31697;ls351cf[1343]<=qi343ac;ls351cf[1341]<=fpbf551;ls351cf[1330]<=do2ac34;ls351cf[1326]<=sud174a;ls351cf[1323]<=tuee7bc;ls351cf[1322]<=zm25bea;ls351cf[1310]<=sjd899;ls351cf[1308]<=yke0381;ls351cf[1305]<=ps58067;ls351cf[1301]<=qi3125d;ls351cf[1289]<=tj13358;ls351cf[1286]<=wwe59b4;ls351cf[1280]<=tw354c3;ls351cf[1279]<=czc6875;ls351cf[1271]<=ieb67b8;ls351cf[1224]<=fpb0d18;ls351cf[1210]<=dob2607;ls351cf[1207]<=db22415;ls351cf[1201]<=hb7191b;ls351cf[1199]<=jra069c;ls351cf[1195]<=ks15d28;ls351cf[1193]<=thdd42b;ls351cf[1163]<=gb5ed3e;ls351cf[1162]<=wl18e80;ls351cf[1155]<=wwd4d46;ls351cf[1144]<=ipc65b2;ls351cf[1136]<=ofe76d1;ls351cf[1130]<=ldcd5e6;ls351cf[1125]<=rv8b00c;ls351cf[1120]<=mr6fa1c;ls351cf[1112]<=wlaea9b;ls351cf[1110]<=fa4211d;ls351cf[1104]<=zkd013b;ls351cf[1098]<=uic4e53;ls351cf[1096]<=jr2245e;ls351cf[1086]<=xy2afad;ls351cf[1076]<=ykff9d5;ls351cf[1067]<=kdd6f0e;ls351cf[1065]<=rv19ac2;ls351cf[1060]<=fa57824;ls351cf[1054]<=ym2e1ac;ls351cf[1053]<=oha46d4;ls351cf[1051]<=vxb5b5d;ls351cf[1048]<=mg92ffd;ls351cf[1039]<=meef7c0;ls351cf[1026]<=gqbc45e;ls351cf[1023]<=wlabdde[0];ls351cf[1021]<=an29990;ls351cf[1006]<=lqf4a58;ls351cf[1001]<=jr8bdda;ls351cf[995]<=hq2a714;ls351cf[991]<=jr9ee08;ls351cf[990]<=dmfe2fc;ls351cf[981]<=ph6511;ls351cf[978]<=jr949a7;ls351cf[976]<=wjedd33;ls351cf[971]<=rte35be;ls351cf[964]<=zkda5dd;ls351cf[961]<=pub7827;ls351cf[960]<=ep236a5;ls351cf[957]<=wl9a526;ls351cf[951]<=hb6466a;ls351cf[938]<=qgc120b;ls351cf[936]<=thf328f;ls351cf[931]<=hd131a8;ls351cf[901]<=ba898cd;ls351cf[891]<=tja04f8;ls351cf[885]<=os6dbe6;ls351cf[850]<=vv55280;ls351cf[849]<=ria8eca;ls351cf[839]<=yz29b02;ls351cf[812]<=yz9f055;ls351cf[802]<=tj13cb0;ls351cf[794]<=xwcff6d;ls351cf[786]<=dm5d28e;ls351cf[783]<=wjdc2f5;ls351cf[778]<=ph133cc;ls351cf[774]<=cbb1391;ls351cf[760]<=je18d7;ls351cf[756]<=go53f58;ls351cf[752]<=ri3fdd6;ls351cf[749]<=suf5d58;ls351cf[746]<=ne58241;ls351cf[733]<=gq82e31;ls351cf[710]<=lq6c8cd;ls351cf[708]<=wj44e94;ls351cf[707]<=hqad6a9;ls351cf[702]<=gb44fd5;ls351cf[701]<=of65b65;ls351cf[700]<=lq7c001;ls351cf[699]<=mt122f6;ls351cf[688]<=aa2ee58;ls351cf[687]<=lfb501b;ls351cf[679]<=ng1ba85;ls351cf[677]<=ld61cba;ls351cf[674]<=ne482c6;ls351cf[671]<=ofc3750;ls351cf[670]<=zxc2db3;ls351cf[663]<=ipfd144;ls351cf[661]<=mg3409f;ls351cf[652]<=jp6b496;ls351cf[650]<=ayef977;ls351cf[643]<=ph276eb;ls351cf[640]<=ou3ee1e;ls351cf[639]<=ym15317;ls351cf[635]<=ymb6cf7;ls351cf[612]<=ep9f7e1;ls351cf[605]<=ks24da8;ls351cf[599]<=wjf8aab;ls351cf[597]<=je2fff9;ls351cf[596]<=sj18430;ls351cf[581]<=dm661f6;ls351cf[577]<=cze8e6b;ls351cf[572]<=fc99ac6;ls351cf[568]<=ec822fe;ls351cf[562]<=mec1564;ls351cf[556]<=go6866d;ls351cf[555]<=zk7cbb9;ls351cf[552]<=zm3a027;ls351cf[530]<=je3f115;ls351cf[526]<=xw732a4;ls351cf[525]<=cmdbaf1;ls351cf[513]<=jrb034c;ls351cf[510]<=gb65982;ls351cf[503]<=swa3f17;ls351cf[495]<=shc3d28;ls351cf[490]<=ouca2;ls351cf[482]<=pu2a660;ls351cf[480]<=fc99523;ls351cf[465]<=god4b13;ls351cf[450]<=mtaeb3b;ls351cf[425]<=cb8227;ls351cf[419]<=sh4b0fd;ls351cf[406]<=zmad9e7;ls351cf[401]<=ri868c7;ls351cf[389]<=kd4e139;ls351cf[387]<=dz61daf;ls351cf[373]<=sw599f;ls351cf[366]<=pu3a9c4;ls351cf[355]<=irab06c;ls351cf[354]<=hq8c8df;ls351cf[351]<=zk5d4fd;ls351cf[350]<=qi2e38b;ls351cf[344]<=by58d6a;ls351cf[343]<=mg3e8f6;ls351cf[339]<=aaa3086;ls351cf[338]<=qgcb6ee;ls351cf[335]<=rg585b6;ls351cf[321]<=ba4edd;ls351cf[298]<=fcb89ca;ls351cf[290]<=qi981da;ls351cf[288]<=ymb6573;ls351cf[278]<=co3ebab;ls351cf[276]<=nef45c0;ls351cf[263]<=yz269f4;ls351cf[251]<=ou3e94b;ls351cf[245]<=fac0194;ls351cf[241]<=an9f1ef;ls351cf[240]<=ngb2b99;ls351cf[232]<=os5c36f;ls351cf[225]<=yxe7e2a;ls351cf[212]<=rte6d59;ls351cf[209]<=uka97bb;ls351cf[203]<=pfe6d6c;ls351cf[194]<=baa8c22;ls351cf[193]<=dz4518e;ls351cf[177]<=nta586c;ls351cf[175]<=czf22b3;ls351cf[172]<=yke5dcb;ls351cf[169]<=vv6ee2f;ls351cf[167]<=nefec36;ls351cf[160]<=vk9c4af;ls351cf[149]<=hbc2185;ls351cf[145]<=wjd931f;ls351cf[144]<=jc58cb6;ls351cf[125]<=yx416b2;ls351cf[122]<=kdf8032;ls351cf[120]<=ym82969;ls351cf[116]<=nr55112;ls351cf[109]<=hd946ae;ls351cf[104]<=gb41632;ls351cf[97]<=uv6fd78;ls351cf[87]<=tjbf2b7;ls351cf[84]<=sw5867;ls351cf[83]<=vvcd616;ls351cf[72]<=iea456;ls351cf[61]<=tudf006;ls351cf[60]<=nt8efed;
-ls351cf[58]<=kf1ddcf;ls351cf[54]<=qv23932;ls351cf[48]<=al752c3;ls351cf[42]<=me78221;ls351cf[30]<=pf7be00;ls351cf[21]<=qgcb534;ls351cf[10]<=ld5a8a4;ls351cf[5]<=qv23d0e;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module nr553d0 (rst_n,
- gbe_mode,
- al7a1c7,
-
- hod0e3d,
- force_isolate,
-
- zz38f51,
- blc7a8f,
- lf3d47e,
-
- meea3f6,
- of51fb0,
- sj8fd84,
- vv7ec24
- );
-input rst_n;
-input gbe_mode;
-input al7a1c7;
-input [1:0] hod0e3d;
-input force_isolate;
-input [7:0] zz38f51;
-input blc7a8f;
-input lf3d47e;
-input meea3f6;
-output [7:0] of51fb0;
-output sj8fd84;
-output vv7ec24;
-reg [7:0] of51fb0;
-reg sj8fd84;
-reg vv7ec24;
-reg [1:0] ic59746;
-reg [1:0] cmcba31;
-reg [1:0] vi5d188;
-reg [1:0] ene8c43;
-reg [1:0] ay4621c;
-reg [1:0] ec310e1;
-reg ec88708;
-reg kq43840;
-reg fp1c200;
-reg fae1007;
-reg [7:0] kf803b;
-reg jp401dc;
-reg ukee6;
-reg [7:0] kf7731;
-reg gq3b98d;
-reg aldcc68;
-reg [7:0] pfe6344;
-reg gq31a26;
-reg ym8d131;
-reg os68988;
-wire en44c40;
-wire mt26205;
-wire [7:0] ie3102c;
-wire ks88160;
-reg jp40b00;
-reg ym5807;
-reg qv2c039;
-reg yx601cd;
-reg ece6d;
-reg mt7369;
-reg yz39b4d;
-reg thcda6d;
-reg [6:0] ea6d36f;
-reg fa69b79;
-reg jc4dbca;
-reg cm6de53;
-reg mr6f298;
-reg ne794c4;
-reg dmca622;
-reg go53113;
-reg ec98898;
-reg suc44c0;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-`endif\r
-reg rv22600;
-reg [1 : 0] zz13006;
-reg aa98036;
-reg [7 : 0] rgc01b1;
-reg gqd8a;
-reg db6c51;
-reg [1 : 0] an3628e;
-reg [1 : 0] epb1475;
-reg [1 : 0] gd8a3ac;
-reg [1 : 0] gb51d65;
-reg [1 : 0] hd8eb2c;
-reg [1 : 0] kd75966;
-reg ecacb35;
-reg cz659a8;
-reg ir2cd44;
-reg ho66a24;
-reg [7 : 0] zm35123;
-reg ria891a;
-reg cz448d2;
-reg [7 : 0] uk24695;
-reg an234a9;
-reg qi1a54c;
-reg [7 : 0] nrd2a60;
-reg oh95307;
-reg uka983d;
-reg yk4c1e8;
-reg qt60f40;
-reg qv7a04;
-reg [7 : 0] bn3d024;
-reg mre8126;
-reg th40935;
-reg ba49af;
-reg mg24d7b;
-reg kf26bd8;
-reg xy35ec5;
-reg hdaf62b;
-reg bl7b15e;
-reg rtd8af7;
-reg [6 : 0] tuc57be;
-reg wy2bdf2;
-reg uv5ef91;
-reg wjf7c8d;
-reg uxbe46c;
-reg mrf2365;
-reg xl91b2d;
-reg ks8d96e;
-reg lq6cb71;
-reg gb65b8a;
-reg [2047:0] ls351cf;
-wire [47:0] jea8e7a;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-localparam ps473d2 = 48,wl39e93 = 32'hfdffca8b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-
-always @(posedge al7a1c7 or negedge rst_n)
-begin if (rst_n == 1'b0) begin qv2c039 <= 1'd1; yx601cd <= 1'd1; end else begin qv2c039 <= ba49af; yx601cd <= mg24d7b; end
-end
-
-
-
-
-always @(posedge al7a1c7 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ece6d <= 1'd1; mt7369 <= 1'd1; end else begin ece6d <= cz659a8; mt7369 <= xy35ec5; end
-end
-
-
-always @(posedge al7a1c7 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ec98898 <= 1'b0; suc44c0 <= 1'b0; end else begin ec98898 <= aa98036; suc44c0 <= lq6cb71; end
-end
-
-
-always @(posedge al7a1c7 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jp401dc <= 1'b0; ukee6 <= 1'b0; kf803b <= 8'd0; gq3b98d <= 1'b0; aldcc68 <= 1'b0; kf7731 <= 8'd0; gq31a26 <= 1'b0; ym8d131 <= 1'b0; pfe6344 <= 8'd0; os68988 <= 1'b0; end else begin if (gb65b8a) begin kf803b <= 8'd0; ukee6 <= 1'b0; jp401dc <= 1'b0; end else begin kf803b <= rgc01b1; ukee6 <= db6c51; jp401dc <= gqd8a; end kf7731 <= zm35123; aldcc68 <= cz448d2; gq3b98d <= ria891a;
- if (kf26bd8) begin os68988 <= 1'b0; end else if (((cz448d2==1'd1) && (qi1a54c==1'd0)) || (hdaf62b ==1'd1)) os68988 <= 1'b1; else os68988 <= (~yk4c1e8); if (yk4c1e8) begin pfe6344[3:0] <= uk24695[3:0]; ym8d131 <= qi1a54c; gq31a26 <= an234a9; if (hdaf62b) begin pfe6344[7:4] <= uk24695[7:4]; end else begin pfe6344[7:4] <= zm35123[3:0]; end end end
-end
-
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) wj4e6f9 ( .Reset(yx601cd), .RPReset(yx601cd), .WrClock(al7a1c7), .WrEn(os68988), .Data({gq31a26, ym8d131, pfe6344}),
- .RdClock(meea3f6), .RdEn(jp40b00), .Q({en44c40, mt26205, ie3102c}),
- .Empty(ks88160), .Full(), .AlmostEmpty(), .AlmostFull() );
-
-`endif\r
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) wj4e6f9 ( .Reset(yx601cd), .RPReset(yx601cd), .WrClock(al7a1c7), .WrEn(os68988), .Data({gq31a26, ym8d131, pfe6344}),
- .RdClock(meea3f6), .RdEn(jp40b00), .Q({en44c40, mt26205, ie3102c}),
- .Empty(ks88160), .Full(), .AlmostEmpty(), .AlmostFull() );
-
-`endif\r
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) wj4e6f9 ( .Reset(yx601cd), .RPReset(yx601cd), .WrClock(al7a1c7), .WrEn(os68988), .Data({gq31a26, ym8d131, pfe6344}),
- .RdClock(meea3f6), .RdEn(jp40b00), .Q({en44c40, mt26205, ie3102c}),
- .Empty(ks88160), .Full(), .AlmostEmpty(), .AlmostFull() );
-
-`endif\r
-
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jc4dbca <= 1'b0; cm6de53 <= 1'b0; mr6f298 <= 1'b0; ne794c4 <= 1'b0; dmca622 <= 1'b0; go53113 <= 1'b0; end else begin jc4dbca <= rv22600; cm6de53 <= uv5ef91;
- mr6f298 <= wjf7c8d; ne794c4 <= wjf7c8d & (~uxbe46c); dmca622 <= ~wjf7c8d & (uxbe46c); go53113 <= mrf2365 || xl91b2d; end
-end
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ic59746 <= 2'd0; cmcba31 <= 2'd0; vi5d188 <= 2'd0; ene8c43 <= 2'd0; ay4621c <= 2'd0; ec310e1 <= 2'd0; ec88708 <= 1'b0; kq43840 <= 1'b0; fp1c200 <= 1'b0; fae1007 <= 1'b0; end else begin ic59746 <= zz13006; cmcba31 <= an3628e; vi5d188 <= epb1475; ene8c43 <= gd8a3ac; if ((epb1475==gd8a3ac) && (epb1475==gb51d65)) ay4621c <= gb51d65; ec310e1 <= hd8eb2c; if (ks8d96e) ec88708 <= 1'b1; else if (hd8eb2c != kd75966) ec88708 <= 1'b1; else ec88708 <= 1'b0; if (uxbe46c) begin kq43840 <= 1'b1; fp1c200 <= 1'b0; fae1007 <= 1'b0; end else begin kq43840 <= hd8eb2c[1]; fp1c200 <= !hd8eb2c[1] & ( hd8eb2c[0]); fae1007 <= !hd8eb2c[1] & (!hd8eb2c[0]); end
- case (bl7b15e) 1'd0: begin if (ecacb35) begin ym5807 <= 1'b1; yz39b4d <= 1'd1; end else begin ym5807 <= 1'b0; yz39b4d <= 1'd0; end end 1'd1: begin ym5807 <= 1'b1; if (rtd8af7) begin yz39b4d <= 1'd0; end else begin yz39b4d <= 1'd1; end end default: begin yz39b4d <= 1'd0; end endcase
- end
-end
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ea6d36f <= 7'd0; fa69b79 <= 1'b0; end else begin if (ecacb35 || wy2bdf2) begin ea6d36f <= 7'd0; end else begin ea6d36f <= tuc57be + 1; end
- if (ecacb35) begin fa69b79 <= 1'b0; end else if (ir2cd44) begin if (tuc57be == 7'd8) begin fa69b79 <= 1'b1; end else begin fa69b79 <= 1'b0; end end else if (ho66a24) begin if (tuc57be == 7'd98) begin fa69b79 <= 1'b1; end else begin fa69b79 <= 1'b0; end end else begin fa69b79 <= 1'b1; end end
-end
-
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin thcda6d <= 1'b0; end else begin if (ecacb35) begin thcda6d <= 1'b0; end else if (ir2cd44) begin if (tuc57be == 7'd3) begin thcda6d <= 1'b1; end else begin thcda6d <= 1'b0; end end else if (ho66a24) begin if (tuc57be == 7'd49) begin thcda6d <= 1'b1; end else begin thcda6d <= 1'b0; end end else begin thcda6d <= 1'b1; end end
-end
-
-
-
-
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jp40b00 <= 1'b0; end else begin if (ba49af) begin jp40b00 <= 1'b0; end else if (!mre8126 && rtd8af7) begin jp40b00 <= 1'b1; end else begin jp40b00 <= 1'b0; end end
-end
-
-
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin of51fb0 <= 8'd0; sj8fd84 <= 1'd0; vv7ec24 <= 1'd0; end else begin of51fb0 <= bn3d024; sj8fd84 <= qt60f40; vv7ec24 <= qv7a04; end
-end
-
-always@* begin rv22600<=jea8e7a[0];zz13006<={hod0e3d>>1,jea8e7a[1]};aa98036<=jea8e7a[2];rgc01b1<={zz38f51>>1,jea8e7a[3]};gqd8a<=jea8e7a[4];db6c51<=jea8e7a[5];an3628e<={ic59746>>1,jea8e7a[6]};epb1475<={cmcba31>>1,jea8e7a[7]};gd8a3ac<={vi5d188>>1,jea8e7a[8]};gb51d65<={ene8c43>>1,jea8e7a[9]};hd8eb2c<={ay4621c>>1,jea8e7a[10]};kd75966<={ec310e1>>1,jea8e7a[11]};ecacb35<=jea8e7a[12];cz659a8<=jea8e7a[13];ir2cd44<=jea8e7a[14];ho66a24<=jea8e7a[15];zm35123<={kf803b>>1,jea8e7a[16]};ria891a<=jea8e7a[17];cz448d2<=jea8e7a[18];uk24695<={kf7731>>1,jea8e7a[19]};an234a9<=jea8e7a[20];qi1a54c<=jea8e7a[21];nrd2a60<={pfe6344>>1,jea8e7a[22]};oh95307<=jea8e7a[23];uka983d<=jea8e7a[24];yk4c1e8<=jea8e7a[25];qt60f40<=jea8e7a[26];qv7a04<=jea8e7a[27];bn3d024<={ie3102c>>1,jea8e7a[28]};mre8126<=jea8e7a[29];th40935<=jea8e7a[30];ba49af<=jea8e7a[31];mg24d7b<=jea8e7a[32];kf26bd8<=jea8e7a[33];xy35ec5<=jea8e7a[34];hdaf62b<=jea8e7a[35];bl7b15e<=jea8e7a[36];rtd8af7<=jea8e7a[37];tuc57be<={ea6d36f>>1,jea8e7a[38]};wy2bdf2<=jea8e7a[39];uv5ef91<=jea8e7a[40];wjf7c8d<=jea8e7a[41];uxbe46c<=jea8e7a[42];mrf2365<=jea8e7a[43];xl91b2d<=jea8e7a[44];ks8d96e<=jea8e7a[45];lq6cb71<=jea8e7a[46];gb65b8a<=jea8e7a[47];end
-always@* begin ls351cf[2047]<=hod0e3d[0];ls351cf[2046]<=force_isolate;ls351cf[2044]<=zz38f51[0];ls351cf[2040]<=blc7a8f;ls351cf[2032]<=lf3d47e;ls351cf[2017]<=ic59746[0];ls351cf[1987]<=cmcba31[0];ls351cf[1926]<=vi5d188[0];ls351cf[1805]<=mt7369;ls351cf[1804]<=ene8c43[0];ls351cf[1803]<=gq31a26;ls351cf[1761]<=qv2c039;ls351cf[1668]<=mr6f298;ls351cf[1562]<=yz39b4d;ls351cf[1560]<=ay4621c[0];ls351cf[1558]<=ym8d131;ls351cf[1550]<=kf803b[0];ls351cf[1475]<=yx601cd;ls351cf[1464]<=jp40b00;ls351cf[1288]<=ne794c4;ls351cf[1076]<=thcda6d;ls351cf[1072]<=ec310e1[0];ls351cf[1069]<=os68988;ls351cf[1056]<=go53113;ls351cf[1052]<=jp401dc;ls351cf[1023]<=gbe_mode;ls351cf[902]<=ece6d;ls351cf[901]<=pfe6344[0];ls351cf[880]<=ym5807;ls351cf[834]<=cm6de53;ls351cf[775]<=fae1007;ls351cf[732]<=ks88160;ls351cf[528]<=dmca622;ls351cf[450]<=aldcc68;ls351cf[417]<=jc4dbca;ls351cf[387]<=fp1c200;ls351cf[366]<=ie3102c[0];ls351cf[225]<=gq3b98d;ls351cf[208]<=fa69b79;ls351cf[193]<=kq43840;ls351cf[183]<=mt26205;ls351cf[128]<=suc44c0;ls351cf[112]<=kf7731[0];ls351cf[104]<=ea6d36f[0];ls351cf[96]<=ec88708;ls351cf[91]<=en44c40;ls351cf[64]<=ec98898;ls351cf[56]<=ukee6;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module uie0f07 (rst_n,
- gbe_mode,
- force_isolate,
- al7a1c7,
-
- zz38f51,
- blc7a8f,
- lf3d47e,
- do20bc9,
- ou5e4a,
-
- meea3f6,
- vi7928a,
- of51fb0,
- sj8fd84,
- vv7ec24,
- yz8a53d,
- tu529ed
- );
-input rst_n;
-input gbe_mode;
-input force_isolate;
-input al7a1c7;
-input [7:0] zz38f51;
-input blc7a8f;
-input lf3d47e;
-input do20bc9;
-input ou5e4a;
-input meea3f6;
-input [1:0] vi7928a;
-output [7:0] of51fb0;
-output sj8fd84;
-output vv7ec24;
-output yz8a53d;
-output tu529ed;
-reg [7:0] of51fb0;
-reg sj8fd84;
-reg vv7ec24;
-reg yz8a53d;
-reg tu529ed;
-reg [1:0] ic59746;
-reg [1:0] cmcba31;
-reg [1:0] vi5d188;
-reg [1:0] ene8c43;
-reg [1:0] ay4621c;
-reg [1:0] ec310e1;
-reg ec88708;
-reg kq43840;
-reg fp1c200;
-reg fae1007;
-reg ym5807;
-reg qv2c039;
-reg god13fa;
-reg thcda6d;
-reg [6:0] ea6d36f;
-reg fa69b79;
-reg kqfa2f5;
-reg icd17a9;
-reg jp40b00;
-reg [7:0] kf803b;
-reg ukee6;
-reg jp401dc;
-reg kq49d41;
-reg mr4ea09;
-wire [7:0] ie3102c;
-wire mt26205;
-wire en44c40;
-wire hd991c;
-wire me4c8e7;
-reg [7:0] dz64739;
-reg ux239cf;
-reg bn1ce7d;
-reg wje73ee;
-reg mt39f74;
-reg yz39b4d;
-reg ece6d;
-reg byee951;
-reg jc4dbca;
-reg cm6de53;
-reg mr6f298;
-reg ne794c4;
-reg dmca622;
-reg go53113;
-reg ec98898;
-reg suc44c0;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-`endif\r
-reg rv22600;
-reg aa98036;
-reg [7 : 0] rgc01b1;
-reg gqd8a;
-reg db6c51;
-reg zk42a46;
-reg sw15232;
-reg [1 : 0] aaa9191;
-reg [1 : 0] an3628e;
-reg [1 : 0] epb1475;
-reg [1 : 0] gd8a3ac;
-reg [1 : 0] gb51d65;
-reg [1 : 0] hd8eb2c;
-reg [1 : 0] kd75966;
-reg ecacb35;
-reg cz659a8;
-reg ir2cd44;
-reg ho66a24;
-reg ba49af;
-reg mg24d7b;
-reg jc42a1b;
-reg rtd8af7;
-reg [6 : 0] tuc57be;
-reg wy2bdf2;
-reg ls1b459;
-reg xwda2ca;
-reg th40935;
-reg [7 : 0] zm35123;
-reg cz448d2;
-reg ria891a;
-reg fa523cb;
-reg zz91e5a;
-reg [7 : 0] bn3d024;
-reg qv7a04;
-reg qt60f40;
-reg pf5ad51;
-reg ipd6a8f;
-reg [7 : 0] bnb547d;
-reg jraa3ee;
-reg qt51f76;
-reg ir8fbb4;
-reg qg7dda4;
-reg bl7b15e;
-reg xy35ec5;
-reg anb485a;
-reg uv5ef91;
-reg wjf7c8d;
-reg uxbe46c;
-reg mrf2365;
-reg xl91b2d;
-reg ks8d96e;
-reg lq6cb71;
-reg gb65b8a;
-reg [2047:0] ls351cf;
-wire [52:0] jea8e7a;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-localparam ps473d2 = 53,wl39e93 = 32'hfdffe06b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-
-always @(posedge al7a1c7 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jc4dbca <= 1'b0; cm6de53 <= 1'b0; mr6f298 <= 1'b0; ne794c4 <= 1'b0; dmca622 <= 1'b0; go53113 <= 1'b0; end else begin jc4dbca <= rv22600; cm6de53 <= uv5ef91;
- mr6f298 <= wjf7c8d; ne794c4 <= wjf7c8d & (~uxbe46c); dmca622 <= ~wjf7c8d & (uxbe46c); go53113 <= mrf2365 || xl91b2d; end
-end
-
-
-always @(posedge al7a1c7 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ic59746 <= 2'd0; cmcba31 <= 2'd0; vi5d188 <= 2'd0; ene8c43 <= 2'd0; ay4621c <= 2'd0; ec310e1 <= 2'd0; ec88708 <= 1'b1; kq43840 <= 1'b0; fp1c200 <= 1'b0; fae1007 <= 1'b0; end else begin ic59746 <= aaa9191; cmcba31 <= an3628e; vi5d188 <= epb1475; ene8c43 <= gd8a3ac; if ((epb1475==gd8a3ac) && (epb1475==gb51d65)) ay4621c <= gb51d65; ec310e1 <= hd8eb2c; if (ks8d96e) ec88708 <= 1'b1; else if (hd8eb2c != kd75966) ec88708 <= 1'b1; else ec88708 <= 1'b0; if (uxbe46c) begin kq43840 <= 1'b1; fp1c200 <= 1'b0; fae1007 <= 1'b0; end else begin kq43840 <= hd8eb2c[1]; fp1c200 <= !hd8eb2c[1] & ( hd8eb2c[0]); fae1007 <= !hd8eb2c[1] & (!hd8eb2c[0]); end case (bl7b15e) 1'd0: begin if (ecacb35) begin ym5807 <= 1'b1; yz39b4d <= 1'd1; end else begin ym5807 <= 1'b0; yz39b4d <= 1'd0; end end 1'd1: begin ym5807 <= 1'b1; if (rtd8af7) begin yz39b4d <= 1'd0; end else begin yz39b4d <= 1'd1; end end default: begin yz39b4d <= 1'd0; end endcase end
-end
-
-
-always @(posedge al7a1c7 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ea6d36f <= 7'd0; fa69b79 <= 1'b0; end else begin if (ecacb35 || wy2bdf2) begin ea6d36f <= 7'd0; end else begin ea6d36f <= tuc57be + 1; end
- if (ecacb35) begin fa69b79 <= 1'b0; end else if (ir2cd44) begin if (tuc57be == 7'd8) begin fa69b79 <= 1'b1; end else begin fa69b79 <= 1'b0; end end else if (ho66a24) begin if (tuc57be == 7'd98) begin fa69b79 <= 1'b1; end else begin fa69b79 <= 1'b0; end end else begin fa69b79 <= 1'b1; end end
-end
-
-
-
-always @(posedge al7a1c7 or negedge rst_n)
-begin if (rst_n == 1'b0) begin thcda6d <= 1'b0; end else begin if (ecacb35) begin thcda6d <= 1'b0; end else if (ir2cd44) begin if (tuc57be == 7'd3) begin thcda6d <= 1'b1; end else begin thcda6d <= 1'b0; end end else if (ho66a24) begin if (tuc57be == 7'd49) begin thcda6d <= 1'b1; end else begin thcda6d <= 1'b0; end end else begin thcda6d <= 1'b1; end end
-end
-
-
-
-always @(posedge al7a1c7 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jp401dc <= 0; ukee6 <= 0; kq49d41 <= 0; mr4ea09 <= 0; kf803b <= 8'd0; end else begin kf803b <= rgc01b1; ukee6 <= db6c51; jp401dc <= gqd8a; kq49d41 <= zk42a46; mr4ea09 <= sw15232; end
-end
-
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(12), .pmi_data_width_r(12), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) yxfdbcb ( .Reset(god13fa), .RPReset(god13fa), .WrClock(al7a1c7), .WrEn(thcda6d), .Data({mr4ea09, kq49d41, jp401dc, ukee6, kf803b}),
- .RdClock(meea3f6), .RdEn(jp40b00), .Q({me4c8e7, hd991c, en44c40, mt26205, ie3102c}),
- .Empty(ks88160), .Full(), .AlmostEmpty(), .AlmostFull() );
-
-`endif\r
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(12), .pmi_data_width_r(12), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) yxfdbcb ( .Reset(god13fa), .RPReset(god13fa), .WrClock(al7a1c7), .WrEn(thcda6d), .Data({mr4ea09, kq49d41, jp401dc, ukee6, kf803b}),
- .RdClock(meea3f6), .RdEn(jp40b00), .Q({me4c8e7, hd991c, en44c40, mt26205, ie3102c}),
- .Empty(ks88160), .Full(), .AlmostEmpty(), .AlmostFull() );
-
-`endif\r
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(12), .pmi_data_width_r(12), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) yxfdbcb ( .Reset(god13fa), .RPReset(god13fa), .WrClock(al7a1c7), .WrEn(thcda6d), .Data({mr4ea09, kq49d41, jp401dc, ukee6, kf803b}),
- .RdClock(meea3f6), .RdEn(jp40b00), .Q({me4c8e7, hd991c, en44c40, mt26205, ie3102c}),
- .Empty(ks88160), .Full(), .AlmostEmpty(), .AlmostFull() );
-
-`endif\r
-
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin qv2c039 <= 1'd1; god13fa <= 1'd1; end else begin qv2c039 <= ba49af; god13fa <= mg24d7b; end
-end
-
-
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ece6d <= 1'd1; byee951 <= 1'd1; end else begin ece6d <= cz659a8; byee951 <= xy35ec5; end
-end
-
-
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin kqfa2f5 <= 1'b0; icd17a9 <= 1'b0; end else begin if (jc42a1b) begin kqfa2f5 <= 1'b0; end else begin if (anb485a) begin kqfa2f5 <= 1'b1; end else begin kqfa2f5 <= ~ls1b459; end end
- icd17a9 <= ls1b459;
- end
-end
-
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jp40b00 <= 1'b0; end else begin if (jc42a1b) begin jp40b00 <= 1'b0; end else begin if (!ks88160 && ls1b459) begin jp40b00 <= 1'b1; end else begin jp40b00 <= 1'b0; end end end
-end
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin bn1ce7d <= 0; ux239cf <= 0; wje73ee <= 0; mt39f74 <= 0; dz64739 <= 8'd0; end else begin if (ls1b459) begin ux239cf <= qv7a04; wje73ee <= pf5ad51; mt39f74 <= ipd6a8f; if ((!anb485a) && qt60f40 && (bn3d024 == 8'h0F) && (!qv7a04) && jraa3ee) begin bn1ce7d <= 1'b0; dz64739 <= 8'h00; end else begin bn1ce7d <= qt60f40; dz64739 <= bn3d024; end end
- end
-end
-
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ec98898 <= 1'b0; suc44c0 <= 1'b0; end else begin ec98898 <= aa98036; suc44c0 <= lq6cb71; end
-end
-
-
-always @(posedge meea3f6 or negedge rst_n)
-begin if (rst_n == 1'b0) begin sj8fd84 <= 0; vv7ec24 <= 0; yz8a53d <= 0; tu529ed <= 0; of51fb0 <= 8'd0; end else begin if (gb65b8a) begin sj8fd84 <= 0; vv7ec24 <= 0; yz8a53d <= 0; tu529ed <= 0; of51fb0 <= 8'd0; end else begin if (xwda2ca) begin of51fb0[3:0] <= bnb547d[3:0]; end else begin of51fb0[3:0] <= bnb547d[7:4]; end of51fb0[7:4] <= bnb547d[7:4]; vv7ec24 <= jraa3ee; sj8fd84 <= qt51f76; yz8a53d <= ir8fbb4; tu529ed <= qg7dda4; end end
-end
-
-
-
-always@* begin rv22600<=jea8e7a[0];aa98036<=jea8e7a[1];rgc01b1<={zz38f51>>1,jea8e7a[2]};gqd8a<=jea8e7a[3];db6c51<=jea8e7a[4];zk42a46<=jea8e7a[5];sw15232<=jea8e7a[6];aaa9191<={vi7928a>>1,jea8e7a[7]};an3628e<={ic59746>>1,jea8e7a[8]};epb1475<={cmcba31>>1,jea8e7a[9]};gd8a3ac<={vi5d188>>1,jea8e7a[10]};gb51d65<={ene8c43>>1,jea8e7a[11]};hd8eb2c<={ay4621c>>1,jea8e7a[12]};kd75966<={ec310e1>>1,jea8e7a[13]};ecacb35<=jea8e7a[14];cz659a8<=jea8e7a[15];ir2cd44<=jea8e7a[16];ho66a24<=jea8e7a[17];ba49af<=jea8e7a[18];mg24d7b<=jea8e7a[19];jc42a1b<=jea8e7a[20];rtd8af7<=jea8e7a[21];tuc57be<={ea6d36f>>1,jea8e7a[22]};wy2bdf2<=jea8e7a[23];ls1b459<=jea8e7a[24];xwda2ca<=jea8e7a[25];th40935<=jea8e7a[26];zm35123<={kf803b>>1,jea8e7a[27]};cz448d2<=jea8e7a[28];ria891a<=jea8e7a[29];fa523cb<=jea8e7a[30];zz91e5a<=jea8e7a[31];bn3d024<={ie3102c>>1,jea8e7a[32]};qv7a04<=jea8e7a[33];qt60f40<=jea8e7a[34];pf5ad51<=jea8e7a[35];ipd6a8f<=jea8e7a[36];bnb547d<={dz64739>>1,jea8e7a[37]};jraa3ee<=jea8e7a[38];qt51f76<=jea8e7a[39];ir8fbb4<=jea8e7a[40];qg7dda4<=jea8e7a[41];bl7b15e<=jea8e7a[42];xy35ec5<=jea8e7a[43];anb485a<=jea8e7a[44];uv5ef91<=jea8e7a[45];wjf7c8d<=jea8e7a[46];uxbe46c<=jea8e7a[47];mrf2365<=jea8e7a[48];xl91b2d<=jea8e7a[49];ks8d96e<=jea8e7a[50];lq6cb71<=jea8e7a[51];gb65b8a<=jea8e7a[52];end
-always@* begin ls351cf[2047]<=force_isolate;ls351cf[2046]<=zz38f51[0];ls351cf[2044]<=blc7a8f;ls351cf[2041]<=lf3d47e;ls351cf[2034]<=do20bc9;ls351cf[2021]<=ou5e4a;ls351cf[2017]<=thcda6d;ls351cf[1995]<=vi7928a[0];ls351cf[1986]<=ea6d36f[0];ls351cf[1943]<=ic59746[0];ls351cf[1925]<=fa69b79;ls351cf[1908]<=mt26205;ls351cf[1864]<=dz64739[0];ls351cf[1855]<=fp1c200;ls351cf[1838]<=cmcba31[0];ls351cf[1803]<=kqfa2f5;ls351cf[1769]<=en44c40;ls351cf[1680]<=ux239cf;ls351cf[1662]<=fae1007;ls351cf[1628]<=vi5d188[0];ls351cf[1583]<=go53113;ls351cf[1559]<=icd17a9;ls351cf[1501]<=mr4ea09;ls351cf[1490]<=hd991c;ls351cf[1487]<=ec88708;ls351cf[1312]<=bn1ce7d;ls351cf[1276]<=ym5807;ls351cf[1209]<=ene8c43[0];ls351cf[1155]<=mt39f74;ls351cf[1118]<=ec98898;ls351cf[1070]<=jp40b00;ls351cf[1048]<=byee951;ls351cf[1023]<=gbe_mode;ls351cf[1008]<=god13fa;ls351cf[954]<=ie3102c[0];ls351cf[932]<=me4c8e7;ls351cf[927]<=kq43840;ls351cf[791]<=dmca622;ls351cf[750]<=kq49d41;ls351cf[743]<=ec310e1[0];ls351cf[577]<=wje73ee;ls351cf[524]<=ece6d;ls351cf[504]<=qv2c039;ls351cf[395]<=ne794c4;ls351cf[375]<=jp401dc;ls351cf[371]<=ay4621c[0];ls351cf[262]<=yz39b4d;ls351cf[197]<=mr6f298;ls351cf[189]<=suc44c0;ls351cf[187]<=ukee6;ls351cf[98]<=cm6de53;ls351cf[93]<=kf803b[0];ls351cf[49]<=jc4dbca;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module dm4d132 (rst_n,
- gbe_mode,
- yz26485,
- db3242c,
- thcda6d,
-
- force_isolate,
- zz38f51,
- blc7a8f,
- lf3d47e,
-
- zz38960,
- of51fb0,
- sj8fd84,
- vv7ec24
- );
-input rst_n;
-input gbe_mode;
-input yz26485;
-input db3242c;
-output thcda6d;
-input force_isolate;
-input [7:0] zz38f51;
-input blc7a8f;
-input lf3d47e;
-input [1:0] zz38960;
-output [7:0] of51fb0;
-output sj8fd84;
-output vv7ec24;
-reg [7:0] of51fb0;
-reg sj8fd84;
-reg vv7ec24;
-reg [1:0] ic59746;
-reg [1:0] cmcba31;
-reg [1:0] vi5d188;
-reg [1:0] ene8c43;
-reg [1:0] ay4621c;
-reg [1:0] ec310e1;
-reg ec88708;
-reg kq43840;
-reg fp1c200;
-reg fae1007;
-reg thcda6d;
-reg [6:0] ea6d36f;
-reg fa69b79;
-reg kqfa2f5;
-reg jp40b00;
-reg [7:0] kf803b;
-reg ukee6;
-reg jp401dc;
-reg jc4dbca;
-reg cm6de53;
-reg mr6f298;
-reg ne794c4;
-reg dmca622;
-reg go53113;
-reg ec98898;
-reg suc44c0;
-reg rv22600;
-reg aycb494;
-reg aa98036;
-reg [7 : 0] rgc01b1;
-reg gqd8a;
-reg db6c51;
-reg [1 : 0] epa1d8f;
-reg [1 : 0] an3628e;
-reg [1 : 0] epb1475;
-reg [1 : 0] gd8a3ac;
-reg [1 : 0] gb51d65;
-reg [1 : 0] hd8eb2c;
-reg [1 : 0] kd75966;
-reg ecacb35;
-reg cz659a8;
-reg ir2cd44;
-reg ho66a24;
-reg [6 : 0] tuc57be;
-reg wy2bdf2;
-reg ls1b459;
-reg th40935;
-reg [7 : 0] zm35123;
-reg cz448d2;
-reg ria891a;
-reg uv5ef91;
-reg wjf7c8d;
-reg uxbe46c;
-reg mrf2365;
-reg xl91b2d;
-reg ks8d96e;
-reg lq6cb71;
-reg gb65b8a;
-reg [2047:0] ls351cf;
-wire [31:0] jea8e7a;
-
-localparam ps473d2 = 32,wl39e93 = 32'hfdffca8b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ec98898 <= 1'b0; suc44c0 <= 1'b0; end else begin ec98898 <= aa98036; suc44c0 <= lq6cb71; end
-end
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jc4dbca <= 1'b0; cm6de53 <= 1'b0; mr6f298 <= 1'b0; ne794c4 <= 1'b0; dmca622 <= 1'b0; go53113 <= 1'b0; end else begin jc4dbca <= rv22600; cm6de53 <= uv5ef91;
- mr6f298 <= wjf7c8d; ne794c4 <= wjf7c8d & (~uxbe46c); dmca622 <= ~wjf7c8d & (uxbe46c); go53113 <= mrf2365 || xl91b2d; end
-end
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ic59746 <= 2'd0; cmcba31 <= 2'd0; vi5d188 <= 2'd0; ene8c43 <= 2'd0; ay4621c <= 2'd0; ec310e1 <= 2'd0; ec88708 <= 1'b1; kq43840 <= 1'b0; fp1c200 <= 1'b0; fae1007 <= 1'b0; end else begin ic59746 <= epa1d8f; cmcba31 <= an3628e; vi5d188 <= epb1475; ene8c43 <= gd8a3ac; if ((epb1475==gd8a3ac) && (epb1475==gb51d65)) ay4621c <= gb51d65; ec310e1 <= hd8eb2c; if (ks8d96e) ec88708 <= 1'b1; else if (hd8eb2c != kd75966) ec88708 <= 1'b1; else ec88708 <= 1'b0; if (uxbe46c) begin kq43840 <= 1'b1; fp1c200 <= 1'b0; fae1007 <= 1'b0; end else begin kq43840 <= hd8eb2c[1]; fp1c200 <= !hd8eb2c[1] & ( hd8eb2c[0]); fae1007 <= !hd8eb2c[1] & (!hd8eb2c[0]); end end
-end
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ea6d36f <= 7'd0; fa69b79 <= 1'b0; end else begin if (ecacb35 || wy2bdf2) begin ea6d36f <= 7'd0; end else begin ea6d36f <= tuc57be + 1; end
- if (ecacb35) begin fa69b79 <= 1'b0; end else if (ir2cd44) begin if (tuc57be == 7'd8) begin fa69b79 <= 1'b1; end else begin fa69b79 <= 1'b0; end end else if (ho66a24) begin if (tuc57be == 7'd98) begin fa69b79 <= 1'b1; end else begin fa69b79 <= 1'b0; end end else begin fa69b79 <= 1'b1; end end
-end
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin thcda6d <= 1'b0; end else begin if (ecacb35) begin thcda6d <= 1'b0; end else if (ir2cd44) begin if (tuc57be == 7'd3) begin thcda6d <= 1'b1; end else begin thcda6d <= 1'b0; end end else if (ho66a24) begin if (tuc57be == 7'd49) begin thcda6d <= 1'b1; end else begin thcda6d <= 1'b0; end end else begin thcda6d <= 1'b1; end end
-end
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jp401dc <= 0; ukee6 <= 0; kf803b <= 8'd0; end else begin if (aycb494) begin if (gb65b8a) begin kf803b <= 8'd0; ukee6 <= 1'b0; jp401dc <= 1'b0; end else begin kf803b <= rgc01b1; ukee6 <= db6c51; jp401dc <= gqd8a; end end end
-end
-
-
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin sj8fd84 <= 0; vv7ec24 <= 0; of51fb0 <= 8'd0; end else begin if (aycb494) begin vv7ec24 <= cz448d2; sj8fd84 <= ria891a; of51fb0 <= zm35123; end end
-end
-
-
-
-
-
-always@* begin rv22600<=jea8e7a[0];aycb494<=jea8e7a[1];aa98036<=jea8e7a[2];rgc01b1<={zz38f51>>1,jea8e7a[3]};gqd8a<=jea8e7a[4];db6c51<=jea8e7a[5];epa1d8f<={zz38960>>1,jea8e7a[6]};an3628e<={ic59746>>1,jea8e7a[7]};epb1475<={cmcba31>>1,jea8e7a[8]};gd8a3ac<={vi5d188>>1,jea8e7a[9]};gb51d65<={ene8c43>>1,jea8e7a[10]};hd8eb2c<={ay4621c>>1,jea8e7a[11]};kd75966<={ec310e1>>1,jea8e7a[12]};ecacb35<=jea8e7a[13];cz659a8<=jea8e7a[14];ir2cd44<=jea8e7a[15];ho66a24<=jea8e7a[16];tuc57be<={ea6d36f>>1,jea8e7a[17]};wy2bdf2<=jea8e7a[18];ls1b459<=jea8e7a[19];th40935<=jea8e7a[20];zm35123<={kf803b>>1,jea8e7a[21]};cz448d2<=jea8e7a[22];ria891a<=jea8e7a[23];uv5ef91<=jea8e7a[24];wjf7c8d<=jea8e7a[25];uxbe46c<=jea8e7a[26];mrf2365<=jea8e7a[27];xl91b2d<=jea8e7a[28];ks8d96e<=jea8e7a[29];lq6cb71<=jea8e7a[30];gb65b8a<=jea8e7a[31];end
-always@* begin ls351cf[2047]<=db3242c;ls351cf[2046]<=force_isolate;ls351cf[2044]<=zz38f51[0];ls351cf[2040]<=blc7a8f;ls351cf[2032]<=lf3d47e;ls351cf[2017]<=zz38960[0];ls351cf[1987]<=ic59746[0];ls351cf[1926]<=cmcba31[0];ls351cf[1804]<=vi5d188[0];ls351cf[1803]<=jp401dc;ls351cf[1560]<=ene8c43[0];ls351cf[1558]<=jc4dbca;ls351cf[1550]<=fae1007;ls351cf[1464]<=ec98898;ls351cf[1072]<=ay4621c[0];ls351cf[1069]<=cm6de53;ls351cf[1052]<=ea6d36f[0];ls351cf[1023]<=gbe_mode;ls351cf[901]<=ukee6;ls351cf[880]<=suc44c0;ls351cf[775]<=fp1c200;ls351cf[732]<=go53113;ls351cf[450]<=kf803b[0];ls351cf[387]<=kq43840;ls351cf[366]<=dmca622;ls351cf[225]<=jp40b00;ls351cf[193]<=ec88708;ls351cf[183]<=ne794c4;ls351cf[112]<=kqfa2f5;ls351cf[96]<=ec310e1[0];ls351cf[91]<=mr6f298;ls351cf[56]<=fa69b79;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module vv55b56 (rst_n,
- gbe_mode,
- force_isolate,
- yz26485,
- db3242c,
- thcda6d,
-
- zz38f51,
- blc7a8f,
- lf3d47e,
- do20bc9,
- ou5e4a,
-
- zz38960,
- of51fb0,
- sj8fd84,
- vv7ec24,
- yz8a53d,
- tu529ed
- );
-input rst_n;
-input gbe_mode;
-input force_isolate;
-input yz26485;
-input db3242c;
-output thcda6d;
-input [7:0] zz38f51;
-input blc7a8f;
-input lf3d47e;
-input do20bc9;
-input ou5e4a;
-input [1:0] zz38960;
-output [7:0] of51fb0;
-output sj8fd84;
-output vv7ec24;
-output yz8a53d;
-output tu529ed;
-reg [7:0] of51fb0;
-reg sj8fd84;
-reg vv7ec24;
-reg yz8a53d;
-reg tu529ed;
-reg [1:0] ic59746;
-reg [1:0] cmcba31;
-reg [1:0] vi5d188;
-reg [1:0] ene8c43;
-reg [1:0] ay4621c;
-reg [1:0] ec310e1;
-reg ec88708;
-reg kq43840;
-reg fp1c200;
-reg fae1007;
-reg thcda6d;
-reg [6:0] ea6d36f;
-reg fa69b79;
-reg kqfa2f5;
-reg jp40b00;
-reg [7:0] kf803b;
-reg ukee6;
-reg jp401dc;
-reg kq49d41;
-reg mr4ea09;
-reg jc4dbca;
-reg cm6de53;
-reg mr6f298;
-reg ne794c4;
-reg dmca622;
-reg go53113;
-reg ec98898;
-reg suc44c0;
-reg rv22600;
-reg aa98036;
-reg aycb494;
-reg [7 : 0] rgc01b1;
-reg gqd8a;
-reg db6c51;
-reg zk42a46;
-reg sw15232;
-reg [1 : 0] epa1d8f;
-reg [1 : 0] an3628e;
-reg [1 : 0] epb1475;
-reg [1 : 0] gd8a3ac;
-reg [1 : 0] gb51d65;
-reg [1 : 0] hd8eb2c;
-reg [1 : 0] kd75966;
-reg ecacb35;
-reg cz659a8;
-reg ir2cd44;
-reg ho66a24;
-reg [6 : 0] tuc57be;
-reg wy2bdf2;
-reg ls1b459;
-reg th40935;
-reg [7 : 0] zm35123;
-reg cz448d2;
-reg ria891a;
-reg fa523cb;
-reg zz91e5a;
-reg uv5ef91;
-reg wjf7c8d;
-reg uxbe46c;
-reg mrf2365;
-reg xl91b2d;
-reg ks8d96e;
-reg lq6cb71;
-reg gb65b8a;
-reg [2047:0] ls351cf;
-wire [35:0] jea8e7a;
-
-localparam ps473d2 = 36,wl39e93 = 32'hfdffd42b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jc4dbca <= 1'b0; cm6de53 <= 1'b0; mr6f298 <= 1'b0; ne794c4 <= 1'b0; dmca622 <= 1'b0; go53113 <= 1'b0; end else begin jc4dbca <= rv22600; cm6de53 <= uv5ef91;
- mr6f298 <= wjf7c8d; ne794c4 <= wjf7c8d & (~uxbe46c); dmca622 <= ~wjf7c8d & (uxbe46c); go53113 <= mrf2365 || xl91b2d; end
-end
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ic59746 <= 2'd0; cmcba31 <= 2'd0; vi5d188 <= 2'd0; ene8c43 <= 2'd0; ay4621c <= 2'd0; ec310e1 <= 2'd0; ec88708 <= 1'b1; kq43840 <= 1'b0; fp1c200 <= 1'b0; fae1007 <= 1'b0; end else begin ic59746 <= epa1d8f; cmcba31 <= an3628e; vi5d188 <= epb1475; ene8c43 <= gd8a3ac; if ((epb1475==gd8a3ac) && (epb1475==gb51d65)) ay4621c <= gb51d65; ec310e1 <= hd8eb2c; if (ks8d96e) ec88708 <= 1'b1; else if (hd8eb2c != kd75966) ec88708 <= 1'b1; else ec88708 <= 1'b0; if (uxbe46c) begin kq43840 <= 1'b1; fp1c200 <= 1'b0; fae1007 <= 1'b0; end else begin kq43840 <= hd8eb2c[1]; fp1c200 <= !hd8eb2c[1] & ( hd8eb2c[0]); fae1007 <= !hd8eb2c[1] & (!hd8eb2c[0]); end end
-end
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ea6d36f <= 7'd0; fa69b79 <= 1'b0; end else begin if (ecacb35 || wy2bdf2) begin ea6d36f <= 7'd0; end else begin ea6d36f <= tuc57be + 1; end
- if (ecacb35) begin fa69b79 <= 1'b0; end else if (ir2cd44) begin if (tuc57be == 7'd8) begin fa69b79 <= 1'b1; end else begin fa69b79 <= 1'b0; end end else if (ho66a24) begin if (tuc57be == 7'd98) begin fa69b79 <= 1'b1; end else begin fa69b79 <= 1'b0; end end else begin fa69b79 <= 1'b1; end end
-end
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin thcda6d <= 1'b0; end else begin if (ecacb35) begin thcda6d <= 1'b0; end else if (ir2cd44) begin if (tuc57be == 7'd3) begin thcda6d <= 1'b1; end else begin thcda6d <= 1'b0; end end else if (ho66a24) begin if (tuc57be == 7'd49) begin thcda6d <= 1'b1; end else begin thcda6d <= 1'b0; end end else begin thcda6d <= 1'b1; end end
-end
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jp401dc <= 0; ukee6 <= 0; kq49d41 <= 0; mr4ea09 <= 0; kf803b <= 8'd0; end else begin if (aycb494) begin kf803b <= rgc01b1; ukee6 <= db6c51; jp401dc <= gqd8a; kq49d41 <= zk42a46; mr4ea09 <= sw15232; end end
-end
-
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ec98898 <= 1'b0; suc44c0 <= 1'b0; end else begin ec98898 <= aa98036; suc44c0 <= lq6cb71; end
-end
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if (rst_n == 1'b0) begin sj8fd84 <= 0; vv7ec24 <= 0; yz8a53d <= 0; tu529ed <= 0; of51fb0 <= 8'd0; end else begin if (aycb494) begin if (gb65b8a) begin sj8fd84 <= 0; vv7ec24 <= 0; yz8a53d <= 0; tu529ed <= 0; of51fb0 <= 8'd0; end else begin vv7ec24 <= cz448d2; yz8a53d <= fa523cb; tu529ed <= zz91e5a; if ((!cz659a8) && ria891a && (zm35123 == 8'h0F) && (!cz448d2) && vv7ec24) begin sj8fd84 <= 1'b0; of51fb0 <= 8'h00; end else begin sj8fd84 <= ria891a; of51fb0 <= zm35123; end end end
- end
-end
-
-
-
-
-
-always@* begin rv22600<=jea8e7a[0];aa98036<=jea8e7a[1];aycb494<=jea8e7a[2];rgc01b1<={zz38f51>>1,jea8e7a[3]};gqd8a<=jea8e7a[4];db6c51<=jea8e7a[5];zk42a46<=jea8e7a[6];sw15232<=jea8e7a[7];epa1d8f<={zz38960>>1,jea8e7a[8]};an3628e<={ic59746>>1,jea8e7a[9]};epb1475<={cmcba31>>1,jea8e7a[10]};gd8a3ac<={vi5d188>>1,jea8e7a[11]};gb51d65<={ene8c43>>1,jea8e7a[12]};hd8eb2c<={ay4621c>>1,jea8e7a[13]};kd75966<={ec310e1>>1,jea8e7a[14]};ecacb35<=jea8e7a[15];cz659a8<=jea8e7a[16];ir2cd44<=jea8e7a[17];ho66a24<=jea8e7a[18];tuc57be<={ea6d36f>>1,jea8e7a[19]};wy2bdf2<=jea8e7a[20];ls1b459<=jea8e7a[21];th40935<=jea8e7a[22];zm35123<={kf803b>>1,jea8e7a[23]};cz448d2<=jea8e7a[24];ria891a<=jea8e7a[25];fa523cb<=jea8e7a[26];zz91e5a<=jea8e7a[27];uv5ef91<=jea8e7a[28];wjf7c8d<=jea8e7a[29];uxbe46c<=jea8e7a[30];mrf2365<=jea8e7a[31];xl91b2d<=jea8e7a[32];ks8d96e<=jea8e7a[33];lq6cb71<=jea8e7a[34];gb65b8a<=jea8e7a[35];end
-always@* begin ls351cf[2047]<=force_isolate;ls351cf[2046]<=db3242c;ls351cf[2044]<=zz38f51[0];ls351cf[2041]<=blc7a8f;ls351cf[2035]<=lf3d47e;ls351cf[2022]<=do20bc9;ls351cf[1996]<=ou5e4a;ls351cf[1945]<=zz38960[0];ls351cf[1922]<=jp401dc;ls351cf[1842]<=ic59746[0];ls351cf[1797]<=kq49d41;ls351cf[1776]<=jp40b00;ls351cf[1637]<=cmcba31[0];ls351cf[1622]<=ec310e1[0];ls351cf[1546]<=mr4ea09;ls351cf[1504]<=kf803b[0];ls351cf[1468]<=fa69b79;ls351cf[1391]<=fae1007;ls351cf[1312]<=ec98898;ls351cf[1226]<=vi5d188[0];ls351cf[1197]<=ec88708;ls351cf[1044]<=jc4dbca;ls351cf[1023]<=gbe_mode;ls351cf[961]<=ukee6;ls351cf[888]<=kqfa2f5;ls351cf[811]<=ay4621c[0];ls351cf[734]<=ea6d36f[0];ls351cf[695]<=fp1c200;ls351cf[656]<=go53113;ls351cf[576]<=suc44c0;ls351cf[405]<=ene8c43[0];ls351cf[347]<=kq43840;ls351cf[328]<=dmca622;ls351cf[164]<=ne794c4;ls351cf[82]<=mr6f298;ls351cf[41]<=cm6de53;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module ldf627d ( yz26485,
- rst_n,
-
- gbe_mode,
- sgmii_mode,
- force_unidir,
-
- mr_main_reset,
- mr_restart_an,
- mr_an_enable,
- mr_adv_ability,
- mr_lp_adv_ability,
- nr4ae92,
- mr_page_rx,
- mr_an_complete,
-
- bld2597,
-
- qi92cbe,
- ls965f1,
- twb2f8a,
-
- uk97c52,
- sjbe291,
- vif148d,
- an_link_ok
- );
-input yz26485;
-input rst_n;
-input gbe_mode;
-input sgmii_mode;
-input force_unidir;
-input mr_main_reset;
-input mr_restart_an;
-input mr_an_enable;
-input [16:1] mr_adv_ability;
-output [16:1] mr_lp_adv_ability;
-input nr4ae92;
-output mr_page_rx;
-output mr_an_complete;
-input bld2597;
-input qi92cbe;
-input ls965f1;
-input twb2f8a;
-input [15:0] uk97c52;
-output [15:0] sjbe291;
-output [1:0] vif148d;
-output an_link_ok;
-reg [16:1] mr_lp_adv_ability;
-reg mr_page_rx;
-reg mr_an_complete;
-reg [15:0] sjbe291;
-reg [1:0] vif148d;
-reg [15:0] kq68466;
-reg [15:0] by42331;
-reg [15:0] ng1198b;
-reg [15:0] je8cc5a;
-reg [15:0] dm662d3;
-reg ou3169a;
-localparam jr8b4d0 = 2'b00, fn5a687 = 2'b01, czd343e = 2'b10;
-localparam an9a1f4 = 4'b0000, ned0fa4 = 4'b0001, ie87d22 = 4'b0010, mg3e910 = 4'b0011, vif4880 = 4'b0100, qva4403 = 4'b0101, vx2201d = 4'b0111, co100ee = 4'b1000;
-parameter ep80771 = 21'h1cf2bf, jr3b8c = 21'h0ced2f, LINK_TIMER_SH = 21'h1fff01;
-reg hoee334;
-reg bl719a2;
-reg ls8cd17;
-reg tu668bb;
-reg qi345db;
-reg [20:0] xya2ed8;
-reg yz176c3;
-reg [20:0] uxbb61c;
-reg kqdb0e5;
-reg [3:0] rtd8728, yxc3947, nt1ca3c;
-wire [15:0] uk97c52;
-reg [15:0] ph28f31;
-reg [15:0] lq4798e;
-reg [15:0] mt3cc72;
-reg [ 1:0] ble6395;
-reg [ 1:0] ym31cae;
-reg [ 1:0] ph8e571;
-wire twb2f8a;
-reg kf95c78;
-wire ls965f1;
-reg pf71e24;
-reg ux8f127;
-reg me7893d;
-reg ykc49e9;
-reg ou24f49;
-reg bn27a48;
-reg fp3d247;
-reg the923e;
-reg ui491f7;
-reg jc48fb8;
-reg dm47dc3;
-reg ym3ee1a;
-reg [16:1] off70d0;
-reg lsb8685;
-reg ofc342a;
-reg mg1a155;
-reg fad0aa8;
-reg yz85542;
-reg[15:0] ls2aa14;
-reg ld550a3;
-reg xya851f;
-reg by428fb;
-reg je147da;
-reg [16:1] gqa3ed3;
-reg qi1f699;
-reg lqfb4c8;
-reg rgda643;
-reg uvd321a;
-reg ng990d4;
-reg[15:0] thc86a3;
-reg ay4351e ;
-reg ec1a8f1 ;
-wire wwd4789 ;
-reg [(22*8):1] gqa3c49;
-reg rv22600;
-reg tuf124a;
-reg vk89252;
-reg qg49292;
-reg cm49490;
-reg xj4a480;
-reg [16 : 1] lq52407;
-reg sw9203a;
-reg yz901d0;
-reg yz80e85;
-reg qv742d;
-reg do3a16d;
-reg [15 : 0] fad0b6b;
-reg [15 : 0] yz85b5a;
-reg [15 : 0] rv2dad5;
-reg [15 : 0] ay6d6ae;
-reg [15 : 0] bl6b571;
-reg fn5ab8e;
-reg fad5c77;
-reg yzae3ba;
-reg hb71dd4;
-reg jr8eea7;
-reg yk7753e;
-reg [20 : 0] phba9f1;
-reg sud4f8e;
-reg [20 : 0] xya7c70;
-reg wy3e383;
-reg [3 : 0] byf1c19;
-reg [3 : 0] nt8e0cb;
-reg [3 : 0] kd7065f;
-reg [15 : 0] ba832fc;
-reg [15 : 0] ph197e3;
-reg [15 : 0] gocbf1f;
-reg [1 : 0] dz5f8f8;
-reg [1 : 0] rtfc7c7;
-reg [1 : 0] lde3e3e;
-reg ec1f1f7;
-reg uvf8fb8;
-reg nrc7dc5;
-reg aa3ee2e;
-reg enf7170;
-reg jeb8b85;
-reg byc5c2b;
-reg mg2e15b;
-reg of70ad8;
-reg mt856c5;
-reg sw2b62c;
-reg kd5b160;
-reg rtd8b04;
-reg [16 : 1] tuc5826;
-reg cb2c133;
-reg qt6099d;
-reg pu4cec;
-reg wl26763;
-reg mt33b1c;
-reg [15 : 0] qi9d8e4;
-reg nrec720;
-reg zk63907;
-reg ph1c83b;
-reg dme41de;
-reg [16 : 1] tw20ef3;
-reg oh779a;
-reg mg3bcd5;
-reg uide6a8;
-reg thf3540;
-reg an9aa07;
-reg [15 : 0] rgd503d;
-reg twa81eb;
-reg xj40f5b;
-reg ir7adf;
-reg [(22 * 8) : 1] ph3d6fc;
-reg [2047:0] ls351cf;
-wire [70:0] jea8e7a;
-
-localparam ps473d2 = 71,wl39e93 = 32'hfdffd84b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if(!rst_n) begin ay4351e <= 1'b1; ec1a8f1 <= 1'b1; end else begin ay4351e <= qg49292; ec1a8f1 <= twa81eb; end
-end
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if(!rst_n) begin ui491f7 <= 1'b0; jc48fb8 <= 1'b0; dm47dc3 <= 1'b0; ym3ee1a <= 1'b0; off70d0 <= 16'd0; lsb8685 <= 1'b0; ofc342a <= 1'b0; mg1a155 <= 1'b0; fad0aa8 <= 1'b0; yz85542 <= 1'b0; ls2aa14 <= 16'b0; ld550a3 <= 1'b0; xya851f <= 1'b0; by428fb <= 1'b0; je147da <= 1'b0; gqa3ed3 <= 16'b0; qi1f699 <= 1'b0; lqfb4c8 <= 1'b0; rgda643 <= 1'b0; uvd321a <= 1'b0; ng990d4 <= 1'b0; thc86a3 <= 16'b0; end else begin ui491f7 <= rv22600; jc48fb8 <= tuf124a; dm47dc3 <= cm49490; ym3ee1a <= xj4a480 & (!vk89252); off70d0 <= lq52407; lsb8685 <= sw9203a; ofc342a <= yz901d0; mg1a155 <= yz80e85; fad0aa8 <= qv742d; yz85542 <= do3a16d; ls2aa14 <= uk97c52; ld550a3 <= mt856c5; xya851f <= sw2b62c; by428fb <= kd5b160; je147da <= rtd8b04; gqa3ed3 <= tuc5826; qi1f699 <= cb2c133; lqfb4c8 <= qt6099d; rgda643 <= pu4cec; uvd321a <= wl26763; ng990d4 <= mt33b1c; thc86a3 <= qi9d8e4; end
-end
-
-
-
-assign wwd4789 = (rgd503d[15] == ph197e3[15]) & (rgd503d[13:0] == ph197e3[13:0]);
-
-always @(posedge yz26485 or negedge rst_n) begin : mg3b5b9 if(!rst_n) begin pf71e24 <= 1'b0; ux8f127 <= 1'b0; me7893d <= 1'b0; ykc49e9 <= 1'b0; ou24f49 <= 1'b0; bn27a48 <= 1'b0; fp3d247 <= 1'b0; the923e <= 1'b0; end else begin pf71e24 <= (fad5c77 != dme41de); ux8f127 <= ir7adf ; me7893d <= ir7adf & rgd503d[14] & ph197e3[14]; ykc49e9 <= (dz5f8f8 == 2'b10) & ec1f1f7; ou24f49 <= (rtfc7c7 == 2'b10) & ec1f1f7; bn27a48 <= (lde3e3e == 2'b11); fp3d247 <= (dz5f8f8 == 2'b10) & ec1f1f7 & ir7adf ; the923e <= (kd7065f != nt8e0cb); end
-end
-
-always @(posedge yz26485 or negedge rst_n) begin : fa73b89 if(!rst_n) begin yxc3947 <= an9a1f4; end else begin if(ph1c83b || !wy3e383 || uvf8fb8 || uide6a8 || fn5ab8e || xj40f5b) begin yxc3947 <= an9a1f4; end else begin yxc3947 <= byf1c19; end end
-end
-always @(posedge yz26485 or negedge rst_n) begin if(!rst_n) begin nt1ca3c <= an9a1f4; hoee334 <= 1'b0; kf95c78 <= 1'b0; ph28f31 <= 16'h0000; end else begin if(xj40f5b) begin nt1ca3c <= an9a1f4; end else begin nt1ca3c <= nt8e0cb; hoee334 <= dme41de; kf95c78 <= an9aa07; ph28f31 <= rgd503d; end end
-end
-
-always @( nt8e0cb or dme41de or sud4f8e or enf7170 or ba832fc or jeb8b85 or mg2e15b or byc5c2b) begin : zkdfcb3 case (nt8e0cb) an9a1f4 : begin if(dme41de) rtd8728 = ned0fa4; else rtd8728 = ie87d22; end
- ned0fa4 : begin if(sud4f8e) rtd8728 = mg3e910; else rtd8728 = ned0fa4; end
- mg3e910 : begin if(enf7170 && ba832fc != 16'd0) rtd8728 = vif4880; else rtd8728 = mg3e910; end
- vif4880 : begin if((jeb8b85 && !mg2e15b) || (enf7170 && ba832fc == 16'h0000)) rtd8728 = an9a1f4; else if(jeb8b85 && mg2e15b) rtd8728 = qva4403; else rtd8728 = vif4880; end
- qva4403 : begin if(enf7170 && ba832fc == 16'h0000) rtd8728 = an9a1f4; else if((sud4f8e) && (!enf7170 || ba832fc != 16'h0000)) rtd8728 = vx2201d; else rtd8728 = qva4403; end
- vx2201d : begin if (enf7170 && ba832fc == 16'h0000) rtd8728 = an9a1f4; else if (byc5c2b && sud4f8e) rtd8728 = co100ee; else rtd8728 = vx2201d; end
- co100ee : begin if (enf7170) rtd8728 = an9a1f4; else rtd8728 = co100ee; end
- ie87d22 : rtd8728 = ie87d22;
- default : begin rtd8728 = an9a1f4; end
- endcase
-end
-
-always @(posedge yz26485 or negedge rst_n) begin if(!rst_n) begin mr_page_rx <= 1'b0; end else begin if (nt8e0cb == qva4403) begin mr_page_rx <= 1'b1; end else begin mr_page_rx <= 1'b0; end end
-end
-
-always @(posedge yz26485 or negedge rst_n) begin if(!rst_n ) begin mr_lp_adv_ability <= 16'h0000; end else begin if ((nt8e0cb == an9a1f4) || (nt8e0cb == mg3e910)) begin mr_lp_adv_ability <= 16'h0000; end else if (nt8e0cb == qva4403) begin mr_lp_adv_ability <= rgd503d; end else begin mr_lp_adv_ability <= mr_lp_adv_ability; end end
-end
-
-
-always @(posedge yz26485 or negedge rst_n) begin : xjd751c if(!rst_n ) begin mr_an_complete <= 1'b0; end else begin if (nt8e0cb == an9a1f4) begin mr_an_complete <= 1'b0; end else if (nt8e0cb == co100ee) begin mr_an_complete <= 1'b1; end else begin mr_an_complete <= mr_an_complete; end end
-end
-
-always @(posedge yz26485 or negedge rst_n) begin : ho6381f if(!rst_n ) begin sjbe291 <= 16'd0; end else begin if ((nt8e0cb == an9a1f4 && dme41de) || (nt8e0cb == ned0fa4)) begin sjbe291 <= 16'd0; end else if (nt8e0cb == mg3e910) begin sjbe291 <= {tw20ef3[16],1'b0,tw20ef3[14:1]}; end else if (nt8e0cb == vif4880) begin sjbe291 <= (sjbe291 | 16'h4000); end else begin sjbe291 <= sjbe291; end end
-end
-
-always @(posedge yz26485 or negedge rst_n) begin : qva1bd8 if(!rst_n ) begin vif148d <= jr8b4d0; end else begin if (((nt8e0cb == an9a1f4) && dme41de) || (nt8e0cb == ned0fa4)) begin vif148d <= fn5a687; end else if (((nt8e0cb == an9a1f4) && !dme41de) || (nt8e0cb == vx2201d)) begin vif148d <= jr8b4d0; end else if ((nt8e0cb == ie87d22) || (nt8e0cb == co100ee)) begin vif148d <= czd343e; end else begin vif148d <= vif148d; end end
-end
-
-
-
-
-always @(posedge yz26485 or negedge rst_n) begin if(!rst_n ) begin ls8cd17 <= 1'b0; tu668bb <= 1'b0; qi345db <= 1'b0; bl719a2 <= 1'b0; end else begin if ((nt8e0cb == ned0fa4) && (kd7065f == an9a1f4)) begin ls8cd17 <= 1'b1; end else begin ls8cd17 <= 1'b0; end if ((nt8e0cb == qva4403) && (kd7065f == vif4880)) begin tu668bb <= 1'b1; end else begin tu668bb <= 1'b0; end if ((nt8e0cb == vx2201d) && (kd7065f == qva4403)) begin qi345db <= 1'b1; end else begin qi345db <= 1'b0; end if (hb71dd4 || jr8eea7 || yk7753e) begin bl719a2 <= 1'b1; end else begin bl719a2 <= 1'b0; end end
-end
-always @(posedge yz26485 or negedge rst_n) begin : th74e8a if(!rst_n ) begin xya2ed8 <= ep80771; end else if (yzae3ba) begin if (oh779a) begin xya2ed8 <= LINK_TIMER_SH; end else if (nrec720) begin xya2ed8 <= jr3b8c; end else begin xya2ed8 <= ep80771; end end else if (!sud4f8e) begin xya2ed8 <= phba9f1 + 'd1; end else begin xya2ed8 <= phba9f1; end
-end
-always @(posedge yz26485 or negedge rst_n) begin : yk5c831 if(!rst_n ) begin yz176c3 <= 1'b0; end else begin if (phba9f1 == 'd0 && !yzae3ba) begin yz176c3 <= 1'b1; end else begin yz176c3 <= 1'b0; end end
-end
-
-
-
-always @(posedge yz26485 or negedge rst_n) begin : rib804e if(!rst_n ) begin uxbb61c <= 21'd0; end else if (mg3bcd5) begin if (oh779a) begin uxbb61c <= LINK_TIMER_SH; end else if (nrec720) begin uxbb61c <= jr3b8c; end else begin uxbb61c <= ep80771; end end else begin uxbb61c <= xya7c70 + 'd1; end
-end
-
-always @(posedge yz26485 or negedge rst_n) begin : xlba9b2 if(!rst_n ) begin kqdb0e5 <= 1'b0; end else begin case(wy3e383) 1'b0: begin if (mg3bcd5) begin kqdb0e5 <= 1'b1; end end 1'b1: begin if(xya7c70 == 21'd0) begin kqdb0e5 <= 1'b0; end end default: begin kqdb0e5 <= 1'b0; end endcase end
-end
-
-
-
-always @(posedge yz26485 or negedge rst_n) begin : pu96f23 if(!rst_n ) lq4798e <= 16'h0000; else if(of70ad8) lq4798e <= 16'h0000; else if(an9aa07) lq4798e <= rgd503d; else lq4798e <= ph197e3;
-end
-
-
-always @(posedge yz26485 or negedge rst_n) begin : tj91c64 if(!rst_n ) begin mt3cc72 <= 16'h0000; end else begin if(enf7170) begin mt3cc72 <= rgd503d; end else begin mt3cc72 <= gocbf1f; end end
-end
-
-always @(posedge yz26485 or negedge rst_n) begin : icf5dd1 if(!rst_n ) ble6395 <= 2'b00; else if(of70ad8 || thf3540) ble6395 <= 2'b00; else if(an9aa07 && nrc7dc5 && (dz5f8f8 != 2'b10)) ble6395 <= dz5f8f8 + 2'b01; else ble6395 <= dz5f8f8;
-end
-always @(posedge yz26485 or negedge rst_n) begin : god1dc7 if(!rst_n ) ym31cae <= 2'b00; else if(of70ad8 || thf3540) ym31cae <= 2'b00; else if(an9aa07 && aa3ee2e && (rtfc7c7 != 2'b10)) ym31cae <= rtfc7c7 + 2'b01; else ym31cae <= rtfc7c7;
-end
-
-always @(posedge yz26485 or negedge rst_n) begin : fcb8907 if(!rst_n ) ph8e571 <= 2'b00; else if(of70ad8) ph8e571 <= 2'b00; else if(thf3540 && !byc5c2b) ph8e571 <= lde3e3e + 2'b01; else ph8e571 <= lde3e3e;
-end
-
-
-
-
-always @(posedge yz26485 or negedge rst_n) begin if(!rst_n) begin kq68466 <= 16'd0; by42331 <= 16'd0; ng1198b <= 16'd0; je8cc5a <= 16'd0; dm662d3 <= 16'd0; ou3169a <= 1'b0; end else begin kq68466[15:0] <= tw20ef3[16:1]; by42331 <= fad0b6b; ng1198b <= yz85b5a; if ((fad0b6b == yz85b5a) && (fad0b6b == rv2dad5)) dm662d3 <= rv2dad5; else dm662d3 <= bl6b571; je8cc5a <= bl6b571; if ((zk63907==1'b1) && (nrec720==1'b0)) begin if (bl6b571 != ay6d6ae) begin ou3169a <= 1'b1; end else begin ou3169a <= 1'b0; end end else begin ou3169a <= 1'b0; end end
-end
-assign an_link_ok = ((nt8e0cb==co100ee) || (nt8e0cb==ie87d22)) ? 1'b1 : 1'b0;
-
-
-
-
-
-
-
-always @(nt8e0cb) begin case (nt8e0cb) an9a1f4 : gqa3c49 = "AN_ENABLE"; ned0fa4 : gqa3c49 = "AN_RESTART"; ie87d22 : gqa3c49 = "AN_DISABLE_LINK_OK"; mg3e910 : gqa3c49 = "ABILITY_DETECT"; vif4880 : gqa3c49 = "ACKNOWLEDGE_DETECT"; qva4403 : gqa3c49 = "COMPLETE_ACKNOWLEDGE"; vx2201d : gqa3c49 = "IDLE_DETECT"; co100ee : gqa3c49 = "LINK_OK";
- default : gqa3c49 = "***ERROR***"; endcase
-end
-
-always@* begin rv22600<=jea8e7a[0];tuf124a<=jea8e7a[1];vk89252<=jea8e7a[2];qg49292<=jea8e7a[3];cm49490<=jea8e7a[4];xj4a480<=jea8e7a[5];lq52407<={mr_adv_ability>>1,jea8e7a[6]};sw9203a<=jea8e7a[7];yz901d0<=jea8e7a[8];yz80e85<=jea8e7a[9];qv742d<=jea8e7a[10];do3a16d<=jea8e7a[11];fad0b6b<={kq68466>>1,jea8e7a[12]};yz85b5a<={by42331>>1,jea8e7a[13]};rv2dad5<={ng1198b>>1,jea8e7a[14]};ay6d6ae<={je8cc5a>>1,jea8e7a[15]};bl6b571<={dm662d3>>1,jea8e7a[16]};fn5ab8e<=jea8e7a[17];fad5c77<=jea8e7a[18];yzae3ba<=jea8e7a[19];hb71dd4<=jea8e7a[20];jr8eea7<=jea8e7a[21];yk7753e<=jea8e7a[22];phba9f1<={xya2ed8>>1,jea8e7a[23]};sud4f8e<=jea8e7a[24];xya7c70<={uxbb61c>>1,jea8e7a[25]};wy3e383<=jea8e7a[26];byf1c19<={rtd8728>>1,jea8e7a[27]};nt8e0cb<={yxc3947>>1,jea8e7a[28]};kd7065f<={nt1ca3c>>1,jea8e7a[29]};ba832fc<={ph28f31>>1,jea8e7a[30]};ph197e3<={lq4798e>>1,jea8e7a[31]};gocbf1f<={mt3cc72>>1,jea8e7a[32]};dz5f8f8<={ble6395>>1,jea8e7a[33]};rtfc7c7<={ym31cae>>1,jea8e7a[34]};lde3e3e<={ph8e571>>1,jea8e7a[35]};ec1f1f7<=jea8e7a[36];uvf8fb8<=jea8e7a[37];nrc7dc5<=jea8e7a[38];aa3ee2e<=jea8e7a[39];enf7170<=jea8e7a[40];jeb8b85<=jea8e7a[41];byc5c2b<=jea8e7a[42];mg2e15b<=jea8e7a[43];of70ad8<=jea8e7a[44];mt856c5<=jea8e7a[45];sw2b62c<=jea8e7a[46];kd5b160<=jea8e7a[47];rtd8b04<=jea8e7a[48];tuc5826<={off70d0>>1,jea8e7a[49]};cb2c133<=jea8e7a[50];qt6099d<=jea8e7a[51];pu4cec<=jea8e7a[52];wl26763<=jea8e7a[53];mt33b1c<=jea8e7a[54];qi9d8e4<={ls2aa14>>1,jea8e7a[55]};nrec720<=jea8e7a[56];zk63907<=jea8e7a[57];ph1c83b<=jea8e7a[58];dme41de<=jea8e7a[59];tw20ef3<={gqa3ed3>>1,jea8e7a[60]};oh779a<=jea8e7a[61];mg3bcd5<=jea8e7a[62];uide6a8<=jea8e7a[63];thf3540<=jea8e7a[64];an9aa07<=jea8e7a[65];rgd503d<={thc86a3>>1,jea8e7a[66]};twa81eb<=jea8e7a[67];xj40f5b<=jea8e7a[68];ir7adf<=jea8e7a[69];ph3d6fc<={gqa3c49>>1,jea8e7a[70]};end
-always@* begin ls351cf[2047]<=sgmii_mode;ls351cf[2046]<=force_unidir;ls351cf[2044]<=mr_main_reset;ls351cf[2040]<=mr_restart_an;ls351cf[2033]<=mr_an_enable;ls351cf[2019]<=mr_adv_ability[1];ls351cf[1999]<=ph8e571[0];ls351cf[1991]<=nr4ae92;ls351cf[1981]<=ofc342a;ls351cf[1958]<=ld550a3;ls351cf[1950]<=kf95c78;ls351cf[1947]<=bn27a48;ls351cf[1934]<=bld2597;ls351cf[1914]<=mg1a155;ls351cf[1892]<=ls8cd17;ls351cf[1868]<=xya851f;ls351cf[1852]<=pf71e24;ls351cf[1851]<=je8cc5a[0];ls351cf[1847]<=fp3d247;ls351cf[1820]<=qi92cbe;ls351cf[1783]<=ym3ee1a;ls351cf[1780]<=fad0aa8;ls351cf[1737]<=tu668bb;ls351cf[1689]<=by428fb;ls351cf[1657]<=ux8f127;ls351cf[1654]<=dm662d3[0];ls351cf[1647]<=the923e;ls351cf[1610]<=yz176c3;ls351cf[1608]<=uvd321a;ls351cf[1593]<=ls965f1;ls351cf[1523]<=ble6395[0];ls351cf[1519]<=off70d0[1];ls351cf[1513]<=yz85542;ls351cf[1426]<=qi345db;ls351cf[1404]<=lq4798e[0];ls351cf[1330]<=je147da;ls351cf[1267]<=me7893d;ls351cf[1260]<=ou3169a;ls351cf[1246]<=ui491f7;ls351cf[1225]<=qi1f699;ls351cf[1199]<=yxc3947[0];ls351cf[1173]<=uxbb61c[0];ls351cf[1169]<=ng990d4;ls351cf[1163]<=ec1a8f1;ls351cf[1139]<=twb2f8a;ls351cf[1023]<=gbe_mode;ls351cf[999]<=ym31cae[0];ls351cf[990]<=lsb8685;ls351cf[979]<=ls2aa14[0];ls351cf[973]<=ou24f49;ls351cf[946]<=bl719a2;ls351cf[925]<=ng1198b[0];ls351cf[891]<=dm47dc3;ls351cf[805]<=xya2ed8[0];ls351cf[804]<=rgda643;ls351cf[761]<=mt3cc72[0];ls351cf[702]<=ph28f31[0];ls351cf[612]<=gqa3ed3[1];ls351cf[599]<=rtd8728[0];ls351cf[581]<=ay4351e;ls351cf[556]<=gqa3c49[1];ls351cf[486]<=ykc49e9;ls351cf[473]<=hoee334;ls351cf[462]<=by42331[0];ls351cf[445]<=jc48fb8;ls351cf[402]<=lqfb4c8;ls351cf[351]<=nt1ca3c[0];ls351cf[299]<=kqdb0e5;ls351cf[290]<=thc86a3[0];ls351cf[278]<=wwd4789;ls351cf[231]<=kq68466[0];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module gb65565 (
-
- ri2ab2d ,
- rst_n ,
- mr_main_reset ,
- sgmii_mode ,
- gbe_mode ,
- jp6bc27 ,
-
-
- rx_data ,
- rx_kcntl ,
- db84fe1 ,
-
- bld2597 ,
- rx_even ,
- vif148d ,
-
-
- uk97c52 ,
- cofeb2 ,
- wj7f590 ,
- ayfac85 ,
-
- end6428 ,
- pub2144 ,
- ux90a23
- );
-input ri2ab2d;
-input rst_n;
-input mr_main_reset;
-input sgmii_mode;
-input gbe_mode;
-input jp6bc27;
-input [7:0] rx_data;
-input rx_kcntl;
-input db84fe1;
-input bld2597;
-input rx_even;
-input [1:0] vif148d;
-output [15:0] uk97c52;
-output cofeb2;
-output wj7f590;
-output ayfac85;
-output [7:0] end6428;
-output pub2144;
-output ux90a23;
-localparam ep2ca37 = 8'hBC , cz651bc = 8'hFE , nt28de5 = 8'hFB , ui46f2e = 8'hFD , hd37970 = 8'hF7 , cobcb86 = 8'hB5 , wwe5c31 = 8'h42 , ks2e188 = 8'hC5 , yx70c40 = 8'h50 , ng86205 = 8'h00 , ec3102b = 8'hFC , ec88158 = 8'h3C ;
-localparam nr40ac0 = 5'd0 , ec5607 = 5'd1 , gq2b038 = 5'd2 , rg581c0 = 5'd3 , xwc0e03 = 5'd4 , ir701b = 5'd5 , tj380dd = 5'd6 , zkc06ee = 5'd7 , vx3772 = 5'd8 , ri1bb97 = 5'd9 , zxddcbb = 5'd10 , faee5de = 5'd11 , ic72ef2 = 5'd12 , ks97790 = 5'd13 , mtbbc80 = 5'd14 , uide404 = 5'd15 , shf2020 = 5'd16 , sj90105 = 5'd17 ;
-reg cb8082d;
-wire vk416d;
-wire ux90a23;
-reg pub2144;
-reg [7:0] end6428;
-reg ic6d48e;
-reg [15:0] uk97c52;
-reg cofeb2;
-reg wj7f590;
-reg ayfac85;
-reg [7:0] xj718b7 ;
-reg [7:0] fc8c5bf ;
-reg [7:0] su62dfa ;
-reg [7:0] lf16fd1 ;
-reg [7:0] xyb7e8f ;
-reg dbbf47a ;
-reg eafa3d7 ;
-reg med1eb9 ;
-reg cb8f5c8 ;
-reg al7ae45 ;
-reg fnd722c ;
-reg wyb9166 ;
-reg zxc8b30 ;
-reg dz45987 ;
-reg ep2cc3f ;
-reg by661fc ;
-reg zm30fe2 ;
-reg uk87f13 ;
-reg fc3f898 ;
-reg thfc4c2 ;
-reg ale2616 ;
-reg tj130b4 ;
-reg ec985a6 ;
-reg zxc2d31 ;
-reg vx1698e ;
-reg anb4c77 ;
-reg coa63bd ;
-reg gq31de8 ;
-reg bn8ef41 ;
-reg [4:0] me77a0e ;
-reg [4:0] ribd070 ;
-wire kde8382 ;
-wire cz41c15 ;
-wire vke0ad ;
-wire wj7056b ;
-wire sw82b5c ;
-wire ou15ae0 ;
-wire riad700 ;
-wire hb6b803 ;
-wire cm5c01f ;
-wire goe00f9 ;
-wire qi7c9 ;
-wire bn3e48 ;
-wire ie1f246 ;
-wire blf9230 ;
-reg [1:0] mrc9186;
-reg [1:0] xw48c34;
-reg ay4351e ;
-reg ec1a8f1 ;
-reg hq868cb;
-reg ec3465a;
-reg eca32d0;
-reg zz19680;
-reg jc4dbca;
-reg cm6de53;
-reg [(20*8):1] psd01ce;
-reg qg49292;
-reg tuf124a;
-reg rv22600;
-reg qgce76d;
-reg [7 : 0] ho73b69;
-reg co9db4a;
-reg eneda50;
-reg yz901d0;
-reg zk69421;
-reg [1 : 0] th4a10b;
-reg hb5085f;
-reg ph842fe;
-reg qi217f6;
-reg [7 : 0] twbfb1;
-reg [7 : 0] dz5fd8a;
-reg [7 : 0] psfec57;
-reg [7 : 0] vvf62ba;
-reg [7 : 0] qvb15d7;
-reg yz8aebc;
-reg ps575e4;
-reg bnbaf22;
-reg nrd7916;
-reg mgbc8b7;
-reg zke45b9;
-reg ph22dcb;
-reg nt16e5f;
-reg ngb72ff;
-reg cob97fb;
-reg sucbfd8;
-reg vv5fec0;
-reg cmff607;
-reg xwfb039;
-reg ldd81cb;
-reg byc0e5f;
-reg oh72fb;
-reg oh397dd;
-reg kqcbeec;
-reg jp5f760;
-reg hofbb06;
-reg jpdd832;
-reg jpec196;
-reg uv60cb7;
-reg [4 : 0] xl65bc;
-reg [4 : 0] jr32de7;
-reg tw96f3e;
-reg jeb79f3;
-reg swbcf9a;
-reg wje7cd1;
-reg ou3e68d;
-reg rtf3469;
-reg kf9a34f;
-reg osd1a7c;
-reg qi8d3e0;
-reg dm69f00;
-reg vv4f802;
-reg rg7c016;
-reg ice00b2;
-reg gq591;
-reg [1 : 0] yz2c88;
-reg [1 : 0] nt16444;
-reg twa81eb;
-reg xj40f5b;
-reg ec8899f;
-reg qt44cf9;
-reg ep267cd;
-reg yz33e6c;
-reg uv5ef91;
-reg wjf7c8d;
-reg [(20 * 8) : 1] pfcd927;
-reg [2047:0] ls351cf;
-wire [68:0] jea8e7a;
-
-localparam ps473d2 = 69,wl39e93 = 32'hfdffc70b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-always @(posedge ri2ab2d or negedge rst_n) begin if (!rst_n) begin xj718b7 <= 8'h00 ; fc8c5bf <= 8'h00 ; su62dfa <= 8'h00 ; lf16fd1 <= 8'h00 ; xyb7e8f <= 8'h00 ; dbbf47a <= 1'b0 ; eafa3d7 <= 1'b0 ; med1eb9 <= 1'b0 ; cb8f5c8 <= 1'b0 ; al7ae45 <= 1'b0 ; fnd722c <= 1'b0 ; wyb9166 <= 1'b0 ; zxc8b30 <= 1'b0 ; dz45987 <= 1'b0 ; ep2cc3f <= 1'b0 ; by661fc <= 1'b0 ; zm30fe2 <= 1'b0 ; end else begin xj718b7 <= ho73b69 ; fc8c5bf <= twbfb1 ; su62dfa <= dz5fd8a ; lf16fd1 <= psfec57 ; xyb7e8f <= vvf62ba ; dbbf47a <= co9db4a ; eafa3d7 <= yz8aebc ; med1eb9 <= ps575e4 ; cb8f5c8 <= bnbaf22 ; al7ae45 <= eneda50 ; fnd722c <= mgbc8b7 ; wyb9166 <= zke45b9 ; zxc8b30 <= ph22dcb ; ep2cc3f <= zk69421 ; by661fc <= cob97fb ; zm30fe2 <= sucbfd8 ; end
-end
-always @(posedge ri2ab2d or negedge rst_n)
-begin if(!rst_n) begin ay4351e <= 1'b1; ec1a8f1 <= 1'b1; end else begin ay4351e <= qg49292; ec1a8f1 <= twa81eb; end
-end
-
-always @(posedge ri2ab2d or negedge rst_n) begin if (!rst_n) begin mrc9186 <= 2'd0 ; xw48c34 <= 2'd0 ; hq868cb <= 1'b0 ; ec3465a <= 1'b0 ; eca32d0 <= 1'b0 ; zz19680 <= 1'b0 ; jc4dbca <= 1'b0 ; cm6de53 <= 1'b0 ; end else begin mrc9186 <= th4a10b ; xw48c34 <= yz2c88 ; hq868cb <= qgce76d ; ec3465a <= ec8899f ; eca32d0 <= tuf124a ; zz19680 <= ep267cd ; jc4dbca <= rv22600 ; cm6de53 <= uv5ef91 ; end
-end
-
-assign kde8382 = ((psfec57 == ep2ca37) & bnbaf22) ;
-assign cz41c15 = ((psfec57 == nt28de5) & bnbaf22) ;
-assign vke0ad = ((psfec57 == cobcb86) & ~bnbaf22) ;
-assign wj7056b = ((psfec57 == wwe5c31) & ~bnbaf22) ;
-assign sw82b5c = ~((psfec57 == ep2ca37) & bnbaf22) ;
-
-always @(posedge ri2ab2d or negedge rst_n) begin if (!rst_n) begin uk87f13 <= 1'b0 ; fc3f898 <= 1'b0 ; thfc4c2 <= 1'b0 ; ale2616 <= 1'b0 ; tj130b4 <= 1'b0 ; end else begin uk87f13 <= tw96f3e ; fc3f898 <= jeb79f3 ; thfc4c2 <= swbcf9a ; ale2616 <= wje7cd1 ; tj130b4 <= ou3e68d ; end
-end
-
-
-assign ou15ae0 = (((psfec57 == ep2ca37) & bnbaf22 ) & ( ~ps575e4 ) & ((twbfb1 == ep2ca37) & yz8aebc ) ) ;
-
-
-assign riad700 = (((psfec57 == ep2ca37) & bnbaf22 ) & (((dz5fd8a == cobcb86) | (dz5fd8a == wwe5c31)) & ~ps575e4 ) & ((twbfb1 == ng86205) & ~yz8aebc ) ) ;
-
-
-assign hb6b803 = (((psfec57 == ui46f2e) & bnbaf22 ) & ((dz5fd8a == hd37970) & ps575e4 ) & ((twbfb1 == ep2ca37) & yz8aebc ) ) ;
-
-
-assign cm5c01f = (((psfec57 == ui46f2e) & bnbaf22 ) & ((dz5fd8a == hd37970) & ps575e4 ) & ((twbfb1 == hd37970) & yz8aebc ) ) ;
-
-
-assign goe00f9 = (((psfec57 == hd37970) & bnbaf22 ) & ((dz5fd8a == hd37970) & ps575e4 ) & ((twbfb1 == hd37970) & yz8aebc ) ) ;
-
-
-assign qi7c9 = (((psfec57 == hd37970) & bnbaf22 ) & ((dz5fd8a == hd37970) & ps575e4 ) & ((twbfb1 == ep2ca37) & yz8aebc ) ) ;
-
-
-assign bn3e48 = (((psfec57 == hd37970) & bnbaf22 ) & ((dz5fd8a == hd37970) & ps575e4 ) & ((twbfb1 == nt28de5) & yz8aebc ) ) ;
-
-always @(posedge ri2ab2d or negedge rst_n) begin if (!rst_n) begin ec985a6 <= 1'b0 ; zxc2d31 <= 1'b0 ; vx1698e <= 1'b0 ; anb4c77 <= 1'b0 ; coa63bd <= 1'b0 ; gq31de8 <= 1'b0 ; bn8ef41 <= 1'b0 ; end else begin ec985a6 <= rtf3469 ; zxc2d31 <= kf9a34f ; vx1698e <= osd1a7c ; anb4c77 <= qi8d3e0 ; coa63bd <= dm69f00 ; gq31de8 <= vv4f802 ; bn8ef41 <= rg7c016 ; end
-end
-
- assign ie1f246 = (nt16444 == 2'b01) ; assign blf9230 = (nt16444 == 2'b10) ;
-
-
-always @(posedge ri2ab2d or negedge rst_n) begin if (!rst_n) me77a0e <= ec5607 ; else if (xj40f5b) me77a0e <= ec5607 ; else if (!yz901d0) me77a0e <= nr40ac0 ; else me77a0e <= jr32de7 ;
-end
-
-
-always @(xl65bc or sucbfd8 or gq591 or ice00b2 or nrd7916 or nt16e5f or oh397dd or kqcbeec or jp5f760 or hofbb06 or jpdd832 or jpec196 or uv60cb7 or cmff607 or xwfb039 or ldd81cb or byc0e5f or oh72fb ) begin case (xl65bc) nr40ac0 : ribd070 = ec5607 ; ec5607 : if (cmff607 && sucbfd8) ribd070 = gq2b038 ; else ribd070 = ec5607 ; gq2b038 : if (ldd81cb || byc0e5f) ribd070 = rg581c0 ; else if (!gq591 && (nrd7916 || nt16e5f)) ribd070 = tj380dd ; else if ((!gq591 && (!nrd7916 && !nt16e5f) && !ldd81cb && !byc0e5f) || (gq591 && !ldd81cb && !byc0e5f)) ribd070 = zkc06ee ; else ribd070 = gq2b038 ; rg581c0 : if (!nrd7916 && !nt16e5f) ribd070 = xwc0e03 ; else ribd070 = tj380dd ; xwc0e03 : if (!nrd7916 && !nt16e5f) ribd070 = ir701b ; else ribd070 = tj380dd ; ir701b : if (cmff607 && sucbfd8) ribd070 = gq2b038 ; else if (!cmff607 || !sucbfd8) ribd070 = tj380dd ; else ribd070 = ir701b ; tj380dd : if (cmff607 && sucbfd8) ribd070 = gq2b038; else if (!cmff607 && sucbfd8) ribd070 = ec5607; else ribd070 = tj380dd; zkc06ee : if (!cmff607 && !gq591) ribd070 = tj380dd; else if (gq591 && oh72fb) if (!xwfb039) ribd070 = vx3772; else ribd070 = ri1bb97; else if ((gq591 && !oh72fb) || cmff607) ribd070 = gq2b038; else ribd070 = zkc06ee; vx3772 : if (cmff607 && sucbfd8) ribd070 = gq2b038; else ribd070 = vx3772; ri1bb97 : if ((oh397dd || kqcbeec) && sucbfd8) ribd070 = zxddcbb; else if (jp5f760 && sucbfd8) ribd070 = faee5de; else if (hofbb06) ribd070 = ic72ef2; else if (jpdd832) ribd070 = uide404; else if (!nrd7916 && !nt16e5f) ribd070 = mtbbc80; else ribd070 = ks97790; zxddcbb : if (!ldd81cb && !byc0e5f) ribd070 = zkc06ee; else ribd070 = rg581c0; faee5de : if (cmff607) ribd070 = gq2b038; else ribd070 = faee5de; ic72ef2 : if (jpdd832) ribd070 = ic72ef2; else if (jpec196 && sucbfd8) ribd070 = faee5de; else if (uv60cb7) ribd070 = shf2020; else ribd070 = sj90105; ks97790 : if ((oh397dd || kqcbeec) && sucbfd8) ribd070 = zxddcbb; else if (jp5f760 && sucbfd8) ribd070 = faee5de; else if (hofbb06) ribd070 = ic72ef2; else if (jpdd832) ribd070 = uide404; else if (!nrd7916 && !nt16e5f) ribd070 = mtbbc80; else ribd070 = ks97790; mtbbc80 : if ((oh397dd || kqcbeec) && sucbfd8) ribd070 = zxddcbb; else if (jp5f760 && sucbfd8) ribd070 = faee5de; else if (hofbb06) ribd070 = ic72ef2; else if (jpdd832) ribd070 = uide404; else if (!nrd7916 && !nt16e5f) ribd070 = mtbbc80; else ribd070 = ks97790; uide404 : if (jpdd832) ribd070 = ic72ef2; else if (jpec196 && sucbfd8) ribd070 = faee5de; else if (uv60cb7) ribd070 = shf2020; else ribd070 = sj90105; shf2020 : if (xwfb039) ribd070 = ri1bb97; else ribd070 = shf2020; sj90105 : if (xwfb039) ribd070 = ri1bb97; else if (cmff607 && sucbfd8) ribd070 = gq2b038; else if (!xwfb039 && !cmff607 && sucbfd8) if (jpdd832) ribd070 = ic72ef2; else if (jpec196 && sucbfd8) ribd070 = faee5de; else if (uv60cb7) ribd070 = shf2020; else ribd070 = sj90105; else ribd070 = sj90105; default : ribd070 = ec5607; endcase
-end
-
-
-
-always @(posedge ri2ab2d or negedge rst_n) begin if(!rst_n) cb8082d <= 1'b0; else if (xl65bc == vx3772 || xl65bc == zxddcbb || xl65bc == ks97790 || xl65bc == uide404 || xl65bc == ic72ef2 || (xl65bc == nr40ac0 && qi217f6)) cb8082d <= 1'b1; else if (xl65bc == xwc0e03 || xl65bc == ir701b || xl65bc == tj380dd || xl65bc == sj90105 || xl65bc == shf2020) cb8082d <= hb5085f; else cb8082d <= 1'b0;
-end
-
-
-always @(posedge ri2ab2d or negedge rst_n) begin if(!rst_n) pub2144 <= 1'b0; else if (xl65bc == ri1bb97) pub2144 <= 1'b1; else if (xl65bc == xwc0e03 || xl65bc == ir701b || xl65bc == tj380dd || xl65bc == vx3772 || (xl65bc == nr40ac0 && qi217f6 == 1'b1) || xl65bc == zxddcbb || xl65bc == ks97790 || xl65bc == mtbbc80 || xl65bc == uide404) pub2144 <= pub2144; else pub2144 <= 1'b0;
-end
-
-
-always @(posedge ri2ab2d or negedge rst_n) begin if(!rst_n) end6428 <= 8'b00000000; else if (xl65bc == ri1bb97) end6428 <= 8'b01010101; else if (xl65bc == shf2020 || xl65bc == ic72ef2) end6428 <= 8'b00001111; else if (xl65bc == sj90105) end6428 <= 8'b00011111; else if (xl65bc == vx3772) end6428 <= 8'b00001110; else if (xl65bc == mtbbc80) end6428 <= qvb15d7; else end6428 <= 8'b00000000;
-end
-
-
-always @(posedge ri2ab2d or negedge rst_n) begin if(!rst_n) ic6d48e <= 1'b0; else if (xl65bc == zkc06ee && gq591 && oh72fb) ic6d48e <= 1'b1; else if (xl65bc == faee5de || (xl65bc == nr40ac0 && qi217f6) || xl65bc == ec5607 || xl65bc == gq2b038 || xl65bc == rg581c0 || xl65bc == zkc06ee) ic6d48e <= 1'b0; else ic6d48e <= qi217f6;
-end always @(posedge ri2ab2d or negedge rst_n) begin if(!rst_n) begin uk97c52 <= 16'h0000; end else if(xl65bc == xwc0e03) begin uk97c52[7:0] <= qvb15d7; uk97c52[15:8] <= uk97c52[15:8]; end else if(xl65bc == ir701b) begin uk97c52[ 7:0] <= uk97c52[7:0]; uk97c52[15:8] <= qvb15d7; end else uk97c52 <= uk97c52; end
- always @(posedge ri2ab2d or negedge rst_n) begin if(!rst_n) cofeb2 <= 1'b0; else if(xl65bc == ir701b) cofeb2 <= 1'b1; else cofeb2 <= 1'b0; end always @(posedge ri2ab2d or negedge rst_n) begin if(!rst_n) wj7f590 <= 1'b0; else if(xl65bc == zkc06ee) wj7f590 <= 1'b1; else wj7f590 <= 1'b0; end always @(posedge ri2ab2d or negedge rst_n) begin if(!rst_n) ayfac85 <= 1'b0; else if((xl65bc == tj380dd && ice00b2) || (xl65bc == nr40ac0 && !gq591)) ayfac85 <= 1'b1; else ayfac85 <= 1'b0; end
-
-
-
-
-
-assign vk416d = qt44cf9 ? (hb5085f & pub2144) : hb5085f;
-assign ux90a23 = (yz33e6c & !wjf7c8d) ? ph842fe : hb5085f;
-
-
-
-
-always @(xl65bc)
-begin case (xl65bc) nr40ac0 : psd01ce = "LNK_FAIL"; ec5607 : psd01ce = "WAIT_K"; gq2b038 : psd01ce = "RX_K"; rg581c0 : psd01ce = "RX_CB"; xwc0e03 : psd01ce = "RX_CC"; ir701b : psd01ce = "RX_CD"; tj380dd : psd01ce = "RX_INV"; zkc06ee : psd01ce = "IDL_D"; vx3772 : psd01ce = "FLS_CARR"; ri1bb97 : psd01ce = "SOP"; zxddcbb : psd01ce = "ERLY_END"; faee5de : psd01ce = "TRI_RRI"; ic72ef2 : psd01ce = "TRR_EXT"; ks97790 : psd01ce = "RXD_ERR"; mtbbc80 : psd01ce = "RX_D"; uide404 : psd01ce = "EEND_EXT"; shf2020 : psd01ce = "PKT_BRRS"; sj90105 : psd01ce = "EXT_ERR"; default : psd01ce = " ERROR "; endcase
-end
-
-
-always@* begin qg49292<=jea8e7a[0];tuf124a<=jea8e7a[1];rv22600<=jea8e7a[2];qgce76d<=jea8e7a[3];ho73b69<={rx_data>>1,jea8e7a[4]};co9db4a<=jea8e7a[5];eneda50<=jea8e7a[6];yz901d0<=jea8e7a[7];zk69421<=jea8e7a[8];th4a10b<={vif148d>>1,jea8e7a[9]};hb5085f<=jea8e7a[10];ph842fe<=jea8e7a[11];qi217f6<=jea8e7a[12];twbfb1<={xj718b7>>1,jea8e7a[13]};dz5fd8a<={fc8c5bf>>1,jea8e7a[14]};psfec57<={su62dfa>>1,jea8e7a[15]};vvf62ba<={lf16fd1>>1,jea8e7a[16]};qvb15d7<={xyb7e8f>>1,jea8e7a[17]};yz8aebc<=jea8e7a[18];ps575e4<=jea8e7a[19];bnbaf22<=jea8e7a[20];nrd7916<=jea8e7a[21];mgbc8b7<=jea8e7a[22];zke45b9<=jea8e7a[23];ph22dcb<=jea8e7a[24];nt16e5f<=jea8e7a[25];ngb72ff<=jea8e7a[26];cob97fb<=jea8e7a[27];sucbfd8<=jea8e7a[28];vv5fec0<=jea8e7a[29];cmff607<=jea8e7a[30];xwfb039<=jea8e7a[31];ldd81cb<=jea8e7a[32];byc0e5f<=jea8e7a[33];oh72fb<=jea8e7a[34];oh397dd<=jea8e7a[35];kqcbeec<=jea8e7a[36];jp5f760<=jea8e7a[37];hofbb06<=jea8e7a[38];jpdd832<=jea8e7a[39];jpec196<=jea8e7a[40];uv60cb7<=jea8e7a[41];xl65bc<={me77a0e>>1,jea8e7a[42]};jr32de7<={ribd070>>1,jea8e7a[43]};tw96f3e<=jea8e7a[44];jeb79f3<=jea8e7a[45];swbcf9a<=jea8e7a[46];wje7cd1<=jea8e7a[47];ou3e68d<=jea8e7a[48];rtf3469<=jea8e7a[49];kf9a34f<=jea8e7a[50];osd1a7c<=jea8e7a[51];qi8d3e0<=jea8e7a[52];dm69f00<=jea8e7a[53];vv4f802<=jea8e7a[54];rg7c016<=jea8e7a[55];ice00b2<=jea8e7a[56];gq591<=jea8e7a[57];yz2c88<={mrc9186>>1,jea8e7a[58]};nt16444<={xw48c34>>1,jea8e7a[59]};twa81eb<=jea8e7a[60];xj40f5b<=jea8e7a[61];ec8899f<=jea8e7a[62];qt44cf9<=jea8e7a[63];ep267cd<=jea8e7a[64];yz33e6c<=jea8e7a[65];uv5ef91<=jea8e7a[66];wjf7c8d<=jea8e7a[67];pfcd927<={psd01ce>>1,jea8e7a[68]};end
-always@* begin ls351cf[2047]<=sgmii_mode;ls351cf[2046]<=gbe_mode;ls351cf[2044]<=jp6bc27;ls351cf[2040]<=rx_data[0];ls351cf[2032]<=rx_kcntl;ls351cf[2016]<=db84fe1;ls351cf[1985]<=bld2597;ls351cf[1927]<=hq868cb;ls351cf[1922]<=rx_even;ls351cf[1867]<=eafa3d7;ls351cf[1807]<=ec3465a;ls351cf[1804]<=wj7056b;ls351cf[1797]<=vif148d[0];ls351cf[1761]<=kde8382;ls351cf[1686]<=med1eb9;ls351cf[1623]<=qi7c9;ls351cf[1567]<=eca32d0;ls351cf[1561]<=sw82b5c;ls351cf[1558]<=by661fc;ls351cf[1547]<=cb8082d;ls351cf[1542]<=zxc2d31;ls351cf[1505]<=ay4351e;ls351cf[1490]<=xyb7e8f[0];ls351cf[1475]<=cz41c15;ls351cf[1413]<=dz45987;ls351cf[1409]<=tj130b4;ls351cf[1400]<=mrc9186[0];ls351cf[1324]<=cb8f5c8;ls351cf[1200]<=fnd722c;ls351cf[1199]<=bn3e48;ls351cf[1086]<=zz19680;ls351cf[1074]<=ou15ae0;ls351cf[1068]<=zm30fe2;ls351cf[1047]<=vk416d;ls351cf[1037]<=vx1698e;ls351cf[1023]<=mr_main_reset;ls351cf[963]<=ec1a8f1;ls351cf[933]<=dbbf47a;ls351cf[902]<=vke0ad;ls351cf[880]<=ribd070[0];ls351cf[811]<=goe00f9;ls351cf[779]<=ep2cc3f;ls351cf[771]<=ec985a6;ls351cf[752]<=xw48c34[0];ls351cf[745]<=lf16fd1[0];ls351cf[706]<=zxc8b30;ls351cf[704]<=ale2616;ls351cf[700]<=blf9230;ls351cf[600]<=al7ae45;ls351cf[503]<=psd01ce[1];ls351cf[440]<=me77a0e[0];ls351cf[405]<=cm5c01f;ls351cf[372]<=su62dfa[0];ls351cf[353]<=wyb9166;ls351cf[352]<=thfc4c2;ls351cf[350]<=ie1f246;ls351cf[251]<=cm6de53;ls351cf[220]<=bn8ef41;ls351cf[202]<=hb6b803;ls351cf[186]<=fc8c5bf[0];ls351cf[176]<=fc3f898;ls351cf[125]<=jc4dbca;ls351cf[110]<=gq31de8;ls351cf[101]<=riad700;ls351cf[93]<=xj718b7[0];ls351cf[88]<=uk87f13;ls351cf[55]<=coa63bd;ls351cf[46]<=ic6d48e;ls351cf[27]<=anb4c77;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module gb51bec (
- ri2ab2d ,
- rst_n ,
- mr_main_reset ,
-
- signal_detect ,
- rx_data ,
- rx_kcntl ,
- db84fe1 ,
-
- bld2597 ,
- rx_even
- );
-input ri2ab2d ;
-input rst_n ;
-input mr_main_reset ;
-input signal_detect ;
-input [7:0] rx_data ;
-input rx_kcntl ;
-input db84fe1 ;
-output bld2597 ;
-output rx_even ;
-localparam aa3bad7 = 4'b0000 , fndd6b8 = 4'b0001 , faeb5c7 = 4'b0010 , ld5ae3a = 4'b0011 , dzd71d7 = 4'b0100 , hqb8ebe = 4'b0101 , nrc75f3 = 4'b0110 , fc3af9f = 4'b0111 , thd7cfa = 4'b1000 , kfbe7d7 = 4'b1001 , ldf3ebd = 4'b1010 , kf9f5ee = 4'b1011 , osfaf74 = 4'b1100 ;
-reg bld2597 ;
-reg rx_even ;
-reg [3:0] hoee83b ;
-reg [3:0] fn741db ;
-reg [1:0] pha0ede ;
-reg ir76f6 ;
-reg qi3b7b5 ;
-reg ay4351e ;
-reg ec1a8f1 ;
-reg nrf6a49 ;
-reg bnb524e ;
-reg gqa9276 ;
-wire ui493b1 ;
-reg ic49d88 ;
-reg wj4ec41 ;
-reg zk7620c ;
-reg [(20*8):1] wlb1063;
-reg qg49292;
-reg uv418e0;
-reg [7 : 0] ho73b69;
-reg co9db4a;
-reg eneda50;
-reg [3 : 0] qge0b9f;
-reg [3 : 0] ou5cf8;
-reg [1 : 0] mg2e7c1;
-reg ne73e08;
-reg an9f042;
-reg twa81eb;
-reg xj40f5b;
-reg ep8520;
-reg lq42904;
-reg ls14822;
-reg uxa4112;
-reg zm20895;
-reg je44aa;
-reg xl22552;
-reg [(20 * 8) : 1] ux12a96;
-reg [2047:0] ls351cf;
-wire [19:0] jea8e7a;
-
-localparam ps473d2 = 20,wl39e93 = 32'hfdffe0cb;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-assign ui493b1 = ( co9db4a & (ho73b69[5:0] == 6'b111100) & ((ho73b69[7:6] == 2'b00) | (ho73b69[7:6] == 2'b10) | (ho73b69[7:6] == 2'b11)));
-
-
-
-
-
-
-
-
-always @(posedge ri2ab2d or negedge rst_n)
-begin if(!rst_n) begin ay4351e <= 1'b1; ec1a8f1 <= 1'b1; end else begin ay4351e <= qg49292; ec1a8f1 <= twa81eb; end
-end
-always @(posedge ri2ab2d or negedge rst_n) begin if (!rst_n) begin zk7620c <= 1'b0 ; ic49d88 <= 1'b0 ; wj4ec41 <= 1'b0 ; end else begin zk7620c <= uxa4112 & ~eneda50; ic49d88 <= (eneda50 | (uxa4112 & ls14822)); wj4ec41 <= ~co9db4a & ~zm20895 ; end
-end
-
-always @(posedge ri2ab2d or negedge rst_n) begin if (!rst_n) begin ir76f6 <= 1'b0 ; qi3b7b5 <= 1'b0 ; nrf6a49 <= 1'b0 ; bnb524e <= 1'b0 ; gqa9276 <= 1'b0 ; end else begin ir76f6 <= uv418e0 ; qi3b7b5 <= ne73e08 ; nrf6a49 <= an9f042 ; bnb524e <= (an9f042 ^ ep8520) ; gqa9276 <= rx_even ; end
-end
-
-always @(posedge ri2ab2d or negedge rst_n) begin if(!rst_n) hoee83b <= aa3bad7 ; else if (xj40f5b || lq42904) hoee83b <= aa3bad7 ; else hoee83b <= ou5cf8 ;
-end
-
-
-always @(qge0b9f or xl22552 or je44aa or mg2e7c1 or rx_even or zm20895) begin case (qge0b9f) aa3bad7 : if (xl22552 && ep8520) fn741db = fndd6b8 ; else fn741db = aa3bad7 ; fndd6b8 : if (je44aa) fn741db = faeb5c7 ; else fn741db = aa3bad7 ; faeb5c7 : if (!rx_even && xl22552) fn741db = ld5ae3a ; else if (zm20895) fn741db = aa3bad7 ; else fn741db = faeb5c7 ; ld5ae3a : if (je44aa) fn741db = dzd71d7 ; else fn741db = aa3bad7 ; dzd71d7 : if (!rx_even && xl22552) fn741db = hqb8ebe ; else if (zm20895) fn741db = aa3bad7 ; else fn741db = dzd71d7 ; hqb8ebe: if (je44aa) fn741db = nrc75f3; else fn741db = aa3bad7; nrc75f3: if (zm20895) fn741db = fc3af9f; else fn741db = nrc75f3; fc3af9f: if (zm20895) fn741db = kfbe7d7; else fn741db = thd7cfa; thd7cfa: if (zm20895) fn741db = kfbe7d7; else if (mg2e7c1 == 2'b11) fn741db = nrc75f3; else fn741db = thd7cfa; kfbe7d7: if (zm20895) fn741db = kf9f5ee; else fn741db = ldf3ebd; ldf3ebd: if (zm20895) fn741db = kf9f5ee; else if (mg2e7c1 == 2'b11) fn741db = fc3af9f; else fn741db = ldf3ebd; kf9f5ee: if (zm20895) fn741db = aa3bad7; else fn741db = osfaf74; osfaf74: if (zm20895) fn741db = aa3bad7; else if (mg2e7c1 == 2'b11) fn741db = kfbe7d7; else fn741db = osfaf74; default: fn741db = aa3bad7; endcase
-end
-
-always @(posedge ri2ab2d or negedge rst_n) begin if (!rst_n) pha0ede <= 2'b00; else if ((qge0b9f == thd7cfa) || (qge0b9f == ldf3ebd) || (qge0b9f == osfaf74)) pha0ede <= mg2e7c1 + 1'b1; else pha0ede <= 2'b00;
-end
-
-
-always @(posedge ri2ab2d or negedge rst_n) begin if (!rst_n) bld2597 <= 1'b0; else if (qge0b9f == aa3bad7) bld2597 <= 1'b0; else if (qge0b9f == nrc75f3) bld2597 <= 1'b1; else bld2597 <= bld2597 ;
-end
-always @(qge0b9f or ls14822) begin case (qge0b9f) fndd6b8, ld5ae3a, hqb8ebe : rx_even = 1'b1 ; aa3bad7, faeb5c7, dzd71d7, nrc75f3, fc3af9f, kfbe7d7, kf9f5ee, thd7cfa, ldf3ebd, osfaf74 : rx_even = ~ls14822 ; default : rx_even = 1'b0; endcase
-end
-
-
-
-
-
-always @(qge0b9f)
-begin case (qge0b9f) aa3bad7 : wlb1063 = "LOS"; fndd6b8 : wlb1063 = "COM_DET1"; faeb5c7 : wlb1063 = "AQR_SYNC1"; ld5ae3a : wlb1063 = "COM_DET2"; dzd71d7 : wlb1063 = "AQR_SYNC2"; hqb8ebe : wlb1063 = "COM_DET3"; nrc75f3 : wlb1063 = "SYNC_AQRD1"; fc3af9f : wlb1063 = "SYNC_AQRD2"; thd7cfa : wlb1063 = "SYNC_AQRD2A"; kfbe7d7 : wlb1063 = "SYNC_AQRD3"; ldf3ebd : wlb1063 = "SYNC_AQRD3A"; kf9f5ee : wlb1063 = "SYNC_AQRD4"; osfaf74 : wlb1063 = "SYNC_AQRD4A"; default : wlb1063 = " ERROR "; endcase
-end
-
-
-always@* begin qg49292<=jea8e7a[0];uv418e0<=jea8e7a[1];ho73b69<={rx_data>>1,jea8e7a[2]};co9db4a<=jea8e7a[3];eneda50<=jea8e7a[4];qge0b9f<={hoee83b>>1,jea8e7a[5]};ou5cf8<={fn741db>>1,jea8e7a[6]};mg2e7c1<={pha0ede>>1,jea8e7a[7]};ne73e08<=jea8e7a[8];an9f042<=jea8e7a[9];twa81eb<=jea8e7a[10];xj40f5b<=jea8e7a[11];ep8520<=jea8e7a[12];lq42904<=jea8e7a[13];ls14822<=jea8e7a[14];uxa4112<=jea8e7a[15];zm20895<=jea8e7a[16];je44aa<=jea8e7a[17];xl22552<=jea8e7a[18];ux12a96<={wlb1063>>1,jea8e7a[19]};end
-always@* begin ls351cf[2047]<=signal_detect;ls351cf[2046]<=rx_data[0];ls351cf[2044]<=rx_kcntl;ls351cf[2040]<=db84fe1;ls351cf[2033]<=hoee83b[0];ls351cf[2018]<=fn741db[0];ls351cf[1988]<=pha0ede[0];ls351cf[1929]<=ir76f6;ls351cf[1811]<=qi3b7b5;ls351cf[1789]<=zk7620c;ls351cf[1574]<=ay4351e;ls351cf[1530]<=wlb1063[1];ls351cf[1247]<=ui493b1;ls351cf[1101]<=ec1a8f1;ls351cf[1023]<=mr_main_reset;ls351cf[894]<=wj4ec41;ls351cf[623]<=gqa9276;ls351cf[447]<=ic49d88;ls351cf[311]<=bnb524e;ls351cf[155]<=nrf6a49;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module ba1bf62 (
- rst_n,
- mr_main_reset,
- an_link_ok,
- ic626ef,
-
- gbe_mode,
- operational_rate,
-
- lddde37,
- wwef1be,
- os78df0,
- qtc6f81,
-
- bn37c0c,
- irbe066,
- suf0335,
- ph819a8,
- xlcd47,
- ctc_drop_flag,
- ctc_add_flag
-);
-input rst_n;
-input mr_main_reset;
-input an_link_ok;
-input ic626ef;
-input gbe_mode;
-input [1:0] operational_rate;
-input lddde37;
-input [7:0] wwef1be;
-input os78df0;
-input qtc6f81;
-input bn37c0c;
-output [7:0] irbe066;
-output suf0335;
-output ph819a8;
-output xlcd47;
-output ctc_drop_flag;
-output ctc_add_flag;
-parameter DYNAMIC_LT_10MBPS = 340;
-parameter DYNAMIC_HT_10MBPS = 680;
-parameter DYNAMIC_LT_100MBPS = 34;
-parameter DYNAMIC_HT_100MBPS = 68;
-parameter DYNAMIC_LT_1000MBPS = 16;
-parameter DYNAMIC_HT_1000MBPS = 32;
-localparam jr9b431 = 2'd0, hoda18e = 2'd1, rgd0c72 = 2'd2, pu86392 = 2'd3;
-reg[1:0] uk31c93;
-localparam jr8e499 = 3'd0, cm724cf = 3'd1, sw92679 = 3'd2, xy933c8 = 3'd3, ls99e42 = 3'd4, xwcf212 = 3'd5;
-reg [2:0] lq79093;
-reg [7:0] pfc849a;
-reg vi424d6;
-reg sj126b3 ;
-reg [7:0] xy9359c;
-reg mt9ace2;
-reg kdd6715 ;
-reg [7:0] ksb38ac;
-reg ba9c560;
-reg ale2b03 ;
-reg uk1581d;
-reg mgac0e8;
-reg sh60741;
-reg lf3a0d;
-reg mt1d06e;
-reg kde8375;
-reg cz41bad;
-reg jp40b00;
-reg [7:0] irbe066;
-reg suf0335;
-reg ph819a8;
-wire [7:0] ie3102c;
-wire ay6df50;
-wire en44c40;
-wire su7d405;
-wire qgea028;
-wire vv50140;
-reg an80a07;
-wire ks88160;
-reg jr281e8;
-reg vv40f47;
-reg sj7a3f;
-reg rv3d1fc;
-reg kde8fe6;
-reg xw47f34;
-reg do3f9a2;
-wire xlcd47;
-wire [7:0] hbe6897;
-reg [1:0] cmcba31;
-reg [1:0] vi5d188;
-reg [1:0] mt12fc2;
-reg [1:0] ec97e15;
-reg vxbf0a9;
-reg uvf854f;
-reg jpc2a7c;
-reg uk153e6;
-reg ec88708;
-reg vv4f988;
-reg rg7cc46;
-reg pfe6233;
-reg gq3119e;
-reg uk88cf0;
-reg me46781;
-reg [9:0] yz33c09;
-reg [9:0] lf9e04c;
-reg jc4dbca;
-reg cm6de53;
-reg [1:0] ph9986;
-reg [1:0] yk4cc37;
-reg tu661b9;
-reg ng30dca;
-reg do86e53;
-reg bn3729a;
-reg ksb94d7 ;
-reg faca6b8 ;
-reg ww535c3 ;
-reg ep9ae18 ;
-reg zxd70c5;
-reg bab862e;
-reg ctc_drop_flag;
-reg yz18b95;
-reg xwc5cac;
-reg ctc_add_flag;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-`endif\r
-reg [(22*8):1] qg72b18;
-reg [(22*8):1] yz958c0;
-reg qg49292;
-reg ne63021;
-reg sj1810a;
-reg rv22600;
-reg [1 : 0] tw42ab;
-reg [7 : 0] wy2155a;
-reg ouaad1;
-reg pf55688;
-reg [1 : 0] epab447;
-reg [2 : 0] dz5a23c;
-reg [7 : 0] kqd11e6;
-reg ou88f31;
-reg rg47989;
-reg [7 : 0] ir3cc4a;
-reg vve6255;
-reg co312ae;
-reg [7 : 0] pu89570;
-reg xj4ab82;
-reg jp55c16;
-reg epae0b6;
-reg cz705b4;
-reg ou82da4;
-reg lf16d20;
-reg wyb6907;
-reg uxb4838;
-reg ira41c5;
-reg th40935;
-reg [7 : 0] bn3d024;
-reg bn38b55;
-reg qt60f40;
-reg xl2d57b;
-reg cz6abdf;
-reg rt55efd;
-reg rvaf7ee;
-reg mre8126;
-reg bydfbb6;
-reg alfddb3;
-reg hoeed9d;
-reg dm76ceb;
-reg wyb675a;
-reg wyb3ad1;
-reg sw9d688;
-reg [7 : 0] faeb441;
-reg [1 : 0] epb1475;
-reg [1 : 0] gd8a3ac;
-reg [1 : 0] gq882b1;
-reg [1 : 0] cz41588;
-reg qiac44;
-reg cm56220;
-reg anb1100;
-reg ym88804;
-reg ecacb35;
-reg fc2010c;
-reg ie863;
-reg ri4319;
-reg gq218ca;
-reg phc650;
-reg vi63286;
-reg [9 : 0] fp19432;
-reg [9 : 0] faca197;
-reg uv5ef91;
-reg wjf7c8d;
-reg [1 : 0] ph32ef3;
-reg [1 : 0] ou9779e;
-reg sjbbcf0;
-reg qgde784;
-reg nrf3c20;
-reg bn9e106;
-reg uif0836;
-reg jr841b1;
-reg vk20d8e;
-reg fp6c72;
-reg qv36396;
-reg cbb1cb5;
-reg vx8e5ad;
-reg ui72d6f;
-reg [(22 * 8) : 1] do96b78;
-reg [(22 * 8) : 1] ntb5bc3;
-reg [2047:0] ls351cf;
-wire [77:0] jea8e7a;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-localparam ps473d2 = 78,wl39e93 = 32'hfdffd48b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin ww535c3 <= 1'b1; ep9ae18 <= 1'b1; end else begin ww535c3 <= qg49292; ep9ae18 <= vk20d8e; end
-end
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin jc4dbca <= 1'b0; cm6de53 <= 1'b0; end else begin jc4dbca <= rv22600; cm6de53 <= uv5ef91; end
-end
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin ph9986 <= 2'b10; yk4cc37 <= 2'b10; end else begin ph9986 <= tw42ab; yk4cc37 <= ph32ef3; end
-end
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin tu661b9 <= 1'b0; ng30dca <= 1'b0; do86e53 <= 1'b1; bn3729a <= 1'b1; end else begin tu661b9 <= ne63021; ng30dca <= sjbbcf0; do86e53 <= sj1810a; bn3729a <= nrf3c20; end
-end
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin cmcba31 <= 2'b10; vi5d188 <= 2'b10; vxbf0a9 <= 1'b1; uvf854f <= 1'b1; jpc2a7c <= 1'b1; uk153e6 <= 1'b1; ec88708 <= 1'b1; end else begin if (wjf7c8d) begin cmcba31 <= 2'b10; end else if (qgde784 || (!bn9e106)) begin cmcba31 <= ou9779e; end else begin cmcba31 <= 2'b10; end vi5d188 <= epb1475; vxbf0a9 <= epb1475 != gd8a3ac; uvf854f <= qiac44; jpc2a7c <= cm56220; uk153e6 <= anb1100; ec88708 <= qiac44 | cm56220 | anb1100 | ym88804; end
-end
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ksb94d7 <= 1'b1; faca6b8 <= 1'b1; end else begin ksb94d7 <= qg49292; faca6b8 <= uif0836; end
-end
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin mt12fc2 <= 2'b10; ec97e15 <= 2'b10; end else begin mt12fc2 <= epb1475; ec97e15 <= gq882b1; end
-end
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin vv4f988 <= 1'b1; rg7cc46 <= 1'b1; pfe6233 <= 1'b1; end else begin if (jr841b1) begin vv4f988 <= 1'b1; rg7cc46 <= 1'b1; pfe6233 <= 1'b1; end else begin vv4f988 <= ecacb35; rg7cc46 <= fc2010c; pfe6233 <= ie863; end
-end
-end
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin gq3119e <= 1'b1; uk88cf0 <= 1'b1; me46781 <= 1'b1; end else begin if (fp6c72) begin gq3119e <= 1'b1; uk88cf0 <= 1'b1; me46781 <= 1'b1; end else begin gq3119e <= ecacb35; uk88cf0 <= gq218ca; me46781 <= phc650; end
-end
-end
-
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin yz33c09 <= 10'd16; end else begin case (gd8a3ac) 2'd0: begin yz33c09 <= DYNAMIC_LT_10MBPS; end 2'd1: begin yz33c09 <= DYNAMIC_LT_100MBPS; end 2'd2: begin yz33c09 <= DYNAMIC_LT_1000MBPS; end 2'd3: begin yz33c09 <= DYNAMIC_LT_1000MBPS; end default: begin yz33c09 <= fp19432; end endcase end
-end
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin lf9e04c <= 10'd32; end else begin case (cz41588) 2'd0: begin lf9e04c <= DYNAMIC_HT_10MBPS; end 2'd1: begin lf9e04c <= DYNAMIC_HT_100MBPS; end 2'd2: begin lf9e04c <= DYNAMIC_HT_1000MBPS; end 2'd3: begin lf9e04c <= DYNAMIC_HT_1000MBPS; end default: begin lf9e04c <= faca197; end endcase end
-end
-
-
-
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin pfc849a <= 8'd0; vi424d6 <= 1'b0; sj126b3 <= 1'b0; xy9359c <= 8'd0; mt9ace2 <= 1'b0; kdd6715 <= 1'b0; ksb38ac <= 8'd0; ba9c560 <= 1'b0; ale2b03 <= 1'b0; end else begin pfc849a <= wy2155a; vi424d6 <= ouaad1; sj126b3 <= pf55688; xy9359c <= kqd11e6; mt9ace2 <= ou88f31; kdd6715 <= rg47989; ksb38ac <= ir3cc4a; ba9c560 <= vve6255; ale2b03 <= co312ae; end
-end
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin uk1581d <= 1'b0; mgac0e8 <= 1'b0; sh60741 <= 1'b0; lf3a0d <= 1'b0; mt1d06e <= 1'b0; kde8375 <= 1'b0; end else begin if ((ou88f31 == 1'b1) && (kqd11e6 == 8'hBC)) begin uk1581d <= 1'b1; end else begin uk1581d <= 1'b0; end
- if ((ouaad1 == 1'b0) && (wy2155a == 8'hC5)) begin mgac0e8 <= 1'b1; end else begin mgac0e8 <= 1'b0; end if ((ouaad1 == 1'b0) && (wy2155a == 8'h50)) begin sh60741 <= 1'b1; end else begin sh60741 <= 1'b0; end if ((ouaad1 == 1'b0) && (wy2155a == 8'h42)) begin lf3a0d <= 1'b1; end else begin lf3a0d <= 1'b0; end if ((ouaad1 == 1'b0) && (wy2155a == 8'hB5)) begin mt1d06e <= 1'b1; end else begin mt1d06e <= 1'b0; end if (epae0b6 && (lf16d20 || wyb6907)) begin kde8375 <= 1'b1; end else begin kde8375 <= 1'b0; end end
-end
-
-
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin uk31c93 <= jr9b431; cz41bad <= 1'b0; zxd70c5 <= 1'b0; end else begin if (ri4319) begin uk31c93 <= jr9b431; cz41bad <= 1'b0; zxd70c5 <= 1'b0; end else begin zxd70c5 <= 1'b0; case (epab447) jr9b431: begin if (cz6abdf) begin if (epae0b6 && (ou82da4 || lf16d20 || wyb6907)) begin cz41bad <= 1'b0; uk31c93 <= hoda18e; zxd70c5 <= 1'b1; end end else begin cz41bad <= 1'b1; uk31c93 <= jr9b431; end end hoda18e: begin cz41bad <= 1'b0; zxd70c5 <= 1'b1; if (uxb4838) begin uk31c93 <= rgd0c72; end else begin uk31c93 <= jr9b431; end end rgd0c72: begin cz41bad <= 1'b0; zxd70c5 <= 1'b1; uk31c93 <= pu86392; end pu86392: begin cz41bad <= 1'b0; zxd70c5 <= 1'b1; uk31c93 <= jr9b431; end
- default: begin uk31c93 <= jr9b431; end endcase end end
-end
-
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin bab862e <= 1'b0; ctc_drop_flag <= 1'b0; end else begin bab862e <= qv36396; ctc_drop_flag <= qv36396 | cbb1cb5; end
-end
-
-
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin lq79093 <= jr8e499; irbe066 <= 8'hBC; suf0335 <= 1'b1; ph819a8 <= 1'b0; jp40b00 <= 1'b0; yz18b95 <= 1'b1; end else begin if (vi63286) begin lq79093 <= jr8e499; irbe066 <= 8'hBC; suf0335 <= 1'b1; ph819a8 <= 1'b0; jp40b00 <= 1'b0; yz18b95 <= 1'b1; end else begin irbe066 <= bn3d024; suf0335 <= bn38b55; ph819a8 <= qt60f40; jp40b00 <= 1'b0; yz18b95 <= 1'b0; case (dz5a23c) jr8e499: begin suf0335 <= 1'b1; ph819a8 <= 1'b0; irbe066 <= 8'hBC; yz18b95 <= 1'b1; if (xl2d57b) begin lq79093 <= xwcf212; end else begin jp40b00 <= 1'b1; lq79093 <= cm724cf; end end cm724cf: begin suf0335 <= 1'b0; ph819a8 <= 1'b0; irbe066 <= 8'h50; yz18b95 <= 1'b1; jp40b00 <= 1'b1; lq79093 <= ls99e42; end sw92679: begin suf0335 <= 1'b1; ph819a8 <= 1'b0; irbe066 <= 8'hBC; yz18b95 <= 1'b1; if (xl2d57b) begin lq79093 <= xwcf212; end else begin jp40b00 <= 1'b1; lq79093 <= xy933c8; end end
- xy933c8: begin jp40b00 <= 1'b1; lq79093 <= ls99e42; end
-
- ls99e42: begin if (xl2d57b && bn38b55 && (bn3d024 == 8'hBC)) begin suf0335 <= 1'b1; ph819a8 <= 1'b0; irbe066 <= 8'hBC; yz18b95 <= 1'b1; lq79093 <= xwcf212; end else begin jp40b00 <= 1'b1; lq79093 <= ls99e42; end end xwcf212: begin suf0335 <= 1'b0; ph819a8 <= 1'b0; irbe066 <= 8'h50; yz18b95 <= 1'b1; lq79093 <= sw92679; end default: begin lq79093 <= jr8e499; end endcase end end
-end
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin xwc5cac <= 1'b1; ctc_add_flag <= 1'b1; end else begin xwc5cac <= vx8e5ad; ctc_add_flag <= vx8e5ad | ui72d6f; end
-end
-
-
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin vv40f47 <= 1'd0; sj7a3f <= 1'd0; rv3d1fc <= 1'd0; an80a07 <= 1'd0; end else begin if (ri4319) begin vv40f47 <= 1'd0; sj7a3f <= 1'd0; rv3d1fc <= 1'd0; an80a07 <= 1'd0; end else begin an80a07 <= rt55efd; if (rvaf7ee && ira41c5) begin vv40f47 <= 1'd1; end else begin vv40f47 <= 1'd0; end sj7a3f <= alfddb3; rv3d1fc <= alfddb3 | hoeed9d; end end
-end
-
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin kde8fe6 <= 1'd0; xw47f34 <= 1'd0; do3f9a2 <= 1'd0; jr281e8 <= 1'd1; end else begin if (vi63286) begin kde8fe6 <= 1'd0; xw47f34 <= 1'd0; do3f9a2 <= 1'd0; jr281e8 <= 1'd1; end else begin jr281e8 <= mre8126; if (bydfbb6 && th40935) begin kde8fe6 <= 1'd1; end else begin kde8fe6 <= 1'd0; end xw47f34 <= wyb675a; do3f9a2 <= wyb675a | wyb3ad1; end end
-end
-
-
-assign xlcd47 = dm76ceb | sw9d688;
-
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
- tjb57bb ohab5fd ( .icf5b61(ri4319), .uv5eef5(lddde37), .yzbbd6d(ira41c5), .xw6c250(faca197), .wlabdde({8'd0, jp55c16, xj4ab82, pu89570}),
- .puadb09(vi63286), .wjf77ad(bn37c0c), .medeb6c(th40935), .kq6d84a(fp19432), .dz61283({hbe6897, en44c40, ay6df50, ie3102c}),
- .vx941f(ks88160), .th4a0fe(vv50140), .hb507f7(su7d405), .ri83fbf(qgea028) );
-
-`endif\r
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- zm209c0 ohab5fd ( .icf5b61(ri4319), .uv5eef5(lddde37), .yzbbd6d(ira41c5), .xw6c250(faca197), .wlabdde({8'd0, jp55c16, xj4ab82, pu89570}),
- .puadb09(vi63286), .wjf77ad(bn37c0c), .medeb6c(th40935), .kq6d84a(fp19432), .dz61283({hbe6897, en44c40, ay6df50, ie3102c}),
- .vx941f(ks88160), .th4a0fe(vv50140), .hb507f7(su7d405), .ri83fbf(qgea028) );
-
-`endif\r
-
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- jr8178b ohab5fd ( .icf5b61(ri4319), .uv5eef5(lddde37), .yzbbd6d(ira41c5), .xw6c250(faca197), .wlabdde({8'd0, jp55c16, xj4ab82, pu89570}),
- .puadb09(vi63286), .wjf77ad(bn37c0c), .medeb6c(th40935), .kq6d84a(fp19432), .dz61283({hbe6897, en44c40, ay6df50, ie3102c}),
- .vx941f(ks88160), .th4a0fe(vv50140), .hb507f7(su7d405), .ri83fbf(qgea028) );
-
-`endif\r
-
-
-
-
-
-
-always @(epab447) begin case (epab447) jr9b431 : qg72b18 = "SEEK_IDLE_START"; hoda18e : qg72b18 = "DISABLE_WRITES"; rgd0c72 : qg72b18 = "DISABLE_W3"; pu86392 : qg72b18 = "DISABLE_W4"; default : qg72b18 = "***ERROR***"; endcase
-end
-
-always @(dz5a23c) begin case (dz5a23c) jr8e499 : yz958c0 = "SEEK_BEGIN_THRESH"; cm724cf : yz958c0 = "DELAY_BEGIN"; sw92679 : yz958c0 = "SEEK_START_THRESH"; xy933c8 : yz958c0 = "DELAY"; ls99e42 : yz958c0 = "SEEK_STOP_THRESH"; xwcf212 : yz958c0 = "INSERT_IDLE"; default : yz958c0 = "***ERROR***"; endcase
-end
-
-
-
-
-always@* begin qg49292<=jea8e7a[0];ne63021<=jea8e7a[1];sj1810a<=jea8e7a[2];rv22600<=jea8e7a[3];tw42ab<={operational_rate>>1,jea8e7a[4]};wy2155a<={wwef1be>>1,jea8e7a[5]};ouaad1<=jea8e7a[6];pf55688<=jea8e7a[7];epab447<={uk31c93>>1,jea8e7a[8]};dz5a23c<={lq79093>>1,jea8e7a[9]};kqd11e6<={pfc849a>>1,jea8e7a[10]};ou88f31<=jea8e7a[11];rg47989<=jea8e7a[12];ir3cc4a<={xy9359c>>1,jea8e7a[13]};vve6255<=jea8e7a[14];co312ae<=jea8e7a[15];pu89570<={ksb38ac>>1,jea8e7a[16]};xj4ab82<=jea8e7a[17];jp55c16<=jea8e7a[18];epae0b6<=jea8e7a[19];cz705b4<=jea8e7a[20];ou82da4<=jea8e7a[21];lf16d20<=jea8e7a[22];wyb6907<=jea8e7a[23];uxb4838<=jea8e7a[24];ira41c5<=jea8e7a[25];th40935<=jea8e7a[26];bn3d024<={ie3102c>>1,jea8e7a[27]};bn38b55<=jea8e7a[28];qt60f40<=jea8e7a[29];xl2d57b<=jea8e7a[30];cz6abdf<=jea8e7a[31];rt55efd<=jea8e7a[32];rvaf7ee<=jea8e7a[33];mre8126<=jea8e7a[34];bydfbb6<=jea8e7a[35];alfddb3<=jea8e7a[36];hoeed9d<=jea8e7a[37];dm76ceb<=jea8e7a[38];wyb675a<=jea8e7a[39];wyb3ad1<=jea8e7a[40];sw9d688<=jea8e7a[41];faeb441<={hbe6897>>1,jea8e7a[42]};epb1475<={cmcba31>>1,jea8e7a[43]};gd8a3ac<={vi5d188>>1,jea8e7a[44]};gq882b1<={mt12fc2>>1,jea8e7a[45]};cz41588<={ec97e15>>1,jea8e7a[46]};qiac44<=jea8e7a[47];cm56220<=jea8e7a[48];anb1100<=jea8e7a[49];ym88804<=jea8e7a[50];ecacb35<=jea8e7a[51];fc2010c<=jea8e7a[52];ie863<=jea8e7a[53];ri4319<=jea8e7a[54];gq218ca<=jea8e7a[55];phc650<=jea8e7a[56];vi63286<=jea8e7a[57];fp19432<={yz33c09>>1,jea8e7a[58]};faca197<={lf9e04c>>1,jea8e7a[59]};uv5ef91<=jea8e7a[60];wjf7c8d<=jea8e7a[61];ph32ef3<={ph9986>>1,jea8e7a[62]};ou9779e<={yk4cc37>>1,jea8e7a[63]};sjbbcf0<=jea8e7a[64];qgde784<=jea8e7a[65];nrf3c20<=jea8e7a[66];bn9e106<=jea8e7a[67];uif0836<=jea8e7a[68];jr841b1<=jea8e7a[69];vk20d8e<=jea8e7a[70];fp6c72<=jea8e7a[71];qv36396<=jea8e7a[72];cbb1cb5<=jea8e7a[73];vx8e5ad<=jea8e7a[74];ui72d6f<=jea8e7a[75];do96b78<={qg72b18>>1,jea8e7a[76]};ntb5bc3<={yz958c0>>1,jea8e7a[77]};end
-always@* begin ls351cf[2047]<=an_link_ok;ls351cf[2046]<=ic626ef;ls351cf[2044]<=gbe_mode;ls351cf[2040]<=operational_rate[0];ls351cf[2032]<=wwef1be[0];ls351cf[2018]<=hbe6897[0];ls351cf[2017]<=os78df0;ls351cf[1989]<=cmcba31[0];ls351cf[1987]<=qtc6f81;ls351cf[1931]<=vi5d188[0];ls351cf[1927]<=uk31c93[0];ls351cf[1865]<=ksb38ac[0];ls351cf[1859]<=an80a07;ls351cf[1844]<=rg7cc46;ls351cf[1815]<=mt12fc2[0];ls351cf[1806]<=lq79093[0];ls351cf[1682]<=ba9c560;ls351cf[1674]<=yz33c09[0];ls351cf[1671]<=ks88160;ls351cf[1640]<=pfe6233;ls351cf[1582]<=ec97e15[0];ls351cf[1565]<=pfc849a[0];ls351cf[1488]<=qgea028;ls351cf[1485]<=ec88708;ls351cf[1326]<=jp40b00;ls351cf[1317]<=ale2b03;ls351cf[1300]<=lf9e04c[0];ls351cf[1297]<=ng30dca;ls351cf[1295]<=jr281e8;ls351cf[1233]<=gq3119e;ls351cf[1210]<=ay6df50;ls351cf[1189]<=mt1d06e;ls351cf[1172]<=mgac0e8;ls351cf[1124]<=xwc5cac;ls351cf[1116]<=vxbf0a9;ls351cf[1105]<=cm6de53;ls351cf[1094]<=ep9ae18;ls351cf[1092]<=bn3729a;ls351cf[1087]<=sj7a3f;ls351cf[1082]<=vi424d6;ls351cf[1023]<=mr_main_reset;ls351cf[1009]<=do3f9a2;ls351cf[932]<=kdd6715;ls351cf[929]<=vv50140;ls351cf[922]<=vv4f988;ls351cf[837]<=me46781;ls351cf[744]<=su7d405;ls351cf[742]<=uk153e6;ls351cf[663]<=cz41bad;ls351cf[648]<=tu661b9;ls351cf[605]<=ie3102c[0];ls351cf[594]<=lf3a0d;ls351cf[586]<=uk1581d;ls351cf[562]<=yz18b95;ls351cf[552]<=jc4dbca;ls351cf[547]<=ww535c3;ls351cf[546]<=do86e53;ls351cf[543]<=vv40f47;ls351cf[504]<=xw47f34;ls351cf[466]<=mt9ace2;ls351cf[418]<=uk88cf0;ls351cf[400]<=yz958c0[1];ls351cf[372]<=en44c40;ls351cf[371]<=jpc2a7c;ls351cf[331]<=kde8375;ls351cf[324]<=yk4cc37[0];ls351cf[297]<=sh60741;ls351cf[281]<=bab862e;ls351cf[273]<=faca6b8;ls351cf[252]<=kde8fe6;ls351cf[233]<=xy9359c[0];ls351cf[200]<=qg72b18[1];ls351cf[185]<=uvf854f;ls351cf[162]<=ph9986[0];ls351cf[140]<=zxd70c5;ls351cf[136]<=ksb94d7;ls351cf[126]<=rv3d1fc;ls351cf[116]<=sj126b3;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module mtb4bc4 (
- rst_n,
- mr_main_reset,
-
- lddde37,
- wwef1be,
- os78df0,
- qtc6f81,
-
- bn37c0c,
- irbe066,
- suf0335,
- ph819a8,
- xlcd47,
- ctc_drop_flag,
- ctc_add_flag
-);
-input rst_n;
-input mr_main_reset;
-input lddde37;
-input [7:0] wwef1be;
-input os78df0;
-input qtc6f81;
-input bn37c0c;
-output [7:0] irbe066;
-output suf0335;
-output ph819a8;
-output xlcd47;
-output ctc_drop_flag;
-output ctc_add_flag;
-parameter STATIC_HI_THRESH = 32;
-parameter STATIC_LO_THRESH = 16;
-localparam jr9b431 = 2'd0, hoda18e = 2'd1, rgd0c72 = 2'd2, pu86392 = 2'd3;
-reg[1:0] uk31c93;
-localparam jr8e499 = 3'd0, cm724cf = 3'd1, sw92679 = 3'd2, xy933c8 = 3'd3, ls99e42 = 3'd4, xwcf212 = 3'd5;
-reg [2:0] lq79093;
-reg [7:0] pfc849a;
-reg vi424d6;
-reg sj126b3 ;
-reg [7:0] xy9359c;
-reg mt9ace2;
-reg kdd6715 ;
-reg [7:0] ksb38ac;
-reg ba9c560;
-reg ale2b03 ;
-reg uk1581d;
-reg mgac0e8;
-reg sh60741;
-reg lf3a0d;
-reg mt1d06e;
-reg kde8375;
-reg cz41bad;
-reg jp40b00;
-reg [7:0] irbe066;
-reg suf0335;
-reg ph819a8;
-wire [7:0] ie3102c;
-wire ay6df50;
-wire en44c40;
-wire su7d405;
-wire qgea028;
-wire vv50140;
-reg an80a07;
-wire ks88160;
-reg jr281e8;
-reg vv40f47;
-reg sj7a3f;
-reg rv3d1fc;
-reg kde8fe6;
-reg xw47f34;
-reg do3f9a2;
-wire xlcd47;
-wire [7:0] hbe6897;
-reg ksb94d7 ;
-reg faca6b8 ;
-reg ww535c3 ;
-reg ep9ae18 ;
-reg zxd70c5;
-reg bab862e;
-reg ctc_drop_flag;
-reg yz18b95;
-reg xwc5cac;
-reg ctc_add_flag;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-`endif\r
-reg [(22*8):1] qg72b18;
-reg [(22*8):1] yz958c0;
-reg qg49292;
-reg [7 : 0] wy2155a;
-reg ouaad1;
-reg pf55688;
-reg [1 : 0] epab447;
-reg [2 : 0] dz5a23c;
-reg [7 : 0] kqd11e6;
-reg ou88f31;
-reg rg47989;
-reg [7 : 0] ir3cc4a;
-reg vve6255;
-reg co312ae;
-reg [7 : 0] pu89570;
-reg xj4ab82;
-reg jp55c16;
-reg epae0b6;
-reg cz705b4;
-reg ou82da4;
-reg lf16d20;
-reg wyb6907;
-reg uxb4838;
-reg ira41c5;
-reg th40935;
-reg [7 : 0] bn3d024;
-reg bn38b55;
-reg qt60f40;
-reg xl2d57b;
-reg cz6abdf;
-reg rt55efd;
-reg rvaf7ee;
-reg mre8126;
-reg bydfbb6;
-reg alfddb3;
-reg hoeed9d;
-reg dm76ceb;
-reg wyb675a;
-reg wyb3ad1;
-reg sw9d688;
-reg [7 : 0] faeb441;
-reg uif0836;
-reg jr841b1;
-reg vk20d8e;
-reg fp6c72;
-reg qv36396;
-reg cbb1cb5;
-reg vx8e5ad;
-reg ui72d6f;
-reg [(22 * 8) : 1] do96b78;
-reg [(22 * 8) : 1] ntb5bc3;
-reg [2047:0] ls351cf;
-wire [48:0] jea8e7a;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-localparam ps473d2 = 49,wl39e93 = 32'hfdffe44b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ksb94d7 <= 1'b1; faca6b8 <= 1'b1; end else begin ksb94d7 <= qg49292; faca6b8 <= uif0836; end
-end
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin ww535c3 <= 1'b1; ep9ae18 <= 1'b1; end else begin ww535c3 <= qg49292; ep9ae18 <= vk20d8e; end
-end
-
-
-
-
-
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin pfc849a <= 8'd0; vi424d6 <= 1'b0; sj126b3 <= 1'b0; xy9359c <= 8'd0; mt9ace2 <= 1'b0; kdd6715 <= 1'b0; ksb38ac <= 8'd0; ba9c560 <= 1'b0; ale2b03 <= 1'b0; end else begin pfc849a <= wy2155a; vi424d6 <= ouaad1; sj126b3 <= pf55688; xy9359c <= kqd11e6; mt9ace2 <= ou88f31; kdd6715 <= rg47989; ksb38ac <= ir3cc4a; ba9c560 <= vve6255; ale2b03 <= co312ae; end
-end
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin uk1581d <= 1'b0; mgac0e8 <= 1'b0; sh60741 <= 1'b0; lf3a0d <= 1'b0; mt1d06e <= 1'b0; kde8375 <= 1'b0; end else begin if ((ou88f31 == 1'b1) && (kqd11e6 == 8'hBC)) begin uk1581d <= 1'b1; end else begin uk1581d <= 1'b0; end
- if ((ouaad1 == 1'b0) && (wy2155a == 8'hC5)) begin mgac0e8 <= 1'b1; end else begin mgac0e8 <= 1'b0; end if ((ouaad1 == 1'b0) && (wy2155a == 8'h50)) begin sh60741 <= 1'b1; end else begin sh60741 <= 1'b0; end if ((ouaad1 == 1'b0) && (wy2155a == 8'h42)) begin lf3a0d <= 1'b1; end else begin lf3a0d <= 1'b0; end if ((ouaad1 == 1'b0) && (wy2155a == 8'hB5)) begin mt1d06e <= 1'b1; end else begin mt1d06e <= 1'b0; end if (epae0b6 && (lf16d20 || wyb6907)) begin kde8375 <= 1'b1; end else begin kde8375 <= 1'b0; end end
-end
-
-
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin uk31c93 <= jr9b431; cz41bad <= 1'b0; zxd70c5 <= 1'b0; end else begin if (jr841b1) begin uk31c93 <= jr9b431; cz41bad <= 1'b0; end else begin zxd70c5 <= 1'b0; case (epab447) jr9b431: begin if (cz6abdf) begin if (epae0b6 && (ou82da4 || lf16d20 || wyb6907)) begin cz41bad <= 1'b0; uk31c93 <= hoda18e; zxd70c5 <= 1'b1; end end else begin cz41bad <= 1'b1; uk31c93 <= jr9b431; end end hoda18e: begin cz41bad <= 1'b0; zxd70c5 <= 1'b1; if (uxb4838) begin uk31c93 <= rgd0c72; end else begin uk31c93 <= jr9b431; end end rgd0c72: begin cz41bad <= 1'b0; zxd70c5 <= 1'b1; uk31c93 <= pu86392; end pu86392: begin cz41bad <= 1'b0; zxd70c5 <= 1'b1; uk31c93 <= jr9b431; end
- default: begin uk31c93 <= jr9b431; end endcase end end
-end
-
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin bab862e <= 1'b0; ctc_drop_flag <= 1'b0; end else begin bab862e <= qv36396; ctc_drop_flag <= qv36396 | cbb1cb5; end
-end
-
-
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin lq79093 <= jr8e499; irbe066 <= 8'hBC; suf0335 <= 1'b1; ph819a8 <= 1'b0; jp40b00 <= 1'b0; yz18b95 <= 1'b1; end else begin if (fp6c72) begin lq79093 <= jr8e499; jp40b00 <= 1'b0; end else begin irbe066 <= bn3d024; suf0335 <= bn38b55; ph819a8 <= qt60f40; jp40b00 <= 1'b0; yz18b95 <= 1'b0; case (dz5a23c) jr8e499: begin suf0335 <= 1'b1; ph819a8 <= 1'b0; irbe066 <= 8'hBC; yz18b95 <= 1'b1; if (xl2d57b) begin lq79093 <= xwcf212; end else begin jp40b00 <= 1'b1; lq79093 <= cm724cf; end end cm724cf: begin suf0335 <= 1'b0; ph819a8 <= 1'b0; irbe066 <= 8'h50; yz18b95 <= 1'b1; jp40b00 <= 1'b1; lq79093 <= ls99e42; end sw92679: begin suf0335 <= 1'b1; ph819a8 <= 1'b0; irbe066 <= 8'hBC; yz18b95 <= 1'b1; if (xl2d57b) begin lq79093 <= xwcf212; end else begin jp40b00 <= 1'b1; lq79093 <= xy933c8; end end
- xy933c8: begin jp40b00 <= 1'b1; lq79093 <= ls99e42; end
-
- ls99e42: begin if (xl2d57b && bn38b55 && (bn3d024 == 8'hBC)) begin suf0335 <= 1'b1; ph819a8 <= 1'b0; irbe066 <= 8'hBC; yz18b95 <= 1'b1; lq79093 <= xwcf212; end else begin jp40b00 <= 1'b1; lq79093 <= ls99e42; end end xwcf212: begin suf0335 <= 1'b0; ph819a8 <= 1'b0; irbe066 <= 8'h50; yz18b95 <= 1'b1; lq79093 <= sw92679; end default: begin lq79093 <= jr8e499; end endcase end end
-end
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin xwc5cac <= 1'b1; ctc_add_flag <= 1'b1; end else begin xwc5cac <= vx8e5ad; ctc_add_flag <= vx8e5ad | ui72d6f; end
-end
-
-
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin vv40f47 <= 1'd0; sj7a3f <= 1'd0; rv3d1fc <= 1'd0; an80a07 <= 1'd0; end else begin an80a07 <= rt55efd; if (rvaf7ee && ira41c5) begin vv40f47 <= 1'd1; end else begin vv40f47 <= 1'd0; end sj7a3f <= alfddb3; rv3d1fc <= alfddb3 | hoeed9d; end
-end
-
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin kde8fe6 <= 1'd0; xw47f34 <= 1'd0; do3f9a2 <= 1'd0; jr281e8 <= 1'd1; end else begin jr281e8 <= mre8126; if (bydfbb6 && th40935) begin kde8fe6 <= 1'd1; end else begin kde8fe6 <= 1'd0; end xw47f34 <= wyb675a; do3f9a2 <= wyb675a | wyb3ad1; end
-end
-
-
-assign xlcd47 = dm76ceb | sw9d688;
-
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(18), .pmi_data_width_r(18), .pmi_data_depth_w(1024), .pmi_data_depth_r(1024), .pmi_full_flag(1024), .pmi_empty_flag(0), .pmi_almost_full_flag(STATIC_HI_THRESH), .pmi_almost_empty_flag(STATIC_LO_THRESH), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("EBR")) ohab5fd ( .Reset(faca6b8), .RPReset(ep9ae18), .WrClock(lddde37), .WrEn(cz41bad), .Data({8'd0, ale2b03, ba9c560, ksb38ac}),
- .RdClock(bn37c0c), .RdEn(jp40b00), .Q({hbe6897, en44c40, ay6df50, ie3102c}),
- .Empty(ks88160), .Full(vv50140), .AlmostEmpty(su7d405), .AlmostFull(qgea028) );
-
-`endif\r
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(18), .pmi_data_width_r(18), .pmi_data_depth_w(1024), .pmi_data_depth_r(1024), .pmi_full_flag(1024), .pmi_empty_flag(0), .pmi_almost_full_flag(STATIC_HI_THRESH), .pmi_almost_empty_flag(STATIC_LO_THRESH), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("EBR")) ohab5fd ( .Reset(faca6b8), .RPReset(ep9ae18), .WrClock(lddde37), .WrEn(cz41bad), .Data({8'd0, ale2b03, ba9c560, ksb38ac}),
- .RdClock(bn37c0c), .RdEn(jp40b00), .Q({hbe6897, en44c40, ay6df50, ie3102c}),
- .Empty(ks88160), .Full(vv50140), .AlmostEmpty(su7d405), .AlmostFull(qgea028) );
-
-`endif\r
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(18), .pmi_data_width_r(18), .pmi_data_depth_w(1024), .pmi_data_depth_r(1024), .pmi_full_flag(1024), .pmi_empty_flag(0), .pmi_almost_full_flag(STATIC_HI_THRESH), .pmi_almost_empty_flag(STATIC_LO_THRESH), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("EBR")) ohab5fd ( .Reset(faca6b8), .RPReset(ep9ae18), .WrClock(lddde37), .WrEn(cz41bad), .Data({8'd0, ale2b03, ba9c560, ksb38ac}),
- .RdClock(bn37c0c), .RdEn(jp40b00), .Q({hbe6897, en44c40, ay6df50, ie3102c}),
- .Empty(ks88160), .Full(vv50140), .AlmostEmpty(su7d405), .AlmostFull(qgea028) );
-
-`endif\r
-
-
-
-
-
-
-always @(epab447) begin case (epab447) jr9b431 : qg72b18 = "SEEK_IDLE_START"; hoda18e : qg72b18 = "DISABLE_WRITES"; rgd0c72 : qg72b18 = "DISABLE_W3"; pu86392 : qg72b18 = "DISABLE_W4"; default : qg72b18 = "***ERROR***"; endcase
-end
-
-always @(dz5a23c) begin case (dz5a23c) jr8e499 : yz958c0 = "SEEK_BEGIN_THRESH"; cm724cf : yz958c0 = "DELAY_BEGIN"; sw92679 : yz958c0 = "SEEK_START_THRESH"; xy933c8 : yz958c0 = "DELAY"; ls99e42 : yz958c0 = "SEEK_STOP_THRESH"; xwcf212 : yz958c0 = "INSERT_IDLE"; default : yz958c0 = "***ERROR***"; endcase
-end
-
-
-
-
-always@* begin qg49292<=jea8e7a[0];wy2155a<={wwef1be>>1,jea8e7a[1]};ouaad1<=jea8e7a[2];pf55688<=jea8e7a[3];epab447<={uk31c93>>1,jea8e7a[4]};dz5a23c<={lq79093>>1,jea8e7a[5]};kqd11e6<={pfc849a>>1,jea8e7a[6]};ou88f31<=jea8e7a[7];rg47989<=jea8e7a[8];ir3cc4a<={xy9359c>>1,jea8e7a[9]};vve6255<=jea8e7a[10];co312ae<=jea8e7a[11];pu89570<={ksb38ac>>1,jea8e7a[12]};xj4ab82<=jea8e7a[13];jp55c16<=jea8e7a[14];epae0b6<=jea8e7a[15];cz705b4<=jea8e7a[16];ou82da4<=jea8e7a[17];lf16d20<=jea8e7a[18];wyb6907<=jea8e7a[19];uxb4838<=jea8e7a[20];ira41c5<=jea8e7a[21];th40935<=jea8e7a[22];bn3d024<={ie3102c>>1,jea8e7a[23]};bn38b55<=jea8e7a[24];qt60f40<=jea8e7a[25];xl2d57b<=jea8e7a[26];cz6abdf<=jea8e7a[27];rt55efd<=jea8e7a[28];rvaf7ee<=jea8e7a[29];mre8126<=jea8e7a[30];bydfbb6<=jea8e7a[31];alfddb3<=jea8e7a[32];hoeed9d<=jea8e7a[33];dm76ceb<=jea8e7a[34];wyb675a<=jea8e7a[35];wyb3ad1<=jea8e7a[36];sw9d688<=jea8e7a[37];faeb441<={hbe6897>>1,jea8e7a[38]};uif0836<=jea8e7a[39];jr841b1<=jea8e7a[40];vk20d8e<=jea8e7a[41];fp6c72<=jea8e7a[42];qv36396<=jea8e7a[43];cbb1cb5<=jea8e7a[44];vx8e5ad<=jea8e7a[45];ui72d6f<=jea8e7a[46];do96b78<={qg72b18>>1,jea8e7a[47]};ntb5bc3<={yz958c0>>1,jea8e7a[48]};end
-always@* begin ls351cf[2047]<=wwef1be[0];ls351cf[2046]<=os78df0;ls351cf[2044]<=qtc6f81;ls351cf[2040]<=uk31c93[0];ls351cf[2033]<=lq79093[0];ls351cf[2019]<=pfc849a[0];ls351cf[1991]<=vi424d6;ls351cf[1934]<=sj126b3;ls351cf[1929]<=qg72b18[1];ls351cf[1898]<=uk1581d;ls351cf[1821]<=xy9359c[0];ls351cf[1810]<=yz958c0[1];ls351cf[1749]<=mgac0e8;ls351cf[1707]<=mt1d06e;ls351cf[1666]<=vv50140;ls351cf[1630]<=ww535c3;ls351cf[1595]<=mt9ace2;ls351cf[1506]<=yz18b95;ls351cf[1450]<=sh60741;ls351cf[1440]<=su7d405;ls351cf[1384]<=ay6df50;ls351cf[1370]<=jp40b00;ls351cf[1366]<=kde8375;ls351cf[1284]<=an80a07;ls351cf[1212]<=ep9ae18;ls351cf[1142]<=kdd6715;ls351cf[1125]<=do3f9a2;ls351cf[1041]<=jr281e8;ls351cf[1023]<=mr_main_reset;ls351cf[964]<=xwc5cac;ls351cf[949]<=ale2b03;ls351cf[853]<=lf3a0d;ls351cf[833]<=qgea028;ls351cf[815]<=faca6b8;ls351cf[753]<=bab862e;ls351cf[720]<=en44c40;ls351cf[692]<=ie3102c[0];ls351cf[685]<=cz41bad;ls351cf[562]<=xw47f34;ls351cf[520]<=ks88160;ls351cf[474]<=ba9c560;ls351cf[407]<=ksb94d7;ls351cf[376]<=zxd70c5;ls351cf[281]<=kde8fe6;ls351cf[237]<=ksb38ac[0];ls351cf[203]<=hbe6897[0];ls351cf[140]<=rv3d1fc;ls351cf[70]<=sj7a3f;ls351cf[35]<=vv40f47;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module mtbbc32 (
- rst_n,
- mr_main_reset,
-
- lddde37,
- wwef1be,
- os78df0,
- qtc6f81,
-
- bn37c0c,
- irbe066,
- suf0335,
- ph819a8,
- xlcd47
-);
-input rst_n;
-input mr_main_reset;
-input lddde37;
-input [7:0] wwef1be;
-input os78df0;
-input qtc6f81;
-input bn37c0c;
-output [7:0] irbe066;
-output suf0335;
-output ph819a8;
-output xlcd47;
-reg [7:0] pfc849a;
-reg vi424d6;
-reg sj126b3;
-reg cz41bad;
-reg jp40b00;
-reg [7:0] irbe066;
-reg suf0335;
-reg ph819a8;
-wire [7:0] ie3102c;
-wire ay6df50;
-wire en44c40;
-wire su7d405;
-wire qgea028;
-wire vv50140;
-wire ks88160;
-reg vv40f47;
-reg sj7a3f;
-reg rv3d1fc;
-reg kde8fe6;
-reg xw47f34;
-reg do3f9a2;
-wire xlcd47;
-reg ksb94d7 ;
-reg faca6b8 ;
-reg ww535c3 ;
-reg ep9ae18 ;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-`endif\r
-reg qg49292;
-reg [7 : 0] wy2155a;
-reg ouaad1;
-reg pf55688;
-reg [7 : 0] kqd11e6;
-reg ou88f31;
-reg rg47989;
-reg ira41c5;
-reg th40935;
-reg [7 : 0] bn3d024;
-reg bn38b55;
-reg qt60f40;
-reg xl2d57b;
-reg cz6abdf;
-reg rt55efd;
-reg mre8126;
-reg alfddb3;
-reg hoeed9d;
-reg dm76ceb;
-reg wyb675a;
-reg wyb3ad1;
-reg sw9d688;
-reg uif0836;
-reg jr841b1;
-reg vk20d8e;
-reg fp6c72;
-reg [2047:0] ls351cf;
-wire [25:0] jea8e7a;
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-localparam ps473d2 = 26,wl39e93 = 32'hfdffd14b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-
-
-`endif\r
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-
-
-`endif\r
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin ksb94d7 <= 1'b1; faca6b8 <= 1'b1; end else begin ksb94d7 <= qg49292; faca6b8 <= uif0836; end
-end
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin ww535c3 <= 1'b1; ep9ae18 <= 1'b1; end else begin ww535c3 <= qg49292; ep9ae18 <= vk20d8e; end
-end
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin pfc849a <= 8'd0; vi424d6 <= 1'b0; sj126b3 <= 1'b0; end else begin pfc849a <= wy2155a; vi424d6 <= ouaad1; sj126b3 <= pf55688; end
-end
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin irbe066 <= 8'd0; suf0335 <= 1'b0; ph819a8 <= 1'b0; end else begin irbe066 <= bn3d024; suf0335 <= bn38b55; ph819a8 <= qt60f40; end
-end
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin cz41bad <= 1'b0; end else begin if (jr841b1) begin cz41bad <= 1'b0; end else begin if (rt55efd) begin cz41bad <= 1'b0; end else begin cz41bad <= 1'b1; end end end
-end
-
-
-
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin jp40b00 <= 1'b0; end else begin if (fp6c72) begin jp40b00 <= 1'b0; end else begin if (mre8126) begin jp40b00 <= 1'b0; end else if (xl2d57b) begin jp40b00 <= 1'b0; end else begin jp40b00 <= 1'b1; end end end
-end
-
-
-
-
-always @(posedge lddde37 or negedge rst_n)
-begin if (rst_n == 1'b0) begin vv40f47 <= 1'd0; sj7a3f <= 1'd0; rv3d1fc <= 1'd0; end else begin if (rt55efd && ira41c5) begin vv40f47 <= 1'd1; end else begin vv40f47 <= 1'd0; end sj7a3f <= alfddb3; rv3d1fc <= alfddb3 | hoeed9d; end
-end
-
-
-
-always @(posedge bn37c0c or negedge rst_n)
-begin if (rst_n == 1'b0) begin kde8fe6 <= 1'd0; xw47f34 <= 1'd0; do3f9a2 <= 1'd0; end else begin if (mre8126 && th40935) begin kde8fe6 <= 1'd1; end else begin kde8fe6 <= 1'd0; end xw47f34 <= wyb675a; do3f9a2 <= wyb675a | wyb3ad1; end
-end
-
-
-assign xlcd47 = dm76ceb | sw9d688;
-
-
-
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(16), .pmi_data_depth_r(16), .pmi_full_flag(16), .pmi_empty_flag(0), .pmi_almost_full_flag(13), .pmi_almost_empty_flag(7), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) ohab5fd ( .Reset(faca6b8), .RPReset(ep9ae18), .WrClock(lddde37), .WrEn(cz41bad), .Data({sj126b3, vi424d6, pfc849a}),
- .RdClock(bn37c0c), .RdEn(jp40b00), .Q({en44c40, ay6df50, ie3102c}),
- .Empty(ks88160), .Full(vv50140), .AlmostEmpty(su7d405), .AlmostFull(qgea028) );
-
-`endif\r
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(16), .pmi_data_depth_r(16), .pmi_full_flag(16), .pmi_empty_flag(0), .pmi_almost_full_flag(13), .pmi_almost_empty_flag(7), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) ohab5fd ( .Reset(faca6b8), .RPReset(ep9ae18), .WrClock(lddde37), .WrEn(cz41bad), .Data({sj126b3, vi424d6, pfc849a}),
- .RdClock(bn37c0c), .RdEn(jp40b00), .Q({en44c40, ay6df50, ie3102c}),
- .Empty(ks88160), .Full(vv50140), .AlmostEmpty(su7d405), .AlmostFull(qgea028) );
-
-`endif\r
-
-
-
-
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(16), .pmi_data_depth_r(16), .pmi_full_flag(16), .pmi_empty_flag(0), .pmi_almost_full_flag(13), .pmi_almost_empty_flag(7), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) ohab5fd ( .Reset(faca6b8), .RPReset(ep9ae18), .WrClock(lddde37), .WrEn(cz41bad), .Data({sj126b3, vi424d6, pfc849a}),
- .RdClock(bn37c0c), .RdEn(jp40b00), .Q({en44c40, ay6df50, ie3102c}),
- .Empty(ks88160), .Full(vv50140), .AlmostEmpty(su7d405), .AlmostFull(qgea028) );
-
-`endif\r
-
-
-
-
-always@* begin qg49292<=jea8e7a[0];wy2155a<={wwef1be>>1,jea8e7a[1]};ouaad1<=jea8e7a[2];pf55688<=jea8e7a[3];kqd11e6<={pfc849a>>1,jea8e7a[4]};ou88f31<=jea8e7a[5];rg47989<=jea8e7a[6];ira41c5<=jea8e7a[7];th40935<=jea8e7a[8];bn3d024<={ie3102c>>1,jea8e7a[9]};bn38b55<=jea8e7a[10];qt60f40<=jea8e7a[11];xl2d57b<=jea8e7a[12];cz6abdf<=jea8e7a[13];rt55efd<=jea8e7a[14];mre8126<=jea8e7a[15];alfddb3<=jea8e7a[16];hoeed9d<=jea8e7a[17];dm76ceb<=jea8e7a[18];wyb675a<=jea8e7a[19];wyb3ad1<=jea8e7a[20];sw9d688<=jea8e7a[21];uif0836<=jea8e7a[22];jr841b1<=jea8e7a[23];vk20d8e<=jea8e7a[24];fp6c72<=jea8e7a[25];end
-always@* begin ls351cf[2047]<=wwef1be[0];ls351cf[2046]<=os78df0;ls351cf[2044]<=qtc6f81;ls351cf[2040]<=pfc849a[0];ls351cf[2033]<=vi424d6;ls351cf[2019]<=sj126b3;ls351cf[1990]<=cz41bad;ls351cf[1939]<=rv3d1fc;ls351cf[1933]<=jp40b00;ls351cf[1831]<=kde8fe6;ls351cf[1819]<=ie3102c[0];ls351cf[1778]<=ks88160;ls351cf[1615]<=xw47f34;ls351cf[1591]<=ay6df50;ls351cf[1508]<=vv40f47;ls351cf[1271]<=ww535c3;ls351cf[1182]<=do3f9a2;ls351cf[1135]<=en44c40;ls351cf[1023]<=mr_main_reset;ls351cf[969]<=sj7a3f;ls351cf[889]<=vv50140;ls351cf[635]<=faca6b8;ls351cf[495]<=ep9ae18;ls351cf[444]<=qgea028;ls351cf[317]<=ksb94d7;ls351cf[222]<=su7d405;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module th4f530 ( yz26485,
- rst_n,
- mr_main_reset,
- force_unidir,
- vif148d,
- an3c018,
- tx_en,
- tx_er,
- sjbe291,
- ux18847,
- qgc423c,
- ym211e0
- );
-parameter ep2ca37 = 8'hbc, cz651bc = 8'hfe, nt28de5 = 8'hfb, ui46f2e = 8'hfd, hd37970 = 8'hf7, cobcb86 = 8'hb5, wwe5c31 = 8'h42, ks2e188 = 8'hc5, yx70c40 = 8'h50;
-parameter jr8b4d0 = 2'b00, fn5a687 = 2'b01, czd343e = 2'b10;
-parameter ph2da80 = 5'd0, kq6d406 = 5'd1, cz6a031 = 5'd2, nr5018c = 5'd3, oh80c67 = 5'd4, ph633d = 5'd5, uk319ef = 5'd6, hq8cf79 = 5'd7, me67bcb = 5'd8, ph3de59 = 5'd9, wwef2cf = 5'd10, ps79678 = 5'd11, sucb3c2 = 5'd12, ww59e11 = 5'd13, hocf088 = 5'd14, me78443 = 5'd15, xjc2218 = 5'd16, hq110c7 = 5'd17, qi8863b = 5'd18;
-input yz26485;
-input rst_n;
-input mr_main_reset;
-input force_unidir;
-input [1:0] vif148d;
-input [7:0] an3c018;
-input tx_en;
-input tx_er;
-input [15:0] sjbe291;
-output [7:0] ux18847;
-output qgc423c;
-output ym211e0;
-wire yz26485;
-wire rst_n;
-wire [1:0] vif148d;
-wire [7:0] an3c018;
-wire tx_en;
-wire tx_er;
-wire [15:0] sjbe291;
-reg [7:0] ux18847;
-reg [7:0] ph8415e;
-reg [7:0] ri20af6;
-reg wy57b2;
-reg qgc423c;
-reg en5ec81;
-reg ym211e0;
-reg [7:0] vkb206f;
-reg qv9037b;
-reg nt81bdd;
-reg [4:0] yxc3947;
-reg [4:0] nt1ca3c;
-reg [4:0] rtd8728;
-reg blddf66;
-reg uiefb36;
-reg cm7d9b1;
-reg [1:0] zxecd89;
-wire [1:0] ne66c4e;
-reg wl36273;
-wire yzb139d;
-reg je89cec;
-reg ay4351e ;
-reg ec1a8f1 ;
-reg ou9d8ea;
-reg xjec750;
-reg [(20*8):1] gqa3c49;
-reg qg49292;
-reg vk89252;
-reg rt50ee8;
-reg ou87746;
-reg [7 : 0] mg3ba31;
-reg [7 : 0] xjdd188;
-reg uve8c47;
-reg yk4623c;
-reg [7 : 0] ou311e1;
-reg gq88f08;
-reg fa47841;
-reg [4 : 0] nt8e0cb;
-reg [4 : 0] kd7065f;
-reg [4 : 0] byf1c19;
-reg mr4151c;
-reg swa8e4;
-reg uv54720;
-reg [1 : 0] qia3905;
-reg [1 : 0] vx1c829;
-reg zke414e;
-reg ng20a73;
-reg qi539a;
-reg twa81eb;
-reg xj40f5b;
-reg dm73425;
-reg cb9a12b;
-reg [(20 * 8) : 1] ph3d6fc;
-reg [2047:0] ls351cf;
-wire [26:0] jea8e7a;
-
-localparam ps473d2 = 27,wl39e93 = 32'hfdffd48b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-assign ne66c4e[1:0] = cb9a12b ? czd343e : vif148d;
-assign yzb139d = ((vx1c829 != qia3905) && !swa8e4) || zke414e;
-
-
-
-function [7:0] xl9bd52;
-input [7:0] sudea97;
-input eaf54b9;
-input hdaa5c8;
-input [7:0] zk52e46;
-
-begin if(eaf54b9 == 1'b0 && hdaa5c8 == 1'b1 && zk52e46 != 8'b00001111) xl9bd52 = cz651bc; else if(eaf54b9 == 1'b1 && hdaa5c8 == 1'b1) xl9bd52 = cz651bc; else xl9bd52 = sudea97;
-end
-endfunction
-function sh4bb73;
-input [7:0] sudea97;
-input eaf54b9;
-input hdaa5c8;
-input [7:0] zk52e46;
-
-begin if(eaf54b9 == 1'b0 && hdaa5c8 == 1'b1 && zk52e46 != 8'b00001111) sh4bb73 = 1'b1; else if(eaf54b9 == 1'b1 && hdaa5c8 == 1'b1) sh4bb73 = 1'b1; else sh4bb73 = sudea97;
-end
-endfunction
-
-
-
-
-always @(posedge yz26485 or negedge rst_n)
-begin if(!rst_n) begin ay4351e <= 1'b1; ec1a8f1 <= 1'b1; ou9d8ea <= 1'b0; xjec750 <= 1'b0; end else begin ay4351e <= qg49292; ec1a8f1 <= twa81eb; ou9d8ea <= vk89252; xjec750 <= dm73425; end
-end
-
-always @(posedge yz26485 or negedge rst_n)
-begin : xl8bb74
-if(!rst_n) begin vkb206f <= 8'd0; nt81bdd <= 1'd0; qv9037b <= 1'd0; end
-else begin vkb206f <= an3c018; nt81bdd <= rt50ee8; qv9037b <= ou87746; end
-end
-always @(posedge yz26485 or negedge rst_n)
-begin : cob3765
-if(!rst_n) begin zxecd89 <= 1'd0; wl36273 <= 1'd0; end
-else begin zxecd89 <= vx1c829; wl36273 <= (vx1c829 != qia3905) && swa8e4; end
-end
-always @(posedge yz26485 or negedge rst_n)
-begin : kf36dc3 if(!rst_n) blddf66 <= 1'b0; else begin if(nt8e0cb == ph633d) blddf66 <= ~mr4151c; else blddf66 <= mr4151c; end
-end
-always @(posedge yz26485 or negedge rst_n)
-begin : kf39e42
-if(!rst_n) cm7d9b1 <= 1'd0;
-else cm7d9b1 <= swa8e4;
-end
-always @(posedge yz26485 or negedge rst_n)
-begin : hb5ac8c if (!rst_n) begin yxc3947 <= ph2da80; nt1ca3c <= ph2da80; je89cec <= 1'b0; end else if (xj40f5b) begin yxc3947 <= ph2da80; nt1ca3c <= ph2da80; je89cec <= 1'b0; end else begin nt1ca3c <= nt8e0cb; if (ng20a73) begin je89cec <= 1'b0; case (nt8e0cb) cz6a031: begin yxc3947 <= xjc2218; end nr5018c: begin yxc3947 <= hq110c7; end oh80c67: begin yxc3947 <= qi8863b; end default: begin yxc3947 <= ph2da80; end
- endcase end else begin yxc3947 <= byf1c19; case(qi539a) 0: begin if (nt8e0cb == kq6d406) begin je89cec <= 1'b1; end end 1: begin if ( (nt8e0cb != ph2da80) && (nt8e0cb != kq6d406) ) begin je89cec <= 1'b0; end end default: begin je89cec <= qi539a; end endcase
- end end
-end
-
-
-
-
-always @(nt8e0cb or vif148d or vx1c829 or rt50ee8 or ou87746 or swa8e4)
-begin : zkdfcb3 case (nt8e0cb) ph2da80 : rtd8728 = kq6d406; kq6d406 : begin if (vx1c829 == fn5a687) rtd8728 = cz6a031;
-
- else if (vx1c829 == jr8b4d0) rtd8728 = ph2da80; else if (vx1c829 == czd343e) begin if (rt50ee8) begin if(ou87746 == 1'b0) rtd8728 = uk319ef; else rtd8728 = hocf088; end else rtd8728 = ph2da80; end else rtd8728 = ph2da80; end cz6a031 : rtd8728 = nr5018c; nr5018c : rtd8728 = oh80c67; oh80c67 : rtd8728 = ph633d; ph633d : rtd8728 = cz6a031; xjc2218 : rtd8728 = hq110c7; hq110c7 : rtd8728 = qi8863b; qi8863b : rtd8728 = ph2da80;
-
-
-
- uk319ef : begin if (rt50ee8 == 1'b1) rtd8728 = hq8cf79; else begin if (ou87746 == 1'b0) rtd8728 = me67bcb; else rtd8728 = ps79678; end end hq8cf79 : begin if (rt50ee8 == 1'b1) rtd8728 = hq8cf79; else begin if (ou87746 == 1'b0) rtd8728 = me67bcb; else rtd8728 = ps79678; end end me67bcb : rtd8728 = ph3de59; ph3de59 : begin if (swa8e4 == 1'b0) rtd8728 = ph2da80; else rtd8728 = wwef2cf; end wwef2cf : rtd8728 = ph2da80; ps79678 : begin if (ou87746 == 1'b0) rtd8728 = sucb3c2; else rtd8728 = ww59e11; end sucb3c2 : rtd8728 = ph3de59; ww59e11 : begin if (rt50ee8 == 1'b0 && ou87746 == 1'b0) rtd8728 = sucb3c2; else if (rt50ee8 == 1'b1 && ou87746 == 1'b1) rtd8728 = hocf088; else if (rt50ee8 == 1'b1 && ou87746 == 1'b0) rtd8728 = uk319ef; else rtd8728 = ww59e11; end hocf088 : rtd8728 = me78443; me78443 : begin if (rt50ee8 == 1'b1) rtd8728 = hq8cf79; else begin if (ou87746 == 1'b0) rtd8728 = me67bcb; else rtd8728 = ps79678; end end default : rtd8728 = ph2da80; endcase
-end
-
-always @(posedge yz26485 or negedge rst_n)
-begin : ls35a57
-if(!rst_n) begin ux18847 <= ep2ca37; ph8415e <= ep2ca37; ri20af6 <= ep2ca37; qgc423c <= 1'b1; wy57b2 <= 1'b1; ym211e0 <= 1'b0; en5ec81 <= 1'b0; end
-else begin if(kd7065f < 7) ux18847 <= mg3ba31; else ux18847 <= xjdd188;
- qgc423c <= uve8c47; ym211e0 <= yk4623c; en5ec81 <= 1'b0;
- case(nt8e0cb) ph2da80 : begin ph8415e <= ep2ca37; wy57b2 <= 1'b1; end kq6d406 : begin ph8415e <= yx70c40; wy57b2 <= 1'b0; en5ec81 <= ~qi539a; end cz6a031 : begin ph8415e <= ep2ca37; wy57b2 <= 1'b1; end nr5018c, xjc2218 : begin ph8415e <= mr4151c ? wwe5c31 : cobcb86; wy57b2 <= 1'b0; end oh80c67 , hq110c7: begin ph8415e <= sjbe291[7:0]; wy57b2 <= 1'b0; end ph633d , qi8863b: begin ph8415e <= sjbe291[15:8]; wy57b2 <= 1'b0; end uk319ef : begin ph8415e <= nt28de5; wy57b2 <= 1'b1; end hocf088 : begin ri20af6 <= nt28de5; wy57b2 <= 1'b1; end hq8cf79 : begin ri20af6 <= xl9bd52(ou311e1, fa47841, gq88f08, ou311e1); wy57b2 <= sh4bb73(1'b0, fa47841, gq88f08, ou311e1); end me67bcb : begin ri20af6 <= ui46f2e; wy57b2 <= 1'b1; end ph3de59, wwef2cf, sucb3c2 : begin ri20af6 <= hd37970; wy57b2 <= 1'b1; end ps79678 : begin ri20af6 <= xl9bd52(ui46f2e, fa47841, gq88f08, ou311e1); wy57b2 <= 1'b1; end ww59e11 : begin ri20af6 <= xl9bd52(hd37970, fa47841, gq88f08, ou311e1); wy57b2 <= 1'b1; end me78443 : begin ri20af6 <= cz651bc; wy57b2 <= 1'b1; end default : begin ri20af6 <= ep2ca37; wy57b2 <= 1'b1; end endcase
-end
-end
-always @(nt8e0cb or uv54720)
-begin : cbbea6c case(nt8e0cb) ph2da80 : uiefb36 = 1'b1; kq6d406 : uiefb36 = 1'b0; cz6a031 : uiefb36 = 1'b1; nr5018c : uiefb36 = 1'b0; xjc2218 : uiefb36 = 1'b0; oh80c67 : uiefb36 = 1'b1; hq110c7 : uiefb36 = 1'b1; ph633d : uiefb36 = 1'b0; qi8863b : uiefb36 = 1'b0; uk319ef : uiefb36 = ~uv54720; hocf088 : uiefb36 = ~uv54720; hq8cf79 : uiefb36 = ~uv54720; me67bcb : uiefb36 = ~uv54720; ph3de59 : uiefb36 = ~uv54720; wwef2cf : uiefb36 = ~uv54720; sucb3c2 : uiefb36 = ~uv54720; ps79678 : uiefb36 = ~uv54720; ww59e11 : uiefb36 = ~uv54720; me78443 : uiefb36 = ~uv54720; default : uiefb36 = 1'b1; endcase
-end
-
-
-
-
-
-always @(nt8e0cb)
-begin case (nt8e0cb) ph2da80 : gqa3c49 = "IDLE_A"; kq6d406 : gqa3c49 = "IDLE_B"; cz6a031 : gqa3c49 = "CFG_A"; nr5018c : gqa3c49 = "CFG_B"; oh80c67 : gqa3c49 = "CFG_C"; ph633d : gqa3c49 = "CFG_D"; uk319ef : gqa3c49 = "START_OF_PACKET"; hq8cf79 : gqa3c49 = "TX_DATA"; me67bcb : gqa3c49 = "END_OF_PACKET_NOEXT"; ph3de59 : gqa3c49 = "EPD2_NOEXT"; wwef2cf : gqa3c49 = "EPD3"; ps79678 : gqa3c49 = "END_OF_PACKET_EXT"; sucb3c2 : gqa3c49 = "EXTEND_BY_1"; ww59e11 : gqa3c49 = "CARRIER_EXTEND"; hocf088 : gqa3c49 = "START_ERROR"; me78443 : gqa3c49 = "TX_DATA_ERROR"; xjc2218 : gqa3c49 = "cleanup_CFG_B"; hq110c7 : gqa3c49 = "cleanup_CFG_C"; qi8863b : gqa3c49 = "cleanup_CFG_D"; default : gqa3c49 = " ERROR "; endcase
-end
-
-always@* begin qg49292<=jea8e7a[0];vk89252<=jea8e7a[1];rt50ee8<=jea8e7a[2];ou87746<=jea8e7a[3];mg3ba31<={ph8415e>>1,jea8e7a[4]};xjdd188<={ri20af6>>1,jea8e7a[5]};uve8c47<=jea8e7a[6];yk4623c<=jea8e7a[7];ou311e1<={vkb206f>>1,jea8e7a[8]};gq88f08<=jea8e7a[9];fa47841<=jea8e7a[10];nt8e0cb<={yxc3947>>1,jea8e7a[11]};kd7065f<={nt1ca3c>>1,jea8e7a[12]};byf1c19<={rtd8728>>1,jea8e7a[13]};mr4151c<=jea8e7a[14];swa8e4<=jea8e7a[15];uv54720<=jea8e7a[16];qia3905<={zxecd89>>1,jea8e7a[17]};vx1c829<={ne66c4e>>1,jea8e7a[18]};zke414e<=jea8e7a[19];ng20a73<=jea8e7a[20];qi539a<=jea8e7a[21];twa81eb<=jea8e7a[22];xj40f5b<=jea8e7a[23];dm73425<=jea8e7a[24];cb9a12b<=jea8e7a[25];ph3d6fc<={gqa3c49>>1,jea8e7a[26]};end
-always@* begin ls351cf[2047]<=force_unidir;ls351cf[2046]<=tx_en;ls351cf[2044]<=tx_er;ls351cf[2040]<=ph8415e[0];ls351cf[2032]<=ri20af6[0];ls351cf[2017]<=wy57b2;ls351cf[1987]<=en5ec81;ls351cf[1927]<=vkb206f[0];ls351cf[1865]<=cm7d9b1;ls351cf[1806]<=qv9037b;ls351cf[1682]<=zxecd89[0];ls351cf[1565]<=nt81bdd;ls351cf[1326]<=gqa3c49[1];ls351cf[1317]<=ne66c4e[0];ls351cf[1189]<=ec1a8f1;ls351cf[1172]<=yzb139d;ls351cf[1082]<=yxc3947[0];ls351cf[1023]<=mr_main_reset;ls351cf[932]<=uiefb36;ls351cf[663]<=xjec750;ls351cf[594]<=ay4351e;ls351cf[586]<=wl36273;ls351cf[466]<=blddf66;ls351cf[331]<=ou9d8ea;ls351cf[297]<=je89cec;ls351cf[233]<=rtd8728[0];ls351cf[116]<=nt1ca3c[0];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module mt8230 ( yz26485,
- rst_n,
- qgc423c,
- fc30929,
- tj8494b,
- aa24a5f,
- ri252f8,
- cb297c3,
- ym211e0,
- fn5f0ec );
-input yz26485;
-input rst_n;
-input qgc423c;
-input [7:0] fc30929;
-input tj8494b;
-input aa24a5f;
-input ri252f8;
-input cb297c3;
-input ym211e0;
-output [9:0] fn5f0ec;
-reg [9:0] fn5f0ec;
-reg [7:0] uvcc12a;
-reg kd60954;
-wire tw4aa4;
-reg [9:6] ba25523;
-reg [5:0] do2a91b;
-reg [9:6] yx548db;
-reg [5:0] uxa46dc;
-reg an236e5, ri1b72c, sudb962, gbdcb11, ice588c;
-reg ep2c460, ea62305, xy11828, ls8c142, qt60a12;
-reg ou5094;
-reg [7 : 0] lf284a0;
-reg jc42507;
-reg an1283b;
-reg ph941dd;
-reg fpa0eef;
-reg gd777e;
-reg [7 : 0] aa3bbf5;
-reg fnddfa8;
-reg ayefd46;
-reg [9 : 6] bl7ea31;
-reg [5 : 0] kqf518e;
-reg [9 : 6] baa8c70;
-reg [5 : 0] cm46382;
-reg uk31c11;
-reg jr8e089;
-reg en7044f;
-reg ec8227c;
-reg ls113e1;
-reg xy89f0b;
-reg nr4f85b;
-reg fa7c2de;
-reg rge16f2;
-reg bab793;
-reg [2047:0] ls351cf;
-wire [23:0] jea8e7a;
-
-localparam ps473d2 = 24,wl39e93 = 32'hfdffd30b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-
-
-
-
-
-
-
-always @(posedge yz26485 or negedge rst_n) begin if (rst_n == 1'b0) kd60954 <= 1'b0; else kd60954 <= bab793; end
-
-
-assign tw4aa4 = jc42507 ? an1283b : fnddfa8;
-
-
-
-always @(posedge yz26485 or negedge rst_n) begin if (rst_n == 1'b0) fn5f0ec <= 10'b00_0000_0000; else fn5f0ec <= {baa8c70[9:6], cm46382[5:0]}; end
-
-
-
-
-always @(lf284a0 or ph941dd or fpa0eef or ayefd46 or gd777e)
-begin if(gd777e && !ayefd46) begin if (ph941dd) uvcc12a = {lf284a0[7:6], 1'b1, lf284a0[4:0]}; if (fpa0eef) uvcc12a = 8'b110_00101; else uvcc12a = lf284a0; end else uvcc12a = lf284a0;
-end
-
-
-
-
-
-
-
-
-
-always@(aa3bbf5 or ou5094)
-begin: rtc2fe0
-case (aa3bbf5[3:0]) 4'b0000 : begin do2a91b[0] = aa3bbf5[0]; do2a91b[1] = 1; do2a91b[2] = 1; do2a91b[3] = aa3bbf5[3]; do2a91b[4] = aa3bbf5[4]; do2a91b[5] = aa3bbf5[4]; an236e5 = aa3bbf5[4]; ri1b72c = !aa3bbf5[4]; sudb962 = !aa3bbf5[4]; gbdcb11 = aa3bbf5[4]; end 4'b1000 , 4'b0100 , 4'b0010 , 4'b0001 : begin if (aa3bbf5[4] == 0) begin do2a91b[0] = aa3bbf5[0]; do2a91b[1] = aa3bbf5[1]; do2a91b[2] = aa3bbf5[2]; do2a91b[3] = aa3bbf5[3]; do2a91b[4] = 1; do2a91b[5] = 0; an236e5 = aa3bbf5[4]; ri1b72c = !aa3bbf5[4]; sudb962 = !aa3bbf5[4]; gbdcb11 = aa3bbf5[4]; end else if (aa3bbf5[3] == 0) begin do2a91b[0] = aa3bbf5[0]; do2a91b[1] = aa3bbf5[1]; do2a91b[2] = aa3bbf5[2]; do2a91b[3] = aa3bbf5[3]; do2a91b[4] = aa3bbf5[4]; do2a91b[5] = 1; an236e5 = 0; ri1b72c = 0; sudb962 = 0; gbdcb11 = 0; end else begin do2a91b[0] = aa3bbf5[0]; do2a91b[1] = aa3bbf5[1]; do2a91b[2] = 1; do2a91b[3] = aa3bbf5[3]; do2a91b[4] = 0; do2a91b[5] = 0; an236e5 = 0; ri1b72c = 1; sudb962 = 1; gbdcb11 = 0; end end 4'b1100 : begin do2a91b[0] = aa3bbf5[0]; do2a91b[1] = aa3bbf5[1]; do2a91b[2] = aa3bbf5[2]; do2a91b[3] = aa3bbf5[3]; do2a91b[4] = aa3bbf5[4]; if (ou5094 == 1 && aa3bbf5[4] == 1) begin an236e5 = ou5094; ri1b72c = !ou5094; sudb962 = 0; gbdcb11 = 1; do2a91b[5] = 1; end else begin an236e5 = 0; ri1b72c = 0; sudb962 = 0; gbdcb11 = 0; if (aa3bbf5[4] == 0) do2a91b[5] = 1; else do2a91b[5] = 0; end end 4'b0011 , 4'b1010 , 4'b0101 , 4'b1001 , 4'b0110 : begin do2a91b[0] = aa3bbf5[0]; do2a91b[1] = aa3bbf5[1]; do2a91b[2] = aa3bbf5[2]; do2a91b[3] = aa3bbf5[3]; do2a91b[4] = aa3bbf5[4]; an236e5 = 0; ri1b72c = 0; sudb962 = 0; gbdcb11 = 0; if (aa3bbf5[4] == 0) do2a91b[5] = 1; else do2a91b[5] = 0; end 4'b1111: begin do2a91b[0] = aa3bbf5[0]; do2a91b[1] = 0; do2a91b[2] = aa3bbf5[2]; do2a91b[3] = 0; do2a91b[4] = aa3bbf5[4]; do2a91b[5] = aa3bbf5[4]; an236e5 = aa3bbf5[4]; ri1b72c = !aa3bbf5[4]; sudb962 = !aa3bbf5[4]; gbdcb11 = aa3bbf5[4]; end 4'b0111 : begin do2a91b[0] = aa3bbf5[0]; do2a91b[1] = aa3bbf5[1]; do2a91b[2] = aa3bbf5[2]; do2a91b[3] = aa3bbf5[3]; do2a91b[4] = aa3bbf5[4]; do2a91b[5] = 0; ri1b72c = 0; an236e5 = aa3bbf5[4]; sudb962 = 0; gbdcb11 = 1; end 4'b1101 , 4'b1011 , 4'b1110 : begin do2a91b[0] = aa3bbf5[0]; do2a91b[1] = aa3bbf5[1]; do2a91b[2] = aa3bbf5[2]; do2a91b[3] = aa3bbf5[3]; do2a91b[4] = aa3bbf5[4]; do2a91b[5] = 0; ri1b72c = 0; an236e5 = aa3bbf5[4]; sudb962 = 0; gbdcb11 = aa3bbf5[4]; end default : begin do2a91b[5:0] = 0; an236e5 = 0; ri1b72c = 0; sudb962 = 0; gbdcb11 = 0; end
-endcase
-end
-
-
-
-
-always@(uk31c11 or jr8e089 or en7044f or ec8227c or ayefd46 or kqf518e)
-begin: zx55650
-if ((en7044f && ayefd46) || (ec8227c && !ayefd46) || (!en7044f && !ec8227c)) begin uxa46dc[5:0] = kqf518e[5:0]; if (!uk31c11 && !jr8e089) ice588c = ayefd46; else ice588c = uk31c11;
-end
-else begin uxa46dc[0] = !kqf518e[0]; uxa46dc[1] = !kqf518e[1]; uxa46dc[2] = !kqf518e[2]; uxa46dc[3] = !kqf518e[3]; uxa46dc[4] = !kqf518e[4]; uxa46dc[5] = !kqf518e[5]; if (!uk31c11 && !jr8e089) ice588c = ayefd46; else ice588c = !uk31c11;
-end
-end
-
-
-
-always@(aa3bbf5 or ou5094 or cm46382 or ls113e1)
-begin: fc35924
-case (aa3bbf5[7:5]) 3'b000 : begin ba25523[6] = aa3bbf5[5]; ba25523[7] = !aa3bbf5[6]; ba25523[8] = aa3bbf5[7]; ba25523[9] = 0; xy11828 = 1; ls8c142 = 0; ep2c460 = 0; ea62305 = 1; end 3'b001 , 3'b010 , 3'b101 , 3'b110 : begin ba25523[6] = aa3bbf5[5]; ba25523[7] = aa3bbf5[6]; ba25523[8] = aa3bbf5[7]; ba25523[9] = !aa3bbf5[7]; if (ou5094 == 1) xy11828 = 1; else xy11828 = 0; ls8c142 = 0; ep2c460 = 0; ea62305 = 0; end 3'b011 : begin ba25523[6] = aa3bbf5[5]; ba25523[7] = aa3bbf5[6]; ba25523[8] = aa3bbf5[7]; ba25523[9] = 0; xy11828 = 0; ls8c142 = 1; ep2c460 = 0; ea62305 = 0; end 3'b100 : begin ba25523[6] = aa3bbf5[5]; ba25523[7] = aa3bbf5[6]; ba25523[8] = aa3bbf5[7]; ba25523[9] = 0; xy11828 = 1; ls8c142 = 0; ep2c460 = 0; ea62305 = 1; end 3'b111 : begin if ((cm46382[4] == 1 && cm46382[5] == 1 && ls113e1 == 0) || (cm46382[4] == 0 && cm46382[5] == 0 && ls113e1 == 1) || (ou5094 == 1)) begin ba25523[6] = 0; ba25523[7] = aa3bbf5[6]; ba25523[8] = aa3bbf5[7]; ba25523[9] = 1; xy11828 = 0; ls8c142 = 1; ep2c460 = 1; ea62305 = 0; end else begin ba25523[6] = aa3bbf5[5]; ba25523[7] = aa3bbf5[6]; ba25523[8] = aa3bbf5[7]; ba25523[9] = 0; xy11828 = 0; ls8c142 = 1; ep2c460 = 1; ea62305 = 0; end end default : begin ba25523[6] = aa3bbf5[5]; ba25523[7] = aa3bbf5[6]; ba25523[8] = aa3bbf5[7]; ba25523[9] = 0; xy11828 = 0; ls8c142 = 0; ep2c460 = 0; ea62305 = 0; end
-endcase
-end
-
-
-
-always@(xy89f0b or nr4f85b or fa7c2de or rge16f2 or ls113e1 or bl7ea31)
-begin: ykd1487
-if ((fa7c2de && ls113e1) || (rge16f2 && !ls113e1) || (!fa7c2de && !rge16f2)) begin yx548db[9:6] = bl7ea31[9:6]; if (!xy89f0b && !nr4f85b) qt60a12 = ls113e1; else qt60a12 = xy89f0b;
-end
-else begin yx548db[6] = !bl7ea31[6]; yx548db[7] = !bl7ea31[7]; yx548db[8] = !bl7ea31[8]; yx548db[9] = !bl7ea31[9]; if (!xy89f0b && !nr4f85b) qt60a12 = ls113e1; else qt60a12 = !xy89f0b;
-end
-end
-
-always@* begin ou5094<=jea8e7a[0];lf284a0<={fc30929>>1,jea8e7a[1]};jc42507<=jea8e7a[2];an1283b<=jea8e7a[3];ph941dd<=jea8e7a[4];fpa0eef<=jea8e7a[5];gd777e<=jea8e7a[6];aa3bbf5<={uvcc12a>>1,jea8e7a[7]};fnddfa8<=jea8e7a[8];ayefd46<=jea8e7a[9];bl7ea31<={ba25523>>1,jea8e7a[10]};kqf518e<={do2a91b>>1,jea8e7a[11]};baa8c70<={yx548db>>1,jea8e7a[12]};cm46382<={uxa46dc>>1,jea8e7a[13]};uk31c11<=jea8e7a[14];jr8e089<=jea8e7a[15];en7044f<=jea8e7a[16];ec8227c<=jea8e7a[17];ls113e1<=jea8e7a[18];xy89f0b<=jea8e7a[19];nr4f85b<=jea8e7a[20];fa7c2de<=jea8e7a[21];rge16f2<=jea8e7a[22];bab793<=jea8e7a[23];end
-always@* begin ls351cf[2047]<=fc30929[0];ls351cf[2046]<=tj8494b;ls351cf[2044]<=aa24a5f;ls351cf[2040]<=ri252f8;ls351cf[2032]<=cb297c3;ls351cf[2016]<=ym211e0;ls351cf[1985]<=uvcc12a[0];ls351cf[1922]<=kd60954;ls351cf[1796]<=tw4aa4;ls351cf[1544]<=ba25523[6];ls351cf[1302]<=xy11828;ls351cf[1115]<=qt60a12;ls351cf[1105]<=gbdcb11;ls351cf[1041]<=do2a91b[0];ls351cf[1023]<=qgc423c;ls351cf[651]<=ea62305;ls351cf[557]<=ls8c142;ls351cf[552]<=sudb962;ls351cf[325]<=ep2c460;ls351cf[276]<=ri1b72c;ls351cf[162]<=ice588c;ls351cf[138]<=an236e5;ls351cf[69]<=uxa46dc[0];ls351cf[34]<=yx548db[6];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`timescale 1 ns / 100 ps
-module sgmii_gbe_pcs34 (
-
- tx_clk_125 ,
- serdes_recovered_clk ,
- rx_clk_125 ,
- rst_n ,
- gbe_mode ,
- sgmii_mode ,
- signal_detect ,
- debug_link_timer_short,
-
- force_isolate,
- force_loopback,
- force_unidir,
-
- operational_rate,
- rx_compensation_err,
- ctc_drop_flag,
- ctc_add_flag,
- an_link_ok,
-
-`ifdef SGMII_YES_SINGLE_CLOCK\r
- tx_clock_enable_sink ,
- tx_clock_enable_source ,
-
- rx_clock_enable_sink ,
- rx_clock_enable_source ,
-`else\r
- tx_clk_mii ,
- rx_clk_mii ,
-`endif\r
-
-
-
- rx_data ,
- rx_kcntl ,
- rx_even ,
- rx_disp_err ,
- rx_cv_err ,
- rx_err_decode_mode ,
-
-
- tx_d ,
- tx_en ,
- tx_er ,
-
-
- mr_adv_ability ,
- mr_an_enable ,
- mr_main_reset ,
- mr_restart_an ,
-
- mr_an_complete ,
- mr_lp_adv_ability ,
- mr_page_rx ,
-
-
-
- rx_d ,
- rx_dv ,
- rx_er ,
- col ,
- crs ,
-
-
- tx_data,
- tx_kcntl,
- tx_disparity_cntl,
- xmit_autoneg
- ) ;
-input tx_clk_125 ;
-input serdes_recovered_clk ;
-input rx_clk_125 ;
-
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-input tx_clock_enable_sink;
-output tx_clock_enable_source;
-input rx_clock_enable_sink;
-output rx_clock_enable_source;
-
-`else\r
-input tx_clk_mii;
-input rx_clk_mii;
-
-`endif\r
-input rst_n ;
-input signal_detect ;
-input gbe_mode ;
-input sgmii_mode ;
-input debug_link_timer_short ;
-input force_isolate ;
-input force_loopback ;
-input force_unidir ;
-input [1:0] operational_rate;
-output rx_compensation_err;
-output ctc_drop_flag;
-output ctc_add_flag;
-output an_link_ok;
-input [7:0] rx_data ;
-input rx_kcntl ;
-input rx_even ;
-input rx_disp_err ;
-input rx_cv_err ;
-input rx_err_decode_mode ;
-input [7:0] tx_d ;
-input tx_en ;
-input tx_er ;
-input [15:0] mr_adv_ability;
-input mr_an_enable;
-input mr_main_reset;
-input mr_restart_an;
-output mr_an_complete;
-output [15:0] mr_lp_adv_ability;
-output mr_page_rx;
-output [7:0] rx_d ;
-output rx_dv ;
-output rx_er ;
-output col ;
-output crs ;
-output [7:0] tx_data ;
-output tx_kcntl ;
-output tx_disparity_cntl ;
-output xmit_autoneg ;
-
-`ifdef SGMII_YES_ENC\r
-wire [7:0] yx754b7 ;
-wire lfaa5bc ;
-wire en5ec81 ;
-
-`endif\r
-wire [1:0] vif148d ;
-wire [15:0] uk97c52 ;
-wire [15:0] sjbe291 ;
-wire [15:0] mr_adv_ability ;
-wire [15:0] mr_lp_adv_ability ;
-wire db84fe1;
-wire [7:0] zkda3ae;
-wire ead1d72;
-wire rv8eb90;
-wire rx_compensation_err;
-wire wlae435;
-wire os721ac;
-wire mt90d61;
-wire ba86b0c;
-wire je35862;
-wire an_link_ok;
-reg jc4dbca;
-reg cm6de53;
-reg mr6f298;
-reg ne794c4;
-reg dmca622;
-reg go53113;
-reg xw76190 ;
-reg hdb0c83 ;
-reg hq8641f ;
-reg lf320fb ;
-reg oh907df ;
-reg vk83efd ;
-reg mg1f7ea ;
-wire [7:0] fafbf50;
-wire rgdfa82;
-wire yxfd413;
-wire [7:0] meea09c;
-wire pf504e0;
-wire co82707;
-wire xl13839;
-wire pu9c1cf;
-wire ctc_drop_flag;
-wire ctc_add_flag;
-reg oh39ec5;
-reg pscf62d;
-wire [7:0] bl7b16b;
-wire rtd8b5f;
-wire tuc5afe;
-reg db2d7f3;
-reg zx6bf9f;
-reg th5fcff;
-
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-reg nefe7ff;
-reg jpf3ffb;
-
-`endif\r
-parameter DYNAMIC_LT_10MBPS = 340;
-parameter DYNAMIC_HT_10MBPS = 680;
-parameter DYNAMIC_LT_100MBPS = 34;
-parameter DYNAMIC_HT_100MBPS = 68;
-parameter DYNAMIC_LT_1000MBPS = 16;
-parameter DYNAMIC_HT_1000MBPS = 32;
-parameter STATIC_LO_THRESH = 16;\r
-parameter STATIC_HI_THRESH = 32;\r
-parameter LINK_TIMER_SH = 21'h1fff01;\r
-
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-
-`endif\r
-
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-
-`else\r
-
-`endif\r
-
-`ifdef SGMII_YES_CTC_DYNAMIC\r
-
-`endif\r
-
-`ifdef SGMII_YES_CTC_STATIC\r
-
-`endif\r
-
-`ifdef SGMII_NO_CTC\r
-
-`endif\r
-
-`ifdef SGMII_YES_ENC\r
-
-`else\r
-
-`endif\r
-
-`ifdef SGMII_YES_ENC\r
-
-`else\r
-
-`endif\r
-reg rv22600;
-reg tuf124a;
-reg uv418e0;
-reg lf1c340;
-reg aa98036;
-reg and03a;
-reg vk89252;
-reg [1 : 0] tw42ab;
-reg [7 : 0] ho73b69;
-reg co9db4a;
-reg zk69421;
-reg kfa1f51;
-reg swfa8c;
-reg su7d460;
-reg [7 : 0] qgea300;
-reg rt50ee8;
-reg ou87746;
-reg xj4a480;
-reg qg49292;
-reg cm49490;
-reg [1 : 0] th4a10b;
-reg [15 : 0] tj22a0a;
-reg [15 : 0] qi15057;
-reg eneda50;
-reg [7 : 0] kd415cb;
-reg coae5c;
-reg vi572e0;
-reg ukb9702;
-reg gocb810;
-reg ay5c080;
-reg qge0401;
-reg ux2009;
-reg uv5ef91;
-reg wjf7c8d;
-reg uxbe46c;
-reg mrf2365;
-reg xl91b2d;
-reg ks8d96e;
-reg cm4c5d2;
-reg ui62e90;
-reg an17481;
-reg lfba40c;
-reg thd2067;
-reg gd9033e;
-reg lf819f5;
-reg [7 : 0] rvcfaf;
-reg os67d7f;
-reg co3ebf9;
-reg [7 : 0] suf5fc8;
-reg tjafe41;
-reg wj7f20f;
-reg dzf907d;
-reg dzc83ee;
-reg en41f76;
-reg ksfbb5;
-reg [7 : 0] go7dda8;
-reg dmeed41;
-reg xw76a0b;
-reg dbb505a;
-reg xya82d6;
-reg cz416b3;
-reg [2047:0] ls351cf;
-wire [60:0] jea8e7a;
-
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-
-`else\r
-
-`endif\r
-
-`ifdef SGMII_YES_ENC\r
-
-`endif\r
-
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-
-`endif\r
-
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-
-`endif\r
-
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-
-
-
-`else\r
-
-
-
-`endif\r
-
-`ifdef SGMII_YES_CTC_DYNAMIC\r
-
-
-`endif\r
-
-`ifdef SGMII_YES_CTC_STATIC\r
-
-
-`endif\r
-
-`ifdef SGMII_NO_CTC\r
-
-
-`endif\r
-
-`ifdef SGMII_YES_ENC\r
-
-`else\r
-
-`endif\r
-
-
-
-
-`ifdef SGMII_YES_ENC\r
-
-
-
-`else\r
-
-
-`endif\r
-
-localparam ps473d2 = 61,wl39e93 = 32'hfdffca8b;
-localparam [31:0] bycf49d = wl39e93;
-localparam xjd275d = wl39e93 & 4'hf;
-localparam [11:0] wy9d773 = 'h7ff;
-wire [(1 << xjd275d) -1:0] jc5dccb;
-reg [ps473d2-1:0] zk732d2;
-reg [xjd275d-1:0] cmcb49b [0:1];
-reg [xjd275d-1:0] xjd26ce;
-reg ls93676;
-integer vx9b3b2;
-integer ald9d96;
-
-
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-
-
-`else\r
-
-
-`endif\r
-
-
-`ifdef SGMII_YES_ENC\r
-
-
-`endif\r
-
-
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-
-
-`endif\r
-
-
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-
-
-`endif\r
-
-
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-
-
-`else\r
-
-
-`endif\r
-
-
-`ifdef SGMII_YES_CTC_DYNAMIC\r
-
-
-`endif\r
-
-
-`ifdef SGMII_YES_CTC_STATIC\r
-
-
-`endif\r
-
-
-`ifdef SGMII_NO_CTC\r
-
-
-`endif\r
-
-
-`ifdef SGMII_YES_ENC\r
-
-
-`else\r
-
-
-`endif\r
-
-
-`ifdef SGMII_YES_ENC\r
-
-
-`else\r
-
-
-`endif\r
-
-
-
-
-
-
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-
-
-
-`else\r
-
-
-
-`endif\r
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-`ifdef SGMII_YES_ENC\r
-
-
-
-`endif\r
-
-
-
-
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-
-
-
-`endif\r
-
-
-
-
-assign os721ac = ({zk69421, swfa8c, kfa1f51} == 3'b100) ? 1'b1 : 1'b0;
-assign mt90d61 = ({zk69421, swfa8c, kfa1f51} == 3'b111) ? 1'b1 : 1'b0;
-assign ba86b0c = gocb810 | ay5c080;
-
-assign je35862 = swfa8c | kfa1f51;
-
-assign db84fe1 = (su7d460) ? qge0401 : ux2009;
-
-
-
-
-
-
-
-
-
-
-
-
-always @(posedge tx_clk_125 or negedge rst_n)
-begin if (rst_n == 1'b0) begin db2d7f3 <= 1'b0; end else begin db2d7f3 <= ~dbb505a; end
-end
-always @(posedge rx_clk_125 or negedge rst_n)
-begin if (rst_n == 1'b0) begin zx6bf9f <= 1'b0; end else begin zx6bf9f <= ~xya82d6; end
-end
-always @(posedge serdes_recovered_clk or negedge rst_n)
-begin if (rst_n == 1'b0) begin th5fcff <= 1'b0; end else begin th5fcff <= ~cz416b3; end
-end
-
-`ifndef SGMII_YES_SINGLE_CLOCK\r
- always @(posedge tx_clk_mii or negedge rst_n) begin if (rst_n == 1'b0) begin nefe7ff <= 1'b0; end else begin nefe7ff <= ~nefe7ff; end end always @(posedge rx_clk_mii or negedge rst_n) begin if (rst_n == 1'b0) begin jpf3ffb <= 1'b0; end else begin jpf3ffb <= ~jpf3ffb; end end
-
-
-`endif\r
-
-
-
-
-
-
-
-
-
-
-`ifdef SGMII_YES_SINGLE_CLOCK\r
- dm4d132 vk839b5 ( .rst_n ( rst_n ) , .gbe_mode ( rv22600 ) , .yz26485 ( tx_clk_125 ) , .db3242c ( tx_clock_enable_sink ) , .thcda6d ( tx_clock_enable_source ) , .zz38960 ( tw42ab ) , .force_isolate ( aa98036 ) , .zz38f51 ( qgea300 ) , .blc7a8f ( ou87746 ) , .lf3d47e ( rt50ee8 ) , .of51fb0 ( fafbf50 ) , .sj8fd84 ( rgdfa82 ) , .vv7ec24 ( yxfd413 ) ); vv55b56 uk34e71 ( .rst_n ( rst_n ) , .gbe_mode ( rv22600 ) , .force_isolate ( aa98036 ) , .yz26485 ( rx_clk_125 ) , .db3242c ( rx_clock_enable_sink ) , .thcda6d ( rx_clock_enable_source ) , .zz38960 ( tw42ab ) , .zz38f51 ( suf5fc8 ) , .blc7a8f ( tjafe41 ) , .lf3d47e ( wj7f20f ) , .do20bc9 ( dzf907d ) , .ou5e4a ( dzc83ee ) , .of51fb0 ( rx_d ) , .sj8fd84 ( rx_er ) , .vv7ec24 ( rx_dv ), .yz8a53d ( col ) , .tu529ed ( crs ) );
-
-`else\r
- nr553d0 vk839b5 ( .rst_n ( rst_n ) , .gbe_mode ( rv22600 ) , .al7a1c7 ( tx_clk_mii ) , .hod0e3d ( tw42ab ) , .force_isolate ( aa98036 ) , .zz38f51 ( qgea300 ) , .blc7a8f ( ou87746 ) , .lf3d47e ( rt50ee8 ) , .meea3f6 ( tx_clk_125 ) , .of51fb0 ( fafbf50 ) , .sj8fd84 ( rgdfa82 ) , .vv7ec24 ( yxfd413 ) ); uie0f07 uk34e71 ( .rst_n ( rst_n ) , .gbe_mode ( rv22600 ) , .force_isolate ( aa98036 ) , .al7a1c7 ( rx_clk_125 ) , .zz38f51 ( suf5fc8 ) , .blc7a8f ( tjafe41 ) , .lf3d47e ( wj7f20f ) , .do20bc9 ( dzf907d ) , .ou5e4a ( dzc83ee ) , .meea3f6 ( rx_clk_mii ) , .vi7928a ( tw42ab ) , .of51fb0 ( rx_d ) , .sj8fd84 ( rx_er ) , .vv7ec24 ( rx_dv ), .yz8a53d ( col ) , .tu529ed ( crs ) );
-
-`endif\r
-
-
-
-
-
-`ifdef SGMII_YES_CTC_DYNAMIC\r
- ba1bf62 # (.DYNAMIC_HT_1000MBPS(DYNAMIC_HT_1000MBPS), .DYNAMIC_LT_1000MBPS(DYNAMIC_LT_1000MBPS), .DYNAMIC_HT_100MBPS (DYNAMIC_HT_100MBPS), .DYNAMIC_LT_100MBPS (DYNAMIC_LT_100MBPS), .DYNAMIC_HT_10MBPS (DYNAMIC_HT_10MBPS), .DYNAMIC_LT_10MBPS (DYNAMIC_LT_10MBPS)) by6ca4a ( .rst_n (rst_n), .mr_main_reset (lf819f5), .an_link_ok (an_link_ok), .ic626ef (xj4a480), .gbe_mode (rv22600), .operational_rate (tw42ab), .lddde37 (serdes_recovered_clk), .wwef1be (ho73b69), .os78df0 (co9db4a), .qtc6f81 (eneda50), .bn37c0c (rx_clk_125), .irbe066 (zkda3ae), .suf0335 (ead1d72), .ph819a8 (rv8eb90), .xlcd47 (rx_compensation_err), .ctc_drop_flag (ctc_drop_flag), .ctc_add_flag (ctc_add_flag) );
-
-`endif\r
-
-
-
-`ifdef SGMII_YES_CTC_STATIC\r
- mtb4bc4 # (.STATIC_HI_THRESH(STATIC_HI_THRESH), .STATIC_LO_THRESH(STATIC_LO_THRESH)) by6ca4a ( .rst_n (rst_n), .mr_main_reset (lf819f5), .lddde37 (serdes_recovered_clk), .wwef1be (ho73b69), .os78df0 (co9db4a), .qtc6f81 (eneda50), .bn37c0c (rx_clk_125), .irbe066 (zkda3ae), .suf0335 (ead1d72), .ph819a8 (rv8eb90), .xlcd47 (rx_compensation_err), .ctc_drop_flag (ctc_drop_flag), .ctc_add_flag (ctc_add_flag) );
-
-`endif\r
-
-
-
-`ifdef SGMII_NO_CTC\r
- mtbbc32 by6ca4a ( .rst_n (rst_n), .mr_main_reset (lf819f5), .lddde37 (serdes_recovered_clk), .wwef1be (ho73b69), .os78df0 (co9db4a), .qtc6f81 (eneda50), .bn37c0c (rx_clk_125), .irbe066 (zkda3ae), .suf0335 (ead1d72), .ph819a8 (rv8eb90), .xlcd47 (rx_compensation_err) );
-assign ctc_drop_flag = 1'b0;
-assign ctc_add_flag = 1'b0;
-
-`endif\r
-
-
-
-
-
-
-
-always @(posedge rx_clk_125 or negedge rst_n)
-begin if (rst_n == 1'b0) begin oh39ec5 <= 1'b0; pscf62d <= 1'b0; end else begin oh39ec5 <= and03a; pscf62d <= en41f76; end
-end
-
-
-`ifdef SGMII_YES_ENC\r
- assign bl7b16b = ksfbb5 ? yx754b7 : kd415cb; assign rtd8b5f = ksfbb5 ? lfaa5bc : coae5c; assign tuc5afe = ksfbb5 ? 1'b0 : vi572e0;
-
-`else\r
- assign bl7b16b = ksfbb5 ? tx_data : kd415cb; assign rtd8b5f = ksfbb5 ? tx_kcntl : coae5c; assign tuc5afe = ksfbb5 ? 1'b0 : vi572e0;
-
-`endif\r
-
-
-
-
-
-gb51bec gb51bec ( .ri2ab2d ( rx_clk_125 ) , .rst_n ( rst_n ) , .mr_main_reset ( lf819f5 ) , .signal_detect ( uv418e0 ) , .rx_data ( go7dda8 ) , .rx_kcntl ( dmeed41 ) , .db84fe1 ( xw76a0b ) , .bld2597 ( bld2597 ) , .rx_even ( wlae435 ) );
-
-
-
-
-
-
-gb65565 gb65565 ( .ri2ab2d ( rx_clk_125 ) , .rst_n ( rst_n ) , .mr_main_reset ( lf819f5 ) , .sgmii_mode ( tuf124a ) , .gbe_mode ( rv22600 ) , .jp6bc27 ( mr_adv_ability[12] ) , .rx_data ( go7dda8 ) , .rx_kcntl ( dmeed41 ) , .db84fe1 ( xw76a0b ) , .bld2597 ( bld2597 ) , .rx_even ( ukb9702 ) , .vif148d ( th4a10b ) , .uk97c52( uk97c52 ) , .cofeb2 ( cofeb2 ) , .wj7f590 ( wj7f590 ) , .ayfac85 ( ayfac85 ) , .end6428 ( meea09c ) , .pub2144 ( co82707 ) , .ux90a23 ( pf504e0 ) );
-
-
-
-
- ldf627d # (.LINK_TIMER_SH(LINK_TIMER_SH)) ldf627d ( .yz26485 ( tx_clk_125 ) , .rst_n ( rst_n ) , .gbe_mode ( rv22600 ) , .sgmii_mode ( tuf124a ) , .force_unidir ( vk89252 ) , .mr_main_reset ( lf819f5 ) , .mr_restart_an ( cm49490 ) , .mr_an_enable ( xj4a480 ) , .mr_adv_ability ( mr_adv_ability ) , .mr_lp_adv_ability ( mr_lp_adv_ability ) , .mr_page_rx ( mr_page_rx ) , .mr_an_complete ( mr_an_complete ) , .nr4ae92 ( lf1c340 ) , .bld2597 ( bld2597 ) , .qi92cbe ( ayfac85 ) , .ls965f1 ( wj7f590 ) , .twb2f8a ( cofeb2 ) , .uk97c52 ( tj22a0a ) , .sjbe291 ( sjbe291 ) , .vif148d ( vif148d ), .an_link_ok ( an_link_ok ) );
-
-
-`ifdef SGMII_YES_ENC\r
- th4f530 th4f530 ( .yz26485 ( tx_clk_125 ) , .rst_n ( rst_n ) , .mr_main_reset ( lf819f5 ), .force_unidir ( vk89252 ), .an3c018 ( rvcfaf ) , .tx_en ( co3ebf9 ) , .tx_er ( os67d7f ) , .vif148d ( th4a10b ) , .sjbe291 ( qi15057 ) , .ux18847 ( yx754b7 ) , .qgc423c ( lfaa5bc ), .ym211e0 ( en5ec81 ) );
- mt8230 mt8230 ( .yz26485 (tx_clk_125), .rst_n (rst_n), .qgc423c (lfaa5bc), .fc30929 (yx754b7), .tj8494b (1'b0), .aa24a5f (1'b0), .ri252f8 (1'b0), .cb297c3 (1'b1), .ym211e0 (en5ec81), .fn5f0ec ({tx_disparity_cntl, tx_kcntl, tx_data}) );
-
-`else\r
- th4f530 th4f530 ( .yz26485 ( tx_clk_125 ) , .rst_n ( rst_n ) , .mr_main_reset ( lf819f5 ), .force_unidir ( vk89252 ), .an3c018 ( rvcfaf ) , .tx_en ( co3ebf9 ) , .tx_er ( os67d7f ) , .vif148d ( th4a10b ) , .sjbe291 ( qi15057 ) , .ux18847 ( tx_data ) , .qgc423c ( tx_kcntl ), .ym211e0 ( tx_disparity_cntl ) );
-
-`endif\r
-
-
-
-
-
-assign xl13839 = rx_dv & rt50ee8;
-assign pu9c1cf = rx_dv;
-assign xmit_autoneg = ((th4a10b==2'b01)||(th4a10b==2'b00)) ? 1'b1 : 1'b0;
-
-
-always @(posedge tx_clk_125 or negedge rst_n)
-begin if (rst_n == 1'b0) begin jc4dbca <= 1'b0; cm6de53 <= 1'b0; mr6f298 <= 1'b0; ne794c4 <= 1'b0; dmca622 <= 1'b0; go53113 <= 1'b0; xw76190 <= 1'b1; hdb0c83 <= 1'b1; hq8641f <= 1'b1; lf320fb <= 1'b1; oh907df <= 1'b1; vk83efd <= 1'b1; mg1f7ea <= 1'b1; end else begin jc4dbca <= rv22600; cm6de53 <= uv5ef91; xw76190 <= qg49292; hdb0c83 <= cm4c5d2; mr6f298 <= wjf7c8d; ne794c4 <= wjf7c8d & (~uxbe46c); dmca622 <= ~wjf7c8d & (uxbe46c); go53113 <= mrf2365 || xl91b2d; hq8641f <= ui62e90 | ks8d96e; lf320fb <= an17481; oh907df <= lfba40c; vk83efd <= thd2067; mg1f7ea <= an17481 | lfba40c | thd2067 | gd9033e; end
-end
-
-
-
-always@* begin rv22600<=jea8e7a[0];tuf124a<=jea8e7a[1];uv418e0<=jea8e7a[2];lf1c340<=jea8e7a[3];aa98036<=jea8e7a[4];and03a<=jea8e7a[5];vk89252<=jea8e7a[6];tw42ab<={operational_rate>>1,jea8e7a[7]};ho73b69<={rx_data>>1,jea8e7a[8]};co9db4a<=jea8e7a[9];zk69421<=jea8e7a[10];kfa1f51<=jea8e7a[11];swfa8c<=jea8e7a[12];su7d460<=jea8e7a[13];qgea300<={tx_d>>1,jea8e7a[14]};rt50ee8<=jea8e7a[15];ou87746<=jea8e7a[16];xj4a480<=jea8e7a[17];qg49292<=jea8e7a[18];cm49490<=jea8e7a[19];th4a10b<={vif148d>>1,jea8e7a[20]};tj22a0a<={uk97c52>>1,jea8e7a[21]};qi15057<={sjbe291>>1,jea8e7a[22]};eneda50<=jea8e7a[23];kd415cb<={zkda3ae>>1,jea8e7a[24]};coae5c<=jea8e7a[25];vi572e0<=jea8e7a[26];ukb9702<=jea8e7a[27];gocb810<=jea8e7a[28];ay5c080<=jea8e7a[29];qge0401<=jea8e7a[30];ux2009<=jea8e7a[31];uv5ef91<=jea8e7a[32];wjf7c8d<=jea8e7a[33];uxbe46c<=jea8e7a[34];mrf2365<=jea8e7a[35];xl91b2d<=jea8e7a[36];ks8d96e<=jea8e7a[37];cm4c5d2<=jea8e7a[38];ui62e90<=jea8e7a[39];an17481<=jea8e7a[40];lfba40c<=jea8e7a[41];thd2067<=jea8e7a[42];gd9033e<=jea8e7a[43];lf819f5<=jea8e7a[44];rvcfaf<={fafbf50>>1,jea8e7a[45]};os67d7f<=jea8e7a[46];co3ebf9<=jea8e7a[47];suf5fc8<={meea09c>>1,jea8e7a[48]};tjafe41<=jea8e7a[49];wj7f20f<=jea8e7a[50];dzf907d<=jea8e7a[51];dzc83ee<=jea8e7a[52];en41f76<=jea8e7a[53];ksfbb5<=jea8e7a[54];go7dda8<={bl7b16b>>1,jea8e7a[55]};dmeed41<=jea8e7a[56];xw76a0b<=jea8e7a[57];dbb505a<=jea8e7a[58];xya82d6<=jea8e7a[59];cz416b3<=jea8e7a[60];end
-always@* begin ls351cf[2047]<=sgmii_mode;ls351cf[2046]<=signal_detect;ls351cf[2044]<=debug_link_timer_short;ls351cf[2040]<=force_isolate;ls351cf[2032]<=force_loopback;ls351cf[2017]<=force_unidir;ls351cf[1987]<=operational_rate[0];ls351cf[1926]<=rx_data[0];ls351cf[1805]<=ne794c4;ls351cf[1804]<=rx_kcntl;ls351cf[1803]<=db84fe1;ls351cf[1761]<=jc4dbca;ls351cf[1668]<=oh907df;ls351cf[1562]<=dmca622;ls351cf[1560]<=rx_even;ls351cf[1558]<=zkda3ae[0];ls351cf[1550]<=tx_er;ls351cf[1475]<=cm6de53;ls351cf[1464]<=ba86b0c;ls351cf[1288]<=vk83efd;ls351cf[1242]<=db2d7f3;ls351cf[1076]<=go53113;ls351cf[1072]<=rx_disp_err;ls351cf[1069]<=ead1d72;ls351cf[1056]<=fafbf50[0];ls351cf[1052]<=mr_an_enable;ls351cf[1028]<=co82707;ls351cf[1023]<=gbe_mode;ls351cf[902]<=mr6f298;ls351cf[901]<=sjbe291[0];ls351cf[880]<=je35862;ls351cf[874]<=th5fcff;ls351cf[834]<=lf320fb;ls351cf[775]<=tx_en;ls351cf[732]<=mt90d61;ls351cf[621]<=tuc5afe;ls351cf[528]<=mg1f7ea;ls351cf[514]<=pf504e0;ls351cf[450]<=uk97c52[0];ls351cf[437]<=zx6bf9f;ls351cf[417]<=hq8641f;ls351cf[387]<=tx_d[0];ls351cf[366]<=os721ac;ls351cf[310]<=rtd8b5f;ls351cf[257]<=meea09c[0];ls351cf[225]<=vif148d[0];ls351cf[208]<=hdb0c83;ls351cf[193]<=rx_err_decode_mode;ls351cf[183]<=wlae435;ls351cf[155]<=bl7b16b[0];ls351cf[128]<=yxfd413;ls351cf[112]<=mr_restart_an;ls351cf[104]<=xw76190;ls351cf[96]<=rx_cv_err;ls351cf[91]<=rv8eb90;ls351cf[77]<=pscf62d;ls351cf[64]<=rgdfa82;ls351cf[56]<=mr_main_reset;ls351cf[38]<=oh39ec5;ls351cf[19]<=pu9c1cf;ls351cf[9]<=xl13839;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96<ps473d2; ald9d96=ald9d96+1) begin zk732d2[ald9d96] = jc5dccb[xjd26ce]; ls93676 = ^(xjd26ce & cmcb49b[0]); xjd26ce = {xjd26ce, ls93676}; end end
-endmodule
-
-
+++ /dev/null
-=============================================================================
-Filelist generated by IPexpress 10/04/2011 13:50:21
-Filename: sgmii_gbe_pcs34_filelist.log
-Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-=============================================================================
-
------------------------------------------------------------------------------
-Basic IP Core Files
-Output Directory: /home/greg/projects/trb3/trb3_gbe/ipcores
------------------------------------------------------------------------------
- sgmii_gbe_pcs34.lpc
- : IP ispLEVER LPC File
- sgmii_gbe_pcs34.ngo
- : IP ispLEVER Database File
- sgmii_gbe_pcs34_bb.v
- : IP Verilog Blackbox Module
- sgmii_gbe_pcs34_inst.v
- : IP Verilog Instantiation Template
- sgmii_gbe_pcs34_beh.v
- : IP Verilog Behaviorial Sim Model
- sgmii_gbe_pcs34_gen.log
- : IP Status Log
- sgmii_gbe_pcs34_generate.log
- : IP Generate Log
-
------------------------------------------------------------------------------
-Supplemental Evaluation Files:
------------------------------------------------------------------------------
-
----------------------------------:
- COMMON TO ALL CONFIGURATIONS :
----------------------------------:
-
- Hardware Specific Models
- ../sgmii_pcs_eval/models/ecp3/pcs_serdes
-
- Testbench
- ../sgmii_pcs_eval/testbench
-
-------------------------------------------------
- SPECIFIC TO sgmii_gbe_pcs34 CONFIGURATION
-------------------------------------------------
-
- Source Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs34/src/rtl/ecp3
-
- Simulation
- ../sgmii_pcs_eval/sgmii_gbe_pcs34/sim/modelsim
-
- FPGA Implementation Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs34/impl
-
+++ /dev/null
-Parameters loaded ok.
-No optional files required.
-Running parameter check.
-Parameter values ok.
-IP core generation completed ok.
-Simulation model successfully created.
-IP template generation completed ok.
-Eval Directory succussfully created.
-ModelSim do file successfully created.
-Generation completed ok.
+++ /dev/null
-Starting process: IPCFG
-
-GenerateCore within package Core_Generate 1.0.0 in file LatticeIP_generate.tcl
-Starting process: '"/opt/lattice/diamond/1.3/bin/lin/synpwrap" -rem -e sgmii_gbe_pcs34 -target lattice-ecp3'
-
-Warning: You are running on an unsupported platform
-End process: completed successfully.
-
-Starting process: '"/opt/lattice/diamond/1.3/bin/lin/../../ispfpga/bin/lin/edif2ngd" -ip "/home/greg/sgmii_gbepcs_v3.4/lib/../.." -ic sgmii_gbepcs_v3.4 -l LatticeECP3 -nopropwarn "syn_results/sgmii_gbe_pcs34.edi" "sgmii_gbe_pcs34.ngo"'
-edif2ngd: version Diamond_1.3_Production (92)
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
- Copyright (c) 1995 AT&T Corp. All rights reserved.
- Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
- Copyright (c) 2001 Agere Systems All rights reserved.
- Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-No device specified. Will use default.
-Writing the design to sgmii_gbe_pcs34.ngo...
-End process: completed successfully.
-
-=============================================================================
-Filelist generated by IPexpress 10/04/2011 13:50:21
-Filename: sgmii_gbe_pcs34_filelist.log
-Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-=============================================================================
------------------------------------------------------------------------------
-Basic IP Core Files
-Output Directory: /home/greg/projects/trb3/trb3_gbe/ipcores
------------------------------------------------------------------------------
- sgmii_gbe_pcs34.lpc
- : IP ispLEVER LPC File
- sgmii_gbe_pcs34.ngo
- : IP ispLEVER Database File
- sgmii_gbe_pcs34_bb.v
- : IP Verilog Blackbox Module
- sgmii_gbe_pcs34_inst.v
- : IP Verilog Instantiation Template
- sgmii_gbe_pcs34_beh.v
- : IP Verilog Behaviorial Sim Model
- sgmii_gbe_pcs34_gen.log
- : IP Status Log
- sgmii_gbe_pcs34_generate.log
- : IP Generate Log
------------------------------------------------------------------------------
-Supplemental Evaluation Files:
------------------------------------------------------------------------------
-
----------------------------------:
- COMMON TO ALL CONFIGURATIONS :
----------------------------------:
-
- Hardware Specific Models
- ../sgmii_pcs_eval/models/ecp3/pcs_serdes
-
- Testbench
- ../sgmii_pcs_eval/testbench
-
-------------------------------------------------
- SPECIFIC TO sgmii_gbe_pcs34 CONFIGURATION
-------------------------------------------------
-
- Source Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs34/src/rtl/ecp3
-
- Simulation
- ../sgmii_pcs_eval/sgmii_gbe_pcs34/sim/modelsim
-
- FPGA Implementation Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs34/impl
-
-Total Warnings: 1
-
-
-Total Errors: 0
-
-
-
+++ /dev/null
-//=============================================================================
-// Verilog module generated by IPExpress 10/04/2011 13:50:20
-// Filename: sgmii_gbe_pcs34_inst.v
-// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-//=============================================================================
-
-/* WARNING - Changes to this file should be performed by re-running IPexpress
-or modifying the .LPC file and regenerating the core. Other changes may lead
-to inconsistent simulation and/or implemenation results */
-
-//---------------------------------------------------------------
-// sgmii_gbe_pcs34 module instantiation template
-//---------------------------------------------------------------
-
-
- \r
-\r
-sgmii_gbe_pcs34 sgmii_gbe_pcs34_U (\r
-\r
- // Control Interface\r
- .rst_n ( rst_n ) ,\r
- .signal_detect ( signal_detect ) ,\r
- .gbe_mode ( gbe_mode ) ,\r
- .sgmii_mode ( sgmii_mode ) ,\r
- .operational_rate ( operational_rate ) ,\r
- .debug_link_timer_short ( debug_link_timer_short ) ,\r
- .force_isolate ( force_isolate ) ,\r
- .force_loopback ( force_loopback ) ,\r
- .force_unidir ( force_unidir ) ,\r
-\r
- .rx_compensation_err ( rx_compensation_err ) ,\r
- .ctc_drop_flag ( ctc_drop_flag ) ,\r
- .ctc_add_flag ( ctc_add_flag ) ,\r
- .an_link_ok ( an_link_ok ) ,\r
-\r
- // (G)MII Interface\r
- .tx_clock_enable_sink ( tx_clock_enable_sink ),\r
- .tx_clock_enable_source ( tx_clock_enable_source ),\r
- .tx_clk_125 ( tx_clk_125 ) ,\r
- .tx_d ( tx_d ) ,\r
- .tx_en ( tx_en ) ,\r
- .tx_er ( tx_er ) ,\r
-\r
- .rx_clock_enable_sink ( rx_clock_enable_sink ),\r
- .rx_clock_enable_source ( rx_clock_enable_source ),\r
- .rx_clk_125 ( rx_clk_125 ) ,\r
- .rx_d ( rx_d ) ,\r
- .rx_dv ( rx_dv ) ,\r
- .rx_er ( rx_er ) ,\r
- .col ( col ) ,\r
- .crs ( crs ) ,\r
- \r
- // 8BI Interface\r
- .tx_data ( tx_data ) ,\r
- .tx_kcntl ( tx_kcntl ) ,\r
- .tx_disparity_cntl ( tx_disparity_cntl ) ,\r
- .xmit_autoneg ( xmit_autoneg ) ,\r
-\r
- .serdes_recovered_clk ( serdes_recovered_clk ) ,\r
- .rx_data ( rx_data ) ,\r
- .rx_kcntl ( rx_kcntl) ,\r
- .rx_even ( rx_even ) ,\r
- .rx_disp_err ( rx_disp_err ) ,\r
- .rx_cv_err ( rx_cv_err ) ,\r
- .rx_err_decode_mode ( rx_err_decode_mode ) ,\r
-\r
- // Management Interface\r
- .mr_adv_ability ( mr_adv_ability ),\r
- .mr_an_enable ( mr_an_enable ), \r
- .mr_main_reset ( mr_main_reset ), \r
- .mr_restart_an ( mr_restart_an ), \r
-\r
- .mr_an_complete ( mr_an_complete ), \r
- .mr_lp_adv_ability ( mr_lp_adv_ability ), \r
- .mr_page_rx ( mr_page_rx )\r
- );\r
- \r
-);\r
-\r
+++ /dev/null
-
-#!/usr/local/bin/wish
-
-set Para(cmd) ""
-if ![catch {set temp $argc} result] {
- if {$argc > 0} {
- for {set i 0} {$i < $argc} {incr i 2} {
- set temp [lindex $argv $i]
- set temp [string range $temp 1 end]
- lappend argv_list $temp
- lappend value_list [lindex $argv [expr $i+1]]
- }
- foreach argument $argv_list value $value_list {
- switch $argument {
- "cmd" {set Para(cmd) $value;}
- }
- }
- }
-}
-
-set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35"
-set Para(ModuleName) "sgmii_gbe_pcs35"
-set Para(lib) "/home/greg/sgmii_gbepcs_v3.5/lib"
-set Para(CoreName) "SGMII/Gb Ethernet PCS"
-set Para(arch) "ep5c00"
-set Para(family) "latticeecp3"
-set Para(Family) "latticeecp3"
-set Para(design) "VHDL"
-set Para(install_dir) "/opt/lattice/diamond/1.4.2.105/bin/lin/../.."
-set Para(Bin) "/opt/lattice/diamond/1.4.2.105/bin/lin"
-set Para(SpeedGrade) "Para(spd)"
-set Para(FPGAPath) "/opt/lattice/diamond/1.4.2.105/bin/lin/../../ispfpga/bin/sol"
-
-lappend auto_path "/home/greg/sgmii_gbepcs_v3.5/gui"
-
-lappend auto_path "/home/greg/sgmii_gbepcs_v3.5/script"
-package require Core_Generate
-
-lappend auto_path "/opt/lattice/diamond/1.4.2.105/tcltk/lib/ipwidgets/ispipbuilder/../runproc"
-package require runcmd
-
-
-set Para(result) [GenerateCore]
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="sgmii_gbe_pcs35" module="SGMII/Gb Ethernet PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 06 19 09:57:33.085" version="3.5" type="IP" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="sgmii_gbe_pcs35.lpc" type="lpc" modified="2012 06 19 09:57:17.000"/>
- <File name="sgmii_gbe_pcs35.ngo" type="database" modified="2012 06 19 09:57:29.000"/>
- <File name="sgmii_gbe_pcs35_bb.v" type="black_box_verilog" modified="2012 06 19 09:57:30.000"/>
- <File name="sgmii_gbe_pcs35_beh.v" type="behavioral_verilog" modified="2012 06 19 09:57:30.000"/>
- <File name="sgmii_gbe_pcs35_inst.v" type="instantiation_verilog" modified="2012 06 19 09:57:30.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=ep5c00
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=IPCFG
-CoreStatus=Demo
-CoreName=SGMII/Gb Ethernet PCS
-CoreRevision=3.5
-ModuleName=sgmii_gbe_pcs35
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=06/19/2012
-Time=09:57:17
-
-[Parameters]
-RX_CTC=2
-RX_CTC_LOW=16
-RX_CTC_HIGH=32
-EasyConnect=1
+++ /dev/null
-//=============================================================================
-// Verilog module generated by IPExpress 06/19/2012 09:57:30
-// Filename: sgmii_gbe_pcs35_bb.v
-// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-//=============================================================================
-
-//---------------------------------------------------------------
-// sgmii_gbe_pcs35 synthesis black box definition
-//---------------------------------------------------------------
-
-/* WARNING - Changes to this file should be performed by re-running IPexpress
-or modifying the .LPC file and regenerating the core. Other changes may lead
-to inconsistent simulation and/or implemenation results */
-
-
-
- \r
-\r
-\r
-module sgmii_gbe_pcs35 (\r
- // Control Interface\r
- rst_n,\r
- signal_detect,\r
- gbe_mode,\r
- sgmii_mode,\r
- operational_rate,\r
- debug_link_timer_short,\r
- force_isolate,\r
- force_loopback,\r
- force_unidir,\r
-\r
- rx_compensation_err,\r
- ctc_drop_flag,\r
- ctc_add_flag,\r
- an_link_ok,\r
- \r
- // G/MII Interface\r
- tx_clock_enable_sink ,\r
- tx_clock_enable_source ,\r
- tx_clk_125,\r
- tx_d,\r
- tx_en,\r
- tx_er,\r
-\r
- rx_clock_enable_sink ,\r
- rx_clock_enable_source ,\r
- rx_clk_125,\r
- rx_d,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
-\r
- // 8-bit Interface\r
- tx_data,\r
- tx_kcntl,\r
- tx_disparity_cntl,\r
- xmit_autoneg,\r
-\r
- serdes_recovered_clk,\r
- rx_data,\r
- rx_kcntl,\r
- rx_even ,\r
- rx_disp_err ,\r
- rx_cv_err ,\r
- rx_err_decode_mode ,\r
- \r
- // Managment Control Outputs\r
- mr_an_complete,\r
- mr_page_rx,\r
- mr_lp_adv_ability,\r
-\r
- // Managment Control Inputs\r
- mr_main_reset,\r
- mr_an_enable,\r
- mr_restart_an,\r
- mr_adv_ability\r
- );\r
-\r
-\r
-\r
-// Control Interface\r
-input rst_n ;\r
-input signal_detect ;\r
-input gbe_mode ;\r
-input sgmii_mode ;\r
-input [1:0] operational_rate ;\r
-input debug_link_timer_short ;\r
-input force_isolate ;\r
-input force_loopback ;\r
-input force_unidir ;\r
-\r
-output rx_compensation_err ;\r
-output ctc_drop_flag ;\r
-output ctc_add_flag ;\r
-output an_link_ok ;\r
-\r
-// G/MII Interface\r
-input tx_clock_enable_sink;\r
-output tx_clock_enable_source;\r
-input tx_clk_125 ;\r
-input [7:0] tx_d ;\r
-input tx_en ;\r
-input tx_er ;\r
-\r
-input rx_clock_enable_sink;\r
-output rx_clock_enable_source;\r
-input rx_clk_125 ;\r
-output [7:0] rx_d ;\r
-output rx_dv ;\r
-output rx_er ;\r
-output col ;\r
-output crs ;\r
-\r
-// 8-bit Interface\r
-output [7:0] tx_data ;\r
-output tx_kcntl;\r
-output tx_disparity_cntl;\r
-output xmit_autoneg;\r
-\r
-input serdes_recovered_clk ;\r
-input [7:0] rx_data ;\r
-input rx_even ;\r
-input rx_kcntl;\r
-input rx_disp_err ;\r
-input rx_cv_err ;\r
-input rx_err_decode_mode ;\r
-\r
-// Managment Control Outputs\r
-output mr_an_complete;\r
-output mr_page_rx;\r
-output [15:0] mr_lp_adv_ability;\r
-\r
-// Managment Control Inputs\r
-input mr_main_reset;\r
-input mr_an_enable;\r
-input mr_restart_an;\r
-input [15:0] mr_adv_ability;\r
-\r
-\r
-\r
-endmodule\r
-\r
+++ /dev/null
-// sgmii_pcs_core_beh_pp.v generated by Lattice IP Model Creator version 1\r
-// created on Fri Mar 23 11:01:38 CST 2012\r
-// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved\r
-// obfuscator_exe version 1.mar0807\r
-// top\r
-`define SGMII_NO_ENC\r
-`define SGMII_YES_CTC_DYNAMIC\r
-`define SGMII_FIFO_FAMILY_ECP3\r
-`define SGMII_YES_SINGLE_CLOCK\r
-`timescale 1 ns / 100 ps\r
-module vi7cf1f (uve78fb, an3c7dd, fne3eec, ie1f767, zkfbb38, xjdd9c2,\r
- rtece16, ay670b6, tj385b0, blc2d86, lf16c36, wyb61b7, zzb0db9,\r
- vk86dcf);\r
-input [17:0] uve78fb;\r
-input an3c7dd;\r
-input fne3eec;\r
-input ie1f767;\r
-input zkfbb38;\r
-input xjdd9c2;\r
-input rtece16;\r
-input [9:0] ay670b6;\r
-input [9:0] tj385b0;\r
-output [17:0] blc2d86;\r
-output lf16c36;\r
-output wyb61b7;\r
-output zzb0db9;\r
-output vk86dcf;\r
-reg [17 : 0] icc175e;\r
-reg ngbaf0;\r
-reg fa5d782;\r
-reg faebc13;\r
-reg of5e09b;\r
-reg uif04dc;\r
-reg co826e0;\r
-reg [9 : 0] xl13701;\r
-reg [9 : 0] nt9b80e;\r
-reg [2047:0] shdc077;\r
-wire [8:0] eae03bd;\r
-localparam ba1de9 = 9,ngef4b = 32'hfdffc68b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-AND2 gq98434 (.A(ie1f767), .B(uk10d0f), .Z(ng86878)); INV aa343c2 (.A(ana1e10), .Z(uk10d0f)); AND2 go78421 (.A(zkfbb38), .B(mg10847), .Z(db84238)); INV ym211c6 (.A(gd8e31), .Z(mg10847)); OR2 vx38c6b (.A(xjdd9c2), .B(rtece16), .Z(ou8d7e9)); XOR2 pf6bf48 (.A(rt5fa47), .B(yxfd23f), .Z(pfe91fc)); XOR2 ps48fe7 (.A(yxfd23f), .B(tw3f9da), .Z(blfced2)); XOR2 qte7697 (.A(tw3f9da), .B(psda5e1), .Z(fnd2f0a)); XOR2 aa97857 (.A(psda5e1), .B(vie15c8), .Z(gqae43)); XOR2 by57218 (.A(vie15c8), .B(dzc8610), .Z(cm43086)); XOR2 wl18431 (.A(dzc8610), .B(ec10c6f), .Z(pu86378)); XOR2 uk31bc3 (.A(ec10c6f), .B(gb6f0c9), .Z(qg7864c)); XOR2 czc3260 (.A(gb6f0c9), .B(uvc982f), .Z(me4c17d)); XOR2 yx60be8 (.A(uvc982f), .B(fc2fa21), .Z(me7d10b)); XOR2 wje8858 (.A(fc2fa21), .B(ym21624), .Z(fcb121)); XOR2 xw5890b (.A(osc485a), .B(mg242d1), .Z(mg21689)); XOR2 ngb449 (.A(mg242d1), .B(wwd125e), .Z(hq892f1)); XOR2 ic4978a (.A(wwd125e), .B(uv5e284), .Z(rgf1424)); XOR2 gd8a122 (.A(uv5e284), .B(ph848ae), .Z(uk24577)); XOR2 bn22bb9 (.A(ph848ae), .B(anaee78), .Z(yk773c5)); XOR2 mgb9e29 (.A(anaee78), .B(ay78a4b), .Z(hoc5259)); XOR2 gd292ca (.A(ay78a4b), .B(kd4b2a8), .Z(kq59545)); XOR2 tucaa29 (.A(kd4b2a8), .B(lsa8a57), .Z(hb452ba)); XOR2 gd295d6 (.A(lsa8a57), .B(ho575ae), .Z(phbad72)); XOR2 uvd6b96 (.A(ho575ae), .B(anae5af), .Z(ui72d7c)); defparam do96be0.initval = 16'h6996 ; ROM16X1 do96be0 (.AD3(fpaf81f), .AD2(ne7c0ff), .AD1(cme07fa), .AD0(nt3fd1), .DO0(aa1fe8e)) ; defparam qgff471.initval = 16'h6996 ; ROM16X1 qgff471 (.AD3(med1c49), .AD2(db8e248), .AD1(jp71247), .AD0(tw8923e), .DO0(ay491f2)) ; defparam fa48f90.initval = 16'h6996 ; ROM16X1 fa48f90 (.AD3(cme07fa), .AD2(nt3fd1), .AD1(oh9068d), .AD0(oh9068d), .DO0(qi1a36b)) ; defparam kqd1b58.initval = 16'h6996 ; ROM16X1 kqd1b58 (.AD3(ne7c0ff), .AD2(cme07fa), .AD1(nt3fd1), .AD0(oh9068d), .DO0(ba139a)) ; defparam lf9cd2.initval = 16'h6996 ; ROM16X1 lf9cd2 (.AD3(tw8923e), .AD2(fpaf81f), .AD1(ne7c0ff), .AD0(qi1a36b), .DO0(xybd739)) ; defparam faeb9ca.initval = 16'h6996 ; ROM16X1 faeb9ca (.AD3(jp71247), .AD2(tw8923e), .AD1(fpaf81f), .AD0(ba139a), .DO0(wy98918)) ; defparam goc48c0.initval = 16'h6996 ; ROM16X1 goc48c0 (.AD3(db8e248), .AD2(jp71247), .AD1(tw8923e), .AD0(aa1fe8e), .DO0(ph9952)) ; defparam yk4ca97.initval = 16'h6996 ; ROM16X1 yk4ca97 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(oh9068d), .AD0(oh9068d), .DO0(jpcd4c1)) ; defparam al6a60e.initval = 16'h6996 ; ROM16X1 al6a60e (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(rie809), .AD0(oh9068d), .DO0(bna0256)) ; defparam do12b7.initval = 16'h6996 ; ROM16X1 do12b7 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(rib75b1), .AD0(rie809), .DO0(ofd6c5e)) ; defparam ukb62f5.initval = 16'h6996 ; ROM16X1 ukb62f5 (.AD3(nt8bd4c), .AD2(rib75b1), .AD1(rie809), .AD0(oh9068d), .DO0(su4cd40)) ; defparam xw66a01.initval = 16'h6996 ; ROM16X1 xw66a01 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(su4cd40), .AD0(oh9068d), .DO0(ld5a793)) ; defparam yxd3c9e.initval = 16'h6996 ; ROM16X1 yxd3c9e (.AD3(gbf27ae), .AD2(zm93d75), .AD1(hd9ebab), .AD0(uif5d5f), .DO0(iraeaf9)) ; defparam mr757cd.initval = 16'h6996 ; ROM16X1 mr757cd (.AD3(pf5f365), .AD2(fnf9b2e), .AD1(xjcd977), .AD0(lq6cbbf), .DO0(gb65dfa)) ; defparam mg2efd4.initval = 16'h6996 ; ROM16X1 mg2efd4 (.AD3(hd9ebab), .AD2(uif5d5f), .AD1(oh9068d), .AD0(oh9068d), .DO0(sj8e0d)) ; defparam xw4706d.initval = 16'h6996 ; ROM16X1 xw4706d (.AD3(zm93d75), .AD2(hd9ebab), .AD1(uif5d5f), .AD0(oh9068d), .DO0(al5e34f)) ; defparam nef1a7c.initval = 16'h6996 ; ROM16X1 nef1a7c (.AD3(lq6cbbf), .AD2(gbf27ae), .AD1(zm93d75), .AD0(sj8e0d), .DO0(ux18596)) ; defparam xjc2cb5.initval = 16'h6996 ; ROM16X1 xjc2cb5 (.AD3(xjcd977), .AD2(lq6cbbf), .AD1(gbf27ae), .AD0(al5e34f), .DO0(vi764fd)) ; defparam pub27eb.initval = 16'h6996 ; ROM16X1 pub27eb (.AD3(fnf9b2e), .AD2(xjcd977), .AD1(lq6cbbf), .AD0(iraeaf9), .DO0(medbb14)) ; defparam lddd8a1.initval = 16'h6996 ; ROM16X1 lddd8a1 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(oh9068d), .AD0(oh9068d), .DO0(ay772e2)) ; defparam cob9711.initval = 16'h6996 ; ROM16X1 cob9711 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(ng1100c), .AD0(oh9068d), .DO0(zx40318)) ; defparam tw18c6.initval = 16'h6996 ; ROM16X1 tw18c6 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(mrc6794), .AD0(ng1100c), .DO0(lf9e52c)) ; defparam yxf2966.initval = 16'h6996 ; ROM16X1 yxf2966 (.AD3(vxa59a6), .AD2(mrc6794), .AD1(ng1100c), .AD0(oh9068d), .DO0(swa6d19)) ; defparam kf368c9.initval = 16'h6996 ; ROM16X1 kf368c9 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(swa6d19), .AD0(oh9068d), .DO0(xj641e9)) ; XOR2 xy20f4f (.A(ym21624), .B(uif5d5f), .Z(jpe9ea6)); XOR2 rt4f536 (.A(nt3fd1), .B(anae5af), .Z(iea6de0)); defparam ir36f01.initval = 16'h0410 ; ROM16X1 ir36f01 (.AD3(iebc062), .AD2(anae5af), .AD1(nt3fd1), .AD0(oh9068d), .DO0(su6205e)) ; defparam ec102f0.initval = 16'h1004 ; ROM16X1 ec102f0 (.AD3(iebc062), .AD2(anae5af), .AD1(nt3fd1), .AD0(oh9068d), .DO0(fce507)) ; defparam ww7283b.initval = 16'h0140 ; ROM16X1 ww7283b (.AD3(bna0ec7), .AD2(ym21624), .AD1(uif5d5f), .AD0(oh9068d), .DO0(fnc7d4e)) ; defparam ou3ea76.initval = 16'h4001 ; ROM16X1 ou3ea76 (.AD3(bna0ec7), .AD2(ym21624), .AD1(uif5d5f), .AD0(oh9068d), .DO0(cb8011e)) ; INV qi8f4 (.A(do47a1), .Z(an23d0a)); AND2 vk1e855 (.A(dmf42ab), .B(an23d0a), .Z(ecaad5)); AND2 nr556a8 (.A(dmf42ab), .B(do47a1), .Z(fad51e7)); defparam baa8f3b.CSDECODE_R = 3'b000 ; defparam baa8f3b.CSDECODE_W = 3'b000 ; defparam baa8f3b.GSR = "ENABLED" ; defparam baa8f3b.RESETMODE = "ASYNC" ; defparam baa8f3b.REGMODE = "NOREG" ; defparam baa8f3b.DATA_WIDTH_R = 18 ; defparam baa8f3b.DATA_WIDTH_W = 18 ; PDP16KA baa8f3b (.DI0(uve78fb[0]), .DI1(uve78fb[1]), .DI2(uve78fb[2]), .DI3(uve78fb[3]), .DI4(uve78fb[4]), .DI5(uve78fb[5]), .DI6(uve78fb[6]), .DI7(uve78fb[7]), .DI8(uve78fb[8]), .DI9(uve78fb[9]), .DI10(uve78fb[10]), .DI11(uve78fb[11]), .DI12(uve78fb[12]), .DI13(uve78fb[13]), .DI14(uve78fb[14]), .DI15(uve78fb[15]), .DI16(uve78fb[16]), .DI17(uve78fb[17]), .DI18(uve78fb[0]), .DI19(uve78fb[1]), .DI20(uve78fb[2]), .DI21(uve78fb[3]), .DI22(uve78fb[4]), .DI23(uve78fb[5]), .DI24(uve78fb[6]), .DI25(uve78fb[7]), .DI26(uve78fb[8]), .DI27(uve78fb[9]), .DI28(uve78fb[10]), .DI29(uve78fb[11]), .DI30(uve78fb[12]), .DI31(uve78fb[13]), .DI32(uve78fb[14]), .DI33(uve78fb[15]), .DI34(uve78fb[16]), .DI35(uve78fb[17]), .ADW0(oh3c44c), .ADW1(oh3c44c), .ADW2(oh9068d), .ADW3(oh9068d), .ADW4(me4c91b), .ADW5(dz648d9), .ADW6(ou246ce), .ADW7(ep23671), .ADW8(xy1b38c), .ADW9(qtd9c62), .ADW10(kqce314), .ADW11(nr718a1), .ADW12(do8c50f), .ADW13(cm6287a), .CEW(ng86878), .CLKW(an3c7dd), .WE(oh3c44c), .CSW0(oh9068d), .CSW1(oh9068d), .CSW2(oh9068d), .ADR0(oh9068d), .ADR1(oh9068d), .ADR2(oh9068d), .ADR3(oh9068d), .ADR4(yx4e2a2), .ADR5(vv71515), .ADR6(mt8a8ae), .ADR7(yx54574), .ADR8(xya2ba5), .ADR9(wy15d2b), .ADR10(epae958), .ADR11(hb74ac5), .ADR12(jra562f), .ADR13(ou2b17f), .CER(db84238), .CLKR(fne3eec), .CSR0(oh9068d), .CSR1(oh9068d), .CSR2(oh9068d), .RST(xjdd9c2), .DO0(blc2d86[0]), .DO1(blc2d86[1]), .DO2(blc2d86[2]), .DO3(blc2d86[3]), .DO4(blc2d86[4]), .DO5(blc2d86[5]), .DO6(blc2d86[6]), .DO7\r
-(blc2d86[7]), .DO8(blc2d86[8]), .DO9(blc2d86[9]), .DO10(blc2d86[10]), .DO11(blc2d86[11]), .DO12(blc2d86[12]), .DO13(blc2d86[13]), .DO14(blc2d86[14]), .DO15(blc2d86[15]), .DO16(blc2d86[16]), .DO17(blc2d86[17]), .DO18(), .DO19(), .DO20(), .DO21(), .DO22(), .DO23(), .DO24(), .DO25(), .DO26(), .DO27(), .DO28(), .DO29(), .DO30(), .DO31(), .DO32(), .DO33(), .DO34(), .DO35()) ; defparam vi478a0.GSR = "ENABLED" ; FD1P3BX vi478a0 (.D(mre2814), .SP(ng86878), .CK(an3c7dd), .PD(xjdd9c2), .Q(rt5fa47)) ; defparam hda57e2.GSR = "ENABLED" ; FD1P3DX hda57e2 (.D(ld5f8b9), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(yxfd23f)) ; defparam hocfd61.GSR = "ENABLED" ; FD1P3DX hocfd61 (.D(mef5856), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(tw3f9da)) ; defparam irb13c0.GSR = "ENABLED" ; FD1P3DX irb13c0 (.D(vv4f023), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(psda5e1)) ; defparam ou1f0d5.GSR = "ENABLED" ; FD1P3DX ou1f0d5 (.D(yxc3544), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(vie15c8)) ; defparam hq252d5.GSR = "ENABLED" ; FD1P3DX hq252d5 (.D(al4b55d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dzc8610)) ; defparam kdedeea.GSR = "ENABLED" ; FD1P3DX kdedeea (.D(hb7baa4), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ec10c6f)) ; defparam sj26e64.GSR = "ENABLED" ; FD1P3DX sj26e64 (.D(mgb992f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(gb6f0c9)) ; defparam ne79b92.GSR = "ENABLED" ; FD1P3DX ne79b92 (.D(fn6e49f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(uvc982f)) ; defparam vife21d.GSR = "ENABLED" ; FD1P3DX vife21d (.D(uk8875a), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fc2fa21)) ; defparam dmd0156.GSR = "ENABLED" ; FD1P3DX dmd0156 (.D(wy559d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ym21624)) ; defparam she8601.GSR = "ENABLED" ; FD1P3DX she8601 (.D(pfe91fc), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fa69a9c)) ; defparam jc4d4e2.GSR = "ENABLED" ; FD1P3DX jc4d4e2 (.D(blfced2), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fp942e5)) ; defparam cba172f.GSR = "ENABLED" ; FD1P3DX cba172f (.D(fnd2f0a), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(eaea018)) ; defparam dz500c0.GSR = "ENABLED" ; FD1P3DX dz500c0 (.D(gqae43), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(gd3cf5c)) ; defparam ene7ae5.GSR = "ENABLED" ; FD1P3DX ene7ae5 (.D(cm43086), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ld6e606)) ; defparam fa73036.GSR = "ENABLED" ; FD1P3DX fa73036 (.D(pu86378), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(pu997a9)) ; defparam gocbd4b.GSR = "ENABLED" ; FD1P3DX gocbd4b (.D(qg7864c), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dmc506a)) ; defparam bn28352.GSR = "ENABLED" ; FD1P3DX bn28352 (.D(me4c17d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(twbd919)) ; defparam fnec8cb.GSR = "ENABLED" ; FD1P3DX fnec8cb (.D(me7d10b), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ipf79c5)) ; defparam ksbce2c.GSR = "ENABLED" ; FD1P3DX ksbce2c (.D(fcb121), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(zzceee)) ; defparam ay67777.GSR = "ENABLED" ; FD1P3DX ay67777 (.D(ym21624), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(tuc0cca)) ; defparam db6653.GSR = "ENABLED" ; FD1P3DX db6653 (.D(rt5fa47), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(me4c91b)) ; defparam pseb66c.GSR = "ENABLED" ; FD1P3DX pseb66c (.D(yxfd23f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dz648d9)) ; defparam cba4eca.GSR = "ENABLED" ; FD1P3DX cba4eca (.D(tw3f9da), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ou246ce)) ; defparam aa31aa0.GSR = "ENABLED" ; FD1P3DX aa31aa0 (.D(psda5e1), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ep23671)) ; defparam xj45bd5.GSR = "ENABLED" ; FD1P3DX xj45bd5 (.D(vie15c8), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(xy1b38c)) ; defparam jcf48be.GSR = "ENABLED" ; FD1P3DX jcf48be (.D(dzc8610), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(qtd9c62)) ; defparam suefb70.GSR = "ENABLED" ; FD1P3DX suefb70 (.D(ec10c6f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(kqce314)) ; defparam ic4cd37.GSR = "ENABLED" ; FD1P3DX ic4cd37 (.D(gb6f0c9), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(nr718a1)) ; defparam su593c1.GSR = "ENABLED" ; FD1P3DX su593c1 (.D(uvc982f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(do8c50f)) ; defparam kd6f03b.GSR = "ENABLED" ; FD1P3DX kd6f03b (.D(fc2fa21), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(cm6287a)) ; defparam tj3a29.GSR = "ENABLED" ; FD1P3DX tj3a29 (.D(ym21624), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(bna0ec7)) ; defparam mgacd25.GSR = "ENABLED" ; FD1P3BX mgacd25 (.D(uk34943), .SP(db84238), .CK(fne3eec), .PD(ou8d7e9), .Q(osc485a)) ; defparam jr198f9.GSR = "ENABLED" ; FD1P3DX jr198f9 (.D(rg63e74), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(mg242d1)) ; defparam gqa31c6.GSR = "ENABLED" ; FD1P3DX gqa31c6 (.D(xjc7184), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(wwd125e)) ; defparam nt27f5f.GSR = "ENABLED" ; FD1P3DX nt27f5f (.D(qtfd7fa), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(uv5e284)) ; defparam osd47c8.GSR = "ENABLED" ; FD1P3DX osd47c8 (.D(ym1f209), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ph848ae)) ; defparam vi48da6.GSR = "ENABLED" ; FD1P3DX vi48da6 (.D(gd36998), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(anaee78)) ; defparam qgc4a28.GSR = "ENABLED" ; FD1P3DX qgc4a28 (.D(vx28a0b), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ay78a4b)) ; defparam mr5ede2.GSR = "ENABLED" ; FD1P3DX mr5ede2 (.D(jeb78ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kd4b2a8)) ; defparam os72144.GSR = "ENABLED" ; FD1P3DX os72144 (.D(cb8510c), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(lsa8a57)) ; defparam th64d07.GSR = "ENABLED" ; FD1P3DX th64d07 (.D(co341f5), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ho575ae)) ; defparam fca8d00.GSR = "ENABLED" ; FD1P3DX fca8d00 (.D(mg34010), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(anae5af)) ; defparam ux80e29.GSR = "ENABLED" ; FD1P3DX ux80e29 (.D(mg21689), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kq6dea3)) ; defparam yx6f518.GSR = "ENABLED" ; FD1P3DX yx6f518 (.D(hq892f1), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ks24221)) ; defparam wy21109.GSR = "ENABLED" ; FD1P3DX wy21109 (.D(rgf1424), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ne4d871)) ; defparam jc6c38b.GSR = "ENABLED" ; FD1P3DX jc6c38b (.D(uk24577), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kqde7bd)) ; defparam rtf3de8.GSR = "ENABLED" ; FD1P3DX rtf3de8 (.D(yk773c5), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(hd378a0)) ; defparam cobc506.GSR = "ENABLED" ; FD1P3DX cobc506 (.D(hoc5259), .SP(\r
-db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ir857bb)) ; defparam mg2bddc.GSR = "ENABLED" ; FD1P3DX mg2bddc (.D(kq59545), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(uxdb2a)) ; defparam me6d955.GSR = "ENABLED" ; FD1P3DX me6d955 (.D(hb452ba), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(vi42afb)) ; defparam mg157da.GSR = "ENABLED" ; FD1P3DX mg157da (.D(phbad72), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(qi8dcd0)) ; defparam jp6e681.GSR = "ENABLED" ; FD1P3DX jp6e681 (.D(ui72d7c), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ps738fb)) ; defparam pu9c7da.GSR = "ENABLED" ; FD1P3DX pu9c7da (.D(anae5af), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(qv9f0d5)) ; defparam mrf86ac.GSR = "ENABLED" ; FD1P3DX mrf86ac (.D(osc485a), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(yx4e2a2)) ; defparam ux29433.GSR = "ENABLED" ; FD1P3DX ux29433 (.D(mg242d1), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(vv71515)) ; defparam nr7e701.GSR = "ENABLED" ; FD1P3DX nr7e701 (.D(wwd125e), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(mt8a8ae)) ; defparam jpf32c7.GSR = "ENABLED" ; FD1P3DX jpf32c7 (.D(uv5e284), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(yx54574)) ; defparam shd959b.GSR = "ENABLED" ; FD1P3DX shd959b (.D(ph848ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(xya2ba5)) ; defparam xj503f8.GSR = "ENABLED" ; FD1P3DX xj503f8 (.D(anaee78), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(wy15d2b)) ; defparam qtf8b73.GSR = "ENABLED" ; FD1P3DX qtf8b73 (.D(ay78a4b), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(epae958)) ; defparam sh5ec8b.GSR = "ENABLED" ; FD1P3DX sh5ec8b (.D(kd4b2a8), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(hb74ac5)) ; defparam dz7bf90.GSR = "ENABLED" ; FD1P3DX dz7bf90 (.D(lsa8a57), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(jra562f)) ; defparam zz9bb1d.GSR = "ENABLED" ; FD1P3DX zz9bb1d (.D(ho575ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ou2b17f)) ; defparam kdf770e.GSR = "ENABLED" ; FD1P3DX kdf770e (.D(anae5af), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(iebc062)) ; defparam en654a8.GSR = "ENABLED" ; FD1S3DX en654a8 (.D(fa69a9c), .CK(fne3eec), .CD(xjdd9c2), .Q(ld454ea)) ; defparam ls2a756.GSR = "ENABLED" ; FD1S3DX ls2a756 (.D(fp942e5), .CK(fne3eec), .CD(xjdd9c2), .Q(pub2248)) ; defparam vx91243.GSR = "ENABLED" ; FD1S3DX vx91243 (.D(eaea018), .CK(fne3eec), .CD(xjdd9c2), .Q(uk1f410)) ; defparam qgfa080.GSR = "ENABLED" ; FD1S3DX qgfa080 (.D(gd3cf5c), .CK(fne3eec), .CD(xjdd9c2), .Q(fc164c)) ; defparam pub262.GSR = "ENABLED" ; FD1S3DX pub262 (.D(ld6e606), .CK(fne3eec), .CD(xjdd9c2), .Q(bn13340)) ; defparam ri99a06.GSR = "ENABLED" ; FD1S3DX ri99a06 (.D(pu997a9), .CK(fne3eec), .CD(xjdd9c2), .Q(zz32c7f)) ; defparam ri963fe.GSR = "ENABLED" ; FD1S3DX ri963fe (.D(dmc506a), .CK(fne3eec), .CD(xjdd9c2), .Q(kdf2b23)) ; defparam cb9591c.GSR = "ENABLED" ; FD1S3DX cb9591c (.D(twbd919), .CK(fne3eec), .CD(xjdd9c2), .Q(pse41ee)) ; defparam ls20f73.GSR = "ENABLED" ; FD1S3DX ls20f73 (.D(ipf79c5), .CK(fne3eec), .CD(xjdd9c2), .Q(an9a9d3)) ; defparam qgd4e9d.GSR = "ENABLED" ; FD1S3DX qgd4e9d (.D(zzceee), .CK(fne3eec), .CD(xjdd9c2), .Q(qte84e9)) ; defparam xw4274d.GSR = "ENABLED" ; FD1S3DX xw4274d (.D(tuc0cca), .CK(fne3eec), .CD(xjdd9c2), .Q(rt6be72)) ; defparam hb5f397.GSR = "ENABLED" ; FD1S3DX hb5f397 (.D(kq6dea3), .CK(an3c7dd), .CD(ou8d7e9), .Q(anbee41)) ; defparam enf720c.GSR = "ENABLED" ; FD1S3DX enf720c (.D(ks24221), .CK(an3c7dd), .CD(ou8d7e9), .Q(cz651af)) ; defparam nt28d7d.GSR = "ENABLED" ; FD1S3DX nt28d7d (.D(ne4d871), .CK(an3c7dd), .CD(ou8d7e9), .Q(lqee0f9)) ; defparam gb707ca.GSR = "ENABLED" ; FD1S3DX gb707ca (.D(kqde7bd), .CK(an3c7dd), .CD(ou8d7e9), .Q(kd54432)) ; defparam pua2195.GSR = "ENABLED" ; FD1S3DX pua2195 (.D(hd378a0), .CK(an3c7dd), .CD(ou8d7e9), .Q(hdaa0f5)) ; defparam bl507ae.GSR = "ENABLED" ; FD1S3DX bl507ae (.D(ir857bb), .CK(an3c7dd), .CD(ou8d7e9), .Q(os774cd)) ; defparam ntba669.GSR = "ENABLED" ; FD1S3DX ntba669 (.D(uxdb2a), .CK(an3c7dd), .CD(ou8d7e9), .Q(xj4f8b2)) ; defparam ho7c596.GSR = "ENABLED" ; FD1S3DX ho7c596 (.D(vi42afb), .CK(an3c7dd), .CD(ou8d7e9), .Q(lsb2b92)) ; defparam kf95c92.GSR = "ENABLED" ; FD1S3DX kf95c92 (.D(qi8dcd0), .CK(an3c7dd), .CD(ou8d7e9), .Q(hd94841)) ; defparam oha420e.GSR = "ENABLED" ; FD1S3DX oha420e (.D(ps738fb), .CK(an3c7dd), .CD(ou8d7e9), .Q(wj7532a)) ; defparam swa9954.GSR = "ENABLED" ; FD1S3DX swa9954 (.D(qv9f0d5), .CK(an3c7dd), .CD(ou8d7e9), .Q(nta035d)) ; defparam vk1aef.GSR = "ENABLED" ; FD1S3DX vk1aef (.D(ld454ea), .CK(fne3eec), .CD(xjdd9c2), .Q(nt8bd4c)) ; defparam kddce86.GSR = "ENABLED" ; FD1S3DX kddce86 (.D(pub2248), .CK(fne3eec), .CD(xjdd9c2), .Q(rib75b1)) ; defparam gda4691.GSR = "ENABLED" ; FD1S3DX gda4691 (.D(uk1f410), .CK(fne3eec), .CD(xjdd9c2), .Q(rie809)) ; defparam lq6c1b1.GSR = "ENABLED" ; FD1S3DX lq6c1b1 (.D(fc164c), .CK(fne3eec), .CD(xjdd9c2), .Q(med1c49)) ; defparam ay5cd66.GSR = "ENABLED" ; FD1S3DX ay5cd66 (.D(bn13340), .CK(fne3eec), .CD(xjdd9c2), .Q(db8e248)) ; defparam ie87613.GSR = "ENABLED" ; FD1S3DX ie87613 (.D(zz32c7f), .CK(fne3eec), .CD(xjdd9c2), .Q(jp71247)) ; defparam qtc9ff3.GSR = "ENABLED" ; FD1S3DX qtc9ff3 (.D(kdf2b23), .CK(fne3eec), .CD(xjdd9c2), .Q(tw8923e)) ; defparam dmee8f0.GSR = "ENABLED" ; FD1S3DX dmee8f0 (.D(pse41ee), .CK(fne3eec), .CD(xjdd9c2), .Q(fpaf81f)) ; defparam ls1e282.GSR = "ENABLED" ; FD1S3DX ls1e282 (.D(an9a9d3), .CK(fne3eec), .CD(xjdd9c2), .Q(ne7c0ff)) ; defparam ks92bcc.GSR = "ENABLED" ; FD1S3DX ks92bcc (.D(qte84e9), .CK(fne3eec), .CD(xjdd9c2), .Q(cme07fa)) ; defparam zzcce6.GSR = "ENABLED" ; FD1S3DX zzcce6 (.D(rt6be72), .CK(fne3eec), .CD(xjdd9c2), .Q(nt3fd1)) ; defparam ntba8bf.GSR = "ENABLED" ; FD1S3DX ntba8bf (.D(anbee41), .CK(an3c7dd), .CD(ou8d7e9), .Q(vxa59a6)) ; defparam zkf1773.GSR = "ENABLED" ; FD1S3DX zkf1773 (.D(cz651af), .CK(an3c7dd), .CD(ou8d7e9), .Q(mrc6794)) ; defparam end649d.GSR = "ENABLED" ; FD1S3DX end649d (.D(lqee0f9), .CK(an3c7dd), .CD(ou8d7e9), .Q(ng1100c)) ; defparam by630c7.GSR = "ENABLED" ; FD1S3DX by630c7 (.D(kd54432), .CK(an3c7dd), .CD(ou8d7e9), .Q(pf5f365)) ; defparam lqd5b3a.GSR = "ENABLED" ; FD1S3DX lqd5b3a (.D(hdaa0f5), .CK(an3c7dd), .CD(ou8d7e9), .Q(fnf9b2e)) ; defparam ym9241e.GSR = "ENABLED" ; FD1S3DX ym9241e (.D(os774cd), .CK(an3c7dd), .CD(ou8d7e9), .Q(xjcd977)) ; defparam cb80a90.GSR = "ENABLED" ; FD1S3DX cb80a90 (.D(xj4f8b2), .CK(an3c7dd), .CD(ou8d7e9), .Q(lq6cbbf)) ; defparam bn284a4.GSR = "ENABLED" ; FD1S3DX bn284a4 (.D(lsb2b92), .CK(an3c7dd), .CD(ou8d7e9), .Q(gbf27ae)) ; defparam wy3bba6.GSR = "ENABLED" ; FD1S3DX wy3bba6 (.D(hd94841), .CK(an3c7dd), .CD(ou8d7e9), .Q(zm93d75)) ; defparam ri867c3.GSR = "ENABLED" ; FD1S3DX ri867c3 (.D(wj7532a), .CK(an3c7dd), .\r
-CD(ou8d7e9), .Q(hd9ebab)) ; defparam mrdc92b.GSR = "ENABLED" ; FD1S3DX mrdc92b (.D(nta035d), .CK(an3c7dd), .CD(ou8d7e9), .Q(uif5d5f)) ; defparam gbe20c9.GSR = "ENABLED" ; FD1S3BX gbe20c9 (.D(fc83261), .CK(fne3eec), .PD(ou8d7e9), .Q(gd8e31)) ; defparam pf617e8.GSR = "ENABLED" ; FD1S3DX pf617e8 (.D(rt5fa3a), .CK(an3c7dd), .CD(xjdd9c2), .Q(ana1e10)) ; defparam do3af23.GSR = "ENABLED" ; FD1S3BX do3af23 (.D(ksbc8d7), .CK(fne3eec), .PD(ou8d7e9), .Q(zzb0db9)) ; defparam bld72e1.GSR = "ENABLED" ; FD1S3DX bld72e1 (.D(aycb870), .CK(an3c7dd), .CD(xjdd9c2), .Q(vk86dcf)) ; CU2 gb70053 (.CI(oh3c44c), .PC1(yxfd23f), .PC0(rt5fa47), .CO(ay53911), .NC1(ld5f8b9), .NC0(mre2814)); CU2 xl22253 (.CI(ay53911), .PC1(psda5e1), .PC0(tw3f9da), .CO(qg53cd7), .NC1(vv4f023), .NC0(mef5856)); CU2 ux9ae77 (.CI(qg53cd7), .PC1(dzc8610), .PC0(vie15c8), .CO(qg77b88), .NC1(al4b55d), .NC0(yxc3544)); CU2 rt7101a (.CI(qg77b88), .PC1(gb6f0c9), .PC0(ec10c6f), .CO(co1ac37), .NC1(mgb992f), .NC0(hb7baa4)); CU2 fc86e67 (.CI(co1ac37), .PC1(fc2fa21), .PC0(uvc982f), .CO(me675cd), .NC1(uk8875a), .NC0(fn6e49f)); CU2 aab9a16 (.CI(me675cd), .PC1(oh9068d), .PC0(ym21624), .CO(xl1638a), .NC1(), .NC0(wy559d)); CU2 xl8e2b5 (.CI(oh3c44c), .PC1(mg242d1), .PC0(osc485a), .CO(vxb5fa1), .NC1(rg63e74), .NC0(uk34943)); CU2 hof43fe (.CI(vxb5fa1), .PC1(uv5e284), .PC0(wwd125e), .CO(dmfe504), .NC1(qtfd7fa), .NC0(xjc7184)); CU2 rva08e7 (.CI(dmfe504), .PC1(anaee78), .PC0(ph848ae), .CO(mre7cae), .NC1(gd36998), .NC0(ym1f209)); CU2 an95d4c (.CI(mre7cae), .PC1(kd4b2a8), .PC0(ay78a4b), .CO(cm4c960), .NC1(jeb78ae), .NC0(vx28a0b)); CU2 kf2c072 (.CI(cm4c960), .PC1(ho575ae), .PC0(lsa8a57), .CO(yk72b5b), .NC1(co341f5), .NC0(cb8510c)); CU2 ld6b623 (.CI(yk72b5b), .PC1(oh9068d), .PC0(anae5af), .CO(wl23d30), .NC1(), .NC0(mg34010)); FSUB2 hof4c2b (.A1(yxfd23f), .A0(rt5fa47), .B1(lf9e52c), .B0(xj641e9), .BI(oh3c44c), .BOUT1(dzd8704), .BOUT0(), .S1(qtc3827), .S0(bn1c13c)); FSUB2 yke09e7 (.A1(psda5e1), .A0(tw3f9da), .B1(ay772e2), .B0(zx40318), .BI(dzd8704), .BOUT1(alc3f66), .BOUT0(), .S1(aa1fb34), .S0(shfd9a1)); FSUB2 xjecd0d (.A1(dzc8610), .A0(vie15c8), .B1(vi764fd), .B0(medbb14), .BI(alc3f66), .BOUT1(jc7312e), .BOUT0(), .S1(wy98973), .S0(goc4b98)); FSUB2 ba25cc1 (.A1(gb6f0c9), .A0(ec10c6f), .B1(iraeaf9), .B0(ux18596), .BI(jc7312e), .BOUT1(xj50641), .BOUT0(), .S1(pu8320f), .S0(xl1907b)); FSUB2 vvc83df (.A1(fc2fa21), .A0(uvc982f), .B1(sj8e0d), .B0(al5e34f), .BI(xj50641), .BOUT1(ayf539a), .BOUT0(), .S1(yma9cd0), .S0(gb4e680)); FSUB2 fa73405 (.A1(oh9068d), .A0(jpe9ea6), .B1(oh9068d), .B0(oh9068d), .BI(ayf539a), .BOUT1(), .BOUT0(), .S1(), .S0(ay5c741)); VHI the3a09 (.Z(oh3c44c)); FSUB2 gbe827d (.A1(ofd6c5e), .A0(ld5a793), .B1(mg242d1), .B0(osc485a), .BI(oh3c44c), .BOUT1(dm6cf8c), .BOUT0(), .S1(su67c62), .S0(ie3e311)); FSUB2 tuf1889 (.A1(jpcd4c1), .A0(bna0256), .B1(uv5e284), .B0(wwd125e), .BI(dm6cf8c), .BOUT1(xj5a0d5), .BOUT0(), .S1(psd06ae), .S0(do83573)); FSUB2 co1ab9b (.A1(wy98918), .A0(ph9952), .B1(anaee78), .B0(ph848ae), .BI(xj5a0d5), .BOUT1(jcca8f5), .BOUT0(), .S1(al547aa), .S0(mga3d55)); FSUB2 ng1eaa9 (.A1(aa1fe8e), .A0(xybd739), .B1(kd4b2a8), .B0(ay78a4b), .BI(jcca8f5), .BOUT1(by58fcd), .BOUT0(), .S1(xjc7e6a), .S0(do3f356)); FSUB2 hbf9ab3 (.A1(qi1a36b), .A0(ba139a), .B1(ho575ae), .B0(lsa8a57), .BI(by58fcd), .BOUT1(fafea05), .BOUT0(), .S1(do47a1), .S0(xya8150)); FSUB2 dz40a83 (.A1(oh9068d), .A0(iea6de0), .B1(oh9068d), .B0(oh9068d), .BI(fafea05), .BOUT1(), .BOUT0(), .S1(), .S0(dmf42ab)); AGEB2 dzc2e84 (.A1(mg242d1), .A0(osc485a), .B1(ofd6c5e), .B0(ld5a793), .CI(db84238), .GE(mg34ebd)); AGEB2 vka75e9 (.A1(uv5e284), .A0(wwd125e), .B1(jpcd4c1), .B0(bna0256), .CI(mg34ebd), .GE(ps52ebf)); AGEB2 co975fb (.A1(anaee78), .A0(ph848ae), .B1(wy98918), .B0(ph9952), .CI(ps52ebf), .GE(yxc6fde)); AGEB2 nt37ef4 (.A1(kd4b2a8), .A0(ay78a4b), .B1(aa1fe8e), .B0(xybd739), .CI(yxc6fde), .GE(vx37459)); AGEB2 rvba2cf (.A1(ho575ae), .A0(lsa8a57), .B1(qi1a36b), .B0(ba139a), .CI(vx37459), .GE(nrf9e15)); AGEB2 hocf0af (.A1(oh9068d), .A0(su6205e), .B1(oh9068d), .B0(fce507), .CI(nrf9e15), .GE(xjd8c37)); FADD2 qtc61be (.A1(oh9068d), .A0(oh9068d), .B1(oh9068d), .B0(oh9068d), .CI(xjd8c37), .COUT1(), .COUT0(), .S1(), .S0(fc83261)); AGEB2 th5ad04 (.A1(yxfd23f), .A0(rt5fa47), .B1(lf9e52c), .B0(xj641e9), .CI(ng86878), .GE(lf3d99f)); AGEB2 theccff (.A1(psda5e1), .A0(tw3f9da), .B1(ay772e2), .B0(zx40318), .CI(lf3d99f), .GE(off2943)); AGEB2 jr94a1c (.A1(dzc8610), .A0(vie15c8), .B1(vi764fd), .B0(medbb14), .CI(off2943), .GE(lf37e37)); AGEB2 lfbf1be (.A1(gb6f0c9), .A0(ec10c6f), .B1(iraeaf9), .B0(ux18596), .CI(lf37e37), .GE(dobd9a4)); AGEB2 hbecd23 (.A1(fc2fa21), .A0(uvc982f), .B1(sj8e0d), .B0(al5e34f), .CI(dobd9a4), .GE(ldf336a)); AGEB2 ng99b57 (.A1(oh9068d), .A0(fnc7d4e), .B1(oh9068d), .B0(cb8011e), .CI(ldf336a), .GE(bld7356)); FADD2 qib9ab6 (.A1(oh9068d), .A0(oh9068d), .B1(oh9068d), .B0(oh9068d), .CI(bld7356), .COUT1(), .COUT0(), .S1(), .S0(rt5fa3a)); AGEB2 yx7526e (.A1(ay670b6[1]), .A0(ay670b6[0]), .B1(su67c62), .B0(ie3e311), .CI(db84238), .GE(ana12fe)); AGEB2 xl97f5 (.A1(ay670b6[3]), .A0(ay670b6[2]), .B1(psd06ae), .B0(do83573), .CI(ana12fe), .GE(fn74e8d)); AGEB2 ria746f (.A1(ay670b6[5]), .A0(ay670b6[4]), .B1(al547aa), .B0(mga3d55), .CI(fn74e8d), .GE(ofd3065)); AGEB2 qi9832c (.A1(ay670b6[7]), .A0(ay670b6[6]), .B1(xjc7e6a), .B0(do3f356), .CI(ofd3065), .GE(nt9f2f)); AGEB2 ld4f97f (.A1(ay670b6[9]), .A0(ay670b6[8]), .B1(do47a1), .B0(xya8150), .CI(nt9f2f), .GE(xjf30e3)); AGEB2 ec9871f (.A1(oh9068d), .A0(fad51e7), .B1(oh9068d), .B0(ecaad5), .CI(xjf30e3), .GE(ipccfc7)); FADD2 ui67e3d (.A1(oh9068d), .A0(oh9068d), .B1(oh9068d), .B0(oh9068d), .CI(ipccfc7), .COUT1(), .COUT0(), .S1(), .S0(ksbc8d7)); AGEB2 lq5ddbc (.A1(qtc3827), .A0(bn1c13c), .B1(tj385b0[1]), .B0(tj385b0[0]), .CI(ng86878), .GE(xl13484)); AGEB2 mt9a426 (.A1(aa1fb34), .A0(shfd9a1), .B1(tj385b0[3]), .B0(tj385b0[2]), .CI(xl13484), .GE(eca69e9)); AGEB2 aa34f49 (.A1(wy98973), .A0(goc4b98), .B1(tj385b0[5]), .B0(tj385b0[4]), .CI(eca69e9), .GE(ip4bdc0)); AGEB2 sh5ee04 (.A1(pu8320f), .A0(xl1907b), .B1(tj385b0[7]), .B0(tj385b0[6]), .CI(ip4bdc0), .GE(db2d4da)); AGEB2 yx6a6d7 (.A1(yma9cd0), .A0(gb4e680), .B1(tj385b0[9]), .B0(tj385b0[8]), .CI(db2d4da), .GE(sue0cf8)); AGEB2 hd67c0 (.A1(oh9068d), .A0(ay5c741), .B1(oh9068d), .B0(oh9068d), .CI(sue0cf8), .GE(cb3c91c)); VLO xwe48e5 (.Z(oh9068d)); FADD2 kf23951 (.A1(oh9068d), .A0(oh9068d), .B1(oh9068d), .B0(oh9068d), .CI(cb3c91c), .COUT1(), .COUT0(), .S1(), .S0(aycb870)); assign lf16c36 = gd8e31; assign wyb61b7 = ana1e10;\r
-always@* begin icc175e<={uve78fb>>1,eae03bd[0]};ngbaf0<=eae03bd[1];fa5d782<=eae03bd[2];faebc13<=eae03bd[3];of5e09b<=eae03bd[4];uif04dc<=eae03bd[5];co826e0<=eae03bd[6];xl13701<={ay670b6>>1,eae03bd[7]};nt9b80e<={tj385b0>>1,eae03bd[8]};end\r
-always@* begin shdc077[2047]<=an3c7dd;shdc077[2046]<=fne3eec;shdc077[2044]<=ie1f767;shdc077[2040]<=zkfbb38;shdc077[2032]<=xjdd9c2;shdc077[2017]<=rtece16;shdc077[1987]<=ay670b6[0];shdc077[1926]<=tj385b0[0];shdc077[1023]<=uve78fb[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module doad889 (uve78fb, an3c7dd, fne3eec, ie1f767, zkfbb38, xjdd9c2,\r
- rtece16, ay670b6, tj385b0, blc2d86, lf16c36, wyb61b7, zzb0db9,\r
- vk86dcf);\r
-input [17:0] uve78fb;\r
-input an3c7dd;\r
-input fne3eec;\r
-input ie1f767;\r
-input zkfbb38;\r
-input xjdd9c2;\r
-input rtece16;\r
-input [9:0] ay670b6;\r
-input [9:0] tj385b0;\r
-output [17:0] blc2d86;\r
-output lf16c36;\r
-output wyb61b7;\r
-output zzb0db9;\r
-output vk86dcf;\r
-reg [17 : 0] icc175e;\r
-reg ngbaf0;\r
-reg fa5d782;\r
-reg faebc13;\r
-reg of5e09b;\r
-reg uif04dc;\r
-reg co826e0;\r
-reg [9 : 0] xl13701;\r
-reg [9 : 0] nt9b80e;\r
-reg [2047:0] shdc077;\r
-wire [8:0] eae03bd;\r
-localparam ba1de9 = 9,ngef4b = 32'hfdffc68b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-AND2 gq98434 (.A(ie1f767), .B(uk10d0f), .Z(ng86878)); INV aa343c2 (.A(ana1e10), .Z(uk10d0f)); AND2 go78421 (.A(zkfbb38), .B(mg10847), .Z(db84238)); INV ym211c6 (.A(gd8e31), .Z(mg10847)); OR2 vx38c6b (.A(xjdd9c2), .B(rtece16), .Z(ou8d7e9)); XOR2 pf6bf48 (.A(rt5fa47), .B(yxfd23f), .Z(pfe91fc)); XOR2 ps48fe7 (.A(yxfd23f), .B(tw3f9da), .Z(blfced2)); XOR2 qte7697 (.A(tw3f9da), .B(psda5e1), .Z(fnd2f0a)); XOR2 aa97857 (.A(psda5e1), .B(vie15c8), .Z(gqae43)); XOR2 by57218 (.A(vie15c8), .B(dzc8610), .Z(cm43086)); XOR2 wl18431 (.A(dzc8610), .B(ec10c6f), .Z(pu86378)); XOR2 uk31bc3 (.A(ec10c6f), .B(gb6f0c9), .Z(qg7864c)); XOR2 czc3260 (.A(gb6f0c9), .B(uvc982f), .Z(me4c17d)); XOR2 yx60be8 (.A(uvc982f), .B(fc2fa21), .Z(me7d10b)); XOR2 wje8858 (.A(fc2fa21), .B(ym21624), .Z(fcb121)); XOR2 xw5890b (.A(osc485a), .B(mg242d1), .Z(mg21689)); XOR2 ngb449 (.A(mg242d1), .B(wwd125e), .Z(hq892f1)); XOR2 ic4978a (.A(wwd125e), .B(uv5e284), .Z(rgf1424)); XOR2 gd8a122 (.A(uv5e284), .B(ph848ae), .Z(uk24577)); XOR2 bn22bb9 (.A(ph848ae), .B(anaee78), .Z(yk773c5)); XOR2 mgb9e29 (.A(anaee78), .B(ay78a4b), .Z(hoc5259)); XOR2 gd292ca (.A(ay78a4b), .B(kd4b2a8), .Z(kq59545)); XOR2 tucaa29 (.A(kd4b2a8), .B(lsa8a57), .Z(hb452ba)); XOR2 gd295d6 (.A(lsa8a57), .B(ho575ae), .Z(phbad72)); XOR2 uvd6b96 (.A(ho575ae), .B(anae5af), .Z(ui72d7c)); defparam do96be0.initval = 16'h6996 ; ROM16X1 do96be0 (.AD3(fpaf81f), .AD2(ne7c0ff), .AD1(cme07fa), .AD0(nt3fd1), .DO0(aa1fe8e)) ; defparam qgff471.initval = 16'h6996 ; ROM16X1 qgff471 (.AD3(med1c49), .AD2(db8e248), .AD1(jp71247), .AD0(tw8923e), .DO0(ay491f2)) ; defparam fa48f90.initval = 16'h6996 ; ROM16X1 fa48f90 (.AD3(cme07fa), .AD2(nt3fd1), .AD1(oh9068d), .AD0(oh9068d), .DO0(qi1a36b)) ; defparam kqd1b58.initval = 16'h6996 ; ROM16X1 kqd1b58 (.AD3(ne7c0ff), .AD2(cme07fa), .AD1(nt3fd1), .AD0(oh9068d), .DO0(ba139a)) ; defparam lf9cd2.initval = 16'h6996 ; ROM16X1 lf9cd2 (.AD3(tw8923e), .AD2(fpaf81f), .AD1(ne7c0ff), .AD0(qi1a36b), .DO0(xybd739)) ; defparam faeb9ca.initval = 16'h6996 ; ROM16X1 faeb9ca (.AD3(jp71247), .AD2(tw8923e), .AD1(fpaf81f), .AD0(ba139a), .DO0(wy98918)) ; defparam goc48c0.initval = 16'h6996 ; ROM16X1 goc48c0 (.AD3(db8e248), .AD2(jp71247), .AD1(tw8923e), .AD0(aa1fe8e), .DO0(ph9952)) ; defparam yk4ca97.initval = 16'h6996 ; ROM16X1 yk4ca97 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(oh9068d), .AD0(oh9068d), .DO0(jpcd4c1)) ; defparam al6a60e.initval = 16'h6996 ; ROM16X1 al6a60e (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(rie809), .AD0(oh9068d), .DO0(bna0256)) ; defparam do12b7.initval = 16'h6996 ; ROM16X1 do12b7 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(rib75b1), .AD0(rie809), .DO0(ofd6c5e)) ; defparam ukb62f5.initval = 16'h6996 ; ROM16X1 ukb62f5 (.AD3(nt8bd4c), .AD2(rib75b1), .AD1(rie809), .AD0(oh9068d), .DO0(su4cd40)) ; defparam xw66a01.initval = 16'h6996 ; ROM16X1 xw66a01 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(su4cd40), .AD0(oh9068d), .DO0(ld5a793)) ; defparam yxd3c9e.initval = 16'h6996 ; ROM16X1 yxd3c9e (.AD3(gbf27ae), .AD2(zm93d75), .AD1(hd9ebab), .AD0(uif5d5f), .DO0(iraeaf9)) ; defparam mr757cd.initval = 16'h6996 ; ROM16X1 mr757cd (.AD3(pf5f365), .AD2(fnf9b2e), .AD1(xjcd977), .AD0(lq6cbbf), .DO0(gb65dfa)) ; defparam mg2efd4.initval = 16'h6996 ; ROM16X1 mg2efd4 (.AD3(hd9ebab), .AD2(uif5d5f), .AD1(oh9068d), .AD0(oh9068d), .DO0(sj8e0d)) ; defparam xw4706d.initval = 16'h6996 ; ROM16X1 xw4706d (.AD3(zm93d75), .AD2(hd9ebab), .AD1(uif5d5f), .AD0(oh9068d), .DO0(al5e34f)) ; defparam nef1a7c.initval = 16'h6996 ; ROM16X1 nef1a7c (.AD3(lq6cbbf), .AD2(gbf27ae), .AD1(zm93d75), .AD0(sj8e0d), .DO0(ux18596)) ; defparam xjc2cb5.initval = 16'h6996 ; ROM16X1 xjc2cb5 (.AD3(xjcd977), .AD2(lq6cbbf), .AD1(gbf27ae), .AD0(al5e34f), .DO0(vi764fd)) ; defparam pub27eb.initval = 16'h6996 ; ROM16X1 pub27eb (.AD3(fnf9b2e), .AD2(xjcd977), .AD1(lq6cbbf), .AD0(iraeaf9), .DO0(medbb14)) ; defparam lddd8a1.initval = 16'h6996 ; ROM16X1 lddd8a1 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(oh9068d), .AD0(oh9068d), .DO0(ay772e2)) ; defparam cob9711.initval = 16'h6996 ; ROM16X1 cob9711 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(ng1100c), .AD0(oh9068d), .DO0(zx40318)) ; defparam tw18c6.initval = 16'h6996 ; ROM16X1 tw18c6 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(mrc6794), .AD0(ng1100c), .DO0(lf9e52c)) ; defparam yxf2966.initval = 16'h6996 ; ROM16X1 yxf2966 (.AD3(vxa59a6), .AD2(mrc6794), .AD1(ng1100c), .AD0(oh9068d), .DO0(swa6d19)) ; defparam kf368c9.initval = 16'h6996 ; ROM16X1 kf368c9 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(swa6d19), .AD0(oh9068d), .DO0(xj641e9)) ; XOR2 xy20f4f (.A(ym21624), .B(uif5d5f), .Z(jpe9ea6)); XOR2 rt4f536 (.A(nt3fd1), .B(anae5af), .Z(iea6de0)); defparam ir36f01.initval = 16'h0410 ; ROM16X1 ir36f01 (.AD3(iebc062), .AD2(anae5af), .AD1(nt3fd1), .AD0(oh9068d), .DO0(su6205e)) ; defparam ec102f0.initval = 16'h1004 ; ROM16X1 ec102f0 (.AD3(iebc062), .AD2(anae5af), .AD1(nt3fd1), .AD0(oh9068d), .DO0(fce507)) ; defparam ww7283b.initval = 16'h0140 ; ROM16X1 ww7283b (.AD3(bna0ec7), .AD2(ym21624), .AD1(uif5d5f), .AD0(oh9068d), .DO0(fnc7d4e)) ; defparam ou3ea76.initval = 16'h4001 ; ROM16X1 ou3ea76 (.AD3(bna0ec7), .AD2(ym21624), .AD1(uif5d5f), .AD0(oh9068d), .DO0(cb8011e)) ; INV qi8f4 (.A(do47a1), .Z(an23d0a)); AND2 vk1e855 (.A(dmf42ab), .B(an23d0a), .Z(ecaad5)); AND2 nr556a8 (.A(dmf42ab), .B(do47a1), .Z(fad51e7)); defparam baa8f3b.CSDECODE_B = 3'b000 ; defparam baa8f3b.CSDECODE_A = 3'b000 ; defparam baa8f3b.WRITEMODE_B = "NORMAL" ; defparam baa8f3b.WRITEMODE_A = "NORMAL" ; defparam baa8f3b.GSR = "ENABLED" ; defparam baa8f3b.RESETMODE = "ASYNC" ; defparam baa8f3b.REGMODE_B = "NOREG" ; defparam baa8f3b.REGMODE_A = "NOREG" ; defparam baa8f3b.DATA_WIDTH_B = 18 ; defparam baa8f3b.DATA_WIDTH_A = 18 ; DP16KB baa8f3b (.DIA0(uve78fb[0]), .DIA1(uve78fb[1]), .DIA2(uve78fb[2]), .DIA3(uve78fb[3]), .DIA4(uve78fb[4]), .DIA5(uve78fb[5]), .DIA6(uve78fb[6]), .DIA7(uve78fb[7]), .DIA8(uve78fb[8]), .DIA9(uve78fb[9]), .DIA10(uve78fb[10]), .DIA11(uve78fb[11]), .DIA12(uve78fb[12]), .DIA13(uve78fb[13]), .DIA14(uve78fb[14]), .DIA15(uve78fb[15]), .DIA16(uve78fb[16]), .DIA17(uve78fb[17]), .ADA0(oh3c44c), .ADA1(oh3c44c), .ADA2(oh9068d), .ADA3(oh9068d), .ADA4(me4c91b), .ADA5(dz648d9), .ADA6(ou246ce), .ADA7(ep23671), .ADA8(xy1b38c), .ADA9(qtd9c62), .ADA10(kqce314), .ADA11(nr718a1), .ADA12(do8c50f), .ADA13(cm6287a), .CEA(ng86878), .CLKA(an3c7dd), .WEA(oh3c44c), .CSA0(oh9068d), .CSA1(oh9068d), .CSA2(oh9068d), .RSTA(xjdd9c2), .DIB0(oh9068d), .DIB1(oh9068d), .DIB2(oh9068d), .DIB3(oh9068d), .DIB4(oh9068d), .DIB5(oh9068d), .DIB6(oh9068d), .DIB7(oh9068d), .DIB8(oh9068d), .DIB9(oh9068d), .DIB10(oh9068d), .DIB11(oh9068d), .DIB12(oh9068d), .DIB13(oh9068d), .DIB14(oh9068d), .DIB15(oh9068d), .DIB16(oh9068d), .DIB17(oh9068d), .ADB0(oh9068d), .ADB1(oh9068d), .ADB2(oh9068d), .ADB3(oh9068d), .ADB4(yx4e2a2), .ADB5(vv71515), .ADB6(mt8a8ae), .ADB7(yx54574), .ADB8(xya2ba5), .ADB9(wy15d2b), .ADB10(epae958), .ADB11(hb74ac5), .ADB12(jra562f), .ADB13(ou2b17f), .CEB(db84238), .CLKB(fne3eec), .WEB(oh9068d), .CSB0(oh9068d), .CSB1(oh9068d), .CSB2(oh9068d), .RSTB(xjdd9c2), .DOA0()\r
-, .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOA9(), .DOA10(), .DOA11(), .DOA12(), .DOA13(), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(blc2d86[0]), .DOB1(blc2d86[1]), .DOB2(blc2d86[2]), .DOB3(blc2d86[3]), .DOB4(blc2d86[4]), .DOB5(blc2d86[5]), .DOB6(blc2d86[6]), .DOB7(blc2d86[7]), .DOB8(blc2d86[8]), .DOB9(blc2d86[9]), .DOB10(blc2d86[10]), .DOB11(blc2d86[11]), .DOB12(blc2d86[12]), .DOB13(blc2d86[13]), .DOB14(blc2d86[14]), .DOB15(blc2d86[15]), .DOB16(blc2d86[16]), .DOB17(blc2d86[17])) ; defparam vi478a0.GSR = "ENABLED" ; FD1P3BX vi478a0 (.D(mre2814), .SP(ng86878), .CK(an3c7dd), .PD(xjdd9c2), .Q(rt5fa47)) ; defparam hda57e2.GSR = "ENABLED" ; FD1P3DX hda57e2 (.D(ld5f8b9), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(yxfd23f)) ; defparam hocfd61.GSR = "ENABLED" ; FD1P3DX hocfd61 (.D(mef5856), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(tw3f9da)) ; defparam irb13c0.GSR = "ENABLED" ; FD1P3DX irb13c0 (.D(vv4f023), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(psda5e1)) ; defparam ou1f0d5.GSR = "ENABLED" ; FD1P3DX ou1f0d5 (.D(yxc3544), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(vie15c8)) ; defparam hq252d5.GSR = "ENABLED" ; FD1P3DX hq252d5 (.D(al4b55d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dzc8610)) ; defparam kdedeea.GSR = "ENABLED" ; FD1P3DX kdedeea (.D(hb7baa4), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ec10c6f)) ; defparam sj26e64.GSR = "ENABLED" ; FD1P3DX sj26e64 (.D(mgb992f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(gb6f0c9)) ; defparam ne79b92.GSR = "ENABLED" ; FD1P3DX ne79b92 (.D(fn6e49f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(uvc982f)) ; defparam vife21d.GSR = "ENABLED" ; FD1P3DX vife21d (.D(uk8875a), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fc2fa21)) ; defparam dmd0156.GSR = "ENABLED" ; FD1P3DX dmd0156 (.D(wy559d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ym21624)) ; defparam she8601.GSR = "ENABLED" ; FD1P3DX she8601 (.D(pfe91fc), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fa69a9c)) ; defparam jc4d4e2.GSR = "ENABLED" ; FD1P3DX jc4d4e2 (.D(blfced2), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fp942e5)) ; defparam cba172f.GSR = "ENABLED" ; FD1P3DX cba172f (.D(fnd2f0a), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(eaea018)) ; defparam dz500c0.GSR = "ENABLED" ; FD1P3DX dz500c0 (.D(gqae43), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(gd3cf5c)) ; defparam ene7ae5.GSR = "ENABLED" ; FD1P3DX ene7ae5 (.D(cm43086), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ld6e606)) ; defparam fa73036.GSR = "ENABLED" ; FD1P3DX fa73036 (.D(pu86378), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(pu997a9)) ; defparam gocbd4b.GSR = "ENABLED" ; FD1P3DX gocbd4b (.D(qg7864c), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dmc506a)) ; defparam bn28352.GSR = "ENABLED" ; FD1P3DX bn28352 (.D(me4c17d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(twbd919)) ; defparam fnec8cb.GSR = "ENABLED" ; FD1P3DX fnec8cb (.D(me7d10b), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ipf79c5)) ; defparam ksbce2c.GSR = "ENABLED" ; FD1P3DX ksbce2c (.D(fcb121), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(zzceee)) ; defparam ay67777.GSR = "ENABLED" ; FD1P3DX ay67777 (.D(ym21624), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(tuc0cca)) ; defparam db6653.GSR = "ENABLED" ; FD1P3DX db6653 (.D(rt5fa47), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(me4c91b)) ; defparam pseb66c.GSR = "ENABLED" ; FD1P3DX pseb66c (.D(yxfd23f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dz648d9)) ; defparam cba4eca.GSR = "ENABLED" ; FD1P3DX cba4eca (.D(tw3f9da), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ou246ce)) ; defparam aa31aa0.GSR = "ENABLED" ; FD1P3DX aa31aa0 (.D(psda5e1), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ep23671)) ; defparam xj45bd5.GSR = "ENABLED" ; FD1P3DX xj45bd5 (.D(vie15c8), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(xy1b38c)) ; defparam jcf48be.GSR = "ENABLED" ; FD1P3DX jcf48be (.D(dzc8610), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(qtd9c62)) ; defparam suefb70.GSR = "ENABLED" ; FD1P3DX suefb70 (.D(ec10c6f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(kqce314)) ; defparam ic4cd37.GSR = "ENABLED" ; FD1P3DX ic4cd37 (.D(gb6f0c9), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(nr718a1)) ; defparam su593c1.GSR = "ENABLED" ; FD1P3DX su593c1 (.D(uvc982f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(do8c50f)) ; defparam kd6f03b.GSR = "ENABLED" ; FD1P3DX kd6f03b (.D(fc2fa21), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(cm6287a)) ; defparam tj3a29.GSR = "ENABLED" ; FD1P3DX tj3a29 (.D(ym21624), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(bna0ec7)) ; defparam mgacd25.GSR = "ENABLED" ; FD1P3BX mgacd25 (.D(uk34943), .SP(db84238), .CK(fne3eec), .PD(ou8d7e9), .Q(osc485a)) ; defparam jr198f9.GSR = "ENABLED" ; FD1P3DX jr198f9 (.D(rg63e74), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(mg242d1)) ; defparam gqa31c6.GSR = "ENABLED" ; FD1P3DX gqa31c6 (.D(xjc7184), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(wwd125e)) ; defparam nt27f5f.GSR = "ENABLED" ; FD1P3DX nt27f5f (.D(qtfd7fa), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(uv5e284)) ; defparam osd47c8.GSR = "ENABLED" ; FD1P3DX osd47c8 (.D(ym1f209), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ph848ae)) ; defparam vi48da6.GSR = "ENABLED" ; FD1P3DX vi48da6 (.D(gd36998), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(anaee78)) ; defparam qgc4a28.GSR = "ENABLED" ; FD1P3DX qgc4a28 (.D(vx28a0b), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ay78a4b)) ; defparam mr5ede2.GSR = "ENABLED" ; FD1P3DX mr5ede2 (.D(jeb78ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kd4b2a8)) ; defparam os72144.GSR = "ENABLED" ; FD1P3DX os72144 (.D(cb8510c), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(lsa8a57)) ; defparam th64d07.GSR = "ENABLED" ; FD1P3DX th64d07 (.D(co341f5), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ho575ae)) ; defparam fca8d00.GSR = "ENABLED" ; FD1P3DX fca8d00 (.D(mg34010), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(anae5af)) ; defparam ux80e29.GSR = "ENABLED" ; FD1P3DX ux80e29 (.D(mg21689), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kq6dea3)) ; defparam yx6f518.GSR = "ENABLED" ; FD1P3DX yx6f518 (.D(hq892f1), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ks24221)) ; defparam wy21109.GSR = "ENABLED" ; FD1P3DX wy21109 (.D(rgf1424), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ne4d871)) ; defparam jc6c38b.GSR = "ENABLED" ; FD1P3DX jc6c38b (.D(uk24577), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kqde7bd)) ; defparam rtf3de8.GSR = "ENABLED"\r
-; FD1P3DX rtf3de8 (.D(yk773c5), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(hd378a0)) ; defparam cobc506.GSR = "ENABLED" ; FD1P3DX cobc506 (.D(hoc5259), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ir857bb)) ; defparam mg2bddc.GSR = "ENABLED" ; FD1P3DX mg2bddc (.D(kq59545), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(uxdb2a)) ; defparam me6d955.GSR = "ENABLED" ; FD1P3DX me6d955 (.D(hb452ba), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(vi42afb)) ; defparam mg157da.GSR = "ENABLED" ; FD1P3DX mg157da (.D(phbad72), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(qi8dcd0)) ; defparam jp6e681.GSR = "ENABLED" ; FD1P3DX jp6e681 (.D(ui72d7c), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ps738fb)) ; defparam pu9c7da.GSR = "ENABLED" ; FD1P3DX pu9c7da (.D(anae5af), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(qv9f0d5)) ; defparam mrf86ac.GSR = "ENABLED" ; FD1P3DX mrf86ac (.D(osc485a), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(yx4e2a2)) ; defparam ux29433.GSR = "ENABLED" ; FD1P3DX ux29433 (.D(mg242d1), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(vv71515)) ; defparam nr7e701.GSR = "ENABLED" ; FD1P3DX nr7e701 (.D(wwd125e), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(mt8a8ae)) ; defparam jpf32c7.GSR = "ENABLED" ; FD1P3DX jpf32c7 (.D(uv5e284), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(yx54574)) ; defparam shd959b.GSR = "ENABLED" ; FD1P3DX shd959b (.D(ph848ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(xya2ba5)) ; defparam xj503f8.GSR = "ENABLED" ; FD1P3DX xj503f8 (.D(anaee78), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(wy15d2b)) ; defparam qtf8b73.GSR = "ENABLED" ; FD1P3DX qtf8b73 (.D(ay78a4b), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(epae958)) ; defparam sh5ec8b.GSR = "ENABLED" ; FD1P3DX sh5ec8b (.D(kd4b2a8), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(hb74ac5)) ; defparam dz7bf90.GSR = "ENABLED" ; FD1P3DX dz7bf90 (.D(lsa8a57), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(jra562f)) ; defparam zz9bb1d.GSR = "ENABLED" ; FD1P3DX zz9bb1d (.D(ho575ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ou2b17f)) ; defparam kdf770e.GSR = "ENABLED" ; FD1P3DX kdf770e (.D(anae5af), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(iebc062)) ; defparam en654a8.GSR = "ENABLED" ; FD1S3DX en654a8 (.D(fa69a9c), .CK(fne3eec), .CD(xjdd9c2), .Q(ld454ea)) ; defparam ls2a756.GSR = "ENABLED" ; FD1S3DX ls2a756 (.D(fp942e5), .CK(fne3eec), .CD(xjdd9c2), .Q(pub2248)) ; defparam vx91243.GSR = "ENABLED" ; FD1S3DX vx91243 (.D(eaea018), .CK(fne3eec), .CD(xjdd9c2), .Q(uk1f410)) ; defparam qgfa080.GSR = "ENABLED" ; FD1S3DX qgfa080 (.D(gd3cf5c), .CK(fne3eec), .CD(xjdd9c2), .Q(fc164c)) ; defparam pub262.GSR = "ENABLED" ; FD1S3DX pub262 (.D(ld6e606), .CK(fne3eec), .CD(xjdd9c2), .Q(bn13340)) ; defparam ri99a06.GSR = "ENABLED" ; FD1S3DX ri99a06 (.D(pu997a9), .CK(fne3eec), .CD(xjdd9c2), .Q(zz32c7f)) ; defparam ri963fe.GSR = "ENABLED" ; FD1S3DX ri963fe (.D(dmc506a), .CK(fne3eec), .CD(xjdd9c2), .Q(kdf2b23)) ; defparam cb9591c.GSR = "ENABLED" ; FD1S3DX cb9591c (.D(twbd919), .CK(fne3eec), .CD(xjdd9c2), .Q(pse41ee)) ; defparam ls20f73.GSR = "ENABLED" ; FD1S3DX ls20f73 (.D(ipf79c5), .CK(fne3eec), .CD(xjdd9c2), .Q(an9a9d3)) ; defparam qgd4e9d.GSR = "ENABLED" ; FD1S3DX qgd4e9d (.D(zzceee), .CK(fne3eec), .CD(xjdd9c2), .Q(qte84e9)) ; defparam xw4274d.GSR = "ENABLED" ; FD1S3DX xw4274d (.D(tuc0cca), .CK(fne3eec), .CD(xjdd9c2), .Q(rt6be72)) ; defparam hb5f397.GSR = "ENABLED" ; FD1S3DX hb5f397 (.D(kq6dea3), .CK(an3c7dd), .CD(ou8d7e9), .Q(anbee41)) ; defparam enf720c.GSR = "ENABLED" ; FD1S3DX enf720c (.D(ks24221), .CK(an3c7dd), .CD(ou8d7e9), .Q(cz651af)) ; defparam nt28d7d.GSR = "ENABLED" ; FD1S3DX nt28d7d (.D(ne4d871), .CK(an3c7dd), .CD(ou8d7e9), .Q(lqee0f9)) ; defparam gb707ca.GSR = "ENABLED" ; FD1S3DX gb707ca (.D(kqde7bd), .CK(an3c7dd), .CD(ou8d7e9), .Q(kd54432)) ; defparam pua2195.GSR = "ENABLED" ; FD1S3DX pua2195 (.D(hd378a0), .CK(an3c7dd), .CD(ou8d7e9), .Q(hdaa0f5)) ; defparam bl507ae.GSR = "ENABLED" ; FD1S3DX bl507ae (.D(ir857bb), .CK(an3c7dd), .CD(ou8d7e9), .Q(os774cd)) ; defparam ntba669.GSR = "ENABLED" ; FD1S3DX ntba669 (.D(uxdb2a), .CK(an3c7dd), .CD(ou8d7e9), .Q(xj4f8b2)) ; defparam ho7c596.GSR = "ENABLED" ; FD1S3DX ho7c596 (.D(vi42afb), .CK(an3c7dd), .CD(ou8d7e9), .Q(lsb2b92)) ; defparam kf95c92.GSR = "ENABLED" ; FD1S3DX kf95c92 (.D(qi8dcd0), .CK(an3c7dd), .CD(ou8d7e9), .Q(hd94841)) ; defparam oha420e.GSR = "ENABLED" ; FD1S3DX oha420e (.D(ps738fb), .CK(an3c7dd), .CD(ou8d7e9), .Q(wj7532a)) ; defparam swa9954.GSR = "ENABLED" ; FD1S3DX swa9954 (.D(qv9f0d5), .CK(an3c7dd), .CD(ou8d7e9), .Q(nta035d)) ; defparam vk1aef.GSR = "ENABLED" ; FD1S3DX vk1aef (.D(ld454ea), .CK(fne3eec), .CD(xjdd9c2), .Q(nt8bd4c)) ; defparam kddce86.GSR = "ENABLED" ; FD1S3DX kddce86 (.D(pub2248), .CK(fne3eec), .CD(xjdd9c2), .Q(rib75b1)) ; defparam gda4691.GSR = "ENABLED" ; FD1S3DX gda4691 (.D(uk1f410), .CK(fne3eec), .CD(xjdd9c2), .Q(rie809)) ; defparam lq6c1b1.GSR = "ENABLED" ; FD1S3DX lq6c1b1 (.D(fc164c), .CK(fne3eec), .CD(xjdd9c2), .Q(med1c49)) ; defparam ay5cd66.GSR = "ENABLED" ; FD1S3DX ay5cd66 (.D(bn13340), .CK(fne3eec), .CD(xjdd9c2), .Q(db8e248)) ; defparam ie87613.GSR = "ENABLED" ; FD1S3DX ie87613 (.D(zz32c7f), .CK(fne3eec), .CD(xjdd9c2), .Q(jp71247)) ; defparam qtc9ff3.GSR = "ENABLED" ; FD1S3DX qtc9ff3 (.D(kdf2b23), .CK(fne3eec), .CD(xjdd9c2), .Q(tw8923e)) ; defparam dmee8f0.GSR = "ENABLED" ; FD1S3DX dmee8f0 (.D(pse41ee), .CK(fne3eec), .CD(xjdd9c2), .Q(fpaf81f)) ; defparam ls1e282.GSR = "ENABLED" ; FD1S3DX ls1e282 (.D(an9a9d3), .CK(fne3eec), .CD(xjdd9c2), .Q(ne7c0ff)) ; defparam ks92bcc.GSR = "ENABLED" ; FD1S3DX ks92bcc (.D(qte84e9), .CK(fne3eec), .CD(xjdd9c2), .Q(cme07fa)) ; defparam zzcce6.GSR = "ENABLED" ; FD1S3DX zzcce6 (.D(rt6be72), .CK(fne3eec), .CD(xjdd9c2), .Q(nt3fd1)) ; defparam ntba8bf.GSR = "ENABLED" ; FD1S3DX ntba8bf (.D(anbee41), .CK(an3c7dd), .CD(ou8d7e9), .Q(vxa59a6)) ; defparam zkf1773.GSR = "ENABLED" ; FD1S3DX zkf1773 (.D(cz651af), .CK(an3c7dd), .CD(ou8d7e9), .Q(mrc6794)) ; defparam end649d.GSR = "ENABLED" ; FD1S3DX end649d (.D(lqee0f9), .CK(an3c7dd), .CD(ou8d7e9), .Q(ng1100c)) ; defparam by630c7.GSR = "ENABLED" ; FD1S3DX by630c7 (.D(kd54432), .CK(an3c7dd), .CD(ou8d7e9), .Q(pf5f365)) ; defparam lqd5b3a.GSR = "ENABLED" ; FD1S3DX lqd5b3a (.D(hdaa0f5), .CK(an3c7dd), .CD(ou8d7e9), .Q(fnf9b2e)) ; defparam ym9241e.GSR = "ENABLED" ; FD1S3DX ym9241e (.D(os774cd), .CK(an3c7dd), .CD(ou8d7e9), .Q(xjcd977)) ; defparam cb80a90.GSR = "ENABLED" ; FD1S3DX cb80a90 (.D(xj4f8b2), .CK(an3c7dd), .CD(ou8d7e9), .Q(lq6cbbf)) ; defparam bn284a4.GSR = "ENABLED" ; FD1S3DX bn284a4 (.D(lsb2b92), .CK(an3c7dd), .CD(ou8d7e9), .Q(gbf27ae)) ; defparam wy3bba6.GSR =\r
-"ENABLED" ; FD1S3DX wy3bba6 (.D(hd94841), .CK(an3c7dd), .CD(ou8d7e9), .Q(zm93d75)) ; defparam ri867c3.GSR = "ENABLED" ; FD1S3DX ri867c3 (.D(wj7532a), .CK(an3c7dd), .CD(ou8d7e9), .Q(hd9ebab)) ; defparam mrdc92b.GSR = "ENABLED" ; FD1S3DX mrdc92b (.D(nta035d), .CK(an3c7dd), .CD(ou8d7e9), .Q(uif5d5f)) ; defparam gbe20c9.GSR = "ENABLED" ; FD1S3BX gbe20c9 (.D(fc83261), .CK(fne3eec), .PD(ou8d7e9), .Q(gd8e31)) ; defparam pf617e8.GSR = "ENABLED" ; FD1S3DX pf617e8 (.D(rt5fa3a), .CK(an3c7dd), .CD(xjdd9c2), .Q(ana1e10)) ; defparam do3af23.GSR = "ENABLED" ; FD1S3BX do3af23 (.D(ksbc8d7), .CK(fne3eec), .PD(ou8d7e9), .Q(zzb0db9)) ; defparam bld72e1.GSR = "ENABLED" ; FD1S3DX bld72e1 (.D(aycb870), .CK(an3c7dd), .CD(xjdd9c2), .Q(vk86dcf)) ; FADD2B fa4dd42 (.A0(oh9068d), .A1(oh3c44c), .B0(oh9068d), .B1(oh3c44c), .CI(oh9068d), .COUT(gd9f8df), .S0(), .S1()); CU2 gb70053 (.CI(gd9f8df), .PC0(rt5fa47), .PC1(yxfd23f), .CO(ay53911), .NC0(mre2814), .NC1(ld5f8b9)); CU2 xl22253 (.CI(ay53911), .PC0(tw3f9da), .PC1(psda5e1), .CO(qg53cd7), .NC0(mef5856), .NC1(vv4f023)); CU2 ux9ae77 (.CI(qg53cd7), .PC0(vie15c8), .PC1(dzc8610), .CO(qg77b88), .NC0(yxc3544), .NC1(al4b55d)); CU2 rt7101a (.CI(qg77b88), .PC0(ec10c6f), .PC1(gb6f0c9), .CO(co1ac37), .NC0(hb7baa4), .NC1(mgb992f)); CU2 fc86e67 (.CI(co1ac37), .PC0(uvc982f), .PC1(fc2fa21), .CO(me675cd), .NC0(fn6e49f), .NC1(uk8875a)); CU2 aab9a16 (.CI(me675cd), .PC0(ym21624), .PC1(oh9068d), .CO(xl1638a), .NC0(wy559d), .NC1()); FADD2B mr4b213 (.A0(oh9068d), .A1(oh3c44c), .B0(oh9068d), .B1(oh3c44c), .CI(oh9068d), .COUT(jpe9cf9), .S0(), .S1()); CU2 xl8e2b5 (.CI(jpe9cf9), .PC0(osc485a), .PC1(mg242d1), .CO(vxb5fa1), .NC0(uk34943), .NC1(rg63e74)); CU2 hof43fe (.CI(vxb5fa1), .PC0(wwd125e), .PC1(uv5e284), .CO(dmfe504), .NC0(xjc7184), .NC1(qtfd7fa)); CU2 rva08e7 (.CI(dmfe504), .PC0(ph848ae), .PC1(anaee78), .CO(mre7cae), .NC0(ym1f209), .NC1(gd36998)); CU2 an95d4c (.CI(mre7cae), .PC0(ay78a4b), .PC1(kd4b2a8), .CO(cm4c960), .NC0(vx28a0b), .NC1(jeb78ae)); CU2 kf2c072 (.CI(cm4c960), .PC0(lsa8a57), .PC1(ho575ae), .CO(yk72b5b), .NC0(cb8510c), .NC1(co341f5)); CU2 ld6b623 (.CI(yk72b5b), .PC0(anae5af), .PC1(oh9068d), .CO(wl23d30), .NC0(mg34010), .NC1()); FSUB2B hof4c2b (.A0(oh3c44c), .A1(rt5fa47), .B0(oh9068d), .B1(xj641e9), .BI(oh9068d), .BOUT(dzd8704), .S0(), .S1(bn1c13c)); FSUB2B yke09e7 (.A0(yxfd23f), .A1(tw3f9da), .B0(lf9e52c), .B1(zx40318), .BI(dzd8704), .BOUT(alc3f66), .S0(qtc3827), .S1(shfd9a1)); FSUB2B xjecd0d (.A0(psda5e1), .A1(vie15c8), .B0(ay772e2), .B1(medbb14), .BI(alc3f66), .BOUT(jc7312e), .S0(aa1fb34), .S1(goc4b98)); FSUB2B ba25cc1 (.A0(dzc8610), .A1(ec10c6f), .B0(vi764fd), .B1(ux18596), .BI(jc7312e), .BOUT(xj50641), .S0(wy98973), .S1(xl1907b)); FSUB2B vvc83df (.A0(gb6f0c9), .A1(uvc982f), .B0(iraeaf9), .B1(al5e34f), .BI(xj50641), .BOUT(ayf539a), .S0(pu8320f), .S1(gb4e680)); FSUB2B fa73405 (.A0(fc2fa21), .A1(jpe9ea6), .B0(sj8e0d), .B1(oh9068d), .BI(ayf539a), .BOUT(), .S0(yma9cd0), .S1(ay5c741)); VHI the3a09 (.Z(oh3c44c)); FSUB2B gbe827d (.A0(oh3c44c), .A1(ld5a793), .B0(oh9068d), .B1(osc485a), .BI(oh9068d), .BOUT(dm6cf8c), .S0(), .S1(ie3e311)); FSUB2B tuf1889 (.A0(ofd6c5e), .A1(bna0256), .B0(mg242d1), .B1(wwd125e), .BI(dm6cf8c), .BOUT(xj5a0d5), .S0(su67c62), .S1(do83573)); FSUB2B co1ab9b (.A0(jpcd4c1), .A1(ph9952), .B0(uv5e284), .B1(ph848ae), .BI(xj5a0d5), .BOUT(jcca8f5), .S0(psd06ae), .S1(mga3d55)); FSUB2B ng1eaa9 (.A0(wy98918), .A1(xybd739), .B0(anaee78), .B1(ay78a4b), .BI(jcca8f5), .BOUT(by58fcd), .S0(al547aa), .S1(do3f356)); FSUB2B hbf9ab3 (.A0(aa1fe8e), .A1(ba139a), .B0(kd4b2a8), .B1(lsa8a57), .BI(by58fcd), .BOUT(fafea05), .S0(xjc7e6a), .S1(xya8150)); FSUB2B dz40a83 (.A0(qi1a36b), .A1(iea6de0), .B0(ho575ae), .B1(oh9068d), .BI(fafea05), .BOUT(), .S0(do47a1), .S1(dmf42ab)); FADD2B nee495e (.A0(oh9068d), .A1(db84238), .B0(oh9068d), .B1(db84238), .CI(oh9068d), .COUT(kf90665), .S0(), .S1()); AGEB2 dzc2e84 (.A0(osc485a), .A1(mg242d1), .B0(ld5a793), .B1(ofd6c5e), .CI(kf90665), .GE(mg34ebd)); AGEB2 vka75e9 (.A0(wwd125e), .A1(uv5e284), .B0(bna0256), .B1(jpcd4c1), .CI(mg34ebd), .GE(ps52ebf)); AGEB2 co975fb (.A0(ph848ae), .A1(anaee78), .B0(ph9952), .B1(wy98918), .CI(ps52ebf), .GE(yxc6fde)); AGEB2 nt37ef4 (.A0(ay78a4b), .A1(kd4b2a8), .B0(xybd739), .B1(aa1fe8e), .CI(yxc6fde), .GE(vx37459)); AGEB2 rvba2cf (.A0(lsa8a57), .A1(ho575ae), .B0(ba139a), .B1(qi1a36b), .CI(vx37459), .GE(nrf9e15)); AGEB2 hocf0af (.A0(su6205e), .A1(oh9068d), .B0(fce507), .B1(oh9068d), .CI(nrf9e15), .GE(xjd8c37)); FADD2B qtc61be (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(xjd8c37), .COUT(), .S0(fc83261), .S1()); FADD2B vx3818d (.A0(oh9068d), .A1(ng86878), .B0(oh9068d), .B1(ng86878), .CI(oh9068d), .COUT(ho73e4e), .S0(), .S1()); AGEB2 th5ad04 (.A0(rt5fa47), .A1(yxfd23f), .B0(xj641e9), .B1(lf9e52c), .CI(ho73e4e), .GE(lf3d99f)); AGEB2 theccff (.A0(tw3f9da), .A1(psda5e1), .B0(zx40318), .B1(ay772e2), .CI(lf3d99f), .GE(off2943)); AGEB2 jr94a1c (.A0(vie15c8), .A1(dzc8610), .B0(medbb14), .B1(vi764fd), .CI(off2943), .GE(lf37e37)); AGEB2 lfbf1be (.A0(ec10c6f), .A1(gb6f0c9), .B0(ux18596), .B1(iraeaf9), .CI(lf37e37), .GE(dobd9a4)); AGEB2 hbecd23 (.A0(uvc982f), .A1(fc2fa21), .B0(al5e34f), .B1(sj8e0d), .CI(dobd9a4), .GE(ldf336a)); AGEB2 ng99b57 (.A0(fnc7d4e), .A1(oh9068d), .B0(cb8011e), .B1(oh9068d), .CI(ldf336a), .GE(bld7356)); FADD2B qib9ab6 (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(bld7356), .COUT(), .S0(rt5fa3a), .S1()); FADD2B go4cfd4 (.A0(oh9068d), .A1(db84238), .B0(oh9068d), .B1(db84238), .CI(oh9068d), .COUT(vx960d), .S0(), .S1()); AGEB2 yx7526e (.A0(ay670b6[0]), .A1(ay670b6[1]), .B0(ie3e311), .B1(su67c62), .CI(vx960d), .GE(ana12fe)); AGEB2 xl97f5 (.A0(ay670b6[2]), .A1(ay670b6[3]), .B0(do83573), .B1(psd06ae), .CI(ana12fe), .GE(fn74e8d)); AGEB2 ria746f (.A0(ay670b6[4]), .A1(ay670b6[5]), .B0(mga3d55), .B1(al547aa), .CI(fn74e8d), .GE(ofd3065)); AGEB2 qi9832c (.A0(ay670b6[6]), .A1(ay670b6[7]), .B0(do3f356), .B1(xjc7e6a), .CI(ofd3065), .GE(nt9f2f)); AGEB2 ld4f97f (.A0(ay670b6[8]), .A1(ay670b6[9]), .B0(xya8150), .B1(do47a1), .CI(nt9f2f), .GE(xjf30e3)); AGEB2 ec9871f (.A0(fad51e7), .A1(oh9068d), .B0(ecaad5), .B1(oh9068d), .CI(xjf30e3), .GE(ipccfc7)); FADD2B ui67e3d (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(ipccfc7), .COUT(), .S0(ksbc8d7), .S1()); FADD2B by790f2 (.A0(oh9068d), .A1(ng86878), .B0(oh9068d), .B1(ng86878), .CI(oh9068d), .COUT(ls960a9), .S0(), .S1()); AGEB2 lq5ddbc (.A0(bn1c13c), .A1(qtc3827), .B0(tj385b0[0]), .B1(tj385b0[1]), .CI(ls960a9), .GE(xl13484)); AGEB2 mt9a426 (.A0(shfd9a1), .A1(aa1fb34), .B0(tj385b0[2]), .B1(tj385b0[3]), .CI(xl13484), .GE(eca69e9)); AGEB2 aa34f49 (.A0(goc4b98), .A1(wy98973), .B0(tj385b0[4]), .B1(tj385b0[5]), .CI(eca69e9), .GE(ip4bdc0)); AGEB2 sh5ee04 (.A0(xl1907b), .A1(pu8320f), .B0(tj385b0[6]), .B1(tj385b0[7]), .CI(ip4bdc0), .GE(db2d4da)); AGEB2 yx6a6d7 (.A0(gb4e680), .A1(yma9cd0), .B0(tj385b0[8]), .B1(tj385b0[9]), .CI(db2d4da), .GE(sue0cf8)); AGEB2 hd67c0 (.A0(ay5c741), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(sue0cf8), .GE(cb3c91c)); VLO xwe48e5 (.Z(oh9068d)); FADD2B kf23951 (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(cb3c91c), .COUT(), .S0(aycb870), .S1()); assign lf16c36 = gd8e31; assign wyb61b7 = ana1e10;\r
-always@* begin icc175e<={uve78fb>>1,eae03bd[0]};ngbaf0<=eae03bd[1];fa5d782<=eae03bd[2];faebc13<=eae03bd[3];of5e09b<=eae03bd[4];uif04dc<=eae03bd[5];co826e0<=eae03bd[6];xl13701<={ay670b6>>1,eae03bd[7]};nt9b80e<={tj385b0>>1,eae03bd[8]};end\r
-always@* begin shdc077[2047]<=an3c7dd;shdc077[2046]<=fne3eec;shdc077[2044]<=ie1f767;shdc077[2040]<=zkfbb38;shdc077[2032]<=xjdd9c2;shdc077[2017]<=rtece16;shdc077[1987]<=ay670b6[0];shdc077[1926]<=tj385b0[0];shdc077[1023]<=uve78fb[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module do93e46 (uve78fb, an3c7dd, fne3eec, ie1f767, zkfbb38, xjdd9c2,\r
- rtece16, ay670b6, tj385b0, blc2d86, lf16c36, wyb61b7, zzb0db9,\r
- vk86dcf);\r
-input wire [17:0] uve78fb;\r
-input wire an3c7dd;\r
-input wire fne3eec;\r
-input wire ie1f767;\r
-input wire zkfbb38;\r
-input wire xjdd9c2;\r
-input wire rtece16;\r
-input wire [9:0] ay670b6;\r
-input wire [9:0] tj385b0;\r
-output wire [17:0] blc2d86;\r
-output wire lf16c36;\r
-output wire wyb61b7;\r
-output wire zzb0db9;\r
-output wire vk86dcf;\r
-wire uk10d0f;\r
-wire mg10847;\r
-wire su4cd40;\r
-wire ay491f2;\r
-wire swa6d19;\r
-wire gb65dfa;\r
-wire twb7f1d;\r
-wire pfe91fc;\r
-wire blfced2;\r
-wire fnd2f0a;\r
-wire gqae43;\r
-wire cm43086;\r
-wire pu86378;\r
-wire qg7864c;\r
-wire me4c17d;\r
-wire me7d10b;\r
-wire fcb121;\r
-wire me4c91b;\r
-wire dz648d9;\r
-wire ou246ce;\r
-wire ep23671;\r
-wire xy1b38c;\r
-wire qtd9c62;\r
-wire kqce314;\r
-wire nr718a1;\r
-wire do8c50f;\r
-wire cm6287a;\r
-wire bna0ec7;\r
-wire mg21689;\r
-wire hq892f1;\r
-wire rgf1424;\r
-wire uk24577;\r
-wire yk773c5;\r
-wire hoc5259;\r
-wire kq59545;\r
-wire hb452ba;\r
-wire phbad72;\r
-wire ui72d7c;\r
-wire yx4e2a2;\r
-wire vv71515;\r
-wire mt8a8ae;\r
-wire yx54574;\r
-wire xya2ba5;\r
-wire wy15d2b;\r
-wire epae958;\r
-wire hb74ac5;\r
-wire jra562f;\r
-wire ou2b17f;\r
-wire iebc062;\r
-wire fa69a9c;\r
-wire fp942e5;\r
-wire eaea018;\r
-wire gd3cf5c;\r
-wire ld6e606;\r
-wire pu997a9;\r
-wire dmc506a;\r
-wire twbd919;\r
-wire ipf79c5;\r
-wire zzceee;\r
-wire tuc0cca;\r
-wire kq6dea3;\r
-wire ks24221;\r
-wire ne4d871;\r
-wire kqde7bd;\r
-wire hd378a0;\r
-wire ir857bb;\r
-wire uxdb2a;\r
-wire vi42afb;\r
-wire qi8dcd0;\r
-wire ps738fb;\r
-wire qv9f0d5;\r
-wire nt8bd4c;\r
-wire ld454ea;\r
-wire rib75b1;\r
-wire pub2248;\r
-wire rie809;\r
-wire uk1f410;\r
-wire med1c49;\r
-wire fc164c;\r
-wire db8e248;\r
-wire bn13340;\r
-wire jp71247;\r
-wire zz32c7f;\r
-wire tw8923e;\r
-wire kdf2b23;\r
-wire fpaf81f;\r
-wire pse41ee;\r
-wire ne7c0ff;\r
-wire an9a9d3;\r
-wire cme07fa;\r
-wire qte84e9;\r
-wire nt3fd1;\r
-wire rt6be72;\r
-wire vxa59a6;\r
-wire anbee41;\r
-wire mrc6794;\r
-wire cz651af;\r
-wire ng1100c;\r
-wire lqee0f9;\r
-wire pf5f365;\r
-wire kd54432;\r
-wire fnf9b2e;\r
-wire hdaa0f5;\r
-wire xjcd977;\r
-wire os774cd;\r
-wire lq6cbbf;\r
-wire xj4f8b2;\r
-wire gbf27ae;\r
-wire lsb2b92;\r
-wire zm93d75;\r
-wire hd94841;\r
-wire hd9ebab;\r
-wire wj7532a;\r
-wire uif5d5f;\r
-wire nta035d;\r
-wire nga760e;\r
-wire gd8e31;\r
-wire ana1e10;\r
-wire ou8d7e9;\r
-wire mre2814;\r
-wire ld5f8b9;\r
-wire gd9f8df;\r
-wire mef5856;\r
-wire vv4f023;\r
-wire ay53911;\r
-wire yxc3544;\r
-wire al4b55d;\r
-wire qg53cd7;\r
-wire hb7baa4;\r
-wire mgb992f;\r
-wire qg77b88;\r
-wire fn6e49f;\r
-wire uk8875a;\r
-wire co1ac37;\r
-wire wy559d;\r
-wire xl1638a;\r
-wire ym21624;\r
-wire me675cd;\r
-wire uk34943;\r
-wire rg63e74;\r
-wire jpe9cf9;\r
-wire xjc7184;\r
-wire qtfd7fa;\r
-wire vxb5fa1;\r
-wire ym1f209;\r
-wire gd36998;\r
-wire dmfe504;\r
-wire vx28a0b;\r
-wire jeb78ae;\r
-wire mre7cae;\r
-wire cb8510c;\r
-wire co341f5;\r
-wire cm4c960;\r
-wire mg34010;\r
-wire wl23d30;\r
-wire anae5af;\r
-wire yk72b5b;\r
-wire bn1c13c;\r
-wire qtc3827;\r
-wire shfd9a1;\r
-wire dzd8704;\r
-wire aa1fb34;\r
-wire goc4b98;\r
-wire alc3f66;\r
-wire wy98973;\r
-wire xl1907b;\r
-wire jc7312e;\r
-wire pu8320f;\r
-wire gb4e680;\r
-wire xj50641;\r
-wire yma9cd0;\r
-wire ay5c741;\r
-wire ayf539a;\r
-wire jpe9ea6;\r
-wire aaa6dde;\r
-wire wl36ef1;\r
-wire ie3e311;\r
-wire oh3c44c;\r
-wire su67c62;\r
-wire do83573;\r
-wire dm6cf8c;\r
-wire psd06ae;\r
-wire mga3d55;\r
-wire xj5a0d5;\r
-wire al547aa;\r
-wire do3f356;\r
-wire jcca8f5;\r
-wire xjc7e6a;\r
-wire xya8150;\r
-wire by58fcd;\r
-wire do47a1;\r
-wire dmf42ab;\r
-wire fafea05;\r
-wire iea6de0;\r
-wire ie3b2e0;\r
-wire uvd9701;\r
-wire kf90665;\r
-wire ld5a793;\r
-wire ofd6c5e;\r
-wire osc485a;\r
-wire mg242d1;\r
-wire mg34ebd;\r
-wire bna0256;\r
-wire jpcd4c1;\r
-wire wwd125e;\r
-wire uv5e284;\r
-wire ps52ebf;\r
-wire ph9952;\r
-wire wy98918;\r
-wire ph848ae;\r
-wire anaee78;\r
-wire yxc6fde;\r
-wire xybd739;\r
-wire aa1fe8e;\r
-wire ay78a4b;\r
-wire kd4b2a8;\r
-wire vx37459;\r
-wire ba139a;\r
-wire qi1a36b;\r
-wire lsa8a57;\r
-wire ho575ae;\r
-wire nrf9e15;\r
-wire fce507;\r
-wire su6205e;\r
-wire fc83261;\r
-wire xjd8c37;\r
-wire ho73e4e;\r
-wire xj641e9;\r
-wire lf9e52c;\r
-wire rt5fa47;\r
-wire yxfd23f;\r
-wire lf3d99f;\r
-wire zx40318;\r
-wire ay772e2;\r
-wire tw3f9da;\r
-wire psda5e1;\r
-wire off2943;\r
-wire medbb14;\r
-wire vi764fd;\r
-wire vie15c8;\r
-wire dzc8610;\r
-wire lf37e37;\r
-wire ux18596;\r
-wire iraeaf9;\r
-wire ec10c6f;\r
-wire gb6f0c9;\r
-wire dobd9a4;\r
-wire al5e34f;\r
-wire sj8e0d;\r
-wire uvc982f;\r
-wire fc2fa21;\r
-wire ldf336a;\r
-wire cb8011e;\r
-wire fnc7d4e;\r
-wire rt5fa3a;\r
-wire bld7356;\r
-wire db84238;\r
-wire vx960d;\r
-wire jc760c3;\r
-wire zzb061b;\r
-wire ana12fe;\r
-wire mt186f3;\r
-wire kdc379d;\r
-wire fn74e8d;\r
-wire uide76b;\r
-wire thf3b58;\r
-wire ofd3065;\r
-wire shed630;\r
-wire pf6b185;\r
-wire nt9f2f;\r
-wire yxc6172;\r
-wire pu30b95;\r
-wire xjf30e3;\r
-wire ecaad5;\r
-wire fad51e7;\r
-wire ksbc8d7;\r
-wire ipccfc7;\r
-wire ng86878;\r
-wire ls960a9;\r
-wire rt40b5d;\r
-wire ks5aef;\r
-wire xl13484;\r
-wire vv6bbcf;\r
-wire lq5de7f;\r
-wire eca69e9;\r
-wire ps79fd0;\r
-wire xwcfe83;\r
-wire ip4bdc0;\r
-wire sufa0d5;\r
-wire vid06a9;\r
-wire db2d4da;\r
-wire wy1aa5b;\r
-wire lqd52d9;\r
-wire sue0cf8;\r
-wire uv4b659;\r
-wire aycb870;\r
-wire cb3c91c;\r
-wire oh9068d;\r
-reg [17 : 0] icc175e;\r
-reg ngbaf0;\r
-reg fa5d782;\r
-reg faebc13;\r
-reg of5e09b;\r
-reg uif04dc;\r
-reg co826e0;\r
-reg [9 : 0] xl13701;\r
-reg [9 : 0] nt9b80e;\r
-reg puad6d2;\r
-reg rt6b693;\r
-reg cz5b49e;\r
-reg dmda4f4;\r
-reg nrd27a2;\r
-reg je93d16;\r
-reg jr9e8b3;\r
-reg lqf459f;\r
-reg jea2cfa;\r
-reg rv167d3;\r
-reg oub3e9e;\r
-reg ir9f4f0;\r
-reg ykfa784;\r
-reg shd3c21;\r
-reg db9e10d;\r
-reg kqf086e;\r
-reg hd84371;\r
-reg ec21b8e;\r
-reg yzdc70;\r
-reg vv6e385;\r
-reg jp71c2e;\r
-reg zz8e177;\r
-reg cz70bbf;\r
-reg ux85dfd;\r
-reg ie2efed;\r
-reg kq77f69;\r
-reg dbbfb48;\r
-reg czfda46;\r
-reg yxed235;\r
-reg jc691ad;\r
-reg tu48d6b;\r
-reg ea46b5b;\r
-reg hq35ad8;\r
-reg hqad6c3;\r
-reg fn6b61b;\r
-reg kd5b0de;\r
-reg rtd86f4;\r
-reg yxc37a7;\r
-reg pu1bd3d;\r
-reg gode9eb;\r
-reg nef4f59;\r
-reg doa7acb;\r
-reg vx3d65b;\r
-reg pseb2de;\r
-reg kq596f2;\r
-reg sucb791;\r
-reg yx5bc89;\r
-reg ayde44d;\r
-reg off2268;\r
-reg nt91345;\r
-reg ng89a2f;\r
-reg jc4d17b;\r
-reg yk68bda;\r
-reg hb45ed0;\r
-reg je2f687;\r
-reg rt7b43a;\r
-reg neda1d7;\r
-reg ned0eba;\r
-reg ie875d2;\r
-reg ri3ae91;\r
-reg ldd748a;\r
-reg vxba456;\r
-reg vvd22b7;\r
-reg xl915be;\r
-reg qv8adf7;\r
-reg cm56fbc;\r
-reg dob7de1;\r
-reg yzbef0a;\r
-reg off7854;\r
-reg gqbc2a4;\r
-reg zke1520;\r
-reg mga903;\r
-reg yx54818;\r
-reg uxa40c4;\r
-reg zm20625;\r
-reg ph312b;\r
-reg wl1895f;\r
-reg goc4afc;\r
-reg ba257e1;\r
-reg co2bf0b;\r
-reg rt5f859;\r
-reg zxfc2cf;\r
-reg vie167e;\r
-reg hqb3f3;\r
-reg me59f9b;\r
-reg facfcd8;\r
-reg vv7e6c2;\r
-reg vvf3617;\r
-reg rv9b0bf;\r
-reg vvd85fe;\r
-reg fnc2ff7;\r
-reg qv17fbe;\r
-reg ntbfdf5;\r
-reg dmfefae;\r
-reg czf7d72;\r
-reg qvbeb94;\r
-reg ayf5ca4;\r
-reg epae521;\r
-reg ay7290c;\r
-reg bn94860;\r
-reg sja4306;\r
-reg ie21835;\r
-reg fpc1a8;\r
-reg uv60d46;\r
-reg xl6a34;\r
-reg do351a6;\r
-reg xya8d32;\r
-reg ww46992;\r
-reg uk34c90;\r
-reg gqa6481;\r
-reg ph32408;\r
-reg sw92047;\r
-reg yz90238;\r
-reg zz811c5;\r
-reg ux8e2e;\r
-reg ne47175;\r
-reg hd38bab;\r
-reg lqc5d5f;\r
-reg ou2eafb;\r
-reg ip757d9;\r
-reg mtabecc;\r
-reg th5f665;\r
-reg jcfb32e;\r
-reg czd9973;\r
-reg enccb9c;\r
-reg qt65ce5;\r
-reg ou2e72c;\r
-reg dm73960;\r
-reg xy9cb02;\r
-reg ose5812;\r
-reg an2c090;\r
-reg al60485;\r
-reg wl242d;\r
-reg an1216d;\r
-reg kf90b6c;\r
-reg mt85b64;\r
-reg zz2db25;\r
-reg me6d92e;\r
-reg ne6c970;\r
-reg xj64b82;\r
-reg tw25c16;\r
-reg mg2e0b2;\r
-reg of70590;\r
-reg gq82c84;\r
-reg zz16420;\r
-reg bab2106;\r
-reg mt90833;\r
-reg db8419c;\r
-reg zm20ce6;\r
-reg lf6732;\r
-reg qv33997;\r
-reg xy9ccbc;\r
-reg rte65e2;\r
-reg zz32f16;\r
-reg qi978b6;\r
-reg ksbc5b1;\r
-reg gbe2d88;\r
-reg tj16c45;\r
-reg ieb622f;\r
-reg qvb1179;\r
-reg wy88bcc;\r
-reg fn45e61;\r
-reg tw2f30f;\r
-reg rg7987a;\r
-reg ofcc3d3;\r
-reg pf61e9c;\r
-reg gqf4e6;\r
-reg gb7a731;\r
-reg end398d;\r
-reg tw9cc6d;\r
-reg lde636a;\r
-reg aa31b56;\r
-reg co8dab1;\r
-reg yk6d589;\r
-reg kd6ac49;\r
-reg ay5624d;\r
-reg kfb1268;\r
-reg ba89344;\r
-reg me49a22;\r
-reg by4d111;\r
-reg me6888a;\r
-reg of44450;\r
-reg lf22284;\r
-reg ba11426;\r
-reg wl8a133;\r
-reg fn5099d;\r
-reg zz84cee;\r
-reg yz26777;\r
-reg cb33bbc;\r
-reg ou9dde4;\r
-reg vieef20;\r
-reg kq77903;\r
-reg aabc818;\r
-reg hoe40c1;\r
-reg zm2060b;\r
-reg ph305b;\r
-reg wl182df;\r
-reg kqc16fd;\r
-reg dob7e8;\r
-reg ip5bf43;\r
-reg dmdfa1d;\r
-reg qtfd0eb;\r
-reg cze875c;\r
-reg os43ae5;\r
-reg kf1d728;\r
-reg tueb945;\r
-reg ui5ca2b;\r
-reg qge5158;\r
-reg vx28ac1;\r
-reg jp4560e;\r
-reg uk2b076;\r
-reg zk583b0;\r
-reg icc1d83;\r
-reg riec19;\r
-reg lq760ca;\r
-reg phb0653;\r
-reg pu8329e;\r
-reg xl194f3;\r
-reg tuca79f;\r
-reg ea53cfb;\r
-reg vx9e7d9;\r
-reg blf3ece;\r
-reg ir9f676;\r
-reg zkfb3b4;\r
-reg ald9da3;\r
-reg meced1c;\r
-reg xw768e0;\r
-reg cbb4702;\r
-reg oua3814;\r
-reg fp1c0a1;\r
-reg eae050f;\r
-reg cb2879;\r
-reg ri143cc;\r
-reg uxa1e63;\r
-reg ukf31c;\r
-reg ne798e1;\r
-reg ipcc70b;\r
-reg rg6385c;\r
-reg db1c2e3;\r
-reg pse171f;\r
-reg lsb8fb;\r
-reg os5c7da;\r
-reg ble3ed1;\r
-reg co1f68f;\r
-reg dmfb478;\r
-reg fada3c3;\r
-reg ayd1e1a;\r
-reg kf8f0d0;\r
-reg kq78685;\r
-reg gbc3428;\r
-reg aa1a145;\r
-reg ned0a28;\r
-reg kf85142;\r
-reg fp28a14;\r
-reg ld450a6;\r
-reg nt28536;\r
-reg zk429b7;\r
-reg tw14dba;\r
-reg eca6dd2;\r
-reg cb36e91;\r
-reg pub748c;\r
-reg vxba463;\r
-reg vvd231f;\r
-reg xl918fe;\r
-reg ls8c7f6;\r
-reg ps63fb2;\r
-reg ks1fd93;\r
-reg tufec99;\r
-reg blf64ca;\r
-reg lsb2657;\r
-reg ng932bb;\r
-reg je995da;\r
-reg lqcaed3;\r
-reg ps5769a;\r
-reg anbb4d2;\r
-reg hoda695;\r
-reg shd34aa;\r
-reg yz9a554;\r
-reg zxd2aa4;\r
-reg gd95527;\r
-reg lfaa93d;\r
-reg kd549ef;\r
-reg mta4f7c;\r
-reg lf27be4;\r
-reg hd3df27;\r
-reg kqef93f;\r
-reg by7c9f9;\r
-reg pse4fcb;\r
-reg jr27e5a;\r
-reg pu3f2d7;\r
-reg zxf96bb;\r
-reg uicb5de;\r
-reg pf5aef1;\r
-reg jpd778f;\r
-reg epbbc7e;\r
-reg icde3f4;\r
-reg zkf1fa0;\r
-reg wl8fd03;\r
-reg [2047:0] shdc077;\r
-wire [306:0] eae03bd;\r
-localparam ba1de9 = 307,ngef4b = 32'hfdffca8b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-AND2 gq98434 (.A(ie1f767), .B(uk10d0f), .Z(ng86878)); INV aa343c2 (.A(ana1e10), .Z(uk10d0f)); AND2 go78421 (.A(zkfbb38), .B(mg10847), .Z(db84238)); INV ym211c6 (.A(gd8e31), .Z(mg10847)); OR2 vx38c6b (.A(xjdd9c2), .B(rtece16), .Z(ou8d7e9)); XOR2 pf6bf48 (.A(rt5fa47), .B(yxfd23f), .Z(pfe91fc)); XOR2 ps48fe7 (.A(yxfd23f), .B(tw3f9da), .Z(blfced2)); XOR2 qte7697 (.A(tw3f9da), .B(psda5e1), .Z(fnd2f0a)); XOR2 aa97857 (.A(psda5e1), .B(vie15c8), .Z(gqae43)); XOR2 by57218 (.A(vie15c8), .B(dzc8610), .Z(cm43086)); XOR2 wl18431 (.A(dzc8610), .B(ec10c6f), .Z(pu86378)); XOR2 uk31bc3 (.A(ec10c6f), .B(gb6f0c9), .Z(qg7864c)); XOR2 czc3260 (.A(gb6f0c9), .B(uvc982f), .Z(me4c17d)); XOR2 yx60be8 (.A(uvc982f), .B(fc2fa21), .Z(me7d10b)); XOR2 wje8858 (.A(fc2fa21), .B(ym21624), .Z(fcb121)); XOR2 xw5890b (.A(osc485a), .B(mg242d1), .Z(mg21689)); XOR2 ngb449 (.A(mg242d1), .B(wwd125e), .Z(hq892f1)); XOR2 ic4978a (.A(wwd125e), .B(uv5e284), .Z(rgf1424)); XOR2 gd8a122 (.A(uv5e284), .B(ph848ae), .Z(uk24577)); XOR2 bn22bb9 (.A(ph848ae), .B(anaee78), .Z(yk773c5)); XOR2 mgb9e29 (.A(anaee78), .B(ay78a4b), .Z(hoc5259)); XOR2 gd292ca (.A(ay78a4b), .B(kd4b2a8), .Z(kq59545)); XOR2 tucaa29 (.A(kd4b2a8), .B(lsa8a57), .Z(hb452ba)); XOR2 gd295d6 (.A(lsa8a57), .B(ho575ae), .Z(phbad72)); XOR2 uvd6b96 (.A(ho575ae), .B(anae5af), .Z(ui72d7c)); defparam do96be0.initval = 16'h6996 ; ROM16X1A do96be0 (.AD3(fpaf81f), .AD2(ne7c0ff), .AD1(cme07fa), .AD0(nt3fd1), .DO0(aa1fe8e)); defparam qgff471.initval = 16'h6996 ; ROM16X1A qgff471 (.AD3(med1c49), .AD2(db8e248), .AD1(jp71247), .AD0(tw8923e), .DO0(ay491f2)); defparam fa48f90.initval = 16'h6996 ; ROM16X1A fa48f90 (.AD3(cme07fa), .AD2(nt3fd1), .AD1(oh9068d), .AD0(oh9068d), .DO0(qi1a36b)); defparam kqd1b58.initval = 16'h6996 ; ROM16X1A kqd1b58 (.AD3(ne7c0ff), .AD2(cme07fa), .AD1(nt3fd1), .AD0(oh9068d), .DO0(ba139a)); defparam lf9cd2.initval = 16'h6996 ; ROM16X1A lf9cd2 (.AD3(tw8923e), .AD2(fpaf81f), .AD1(ne7c0ff), .AD0(qi1a36b), .DO0(xybd739)); defparam faeb9ca.initval = 16'h6996 ; ROM16X1A faeb9ca (.AD3(jp71247), .AD2(tw8923e), .AD1(fpaf81f), .AD0(ba139a), .DO0(wy98918)); defparam goc48c0.initval = 16'h6996 ; ROM16X1A goc48c0 (.AD3(db8e248), .AD2(jp71247), .AD1(tw8923e), .AD0(aa1fe8e), .DO0(ph9952)); defparam yk4ca97.initval = 16'h6996 ; ROM16X1A yk4ca97 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(oh9068d), .AD0(oh9068d), .DO0(jpcd4c1)); defparam al6a60e.initval = 16'h6996 ; ROM16X1A al6a60e (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(rie809), .AD0(oh9068d), .DO0(bna0256)); defparam do12b7.initval = 16'h6996 ; ROM16X1A do12b7 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(rib75b1), .AD0(rie809), .DO0(ofd6c5e)); defparam ukb62f5.initval = 16'h6996 ; ROM16X1A ukb62f5 (.AD3(nt8bd4c), .AD2(rib75b1), .AD1(rie809), .AD0(oh9068d), .DO0(su4cd40)); defparam xw66a01.initval = 16'h6996 ; ROM16X1A xw66a01 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(su4cd40), .AD0(oh9068d), .DO0(ld5a793)); defparam yxd3c9e.initval = 16'h6996 ; ROM16X1A yxd3c9e (.AD3(gbf27ae), .AD2(zm93d75), .AD1(hd9ebab), .AD0(uif5d5f), .DO0(iraeaf9)); defparam mr757cd.initval = 16'h6996 ; ROM16X1A mr757cd (.AD3(pf5f365), .AD2(fnf9b2e), .AD1(xjcd977), .AD0(lq6cbbf), .DO0(gb65dfa)); defparam mg2efd4.initval = 16'h6996 ; ROM16X1A mg2efd4 (.AD3(hd9ebab), .AD2(uif5d5f), .AD1(oh9068d), .AD0(oh9068d), .DO0(sj8e0d)); defparam xw4706d.initval = 16'h6996 ; ROM16X1A xw4706d (.AD3(zm93d75), .AD2(hd9ebab), .AD1(uif5d5f), .AD0(oh9068d), .DO0(al5e34f)); defparam nef1a7c.initval = 16'h6996 ; ROM16X1A nef1a7c (.AD3(lq6cbbf), .AD2(gbf27ae), .AD1(zm93d75), .AD0(sj8e0d), .DO0(ux18596)); defparam xjc2cb5.initval = 16'h6996 ; ROM16X1A xjc2cb5 (.AD3(xjcd977), .AD2(lq6cbbf), .AD1(gbf27ae), .AD0(al5e34f), .DO0(vi764fd)); defparam pub27eb.initval = 16'h6996 ; ROM16X1A pub27eb (.AD3(fnf9b2e), .AD2(xjcd977), .AD1(lq6cbbf), .AD0(iraeaf9), .DO0(medbb14)); defparam lddd8a1.initval = 16'h6996 ; ROM16X1A lddd8a1 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(oh9068d), .AD0(oh9068d), .DO0(ay772e2)); defparam cob9711.initval = 16'h6996 ; ROM16X1A cob9711 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(ng1100c), .AD0(oh9068d), .DO0(zx40318)); defparam tw18c6.initval = 16'h6996 ; ROM16X1A tw18c6 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(mrc6794), .AD0(ng1100c), .DO0(lf9e52c)); defparam yxf2966.initval = 16'h6996 ; ROM16X1A yxf2966 (.AD3(vxa59a6), .AD2(mrc6794), .AD1(ng1100c), .AD0(oh9068d), .DO0(swa6d19)); defparam kf368c9.initval = 16'h6996 ; ROM16X1A kf368c9 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(swa6d19), .AD0(oh9068d), .DO0(xj641e9)); XOR2 xy20f4f (.A(ym21624), .B(uif5d5f), .Z(jpe9ea6)); XOR2 rt4f536 (.A(nt3fd1), .B(anae5af), .Z(iea6de0)); defparam ir36f01.initval = 16'h0410 ; ROM16X1A ir36f01 (.AD3(iebc062), .AD2(anae5af), .AD1(nt3fd1), .AD0(oh9068d), .DO0(su6205e)); defparam ec102f0.initval = 16'h1004 ; ROM16X1A ec102f0 (.AD3(iebc062), .AD2(anae5af), .AD1(nt3fd1), .AD0(oh9068d), .DO0(fce507)); defparam ww7283b.initval = 16'h0140 ; ROM16X1A ww7283b (.AD3(bna0ec7), .AD2(ym21624), .AD1(uif5d5f), .AD0(oh9068d), .DO0(fnc7d4e)); defparam ou3ea76.initval = 16'h4001 ; ROM16X1A ou3ea76 (.AD3(bna0ec7), .AD2(ym21624), .AD1(uif5d5f), .AD0(oh9068d), .DO0(cb8011e)); INV qi8f4 (.A(pu30b95), .Z(twb7f1d)); AND2 vk1e855 (.A(nga760e), .B(twb7f1d), .Z(ecaad5)); AND2 nr556a8 (.A(nga760e), .B(pu30b95), .Z(fad51e7)); defparam baa8f3b.CSDECODE_B = "0b000" ; defparam baa8f3b.CSDECODE_A = "0b000" ; defparam baa8f3b.WRITEMODE_B = "NORMAL" ; defparam baa8f3b.WRITEMODE_A = "NORMAL" ; defparam baa8f3b.GSR = "ENABLED" ; defparam baa8f3b.REGMODE_B = "NOREG" ; defparam baa8f3b.REGMODE_A = "NOREG" ; defparam baa8f3b.DATA_WIDTH_B = 18 ; defparam baa8f3b.DATA_WIDTH_A = 18 ; DP16KC baa8f3b (.DIA0(uve78fb[0]), .DIA1(uve78fb[1]), .DIA2(uve78fb[2]), .DIA3(uve78fb[3]), .DIA4(uve78fb[4]), .DIA5(uve78fb[5]), .DIA6(uve78fb[6]), .DIA7(uve78fb[7]), .DIA8(uve78fb[8]), .DIA9(uve78fb[9]), .DIA10(uve78fb[10]), .DIA11(uve78fb[11]), .DIA12(uve78fb[12]), .DIA13(uve78fb[13]), .DIA14(uve78fb[14]), .DIA15(uve78fb[15]), .DIA16(uve78fb[16]), .DIA17(uve78fb[17]), .ADA0(oh3c44c), .ADA1(oh3c44c), .ADA2(oh9068d), .ADA3(oh9068d), .ADA4(me4c91b), .ADA5(dz648d9), .ADA6(ou246ce), .ADA7(ep23671), .ADA8(xy1b38c), .ADA9(qtd9c62), .ADA10(kqce314), .ADA11(nr718a1), .ADA12(do8c50f), .ADA13(cm6287a), .CEA(ng86878), .CLKA(an3c7dd), .OCEA(ng86878), .WEA(oh3c44c), .CSA0(oh9068d), .CSA1(oh9068d), .CSA2(oh9068d), .RSTA(xjdd9c2), .DIB0(oh9068d), .DIB1(oh9068d), .DIB2(oh9068d), .DIB3(oh9068d), .DIB4(oh9068d), .DIB5(oh9068d), .DIB6(oh9068d), .DIB7(oh9068d), .DIB8(oh9068d), .DIB9(oh9068d), .DIB10(oh9068d), .DIB11(oh9068d), .DIB12(oh9068d), .DIB13(oh9068d), .DIB14(oh9068d), .DIB15(oh9068d), .DIB16(oh9068d), .DIB17(oh9068d), .ADB0(oh9068d), .ADB1(oh9068d), .ADB2(oh9068d), .ADB3(oh9068d), .ADB4(yx4e2a2), .ADB5(vv71515), .ADB6(mt8a8ae), .ADB7(yx54574), .ADB8(xya2ba5), .ADB9(wy15d2b), .ADB10(epae958), .ADB11(hb74ac5), .ADB12(jra562f), .ADB13(ou2b17f), .CEB(db84238), .CLKB(fne3eec), .OCEB(db84238), .WEB(oh9068d), .CSB0(oh9068d), .CSB1(oh9068d), .CSB2(oh9068d), .RSTB(xjdd9c2), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOA9(), .DOA10(), .DOA11(), .DOA12(), .DOA13(), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(blc2d86[0]), .DOB1(blc2d86[1]), .DOB2(blc2d86[2]), .DOB3(blc2d86[3]), .DOB4(blc2d86[4]), .DOB5(blc2d86[5]), .DOB6(blc2d86[6]), .DOB7(blc2d86[7]), .DOB8(blc2d86[8]), .DOB9(blc2d86[9]), .DOB10(blc2d86[10]), .DOB11(blc2d86[11]), .DOB12(blc2d86[12]), .DOB13(blc2d86[13]), .DOB14(blc2d86[14]), .DOB15(blc2d86[15]), .DOB16(blc2d86[16]), .DOB17(blc2d86[17]))\r
- ; FD1P3BX uvfd113 (.D(mre2814), .SP(ng86878), .CK(an3c7dd), .PD(xjdd9c2), .Q(rt5fa47)) ; FD1P3DX rge49ba (.D(ld5f8b9), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(yxfd23f)) ; FD1P3DX wl90bfe (.D(mef5856), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(tw3f9da)) ; FD1P3DX lfa5713 (.D(vv4f023), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(psda5e1)) ; FD1P3DX hbf933c (.D(yxc3544), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(vie15c8)) ; FD1P3DX ba3526f (.D(al4b55d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dzc8610)) ; FD1P3DX qgd12e5 (.D(hb7baa4), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ec10c6f)) ; FD1P3DX th4a80d (.D(mgb992f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(gb6f0c9)) ; FD1P3DX kd75eef (.D(fn6e49f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(uvc982f)) ; FD1P3DX faeed89 (.D(uk8875a), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fc2fa21)) ; FD1P3DX nr5a315 (.D(wy559d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ym21624)) ; FD1P3DX mr70444 (.D(pfe91fc), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fa69a9c)) ; FD1P3DX ou21669 (.D(blfced2), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fp942e5)) ; FD1P3DX of4b198 (.D(fnd2f0a), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(eaea018)) ; FD1P3DX xy2ab42 (.D(gqae43), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(gd3cf5c)) ; FD1P3DX rv9e65f (.D(cm43086), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ld6e606)) ; FD1P3DX uvf763a (.D(pu86378), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(pu997a9)) ; FD1P3DX hqaddd2 (.D(qg7864c), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dmc506a)) ; FD1P3DX uk973f1 (.D(me4c17d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(twbd919)) ; FD1P3DX en415d0 (.D(me7d10b), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ipf79c5)) ; FD1P3DX vk205d6 (.D(fcb121), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(zzceee)) ; FD1P3DX ls9c9a0 (.D(ym21624), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(tuc0cca)) ; FD1P3DX vi478a0 (.D(rt5fa47), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(me4c91b)) ; FD1P3DX hda57e2 (.D(yxfd23f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dz648d9)) ; FD1P3DX hocfd61 (.D(tw3f9da), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ou246ce)) ; FD1P3DX irb13c0 (.D(psda5e1), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ep23671)) ; FD1P3DX ou1f0d5 (.D(vie15c8), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(xy1b38c)) ; FD1P3DX hq252d5 (.D(dzc8610), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(qtd9c62)) ; FD1P3DX kdedeea (.D(ec10c6f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(kqce314)) ; FD1P3DX sj26e64 (.D(gb6f0c9), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(nr718a1)) ; FD1P3DX ne79b92 (.D(uvc982f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(do8c50f)) ; FD1P3DX vife21d (.D(fc2fa21), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(cm6287a)) ; FD1P3DX dmd0156 (.D(ym21624), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(bna0ec7)) ; FD1P3BX she8601 (.D(uk34943), .SP(db84238), .CK(fne3eec), .PD(ou8d7e9), .Q(osc485a)) ; FD1P3DX jc4d4e2 (.D(rg63e74), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(mg242d1)) ; FD1P3DX cba172f (.D(xjc7184), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(wwd125e)) ; FD1P3DX dz500c0 (.D(qtfd7fa), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(uv5e284)) ; FD1P3DX ene7ae5 (.D(ym1f209), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ph848ae)) ; FD1P3DX fa73036 (.D(gd36998), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(anaee78)) ; FD1P3DX gocbd4b (.D(vx28a0b), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ay78a4b)) ; FD1P3DX bn28352 (.D(jeb78ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kd4b2a8)) ; FD1P3DX fnec8cb (.D(cb8510c), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(lsa8a57)) ; FD1P3DX ksbce2c (.D(co341f5), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ho575ae)) ; FD1P3DX ay67777 (.D(mg34010), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(anae5af)) ; FD1P3DX db6653 (.D(mg21689), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kq6dea3)) ; FD1P3DX pseb66c (.D(hq892f1), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ks24221)) ; FD1P3DX cba4eca (.D(rgf1424), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ne4d871)) ; FD1P3DX aa31aa0 (.D(uk24577), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kqde7bd)) ; FD1P3DX xj45bd5 (.D(yk773c5), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(hd378a0)) ; FD1P3DX jcf48be (.D(hoc5259), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ir857bb)) ; FD1P3DX suefb70 (.D(kq59545), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(uxdb2a)) ; FD1P3DX ic4cd37 (.D(hb452ba), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(vi42afb)) ; FD1P3DX su593c1 (.D(phbad72), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(qi8dcd0)) ; FD1P3DX kd6f03b (.D(ui72d7c), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ps738fb)) ; FD1P3DX tj3a29 (.D(anae5af), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(qv9f0d5)) ; FD1P3DX mgacd25 (.D(osc485a), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(yx4e2a2)) ; FD1P3DX jr198f9 (.D(mg242d1), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(vv71515)) ; FD1P3DX gqa31c6 (.D(wwd125e), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(mt8a8ae)) ; FD1P3DX nt27f5f (.D(uv5e284), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(yx54574)) ; FD1P3DX osd47c8 (.D(ph848ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(xya2ba5)) ; FD1P3DX vi48da6 (.D(anaee78), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(wy15d2b)) ; FD1P3DX qgc4a28 (.D(ay78a4b), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(epae958)) ; FD1P3DX mr5ede2 (.D(kd4b2a8), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(hb74ac5)) ; FD1P3DX os72144 (.D(lsa8a57), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(jra562f)) ; FD1P3DX th64d07 (.D(ho575ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ou2b17f)) ; FD1P3DX fca8d00 (.D(anae5af), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(iebc062)) ; FD1S3DX ux80e29 (.D(fa69a9c), .CK(fne3eec), .CD(xjdd9c2), .Q(ld454ea)) ; FD1S3DX yx6f518 (.D(fp942e5), .CK(fne3eec), .CD(xjdd9c2), .Q(pub2248)) ; FD1S3DX wy21109 (.D(eaea018), .CK(fne3eec), .CD(xjdd9c2), .Q(uk1f410)) ; FD1S3DX jc6c38b (.D(gd3cf5c), .CK(fne3eec), .CD(xjdd9c2), .Q(fc164c)) ; FD1S3DX rtf3de8 (.D(ld6e606), .CK(fne3eec), .CD(xjdd9c2), .Q(bn13340)) ; FD1S3DX cobc506 (.D(pu997a9), .CK(fne3eec), .CD(xjdd9c2), .Q(zz32c7f)) ; FD1S3DX mg2bddc (.D(dmc506a), .CK(fne3eec), .CD(xjdd9c2), .Q(kdf2b23)) ; FD1S3DX me6d955 (.D(twbd919), .CK(fne3eec), .CD(xjdd9c2), .Q(pse41ee)) ; FD1S3DX mg157da (.D(ipf79c5), .CK(fne3eec), .CD(xjdd9c2), .Q(an9a9d3)) ; FD1S3DX jp6e681 (.D(zzceee), .CK(fne3eec), .CD(xjdd9c2), .Q(qte84e9)) ; FD1S3DX pu9c7da (.D(tuc0cca), .CK(fne3eec), .CD(xjdd9c2), .Q(rt6be72)) ; FD1S3DX mrf86ac (.D(kq6dea3), .CK(an3c7dd), .CD(ou8d7e9), .Q(anbee41))\r
- ; FD1S3DX ux29433 (.D(ks24221), .CK(an3c7dd), .CD(ou8d7e9), .Q(cz651af)) ; FD1S3DX nr7e701 (.D(ne4d871), .CK(an3c7dd), .CD(ou8d7e9), .Q(lqee0f9)) ; FD1S3DX jpf32c7 (.D(kqde7bd), .CK(an3c7dd), .CD(ou8d7e9), .Q(kd54432)) ; FD1S3DX shd959b (.D(hd378a0), .CK(an3c7dd), .CD(ou8d7e9), .Q(hdaa0f5)) ; FD1S3DX xj503f8 (.D(ir857bb), .CK(an3c7dd), .CD(ou8d7e9), .Q(os774cd)) ; FD1S3DX qtf8b73 (.D(uxdb2a), .CK(an3c7dd), .CD(ou8d7e9), .Q(xj4f8b2)) ; FD1S3DX sh5ec8b (.D(vi42afb), .CK(an3c7dd), .CD(ou8d7e9), .Q(lsb2b92)) ; FD1S3DX dz7bf90 (.D(qi8dcd0), .CK(an3c7dd), .CD(ou8d7e9), .Q(hd94841)) ; FD1S3DX zz9bb1d (.D(ps738fb), .CK(an3c7dd), .CD(ou8d7e9), .Q(wj7532a)) ; FD1S3DX kdf770e (.D(qv9f0d5), .CK(an3c7dd), .CD(ou8d7e9), .Q(nta035d)) ; FD1S3DX en654a8 (.D(ld454ea), .CK(fne3eec), .CD(xjdd9c2), .Q(nt8bd4c)) ; FD1S3DX ls2a756 (.D(pub2248), .CK(fne3eec), .CD(xjdd9c2), .Q(rib75b1)) ; FD1S3DX vx91243 (.D(uk1f410), .CK(fne3eec), .CD(xjdd9c2), .Q(rie809)) ; FD1S3DX qgfa080 (.D(fc164c), .CK(fne3eec), .CD(xjdd9c2), .Q(med1c49)) ; FD1S3DX pub262 (.D(bn13340), .CK(fne3eec), .CD(xjdd9c2), .Q(db8e248)) ; FD1S3DX ri99a06 (.D(zz32c7f), .CK(fne3eec), .CD(xjdd9c2), .Q(jp71247)) ; FD1S3DX ri963fe (.D(kdf2b23), .CK(fne3eec), .CD(xjdd9c2), .Q(tw8923e)) ; FD1S3DX cb9591c (.D(pse41ee), .CK(fne3eec), .CD(xjdd9c2), .Q(fpaf81f)) ; FD1S3DX ls20f73 (.D(an9a9d3), .CK(fne3eec), .CD(xjdd9c2), .Q(ne7c0ff)) ; FD1S3DX qgd4e9d (.D(qte84e9), .CK(fne3eec), .CD(xjdd9c2), .Q(cme07fa)) ; FD1S3DX xw4274d (.D(rt6be72), .CK(fne3eec), .CD(xjdd9c2), .Q(nt3fd1)) ; FD1S3DX hb5f397 (.D(anbee41), .CK(an3c7dd), .CD(ou8d7e9), .Q(vxa59a6)) ; FD1S3DX enf720c (.D(cz651af), .CK(an3c7dd), .CD(ou8d7e9), .Q(mrc6794)) ; FD1S3DX nt28d7d (.D(lqee0f9), .CK(an3c7dd), .CD(ou8d7e9), .Q(ng1100c)) ; FD1S3DX gb707ca (.D(kd54432), .CK(an3c7dd), .CD(ou8d7e9), .Q(pf5f365)) ; FD1S3DX pua2195 (.D(hdaa0f5), .CK(an3c7dd), .CD(ou8d7e9), .Q(fnf9b2e)) ; FD1S3DX bl507ae (.D(os774cd), .CK(an3c7dd), .CD(ou8d7e9), .Q(xjcd977)) ; FD1S3DX ntba669 (.D(xj4f8b2), .CK(an3c7dd), .CD(ou8d7e9), .Q(lq6cbbf)) ; FD1S3DX ho7c596 (.D(lsb2b92), .CK(an3c7dd), .CD(ou8d7e9), .Q(gbf27ae)) ; FD1S3DX kf95c92 (.D(hd94841), .CK(an3c7dd), .CD(ou8d7e9), .Q(zm93d75)) ; FD1S3DX oha420e (.D(wj7532a), .CK(an3c7dd), .CD(ou8d7e9), .Q(hd9ebab)) ; FD1S3DX swa9954 (.D(nta035d), .CK(an3c7dd), .CD(ou8d7e9), .Q(uif5d5f)) ; FD1S3DX vk1aef (.D(bn1c13c), .CK(an3c7dd), .CD(xjdd9c2), .Q(rt40b5d)) ; FD1S3DX kddce86 (.D(qtc3827), .CK(an3c7dd), .CD(xjdd9c2), .Q(ks5aef)) ; FD1S3DX gda4691 (.D(shfd9a1), .CK(an3c7dd), .CD(xjdd9c2), .Q(vv6bbcf)) ; FD1S3DX lq6c1b1 (.D(aa1fb34), .CK(an3c7dd), .CD(xjdd9c2), .Q(lq5de7f)) ; FD1S3DX ay5cd66 (.D(goc4b98), .CK(an3c7dd), .CD(xjdd9c2), .Q(ps79fd0)) ; FD1S3DX ie87613 (.D(wy98973), .CK(an3c7dd), .CD(xjdd9c2), .Q(xwcfe83)) ; FD1S3DX qtc9ff3 (.D(xl1907b), .CK(an3c7dd), .CD(xjdd9c2), .Q(sufa0d5)) ; FD1S3DX dmee8f0 (.D(pu8320f), .CK(an3c7dd), .CD(xjdd9c2), .Q(vid06a9)) ; FD1S3DX ls1e282 (.D(gb4e680), .CK(an3c7dd), .CD(xjdd9c2), .Q(wy1aa5b)) ; FD1S3DX ks92bcc (.D(yma9cd0), .CK(an3c7dd), .CD(xjdd9c2), .Q(lqd52d9)) ; FD1S3DX zzcce6 (.D(ay5c741), .CK(an3c7dd), .CD(xjdd9c2), .Q(uv4b659)) ; FD1S3DX ntba8bf (.D(ie3e311), .CK(fne3eec), .CD(ou8d7e9), .Q(jc760c3)) ; FD1S3DX zkf1773 (.D(su67c62), .CK(fne3eec), .CD(ou8d7e9), .Q(zzb061b)) ; FD1S3DX end649d (.D(do83573), .CK(fne3eec), .CD(ou8d7e9), .Q(mt186f3)) ; FD1S3DX by630c7 (.D(psd06ae), .CK(fne3eec), .CD(ou8d7e9), .Q(kdc379d)) ; FD1S3DX lqd5b3a (.D(mga3d55), .CK(fne3eec), .CD(ou8d7e9), .Q(uide76b)) ; FD1S3DX ym9241e (.D(al547aa), .CK(fne3eec), .CD(ou8d7e9), .Q(thf3b58)) ; FD1S3DX cb80a90 (.D(do3f356), .CK(fne3eec), .CD(ou8d7e9), .Q(shed630)) ; FD1S3DX bn284a4 (.D(xjc7e6a), .CK(fne3eec), .CD(ou8d7e9), .Q(pf6b185)) ; FD1S3DX wy3bba6 (.D(xya8150), .CK(fne3eec), .CD(ou8d7e9), .Q(yxc6172)) ; FD1S3DX ri867c3 (.D(do47a1), .CK(fne3eec), .CD(ou8d7e9), .Q(pu30b95)) ; FD1S3DX mrdc92b (.D(dmf42ab), .CK(fne3eec), .CD(ou8d7e9), .Q(nga760e)) ; FD1S3BX gbe20c9 (.D(fc83261), .CK(fne3eec), .PD(ou8d7e9), .Q(gd8e31)) ; FD1S3DX pf617e8 (.D(rt5fa3a), .CK(an3c7dd), .CD(xjdd9c2), .Q(ana1e10)) ; FD1S3BX do3af23 (.D(ksbc8d7), .CK(fne3eec), .PD(ou8d7e9), .Q(zzb0db9)) ; FD1S3DX bld72e1 (.D(aycb870), .CK(an3c7dd), .CD(xjdd9c2), .Q(vk86dcf)) ; FADD2B fa4dd42 (.A0(oh9068d), .A1(oh3c44c), .B0(oh9068d), .B1(oh3c44c), .CI(oh9068d), .COUT(gd9f8df), .S0(), .S1()); CU2 gb70053 (.CI(gd9f8df), .PC0(rt5fa47), .PC1(yxfd23f), .CO(ay53911), .NC0(mre2814), .NC1(ld5f8b9)); CU2 xl22253 (.CI(ay53911), .PC0(tw3f9da), .PC1(psda5e1), .CO(qg53cd7), .NC0(mef5856), .NC1(vv4f023)); CU2 ux9ae77 (.CI(qg53cd7), .PC0(vie15c8), .PC1(dzc8610), .CO(qg77b88), .NC0(yxc3544), .NC1(al4b55d)); CU2 rt7101a (.CI(qg77b88), .PC0(ec10c6f), .PC1(gb6f0c9), .CO(co1ac37), .NC0(hb7baa4), .NC1(mgb992f)); CU2 fc86e67 (.CI(co1ac37), .PC0(uvc982f), .PC1(fc2fa21), .CO(me675cd), .NC0(fn6e49f), .NC1(uk8875a)); CU2 aab9a16 (.CI(me675cd), .PC0(ym21624), .PC1(oh9068d), .CO(xl1638a), .NC0(wy559d), .NC1()); FADD2B mr4b213 (.A0(oh9068d), .A1(oh3c44c), .B0(oh9068d), .B1(oh3c44c), .CI(oh9068d), .COUT(jpe9cf9), .S0(), .S1()); CU2 xl8e2b5 (.CI(jpe9cf9), .PC0(osc485a), .PC1(mg242d1), .CO(vxb5fa1), .NC0(uk34943), .NC1(rg63e74)); CU2 hof43fe (.CI(vxb5fa1), .PC0(wwd125e), .PC1(uv5e284), .CO(dmfe504), .NC0(xjc7184), .NC1(qtfd7fa)); CU2 rva08e7 (.CI(dmfe504), .PC0(ph848ae), .PC1(anaee78), .CO(mre7cae), .NC0(ym1f209), .NC1(gd36998)); CU2 an95d4c (.CI(mre7cae), .PC0(ay78a4b), .PC1(kd4b2a8), .CO(cm4c960), .NC0(vx28a0b), .NC1(jeb78ae)); CU2 kf2c072 (.CI(cm4c960), .PC0(lsa8a57), .PC1(ho575ae), .CO(yk72b5b), .NC0(cb8510c), .NC1(co341f5)); CU2 ld6b623 (.CI(yk72b5b), .PC0(anae5af), .PC1(oh9068d), .CO(wl23d30), .NC0(mg34010), .NC1()); FSUB2B hof4c2b (.A0(oh3c44c), .A1(rt5fa47), .B0(oh9068d), .B1(xj641e9), .BI(oh9068d), .BOUT(dzd8704), .S0(), .S1(bn1c13c)); FSUB2B yke09e7 (.A0(yxfd23f), .A1(tw3f9da), .B0(lf9e52c), .B1(zx40318), .BI(dzd8704), .BOUT(alc3f66), .S0(qtc3827), .S1(shfd9a1)); FSUB2B xjecd0d (.A0(psda5e1), .A1(vie15c8), .B0(ay772e2), .B1(medbb14), .BI(alc3f66), .BOUT(jc7312e), .S0(aa1fb34), .S1(goc4b98)); FSUB2B ba25cc1 (.A0(dzc8610), .A1(ec10c6f), .B0(vi764fd), .B1(ux18596), .BI(jc7312e), .BOUT(xj50641), .S0(wy98973), .S1(xl1907b)); FSUB2B vvc83df (.A0(gb6f0c9), .A1(uvc982f), .B0(iraeaf9), .B1(al5e34f), .BI(xj50641), .BOUT(ayf539a), .S0(pu8320f), .S1(gb4e680)); FSUB2B fa73405 (.A0(fc2fa21), .A1(jpe9ea6), .B0(sj8e0d), .B1(oh9068d), .BI(ayf539a), .BOUT(wl36ef1), .S0(yma9cd0), .S1(ay5c741)); FADD2B icff90e (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(wl36ef1), .COUT(), .S0(aaa6dde), .S1()); VHI the3a09 (.Z(oh3c44c)); FSUB2B gbe827d (.A0(oh3c44c), .A1(ld5a793), .B0(oh9068d), .B1(osc485a), .BI(oh9068d), .BOUT(dm6cf8c), .S0(), .S1(ie3e311)); FSUB2B tuf1889 (.A0(ofd6c5e), .A1(bna0256), .B0(mg242d1), .B1(wwd125e), .BI(dm6cf8c), .BOUT(xj5a0d5), .S0(su67c62), .S1(do83573)); FSUB2B co1ab9b (.A0(jpcd4c1), .A1(ph9952), .B0(uv5e284), .B1(ph848ae), .BI(xj5a0d5), .BOUT(jcca8f5), .S0(psd06ae), .S1(mga3d55)); FSUB2B ng1eaa9 (.A0(wy98918), .A1(xybd739), .B0(anaee78), .B1(ay78a4b), .BI(\r
-jcca8f5), .BOUT(by58fcd), .S0(al547aa), .S1(do3f356)); FSUB2B hbf9ab3 (.A0(aa1fe8e), .A1(ba139a), .B0(kd4b2a8), .B1(lsa8a57), .BI(by58fcd), .BOUT(fafea05), .S0(xjc7e6a), .S1(xya8150)); FSUB2B dz40a83 (.A0(qi1a36b), .A1(iea6de0), .B0(ho575ae), .B1(oh9068d), .BI(fafea05), .BOUT(uvd9701), .S0(do47a1), .S1(dmf42ab)); FADD2B dm79412 (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(uvd9701), .COUT(), .S0(ie3b2e0), .S1()); FADD2B nee495e (.A0(oh9068d), .A1(db84238), .B0(oh9068d), .B1(db84238), .CI(oh9068d), .COUT(kf90665), .S0(), .S1()); AGEB2 dzc2e84 (.A0(osc485a), .A1(mg242d1), .B0(ld5a793), .B1(ofd6c5e), .CI(kf90665), .GE(mg34ebd)); AGEB2 vka75e9 (.A0(wwd125e), .A1(uv5e284), .B0(bna0256), .B1(jpcd4c1), .CI(mg34ebd), .GE(ps52ebf)); AGEB2 co975fb (.A0(ph848ae), .A1(anaee78), .B0(ph9952), .B1(wy98918), .CI(ps52ebf), .GE(yxc6fde)); AGEB2 nt37ef4 (.A0(ay78a4b), .A1(kd4b2a8), .B0(xybd739), .B1(aa1fe8e), .CI(yxc6fde), .GE(vx37459)); AGEB2 rvba2cf (.A0(lsa8a57), .A1(ho575ae), .B0(ba139a), .B1(qi1a36b), .CI(vx37459), .GE(nrf9e15)); AGEB2 hocf0af (.A0(su6205e), .A1(oh9068d), .B0(fce507), .B1(oh9068d), .CI(nrf9e15), .GE(xjd8c37)); FADD2B qtc61be (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(xjd8c37), .COUT(), .S0(fc83261), .S1()); FADD2B vx3818d (.A0(oh9068d), .A1(ng86878), .B0(oh9068d), .B1(ng86878), .CI(oh9068d), .COUT(ho73e4e), .S0(), .S1()); AGEB2 th5ad04 (.A0(rt5fa47), .A1(yxfd23f), .B0(xj641e9), .B1(lf9e52c), .CI(ho73e4e), .GE(lf3d99f)); AGEB2 theccff (.A0(tw3f9da), .A1(psda5e1), .B0(zx40318), .B1(ay772e2), .CI(lf3d99f), .GE(off2943)); AGEB2 jr94a1c (.A0(vie15c8), .A1(dzc8610), .B0(medbb14), .B1(vi764fd), .CI(off2943), .GE(lf37e37)); AGEB2 lfbf1be (.A0(ec10c6f), .A1(gb6f0c9), .B0(ux18596), .B1(iraeaf9), .CI(lf37e37), .GE(dobd9a4)); AGEB2 hbecd23 (.A0(uvc982f), .A1(fc2fa21), .B0(al5e34f), .B1(sj8e0d), .CI(dobd9a4), .GE(ldf336a)); AGEB2 ng99b57 (.A0(fnc7d4e), .A1(oh9068d), .B0(cb8011e), .B1(oh9068d), .CI(ldf336a), .GE(bld7356)); FADD2B qib9ab6 (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(bld7356), .COUT(), .S0(rt5fa3a), .S1()); FADD2B go4cfd4 (.A0(oh9068d), .A1(db84238), .B0(oh9068d), .B1(db84238), .CI(oh9068d), .COUT(vx960d), .S0(), .S1()); AGEB2 yx7526e (.A0(ay670b6[0]), .A1(ay670b6[1]), .B0(jc760c3), .B1(zzb061b), .CI(vx960d), .GE(ana12fe)); AGEB2 xl97f5 (.A0(ay670b6[2]), .A1(ay670b6[3]), .B0(mt186f3), .B1(kdc379d), .CI(ana12fe), .GE(fn74e8d)); AGEB2 ria746f (.A0(ay670b6[4]), .A1(ay670b6[5]), .B0(uide76b), .B1(thf3b58), .CI(fn74e8d), .GE(ofd3065)); AGEB2 qi9832c (.A0(ay670b6[6]), .A1(ay670b6[7]), .B0(shed630), .B1(pf6b185), .CI(ofd3065), .GE(nt9f2f)); AGEB2 ld4f97f (.A0(ay670b6[8]), .A1(ay670b6[9]), .B0(yxc6172), .B1(pu30b95), .CI(nt9f2f), .GE(xjf30e3)); AGEB2 ec9871f (.A0(fad51e7), .A1(oh9068d), .B0(ecaad5), .B1(oh9068d), .CI(xjf30e3), .GE(ipccfc7)); FADD2B ui67e3d (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(ipccfc7), .COUT(), .S0(ksbc8d7), .S1()); FADD2B by790f2 (.A0(oh9068d), .A1(ng86878), .B0(oh9068d), .B1(ng86878), .CI(oh9068d), .COUT(ls960a9), .S0(), .S1()); AGEB2 lq5ddbc (.A0(rt40b5d), .A1(ks5aef), .B0(tj385b0[0]), .B1(tj385b0[1]), .CI(ls960a9), .GE(xl13484)); AGEB2 mt9a426 (.A0(vv6bbcf), .A1(lq5de7f), .B0(tj385b0[2]), .B1(tj385b0[3]), .CI(xl13484), .GE(eca69e9)); AGEB2 aa34f49 (.A0(ps79fd0), .A1(xwcfe83), .B0(tj385b0[4]), .B1(tj385b0[5]), .CI(eca69e9), .GE(ip4bdc0)); AGEB2 sh5ee04 (.A0(sufa0d5), .A1(vid06a9), .B0(tj385b0[6]), .B1(tj385b0[7]), .CI(ip4bdc0), .GE(db2d4da)); AGEB2 yx6a6d7 (.A0(wy1aa5b), .A1(lqd52d9), .B0(tj385b0[8]), .B1(tj385b0[9]), .CI(db2d4da), .GE(sue0cf8)); AGEB2 hd67c0 (.A0(uv4b659), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(sue0cf8), .GE(cb3c91c)); VLO xwe48e5 (.Z(oh9068d)); FADD2B kf23951 (.A0(oh9068d), .A1(oh9068d), .B0(oh9068d), .B1(oh9068d), .CI(cb3c91c), .COUT(), .S0(aycb870), .S1()); assign lf16c36 = hd38bab; assign wyb61b7 = lqc5d5f;\r
-always@* begin icc175e<={uve78fb>>1,eae03bd[0]};ngbaf0<=eae03bd[1];fa5d782<=eae03bd[2];faebc13<=eae03bd[3];of5e09b<=eae03bd[4];uif04dc<=eae03bd[5];co826e0<=eae03bd[6];xl13701<={ay670b6>>1,eae03bd[7]};nt9b80e<={tj385b0>>1,eae03bd[8]};puad6d2<=eae03bd[9];rt6b693<=eae03bd[10];cz5b49e<=eae03bd[11];dmda4f4<=eae03bd[12];nrd27a2<=eae03bd[13];je93d16<=eae03bd[14];jr9e8b3<=eae03bd[15];lqf459f<=eae03bd[16];jea2cfa<=eae03bd[17];rv167d3<=eae03bd[18];oub3e9e<=eae03bd[19];ir9f4f0<=eae03bd[20];ykfa784<=eae03bd[21];shd3c21<=eae03bd[22];db9e10d<=eae03bd[23];kqf086e<=eae03bd[24];hd84371<=eae03bd[25];ec21b8e<=eae03bd[26];yzdc70<=eae03bd[27];vv6e385<=eae03bd[28];jp71c2e<=eae03bd[29];zz8e177<=eae03bd[30];cz70bbf<=eae03bd[31];ux85dfd<=eae03bd[32];ie2efed<=eae03bd[33];kq77f69<=eae03bd[34];dbbfb48<=eae03bd[35];czfda46<=eae03bd[36];yxed235<=eae03bd[37];jc691ad<=eae03bd[38];tu48d6b<=eae03bd[39];ea46b5b<=eae03bd[40];hq35ad8<=eae03bd[41];hqad6c3<=eae03bd[42];fn6b61b<=eae03bd[43];kd5b0de<=eae03bd[44];rtd86f4<=eae03bd[45];yxc37a7<=eae03bd[46];pu1bd3d<=eae03bd[47];gode9eb<=eae03bd[48];nef4f59<=eae03bd[49];doa7acb<=eae03bd[50];vx3d65b<=eae03bd[51];pseb2de<=eae03bd[52];kq596f2<=eae03bd[53];sucb791<=eae03bd[54];yx5bc89<=eae03bd[55];ayde44d<=eae03bd[56];off2268<=eae03bd[57];nt91345<=eae03bd[58];ng89a2f<=eae03bd[59];jc4d17b<=eae03bd[60];yk68bda<=eae03bd[61];hb45ed0<=eae03bd[62];je2f687<=eae03bd[63];rt7b43a<=eae03bd[64];neda1d7<=eae03bd[65];ned0eba<=eae03bd[66];ie875d2<=eae03bd[67];ri3ae91<=eae03bd[68];ldd748a<=eae03bd[69];vxba456<=eae03bd[70];vvd22b7<=eae03bd[71];xl915be<=eae03bd[72];qv8adf7<=eae03bd[73];cm56fbc<=eae03bd[74];dob7de1<=eae03bd[75];yzbef0a<=eae03bd[76];off7854<=eae03bd[77];gqbc2a4<=eae03bd[78];zke1520<=eae03bd[79];mga903<=eae03bd[80];yx54818<=eae03bd[81];uxa40c4<=eae03bd[82];zm20625<=eae03bd[83];ph312b<=eae03bd[84];wl1895f<=eae03bd[85];goc4afc<=eae03bd[86];ba257e1<=eae03bd[87];co2bf0b<=eae03bd[88];rt5f859<=eae03bd[89];zxfc2cf<=eae03bd[90];vie167e<=eae03bd[91];hqb3f3<=eae03bd[92];me59f9b<=eae03bd[93];facfcd8<=eae03bd[94];vv7e6c2<=eae03bd[95];vvf3617<=eae03bd[96];rv9b0bf<=eae03bd[97];vvd85fe<=eae03bd[98];fnc2ff7<=eae03bd[99];qv17fbe<=eae03bd[100];ntbfdf5<=eae03bd[101];dmfefae<=eae03bd[102];czf7d72<=eae03bd[103];qvbeb94<=eae03bd[104];ayf5ca4<=eae03bd[105];epae521<=eae03bd[106];ay7290c<=eae03bd[107];bn94860<=eae03bd[108];sja4306<=eae03bd[109];ie21835<=eae03bd[110];fpc1a8<=eae03bd[111];uv60d46<=eae03bd[112];xl6a34<=eae03bd[113];do351a6<=eae03bd[114];xya8d32<=eae03bd[115];ww46992<=eae03bd[116];uk34c90<=eae03bd[117];gqa6481<=eae03bd[118];ph32408<=eae03bd[119];sw92047<=eae03bd[120];yz90238<=eae03bd[121];zz811c5<=eae03bd[122];ux8e2e<=eae03bd[123];ne47175<=eae03bd[124];hd38bab<=eae03bd[125];lqc5d5f<=eae03bd[126];ou2eafb<=eae03bd[127];ip757d9<=eae03bd[128];mtabecc<=eae03bd[129];th5f665<=eae03bd[130];jcfb32e<=eae03bd[131];czd9973<=eae03bd[132];enccb9c<=eae03bd[133];qt65ce5<=eae03bd[134];ou2e72c<=eae03bd[135];dm73960<=eae03bd[136];xy9cb02<=eae03bd[137];ose5812<=eae03bd[138];an2c090<=eae03bd[139];al60485<=eae03bd[140];wl242d<=eae03bd[141];an1216d<=eae03bd[142];kf90b6c<=eae03bd[143];mt85b64<=eae03bd[144];zz2db25<=eae03bd[145];me6d92e<=eae03bd[146];ne6c970<=eae03bd[147];xj64b82<=eae03bd[148];tw25c16<=eae03bd[149];mg2e0b2<=eae03bd[150];of70590<=eae03bd[151];gq82c84<=eae03bd[152];zz16420<=eae03bd[153];bab2106<=eae03bd[154];mt90833<=eae03bd[155];db8419c<=eae03bd[156];zm20ce6<=eae03bd[157];lf6732<=eae03bd[158];qv33997<=eae03bd[159];xy9ccbc<=eae03bd[160];rte65e2<=eae03bd[161];zz32f16<=eae03bd[162];qi978b6<=eae03bd[163];ksbc5b1<=eae03bd[164];gbe2d88<=eae03bd[165];tj16c45<=eae03bd[166];ieb622f<=eae03bd[167];qvb1179<=eae03bd[168];wy88bcc<=eae03bd[169];fn45e61<=eae03bd[170];tw2f30f<=eae03bd[171];rg7987a<=eae03bd[172];ofcc3d3<=eae03bd[173];pf61e9c<=eae03bd[174];gqf4e6<=eae03bd[175];gb7a731<=eae03bd[176];end398d<=eae03bd[177];tw9cc6d<=eae03bd[178];lde636a<=eae03bd[179];aa31b56<=eae03bd[180];co8dab1<=eae03bd[181];yk6d589<=eae03bd[182];kd6ac49<=eae03bd[183];ay5624d<=eae03bd[184];kfb1268<=eae03bd[185];ba89344<=eae03bd[186];me49a22<=eae03bd[187];by4d111<=eae03bd[188];me6888a<=eae03bd[189];of44450<=eae03bd[190];lf22284<=eae03bd[191];ba11426<=eae03bd[192];wl8a133<=eae03bd[193];fn5099d<=eae03bd[194];zz84cee<=eae03bd[195];yz26777<=eae03bd[196];cb33bbc<=eae03bd[197];ou9dde4<=eae03bd[198];vieef20<=eae03bd[199];kq77903<=eae03bd[200];aabc818<=eae03bd[201];hoe40c1<=eae03bd[202];zm2060b<=eae03bd[203];ph305b<=eae03bd[204];wl182df<=eae03bd[205];kqc16fd<=eae03bd[206];dob7e8<=eae03bd[207];ip5bf43<=eae03bd[208];dmdfa1d<=eae03bd[209];qtfd0eb<=eae03bd[210];cze875c<=eae03bd[211];os43ae5<=eae03bd[212];kf1d728<=eae03bd[213];tueb945<=eae03bd[214];ui5ca2b<=eae03bd[215];qge5158<=eae03bd[216];vx28ac1<=eae03bd[217];jp4560e<=eae03bd[218];uk2b076<=eae03bd[219];zk583b0<=eae03bd[220];icc1d83<=eae03bd[221];riec19<=eae03bd[222];lq760ca<=eae03bd[223];phb0653<=eae03bd[224];pu8329e<=eae03bd[225];xl194f3<=eae03bd[226];tuca79f<=eae03bd[227];ea53cfb<=eae03bd[228];vx9e7d9<=eae03bd[229];blf3ece<=eae03bd[230];ir9f676<=eae03bd[231];zkfb3b4<=eae03bd[232];ald9da3<=eae03bd[233];meced1c<=eae03bd[234];xw768e0<=eae03bd[235];cbb4702<=eae03bd[236];oua3814<=eae03bd[237];fp1c0a1<=eae03bd[238];eae050f<=eae03bd[239];cb2879<=eae03bd[240];ri143cc<=eae03bd[241];uxa1e63<=\r
-eae03bd[242];ukf31c<=eae03bd[243];ne798e1<=eae03bd[244];ipcc70b<=eae03bd[245];rg6385c<=eae03bd[246];db1c2e3<=eae03bd[247];pse171f<=eae03bd[248];lsb8fb<=eae03bd[249];os5c7da<=eae03bd[250];ble3ed1<=eae03bd[251];co1f68f<=eae03bd[252];dmfb478<=eae03bd[253];fada3c3<=eae03bd[254];ayd1e1a<=eae03bd[255];kf8f0d0<=eae03bd[256];kq78685<=eae03bd[257];gbc3428<=eae03bd[258];aa1a145<=eae03bd[259];ned0a28<=eae03bd[260];kf85142<=eae03bd[261];fp28a14<=eae03bd[262];ld450a6<=eae03bd[263];nt28536<=eae03bd[264];zk429b7<=eae03bd[265];tw14dba<=eae03bd[266];eca6dd2<=eae03bd[267];cb36e91<=eae03bd[268];pub748c<=eae03bd[269];vxba463<=eae03bd[270];vvd231f<=eae03bd[271];xl918fe<=eae03bd[272];ls8c7f6<=eae03bd[273];ps63fb2<=eae03bd[274];ks1fd93<=eae03bd[275];tufec99<=eae03bd[276];blf64ca<=eae03bd[277];lsb2657<=eae03bd[278];ng932bb<=eae03bd[279];je995da<=eae03bd[280];lqcaed3<=eae03bd[281];ps5769a<=eae03bd[282];anbb4d2<=eae03bd[283];hoda695<=eae03bd[284];shd34aa<=eae03bd[285];yz9a554<=eae03bd[286];zxd2aa4<=eae03bd[287];gd95527<=eae03bd[288];lfaa93d<=eae03bd[289];kd549ef<=eae03bd[290];mta4f7c<=eae03bd[291];lf27be4<=eae03bd[292];hd3df27<=eae03bd[293];kqef93f<=eae03bd[294];by7c9f9<=eae03bd[295];pse4fcb<=eae03bd[296];jr27e5a<=eae03bd[297];pu3f2d7<=eae03bd[298];zxf96bb<=eae03bd[299];uicb5de<=eae03bd[300];pf5aef1<=eae03bd[301];jpd778f<=eae03bd[302];epbbc7e<=eae03bd[303];icde3f4<=eae03bd[304];zkf1fa0<=eae03bd[305];wl8fd03<=eae03bd[306];end\r
-always@* begin shdc077[2047]<=an3c7dd;shdc077[2046]<=fne3eec;shdc077[2044]<=ie1f767;shdc077[2040]<=zkfbb38;shdc077[2032]<=xjdd9c2;shdc077[2030]<=vxb5fa1;shdc077[2028]<=tw8923e;shdc077[2017]<=rtece16;shdc077[2012]<=ym1f209;shdc077[2008]<=kdf2b23;shdc077[2005]<=fc83261;shdc077[1992]<=psd06ae;shdc077[1988]<=uxdb2a;shdc077[1987]<=ay670b6[0];shdc077[1977]<=gd36998;shdc077[1969]<=fpaf81f;shdc077[1962]<=xjd8c37;shdc077[1937]<=mga3d55;shdc077[1928]<=vi42afb;shdc077[1926]<=tj385b0[0];shdc077[1906]<=dmfe504;shdc077[1891]<=pse41ee;shdc077[1877]<=db84238;shdc077[1876]<=ho73e4e;shdc077[1866]<=lsb2b92;shdc077[1842]<=qg77b88;shdc077[1837]<=qtc3827;shdc077[1831]<=cb8510c;shdc077[1826]<=xj5a0d5;shdc077[1809]<=qi8dcd0;shdc077[1805]<=cm6287a;shdc077[1804]<=uk10d0f;shdc077[1803]<=me4c17d;shdc077[1801]<=ksbc8d7;shdc077[1764]<=vx28a0b;shdc077[1761]<=kqce314;shdc077[1748]<=gd3cf5c;shdc077[1746]<=xl1907b;shdc077[1739]<=ofd3065;shdc077[1734]<=ne7c0ff;shdc077[1733]<=ux18596;shdc077[1727]<=fc164c;shdc077[1707]<=vx960d;shdc077[1705]<=xj641e9;shdc077[1696]<=dmc506a;shdc077[1684]<=zm93d75;shdc077[1683]<=gb4e680;shdc077[1681]<=uvd9701;shdc077[1668]<=hoc5259;shdc077[1660]<=oh3c44c;shdc077[1636]<=fn6e49f;shdc077[1633]<=mrc6794;shdc077[1628]<=nt9f2f;shdc077[1627]<=shfd9a1;shdc077[1614]<=co341f5;shdc077[1607]<=xl1638a;shdc077[1604]<=al547aa;shdc077[1587]<=qte84e9;shdc077[1578]<=gb6f0c9;shdc077[1574]<=vid06a9;shdc077[1571]<=ps738fb;shdc077[1567]<=qi1a36b;shdc077[1563]<=oh9068d;shdc077[1562]<=bna0ec7;shdc077[1560]<=mg10847;shdc077[1558]<=me7d10b;shdc077[1555]<=pf5f365;shdc077[1554]<=ipccfc7;shdc077[1550]<=pfe91fc;shdc077[1548]<=yxc6fde;shdc077[1531]<=jp71247;shdc077[1493]<=rt5fa3a;shdc077[1484]<=hb7baa4;shdc077[1481]<=jeb78ae;shdc077[1475]<=nr718a1;shdc077[1474]<=ecaad5;shdc077[1464]<=xy1b38c;shdc077[1460]<=alc3f66;shdc077[1458]<=uide76b;shdc077[1448]<=ld6e606;shdc077[1444]<=jc7312e;shdc077[1431]<=shed630;shdc077[1420]<=an9a9d3;shdc077[1418]<=iraeaf9;shdc077[1417]<=ip4bdc0;shdc077[1411]<=ph848ae;shdc077[1406]<=db8e248;shdc077[1397]<=cb8011e;shdc077[1395]<=al4b55d;shdc077[1388]<=kdc379d;shdc077[1378]<=ps79fd0;shdc077[1373]<=fc2fa21;shdc077[1371]<=ana12fe;shdc077[1366]<=jc760c3;shdc077[1362]<=lf9e52c;shdc077[1354]<=yxfd23f;shdc077[1345]<=twbd919;shdc077[1334]<=medbb14;shdc077[1323]<=gd9f8df;shdc077[1321]<=zx40318;shdc077[1320]<=hd94841;shdc077[1318]<=xj50641;shdc077[1314]<=kf90665;shdc077[1300]<=nga760e;shdc077[1288]<=kq59545;shdc077[1287]<=zzceee;shdc077[1273]<=su67c62;shdc077[1257]<=lq6cbbf;shdc077[1253]<=anae5af;shdc077[1242]<=fa69a9c;shdc077[1240]<=vie15c8;shdc077[1234]<=fafea05;shdc077[1231]<=aaa6dde;shdc077[1224]<=uk8875a;shdc077[1219]<=uv4b659;shdc077[1218]<=cz651af;shdc077[1208]<=yxc6172;shdc077[1206]<=dzd8704;shdc077[1198]<=vv4f023;shdc077[1196]<=vv6bbcf;shdc077[1190]<=tw3f9da;shdc077[1186]<=wj7532a;shdc077[1180]<=cm4c960;shdc077[1177]<=ay5c741;shdc077[1167]<=ym21624;shdc077[1161]<=do3f356;shdc077[1160]<=ofd6c5e;shdc077[1150]<=rg63e74;shdc077[1131]<=pub2248;shdc077[1126]<=nt3fd1;shdc077[1112]<=uv5e284;shdc077[1109]<=dobd9a4;shdc077[1106]<=ana1e10;shdc077[1101]<=xya8150;shdc077[1100]<=db2d4da;shdc077[1094]<=qv9f0d5;shdc077[1093]<=mg34ebd;shdc077[1086]<=lsa8a57;shdc077[1076]<=mg21689;shdc077[1072]<=su4cd40;shdc077[1069]<=fcb121;shdc077[1063]<=kd54432;shdc077[1061]<=ng86878;shdc077[1056]<=phbad72;shdc077[1055]<=kq6dea3;shdc077[1052]<=blfced2;shdc077[1048]<=xybd739;shdc077[1028]<=yx54574;shdc077[1023]<=uve78fb[0];shdc077[1015]<=qtfd7fa;shdc077[1014]<=zz32c7f;shdc077[1002]<=su6205e;shdc077[996]<=dm6cf8c;shdc077[994]<=ir857bb;shdc077[938]<=bld7356;shdc077[933]<=gbf27ae;shdc077[921]<=mgb992f;shdc077[918]<=bn1c13c;shdc077[915]<=mre7cae;shdc077[902]<=do8c50f;shdc077[901]<=qg7864c;shdc077[900]<=fad51e7;shdc077[880]<=qtd9c62;shdc077[874]<=eaea018;shdc077[873]<=wy98973;shdc077[869]<=thf3b58;shdc077[866]<=lf37e37;shdc077[863]<=med1c49;shdc077[848]<=pu997a9;shdc077[841]<=pu8320f;shdc077[840]<=ie3b2e0;shdc077[834]<=yk773c5;shdc077[830]<=ie3e311;shdc077[816]<=anbee41;shdc077[814]<=pf6b185;shdc077[803]<=wy559d;shdc077[793]<=cme07fa;shdc077[789]<=ec10c6f;shdc077[787]<=sufa0d5;shdc077[783]<=ba139a;shdc077[781]<=cb3c91c;shdc077[777]<=lqee0f9;shdc077[775]<=twb7f1d;shdc077[774]<=anaee78;shdc077[765]<=bn13340;shdc077[746]<=fnc7d4e;shdc077[742]<=qg53cd7;shdc077[737]<=xjf30e3;shdc077[732]<=ep23671;shdc077[730]<=goc4b98;shdc077[729]<=fn74e8d;shdc077[708]<=xwcfe83;shdc077[705]<=wy98918;shdc077[698]<=ldf336a;shdc077[697]<=yxc3544;shdc077[694]<=mt186f3;shdc077[689]<=eca69e9;shdc077[686]<=uvc982f;shdc077[685]<=zzb061b;shdc077[677]<=rt5fa47;shdc077[667]<=off2943;shdc077[661]<=ld5f8b9;shdc077[660]<=lf3d99f;shdc077[650]<=nta035d;shdc077[643]<=ipf79c5;shdc077[628]<=os774cd;shdc077[626]<=wl23d30;shdc077[621]<=iebc062;shdc077[620]<=vi764fd;shdc077[617]<=dmf42ab;shdc077[615]<=jpe9ea6;shdc077[609]<=sue0cf8;shdc077[599]<=mef5856;shdc077[598]<=xl13484;shdc077[595]<=ay772e2;shdc077[593]<=hd9ebab;shdc077[588]<=yma9cd0;shdc077[580]<=ld5a793;shdc077[575]<=uk34943;shdc077[565]<=rib75b1;shdc077[556]<=wwd125e;shdc077[553]<=gd8e31;shdc077[550]<=xjc7e6a;shdc077[546]<=mg242d1;shdc077[528]<=hb452ba;shdc077[527]<=tuc0cca;shdc077[514]<=mt8a8ae;shdc077[507]<=xjc7184;shdc077[501]<=fce507;shdc077[498]<=do83573;shdc077[497]<=hd378a0;shdc077[466]<=xj4f8b2;shdc077[459]<=yk72b5b;shdc077[450]<=pu86378;shdc077[437]<=fp942e5;shdc077[433]<=dzc8610;shdc077[431]<=uk1f410;shdc077[420]<=iea6de0;shdc077[417]<=uk24577;shdc077[415]<=wl36ef1;shdc077[408]<=vxa59a6;shdc077[401]<=co1ac37;shdc077[391]<=vx37459;shdc077[390]<=aycb870;shdc077[388]<=ng1100c;shdc077[387]<=gb65dfa;shdc077[368]<=pu30b95;shdc077[366]<=ou246ce;shdc077[365]<=aa1fb34;shdc077[352]<=ph9952;shdc077[348]<=ay53911;shdc077[344]<=lq5de7f;shdc077[343]<=sj8e0d;shdc077[333]<=psda5e1;shdc077[330]<=mre2814;shdc077[325]<=uif5d5f;shdc077[314]<=xjcd977;shdc077[313]<=mg34010;shdc077[310]<=ou2b17f;shdc077[308]<=do47a1;shdc077[307]<=ayf539a;shdc077[304]<=lqd52d9;shdc077[299]<=ks5aef;shdc077[287]<=me675cd;shdc077[282]<=ld454ea;shdc077[278]<=jpcd4c1;shdc077[275]<=jcca8f5;shdc077[273]<=osc485a;shdc077[257]<=vv71515;shdc077[253]<=jpe9cf9;shdc077[250]<=nrf9e15;shdc077[248]<=kqde7bd;shdc077[225]<=cm43086;shdc077[215]<=rie809;shdc077[208]<=rgf1424;shdc077[204]<=rt6be72;shdc077[195]<=kd4b2a8;shdc077[193]<=swa6d19;shdc077[183]<=dz648d9;shdc077[176]<=ps52ebf;shdc077[171]<=al5e34f;shdc077[165]<=ou8d7e9;shdc077[157]<=hdaa0f5;shdc077[155]<=jra562f;shdc077[154]<=by58fcd;shdc077[152]<=wy1aa5b;shdc077[149]<=rt40b5d;shdc077[141]<=nt8bd4c;shdc077[139]<=bna0256;shdc077[128]<=yx4e2a2;shdc077[125]<=ho575ae;shdc077[124]<=ne4d871;shdc077[112]<=gqae43;shdc077[104]<=hq892f1;shdc077[97]<=ay78a4b;shdc077[96]<=ay491f2;shdc077[91]<=me4c91b;shdc077[78]<=fnf9b2e;shdc077[77]<=hb74ac5;shdc077[74]<=\r
-ls960a9;shdc077[64]<=ui72d7c;shdc077[62]<=ks24221;shdc077[56]<=fnd2f0a;shdc077[48]<=aa1fe8e;shdc077[38]<=epae958;shdc077[19]<=wy15d2b;shdc077[9]<=xya2ba5;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module ay68728 (rst_n,\r
- gbe_mode,\r
- mee5046,\r
- ph28231,\r
- force_isolate,\r
- an8c7c,\r
- ic463e5,\r
- qi31f29,\r
- cb8f949,\r
- vi7ca4c,\r
- sue5263,\r
- kf29319\r
- );\r
-input rst_n;\r
-input gbe_mode;\r
-input mee5046;\r
-input [1:0] ph28231;\r
-input force_isolate;\r
-input [7:0] an8c7c;\r
-input ic463e5;\r
-input qi31f29;\r
-input cb8f949;\r
-output [7:0] vi7ca4c;\r
-output sue5263;\r
-output kf29319;\r
-reg [7:0] vi7ca4c;\r
-reg sue5263;\r
-reg kf29319;\r
-reg [1:0] mrc99c0;\r
-reg [1:0] ay4ce05;\r
-reg [1:0] ic67029;\r
-reg [1:0] fp38148;\r
-reg [1:0] rgc0a46;\r
-reg [1:0] ks5233;\r
-reg ep29198;\r
-reg fa48cc5;\r
-reg ww4662b;\r
-reg an33159;\r
-reg [7:0] co98acd;\r
-reg dmc5668;\r
-reg ym2b342;\r
-reg [7:0] ea59a10;\r
-reg vvcd080;\r
-reg qg68406;\r
-reg [7:0] xw42031;\r
-reg gq1018b;\r
-reg kf80c59;\r
-reg jr62cd;\r
-wire ym3166f;\r
-wire lf8b378;\r
-wire [7:0] su59bc7;\r
-wire dzcde38;\r
-reg ip6f1c7;\r
-reg go78e3c;\r
-reg fnc71e1;\r
-reg vx38f0f;\r
-reg vvc787f;\r
-reg oh3c3fe;\r
-reg lqe1ff4;\r
-reg aaffa2;\r
-reg [6:0] gb7fd10;\r
-reg zkfe884;\r
-reg vif4422;\r
-reg lsa2112;\r
-reg aa10892;\r
-reg lf84490;\r
-reg nt22486;\r
-reg sj12436;\r
-reg wy921b4;\r
-reg ep90da0;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-reg pu86d04;\r
-reg [1 : 0] sj36822;\r
-reg ohb4114;\r
-reg [7 : 0] jra08a4;\r
-reg ls4526;\r
-reg nt22932;\r
-reg [1 : 0] vk14997;\r
-reg [1 : 0] wla4cba;\r
-reg [1 : 0] mt265d4;\r
-reg [1 : 0] lf32ea4;\r
-reg [1 : 0] ie97526;\r
-reg [1 : 0] xlba930;\r
-reg ead4986;\r
-reg qva4c30;\r
-reg qv26184;\r
-reg pu30c24;\r
-reg [7 : 0] tw86123;\r
-reg ba3091b;\r
-reg nt848db;\r
-reg [7 : 0] ec246df;\r
-reg cb236f9;\r
-reg hq1b7cc;\r
-reg [7 : 0] qgdbe62;\r
-reg psdf311;\r
-reg fnf988a;\r
-reg wjcc457;\r
-reg yk622bc;\r
-reg ba115e0;\r
-reg [7 : 0] wl8af03;\r
-reg zk5781c;\r
-reg ecbc0e3;\r
-reg ice0718;\r
-reg jr38c1;\r
-reg xl1c60e;\r
-reg vve3077;\r
-reg ep183be;\r
-reg wwc1df5;\r
-reg zmefa9;\r
-reg [6 : 0] ww77d4a;\r
-reg uxbea50;\r
-reg gof5284;\r
-reg uka9420;\r
-reg fn4a101;\r
-reg zx5080f;\r
-reg db8407e;\r
-reg zm203f6;\r
-reg ng1fb3;\r
-reg ecfd9b;\r
-reg [2047:0] shdc077;\r
-wire [47:0] eae03bd;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-localparam ba1de9 = 48,ngef4b = 32'hfdffe06b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-always @(posedge mee5046 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin fnc71e1 <= 1'd1; vx38f0f <= 1'd1; end else begin fnc71e1 <= ice0718; vx38f0f <= jr38c1; end\r
-end\r
-always @(posedge mee5046 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vvc787f <= 1'd1; oh3c3fe <= 1'd1; end else begin vvc787f <= qva4c30; oh3c3fe <= vve3077; end\r
-end\r
-always @(posedge mee5046 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin wy921b4 <= 1'b0; ep90da0 <= 1'b0; end else begin wy921b4 <= ohb4114; ep90da0 <= ng1fb3; end\r
-end\r
-always @(posedge mee5046 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin dmc5668 <= 1'b0; ym2b342 <= 1'b0; co98acd <= 8'd0; vvcd080 <= 1'b0; qg68406 <= 1'b0; ea59a10 <= 8'd0; gq1018b <= 1'b0; kf80c59 <= 1'b0; xw42031 <= 8'd0; jr62cd <= 1'b0; end else begin if (ecfd9b) begin co98acd <= 8'd0; ym2b342 <= 1'b0; dmc5668 <= 1'b0; end else begin co98acd <= jra08a4; ym2b342 <= nt22932; dmc5668 <= ls4526; end ea59a10 <= tw86123; qg68406 <= nt848db; vvcd080 <= ba3091b;\r
- if (xl1c60e) begin jr62cd <= 1'b0; end else if (((nt848db==1'd1) && (hq1b7cc==1'd0)) || (ep183be ==1'd1)) jr62cd <= 1'b1; else jr62cd <= (~wjcc457); if (wjcc457) begin xw42031[3:0] <= ec246df[3:0]; kf80c59 <= hq1b7cc; gq1018b <= cb236f9; if (ep183be) begin xw42031[7:4] <= ec246df[7:4]; end else begin xw42031[7:4] <= tw86123[3:0]; end end end\r
-end\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) xjf9222 ( .Reset(vx38f0f), .RPReset(vx38f0f), .WrClock(mee5046), .WrEn(jr62cd), .Data({gq1018b, kf80c59, xw42031}),\r
- .RdClock(cb8f949), .RdEn(ip6f1c7), .Q({ym3166f, lf8b378, su59bc7}),\r
- .Empty(dzcde38), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) xjf9222 ( .Reset(vx38f0f), .RPReset(vx38f0f), .WrClock(mee5046), .WrEn(jr62cd), .Data({gq1018b, kf80c59, xw42031}),\r
- .RdClock(cb8f949), .RdEn(ip6f1c7), .Q({ym3166f, lf8b378, su59bc7}),\r
- .Empty(dzcde38), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) xjf9222 ( .Reset(vx38f0f), .RPReset(vx38f0f), .WrClock(mee5046), .WrEn(jr62cd), .Data({gq1018b, kf80c59, xw42031}),\r
- .RdClock(cb8f949), .RdEn(ip6f1c7), .Q({ym3166f, lf8b378, su59bc7}),\r
- .Empty(dzcde38), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-`endif\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vif4422 <= 1'b0; lsa2112 <= 1'b0; aa10892 <= 1'b0; lf84490 <= 1'b0; nt22486 <= 1'b0; sj12436 <= 1'b0; end else begin vif4422 <= pu86d04; lsa2112 <= gof5284;\r
- aa10892 <= uka9420; lf84490 <= uka9420 & (~fn4a101); nt22486 <= ~uka9420 & (fn4a101); sj12436 <= zx5080f || db8407e; end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin mrc99c0 <= 2'd0; ay4ce05 <= 2'd0; ic67029 <= 2'd0; fp38148 <= 2'd0; rgc0a46 <= 2'd0; ks5233 <= 2'd0; ep29198 <= 1'b0; fa48cc5 <= 1'b0; ww4662b <= 1'b0; an33159 <= 1'b0; end else begin mrc99c0 <= sj36822; ay4ce05 <= vk14997; ic67029 <= wla4cba; fp38148 <= mt265d4; if ((wla4cba==mt265d4) && (wla4cba==lf32ea4)) rgc0a46 <= lf32ea4; ks5233 <= ie97526; if (zm203f6) ep29198 <= 1'b1; else if (ie97526 != xlba930) ep29198 <= 1'b1; else ep29198 <= 1'b0; if (fn4a101) begin fa48cc5 <= 1'b1; ww4662b <= 1'b0; an33159 <= 1'b0; end else begin fa48cc5 <= ie97526[1]; ww4662b <= !ie97526[1] & ( ie97526[0]); an33159 <= !ie97526[1] & (!ie97526[0]); end\r
- case (wwc1df5) 1'd0: begin if (ead4986) begin go78e3c <= 1'b1; lqe1ff4 <= 1'd1; end else begin go78e3c <= 1'b0; lqe1ff4 <= 1'd0; end end 1'd1: begin go78e3c <= 1'b1; if (zmefa9) begin lqe1ff4 <= 1'd0; end else begin lqe1ff4 <= 1'd1; end end default: begin lqe1ff4 <= 1'd0; end endcase\r
- end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin gb7fd10 <= 7'd0; zkfe884 <= 1'b0; end else begin if (ead4986 || uxbea50) begin gb7fd10 <= 7'd0; end else begin gb7fd10 <= ww77d4a + 1; end\r
- if (ead4986) begin zkfe884 <= 1'b0; end else if (qv26184) begin if (ww77d4a == 7'd8) begin zkfe884 <= 1'b1; end else begin zkfe884 <= 1'b0; end end else if (pu30c24) begin if (ww77d4a == 7'd98) begin zkfe884 <= 1'b1; end else begin zkfe884 <= 1'b0; end end else begin zkfe884 <= 1'b1; end end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin aaffa2 <= 1'b0; end else begin if (ead4986) begin aaffa2 <= 1'b0; end else if (qv26184) begin if (ww77d4a == 7'd3) begin aaffa2 <= 1'b1; end else begin aaffa2 <= 1'b0; end end else if (pu30c24) begin if (ww77d4a == 7'd49) begin aaffa2 <= 1'b1; end else begin aaffa2 <= 1'b0; end end else begin aaffa2 <= 1'b1; end end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ip6f1c7 <= 1'b0; end else begin if (ice0718) begin ip6f1c7 <= 1'b0; end else if (!zk5781c && zmefa9) begin ip6f1c7 <= 1'b1; end else begin ip6f1c7 <= 1'b0; end end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vi7ca4c <= 8'd0; sue5263 <= 1'd0; kf29319 <= 1'd0; end else begin vi7ca4c <= wl8af03; sue5263 <= yk622bc; kf29319 <= ba115e0; end\r
-end\r
-always@* begin pu86d04<=eae03bd[0];sj36822<={ph28231>>1,eae03bd[1]};ohb4114<=eae03bd[2];jra08a4<={an8c7c>>1,eae03bd[3]};ls4526<=eae03bd[4];nt22932<=eae03bd[5];vk14997<={mrc99c0>>1,eae03bd[6]};wla4cba<={ay4ce05>>1,eae03bd[7]};mt265d4<={ic67029>>1,eae03bd[8]};lf32ea4<={fp38148>>1,eae03bd[9]};ie97526<={rgc0a46>>1,eae03bd[10]};xlba930<={ks5233>>1,eae03bd[11]};ead4986<=eae03bd[12];qva4c30<=eae03bd[13];qv26184<=eae03bd[14];pu30c24<=eae03bd[15];tw86123<={co98acd>>1,eae03bd[16]};ba3091b<=eae03bd[17];nt848db<=eae03bd[18];ec246df<={ea59a10>>1,eae03bd[19]};cb236f9<=eae03bd[20];hq1b7cc<=eae03bd[21];qgdbe62<={xw42031>>1,eae03bd[22]};psdf311<=eae03bd[23];fnf988a<=eae03bd[24];wjcc457<=eae03bd[25];yk622bc<=eae03bd[26];ba115e0<=eae03bd[27];wl8af03<={su59bc7>>1,eae03bd[28]};zk5781c<=eae03bd[29];ecbc0e3<=eae03bd[30];ice0718<=eae03bd[31];jr38c1<=eae03bd[32];xl1c60e<=eae03bd[33];vve3077<=eae03bd[34];ep183be<=eae03bd[35];wwc1df5<=eae03bd[36];zmefa9<=eae03bd[37];ww77d4a<={gb7fd10>>1,eae03bd[38]};uxbea50<=eae03bd[39];gof5284<=eae03bd[40];uka9420<=eae03bd[41];fn4a101<=eae03bd[42];zx5080f<=eae03bd[43];db8407e<=eae03bd[44];zm203f6<=eae03bd[45];ng1fb3<=eae03bd[46];ecfd9b<=eae03bd[47];end\r
-always@* begin shdc077[2047]<=ph28231[0];shdc077[2046]<=force_isolate;shdc077[2044]<=an8c7c[0];shdc077[2041]<=ic463e5;shdc077[2034]<=qi31f29;shdc077[2021]<=mrc99c0[0];shdc077[2017]<=qg68406;shdc077[1995]<=ay4ce05[0];shdc077[1986]<=xw42031[0];shdc077[1943]<=ic67029[0];shdc077[1925]<=gq1018b;shdc077[1908]<=vx38f0f;shdc077[1864]<=aaffa2;shdc077[1855]<=co98acd[0];shdc077[1838]<=fp38148[0];shdc077[1803]<=kf80c59;shdc077[1769]<=vvc787f;shdc077[1680]<=gb7fd10[0];shdc077[1662]<=dmc5668;shdc077[1628]<=rgc0a46[0];shdc077[1559]<=jr62cd;shdc077[1501]<=go78e3c;shdc077[1490]<=oh3c3fe;shdc077[1487]<=ww4662b;shdc077[1312]<=zkfe884;shdc077[1276]<=ym2b342;shdc077[1209]<=ks5233[0];shdc077[1155]<=lsa2112;shdc077[1070]<=ym3166f;shdc077[1048]<=nt22486;shdc077[1023]<=gbe_mode;shdc077[1008]<=vvcd080;shdc077[954]<=fnc71e1;shdc077[932]<=lqe1ff4;shdc077[927]<=an33159;shdc077[750]<=ip6f1c7;shdc077[743]<=fa48cc5;shdc077[577]<=vif4422;shdc077[524]<=lf84490;shdc077[504]<=ea59a10[0];shdc077[375]<=dzcde38;shdc077[371]<=ep29198;shdc077[262]<=aa10892;shdc077[197]<=ep90da0;shdc077[187]<=su59bc7[0];shdc077[98]<=wy921b4;shdc077[93]<=lf8b378;shdc077[49]<=sj12436;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module ld4aee6 (rst_n,\r
- gbe_mode,\r
- force_isolate,\r
- mee5046,\r
- an8c7c,\r
- ic463e5,\r
- qi31f29,\r
- qva4f56,\r
- rv27ab4,\r
- cb8f949,\r
- ayead3e,\r
- vi7ca4c,\r
- sue5263,\r
- kf29319,\r
- uk3e26b,\r
- lqf1359\r
- );\r
-input rst_n;\r
-input gbe_mode;\r
-input force_isolate;\r
-input mee5046;\r
-input [7:0] an8c7c;\r
-input ic463e5;\r
-input qi31f29;\r
-input qva4f56;\r
-input rv27ab4;\r
-input cb8f949;\r
-input [1:0] ayead3e;\r
-output [7:0] vi7ca4c;\r
-output sue5263;\r
-output kf29319;\r
-output uk3e26b;\r
-output lqf1359;\r
-reg [7:0] vi7ca4c;\r
-reg sue5263;\r
-reg kf29319;\r
-reg uk3e26b;\r
-reg lqf1359;\r
-reg [1:0] mrc99c0;\r
-reg [1:0] ay4ce05;\r
-reg [1:0] ic67029;\r
-reg [1:0] fp38148;\r
-reg [1:0] rgc0a46;\r
-reg [1:0] ks5233;\r
-reg ep29198;\r
-reg fa48cc5;\r
-reg ww4662b;\r
-reg an33159;\r
-reg go78e3c;\r
-reg fnc71e1;\r
-reg tw35e83;\r
-reg aaffa2;\r
-reg [6:0] gb7fd10;\r
-reg zkfe884;\r
-reg ng837ab;\r
-reg fc1bd5b;\r
-reg ip6f1c7;\r
-reg [7:0] co98acd;\r
-reg ym2b342;\r
-reg dmc5668;\r
-reg medb224;\r
-reg gbd9120;\r
-wire [7:0] su59bc7;\r
-wire lf8b378;\r
-wire ym3166f;\r
-wire ba20be9;\r
-wire ym5f4a;\r
-reg [7:0] pu2fa51;\r
-reg os7d28b;\r
-reg nre9458;\r
-reg bl4a2c7;\r
-reg sh5163f;\r
-reg lqe1ff4;\r
-reg vvc787f;\r
-reg thc7f7a;\r
-reg vif4422;\r
-reg lsa2112;\r
-reg aa10892;\r
-reg lf84490;\r
-reg nt22486;\r
-reg sj12436;\r
-reg wy921b4;\r
-reg ep90da0;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-reg pu86d04;\r
-reg ohb4114;\r
-reg [7 : 0] jra08a4;\r
-reg ls4526;\r
-reg nt22932;\r
-reg jp553cf;\r
-reg gqa9e7f;\r
-reg [1 : 0] th4f3f8;\r
-reg [1 : 0] vk14997;\r
-reg [1 : 0] wla4cba;\r
-reg [1 : 0] mt265d4;\r
-reg [1 : 0] lf32ea4;\r
-reg [1 : 0] ie97526;\r
-reg [1 : 0] xlba930;\r
-reg ead4986;\r
-reg qva4c30;\r
-reg qv26184;\r
-reg pu30c24;\r
-reg ice0718;\r
-reg jr38c1;\r
-reg rt5a511;\r
-reg zmefa9;\r
-reg [6 : 0] ww77d4a;\r
-reg uxbea50;\r
-reg do11dfa;\r
-reg jr8efd2;\r
-reg ecbc0e3;\r
-reg [7 : 0] tw86123;\r
-reg nt848db;\r
-reg ba3091b;\r
-reg ri961cf;\r
-reg rvb0e7a;\r
-reg [7 : 0] wl8af03;\r
-reg ba115e0;\r
-reg yk622bc;\r
-reg wj7ae6b;\r
-reg zxd735c;\r
-reg [7 : 0] aab9ae6;\r
-reg jpcd731;\r
-reg bl6b98e;\r
-reg go5cc77;\r
-reg lde63b8;\r
-reg wwc1df5;\r
-reg vve3077;\r
-reg su7718e;\r
-reg gof5284;\r
-reg uka9420;\r
-reg fn4a101;\r
-reg zx5080f;\r
-reg db8407e;\r
-reg zm203f6;\r
-reg ng1fb3;\r
-reg ecfd9b;\r
-reg [2047:0] shdc077;\r
-wire [52:0] eae03bd;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-localparam ba1de9 = 53,ngef4b = 32'hfdffca8b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-always @(posedge mee5046 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vif4422 <= 1'b0; lsa2112 <= 1'b0; aa10892 <= 1'b0; lf84490 <= 1'b0; nt22486 <= 1'b0; sj12436 <= 1'b0; end else begin vif4422 <= pu86d04; lsa2112 <= gof5284;\r
- aa10892 <= uka9420; lf84490 <= uka9420 & (~fn4a101); nt22486 <= ~uka9420 & (fn4a101); sj12436 <= zx5080f || db8407e; end\r
-end\r
-always @(posedge mee5046 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin mrc99c0 <= 2'd0; ay4ce05 <= 2'd0; ic67029 <= 2'd0; fp38148 <= 2'd0; rgc0a46 <= 2'd0; ks5233 <= 2'd0; ep29198 <= 1'b1; fa48cc5 <= 1'b0; ww4662b <= 1'b0; an33159 <= 1'b0; end else begin mrc99c0 <= th4f3f8; ay4ce05 <= vk14997; ic67029 <= wla4cba; fp38148 <= mt265d4; if ((wla4cba==mt265d4) && (wla4cba==lf32ea4)) rgc0a46 <= lf32ea4; ks5233 <= ie97526; if (zm203f6) ep29198 <= 1'b1; else if (ie97526 != xlba930) ep29198 <= 1'b1; else ep29198 <= 1'b0; if (fn4a101) begin fa48cc5 <= 1'b1; ww4662b <= 1'b0; an33159 <= 1'b0; end else begin fa48cc5 <= ie97526[1]; ww4662b <= !ie97526[1] & ( ie97526[0]); an33159 <= !ie97526[1] & (!ie97526[0]); end case (wwc1df5) 1'd0: begin if (ead4986) begin go78e3c <= 1'b1; lqe1ff4 <= 1'd1; end else begin go78e3c <= 1'b0; lqe1ff4 <= 1'd0; end end 1'd1: begin go78e3c <= 1'b1; if (zmefa9) begin lqe1ff4 <= 1'd0; end else begin lqe1ff4 <= 1'd1; end end default: begin lqe1ff4 <= 1'd0; end endcase end\r
-end\r
-always @(posedge mee5046 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin gb7fd10 <= 7'd0; zkfe884 <= 1'b0; end else begin if (ead4986 || uxbea50) begin gb7fd10 <= 7'd0; end else begin gb7fd10 <= ww77d4a + 1; end\r
- if (ead4986) begin zkfe884 <= 1'b0; end else if (qv26184) begin if (ww77d4a == 7'd8) begin zkfe884 <= 1'b1; end else begin zkfe884 <= 1'b0; end end else if (pu30c24) begin if (ww77d4a == 7'd98) begin zkfe884 <= 1'b1; end else begin zkfe884 <= 1'b0; end end else begin zkfe884 <= 1'b1; end end\r
-end\r
-always @(posedge mee5046 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin aaffa2 <= 1'b0; end else begin if (ead4986) begin aaffa2 <= 1'b0; end else if (qv26184) begin if (ww77d4a == 7'd3) begin aaffa2 <= 1'b1; end else begin aaffa2 <= 1'b0; end end else if (pu30c24) begin if (ww77d4a == 7'd49) begin aaffa2 <= 1'b1; end else begin aaffa2 <= 1'b0; end end else begin aaffa2 <= 1'b1; end end\r
-end\r
-always @(posedge mee5046 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin dmc5668 <= 0; ym2b342 <= 0; medb224 <= 0; gbd9120 <= 0; co98acd <= 8'd0; end else begin co98acd <= jra08a4; ym2b342 <= nt22932; dmc5668 <= ls4526; medb224 <= jp553cf; gbd9120 <= gqa9e7f; end\r
-end\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(12), .pmi_data_width_r(12), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) pff98c7 ( .Reset(tw35e83), .RPReset(tw35e83), .WrClock(mee5046), .WrEn(aaffa2), .Data({gbd9120, medb224, dmc5668, ym2b342, co98acd}),\r
- .RdClock(cb8f949), .RdEn(ip6f1c7), .Q({ym5f4a, ba20be9, ym3166f, lf8b378, su59bc7}),\r
- .Empty(dzcde38), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(12), .pmi_data_width_r(12), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) pff98c7 ( .Reset(tw35e83), .RPReset(tw35e83), .WrClock(mee5046), .WrEn(aaffa2), .Data({gbd9120, medb224, dmc5668, ym2b342, co98acd}),\r
- .RdClock(cb8f949), .RdEn(ip6f1c7), .Q({ym5f4a, ba20be9, ym3166f, lf8b378, su59bc7}),\r
- .Empty(dzcde38), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(12), .pmi_data_width_r(12), .pmi_data_depth_w(8), .pmi_data_depth_r(8), .pmi_full_flag(8), .pmi_empty_flag(0), .pmi_almost_full_flag(3), .pmi_almost_empty_flag(1), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) pff98c7 ( .Reset(tw35e83), .RPReset(tw35e83), .WrClock(mee5046), .WrEn(aaffa2), .Data({gbd9120, medb224, dmc5668, ym2b342, co98acd}),\r
- .RdClock(cb8f949), .RdEn(ip6f1c7), .Q({ym5f4a, ba20be9, ym3166f, lf8b378, su59bc7}),\r
- .Empty(dzcde38), .Full(), .AlmostEmpty(), .AlmostFull() );\r
-`endif\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin fnc71e1 <= 1'd1; tw35e83 <= 1'd1; end else begin fnc71e1 <= ice0718; tw35e83 <= jr38c1; end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vvc787f <= 1'd1; thc7f7a <= 1'd1; end else begin vvc787f <= qva4c30; thc7f7a <= vve3077; end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ng837ab <= 1'b0; fc1bd5b <= 1'b0; end else begin if (rt5a511) begin ng837ab <= 1'b0; end else begin if (su7718e) begin ng837ab <= 1'b1; end else begin ng837ab <= ~do11dfa; end end\r
- fc1bd5b <= do11dfa;\r
- end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ip6f1c7 <= 1'b0; end else begin if (rt5a511) begin ip6f1c7 <= 1'b0; end else begin if (!dzcde38 && do11dfa) begin ip6f1c7 <= 1'b1; end else begin ip6f1c7 <= 1'b0; end end end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin nre9458 <= 0; os7d28b <= 0; bl4a2c7 <= 0; sh5163f <= 0; pu2fa51 <= 8'd0; end else begin if (do11dfa) begin os7d28b <= ba115e0; bl4a2c7 <= wj7ae6b; sh5163f <= zxd735c; if ((!su7718e) && yk622bc && (wl8af03 == 8'h0F) && (!ba115e0) && jpcd731) begin nre9458 <= 1'b0; pu2fa51 <= 8'h00; end else begin nre9458 <= yk622bc; pu2fa51 <= wl8af03; end end\r
- end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin wy921b4 <= 1'b0; ep90da0 <= 1'b0; end else begin wy921b4 <= ohb4114; ep90da0 <= ng1fb3; end\r
-end\r
-always @(posedge cb8f949 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin sue5263 <= 0; kf29319 <= 0; uk3e26b <= 0; lqf1359 <= 0; vi7ca4c <= 8'd0; end else begin if (ecfd9b) begin sue5263 <= 0; kf29319 <= 0; uk3e26b <= 0; lqf1359 <= 0; vi7ca4c <= 8'd0; end else begin if (jr8efd2) begin vi7ca4c[3:0] <= aab9ae6[3:0]; end else begin vi7ca4c[3:0] <= aab9ae6[7:4]; end vi7ca4c[7:4] <= aab9ae6[7:4]; kf29319 <= jpcd731; sue5263 <= bl6b98e; uk3e26b <= go5cc77; lqf1359 <= lde63b8; end end\r
-end\r
-always@* begin pu86d04<=eae03bd[0];ohb4114<=eae03bd[1];jra08a4<={an8c7c>>1,eae03bd[2]};ls4526<=eae03bd[3];nt22932<=eae03bd[4];jp553cf<=eae03bd[5];gqa9e7f<=eae03bd[6];th4f3f8<={ayead3e>>1,eae03bd[7]};vk14997<={mrc99c0>>1,eae03bd[8]};wla4cba<={ay4ce05>>1,eae03bd[9]};mt265d4<={ic67029>>1,eae03bd[10]};lf32ea4<={fp38148>>1,eae03bd[11]};ie97526<={rgc0a46>>1,eae03bd[12]};xlba930<={ks5233>>1,eae03bd[13]};ead4986<=eae03bd[14];qva4c30<=eae03bd[15];qv26184<=eae03bd[16];pu30c24<=eae03bd[17];ice0718<=eae03bd[18];jr38c1<=eae03bd[19];rt5a511<=eae03bd[20];zmefa9<=eae03bd[21];ww77d4a<={gb7fd10>>1,eae03bd[22]};uxbea50<=eae03bd[23];do11dfa<=eae03bd[24];jr8efd2<=eae03bd[25];ecbc0e3<=eae03bd[26];tw86123<={co98acd>>1,eae03bd[27]};nt848db<=eae03bd[28];ba3091b<=eae03bd[29];ri961cf<=eae03bd[30];rvb0e7a<=eae03bd[31];wl8af03<={su59bc7>>1,eae03bd[32]};ba115e0<=eae03bd[33];yk622bc<=eae03bd[34];wj7ae6b<=eae03bd[35];zxd735c<=eae03bd[36];aab9ae6<={pu2fa51>>1,eae03bd[37]};jpcd731<=eae03bd[38];bl6b98e<=eae03bd[39];go5cc77<=eae03bd[40];lde63b8<=eae03bd[41];wwc1df5<=eae03bd[42];vve3077<=eae03bd[43];su7718e<=eae03bd[44];gof5284<=eae03bd[45];uka9420<=eae03bd[46];fn4a101<=eae03bd[47];zx5080f<=eae03bd[48];db8407e<=eae03bd[49];zm203f6<=eae03bd[50];ng1fb3<=eae03bd[51];ecfd9b<=eae03bd[52];end\r
-always@* begin shdc077[2047]<=force_isolate;shdc077[2046]<=an8c7c[0];shdc077[2044]<=ic463e5;shdc077[2040]<=qi31f29;shdc077[2032]<=qva4f56;shdc077[2017]<=rv27ab4;shdc077[1987]<=ayead3e[0];shdc077[1926]<=mrc99c0[0];shdc077[1805]<=ba20be9;shdc077[1804]<=ay4ce05[0];shdc077[1803]<=zkfe884;shdc077[1761]<=su59bc7[0];shdc077[1668]<=lqe1ff4;shdc077[1562]<=ym5f4a;shdc077[1560]<=ic67029[0];shdc077[1558]<=ng837ab;shdc077[1550]<=ww4662b;shdc077[1475]<=lf8b378;shdc077[1464]<=medb224;shdc077[1288]<=vvc787f;shdc077[1076]<=pu2fa51[0];shdc077[1072]<=fp38148[0];shdc077[1069]<=fc1bd5b;shdc077[1056]<=vif4422;shdc077[1052]<=an33159;shdc077[1028]<=sj12436;shdc077[1023]<=gbe_mode;shdc077[902]<=ym3166f;shdc077[901]<=gb7fd10[0];shdc077[880]<=gbd9120;shdc077[834]<=sh5163f;shdc077[775]<=fa48cc5;shdc077[732]<=dmc5668;shdc077[528]<=thc7f7a;shdc077[514]<=nt22486;shdc077[450]<=aaffa2;shdc077[417]<=bl4a2c7;shdc077[387]<=ep29198;shdc077[366]<=ym2b342;shdc077[257]<=lf84490;shdc077[225]<=tw35e83;shdc077[208]<=nre9458;shdc077[193]<=ks5233[0];shdc077[183]<=co98acd[0];shdc077[128]<=aa10892;shdc077[112]<=fnc71e1;shdc077[104]<=os7d28b;shdc077[96]<=rgc0a46[0];shdc077[91]<=ip6f1c7;shdc077[64]<=lsa2112;shdc077[56]<=go78e3c;shdc077[19]<=ep90da0;shdc077[9]<=wy921b4;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module coac47 (rst_n,\r
- gbe_mode,\r
- gq88e04,\r
- fa47021,\r
- aaffa2,\r
- force_isolate,\r
- an8c7c,\r
- ic463e5,\r
- qi31f29,\r
- gb5e68a,\r
- vi7ca4c,\r
- sue5263,\r
- kf29319\r
- );\r
-input rst_n;\r
-input gbe_mode;\r
-input gq88e04;\r
-input fa47021;\r
-output aaffa2;\r
-input force_isolate;\r
-input [7:0] an8c7c;\r
-input ic463e5;\r
-input qi31f29;\r
-input [1:0] gb5e68a;\r
-output [7:0] vi7ca4c;\r
-output sue5263;\r
-output kf29319;\r
-reg [7:0] vi7ca4c;\r
-reg sue5263;\r
-reg kf29319;\r
-reg [1:0] mrc99c0;\r
-reg [1:0] ay4ce05;\r
-reg [1:0] ic67029;\r
-reg [1:0] fp38148;\r
-reg [1:0] rgc0a46;\r
-reg [1:0] ks5233;\r
-reg ep29198;\r
-reg fa48cc5;\r
-reg ww4662b;\r
-reg an33159;\r
-reg aaffa2;\r
-reg [6:0] gb7fd10;\r
-reg zkfe884;\r
-reg ng837ab;\r
-reg ip6f1c7;\r
-reg [7:0] co98acd;\r
-reg ym2b342;\r
-reg dmc5668;\r
-reg vif4422;\r
-reg lsa2112;\r
-reg aa10892;\r
-reg lf84490;\r
-reg nt22486;\r
-reg sj12436;\r
-reg wy921b4;\r
-reg ep90da0;\r
-reg pu86d04;\r
-reg an858e4;\r
-reg ohb4114;\r
-reg [7 : 0] jra08a4;\r
-reg ls4526;\r
-reg nt22932;\r
-reg [1 : 0] vk25af2;\r
-reg [1 : 0] vk14997;\r
-reg [1 : 0] wla4cba;\r
-reg [1 : 0] mt265d4;\r
-reg [1 : 0] lf32ea4;\r
-reg [1 : 0] ie97526;\r
-reg [1 : 0] xlba930;\r
-reg ead4986;\r
-reg qva4c30;\r
-reg qv26184;\r
-reg pu30c24;\r
-reg [6 : 0] ww77d4a;\r
-reg uxbea50;\r
-reg do11dfa;\r
-reg ecbc0e3;\r
-reg [7 : 0] tw86123;\r
-reg nt848db;\r
-reg ba3091b;\r
-reg gof5284;\r
-reg uka9420;\r
-reg fn4a101;\r
-reg zx5080f;\r
-reg db8407e;\r
-reg zm203f6;\r
-reg ng1fb3;\r
-reg ecfd9b;\r
-reg [2047:0] shdc077;\r
-wire [31:0] eae03bd;\r
-localparam ba1de9 = 32,ngef4b = 32'hfdffd42b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin wy921b4 <= 1'b0; ep90da0 <= 1'b0; end else begin wy921b4 <= ohb4114; ep90da0 <= ng1fb3; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vif4422 <= 1'b0; lsa2112 <= 1'b0; aa10892 <= 1'b0; lf84490 <= 1'b0; nt22486 <= 1'b0; sj12436 <= 1'b0; end else begin vif4422 <= pu86d04; lsa2112 <= gof5284;\r
- aa10892 <= uka9420; lf84490 <= uka9420 & (~fn4a101); nt22486 <= ~uka9420 & (fn4a101); sj12436 <= zx5080f || db8407e; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin mrc99c0 <= 2'd0; ay4ce05 <= 2'd0; ic67029 <= 2'd0; fp38148 <= 2'd0; rgc0a46 <= 2'd0; ks5233 <= 2'd0; ep29198 <= 1'b1; fa48cc5 <= 1'b0; ww4662b <= 1'b0; an33159 <= 1'b0; end else begin mrc99c0 <= vk25af2; ay4ce05 <= vk14997; ic67029 <= wla4cba; fp38148 <= mt265d4; if ((wla4cba==mt265d4) && (wla4cba==lf32ea4)) rgc0a46 <= lf32ea4; ks5233 <= ie97526; if (zm203f6) ep29198 <= 1'b1; else if (ie97526 != xlba930) ep29198 <= 1'b1; else ep29198 <= 1'b0; if (fn4a101) begin fa48cc5 <= 1'b1; ww4662b <= 1'b0; an33159 <= 1'b0; end else begin fa48cc5 <= ie97526[1]; ww4662b <= !ie97526[1] & ( ie97526[0]); an33159 <= !ie97526[1] & (!ie97526[0]); end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin gb7fd10 <= 7'd0; zkfe884 <= 1'b0; end else begin if (ead4986 || uxbea50) begin gb7fd10 <= 7'd0; end else begin gb7fd10 <= ww77d4a + 1; end\r
- if (ead4986) begin zkfe884 <= 1'b0; end else if (qv26184) begin if (ww77d4a == 7'd8) begin zkfe884 <= 1'b1; end else begin zkfe884 <= 1'b0; end end else if (pu30c24) begin if (ww77d4a == 7'd98) begin zkfe884 <= 1'b1; end else begin zkfe884 <= 1'b0; end end else begin zkfe884 <= 1'b1; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin aaffa2 <= 1'b0; end else begin if (ead4986) begin aaffa2 <= 1'b0; end else if (qv26184) begin if (ww77d4a == 7'd3) begin aaffa2 <= 1'b1; end else begin aaffa2 <= 1'b0; end end else if (pu30c24) begin if (ww77d4a == 7'd49) begin aaffa2 <= 1'b1; end else begin aaffa2 <= 1'b0; end end else begin aaffa2 <= 1'b1; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin dmc5668 <= 0; ym2b342 <= 0; co98acd <= 8'd0; end else begin if (an858e4) begin if (ecfd9b) begin co98acd <= 8'd0; ym2b342 <= 1'b0; dmc5668 <= 1'b0; end else begin co98acd <= jra08a4; ym2b342 <= nt22932; dmc5668 <= ls4526; end end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin sue5263 <= 0; kf29319 <= 0; vi7ca4c <= 8'd0; end else begin if (an858e4) begin kf29319 <= nt848db; sue5263 <= ba3091b; vi7ca4c <= tw86123; end end\r
-end\r
-always@* begin pu86d04<=eae03bd[0];an858e4<=eae03bd[1];ohb4114<=eae03bd[2];jra08a4<={an8c7c>>1,eae03bd[3]};ls4526<=eae03bd[4];nt22932<=eae03bd[5];vk25af2<={gb5e68a>>1,eae03bd[6]};vk14997<={mrc99c0>>1,eae03bd[7]};wla4cba<={ay4ce05>>1,eae03bd[8]};mt265d4<={ic67029>>1,eae03bd[9]};lf32ea4<={fp38148>>1,eae03bd[10]};ie97526<={rgc0a46>>1,eae03bd[11]};xlba930<={ks5233>>1,eae03bd[12]};ead4986<=eae03bd[13];qva4c30<=eae03bd[14];qv26184<=eae03bd[15];pu30c24<=eae03bd[16];ww77d4a<={gb7fd10>>1,eae03bd[17]};uxbea50<=eae03bd[18];do11dfa<=eae03bd[19];ecbc0e3<=eae03bd[20];tw86123<={co98acd>>1,eae03bd[21]};nt848db<=eae03bd[22];ba3091b<=eae03bd[23];gof5284<=eae03bd[24];uka9420<=eae03bd[25];fn4a101<=eae03bd[26];zx5080f<=eae03bd[27];db8407e<=eae03bd[28];zm203f6<=eae03bd[29];ng1fb3<=eae03bd[30];ecfd9b<=eae03bd[31];end\r
-always@* begin shdc077[2047]<=fa47021;shdc077[2046]<=force_isolate;shdc077[2044]<=an8c7c[0];shdc077[2041]<=ic463e5;shdc077[2035]<=qi31f29;shdc077[2022]<=gb5e68a[0];shdc077[1996]<=mrc99c0[0];shdc077[1945]<=ay4ce05[0];shdc077[1922]<=lsa2112;shdc077[1842]<=ic67029[0];shdc077[1797]<=aa10892;shdc077[1776]<=ym2b342;shdc077[1637]<=fp38148[0];shdc077[1622]<=fa48cc5;shdc077[1546]<=lf84490;shdc077[1504]<=dmc5668;shdc077[1468]<=ip6f1c7;shdc077[1391]<=zkfe884;shdc077[1226]<=rgc0a46[0];shdc077[1197]<=ww4662b;shdc077[1044]<=nt22486;shdc077[1023]<=gbe_mode;shdc077[961]<=vif4422;shdc077[888]<=co98acd[0];shdc077[811]<=ep29198;shdc077[734]<=ng837ab;shdc077[695]<=gb7fd10[0];shdc077[405]<=ks5233[0];shdc077[347]<=an33159;shdc077[164]<=ep90da0;shdc077[82]<=wy921b4;shdc077[41]<=sj12436;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module thddcda (rst_n,\r
- gbe_mode,\r
- force_isolate,\r
- gq88e04,\r
- fa47021,\r
- aaffa2,\r
- an8c7c,\r
- ic463e5,\r
- qi31f29,\r
- qva4f56,\r
- rv27ab4,\r
- gb5e68a,\r
- vi7ca4c,\r
- sue5263,\r
- kf29319,\r
- uk3e26b,\r
- lqf1359\r
- );\r
-input rst_n;\r
-input gbe_mode;\r
-input force_isolate;\r
-input gq88e04;\r
-input fa47021;\r
-output aaffa2;\r
-input [7:0] an8c7c;\r
-input ic463e5;\r
-input qi31f29;\r
-input qva4f56;\r
-input rv27ab4;\r
-input [1:0] gb5e68a;\r
-output [7:0] vi7ca4c;\r
-output sue5263;\r
-output kf29319;\r
-output uk3e26b;\r
-output lqf1359;\r
-reg [7:0] vi7ca4c;\r
-reg sue5263;\r
-reg kf29319;\r
-reg uk3e26b;\r
-reg lqf1359;\r
-reg [1:0] mrc99c0;\r
-reg [1:0] ay4ce05;\r
-reg [1:0] ic67029;\r
-reg [1:0] fp38148;\r
-reg [1:0] rgc0a46;\r
-reg [1:0] ks5233;\r
-reg ep29198;\r
-reg fa48cc5;\r
-reg ww4662b;\r
-reg an33159;\r
-reg aaffa2;\r
-reg [6:0] gb7fd10;\r
-reg zkfe884;\r
-reg ng837ab;\r
-reg ip6f1c7;\r
-reg [7:0] co98acd;\r
-reg ym2b342;\r
-reg dmc5668;\r
-reg medb224;\r
-reg gbd9120;\r
-reg vif4422;\r
-reg lsa2112;\r
-reg aa10892;\r
-reg lf84490;\r
-reg nt22486;\r
-reg sj12436;\r
-reg wy921b4;\r
-reg ep90da0;\r
-reg pu86d04;\r
-reg ohb4114;\r
-reg an858e4;\r
-reg [7 : 0] jra08a4;\r
-reg ls4526;\r
-reg nt22932;\r
-reg jp553cf;\r
-reg gqa9e7f;\r
-reg [1 : 0] vk25af2;\r
-reg [1 : 0] vk14997;\r
-reg [1 : 0] wla4cba;\r
-reg [1 : 0] mt265d4;\r
-reg [1 : 0] lf32ea4;\r
-reg [1 : 0] ie97526;\r
-reg [1 : 0] xlba930;\r
-reg ead4986;\r
-reg qva4c30;\r
-reg qv26184;\r
-reg pu30c24;\r
-reg [6 : 0] ww77d4a;\r
-reg uxbea50;\r
-reg do11dfa;\r
-reg ecbc0e3;\r
-reg [7 : 0] tw86123;\r
-reg nt848db;\r
-reg ba3091b;\r
-reg ri961cf;\r
-reg rvb0e7a;\r
-reg gof5284;\r
-reg uka9420;\r
-reg fn4a101;\r
-reg zx5080f;\r
-reg db8407e;\r
-reg zm203f6;\r
-reg ng1fb3;\r
-reg ecfd9b;\r
-reg [2047:0] shdc077;\r
-wire [35:0] eae03bd;\r
-localparam ba1de9 = 36,ngef4b = 32'hfdffd84b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vif4422 <= 1'b0; lsa2112 <= 1'b0; aa10892 <= 1'b0; lf84490 <= 1'b0; nt22486 <= 1'b0; sj12436 <= 1'b0; end else begin vif4422 <= pu86d04; lsa2112 <= gof5284;\r
- aa10892 <= uka9420; lf84490 <= uka9420 & (~fn4a101); nt22486 <= ~uka9420 & (fn4a101); sj12436 <= zx5080f || db8407e; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin mrc99c0 <= 2'd0; ay4ce05 <= 2'd0; ic67029 <= 2'd0; fp38148 <= 2'd0; rgc0a46 <= 2'd0; ks5233 <= 2'd0; ep29198 <= 1'b1; fa48cc5 <= 1'b0; ww4662b <= 1'b0; an33159 <= 1'b0; end else begin mrc99c0 <= vk25af2; ay4ce05 <= vk14997; ic67029 <= wla4cba; fp38148 <= mt265d4; if ((wla4cba==mt265d4) && (wla4cba==lf32ea4)) rgc0a46 <= lf32ea4; ks5233 <= ie97526; if (zm203f6) ep29198 <= 1'b1; else if (ie97526 != xlba930) ep29198 <= 1'b1; else ep29198 <= 1'b0; if (fn4a101) begin fa48cc5 <= 1'b1; ww4662b <= 1'b0; an33159 <= 1'b0; end else begin fa48cc5 <= ie97526[1]; ww4662b <= !ie97526[1] & ( ie97526[0]); an33159 <= !ie97526[1] & (!ie97526[0]); end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin gb7fd10 <= 7'd0; zkfe884 <= 1'b0; end else begin if (ead4986 || uxbea50) begin gb7fd10 <= 7'd0; end else begin gb7fd10 <= ww77d4a + 1; end\r
- if (ead4986) begin zkfe884 <= 1'b0; end else if (qv26184) begin if (ww77d4a == 7'd8) begin zkfe884 <= 1'b1; end else begin zkfe884 <= 1'b0; end end else if (pu30c24) begin if (ww77d4a == 7'd98) begin zkfe884 <= 1'b1; end else begin zkfe884 <= 1'b0; end end else begin zkfe884 <= 1'b1; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin aaffa2 <= 1'b0; end else begin if (ead4986) begin aaffa2 <= 1'b0; end else if (qv26184) begin if (ww77d4a == 7'd3) begin aaffa2 <= 1'b1; end else begin aaffa2 <= 1'b0; end end else if (pu30c24) begin if (ww77d4a == 7'd49) begin aaffa2 <= 1'b1; end else begin aaffa2 <= 1'b0; end end else begin aaffa2 <= 1'b1; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin dmc5668 <= 0; ym2b342 <= 0; medb224 <= 0; gbd9120 <= 0; co98acd <= 8'd0; end else begin if (an858e4) begin co98acd <= jra08a4; ym2b342 <= nt22932; dmc5668 <= ls4526; medb224 <= jp553cf; gbd9120 <= gqa9e7f; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin wy921b4 <= 1'b0; ep90da0 <= 1'b0; end else begin wy921b4 <= ohb4114; ep90da0 <= ng1fb3; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin sue5263 <= 0; kf29319 <= 0; uk3e26b <= 0; lqf1359 <= 0; vi7ca4c <= 8'd0; end else begin if (an858e4) begin if (ecfd9b) begin sue5263 <= 0; kf29319 <= 0; uk3e26b <= 0; lqf1359 <= 0; vi7ca4c <= 8'd0; end else begin kf29319 <= nt848db; uk3e26b <= ri961cf; lqf1359 <= rvb0e7a; if ((!qva4c30) && ba3091b && (tw86123 == 8'h0F) && (!nt848db) && kf29319) begin sue5263 <= 1'b0; vi7ca4c <= 8'h00; end else begin sue5263 <= ba3091b; vi7ca4c <= tw86123; end end end\r
- end\r
-end\r
-always@* begin pu86d04<=eae03bd[0];ohb4114<=eae03bd[1];an858e4<=eae03bd[2];jra08a4<={an8c7c>>1,eae03bd[3]};ls4526<=eae03bd[4];nt22932<=eae03bd[5];jp553cf<=eae03bd[6];gqa9e7f<=eae03bd[7];vk25af2<={gb5e68a>>1,eae03bd[8]};vk14997<={mrc99c0>>1,eae03bd[9]};wla4cba<={ay4ce05>>1,eae03bd[10]};mt265d4<={ic67029>>1,eae03bd[11]};lf32ea4<={fp38148>>1,eae03bd[12]};ie97526<={rgc0a46>>1,eae03bd[13]};xlba930<={ks5233>>1,eae03bd[14]};ead4986<=eae03bd[15];qva4c30<=eae03bd[16];qv26184<=eae03bd[17];pu30c24<=eae03bd[18];ww77d4a<={gb7fd10>>1,eae03bd[19]};uxbea50<=eae03bd[20];do11dfa<=eae03bd[21];ecbc0e3<=eae03bd[22];tw86123<={co98acd>>1,eae03bd[23]};nt848db<=eae03bd[24];ba3091b<=eae03bd[25];ri961cf<=eae03bd[26];rvb0e7a<=eae03bd[27];gof5284<=eae03bd[28];uka9420<=eae03bd[29];fn4a101<=eae03bd[30];zx5080f<=eae03bd[31];db8407e<=eae03bd[32];zm203f6<=eae03bd[33];ng1fb3<=eae03bd[34];ecfd9b<=eae03bd[35];end\r
-always@* begin shdc077[2047]<=force_isolate;shdc077[2046]<=fa47021;shdc077[2044]<=an8c7c[0];shdc077[2040]<=ic463e5;shdc077[2033]<=qi31f29;shdc077[2019]<=qva4f56;shdc077[1999]<=ep90da0;shdc077[1991]<=rv27ab4;shdc077[1934]<=gb5e68a[0];shdc077[1892]<=zkfe884;shdc077[1851]<=ep29198;shdc077[1820]<=mrc99c0[0];shdc077[1737]<=ng837ab;shdc077[1654]<=fa48cc5;shdc077[1610]<=ym2b342;shdc077[1593]<=ay4ce05[0];shdc077[1523]<=sj12436;shdc077[1426]<=ip6f1c7;shdc077[1404]<=lf84490;shdc077[1260]<=ww4662b;shdc077[1199]<=vif4422;shdc077[1173]<=dmc5668;shdc077[1139]<=ic67029[0];shdc077[1023]<=gbe_mode;shdc077[999]<=wy921b4;shdc077[946]<=gb7fd10[0];shdc077[925]<=ks5233[0];shdc077[805]<=co98acd[0];shdc077[761]<=nt22486;shdc077[702]<=aa10892;shdc077[599]<=gbd9120;shdc077[473]<=an33159;shdc077[462]<=rgc0a46[0];shdc077[351]<=lsa2112;shdc077[299]<=medb224;shdc077[231]<=fp38148[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module shf7264 ( gq88e04,\r
- rst_n,\r
- gbe_mode,\r
- sgmii_mode,\r
- force_unidir,\r
- mr_main_reset,\r
- mr_restart_an,\r
- mr_an_enable,\r
- mr_adv_ability,\r
- mr_lp_adv_ability,\r
- fp9ed2a,\r
- mr_page_rx,\r
- mr_an_complete,\r
- lfa55f5,\r
- fc2afaf,\r
- ne57d7b,\r
- ohbebdb,\r
- kqf5edc,\r
- hdaf6e1,\r
- bl7b70e,\r
- an_link_ok\r
- );\r
-input gq88e04;\r
-input rst_n;\r
-input gbe_mode;\r
-input sgmii_mode;\r
-input force_unidir;\r
-input mr_main_reset;\r
-input mr_restart_an;\r
-input mr_an_enable;\r
-input [16:1] mr_adv_ability;\r
-output [16:1] mr_lp_adv_ability;\r
-input fp9ed2a;\r
-output mr_page_rx;\r
-output mr_an_complete;\r
-input lfa55f5;\r
-input fc2afaf;\r
-input ne57d7b;\r
-input ohbebdb;\r
-input [15:0] kqf5edc;\r
-output [15:0] hdaf6e1;\r
-output [1:0] bl7b70e;\r
-output an_link_ok;\r
-reg [16:1] mr_lp_adv_ability;\r
-reg mr_page_rx;\r
-reg mr_an_complete;\r
-reg [15:0] hdaf6e1;\r
-reg [1:0] bl7b70e;\r
-reg [15:0] cb850a4;\r
-reg [15:0] tj28524;\r
-reg [15:0] vi42927;\r
-reg [15:0] ng1493a;\r
-reg [15:0] kfa49d2;\r
-reg sw24e94;\r
-localparam hd274a0 = 2'b00, vk3a506 = 2'b01, vvd2833 = 2'b10;\r
-localparam bn9419f = 4'b0000, xla0cff = 4'b0001, vx67fe = 4'b0010, sj33ff7 = 4'b0011, oh9ffbc = 4'b0100, ykffde5 = 4'b0101, nefef28 = 4'b0111, enf7942 = 4'b1000;\r
-parameter ecbca14 = 21'h1cf2bf, mee50a1 = 21'h0ced2f, LINK_TIMER_SH = 21'h1fff01;\r
-reg ps4284f;\r
-reg ri1427a;\r
-reg uxa13d3;\r
-reg bn9e9d;\r
-reg th4f4ef;\r
-reg [20:0] gb7a77f;\r
-reg end3bfd;\r
-reg [20:0] sw9dfed;\r
-reg ayeff68;\r
-reg [3:0] al7fb41, enfda0c, ofed065;\r
-wire [15:0] kqf5edc;\r
-reg [15:0] wj41969;\r
-reg [15:0] bncb4d;\r
-reg [15:0] sh65a6f;\r
-reg [ 1:0] hd2d37c;\r
-reg [ 1:0] dm69be7;\r
-reg [ 1:0] tu4df3a;\r
-wire ohbebdb;\r
-reg vi7ce9d;\r
-wire ne57d7b;\r
-reg vk3a75c;\r
-reg uvd3ae3;\r
-reg qi9d71d;\r
-reg pseb8e9;\r
-reg os5c74b;\r
-reg ble3a59;\r
-reg ep1d2cf;\r
-reg zxe967d;\r
-reg sh4b3ef;\r
-reg ww59f7d;\r
-reg hocfbe8;\r
-reg ic7df42;\r
-reg [16:1] suefa11;\r
-reg me7d089;\r
-reg wje8448;\r
-reg tu42245;\r
-reg ba1122b;\r
-reg vk8915b;\r
-reg[15:0] rg48ada;\r
-reg rt456d3;\r
-reg gq2b69e;\r
-reg sh5b4f0;\r
-reg byda784;\r
-reg [16:1] wjd3c22;\r
-reg jr9e115;\r
-reg gof08ae;\r
-reg bn84571;\r
-reg lf22b8e;\r
-reg ec15c77;\r
-reg[15:0] qvae3b8;\r
-reg vv71dc4 ;\r
-reg rv8ee27 ;\r
-wire kq7713e ;\r
-reg [(22*8):1] fcb89f1;\r
-reg pu86d04;\r
-reg lf27c59;\r
-reg ec3e2cf;\r
-reg nef1679;\r
-reg bn8b3ca;\r
-reg qg59e57;\r
-reg [16 : 1] lqcf2b8;\r
-reg tu795c3;\r
-reg zkcae1a;\r
-reg xw570d2;\r
-reg lsb8692;\r
-reg ofc3492;\r
-reg [15 : 0] mg1a495;\r
-reg [15 : 0] hbd24a8;\r
-reg [15 : 0] mg92546;\r
-reg [15 : 0] aa92a30;\r
-reg [15 : 0] oh95181;\r
-reg vka8c0d;\r
-reg go4606a;\r
-reg ba30351;\r
-reg jr81a8a;\r
-reg and457;\r
-reg gb6a2bc;\r
-reg [20 : 0] sh515e4;\r
-reg cb8af25;\r
-reg [20 : 0] vi5792c;\r
-reg ymbc963;\r
-reg [3 : 0] rge4b19;\r
-reg [3 : 0] xy258ca;\r
-reg [3 : 0] ux2c652;\r
-reg [15 : 0] dm63295;\r
-reg [15 : 0] rv194aa;\r
-reg [15 : 0] xwca557;\r
-reg [1 : 0] lq52abb;\r
-reg [1 : 0] yz955db;\r
-reg [1 : 0] zzaaedd;\r
-reg rg576ef;\r
-reg qvbb77a;\r
-reg eadbbd5;\r
-reg zxddea9;\r
-reg eaef54e;\r
-reg cz7aa70;\r
-reg tud5384;\r
-reg iea9c23;\r
-reg ip4e118;\r
-reg wj708c5;\r
-reg zz8462d;\r
-reg ux2316e;\r
-reg wl18b74;\r
-reg [16 : 1] hoc5ba4;\r
-reg lf2dd23;\r
-reg hb6e91e;\r
-reg fn748f7;\r
-reg sja47bf;\r
-reg kf23dfd;\r
-reg [15 : 0] xy1efed;\r
-reg uvf7f6b;\r
-reg fpbfb5c;\r
-reg shfdae6;\r
-reg wjed735;\r
-reg [16 : 1] vv6b9ad;\r
-reg kq5cd6f;\r
-reg rte6b78;\r
-reg ba35bc7;\r
-reg lsade3b;\r
-reg gb6f1da;\r
-reg [15 : 0] qg78ed4;\r
-reg hbc76a1;\r
-reg ie3b50f;\r
-reg tuda879;\r
-reg [(22 * 8) : 1] med43cb;\r
-reg [2047:0] shdc077;\r
-wire [70:0] eae03bd;\r
-localparam ba1de9 = 71,ngef4b = 32'hfdffc70b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if(!rst_n) begin vv71dc4 <= 1'b1; rv8ee27 <= 1'b1; end else begin vv71dc4 <= nef1679; rv8ee27 <= hbc76a1; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if(!rst_n) begin sh4b3ef <= 1'b0; ww59f7d <= 1'b0; hocfbe8 <= 1'b0; ic7df42 <= 1'b0; suefa11 <= 16'd0; me7d089 <= 1'b0; wje8448 <= 1'b0; tu42245 <= 1'b0; ba1122b <= 1'b0; vk8915b <= 1'b0; rg48ada <= 16'b0; rt456d3 <= 1'b0; gq2b69e <= 1'b0; sh5b4f0 <= 1'b0; byda784 <= 1'b0; wjd3c22 <= 16'b0; jr9e115 <= 1'b0; gof08ae <= 1'b0; bn84571 <= 1'b0; lf22b8e <= 1'b0; ec15c77 <= 1'b0; qvae3b8 <= 16'b0; end else begin sh4b3ef <= pu86d04; ww59f7d <= lf27c59; hocfbe8 <= bn8b3ca; ic7df42 <= qg59e57 & (!ec3e2cf); suefa11 <= lqcf2b8; me7d089 <= tu795c3; wje8448 <= zkcae1a; tu42245 <= xw570d2; ba1122b <= lsb8692; vk8915b <= ofc3492; rg48ada <= kqf5edc; rt456d3 <= wj708c5; gq2b69e <= zz8462d; sh5b4f0 <= ux2316e; byda784 <= wl18b74; wjd3c22 <= hoc5ba4; jr9e115 <= lf2dd23; gof08ae <= hb6e91e; bn84571 <= fn748f7; lf22b8e <= sja47bf; ec15c77 <= kf23dfd; qvae3b8 <= xy1efed; end\r
-end\r
-assign kq7713e = (qg78ed4[15] == rv194aa[15]) & (qg78ed4[13:0] == rv194aa[13:0]);\r
-always @(posedge gq88e04 or negedge rst_n) begin : ie24984 if(!rst_n) begin vk3a75c <= 1'b0; uvd3ae3 <= 1'b0; qi9d71d <= 1'b0; pseb8e9 <= 1'b0; os5c74b <= 1'b0; ble3a59 <= 1'b0; ep1d2cf <= 1'b0; zxe967d <= 1'b0; end else begin vk3a75c <= (go4606a != wjed735); uvd3ae3 <= tuda879 ; qi9d71d <= tuda879 & qg78ed4[14] & rv194aa[14]; pseb8e9 <= (lq52abb == 2'b10) & rg576ef; os5c74b <= (yz955db == 2'b10) & rg576ef; ble3a59 <= (zzaaedd == 2'b11); ep1d2cf <= (lq52abb == 2'b10) & rg576ef & tuda879 ; zxe967d <= (ux2c652 != xy258ca); end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : lqee2f4 if(!rst_n) begin enfda0c <= bn9419f; end else begin if(shfdae6 || !ymbc963 || qvbb77a || ba35bc7 || vka8c0d || ie3b50f) begin enfda0c <= bn9419f; end else begin enfda0c <= rge4b19; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin if(!rst_n) begin ofed065 <= bn9419f; ps4284f <= 1'b0; vi7ce9d <= 1'b0; wj41969 <= 16'h0000; end else begin if(ie3b50f) begin ofed065 <= bn9419f; end else begin ofed065 <= xy258ca; ps4284f <= wjed735; vi7ce9d <= gb6f1da; wj41969 <= qg78ed4; end end\r
-end\r
-always @( xy258ca or wjed735 or cb8af25 or eaef54e or dm63295 or cz7aa70 or iea9c23 or tud5384) begin : cb85a23 case (xy258ca) bn9419f : begin if(wjed735) al7fb41 = xla0cff; else al7fb41 = vx67fe; end\r
- xla0cff : begin if(cb8af25) al7fb41 = sj33ff7; else al7fb41 = xla0cff; end\r
- sj33ff7 : begin if(eaef54e && dm63295 != 16'd0) al7fb41 = oh9ffbc; else al7fb41 = sj33ff7; end\r
- oh9ffbc : begin if((cz7aa70 && !iea9c23) || (eaef54e && dm63295 == 16'h0000)) al7fb41 = bn9419f; else if(cz7aa70 && iea9c23) al7fb41 = ykffde5; else al7fb41 = oh9ffbc; end\r
- ykffde5 : begin if(eaef54e && dm63295 == 16'h0000) al7fb41 = bn9419f; else if((cb8af25) && (!eaef54e || dm63295 != 16'h0000)) al7fb41 = nefef28; else al7fb41 = ykffde5; end\r
- nefef28 : begin if (eaef54e && dm63295 == 16'h0000) al7fb41 = bn9419f; else if (tud5384 && cb8af25) al7fb41 = enf7942; else al7fb41 = nefef28; end\r
- enf7942 : begin if (eaef54e) al7fb41 = bn9419f; else al7fb41 = enf7942; end\r
- vx67fe : al7fb41 = vx67fe;\r
- default : begin al7fb41 = bn9419f; end\r
- endcase\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin if(!rst_n) begin mr_page_rx <= 1'b0; end else begin if (xy258ca == ykffde5) begin mr_page_rx <= 1'b1; end else begin mr_page_rx <= 1'b0; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin if(!rst_n ) begin mr_lp_adv_ability <= 16'h0000; end else begin if ((xy258ca == bn9419f) || (xy258ca == sj33ff7)) begin mr_lp_adv_ability <= 16'h0000; end else if (xy258ca == ykffde5) begin mr_lp_adv_ability <= qg78ed4; end else begin mr_lp_adv_ability <= mr_lp_adv_ability; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : czcceef if(!rst_n ) begin mr_an_complete <= 1'b0; end else begin if (xy258ca == bn9419f) begin mr_an_complete <= 1'b0; end else if (xy258ca == enf7942) begin mr_an_complete <= 1'b1; end else begin mr_an_complete <= mr_an_complete; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : sh7f07b if(!rst_n ) begin hdaf6e1 <= 16'd0; end else begin if ((xy258ca == bn9419f && wjed735) || (xy258ca == xla0cff)) begin hdaf6e1 <= 16'd0; end else if (xy258ca == sj33ff7) begin hdaf6e1 <= {vv6b9ad[16],1'b0,vv6b9ad[14:1]}; end else if (xy258ca == oh9ffbc) begin hdaf6e1 <= (hdaf6e1 | 16'h4000); end else begin hdaf6e1 <= hdaf6e1; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : xy2ae8f if(!rst_n ) begin bl7b70e <= hd274a0; end else begin if (((xy258ca == bn9419f) && wjed735) || (xy258ca == xla0cff)) begin bl7b70e <= vk3a506; end else if (((xy258ca == bn9419f) && !wjed735) || (xy258ca == nefef28)) begin bl7b70e <= hd274a0; end else if ((xy258ca == vx67fe) || (xy258ca == enf7942)) begin bl7b70e <= vvd2833; end else begin bl7b70e <= bl7b70e; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin if(!rst_n ) begin uxa13d3 <= 1'b0; bn9e9d <= 1'b0; th4f4ef <= 1'b0; ri1427a <= 1'b0; end else begin if ((xy258ca == xla0cff) && (ux2c652 == bn9419f)) begin uxa13d3 <= 1'b1; end else begin uxa13d3 <= 1'b0; end if ((xy258ca == ykffde5) && (ux2c652 == oh9ffbc)) begin bn9e9d <= 1'b1; end else begin bn9e9d <= 1'b0; end if ((xy258ca == nefef28) && (ux2c652 == ykffde5)) begin th4f4ef <= 1'b1; end else begin th4f4ef <= 1'b0; end if (jr81a8a || and457 || gb6a2bc) begin ri1427a <= 1'b1; end else begin ri1427a <= 1'b0; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : wje876e if(!rst_n ) begin gb7a77f <= ecbca14; end else if (ba30351) begin if (kq5cd6f) begin gb7a77f <= LINK_TIMER_SH; end else if (uvf7f6b) begin gb7a77f <= mee50a1; end else begin gb7a77f <= ecbca14; end end else if (!cb8af25) begin gb7a77f <= sh515e4 + 'd1; end else begin gb7a77f <= sh515e4; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : kf9537b if(!rst_n ) begin end3bfd <= 1'b0; end else begin if (sh515e4 == 'd0 && !ba30351) begin end3bfd <= 1'b1; end else begin end3bfd <= 1'b0; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : nre6f46 if(!rst_n ) begin sw9dfed <= 21'd0; end else if (rte6b78) begin if (kq5cd6f) begin sw9dfed <= LINK_TIMER_SH; end else if (uvf7f6b) begin sw9dfed <= mee50a1; end else begin sw9dfed <= ecbca14; end end else begin sw9dfed <= vi5792c + 'd1; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : ukb3047 if(!rst_n ) begin ayeff68 <= 1'b0; end else begin case(ymbc963) 1'b0: begin if (rte6b78) begin ayeff68 <= 1'b1; end end 1'b1: begin if(vi5792c == 21'd0) begin ayeff68 <= 1'b0; end end default: begin ayeff68 <= 1'b0; end endcase end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : fae4788 if(!rst_n ) bncb4d <= 16'h0000; else if(ip4e118) bncb4d <= 16'h0000; else if(gb6f1da) bncb4d <= qg78ed4; else bncb4d <= rv194aa;\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : fp28568 if(!rst_n ) begin sh65a6f <= 16'h0000; end else begin if(eaef54e) begin sh65a6f <= qg78ed4; end else begin sh65a6f <= xwca557; end end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : wjc36dd if(!rst_n ) hd2d37c <= 2'b00; else if(ip4e118 || lsade3b || (gb6f1da && !eadbbd5)) hd2d37c <= 2'b00; else if(gb6f1da && eadbbd5 && (lq52abb != 2'b10)) hd2d37c <= lq52abb + 2'b01; else hd2d37c <= lq52abb;\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : sh4161b if(!rst_n ) dm69be7 <= 2'b00; else if(ip4e118 || lsade3b) dm69be7 <= 2'b00; else if(gb6f1da && zxddea9 && (yz955db != 2'b10)) dm69be7 <= yz955db + 2'b01; else dm69be7 <= yz955db;\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin : rgda4a3 if(!rst_n ) tu4df3a <= 2'b00; else if(ip4e118) tu4df3a <= 2'b00; else if(lsade3b && !tud5384) tu4df3a <= zzaaedd + 2'b01; else tu4df3a <= zzaaedd;\r
-end\r
-always @(posedge gq88e04 or negedge rst_n) begin if(!rst_n) begin cb850a4 <= 16'd0; tj28524 <= 16'd0; vi42927 <= 16'd0; ng1493a <= 16'd0; kfa49d2 <= 16'd0; sw24e94 <= 1'b0; end else begin cb850a4[15:0] <= vv6b9ad[16:1]; tj28524 <= mg1a495; vi42927 <= hbd24a8; if ((mg1a495 == hbd24a8) && (mg1a495 == mg92546)) kfa49d2 <= mg92546; else kfa49d2 <= oh95181; ng1493a <= oh95181; if ((fpbfb5c==1'b1) && (uvf7f6b==1'b0)) begin if (oh95181 != aa92a30) begin sw24e94 <= 1'b1; end else begin sw24e94 <= 1'b0; end end else begin sw24e94 <= 1'b0; end end\r
-end\r
-assign an_link_ok = ((xy258ca==enf7942) || (xy258ca==vx67fe)) ? 1'b1 : 1'b0;\r
-always @(xy258ca) begin case (xy258ca) bn9419f : fcb89f1 = "AN_ENABLE"; xla0cff : fcb89f1 = "AN_RESTART"; vx67fe : fcb89f1 = "AN_DISABLE_LINK_OK"; sj33ff7 : fcb89f1 = "ABILITY_DETECT"; oh9ffbc : fcb89f1 = "ACKNOWLEDGE_DETECT"; ykffde5 : fcb89f1 = "COMPLETE_ACKNOWLEDGE"; nefef28 : fcb89f1 = "IDLE_DETECT"; enf7942 : fcb89f1 = "LINK_OK";\r
- default : fcb89f1 = "***ERROR***"; endcase\r
-end\r
-always@* begin pu86d04<=eae03bd[0];lf27c59<=eae03bd[1];ec3e2cf<=eae03bd[2];nef1679<=eae03bd[3];bn8b3ca<=eae03bd[4];qg59e57<=eae03bd[5];lqcf2b8<={mr_adv_ability>>1,eae03bd[6]};tu795c3<=eae03bd[7];zkcae1a<=eae03bd[8];xw570d2<=eae03bd[9];lsb8692<=eae03bd[10];ofc3492<=eae03bd[11];mg1a495<={cb850a4>>1,eae03bd[12]};hbd24a8<={tj28524>>1,eae03bd[13]};mg92546<={vi42927>>1,eae03bd[14]};aa92a30<={ng1493a>>1,eae03bd[15]};oh95181<={kfa49d2>>1,eae03bd[16]};vka8c0d<=eae03bd[17];go4606a<=eae03bd[18];ba30351<=eae03bd[19];jr81a8a<=eae03bd[20];and457<=eae03bd[21];gb6a2bc<=eae03bd[22];sh515e4<={gb7a77f>>1,eae03bd[23]};cb8af25<=eae03bd[24];vi5792c<={sw9dfed>>1,eae03bd[25]};ymbc963<=eae03bd[26];rge4b19<={al7fb41>>1,eae03bd[27]};xy258ca<={enfda0c>>1,eae03bd[28]};ux2c652<={ofed065>>1,eae03bd[29]};dm63295<={wj41969>>1,eae03bd[30]};rv194aa<={bncb4d>>1,eae03bd[31]};xwca557<={sh65a6f>>1,eae03bd[32]};lq52abb<={hd2d37c>>1,eae03bd[33]};yz955db<={dm69be7>>1,eae03bd[34]};zzaaedd<={tu4df3a>>1,eae03bd[35]};rg576ef<=eae03bd[36];qvbb77a<=eae03bd[37];eadbbd5<=eae03bd[38];zxddea9<=eae03bd[39];eaef54e<=eae03bd[40];cz7aa70<=eae03bd[41];tud5384<=eae03bd[42];iea9c23<=eae03bd[43];ip4e118<=eae03bd[44];wj708c5<=eae03bd[45];zz8462d<=eae03bd[46];ux2316e<=eae03bd[47];wl18b74<=eae03bd[48];hoc5ba4<={suefa11>>1,eae03bd[49]};lf2dd23<=eae03bd[50];hb6e91e<=eae03bd[51];fn748f7<=eae03bd[52];sja47bf<=eae03bd[53];kf23dfd<=eae03bd[54];xy1efed<={rg48ada>>1,eae03bd[55]};uvf7f6b<=eae03bd[56];fpbfb5c<=eae03bd[57];shfdae6<=eae03bd[58];wjed735<=eae03bd[59];vv6b9ad<={wjd3c22>>1,eae03bd[60]};kq5cd6f<=eae03bd[61];rte6b78<=eae03bd[62];ba35bc7<=eae03bd[63];lsade3b<=eae03bd[64];gb6f1da<=eae03bd[65];qg78ed4<={qvae3b8>>1,eae03bd[66]};hbc76a1<=eae03bd[67];ie3b50f<=eae03bd[68];tuda879<=eae03bd[69];med43cb<={fcb89f1>>1,eae03bd[70]};end\r
-always@* begin shdc077[2047]<=sgmii_mode;shdc077[2046]<=force_unidir;shdc077[2044]<=mr_main_reset;shdc077[2040]<=mr_restart_an;shdc077[2032]<=mr_an_enable;shdc077[2016]<=mr_adv_ability[1];shdc077[2014]<=fcb89f1[1];shdc077[1985]<=fp9ed2a;shdc077[1927]<=gof08ae;shdc077[1922]<=lfa55f5;shdc077[1867]<=ri1427a;shdc077[1807]<=bn84571;shdc077[1804]<=hocfbe8;shdc077[1797]<=fc2afaf;shdc077[1761]<=zxe967d;shdc077[1686]<=uxa13d3;shdc077[1623]<=vk8915b;shdc077[1567]<=lf22b8e;shdc077[1561]<=ic7df42;shdc077[1558]<=enfda0c[0];shdc077[1547]<=ne57d7b;shdc077[1542]<=vi7ce9d;shdc077[1505]<=wjd3c22[1];shdc077[1490]<=sw24e94;shdc077[1475]<=sh4b3ef;shdc077[1413]<=ayeff68;shdc077[1409]<=dm69be7[0];shdc077[1400]<=sh5b4f0;shdc077[1324]<=bn9e9d;shdc077[1200]<=gb7a77f[0];shdc077[1199]<=rg48ada[0];shdc077[1086]<=ec15c77;shdc077[1074]<=suefa11[1];shdc077[1068]<=ofed065[0];shdc077[1047]<=ohbebdb;shdc077[1037]<=vk3a75c;shdc077[1023]<=gbe_mode;shdc077[1007]<=kq7713e;shdc077[963]<=jr9e115;shdc077[933]<=ps4284f;shdc077[902]<=ww59f7d;shdc077[880]<=ep1d2cf;shdc077[811]<=ba1122b;shdc077[779]<=al7fb41[0];shdc077[771]<=tu4df3a[0];shdc077[752]<=byda784;shdc077[745]<=kfa49d2[0];shdc077[706]<=sw9dfed[0];shdc077[704]<=hd2d37c[0];shdc077[700]<=gq2b69e;shdc077[600]<=th4f4ef;shdc077[503]<=rv8ee27;shdc077[440]<=ble3a59;shdc077[405]<=tu42245;shdc077[372]<=ng1493a[0];shdc077[353]<=end3bfd;shdc077[352]<=sh65a6f[0];shdc077[350]<=rt456d3;shdc077[251]<=vv71dc4;shdc077[220]<=os5c74b;shdc077[202]<=wje8448;shdc077[186]<=vi42927[0];shdc077[176]<=bncb4d[0];shdc077[125]<=qvae3b8[0];shdc077[110]<=pseb8e9;shdc077[101]<=me7d089;shdc077[93]<=tj28524[0];shdc077[88]<=wj41969[0];shdc077[55]<=qi9d71d;shdc077[46]<=cb850a4[0];shdc077[27]<=uvd3ae3;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module pf74aee (\r
- vxa5777 ,\r
- rst_n ,\r
- mr_main_reset ,\r
- sgmii_mode ,\r
- gbe_mode ,\r
- zzbf298 ,\r
- rx_data ,\r
- rx_kcntl ,\r
- su531f3 ,\r
- lfa55f5 ,\r
- rx_even ,\r
- bl7b70e ,\r
- kqf5edc ,\r
- co9818f ,\r
- hoc0c79 ,\r
- lf63cb ,\r
- ou31e5f ,\r
- mt8f2f9 ,\r
- by797cd\r
- );\r
-input vxa5777;\r
-input rst_n;\r
-input mr_main_reset;\r
-input sgmii_mode;\r
-input gbe_mode;\r
-input zzbf298;\r
-input [7:0] rx_data;\r
-input rx_kcntl;\r
-input su531f3;\r
-input lfa55f5;\r
-input rx_even;\r
-input [1:0] bl7b70e;\r
-output [15:0] kqf5edc;\r
-output co9818f;\r
-output hoc0c79;\r
-output lf63cb;\r
-output [7:0] ou31e5f;\r
-output mt8f2f9;\r
-output by797cd;\r
-localparam qge0963 = 8'hBC , pu4b18 = 8'hFE , vk258c3 = 8'hFB , ep2c61a = 8'hFD , fa630d5 = 8'hF7 , gd186aa = 8'hB5 , ofc3555 = 8'h42 , mg1aaad = 8'hC5 , jcd5569 = 8'h50 , jraab4b = 8'h00 , vv55a5f = 8'hFC , vkad2fe = 8'h3C ;\r
-localparam lq697f3 = 5'd0 , kd4bf9b = 5'd1 , jp5fcdc = 5'd2 , lqfe6e7 = 5'd3 , thf373b = 5'd4 , bn9b9df = 5'd5 , aldceff = 5'd6 , ofe77fc = 5'd7 , ym3bfe4 = 5'd8 , nedff20 = 5'd9 , qgff903 = 5'd10 , dzfc818 = 5'd11 , fae40c7 = 5'd12 , je2063b = 5'd13 , rv31db = 5'd14 , mt18edf = 5'd15 , hbc76fc = 5'd16 , ie3b7e7 = 5'd17 ;\r
-reg sudbf39;\r
-wire fadf9c9;\r
-wire by797cd;\r
-reg mt8f2f9;\r
-reg [7:0] ou31e5f;\r
-reg gbc97e4;\r
-reg [15:0] kqf5edc;\r
-reg co9818f;\r
-reg hoc0c79;\r
-reg lf63cb;\r
-reg [7:0] mg249fa ;\r
-reg [7:0] ie24fd0 ;\r
-reg [7:0] fp27e80 ;\r
-reg [7:0] je3f407 ;\r
-reg [7:0] ayfa03b ;\r
-reg hod01d9 ;\r
-reg sj80ecb ;\r
-reg ux765d ;\r
-reg ie3b2ed ;\r
-reg uvd9769 ;\r
-reg uicbb4d ;\r
-reg jc5da68 ;\r
-reg iped342 ;\r
-reg lq69a15 ;\r
-reg fa4d0aa ;\r
-reg su68552 ;\r
-reg ne42a91 ;\r
-reg aa1548a ;\r
-reg phaa451 ;\r
-reg lq5228e ;\r
-reg vx91472 ;\r
-reg an8a397 ;\r
-reg kd51cbd ;\r
-reg nt8e5ec ;\r
-reg ic72f67 ;\r
-reg ks97b38 ;\r
-reg pubd9c1 ;\r
-reg zxece0b ;\r
-reg me6705e ;\r
-reg [4:0] lf382f0 ;\r
-reg [4:0] mec1786 ;\r
-wire twbc30 ;\r
-wire cz5e182 ;\r
-wire cmf0c14 ;\r
-wire tw860a1 ;\r
-wire ba3050b ;\r
-wire gq8285a ;\r
-wire xy142d0 ;\r
-wire qva1683 ;\r
-wire twb41d ;\r
-wire hb5a0eb ;\r
-wire rgd075e ;\r
-wire tw83af3 ;\r
-wire yz1d79a ;\r
-wire byebcd5 ;\r
-reg [1:0] ip5e6ab;\r
-reg [1:0] blf355c;\r
-reg vv71dc4 ;\r
-reg rv8ee27 ;\r
-reg irab9eb;\r
-reg kq5cf5d;\r
-reg qte7ae8;\r
-reg vx3d745;\r
-reg vif4422;\r
-reg lsa2112;\r
-reg [(20*8):1] ipe8b9b;\r
-reg nef1679;\r
-reg lf27c59;\r
-reg pu86d04;\r
-reg tj9b9c3;\r
-reg [7 : 0] ofdce1f;\r
-reg wje70fc;\r
-reg nt387e4;\r
-reg zkcae1a;\r
-reg gq1f934;\r
-reg [1 : 0] pffc9a1;\r
-reg xwe4d0f;\r
-reg ux2687a;\r
-reg ym343d5;\r
-reg [7 : 0] kfa1ea8;\r
-reg [7 : 0] swf544;\r
-reg [7 : 0] yx7aa21;\r
-reg [7 : 0] ned510c;\r
-reg [7 : 0] nga8863;\r
-reg wj4431a;\r
-reg uk218d4;\r
-reg xlc6a0;\r
-reg ho63506;\r
-reg uk1a832;\r
-reg uid4191;\r
-reg tja0c89;\r
-reg ph644e;\r
-reg xl32277;\r
-reg hd913bf;\r
-reg ri89dff;\r
-reg qt4effb;\r
-reg cm77fdc;\r
-reg rvbfee0;\r
-reg icff706;\r
-reg tufb831;\r
-reg aldc18a;\r
-reg qge0c55;\r
-reg rv62a8;\r
-reg ks31547;\r
-reg cb8aa38;\r
-reg xj551c4;\r
-reg pua8e27;\r
-reg lq4713a;\r
-reg [4 : 0] rv389d3;\r
-reg [4 : 0] mec4e9f;\r
-reg zz274f9;\r
-reg je3a7ce;\r
-reg czd3e73;\r
-reg ep9f39d;\r
-reg vvf9cec;\r
-reg suce767;\r
-reg xw73b39;\r
-reg aa9d9ca;\r
-reg pfece50;\r
-reg kq67286;\r
-reg ux39430;\r
-reg hoca184;\r
-reg pf50c23;\r
-reg zm8611e;\r
-reg [1 : 0] xy308f3;\r
-reg [1 : 0] hd8479b;\r
-reg hbc76a1;\r
-reg ie3b50f;\r
-reg vvf37aa;\r
-reg rv9bd57;\r
-reg wwdeabf;\r
-reg kqf55f9;\r
-reg gof5284;\r
-reg uka9420;\r
-reg [(20 * 8) : 1] rvbf23b;\r
-reg [2047:0] shdc077;\r
-wire [68:0] eae03bd;\r
-localparam ba1de9 = 69,ngef4b = 32'hfdffe0cb;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-always @(posedge vxa5777 or negedge rst_n) begin if (!rst_n) begin mg249fa <= 8'h00 ; ie24fd0 <= 8'h00 ; fp27e80 <= 8'h00 ; je3f407 <= 8'h00 ; ayfa03b <= 8'h00 ; hod01d9 <= 1'b0 ; sj80ecb <= 1'b0 ; ux765d <= 1'b0 ; ie3b2ed <= 1'b0 ; uvd9769 <= 1'b0 ; uicbb4d <= 1'b0 ; jc5da68 <= 1'b0 ; iped342 <= 1'b0 ; lq69a15 <= 1'b0 ; fa4d0aa <= 1'b0 ; su68552 <= 1'b0 ; ne42a91 <= 1'b0 ; end else begin mg249fa <= ofdce1f ; ie24fd0 <= kfa1ea8 ; fp27e80 <= swf544 ; je3f407 <= yx7aa21 ; ayfa03b <= ned510c ; hod01d9 <= wje70fc ; sj80ecb <= wj4431a ; ux765d <= uk218d4 ; ie3b2ed <= xlc6a0 ; uvd9769 <= nt387e4 ; uicbb4d <= uk1a832 ; jc5da68 <= uid4191 ; iped342 <= tja0c89 ; fa4d0aa <= gq1f934 ; su68552 <= hd913bf ; ne42a91 <= ri89dff ; end\r
-end\r
-always @(posedge vxa5777 or negedge rst_n)\r
-begin if(!rst_n) begin vv71dc4 <= 1'b1; rv8ee27 <= 1'b1; end else begin vv71dc4 <= nef1679; rv8ee27 <= hbc76a1; end\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if (!rst_n) begin ip5e6ab <= 2'd0 ; blf355c <= 2'd0 ; irab9eb <= 1'b0 ; kq5cf5d <= 1'b0 ; qte7ae8 <= 1'b0 ; vx3d745 <= 1'b0 ; vif4422 <= 1'b0 ; lsa2112 <= 1'b0 ; end else begin ip5e6ab <= pffc9a1 ; blf355c <= xy308f3 ; irab9eb <= tj9b9c3 ; kq5cf5d <= vvf37aa ; qte7ae8 <= lf27c59 ; vx3d745 <= wwdeabf ; vif4422 <= pu86d04 ; lsa2112 <= gof5284 ; end\r
-end\r
-assign twbc30 = ((yx7aa21 == qge0963) & xlc6a0) ;\r
-assign cz5e182 = ((yx7aa21 == vk258c3) & xlc6a0) ;\r
-assign cmf0c14 = ((yx7aa21 == gd186aa) & ~xlc6a0) ;\r
-assign tw860a1 = ((yx7aa21 == ofc3555) & ~xlc6a0) ;\r
-assign ba3050b = ~((yx7aa21 == qge0963) & xlc6a0) ;\r
-always @(posedge vxa5777 or negedge rst_n) begin if (!rst_n) begin aa1548a <= 1'b0 ; phaa451 <= 1'b0 ; lq5228e <= 1'b0 ; vx91472 <= 1'b0 ; an8a397 <= 1'b0 ; end else begin aa1548a <= zz274f9 ; phaa451 <= je3a7ce ; lq5228e <= czd3e73 ; vx91472 <= ep9f39d ; an8a397 <= vvf9cec ; end\r
-end\r
-assign gq8285a = (((yx7aa21 == qge0963) & xlc6a0 ) & ( ~uk218d4 ) & ((kfa1ea8 == qge0963) & wj4431a ) ) ;\r
-assign xy142d0 = (((yx7aa21 == qge0963) & xlc6a0 ) & (((swf544 == gd186aa) | (swf544 == ofc3555)) & ~uk218d4 ) & ((kfa1ea8 == jraab4b) & ~wj4431a ) ) ;\r
-assign qva1683 = (((yx7aa21 == ep2c61a) & xlc6a0 ) & ((swf544 == fa630d5) & uk218d4 ) & ((kfa1ea8 == qge0963) & wj4431a ) ) ;\r
-assign twb41d = (((yx7aa21 == ep2c61a) & xlc6a0 ) & ((swf544 == fa630d5) & uk218d4 ) & ((kfa1ea8 == fa630d5) & wj4431a ) ) ;\r
-assign hb5a0eb = (((yx7aa21 == fa630d5) & xlc6a0 ) & ((swf544 == fa630d5) & uk218d4 ) & ((kfa1ea8 == fa630d5) & wj4431a ) ) ;\r
-assign rgd075e = (((yx7aa21 == fa630d5) & xlc6a0 ) & ((swf544 == fa630d5) & uk218d4 ) & ((kfa1ea8 == qge0963) & wj4431a ) ) ;\r
-assign tw83af3 = (((yx7aa21 == fa630d5) & xlc6a0 ) & ((swf544 == fa630d5) & uk218d4 ) & ((kfa1ea8 == vk258c3) & wj4431a ) ) ;\r
-always @(posedge vxa5777 or negedge rst_n) begin if (!rst_n) begin kd51cbd <= 1'b0 ; nt8e5ec <= 1'b0 ; ic72f67 <= 1'b0 ; ks97b38 <= 1'b0 ; pubd9c1 <= 1'b0 ; zxece0b <= 1'b0 ; me6705e <= 1'b0 ; end else begin kd51cbd <= suce767 ; nt8e5ec <= xw73b39 ; ic72f67 <= aa9d9ca ; ks97b38 <= pfece50 ; pubd9c1 <= kq67286 ; zxece0b <= ux39430 ; me6705e <= hoca184 ; end\r
-end\r
- assign yz1d79a = (hd8479b == 2'b01) ; assign byebcd5 = (hd8479b == 2'b10) ;\r
-always @(posedge vxa5777 or negedge rst_n) begin if (!rst_n) lf382f0 <= kd4bf9b ; else if (ie3b50f) lf382f0 <= kd4bf9b ; else if (!zkcae1a) lf382f0 <= lq697f3 ; else lf382f0 <= mec4e9f ;\r
-end\r
-always @(rv389d3 or ri89dff or zm8611e or pf50c23 or ho63506 or ph644e or qge0c55 or rv62a8 or ks31547 or cb8aa38 or xj551c4 or pua8e27 or lq4713a or cm77fdc or rvbfee0 or icff706 or tufb831 or aldc18a ) begin case (rv389d3) lq697f3 : mec1786 = kd4bf9b ; kd4bf9b : if (cm77fdc && ri89dff) mec1786 = jp5fcdc ; else mec1786 = kd4bf9b ; jp5fcdc : if (icff706 || tufb831) mec1786 = lqfe6e7 ; else if (!zm8611e && (ho63506 || ph644e)) mec1786 = aldceff ; else if ((!zm8611e && (!ho63506 && !ph644e) && !icff706 && !tufb831) || (zm8611e && !icff706 && !tufb831)) mec1786 = ofe77fc ; else mec1786 = jp5fcdc ; lqfe6e7 : if (!ho63506 && !ph644e) mec1786 = thf373b ; else mec1786 = aldceff ; thf373b : if (!ho63506 && !ph644e) mec1786 = bn9b9df ; else mec1786 = aldceff ; bn9b9df : if (cm77fdc && ri89dff) mec1786 = jp5fcdc ; else if (!cm77fdc || !ri89dff) mec1786 = aldceff ; else mec1786 = bn9b9df ; aldceff : if (cm77fdc && ri89dff) mec1786 = jp5fcdc; else if (!cm77fdc && ri89dff) mec1786 = kd4bf9b; else mec1786 = aldceff; ofe77fc : if (!cm77fdc && !zm8611e) mec1786 = aldceff; else if (zm8611e && aldc18a) if (!rvbfee0) mec1786 = ym3bfe4; else mec1786 = nedff20; else if ((zm8611e && !aldc18a) || cm77fdc) mec1786 = jp5fcdc; else mec1786 = ofe77fc; ym3bfe4 : if (cm77fdc && ri89dff) mec1786 = jp5fcdc; else mec1786 = ym3bfe4; nedff20 : if ((qge0c55 || rv62a8) && ri89dff) mec1786 = qgff903; else if (ks31547 && ri89dff) mec1786 = dzfc818; else if (cb8aa38) mec1786 = fae40c7; else if (xj551c4) mec1786 = mt18edf; else if (!ho63506 && !ph644e) mec1786 = rv31db; else mec1786 = je2063b; qgff903 : if (!icff706 && !tufb831) mec1786 = ofe77fc; else mec1786 = lqfe6e7; dzfc818 : if (cm77fdc) mec1786 = jp5fcdc; else mec1786 = dzfc818; fae40c7 : if (xj551c4) mec1786 = fae40c7; else if (pua8e27 && ri89dff) mec1786 = dzfc818; else if (lq4713a) mec1786 = hbc76fc; else mec1786 = ie3b7e7; je2063b : if ((qge0c55 || rv62a8) && ri89dff) mec1786 = qgff903; else if (ks31547 && ri89dff) mec1786 = dzfc818; else if (cb8aa38) mec1786 = fae40c7; else if (xj551c4) mec1786 = mt18edf; else if (!ho63506 && !ph644e) mec1786 = rv31db; else mec1786 = je2063b; rv31db : if ((qge0c55 || rv62a8) && ri89dff) mec1786 = qgff903; else if (ks31547 && ri89dff) mec1786 = dzfc818; else if (cb8aa38) mec1786 = fae40c7; else if (xj551c4) mec1786 = mt18edf; else if (!ho63506 && !ph644e) mec1786 = rv31db; else mec1786 = je2063b; mt18edf : if (xj551c4) mec1786 = fae40c7; else if (pua8e27 && ri89dff) mec1786 = dzfc818; else if (lq4713a) mec1786 = hbc76fc; else mec1786 = ie3b7e7; hbc76fc : if (rvbfee0) mec1786 = nedff20; else mec1786 = hbc76fc; ie3b7e7 : if (rvbfee0) mec1786 = nedff20; else if (cm77fdc && ri89dff) mec1786 = jp5fcdc; else if (!rvbfee0 && !cm77fdc && ri89dff) if (xj551c4) mec1786 = fae40c7; else if (pua8e27 && ri89dff) mec1786 = dzfc818; else if (lq4713a) mec1786 = hbc76fc; else mec1786 = ie3b7e7; else mec1786 = ie3b7e7; default : mec1786 = kd4bf9b; endcase\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if(!rst_n) sudbf39 <= 1'b0; else if (rv389d3 == ym3bfe4 || rv389d3 == qgff903 || rv389d3 == je2063b || rv389d3 == mt18edf || rv389d3 == fae40c7 || (rv389d3 == lq697f3 && ym343d5)) sudbf39 <= 1'b1; else if (rv389d3 == thf373b || rv389d3 == bn9b9df || rv389d3 == aldceff || rv389d3 == ie3b7e7 || rv389d3 == hbc76fc) sudbf39 <= xwe4d0f; else sudbf39 <= 1'b0;\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if(!rst_n) mt8f2f9 <= 1'b0; else if (rv389d3 == nedff20) mt8f2f9 <= 1'b1; else if (rv389d3 == thf373b || rv389d3 == bn9b9df || rv389d3 == aldceff || rv389d3 == ym3bfe4 || (rv389d3 == lq697f3 && ym343d5 == 1'b1) || rv389d3 == qgff903 || rv389d3 == je2063b || rv389d3 == rv31db || rv389d3 == mt18edf) mt8f2f9 <= mt8f2f9; else mt8f2f9 <= 1'b0;\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if(!rst_n) ou31e5f <= 8'b00000000; else if (rv389d3 == nedff20) ou31e5f <= 8'b01010101; else if (rv389d3 == hbc76fc || rv389d3 == fae40c7) ou31e5f <= 8'b00001111; else if (rv389d3 == ie3b7e7) ou31e5f <= 8'b00011111; else if (rv389d3 == ym3bfe4) ou31e5f <= 8'b00001110; else if (rv389d3 == rv31db) ou31e5f <= nga8863; else ou31e5f <= 8'b00000000;\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if(!rst_n) gbc97e4 <= 1'b0; else if (rv389d3 == ofe77fc && zm8611e && aldc18a) gbc97e4 <= 1'b1; else if (rv389d3 == dzfc818 || (rv389d3 == lq697f3 && ym343d5) || rv389d3 == kd4bf9b || rv389d3 == jp5fcdc || rv389d3 == lqfe6e7 || rv389d3 == ofe77fc) gbc97e4 <= 1'b0; else gbc97e4 <= ym343d5;\r
-end always @(posedge vxa5777 or negedge rst_n) begin if(!rst_n) begin kqf5edc <= 16'h0000; end else if(rv389d3 == thf373b) begin kqf5edc[7:0] <= nga8863; kqf5edc[15:8] <= kqf5edc[15:8]; end else if(rv389d3 == bn9b9df) begin kqf5edc[ 7:0] <= kqf5edc[7:0]; kqf5edc[15:8] <= nga8863; end else kqf5edc <= kqf5edc; end\r
- always @(posedge vxa5777 or negedge rst_n) begin if(!rst_n) co9818f <= 1'b0; else if(rv389d3 == bn9b9df) co9818f <= 1'b1; else co9818f <= 1'b0; end always @(posedge vxa5777 or negedge rst_n) begin if(!rst_n) hoc0c79 <= 1'b0; else if(rv389d3 == ofe77fc) hoc0c79 <= 1'b1; else hoc0c79 <= 1'b0; end always @(posedge vxa5777 or negedge rst_n) begin if(!rst_n) lf63cb <= 1'b0; else if((rv389d3 == aldceff && pf50c23) || (rv389d3 == lq697f3 && !zm8611e)) lf63cb <= 1'b1; else lf63cb <= 1'b0; end\r
-assign fadf9c9 = rv9bd57 ? (xwe4d0f & mt8f2f9) : xwe4d0f;\r
-assign by797cd = (kqf55f9 & !uka9420) ? ux2687a : xwe4d0f;\r
-always @(rv389d3)\r
-begin case (rv389d3) lq697f3 : ipe8b9b = "LNK_FAIL"; kd4bf9b : ipe8b9b = "WAIT_K"; jp5fcdc : ipe8b9b = "RX_K"; lqfe6e7 : ipe8b9b = "RX_CB"; thf373b : ipe8b9b = "RX_CC"; bn9b9df : ipe8b9b = "RX_CD"; aldceff : ipe8b9b = "RX_INV"; ofe77fc : ipe8b9b = "IDL_D"; ym3bfe4 : ipe8b9b = "FLS_CARR"; nedff20 : ipe8b9b = "SOP"; qgff903 : ipe8b9b = "ERLY_END"; dzfc818 : ipe8b9b = "TRI_RRI"; fae40c7 : ipe8b9b = "TRR_EXT"; je2063b : ipe8b9b = "RXD_ERR"; rv31db : ipe8b9b = "RX_D"; mt18edf : ipe8b9b = "EEND_EXT"; hbc76fc : ipe8b9b = "PKT_BRRS"; ie3b7e7 : ipe8b9b = "EXT_ERR"; default : ipe8b9b = " ERROR "; endcase\r
-end\r
-always@* begin nef1679<=eae03bd[0];lf27c59<=eae03bd[1];pu86d04<=eae03bd[2];tj9b9c3<=eae03bd[3];ofdce1f<={rx_data>>1,eae03bd[4]};wje70fc<=eae03bd[5];nt387e4<=eae03bd[6];zkcae1a<=eae03bd[7];gq1f934<=eae03bd[8];pffc9a1<={bl7b70e>>1,eae03bd[9]};xwe4d0f<=eae03bd[10];ux2687a<=eae03bd[11];ym343d5<=eae03bd[12];kfa1ea8<={mg249fa>>1,eae03bd[13]};swf544<={ie24fd0>>1,eae03bd[14]};yx7aa21<={fp27e80>>1,eae03bd[15]};ned510c<={je3f407>>1,eae03bd[16]};nga8863<={ayfa03b>>1,eae03bd[17]};wj4431a<=eae03bd[18];uk218d4<=eae03bd[19];xlc6a0<=eae03bd[20];ho63506<=eae03bd[21];uk1a832<=eae03bd[22];uid4191<=eae03bd[23];tja0c89<=eae03bd[24];ph644e<=eae03bd[25];xl32277<=eae03bd[26];hd913bf<=eae03bd[27];ri89dff<=eae03bd[28];qt4effb<=eae03bd[29];cm77fdc<=eae03bd[30];rvbfee0<=eae03bd[31];icff706<=eae03bd[32];tufb831<=eae03bd[33];aldc18a<=eae03bd[34];qge0c55<=eae03bd[35];rv62a8<=eae03bd[36];ks31547<=eae03bd[37];cb8aa38<=eae03bd[38];xj551c4<=eae03bd[39];pua8e27<=eae03bd[40];lq4713a<=eae03bd[41];rv389d3<={lf382f0>>1,eae03bd[42]};mec4e9f<={mec1786>>1,eae03bd[43]};zz274f9<=eae03bd[44];je3a7ce<=eae03bd[45];czd3e73<=eae03bd[46];ep9f39d<=eae03bd[47];vvf9cec<=eae03bd[48];suce767<=eae03bd[49];xw73b39<=eae03bd[50];aa9d9ca<=eae03bd[51];pfece50<=eae03bd[52];kq67286<=eae03bd[53];ux39430<=eae03bd[54];hoca184<=eae03bd[55];pf50c23<=eae03bd[56];zm8611e<=eae03bd[57];xy308f3<={ip5e6ab>>1,eae03bd[58]};hd8479b<={blf355c>>1,eae03bd[59]};hbc76a1<=eae03bd[60];ie3b50f<=eae03bd[61];vvf37aa<=eae03bd[62];rv9bd57<=eae03bd[63];wwdeabf<=eae03bd[64];kqf55f9<=eae03bd[65];gof5284<=eae03bd[66];uka9420<=eae03bd[67];rvbf23b<={ipe8b9b>>1,eae03bd[68]};end\r
-always@* begin shdc077[2047]<=sgmii_mode;shdc077[2046]<=gbe_mode;shdc077[2044]<=zzbf298;shdc077[2041]<=hb5a0eb;shdc077[2040]<=rx_data[0];shdc077[2035]<=rgd075e;shdc077[2033]<=rx_kcntl;shdc077[2024]<=ie3b2ed;shdc077[2022]<=tw83af3;shdc077[2018]<=su531f3;shdc077[2001]<=uvd9769;shdc077[1997]<=yz1d79a;shdc077[1988]<=lfa55f5;shdc077[1954]<=uicbb4d;shdc077[1946]<=byebcd5;shdc077[1929]<=rx_even;shdc077[1874]<=kd51cbd;shdc077[1860]<=jc5da68;shdc077[1851]<=ipe8b9b[1];shdc077[1845]<=ip5e6ab[0];shdc077[1811]<=bl7b70e[0];shdc077[1789]<=hod01d9;shdc077[1721]<=kq5cf5d;shdc077[1700]<=nt8e5ec;shdc077[1673]<=iped342;shdc077[1643]<=blf355c[0];shdc077[1574]<=sudbf39;shdc077[1530]<=sj80ecb;shdc077[1486]<=vif4422;shdc077[1395]<=qte7ae8;shdc077[1353]<=ic72f67;shdc077[1317]<=pubd9c1;shdc077[1311]<=tw860a1;shdc077[1299]<=lq69a15;shdc077[1258]<=lq5228e;shdc077[1247]<=fp27e80[0];shdc077[1239]<=vv71dc4;shdc077[1187]<=twbc30;shdc077[1172]<=me6705e;shdc077[1151]<=gq8285a;shdc077[1102]<=su68552;shdc077[1101]<=fadf9c9;shdc077[1023]<=mr_main_reset;shdc077[1020]<=twb41d;shdc077[1012]<=ux765d;shdc077[937]<=an8a397;shdc077[925]<=lsa2112;shdc077[894]<=ayfa03b[0];shdc077[860]<=irab9eb;shdc077[743]<=vx3d745;shdc077[658]<=ks97b38;shdc077[655]<=cmf0c14;shdc077[629]<=phaa451;shdc077[623]<=ie24fd0[0];shdc077[593]<=mec1786[0];shdc077[586]<=zxece0b;shdc077[575]<=ba3050b;shdc077[551]<=fa4d0aa;shdc077[510]<=qva1683;shdc077[468]<=vx91472;shdc077[447]<=je3f407[0];shdc077[430]<=rv8ee27;shdc077[327]<=cz5e182;shdc077[314]<=aa1548a;shdc077[311]<=mg249fa[0];shdc077[296]<=lf382f0[0];shdc077[255]<=xy142d0;shdc077[157]<=ne42a91;shdc077[155]<=gbc97e4;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module ecaab (\r
- vxa5777 ,\r
- rst_n ,\r
- mr_main_reset ,\r
- signal_detect ,\r
- rx_data ,\r
- rx_kcntl ,\r
- su531f3 ,\r
- lfa55f5 ,\r
- rx_even\r
- );\r
-input vxa5777 ;\r
-input rst_n ;\r
-input mr_main_reset ;\r
-input signal_detect ;\r
-input [7:0] rx_data ;\r
-input rx_kcntl ;\r
-input su531f3 ;\r
-output lfa55f5 ;\r
-output rx_even ;\r
-localparam mg3b2d4 = 4'b0000 , ald96a1 = 4'b0001 , qgcb50d = 4'b0010 , jp5a869 = 4'b0011 , kqd434f = 4'b0100 , qva1a79 = 4'b0101 , qvd3cc = 4'b0110 , dm69e64 = 4'b0111 , vv4f322 = 4'b1000 , vi79917 = 4'b1001 , uvcc8bb = 4'b1010 , pf645dd = 4'b1011 , nt22eef = 4'b1100 ;\r
-reg lfa55f5 ;\r
-reg rx_even ;\r
-reg [3:0] ldddfe4 ;\r
-reg [3:0] wweff26 ;\r
-reg [1:0] uv7f931 ;\r
-reg jpfc98c ;\r
-reg bye4c67 ;\r
-reg vv71dc4 ;\r
-reg rv8ee27 ;\r
-reg ba8cea1 ;\r
-reg qg6750b ;\r
-reg pu3a858 ;\r
-wire sud42c2 ;\r
-reg cba1611 ;\r
-reg lsb08d ;\r
-reg tu5846b ;\r
-reg [(20*8):1] pfc235b;\r
-reg nef1679;\r
-reg uk8d6fa;\r
-reg [7 : 0] ofdce1f;\r
-reg wje70fc;\r
-reg nt387e4;\r
-reg [3 : 0] mefa1aa;\r
-reg [3 : 0] zkd0d51;\r
-reg [1 : 0] ba86a8a;\r
-reg je35452;\r
-reg vxaa292;\r
-reg hbc76a1;\r
-reg ie3b50f;\r
-reg jc525ad;\r
-reg co92d6a;\r
-reg do96b51;\r
-reg ntb5a8b;\r
-reg doad45f;\r
-reg yx6a2fb;\r
-reg gb517dc;\r
-reg [(20 * 8) : 1] lf8bee5;\r
-reg [2047:0] shdc077;\r
-wire [19:0] eae03bd;\r
-localparam ba1de9 = 20,ngef4b = 32'hfdffd48b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-assign sud42c2 = ( wje70fc & (ofdce1f[5:0] == 6'b111100) & ((ofdce1f[7:6] == 2'b00) | (ofdce1f[7:6] == 2'b10) | (ofdce1f[7:6] == 2'b11)));\r
-always @(posedge vxa5777 or negedge rst_n)\r
-begin if(!rst_n) begin vv71dc4 <= 1'b1; rv8ee27 <= 1'b1; end else begin vv71dc4 <= nef1679; rv8ee27 <= hbc76a1; end\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if (!rst_n) begin tu5846b <= 1'b0 ; cba1611 <= 1'b0 ; lsb08d <= 1'b0 ; end else begin tu5846b <= ntb5a8b & ~nt387e4; cba1611 <= (nt387e4 | (ntb5a8b & do96b51)); lsb08d <= ~wje70fc & ~doad45f ; end\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if (!rst_n) begin jpfc98c <= 1'b0 ; bye4c67 <= 1'b0 ; ba8cea1 <= 1'b0 ; qg6750b <= 1'b0 ; pu3a858 <= 1'b0 ; end else begin jpfc98c <= uk8d6fa ; bye4c67 <= je35452 ; ba8cea1 <= vxaa292 ; qg6750b <= (vxaa292 ^ jc525ad) ; pu3a858 <= rx_even ; end\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if(!rst_n) ldddfe4 <= mg3b2d4 ; else if (ie3b50f || co92d6a) ldddfe4 <= mg3b2d4 ; else ldddfe4 <= zkd0d51 ;\r
-end\r
-always @(mefa1aa or gb517dc or yx6a2fb or ba86a8a or rx_even or doad45f) begin case (mefa1aa) mg3b2d4 : if (gb517dc && jc525ad) wweff26 = ald96a1 ; else wweff26 = mg3b2d4 ; ald96a1 : if (yx6a2fb) wweff26 = qgcb50d ; else wweff26 = mg3b2d4 ; qgcb50d : if (!rx_even && gb517dc) wweff26 = jp5a869 ; else if (doad45f) wweff26 = mg3b2d4 ; else wweff26 = qgcb50d ; jp5a869 : if (yx6a2fb) wweff26 = kqd434f ; else wweff26 = mg3b2d4 ; kqd434f : if (!rx_even && gb517dc) wweff26 = qva1a79 ; else if (doad45f) wweff26 = mg3b2d4 ; else wweff26 = kqd434f ; qva1a79: if (yx6a2fb) wweff26 = qvd3cc; else wweff26 = mg3b2d4; qvd3cc: if (doad45f) wweff26 = dm69e64; else wweff26 = qvd3cc; dm69e64: if (doad45f) wweff26 = vi79917; else wweff26 = vv4f322; vv4f322: if (doad45f) wweff26 = vi79917; else if (ba86a8a == 2'b11) wweff26 = qvd3cc; else wweff26 = vv4f322; vi79917: if (doad45f) wweff26 = pf645dd; else wweff26 = uvcc8bb; uvcc8bb: if (doad45f) wweff26 = pf645dd; else if (ba86a8a == 2'b11) wweff26 = dm69e64; else wweff26 = uvcc8bb; pf645dd: if (doad45f) wweff26 = mg3b2d4; else wweff26 = nt22eef; nt22eef: if (doad45f) wweff26 = mg3b2d4; else if (ba86a8a == 2'b11) wweff26 = vi79917; else wweff26 = nt22eef; default: wweff26 = mg3b2d4; endcase\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if (!rst_n) uv7f931 <= 2'b00; else if ((mefa1aa == vv4f322) || (mefa1aa == uvcc8bb) || (mefa1aa == nt22eef)) uv7f931 <= ba86a8a + 1'b1; else uv7f931 <= 2'b00;\r
-end\r
-always @(posedge vxa5777 or negedge rst_n) begin if (!rst_n) lfa55f5 <= 1'b0; else if (mefa1aa == mg3b2d4) lfa55f5 <= 1'b0; else if (mefa1aa == qvd3cc) lfa55f5 <= 1'b1; else lfa55f5 <= lfa55f5 ;\r
-end\r
-always @(mefa1aa or do96b51) begin case (mefa1aa) ald96a1, jp5a869, qva1a79 : rx_even = 1'b1 ; mg3b2d4, qgcb50d, kqd434f, qvd3cc, dm69e64, vi79917, pf645dd, vv4f322, uvcc8bb, nt22eef : rx_even = ~do96b51 ; default : rx_even = 1'b0; endcase\r
-end\r
-always @(mefa1aa)\r
-begin case (mefa1aa) mg3b2d4 : pfc235b = "LOS"; ald96a1 : pfc235b = "COM_DET1"; qgcb50d : pfc235b = "AQR_SYNC1"; jp5a869 : pfc235b = "COM_DET2"; kqd434f : pfc235b = "AQR_SYNC2"; qva1a79 : pfc235b = "COM_DET3"; qvd3cc : pfc235b = "SYNC_AQRD1"; dm69e64 : pfc235b = "SYNC_AQRD2"; vv4f322 : pfc235b = "SYNC_AQRD2A"; vi79917 : pfc235b = "SYNC_AQRD3"; uvcc8bb : pfc235b = "SYNC_AQRD3A"; pf645dd : pfc235b = "SYNC_AQRD4"; nt22eef : pfc235b = "SYNC_AQRD4A"; default : pfc235b = " ERROR "; endcase\r
-end\r
-always@* begin nef1679<=eae03bd[0];uk8d6fa<=eae03bd[1];ofdce1f<={rx_data>>1,eae03bd[2]};wje70fc<=eae03bd[3];nt387e4<=eae03bd[4];mefa1aa<={ldddfe4>>1,eae03bd[5]};zkd0d51<={wweff26>>1,eae03bd[6]};ba86a8a<={uv7f931>>1,eae03bd[7]};je35452<=eae03bd[8];vxaa292<=eae03bd[9];hbc76a1<=eae03bd[10];ie3b50f<=eae03bd[11];jc525ad<=eae03bd[12];co92d6a<=eae03bd[13];do96b51<=eae03bd[14];ntb5a8b<=eae03bd[15];doad45f<=eae03bd[16];yx6a2fb<=eae03bd[17];gb517dc<=eae03bd[18];lf8bee5<={pfc235b>>1,eae03bd[19]};end\r
-always@* begin shdc077[2047]<=signal_detect;shdc077[2046]<=rx_data[0];shdc077[2044]<=rx_kcntl;shdc077[2040]<=su531f3;shdc077[2032]<=ldddfe4[0];shdc077[2017]<=wweff26[0];shdc077[1987]<=uv7f931[0];shdc077[1927]<=jpfc98c;shdc077[1865]<=cba1611;shdc077[1806]<=bye4c67;shdc077[1682]<=lsb08d;shdc077[1565]<=vv71dc4;shdc077[1317]<=tu5846b;shdc077[1082]<=rv8ee27;shdc077[1023]<=mr_main_reset;shdc077[932]<=sud42c2;shdc077[586]<=pfc235b[1];shdc077[466]<=pu3a858;shdc077[233]<=qg6750b;shdc077[116]<=ba8cea1;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module phc858 (\r
- rst_n,\r
- mr_main_reset,\r
- an_link_ok,\r
- tu58fcb,\r
- gbe_mode,\r
- operational_rate,\r
- thf96b3,\r
- ykcb59e,\r
- vv5acf1,\r
- end678f,\r
- oub3c7c,\r
- jr9e3e0,\r
- hof1f06,\r
- ir8f833,\r
- rg7c19c,\r
- ctc_drop_flag,\r
- ctc_add_flag\r
-);\r
-input rst_n;\r
-input mr_main_reset;\r
-input an_link_ok;\r
-input tu58fcb;\r
-input gbe_mode;\r
-input [1:0] operational_rate;\r
-input thf96b3;\r
-input [7:0] ykcb59e;\r
-input vv5acf1;\r
-input end678f;\r
-input oub3c7c;\r
-output [7:0] jr9e3e0;\r
-output hof1f06;\r
-output ir8f833;\r
-output rg7c19c;\r
-output ctc_drop_flag;\r
-output ctc_add_flag;\r
-parameter DYNAMIC_LT_10MBPS = 340;\r
-parameter DYNAMIC_HT_10MBPS = 680;\r
-parameter DYNAMIC_LT_100MBPS = 34;\r
-parameter DYNAMIC_HT_100MBPS = 68;\r
-parameter DYNAMIC_LT_1000MBPS = 16;\r
-parameter DYNAMIC_HT_1000MBPS = 32;\r
-localparam lf91727 = 2'd0, zz8b93f = 2'd1, ww5c9fe = 2'd2, hoe4ff0 = 2'd3;\r
-reg[1:0] xl27f82;\r
-localparam xy3fc17 = 3'd0, fafe0ba = 3'd1, uif05d3 = 3'd2, co82e98 = 3'd3, sj174c0 = 3'd4, zzba604 = 3'd5;\r
-reg [2:0] ald3027;\r
-reg [7:0] ie9813c;\r
-reg dmc09e1;\r
-reg do4f0b ;\r
-reg [7:0] fp2785b;\r
-reg kf3c2df;\r
-reg fae16fc ;\r
-reg [7:0] jeb7e3;\r
-reg en5bf1b;\r
-reg xwdf8dd ;\r
-reg vvfc6eb;\r
-reg rte375e;\r
-reg xy1baf6;\r
-reg vvdd7b3;\r
-reg dmebd9f;\r
-reg yx5ecfb;\r
-reg dzf67dd;\r
-reg ip6f1c7;\r
-reg [7:0] jr9e3e0;\r
-reg hof1f06;\r
-reg ir8f833;\r
-wire [7:0] su59bc7;\r
-wire ui788b0;\r
-wire ym3166f;\r
-wire fp22c08;\r
-wire lf16047;\r
-wire vxb023e;\r
-reg nt811f6;\r
-wire dzcde38;\r
-reg zk47db5;\r
-reg sw3edaa;\r
-reg thf6d50;\r
-reg ukb6a86;\r
-reg fpb5430;\r
-reg phaa186;\r
-reg nr50c36;\r
-wire rg7c19c;\r
-wire [7:0] zm30db3;\r
-reg [1:0] ay4ce05;\r
-reg [1:0] ic67029;\r
-reg [1:0] gqb66d4;\r
-reg [1:0] ymb36a1;\r
-reg ph9b509;\r
-reg dmda84e;\r
-reg osd4273;\r
-reg wla1399;\r
-reg ep29198;\r
-reg qt4e66f;\r
-reg ho7337d;\r
-reg hq99beb;\r
-reg thcdf5a;\r
-reg gb6fad7;\r
-reg ui7d6bd;\r
-reg [9:0] hoeb5e8;\r
-reg [9:0] bl5af42;\r
-reg vif4422;\r
-reg lsa2112;\r
-reg [1:0] qte85fa;\r
-reg [1:0] xw42fd5;\r
-reg ep17eaa;\r
-reg vxbf555;\r
-reg sufaaaf;\r
-reg rgd5578;\r
-reg vxaabc3 ;\r
-reg nr55e1f ;\r
-reg lfaf0fe ;\r
-reg ea787f6 ;\r
-reg kdc3fb0;\r
-reg co1fd84;\r
-reg ctc_drop_flag;\r
-reg jpf610a;\r
-reg zzb0857;\r
-reg ctc_add_flag;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-reg [(22*8):1] co215fe;\r
-reg [(22*8):1] ksaff1;\r
-reg nef1679;\r
-reg tjbfc43;\r
-reg zkfe21e;\r
-reg pu86d04;\r
-reg [1 : 0] qi8879a;\r
-reg [7 : 0] cm43cd0;\r
-reg ri1e680;\r
-reg vvf3402;\r
-reg [1 : 0] qv9a017;\r
-reg [2 : 0] lqd00bc;\r
-reg [7 : 0] yz805e3;\r
-reg mt2f1c;\r
-reg ux178e4;\r
-reg [7 : 0] qibc725;\r
-reg dze3928;\r
-reg vx1c947;\r
-reg [7 : 0] zke4a3e;\r
-reg je251f2;\r
-reg rv28f93;\r
-reg by47c9e;\r
-reg ie3e4f2;\r
-reg uvf2791;\r
-reg hq93c8d;\r
-reg tj9e46b;\r
-reg kdf235e;\r
-reg hd91af5;\r
-reg ecbc0e3;\r
-reg [7 : 0] wl8af03;\r
-reg sh5eb87;\r
-reg yk622bc;\r
-reg kfae1e9;\r
-reg yx70f4c;\r
-reg mg87a65;\r
-reg vx3d328;\r
-reg zk5781c;\r
-reg ay4ca36;\r
-reg kd651b1;\r
-reg zz28d8d;\r
-reg me46c6e;\r
-reg ux36370;\r
-reg irb1b85;\r
-reg ou8dc2d;\r
-reg [7 : 0] th6e169;\r
-reg [1 : 0] wla4cba;\r
-reg [1 : 0] mt265d4;\r
-reg [1 : 0] vx2d3ad;\r
-reg [1 : 0] lq69d6f;\r
-reg gb4eb7a;\r
-reg cz75bd4;\r
-reg twadea5;\r
-reg sh6f52a;\r
-reg ead4986;\r
-reg ead4aa4;\r
-reg rva5520;\r
-reg ba2a907;\r
-reg ip5483b;\r
-reg wla41dc;\r
-reg pu20ee5;\r
-reg [9 : 0] ir772a;\r
-reg [9 : 0] qi3b955;\r
-reg gof5284;\r
-reg uka9420;\r
-reg [1 : 0] ls2aa21;\r
-reg [1 : 0] ld5510b;\r
-reg xya885f;\r
-reg yx442fa;\r
-reg ks217d4;\r
-reg xybea1;\r
-reg jp5f50a;\r
-reg gofa856;\r
-reg ykd42b0;\r
-reg yza1581;\r
-reg ecac0d;\r
-reg kq56068;\r
-reg ntb0340;\r
-reg bn81a06;\r
-reg [(22 * 8) : 1] ohd037;\r
-reg [(22 * 8) : 1] me681bc;\r
-reg [2047:0] shdc077;\r
-wire [77:0] eae03bd;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-localparam ba1de9 = 78,ngef4b = 32'hfdffe44b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin lfaf0fe <= 1'b1; ea787f6 <= 1'b1; end else begin lfaf0fe <= nef1679; ea787f6 <= ykd42b0; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vif4422 <= 1'b0; lsa2112 <= 1'b0; end else begin vif4422 <= pu86d04; lsa2112 <= gof5284; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qte85fa <= 2'b10; xw42fd5 <= 2'b10; end else begin qte85fa <= qi8879a; xw42fd5 <= ls2aa21; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ep17eaa <= 1'b0; vxbf555 <= 1'b0; sufaaaf <= 1'b1; rgd5578 <= 1'b1; end else begin ep17eaa <= tjbfc43; vxbf555 <= xya885f; sufaaaf <= zkfe21e; rgd5578 <= ks217d4; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ay4ce05 <= 2'b10; ic67029 <= 2'b10; ph9b509 <= 1'b1; dmda84e <= 1'b1; osd4273 <= 1'b1; wla1399 <= 1'b1; ep29198 <= 1'b1; end else begin if (uka9420) begin ay4ce05 <= 2'b10; end else if (yx442fa || (!xybea1)) begin ay4ce05 <= ld5510b; end else begin ay4ce05 <= 2'b10; end ic67029 <= wla4cba; ph9b509 <= wla4cba != mt265d4; dmda84e <= gb4eb7a; osd4273 <= cz75bd4; wla1399 <= twadea5; ep29198 <= gb4eb7a | cz75bd4 | twadea5 | sh6f52a; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vxaabc3 <= 1'b1; nr55e1f <= 1'b1; end else begin vxaabc3 <= nef1679; nr55e1f <= jp5f50a; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin gqb66d4 <= 2'b10; ymb36a1 <= 2'b10; end else begin gqb66d4 <= wla4cba; ymb36a1 <= vx2d3ad; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin qt4e66f <= 1'b1; ho7337d <= 1'b1; hq99beb <= 1'b1; end else begin if (gofa856) begin qt4e66f <= 1'b1; ho7337d <= 1'b1; hq99beb <= 1'b1; end else begin qt4e66f <= ead4986; ho7337d <= ead4aa4; hq99beb <= rva5520; end\r
-end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin thcdf5a <= 1'b1; gb6fad7 <= 1'b1; ui7d6bd <= 1'b1; end else begin if (yza1581) begin thcdf5a <= 1'b1; gb6fad7 <= 1'b1; ui7d6bd <= 1'b1; end else begin thcdf5a <= ead4986; gb6fad7 <= ip5483b; ui7d6bd <= wla41dc; end\r
-end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin hoeb5e8 <= 10'd16; end else begin case (mt265d4) 2'd0: begin hoeb5e8 <= DYNAMIC_LT_10MBPS; end 2'd1: begin hoeb5e8 <= DYNAMIC_LT_100MBPS; end 2'd2: begin hoeb5e8 <= DYNAMIC_LT_1000MBPS; end 2'd3: begin hoeb5e8 <= DYNAMIC_LT_1000MBPS; end default: begin hoeb5e8 <= ir772a; end endcase end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin bl5af42 <= 10'd32; end else begin case (lq69d6f) 2'd0: begin bl5af42 <= DYNAMIC_HT_10MBPS; end 2'd1: begin bl5af42 <= DYNAMIC_HT_100MBPS; end 2'd2: begin bl5af42 <= DYNAMIC_HT_1000MBPS; end 2'd3: begin bl5af42 <= DYNAMIC_HT_1000MBPS; end default: begin bl5af42 <= qi3b955; end endcase end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ie9813c <= 8'd0; dmc09e1 <= 1'b0; do4f0b <= 1'b0; fp2785b <= 8'd0; kf3c2df <= 1'b0; fae16fc <= 1'b0; jeb7e3 <= 8'd0; en5bf1b <= 1'b0; xwdf8dd <= 1'b0; end else begin ie9813c <= cm43cd0; dmc09e1 <= ri1e680; do4f0b <= vvf3402; fp2785b <= yz805e3; kf3c2df <= mt2f1c; fae16fc <= ux178e4; jeb7e3 <= qibc725; en5bf1b <= dze3928; xwdf8dd <= vx1c947; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vvfc6eb <= 1'b0; rte375e <= 1'b0; xy1baf6 <= 1'b0; vvdd7b3 <= 1'b0; dmebd9f <= 1'b0; yx5ecfb <= 1'b0; end else begin if ((mt2f1c == 1'b1) && (yz805e3 == 8'hBC)) begin vvfc6eb <= 1'b1; end else begin vvfc6eb <= 1'b0; end\r
- if ((ri1e680 == 1'b0) && (cm43cd0 == 8'hC5)) begin rte375e <= 1'b1; end else begin rte375e <= 1'b0; end if ((ri1e680 == 1'b0) && (cm43cd0 == 8'h50)) begin xy1baf6 <= 1'b1; end else begin xy1baf6 <= 1'b0; end if ((ri1e680 == 1'b0) && (cm43cd0 == 8'h42)) begin vvdd7b3 <= 1'b1; end else begin vvdd7b3 <= 1'b0; end if ((ri1e680 == 1'b0) && (cm43cd0 == 8'hB5)) begin dmebd9f <= 1'b1; end else begin dmebd9f <= 1'b0; end if (by47c9e && (hq93c8d || tj9e46b)) begin yx5ecfb <= 1'b1; end else begin yx5ecfb <= 1'b0; end end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin xl27f82 <= lf91727; dzf67dd <= 1'b0; kdc3fb0 <= 1'b0; end else begin if (ba2a907) begin xl27f82 <= lf91727; dzf67dd <= 1'b0; kdc3fb0 <= 1'b0; end else begin kdc3fb0 <= 1'b0; case (qv9a017) lf91727: begin if (yx70f4c) begin if (by47c9e && (uvf2791 || hq93c8d || tj9e46b)) begin dzf67dd <= 1'b0; xl27f82 <= zz8b93f; kdc3fb0 <= 1'b1; end end else begin dzf67dd <= 1'b1; xl27f82 <= lf91727; end end zz8b93f: begin dzf67dd <= 1'b0; kdc3fb0 <= 1'b1; if (kdf235e) begin xl27f82 <= ww5c9fe; end else begin xl27f82 <= lf91727; end end ww5c9fe: begin dzf67dd <= 1'b0; kdc3fb0 <= 1'b1; xl27f82 <= hoe4ff0; end hoe4ff0: begin dzf67dd <= 1'b0; kdc3fb0 <= 1'b1; xl27f82 <= lf91727; end\r
- default: begin xl27f82 <= lf91727; end endcase end end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin co1fd84 <= 1'b0; ctc_drop_flag <= 1'b0; end else begin co1fd84 <= ecac0d; ctc_drop_flag <= ecac0d | kq56068; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ald3027 <= xy3fc17; jr9e3e0 <= 8'hBC; hof1f06 <= 1'b1; ir8f833 <= 1'b0; ip6f1c7 <= 1'b0; jpf610a <= 1'b1; end else begin if (pu20ee5) begin ald3027 <= xy3fc17; jr9e3e0 <= 8'hBC; hof1f06 <= 1'b1; ir8f833 <= 1'b0; ip6f1c7 <= 1'b0; jpf610a <= 1'b1; end else begin jr9e3e0 <= wl8af03; hof1f06 <= sh5eb87; ir8f833 <= yk622bc; ip6f1c7 <= 1'b0; jpf610a <= 1'b0; case (lqd00bc) xy3fc17: begin hof1f06 <= 1'b1; ir8f833 <= 1'b0; jr9e3e0 <= 8'hBC; jpf610a <= 1'b1; if (kfae1e9) begin ald3027 <= zzba604; end else begin ip6f1c7 <= 1'b1; ald3027 <= fafe0ba; end end fafe0ba: begin hof1f06 <= 1'b0; ir8f833 <= 1'b0; jr9e3e0 <= 8'h50; jpf610a <= 1'b1; ip6f1c7 <= 1'b1; ald3027 <= sj174c0; end uif05d3: begin hof1f06 <= 1'b1; ir8f833 <= 1'b0; jr9e3e0 <= 8'hBC; jpf610a <= 1'b1; if (kfae1e9) begin ald3027 <= zzba604; end else begin ip6f1c7 <= 1'b1; ald3027 <= co82e98; end end\r
- co82e98: begin ip6f1c7 <= 1'b1; ald3027 <= sj174c0; end\r
- sj174c0: begin if (kfae1e9 && sh5eb87 && (wl8af03 == 8'hBC)) begin hof1f06 <= 1'b1; ir8f833 <= 1'b0; jr9e3e0 <= 8'hBC; jpf610a <= 1'b1; ald3027 <= zzba604; end else begin ip6f1c7 <= 1'b1; ald3027 <= sj174c0; end end zzba604: begin hof1f06 <= 1'b0; ir8f833 <= 1'b0; jr9e3e0 <= 8'h50; jpf610a <= 1'b1; ald3027 <= uif05d3; end default: begin ald3027 <= xy3fc17; end endcase end end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin zzb0857 <= 1'b1; ctc_add_flag <= 1'b1; end else begin zzb0857 <= ntb0340; ctc_add_flag <= ntb0340 | bn81a06; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin sw3edaa <= 1'd0; thf6d50 <= 1'd0; ukb6a86 <= 1'd0; nt811f6 <= 1'd0; end else begin if (ba2a907) begin sw3edaa <= 1'd0; thf6d50 <= 1'd0; ukb6a86 <= 1'd0; nt811f6 <= 1'd0; end else begin nt811f6 <= mg87a65; if (vx3d328 && hd91af5) begin sw3edaa <= 1'd1; end else begin sw3edaa <= 1'd0; end thf6d50 <= kd651b1; ukb6a86 <= kd651b1 | zz28d8d; end end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin fpb5430 <= 1'd0; phaa186 <= 1'd0; nr50c36 <= 1'd0; zk47db5 <= 1'd1; end else begin if (pu20ee5) begin fpb5430 <= 1'd0; phaa186 <= 1'd0; nr50c36 <= 1'd0; zk47db5 <= 1'd1; end else begin zk47db5 <= zk5781c; if (ay4ca36 && ecbc0e3) begin fpb5430 <= 1'd1; end else begin fpb5430 <= 1'd0; end phaa186 <= ux36370; nr50c36 <= ux36370 | irb1b85; end end\r
-end\r
-assign rg7c19c = me46c6e | ou8dc2d;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- vi7cf1f epa4aa7 ( .xjdd9c2(ba2a907), .an3c7dd(thf96b3), .ie1f767(hd91af5), .tj385b0(qi3b955), .uve78fb({8'd0, rv28f93, je251f2, zke4a3e}),\r
- .rtece16(pu20ee5), .fne3eec(oub3c7c), .zkfbb38(ecbc0e3), .ay670b6(ir772a), .blc2d86({zm30db3, ym3166f, ui788b0, su59bc7}),\r
- .lf16c36(dzcde38), .wyb61b7(vxb023e), .zzb0db9(fp22c08), .vk86dcf(lf16047) );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- doad889 epa4aa7 ( .xjdd9c2(ba2a907), .an3c7dd(thf96b3), .ie1f767(hd91af5), .tj385b0(qi3b955), .uve78fb({8'd0, rv28f93, je251f2, zke4a3e}),\r
- .rtece16(pu20ee5), .fne3eec(oub3c7c), .zkfbb38(ecbc0e3), .ay670b6(ir772a), .blc2d86({zm30db3, ym3166f, ui788b0, su59bc7}),\r
- .lf16c36(dzcde38), .wyb61b7(vxb023e), .zzb0db9(fp22c08), .vk86dcf(lf16047) );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- do93e46 epa4aa7 ( .xjdd9c2(ba2a907), .an3c7dd(thf96b3), .ie1f767(hd91af5), .tj385b0(qi3b955), .uve78fb({8'd0, rv28f93, je251f2, zke4a3e}),\r
- .rtece16(pu20ee5), .fne3eec(oub3c7c), .zkfbb38(ecbc0e3), .ay670b6(ir772a), .blc2d86({zm30db3, ym3166f, ui788b0, su59bc7}),\r
- .lf16c36(dzcde38), .wyb61b7(vxb023e), .zzb0db9(fp22c08), .vk86dcf(lf16047) );\r
-`endif\r
-always @(qv9a017) begin case (qv9a017) lf91727 : co215fe = "SEEK_IDLE_START"; zz8b93f : co215fe = "DISABLE_WRITES"; ww5c9fe : co215fe = "DISABLE_W3"; hoe4ff0 : co215fe = "DISABLE_W4"; default : co215fe = "***ERROR***"; endcase\r
-end\r
-always @(lqd00bc) begin case (lqd00bc) xy3fc17 : ksaff1 = "SEEK_BEGIN_THRESH"; fafe0ba : ksaff1 = "DELAY_BEGIN"; uif05d3 : ksaff1 = "SEEK_START_THRESH"; co82e98 : ksaff1 = "DELAY"; sj174c0 : ksaff1 = "SEEK_STOP_THRESH"; zzba604 : ksaff1 = "INSERT_IDLE"; default : ksaff1 = "***ERROR***"; endcase\r
-end\r
-always@* begin nef1679<=eae03bd[0];tjbfc43<=eae03bd[1];zkfe21e<=eae03bd[2];pu86d04<=eae03bd[3];qi8879a<={operational_rate>>1,eae03bd[4]};cm43cd0<={ykcb59e>>1,eae03bd[5]};ri1e680<=eae03bd[6];vvf3402<=eae03bd[7];qv9a017<={xl27f82>>1,eae03bd[8]};lqd00bc<={ald3027>>1,eae03bd[9]};yz805e3<={ie9813c>>1,eae03bd[10]};mt2f1c<=eae03bd[11];ux178e4<=eae03bd[12];qibc725<={fp2785b>>1,eae03bd[13]};dze3928<=eae03bd[14];vx1c947<=eae03bd[15];zke4a3e<={jeb7e3>>1,eae03bd[16]};je251f2<=eae03bd[17];rv28f93<=eae03bd[18];by47c9e<=eae03bd[19];ie3e4f2<=eae03bd[20];uvf2791<=eae03bd[21];hq93c8d<=eae03bd[22];tj9e46b<=eae03bd[23];kdf235e<=eae03bd[24];hd91af5<=eae03bd[25];ecbc0e3<=eae03bd[26];wl8af03<={su59bc7>>1,eae03bd[27]};sh5eb87<=eae03bd[28];yk622bc<=eae03bd[29];kfae1e9<=eae03bd[30];yx70f4c<=eae03bd[31];mg87a65<=eae03bd[32];vx3d328<=eae03bd[33];zk5781c<=eae03bd[34];ay4ca36<=eae03bd[35];kd651b1<=eae03bd[36];zz28d8d<=eae03bd[37];me46c6e<=eae03bd[38];ux36370<=eae03bd[39];irb1b85<=eae03bd[40];ou8dc2d<=eae03bd[41];th6e169<={zm30db3>>1,eae03bd[42]};wla4cba<={ay4ce05>>1,eae03bd[43]};mt265d4<={ic67029>>1,eae03bd[44]};vx2d3ad<={gqb66d4>>1,eae03bd[45]};lq69d6f<={ymb36a1>>1,eae03bd[46]};gb4eb7a<=eae03bd[47];cz75bd4<=eae03bd[48];twadea5<=eae03bd[49];sh6f52a<=eae03bd[50];ead4986<=eae03bd[51];ead4aa4<=eae03bd[52];rva5520<=eae03bd[53];ba2a907<=eae03bd[54];ip5483b<=eae03bd[55];wla41dc<=eae03bd[56];pu20ee5<=eae03bd[57];ir772a<={hoeb5e8>>1,eae03bd[58]};qi3b955<={bl5af42>>1,eae03bd[59]};gof5284<=eae03bd[60];uka9420<=eae03bd[61];ls2aa21<={qte85fa>>1,eae03bd[62]};ld5510b<={xw42fd5>>1,eae03bd[63]};xya885f<=eae03bd[64];yx442fa<=eae03bd[65];ks217d4<=eae03bd[66];xybea1<=eae03bd[67];jp5f50a<=eae03bd[68];gofa856<=eae03bd[69];ykd42b0<=eae03bd[70];yza1581<=eae03bd[71];ecac0d<=eae03bd[72];kq56068<=eae03bd[73];ntb0340<=eae03bd[74];bn81a06<=eae03bd[75];ohd037<={co215fe>>1,eae03bd[76]};me681bc<={ksaff1>>1,eae03bd[77]};end\r
-always@* begin shdc077[2047]<=an_link_ok;shdc077[2046]<=tu58fcb;shdc077[2044]<=gbe_mode;shdc077[2040]<=operational_rate[0];shdc077[2033]<=ykcb59e[0];shdc077[2019]<=vv5acf1;shdc077[1991]<=end678f;shdc077[1934]<=xl27f82[0];shdc077[1929]<=ph9b509;shdc077[1898]<=fae16fc;shdc077[1821]<=ald3027[0];shdc077[1813]<=zzb0857;shdc077[1810]<=dmda84e;shdc077[1749]<=jeb7e3[0];shdc077[1707]<=vvfc6eb;shdc077[1666]<=ui788b0;shdc077[1630]<=nr50c36;shdc077[1617]<=vxbf555;shdc077[1595]<=ie9813c[0];shdc077[1579]<=co215fe[1];shdc077[1572]<=osd4273;shdc077[1506]<=gqb66d4[0];shdc077[1450]<=en5bf1b;shdc077[1440]<=ip6f1c7;shdc077[1428]<=xw42fd5[0];shdc077[1384]<=yx5ecfb;shdc077[1370]<=vvdd7b3;shdc077[1366]<=rte375e;shdc077[1308]<=nr55e1f;shdc077[1284]<=ym3166f;shdc077[1212]<=zm30db3[0];shdc077[1202]<=vif4422;shdc077[1187]<=sufaaaf;shdc077[1174]<=ui7d6bd;shdc077[1170]<=hq99beb;shdc077[1142]<=dmc09e1;shdc077[1137]<=ea787f6;shdc077[1125]<=thf6d50;shdc077[1110]<=ksaff1[1];shdc077[1097]<=wla1399;shdc077[1041]<=lf16047;shdc077[1023]<=mr_main_reset;shdc077[964]<=ymb36a1[0];shdc077[949]<=kf3c2df;shdc077[906]<=jpf610a;shdc077[853]<=xwdf8dd;shdc077[833]<=su59bc7[0];shdc077[815]<=phaa186;shdc077[808]<=ep17eaa;shdc077[753]<=ic67029[0];shdc077[720]<=dzf67dd;shdc077[714]<=qte85fa[0];shdc077[692]<=dmebd9f;shdc077[685]<=xy1baf6;shdc077[654]<=vxaabc3;shdc077[601]<=bl5af42[0];shdc077[587]<=gb6fad7;shdc077[585]<=ho7337d;shdc077[568]<=lfaf0fe;shdc077[562]<=sw3edaa;shdc077[520]<=fp22c08;shdc077[474]<=fp2785b[0];shdc077[453]<=co1fd84;shdc077[407]<=fpb5430;shdc077[376]<=ay4ce05[0];shdc077[357]<=lsa2112;shdc077[327]<=rgd5578;shdc077[300]<=hoeb5e8[0];shdc077[293]<=thcdf5a;shdc077[292]<=qt4e66f;shdc077[281]<=zk47db5;shdc077[237]<=do4f0b;shdc077[226]<=kdc3fb0;shdc077[203]<=ukb6a86;shdc077[146]<=ep29198;shdc077[140]<=dzcde38;shdc077[70]<=nt811f6;shdc077[35]<=vxb023e;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module vvd70c4 (\r
- rst_n,\r
- mr_main_reset,\r
- thf96b3,\r
- ykcb59e,\r
- vv5acf1,\r
- end678f,\r
- oub3c7c,\r
- jr9e3e0,\r
- hof1f06,\r
- ir8f833,\r
- rg7c19c,\r
- ctc_drop_flag,\r
- ctc_add_flag\r
-);\r
-input rst_n;\r
-input mr_main_reset;\r
-input thf96b3;\r
-input [7:0] ykcb59e;\r
-input vv5acf1;\r
-input end678f;\r
-input oub3c7c;\r
-output [7:0] jr9e3e0;\r
-output hof1f06;\r
-output ir8f833;\r
-output rg7c19c;\r
-output ctc_drop_flag;\r
-output ctc_add_flag;\r
-parameter STATIC_HI_THRESH = 32;\r
-parameter STATIC_LO_THRESH = 16;\r
-localparam lf91727 = 2'd0, zz8b93f = 2'd1, ww5c9fe = 2'd2, hoe4ff0 = 2'd3;\r
-reg[1:0] xl27f82;\r
-localparam xy3fc17 = 3'd0, fafe0ba = 3'd1, uif05d3 = 3'd2, co82e98 = 3'd3, sj174c0 = 3'd4, zzba604 = 3'd5;\r
-reg [2:0] ald3027;\r
-reg [7:0] ie9813c;\r
-reg dmc09e1;\r
-reg do4f0b ;\r
-reg [7:0] fp2785b;\r
-reg kf3c2df;\r
-reg fae16fc ;\r
-reg [7:0] jeb7e3;\r
-reg en5bf1b;\r
-reg xwdf8dd ;\r
-reg vvfc6eb;\r
-reg rte375e;\r
-reg xy1baf6;\r
-reg vvdd7b3;\r
-reg dmebd9f;\r
-reg yx5ecfb;\r
-reg dzf67dd;\r
-reg ip6f1c7;\r
-reg [7:0] jr9e3e0;\r
-reg hof1f06;\r
-reg ir8f833;\r
-wire [7:0] su59bc7;\r
-wire ui788b0;\r
-wire ym3166f;\r
-wire fp22c08;\r
-wire lf16047;\r
-wire vxb023e;\r
-reg nt811f6;\r
-wire dzcde38;\r
-reg zk47db5;\r
-reg sw3edaa;\r
-reg thf6d50;\r
-reg ukb6a86;\r
-reg fpb5430;\r
-reg phaa186;\r
-reg nr50c36;\r
-wire rg7c19c;\r
-wire [7:0] zm30db3;\r
-reg vxaabc3 ;\r
-reg nr55e1f ;\r
-reg lfaf0fe ;\r
-reg ea787f6 ;\r
-reg kdc3fb0;\r
-reg co1fd84;\r
-reg ctc_drop_flag;\r
-reg jpf610a;\r
-reg zzb0857;\r
-reg ctc_add_flag;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-reg [(22*8):1] co215fe;\r
-reg [(22*8):1] ksaff1;\r
-reg nef1679;\r
-reg [7 : 0] cm43cd0;\r
-reg ri1e680;\r
-reg vvf3402;\r
-reg [1 : 0] qv9a017;\r
-reg [2 : 0] lqd00bc;\r
-reg [7 : 0] yz805e3;\r
-reg mt2f1c;\r
-reg ux178e4;\r
-reg [7 : 0] qibc725;\r
-reg dze3928;\r
-reg vx1c947;\r
-reg [7 : 0] zke4a3e;\r
-reg je251f2;\r
-reg rv28f93;\r
-reg by47c9e;\r
-reg ie3e4f2;\r
-reg uvf2791;\r
-reg hq93c8d;\r
-reg tj9e46b;\r
-reg kdf235e;\r
-reg hd91af5;\r
-reg ecbc0e3;\r
-reg [7 : 0] wl8af03;\r
-reg sh5eb87;\r
-reg yk622bc;\r
-reg kfae1e9;\r
-reg yx70f4c;\r
-reg mg87a65;\r
-reg vx3d328;\r
-reg zk5781c;\r
-reg ay4ca36;\r
-reg kd651b1;\r
-reg zz28d8d;\r
-reg me46c6e;\r
-reg ux36370;\r
-reg irb1b85;\r
-reg ou8dc2d;\r
-reg [7 : 0] th6e169;\r
-reg jp5f50a;\r
-reg gofa856;\r
-reg ykd42b0;\r
-reg yza1581;\r
-reg ecac0d;\r
-reg kq56068;\r
-reg ntb0340;\r
-reg bn81a06;\r
-reg [(22 * 8) : 1] ohd037;\r
-reg [(22 * 8) : 1] me681bc;\r
-reg [2047:0] shdc077;\r
-wire [48:0] eae03bd;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-localparam ba1de9 = 49,ngef4b = 32'hfdffd14b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vxaabc3 <= 1'b1; nr55e1f <= 1'b1; end else begin vxaabc3 <= nef1679; nr55e1f <= jp5f50a; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin lfaf0fe <= 1'b1; ea787f6 <= 1'b1; end else begin lfaf0fe <= nef1679; ea787f6 <= ykd42b0; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ie9813c <= 8'd0; dmc09e1 <= 1'b0; do4f0b <= 1'b0; fp2785b <= 8'd0; kf3c2df <= 1'b0; fae16fc <= 1'b0; jeb7e3 <= 8'd0; en5bf1b <= 1'b0; xwdf8dd <= 1'b0; end else begin ie9813c <= cm43cd0; dmc09e1 <= ri1e680; do4f0b <= vvf3402; fp2785b <= yz805e3; kf3c2df <= mt2f1c; fae16fc <= ux178e4; jeb7e3 <= qibc725; en5bf1b <= dze3928; xwdf8dd <= vx1c947; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vvfc6eb <= 1'b0; rte375e <= 1'b0; xy1baf6 <= 1'b0; vvdd7b3 <= 1'b0; dmebd9f <= 1'b0; yx5ecfb <= 1'b0; end else begin if ((mt2f1c == 1'b1) && (yz805e3 == 8'hBC)) begin vvfc6eb <= 1'b1; end else begin vvfc6eb <= 1'b0; end\r
- if ((ri1e680 == 1'b0) && (cm43cd0 == 8'hC5)) begin rte375e <= 1'b1; end else begin rte375e <= 1'b0; end if ((ri1e680 == 1'b0) && (cm43cd0 == 8'h50)) begin xy1baf6 <= 1'b1; end else begin xy1baf6 <= 1'b0; end if ((ri1e680 == 1'b0) && (cm43cd0 == 8'h42)) begin vvdd7b3 <= 1'b1; end else begin vvdd7b3 <= 1'b0; end if ((ri1e680 == 1'b0) && (cm43cd0 == 8'hB5)) begin dmebd9f <= 1'b1; end else begin dmebd9f <= 1'b0; end if (by47c9e && (hq93c8d || tj9e46b)) begin yx5ecfb <= 1'b1; end else begin yx5ecfb <= 1'b0; end end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin xl27f82 <= lf91727; dzf67dd <= 1'b0; kdc3fb0 <= 1'b0; end else begin if (gofa856) begin xl27f82 <= lf91727; dzf67dd <= 1'b0; end else begin kdc3fb0 <= 1'b0; case (qv9a017) lf91727: begin if (yx70f4c) begin if (by47c9e && (uvf2791 || hq93c8d || tj9e46b)) begin dzf67dd <= 1'b0; xl27f82 <= zz8b93f; kdc3fb0 <= 1'b1; end end else begin dzf67dd <= 1'b1; xl27f82 <= lf91727; end end zz8b93f: begin dzf67dd <= 1'b0; kdc3fb0 <= 1'b1; if (kdf235e) begin xl27f82 <= ww5c9fe; end else begin xl27f82 <= lf91727; end end ww5c9fe: begin dzf67dd <= 1'b0; kdc3fb0 <= 1'b1; xl27f82 <= hoe4ff0; end hoe4ff0: begin dzf67dd <= 1'b0; kdc3fb0 <= 1'b1; xl27f82 <= lf91727; end\r
- default: begin xl27f82 <= lf91727; end endcase end end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin co1fd84 <= 1'b0; ctc_drop_flag <= 1'b0; end else begin co1fd84 <= ecac0d; ctc_drop_flag <= ecac0d | kq56068; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ald3027 <= xy3fc17; jr9e3e0 <= 8'hBC; hof1f06 <= 1'b1; ir8f833 <= 1'b0; ip6f1c7 <= 1'b0; jpf610a <= 1'b1; end else begin if (yza1581) begin ald3027 <= xy3fc17; ip6f1c7 <= 1'b0; end else begin jr9e3e0 <= wl8af03; hof1f06 <= sh5eb87; ir8f833 <= yk622bc; ip6f1c7 <= 1'b0; jpf610a <= 1'b0; case (lqd00bc) xy3fc17: begin hof1f06 <= 1'b1; ir8f833 <= 1'b0; jr9e3e0 <= 8'hBC; jpf610a <= 1'b1; if (kfae1e9) begin ald3027 <= zzba604; end else begin ip6f1c7 <= 1'b1; ald3027 <= fafe0ba; end end fafe0ba: begin hof1f06 <= 1'b0; ir8f833 <= 1'b0; jr9e3e0 <= 8'h50; jpf610a <= 1'b1; ip6f1c7 <= 1'b1; ald3027 <= sj174c0; end uif05d3: begin hof1f06 <= 1'b1; ir8f833 <= 1'b0; jr9e3e0 <= 8'hBC; jpf610a <= 1'b1; if (kfae1e9) begin ald3027 <= zzba604; end else begin ip6f1c7 <= 1'b1; ald3027 <= co82e98; end end\r
- co82e98: begin ip6f1c7 <= 1'b1; ald3027 <= sj174c0; end\r
- sj174c0: begin if (kfae1e9 && sh5eb87 && (wl8af03 == 8'hBC)) begin hof1f06 <= 1'b1; ir8f833 <= 1'b0; jr9e3e0 <= 8'hBC; jpf610a <= 1'b1; ald3027 <= zzba604; end else begin ip6f1c7 <= 1'b1; ald3027 <= sj174c0; end end zzba604: begin hof1f06 <= 1'b0; ir8f833 <= 1'b0; jr9e3e0 <= 8'h50; jpf610a <= 1'b1; ald3027 <= uif05d3; end default: begin ald3027 <= xy3fc17; end endcase end end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin zzb0857 <= 1'b1; ctc_add_flag <= 1'b1; end else begin zzb0857 <= ntb0340; ctc_add_flag <= ntb0340 | bn81a06; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin sw3edaa <= 1'd0; thf6d50 <= 1'd0; ukb6a86 <= 1'd0; nt811f6 <= 1'd0; end else begin nt811f6 <= mg87a65; if (vx3d328 && hd91af5) begin sw3edaa <= 1'd1; end else begin sw3edaa <= 1'd0; end thf6d50 <= kd651b1; ukb6a86 <= kd651b1 | zz28d8d; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin fpb5430 <= 1'd0; phaa186 <= 1'd0; nr50c36 <= 1'd0; zk47db5 <= 1'd1; end else begin zk47db5 <= zk5781c; if (ay4ca36 && ecbc0e3) begin fpb5430 <= 1'd1; end else begin fpb5430 <= 1'd0; end phaa186 <= ux36370; nr50c36 <= ux36370 | irb1b85; end\r
-end\r
-assign rg7c19c = me46c6e | ou8dc2d;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(18), .pmi_data_width_r(18), .pmi_data_depth_w(1024), .pmi_data_depth_r(1024), .pmi_full_flag(1024), .pmi_empty_flag(0), .pmi_almost_full_flag(STATIC_HI_THRESH), .pmi_almost_empty_flag(STATIC_LO_THRESH), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("EBR")) epa4aa7 ( .Reset(nr55e1f), .RPReset(ea787f6), .WrClock(thf96b3), .WrEn(dzf67dd), .Data({8'd0, xwdf8dd, en5bf1b, jeb7e3}),\r
- .RdClock(oub3c7c), .RdEn(ip6f1c7), .Q({zm30db3, ym3166f, ui788b0, su59bc7}),\r
- .Empty(dzcde38), .Full(vxb023e), .AlmostEmpty(fp22c08), .AlmostFull(lf16047) );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(18), .pmi_data_width_r(18), .pmi_data_depth_w(1024), .pmi_data_depth_r(1024), .pmi_full_flag(1024), .pmi_empty_flag(0), .pmi_almost_full_flag(STATIC_HI_THRESH), .pmi_almost_empty_flag(STATIC_LO_THRESH), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("EBR")) epa4aa7 ( .Reset(nr55e1f), .RPReset(ea787f6), .WrClock(thf96b3), .WrEn(dzf67dd), .Data({8'd0, xwdf8dd, en5bf1b, jeb7e3}),\r
- .RdClock(oub3c7c), .RdEn(ip6f1c7), .Q({zm30db3, ym3166f, ui788b0, su59bc7}),\r
- .Empty(dzcde38), .Full(vxb023e), .AlmostEmpty(fp22c08), .AlmostFull(lf16047) );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(18), .pmi_data_width_r(18), .pmi_data_depth_w(1024), .pmi_data_depth_r(1024), .pmi_full_flag(1024), .pmi_empty_flag(0), .pmi_almost_full_flag(STATIC_HI_THRESH), .pmi_almost_empty_flag(STATIC_LO_THRESH), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("EBR")) epa4aa7 ( .Reset(nr55e1f), .RPReset(ea787f6), .WrClock(thf96b3), .WrEn(dzf67dd), .Data({8'd0, xwdf8dd, en5bf1b, jeb7e3}),\r
- .RdClock(oub3c7c), .RdEn(ip6f1c7), .Q({zm30db3, ym3166f, ui788b0, su59bc7}),\r
- .Empty(dzcde38), .Full(vxb023e), .AlmostEmpty(fp22c08), .AlmostFull(lf16047) );\r
-`endif\r
-always @(qv9a017) begin case (qv9a017) lf91727 : co215fe = "SEEK_IDLE_START"; zz8b93f : co215fe = "DISABLE_WRITES"; ww5c9fe : co215fe = "DISABLE_W3"; hoe4ff0 : co215fe = "DISABLE_W4"; default : co215fe = "***ERROR***"; endcase\r
-end\r
-always @(lqd00bc) begin case (lqd00bc) xy3fc17 : ksaff1 = "SEEK_BEGIN_THRESH"; fafe0ba : ksaff1 = "DELAY_BEGIN"; uif05d3 : ksaff1 = "SEEK_START_THRESH"; co82e98 : ksaff1 = "DELAY"; sj174c0 : ksaff1 = "SEEK_STOP_THRESH"; zzba604 : ksaff1 = "INSERT_IDLE"; default : ksaff1 = "***ERROR***"; endcase\r
-end\r
-always@* begin nef1679<=eae03bd[0];cm43cd0<={ykcb59e>>1,eae03bd[1]};ri1e680<=eae03bd[2];vvf3402<=eae03bd[3];qv9a017<={xl27f82>>1,eae03bd[4]};lqd00bc<={ald3027>>1,eae03bd[5]};yz805e3<={ie9813c>>1,eae03bd[6]};mt2f1c<=eae03bd[7];ux178e4<=eae03bd[8];qibc725<={fp2785b>>1,eae03bd[9]};dze3928<=eae03bd[10];vx1c947<=eae03bd[11];zke4a3e<={jeb7e3>>1,eae03bd[12]};je251f2<=eae03bd[13];rv28f93<=eae03bd[14];by47c9e<=eae03bd[15];ie3e4f2<=eae03bd[16];uvf2791<=eae03bd[17];hq93c8d<=eae03bd[18];tj9e46b<=eae03bd[19];kdf235e<=eae03bd[20];hd91af5<=eae03bd[21];ecbc0e3<=eae03bd[22];wl8af03<={su59bc7>>1,eae03bd[23]};sh5eb87<=eae03bd[24];yk622bc<=eae03bd[25];kfae1e9<=eae03bd[26];yx70f4c<=eae03bd[27];mg87a65<=eae03bd[28];vx3d328<=eae03bd[29];zk5781c<=eae03bd[30];ay4ca36<=eae03bd[31];kd651b1<=eae03bd[32];zz28d8d<=eae03bd[33];me46c6e<=eae03bd[34];ux36370<=eae03bd[35];irb1b85<=eae03bd[36];ou8dc2d<=eae03bd[37];th6e169<={zm30db3>>1,eae03bd[38]};jp5f50a<=eae03bd[39];gofa856<=eae03bd[40];ykd42b0<=eae03bd[41];yza1581<=eae03bd[42];ecac0d<=eae03bd[43];kq56068<=eae03bd[44];ntb0340<=eae03bd[45];bn81a06<=eae03bd[46];ohd037<={co215fe>>1,eae03bd[47]};me681bc<={ksaff1>>1,eae03bd[48]};end\r
-always@* begin shdc077[2047]<=ykcb59e[0];shdc077[2046]<=vv5acf1;shdc077[2044]<=end678f;shdc077[2040]<=xl27f82[0];shdc077[2033]<=ald3027[0];shdc077[2019]<=ie9813c[0];shdc077[1994]<=ea787f6;shdc077[1990]<=dmc09e1;shdc077[1981]<=lf16047;shdc077[1965]<=sw3edaa;shdc077[1940]<=kdc3fb0;shdc077[1939]<=vvdd7b3;shdc077[1933]<=do4f0b;shdc077[1914]<=vxb023e;shdc077[1883]<=thf6d50;shdc077[1832]<=co1fd84;shdc077[1831]<=dmebd9f;shdc077[1819]<=fp2785b[0];shdc077[1785]<=vxaabc3;shdc077[1781]<=nt811f6;shdc077[1778]<=vvfc6eb;shdc077[1719]<=ukb6a86;shdc077[1616]<=jpf610a;shdc077[1615]<=yx5ecfb;shdc077[1591]<=kf3c2df;shdc077[1522]<=nr55e1f;shdc077[1515]<=dzcde38;shdc077[1508]<=rte375e;shdc077[1470]<=nr50c36;shdc077[1391]<=fpb5430;shdc077[1271]<=ui788b0;shdc077[1184]<=zzb0857;shdc077[1182]<=dzf67dd;shdc077[1135]<=fae16fc;shdc077[1023]<=mr_main_reset;shdc077[997]<=lfaf0fe;shdc077[990]<=fp22c08;shdc077[982]<=zk47db5;shdc077[969]<=xy1baf6;shdc077[892]<=zm30db3[0];shdc077[889]<=xwdf8dd;shdc077[735]<=phaa186;shdc077[643]<=ksaff1[1];shdc077[635]<=su59bc7[0];shdc077[495]<=ym3166f;shdc077[444]<=en5bf1b;shdc077[321]<=co215fe[1];shdc077[317]<=ip6f1c7;shdc077[222]<=jeb7e3[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module yz29ae8 (\r
- rst_n,\r
- mr_main_reset,\r
- thf96b3,\r
- ykcb59e,\r
- vv5acf1,\r
- end678f,\r
- oub3c7c,\r
- jr9e3e0,\r
- hof1f06,\r
- ir8f833,\r
- rg7c19c\r
-);\r
-input rst_n;\r
-input mr_main_reset;\r
-input thf96b3;\r
-input [7:0] ykcb59e;\r
-input vv5acf1;\r
-input end678f;\r
-input oub3c7c;\r
-output [7:0] jr9e3e0;\r
-output hof1f06;\r
-output ir8f833;\r
-output rg7c19c;\r
-reg [7:0] ie9813c;\r
-reg dmc09e1;\r
-reg do4f0b;\r
-reg dzf67dd;\r
-reg ip6f1c7;\r
-reg [7:0] jr9e3e0;\r
-reg hof1f06;\r
-reg ir8f833;\r
-wire [7:0] su59bc7;\r
-wire ui788b0;\r
-wire ym3166f;\r
-wire fp22c08;\r
-wire lf16047;\r
-wire vxb023e;\r
-wire dzcde38;\r
-reg sw3edaa;\r
-reg thf6d50;\r
-reg ukb6a86;\r
-reg fpb5430;\r
-reg phaa186;\r
-reg nr50c36;\r
-wire rg7c19c;\r
-reg vxaabc3 ;\r
-reg nr55e1f ;\r
-reg lfaf0fe ;\r
-reg ea787f6 ;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-reg nef1679;\r
-reg [7 : 0] cm43cd0;\r
-reg ri1e680;\r
-reg vvf3402;\r
-reg [7 : 0] yz805e3;\r
-reg mt2f1c;\r
-reg ux178e4;\r
-reg hd91af5;\r
-reg ecbc0e3;\r
-reg [7 : 0] wl8af03;\r
-reg sh5eb87;\r
-reg yk622bc;\r
-reg kfae1e9;\r
-reg yx70f4c;\r
-reg mg87a65;\r
-reg zk5781c;\r
-reg kd651b1;\r
-reg zz28d8d;\r
-reg me46c6e;\r
-reg ux36370;\r
-reg irb1b85;\r
-reg ou8dc2d;\r
-reg jp5f50a;\r
-reg gofa856;\r
-reg ykd42b0;\r
-reg yza1581;\r
-reg [2047:0] shdc077;\r
-wire [25:0] eae03bd;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-localparam ba1de9 = 26,ngef4b = 32'hfdffd48b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
-`endif\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vxaabc3 <= 1'b1; nr55e1f <= 1'b1; end else begin vxaabc3 <= nef1679; nr55e1f <= jp5f50a; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin lfaf0fe <= 1'b1; ea787f6 <= 1'b1; end else begin lfaf0fe <= nef1679; ea787f6 <= ykd42b0; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ie9813c <= 8'd0; dmc09e1 <= 1'b0; do4f0b <= 1'b0; end else begin ie9813c <= cm43cd0; dmc09e1 <= ri1e680; do4f0b <= vvf3402; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin jr9e3e0 <= 8'd0; hof1f06 <= 1'b0; ir8f833 <= 1'b0; end else begin jr9e3e0 <= wl8af03; hof1f06 <= sh5eb87; ir8f833 <= yk622bc; end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin dzf67dd <= 1'b0; end else begin if (gofa856) begin dzf67dd <= 1'b0; end else begin if (mg87a65) begin dzf67dd <= 1'b0; end else begin dzf67dd <= 1'b1; end end end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin ip6f1c7 <= 1'b0; end else begin if (yza1581) begin ip6f1c7 <= 1'b0; end else begin if (zk5781c) begin ip6f1c7 <= 1'b0; end else if (kfae1e9) begin ip6f1c7 <= 1'b0; end else begin ip6f1c7 <= 1'b1; end end end\r
-end\r
-always @(posedge thf96b3 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin sw3edaa <= 1'd0; thf6d50 <= 1'd0; ukb6a86 <= 1'd0; end else begin if (mg87a65 && hd91af5) begin sw3edaa <= 1'd1; end else begin sw3edaa <= 1'd0; end thf6d50 <= kd651b1; ukb6a86 <= kd651b1 | zz28d8d; end\r
-end\r
-always @(posedge oub3c7c or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin fpb5430 <= 1'd0; phaa186 <= 1'd0; nr50c36 <= 1'd0; end else begin if (zk5781c && ecbc0e3) begin fpb5430 <= 1'd1; end else begin fpb5430 <= 1'd0; end phaa186 <= ux36370; nr50c36 <= ux36370 | irb1b85; end\r
-end\r
-assign rg7c19c = me46c6e | ou8dc2d;\r
-`ifdef SGMII_FIFO_FAMILY_SC\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(16), .pmi_data_depth_r(16), .pmi_full_flag(16), .pmi_empty_flag(0), .pmi_almost_full_flag(13), .pmi_almost_empty_flag(7), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("SC"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) epa4aa7 ( .Reset(nr55e1f), .RPReset(ea787f6), .WrClock(thf96b3), .WrEn(dzf67dd), .Data({do4f0b, dmc09e1, ie9813c}),\r
- .RdClock(oub3c7c), .RdEn(ip6f1c7), .Q({ym3166f, ui788b0, su59bc7}),\r
- .Empty(dzcde38), .Full(vxb023e), .AlmostEmpty(fp22c08), .AlmostFull(lf16047) );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP2M\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(16), .pmi_data_depth_r(16), .pmi_full_flag(16), .pmi_empty_flag(0), .pmi_almost_full_flag(13), .pmi_almost_empty_flag(7), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP2M"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) epa4aa7 ( .Reset(nr55e1f), .RPReset(ea787f6), .WrClock(thf96b3), .WrEn(dzf67dd), .Data({do4f0b, dmc09e1, ie9813c}),\r
- .RdClock(oub3c7c), .RdEn(ip6f1c7), .Q({ym3166f, ui788b0, su59bc7}),\r
- .Empty(dzcde38), .Full(vxb023e), .AlmostEmpty(fp22c08), .AlmostFull(lf16047) );\r
-`endif\r
-`ifdef SGMII_FIFO_FAMILY_ECP3\r
- pmi_fifo_dc #( .pmi_data_width_w(10), .pmi_data_width_r(10), .pmi_data_depth_w(16), .pmi_data_depth_r(16), .pmi_full_flag(16), .pmi_empty_flag(0), .pmi_almost_full_flag(13), .pmi_almost_empty_flag(7), .pmi_regmode("no_reg"), .pmi_resetmode("async"), .pmi_family("ECP3"), .module_type("pmi_fifo_dc"), .pmi_implementation("LUT")) epa4aa7 ( .Reset(nr55e1f), .RPReset(ea787f6), .WrClock(thf96b3), .WrEn(dzf67dd), .Data({do4f0b, dmc09e1, ie9813c}),\r
- .RdClock(oub3c7c), .RdEn(ip6f1c7), .Q({ym3166f, ui788b0, su59bc7}),\r
- .Empty(dzcde38), .Full(vxb023e), .AlmostEmpty(fp22c08), .AlmostFull(lf16047) );\r
-`endif\r
-always@* begin nef1679<=eae03bd[0];cm43cd0<={ykcb59e>>1,eae03bd[1]};ri1e680<=eae03bd[2];vvf3402<=eae03bd[3];yz805e3<={ie9813c>>1,eae03bd[4]};mt2f1c<=eae03bd[5];ux178e4<=eae03bd[6];hd91af5<=eae03bd[7];ecbc0e3<=eae03bd[8];wl8af03<={su59bc7>>1,eae03bd[9]};sh5eb87<=eae03bd[10];yk622bc<=eae03bd[11];kfae1e9<=eae03bd[12];yx70f4c<=eae03bd[13];mg87a65<=eae03bd[14];zk5781c<=eae03bd[15];kd651b1<=eae03bd[16];zz28d8d<=eae03bd[17];me46c6e<=eae03bd[18];ux36370<=eae03bd[19];irb1b85<=eae03bd[20];ou8dc2d<=eae03bd[21];jp5f50a<=eae03bd[22];gofa856<=eae03bd[23];ykd42b0<=eae03bd[24];yza1581<=eae03bd[25];end\r
-always@* begin shdc077[2047]<=ykcb59e[0];shdc077[2046]<=vv5acf1;shdc077[2044]<=end678f;shdc077[2040]<=ie9813c[0];shdc077[2032]<=dmc09e1;shdc077[2017]<=do4f0b;shdc077[1987]<=dzf67dd;shdc077[1927]<=ip6f1c7;shdc077[1865]<=sw3edaa;shdc077[1806]<=su59bc7[0];shdc077[1682]<=thf6d50;shdc077[1565]<=ui788b0;shdc077[1317]<=ukb6a86;shdc077[1189]<=nr55e1f;shdc077[1172]<=phaa186;shdc077[1082]<=ym3166f;shdc077[1023]<=mr_main_reset;shdc077[932]<=dzcde38;shdc077[663]<=ea787f6;shdc077[594]<=vxaabc3;shdc077[586]<=fpb5430;shdc077[466]<=vxb023e;shdc077[331]<=lfaf0fe;shdc077[297]<=nr50c36;shdc077[233]<=lf16047;shdc077[116]<=fp22c08;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module wl3c3b2 ( gq88e04,\r
- rst_n,\r
- mr_main_reset,\r
- force_unidir,\r
- bl7b70e,\r
- xya24d7,\r
- tx_en,\r
- tx_er,\r
- hdaf6e1,\r
- vvd7515,\r
- xlba8ae,\r
- ead4576\r
- );\r
-parameter qge0963 = 8'hbc, pu4b18 = 8'hfe, vk258c3 = 8'hfb, ep2c61a = 8'hfd, fa630d5 = 8'hf7, gd186aa = 8'hb5, ofc3555 = 8'h42, mg1aaad = 8'hc5, jcd5569 = 8'h50;\r
-parameter hd274a0 = 2'b00, vk3a506 = 2'b01, vvd2833 = 2'b10;\r
-parameter bld2223 = 5'd0, tj9111e = 5'd1, ie888f7 = 5'd2, wj447b9 = 5'd3, wl23dcc = 5'd4, pu1ee65 = 5'd5, ipf732b = 5'd6, oub995d = 5'd7, qtccae9 = 5'd8, ip6574d = 5'd9, gq2ba6d = 5'd10, vi5d369 = 5'd11, fne9b4b = 5'd12, jc4da5e = 5'd13, cm6d2f3 = 5'd14, ps69799 = 5'd15, qt4bccb = 5'd16, en5e65c = 5'd17, vvf32e4 = 5'd18;\r
-input gq88e04;\r
-input rst_n;\r
-input mr_main_reset;\r
-input force_unidir;\r
-input [1:0] bl7b70e;\r
-input [7:0] xya24d7;\r
-input tx_en;\r
-input tx_er;\r
-input [15:0] hdaf6e1;\r
-output [7:0] vvd7515;\r
-output xlba8ae;\r
-output ead4576;\r
-wire gq88e04;\r
-wire rst_n;\r
-wire [1:0] bl7b70e;\r
-wire [7:0] xya24d7;\r
-wire tx_en;\r
-wire tx_er;\r
-wire [15:0] hdaf6e1;\r
-reg [7:0] vvd7515;\r
-reg [7:0] hqb4ea;\r
-reg [7:0] pf5a753;\r
-reg end3a9e;\r
-reg xlba8ae;\r
-reg eaea7a9;\r
-reg ead4576;\r
-reg [7:0] ph9ea41;\r
-reg gof520f;\r
-reg uka9078;\r
-reg [4:0] enfda0c;\r
-reg [4:0] ofed065;\r
-reg [4:0] al7fb41;\r
-reg kq782a9;\r
-reg eac1548;\r
-reg gqaa40;\r
-reg [1:0] dz55200;\r
-wire [1:0] ksa9007;\r
-reg by48039;\r
-wire pf401ca;\r
-reg qie56;\r
-reg vv71dc4 ;\r
-reg rv8ee27 ;\r
-reg vicac6c;\r
-reg qg56362;\r
-reg [(20*8):1] fcb89f1;\r
-reg nef1679;\r
-reg ec3e2cf;\r
-reg ea6214b;\r
-reg wy10a58;\r
-reg [7 : 0] ep852c0;\r
-reg [7 : 0] ir29604;\r
-reg mr4b025;\r
-reg by5812d;\r
-reg [7 : 0] zkc096b;\r
-reg xy4b5b;\r
-reg hq25adb;\r
-reg [4 : 0] xy258ca;\r
-reg [4 : 0] ux2c652;\r
-reg [4 : 0] rge4b19;\r
-reg qgdb5f4;\r
-reg lqdafa0;\r
-reg dzd7d03;\r
-reg [1 : 0] mtbe81f;\r
-reg [1 : 0] vif40fc;\r
-reg nta07e2;\r
-reg xl3f17;\r
-reg co1f8be;\r
-reg hbc76a1;\r
-reg ie3b50f;\r
-reg gd17c75;\r
-reg kfbe3ad;\r
-reg [(20 * 8) : 1] med43cb;\r
-reg [2047:0] shdc077;\r
-wire [26:0] eae03bd;\r
-localparam ba1de9 = 27,ngef4b = 32'hfdffd30b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-assign ksa9007[1:0] = kfbe3ad ? vvd2833 : bl7b70e;\r
-assign pf401ca = ((vif40fc != mtbe81f) && !lqdafa0) || nta07e2;\r
-function [7:0] ymbc7a9;\r
-input [7:0] pfe3d48;\r
-input ls1ea47;\r
-input ayf523b;\r
-input [7:0] yma91d8;\r
-begin if(ls1ea47 == 1'b0 && ayf523b == 1'b1 && yma91d8 != 8'b00001111) ymbc7a9 = pu4b18; else if(ls1ea47 == 1'b1 && ayf523b == 1'b1) ymbc7a9 = pu4b18; else ymbc7a9 = pfe3d48;\r
-end\r
-endfunction\r
-function rv1c8c4;\r
-input [7:0] pfe3d48;\r
-input ls1ea47;\r
-input ayf523b;\r
-input [7:0] yma91d8;\r
-begin if(ls1ea47 == 1'b0 && ayf523b == 1'b1 && yma91d8 != 8'b00001111) rv1c8c4 = 1'b1; else if(ls1ea47 == 1'b1 && ayf523b == 1'b1) rv1c8c4 = 1'b1; else rv1c8c4 = pfe3d48;\r
-end\r
-endfunction\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin if(!rst_n) begin vv71dc4 <= 1'b1; rv8ee27 <= 1'b1; vicac6c <= 1'b0; qg56362 <= 1'b0; end else begin vv71dc4 <= nef1679; rv8ee27 <= hbc76a1; vicac6c <= ec3e2cf; qg56362 <= gd17c75; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin : dzd2d7d\r
-if(!rst_n) begin ph9ea41 <= 8'd0; uka9078 <= 1'd0; gof520f <= 1'd0; end\r
-else begin ph9ea41 <= xya24d7; uka9078 <= ea6214b; gof520f <= wy10a58; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin : ls99dcd\r
-if(!rst_n) begin dz55200 <= 1'd0; by48039 <= 1'd0; end\r
-else begin dz55200 <= vif40fc; by48039 <= (vif40fc != mtbe81f) && lqdafa0; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin : ks3ef3b if(!rst_n) kq782a9 <= 1'b0; else begin if(xy258ca == pu1ee65) kq782a9 <= ~qgdb5f4; else kq782a9 <= qgdb5f4; end\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin : kd701b3\r
-if(!rst_n) gqaa40 <= 1'd0;\r
-else gqaa40 <= lqdafa0;\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin : ks2ea10 if (!rst_n) begin enfda0c <= bld2223; ofed065 <= bld2223; qie56 <= 1'b0; end else if (ie3b50f) begin enfda0c <= bld2223; ofed065 <= bld2223; qie56 <= 1'b0; end else begin ofed065 <= xy258ca; if (xl3f17) begin qie56 <= 1'b0; case (xy258ca) ie888f7: begin enfda0c <= qt4bccb; end wj447b9: begin enfda0c <= en5e65c; end wl23dcc: begin enfda0c <= vvf32e4; end default: begin enfda0c <= bld2223; end\r
- endcase end else begin enfda0c <= rge4b19; case(co1f8be) 0: begin if (xy258ca == tj9111e) begin qie56 <= 1'b1; end end 1: begin if ( (xy258ca != bld2223) && (xy258ca != tj9111e) ) begin qie56 <= 1'b0; end end default: begin qie56 <= co1f8be; end endcase\r
- end end\r
-end\r
-always @(xy258ca or bl7b70e or vif40fc or ea6214b or wy10a58 or lqdafa0)\r
-begin : cb85a23 case (xy258ca) bld2223 : al7fb41 = tj9111e; tj9111e : begin if (vif40fc == vk3a506) al7fb41 = ie888f7;\r
- else if (vif40fc == hd274a0) al7fb41 = bld2223; else if (vif40fc == vvd2833) begin if (ea6214b) begin if(wy10a58 == 1'b0) al7fb41 = ipf732b; else al7fb41 = cm6d2f3; end else al7fb41 = bld2223; end else al7fb41 = bld2223; end ie888f7 : al7fb41 = wj447b9; wj447b9 : al7fb41 = wl23dcc; wl23dcc : al7fb41 = pu1ee65; pu1ee65 : al7fb41 = ie888f7; qt4bccb : al7fb41 = en5e65c; en5e65c : al7fb41 = vvf32e4; vvf32e4 : al7fb41 = bld2223;\r
- ipf732b : begin if (ea6214b == 1'b1) al7fb41 = oub995d; else begin if (wy10a58 == 1'b0) al7fb41 = qtccae9; else al7fb41 = vi5d369; end end oub995d : begin if (ea6214b == 1'b1) al7fb41 = oub995d; else begin if (wy10a58 == 1'b0) al7fb41 = qtccae9; else al7fb41 = vi5d369; end end qtccae9 : al7fb41 = ip6574d; ip6574d : begin if (lqdafa0 == 1'b0) al7fb41 = bld2223; else al7fb41 = gq2ba6d; end gq2ba6d : al7fb41 = bld2223; vi5d369 : begin if (wy10a58 == 1'b0) al7fb41 = fne9b4b; else al7fb41 = jc4da5e; end fne9b4b : al7fb41 = ip6574d; jc4da5e : begin if (ea6214b == 1'b0 && wy10a58 == 1'b0) al7fb41 = fne9b4b; else if (ea6214b == 1'b1 && wy10a58 == 1'b1) al7fb41 = cm6d2f3; else if (ea6214b == 1'b1 && wy10a58 == 1'b0) al7fb41 = ipf732b; else al7fb41 = jc4da5e; end cm6d2f3 : al7fb41 = ps69799; ps69799 : begin if (ea6214b == 1'b1) al7fb41 = oub995d; else begin if (wy10a58 == 1'b0) al7fb41 = qtccae9; else al7fb41 = vi5d369; end end default : al7fb41 = bld2223; endcase\r
-end\r
-always @(posedge gq88e04 or negedge rst_n)\r
-begin : kfbb0cb\r
-if(!rst_n) begin vvd7515 <= qge0963; hqb4ea <= qge0963; pf5a753 <= qge0963; xlba8ae <= 1'b1; end3a9e <= 1'b1; ead4576 <= 1'b0; eaea7a9 <= 1'b0; end\r
-else begin if ( (ux2c652 == bld2223) || (ux2c652 == tj9111e) || (ux2c652 == ie888f7) || (ux2c652 == wj447b9) || (ux2c652 == wl23dcc) || (ux2c652 == pu1ee65) || (ux2c652 == ipf732b) || (ux2c652 == qt4bccb) || (ux2c652 == en5e65c) || (ux2c652 == vvf32e4)) begin vvd7515 <= ep852c0; end else begin vvd7515 <= ir29604; end\r
- xlba8ae <= mr4b025; ead4576 <= by5812d; eaea7a9 <= 1'b0;\r
- case(xy258ca) bld2223 : begin hqb4ea <= qge0963; end3a9e <= 1'b1; end tj9111e : begin hqb4ea <= jcd5569; end3a9e <= 1'b0; eaea7a9 <= ~co1f8be; end ie888f7 : begin hqb4ea <= qge0963; end3a9e <= 1'b1; end wj447b9, qt4bccb : begin hqb4ea <= qgdb5f4 ? ofc3555 : gd186aa; end3a9e <= 1'b0; end wl23dcc , en5e65c: begin hqb4ea <= hdaf6e1[7:0]; end3a9e <= 1'b0; end pu1ee65 , vvf32e4: begin hqb4ea <= hdaf6e1[15:8]; end3a9e <= 1'b0; end ipf732b : begin hqb4ea <= vk258c3; end3a9e <= 1'b1; end cm6d2f3 : begin pf5a753 <= vk258c3; end3a9e <= 1'b1; end oub995d : begin pf5a753 <= ymbc7a9(zkc096b, hq25adb, xy4b5b, zkc096b); end3a9e <= rv1c8c4(1'b0, hq25adb, xy4b5b, zkc096b); end qtccae9 : begin pf5a753 <= ep2c61a; end3a9e <= 1'b1; end ip6574d, gq2ba6d, fne9b4b : begin pf5a753 <= fa630d5; end3a9e <= 1'b1; end vi5d369 : begin pf5a753 <= ymbc7a9(ep2c61a, hq25adb, xy4b5b, zkc096b); end3a9e <= 1'b1; end jc4da5e : begin pf5a753 <= ymbc7a9(fa630d5, hq25adb, xy4b5b, zkc096b); end3a9e <= 1'b1; end ps69799 : begin pf5a753 <= pu4b18; end3a9e <= 1'b1; end default : begin pf5a753 <= qge0963; end3a9e <= 1'b1; end endcase\r
-end\r
-end\r
-always @(xy258ca or dzd7d03)\r
-begin : alede5f case(xy258ca) bld2223 : eac1548 = 1'b1; tj9111e : eac1548 = 1'b0; ie888f7 : eac1548 = 1'b1; wj447b9 : eac1548 = 1'b0; qt4bccb : eac1548 = 1'b0; wl23dcc : eac1548 = 1'b1; en5e65c : eac1548 = 1'b1; pu1ee65 : eac1548 = 1'b0; vvf32e4 : eac1548 = 1'b0; ipf732b : eac1548 = ~dzd7d03; cm6d2f3 : eac1548 = ~dzd7d03; oub995d : eac1548 = ~dzd7d03; qtccae9 : eac1548 = ~dzd7d03; ip6574d : eac1548 = ~dzd7d03; gq2ba6d : eac1548 = ~dzd7d03; fne9b4b : eac1548 = ~dzd7d03; vi5d369 : eac1548 = ~dzd7d03; jc4da5e : eac1548 = ~dzd7d03; ps69799 : eac1548 = ~dzd7d03; default : eac1548 = 1'b1; endcase\r
-end\r
-always @(xy258ca)\r
-begin case (xy258ca) bld2223 : fcb89f1 = "IDLE_A"; tj9111e : fcb89f1 = "IDLE_B"; ie888f7 : fcb89f1 = "CFG_A"; wj447b9 : fcb89f1 = "CFG_B"; wl23dcc : fcb89f1 = "CFG_C"; pu1ee65 : fcb89f1 = "CFG_D"; ipf732b : fcb89f1 = "START_OF_PACKET"; oub995d : fcb89f1 = "TX_DATA"; qtccae9 : fcb89f1 = "END_OF_PACKET_NOEXT"; ip6574d : fcb89f1 = "EPD2_NOEXT"; gq2ba6d : fcb89f1 = "EPD3"; vi5d369 : fcb89f1 = "END_OF_PACKET_EXT"; fne9b4b : fcb89f1 = "EXTEND_BY_1"; jc4da5e : fcb89f1 = "CARRIER_EXTEND"; cm6d2f3 : fcb89f1 = "START_ERROR"; ps69799 : fcb89f1 = "TX_DATA_ERROR"; qt4bccb : fcb89f1 = "cleanup_CFG_B"; en5e65c : fcb89f1 = "cleanup_CFG_C"; vvf32e4 : fcb89f1 = "cleanup_CFG_D"; default : fcb89f1 = " ERROR "; endcase\r
-end\r
-always@* begin nef1679<=eae03bd[0];ec3e2cf<=eae03bd[1];ea6214b<=eae03bd[2];wy10a58<=eae03bd[3];ep852c0<={hqb4ea>>1,eae03bd[4]};ir29604<={pf5a753>>1,eae03bd[5]};mr4b025<=eae03bd[6];by5812d<=eae03bd[7];zkc096b<={ph9ea41>>1,eae03bd[8]};xy4b5b<=eae03bd[9];hq25adb<=eae03bd[10];xy258ca<={enfda0c>>1,eae03bd[11]};ux2c652<={ofed065>>1,eae03bd[12]};rge4b19<={al7fb41>>1,eae03bd[13]};qgdb5f4<=eae03bd[14];lqdafa0<=eae03bd[15];dzd7d03<=eae03bd[16];mtbe81f<={dz55200>>1,eae03bd[17]};vif40fc<={ksa9007>>1,eae03bd[18]};nta07e2<=eae03bd[19];xl3f17<=eae03bd[20];co1f8be<=eae03bd[21];hbc76a1<=eae03bd[22];ie3b50f<=eae03bd[23];gd17c75<=eae03bd[24];kfbe3ad<=eae03bd[25];med43cb<={fcb89f1>>1,eae03bd[26]};end\r
-always@* begin shdc077[2047]<=force_unidir;shdc077[2046]<=tx_en;shdc077[2044]<=tx_er;shdc077[2040]<=hqb4ea[0];shdc077[2032]<=pf5a753[0];shdc077[2016]<=end3a9e;shdc077[1985]<=eaea7a9;shdc077[1922]<=ph9ea41[0];shdc077[1796]<=gof520f;shdc077[1544]<=uka9078;shdc077[1302]<=qie56;shdc077[1115]<=rv8ee27;shdc077[1105]<=dz55200[0];shdc077[1041]<=enfda0c[0];shdc077[1023]<=mr_main_reset;shdc077[728]<=fcb89f1[1];shdc077[651]<=pf401ca;shdc077[557]<=vv71dc4;shdc077[552]<=gqaa40;shdc077[364]<=qg56362;shdc077[325]<=by48039;shdc077[276]<=eac1548;shdc077[182]<=vicac6c;shdc077[162]<=ksa9007[0];shdc077[138]<=kq782a9;shdc077[69]<=al7fb41[0];shdc077[34]<=ofed065[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module ale23cd ( gq88e04,\r
- rst_n,\r
- xlba8ae,\r
- nrcd8ab,\r
- jc6c55f,\r
- su62afb,\r
- ie157d9,\r
- anabec9,\r
- ead4576,\r
- vifb26e );\r
-input gq88e04;\r
-input rst_n;\r
-input xlba8ae;\r
-input [7:0] nrcd8ab;\r
-input jc6c55f;\r
-input su62afb;\r
-input ie157d9;\r
-input anabec9;\r
-input ead4576;\r
-output [9:0] vifb26e;\r
-reg [9:0] vifb26e;\r
-reg [7:0] kf85f2c;\r
-reg hq2f965;\r
-wire dm7cb2b;\r
-reg [9:6] eae595b;\r
-reg [5:0] yz2cad8;\r
-reg [9:6] gb656c4;\r
-reg [5:0] qi2b625;\r
-reg uv5b128, thd8944, icc4a26, ri25131, db2898b;\r
-reg uv44c5e, kf262f5, sw317ac, ph8bd60, wj5eb06;\r
-reg kqf5835;\r
-reg [7 : 0] ecac1a9;\r
-reg gb60d49;\r
-reg ph6a4c;\r
-reg ri35266;\r
-reg eca9332;\r
-reg ea49991;\r
-reg [7 : 0] os4cc89;\r
-reg rg66449;\r
-reg zz3224a;\r
-reg [9 : 6] xl91257;\r
-reg [5 : 0] pu892bf;\r
-reg [9 : 6] ui495fa;\r
-reg [5 : 0] ld4afd0;\r
-reg ps57e86;\r
-reg fpbf433;\r
-reg uifa19f;\r
-reg lqd0cf9;\r
-reg tw867ca;\r
-reg cb33e53;\r
-reg qv9f29c;\r
-reg nrf94e4;\r
-reg dmca726;\r
-reg go53933;\r
-reg [2047:0] shdc077;\r
-wire [23:0] eae03bd;\r
-localparam ba1de9 = 24,ngef4b = 32'hfdffca8b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-always @(posedge gq88e04 or negedge rst_n) begin if (rst_n == 1'b0) hq2f965 <= 1'b0; else hq2f965 <= go53933; end\r
-assign dm7cb2b = gb60d49 ? ph6a4c : rg66449;\r
-always @(posedge gq88e04 or negedge rst_n) begin if (rst_n == 1'b0) vifb26e <= 10'b00_0000_0000; else vifb26e <= {ui495fa[9:6], ld4afd0[5:0]}; end\r
-always @(ecac1a9 or ri35266 or eca9332 or zz3224a or ea49991)\r
-begin if(ea49991 && !zz3224a) begin if (ri35266) kf85f2c = {ecac1a9[7:6], 1'b1, ecac1a9[4:0]}; if (eca9332) kf85f2c = 8'b110_00101; else kf85f2c = ecac1a9; end else kf85f2c = ecac1a9;\r
-end\r
-always@(os4cc89 or kqf5835)\r
-begin: qtd6932\r
-case (os4cc89[3:0]) 4'b0000 : begin yz2cad8[0] = os4cc89[0]; yz2cad8[1] = 1; yz2cad8[2] = 1; yz2cad8[3] = os4cc89[3]; yz2cad8[4] = os4cc89[4]; yz2cad8[5] = os4cc89[4]; uv5b128 = os4cc89[4]; thd8944 = !os4cc89[4]; icc4a26 = !os4cc89[4]; ri25131 = os4cc89[4]; end 4'b1000 , 4'b0100 , 4'b0010 , 4'b0001 : begin if (os4cc89[4] == 0) begin yz2cad8[0] = os4cc89[0]; yz2cad8[1] = os4cc89[1]; yz2cad8[2] = os4cc89[2]; yz2cad8[3] = os4cc89[3]; yz2cad8[4] = 1; yz2cad8[5] = 0; uv5b128 = os4cc89[4]; thd8944 = !os4cc89[4]; icc4a26 = !os4cc89[4]; ri25131 = os4cc89[4]; end else if (os4cc89[3] == 0) begin yz2cad8[0] = os4cc89[0]; yz2cad8[1] = os4cc89[1]; yz2cad8[2] = os4cc89[2]; yz2cad8[3] = os4cc89[3]; yz2cad8[4] = os4cc89[4]; yz2cad8[5] = 1; uv5b128 = 0; thd8944 = 0; icc4a26 = 0; ri25131 = 0; end else begin yz2cad8[0] = os4cc89[0]; yz2cad8[1] = os4cc89[1]; yz2cad8[2] = 1; yz2cad8[3] = os4cc89[3]; yz2cad8[4] = 0; yz2cad8[5] = 0; uv5b128 = 0; thd8944 = 1; icc4a26 = 1; ri25131 = 0; end end 4'b1100 : begin yz2cad8[0] = os4cc89[0]; yz2cad8[1] = os4cc89[1]; yz2cad8[2] = os4cc89[2]; yz2cad8[3] = os4cc89[3]; yz2cad8[4] = os4cc89[4]; if (kqf5835 == 1 && os4cc89[4] == 1) begin uv5b128 = kqf5835; thd8944 = !kqf5835; icc4a26 = 0; ri25131 = 1; yz2cad8[5] = 1; end else begin uv5b128 = 0; thd8944 = 0; icc4a26 = 0; ri25131 = 0; if (os4cc89[4] == 0) yz2cad8[5] = 1; else yz2cad8[5] = 0; end end 4'b0011 , 4'b1010 , 4'b0101 , 4'b1001 , 4'b0110 : begin yz2cad8[0] = os4cc89[0]; yz2cad8[1] = os4cc89[1]; yz2cad8[2] = os4cc89[2]; yz2cad8[3] = os4cc89[3]; yz2cad8[4] = os4cc89[4]; uv5b128 = 0; thd8944 = 0; icc4a26 = 0; ri25131 = 0; if (os4cc89[4] == 0) yz2cad8[5] = 1; else yz2cad8[5] = 0; end 4'b1111: begin yz2cad8[0] = os4cc89[0]; yz2cad8[1] = 0; yz2cad8[2] = os4cc89[2]; yz2cad8[3] = 0; yz2cad8[4] = os4cc89[4]; yz2cad8[5] = os4cc89[4]; uv5b128 = os4cc89[4]; thd8944 = !os4cc89[4]; icc4a26 = !os4cc89[4]; ri25131 = os4cc89[4]; end 4'b0111 : begin yz2cad8[0] = os4cc89[0]; yz2cad8[1] = os4cc89[1]; yz2cad8[2] = os4cc89[2]; yz2cad8[3] = os4cc89[3]; yz2cad8[4] = os4cc89[4]; yz2cad8[5] = 0; thd8944 = 0; uv5b128 = os4cc89[4]; icc4a26 = 0; ri25131 = 1; end 4'b1101 , 4'b1011 , 4'b1110 : begin yz2cad8[0] = os4cc89[0]; yz2cad8[1] = os4cc89[1]; yz2cad8[2] = os4cc89[2]; yz2cad8[3] = os4cc89[3]; yz2cad8[4] = os4cc89[4]; yz2cad8[5] = 0; thd8944 = 0; uv5b128 = os4cc89[4]; icc4a26 = 0; ri25131 = os4cc89[4]; end default : begin yz2cad8[5:0] = 0; uv5b128 = 0; thd8944 = 0; icc4a26 = 0; ri25131 = 0; end\r
-endcase\r
-end\r
-always@(ps57e86 or fpbf433 or uifa19f or lqd0cf9 or zz3224a or pu892bf)\r
-begin: by5d135\r
-if ((uifa19f && zz3224a) || (lqd0cf9 && !zz3224a) || (!uifa19f && !lqd0cf9)) begin qi2b625[5:0] = pu892bf[5:0]; if (!ps57e86 && !fpbf433) db2898b = zz3224a; else db2898b = ps57e86;\r
-end\r
-else begin qi2b625[0] = !pu892bf[0]; qi2b625[1] = !pu892bf[1]; qi2b625[2] = !pu892bf[2]; qi2b625[3] = !pu892bf[3]; qi2b625[4] = !pu892bf[4]; qi2b625[5] = !pu892bf[5]; if (!ps57e86 && !fpbf433) db2898b = zz3224a; else db2898b = !ps57e86;\r
-end\r
-end\r
-always@(os4cc89 or kqf5835 or ld4afd0 or tw867ca)\r
-begin: en4e43d\r
-case (os4cc89[7:5]) 3'b000 : begin eae595b[6] = os4cc89[5]; eae595b[7] = !os4cc89[6]; eae595b[8] = os4cc89[7]; eae595b[9] = 0; sw317ac = 1; ph8bd60 = 0; uv44c5e = 0; kf262f5 = 1; end 3'b001 , 3'b010 , 3'b101 , 3'b110 : begin eae595b[6] = os4cc89[5]; eae595b[7] = os4cc89[6]; eae595b[8] = os4cc89[7]; eae595b[9] = !os4cc89[7]; if (kqf5835 == 1) sw317ac = 1; else sw317ac = 0; ph8bd60 = 0; uv44c5e = 0; kf262f5 = 0; end 3'b011 : begin eae595b[6] = os4cc89[5]; eae595b[7] = os4cc89[6]; eae595b[8] = os4cc89[7]; eae595b[9] = 0; sw317ac = 0; ph8bd60 = 1; uv44c5e = 0; kf262f5 = 0; end 3'b100 : begin eae595b[6] = os4cc89[5]; eae595b[7] = os4cc89[6]; eae595b[8] = os4cc89[7]; eae595b[9] = 0; sw317ac = 1; ph8bd60 = 0; uv44c5e = 0; kf262f5 = 1; end 3'b111 : begin if ((ld4afd0[4] == 1 && ld4afd0[5] == 1 && tw867ca == 0) || (ld4afd0[4] == 0 && ld4afd0[5] == 0 && tw867ca == 1) || (kqf5835 == 1)) begin eae595b[6] = 0; eae595b[7] = os4cc89[6]; eae595b[8] = os4cc89[7]; eae595b[9] = 1; sw317ac = 0; ph8bd60 = 1; uv44c5e = 1; kf262f5 = 0; end else begin eae595b[6] = os4cc89[5]; eae595b[7] = os4cc89[6]; eae595b[8] = os4cc89[7]; eae595b[9] = 0; sw317ac = 0; ph8bd60 = 1; uv44c5e = 1; kf262f5 = 0; end end default : begin eae595b[6] = os4cc89[5]; eae595b[7] = os4cc89[6]; eae595b[8] = os4cc89[7]; eae595b[9] = 0; sw317ac = 0; ph8bd60 = 0; uv44c5e = 0; kf262f5 = 0; end\r
-endcase\r
-end\r
-always@(cb33e53 or qv9f29c or nrf94e4 or dmca726 or tw867ca or xl91257)\r
-begin: dbb5df6\r
-if ((nrf94e4 && tw867ca) || (dmca726 && !tw867ca) || (!nrf94e4 && !dmca726)) begin gb656c4[9:6] = xl91257[9:6]; if (!cb33e53 && !qv9f29c) wj5eb06 = tw867ca; else wj5eb06 = cb33e53;\r
-end\r
-else begin gb656c4[6] = !xl91257[6]; gb656c4[7] = !xl91257[7]; gb656c4[8] = !xl91257[8]; gb656c4[9] = !xl91257[9]; if (!cb33e53 && !qv9f29c) wj5eb06 = tw867ca; else wj5eb06 = !cb33e53;\r
-end\r
-end\r
-always@* begin kqf5835<=eae03bd[0];ecac1a9<={nrcd8ab>>1,eae03bd[1]};gb60d49<=eae03bd[2];ph6a4c<=eae03bd[3];ri35266<=eae03bd[4];eca9332<=eae03bd[5];ea49991<=eae03bd[6];os4cc89<={kf85f2c>>1,eae03bd[7]};rg66449<=eae03bd[8];zz3224a<=eae03bd[9];xl91257<={eae595b>>1,eae03bd[10]};pu892bf<={yz2cad8>>1,eae03bd[11]};ui495fa<={gb656c4>>1,eae03bd[12]};ld4afd0<={qi2b625>>1,eae03bd[13]};ps57e86<=eae03bd[14];fpbf433<=eae03bd[15];uifa19f<=eae03bd[16];lqd0cf9<=eae03bd[17];tw867ca<=eae03bd[18];cb33e53<=eae03bd[19];qv9f29c<=eae03bd[20];nrf94e4<=eae03bd[21];dmca726<=eae03bd[22];go53933<=eae03bd[23];end\r
-always@* begin shdc077[2047]<=nrcd8ab[0];shdc077[2046]<=jc6c55f;shdc077[2044]<=su62afb;shdc077[2040]<=ie157d9;shdc077[2032]<=anabec9;shdc077[2017]<=ead4576;shdc077[1987]<=kf85f2c[0];shdc077[1926]<=hq2f965;shdc077[1804]<=dm7cb2b;shdc077[1803]<=wj5eb06;shdc077[1560]<=eae595b[6];shdc077[1550]<=icc4a26;shdc077[1072]<=yz2cad8[0];shdc077[1052]<=ri25131;shdc077[1023]<=xlba8ae;shdc077[901]<=ph8bd60;shdc077[775]<=thd8944;shdc077[450]<=sw317ac;shdc077[387]<=uv5b128;shdc077[225]<=kf262f5;shdc077[193]<=qi2b625[0];shdc077[112]<=uv44c5e;shdc077[96]<=gb656c4[6];shdc077[56]<=db2898b;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
-`timescale 1 ns / 100 ps\r
-module sgmii_gbe_pcs35 (\r
- tx_clk_125 ,\r
- serdes_recovered_clk ,\r
- rx_clk_125 ,\r
- rst_n ,\r
- gbe_mode ,\r
- sgmii_mode ,\r
- signal_detect ,\r
- debug_link_timer_short,\r
- force_isolate,\r
- force_loopback,\r
- force_unidir,\r
- operational_rate,\r
- rx_compensation_err,\r
- ctc_drop_flag,\r
- ctc_add_flag,\r
- an_link_ok,\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
- tx_clock_enable_sink ,\r
- tx_clock_enable_source ,\r
- rx_clock_enable_sink ,\r
- rx_clock_enable_source ,\r
-`else\r
- tx_clk_mii ,\r
- rx_clk_mii ,\r
-`endif\r
- rx_data ,\r
- rx_kcntl ,\r
- rx_even ,\r
- rx_disp_err ,\r
- rx_cv_err ,\r
- rx_err_decode_mode ,\r
- tx_d ,\r
- tx_en ,\r
- tx_er ,\r
- mr_adv_ability ,\r
- mr_an_enable ,\r
- mr_main_reset ,\r
- mr_restart_an ,\r
- mr_an_complete ,\r
- mr_lp_adv_ability ,\r
- mr_page_rx ,\r
- rx_d ,\r
- rx_dv ,\r
- rx_er ,\r
- col ,\r
- crs ,\r
- tx_data,\r
- tx_kcntl,\r
- tx_disparity_cntl,\r
- xmit_autoneg\r
- ) ;\r
-input tx_clk_125 ;\r
-input serdes_recovered_clk ;\r
-input rx_clk_125 ;\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-input tx_clock_enable_sink;\r
-output tx_clock_enable_source;\r
-input rx_clock_enable_sink;\r
-output rx_clock_enable_source;\r
-`else\r
-input tx_clk_mii;\r
-input rx_clk_mii;\r
-`endif\r
-input rst_n ;\r
-input signal_detect ;\r
-input gbe_mode ;\r
-input sgmii_mode ;\r
-input debug_link_timer_short ;\r
-input force_isolate ;\r
-input force_loopback ;\r
-input force_unidir ;\r
-input [1:0] operational_rate;\r
-output rx_compensation_err;\r
-output ctc_drop_flag;\r
-output ctc_add_flag;\r
-output an_link_ok;\r
-input [7:0] rx_data ;\r
-input rx_kcntl ;\r
-input rx_even ;\r
-input rx_disp_err ;\r
-input rx_cv_err ;\r
-input rx_err_decode_mode ;\r
-input [7:0] tx_d ;\r
-input tx_en ;\r
-input tx_er ;\r
-input [15:0] mr_adv_ability;\r
-input mr_an_enable;\r
-input mr_main_reset;\r
-input mr_restart_an;\r
-output mr_an_complete;\r
-output [15:0] mr_lp_adv_ability;\r
-output mr_page_rx;\r
-output [7:0] rx_d ;\r
-output rx_dv ;\r
-output rx_er ;\r
-output col ;\r
-output crs ;\r
-output [7:0] tx_data ;\r
-output tx_kcntl ;\r
-output tx_disparity_cntl ;\r
-output xmit_autoneg ;\r
-`ifdef SGMII_YES_ENC\r
-wire [7:0] mre7ae7 ;\r
-wire ph3d73d ;\r
-wire eaea7a9 ;\r
-`endif\r
-wire [1:0] bl7b70e ;\r
-wire [15:0] kqf5edc ;\r
-wire [15:0] hdaf6e1 ;\r
-wire [15:0] mr_adv_ability ;\r
-wire [15:0] mr_lp_adv_ability ;\r
-wire su531f3;\r
-wire [7:0] psc5e98;\r
-wire vk2f4c3;\r
-wire ip7a61a;\r
-wire rx_compensation_err;\r
-wire mg986ac;\r
-wire kdc3561;\r
-wire gq1ab0d;\r
-wire ned5869;\r
-wire ieac34a;\r
-wire an_link_ok;\r
-reg vif4422;\r
-reg lsa2112;\r
-reg aa10892;\r
-reg lf84490;\r
-reg nt22486;\r
-reg sj12436;\r
-reg mga3f36 ;\r
-reg mg1f9b1 ;\r
-reg ldfcd89 ;\r
-reg the6c4f ;\r
-reg sj3627f ;\r
-reg sjb13fd ;\r
-reg ng89fec ;\r
-wire [7:0] ld4ff63;\r
-wire qt7fb1e;\r
-wire czfd8f4;\r
-wire [7:0] zxec7a5;\r
-wire rg63d2f;\r
-wire ba1e97b;\r
-wire zkf4bdb;\r
-wire xla5edb;\r
-wire ctc_drop_flag;\r
-wire ctc_add_flag;\r
-reg cmdb797;\r
-reg cmdbcb8;\r
-wire [7:0] gode5c1;\r
-wire kdf2e08;\r
-wire aa97044;\r
-reg jeb8220;\r
-reg wwc1102;\r
-reg wl8810;\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-reg en44085;\r
-reg hq2042c;\r
-`endif\r
-parameter DYNAMIC_LT_10MBPS = 340;\r
-parameter DYNAMIC_HT_10MBPS = 680;\r
-parameter DYNAMIC_LT_100MBPS = 34;\r
-parameter DYNAMIC_HT_100MBPS = 68;\r
-parameter DYNAMIC_LT_1000MBPS = 16;\r
-parameter DYNAMIC_HT_1000MBPS = 32;\r
-parameter STATIC_LO_THRESH = 16;\r
-parameter STATIC_HI_THRESH = 32;\r
-parameter LINK_TIMER_SH = 21'h1fff01;\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-`endif\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_CTC_DYNAMIC\r
-`endif\r
-`ifdef SGMII_YES_CTC_STATIC\r
-`endif\r
-`ifdef SGMII_NO_CTC\r
-`endif\r
-`ifdef SGMII_YES_ENC\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_ENC\r
-`else\r
-`endif\r
-reg pu86d04;\r
-reg lf27c59;\r
-reg uk8d6fa;\r
-reg su67fd6;\r
-reg ohb4114;\r
-reg wwff58a;\r
-reg ec3e2cf;\r
-reg [1 : 0] qi8879a;\r
-reg [7 : 0] ofdce1f;\r
-reg wje70fc;\r
-reg gq1f934;\r
-reg qi8892d;\r
-reg ip44969;\r
-reg qi24b4d;\r
-reg [7 : 0] pu25a68;\r
-reg ea6214b;\r
-reg wy10a58;\r
-reg qg59e57;\r
-reg nef1679;\r
-reg bn8b3ca;\r
-reg [1 : 0] pffc9a1;\r
-reg [15 : 0] ntba454;\r
-reg [15 : 0] jpd22a7;\r
-reg nt387e4;\r
-reg [7 : 0] cb8a9f7;\r
-reg wj54fbc;\r
-reg doa7de4;\r
-reg sw3ef23;\r
-reg shf7918;\r
-reg mgbc8c4;\r
-reg zke4621;\r
-reg oh2310b;\r
-reg gof5284;\r
-reg uka9420;\r
-reg fn4a101;\r
-reg zx5080f;\r
-reg db8407e;\r
-reg zm203f6;\r
-reg xy20283;\r
-reg xy141b;\r
-reg coa0da;\r
-reg bl506d1;\r
-reg vk8368f;\r
-reg ri1b47b;\r
-reg tuda3da;\r
-reg [7 : 0] icd1ed2;\r
-reg wl8f690;\r
-reg fn7b485;\r
-reg [7 : 0] vida42f;\r
-reg bld217a;\r
-reg sj90bd6;\r
-reg yz85eb4;\r
-reg pu2f5a5;\r
-reg mr7ad2a;\r
-reg wjd6954;\r
-reg [7 : 0] irb4aa5;\r
-reg rva552d;\r
-reg ba2a96f;\r
-reg ip54b7b;\r
-reg xla5bdc;\r
-reg vx2dee6;\r
-reg [2047:0] shdc077;\r
-wire [60:0] eae03bd;\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_ENC\r
-`endif\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-`endif\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-`endif\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_CTC_DYNAMIC\r
-`endif\r
-`ifdef SGMII_YES_CTC_STATIC\r
-`endif\r
-`ifdef SGMII_NO_CTC\r
-`endif\r
-`ifdef SGMII_YES_ENC\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_ENC\r
-`else\r
-`endif\r
-localparam ba1de9 = 61,ngef4b = 32'hfdffe30b;\r
-localparam [31:0] ea77a5a = ngef4b;\r
-localparam the9682 = ngef4b & 4'hf;\r
-localparam [11:0] fn5a0bd = 'h7ff;\r
-wire [(1 << the9682) -1:0] uk82f73;\r
-reg [ba1de9-1:0] jebdcc5;\r
-reg [the9682-1:0] dm7315a [0:1];\r
-reg [the9682-1:0] nec5698;\r
-reg aa2b4c2;\r
-integer xj5a610;\r
-integer qtd3086;\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_ENC\r
-`endif\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-`endif\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-`endif\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_CTC_DYNAMIC\r
-`endif\r
-`ifdef SGMII_YES_CTC_STATIC\r
-`endif\r
-`ifdef SGMII_NO_CTC\r
-`endif\r
-`ifdef SGMII_YES_ENC\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_ENC\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
-`else\r
-`endif\r
-`ifdef SGMII_YES_ENC\r
-`endif\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
-`endif\r
-assign kdc3561 = ({gq1f934, ip44969, qi8892d} == 3'b100) ? 1'b1 : 1'b0;\r
-assign gq1ab0d = ({gq1f934, ip44969, qi8892d} == 3'b111) ? 1'b1 : 1'b0;\r
-assign ned5869 = shf7918 | mgbc8c4;\r
-assign ieac34a = ip44969 | qi8892d;\r
-assign su531f3 = (qi24b4d) ? zke4621 : oh2310b;\r
-always @(posedge tx_clk_125 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin jeb8220 <= 1'b0; end else begin jeb8220 <= ~ip54b7b; end\r
-end\r
-always @(posedge rx_clk_125 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin wwc1102 <= 1'b0; end else begin wwc1102 <= ~xla5bdc; end\r
-end\r
-always @(posedge serdes_recovered_clk or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin wl8810 <= 1'b0; end else begin wl8810 <= ~vx2dee6; end\r
-end\r
-`ifndef SGMII_YES_SINGLE_CLOCK\r
- always @(posedge tx_clk_mii or negedge rst_n) begin if (rst_n == 1'b0) begin en44085 <= 1'b0; end else begin en44085 <= ~en44085; end end always @(posedge rx_clk_mii or negedge rst_n) begin if (rst_n == 1'b0) begin hq2042c <= 1'b0; end else begin hq2042c <= ~hq2042c; end end\r
-`endif\r
-`ifdef SGMII_YES_SINGLE_CLOCK\r
- coac47 kdfd43d ( .rst_n ( rst_n ) , .gbe_mode ( pu86d04 ) , .gq88e04 ( tx_clk_125 ) , .fa47021 ( tx_clock_enable_sink ) , .aaffa2 ( tx_clock_enable_source ) , .gb5e68a ( qi8879a ) , .force_isolate ( ohb4114 ) , .an8c7c ( pu25a68 ) , .ic463e5 ( wy10a58 ) , .qi31f29 ( ea6214b ) , .vi7ca4c ( ld4ff63 ) , .sue5263 ( qt7fb1e ) , .kf29319 ( czfd8f4 ) ); thddcda ri1b0d3 ( .rst_n ( rst_n ) , .gbe_mode ( pu86d04 ) , .force_isolate ( ohb4114 ) , .gq88e04 ( rx_clk_125 ) , .fa47021 ( rx_clock_enable_sink ) , .aaffa2 ( rx_clock_enable_source ) , .gb5e68a ( qi8879a ) , .an8c7c ( vida42f ) , .ic463e5 ( bld217a ) , .qi31f29 ( sj90bd6 ) , .qva4f56 ( yz85eb4 ) , .rv27ab4 ( pu2f5a5 ) , .vi7ca4c ( rx_d ) , .sue5263 ( rx_er ) , .kf29319 ( rx_dv ), .uk3e26b ( col ) , .lqf1359 ( crs ) );\r
-`else\r
- ay68728 kdfd43d ( .rst_n ( rst_n ) , .gbe_mode ( pu86d04 ) , .mee5046 ( tx_clk_mii ) , .ph28231 ( qi8879a ) , .force_isolate ( ohb4114 ) , .an8c7c ( pu25a68 ) , .ic463e5 ( wy10a58 ) , .qi31f29 ( ea6214b ) , .cb8f949 ( tx_clk_125 ) , .vi7ca4c ( ld4ff63 ) , .sue5263 ( qt7fb1e ) , .kf29319 ( czfd8f4 ) ); ld4aee6 ri1b0d3 ( .rst_n ( rst_n ) , .gbe_mode ( pu86d04 ) , .force_isolate ( ohb4114 ) , .mee5046 ( rx_clk_125 ) , .an8c7c ( vida42f ) , .ic463e5 ( bld217a ) , .qi31f29 ( sj90bd6 ) , .qva4f56 ( yz85eb4 ) , .rv27ab4 ( pu2f5a5 ) , .cb8f949 ( rx_clk_mii ) , .ayead3e ( qi8879a ) , .vi7ca4c ( rx_d ) , .sue5263 ( rx_er ) , .kf29319 ( rx_dv ), .uk3e26b ( col ) , .lqf1359 ( crs ) );\r
-`endif\r
-`ifdef SGMII_YES_CTC_DYNAMIC\r
- phc858 # (.DYNAMIC_HT_1000MBPS(DYNAMIC_HT_1000MBPS), .DYNAMIC_LT_1000MBPS(DYNAMIC_LT_1000MBPS), .DYNAMIC_HT_100MBPS (DYNAMIC_HT_100MBPS), .DYNAMIC_LT_100MBPS (DYNAMIC_LT_100MBPS), .DYNAMIC_HT_10MBPS (DYNAMIC_HT_10MBPS), .DYNAMIC_LT_10MBPS (DYNAMIC_LT_10MBPS)) xjc8ae8 ( .rst_n (rst_n), .mr_main_reset (tuda3da), .an_link_ok (an_link_ok), .tu58fcb (qg59e57), .gbe_mode (pu86d04), .operational_rate (qi8879a), .thf96b3 (serdes_recovered_clk), .ykcb59e (ofdce1f), .vv5acf1 (wje70fc), .end678f (nt387e4), .oub3c7c (rx_clk_125), .jr9e3e0 (psc5e98), .hof1f06 (vk2f4c3), .ir8f833 (ip7a61a), .rg7c19c (rx_compensation_err), .ctc_drop_flag (ctc_drop_flag), .ctc_add_flag (ctc_add_flag) );\r
-`endif\r
-`ifdef SGMII_YES_CTC_STATIC\r
- vvd70c4 # (.STATIC_HI_THRESH(STATIC_HI_THRESH), .STATIC_LO_THRESH(STATIC_LO_THRESH)) xjc8ae8 ( .rst_n (rst_n), .mr_main_reset (tuda3da), .thf96b3 (serdes_recovered_clk), .ykcb59e (ofdce1f), .vv5acf1 (wje70fc), .end678f (nt387e4), .oub3c7c (rx_clk_125), .jr9e3e0 (psc5e98), .hof1f06 (vk2f4c3), .ir8f833 (ip7a61a), .rg7c19c (rx_compensation_err), .ctc_drop_flag (ctc_drop_flag), .ctc_add_flag (ctc_add_flag) );\r
-`endif\r
-`ifdef SGMII_NO_CTC\r
- yz29ae8 xjc8ae8 ( .rst_n (rst_n), .mr_main_reset (tuda3da), .thf96b3 (serdes_recovered_clk), .ykcb59e (ofdce1f), .vv5acf1 (wje70fc), .end678f (nt387e4), .oub3c7c (rx_clk_125), .jr9e3e0 (psc5e98), .hof1f06 (vk2f4c3), .ir8f833 (ip7a61a), .rg7c19c (rx_compensation_err) );\r
-assign ctc_drop_flag = 1'b0;\r
-assign ctc_add_flag = 1'b0;\r
-`endif\r
-always @(posedge rx_clk_125 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin cmdb797 <= 1'b0; cmdbcb8 <= 1'b0; end else begin cmdb797 <= wwff58a; cmdbcb8 <= mr7ad2a; end\r
-end\r
-`ifdef SGMII_YES_ENC\r
- assign gode5c1 = wjd6954 ? mre7ae7 : cb8a9f7; assign kdf2e08 = wjd6954 ? ph3d73d : wj54fbc; assign aa97044 = wjd6954 ? 1'b0 : doa7de4;\r
-`else\r
- assign gode5c1 = wjd6954 ? tx_data : cb8a9f7; assign kdf2e08 = wjd6954 ? tx_kcntl : wj54fbc; assign aa97044 = wjd6954 ? 1'b0 : doa7de4;\r
-`endif\r
-ecaab ecaab ( .vxa5777 ( rx_clk_125 ) , .rst_n ( rst_n ) , .mr_main_reset ( tuda3da ) , .signal_detect ( uk8d6fa ) , .rx_data ( irb4aa5 ) , .rx_kcntl ( rva552d ) , .su531f3 ( ba2a96f ) , .lfa55f5 ( lfa55f5 ) , .rx_even ( mg986ac ) );\r
-pf74aee pf74aee ( .vxa5777 ( rx_clk_125 ) , .rst_n ( rst_n ) , .mr_main_reset ( tuda3da ) , .sgmii_mode ( lf27c59 ) , .gbe_mode ( pu86d04 ) , .zzbf298 ( mr_adv_ability[12] ) , .rx_data ( irb4aa5 ) , .rx_kcntl ( rva552d ) , .su531f3 ( ba2a96f ) , .lfa55f5 ( lfa55f5 ) , .rx_even ( sw3ef23 ) , .bl7b70e ( pffc9a1 ) , .kqf5edc( kqf5edc ) , .co9818f ( co9818f ) , .hoc0c79 ( hoc0c79 ) , .lf63cb ( lf63cb ) , .ou31e5f ( zxec7a5 ) , .mt8f2f9 ( ba1e97b ) , .by797cd ( rg63d2f ) );\r
- shf7264 # (.LINK_TIMER_SH(LINK_TIMER_SH)) shf7264 ( .gq88e04 ( tx_clk_125 ) , .rst_n ( rst_n ) , .gbe_mode ( pu86d04 ) , .sgmii_mode ( lf27c59 ) , .force_unidir ( ec3e2cf ) , .mr_main_reset ( tuda3da ) , .mr_restart_an ( bn8b3ca ) , .mr_an_enable ( qg59e57 ) , .mr_adv_ability ( mr_adv_ability ) , .mr_lp_adv_ability ( mr_lp_adv_ability ) , .mr_page_rx ( mr_page_rx ) , .mr_an_complete ( mr_an_complete ) , .fp9ed2a ( su67fd6 ) , .lfa55f5 ( lfa55f5 ) , .fc2afaf ( lf63cb ) , .ne57d7b ( hoc0c79 ) , .ohbebdb ( co9818f ) , .kqf5edc ( ntba454 ) , .hdaf6e1 ( hdaf6e1 ) , .bl7b70e ( bl7b70e ), .an_link_ok ( an_link_ok ) );\r
-`ifdef SGMII_YES_ENC\r
- wl3c3b2 wl3c3b2 ( .gq88e04 ( tx_clk_125 ) , .rst_n ( rst_n ) , .mr_main_reset ( tuda3da ), .force_unidir ( ec3e2cf ), .xya24d7 ( icd1ed2 ) , .tx_en ( fn7b485 ) , .tx_er ( wl8f690 ) , .bl7b70e ( pffc9a1 ) , .hdaf6e1 ( jpd22a7 ) , .vvd7515 ( mre7ae7 ) , .xlba8ae ( ph3d73d ), .ead4576 ( eaea7a9 ) );\r
- ale23cd ale23cd ( .gq88e04 (tx_clk_125), .rst_n (rst_n), .xlba8ae (ph3d73d), .nrcd8ab (mre7ae7), .jc6c55f (1'b0), .su62afb (1'b0), .ie157d9 (1'b0), .anabec9 (1'b1), .ead4576 (eaea7a9), .vifb26e ({tx_disparity_cntl, tx_kcntl, tx_data}) );\r
-`else\r
- wl3c3b2 wl3c3b2 ( .gq88e04 ( tx_clk_125 ) , .rst_n ( rst_n ) , .mr_main_reset ( tuda3da ), .force_unidir ( ec3e2cf ), .xya24d7 ( icd1ed2 ) , .tx_en ( fn7b485 ) , .tx_er ( wl8f690 ) , .bl7b70e ( pffc9a1 ) , .hdaf6e1 ( jpd22a7 ) , .vvd7515 ( tx_data ) , .xlba8ae ( tx_kcntl ), .ead4576 ( tx_disparity_cntl ) );\r
-`endif\r
-assign zkf4bdb = rx_dv & ea6214b;\r
-assign xla5edb = rx_dv;\r
-assign xmit_autoneg = ((pffc9a1==2'b01)||(pffc9a1==2'b00)) ? 1'b1 : 1'b0;\r
-always @(posedge tx_clk_125 or negedge rst_n)\r
-begin if (rst_n == 1'b0) begin vif4422 <= 1'b0; lsa2112 <= 1'b0; aa10892 <= 1'b0; lf84490 <= 1'b0; nt22486 <= 1'b0; sj12436 <= 1'b0; mga3f36 <= 1'b1; mg1f9b1 <= 1'b1; ldfcd89 <= 1'b1; the6c4f <= 1'b1; sj3627f <= 1'b1; sjb13fd <= 1'b1; ng89fec <= 1'b1; end else begin vif4422 <= pu86d04; lsa2112 <= gof5284; mga3f36 <= nef1679; mg1f9b1 <= xy20283; aa10892 <= uka9420; lf84490 <= uka9420 & (~fn4a101); nt22486 <= ~uka9420 & (fn4a101); sj12436 <= zx5080f || db8407e; ldfcd89 <= xy141b | zm203f6; the6c4f <= coa0da; sj3627f <= bl506d1; sjb13fd <= vk8368f; ng89fec <= coa0da | bl506d1 | vk8368f | ri1b47b; end\r
-end\r
-always@* begin pu86d04<=eae03bd[0];lf27c59<=eae03bd[1];uk8d6fa<=eae03bd[2];su67fd6<=eae03bd[3];ohb4114<=eae03bd[4];wwff58a<=eae03bd[5];ec3e2cf<=eae03bd[6];qi8879a<={operational_rate>>1,eae03bd[7]};ofdce1f<={rx_data>>1,eae03bd[8]};wje70fc<=eae03bd[9];gq1f934<=eae03bd[10];qi8892d<=eae03bd[11];ip44969<=eae03bd[12];qi24b4d<=eae03bd[13];pu25a68<={tx_d>>1,eae03bd[14]};ea6214b<=eae03bd[15];wy10a58<=eae03bd[16];qg59e57<=eae03bd[17];nef1679<=eae03bd[18];bn8b3ca<=eae03bd[19];pffc9a1<={bl7b70e>>1,eae03bd[20]};ntba454<={kqf5edc>>1,eae03bd[21]};jpd22a7<={hdaf6e1>>1,eae03bd[22]};nt387e4<=eae03bd[23];cb8a9f7<={psc5e98>>1,eae03bd[24]};wj54fbc<=eae03bd[25];doa7de4<=eae03bd[26];sw3ef23<=eae03bd[27];shf7918<=eae03bd[28];mgbc8c4<=eae03bd[29];zke4621<=eae03bd[30];oh2310b<=eae03bd[31];gof5284<=eae03bd[32];uka9420<=eae03bd[33];fn4a101<=eae03bd[34];zx5080f<=eae03bd[35];db8407e<=eae03bd[36];zm203f6<=eae03bd[37];xy20283<=eae03bd[38];xy141b<=eae03bd[39];coa0da<=eae03bd[40];bl506d1<=eae03bd[41];vk8368f<=eae03bd[42];ri1b47b<=eae03bd[43];tuda3da<=eae03bd[44];icd1ed2<={ld4ff63>>1,eae03bd[45]};wl8f690<=eae03bd[46];fn7b485<=eae03bd[47];vida42f<={zxec7a5>>1,eae03bd[48]};bld217a<=eae03bd[49];sj90bd6<=eae03bd[50];yz85eb4<=eae03bd[51];pu2f5a5<=eae03bd[52];mr7ad2a<=eae03bd[53];wjd6954<=eae03bd[54];irb4aa5<={gode5c1>>1,eae03bd[55]};rva552d<=eae03bd[56];ba2a96f<=eae03bd[57];ip54b7b<=eae03bd[58];xla5bdc<=eae03bd[59];vx2dee6<=eae03bd[60];end\r
-always@* begin shdc077[2047]<=sgmii_mode;shdc077[2046]<=signal_detect;shdc077[2044]<=debug_link_timer_short;shdc077[2040]<=force_isolate;shdc077[2032]<=force_loopback;shdc077[2016]<=force_unidir;shdc077[1985]<=operational_rate[0];shdc077[1925]<=the6c4f;shdc077[1922]<=rx_data[0];shdc077[1802]<=sj3627f;shdc077[1796]<=rx_kcntl;shdc077[1567]<=kdf2e08;shdc077[1556]<=sjb13fd;shdc077[1544]<=rx_even;shdc077[1505]<=mg1f9b1;shdc077[1415]<=cmdbcb8;shdc077[1324]<=rg63d2f;shdc077[1316]<=mg986ac;shdc077[1200]<=zkf4bdb;shdc077[1169]<=gq1ab0d;shdc077[1163]<=vif4422;shdc077[1118]<=lf84490;shdc077[1106]<=su531f3;shdc077[1087]<=aa97044;shdc077[1065]<=ng89fec;shdc077[1041]<=mr_an_enable;shdc077[1040]<=rx_disp_err;shdc077[1023]<=gbe_mode;shdc077[962]<=ldfcd89;shdc077[783]<=gode5c1[0];shdc077[752]<=mga3f36;shdc077[707]<=cmdb797;shdc077[662]<=zxec7a5[0];shdc077[658]<=ip7a61a;shdc077[600]<=ba1e97b;shdc077[584]<=kdc3561;shdc077[581]<=ieac34a;shdc077[559]<=aa10892;shdc077[553]<=hdaf6e1[0];shdc077[520]<=tx_er;shdc077[508]<=wl8810;shdc077[376]<=sj12436;shdc077[353]<=xla5edb;shdc077[331]<=czfd8f4;shdc077[329]<=vk2f4c3;shdc077[290]<=ned5869;shdc077[279]<=lsa2112;shdc077[276]<=kqf5edc[0];shdc077[260]<=tx_en;shdc077[254]<=wwc1102;shdc077[188]<=nt22486;shdc077[165]<=qt7fb1e;shdc077[164]<=psc5e98[0];shdc077[138]<=bl7b70e[0];shdc077[130]<=tx_d[0];shdc077[127]<=jeb8220;shdc077[82]<=ld4ff63[0];shdc077[69]<=mr_restart_an;shdc077[65]<=rx_err_decode_mode;shdc077[34]<=mr_main_reset;shdc077[32]<=rx_cv_err;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086<ba1de9; qtd3086=qtd3086+1) begin jebdcc5[qtd3086] = uk82f73[nec5698]; aa2b4c2 = ^(nec5698 & dm7315a[0]); nec5698 = {nec5698, aa2b4c2}; end end\r
-endmodule\r
+++ /dev/null
-=============================================================================
-Filelist generated by IPexpress 06/19/2012 09:57:30
-Filename: sgmii_gbe_pcs35_filelist.log
-Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-=============================================================================
-
------------------------------------------------------------------------------
-Basic IP Core Files
-Output Directory: /home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35
------------------------------------------------------------------------------
- sgmii_gbe_pcs35.lpc
- : IP ispLEVER LPC File
- sgmii_gbe_pcs35.ngo
- : IP ispLEVER Database File
- sgmii_gbe_pcs35_bb.v
- : IP Verilog Blackbox Module
- sgmii_gbe_pcs35_inst.v
- : IP Verilog Instantiation Template
- sgmii_gbe_pcs35_beh.v
- : IP Verilog Behaviorial Sim Model
- sgmii_gbe_pcs35_gen.log
- : IP Status Log
- sgmii_gbe_pcs35_generate.log
- : IP Generate Log
-
------------------------------------------------------------------------------
-Supplemental Evaluation Files:
------------------------------------------------------------------------------
-
----------------------------------:
- COMMON TO ALL CONFIGURATIONS :
----------------------------------:
-
- Hardware Specific Models
- ../sgmii_pcs_eval/models/ecp3/pcs_serdes
-
- Testbench
- ../sgmii_pcs_eval/testbench
-
-------------------------------------------------
- SPECIFIC TO sgmii_gbe_pcs35 CONFIGURATION
-------------------------------------------------
-
- Source Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs35/src/rtl/ecp3
-
- Simulation
- ../sgmii_pcs_eval/sgmii_gbe_pcs35/sim/modelsim
-
- FPGA Implementation Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs35/impl
-
+++ /dev/null
-Parameters loaded ok.
-No optional files required.
-Running parameter check.
-Parameter values ok.
-IP core generation completed ok.
-Simulation model successfully created.
-IP template generation completed ok.
-Eval Directory succussfully created.
-ModelSim do file successfully created.
-Generation completed ok.
+++ /dev/null
-Starting process: IPCFG
-
-GenerateCore within package Core_Generate 1.0.0 in file LatticeIP_generate.tcl
-Starting process: '"/opt/lattice/diamond/1.4.2.105/bin/lin/synpwrap" -rem -e sgmii_gbe_pcs35 -target lattice-ecp3'
-
-Warning: You are running on an unsupported platform
-End process: completed successfully.
-
-Starting process: '"/opt/lattice/diamond/1.4.2.105/bin/lin/../../ispfpga/bin/lin/edif2ngd" -ip "/home/greg/sgmii_gbepcs_v3.5/lib/../.." -ic sgmii_gbepcs_v3.5 -l LatticeECP3 -nopropwarn "syn_results/sgmii_gbe_pcs35.edi" "sgmii_gbe_pcs35.ngo"'
-edif2ngd: version Diamond_1.4_Production (87)
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
- Copyright (c) 1995 AT&T Corp. All rights reserved.
- Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
- Copyright (c) 2001 Agere Systems All rights reserved.
- Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-No device specified. Will use default.
-Writing the design to sgmii_gbe_pcs35.ngo...
-End process: completed successfully.
-
-=============================================================================
-Filelist generated by IPexpress 06/19/2012 09:57:30
-Filename: sgmii_gbe_pcs35_filelist.log
-Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-=============================================================================
------------------------------------------------------------------------------
-Basic IP Core Files
-Output Directory: /home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35
------------------------------------------------------------------------------
- sgmii_gbe_pcs35.lpc
- : IP ispLEVER LPC File
- sgmii_gbe_pcs35.ngo
- : IP ispLEVER Database File
- sgmii_gbe_pcs35_bb.v
- : IP Verilog Blackbox Module
- sgmii_gbe_pcs35_inst.v
- : IP Verilog Instantiation Template
- sgmii_gbe_pcs35_beh.v
- : IP Verilog Behaviorial Sim Model
- sgmii_gbe_pcs35_gen.log
- : IP Status Log
- sgmii_gbe_pcs35_generate.log
- : IP Generate Log
------------------------------------------------------------------------------
-Supplemental Evaluation Files:
------------------------------------------------------------------------------
-
----------------------------------:
- COMMON TO ALL CONFIGURATIONS :
----------------------------------:
-
- Hardware Specific Models
- ../sgmii_pcs_eval/models/ecp3/pcs_serdes
-
- Testbench
- ../sgmii_pcs_eval/testbench
-
-------------------------------------------------
- SPECIFIC TO sgmii_gbe_pcs35 CONFIGURATION
-------------------------------------------------
-
- Source Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs35/src/rtl/ecp3
-
- Simulation
- ../sgmii_pcs_eval/sgmii_gbe_pcs35/sim/modelsim
-
- FPGA Implementation Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs35/impl
-
-Total Warnings: 1
-
-
-Total Errors: 0
-
-
-
+++ /dev/null
-//=============================================================================
-// Verilog module generated by IPExpress 06/19/2012 09:57:30
-// Filename: sgmii_gbe_pcs35_inst.v
-// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-//=============================================================================
-
-/* WARNING - Changes to this file should be performed by re-running IPexpress
-or modifying the .LPC file and regenerating the core. Other changes may lead
-to inconsistent simulation and/or implemenation results */
-
-//---------------------------------------------------------------
-// sgmii_gbe_pcs35 module instantiation template
-//---------------------------------------------------------------
-
-
- \r
-\r
-sgmii_gbe_pcs35 sgmii_gbe_pcs35_U (\r
-\r
- // Control Interface\r
- .rst_n ( rst_n ) ,\r
- .signal_detect ( signal_detect ) ,\r
- .gbe_mode ( gbe_mode ) ,\r
- .sgmii_mode ( sgmii_mode ) ,\r
- .operational_rate ( operational_rate ) ,\r
- .debug_link_timer_short ( debug_link_timer_short ) ,\r
- .force_isolate ( force_isolate ) ,\r
- .force_loopback ( force_loopback ) ,\r
- .force_unidir ( force_unidir ) ,\r
-\r
- .rx_compensation_err ( rx_compensation_err ) ,\r
- .ctc_drop_flag ( ctc_drop_flag ) ,\r
- .ctc_add_flag ( ctc_add_flag ) ,\r
- .an_link_ok ( an_link_ok ) ,\r
-\r
- // (G)MII Interface\r
- .tx_clock_enable_sink ( tx_clock_enable_sink ),\r
- .tx_clock_enable_source ( tx_clock_enable_source ),\r
- .tx_clk_125 ( tx_clk_125 ) ,\r
- .tx_d ( tx_d ) ,\r
- .tx_en ( tx_en ) ,\r
- .tx_er ( tx_er ) ,\r
-\r
- .rx_clock_enable_sink ( rx_clock_enable_sink ),\r
- .rx_clock_enable_source ( rx_clock_enable_source ),\r
- .rx_clk_125 ( rx_clk_125 ) ,\r
- .rx_d ( rx_d ) ,\r
- .rx_dv ( rx_dv ) ,\r
- .rx_er ( rx_er ) ,\r
- .col ( col ) ,\r
- .crs ( crs ) ,\r
- \r
- // 8BI Interface\r
- .tx_data ( tx_data ) ,\r
- .tx_kcntl ( tx_kcntl ) ,\r
- .tx_disparity_cntl ( tx_disparity_cntl ) ,\r
- .xmit_autoneg ( xmit_autoneg ) ,\r
-\r
- .serdes_recovered_clk ( serdes_recovered_clk ) ,\r
- .rx_data ( rx_data ) ,\r
- .rx_kcntl ( rx_kcntl) ,\r
- .rx_even ( rx_even ) ,\r
- .rx_disp_err ( rx_disp_err ) ,\r
- .rx_cv_err ( rx_cv_err ) ,\r
- .rx_err_decode_mode ( rx_err_decode_mode ) ,\r
-\r
- // Management Interface\r
- .mr_adv_ability ( mr_adv_ability ),\r
- .mr_an_enable ( mr_an_enable ), \r
- .mr_main_reset ( mr_main_reset ), \r
- .mr_restart_an ( mr_restart_an ), \r
-\r
- .mr_an_complete ( mr_an_complete ), \r
- .mr_lp_adv_ability ( mr_lp_adv_ability ), \r
- .mr_page_rx ( mr_page_rx )\r
- );\r
- \r
-);\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="statts_mem" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 12 05 22:40:39.690" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="" type="mem" modified="2011 12 05 22:40:39.000"/>
- <File name="statts_mem.lpc" type="lpc" modified="2011 12 05 22:40:38.000"/>
- <File name="statts_mem.vhd" type="top_level_vhdl" modified="2011 12 05 22:40:38.000"/>
- <File name="statts_mem_tmpl.vhd" type="template_vhdl" modified="2011 12 05 22:40:38.000"/>
- <File name="tb_statts_mem_tmpl.vhd" type="testbench_vhdl" modified="2011 12 05 22:40:38.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE statts_mem DEFIN statts_mem.vhd
- SUBMODULE PDPW16KC
- INSTANCE statts_mem_0_0_0
- SUBMODULE VLO
- INSTANCE scuba_vlo_inst
- SUBMODULE VHI
- INSTANCE scuba_vhi_inst
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP
-CoreRevision=6.1
-ModuleName=statts_mem
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/05/2011
-Time=22:40:38
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-RAddress=1020
-RData=8
-WAddress=255
-WData=32
-enByte=0
-ByteSize=9
-adPipeline=0
-inPipeline=0
-outPipeline=0
-MOR=0
-InData=Registered
-AdControl=Registered
-MemFile=
-MemFormat=bin
-Reset=Sync
-GSR=Enabled
-Pad=0
-EnECC=0
-Optimization=Speed
-EnSleep=ENABLED
-Pipeline=0
-
-[FilesGenerated]
-=mem
+++ /dev/null
-WrAddress[7] i
-WrAddress[6] i
-WrAddress[5] i
-WrAddress[4] i
-WrAddress[3] i
-WrAddress[2] i
-WrAddress[1] i
-WrAddress[0] i
-RdAddress[9] i
-RdAddress[8] i
-RdAddress[7] i
-RdAddress[6] i
-RdAddress[5] i
-RdAddress[4] i
-RdAddress[3] i
-RdAddress[2] i
-RdAddress[1] i
-RdAddress[0] i
-Data[31] i
-Data[30] i
-Data[29] i
-Data[28] i
-Data[27] i
-Data[26] i
-Data[25] i
-Data[24] i
-Data[23] i
-Data[22] i
-Data[21] i
-Data[20] i
-Data[19] i
-Data[18] i
-Data[17] i
-Data[16] i
-Data[15] i
-Data[14] i
-Data[13] i
-Data[12] i
-Data[11] i
-Data[10] i
-Data[9] i
-Data[8] i
-Data[7] i
-Data[6] i
-Data[5] i
-Data[4] i
-Data[3] i
-Data[2] i
-Data[1] i
-Data[0] i
-WE i
-RdClock i
-RdClockEn i
-Reset i
-WrClock i
-WrClockEn i
-Q[7] o
-Q[6] o
-Q[5] o
-Q[4] o
-Q[3] o
-Q[2] o
-Q[1] o
-Q[0] o
+++ /dev/null
-statts_mem.vhd
+++ /dev/null
-SCUBA, Version Diamond_1.3_Production (92)
-Mon Dec 5 22:40:38 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n statts_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -device LFE3-150EA -type ramdps -raddr_width 10 -rwidth 8 -waddr_width 8 -wwidth 32 -rnum_words 1020 -wnum_words 255 -cascade -1 -e
- Circuit name : statts_mem
- Module type : RAM_DP
- Module Version : 6.1
- Ports :
- Inputs : WrAddress[7:0], RdAddress[9:0], Data[31:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
- Outputs : Q[7:0]
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : statts_mem.vhd
- VHDL template : statts_mem_tmpl.vhd
- VHDL testbench : tb_statts_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : statts_mem.srp
- Element Usage :
- PDPW16KC : 1
- Estimated Resource Usage:
- EBR : 1
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 6.1
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 8 -data_width 32 -num_rows 255 -cascade -1 -e
-
--- Mon Dec 5 22:40:38 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity statts_mem is
- port (
- WrAddress: in std_logic_vector(7 downto 0);
- RdAddress: in std_logic_vector(9 downto 0);
- Data: in std_logic_vector(31 downto 0);
- WE: in std_logic;
- RdClock: in std_logic;
- RdClockEn: in std_logic;
- Reset: in std_logic;
- WrClock: in std_logic;
- WrClockEn: in std_logic;
- Q: out std_logic_vector(7 downto 0));
-end statts_mem;
-
-architecture Structure of statts_mem is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of statts_mem_0_0_0 : label is "statts_mem.lpc";
- attribute MEM_INIT_FILE of statts_mem_0_0_0 : label is "";
- attribute RESETMODE of statts_mem_0_0_0 : label is "SYNC";
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- statts_mem_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>scuba_vlo, DI9=>Data(8), DI10=>Data(9), DI11=>Data(10),
- DI12=>Data(11), DI13=>Data(12), DI14=>Data(13),
- DI15=>Data(14), DI16=>Data(15), DI17=>scuba_vlo,
- DI18=>Data(16), DI19=>Data(17), DI20=>Data(18),
- DI21=>Data(19), DI22=>Data(20), DI23=>Data(21),
- DI24=>Data(22), DI25=>Data(23), DI26=>scuba_vlo,
- DI27=>Data(24), DI28=>Data(25), DI29=>Data(26),
- DI30=>Data(27), DI31=>Data(28), DI32=>Data(29),
- DI33=>Data(30), DI34=>Data(31), DI35=>scuba_vlo,
- ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
- ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
- ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>scuba_vlo,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>RdAddress(0),
- ADR4=>RdAddress(1), ADR5=>RdAddress(2), ADR6=>RdAddress(3),
- ADR7=>RdAddress(4), ADR8=>RdAddress(5), ADR9=>RdAddress(6),
- ADR10=>RdAddress(7), ADR11=>RdAddress(8),
- ADR12=>RdAddress(9), ADR13=>scuba_vlo, CER=>RdClockEn,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2),
- DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7),
- DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
- DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
- DO18=>open, DO19=>open, DO20=>open, DO21=>open, DO22=>open,
- DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open,
- DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open,
- DO33=>open, DO34=>open, DO35=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of statts_mem is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: Module
-
-Starting process:
-
-SCUBA, Version Diamond_1.3_Production (92)
-Mon Dec 5 22:40:38 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n statts_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -device LFE3-150EA -type ramdps -raddr_width 10 -rwidth 8 -waddr_width 8 -wwidth 32 -rnum_words 1020 -wnum_words 255 -cascade -1 -e
- Circuit name : statts_mem
- Module type : RAM_DP
- Module Version : 6.1
- Ports :
- Inputs : WrAddress[7:0], RdAddress[9:0], Data[31:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
- Outputs : Q[7:0]
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : statts_mem.vhd
- VHDL template : statts_mem_tmpl.vhd
- VHDL testbench : tb_statts_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : statts_mem.srp
- Estimated Resource Usage:
- EBR : 1
-
-END SCUBA Module Synthesis
-
-File: statts_mem.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 6.1
--- Mon Dec 5 22:40:38 2011
-
--- parameterized module component declaration
-component statts_mem
- port (WrAddress: in std_logic_vector(7 downto 0);
- RdAddress: in std_logic_vector(9 downto 0);
- Data: in std_logic_vector(31 downto 0); WE: in std_logic;
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; WrClock: in std_logic;
- WrClockEn: in std_logic; Q: out std_logic_vector(7 downto 0));
-end component;
-
--- parameterized module component instance
-__ : statts_mem
- port map (WrAddress(7 downto 0)=>__, RdAddress(9 downto 0)=>__, Data(31 downto 0)=>__,
- WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__,
- WrClockEn=>__, Q(7 downto 0)=>__);
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_1024x16x8
- port (Data : in std_logic_vector(17 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(17 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(8 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_1024x16x8
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 1027 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 1027 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 1027 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_2048x8
- port (Data : in std_logic_vector(7 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(7 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_2048x8
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 2051 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_2048x8x16
- port (Data : in std_logic_vector(8 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(17 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(8 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(17 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_2048x8x16
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 2051 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_32kx16x8_mb2
- port (Data : in std_logic_vector(17 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(8 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(17 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0');
- signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0');
- signal Q : std_logic_vector(8 downto 0);
- signal WCNT : std_logic_vector(15 downto 0);
- signal RCNT : std_logic_vector(16 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
- signal AlmostEmpty: std_logic;
- signal AlmostFull: std_logic;
-begin
- u1 : fifo_32kx16x8_mb2
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh,
- Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full,
- AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 32771 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_32kx16x8_mb
- port (Data : in std_logic_vector(15 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(7 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(15 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0');
- signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0');
- signal Q : std_logic_vector(7 downto 0);
- signal WCNT : std_logic_vector(15 downto 0);
- signal RCNT : std_logic_vector(16 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
- signal AlmostEmpty: std_logic;
- signal AlmostFull: std_logic;
-begin
- u1 : fifo_32kx16x8_mb
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh,
- Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full,
- AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 32771 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41)\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.std_logic_unsigned.all;\r
-\r
-entity tb is\r
-end entity tb;\r
-\r
-\r
-architecture test of tb is \r
-\r
- component fifo_32kx16x8\r
- port (Data : in std_logic_vector(15 downto 0); \r
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; \r
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; \r
- Q : out std_logic_vector(7 downto 0); \r
- WCNT : out std_logic_vector(15 downto 0); \r
- RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; \r
- Full: out std_logic\r
- );\r
- end component;\r
-\r
- signal Data : std_logic_vector(15 downto 0) := (others => '0');\r
- signal WrClock: std_logic := '0';\r
- signal RdClock: std_logic := '0';\r
- signal WrEn: std_logic := '0';\r
- signal RdEn: std_logic := '0';\r
- signal Reset: std_logic := '0';\r
- signal RPReset: std_logic := '0';\r
- signal Q : std_logic_vector(7 downto 0);\r
- signal WCNT : std_logic_vector(15 downto 0);\r
- signal RCNT : std_logic_vector(16 downto 0);\r
- signal Empty: std_logic;\r
- signal Full: std_logic;\r
-begin\r
- u1 : fifo_32kx16x8\r
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock, \r
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, \r
- Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full\r
- );\r
-\r
- process\r
-\r
- begin\r
- Data <= (others => '0') ;\r
- wait for 100 ns;\r
- wait until Reset = '0';\r
- for i in 0 to 32771 loop\r
- wait until WrClock'event and WrClock = '1';\r
- Data <= Data + '1' after 1 ns;\r
- end loop;\r
- wait;\r
- end process;\r
-\r
- WrClock <= not WrClock after 5.00 ns;\r
-\r
- RdClock <= not RdClock after 5.00 ns;\r
-\r
- process\r
-\r
- begin\r
- WrEn <= '0' ;\r
- wait for 100 ns;\r
- wait until Reset = '0';\r
- for i in 0 to 32771 loop\r
- wait until WrClock'event and WrClock = '1';\r
- WrEn <= '1' after 1 ns;\r
- end loop;\r
- WrEn <= '0' ;\r
- wait;\r
- end process;\r
-\r
- process\r
-\r
- begin\r
- RdEn <= '0' ;\r
- wait until Reset = '0';\r
- wait until WrEn = '1';\r
- wait until WrEn = '0';\r
- for i in 0 to 32771 loop\r
- wait until RdClock'event and RdClock = '1';\r
- RdEn <= '1' after 1 ns;\r
- end loop;\r
- RdEn <= '0' ;\r
- wait;\r
- end process;\r
-\r
- process\r
-\r
- begin\r
- Reset <= '1' ;\r
- wait for 100 ns;\r
- Reset <= '0' ;\r
- wait;\r
- end process;\r
-\r
- process\r
-\r
- begin\r
- RPReset <= '1' ;\r
- wait for 100 ns;\r
- RPReset <= '0' ;\r
- wait;\r
- end process;\r
-\r
-end architecture test;\r
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_4096x32
- port (Data : in std_logic_vector(31 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(31 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(31 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(31 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_4096x32
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 4099 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_4096x9
- port (Data : in std_logic_vector(8 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(8 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(8 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_4096x9
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 4099 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_512x32
- port (Data : in std_logic_vector(31 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(31 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(31 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(31 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_512x32
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 515 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_512x64
- port (Data : in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(71 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(71 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(71 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_512x64
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 515 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_512x72
- port (Data : in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(71 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(71 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(71 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_512x72
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 515 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_64kx8
- port (Data : in std_logic_vector(7 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(7 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_64kx8
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 65539 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_64kx9
- port (Data : in std_logic_vector(8 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(8 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(8 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_64kx9
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 65539 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component ip_mem
- port (DataInA : in std_logic_vector(31 downto 0);
- DataInB : in std_logic_vector(31 downto 0);
- AddressA : in std_logic_vector(7 downto 0);
- AddressB : in std_logic_vector(7 downto 0); ClockA: in std_logic;
- ClockB: in std_logic; ClockEnA: in std_logic;
- ClockEnB: in std_logic; WrA: in std_logic; WrB: in std_logic;
- ResetA: in std_logic; ResetB: in std_logic;
- QA : out std_logic_vector(31 downto 0);
- QB : out std_logic_vector(31 downto 0)
- );
- end component;
-
- signal DataInA : std_logic_vector(31 downto 0) := (others => '0');
- signal DataInB : std_logic_vector(31 downto 0) := (others => '0');
- signal AddressA : std_logic_vector(7 downto 0) := (others => '0');
- signal AddressB : std_logic_vector(7 downto 0) := (others => '0');
- signal ClockA: std_logic := '0';
- signal ClockB: std_logic := '0';
- signal ClockEnA: std_logic := '0';
- signal ClockEnB: std_logic := '0';
- signal WrA: std_logic := '0';
- signal WrB: std_logic := '0';
- signal ResetA: std_logic := '0';
- signal ResetB: std_logic := '0';
- signal QA : std_logic_vector(31 downto 0);
- signal QB : std_logic_vector(31 downto 0);
-begin
- u1 : ip_mem
- port map (DataInA => DataInA, DataInB => DataInB, AddressA => AddressA,
- AddressB => AddressB, ClockA => ClockA, ClockB => ClockB,
- ClockEnA => ClockEnA, ClockEnB => ClockEnB, WrA => WrA, WrB => WrB,
- ResetA => ResetA, ResetB => ResetB, QA => QA, QB => QB
- );
-
- process
-
- begin
- DataInA <= (others => '0') ;
- wait for 100 ns;
- wait until ResetA = '0';
- for i in 0 to 259 loop
- wait until ClockA'event and ClockA = '1';
- DataInA <= DataInA + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- DataInB <= (others => '0') ;
- wait for 100 ns;
- wait until ResetB = '0';
- wait until WrB = '1';
- for i in 0 to 259 loop
- wait until ClockB'event and ClockB = '1';
- DataInB <= DataInB + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- AddressA <= (others => '0') ;
- wait for 100 ns;
- wait until ResetA = '0';
- for i in 0 to 518 loop
- wait until ClockA'event and ClockA = '1';
- AddressA <= AddressA + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- AddressB <= (others => '0') ;
- wait for 100 ns;
- wait until ResetB = '0';
- wait until WrB = '1';
- for i in 0 to 518 loop
- wait until ClockB'event and ClockB = '1';
- AddressB <= AddressB + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- ClockA <= not ClockA after 5.00 ns;
-
- ClockB <= not ClockB after 5.00 ns;
-
- process
-
- begin
- ClockEnA <= '0' ;
- wait for 100 ns;
- wait until ResetA = '0';
- ClockEnA <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- ClockEnB <= '0' ;
- wait for 100 ns;
- wait until ResetB = '0';
- ClockEnB <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- WrA <= '0' ;
- wait until ResetA = '0';
- for i in 0 to 259 loop
- wait until ClockA'event and ClockA = '1';
- WrA <= '1' after 1 ns;
- end loop;
- WrA <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- WrB <= '0' ;
- wait until ResetB = '0';
- wait until WrA = '1';
- wait until WrA = '0';
- for i in 0 to 259 loop
- wait until ClockA'event and ClockA = '1';
- end loop;
- for i in 0 to 259 loop
- wait until ClockB'event and ClockB = '1';
- WrB <= '1' after 1 ns;
- end loop;
- WrB <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- ResetA <= '1' ;
- wait for 100 ns;
- ResetA <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- ResetB <= '1' ;
- wait for 100 ns;
- ResetB <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component mac_init_mem
- port (Address : in std_logic_vector(5 downto 0);
- OutClock: in std_logic; OutClockEn: in std_logic;
- Reset: in std_logic; Q : out std_logic_vector(7 downto 0)
- );
- end component;
-
- signal Address : std_logic_vector(5 downto 0) := (others => '0');
- signal OutClock: std_logic := '0';
- signal OutClockEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
-begin
- u1 : mac_init_mem
- port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn,
- Reset => Reset, Q => Q
- );
-
- process
-
- begin
- Address <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 57 loop
- wait until OutClock'event and OutClock = '1';
- Address <= Address + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- OutClock <= not OutClock after 5.00 ns;
-
- process
-
- begin
- OutClockEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- OutClockEn <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component statts_mem
- port (WrAddress : in std_logic_vector(7 downto 0);
- RdAddress : in std_logic_vector(9 downto 0);
- Data : in std_logic_vector(31 downto 0); WE: in std_logic;
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; WrClock: in std_logic;
- WrClockEn: in std_logic; Q : out std_logic_vector(7 downto 0)
- );
- end component;
-
- signal WrAddress : std_logic_vector(7 downto 0) := (others => '0');
- signal RdAddress : std_logic_vector(9 downto 0) := (others => '0');
- signal Data : std_logic_vector(31 downto 0) := (others => '0');
- signal WE: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal RdClockEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal WrClock: std_logic := '0';
- signal WrClockEn: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
-begin
- u1 : statts_mem
- port map (WrAddress => WrAddress, RdAddress => RdAddress, Data => Data,
- WE => WE, RdClock => RdClock, RdClockEn => RdClockEn, Reset => Reset,
- WrClock => WrClock, WrClockEn => WrClockEn, Q => Q
- );
-
- process
-
- begin
- WrAddress <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 516 loop
- wait until WrClock'event and WrClock = '1';
- WrAddress <= WrAddress + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- RdAddress <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 516 loop
- wait until RdClock'event and RdClock = '1';
- RdAddress <= RdAddress + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 258 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- WE <= '0' ;
- wait until Reset = '0';
- for i in 0 to 258 loop
- wait until WrClock'event and WrClock = '1';
- WE <= '1' after 1 ns;
- end loop;
- WE <= '0' ;
- wait;
- end process;
-
- RdClock <= not RdClock after 20.00 ns;
-
- process
-
- begin
- RdClockEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- RdClockEn <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- process
-
- begin
- WrClockEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- WrClockEn <= '1' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
-
-#!/usr/local/bin/wish
-
-set Para(cmd) ""
-if ![catch {set temp $argc} result] {
- if {$argc > 0} {
- for {set i 0} {$i < $argc} {incr i 2} {
- set temp [lindex $argv $i]
- set temp [string range $temp 1 end]
- lappend argv_list $temp
- lappend value_list [lindex $argv [expr $i+1]]
- }
- foreach argument $argv_list value $value_list {
- switch $argument {
- "cmd" {set Para(cmd) $value;}
- }
- }
- }
-}
-
-set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/tsmac3"
-set Para(ModuleName) "tsmac3"
-set Para(lib) "/home/greg/trispeed_mac_v3.4/lib"
-set Para(CoreName) "Tri-Speed Ethernet MAC"
-set Para(family) "latticeecp2m"
-set Para(Family) "ep5m00"
-set Para(design) "VHDL"
-
-lappend auto_path "/home/greg/trispeed_mac_v3.4/gui"
-
-lappend auto_path "/home/greg/trispeed_mac_v3.4/script"
-package require Core_Generate
-
-lappend auto_path "/opt/lattice/ispLEVER8.1/isptools/ispcpld/tcltk/lib/ipwidgets/ispipbuilder/../runproc"
-package require runcmd
-
-set Para(install_dir) "/opt/lattice/ispLEVER8.1/isptools/ispcpld/tcltk/lib/ipwidgets/ispipbuilder/../../../../.."
-
-set Para(result) [GenerateCore]
+++ /dev/null
-#define USER_NAME tsmac3
-#define SGMII_TSMAC
-#define DEVICE_ECP2M
-#define DEVICE_ECP2_ECP2M
+++ /dev/null
-[Device]
-Family=ep5m00
-PartType=LFE2M100E
-PartName=LFE2M100E-6F900C
-SpeedGrade=-6
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=IPCFG
-CoreStatus=Demo
-CoreName=Tri-Speed Ethernet MAC
-CoreRevision=3.4
-ModuleName=tsmac3
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=06/17/2011
-Time=11:30:22
-
-[Parameters]
-MIIM=No
-MODE=SGMII easy connect
-SYNP_TOOL=1
-PREC_TOOL=0
-MODS_TOOL=1
-ALDC_TOOL=0
-MULT_WB=NO
-LOOPBACK=NO
-STAT_REGS=NO
-
-[Files]
-Synthesis=
-Simulation=
-Logical=
-Physical=
-Misc=
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress \r
-// Filename: USERNAME.v \r
-// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
-module tsmac3 (\r
- // clock and reset\r
- hclk,\r
- txmac_clk,\r
- rxmac_clk,\r
- reset_n,\r
- txmac_clk_en,\r
- rxmac_clk_en,\r
-\r
- // Input signals to the GMII\r
- rxd,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
- // Input signals to the CPU Interface\r
- haddr,\r
- hdatain,\r
- hcs_n,\r
- hwrite_n,\r
- hread_n,\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- tx_fifodata,\r
- tx_fifoavail,\r
- tx_fifoeof,\r
- tx_fifoempty,\r
- tx_sndpaustim,\r
- tx_sndpausreq,\r
- tx_fifoctrl,\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- rx_fifo_full,\r
- ignore_pkt,\r
- \r
- // Output signals from the GMII\r
- txd,\r
- tx_en,\r
- tx_er,\r
- \r
- // Output signals from the CPU Interface\r
- hdataout,\r
- hdataout_en_n,\r
- hready_n,\r
- cpu_if_gbit_en,\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- tx_macread,\r
- tx_discfrm,\r
- tx_staten,\r
- tx_statvec,\r
- tx_done,\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
- );\r
- \r
- // ------------------------- clock and reset inputs ---------------------\r
- input hclk; // clock to the CPU I/F\r
- input txmac_clk; // clock to the Tx MAC\r
- input rxmac_clk; // clock to the RX MAC\r
- input reset_n; // Global reset\r
- input txmac_clk_en; // clock enable to the Tx MAC\r
- input rxmac_clk_en; // clock enable to the RX MAC\r
- \r
- // ----------------------- Input signals to the GMII -------------------\r
- input [7:0] rxd; // Receive data\r
- input rx_dv; // Receive data valid\r
- input rx_er; // Receive data error\r
- input col; // Collision detect\r
- input crs; // Carrier Sense\r
- // -------------------- Input signals to the CPU I/F -------------------\r
- input [7:0] haddr; // Address Bus\r
- input [7:0] hdatain; // Input data Bus\r
- input hcs_n; // Chip select\r
- input hwrite_n; // Register write\r
- input hread_n; // Register read\r
- \r
- // -------------------- Input signals to the MII I/F -------------------\r
-\r
- \r
- // ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
- input [7:0] tx_fifodata; // Data Input from FIFO\r
- input tx_fifoavail; // Data Available in FIFO\r
- input tx_fifoeof; // End of Frame\r
- input tx_fifoempty; // FIFO Empty\r
- input [15:0] tx_sndpaustim; // Pause frame parameter\r
- input tx_sndpausreq; // Transmit PAUSE frame\r
- input tx_fifoctrl; // Control frame or Not\r
- \r
- // ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
- input rx_fifo_full; // Receive FIFO Full\r
- input ignore_pkt; // Ignore the frame\r
- \r
- // -------------------- Output signals from the GMII -----------------------\r
- output [7:0] txd; // Transmit data\r
- output tx_en; // Transmit Enable\r
- output tx_er; // Transmit Error\r
- \r
- // -------------------- Output signals from the CPU I/F -------------------\r
- output [7:0] hdataout; // Output data Bus\r
- output hdataout_en_n; // Data Out Enable\r
- output hready_n; // Ready signal\r
- output cpu_if_gbit_en; // Gig or 10/100 mode\r
- \r
- // -------------------- Output signals from the MII I/F -------------------\r
-\r
- \r
- // ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
- output tx_macread; // Read FIFO\r
- output tx_discfrm; // Discard Frame\r
- output tx_staten; // Status Vector Valid\r
- output tx_done; // Transmit of Frame done\r
- output [30:0] tx_statvec; // Tx Status Vector\r
- \r
- // ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
- output rx_fifo_error; // FIFO full detected\r
- output [31:0] rx_stat_vector; // Rx Status Vector\r
- output [7:0] rx_dbout; // Data Output to FIFO\r
- output rx_write; // Write FIFO\r
- output rx_stat_en; // Status Vector Valid\r
- output rx_eof; // Entire frame written\r
- output rx_error; // Erroneous frame\r
- \r
- tsmac_core U1_LSC_ts_mac_core ( \r
-\r
- // clock and reset\r
- .hclk(hclk),\r
- .txmac_clk(txmac_clk),\r
- .rxmac_clk(rxmac_clk),\r
- .reset_n(reset_n),\r
- .txmac_clk_en(txmac_clk_en),\r
- .rxmac_clk_en(rxmac_clk_en),\r
- \r
- // Input signals to the GMII\r
- .rxd(rxd),\r
- .rx_dv(rx_dv),\r
- .rx_er(rx_er),\r
- .col(col),\r
- .crs(crs),\r
- // Input signals to the CPU Interface\r
- .haddr(haddr),\r
- .hdatain(hdatain),\r
- .hcs_n(hcs_n),\r
- .hwrite_n(hwrite_n),\r
- .hread_n(hread_n),\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- .tx_fifodata(tx_fifodata),\r
- .tx_fifoavail(tx_fifoavail),\r
- .tx_fifoeof(tx_fifoeof),\r
- .tx_fifoempty(tx_fifoempty),\r
- .tx_sndpaustim(tx_sndpaustim),\r
- .tx_sndpausreq(tx_sndpausreq),\r
- .tx_fifoctrl(tx_fifoctrl),\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- .rx_fifo_full(rx_fifo_full),\r
- .ignore_pkt(ignore_pkt),\r
- \r
- // Output signals from the GMII\r
- .txd(txd),\r
- .tx_en(tx_en),\r
- .tx_er(tx_er),\r
- \r
- // Output signals from the CPU Interface\r
- .hdataout(hdataout),\r
- .hdataout_en_n(hdataout_en_n),\r
- .hready_n(hready_n),\r
- .cpu_if_gbit_en(cpu_if_gbit_en),\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- .tx_macread(tx_macread),\r
- .tx_discfrm(tx_discfrm),\r
- .tx_staten(tx_staten),\r
- .tx_statvec(tx_statvec),\r
- .tx_done(tx_done),\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- .rx_fifo_error(rx_fifo_error),\r
- .rx_stat_vector(rx_stat_vector),\r
- .rx_dbout(rx_dbout),\r
- .rx_write(rx_write),\r
- .rx_stat_en(rx_stat_en),\r
- .rx_eof(rx_eof),\r
- .rx_error(rx_error)\r
- );\r
-endmodule\r
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress \r
-// Filename: USERNAME_bb.v \r
-// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
-module tsmac3 (\r
- // clock and reset\r
- hclk,\r
- txmac_clk,\r
- rxmac_clk,\r
- reset_n,\r
- txmac_clk_en,\r
- rxmac_clk_en,\r
-\r
- // Input signals to the GMII\r
- rxd,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
- \r
- // Input signals to the CPU Interface\r
- haddr,\r
- hdatain,\r
- hcs_n,\r
- hwrite_n,\r
- hread_n,\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- tx_fifodata,\r
- tx_fifoavail,\r
- tx_fifoeof,\r
- tx_fifoempty,\r
- tx_sndpaustim,\r
- tx_sndpausreq,\r
- tx_fifoctrl,\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- rx_fifo_full,\r
- ignore_pkt,\r
- \r
- // Output signals from the GMII\r
- txd,\r
- tx_en,\r
- tx_er,\r
- \r
- // Output signals from the CPU Interface\r
- hdataout,\r
- hdataout_en_n,\r
- hready_n,\r
- cpu_if_gbit_en,\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- tx_macread,\r
- tx_discfrm,\r
- tx_staten,\r
- tx_statvec,\r
- tx_done,\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
- );\r
- \r
- // ------------------------- clock and reset inputs ---------------------\r
- input hclk; // clock to the CPU I/F\r
- input txmac_clk; // clock to the Tx MAC\r
- input rxmac_clk; // clock to the RX MAC\r
- input reset_n; // Global reset\r
- input txmac_clk_en; // clock enable to the Tx MAC\r
- input rxmac_clk_en; // clock enable to the RX MAC\r
- \r
- // ----------------------- Input signals to the GMII -------------------\r
- input [7:0] rxd; // Receive data\r
- input rx_dv; // Receive data valid\r
- input rx_er; // Receive data error\r
- input col; // Collision detect\r
- input crs; // Carrier Sense\r
- // -------------------- Input signals to the CPU I/F -------------------\r
- input [7:0] haddr; // Address Bus\r
- input [7:0] hdatain; // Input data Bus\r
- input hcs_n; // Chip select\r
- input hwrite_n; // Register write\r
- input hread_n; // Register read\r
- \r
- // -------------------- Input signals to the MII I/F -------------------\r
-\r
- \r
- // ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
- input [7:0] tx_fifodata; // Data Input from FIFO\r
- input tx_fifoavail; // Data Available in FIFO\r
- input tx_fifoeof; // End of Frame\r
- input tx_fifoempty; // FIFO Empty\r
- input [15:0] tx_sndpaustim; // Pause frame parameter\r
- input tx_sndpausreq; // Transmit PAUSE frame\r
- input tx_fifoctrl; // Control frame or Not\r
- \r
- // ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
- input rx_fifo_full; // Receive FIFO Full\r
- input ignore_pkt; // Ignore the frame\r
- \r
- // -------------------- Output signals from the GMII -----------------------\r
- output [7:0] txd; // Transmit data\r
- output tx_en; // Transmit Enable\r
- output tx_er; // Transmit Error\r
- \r
- // -------------------- Output signals from the CPU I/F -------------------\r
- output [7:0] hdataout; // Output data Bus\r
- output hdataout_en_n; // Data Out Enable\r
- output hready_n; // Ready signal\r
- output cpu_if_gbit_en; // Gig or 10/100 mode\r
- \r
- // -------------------- Output signals from the MII I/F -------------------\r
-\r
- \r
- // ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
- output tx_macread; // Read FIFO\r
- output tx_discfrm; // Discard Frame\r
- output tx_staten; // Status Vector Valid\r
- output tx_done; // Transmit of Frame done\r
- output [30:0] tx_statvec; // Tx Status Vector\r
- \r
- // ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
- output rx_fifo_error; // FIFO full detected\r
- output [31:0] rx_stat_vector; // Rx Status Vector\r
- output [7:0] rx_dbout; // Data Output to FIFO\r
- output rx_write; // Write FIFO\r
- output rx_stat_en; // Status Vector Valid\r
- output rx_eof; // Entire frame written\r
- output rx_error; // Erroneous frame\r
- \r
-endmodule\r
+++ /dev/null
-// ts_mac_core_beh.v generated by Lattice IP Model Creator version 1\r
-// created on Wed Mar 23 11:57:00 CST 2011\r
-// Copyright(c) 2007~2011 Lattice Semiconductor Corporation. All rights reserved\r
-// obfuscator_exe version 1.mar0807\r
-\r
-// top\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module hd2df10 (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en, \r
- \r
- \r
- ks10d54, \r
- ls86aa0, \r
- \r
- \r
- ls35502,\r
- lfaa812,\r
- \r
- \r
- kd54097,\r
- rva04bd,\r
- cb25ef,\r
- wl12f7d\r
-);\r
-parameter gq97bed = 8;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input ks10d54;\r
-input ls35502;\r
-input lfaa812;\r
-input [gq97bed-1:0] ls86aa0;\r
-output rva04bd;\r
-output cb25ef;\r
-output wl12f7d;\r
-output [gq97bed-1:0] kd54097;\r
-reg rva04bd;\r
-reg cb25ef;\r
-reg wl12f7d;\r
-reg [gq97bed-1:0] kd54097;\r
-reg wl95504;\r
-parameter jraa825 = 2;\r
-parameter uv5412f = 2'b01;\r
-parameter tja097d = 2'b10;\r
-parameter ng4bee = 0;\r
-parameter fc25f73 = 1;\r
-parameter fc2fb9a = 8'hd5;\r
-parameter me7dcd3 = 8'h55;\r
-wire zkee699;\r
-wire ne734ca;\r
-reg ep9a653;\r
-reg uvd329c;\r
-reg ng994e4;\r
-reg [jraa825-1:0] os5391b;\r
-reg [2:0] vk9c8d9;\r
-reg [jraa825-1:0] oh23653;\r
-reg zm1b29c;\r
-reg [gq97bed - 1 : 0] neca715;\r
-reg ic538ab;\r
-reg zm9c559;\r
-reg kde2acb;\r
-reg wy1565d;\r
-reg irab2e9;\r
-reg go5974c;\r
-reg mecba61;\r
-reg xw5d308;\r
-reg [jraa825 - 1 : 0] go4c21e;\r
-reg [2 : 0] dz610f0;\r
-reg [jraa825 - 1 : 0] ic43c3c;\r
-reg [2047:0] ng1e1e0;\r
-wire [12:0] mef0f02;\r
-\r
-localparam uk87811 = 13,gd3c088 = 32'hfdfff40b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
- \r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin kd54097 <= 0; end else if (rxmac_clk_en) begin if (zm1b29c) begin kd54097 <= neca715; end end\r
-end\r
-\r
-\r
-\r
-\r
-assign zkee699 = neca715[7:0] == fc2fb9a;\r
-assign ne734ca = neca715[7:0] == me7dcd3;\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin oh23653 <= uv5412f; vk9c8d9 <= 3'b0; rva04bd <= 1'b0; wl12f7d <= 1'b0; wl95504 <= 1'b0; cb25ef <= 1'b0; end else if (rxmac_clk_en) begin oh23653 <= go4c21e; wl95504 <= go5974c; cb25ef <= kde2acb; rva04bd <= 1'b0; \r
- vk9c8d9 <= xw5d308 ? 3'h1 : (|dz610f0) ? (dz610f0+3'h1) : ic43c3c[ng4bee] ? 3'h0 : dz610f0;\r
- if (mecba61) begin wl12f7d <= 1'b1; end else if (zm9c559) begin wl12f7d <= 1'b0; end else if (ic538ab) begin wl12f7d <= 1'b0; end end\r
-end\r
-\r
-\r
-always @(ic43c3c or ic538ab or irab2e9 or wy1565d or dz610f0) begin case(ic43c3c) uv5412f : begin if (ic538ab && wy1565d) begin os5391b = uv5412f; ep9a653 = 1'b1; uvd329c = 1'b0; ng994e4 = 1'b0; end else if (ic538ab && irab2e9) begin os5391b = tja097d; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b1; end else if (ic538ab && !wy1565d && !irab2e9) begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b1; ng994e4 = 1'b0; end\r
- else begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b0; end end\r
- tja097d : begin if (wy1565d) begin os5391b = uv5412f; ep9a653 = 1'b1; uvd329c = 1'b0; ng994e4 = 1'b0; end else if (~|dz610f0 & ~irab2e9) begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b1; ng994e4 = 1'b0; end else begin os5391b = tja097d; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b0; end\r
- end\r
- default : begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b0; end endcase\r
-end\r
-\r
-always@* begin zm1b29c<=mef0f02[0];neca715<={ls86aa0>>1,mef0f02[1]};ic538ab<=mef0f02[2];zm9c559<=mef0f02[3];kde2acb<=mef0f02[4];wy1565d<=mef0f02[5];irab2e9<=mef0f02[6];go5974c<=mef0f02[7];mecba61<=mef0f02[8];xw5d308<=mef0f02[9];go4c21e<={os5391b>>1,mef0f02[10]};dz610f0<={vk9c8d9>>1,mef0f02[11]};ic43c3c<={oh23653>>1,mef0f02[12]};end\r
-always@* begin ng1e1e0[2047]<=ls86aa0[0];ng1e1e0[2046]<=ls35502;ng1e1e0[2044]<=lfaa812;ng1e1e0[2040]<=wl95504;ng1e1e0[2032]<=zkee699;ng1e1e0[2016]<=ne734ca;ng1e1e0[1984]<=ep9a653;ng1e1e0[1920]<=uvd329c;ng1e1e0[1793]<=ng994e4;ng1e1e0[1539]<=os5391b[0];ng1e1e0[1030]<=vk9c8d9[0];ng1e1e0[1023]<=ks10d54;ng1e1e0[13]<=oh23653[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module xl8b21c (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- bn1ce70,\r
- cb25ef,\r
-\r
- \r
- lfaa812,\r
- ykce1a5,\r
-\r
- \r
- uv70d29,\r
- hq8694d,\r
- ec34a6a,\r
- lfa5351,\r
- gd29a8f,\r
- rg4d47c,\r
- mr6a3e2,\r
- of51f14,\r
- sj8f8a4,\r
- tu7c524,\r
- ale2922,\r
- vk14915,\r
-\r
- \r
- wla48aa,\r
-\r
- \r
- ks24554,\r
- zz22aa1,\r
- mg1550f,\r
- hdaa879,\r
- en543cf,\r
- uxa1e7d,\r
- ukf3ec\r
-);\r
-parameter gq97bed = 8;\r
-parameter hocfb0b = 48;\r
-parameter ic7d85a = 6;\r
-parameter vvec2d1 = 8;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input cb25ef;\r
-input lfaa812;\r
-input ykce1a5;\r
-input [gq97bed-1:0] bn1ce70;\r
-input [vvec2d1-1:0] uv70d29;\r
-input [vvec2d1-1:0] hq8694d;\r
-input [vvec2d1-1:0] ec34a6a;\r
-input [vvec2d1-1:0] lfa5351;\r
-input [vvec2d1-1:0] gd29a8f;\r
-input [vvec2d1-1:0] rg4d47c;\r
-input [vvec2d1-1:0] mr6a3e2;\r
-input [vvec2d1-1:0] of51f14;\r
-input [hocfb0b-1:0] sj8f8a4;\r
-input tu7c524;\r
-input ale2922;\r
-input vk14915;\r
-input [ic7d85a-1:0] wla48aa;\r
-output zz22aa1;\r
-output mg1550f;\r
-output hdaa879;\r
-output en543cf;\r
-output uxa1e7d;\r
-output ukf3ec;\r
-output ks24554;\r
-reg en543cf;\r
-reg uxa1e7d;\r
-reg ukf3ec;\r
-reg zz22aa1;\r
-localparam zx5f6d5 = 11;\r
-localparam fafb6ae = 11'b00000000001;\r
-localparam uidb573 = 11'b00000000010;\r
-localparam rgdab98 = 11'b00000000100;\r
-localparam xwd5cc3 = 11'b00000001000;\r
-localparam mtae61a = 11'b00000010000;\r
-localparam ne730d4 = 11'b00000100000;\r
-localparam co986a3 = 11'b00001000000;\r
-localparam ipc3519 = 11'b00010000000;\r
-localparam qi1a8cd = 11'b00100000000;\r
-localparam osd4669 = 11'b01000000000;\r
-localparam uka3349 = 11'b10000000000;\r
-localparam ng4bee = 0;\r
-localparam fc25f73 = 1;\r
-localparam lq69236 = 2;\r
-localparam ic491b3 = 3;\r
-localparam rg48d98 = 4;\r
-localparam os46cc3 = 5;\r
-localparam kf36618 = 6;\r
-localparam ecb30c5 = 7;\r
-localparam ie98629 = 8;\r
-localparam enc3149 = 9;\r
-localparam mt18a4d = 10;\r
-wire fac526c;\r
-wire qv29362;\r
-wire ww49b15;\r
-wire dm4d8a9;\r
-wire ho6c54b;\r
-wire cm62a5b;\r
-reg ks152d9;\r
-reg oua96c9;\r
-reg [zx5f6d5-1:0] wj5b24d;\r
-reg [zx5f6d5-1:0] enc9365;\r
-wire kq49b2c;\r
-wire lq4d961;\r
-wire tu6cb0b;\r
-wire sh6585a;\r
-wire gd2c2d4;\r
-wire xj616a5;\r
-reg xyb52f;\r
-reg nr5a97b;\r
-reg [zx5f6d5-1:0] jra5ef8;\r
-reg [zx5f6d5-1:0] hb7be32;\r
-wire hodf196;\r
-reg shf8cb2;\r
-reg [vvec2d1-1:0] bn32cad;\r
-reg hq9656e;\r
-reg ngb2b72;\r
-wire an95b92;\r
-reg jeadc94;\r
-reg rt6e4a2;\r
-reg [zx5f6d5-1:0] co928b1;\r
-reg [zx5f6d5-1:0] baa2c4f;\r
-wire fp1627b;\r
-wire yzb13de;\r
-wire je89ef4;\r
-reg fn4f7a3;\r
-reg zx7bd1f;\r
-reg uide8fe;\r
-reg vif47f1;\r
-reg ksa3f8a;\r
-reg wy1fc51;\r
-reg lqfe289;\r
-reg rgf144b;\r
-reg ks24554;\r
-reg [gq97bed - 1 : 0] je896ad;\r
-reg al4b56a;\r
-reg zm9c559;\r
-reg byd5aaf;\r
-reg [vvec2d1 - 1 : 0] gb6abd3;\r
-reg [vvec2d1 - 1 : 0] ntaf4ee;\r
-reg [vvec2d1 - 1 : 0] czd3bb5;\r
-reg [vvec2d1 - 1 : 0] dmeed68;\r
-reg [vvec2d1 - 1 : 0] dbb5a1a;\r
-reg [vvec2d1 - 1 : 0] go686bb;\r
-reg [vvec2d1 - 1 : 0] ie1aec9;\r
-reg [vvec2d1 - 1 : 0] yzbb24e;\r
-reg [hocfb0b - 1 : 0] gbc93ad;\r
-reg ay49d6c;\r
-reg kd4eb61;\r
-reg ip75b0c;\r
-reg [ic7d85a - 1 : 0] lq6c32a;\r
-reg ld61953;\r
-reg dbca9e;\r
-reg ip654f7;\r
-reg hq2a7bd;\r
-reg yk53dea;\r
-reg zz9ef51;\r
-reg kdf7a8f;\r
-reg babd47c;\r
-reg [zx5f6d5 - 1 : 0] yx51f10;\r
-reg [zx5f6d5 - 1 : 0] jc7c424;\r
-reg yxe2122;\r
-reg aa10914;\r
-reg lf848a0;\r
-reg ou24507;\r
-reg fp22839;\r
-reg je141cf;\r
-reg jra0e7b;\r
-reg mt73de;\r
-reg [zx5f6d5 - 1 : 0] rgcf7ad;\r
-reg [zx5f6d5 - 1 : 0] icdeb5e;\r
-reg cmf5af1;\r
-reg twad789;\r
-reg [vvec2d1 - 1 : 0] cz5e25f;\r
-reg dmf12fc;\r
-reg xy897e2;\r
-reg ip4bf12;\r
-reg th5f894;\r
-reg pffc4a7;\r
-reg [zx5f6d5 - 1 : 0] wl129f4;\r
-reg [zx5f6d5 - 1 : 0] doa7d2e;\r
-reg sw3e973;\r
-reg rgf4b98;\r
-reg lfa5cc3;\r
-reg aa2e61e;\r
-reg vi730f0;\r
-reg ou98783;\r
-reg alc3c19;\r
-reg ba1e0cc;\r
-reg uif0662;\r
-reg do83310;\r
-reg fp19883;\r
-reg [2047:0] ng1e1e0;\r
-wire [57:0] mef0f02;\r
-\r
-localparam uk87811 = 58,gd3c088 = 32'hfdffc68b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-assign fp1627b = (jc7c424[os46cc3] | jc7c424[mt18a4d]) & (ip75b0c | kdf7a8f | jra0e7b | (kd4eb61 & th5f894));\r
-assign je89ef4 = (jc7c424[os46cc3] | jc7c424[mt18a4d]) & ~sw3e973;\r
-assign yzb13de = aa2e61e & ~(vi730f0 | (xy897e2 & ay49d6c & twad789));\r
-\r
-assign mg1550f = ba1e0cc | alc3c19;\r
-\r
-assign hdaa879 = uif0662 | ou98783;\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin vif47f1 <= 1'b0; ksa3f8a <= 1'b0; wy1fc51 <= 1'b0; lqfe289 <= 1'b0; rgf144b <= 1'b0; enc9365 <= fafb6ae; hb7be32 <= fafb6ae; baa2c4f <= fafb6ae; zz22aa1 <= 1'b0; zx7bd1f <= 1'b0; ukf3ec <= 1'b0; en543cf <= 1'b0; uxa1e7d <= 1'b0; hq9656e <= 1'b0; ngb2b72 <= 1'b0; fn4f7a3 <= 1'b0; uide8fe <= 1'b0; end else if (rxmac_clk_en) begin rgf144b <= byd5aaf; vif47f1 <= (xy897e2 & ay49d6c & twad789); ksa3f8a <= vi730f0; wy1fc51 <= rgf4b98; lqfe289 <= al4b56a; if(fp19883) begin enc9365 <= fafb6ae; hb7be32 <= fafb6ae; baa2c4f <= fafb6ae; end else begin enc9365 <= yx51f10; hb7be32 <= rgcf7ad; baa2c4f <= wl129f4; end zx7bd1f <= sw3e973; fn4f7a3 <= lfa5cc3; ngb2b72 <= cmf5af1; if (al4b56a) hq9656e <= je896ad[0]; if (kdf7a8f) zz22aa1 <= kdf7a8f; else if (zm9c559) zz22aa1 <= kdf7a8f; else zz22aa1 <= zz22aa1; if (jra0e7b) ukf3ec <= jra0e7b; else if (zm9c559) ukf3ec <= jra0e7b; else ukf3ec <= ukf3ec; if (rgf4b98 | zm9c559) uide8fe <= rgf4b98; else if (al4b56a) uide8fe <= 1'b0; else uide8fe <= ou98783; if (cmf5af1) en543cf <= (cmf5af1); else if (zm9c559) en543cf <= cmf5af1; else if (al4b56a) en543cf <= 1'b0; else en543cf <= en543cf; if (th5f894) uxa1e7d <= th5f894; else if (zm9c559) uxa1e7d <= th5f894; else if (do83310) uxa1e7d <= 1'b0; else uxa1e7d <= uxa1e7d; end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-assign cm62a5b = gbc93ad[47:40] == je896ad;\r
-\r
-assign ho6c54b = gbc93ad[39:32] == je896ad;\r
-\r
-assign dm4d8a9 = gbc93ad[31:24] == je896ad;\r
-\r
-assign ww49b15 = gbc93ad[23:16] == je896ad;\r
-\r
-assign qv29362 = gbc93ad[15:8] == je896ad;\r
-\r
-assign fac526c = gbc93ad[7:0] == je896ad;\r
-\r
-\r
-always @(jc7c424 or al4b56a or ld61953 or dbca9e or ip654f7 or hq2a7bd or yk53dea or zz9ef51) begin ks24554 = 1'b1; case(jc7c424) fafb6ae : begin if (!al4b56a) begin wj5b24d = fafb6ae; ks152d9 = 1'b0; oua96c9 = 1'b0; ks24554 = 1'b0; end else if (al4b56a) begin if (zz9ef51) begin wj5b24d = uidb573; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = co986a3; ks152d9 = 1'b0; oua96c9 = 1'b0; end end end uidb573 : begin if (yk53dea) begin wj5b24d = rgdab98; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = ipc3519; ks152d9 = 1'b0; oua96c9 = 1'b0; end end rgdab98 : begin if (hq2a7bd) begin wj5b24d = xwd5cc3; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = qi1a8cd; ks152d9 = 1'b0; oua96c9 = 1'b0; end end xwd5cc3 : begin if (ip654f7) begin wj5b24d = mtae61a; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = osd4669; ks152d9 = 1'b0; oua96c9 = 1'b0; end end mtae61a : begin if (dbca9e) begin wj5b24d = ne730d4; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = uka3349; ks152d9 = 1'b0; oua96c9 = 1'b0; end end ne730d4 : begin if (ld61953) begin wj5b24d = fafb6ae; ks152d9 = 1'b1; oua96c9 = 1'b0; end else begin wj5b24d = fafb6ae; ks152d9 = 1'b0; oua96c9 = 1'b1; end end co986a3 : begin wj5b24d = ipc3519; ks152d9 = 1'b0; oua96c9 = 1'b0; end ipc3519 : begin wj5b24d = qi1a8cd; ks152d9 = 1'b0; oua96c9 = 1'b0; end qi1a8cd : begin wj5b24d = osd4669; ks152d9 = 1'b0; oua96c9 = 1'b0; end osd4669 : begin wj5b24d = uka3349; ks152d9 = 1'b0; oua96c9 = 1'b0; end uka3349 : begin wj5b24d = fafb6ae; ks152d9 = 1'b0; oua96c9 = 1'b1; end default : begin wj5b24d = fafb6ae; ks152d9 = 1'b0; oua96c9 = 1'b0; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign xj616a5 = 8'h01 == je896ad;\r
-\r
-assign gd2c2d4 = 8'h80 == je896ad;\r
-\r
-assign sh6585a = 8'hc2 == je896ad;\r
-\r
-assign tu6cb0b = 8'h00 == je896ad;\r
-\r
-assign lq4d961 = 8'h00 == je896ad;\r
-\r
-assign kq49b2c = 8'h01 == je896ad;\r
-\r
-\r
-always @(icdeb5e or al4b56a or yxe2122 or aa10914 or lf848a0 or ou24507 or fp22839 or je141cf) begin case(icdeb5e) fafb6ae : begin if (!al4b56a) begin jra5ef8 = fafb6ae; xyb52f = 1'b0; nr5a97b = 1'b0; end else if (al4b56a) begin if (je141cf) begin jra5ef8 = uidb573; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = co986a3; xyb52f = 1'b0; nr5a97b = 1'b0; end end end uidb573 : begin if (fp22839) begin jra5ef8 = rgdab98; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = ipc3519; xyb52f = 1'b0; nr5a97b = 1'b0; end end rgdab98 : begin if (ou24507) begin jra5ef8 = xwd5cc3; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = qi1a8cd; xyb52f = 1'b0; nr5a97b = 1'b0; end end xwd5cc3 : begin if (lf848a0) begin jra5ef8 = mtae61a; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = osd4669; xyb52f = 1'b0; nr5a97b = 1'b0; end end mtae61a : begin if (aa10914) begin jra5ef8 = ne730d4; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = uka3349; xyb52f = 1'b0; nr5a97b = 1'b0; end end ne730d4 : begin if (yxe2122) begin jra5ef8 = fafb6ae; xyb52f = 1'b1; nr5a97b = 1'b0; end else begin jra5ef8 = fafb6ae; xyb52f = 1'b0; nr5a97b = 1'b1; end end co986a3 : begin jra5ef8 = ipc3519; xyb52f = 1'b0; nr5a97b = 1'b0; end ipc3519 : begin jra5ef8 = qi1a8cd; xyb52f = 1'b0; nr5a97b = 1'b0; end qi1a8cd : begin jra5ef8 = osd4669; xyb52f = 1'b0; nr5a97b = 1'b0; end osd4669 : begin jra5ef8 = uka3349; xyb52f = 1'b0; nr5a97b = 1'b0; end uka3349 : begin jra5ef8 = fafb6ae; xyb52f = 1'b0; nr5a97b = 1'b1; end default : begin jra5ef8 = fafb6ae; xyb52f = 1'b0; nr5a97b = 1'b0; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign hodf196 = dmf12fc & jc7c424[mt18a4d] & ~th5f894 & ~jra0e7b ;\r
-\r
-always @ (lq6c32a[5:3] or gb6abd3 or ntaf4ee or czd3bb5 or dmeed68 or dbb5a1a or go686bb or ie1aec9 or yzbb24e) begin case (lq6c32a[5:3]) 3'b000 : begin bn32cad = gb6abd3; end 3'b001 : begin bn32cad = ntaf4ee; end 3'b010 : begin bn32cad = czd3bb5; end 3'b011 : begin bn32cad = dmeed68; end 3'b100 : begin bn32cad = dbb5a1a; end 3'b101 : begin bn32cad = go686bb; end 3'b110 : begin bn32cad = ie1aec9; end 3'b111 : begin bn32cad = yzbb24e; end endcase\r
-end\r
-\r
-always @ (lq6c32a[2:0] or cz5e25f) begin case (lq6c32a[2:0]) 3'b000 : begin shf8cb2 = cz5e25f[0]; end 3'b001 : begin shf8cb2 = cz5e25f[1]; end 3'b010 : begin shf8cb2 = cz5e25f[2]; end 3'b011 : begin shf8cb2 = cz5e25f[3]; end 3'b100 : begin shf8cb2 = cz5e25f[4]; end 3'b101 : begin shf8cb2 = cz5e25f[5]; end 3'b110 : begin shf8cb2 = cz5e25f[6]; end 3'b111 : begin shf8cb2 = cz5e25f[7]; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign an95b92 = 8'hff == je896ad;\r
-\r
-\r
-always @(doa7d2e or al4b56a or ip4bf12) begin case(doa7d2e) fafb6ae : begin if (!al4b56a) begin co928b1 = fafb6ae; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else if (al4b56a) begin if (ip4bf12) begin co928b1 = uidb573; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = co986a3; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end end uidb573 : begin if (ip4bf12) begin co928b1 = rgdab98; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = ipc3519; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end rgdab98 : begin if (ip4bf12) begin co928b1 = xwd5cc3; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = qi1a8cd; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end xwd5cc3 : begin if (ip4bf12) begin co928b1 = mtae61a; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = osd4669; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end mtae61a : begin if (ip4bf12) begin co928b1 = ne730d4; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = uka3349; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end ne730d4 : begin if (ip4bf12) begin co928b1 = fafb6ae; jeadc94 = 1'b1; rt6e4a2 = 1'b0; end else begin co928b1 = fafb6ae; jeadc94 = 1'b0; rt6e4a2 = 1'b1; end end co986a3 : begin co928b1 = ipc3519; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end ipc3519 : begin co928b1 = qi1a8cd; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end qi1a8cd : begin co928b1 = osd4669; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end osd4669 : begin co928b1 = uka3349; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end uka3349 : begin co928b1 = fafb6ae; jeadc94 = 1'b0; rt6e4a2 = 1'b1; end default : begin co928b1 = fafb6ae; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end endcase\r
-end\r
-\r
-always@* begin je896ad<={bn1ce70>>1,mef0f02[0]};al4b56a<=mef0f02[1];zm9c559<=mef0f02[2];byd5aaf<=mef0f02[3];gb6abd3<={uv70d29>>1,mef0f02[4]};ntaf4ee<={hq8694d>>1,mef0f02[5]};czd3bb5<={ec34a6a>>1,mef0f02[6]};dmeed68<={lfa5351>>1,mef0f02[7]};dbb5a1a<={gd29a8f>>1,mef0f02[8]};go686bb<={rg4d47c>>1,mef0f02[9]};ie1aec9<={mr6a3e2>>1,mef0f02[10]};yzbb24e<={of51f14>>1,mef0f02[11]};gbc93ad<={sj8f8a4>>1,mef0f02[12]};ay49d6c<=mef0f02[13];kd4eb61<=mef0f02[14];ip75b0c<=mef0f02[15];lq6c32a<={wla48aa>>1,mef0f02[16]};ld61953<=mef0f02[17];dbca9e<=mef0f02[18];ip654f7<=mef0f02[19];hq2a7bd<=mef0f02[20];yk53dea<=mef0f02[21];zz9ef51<=mef0f02[22];kdf7a8f<=mef0f02[23];babd47c<=mef0f02[24];yx51f10<={wj5b24d>>1,mef0f02[25]};jc7c424<={enc9365>>1,mef0f02[26]};yxe2122<=mef0f02[27];aa10914<=mef0f02[28];lf848a0<=mef0f02[29];ou24507<=mef0f02[30];fp22839<=mef0f02[31];je141cf<=mef0f02[32];jra0e7b<=mef0f02[33];mt73de<=mef0f02[34];rgcf7ad<={jra5ef8>>1,mef0f02[35]};icdeb5e<={hb7be32>>1,mef0f02[36]};cmf5af1<=mef0f02[37];twad789<=mef0f02[38];cz5e25f<={bn32cad>>1,mef0f02[39]};dmf12fc<=mef0f02[40];xy897e2<=mef0f02[41];ip4bf12<=mef0f02[42];th5f894<=mef0f02[43];pffc4a7<=mef0f02[44];wl129f4<={co928b1>>1,mef0f02[45]};doa7d2e<={baa2c4f>>1,mef0f02[46]};sw3e973<=mef0f02[47];rgf4b98<=mef0f02[48];lfa5cc3<=mef0f02[49];aa2e61e<=mef0f02[50];vi730f0<=mef0f02[51];ou98783<=mef0f02[52];alc3c19<=mef0f02[53];ba1e0cc<=mef0f02[54];uif0662<=mef0f02[55];do83310<=mef0f02[56];fp19883<=mef0f02[57];end\r
-always@* begin ng1e1e0[2047]<=cb25ef;ng1e1e0[2046]<=lfaa812;ng1e1e0[2044]<=ykce1a5;ng1e1e0[2040]<=uv70d29[0];ng1e1e0[2032]<=hq8694d[0];ng1e1e0[2017]<=ec34a6a[0];ng1e1e0[1987]<=lfa5351[0];ng1e1e0[1980]<=je89ef4;ng1e1e0[1963]<=xyb52f;ng1e1e0[1942]<=ksa3f8a;ng1e1e0[1926]<=gd29a8f[0];ng1e1e0[1921]<=ks152d9;ng1e1e0[1913]<=fn4f7a3;ng1e1e0[1903]<=an95b92;ng1e1e0[1879]<=nr5a97b;ng1e1e0[1837]<=wy1fc51;ng1e1e0[1805]<=rg4d47c[0];ng1e1e0[1795]<=oua96c9;ng1e1e0[1783]<=baa2c4f[0];ng1e1e0[1778]<=zx7bd1f;ng1e1e0[1758]<=jeadc94;ng1e1e0[1710]<=jra5ef8[0];ng1e1e0[1679]<=wla48aa[0];ng1e1e0[1627]<=lqfe289;ng1e1e0[1562]<=mr6a3e2[0];ng1e1e0[1543]<=wj5b24d[0];ng1e1e0[1519]<=fp1627b;ng1e1e0[1509]<=uide8fe;ng1e1e0[1499]<=hq9656e;ng1e1e0[1469]<=rt6e4a2;ng1e1e0[1398]<=shf8cb2;ng1e1e0[1373]<=hb7be32[0];ng1e1e0[1310]<=fac526c;ng1e1e0[1207]<=rgf144b;ng1e1e0[1144]<=ww49b15;ng1e1e0[1076]<=of51f14[0];ng1e1e0[1039]<=enc9365[0];ng1e1e0[1023]<=bn1ce70[0];ng1e1e0[990]<=yzb13de;ng1e1e0[981]<=xj616a5;ng1e1e0[971]<=vif47f1;ng1e1e0[960]<=cm62a5b;ng1e1e0[951]<=ngb2b72;ng1e1e0[891]<=co928b1[0];ng1e1e0[839]<=vk14915;ng1e1e0[749]<=bn32cad[0];ng1e1e0[699]<=hodf196;ng1e1e0[572]<=qv29362;ng1e1e0[490]<=gd2c2d4;ng1e1e0[480]<=ho6c54b;ng1e1e0[419]<=ale2922;ng1e1e0[245]<=sh6585a;ng1e1e0[240]<=dm4d8a9;ng1e1e0[209]<=tu7c524;ng1e1e0[122]<=tu6cb0b;ng1e1e0[104]<=sj8f8a4[0];ng1e1e0[61]<=lq4d961;ng1e1e0[30]<=kq49b2c;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module uvd3c42 (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- tu42b90,\r
- wy15c82,\r
- epae410,\r
-\r
- \r
- rx_fifo_full,\r
-\r
- \r
- ep90421,\r
-\r
- \r
- sw8210d,\r
- sw10869,\r
- zz84348,\r
- sw21a46,\r
-\r
- \r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
-);\r
-parameter gq97bed = 8;\r
-parameter ofd97a2 = 20;\r
-parameter ykcbd15 = 32;\r
-parameter qt5e8a8 = 8;\r
-parameter psf4545 = 4;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input wy15c82;\r
-input tu42b90;\r
-input [1:0] epae410;\r
-input rx_fifo_full;\r
-input [ofd97a2-1:0] ep90421;\r
-output [qt5e8a8-1:0] sw8210d;\r
-output [qt5e8a8-1:0] sw10869;\r
-output zz84348;\r
-output sw21a46;\r
-output rx_fifo_error;\r
-output [ykcbd15-1:0] rx_stat_vector;\r
-output [gq97bed-1:0] rx_dbout;\r
-output rx_write;\r
-output rx_stat_en;\r
-output rx_eof;\r
-output rx_error;\r
-reg [qt5e8a8:0] of4bc4f;\r
-reg [qt5e8a8:0] vif13e4;\r
-wire zz84348;\r
-wire sw21a46;\r
-reg rx_fifo_error;\r
-reg [ykcbd15-1:0] rx_stat_vector;\r
-reg [gq97bed-1:0] rx_dbout ;\r
-reg [gq97bed-1:0] hd9bdf7;\r
-reg [gq97bed-1:0] wjf7df9;\r
-reg rx_write ;\r
-reg ipf7e64;\r
-reg ntbf324;\r
-reg jpf9927;\r
-reg rx_stat_en;\r
-reg rx_eof;\r
-reg rx_error;\r
-reg [ofd97a2-1:0] tw3fb87;\r
-reg alfdc3a;\r
-wire hoee1d5;\r
-wire al70eaa;\r
-reg co87555;\r
-reg vk3aaa9;\r
-reg psd554a;\r
-wire fpaaa53;\r
-reg [psf4545-1:0] coa94ff;\r
-reg rt4a7f9;\r
-wire [qt5e8a8:0] wl9fe79;\r
-reg [qt5e8a8:0] ldf9e69;\r
-reg rgcf34f;\r
-reg ps79a7b;\r
-reg zxcd3db;\r
-reg xw69ede;\r
-reg zx4f6f2;\r
-reg dz7b797;\r
-reg [1 : 0] eadbcbf;\r
-reg wwde5f9;\r
-reg [ofd97a2 - 1 : 0] ks97e44;\r
-reg [qt5e8a8 : 0] pff910f;\r
-reg [qt5e8a8 : 0] wj443f7;\r
-reg [gq97bed - 1 : 0] ukfde0;\r
-reg [gq97bed - 1 : 0] off7806;\r
-reg gqbc034;\r
-reg yke01a0;\r
-reg ecd01;\r
-reg [ofd97a2 - 1 : 0] aa3404e;\r
-reg bna0270;\r
-reg do1387;\r
-reg bn9c3a;\r
-reg sh4e1d7;\r
-reg yx70ebd;\r
-reg mg875ed;\r
-reg xy3af69;\r
-reg [psf4545 - 1 : 0] ribda57;\r
-reg ofed2bb;\r
-reg [qt5e8a8 : 0] fn4aeeb;\r
-reg [qt5e8a8 : 0] gdbbaf2;\r
-reg bldd794;\r
-reg zkebca7;\r
-reg sh5e53b;\r
-reg czf29dc;\r
-reg [2047:0] ng1e1e0;\r
-wire [27:0] mef0f02;\r
-\r
-localparam uk87811 = 28,gd3c088 = 32'hfdffc68b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-assign sw8210d = pff910f[qt5e8a8-1:0];\r
-assign sw10869 = wj443f7[qt5e8a8-1:0];\r
-assign wl9fe79 = ({(pff910f[qt5e8a8] ^ wj443f7[qt5e8a8]), pff910f[qt5e8a8-1:0]}) - ({1'b0, wj443f7[qt5e8a8-1:0]});\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin alfdc3a <= 0; co87555 <= 0; end else if (rxmac_clk_en) begin co87555 <= bn9c3a; if ((|ribda57) | (do1387)) begin alfdc3a <= 1; end else begin alfdc3a <= 0; end end\r
-end\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin coa94ff <= 4'h0; rt4a7f9 <= 1'b0; psd554a <= 1'b0; of4bc4f <= 9'd0; vif13e4 <= 9'd0; ldf9e69 <= 9'd0; rgcf34f <= 1'b0; ps79a7b <= 1'b0; tw3fb87 <= 1'b0; rx_stat_vector <= 32'b0; rx_dbout <= 8'd0; hd9bdf7 <= 8'd0; wjf7df9 <= 8'd0; rx_write <= 1'b0; ipf7e64 <= 1'b0; ntbf324 <= 1'b0; jpf9927 <= 1'b0; rx_stat_en <= 1'b0; rx_eof <= 1'b0; rx_error <= 1'b0; vk3aaa9 <= 1'b0; zxcd3db <= 1'b0; xw69ede <= 1'b0; rx_fifo_error <= 1'b0; end else if (rxmac_clk_en) begin tw3fb87 <= ks97e44;\r
- rx_fifo_error <= xy3af69 | (rx_fifo_error & ~rx_eof); if ((zx4f6f2 == 1) & (eadbcbf == 3)) begin vk3aaa9 <= 1; end else begin vk3aaa9 <= 0; end zxcd3db <= yx70ebd; xw69ede <= dz7b797; if (mg875ed == 1) begin coa94ff <= 0; end else if (!bn9c3a && sh5e53b) begin coa94ff <= ribda57 + 4'b0001; end else if (bn9c3a && !sh5e53b) begin coa94ff <= ribda57 - 4'b0001; end if ((fn4aeeb[qt5e8a8-1:1] == 0) && ((fn4aeeb[0] == 0) || (zz84348 == 1))) begin psd554a <= 1; end else begin psd554a <= 0; end if (fn4aeeb[qt5e8a8-1:2] == 6'b111111) begin rt4a7f9 <= 1; end else begin rt4a7f9 <= 0; end\r
- if (yx70ebd) ldf9e69 <= pff910f + 8'd1; if (zx4f6f2) of4bc4f <= pff910f + 8'd1; else if (czf29dc) of4bc4f <= gdbbaf2; if (zz84348) vif13e4 <= wj443f7 + 8'd1; \r
- rgcf34f <= zz84348; ps79a7b <= bldd794; if (aa3404e[18]) begin rx_stat_vector <= {aa3404e[15:0], ks97e44[15:0]}; end wjf7df9 <= aa3404e[7:0]; hd9bdf7 <= off7806; rx_dbout <= ukfde0; ntbf324 <= zkebca7 & ~wwde5f9 & ~aa3404e[19]; ipf7e64 <= yke01a0; rx_write <= gqbc034; jpf9927 <= bldd794 & aa3404e[18]; rx_stat_en <= ecd01; rx_eof <= zkebca7 & aa3404e[17]; rx_error <= zkebca7 & aa3404e[16]; end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign hoee1d5 = (fn4aeeb[qt5e8a8-1:0] >= 7'h42);\r
-\r
-\r
-assign sw21a46 = zx4f6f2 & ~ofed2bb;\r
-assign zz84348 = bna0270 & ~mg875ed & ~bn9c3a & ~sh4e1d7;\r
-\r
-\r
-assign al70eaa = bldd794 & aa3404e[18];\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign fpaaa53 = (bna0270 | rx_write) & wwde5f9 & ~mg875ed & ~bn9c3a;\r
-\r
-always@* begin zx4f6f2<=mef0f02[0];dz7b797<=mef0f02[1];eadbcbf<={epae410>>1,mef0f02[2]};wwde5f9<=mef0f02[3];ks97e44<={ep90421>>1,mef0f02[4]};pff910f<={of4bc4f>>1,mef0f02[5]};wj443f7<={vif13e4>>1,mef0f02[6]};ukfde0<={hd9bdf7>>1,mef0f02[7]};off7806<={wjf7df9>>1,mef0f02[8]};gqbc034<=mef0f02[9];yke01a0<=mef0f02[10];ecd01<=mef0f02[11];aa3404e<={tw3fb87>>1,mef0f02[12]};bna0270<=mef0f02[13];do1387<=mef0f02[14];bn9c3a<=mef0f02[15];sh4e1d7<=mef0f02[16];yx70ebd<=mef0f02[17];mg875ed<=mef0f02[18];xy3af69<=mef0f02[19];ribda57<={coa94ff>>1,mef0f02[20]};ofed2bb<=mef0f02[21];fn4aeeb<={wl9fe79>>1,mef0f02[22]};gdbbaf2<={ldf9e69>>1,mef0f02[23]};bldd794<=mef0f02[24];zkebca7<=mef0f02[25];sh5e53b<=mef0f02[26];czf29dc<=mef0f02[27];end\r
-always@* begin ng1e1e0[2047]<=wy15c82;ng1e1e0[2046]<=epae410[0];ng1e1e0[2044]<=rx_fifo_full;ng1e1e0[2040]<=ep90421[0];ng1e1e0[2032]<=of4bc4f[0];ng1e1e0[2017]<=vif13e4[0];ng1e1e0[1987]<=hd9bdf7[0];ng1e1e0[1926]<=wjf7df9[0];ng1e1e0[1921]<=ldf9e69[0];ng1e1e0[1805]<=ipf7e64;ng1e1e0[1795]<=rgcf34f;ng1e1e0[1679]<=co87555;ng1e1e0[1562]<=ntbf324;ng1e1e0[1543]<=ps79a7b;ng1e1e0[1310]<=vk3aaa9;ng1e1e0[1144]<=fpaaa53;ng1e1e0[1076]<=jpf9927;ng1e1e0[1039]<=zxcd3db;ng1e1e0[1023]<=tu42b90;ng1e1e0[960]<=wl9fe79[0];ng1e1e0[839]<=al70eaa;ng1e1e0[572]<=psd554a;ng1e1e0[480]<=rt4a7f9;ng1e1e0[419]<=hoee1d5;ng1e1e0[240]<=coa94ff[0];ng1e1e0[209]<=alfdc3a;ng1e1e0[104]<=tw3fb87[0];ng1e1e0[30]<=xw69ede;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module cm4cad9 (\r
-\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- bn1ce70,\r
-\r
- \r
- lfaa812,\r
- jc4d12d,\r
- ykce1a5,\r
- gb44b50,\r
-\r
- \r
- ba25a85,\r
-\r
- \r
-\r
- ukf3ec,\r
- zz22aa1,\r
-\r
- \r
-\r
- jp50abc,\r
- ep855e6,\r
- hq2af34,\r
- dm579a3,\r
- ksbcd1b,\r
- lde68d9,\r
- ec346cf,\r
- eca3678,\r
- xy1b3c0,\r
- qtd9e02,\r
- lqcf014,\r
- su780a3,\r
- rgc0518,\r
- ir28c2\r
-\r
-);\r
-parameter gq97bed = 8;\r
-parameter mga30a3 = 14;\r
-parameter kf18518 = 16;\r
-parameter vvc28c5 = 16;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input lfaa812;\r
-input jc4d12d;\r
-input ykce1a5;\r
-input gb44b50;\r
-input zz22aa1;\r
-input ukf3ec;\r
-input [gq97bed-1:0] bn1ce70;\r
-input [kf18518-1:0] ba25a85;\r
-output jp50abc;\r
-output ep855e6;\r
-output hq2af34;\r
-output ec346cf;\r
-output eca3678;\r
-output xy1b3c0;\r
-output lqcf014;\r
-output rgc0518;\r
-output ksbcd1b;\r
-output ir28c2;\r
-output [vvc28c5-1:0] qtd9e02;\r
-output [kf18518-1:0] su780a3;\r
-output [mga30a3-1:0] dm579a3;\r
-output [mga30a3-1:0] lde68d9;\r
-reg jp50abc;\r
-reg ep855e6;\r
-reg hq2af34;\r
-reg ec346cf;\r
-reg eca3678;\r
-reg xy1b3c0;\r
-reg rgc0518;\r
-reg ir28c2;\r
-reg [mga30a3-1:0] lde68d9;\r
-reg [mga30a3-1:0] dm579a3;\r
-reg [kf18518-1:0] su780a3;\r
-reg [gq97bed-1:0] gq3eb5e;\r
-wire lqcf014;\r
-wire [vvc28c5-1:0] qtd9e02;\r
-reg ksbcd1b;\r
-localparam ykf02fc = 16'h8808;\r
-localparam lf817e0 = 16'h8100;\r
-localparam lsbf06 = 16'd46;\r
-localparam rt5f832 = 16'd42;\r
-localparam zxfc197 = 9;\r
-localparam uie0cbe = 9'b000000001;\r
-localparam xl65f0 = 9'b000000010;\r
-localparam jr32f87 = 9'b000000100;\r
-localparam sw97c3e = 9'b000001000;\r
-localparam cbbe1f1 = 9'b000010000;\r
-localparam wwf0f8d = 9'b000100000;\r
-localparam wy87c69 = 9'b001000000;\r
-localparam uk3e348 = 9'b010000000;\r
-localparam lqf1a41 = 9'b100000000;\r
-wire mg8d20b;\r
-wire xw69058;\r
-wire by482c3;\r
-wire of4161a;\r
-wire jeb0d4;\r
-wire dm586a3;\r
-wire qtc351b;\r
-wire co1a8dd;\r
-wire god46e9;\r
-reg [zxfc197-1:0] do1ba48;\r
-reg rtdd243;\r
-reg zxe921f;\r
-reg qg490ff;\r
-reg dm487f8;\r
-reg [zxfc197-1:0] qi1fe10;\r
-reg rgf144b;\r
-reg [gq97bed - 1 : 0] je896ad;\r
-reg zm9c559;\r
-reg fp81339;\r
-reg byd5aaf;\r
-reg os4ce77;\r
-reg [kf18518 - 1 : 0] qv39dc8;\r
-reg eacee45;\r
-reg kq77228;\r
-reg [gq97bed - 1 : 0] ldc8a08;\r
-reg vv45047;\r
-reg ph2823e;\r
-reg qt411f7;\r
-reg an8fbc;\r
-reg jc47de5;\r
-reg uk3ef2a;\r
-reg ipf7950;\r
-reg ksbca84;\r
-reg ice5421;\r
-reg [zxfc197 - 1 : 0] bl5084a;\r
-reg tj84256;\r
-reg wy212b6;\r
-reg rv95b1;\r
-reg nr4ad8e;\r
-reg [zxfc197 - 1 : 0] swb63b1;\r
-reg fp19883;\r
-reg [2047:0] ng1e1e0;\r
-wire [24:0] mef0f02;\r
-\r
-localparam uk87811 = 25,gd3c088 = 32'hfdffca8b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign mg8d20b = fp81339 && ({ldc8a08, je896ad} == ykf02fc);\r
-assign xw69058 = fp81339 && ({ldc8a08, je896ad} != ykf02fc);\r
-\r
-\r
-\r
-\r
-assign by482c3 = fp81339 && ({ldc8a08, je896ad} == lf817e0);\r
-\r
-\r
-\r
-\r
-\r
-assign of4161a = ((fp81339 & (vv45047 | (~vv45047 & ~qt411f7 && {ldc8a08, je896ad} < lsbf06))) | (wy212b6 && {ldc8a08, je896ad} < rt5f832));\r
-\r
-\r
-\r
-\r
-\r
-assign co1a8dd = (kq77228 | eacee45) & rv95b1 && ({ldc8a08, je896ad} == qv39dc8);\r
-assign qtc351b = rv95b1 && ({ldc8a08, je896ad} != qv39dc8);\r
-assign god46e9 = eacee45 & ph2823e;\r
-\r
-\r
-\r
-\r
-assign jeb0d4 = ((fp81339 & ~qt411f7) | (wy212b6) && {ldc8a08, je896ad} >= 16'h0600);\r
-\r
-\r
-\r
-assign dm586a3 = fp81339 & ~vv45047;\r
-\r
-assign lqcf014 = tj84256; \r
-assign qtd9e02 = {ldc8a08, je896ad}; \r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin jp50abc <= 1'b0; ep855e6 <= 1'b0; hq2af34 <= 1'b0; ec346cf <= 1'b0; eca3678 <= 1'b0; xy1b3c0 <= 1'b0; dm579a3 <= 14'b0; lde68d9 <= 14'b0; su780a3 <= 16'b0; rgf144b <= 1'b0; qi1fe10 <= uie0cbe; rgc0518 <= 1'b0; ir28c2 <= 1'b0; ksbcd1b <= 1'b0; gq3eb5e <= 0; end else if (rxmac_clk_en) begin\r
- gq3eb5e <= je896ad; rgf144b <= byd5aaf; ksbcd1b <= (fp81339 & ~qt411f7) | wy212b6; if (fp19883) qi1fe10 <= uie0cbe; else begin qi1fe10 <= bl5084a; if (os4ce77) lde68d9 <= lde68d9 - 14'd1; end if (fp81339 && vv45047) lde68d9 <= 14'd46; else if ((fp81339 && !hq2af34) || wy212b6) begin dm579a3 <= {ldc8a08[5:0], je896ad}; lde68d9 <= {ldc8a08[5:0], je896ad}; end if (nr4ad8e) su780a3 <= {ldc8a08, je896ad}; if (uk3ef2a) jp50abc <= uk3ef2a; else if (zm9c559) jp50abc <= 1'b0; else jp50abc <= jp50abc; if (vv45047) ep855e6 <= vv45047; else if (zm9c559) ep855e6 <= 1'b0; else ep855e6 <= ep855e6; if (jc47de5) xy1b3c0 <= jc47de5; else if (zm9c559) xy1b3c0 <= 1'b0; else xy1b3c0 <= xy1b3c0; if (an8fbc) eca3678 <= an8fbc; else if (zm9c559) eca3678 <= 1'b0; else eca3678 <= eca3678; if (ksbca84) ec346cf <= ksbca84; else if (zm9c559) ec346cf <= 1'b0; else ec346cf <= ec346cf; if (ipf7950) rgc0518 <= ipf7950; else if (zm9c559) rgc0518 <= 1'b0; else rgc0518 <= rgc0518; if (ice5421) ir28c2 <= ice5421; else if (zm9c559) ir28c2 <= 1'b0; else ir28c2 <= ir28c2; if (qt411f7) hq2af34 <= qt411f7; else if (zm9c559) hq2af34 <= 1'b0; else hq2af34 <= hq2af34; end\r
-end\r
-\r
-always @ (swb63b1 or fp81339 or qt411f7 or vv45047 or ipf7950) begin case (swb63b1) uie0cbe : begin if (fp81339 && qt411f7) begin do1ba48 = xl65f0; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end else if (fp81339 && vv45047) begin do1ba48 = wwf0f8d; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end else begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end end xl65f0 : begin do1ba48 = jr32f87; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end jr32f87 : begin do1ba48 = sw97c3e; rtdd243 = 1'b1; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end sw97c3e : begin do1ba48 = cbbe1f1; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end cbbe1f1 : begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b1; qg490ff = 1'b0; dm487f8 = 1'b0; end wwf0f8d : begin do1ba48 = wy87c69; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end wy87c69 : begin if (ipf7950) begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b1; dm487f8 = 1'b0; end else begin do1ba48 = uk3e348; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b1; dm487f8 = 1'b0; end end uk3e348 : begin do1ba48 = lqf1a41; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end lqf1a41 : begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b1; end default : begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end endcase\r
-end\r
-always@* begin je896ad<={bn1ce70>>1,mef0f02[0]};zm9c559<=mef0f02[1];fp81339<=mef0f02[2];byd5aaf<=mef0f02[3];os4ce77<=mef0f02[4];qv39dc8<={ba25a85>>1,mef0f02[5]};eacee45<=mef0f02[6];kq77228<=mef0f02[7];ldc8a08<={gq3eb5e>>1,mef0f02[8]};vv45047<=mef0f02[9];ph2823e<=mef0f02[10];qt411f7<=mef0f02[11];an8fbc<=mef0f02[12];jc47de5<=mef0f02[13];uk3ef2a<=mef0f02[14];ipf7950<=mef0f02[15];ksbca84<=mef0f02[16];ice5421<=mef0f02[17];bl5084a<={do1ba48>>1,mef0f02[18]};tj84256<=mef0f02[19];wy212b6<=mef0f02[20];rv95b1<=mef0f02[21];nr4ad8e<=mef0f02[22];swb63b1<={qi1fe10>>1,mef0f02[23]};fp19883<=mef0f02[24];end\r
-always@* begin ng1e1e0[2047]<=lfaa812;ng1e1e0[2046]<=jc4d12d;ng1e1e0[2044]<=ykce1a5;ng1e1e0[2040]<=gb44b50;ng1e1e0[2032]<=ba25a85[0];ng1e1e0[2017]<=ukf3ec;ng1e1e0[1987]<=zz22aa1;ng1e1e0[1926]<=gq3eb5e[0];ng1e1e0[1804]<=mg8d20b;ng1e1e0[1803]<=qi1fe10[0];ng1e1e0[1560]<=xw69058;ng1e1e0[1558]<=rgf144b;ng1e1e0[1550]<=co1a8dd;ng1e1e0[1072]<=by482c3;ng1e1e0[1052]<=god46e9;ng1e1e0[1023]<=bn1ce70[0];ng1e1e0[901]<=dm487f8;ng1e1e0[775]<=qtc351b;ng1e1e0[450]<=qg490ff;ng1e1e0[387]<=dm586a3;ng1e1e0[225]<=zxe921f;ng1e1e0[193]<=jeb0d4;ng1e1e0[112]<=rtdd243;ng1e1e0[96]<=of4161a;ng1e1e0[56]<=do1ba48[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module oub9ee6 (\r
- pscf731, \r
- bl7b98b, \r
- mrdcc5e,\r
- hbe62f4,\r
- uk317a6,\r
- fp8bd30,\r
- uv5e986,\r
- vif4c35,\r
- oua61ab,\r
- rxmac_clk_en,\r
- vk86ac3\r
- );\r
-output [5:0] pscf731;\r
-output bl7b98b;\r
-input [7:0] mrdcc5e;\r
-input [31:0] vif4c35;\r
-input hbe62f4;\r
-input uk317a6;\r
-input fp8bd30;\r
-input uv5e986;\r
-input oua61ab;\r
-input rxmac_clk_en;\r
-input vk86ac3;\r
-reg [31:0] zm3f362;\r
-reg [5:0] pscf731;\r
-reg bl7b98b;\r
-wire [31:0] ps6c4ff;\r
-wire [31:0] os627fb;\r
-reg [7 : 0] bn13fd8;\r
-reg wl9fec7;\r
-reg kqff63d;\r
-reg jcfb1e9;\r
-reg dzd8f4b;\r
-reg [31 : 0] nrc7a5e;\r
-reg [31 : 0] db3d2f6;\r
-reg [31 : 0] dze97b6;\r
-reg [31 : 0] yx4bdb7;\r
-reg [2047:0] ng1e1e0;\r
-wire [8:0] mef0f02;\r
-\r
-localparam uk87811 = 9,gd3c088 = 32'hfdffe06b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-assign os627fb[0] = ~db3d2f6[0];\r
-assign os627fb[1] = ~db3d2f6[1];\r
-assign os627fb[2] = db3d2f6[2];\r
-assign os627fb[3] = ~db3d2f6[3];\r
-assign os627fb[4] = ~db3d2f6[4];\r
-assign os627fb[5] = ~db3d2f6[5];\r
-assign os627fb[6] = ~db3d2f6[6];\r
-assign os627fb[7] = db3d2f6[7];\r
-assign os627fb[8] = ~db3d2f6[8];\r
-assign os627fb[9] = db3d2f6[9];\r
-assign os627fb[10] = ~db3d2f6[10];\r
-assign os627fb[11] = ~db3d2f6[11];\r
-assign os627fb[12] = ~db3d2f6[12];\r
-assign os627fb[13] = db3d2f6[13];\r
-assign os627fb[14] = ~db3d2f6[14];\r
-assign os627fb[15] = ~db3d2f6[15];\r
-assign os627fb[16] = db3d2f6[16];\r
-assign os627fb[17] = db3d2f6[17];\r
-assign os627fb[18] = ~db3d2f6[18];\r
-assign os627fb[19] = db3d2f6[19];\r
-assign os627fb[20] = db3d2f6[20];\r
-assign os627fb[21] = db3d2f6[21];\r
-assign os627fb[22] = db3d2f6[22];\r
-assign os627fb[23] = db3d2f6[23];\r
-assign os627fb[24] = ~db3d2f6[24];\r
-assign os627fb[25] = ~db3d2f6[25];\r
-assign os627fb[26] = ~db3d2f6[26];\r
-assign os627fb[27] = db3d2f6[27];\r
-assign os627fb[28] = db3d2f6[28];\r
-assign os627fb[29] = db3d2f6[29];\r
-assign os627fb[30] = ~db3d2f6[30];\r
-assign os627fb[31] = ~db3d2f6[31];\r
-\r
-always @ (posedge oua61ab or negedge vk86ac3)\r
-begin if (!vk86ac3) begin zm3f362 <= 32'hffffffff; pscf731 <= 6'b000000; bl7b98b <= 0; end else if (rxmac_clk_en) begin if (wl9fec7) begin zm3f362 <= dze97b6; end else if (dzd8f4b) begin zm3f362 <= nrc7a5e; end if (kqff63d) begin pscf731[5] <= dze97b6[30]; pscf731[4] <= dze97b6[29]; pscf731[3] <= dze97b6[28]; pscf731[2] <= dze97b6[27]; pscf731[1] <= dze97b6[26]; pscf731[0] <= dze97b6[25]; end if (jcfb1e9) begin if (yx4bdb7 == 0) begin bl7b98b <= 0; end else begin bl7b98b <= 1; end end else if (dzd8f4b) begin bl7b98b <= 0; end end\r
-end\r
-\r
-assign ps6c4ff[0] = db3d2f6[30] ^ bn13fd8[7] ^ bn13fd8[1] ^ db3d2f6[24];\r
-assign ps6c4ff[1] = db3d2f6[30] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25];\r
-assign ps6c4ff[2] = db3d2f6[30] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ db3d2f6[26] ^ bn13fd8[5];\r
-assign ps6c4ff[3] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ bn13fd8[6];\r
-assign ps6c4ff[4] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[7];\r
-assign ps6c4ff[5] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[2] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[6] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[7] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[24] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[8] = db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[0];\r
-assign ps6c4ff[9] = db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ db3d2f6[1];\r
-assign ps6c4ff[10] = db3d2f6[24] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[29] ^ bn13fd8[7] ^ db3d2f6[2];\r
-assign ps6c4ff[11] = db3d2f6[3] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ bn13fd8[7];\r
-assign ps6c4ff[12] = db3d2f6[30] ^ db3d2f6[4] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[13] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[5] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[14] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[6] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[28];\r
-assign ps6c4ff[15] = db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[2] ^ db3d2f6[7] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ db3d2f6[29];\r
-assign ps6c4ff[16] = db3d2f6[24] ^ bn13fd8[2] ^ bn13fd8[3] ^ db3d2f6[8] ^ db3d2f6[28] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[17] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[9] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[18] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[26] ^ bn13fd8[5] ^ db3d2f6[10];\r
-assign ps6c4ff[19] = db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[11];\r
-assign ps6c4ff[20] = db3d2f6[12] ^ bn13fd8[3] ^ db3d2f6[28];\r
-assign ps6c4ff[21] = db3d2f6[13] ^ bn13fd8[2] ^ db3d2f6[29];\r
-assign ps6c4ff[22] = db3d2f6[14] ^ db3d2f6[24] ^ bn13fd8[7];\r
-assign ps6c4ff[23] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[15] ^ db3d2f6[25] ^ bn13fd8[6] ^ bn13fd8[7];\r
-assign ps6c4ff[24] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ db3d2f6[16] ^ db3d2f6[26] ^ bn13fd8[5] ^ bn13fd8[6];\r
-assign ps6c4ff[25] = db3d2f6[26] ^ db3d2f6[17] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5];\r
-assign ps6c4ff[26] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[18] ^ db3d2f6[28] ^ bn13fd8[7];\r
-assign ps6c4ff[27] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ bn13fd8[2] ^ bn13fd8[3] ^ db3d2f6[28] ^ db3d2f6[19] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[28] = db3d2f6[30] ^ bn13fd8[1] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[5] ^ db3d2f6[29] ^ db3d2f6[20];\r
-assign ps6c4ff[29] = db3d2f6[30] ^ db3d2f6[21] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ bn13fd8[4] ^ db3d2f6[27];\r
-assign ps6c4ff[30] = db3d2f6[31] ^ db3d2f6[22] ^ bn13fd8[0] ^ bn13fd8[3] ^ db3d2f6[28];\r
-assign ps6c4ff[31] = db3d2f6[23] ^ bn13fd8[2] ^ db3d2f6[29];\r
-always@* begin bn13fd8<={mrdcc5e>>1,mef0f02[0]};wl9fec7<=mef0f02[1];kqff63d<=mef0f02[2];jcfb1e9<=mef0f02[3];dzd8f4b<=mef0f02[4];nrc7a5e<={vif4c35>>1,mef0f02[5]};db3d2f6<={zm3f362>>1,mef0f02[6]};dze97b6<={ps6c4ff>>1,mef0f02[7]};yx4bdb7<={os627fb>>1,mef0f02[8]};end\r
-always@* begin ng1e1e0[2047]<=hbe62f4;ng1e1e0[2046]<=uk317a6;ng1e1e0[2044]<=fp8bd30;ng1e1e0[2041]<=uv5e986;ng1e1e0[2034]<=vif4c35[0];ng1e1e0[2021]<=zm3f362[0];ng1e1e0[1995]<=ps6c4ff[0];ng1e1e0[1943]<=os627fb[0];ng1e1e0[1023]<=mrdcc5e[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module gd33aed (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- ks10d54, \r
- fa6c2d4, \r
- pf616a3, \r
- lsb51f, \r
- vv5a8fb,\r
-\r
- \r
- bn1ce70,\r
- cb25ef,\r
- wl12f7d,\r
- rva04bd,\r
-\r
- \r
- mg1550f,\r
- hdaa879,\r
- en543cf,\r
- uxa1e7d,\r
-\r
- \r
- jp50abc,\r
- ep855e6,\r
- hq2af34,\r
- dm579a3,\r
- ec346cf,\r
- eca3678,\r
- xy1b3c0,\r
- rgc0518,\r
- ksbcd1b,\r
- lde68d9,\r
- yz172cd,\r
-\r
- \r
- ignore_pkt,\r
-\r
- \r
- qgcb360,\r
- go59b01,\r
- ldcd808,\r
- tu6c047,\r
- wj6023b,\r
-\r
- \r
- bl7b98b,\r
-\r
- \r
- lfaa812,\r
- ykce1a5,\r
-\r
- \r
- gq3baab,\r
- bldd558,\r
- ykeaac7,\r
-\r
- \r
- ls35502,\r
- yzab1cf,\r
-\r
- \r
- fa58e7c,\r
-\r
- \r
- jc4d12d,\r
- gb44b50,\r
-\r
- \r
- epae410,\r
- tu42b90,\r
- wy15c82,\r
-\r
- \r
- kf17a95,\r
- ks24554,\r
- fp8bd30,\r
- jc52b50\r
-);\r
-parameter gq97bed = 8;\r
-parameter mga30a3 = 14;\r
-parameter ofd97a2 = 20;\r
-parameter ykcbd15 = 32;\r
-parameter do838e7 = 32;\r
-parameter bn1c73a = 9;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input ks10d54;\r
-input fa6c2d4;\r
-input pf616a3;\r
-input lsb51f;\r
-input vv5a8fb;\r
-input wl12f7d;\r
-input rva04bd;\r
-input cb25ef;\r
-input [gq97bed-1:0] bn1ce70;\r
-input mg1550f;\r
-input hdaa879;\r
-input en543cf;\r
-input uxa1e7d;\r
-input jp50abc;\r
-input ep855e6;\r
-input hq2af34;\r
-input ec346cf;\r
-input yz172cd;\r
-input eca3678;\r
-input xy1b3c0;\r
-input rgc0518;\r
-input ksbcd1b;\r
-input [mga30a3-1:0] lde68d9;\r
-input [mga30a3-1:0] dm579a3;\r
-input ignore_pkt;\r
-input qgcb360;\r
-input go59b01;\r
-input [mga30a3-1:0] ldcd808;\r
-input tu6c047;\r
-input wj6023b;\r
-input bl7b98b;\r
-output lfaa812;\r
-output ls35502;\r
-output yzab1cf;\r
-output jc4d12d;\r
-output tu42b90;\r
-output wy15c82;\r
-output ykce1a5;\r
-output gb44b50;\r
-output [ofd97a2-1:0] epae410;\r
-output gq3baab;\r
-output [bn1c73a-1:0] bldd558;\r
-output ykeaac7;\r
-output fa58e7c;\r
-output [do838e7-1:0] kf17a95;\r
-output ks24554;\r
-output fp8bd30;\r
-output jc52b50;\r
-wire lfaa812;\r
-wire jc4d12d;\r
-wire tu42b90;\r
-wire wy15c82;\r
-wire [ofd97a2-1:0] epae410;\r
-reg gq3baab;\r
-wire [do838e7-1:0] kf17a95;\r
-wire ks24554;\r
-wire jc52b50;\r
-reg fa58e7c;\r
-reg [bn1c73a-1:0] bldd558;\r
-reg ykeaac7;\r
-localparam dzc2fc9 = 8;\r
-localparam an17e4e = 8'b00000001;\r
-localparam phbf275 = 8'b00000010;\r
-localparam zxf93af = 8'b00000100;\r
-localparam wjc9d7e = 8'b00001000;\r
-localparam en4ebf5 = 8'b00010000;\r
-localparam mr75fac = 8'b00100000;\r
-localparam xlafd65 = 8'b01000000;\r
-localparam dz7eb2f = 8'b10000000;\r
-localparam ayf597e = 1'b0;\r
-localparam coacbf1 = 1'b1;\r
-reg [dzc2fc9-1:0] je2fc44;\r
-reg ls35502;\r
-reg tuf111f;\r
-reg uk888fa;\r
-reg of447d1;\r
-reg kf23e8c;\r
-reg ykce1a5;\r
-wire gofa328;\r
-wire gb44b50;\r
-wire zm8ca08;\r
-wire cz65043;\r
-wire nt2821d;\r
-wire al410ef;\r
-wire [mga30a3-1:0] ui43be4;\r
-wire gd1df20;\r
-wire icef904;\r
-reg [dzc2fc9-1:0] rge410b;\r
-reg ba2085b;\r
-reg zm42da;\r
-reg [2:0] sw216d2;\r
-reg jeb691;\r
-reg en5b48b;\r
-reg [mga30a3-1:0] ldd22e2;\r
-reg [mga30a3-1:0] bn8b8b7;\r
-reg me5c5be;\r
-reg kde2df1;\r
-reg zz16f8d;\r
-reg fcb7c6f;\r
-reg [mga30a3-1:0] psf1bd5;\r
-reg sw8deab;\r
-reg yx6f559;\r
-reg gb7aacc;\r
-reg zkd5664;\r
-reg gdab323;\r
-reg [mga30a3-1:0] mrcc8e0;\r
-reg [mga30a3-1:0] ux2382f;\r
-wire bn1c17d;\r
-wire yke0bef;\r
-wire aa5f78;\r
-wire fc2fbc1;\r
-wire me7de0b;\r
-wire ykef059;\r
-wire ea782c8;\r
-reg [ofd97a2-1:0] ngb200;\r
-reg ic59003;\r
-wire fnc8019;\r
-wire vv400ce;\r
-wire [ykcbd15-1:0] vx33b0;\r
-wire yzab1cf;\r
-reg iccec3e;\r
-reg rg761f0;\r
-reg lfb0f83;\r
-reg xw69ede;\r
-reg sw3e0f8;\r
-reg uif07c1;\r
-reg [gq97bed-1:0] ym1f042;\r
-reg yxf8210 ;\r
-reg mec1084;\r
-reg ux8420;\r
-reg jc42104;\r
-reg [4:0] ym10823;\r
-reg vx84118;\r
-reg lqfe289;\r
-wire ri4632;\r
-reg ir23192;\r
-wire fp8bd30;\r
-reg uvc64a4;\r
-wire lf32525;\r
-wire mg9292f;\r
-wire hd94979;\r
-wire oha4bce;\r
-wire zm25e74;\r
-reg je2f3a2;\r
-reg ps79d12;\r
-reg wwce893;\r
-reg bl74498;\r
-reg hqa24c6;\r
-reg wl12632;\r
-reg do93194;\r
-reg gq98ca2;\r
-wire [bn1c73a-1:0] jr32885;\r
-reg [3:0] vx9442e;\r
-reg zma2177;\r
-reg ie10bba;\r
-reg wl85dd0;\r
-reg zm1b29c;\r
-reg ic77429;\r
-reg rvba149;\r
-reg ned0a4f;\r
-reg kf8527a;\r
-reg [gq97bed - 1 : 0] je896ad;\r
-reg al4b56a;\r
-reg qt7a94f;\r
-reg ayd4a7c;\r
-reg lfa53e0;\r
-reg gd29f07;\r
-reg th4f83c;\r
-reg by7c1e6;\r
-reg kqe0f32;\r
-reg ux7990;\r
-reg gd3cc84;\r
-reg [mga30a3 - 1 : 0] hd3212e;\r
-reg ir90977;\r
-reg xl84bbc;\r
-reg hq25de7;\r
-reg uk2ef3a;\r
-reg cm779d1;\r
-reg [mga30a3 - 1 : 0] qte7441;\r
-reg pu3a20c;\r
-reg wwd1063;\r
-reg gq88319;\r
-reg cz418c8;\r
-reg [mga30a3 - 1 : 0] ho6322e;\r
-reg xl19172;\r
-reg vvc8b97;\r
-reg xj45cbf;\r
-reg [dzc2fc9 - 1 : 0] qg72ff8;\r
-reg wy97fc0;\r
-reg jrbfe01;\r
-reg wwff00e;\r
-reg czf8071;\r
-reg tuc038c;\r
-reg xy1c62;\r
-reg hqe313;\r
-reg pf7189b;\r
-reg tw8c4df;\r
-reg [mga30a3 - 1 : 0] tj137d0;\r
-reg hd9be86;\r
-reg vidf437;\r
-reg [dzc2fc9 - 1 : 0] rgd0dd1;\r
-reg pu86e8a;\r
-reg tj37452;\r
-reg [2 : 0] bnba297;\r
-reg osd14bf;\r
-reg wl8a5f9;\r
-reg [mga30a3 - 1 : 0] ks97e6b;\r
-reg [mga30a3 - 1 : 0] pff9acf;\r
-reg zxcd67f;\r
-reg zx6b3fe;\r
-reg me59ff6;\r
-reg facffb0;\r
-reg [mga30a3 - 1 : 0] hofec14;\r
-reg jpf60a2;\r
-reg zzb0517;\r
-reg qi828be;\r
-reg zm145f0;\r
-reg fca2f83;\r
-reg [mga30a3 - 1 : 0] qvbe0dd;\r
-reg [mga30a3 - 1 : 0] fc83768;\r
-reg tw1bb43;\r
-reg pfdda1b;\r
-reg ened0de;\r
-reg ea686f5;\r
-reg ea437a9;\r
-reg ls1bd49;\r
-reg aydea4b;\r
-reg [ofd97a2 - 1 : 0] wya92c8;\r
-reg su49641;\r
-reg uv4b208;\r
-reg me59045;\r
-reg [ykcbd15 - 1 : 0] qt4114e;\r
-reg an8a74;\r
-reg ld453a5;\r
-reg mt29d2e;\r
-reg czf29dc;\r
-reg pf74ba4;\r
-reg vxa5d27;\r
-reg [gq97bed - 1 : 0] rt749f1;\r
-reg kfa4f8f;\r
-reg vx27c7c;\r
-reg gq3e3e7;\r
-reg dmf1f39;\r
-reg [4 : 0] cb8f9cb;\r
-reg vi7ce5c;\r
-reg do83310;\r
-reg wl3971c;\r
-reg wwcb8e4;\r
-reg yk5c720;\r
-reg dze3901;\r
-reg vx1c80f;\r
-reg zke407e;\r
-reg ng203f3;\r
-reg vk1f9b;\r
-reg qifcdb;\r
-reg fn7e6d8;\r
-reg xjf36c7;\r
-reg hd9b63f;\r
-reg qgdb1fe;\r
-reg nrd8ff0;\r
-reg pfc7f86;\r
-reg ri3fc36;\r
-reg [bn1c73a - 1 : 0] ayf0d93;\r
-reg [3 : 0] do86c99;\r
-reg an364ca;\r
-reg dob2655;\r
-reg ba932ab;\r
-reg [2047:0] ng1e1e0;\r
-wire [110:0] mef0f02;\r
-\r
-localparam uk87811 = 111,gd3c088 = 32'hfdffca8b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
-\r
-\r
- \r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin vx9442e <= 4'h0; zma2177 <= ayf597e; ie10bba <= 1'b0; wl85dd0 <= 1'b0; end else if (rxmac_clk_en) begin\r
- wl85dd0 <= dob2655;\r
- case (an364ca) ayf597e : begin ie10bba <= 1'b0; if (al4b56a && vi7ce5c) begin vx9442e <= do86c99 + 1; zma2177 <= coacbf1; end else begin vx9442e <= 4'h0; zma2177 <= ayf597e; end end coacbf1 : begin if (vi7ce5c) begin if (do86c99 <= 4'd12 ) begin vx9442e <= do86c99 + 1; zma2177 <= coacbf1; end else begin zma2177 <= ayf597e; end end else begin if (~cb8f9cb[3] & cb8f9cb[4]) begin zma2177 <= ayf597e; end if (do86c99 <= 4'd12) begin ie10bba <= 1'b1; end else begin ie10bba <= 1'b0; end end end default : begin vx9442e <= 4'h0; ie10bba <= 1'b0; zma2177 <= ayf597e; end\r
- endcase end \r
-\r
-end \r
-\r
-\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin yx6f559 <= 1'b0; gb7aacc <= 1'b0; rge410b <= an17e4e; sw216d2 <= 3'b000; jeb691 <= 1'b0; vx84118 <= 1'b0; yxf8210 <= 1'b0; mec1084 <= 1'b0; kde2df1 <= 1'b0; zz16f8d <= 1'b0; fcb7c6f <= 1'b0; sw8deab <= 1'b0; do93194 <= 1'b0; gq98ca2 <= 1'b0; en5b48b <= 1'b0; end else if (rxmac_clk_en) begin do93194 <= xl19172; gq98ca2 <= pfc7f86; if (jpf60a2) fcb7c6f <= jpf60a2; else if (lfaa812) fcb7c6f <= 1'b0; else if (gd29f07) fcb7c6f <= 1'b0; else fcb7c6f <= facffb0; sw8deab <= lfa53e0; kde2df1 <= wwd1063; zz16f8d <= zx6b3fe; yx6f559 <= gd29f07; gb7aacc <= zzb0517; vx84118 <= zm1b29c; yxf8210 <= vi7ce5c; mec1084 <= kfa4f8f; jeb691 <= lfa53e0 | (osd14bf & ~tuc038c); en5b48b <= wy97fc0; if(xy1c62) sw216d2 <= bnba297 + 2'd1; else if (lfaa812) sw216d2 <= 3'b000; rge410b <= qg72ff8; end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign jc4d12d = wl8a5f9;\r
-\r
-assign zm8ca08 = osd14bf | lfa53e0;\r
-assign gofa328 = bnba297[2] & ~bnba297[1] & bnba297[0];\r
-\r
-always @ (rgd0dd1 or ri3fc36 or zm1b29c or vi7ce5c or al4b56a or qt7a94f or lfa53e0 or gd29f07 or tuc038c or kqe0f32 or ux7990 or me59ff6) begin case (rgd0dd1) an17e4e : begin if (!(ri3fc36 && zm1b29c)) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b1; end else begin if(!me59ff6) kf23e8c = 1'b0; else kf23e8c = 1'b1; je2fc44 = phbf275; ls35502 = 1'b1; tuf111f = 1'b0; of447d1 = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end phbf275 : begin if (qt7a94f) begin je2fc44 = wjc9d7e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b1; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (al4b56a) begin je2fc44 = zxf93af; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (!zm1b29c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else begin je2fc44 = phbf275; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end zxf93af : begin if (lfa53e0) begin je2fc44 = en4ebf5; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (gd29f07) begin je2fc44 = wjc9d7e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (!vi7ce5c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b1; uk888fa = 1'b0; end else begin je2fc44 = zxf93af; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end wjc9d7e : begin if (!zm1b29c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else begin je2fc44 = wjc9d7e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end en4ebf5 : begin if (tuc038c) begin je2fc44 = mr75fac; ls35502 = 1'b0; tuf111f = 1'b1; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (!vi7ce5c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b1; uk888fa = 1'b0; end else begin je2fc44 = en4ebf5; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end mr75fac : begin if(kqe0f32 || ux7990) begin je2fc44 = xlafd65; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (!zm1b29c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b1; uk888fa = 1'b0; end else begin je2fc44 = mr75fac; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end xlafd65 : begin if (!vi7ce5c) begin je2fc44 = dz7eb2f; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else begin je2fc44 = xlafd65; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end dz7eb2f : begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end default : begin je2fc44 = an17e4e;\r
- ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign zk5d9f7 = zm1b29c;\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin iccec3e <= 0; rg761f0 <= 0; ba2085b <= 1'b0; zm42da <= 1'b0; ym1f042 <= 8'h00; lfb0f83 <= 1'b0; xw69ede <= 1'b0; sw3e0f8 <= 1'b0; uif07c1 <= 1'b0; jc42104 <= 1'b0; gq3baab <= 1'b0; ym10823[0] <= 1'b0; ym10823[1] <= 1'b0; ym10823[2] <= 1'b0; ym10823[3] <= 1'b0; ym10823[4] <= 1'b0; end else if (rxmac_clk_en) begin ym10823[0] <= kfa4f8f; ym10823[1] <= cb8f9cb[0]; ym10823[2] <= cb8f9cb[1]; ym10823[3] <= cb8f9cb[2]; ym10823[4] <= cb8f9cb[3]; if (uv4b208) jc42104 <= uv4b208; else if (lfaa812) jc42104 <= 1'b0; else jc42104 <= dmf1f39; sw3e0f8 <= ea437a9; uif07c1 <= pf74ba4; gq3baab <= jrbfe01 & ~pf74ba4; lfb0f83 <= lfaa812; xw69ede <= wy15c82; ym1f042 <= je896ad; iccec3e <= zk5d9f7; rg761f0 <= su49641; if (xl84bbc) ba2085b <= cm779d1 | (pu86e8a & su49641); else ba2085b <= cm779d1 | (pu86e8a & an8a74); zm42da <= al4b56a | (tj37452 & tw1bb43 & ~(gd29f07 & ~zzb0517)); end\r
-end\r
-\r
-\r
-\r
-assign gb44b50 = pu86e8a | cm779d1;\r
-assign yke0bef = (qte7441 == 14'd1);\r
-\r
-always @ (zk5d9f7 or gb44b50 or pfdda1b) begin casex ({gb44b50, pfdda1b}) 2'b0x : ic59003 = zk5d9f7; 2'b11 : ic59003 = 0; default : ic59003 = zk5d9f7; endcase\r
-end\r
-\r
-assign bn1c17d = (xl84bbc) ? ld453a5 : ic77429;\r
-assign aa5f78 = ~qifcdb & tj37452;\r
-assign me7de0b = tj37452;\r
-assign fc2fbc1 = (lfaa812 & ~wy15c82) | (mt29d2e & ~czf29dc);\r
-assign tu42b90 = ened0de | ea686f5;\r
-assign ea782c8 = lfaa812 | mt29d2e;\r
-always @ (lfaa812 or mt29d2e or qt4114e or qgdb1fe) begin case({lfaa812, mt29d2e}) 2'b10 : ngb200 = {2'b11,1'b0,1'b0,qt4114e[31:16]}; 2'b01 : ngb200 = {2'b10,1'b1,qgdb1fe,qt4114e[15:0]}; default : ngb200 = 20'bxxxxxxxxxxxxxxxxxxxx; endcase\r
-end\r
-assign epae410[19:0] = aydea4b ? wya92c8[19:0] : {12'h000, rt749f1};\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign fnc8019 = (~kfa4f8f & vx27c7c) & pf74ba4;\r
-assign vv400ce = uv4b208 | dmf1f39;\r
-assign lfaa812 = me59045 ? vxa5d27 & ~pf74ba4 : facffb0 & ~qt7a94f & ~zzb0517 & ~cb8f9cb[3] & cb8f9cb[4];\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign ykef059 = (pff9acf >= 14'd64);\r
-\r
-\r
-\r
-\r
-assign wy15c82 = ((~gq88319) ? (lfaa812 & ~gq3e3e7) : 1'b0) | (zzb0517 & ~qi828be) | (dob2655 & ~ba932ab) | (vvc8b97 & ux7990 & lfaa812) | (pu3a20c & lfaa812);\r
-\r
-assign cz65043 = al4b56a | (zxcd67f & an8a74);\r
-\r
-\r
-assign nt2821d = gb44b50;\r
-assign al410ef = gb44b50 & ea437a9;\r
-\r
-\r
-assign ui43be4 = (~xl84bbc) ? hofec14 -14'd4 : fc83768;\r
-\r
-assign kf17a95 = 32'hffffffff;\r
-\r
-assign jc52b50 = ls35502;\r
-assign fp8bd30 = ~vi7ce5c & kfa4f8f;\r
-\r
-assign ks24554 = al4b56a | yk5c720;\r
-\r
-\r
-\r
-assign ri4632 = cz418c8 & ir90977 & wwcb8e4 & gq3e3e7 & ~(hd9b63f | xj45cbf);\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin gdab323 <= 1'b0; zkd5664 <= 1'b0; mrcc8e0 <= 14'b0; ldd22e2 <= 14'b0; bn8b8b7 <= 14'b0; me5c5be <= 1'b0; ux8420 <= 1'b0; uvc64a4 <= 1'b0; ps79d12 <= 1'b0; wwce893 <= 1'b0; bl74498 <= 1'b0; hqa24c6 <= 1'b0; ir23192 <= 1'b0; fa58e7c <= 1'b0; je2f3a2 <= 1'b0; psf1bd5 <= 14'd0; ux2382f <= 14'd0; bldd558 <= 9'd0; ykeaac7 <= 1'b0; wl12632 <= 1'b0; lqfe289 <= 1'b0; end else if (rxmac_clk_en) begin ykeaac7 <= mt29d2e & ~czf29dc; if (mt29d2e && !czf29dc) bldd558 <= ayf0d93; ir23192 <= fp8bd30; fa58e7c <= wl3971c; if (czf8071) je2f3a2 <= czf8071; else if (ls35502 && !czf8071) je2f3a2 <= 1'b0; else if (zzb0517) je2f3a2 <= 1'b0; else je2f3a2 <= qifcdb; hqa24c6 <= ~vk1f9b; if (rvba149 & zm1b29c) bl74498 <= rvba149; else if (mt29d2e) bl74498 <= 1'b0; else bl74498 <= hd9b63f; if (zke407e) wwce893 <= zke407e; else if (mt29d2e) wwce893 <= 1'b0; else wwce893 <= xjf36c7; lqfe289 <= al4b56a; if (do83310) ps79d12 <= kf8527a; if (yzab1cf) wl12632 <= ayd4a7c; uvc64a4 <= al4b56a | (yk5c720 & zm1b29c); mrcc8e0 <= tj137d0; zkd5664 <= dze3901; gdab323 <= vidf437; if (zxcd67f && !hqe313) ux8420 <= ls1bd49; me5c5be <= hqe313; if (zxcd67f && !hqe313) ldd22e2 <= pff9acf; if (hqe313) begin bn8b8b7 <= pff9acf + 14'd1; end else bn8b8b7 <= 14'd0; if (tw8c4df && xl84bbc && su49641) ux2382f <= fc83768 + 14'd1; if (pf7189b && !xl84bbc && an8a74) psf1bd5 <= hofec14 + 14'd1; else if (jpf60a2) psf1bd5 <= 14'd0; end\r
-end\r
-\r
-\r
-\r
-assign yzab1cf = jpf60a2;\r
-\r
-\r
-assign lf32525 = gd3cc84 ? (ks97e6b > (ho6322e + 14'd4)) : ks97e6b > ho6322e;\r
-assign mg9292f = (ks97e6b < 14'd64);\r
-assign hd94979 = wwff00e;\r
-\r
-assign gd1df20 = (ks97e6b[6:0] != 7'd64);\r
-assign icef904 = (hd3212e != qvbe0dd);\r
-assign oha4bce = vx1c80f ? 1'b0 : ux7990 | xl84bbc ? hd9be86 : hq25de7 ? 1'b0 : fca2f83;\r
-\r
-assign zm25e74 = ~(hd9b63f | xj45cbf | ng203f3);\r
-assign vx33b0[31] = zm145f0; \r
-assign vx33b0[30] = vx1c80f; \r
-assign vx33b0[29] = fn7e6d8; \r
-assign vx33b0[28] = nrd8ff0;\r
-assign vx33b0[27] = xjf36c7; \r
-assign vx33b0[26] = qifcdb; \r
-assign vx33b0[25] = xj45cbf; \r
-assign vx33b0[24] = ng203f3; \r
-assign vx33b0[23] = vk1f9b; \r
-assign vx33b0[22] = th4f83c; \r
-assign vx33b0[21] = by7c1e6; \r
-assign vx33b0[20] = ned0a4f; \r
-assign vx33b0[19] = uk2ef3a; \r
-assign vx33b0[18] = ux7990; \r
-assign vx33b0[17] = ir90977; \r
-assign vx33b0[16] = gd3cc84; \r
-assign vx33b0[15:14] = 2'b00;\r
-assign vx33b0[13:0] = ks97e6b; \r
-\r
-assign jr32885[0] = ir90977;\r
-assign jr32885[1] = xj45cbf;\r
-assign jr32885[2] = hd9b63f;\r
-assign jr32885[3] = zm145f0;\r
-assign jr32885[4] = vx1c80f;\r
-assign jr32885[5] = fn7e6d8;\r
-assign jr32885[6] = th4f83c;\r
-assign jr32885[7] = by7c1e6;\r
-assign jr32885[8] = gd3cc84;\r
-\r
-always@* begin zm1b29c<=mef0f02[0];ic77429<=mef0f02[1];rvba149<=mef0f02[2];ned0a4f<=mef0f02[3];kf8527a<=mef0f02[4];je896ad<={bn1ce70>>1,mef0f02[5]};al4b56a<=mef0f02[6];qt7a94f<=mef0f02[7];ayd4a7c<=mef0f02[8];lfa53e0<=mef0f02[9];gd29f07<=mef0f02[10];th4f83c<=mef0f02[11];by7c1e6<=mef0f02[12];kqe0f32<=mef0f02[13];ux7990<=mef0f02[14];gd3cc84<=mef0f02[15];hd3212e<={dm579a3>>1,mef0f02[16]};ir90977<=mef0f02[17];xl84bbc<=mef0f02[18];hq25de7<=mef0f02[19];uk2ef3a<=mef0f02[20];cm779d1<=mef0f02[21];qte7441<={lde68d9>>1,mef0f02[22]};pu3a20c<=mef0f02[23];wwd1063<=mef0f02[24];gq88319<=mef0f02[25];cz418c8<=mef0f02[26];ho6322e<={ldcd808>>1,mef0f02[27]};xl19172<=mef0f02[28];vvc8b97<=mef0f02[29];xj45cbf<=mef0f02[30];qg72ff8<={je2fc44>>1,mef0f02[31]};wy97fc0<=mef0f02[32];jrbfe01<=mef0f02[33];wwff00e<=mef0f02[34];czf8071<=mef0f02[35];tuc038c<=mef0f02[36];xy1c62<=mef0f02[37];hqe313<=mef0f02[38];pf7189b<=mef0f02[39];tw8c4df<=mef0f02[40];tj137d0<={ui43be4>>1,mef0f02[41]};hd9be86<=mef0f02[42];vidf437<=mef0f02[43];rgd0dd1<={rge410b>>1,mef0f02[44]};pu86e8a<=mef0f02[45];tj37452<=mef0f02[46];bnba297<={sw216d2>>1,mef0f02[47]};osd14bf<=mef0f02[48];wl8a5f9<=mef0f02[49];ks97e6b<={ldd22e2>>1,mef0f02[50]};pff9acf<={bn8b8b7>>1,mef0f02[51]};zxcd67f<=mef0f02[52];zx6b3fe<=mef0f02[53];me59ff6<=mef0f02[54];facffb0<=mef0f02[55];hofec14<={psf1bd5>>1,mef0f02[56]};jpf60a2<=mef0f02[57];zzb0517<=mef0f02[58];qi828be<=mef0f02[59];zm145f0<=mef0f02[60];fca2f83<=mef0f02[61];qvbe0dd<={mrcc8e0>>1,mef0f02[62]};fc83768<={ux2382f>>1,mef0f02[63]};tw1bb43<=mef0f02[64];pfdda1b<=mef0f02[65];ened0de<=mef0f02[66];ea686f5<=mef0f02[67];ea437a9<=mef0f02[68];ls1bd49<=mef0f02[69];aydea4b<=mef0f02[70];wya92c8<={ngb200>>1,mef0f02[71]};su49641<=mef0f02[72];uv4b208<=mef0f02[73];me59045<=mef0f02[74];qt4114e<={vx33b0>>1,mef0f02[75]};an8a74<=mef0f02[76];ld453a5<=mef0f02[77];mt29d2e<=mef0f02[78];czf29dc<=mef0f02[79];pf74ba4<=mef0f02[80];vxa5d27<=mef0f02[81];rt749f1<={ym1f042>>1,mef0f02[82]};kfa4f8f<=mef0f02[83];vx27c7c<=mef0f02[84];gq3e3e7<=mef0f02[85];dmf1f39<=mef0f02[86];cb8f9cb<={ym10823>>1,mef0f02[87]};vi7ce5c<=mef0f02[88];do83310<=mef0f02[89];wl3971c<=mef0f02[90];wwcb8e4<=mef0f02[91];yk5c720<=mef0f02[92];dze3901<=mef0f02[93];vx1c80f<=mef0f02[94];zke407e<=mef0f02[95];ng203f3<=mef0f02[96];vk1f9b<=mef0f02[97];qifcdb<=mef0f02[98];fn7e6d8<=mef0f02[99];xjf36c7<=mef0f02[100];hd9b63f<=mef0f02[101];qgdb1fe<=mef0f02[102];nrd8ff0<=mef0f02[103];pfc7f86<=mef0f02[104];ri3fc36<=mef0f02[105];ayf0d93<={jr32885>>1,mef0f02[106]};do86c99<={vx9442e>>1,mef0f02[107]};an364ca<=mef0f02[108];dob2655<=mef0f02[109];ba932ab<=mef0f02[110];end\r
-always@* begin ng1e1e0[2047]<=fa6c2d4;ng1e1e0[2046]<=pf616a3;ng1e1e0[2044]<=lsb51f;ng1e1e0[2040]<=vv5a8fb;ng1e1e0[2032]<=bn1ce70[0];ng1e1e0[2028]<=uvc64a4;ng1e1e0[2017]<=cb25ef;ng1e1e0[2008]<=lf32525;ng1e1e0[1988]<=vx33b0[0];ng1e1e0[1987]<=wl12f7d;ng1e1e0[1969]<=mg9292f;ng1e1e0[1928]<=iccec3e;ng1e1e0[1926]<=rva04bd;ng1e1e0[1891]<=hd94979;ng1e1e0[1809]<=rg761f0;ng1e1e0[1805]<=kf23e8c;ng1e1e0[1804]<=mg1550f;ng1e1e0[1803]<=yz172cd;ng1e1e0[1761]<=tuf111f;ng1e1e0[1748]<=gdab323;ng1e1e0[1734]<=oha4bce;ng1e1e0[1727]<=ym10823[0];ng1e1e0[1696]<=bn1c17d;ng1e1e0[1668]<=gd1df20;ng1e1e0[1633]<=do93194;ng1e1e0[1587]<=ps79d12;ng1e1e0[1571]<=lfb0f83;ng1e1e0[1562]<=gofa328;ng1e1e0[1560]<=hdaa879;ng1e1e0[1558]<=ignore_pkt;ng1e1e0[1555]<=zma2177;ng1e1e0[1550]<=dm579a3[0];ng1e1e0[1531]<=ri4632;ng1e1e0[1475]<=uk888fa;ng1e1e0[1464]<=bl7b98b;ng1e1e0[1448]<=mrcc8e0[0];ng1e1e0[1420]<=zm25e74;ng1e1e0[1406]<=vx84118;ng1e1e0[1345]<=yke0bef;ng1e1e0[1288]<=icef904;ng1e1e0[1287]<=fc2fbc1;ng1e1e0[1242]<=yx6f559;ng1e1e0[1218]<=gq98ca2;ng1e1e0[1131]<=yxf8210;ng1e1e0[1126]<=wwce893;ng1e1e0[1094]<=xw69ede;ng1e1e0[1076]<=zm8ca08;ng1e1e0[1072]<=en543cf;ng1e1e0[1069]<=qgcb360;ng1e1e0[1063]<=ie10bba;ng1e1e0[1056]<=ba2085b;ng1e1e0[1055]<=ykef059;ng1e1e0[1052]<=ec346cf;ng1e1e0[1028]<=ldd22e2[0];ng1e1e0[1023]<=ks10d54;ng1e1e0[1014]<=ir23192;ng1e1e0[994]<=vv400ce;ng1e1e0[902]<=of447d1;ng1e1e0[901]<=lde68d9[0];ng1e1e0[880]<=je2fc44[0];ng1e1e0[874]<=zkd5664;ng1e1e0[863]<=jc42104;ng1e1e0[848]<=ux2382f[0];ng1e1e0[834]<=ui43be4[0];ng1e1e0[816]<=wl12632;ng1e1e0[793]<=je2f3a2;ng1e1e0[777]<=vx9442e[0];ng1e1e0[775]<=hq2af34;ng1e1e0[765]<=lqfe289;ng1e1e0[732]<=wj6023b;ng1e1e0[643]<=aa5f78;ng1e1e0[621]<=sw8deab;ng1e1e0[565]<=ym1f042[0];ng1e1e0[528]<=rge410b[0];ng1e1e0[527]<=me7de0b;ng1e1e0[514]<=en5b48b;ng1e1e0[497]<=fnc8019;ng1e1e0[450]<=ksbcd1b;ng1e1e0[437]<=gb7aacc;ng1e1e0[431]<=ux8420;ng1e1e0[417]<=al410ef;ng1e1e0[408]<=hqa24c6;ng1e1e0[388]<=jr32885[0];ng1e1e0[387]<=ep855e6;ng1e1e0[366]<=tu6c047;ng1e1e0[310]<=psf1bd5[0];ng1e1e0[282]<=uif07c1;ng1e1e0[257]<=jeb691;ng1e1e0[248]<=ic59003;ng1e1e0[225]<=rgc0518;ng1e1e0[215]<=mec1084;ng1e1e0[208]<=nt2821d;ng1e1e0[204]<=bl74498;ng1e1e0[193]<=jp50abc;ng1e1e0[183]<=ldcd808[0];ng1e1e0[155]<=fcb7c6f;ng1e1e0[141]<=sw3e0f8;ng1e1e0[128]<=sw216d2[0];ng1e1e0[124]<=ngb200[0];ng1e1e0[112]<=xy1b3c0;ng1e1e0[104]<=cz65043;ng1e1e0[96]<=uxa1e7d;ng1e1e0[91]<=go59b01;ng1e1e0[78]<=wl85dd0;ng1e1e0[77]<=zz16f8d;ng1e1e0[64]<=zm42da;ng1e1e0[62]<=ea782c8;ng1e1e0[56]<=eca3678;ng1e1e0[38]<=kde2df1;ng1e1e0[19]<=me5c5be;ng1e1e0[9]<=bn8b8b7[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module qv835c (\r
- \r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- ks10d54, \r
- fa6c2d4, \r
- ls86aa0, \r
- pf616a3,\r
- lsb51f,\r
- vv5a8fb,\r
-\r
- \r
- uv70d29, \r
- hq8694d, \r
- ec34a6a, \r
- lfa5351, \r
- gd29a8f, \r
- rg4d47c, \r
- mr6a3e2, \r
- of51f14, \r
- sj8f8a4, \r
- tu7c524, \r
- ale2922, \r
- vk14915, \r
- ba25a85, \r
- qgcb360, \r
- go59b01, \r
- ldcd808, \r
- \r
- tu6c047, \r
- wj6023b, \r
-\r
- \r
- rx_fifo_full, \r
- ignore_pkt, \r
-\r
- \r
- gq3baab, \r
- ene2fd7, \r
- cb17ebd, \r
- bldd558, \r
- ykeaac7, \r
-\r
- \r
- su780a3, \r
- fa58e7c, \r
-\r
- \r
- rx_fifo_error, \r
- rx_stat_vector, \r
- rx_dbout, \r
- rx_write, \r
- rx_stat_en, \r
- rx_eof, \r
- rx_error \r
-);\r
-parameter gq97bed = 8;\r
-parameter mga30a3 = 14;\r
-parameter kf18518 = 16;\r
-parameter vvc28c5 = 16;\r
-parameter ofd97a2 = 20;\r
-parameter ykcbd15 = 32;\r
-parameter do838e7 = 32;\r
-parameter qt5e8a8 = 8;\r
-parameter psf4545 = 4;\r
-parameter kd44a33 = 8;\r
-parameter hocfb0b = 48;\r
-parameter bn28ceb = 2;\r
-parameter ic7d85a = 6;\r
-parameter vvec2d1 = 8;\r
-parameter bn1c73a = 9;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input ks10d54;\r
-input fa6c2d4;\r
-input pf616a3;\r
-input lsb51f;\r
-input vv5a8fb;\r
-input [gq97bed-1:0] ls86aa0;\r
-input [kd44a33-1:0] uv70d29;\r
-input [kd44a33-1:0] hq8694d;\r
-input [kd44a33-1:0] ec34a6a;\r
-input [kd44a33-1:0] lfa5351;\r
-input [kd44a33-1:0] gd29a8f;\r
-input [kd44a33-1:0] rg4d47c;\r
-input [kd44a33-1:0] mr6a3e2;\r
-input [kd44a33-1:0] of51f14;\r
-input [hocfb0b-1:0] sj8f8a4;\r
-input [kf18518-1:0] ba25a85;\r
-input [mga30a3-1:0] ldcd808;\r
-input tu7c524;\r
-input ale2922;\r
-input vk14915;\r
-input qgcb360;\r
-input go59b01;\r
-input tu6c047;\r
-input wj6023b;\r
-input ignore_pkt;\r
-input rx_fifo_full;\r
-output gq3baab;\r
-output [bn1c73a-1:0] bldd558;\r
-output ykeaac7;\r
-output cb17ebd;\r
-output [vvc28c5-1:0] ene2fd7;\r
-output [kf18518-1:0] su780a3;\r
-output fa58e7c;\r
-output rx_fifo_error;\r
-output [ykcbd15-1:0] rx_stat_vector;\r
-output [gq97bed-1:0] rx_dbout;\r
-output rx_write;\r
-output rx_stat_en;\r
-output rx_eof;\r
-output rx_error;\r
-parameter pdevice_family = "XP2";\r
-wire [gq97bed-1:0] xw791a7;\r
-wire [gq97bed-1:0] me469d7;\r
-wire sw34eb8;\r
-wire ria75c1;\r
-wire xy3ae0a;\r
-wire hbd7052;\r
-wire ngb8296;\r
-wire [mga30a3-1:0] qia590;\r
-wire ho52c81;\r
-wire ri9640b;\r
-wire pub205a;\r
-wire ux902d3;\r
-wire tj8169d;\r
-wire [kf18518-1:0] nr5a773;\r
-wire [vvc28c5-1:0] uk9dcf5;\r
-wire [mga30a3-1:0] by73d42;\r
-wire jr9ea12;\r
-wire kqf5097;\r
-wire baa84b8;\r
-wire ho425c3;\r
-wire kf12e1b;\r
-wire ou970dd;\r
-wire rib86e8;\r
-wire kdc3742;\r
-wire hq1ba15;\r
-wire xjdd0ab;\r
-wire uve855f;\r
-wire dm42afd;\r
-wire ym157ea;\r
-wire yzabf51;\r
-wire [do838e7-1:0] czfd46f;\r
-wire suea37c;\r
-wire kd51be0;\r
-wire [ofd97a2-1:0] mr6f821;\r
-wire rg7c10d;\r
-wire ice086a;\r
-wire gq3baab;\r
-wire ykeaac7;\r
-wire [bn1c73a-1:0] bldd558;\r
-wire [bn28ceb-1:0] sw82127;\r
-wire [ic7d85a-1:0] zz849c8;\r
-wire [qt5e8a8-1:0] nt27238;\r
-wire [qt5e8a8-1:0] thc8e34;\r
-wire fa471a7;\r
-wire vx38d3b;\r
-wire [ofd97a2-1:0] ec34efc;\r
-reg jea77e1;\r
-reg zm1b29c;\r
-reg ic77429;\r
-reg [gq97bed - 1 : 0] neca715;\r
-reg rvba149;\r
-reg ned0a4f;\r
-reg kf8527a;\r
-reg [kd44a33 - 1 : 0] gb6abd3;\r
-reg [kd44a33 - 1 : 0] ntaf4ee;\r
-reg [kd44a33 - 1 : 0] czd3bb5;\r
-reg [kd44a33 - 1 : 0] dmeed68;\r
-reg [kd44a33 - 1 : 0] dbb5a1a;\r
-reg [kd44a33 - 1 : 0] go686bb;\r
-reg [kd44a33 - 1 : 0] ie1aec9;\r
-reg [kd44a33 - 1 : 0] yzbb24e;\r
-reg [hocfb0b - 1 : 0] gbc93ad;\r
-reg ay49d6c;\r
-reg kd4eb61;\r
-reg ip75b0c;\r
-reg [kf18518 - 1 : 0] qv39dc8;\r
-reg gq88319;\r
-reg cz418c8;\r
-reg [mga30a3 - 1 : 0] ho6322e;\r
-reg xl19172;\r
-reg vvc8b97;\r
-reg wwde5f9;\r
-reg wwd1063;\r
-reg [gq97bed - 1 : 0] ym3e93a;\r
-reg [gq97bed - 1 : 0] epa4e83;\r
-reg zz2741c;\r
-reg je3a0e6;\r
-reg byd0733;\r
-reg vk8399b;\r
-reg ph1ccda;\r
-reg [mga30a3 - 1 : 0] gd336b6;\r
-reg bn9b5b5;\r
-reg vidadae;\r
-reg end6d73;\r
-reg swb6b9d;\r
-reg phb5ce8;\r
-reg [kf18518 - 1 : 0] zk73a3c;\r
-reg [vvc28c5 - 1 : 0] qte8f11;\r
-reg [mga30a3 - 1 : 0] yz3c462;\r
-reg ofe2314;\r
-reg zm118a4;\r
-reg ba8c522;\r
-reg me62912;\r
-reg ng14891;\r
-reg kfa448a;\r
-reg zz22455;\r
-reg kf122ae;\r
-reg nt91574;\r
-reg oh8aba7;\r
-reg pf55d3c;\r
-reg anae9e6;\r
-reg bl74f35;\r
-reg lsa79af;\r
-reg [do838e7 - 1 : 0] fne6bdd;\r
-reg je35eef;\r
-reg zzaf77b;\r
-reg [ofd97a2 - 1 : 0] vvddef6;\r
-reg ykef7b6;\r
-reg hb7bdb0;\r
-reg [bn28ceb - 1 : 0] pff6c31;\r
-reg [ic7d85a - 1 : 0] ntb0c71;\r
-reg [qt5e8a8 - 1 : 0] co31c7b;\r
-reg [qt5e8a8 - 1 : 0] xj71ecf;\r
-reg gd8f67f;\r
-reg hb7b3fd;\r
-reg [ofd97a2 - 1 : 0] facff7c;\r
-reg [2047:0] ng1e1e0;\r
-wire [69:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 70,gd3c088 = 32'hfdffd42b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign me469d7 = ym3e93a;\r
-\r
-\r
-assign cb17ebd = phb5ce8;\r
-assign ene2fd7 = qte8f11;\r
-assign su780a3 = zk73a3c;\r
-\r
-\r
-\r
-\r
-assign sw82127 = vvddef6[19:18];\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-hd2df10 #( .gq97bed(gq97bed) ) sh5e340 ( .rxmac_clk(rxmac_clk), .rxmac_clk_en(rxmac_clk_en), .reset_n(jea77e1), .ks10d54(zm1b29c), .ls86aa0(neca715), .ls35502(nt91574), .lfaa812(pf55d3c), .kd54097(xw791a7), .rva04bd(sw34eb8), .cb25ef(ria75c1), .wl12f7d(xy3ae0a) );\r
-\r
-cm4cad9 #( .gq97bed(gq97bed), .mga30a3(mga30a3), .kf18518(kf18518), .vvc28c5(vvc28c5) ) sj3cedd ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(rxmac_clk_en), .bn1ce70(ym3e93a), .jc4d12d(anae9e6), .lfaa812(oh8aba7), .ykce1a5(bl74f35), .gb44b50(lsa79af), .ba25a85(qv39dc8), .ukf3ec(ba8c522), .zz22aa1(kf122ae), .jp50abc(hbd7052), .ep855e6(ec883a1), .hq2af34(ngb8296), .dm579a3(qia590), .ksbcd1b(jr9ea12), .lde68d9(by73d42), .ec346cf(ho52c81), .eca3678(pub205a), .xy1b3c0(ux902d3), .qtd9e02(uk9dcf5), .lqcf014(tj8169d), .su780a3(nr5a773), .rgc0518(kqf5097), .ir28c2(ri9640b) );\r
-\r
-xl8b21c #( .gq97bed(gq97bed), .hocfb0b(hocfb0b), .ic7d85a(ic7d85a), .vvec2d1(vvec2d1) ) kf361ee ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(rxmac_clk_en), .bn1ce70(ym3e93a), .cb25ef(je3a0e6), .lfaa812(oh8aba7), .ykce1a5(bl74f35), .uv70d29(gb6abd3), .hq8694d(ntaf4ee), .ec34a6a(czd3bb5), .lfa5351(dmeed68), .gd29a8f(dbb5a1a), .rg4d47c(go686bb), .mr6a3e2(ie1aec9), .of51f14(yzbb24e), .sj8f8a4(gbc93ad), .tu7c524(ay49d6c), .ale2922(kd4eb61), .vk14915(ip75b0c), .wla48aa(ntb0c71), .ks24554(mr65e50), .mg1550f(ho425c3), .hdaa879(kf12e1b), .en543cf(ou970dd), .uxa1e7d(rib86e8), .ukf3ec(baa84b8), .zz22aa1(kdc3742) );\r
-\r
-\r
-gd33aed #( .gq97bed(gq97bed), .mga30a3(mga30a3), .ofd97a2(ofd97a2), .ykcbd15(ykcbd15), .do838e7(do838e7), .bn1c73a(bn1c73a) ) xya83f4 ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(rxmac_clk_en), .ks10d54(zm1b29c), .fa6c2d4(ic77429), .pf616a3(rvba149), .lsb51f(ned0a4f), .vv5a8fb(kf8527a), .bn1ce70(ym3e93a), .cb25ef(je3a0e6), .wl12f7d(byd0733), .rva04bd(zz2741c), .mg1550f(me62912), .hdaa879(ng14891), .en543cf(kfa448a), .uxa1e7d(zz22455), .jp50abc(vk8399b), .ep855e6(ec883a1), .hq2af34(ph1ccda), .dm579a3(gd336b6), .ec346cf(bn9b5b5), .yz172cd(vidadae), .eca3678(end6d73), .xy1b3c0(swb6b9d), .rgc0518(zm118a4), .ksbcd1b(ofe2314), .lde68d9(yz3c462), .ignore_pkt(wwd1063), .qgcb360(gq88319), .go59b01(cz418c8), .ldcd808(ho6322e), .tu6c047(xl19172), .wj6023b(vvc8b97), .bl7b98b(db815d6), .lfaa812(xjdd0ab), .ykce1a5(ym157ea),\r
- .gq3baab(gq3baab), .bldd558(bldd558), .ykeaac7(ykeaac7), .fa58e7c(fa58e7c), .ls35502(hq1ba15), .yzab1cf(uve855f), .jc4d12d(dm42afd), .gb44b50(yzabf51), .epae410(mr6f821), .tu42b90(rg7c10d), .wy15c82(ice086a), .kf17a95(czfd46f), .ks24554(suea37c), .fp8bd30(qi5f6f), .jc52b50(kd51be0) );\r
-\r
-oub9ee6 mr6f2cc ( .pscf731(zz849c8), .bl7b98b(db815d6), .mrdcc5e(ym3e93a), .hbe62f4(je35eef), .uk317a6(mr65e50), .fp8bd30(qi5f6f), .uv5e986(zzaf77b), .vif4c35(fne6bdd), .oua61ab(rxmac_clk), .vk86ac3(jea77e1), .rxmac_clk_en(rxmac_clk_en) );\r
-\r
-uvd3c42 #( .gq97bed(gq97bed), .ofd97a2(ofd97a2), .ykcbd15(ykcbd15), .qt5e8a8(qt5e8a8), .psf4545(psf4545) ) uk3bde8 ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(rxmac_clk_en), .tu42b90(ykef7b6), .wy15c82(hb7bdb0), .epae410(pff6c31), .rx_fifo_full(wwde5f9), .ep90421(facff7c), .sw8210d(nt27238), .sw10869(thc8e34), .zz84348(fa471a7), .sw21a46(vx38d3b), .rx_fifo_error(rx_fifo_error), .rx_stat_vector(rx_stat_vector), .rx_dbout(rx_dbout), .rx_write(rx_write), .rx_stat_en(rx_stat_en), .rx_eof(rx_eof), .rx_error(rx_error) );\r
-\r
-pmi_ram_dp #(.pmi_wr_addr_depth(256), .pmi_wr_addr_width(8), .pmi_wr_data_width(20), .pmi_rd_addr_depth(256), .pmi_rd_addr_width(8), .pmi_rd_data_width(20), .pmi_regmode("noreg"), .pmi_gsr("disable"), .pmi_resetmode("sync"), .pmi_init_file("none"), .pmi_init_file_format("binary"), .pmi_family(pdevice_family), .module_type("pmi_ram_dp") )\r
-thc75fb (.Data(mr6f821), .WrAddress(nt27238), .RdAddress(thc8e34), .WrClock(rxmac_clk), .RdClock(rxmac_clk), .WrClockEn(1'b1), .RdClockEn(fa471a7 & rxmac_clk_en), .WE(vx38d3b), .Reset(1'b0), .Q(ec34efc) );\r
-always@* begin jea77e1<=mef0f02[0];zm1b29c<=mef0f02[1];ic77429<=mef0f02[2];neca715<={ls86aa0>>1,mef0f02[3]};rvba149<=mef0f02[4];ned0a4f<=mef0f02[5];kf8527a<=mef0f02[6];gb6abd3<={uv70d29>>1,mef0f02[7]};ntaf4ee<={hq8694d>>1,mef0f02[8]};czd3bb5<={ec34a6a>>1,mef0f02[9]};dmeed68<={lfa5351>>1,mef0f02[10]};dbb5a1a<={gd29a8f>>1,mef0f02[11]};go686bb<={rg4d47c>>1,mef0f02[12]};ie1aec9<={mr6a3e2>>1,mef0f02[13]};yzbb24e<={of51f14>>1,mef0f02[14]};gbc93ad<={sj8f8a4>>1,mef0f02[15]};ay49d6c<=mef0f02[16];kd4eb61<=mef0f02[17];ip75b0c<=mef0f02[18];qv39dc8<={ba25a85>>1,mef0f02[19]};gq88319<=mef0f02[20];cz418c8<=mef0f02[21];ho6322e<={ldcd808>>1,mef0f02[22]};xl19172<=mef0f02[23];vvc8b97<=mef0f02[24];wwde5f9<=mef0f02[25];wwd1063<=mef0f02[26];ym3e93a<={xw791a7>>1,mef0f02[27]};epa4e83<={me469d7>>1,mef0f02[28]};zz2741c<=mef0f02[29];je3a0e6<=mef0f02[30];byd0733<=mef0f02[31];vk8399b<=mef0f02[32];ph1ccda<=mef0f02[33];gd336b6<={qia590>>1,mef0f02[34]};bn9b5b5<=mef0f02[35];vidadae<=mef0f02[36];end6d73<=mef0f02[37];swb6b9d<=mef0f02[38];phb5ce8<=mef0f02[39];zk73a3c<={nr5a773>>1,mef0f02[40]};qte8f11<={uk9dcf5>>1,mef0f02[41]};yz3c462<={by73d42>>1,mef0f02[42]};ofe2314<=mef0f02[43];zm118a4<=mef0f02[44];ba8c522<=mef0f02[45];me62912<=mef0f02[46];ng14891<=mef0f02[47];kfa448a<=mef0f02[48];zz22455<=mef0f02[49];kf122ae<=mef0f02[50];nt91574<=mef0f02[51];oh8aba7<=mef0f02[52];pf55d3c<=mef0f02[53];anae9e6<=mef0f02[54];bl74f35<=mef0f02[55];lsa79af<=mef0f02[56];fne6bdd<={czfd46f>>1,mef0f02[57]};je35eef<=mef0f02[58];zzaf77b<=mef0f02[59];vvddef6<={mr6f821>>1,mef0f02[60]};ykef7b6<=mef0f02[61];hb7bdb0<=mef0f02[62];pff6c31<={sw82127>>1,mef0f02[63]};ntb0c71<={zz849c8>>1,mef0f02[64]};co31c7b<={nt27238>>1,mef0f02[65]};xj71ecf<={thc8e34>>1,mef0f02[66]};gd8f67f<=mef0f02[67];hb7b3fd<=mef0f02[68];facff7c<={ec34efc>>1,mef0f02[69]};end\r
-always@* begin ng1e1e0[2047]<=ks10d54;ng1e1e0[2046]<=fa6c2d4;ng1e1e0[2044]<=ls86aa0[0];ng1e1e0[2041]<=pf616a3;ng1e1e0[2035]<=lsb51f;ng1e1e0[2029]<=czfd46f[0];ng1e1e0[2022]<=vv5a8fb;ng1e1e0[2011]<=suea37c;ng1e1e0[1996]<=uv70d29[0];ng1e1e0[1974]<=kd51be0;ng1e1e0[1945]<=hq8694d[0];ng1e1e0[1943]<=rib86e8;ng1e1e0[1922]<=rx_fifo_full;ng1e1e0[1901]<=mr6f821[0];ng1e1e0[1842]<=ec34a6a[0];ng1e1e0[1839]<=kdc3742;ng1e1e0[1797]<=ignore_pkt;ng1e1e0[1791]<=fa471a7;ng1e1e0[1778]<=ho425c3;ng1e1e0[1776]<=ldcd808[0];ng1e1e0[1759]<=zz849c8[0];ng1e1e0[1755]<=rg7c10d;ng1e1e0[1637]<=lfa5351[0];ng1e1e0[1631]<=hq1ba15;ng1e1e0[1622]<=of51f14[0];ng1e1e0[1546]<=xw791a7[0];ng1e1e0[1535]<=vx38d3b;ng1e1e0[1531]<=ym157ea;ng1e1e0[1509]<=kf12e1b;ng1e1e0[1504]<=tu6c047;ng1e1e0[1471]<=nt27238[0];ng1e1e0[1468]<=qgcb360;ng1e1e0[1463]<=ice086a;ng1e1e0[1391]<=vk14915;ng1e1e0[1312]<=qia590[0];ng1e1e0[1226]<=gd29a8f[0];ng1e1e0[1215]<=xjdd0ab;ng1e1e0[1197]<=sj8f8a4[0];ng1e1e0[1153]<=ri9640b;ng1e1e0[1044]<=me469d7[0];ng1e1e0[1037]<=tj8169d;ng1e1e0[1023]<=reset_n;ng1e1e0[1022]<=ec34efc[0];ng1e1e0[1014]<=yzabf51;ng1e1e0[971]<=ou970dd;ng1e1e0[961]<=wj6023b;ng1e1e0[895]<=thc8e34[0];ng1e1e0[889]<=baa84b8;ng1e1e0[888]<=go59b01;ng1e1e0[879]<=sw82127[0];ng1e1e0[811]<=mr6a3e2[0];ng1e1e0[765]<=dm42afd;ng1e1e0[734]<=ba25a85[0];ng1e1e0[695]<=ale2922;ng1e1e0[656]<=ngb8296;ng1e1e0[576]<=ho52c81;ng1e1e0[518]<=ux902d3;ng1e1e0[444]<=kqf5097;ng1e1e0[405]<=rg4d47c[0];ng1e1e0[382]<=uve855f;ng1e1e0[347]<=tu7c524;ng1e1e0[328]<=hbd7052;ng1e1e0[259]<=pub205a;ng1e1e0[222]<=jr9ea12;ng1e1e0[164]<=xy3ae0a;ng1e1e0[111]<=by73d42[0];ng1e1e0[82]<=ria75c1;ng1e1e0[55]<=uk9dcf5[0];ng1e1e0[41]<=sw34eb8;ng1e1e0[27]<=nr5a773[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module osc4e65 ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- of653ad, \r
- ep29d6d, \r
-\r
- cz4eb6c \r
- );\r
-parameter wj75b64 = 4;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input of653ad;\r
-input [wj75b64-1:0] ep29d6d;\r
-output cz4eb6c;\r
-reg aa82cd7;\r
-reg db166b8;\r
-reg [15:0] gqb35c6;\r
-reg [31:0] an9ae31;\r
-wire thd718d = (~aa82cd7 & of653ad);\r
-wire cz4eb6c = db166b8 & (gqb35c6 == 0);\r
-wire [31:0] tu73a4e;\r
-reg uk9d272;\r
-reg [wj75b64 - 1 : 0] ay49c8f;\r
-reg kd4e479;\r
-reg kq723cd;\r
-reg [15 : 0] hd91e69;\r
-reg [31 : 0] oh8f34e;\r
-reg rg79a75;\r
-reg [31 : 0] pfcd3ab;\r
-reg [2047:0] ng1e1e0;\r
-wire [7:0] mef0f02;\r
-\r
-localparam uk87811 = 8,gd3c088 = 32'hfdffd84b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) gqb35c6 <= 0; else if (txmac_clk_en) begin if (rg79a75) begin casex(ay49c8f) 4'h1: begin gqb35c6[15:0] <= {9'b00000000, oh8f34e[0], {6{1'b0}}}; end 4'h2: begin gqb35c6[15:0] <= {8'b00000000, oh8f34e[1:0], {6{1'b0}}}; end 4'h3: begin gqb35c6[15:0] <= {7'b0000000, oh8f34e[2:0], {6{1'b0}}}; end 4'h4: begin gqb35c6[15:0] <= {6'b000000, oh8f34e[3:0], {6{1'b0}}}; end 4'h5: begin gqb35c6[15:0] <= {5'b00000, oh8f34e[4:0], {6{1'b0}}}; end 4'h6: begin gqb35c6[15:0] <= {4'b0000, oh8f34e[5:0], {6{1'b0}}}; end 4'h7: begin gqb35c6[15:0] <= {3'b000, oh8f34e[6:0], {6{1'b0}}}; end 4'h8: begin gqb35c6[15:0] <= {2'b00, oh8f34e[7:0], {6{1'b0}}}; end 4'h9: begin gqb35c6[15:0] <= {1'b0, oh8f34e[8:0], {6{1'b0}}}; end default: begin gqb35c6[15:0] <= {oh8f34e[9:0], {6{1'b0}}}; end endcase end else if (kq723cd) begin gqb35c6 <= hd91e69 - {{15{1'b0}}, 1'b1}; end end end\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin aa82cd7 <= 1'b0; db166b8 <= 1'b0; end else if (txmac_clk_en) begin aa82cd7 <= uk9d272; db166b8 <= kd4e479; end end assign tu73a4e[31:1] = oh8f34e[30:0]; assign tu73a4e[0] = oh8f34e[1]^oh8f34e[5]^oh8f34e[6]^oh8f34e[31];\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin an9ae31 <= {32{1'b1}}; end else if (txmac_clk_en) begin an9ae31 <= pfcd3ab; end end \r
-\r
-always@* begin uk9d272<=mef0f02[0];ay49c8f<={ep29d6d>>1,mef0f02[1]};kd4e479<=mef0f02[2];kq723cd<=mef0f02[3];hd91e69<={gqb35c6>>1,mef0f02[4]};oh8f34e<={an9ae31>>1,mef0f02[5]};rg79a75<=mef0f02[6];pfcd3ab<={tu73a4e>>1,mef0f02[7]};end\r
-always@* begin ng1e1e0[2047]<=ep29d6d[0];ng1e1e0[2046]<=aa82cd7;ng1e1e0[2044]<=db166b8;ng1e1e0[2040]<=gqb35c6[0];ng1e1e0[2033]<=an9ae31[0];ng1e1e0[2019]<=thd718d;ng1e1e0[1991]<=tu73a4e[0];ng1e1e0[1023]<=of653ad;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module mr7f553 (\r
- os627fb, \r
- mrdcc5e,\r
- hbe62f4,\r
- uv5e986,\r
- vif4c35,\r
- oua61ab,\r
- txmac_clk_en,\r
- vk86ac3\r
- );\r
-output [31:0] os627fb;\r
-input [7:0] mrdcc5e;\r
-input [31:0] vif4c35;\r
-input hbe62f4;\r
-input uv5e986;\r
-input oua61ab;\r
-input txmac_clk_en;\r
-input vk86ac3;\r
-reg [31:0] zm3f362;\r
-wire [31:0] ps6c4ff;\r
-wire [31:0] os627fb;\r
-reg [7 : 0] bn13fd8;\r
-reg wl9fec7;\r
-reg dzd8f4b;\r
-reg [31 : 0] nrc7a5e;\r
-reg [31 : 0] db3d2f6;\r
-reg [31 : 0] dze97b6;\r
-reg [2047:0] ng1e1e0;\r
-wire [5:0] mef0f02;\r
-\r
-localparam uk87811 = 6,gd3c088 = 32'hfdffc70b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-assign os627fb[31] = ~db3d2f6[0];\r
-assign os627fb[30] = ~db3d2f6[1];\r
-assign os627fb[29] = ~db3d2f6[2];\r
-assign os627fb[28] = ~db3d2f6[3];\r
-assign os627fb[27] = ~db3d2f6[4];\r
-assign os627fb[26] = ~db3d2f6[5];\r
-assign os627fb[25] = ~db3d2f6[6];\r
-assign os627fb[24] = ~db3d2f6[7];\r
-assign os627fb[23] = ~db3d2f6[8];\r
-assign os627fb[22] = ~db3d2f6[9];\r
-assign os627fb[21] = ~db3d2f6[10];\r
-assign os627fb[20] = ~db3d2f6[11];\r
-assign os627fb[19] = ~db3d2f6[12];\r
-assign os627fb[18] = ~db3d2f6[13];\r
-assign os627fb[17] = ~db3d2f6[14];\r
-assign os627fb[16] = ~db3d2f6[15];\r
-assign os627fb[15] = ~db3d2f6[16];\r
-assign os627fb[14] = ~db3d2f6[17];\r
-assign os627fb[13] = ~db3d2f6[18];\r
-assign os627fb[12] = ~db3d2f6[19];\r
-assign os627fb[11] = ~db3d2f6[20];\r
-assign os627fb[10] = ~db3d2f6[21];\r
-assign os627fb[9] = ~db3d2f6[22];\r
-assign os627fb[8] = ~db3d2f6[23];\r
-assign os627fb[7] = ~db3d2f6[24];\r
-assign os627fb[6] = ~db3d2f6[25];\r
-assign os627fb[5] = ~db3d2f6[26];\r
-assign os627fb[4] = ~db3d2f6[27];\r
-assign os627fb[3] = ~db3d2f6[28];\r
-assign os627fb[2] = ~db3d2f6[29];\r
-assign os627fb[1] = ~db3d2f6[30];\r
-assign os627fb[0] = ~db3d2f6[31];\r
-\r
-always @ (posedge oua61ab or negedge vk86ac3)\r
-begin if (!vk86ac3) begin zm3f362 <= 32'hffffffff; end else if (txmac_clk_en) begin if (wl9fec7) begin zm3f362 <= dze97b6; end else if (dzd8f4b) begin zm3f362 <= nrc7a5e; end end\r
-end\r
-\r
-assign ps6c4ff[0] = db3d2f6[30] ^ bn13fd8[7] ^ bn13fd8[1] ^ db3d2f6[24];\r
-assign ps6c4ff[1] = db3d2f6[30] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25];\r
-assign ps6c4ff[2] = db3d2f6[30] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ db3d2f6[26] ^ bn13fd8[5];\r
-assign ps6c4ff[3] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ bn13fd8[6];\r
-assign ps6c4ff[4] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[7];\r
-assign ps6c4ff[5] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[2] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[6] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[7] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[24] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[8] = db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[0];\r
-assign ps6c4ff[9] = db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ db3d2f6[1];\r
-assign ps6c4ff[10] = db3d2f6[24] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[29] ^ bn13fd8[7] ^ db3d2f6[2];\r
-assign ps6c4ff[11] = db3d2f6[3] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ bn13fd8[7];\r
-assign ps6c4ff[12] = db3d2f6[30] ^ db3d2f6[4] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[13] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[5] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[14] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[6] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[28];\r
-assign ps6c4ff[15] = db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[2] ^ db3d2f6[7] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ db3d2f6[29];\r
-assign ps6c4ff[16] = db3d2f6[24] ^ bn13fd8[2] ^ bn13fd8[3] ^ db3d2f6[8] ^ db3d2f6[28] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[17] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[9] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[18] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[26] ^ bn13fd8[5] ^ db3d2f6[10];\r
-assign ps6c4ff[19] = db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[11];\r
-assign ps6c4ff[20] = db3d2f6[12] ^ bn13fd8[3] ^ db3d2f6[28];\r
-assign ps6c4ff[21] = db3d2f6[13] ^ bn13fd8[2] ^ db3d2f6[29];\r
-assign ps6c4ff[22] = db3d2f6[14] ^ db3d2f6[24] ^ bn13fd8[7];\r
-assign ps6c4ff[23] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[15] ^ db3d2f6[25] ^ bn13fd8[6] ^ bn13fd8[7];\r
-assign ps6c4ff[24] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ db3d2f6[16] ^ db3d2f6[26] ^ bn13fd8[5] ^ bn13fd8[6];\r
-assign ps6c4ff[25] = db3d2f6[26] ^ db3d2f6[17] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5];\r
-assign ps6c4ff[26] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[18] ^ db3d2f6[28] ^ bn13fd8[7];\r
-assign ps6c4ff[27] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ bn13fd8[2] ^ bn13fd8[3] ^ db3d2f6[28] ^ db3d2f6[19] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[28] = db3d2f6[30] ^ bn13fd8[1] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[5] ^ db3d2f6[29] ^ db3d2f6[20];\r
-assign ps6c4ff[29] = db3d2f6[30] ^ db3d2f6[21] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ bn13fd8[4] ^ db3d2f6[27];\r
-assign ps6c4ff[30] = db3d2f6[31] ^ db3d2f6[22] ^ bn13fd8[0] ^ bn13fd8[3] ^ db3d2f6[28];\r
-assign ps6c4ff[31] = db3d2f6[23] ^ bn13fd8[2] ^ db3d2f6[29];\r
-always@* begin bn13fd8<={mrdcc5e>>1,mef0f02[0]};wl9fec7<=mef0f02[1];dzd8f4b<=mef0f02[2];nrc7a5e<={vif4c35>>1,mef0f02[3]};db3d2f6<={zm3f362>>1,mef0f02[4]};dze97b6<={ps6c4ff>>1,mef0f02[5]};end\r
-always@* begin ng1e1e0[2047]<=hbe62f4;ng1e1e0[2046]<=uv5e986;ng1e1e0[2044]<=vif4c35[0];ng1e1e0[2040]<=zm3f362[0];ng1e1e0[2032]<=ps6c4ff[0];ng1e1e0[1023]<=mrdcc5e[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ng3abec ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- xjec4b9, \r
- ay625cf, \r
- sj12e78, \r
- aa973c5, \r
- ieb9e28, \r
- tucf141 \r
- );\r
-parameter ea78a0b = 5;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input xjec4b9;\r
-input sj12e78;\r
-input aa973c5;\r
-input [ea78a0b-1:0] ay625cf;\r
-output tucf141;\r
-output ieb9e28;\r
-reg [ea78a0b-1:0] cm531bb;\r
-reg [ea78a0b-1:0] yxc6ec0;\r
-reg nt37604;\r
-reg ieb9e28;\r
-reg pfd813d;\r
-reg hoc09ef;\r
-reg tucf141;\r
-parameter bn27bdb = 1'b0;\r
-parameter fp3dedf = 1'b1;\r
-wire [ea78a0b-1:0] bl7b7f8 = ay625cf - 5'd1;\r
-reg [ea78a0b-1:0] icff1cb;\r
-wire uvf8e59 = xjec4b9 & ~nt37604;\r
-reg ykcb37c;\r
-reg [ea78a0b - 1 : 0] dzcdf08;\r
-reg ip6f847;\r
-reg lq7c23d;\r
-reg [ea78a0b - 1 : 0] wl8f53;\r
-reg [ea78a0b - 1 : 0] bn3d4ea;\r
-reg kqea756;\r
-reg ww53ab0;\r
-reg gq9d581;\r
-reg [ea78a0b - 1 : 0] qg56049;\r
-reg [ea78a0b - 1 : 0] vx81246;\r
-reg ph9236;\r
-reg [2047:0] ng1e1e0;\r
-wire [11:0] mef0f02;\r
-\r
-localparam uk87811 = 12,gd3c088 = 32'hfdffe0cb;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-always @ (wl8f53 or vx81246) begin if(wl8f53 == vx81246) tucf141 = 1'b1; else tucf141 = 1'b0; end\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin pfd813d <= bn27bdb; icff1cb <= 6'b0; end else if (txmac_clk_en) begin pfd813d <= gq9d581; icff1cb <= qg56049; end end always @ (ww53ab0 or ykcb37c or tucf141) begin case(ww53ab0) bn27bdb: begin if(!ykcb37c) begin hoc09ef = bn27bdb; end else begin hoc09ef = fp3dedf; end end fp3dedf: begin if(tucf141) begin hoc09ef = bn27bdb; end else begin hoc09ef = fp3dedf; end end endcase end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin cm531bb <= 5'd0; end else if (txmac_clk_en) begin if(ip6f847) begin cm531bb <= 5'd0; end else if(gq9d581) begin cm531bb <= wl8f53 + 5'd1; end else begin cm531bb <= 5'd0; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin nt37604 <= 1'b0; end else if (txmac_clk_en) begin nt37604 <= ykcb37c; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) yxc6ec0 <= 5'd0; else if (txmac_clk_en) begin if( (ph9236 || ((bn3d4ea != vx81246) && (bn3d4ea != 5'd0)) ) && (ieb9e28 || !lq7c23d) ) yxc6ec0 <= bn3d4ea + 5'd1; else if(!ph9236) begin yxc6ec0 <= 5'd0; end end end\r
- always @ (dzcdf08 or bn3d4ea) begin case(dzcdf08) 5'd24: ieb9e28 = bn3d4ea[4]; 5'd27: ieb9e28 = bn3d4ea[4] & (|bn3d4ea[3:1]); 5'd30: ieb9e28 = bn3d4ea[4] & (|bn3d4ea[3:2]); default: ieb9e28 = 1'b0; endcase end\r
-always@* begin ykcb37c<=mef0f02[0];dzcdf08<={ay625cf>>1,mef0f02[1]};ip6f847<=mef0f02[2];lq7c23d<=mef0f02[3];wl8f53<={cm531bb>>1,mef0f02[4]};bn3d4ea<={yxc6ec0>>1,mef0f02[5]};kqea756<=mef0f02[6];ww53ab0<=mef0f02[7];gq9d581<=mef0f02[8];qg56049<={bl7b7f8>>1,mef0f02[9]};vx81246<={icff1cb>>1,mef0f02[10]};ph9236<=mef0f02[11];end\r
-always@* begin ng1e1e0[2047]<=ay625cf[0];ng1e1e0[2046]<=sj12e78;ng1e1e0[2044]<=aa973c5;ng1e1e0[2040]<=cm531bb[0];ng1e1e0[2033]<=yxc6ec0[0];ng1e1e0[2018]<=nt37604;ng1e1e0[1988]<=pfd813d;ng1e1e0[1929]<=hoc09ef;ng1e1e0[1811]<=bl7b7f8[0];ng1e1e0[1574]<=icff1cb[0];ng1e1e0[1101]<=uvf8e59;ng1e1e0[1023]<=xjec4b9;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module bn91cf5 (txmac_clk,\r
- ir3994e,\r
- txmac_clk_en, \r
- gof5dd7, \r
- anaeeb9, \r
- yk775cd, \r
- phbae69, \r
- vvd734e, \r
- ukb9a76, \r
- nrcd3b1, \r
- fa69d8e, \r
- kd4ec72, \r
- ho76394, \r
- irb1ca3, \r
- tx_fifoavail, \r
- os728ef, \r
- jr94778, \r
- gqa3bc7, \r
- sj1de39, \r
- ayef1cc, \r
- ui78e60, \r
- tucf141, \r
- gd3980f, \r
- encc07d, \r
- mr603ec, \r
- ng1f65, \r
- cz4eb6c, \r
- ieb9e28, \r
- ldecac1, \r
- gb6560e, \r
- qi2b075, \r
- tx_discfrm, \r
- mec1d43, \r
- xyea19, \r
- ip750ca, \r
- lsa8654, \r
- ic432a3, \r
- tj19519, \r
- neca8cf, \r
- xjec4b9, \r
- iea33d5, \r
- of653ad, \r
- bycf546, \r
- sh7aa33, \r
- rgd519c, \r
- twa8ce3, \r
- qg4671a, \r
- ep338d1, \r
- fc9c68c, \r
- hbe3463, \r
- uk1a31e, \r
- qgd18f0, \r
- hq8c780, \r
- jc63c02, \r
- pu1e013, \r
- cmf009a, \r
- qv804d0, \r
- ep29d6d, \r
- hd13425, \r
- oh9a12e, \r
- vid0974, \r
- xl84ba2, \r
- hq25d17, \r
- sj12e78, \r
- aa973c5, \r
- nga2e8e \r
- );\r
-parameter wl17473 = 48;\r
-parameter fpba39c = 16;\r
-parameter uid1ce7 = 8;\r
-parameter ph8e738 = 16;\r
-parameter zk739c7 = 32;\r
-parameter ri9ce3a = 14;\r
-parameter wj75b64 = 4;\r
-parameter xl38e94 = 22;\r
-parameter ldc74a7 = 13;\r
-parameter pu3a53f = 13'd6072;\r
-parameter zxd29fb = 8'h55;\r
-parameter hd94fdf = 8'hd5;\r
-parameter nga7efe = 8'h00;\r
-parameter vk3f7f3 = 8'h01;\r
-parameter tufbf9b = 8'h80;\r
-parameter zkdfcda = 8'hc2;\r
-parameter jcfe6d3 = 8'h00;\r
-parameter dzf369b = 8'h00;\r
-parameter db9b4df = 8'h01;\r
-parameter lqda6fe = 8'h88;\r
-parameter yxd37f2 = 8'h08;\r
-parameter vx9bf94 = 8'h00;\r
-input txmac_clk;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input gof5dd7;\r
-input anaeeb9;\r
-input yk775cd;\r
-input phbae69;\r
-input vvd734e;\r
-input ukb9a76;\r
-input [wl17473-1:0] nrcd3b1;\r
-input [fpba39c-1:0] fa69d8e;\r
-input [uid1ce7-1:0] kd4ec72;\r
-input ho76394;\r
-input irb1ca3;\r
-input tx_fifoavail;\r
-input os728ef;\r
-input gqa3bc7;\r
-input sj1de39;\r
-input [ph8e738-1:0] ayef1cc;\r
-input ui78e60;\r
-input tucf141;\r
-input [zk739c7-1:0] gd3980f;\r
-input encc07d;\r
-input mr603ec;\r
-input [uid1ce7:0] jr94778;\r
-input ng1f65;\r
-input cz4eb6c;\r
-input ieb9e28;\r
-input ldecac1;\r
-input gb6560e;\r
-output qi2b075;\r
-output tx_discfrm;\r
-output mec1d43;\r
-output xyea19;\r
-output ip750ca;\r
-output [uid1ce7-1:0] lsa8654;\r
-output ic432a3;\r
-output [uid1ce7-1:0] tj19519;\r
-output neca8cf;\r
-output xjec4b9;\r
-output iea33d5;\r
-output of653ad;\r
-output bycf546;\r
-output sh7aa33;\r
-output rgd519c;\r
-output twa8ce3;\r
-output qg4671a;\r
-output ep338d1;\r
-output fc9c68c;\r
-output hbe3463;\r
-output uk1a31e;\r
-output qgd18f0;\r
-output hq8c780;\r
-output jc63c02;\r
-output pu1e013;\r
-output cmf009a;\r
-output qv804d0;\r
-output [wj75b64-1:0] ep29d6d;\r
-output hd13425;\r
-output oh9a12e;\r
-output vid0974;\r
-output xl84ba2;\r
-output hq25d17;\r
-output sj12e78;\r
-output aa973c5;\r
-output nga2e8e;\r
-reg [4:0] pfd813d ;\r
-reg [4:0] hoc09ef;\r
-reg xjec4b9;\r
-reg mt236ce;\r
-reg je1b674;\r
-reg [uid1ce7-1:0] kdd9d10;\r
-reg [uid1ce7-1:0] pf74420;\r
-reg [uid1ce7-1:0] gq10832;\r
-reg [uid1ce7-1:0] lsa8654;\r
-reg qi2b075;\r
-reg lf32197;\r
-reg oh90cbf;\r
-reg ri865fc;\r
-reg ip750ca;\r
-reg ym97f1e;\r
-reg zzbf8f1;\r
-reg xjfc78e;\r
-reg [1:0] hbe3c76;\r
-reg [1:0] zm1e3b7;\r
-reg faf1dba;\r
-reg tj8edd3;\r
-reg mec1d43;\r
-reg xyea19;\r
-reg tx_discfrm;\r
-reg czd3c9f;\r
-reg fp9e4fd;\r
-reg czf27ee;\r
-reg ic432a3;\r
-reg iea33d5;\r
-reg vid0974;\r
-reg hd13425;\r
-reg oh9a12e;\r
-reg nga2e8e;\r
-reg [wj75b64-1:0] ep29d6d;\r
-reg cmf009a;\r
-reg pu1e013;\r
-reg qv804d0;\r
-reg of653ad;\r
-reg ld55e0b;\r
-reg [ldc74a7-1:0] go782f6;\r
-reg xl84ba2;\r
-reg hq25d17;\r
-reg sj12e78;\r
-reg rtf6015;\r
-reg lfb00af;\r
-reg kf8057e;\r
-reg aa973c5;\r
-reg [3:0] gq15fa4;\r
-reg hdafd20;\r
-reg fn7e907;\r
-reg [1:0] rgf483e;\r
-reg kfa41f3;\r
-reg xy20f9d;\r
-reg ux7cea;\r
-reg ec3e754;\r
-parameter pff3aa1 = 5'd0;\r
-parameter ou9d50e = 5'd1;\r
-parameter ykea871 = 5'd2;\r
-parameter kd54389 = 5'd3;\r
-parameter qva1c4d = 5'd4;\r
-parameter pue26c = 5'd5;\r
-parameter bl71363 = 5'd6;\r
-parameter hq89b1e = 5'd7;\r
-parameter ne4d8f3 = 5'd8;\r
-parameter jc6c79b = 5'd9;\r
-parameter tu63cdb = 5'd10;\r
-parameter ri1e6db = 5'd11;\r
-parameter vvf36da = 5'd12;\r
-parameter rv9b6d7 = 5'd13;\r
-parameter sudb6be = 5'd14;\r
-parameter aydb5f0 = 5'd15;\r
-parameter nedaf80 = 5'd16;\r
-parameter thd7c03 = 5'd17;\r
-parameter kfbe01f = 5'd18;\r
-parameter icf00fd = 5'd19;\r
-parameter mt807e8 = 5'd20;\r
-parameter vx3f44 = 5'd21;\r
-wire bycf546 = (pfd813d == pff3aa1) ? 1 : 0;\r
-wire sh7aa33 = (pfd813d == ou9d50e) ? 1 : 0;\r
-wire rgd519c = (pfd813d == ykea871) ? 1 : 0;\r
-wire twa8ce3 = (pfd813d == kd54389) ? 1 : 0;\r
-wire qg4671a = (pfd813d == qva1c4d) ? 1 : 0;\r
-wire fc9c68c = (pfd813d == pue26c) ? 1 : 0;\r
-wire ep338d1 = (pfd813d == bl71363) ? 1 : 0;\r
-wire hbe3463 = (pfd813d == hq89b1e) ? 1 : 0;\r
-wire uk1a31e = (pfd813d == ne4d8f3) ? 1 : 0;\r
-wire qgd18f0 = (pfd813d == jc6c79b) ? 1 : 0;\r
-wire qv90c78 = (pfd813d == tu63cdb) ? 1 : 0;\r
-wire hq8c780 = (pfd813d == ri1e6db) ? 1 : 0;\r
-wire sj23348 = (pfd813d == vvf36da) ? 1 : 0;\r
-wire by69136 = (pfd813d == rv9b6d7) ? 1 : 0;\r
-wire jc63c02 = (pfd813d == sudb6be) ? 1 : 0;\r
-wire rv9bb69 = (pfd813d == aydb5f0) ? 1 : 0;\r
-wire qg6d3f4 = (pfd813d == nedaf80) ? 1 : 0;\r
-wire zx7e856 = (pfd813d == thd7c03) ? 1 : 0;\r
-wire mgad95 = (go782f6 == pu3a53f);\r
-wire [uid1ce7-1:0] tj19519 = pf74420[7:0];\r
-wire neca8cf = tj8edd3;\r
-reg [2:0] xj4aae6;\r
-reg [5:0] jp55736;\r
-reg [7:0] irab9b7;\r
-reg kq5cdbd;\r
-reg rte6de8;\r
-reg cb36f47;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg pub7a3c;\r
-reg pubd1e2;\r
-reg uve8f12;\r
-reg zk47894;\r
-reg ux3c4a2;\r
-reg ipe2514;\r
-reg [wl17473 - 1 : 0] vx94525;\r
-reg [fpba39c - 1 : 0] ng1497b;\r
-reg [uid1ce7 - 1 : 0] tw25ed4;\r
-reg ng2f6a2;\r
-reg xj7b512;\r
-reg jcda897;\r
-reg kqd44bb;\r
-reg [uid1ce7 : 0] ir12eca;\r
-reg ym97655;\r
-reg uxbb2a8;\r
-reg [ph8e738 - 1 : 0] jccaa2d;\r
-reg bl5516a;\r
-reg vka8b57;\r
-reg [zk739c7 - 1 : 0] bn2d5d7;\r
-reg ip6aebf;\r
-reg lq575fd;\r
-reg vxbafea;\r
-reg rtd7f56;\r
-reg vxbfab7;\r
-reg qtfd5be;\r
-reg ayeadf4;\r
-reg [4 : 0] ww53ab0;\r
-reg [4 : 0] gq9d581;\r
-reg cbbe84a;\r
-reg tuf4254;\r
-reg [uid1ce7 - 1 : 0] rv9515;\r
-reg [uid1ce7 - 1 : 0] gb54576;\r
-reg [uid1ce7 - 1 : 0] ou15dab;\r
-reg sjaed58;\r
-reg ne76ac5;\r
-reg bnb562a;\r
-reg irab156;\r
-reg ho58ab4;\r
-reg rgc55a2;\r
-reg [1 : 0] hq2ad12;\r
-reg [1 : 0] cm56893;\r
-reg epb4499;\r
-reg fca24cc;\r
-reg gd12662;\r
-reg fc93314;\r
-reg xy998a2;\r
-reg qtcc512;\r
-reg [ldc74a7 - 1 : 0] ls144a1;\r
-reg xya250b;\r
-reg ux1285a;\r
-reg tj942d5;\r
-reg [3 : 0] kfa16af;\r
-reg xyb57d;\r
-reg nr5abeb;\r
-reg [1 : 0] rgd5f5f;\r
-reg rvafafa;\r
-reg ea7d7d7;\r
-reg jcebeb8;\r
-reg vv5f5c3;\r
-reg ykfae1e;\r
-reg pfd70f0;\r
-reg zmb8786;\r
-reg wjc3c32;\r
-reg vk1e194;\r
-reg [2 : 0] ykf0ca2;\r
-reg [5 : 0] ng86511;\r
-reg [7 : 0] hd3288b;\r
-reg fp9445e;\r
-reg baa22f7;\r
-reg zm117ba;\r
-reg [2047:0] ng1e1e0;\r
-wire [70:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 71,gd3c088 = 32'hfdffd48b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin pfd813d <= pff3aa1; cb36f47 <= 0; pf74420 <= 0; oh90cbf <= 0; fp9e4fd <= 0; tj8edd3 <= 0; xjfc78e <= 0; zm1e3b7 <= 0; gq10832 <= 0; ri865fc <= 0; czf27ee <= 0; lsa8654 <= 0; ip750ca <= 0; ic432a3 <= 0; iea33d5 <= 0; end else if (txmac_clk_en) begin iea33d5 <= uxbb2a8 & (bycf546 | sh7aa33) ? 1'b1 : ~uxbb2a8 ? 1'b0 : iea33d5; pfd813d <= gq9d581; cb36f47 <= ym97655; pf74420 <= rv9515; oh90cbf <= sjaed58; fp9e4fd <= gd12662; tj8edd3 <= epb4499; xjfc78e <= ho58ab4; zm1e3b7 <= hq2ad12; ri865fc <= ne76ac5 | irab156; czf27ee <= fc93314; if (rgc55a2 == 1) begin case (cm56893) 3: begin gq10832 <= bn2d5d7[7:0]; end 2: begin gq10832 <= bn2d5d7[15:8]; end 1: begin gq10832 <= bn2d5d7[23:16]; end 0: begin gq10832 <= bn2d5d7[31:24]; end endcase end else begin gq10832 <= gb54576; end lsa8654 <= ou15dab; ip750ca <= bnb562a; ic432a3 <= xy998a2; end end always @ (ww53ab0 or jcda897 or tw25ed4 or ng2f6a2 or zm117ba or pub7a3c or zk47894 or pubd1e2 or vka8b57 or uxbb2a8 or lq575fd or vxbafea or bl5516a or aa973c5 or uve8f12 or cbbe84a or kqd44bb or ip6aebf or tj942d5 or ir12eca or ep29d6d or vxbfab7 or qtfd5be or rvafafa or tuf4254 or ec3e754 or ux7cea or nr5abeb or oh9a12e or hd13425 or ayeadf4 or ykf0ca2 or baa22f7 or hd3288b) begin xjec4b9 = 0; kdd9d10 = 0; qi2b075 = 0; lf32197 = 0; ym97f1e = 0; cmf009a = 0; faf1dba = 0; hbe3c76 = 0; zzbf8f1 = 0; xyea19 = 0; tx_discfrm = 0; czd3c9f = 0; pu1e013 = 0; qv804d0 = 0; ld55e0b = 0; of653ad = 0; mec1d43 = 0; hq25d17 = 0; sj12e78 = 0; hdafd20 = 0; xy20f9d = 0;\r
- case (ww53ab0) pff3aa1: begin if(vka8b57) begin hoc09ef = ou9d50e; xjec4b9 = 1'b0; end else begin\r
-\r
-\r
- if(aa973c5 && !vxbfab7 && uve8f12) begin if(jcda897) begin hoc09ef = aydb5f0; end else begin hoc09ef = pff3aa1; end xjec4b9 = 1'b0; sj12e78 = 1'b1; end else begin hoc09ef = pff3aa1; xjec4b9 = 1'b1; end\r
-\r
-\r
- end end ou9d50e: begin\r
-\r
-\r
- if(pub7a3c) begin if(uve8f12) begin if (jcda897) begin if(!aa973c5 || vxbfab7) begin hoc09ef = ykea871; end else begin hoc09ef = aydb5f0; end end else begin hoc09ef = ou9d50e; end end else begin if( (jcda897 && (!uxbb2a8 || zm117ba)) || (pubd1e2 && bl5516a) ) begin hoc09ef = ykea871; end else begin hoc09ef = ou9d50e; end end end else begin hoc09ef = ou9d50e; end \r
-\r
-\r
-\r
- end \r
-\r
-\r
- aydb5f0: begin if(aa973c5) begin hoc09ef = aydb5f0; ld55e0b = 1'b1; sj12e78 = 1'b1; end else begin hoc09ef = nedaf80; end end\r
-\r
-\r
-\r
- nedaf80: begin if(vka8b57) begin hoc09ef = ykea871; xjec4b9 = 1'b0; end else begin\r
-\r
-\r
- if(!aa973c5 || vxbfab7) begin hoc09ef = nedaf80; xjec4b9 = 1'b1; end else begin hoc09ef = aydb5f0; xjec4b9 = 1'b0; sj12e78 = 1'b1; end\r
-\r
-\r
- end end\r
- ykea871: begin kdd9d10 = zxd29fb; lf32197 = 1; if(ykf0ca2 == 0) begin hoc09ef = kd54389; end else begin hoc09ef = ykea871; end end kd54389: begin kdd9d10 = hd94fdf; lf32197 = 1;\r
-\r
-\r
- if(uve8f12) begin if(tj942d5 || tuf4254) begin if(ep29d6d == 4'hf) hoc09ef = thd7c03; else begin hoc09ef = tu63cdb; end end else begin if(kqd44bb) begin hoc09ef = qva1c4d; end else begin pu1e013 = 1; hoc09ef = sudb6be; end end end else begin if(bl5516a && pubd1e2) hoc09ef = pue26c; else begin hoc09ef = qva1c4d; end end \r
-\r
-\r
- end qva1c4d: begin qi2b075 = 1; lf32197 = 1'b1; kdd9d10 = tw25ed4[7:0]; faf1dba = 1;\r
-\r
-\r
- if(qtfd5be) begin if(lq575fd) begin hoc09ef = bl71363; end else begin hoc09ef = ne4d8f3; end end else if(uve8f12) begin if(ip6aebf) begin cmf009a = 1'b1; end if(tj942d5 || cbbe84a) begin if(ip6aebf && (ep29d6d == 4'hf) ) begin hoc09ef = thd7c03; end else if(ip6aebf) begin hq25d17 = 1'b1; hoc09ef = tu63cdb; end else begin hoc09ef = jc6c79b; end end else if (ng2f6a2 && !zk47894) begin if(lq575fd && !vxbafea) begin hoc09ef = bl71363; end else begin hoc09ef = hq89b1e; end end else if (ng2f6a2 && zk47894) begin hoc09ef = kfbe01f; end else begin hoc09ef = qva1c4d; end end else begin if(ng2f6a2 && !zk47894) begin if(lq575fd && !vxbafea) begin hoc09ef = bl71363; end else begin hoc09ef = hq89b1e; end end else if(ng2f6a2 && zk47894) begin hoc09ef = kfbe01f; end else begin hoc09ef = qva1c4d; end end \r
-\r
-\r
- end \r
- pue26c: begin kdd9d10 = hd3288b; lf32197 = 1; faf1dba = 1; if(baa22f7) begin hoc09ef = hq89b1e; end else begin hoc09ef = pue26c; end end \r
- bl71363: begin lf32197 = 1; faf1dba = 1; kdd9d10 = nga7efe; \r
-\r
-\r
- if(uve8f12 && (tj942d5 || cbbe84a)) begin if(ep29d6d == 4'hf) begin hoc09ef = thd7c03; end else begin if(!qtfd5be) begin hq25d17 = 1'b1; hoc09ef = tu63cdb; end else begin hoc09ef = ne4d8f3; end end end else if(zk47894 && qtfd5be && ayeadf4) begin hoc09ef = jc6c79b; end else if(vxbafea) begin if(qtfd5be) begin hoc09ef = ne4d8f3; end else begin hoc09ef = hq89b1e; end end else begin hoc09ef = bl71363; end\r
-\r
-\r
- end hq89b1e: begin lf32197 = 1; zzbf8f1 = 1; case (ykf0ca2[1:0]) 3: begin hbe3c76 = 2'h3; end 2: begin hbe3c76 = 2'h2; end 1: begin hbe3c76 = 2'h1; end 0: begin hbe3c76 = 2'h0; end endcase\r
-\r
-\r
- if(uve8f12 && (tj942d5 || cbbe84a)) begin hoc09ef = jc6c79b; end else if (ykf0ca2[1:0] == 2'b00) begin hoc09ef = kfbe01f; end else begin hoc09ef = hq89b1e; end\r
-\r
-\r
- end\r
- kfbe01f: begin ym97f1e = 1;\r
-\r
-\r
- if(uve8f12 && (tj942d5 || cbbe84a)) begin hoc09ef = icf00fd; xy20f9d = 1; end else begin hoc09ef = vx3f44; end \r
-\r
-\r
- end \r
- vx3f44: begin\r
-\r
-\r
- if(uve8f12 && (tj942d5 || cbbe84a)) begin hoc09ef = icf00fd; xy20f9d = 1; ym97f1e = 1; end else begin xyea19 = 1; qv804d0 = 1; mec1d43 = 1; hoc09ef = pff3aa1; end \r
-\r
-\r
- end \r
-\r
-\r
-\r
- icf00fd: begin ym97f1e = 1; xy20f9d = 1; if(rvafafa) begin hoc09ef = mt807e8; end else begin hoc09ef = icf00fd; end end mt807e8: begin ym97f1e = 1; hoc09ef = pff3aa1; tx_discfrm = 1; mec1d43 = 1; qv804d0 = 1; end \r
-\r
-\r
-\r
- ne4d8f3: begin lf32197 = 1; zzbf8f1 = 1; hbe3c76 = 2'h3; czd3c9f = 1; if (ykf0ca2[1:0] == 2'b01) begin hoc09ef = jc6c79b; end else begin hoc09ef = ne4d8f3; end end\r
-\r
-\r
-\r
- thd7c03: begin lf32197 = 1; zzbf8f1 = 1; hbe3c76 = 2; czd3c9f = 0; hoc09ef = jc6c79b; end\r
-\r
-\r
-\r
- jc6c79b: begin lf32197 = 1;\r
-\r
-\r
- if(oh9a12e || hd13425) begin hdafd20 = 1; if(nr5abeb) begin czd3c9f = 0; tx_discfrm = 1; qv804d0 = 1; mec1d43 = 1; hoc09ef = pff3aa1; end else begin hoc09ef = jc6c79b; end end else begin zzbf8f1 = 1; hbe3c76 = 1; czd3c9f = 1; tx_discfrm = 1; qv804d0 = 1; mec1d43 = 1; hoc09ef = pff3aa1; end\r
-\r
-\r
- end\r
-\r
-\r
- tu63cdb: begin lf32197 = 1; hdafd20 = 1; if(nr5abeb) begin hoc09ef = ri1e6db; end else begin hoc09ef = tu63cdb; end end\r
- ri1e6db: begin case ({ec3e754, ux7cea}) 2'b00: begin xjec4b9 = 1; of653ad = 1; hoc09ef = ri1e6db; end 2'b01: begin xjec4b9 = 1; of653ad = 0; hoc09ef = ri1e6db; end 2'b10: begin xjec4b9 = 0; of653ad = 1; hoc09ef = ri1e6db; end 2'b11: begin xjec4b9 = 0; of653ad = 0; if(aa973c5) begin hoc09ef = vvf36da; ld55e0b = 1; end else begin hoc09ef = ykea871; end end endcase end vvf36da: begin if(aa973c5) begin hoc09ef = vvf36da; ld55e0b = 1; end else begin hoc09ef = rv9b6d7; xjec4b9 = 1; end end\r
-\r
-\r
-\r
- rv9b6d7: begin if(vka8b57) begin hoc09ef = ykea871; xjec4b9 = 0; end else begin\r
-\r
-\r
- if(aa973c5 && !vxbfab7 && uve8f12) begin hoc09ef = vvf36da; xjec4b9 = 0; sj12e78 = 1; end else begin hoc09ef = rv9b6d7; xjec4b9 = 1; end\r
-\r
-\r
- end end sudb6be: begin pu1e013 = 1; lf32197 = 1; kdd9d10 = ir12eca[7:0];\r
-\r
-\r
- if(cbbe84a) begin if(ep29d6d == 4'hf) hoc09ef = thd7c03; else begin hoc09ef = tu63cdb; hq25d17 = 1'b1; end end else if(kqd44bb) begin pu1e013 = 0; if(ir12eca[8]) hoc09ef = bl71363; else begin hoc09ef = qva1c4d; end end else begin hoc09ef = sudb6be; end\r
-\r
-\r
- end default: hoc09ef = pff3aa1;\r
- endcase end \r
-\r
-\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin mt236ce <= 0; end else if (txmac_clk_en) begin if(tj942d5 && (rgd519c || twa8ce3 || qg4671a || ep338d1 || hbe3463 || jc63c02)) begin mt236ce <= 1; end else if(bycf546 || hq8c780) begin mt236ce <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin je1b674 <= 0; end else if (txmac_clk_en) begin if(tj942d5 && rgd519c) begin je1b674 <= 1; end else if(bycf546 || hq8c780) begin je1b674 <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin ep29d6d <= 4'h0; end else if (txmac_clk_en) begin if( nr5abeb ) begin ep29d6d <= ep29d6d + 4'h1; end else if(bycf546) begin ep29d6d <= 4'h0; end end end\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin hd13425 <= 0; end else if (txmac_clk_en) begin if(tj942d5 && !ip6aebf && uve8f12) begin hd13425 <= 1; end else if(bycf546) begin hd13425 <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin vid0974 <= 0; end else if (txmac_clk_en) begin if(pfd70f0 || vv5f5c3) begin vid0974 <= 1; end else if(bycf546) begin vid0974 <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin oh9a12e <= 0; end else if (txmac_clk_en) begin if(wjc3c32) begin oh9a12e <= 1; end else if(bycf546) begin oh9a12e <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin xl84ba2 <= 0; end else if (txmac_clk_en) begin if(vk1e194) begin xl84ba2 <= 1; end else if(bycf546) begin xl84ba2 <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin go782f6 <= 13'd0; end else if (txmac_clk_en) begin if(qtcc512) begin go782f6 <= ls144a1 + 13'd1; end else begin go782f6 <= 13'd0; end end end\r
-\r
-\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin nga2e8e <= 0; end else if (txmac_clk_en) begin if(uk1a31e) begin nga2e8e <= 1; end else if(bycf546) begin nga2e8e <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin xj4aae6 <= 0; end else if (txmac_clk_en) begin if ((sh7aa33) || (zmb8786) || (hq8c780) || (ykfae1e)) begin xj4aae6 <= 6; end else if ((qg4671a) || (fc9c68c) || (ep338d1)) begin xj4aae6 <= 3; end else if (ykf0ca2 != 0) begin xj4aae6 <= ykf0ca2 - 1; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin irab9b7 <= 0; jp55736 <= 0; kq5cdbd <= 0; rte6de8 <= 0; end else if (txmac_clk_en) begin if (rgd519c) begin jp55736 <= 0; kq5cdbd <= 0; rte6de8 <= 0; end else begin jp55736 <= ng86511 + 1; if (ng86511 == 18) begin kq5cdbd <= 1; end if (ng86511 == 59) begin rte6de8 <= 1; end end case ({fp9445e,ng86511}) 0: begin irab9b7 <= vk3f7f3; end 1: begin irab9b7 <= tufbf9b; end 2: begin irab9b7 <= zkdfcda; end 3: begin irab9b7 <= jcfe6d3; end 4: begin irab9b7 <= dzf369b; end 5: begin irab9b7 <= db9b4df; end 6: begin irab9b7 <= vx94525[47:40]; end 7: begin irab9b7 <= vx94525[39:32]; end 8: begin irab9b7 <= vx94525[31:24]; end 9: begin irab9b7 <= vx94525[23:16]; end 10: begin irab9b7 <= vx94525[15:8]; end 11: begin irab9b7 <= vx94525[7:0]; end 12: begin irab9b7 <= lqda6fe; end 13: begin irab9b7 <= yxd37f2; end 14: begin irab9b7 <= ng1497b[15:8]; end 15: begin irab9b7 <= ng1497b[7:0]; end 16: begin irab9b7 <= jccaa2d[15:8]; end 17: begin irab9b7 <= jccaa2d[7:0]; end default: begin irab9b7 <= vx9bf94; end endcase end end\r
-\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin rgf483e <= 0; end else if (txmac_clk_en) begin if(ea7d7d7) begin rgf483e <= rgd5f5f + 1; end else begin rgf483e <= 0; end end end always @ (rgd5f5f) begin if(rgd5f5f == 2'b11) begin kfa41f3 = 1; end else begin kfa41f3 = 0; end end\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin gq15fa4 <= 4'h0; end else if (txmac_clk_en) begin if(xyb57d) begin gq15fa4 <= kfa16af + 4'h1; end else begin gq15fa4 <= 4'h0; end end end always @ (kfa16af) begin fn7e907 = (kfa16af == 4'h3) ? 1'b1 : 1'b0; end\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin rtf6015 <= 0; lfb00af <= 0; kf8057e <= 0; aa973c5 <= 0; end else if (txmac_clk_en) begin rtf6015 <= ipe2514; lfb00af <= ux3c4a2; kf8057e <= xya250b; aa973c5 <= ux1285a; end end \r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin ec3e754 = 0; end else if (txmac_clk_en) begin if(hq8c780 && vka8b57) begin ec3e754 = 1; end else if(rgd519c || vv5f5c3) begin ec3e754 = 0; end end end\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin ux7cea = 0; end else if (txmac_clk_en) begin if(hq8c780 && rtd7f56) begin ux7cea = 1; end else if(rgd519c || vv5f5c3) begin ux7cea = 0; end end end\r
-\r
-\r
-\r
-\r
-always@* begin pub7a3c<=mef0f02[0];pubd1e2<=mef0f02[1];uve8f12<=mef0f02[2];zk47894<=mef0f02[3];ux3c4a2<=mef0f02[4];ipe2514<=mef0f02[5];vx94525<={nrcd3b1>>1,mef0f02[6]};ng1497b<={fa69d8e>>1,mef0f02[7]};tw25ed4<={kd4ec72>>1,mef0f02[8]};ng2f6a2<=mef0f02[9];xj7b512<=mef0f02[10];jcda897<=mef0f02[11];kqd44bb<=mef0f02[12];ir12eca<={jr94778>>1,mef0f02[13]};ym97655<=mef0f02[14];uxbb2a8<=mef0f02[15];jccaa2d<={ayef1cc>>1,mef0f02[16]};bl5516a<=mef0f02[17];vka8b57<=mef0f02[18];bn2d5d7<={gd3980f>>1,mef0f02[19]};ip6aebf<=mef0f02[20];lq575fd<=mef0f02[21];vxbafea<=mef0f02[22];rtd7f56<=mef0f02[23];vxbfab7<=mef0f02[24];qtfd5be<=mef0f02[25];ayeadf4<=mef0f02[26];ww53ab0<={pfd813d>>1,mef0f02[27]};gq9d581<={hoc09ef>>1,mef0f02[28]};cbbe84a<=mef0f02[29];tuf4254<=mef0f02[30];rv9515<={kdd9d10>>1,mef0f02[31]};gb54576<={pf74420>>1,mef0f02[32]};ou15dab<={gq10832>>1,mef0f02[33]};sjaed58<=mef0f02[34];ne76ac5<=mef0f02[35];bnb562a<=mef0f02[36];irab156<=mef0f02[37];ho58ab4<=mef0f02[38];rgc55a2<=mef0f02[39];hq2ad12<={hbe3c76>>1,mef0f02[40]};cm56893<={zm1e3b7>>1,mef0f02[41]};epb4499<=mef0f02[42];fca24cc<=mef0f02[43];gd12662<=mef0f02[44];fc93314<=mef0f02[45];xy998a2<=mef0f02[46];qtcc512<=mef0f02[47];ls144a1<={go782f6>>1,mef0f02[48]};xya250b<=mef0f02[49];ux1285a<=mef0f02[50];tj942d5<=mef0f02[51];kfa16af<={gq15fa4>>1,mef0f02[52]};xyb57d<=mef0f02[53];nr5abeb<=mef0f02[54];rgd5f5f<={rgf483e>>1,mef0f02[55]};rvafafa<=mef0f02[56];ea7d7d7<=mef0f02[57];jcebeb8<=mef0f02[58];vv5f5c3<=mef0f02[59];ykfae1e<=mef0f02[60];pfd70f0<=mef0f02[61];zmb8786<=mef0f02[62];wjc3c32<=mef0f02[63];vk1e194<=mef0f02[64];ykf0ca2<={xj4aae6>>1,mef0f02[65]};ng86511<={jp55736>>1,mef0f02[66]};hd3288b<={irab9b7>>1,mef0f02[67]};fp9445e<=mef0f02[68];baa22f7<=mef0f02[69];zm117ba<=mef0f02[70];end\r
-always@* begin ng1e1e0[2047]<=anaeeb9;ng1e1e0[2046]<=yk775cd;ng1e1e0[2044]<=phbae69;ng1e1e0[2040]<=vvd734e;ng1e1e0[2032]<=ukb9a76;ng1e1e0[2018]<=faf1dba;ng1e1e0[2017]<=nrcd3b1[0];ng1e1e0[1989]<=tj8edd3;ng1e1e0[1987]<=fa69d8e[0];ng1e1e0[1931]<=czd3c9f;ng1e1e0[1927]<=kd4ec72[0];ng1e1e0[1865]<=ayef1cc[0];ng1e1e0[1859]<=gq10832[0];ng1e1e0[1844]<=hdafd20;ng1e1e0[1815]<=fp9e4fd;ng1e1e0[1806]<=ho76394;ng1e1e0[1682]<=ui78e60;ng1e1e0[1674]<=qv90c78;ng1e1e0[1671]<=lf32197;ng1e1e0[1640]<=fn7e907;ng1e1e0[1582]<=czf27ee;ng1e1e0[1565]<=irb1ca3;ng1e1e0[1488]<=kdd9d10[0];ng1e1e0[1485]<=kf8057e;ng1e1e0[1326]<=gb6560e;ng1e1e0[1317]<=tucf141;ng1e1e0[1300]<=sj23348;ng1e1e0[1297]<=xj4aae6[0];ng1e1e0[1295]<=oh90cbf;ng1e1e0[1233]<=rgf483e[0];ng1e1e0[1210]<=hoc09ef[0];ng1e1e0[1189]<=cz4eb6c;ng1e1e0[1172]<=encc07d;ng1e1e0[1116]<=ld55e0b;ng1e1e0[1105]<=rv9bb69;ng1e1e0[1092]<=irab9b7[0];ng1e1e0[1087]<=ym97f1e;ng1e1e0[1082]<=tx_fifoavail;ng1e1e0[1023]<=gof5dd7;ng1e1e0[1009]<=zm1e3b7[0];ng1e1e0[932]<=sj1de39;ng1e1e0[929]<=pf74420[0];ng1e1e0[922]<=gq15fa4[0];ng1e1e0[837]<=xy20f9d;ng1e1e0[744]<=je1b674;ng1e1e0[742]<=lfb00af;ng1e1e0[663]<=ldecac1;ng1e1e0[648]<=mgad95;ng1e1e0[605]<=pfd813d[0];ng1e1e0[594]<=ng1f65;ng1e1e0[586]<=gd3980f[0];ng1e1e0[552]<=by69136;ng1e1e0[547]<=cb36f47;ng1e1e0[546]<=jp55736[0];ng1e1e0[543]<=ri865fc;ng1e1e0[504]<=hbe3c76[0];ng1e1e0[466]<=gqa3bc7;ng1e1e0[418]<=kfa41f3;ng1e1e0[372]<=mt236ce;ng1e1e0[371]<=rtf6015;ng1e1e0[331]<=ieb9e28;ng1e1e0[324]<=zx7e856;ng1e1e0[297]<=mr603ec;ng1e1e0[273]<=rte6de8;ng1e1e0[252]<=xjfc78e;ng1e1e0[233]<=jr94778[0];ng1e1e0[185]<=go782f6[0];ng1e1e0[162]<=qg6d3f4;ng1e1e0[136]<=kq5cdbd;ng1e1e0[126]<=zzbf8f1;ng1e1e0[116]<=os728ef;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module pf61d16 ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- gof5dd7, \r
- anaeeb9, \r
- tx_sndpausreq, \r
- tx_sndpaustim, \r
- wyb3e52, \r
- ux9f290, \r
- tj19519, \r
- ho76394, \r
- by52133, \r
- bycf546, \r
- qg4671a, \r
- ep338d1,\r
- uk1a31e,\r
- hbe3463,\r
- hq8c780,\r
- jc63c02, \r
- fc9c68c,\r
- nga2e8e,\r
- qi2b075,\r
- xyea19,\r
- tx_discfrm,\r
- mec1d43,\r
- ep29d6d,\r
- hd13425,\r
- oh9a12e,\r
- xjc8b1c,\r
- vid0974,\r
- gd2c73f, \r
- vi639fd, \r
- ui78e60, \r
- ayef1cc, \r
- sj1de39, \r
- encc07d, \r
- mr603ec, \r
- ng1f65, \r
- tx_statvec, \r
- tx_staten, \r
- tx_done, \r
- qia3a3d, \r
- gb6560e, \r
- ldecac1 \r
- );\r
-parameter ph8e738 = 16;\r
-parameter uid1ce7 = 8;\r
-parameter wj75b64 = 4;\r
-parameter ri9ce3a = 14;\r
-parameter ho6c5b3 = 31;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input gof5dd7;\r
-input anaeeb9;\r
-input tx_sndpausreq;\r
-input [ph8e738-1:0] tx_sndpaustim;\r
-input wyb3e52;\r
-input ux9f290;\r
-input [uid1ce7-1:0] tj19519;\r
-input ho76394;\r
-input by52133;\r
-input bycf546;\r
-input qg4671a;\r
-input ep338d1;\r
-input uk1a31e;\r
-input hbe3463;\r
-input hq8c780;\r
-input jc63c02;\r
-input fc9c68c;\r
-input nga2e8e;\r
-input qi2b075;\r
-input xyea19;\r
-input tx_discfrm;\r
-input mec1d43;\r
-input [wj75b64-1:0] ep29d6d;\r
-input hd13425;\r
-input oh9a12e;\r
-input xjc8b1c;\r
-input vid0974;\r
-output gd2c73f;\r
-output vi639fd;\r
-output ui78e60;\r
-output [ph8e738-1:0] ayef1cc;\r
-output sj1de39;\r
-output encc07d;\r
-output mr603ec;\r
-output ng1f65;\r
-output [ho6c5b3-1:0] tx_statvec;\r
-output tx_staten;\r
-output tx_done;\r
-output qia3a3d;\r
-output gb6560e;\r
-output ldecac1;\r
-reg [ho6c5b3-1:0] tx_statvec;\r
-reg ui78e60;\r
-reg [ph8e738-1:0] ayef1cc;\r
-reg sj1de39;\r
-reg ps5d2df;\r
-reg [ri9ce3a-1:0] uv4b7df;\r
-reg of5befd;\r
-reg [uid1ce7-1:0] fafbf6a;\r
-reg gd2c73f;\r
-reg vi639fd;\r
-reg shed49d ;\r
-reg of6a4ed ;\r
-reg tx_done ;\r
-reg qia3a3d;\r
-reg qi9db13 ;\r
-reg mred898;\r
-reg tx_staten ;\r
-reg yk62623;\r
-reg db13118;\r
-reg gq988c6;\r
-reg ldecac1;\r
-reg oh23180;\r
-reg an18c04;\r
-reg ofc6024;\r
-reg ng30125;\r
-reg an8092a;\r
-reg fc4955;\r
-reg sw24aab;\r
-reg fc25558;\r
-reg je2aac3;\r
-reg ng1f65;\r
-reg gb6560e;\r
-reg mr603ec;\r
-wire encc07d = mr603ec;\r
-wire bydf8eb;\r
-wire blfc75b = &tj19519;\r
-wire wl1d6f7 = ofc6024 & ng30125 & an8092a & fc4955 & sw24aab & fc25558;\r
-wire dz55311 = ~(|uv4b7df[13:6]);\r
-wire ww4c478 = ldecac1 | nga2e8e;\r
-wire [ho6c5b3-1:0] ww78015 = {dz55311, ep29d6d[3:0], oh9a12e, hd13425, xjc8b1c, vid0974, uv4b7df[13:0], gq988c6, oh23180 | je2aac3, ldecac1, bydf8eb, ww4c478, wl1d6f7, db13118 | an18c04, yk62623};\r
-wire je35187 = qg4671a | ep338d1 | fc9c68c;\r
-wire aa8748b = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & ~uv4b7df[2] & ~uv4b7df[1] & uv4b7df[0];\r
-wire gb5efc8 = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & ~uv4b7df[2] & uv4b7df[1] & ~uv4b7df[0];\r
-wire ui67dfc = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & ~uv4b7df[2] & uv4b7df[1] & uv4b7df[0];\r
-wire wj44d9d = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & uv4b7df[2] & ~uv4b7df[1] & ~uv4b7df[0];\r
-wire ww6d020 = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & uv4b7df[2] & ~uv4b7df[1] & uv4b7df[0];\r
-wire bl4f4d7 = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & uv4b7df[2] & uv4b7df[1] & ~uv4b7df[0];\r
-wire vvecbf5 = je35187 & (~(|uv4b7df[13:4])) & uv4b7df[3] & uv4b7df[2] & uv4b7df[1] & ~uv4b7df[0];\r
-wire yma3c6e = ~gq988c6 & ((|uv4b7df[13:11]) | (&uv4b7df[10:9]) | (uv4b7df[10] & uv4b7df[8] & (&uv4b7df[7:5]) & (uv4b7df[4] | (&uv4b7df[3:0]))));\r
-wire icced42 = (|uv4b7df[13:11]) | (&uv4b7df[10:9]) | (uv4b7df[10] & uv4b7df[8] & (&uv4b7df[7:4]) & ((|uv4b7df[3:2]) | (&uv4b7df[1:0])));\r
-reg pub7a3c;\r
-reg pubd1e2;\r
-reg end918e;\r
-reg [ph8e738 - 1 : 0] ay463af;\r
-reg ec31d79;\r
-reg lf8ebc9;\r
-reg [uid1ce7 - 1 : 0] dbaf275;\r
-reg ng2f6a2;\r
-reg alc9d72;\r
-reg kd4eb95;\r
-reg ip75cac;\r
-reg qvae565;\r
-reg su72b2c;\r
-reg oh95960;\r
-reg qiacb04;\r
-reg uv65820;\r
-reg wl2c104;\r
-reg uv60825;\r
-reg vk412c;\r
-reg ng20962;\r
-reg ri4b12;\r
-reg ls25893;\r
-reg [wj75b64 - 1 : 0] ay49c8f;\r
-reg an126a8;\r
-reg je93544;\r
-reg ep9aa22;\r
-reg xwd5115;\r
-reg pua88ab;\r
-reg [ri9ce3a - 1 : 0] vx22ad4;\r
-reg gq156a7;\r
-reg [uid1ce7 - 1 : 0] zx5a9cc;\r
-reg icd4e67;\r
-reg vka7338;\r
-reg ep399c2;\r
-reg ofcce15;\r
-reg qg670ad;\r
-reg rv38568;\r
-reg ldc2b46;\r
-reg ks15a36;\r
-reg lsad1b0;\r
-reg ic68d83;\r
-reg go46c18;\r
-reg yz360c0;\r
-reg phb0605;\r
-reg pu8302e;\r
-reg wl18173;\r
-reg lqc0b9d;\r
-reg ou5ceb;\r
-reg mg2e759;\r
-reg ne73ac8;\r
-reg ym9d642;\r
-reg byeb211;\r
-reg [ho6c5b3 - 1 : 0] jpc8451;\r
-reg zk4228e;\r
-reg xy11473;\r
-reg qv8a39b;\r
-reg ip51cdd;\r
-reg xl8e6ec;\r
-reg lq73767;\r
-reg ph9bb3b;\r
-reg jpdd9df;\r
-reg jpecefe;\r
-reg os677f6;\r
-reg [2047:0] ng1e1e0;\r
-wire [62:0] mef0f02;\r
-\r
-localparam uk87811 = 63,gd3c088 = 32'hfdffe44b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
- \r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin shed49d <= 1'b0; of6a4ed <= 1'b0; tx_done <= 1'b0; qia3a3d <= 1'b0; qi9db13 <= 1'b0; mred898 <= 1'b0; tx_staten <= 1'b0; end else if (txmac_clk_en) begin tx_done <= vka7338; of6a4ed <= icd4e67; shed49d <= ng20962; qia3a3d <= ri4b12; tx_staten <= ofcce15; mred898 <= ep399c2; qi9db13 <= ls25893; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin sj1de39 <= 1'b0; end else if (txmac_clk_en) begin if(lf8ebc9) begin sj1de39 <= 1'b0; end else if(pua88ab) begin sj1de39 <= pua88ab; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin uv4b7df <= 14'd0; ng1f65 <= 0; gb6560e <= 0; mr603ec <= 1; end else if (txmac_clk_en) begin if (vx22ad4[13:0] == 14'd58) begin ng1f65 <= 1; end else begin ng1f65 <= 0; end if (vx22ad4[13:0] == 14'd63) begin gb6560e <= 1; end else begin gb6560e <= 0; end if (ng1f65 == 1) begin mr603ec <= 0; end if(su72b2c) begin uv4b7df <= vx22ad4 + 14'd4; end else if(ip75cac || uv65820 || oh95960 || wl2c104 || qvae565) begin uv4b7df <= vx22ad4 + 14'd1; end else if(kd4eb95 || qiacb04) begin uv4b7df <= 14'd0; mr603ec <= 1; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin yk62623 <= 1'b0; db13118 <= 1'b0; end else if (txmac_clk_en) begin if (xy11473) begin if(dbaf275[0]) begin yk62623 <= 1'b0; db13118 <= 1'b1; end else begin yk62623 <= 1'b1; db13118 <= 1'b0; end end else if(kd4eb95) begin yk62623 <= 1'b0; db13118 <= 1'b0; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) ofc6024 <= 1'b0; else if (txmac_clk_en) begin if (xy11473) begin if(mg2e759) ofc6024 <= 1'b1; else ofc6024 <= 1'b0; end else if(kd4eb95) ofc6024 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) ng30125 <= 1'b0; else if (txmac_clk_en) begin if (qv8a39b) begin if(mg2e759) ng30125 <= 1'b1; else ng30125 <= 1'b0; end else if(kd4eb95) ng30125 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) an8092a <= 1'b0; else if (txmac_clk_en) begin if (ip51cdd) begin if(mg2e759) an8092a <= 1'b1; else an8092a <= 1'b0; end else if(kd4eb95) an8092a <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) fc4955 <= 1'b0; else if (txmac_clk_en) begin if (xl8e6ec) begin if(mg2e759) fc4955 <= 1'b1; else fc4955 <= 1'b0; end else if(kd4eb95) fc4955 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) sw24aab <= 1'b0; else if (txmac_clk_en) begin if (lq73767) begin if(mg2e759) sw24aab <= 1'b1; else sw24aab <= 1'b0; end else if(kd4eb95) sw24aab <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) fc25558 <= 1'b0; else if (txmac_clk_en) begin if (ph9bb3b) begin if(mg2e759) fc25558 <= 1'b1; else fc25558 <= 1'b0; end else if(kd4eb95) fc25558 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin gq988c6 <= 1'b0; je2aac3 <= 1'b0; end else if (txmac_clk_en) begin if(jpdd9df) begin if ((zx5a9cc == 8'h81) && (dbaf275 == 8'h00)) begin gq988c6 <= 1'b1; je2aac3 <= 1'b0; end else if ((zx5a9cc == 8'h88) && (dbaf275 == 8'h08)) begin gq988c6 <= 1'b0; je2aac3 <= 1'b1; end else begin gq988c6 <= 1'b0; je2aac3 <= 1'b0; end end else if(kd4eb95) begin gq988c6 <= 1'b0; je2aac3 <= 1'b0; end end end \r
- assign bydf8eb = jpecefe | os677f6;\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) ldecac1 <= 1'b0; else if (txmac_clk_en) begin if(ip75cac && alc9d72 && !(gq156a7 || ng2f6a2)) begin ldecac1 <= 1'b1; end else if(kd4eb95) ldecac1 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) oh23180 <= 1'b0; else if (txmac_clk_en) begin if(wl2c104) oh23180 <= 1'b1; else if(kd4eb95) oh23180 <= 1'b0 ; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) an18c04 <= 1'b0; else if (txmac_clk_en) begin if (oh95960 || su72b2c) begin an18c04 <= ks15a36; end end end \r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin gd2c73f <= 1'b0; vi639fd <= 1'b0; ps5d2df <= 1'b0; tx_statvec <= 31'd0; end else if (txmac_clk_en) begin gd2c73f <= pub7a3c; vi639fd <= pubd1e2; ps5d2df <= ec31d79; if (ls25893 == 1) begin tx_statvec <= jpc8451; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin of5befd <= 0; fafbf6a <= 0; end else if (txmac_clk_en) begin fafbf6a <= dbaf275; if(vk412c) begin of5befd <= ng2f6a2; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin ui78e60 <= 1'b0; ayef1cc <= 16'h0000; end else if (txmac_clk_en) begin if(wl2c104) ui78e60 <= 1'b0; else if(end918e) begin ui78e60 <= end918e; ayef1cc <= ay463af; end end end\r
-always@* begin pub7a3c<=mef0f02[0];pubd1e2<=mef0f02[1];end918e<=mef0f02[2];ay463af<={tx_sndpaustim>>1,mef0f02[3]};ec31d79<=mef0f02[4];lf8ebc9<=mef0f02[5];dbaf275<={tj19519>>1,mef0f02[6]};ng2f6a2<=mef0f02[7];alc9d72<=mef0f02[8];kd4eb95<=mef0f02[9];ip75cac<=mef0f02[10];qvae565<=mef0f02[11];su72b2c<=mef0f02[12];oh95960<=mef0f02[13];qiacb04<=mef0f02[14];uv65820<=mef0f02[15];wl2c104<=mef0f02[16];uv60825<=mef0f02[17];vk412c<=mef0f02[18];ng20962<=mef0f02[19];ri4b12<=mef0f02[20];ls25893<=mef0f02[21];ay49c8f<={ep29d6d>>1,mef0f02[22]};an126a8<=mef0f02[23];je93544<=mef0f02[24];ep9aa22<=mef0f02[25];xwd5115<=mef0f02[26];pua88ab<=mef0f02[27];vx22ad4<={uv4b7df>>1,mef0f02[28]};gq156a7<=mef0f02[29];zx5a9cc<={fafbf6a>>1,mef0f02[30]};icd4e67<=mef0f02[31];vka7338<=mef0f02[32];ep399c2<=mef0f02[33];ofcce15<=mef0f02[34];qg670ad<=mef0f02[35];rv38568<=mef0f02[36];ldc2b46<=mef0f02[37];ks15a36<=mef0f02[38];lsad1b0<=mef0f02[39];ic68d83<=mef0f02[40];go46c18<=mef0f02[41];yz360c0<=mef0f02[42];phb0605<=mef0f02[43];pu8302e<=mef0f02[44];wl18173<=mef0f02[45];lqc0b9d<=mef0f02[46];ou5ceb<=mef0f02[47];mg2e759<=mef0f02[48];ne73ac8<=mef0f02[49];ym9d642<=mef0f02[50];byeb211<=mef0f02[51];jpc8451<={ww78015>>1,mef0f02[52]};zk4228e<=mef0f02[53];xy11473<=mef0f02[54];qv8a39b<=mef0f02[55];ip51cdd<=mef0f02[56];xl8e6ec<=mef0f02[57];lq73767<=mef0f02[58];ph9bb3b<=mef0f02[59];jpdd9df<=mef0f02[60];jpecefe<=mef0f02[61];os677f6<=mef0f02[62];end\r
-always@* begin ng1e1e0[2047]<=anaeeb9;ng1e1e0[2046]<=tx_sndpausreq;ng1e1e0[2044]<=tx_sndpaustim[0];ng1e1e0[2040]<=wyb3e52;ng1e1e0[2033]<=ux9f290;ng1e1e0[2019]<=tj19519[0];ng1e1e0[1991]<=ho76394;ng1e1e0[1934]<=by52133;ng1e1e0[1929]<=bydf8eb;ng1e1e0[1898]<=jc63c02;ng1e1e0[1821]<=bycf546;ng1e1e0[1810]<=blfc75b;ng1e1e0[1749]<=fc9c68c;ng1e1e0[1707]<=xyea19;ng1e1e0[1666]<=uv4b7df[0];ng1e1e0[1630]<=ng30125;ng1e1e0[1595]<=qg4671a;ng1e1e0[1572]<=wl1d6f7;ng1e1e0[1506]<=fc25558;ng1e1e0[1450]<=nga2e8e;ng1e1e0[1440]<=vid0974;ng1e1e0[1384]<=oh9a12e;ng1e1e0[1370]<=ep29d6d[0];ng1e1e0[1366]<=tx_discfrm;ng1e1e0[1284]<=of5befd;ng1e1e0[1212]<=an8092a;ng1e1e0[1202]<=vvecbf5;ng1e1e0[1174]<=wj44d9d;ng1e1e0[1170]<=aa8748b;ng1e1e0[1142]<=ep338d1;ng1e1e0[1125]<=gq988c6;ng1e1e0[1097]<=dz55311;ng1e1e0[1041]<=shed49d;ng1e1e0[1023]<=gof5dd7;ng1e1e0[964]<=je2aac3;ng1e1e0[949]<=hq8c780;ng1e1e0[853]<=qi2b075;ng1e1e0[833]<=ps5d2df;ng1e1e0[815]<=ofc6024;ng1e1e0[753]<=sw24aab;ng1e1e0[720]<=xjc8b1c;ng1e1e0[714]<=icced42;ng1e1e0[692]<=hd13425;ng1e1e0[685]<=mec1d43;ng1e1e0[601]<=bl4f4d7;ng1e1e0[587]<=ui67dfc;ng1e1e0[585]<=je35187;ng1e1e0[562]<=db13118;ng1e1e0[520]<=fafbf6a[0];ng1e1e0[474]<=hbe3463;ng1e1e0[407]<=an18c04;ng1e1e0[376]<=fc4955;ng1e1e0[357]<=yma3c6e;ng1e1e0[300]<=ww6d020;ng1e1e0[293]<=gb5efc8;ng1e1e0[292]<=ww78015[0];ng1e1e0[281]<=yk62623;ng1e1e0[237]<=uk1a31e;ng1e1e0[203]<=oh23180;ng1e1e0[146]<=ww4c478;ng1e1e0[140]<=mred898;ng1e1e0[70]<=qi9db13;ng1e1e0[35]<=of6a4ed;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module su77480 ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
- yz803f5, \r
- ls1fac, \r
- oufd63, \r
- ux9f290 \r
- );\r
-parameter ph8e738 = 16;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input yz803f5;\r
-input ls1fac;\r
-input [ph8e738-1:0] oufd63;\r
-output ux9f290;\r
-reg [ph8e738-1:0] xl285a7;\r
-reg [5:0] by42d3f;\r
-reg pfd813d;\r
-reg hoc09ef;\r
-reg ux9f290;\r
-reg vk3f5eb;\r
-parameter bn27bdb = 1'b0;\r
-parameter fp3dedf = 1'b1;\r
-reg jebd6c7;\r
-reg xweb63a;\r
-reg [ph8e738 - 1 : 0] zxd8e94;\r
-reg [ph8e738 - 1 : 0] je3a537;\r
-reg [5 : 0] dzd29bb;\r
-reg ww53ab0;\r
-reg gq9d581;\r
-reg jr377f1;\r
-reg [2047:0] ng1e1e0;\r
-wire [7:0] mef0f02;\r
-\r
-localparam uk87811 = 8,gd3c088 = 32'hfdffd14b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin pfd813d <= bn27bdb; end else if (txmac_clk_en) begin pfd813d <= gq9d581; end end always @ (ww53ab0 or jebd6c7 or ux9f290) begin case(ww53ab0) bn27bdb: begin if(jebd6c7) begin hoc09ef = fp3dedf; end else begin hoc09ef = bn27bdb; end end fp3dedf: begin if(ux9f290) begin hoc09ef = bn27bdb; end else begin hoc09ef = fp3dedf; end end endcase end always @ (posedge ph27329 or negedge ir3994e) begin if (!ir3994e) begin xl285a7 <= 0; ux9f290 <= 0; end else if (txmac_clk_en) begin if (xweb63a == 1) begin xl285a7 <= zxd8e94; end else if(ww53ab0 == fp3dedf) begin if (jr377f1 == 1) begin xl285a7 <= je3a537 - 1; end end else begin xl285a7 <= zxd8e94; end if (je3a537 == 0) begin ux9f290 <= 1; end else begin ux9f290 <= 0; end end end always @ (posedge ph27329 or negedge ir3994e) begin if (!ir3994e) begin by42d3f <= 0; vk3f5eb <= 0; end else if (txmac_clk_en) begin if (jebd6c7 && !xweb63a) begin by42d3f <= dzd29bb + 1; end else begin by42d3f <= 0; end if ((dzd29bb == 6'h3e) && (!xweb63a)) begin vk3f5eb <= 1; end else begin vk3f5eb <= 0; end end end\r
-always@* begin jebd6c7<=mef0f02[0];xweb63a<=mef0f02[1];zxd8e94<={oufd63>>1,mef0f02[2]};je3a537<={xl285a7>>1,mef0f02[3]};dzd29bb<={by42d3f>>1,mef0f02[4]};ww53ab0<=mef0f02[5];gq9d581<=mef0f02[6];jr377f1<=mef0f02[7];end\r
-always@* begin ng1e1e0[2047]<=ls1fac;ng1e1e0[2046]<=oufd63[0];ng1e1e0[2044]<=xl285a7[0];ng1e1e0[2040]<=by42d3f[0];ng1e1e0[2033]<=pfd813d;ng1e1e0[2019]<=hoc09ef;ng1e1e0[1990]<=vk3f5eb;ng1e1e0[1023]<=yz803f5;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ntb5e33 (txmac_clk,\r
- ir3994e,\r
- txmac_clk_en,\r
- tx_discfrm,\r
- tx_fifodata, \r
- tx_fifoeof, \r
- tx_fifoempty, \r
- tx_fifoctrl, \r
- tx_macread, \r
- kd4ec72, \r
- ho76394, \r
- by52133, \r
- gqa3bc7, \r
- irb1ca3, \r
- qi2b075 \r
- );\r
-parameter uid1ce7 = 8;\r
-input txmac_clk;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input tx_discfrm;\r
-input [uid1ce7-1:0] tx_fifodata;\r
-input tx_fifoeof;\r
-input tx_fifoempty;\r
-input tx_fifoctrl;\r
-output tx_macread;\r
-output [uid1ce7-1:0] kd4ec72;\r
-output ho76394;\r
-output by52133;\r
-output gqa3bc7;\r
-output irb1ca3;\r
-input qi2b075;\r
-reg [uid1ce7+2:0] ym9de6f;\r
-reg [uid1ce7+2:0] ps79bc0;\r
-reg [uid1ce7+2:0] cz6f01f;\r
-reg [uid1ce7+2:0] fac07e0;\r
-reg [uid1ce7+2:0] gq1f816;\r
-reg [uid1ce7+2:0] sue058e;\r
-reg [uid1ce7+2:0] fp1638c;\r
-reg [uid1ce7+2:0] ph8e335;\r
-reg [uid1ce7+2:0] ls8cd7f;\r
-reg [uid1ce7+2:0] ri35fdb;\r
-reg [uid1ce7+2:0] kd7f6df;\r
-reg [uid1ce7+2:0] aydb7eb;\r
-reg [uid1ce7+2:0] jcdfac1;\r
-reg [uid1ce7+2:0] vieb05c;\r
-reg [uid1ce7+2:0] uic1713;\r
-reg fcb898;\r
-reg su5c4c2;\r
-wire [uid1ce7-1:0] kd4ec72;\r
-wire tx_macread;\r
-wire ho76394;\r
-wire by52133;\r
-wire gqa3bc7;\r
-wire irb1ca3;\r
-reg ri4b12;\r
-reg [uid1ce7 - 1 : 0] al7a68d;\r
-reg ipd346d;\r
-reg wl9a36c;\r
-reg god1b64;\r
-reg vk412c;\r
-reg [uid1ce7 + 2 : 0] dm6c808;\r
-reg [uid1ce7 + 2 : 0] hq20217;\r
-reg [uid1ce7 + 2 : 0] ux85da;\r
-reg [uid1ce7 + 2 : 0] wl176a2;\r
-reg [uid1ce7 + 2 : 0] neda8a5;\r
-reg [uid1ce7 + 2 : 0] lsa2959;\r
-reg [uid1ce7 + 2 : 0] zza565a;\r
-reg [uid1ce7 + 2 : 0] me596b8;\r
-reg [uid1ce7 + 2 : 0] xj5ae09;\r
-reg [uid1ce7 + 2 : 0] vkb827e;\r
-reg [uid1ce7 + 2 : 0] lf9f90;\r
-reg [uid1ce7 + 2 : 0] th7e43e;\r
-reg [uid1ce7 + 2 : 0] kf90fbd;\r
-reg [uid1ce7 + 2 : 0] co3ef60;\r
-reg [uid1ce7 + 2 : 0] dobd804;\r
-reg hbec023;\r
-reg en6011f;\r
-reg [2047:0] ng1e1e0;\r
-wire [22:0] mef0f02;\r
-\r
-localparam uk87811 = 23,gd3c088 = 32'hfdffd48b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-assign tx_macread = hbec023 & ~wl9a36c;\r
-assign kd4ec72 = dm6c808[uid1ce7-1:0];\r
-assign ho76394 = dm6c808[uid1ce7];\r
-assign by52133 = ~(hq20217[uid1ce7+2] | dobd804[uid1ce7+2]);\r
-assign gqa3bc7 = dm6c808[uid1ce7+1];\r
-assign irb1ca3 = dm6c808[uid1ce7+2];\r
-always @ (dm6c808 or hq20217 or ux85da or wl176a2 or neda8a5 or lsa2959 or zza565a or dobd804 or vk412c) begin casex ({zza565a[uid1ce7+2],lsa2959[uid1ce7+2], neda8a5[uid1ce7+2],wl176a2[uid1ce7+2], ux85da[uid1ce7+2],hq20217[uid1ce7+2], dm6c808[uid1ce7+2],vk412c}) 8'bxxxxxx0x, 8'bxxxxx011: begin ph8e335 = dobd804; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bxxxxx010, 8'bxxxx0111: begin ph8e335 = hq20217; ls8cd7f = dobd804; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bxxxx0110, 8'bxxx01111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = dobd804; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bxxx01110, 8'bxx011111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = dobd804; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bxx011110, 8'bx0111111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = dobd804; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bx0111110, 8'b01111111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = dobd804; vieb05c = 11'h000; end 8'bx1111110, 8'b11111111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = dobd804; end endcase\r
-end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin ym9de6f <= 11'h000; ps79bc0 <= 11'h000; cz6f01f <= 11'h000; fac07e0 <= 11'h000; gq1f816 <= 11'h000; sue058e <= 11'h000; fp1638c <= 11'h000; uic1713 <= 11'h000; fcb898 <= 0; su5c4c2 <= 0; end else if (txmac_clk_en) begin uic1713 <= {en6011f, god1b64, ipd346d, al7a68d}; if ((dm6c808[uid1ce7+2] == 0) || (vk412c == 1)) begin ym9de6f <= me596b8; end if ((hq20217[uid1ce7+2] == 0) || (vk412c == 1)) begin ps79bc0 <= xj5ae09; end if ((ux85da[uid1ce7+2] == 0) || (vk412c == 1)) begin cz6f01f <= vkb827e; end if ((wl176a2[uid1ce7+2] == 0) || (vk412c == 1)) begin fac07e0 <= lf9f90; end if ((neda8a5[uid1ce7+2] == 0) || (vk412c == 1)) begin gq1f816 <= th7e43e; end if ((lsa2959[uid1ce7+2] == 0) || (vk412c == 1)) begin sue058e <= kf90fbd; end if ((zza565a[uid1ce7+2] == 0) || (vk412c == 1)) begin fp1638c <= co3ef60; end case (hbec023) 1: begin if ((wl176a2[uid1ce7+2] == 1) || (neda8a5[uid1ce7+2] == 1) || (lsa2959[uid1ce7+2] == 1) || (zza565a[uid1ce7+2] == 1)) begin fcb898 <= 0; end end 0: begin if ((neda8a5[uid1ce7+2] == 0) && (lsa2959[uid1ce7+2] == 0) && (zza565a[uid1ce7+2] == 0)) begin fcb898 <= 1; end end endcase su5c4c2 <= tx_macread; if (ri4b12 == 1) begin uic1713[uid1ce7+2] <= 0; fp1638c[uid1ce7+2] <= 0; sue058e[uid1ce7+2] <= 0; gq1f816[uid1ce7+2] <= 0; fac07e0[uid1ce7+2] <= 0; cz6f01f[uid1ce7+2] <= 0; ps79bc0[uid1ce7+2] <= 0; ym9de6f[uid1ce7+2] <= 0; su5c4c2 <= 0; fcb898 <= 0; end end end\r
-always@* begin ri4b12<=mef0f02[0];al7a68d<={tx_fifodata>>1,mef0f02[1]};ipd346d<=mef0f02[2];wl9a36c<=mef0f02[3];god1b64<=mef0f02[4];vk412c<=mef0f02[5];dm6c808<={ym9de6f>>1,mef0f02[6]};hq20217<={ps79bc0>>1,mef0f02[7]};ux85da<={cz6f01f>>1,mef0f02[8]};wl176a2<={fac07e0>>1,mef0f02[9]};neda8a5<={gq1f816>>1,mef0f02[10]};lsa2959<={sue058e>>1,mef0f02[11]};zza565a<={fp1638c>>1,mef0f02[12]};me596b8<={ph8e335>>1,mef0f02[13]};xj5ae09<={ls8cd7f>>1,mef0f02[14]};vkb827e<={ri35fdb>>1,mef0f02[15]};lf9f90<={kd7f6df>>1,mef0f02[16]};th7e43e<={aydb7eb>>1,mef0f02[17]};kf90fbd<={jcdfac1>>1,mef0f02[18]};co3ef60<={vieb05c>>1,mef0f02[19]};dobd804<={uic1713>>1,mef0f02[20]};hbec023<=mef0f02[21];en6011f<=mef0f02[22];end\r
-always@* begin ng1e1e0[2047]<=tx_fifodata[0];ng1e1e0[2046]<=tx_fifoeof;ng1e1e0[2044]<=tx_fifoempty;ng1e1e0[2040]<=tx_fifoctrl;ng1e1e0[2032]<=qi2b075;ng1e1e0[2017]<=ym9de6f[0];ng1e1e0[1987]<=ps79bc0[0];ng1e1e0[1927]<=cz6f01f[0];ng1e1e0[1865]<=kd7f6df[0];ng1e1e0[1806]<=fac07e0[0];ng1e1e0[1682]<=aydb7eb[0];ng1e1e0[1565]<=gq1f816[0];ng1e1e0[1317]<=jcdfac1[0];ng1e1e0[1172]<=uic1713[0];ng1e1e0[1082]<=sue058e[0];ng1e1e0[1023]<=tx_discfrm;ng1e1e0[932]<=ri35fdb[0];ng1e1e0[594]<=su5c4c2;ng1e1e0[586]<=vieb05c[0];ng1e1e0[466]<=ls8cd7f[0];ng1e1e0[297]<=fcb898;ng1e1e0[233]<=ph8e335[0];ng1e1e0[116]<=fp1638c[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ep1d3ac ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- ksacba5, \r
- yx65d28, \r
- aa2e944, \r
- bl74a21, \r
-\r
- nta510f, \r
- xl2887f, \r
- yx443fe \r
- );\r
-parameter ks21ff4 = 6;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input ksacba5;\r
-input yx65d28;\r
-input aa2e944;\r
-input bl74a21;\r
-output [ks21ff4-1:0] nta510f;\r
-output [ks21ff4-1:0] xl2887f;\r
-output yx443fe;\r
-reg [ks21ff4-1:0] nta510f;\r
-reg [ks21ff4-1:0] xl2887f;\r
-wire yx443fe = (nta510f == xl2887f);\r
-reg ho73d57;\r
-reg fp9eaba;\r
-reg eaf55d7;\r
-reg hdaaeb8;\r
-reg [2047:0] ng1e1e0;\r
-wire [3:0] mef0f02;\r
-\r
-localparam uk87811 = 4,gd3c088 = 32'hfdffd30b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin nta510f <= 5'd0; end else if (txmac_clk_en) begin if(ho73d57 || fp9eaba) begin nta510f <= 5'd0; end else if(eaf55d7) begin nta510f <= nta510f + 5'd1; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin xl2887f <= 5'd0; end else if (txmac_clk_en) begin if(ho73d57) begin xl2887f <= 5'd0; end else if(hdaaeb8) begin xl2887f <= xl2887f + 5'd1; end end end\r
-always@* begin ho73d57<=mef0f02[0];fp9eaba<=mef0f02[1];eaf55d7<=mef0f02[2];hdaaeb8<=mef0f02[3];end\r
-always@* begin ng1e1e0[2047]<=yx65d28;ng1e1e0[2046]<=aa2e944;ng1e1e0[2044]<=bl74a21;ng1e1e0[1023]<=ksacba5;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module uid1f98 ( txmac_clk,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- \r
- gof5dd7, \r
- anaeeb9, \r
- phbae69, \r
- yk775cd, \r
- vk3f2df, \r
- vvf96fb, \r
- fa69d8e, \r
-\r
- \r
- tx_fifodata, \r
- tx_fifoeof, \r
- tx_fifoempty, \r
- tx_fifoavail, \r
- tx_sndpaustim, \r
- tx_sndpausreq, \r
- tx_fifoctrl, \r
-\r
- \r
- zk520c4, \r
- cb90622, \r
-\r
- \r
- ukb9a76, \r
- vvd734e, \r
-\r
- \r
- suc455c, \r
- \r
- \r
- tx_macread, \r
- tx_discfrm, \r
- tx_staten, \r
- tx_statvec, \r
- tx_done, \r
-\r
- \r
- ip750ca, \r
- lsa8654, \r
- ic432a3 \r
- );\r
-parameter pdevice_family = "XP2";\r
-parameter ea78a0b = 5;\r
-parameter wl17473 = 48;\r
-parameter fpba39c = 16;\r
-parameter uid1ce7 = 8;\r
-parameter ph8e738 = 16;\r
-parameter ho6c5b3 = 31;\r
-parameter zk739c7 = 32;\r
-parameter ri9ce3a = 14;\r
-parameter wj75b64 = 4;\r
-parameter ks21ff4 = 6;\r
-parameter xl38e94 = 22;\r
-parameter ldc74a7 = 13;\r
-parameter pu3a53f = 13'd6072;\r
-parameter zxd29fb = 8'h55;\r
-parameter hd94fdf = 8'hd5;\r
-parameter nga7efe = 8'h00;\r
-parameter vk3f7f3 = 8'h01;\r
-parameter tufbf9b = 8'h80;\r
-parameter zkdfcda = 8'hc2;\r
-parameter jcfe6d3 = 8'h00;\r
-parameter dzf369b = 8'h00;\r
-parameter db9b4df = 8'h01;\r
-parameter lqda6fe = 8'h88;\r
-parameter yxd37f2 = 8'h08;\r
-parameter vx9bf94 = 8'h00;\r
-input txmac_clk;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input gof5dd7;\r
-input anaeeb9;\r
-input phbae69;\r
-input yk775cd;\r
-input [ea78a0b-1:0] vk3f2df;\r
-input [wl17473-1:0] vvf96fb;\r
-input [fpba39c-1:0] fa69d8e;\r
-input [uid1ce7-1:0] tx_fifodata;\r
-input tx_fifoeof;\r
-input tx_fifoempty;\r
-input tx_fifoavail;\r
-input [ph8e738-1:0] tx_sndpaustim;\r
-input tx_sndpausreq;\r
-input tx_fifoctrl;\r
-input zk520c4;\r
-input [ph8e738-1:0] cb90622;\r
-input ukb9a76;\r
-input vvd734e;\r
-output suc455c;\r
-output tx_macread;\r
-output tx_discfrm;\r
-output tx_staten;\r
-output [ho6c5b3-1:0] tx_statvec;\r
-output tx_done;\r
-output ip750ca;\r
-output [uid1ce7-1:0] lsa8654;\r
-output ic432a3;\r
-wire [uid1ce7-1:0] kd4ec72;\r
-wire [ph8e738-1:0] ayef1cc;\r
-wire [zk739c7-1:0] gd3980f;\r
-wire encc07d;\r
-wire [uid1ce7-1:0] tj19519;\r
-wire [uid1ce7-1:0] lsa8654;\r
-wire [uid1ce7:0] jr94778;\r
-wire [wj75b64-1:0] ep29d6d;\r
-wire bycf546;\r
-wire sh7aa33;\r
-wire [ks21ff4-1:0] nr5a6ca;\r
-wire [ks21ff4-1:0] tj9b2b4;\r
-wire suc455c = bycf546 | sh7aa33;\r
-reg ohb4d51;\r
-reg pub7a3c;\r
-reg pubd1e2;\r
-reg zk47894;\r
-reg uve8f12;\r
-reg [ea78a0b - 1 : 0] xw695a0;\r
-reg [wl17473 - 1 : 0] cm5681e;\r
-reg [fpba39c - 1 : 0] ng1497b;\r
-reg [uid1ce7 - 1 : 0] al7a68d;\r
-reg ipd346d;\r
-reg wl9a36c;\r
-reg jcda897;\r
-reg [ph8e738 - 1 : 0] ay463af;\r
-reg end918e;\r
-reg god1b64;\r
-reg ipd9356;\r
-reg [ph8e738 - 1 : 0] ps4d5ad;\r
-reg ipe2514;\r
-reg ux3c4a2;\r
-reg [uid1ce7 - 1 : 0] tw25ed4;\r
-reg [ph8e738 - 1 : 0] jccaa2d;\r
-reg [zk739c7 - 1 : 0] bn2d5d7;\r
-reg ip6aebf;\r
-reg [uid1ce7 - 1 : 0] dbaf275;\r
-reg [uid1ce7 : 0] ir12eca;\r
-reg [wj75b64 - 1 : 0] ay49c8f;\r
-reg kd4eb95;\r
-reg lf81c3e;\r
-reg [ks21ff4 - 1 : 0] al70fbb;\r
-reg [ks21ff4 - 1 : 0] qi3eee8;\r
-reg [2047:0] ng1e1e0;\r
-wire [29:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 30,gd3c088 = 32'hfdffca8b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-ntb5e33 #( .uid1ce7(uid1ce7) ) lfb036d ( .txmac_clk (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .tx_discfrm (qia3a3d), .tx_fifodata (al7a68d), .tx_fifoeof (ipd346d), .tx_fifoempty (wl9a36c), .tx_fifoctrl (god1b64), .tx_macread (tx_macread), .kd4ec72 (kd4ec72), .ho76394 (ho76394), .by52133 (by52133), .gqa3bc7 (gqa3bc7), .irb1ca3 (irb1ca3), .qi2b075 (qi2b075) );\r
-bn91cf5 #( .wl17473( wl17473), .fpba39c(fpba39c), .uid1ce7(uid1ce7), .ph8e738(ph8e738), .zk739c7(zk739c7), .ri9ce3a(ri9ce3a), .wj75b64(wj75b64), .xl38e94(xl38e94), .ldc74a7(ldc74a7), .pu3a53f(pu3a53f), .zxd29fb(zxd29fb), .hd94fdf(hd94fdf), .nga7efe(nga7efe), .vk3f7f3(vk3f7f3), .tufbf9b(tufbf9b), .zkdfcda(zkdfcda), .jcfe6d3(jcfe6d3), .dzf369b(dzf369b), .db9b4df(db9b4df), .lqda6fe(lqda6fe), .yxd37f2(yxd37f2), .vx9bf94(vx9bf94) ) ph813b7 ( .txmac_clk (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .gof5dd7 (gd2c73f), .anaeeb9 (vi639fd), .yk775cd (uve8f12), .phbae69 (zk47894), .vvd734e (ux3c4a2), .ukb9a76 (ipe2514), .nrcd3b1 (cm5681e), .fa69d8e (ng1497b), .kd4ec72 (tw25ed4), .ho76394 (ho76394), .irb1ca3 (irb1ca3), .tx_fifoavail (jcda897), .os728ef (os728ef), .jr94778 (ir12eca), .gqa3bc7 (gqa3bc7), .sj1de39 (sj1de39), .ayef1cc (jccaa2d), .ui78e60 (ui78e60), .tucf141 (tucf141), .gd3980f (bn2d5d7), .encc07d (ip6aebf), .mr603ec (mr603ec), .ng1f65 (ng1f65), .cz4eb6c (cz4eb6c), .ieb9e28 (ieb9e28), .gb6560e (gb6560e), .ldecac1 (ldecac1), .qi2b075 (qi2b075), .tx_discfrm (tx_discfrm), .mec1d43 (mec1d43), .xyea19 (xyea19), .ip750ca (ip750ca), .lsa8654 (lsa8654), .ic432a3 (ic432a3), .tj19519 (tj19519), .neca8cf (neca8cf), .xjec4b9 (xjec4b9), .iea33d5 (iea33d5), .of653ad (of653ad), .bycf546 (bycf546), .sh7aa33 (sh7aa33), .rgd519c (rgd519c), .twa8ce3 (twa8ce3), .qg4671a (qg4671a), .ep338d1 (ep338d1), .fc9c68c (fc9c68c), .hbe3463 (hbe3463), .uk1a31e (uk1a31e), .qgd18f0 (qgd18f0), .hq8c780 (hq8c780), .jc63c02 (jc63c02), .pu1e013 (pu1e013), .cmf009a (cmf009a), .qv804d0 (qv804d0), .ep29d6d (ep29d6d), .hd13425 (hd13425), .oh9a12e (oh9a12e), .vid0974 (vid0974), .xl84ba2 (xl84ba2), .hq25d17 (hq25d17), .sj12e78 (sj12e78), .aa973c5 (aa973c5), .nga2e8e (nga2e8e) );\r
-\r
-pf61d16 #( .ph8e738(ph8e738), .uid1ce7(uid1ce7), .wj75b64(wj75b64), .ri9ce3a(ri9ce3a), .ho6c5b3(ho6c5b3) ) hbc8756 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en),\r
- .gof5dd7 (pub7a3c), .anaeeb9 (pubd1e2), .tx_sndpausreq (end918e), .tx_sndpaustim (ay463af), .wyb3e52 (ipd9356), .ux9f290 (ux9f290), .hq8c780 (hq8c780), .ep29d6d (ay49c8f), .hd13425 (hd13425), .oh9a12e (oh9a12e), .xjc8b1c (xl84ba2), .vid0974 (vid0974), .nga2e8e (nga2e8e), .bycf546 (kd4eb95), .qg4671a (qg4671a), .jc63c02 (jc63c02), .ep338d1 (ep338d1), .uk1a31e (uk1a31e), .hbe3463 (hbe3463), .fc9c68c (fc9c68c), .qi2b075 (qi2b075), .xyea19 (xyea19), .tx_discfrm (tx_discfrm), .mec1d43 (mec1d43), .tj19519 (dbaf275), .ho76394 (ho76394), .by52133 (by52133), .gd2c73f (gd2c73f), .vi639fd (vi639fd), .ui78e60 (ui78e60), .ayef1cc (ayef1cc), .sj1de39 (sj1de39), .encc07d (encc07d), .mr603ec (mr603ec), .ng1f65 (ng1f65), .tx_statvec (tx_statvec), .tx_staten (tx_staten), .tx_done (tx_done), .qia3a3d (qia3a3d), .gb6560e (gb6560e), .ldecac1 (ldecac1) );\r
-osc4e65 #( .wj75b64(wj75b64) ) ls11f27 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .of653ad (of653ad), .ep29d6d (ay49c8f), .cz4eb6c (cz4eb6c) );\r
-\r
-ng3abec #( .ea78a0b(ea78a0b) ) wy1f173 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .ay625cf (xw695a0), .xjec4b9 (xjec4b9), .sj12e78 (sj12e78), .aa973c5 (aa973c5), .ieb9e28 (ieb9e28), .tucf141 (tucf141) );\r
-su77480 #( .ph8e738(ph8e738) ) jr22521 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .yz803f5 (iea33d5), .ls1fac (ipd9356), .oufd63 (ps4d5ad), .ux9f290 (ux9f290) );\r
-mr7f553 byd04d0 ( .os627fb(gd3980f), .mrdcc5e (dbaf275), .hbe62f4 (neca8cf), .uv5e986 (kd4eb95), .vif4c35 (32'hffffffff), .oua61ab (txmac_clk), .vk86ac3 (ohb4d51), .txmac_clk_en (txmac_clk_en) ); ep1d3ac #( .ks21ff4(ks21ff4) ) dz5a743 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .ksacba5 (qv804d0), .yx65d28 (hq25d17), .aa2e944 (pu1e013), .bl74a21 (cmf009a), .nta510f (tj9b2b4), .xl2887f (nr5a6ca), .yx443fe (os728ef) );\r
-pmi_ram_dp #(.pmi_wr_addr_depth(64), .pmi_wr_addr_width(6), .pmi_wr_data_width(9), .pmi_rd_addr_depth(64), .pmi_rd_addr_width(6), .pmi_rd_data_width(9), .pmi_regmode("noreg"), .pmi_gsr("disable"), .pmi_resetmode("sync"), .pmi_init_file("none"), .pmi_init_file_format("binary"), .pmi_family(pdevice_family), .module_type("pmi_ram_dp") )\r
-thc75fb (.Data({ho76394, kd4ec72}), .WrAddress(nr5a6ca), .RdAddress(tj9b2b4), .WrClock(txmac_clk), .RdClock(txmac_clk), .WrClockEn(1'b1), .RdClockEn(txmac_clk_en), .WE(cmf009a), .Reset(1'b0), .Q(jr94778) );\r
-\r
- always@* begin ohb4d51<=mef0f02[0];pub7a3c<=mef0f02[1];pubd1e2<=mef0f02[2];zk47894<=mef0f02[3];uve8f12<=mef0f02[4];xw695a0<={vk3f2df>>1,mef0f02[5]};cm5681e<={vvf96fb>>1,mef0f02[6]};ng1497b<={fa69d8e>>1,mef0f02[7]};al7a68d<={tx_fifodata>>1,mef0f02[8]};ipd346d<=mef0f02[9];wl9a36c<=mef0f02[10];jcda897<=mef0f02[11];ay463af<={tx_sndpaustim>>1,mef0f02[12]};end918e<=mef0f02[13];god1b64<=mef0f02[14];ipd9356<=mef0f02[15];ps4d5ad<={cb90622>>1,mef0f02[16]};ipe2514<=mef0f02[17];ux3c4a2<=mef0f02[18];tw25ed4<={kd4ec72>>1,mef0f02[19]};jccaa2d<={ayef1cc>>1,mef0f02[20]};bn2d5d7<={gd3980f>>1,mef0f02[21]};ip6aebf<=mef0f02[22];dbaf275<={tj19519>>1,mef0f02[23]};ir12eca<={jr94778>>1,mef0f02[24]};ay49c8f<={ep29d6d>>1,mef0f02[25]};kd4eb95<=mef0f02[26];lf81c3e<=mef0f02[27];al70fbb<={nr5a6ca>>1,mef0f02[28]};qi3eee8<={tj9b2b4>>1,mef0f02[29]};end\r
-always@* begin ng1e1e0[2047]<=gof5dd7;ng1e1e0[2046]<=anaeeb9;ng1e1e0[2044]<=phbae69;ng1e1e0[2040]<=yk775cd;ng1e1e0[2032]<=vk3f2df[0];ng1e1e0[2017]<=vvf96fb[0];ng1e1e0[1987]<=fa69d8e[0];ng1e1e0[1926]<=tx_fifodata[0];ng1e1e0[1804]<=tx_fifoeof;ng1e1e0[1803]<=tj19519[0];ng1e1e0[1560]<=tx_fifoempty;ng1e1e0[1558]<=jr94778[0];ng1e1e0[1550]<=cb90622[0];ng1e1e0[1072]<=tx_fifoavail;ng1e1e0[1069]<=ep29d6d[0];ng1e1e0[1052]<=ukb9a76;ng1e1e0[1023]<=ir3994e;ng1e1e0[901]<=encc07d;ng1e1e0[775]<=zk520c4;ng1e1e0[732]<=tj9b2b4[0];ng1e1e0[450]<=gd3980f[0];ng1e1e0[387]<=tx_fifoctrl;ng1e1e0[366]<=nr5a6ca[0];ng1e1e0[225]<=ayef1cc[0];ng1e1e0[193]<=tx_sndpausreq;ng1e1e0[183]<=sh7aa33;ng1e1e0[112]<=kd4ec72[0];ng1e1e0[96]<=tx_sndpaustim[0];ng1e1e0[91]<=bycf546;ng1e1e0[56]<=vvd734e;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module fp8b349(\r
- \r
- hclk, \r
- reset_n, \r
-\r
- \r
- haddr, \r
- hdatain, \r
- hread_n, \r
- hwrite_n, \r
- hcs_n, \r
-\r
- \r
- hdataout, \r
- hready_n, \r
- hdataout_en_n, \r
-\r
- \r
- tx_en, \r
- vvcda9b, \r
- ui6d4df, \r
- vk3f2df, \r
-\r
- \r
- wj6023b, \r
- tu6c047, \r
- bydf307, \r
- go59b01, \r
- vk14915, \r
- ip60ebc, \r
- ep75e4,\r
- ls3af25,\r
- pfd792a,\r
- cobc957,\r
- xwe4ab9,\r
- tw255ca,\r
- ri2ae53, \r
- ale2922, \r
- qgcb360, \r
- ldcd808, \r
- kq53683, \r
-\r
- \r
- ba25a85, \r
- neda0c6, \r
- ned0632, \r
- yk775cd, \r
-\r
- \r
- aye5ebc, \r
-\r
- \r
- ene2fd7, \r
- cb17ebd, \r
- bldd558, \r
- ykeaac7, \r
- gq3baab \r
-);\r
-\r
-parameter oh29c1 = 8;\r
-\r
-parameter doa7062 = 8;\r
-parameter rv38312 = 15;\r
-parameter icc1896 = 15;\r
-parameter tjc4b1 = 15;\r
-parameter ay6258e = 8;\r
-parameter sj12c70 = 3;\r
-parameter ba96385 = 7;\r
-parameter sjb1c2a = 7;\r
-parameter tj8e155 = 15;\r
-parameter gb70aaf = 10;\r
-parameter an8557d = 4;\r
-parameter ba2abec = 10;\r
-parameter jp55f63 = 15;\r
-parameter bn1c73a = 8;\r
-parameter me7d8f7 = 47;\r
-input hclk;\r
-input reset_n;\r
-input [doa7062 - 1:0] haddr;\r
-input [oh29c1 - 1:0] hdatain;\r
-input hread_n;\r
-input hwrite_n;\r
-input hcs_n;\r
-output [oh29c1 - 1:0] hdataout;\r
-output hready_n;\r
-output hdataout_en_n;\r
-output yk775cd;\r
-output ale2922;\r
-output qgcb360;\r
-output [icc1896-2:0] ldcd808;\r
-output kq53683;\r
-output tx_en;\r
-output vvcda9b;\r
-output ui6d4df;\r
-output [an8557d:0] vk3f2df;\r
-input aye5ebc;\r
-input gq3baab;\r
-input [rv38312:0] ene2fd7;\r
-input cb17ebd;\r
-input [bn1c73a:0] bldd558;\r
-input ykeaac7;\r
-output wj6023b;\r
-output tu6c047;\r
-output [me7d8f7:0] neda0c6;\r
-output bydf307;\r
-output go59b01;\r
-output vk14915;\r
-output ned0632;\r
-output [sjb1c2a:0] ip60ebc;\r
-output [sjb1c2a:0] ep75e4;\r
-output [sjb1c2a:0] ls3af25;\r
-output [sjb1c2a:0] pfd792a;\r
-output [sjb1c2a:0] cobc957;\r
-output [sjb1c2a:0] xwe4ab9;\r
-output [sjb1c2a:0] tw255ca;\r
-output [sjb1c2a:0] ri2ae53;\r
-output [tjc4b1:0] ba25a85;\r
-\r
-reg xw734fa;\r
-reg gd9a7d3;\r
-reg kdd3e9c;\r
-reg qv9f4e5;\r
-reg [doa7062 - 1:0] kdd3961;\r
-reg [doa7062 - 1:0] cme586a;\r
-reg [doa7062 - 1:0] nr61a85;\r
-reg [doa7062 - 1:0] uv6a174;\r
-reg [tjc4b1:0] ba25a85;\r
-reg hready_n;\r
-reg [oh29c1 - 1:0] hdataout;\r
-reg hdataout_en_n;\r
-reg pu353e5;\r
-reg [oh29c1 - 1:0] fn4f950;\r
-reg [oh29c1 - 1:0] cme5433;\r
-reg [oh29c1 - 1:0] hb50cca;\r
-reg [oh29c1 - 1:0] gd332b3;\r
-reg [oh29c1 - 1:0] jccaceb;\r
-reg [1:0] yk5675a;\r
-reg swb3ad0;\r
-reg [ba96385:0] jceb401;\r
-reg [ba96385:0] tud0056;\r
-reg [ba96385:0] do159c;\r
-reg [ba96385:0] os56710;\r
-reg [ba96385:0] xy9c400;\r
-reg [ba96385:0] uk1001c;\r
-reg [ba96385:0] ou70c;\r
-reg [ba96385:0] nt1c306;\r
-reg rge1837;\r
-reg zzc1ba;\r
-reg [bn1c73a:0] db6eb4;\r
-reg [an8557d:0] ntbad37;\r
-reg [sj12c70:0] uxb4df5;\r
-reg [ay6258e:0] tj37d69;\r
-reg [icc1896:0] wwf5a74;\r
-reg [tj8e155:0] by69d0b;\r
-reg [tj8e155:0] nr742d4;\r
-reg [tj8e155:0] vkb535;\r
-wire [15:0] xj5a9ab;\r
-reg [rv38312:0] wya6af8;\r
-reg [rv38312:0] qvabe0a;\r
-reg zx5f055;\r
-reg gbf82ae;\r
-reg ykc1574;\r
-reg [oh29c1 - 1:0] jp55d00;\r
-reg epae806;\r
-reg hb74035;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg [doa7062 - 1 : 0] en51e07;\r
-reg [oh29c1 - 1 : 0] go781e5;\r
-reg zkc0f28;\r
-reg yz7943;\r
-reg mt3ca1c;\r
-reg yke50e5;\r
-reg [rv38312 : 0] cm4394f;\r
-reg tj1ca78;\r
-reg [bn1c73a : 0] ir29e31;\r
-reg jp4f18c;\r
-reg cm78c67;\r
-reg yxc6339;\r
-reg ou319cd;\r
-reg ls8ce69;\r
-reg su6734b;\r
-reg [doa7062 - 1 : 0] fncd2c5;\r
-reg [doa7062 - 1 : 0] wj4b173;\r
-reg [doa7062 - 1 : 0] lqc5cea;\r
-reg [doa7062 - 1 : 0] dm73a98;\r
-reg wy9d4c2;\r
-reg [oh29c1 - 1 : 0] ww53088;\r
-reg [oh29c1 - 1 : 0] jpc2201;\r
-reg [oh29c1 - 1 : 0] ec8807b;\r
-reg [oh29c1 - 1 : 0] ba1ec6;\r
-reg [oh29c1 - 1 : 0] dz7b199;\r
-reg [1 : 0] hbd8ccf;\r
-reg shc667e;\r
-reg [ba96385 : 0] hq99fad;\r
-reg [ba96385 : 0] nr7eb52;\r
-reg [ba96385 : 0] twad4b1;\r
-reg [ba96385 : 0] ps52c5c;\r
-reg [ba96385 : 0] irb171a;\r
-reg [ba96385 : 0] ea5c6a6;\r
-reg [ba96385 : 0] ie1a98e;\r
-reg [ba96385 : 0] yma6388;\r
-reg aa31c40;\r
-reg fp8e201;\r
-reg [bn1c73a : 0] qi8807e;\r
-reg [an8557d : 0] pu1f86;\r
-reg [sj12c70 : 0] ld7e198;\r
-reg [ay6258e : 0] ba86639;\r
-reg [icc1896 : 0] ks98e5d;\r
-reg [tj8e155 : 0] mt39747;\r
-reg [tj8e155 : 0] jc5d1e0;\r
-reg [tj8e155 : 0] ne4781c;\r
-reg [15 : 0] cb3c0e2;\r
-reg [rv38312 : 0] lf38a1;\r
-reg [rv38312 : 0] she2877;\r
-reg je143bd;\r
-reg ira1deb;\r
-reg doef5c;\r
-reg [oh29c1 - 1 : 0] pubd710;\r
-reg tueb882;\r
-reg ui5c413;\r
-reg [2047:0] ng1e1e0;\r
-wire [53:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 54,gd3c088 = 32'hfdffe30b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign ip60ebc = hq99fad[7:0];\r
-assign ep75e4 = nr7eb52[7:0];\r
-assign ls3af25 = twad4b1[7:0];\r
-assign pfd792a = ps52c5c[7:0];\r
-assign cobc957 = irb171a[7:0];\r
-assign xwe4ab9 = ea5c6a6[7:0];\r
-assign tw255ca = ie1a98e[7:0];\r
-assign ri2ae53 = yma6388[7:0];\r
-assign tx_en = ld7e198[3];\r
-assign vvcda9b = ld7e198[1];\r
-assign tu6c047 = ld7e198[2];\r
-assign neda0c6 = {mt39747,jc5d1e0,ne4781c};\r
-assign vk14915 = ba86639[0];\r
-assign kq53683 = ba86639[1];\r
-assign ui6d4df = ba86639[2];\r
-assign go59b01 = ba86639[3];\r
-assign bydf307 = ba86639[4];\r
-assign wj6023b = ba86639[6];\r
-assign ale2922 = ba86639[7];\r
-assign qgcb360 = ba86639[8];\r
-assign ldcd808 = ks98e5d[13:0];\r
-assign vk3f2df = (pu1f86 < 4) ? 1 : pu1f86 - 3;\r
-assign xj5a9ab = {5'b00000,ou319cd,qi8807e[8:0],su6734b};\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- assign yk775cd = ld7e198[0] ? 1'b0 : ba86639[5]; assign ned0632 = ld7e198[0];\r
-\r
-\r
-\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin kdd3961 <= 8'h0; cme586a <= 8'h0; nr61a85 <= 8'h0; uv6a174 <= 8'h0; zx5f055 <= 1'b1; gbf82ae <= 1'b1; ykc1574 <= 1'b1; jp55d00 <= 0; end else begin kdd3961 <= en51e07; cme586a <= fncd2c5; nr61a85 <= wj4b173; uv6a174 <= lqc5cea; zx5f055 <= mt3ca1c; gbf82ae <= zkc0f28; ykc1574 <= yz7943; jp55d00 <= go781e5; end\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) xw734fa <= 1'b0; else xw734fa <= cm78c67;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) gd9a7d3 <= 1'b0; else gd9a7d3 <= yxc6339;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) kdd3e9c <= 1'b0; else kdd3e9c <= yke50e5;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) qv9f4e5 <= 1'b0; else qv9f4e5 <= ls8ce69;\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) rge1837 <= 1'b0; else rge1837 <= jp4f18c;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) zzc1ba <= 1'b0; else zzc1ba <= aa31c40;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) db6eb4 <= 9'b000000000; else if (fp8e201) db6eb4 <= ir29e31;\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin wya6af8 <= 16'h00; end else if (tj1ca78) begin wya6af8 <= cm4394f; end\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin qvabe0a <= 16'h00; epae806 <= 1'b1; hb74035 <= 1'b1; end else begin qvabe0a <= lf38a1; epae806 <= wy9d4c2; hb74035 <= tueb882; end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin\r
- yk5675a <= 2'b00; jceb401 <= 8'h00; tud0056 <= 8'h00; do159c <= 8'h00; os56710 <= 8'h00; xy9c400 <= 8'h00; uk1001c <= 8'h00; ou70c <= 8'h00; nt1c306 <= 8'h00; ntbad37 <= 5'b01100; uxb4df5 <= 4'h0; tj37d69 <= 8'h0; wwf5a74 <= 16'd1518; by69d0b <= 16'h00; nr742d4 <= 16'h00; vkb535 <= 16'h00; hready_n <= 1'b1; ba25a85 <= 16'h0001; hdataout <= 0; hdataout_en_n <= 1; swb3ad0 <= 1; fn4f950 <= 0; cme5433 <= 0; hb50cca <= 0; gd332b3 <= 0; jccaceb <= 0; pu353e5 <= 1'b1; end else begin hdataout <= ww53088; hdataout_en_n <= shc667e; hready_n <= wy9d4c2; if (!wy9d4c2 || !tueb882) begin pu353e5 <= 1'b1; swb3ad0 <= 1'b1; end else if (!mt3ca1c && !je143bd && !yz7943 && !doef5c && wy9d4c2 && ui5c413 && tueb882) begin pu353e5 <= 1'b0; if (fncd2c5 == 8'h00) begin uxb4df5 <= pubd710; end else if (!ld7e198[3] && !ld7e198[2]) begin case(fncd2c5) 8'h02 : tj37d69[7:0] <= pubd710[7:0]; 8'h04 : wwf5a74[7:0] <= pubd710; 8'h08 : ntbad37[4:0] <= pubd710; 8'h0A : by69d0b[7:0] <= pubd710; 8'h0C : nr742d4[7:0] <= pubd710; 8'h0E : vkb535[7:0] <= pubd710; 8'h22 : jceb401[7:0] <= pubd710; 8'h24 : tud0056[7:0] <= pubd710; 8'h26 : do159c[7:0] <= pubd710; 8'h28 : os56710[7:0] <= pubd710; 8'h2A : xy9c400[7:0] <= pubd710; 8'h2C : uk1001c[7:0] <= pubd710; 8'h2E : ou70c[7:0] <= pubd710; 8'h30 : nt1c306[7:0] <= pubd710; 8'h34 : ba25a85[7:0] <= pubd710; 8'h03 : tj37d69[8] <= pubd710[0]; 8'h05 : wwf5a74[15:8] <= pubd710; 8'h0B : by69d0b[15:8] <= pubd710; 8'h0D : nr742d4[15:8] <= pubd710; 8'h0F : vkb535[15:8] <= pubd710; 8'h35 : ba25a85[15:8] <= pubd710; default : uxb4df5 <= ld7e198; endcase end end else if (!mt3ca1c && !je143bd && !zkc0f28 && !ira1deb && wy9d4c2 && fncd2c5[0] && ui5c413) begin swb3ad0 <= 1'b0; pu353e5 <= 1'b0; case(fncd2c5) 8'h03 : fn4f950 <= {7'h0,ba86639[8]}; 8'h05 : fn4f950 <= ks98e5d[15:8]; 8'h0B : fn4f950 <= mt39747[15:8]; 8'h0D : fn4f950 <= jc5d1e0[15:8]; 8'h0F : fn4f950 <= ne4781c[15:8]; 8'h13 : fn4f950 <= cb3c0e2[15:8]; default : fn4f950 <= 8'h0; endcase end else if (!mt3ca1c && !je143bd && !zkc0f28 && !ira1deb && wy9d4c2 && !fncd2c5[0] && ui5c413) begin swb3ad0 <= 1'b0; pu353e5 <= 1'b0; case(fncd2c5) 8'h00 : fn4f950 <= {4'b0000,ld7e198};\r
-\r
-\r
- 8'h02 : fn4f950 <= ba86639[7:0];\r
-\r
-\r
- 8'h04 : fn4f950 <= ks98e5d[7:0]; 8'h08 : fn4f950 <= {3'b000,pu1f86[4:0]}; 8'h0A : fn4f950 <= mt39747[7:0]; 8'h0C : fn4f950 <= jc5d1e0[7:0]; 8'h0E : fn4f950 <= ne4781c[7:0]; 8'h12 : fn4f950 <= cb3c0e2[7:0]; 8'h22 : fn4f950 <= hq99fad[7:0]; 8'h24 : fn4f950 <= nr7eb52[7:0]; 8'h26 : fn4f950 <= twad4b1[7:0]; 8'h28 : fn4f950 <= ps52c5c[7:0]; 8'h2A : fn4f950 <= irb171a[7:0]; 8'h2C : fn4f950 <= ea5c6a6[7:0]; 8'h2E : fn4f950 <= ie1a98e[7:0]; 8'h30 : fn4f950 <= yma6388[7:0]; 8'h32 : fn4f950 <= she2877[7:0]; 8'h34 : fn4f950 <= ba25a85[7:0]; default : fn4f950 <= 8'h0; endcase end end\r
-\r
-\r
-\r
-\r
-\r
-always@* begin en51e07<={haddr>>1,mef0f02[0]};go781e5<={hdatain>>1,mef0f02[1]};zkc0f28<=mef0f02[2];yz7943<=mef0f02[3];mt3ca1c<=mef0f02[4];yke50e5<=mef0f02[5];cm4394f<={ene2fd7>>1,mef0f02[6]};tj1ca78<=mef0f02[7];ir29e31<={bldd558>>1,mef0f02[8]};jp4f18c<=mef0f02[9];cm78c67<=mef0f02[10];yxc6339<=mef0f02[11];ou319cd<=mef0f02[12];ls8ce69<=mef0f02[13];su6734b<=mef0f02[14];fncd2c5<={kdd3961>>1,mef0f02[15]};wj4b173<={cme586a>>1,mef0f02[16]};lqc5cea<={nr61a85>>1,mef0f02[17]};dm73a98<={uv6a174>>1,mef0f02[18]};wy9d4c2<=mef0f02[19];ww53088<={fn4f950>>1,mef0f02[20]};jpc2201<={cme5433>>1,mef0f02[21]};ec8807b<={hb50cca>>1,mef0f02[22]};ba1ec6<={gd332b3>>1,mef0f02[23]};dz7b199<={jccaceb>>1,mef0f02[24]};hbd8ccf<={yk5675a>>1,mef0f02[25]};shc667e<=mef0f02[26];hq99fad<={jceb401>>1,mef0f02[27]};nr7eb52<={tud0056>>1,mef0f02[28]};twad4b1<={do159c>>1,mef0f02[29]};ps52c5c<={os56710>>1,mef0f02[30]};irb171a<={xy9c400>>1,mef0f02[31]};ea5c6a6<={uk1001c>>1,mef0f02[32]};ie1a98e<={ou70c>>1,mef0f02[33]};yma6388<={nt1c306>>1,mef0f02[34]};aa31c40<=mef0f02[35];fp8e201<=mef0f02[36];qi8807e<={db6eb4>>1,mef0f02[37]};pu1f86<={ntbad37>>1,mef0f02[38]};ld7e198<={uxb4df5>>1,mef0f02[39]};ba86639<={tj37d69>>1,mef0f02[40]};ks98e5d<={wwf5a74>>1,mef0f02[41]};mt39747<={by69d0b>>1,mef0f02[42]};jc5d1e0<={nr742d4>>1,mef0f02[43]};ne4781c<={vkb535>>1,mef0f02[44]};cb3c0e2<={xj5a9ab>>1,mef0f02[45]};lf38a1<={wya6af8>>1,mef0f02[46]};she2877<={qvabe0a>>1,mef0f02[47]};je143bd<=mef0f02[48];ira1deb<=mef0f02[49];doef5c<=mef0f02[50];pubd710<={jp55d00>>1,mef0f02[51]};tueb882<=mef0f02[52];ui5c413<=mef0f02[53];end\r
-always@* begin ng1e1e0[2047]<=hdatain[0];ng1e1e0[2046]<=hread_n;ng1e1e0[2044]<=hwrite_n;ng1e1e0[2040]<=hcs_n;ng1e1e0[2032]<=aye5ebc;ng1e1e0[2016]<=ene2fd7[0];ng1e1e0[1985]<=cb17ebd;ng1e1e0[1925]<=wwf5a74[0];ng1e1e0[1922]<=bldd558[0];ng1e1e0[1802]<=by69d0b[0];ng1e1e0[1796]<=ykeaac7;ng1e1e0[1556]<=nr742d4[0];ng1e1e0[1544]<=gq3baab;ng1e1e0[1505]<=uxb4df5[0];ng1e1e0[1324]<=gbf82ae;ng1e1e0[1316]<=jceb401[0];ng1e1e0[1200]<=jp55d00[0];ng1e1e0[1169]<=do159c[0];ng1e1e0[1163]<=uk1001c[0];ng1e1e0[1118]<=rge1837;ng1e1e0[1106]<=gd332b3[0];ng1e1e0[1065]<=vkb535[0];ng1e1e0[1041]<=nr61a85[0];ng1e1e0[1040]<=xw734fa;ng1e1e0[1023]<=haddr[0];ng1e1e0[962]<=tj37d69[0];ng1e1e0[752]<=ntbad37[0];ng1e1e0[707]<=hb74035;ng1e1e0[662]<=zx5f055;ng1e1e0[658]<=swb3ad0;ng1e1e0[600]<=ykc1574;ng1e1e0[584]<=tud0056[0];ng1e1e0[581]<=xy9c400[0];ng1e1e0[559]<=nt1c306[0];ng1e1e0[553]<=hb50cca[0];ng1e1e0[520]<=cme586a[0];ng1e1e0[376]<=db6eb4[0];ng1e1e0[353]<=epae806;ng1e1e0[331]<=qvabe0a[0];ng1e1e0[329]<=yk5675a[0];ng1e1e0[290]<=os56710[0];ng1e1e0[279]<=ou70c[0];ng1e1e0[276]<=cme5433[0];ng1e1e0[260]<=kdd3961[0];ng1e1e0[188]<=zzc1ba;ng1e1e0[165]<=wya6af8[0];ng1e1e0[164]<=jccaceb[0];ng1e1e0[138]<=fn4f950[0];ng1e1e0[130]<=qv9f4e5;ng1e1e0[82]<=xj5a9ab[0];ng1e1e0[69]<=pu353e5;ng1e1e0[65]<=kdd3e9c;ng1e1e0[34]<=uv6a174[0];ng1e1e0[32]<=gd9a7d3;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module mefacfd(\r
-gd18c9b, \r
-kdc64dc, \r
-jr326e5, \r
-xy9372f, \r
-nt9b97a, \r
-shdcbd7, \r
-reset_n, \r
-mdc, \r
-mdi, \r
-mdo, \r
-mdio_en \r
-);\r
-localparam bn22331 = 14'b00000000000001;\r
-localparam zm1198e = 14'b00000000000010;\r
-localparam ba8cc72 = 14'b00000000000100;\r
-localparam rg66393 = 14'b00000000001000;\r
-localparam wy31c9a = 14'b00000000010000;\r
-localparam zz8e4d1 = 14'b00000000100000;\r
-localparam ay7268f = 14'b00000001000000;\r
-localparam do93479 = 14'b00000010000000;\r
-localparam ir9a3ca = 14'b00000100000000;\r
-localparam ykd1e54 = 14'b00001000000000;\r
-localparam ux8f2a0 = 14'b00010000000000;\r
-localparam ne79505 = 14'b00100000000000;\r
-localparam dmca82a = 14'b01000000000000;\r
-localparam en54152 = 14'b10000000000000;\r
-parameter vxa0a95 = 10;\r
-parameter co54ae = 15;\r
-parameter ri2a570 = 4;\r
-parameter by52b82 = 2;\r
-parameter wl95c13 = 3;\r
-parameter epae09c = 13;\r
-input reset_n;\r
-input mdc;\r
-input [vxa0a95:0] gd18c9b;\r
-input [co54ae:0] kdc64dc;\r
-input xy9372f;\r
-input mdi;\r
-output mdo;\r
-output mdio_en;\r
-output shdcbd7;\r
-output nt9b97a;\r
-output [co54ae:0] jr326e5;\r
-reg [co54ae:0] jr326e5;\r
-reg nt9b97a;\r
-reg mdio_en;\r
-reg lf2de5b;\r
-reg mdo;\r
-reg [co54ae:0] iccb7a2;\r
-reg [co54ae:0] kqde88d;\r
-reg [co54ae:0] vka234a;\r
-reg [ri2a570:0] gq8d292;\r
-reg [by52b82:0] jp4a483;\r
-reg [by52b82:0] gq920fa;\r
-reg [wl95c13:0] je83e85;\r
-reg [wl95c13:0] qgfa150;\r
-reg [epae09c:0] yz8540a;\r
-reg [epae09c:0] hb502a2;\r
-reg tj81517;\r
-reg wya8be;\r
-reg al545f0;\r
-reg nga2f85;\r
-reg wl17c2b;\r
-reg shdcbd7;\r
-reg [vxa0a95 : 0] sj85769;\r
-reg [co54ae : 0] ho5da61;\r
-reg shed30a;\r
-reg ne69855;\r
-reg ui4c2aa;\r
-reg [co54ae : 0] ecaa87;\r
-reg [co54ae : 0] phaa1c7;\r
-reg [co54ae : 0] ie871f6;\r
-reg [ri2a570 : 0] fnc7d8f;\r
-reg [by52b82 : 0] nrf63f0;\r
-reg [by52b82 : 0] kf8fc3d;\r
-reg [wl95c13 : 0] ayf0f67;\r
-reg [wl95c13 : 0] tj3d9c8;\r
-reg [epae09c : 0] ic6723e;\r
-reg [epae09c : 0] ldc8f84;\r
-reg tu47c27;\r
-reg wy3e13a;\r
-reg ayf09d1;\r
-reg fp84e89;\r
-reg vx2744f;\r
-reg [2047:0] ng1e1e0;\r
-wire [19:0] mef0f02;\r
-\r
-localparam uk87811 = 20,gd3c088 = 32'hfdffd28b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin nga2f85 <= 1'b0; end else begin nga2f85 <= shed30a; end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin wl17c2b <= 1'b0; end else begin wl17c2b <= fp84e89; end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin al545f0 <= 1'b0; tj81517 <= 1'b0; wya8be <= 1'b0; vka234a <= 16'h0; kqde88d <= 16'h0; end else if (nt9b97a) begin al545f0 <= 1'b0; tj81517 <= 1'b0; wya8be <= 1'b0; end else if (vx2744f && !ayf09d1) begin al545f0 <= 1'b1; vka234a <= {3'b000,sj85769,2'b00}; kqde88d <= ho5da61; if (sj85769[10]) tj81517 <= 1'b1; else wya8be <= 1'b1; end\r
-\r
-\r
-always @(negedge mdc or negedge reset_n) begin if (!reset_n) begin mdo <= 1'b0; end else begin mdo <= ui4c2aa; end\r
-end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin gq8d292 <= 5'b00000; lf2de5b <= 1'b0; mdio_en <= 1'b0; nt9b97a <= 1'b0; jr326e5 <= 16'h0; iccb7a2 <= 16'h0; jp4a483 <= 3'b000; gq920fa <= 3'b110; je83e85 <= 4'b1011; qgfa150 <= 4'b1111; end else if (ic6723e == bn22331) begin nt9b97a <= 1'b0; gq8d292 <= 5'b00000; lf2de5b <= 1'b0; mdio_en <= 1'b0; jp4a483 <= 3'b000; gq920fa <= 3'b110; je83e85 <= 4'b1011; qgfa150 <= 4'b1111; end else if (ic6723e == zm1198e) begin gq8d292 <= fnc7d8f + 5'b00001; lf2de5b <= 1'b1; mdio_en <= 1'b1; end else if (ic6723e == rg66393) begin gq8d292 <= 5'b00000; lf2de5b <= 1'b1; mdio_en <= 1'b1; end else if (ic6723e == ba8cc72) begin gq8d292 <= 5'b00000; lf2de5b <= 1'b0; mdio_en <= 1'b1; end else if (ic6723e == ykd1e54) begin if (tu47c27) begin mdio_en <= 1'b1; lf2de5b <= 1'b1; end else begin mdio_en <= 1'b0; lf2de5b <= 1'b0; end end else if (ic6723e == wy31c9a) begin lf2de5b <= 1'b0; mdio_en <= 1'b1; end else if (ic6723e == zz8e4d1) begin lf2de5b <= 1'b1; mdio_en <= 1'b1; end else if (ic6723e == ir9a3ca) begin if (tu47c27) begin lf2de5b <= 1'b0; mdio_en <= 1'b1; end else lf2de5b <= 1'b0; end else if (ic6723e == ne79505) begin if (tu47c27) begin lf2de5b <= phaa1c7[tj3d9c8]; qgfa150 <= tj3d9c8 - 4'b0001; mdio_en <= 1'b1; end else begin lf2de5b <= 1'b0; mdio_en <= 1'b0; iccb7a2[tj3d9c8] <= ne69855; qgfa150 <= tj3d9c8 - 4'b0001; end gq8d292 <= fnc7d8f + 5'b00001; end else if (ic6723e == ay7268f) begin mdio_en <= 1'b1; lf2de5b <= ie871f6[ayf0f67]; je83e85 <= ayf0f67 - 4'b0001; gq8d292 <= fnc7d8f + 5'b00001; end else if (ic6723e == do93479) begin mdio_en <= 1'b1; lf2de5b <= ie871f6[kf8fc3d]; gq920fa <= kf8fc3d - 3'b001; jp4a483 <= nrf63f0 + 3'b001; gq8d292 <= 5'b00000; end else if (ic6723e == dmca82a) begin mdio_en <= 1'b0; lf2de5b <= 1'b0; gq8d292 <= 5'b00000; nt9b97a <= 1'b1; jr326e5 <= ecaa87; end else if (ic6723e == en54152) begin mdio_en <= 1'b0; lf2de5b <= 1'b0; gq8d292 <= 5'b00000; nt9b97a <= 1'b1; jr326e5 <= ecaa87; end\r
-\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin shdcbd7 <= 1'b1; end else if (ic6723e == bn22331 && !vx2744f) begin shdcbd7 <= 1'b1; end else begin shdcbd7 <= 1'b0; end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin yz8540a <= bn22331; end else begin yz8540a <= ldc8f84; end\r
-always @(ic6723e or tu47c27 or wy3e13a or fnc7d8f or nrf63f0) begin case(ic6723e) bn22331 : begin if (tu47c27 || wy3e13a) begin hb502a2 = zm1198e; end else begin hb502a2 = bn22331; end end zm1198e : begin if (fnc7d8f < 5'b11111) begin hb502a2 = zm1198e; end else begin hb502a2 = ba8cc72; end end ba8cc72 : begin hb502a2 = rg66393; end rg66393 : begin if (tu47c27) begin hb502a2 = wy31c9a; end else begin hb502a2 = zz8e4d1; end end wy31c9a : begin if (tu47c27) begin hb502a2 = zz8e4d1; end else begin hb502a2 = ay7268f; end end zz8e4d1 : begin if (wy3e13a) begin hb502a2 = wy31c9a; end else begin hb502a2 = ay7268f; end end ay7268f : begin if (fnc7d8f < 5'b00100) begin hb502a2 = ay7268f; end else begin hb502a2 = do93479; end end do93479 : begin if (nrf63f0 < 3'b100) begin hb502a2 = do93479; end else begin hb502a2 = ykd1e54; end end\r
- ykd1e54 : begin hb502a2 = ir9a3ca; end ir9a3ca : begin if (tu47c27) hb502a2 = ne79505; else hb502a2 = ux8f2a0; end ux8f2a0 : begin hb502a2 = ne79505; end\r
- ne79505 : begin if (fnc7d8f < 5'b01111) begin hb502a2 = ne79505; end else begin hb502a2 = dmca82a; end end dmca82a : begin hb502a2 = en54152; end\r
- en54152 : begin hb502a2 = bn22331; end default : begin hb502a2 = bn22331; end endcase end\r
-always@* begin sj85769<={gd18c9b>>1,mef0f02[0]};ho5da61<={kdc64dc>>1,mef0f02[1]};shed30a<=mef0f02[2];ne69855<=mef0f02[3];ui4c2aa<=mef0f02[4];ecaa87<={iccb7a2>>1,mef0f02[5]};phaa1c7<={kqde88d>>1,mef0f02[6]};ie871f6<={vka234a>>1,mef0f02[7]};fnc7d8f<={gq8d292>>1,mef0f02[8]};nrf63f0<={jp4a483>>1,mef0f02[9]};kf8fc3d<={gq920fa>>1,mef0f02[10]};ayf0f67<={je83e85>>1,mef0f02[11]};tj3d9c8<={qgfa150>>1,mef0f02[12]};ic6723e<={yz8540a>>1,mef0f02[13]};ldc8f84<={hb502a2>>1,mef0f02[14]};tu47c27<=mef0f02[15];wy3e13a<=mef0f02[16];ayf09d1<=mef0f02[17];fp84e89<=mef0f02[18];vx2744f<=mef0f02[19];end\r
-always@* begin ng1e1e0[2047]<=kdc64dc[0];ng1e1e0[2046]<=xy9372f;ng1e1e0[2044]<=mdi;ng1e1e0[2040]<=lf2de5b;ng1e1e0[2032]<=iccb7a2[0];ng1e1e0[2017]<=kqde88d[0];ng1e1e0[1987]<=vka234a[0];ng1e1e0[1926]<=gq8d292[0];ng1e1e0[1804]<=jp4a483[0];ng1e1e0[1614]<=wya8be;ng1e1e0[1561]<=gq920fa[0];ng1e1e0[1180]<=al545f0;ng1e1e0[1074]<=je83e85[0];ng1e1e0[1023]<=gd18c9b[0];ng1e1e0[807]<=tj81517;ng1e1e0[625]<=wl17c2b;ng1e1e0[403]<=hb502a2[0];ng1e1e0[312]<=nga2f85;ng1e1e0[201]<=yz8540a[0];ng1e1e0[100]<=qgfa150[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ksbcf57(\r
-\r
- \r
-txmac_clk, \r
-rxmac_clk, \r
-reset_n, \r
-rxmac_clk_en, \r
-txmac_clk_en, \r
-\r
- \r
-fncdc51, \r
-zx6e28f, \r
-pf7147e, \r
-\r
- \r
-lsb51f, \r
-pf616a3, \r
-ks10d54, \r
-fa6c2d4, \r
-ls86aa0, \r
-vv5a8fb, \r
-\r
- \r
-ksac9b7, \r
-zx64db8, \r
-\r
- crs, \r
- col, \r
-\r
-\r
- \r
-txd_pos, \r
- \r
- \r
-txd_neg, \r
- \r
-tx_en, \r
-tx_er, \r
-\r
-\r
-ned0632, \r
-kq53683, \r
-\r
- \r
-rx_dv_pos, \r
-rx_dv_neg, \r
-rx_er_pos, \r
-rx_er_neg, \r
-rxd_pos, \r
-rxd_neg \r
-);\r
-parameter wy9ddd9 = 8;\r
-parameter hoeeec8 = 8;\r
-parameter cm77643 = 4;\r
-input txmac_clk;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input txmac_clk_en;\r
-input [wy9ddd9-1:0] fncdc51;\r
-input zx6e28f;\r
-input pf7147e;\r
-output lsb51f;\r
-output pf616a3;\r
-output ks10d54;\r
-output fa6c2d4;\r
-output [wy9ddd9-1:0] ls86aa0;\r
-output ksac9b7;\r
-output zx64db8;\r
-input ned0632;\r
-input kq53683;\r
-\r
-input col;\r
-input crs;\r
-\r
-output [7:0] txd_pos;\r
-output [3:0] txd_neg;\r
-output tx_en;\r
-output tx_er;\r
-output vv5a8fb;\r
-input rx_dv_pos;\r
-input rx_dv_neg;\r
-input rx_er_pos;\r
-input rx_er_neg;\r
-input [7:0] rxd_pos;\r
-input [3:0] rxd_neg;\r
-reg qv9f880;\r
-reg rtfc405;\r
-reg kde202e;\r
-reg lsb51f ;\r
-reg cb80ba1;\r
-reg uk5d0d;\r
-reg ie2e869 ;\r
-reg nr74349 ;\r
-reg ana1a4e ;\r
-reg pf616a3 ;\r
-reg tu693a4;\r
-reg ui49d23;\r
-reg [wy9ddd9-1:0] pf748cc;\r
-reg [wy9ddd9-1:0] an2333d;\r
-reg [wy9ddd9-1:0] kdccf66;\r
-reg [wy9ddd9-1:0] ls86aa0 ;\r
-reg [wy9ddd9-1:0] dm66a7e;\r
-reg [wy9ddd9-1:0] uka9f9a;\r
-reg fa6c2d4 ;\r
-reg pf7e686 ;\r
-reg zxf3437 ;\r
-reg wl9a1bf ;\r
-reg ks10d54 ;\r
-reg ng86fe2;\r
-reg db37f12;\r
-reg [7:0] txd_pos;\r
-reg [3:0] txd_neg;\r
-reg tx_en;\r
-reg tx_er;\r
-reg vk96da5;\r
-reg ymb6d2b;\r
-reg ieb6958;\r
-reg vv5a8fb ;\r
-reg xla5605;\r
-reg wy2b02f;\r
-reg [wy9ddd9-1:0] hoc0bc3;\r
-reg ie5e1b;\r
-reg ri2f0d9;\r
-reg ay786ca;\r
-reg enc3650;\r
-reg ls1b285;\r
-reg yxd942a;\r
-reg byca155;\r
-reg th50aab;\r
-reg [cm77643-1:0] xy2aaf4;\r
-reg dz557a3;\r
-reg [hoeeec8-1:0] sh5e8fd;\r
-reg [3:0] faf47ed;\r
-reg [3:0] mga3f6a;\r
-reg mg1fb51;\r
-reg kdfda89;\r
-reg kded44d;\r
-reg cz6a26d;\r
-reg mr5136c;\r
-reg fc89b65;\r
-reg xw4db2b;\r
-reg kq6d95b;\r
-reg xw6cad8;\r
-wire ksac9b7;\r
-wire zx64db8;\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg [wy9ddd9 - 1 : 0] fnd8544;\r
-reg hbc2a27;\r
-reg ec1513e;\r
-reg twa89f1;\r
-reg sh44f8a;\r
-reg vx27c55;\r
-reg gq3e2af;\r
-reg dmf1579;\r
-reg yz8abca;\r
-reg [7 : 0] rt55e54;\r
-reg [3 : 0] rvaf2a6;\r
-reg by79536;\r
-reg lqca9b2;\r
-reg qt54d92;\r
-reg gqa6c94;\r
-reg sj364a1;\r
-reg rib250d;\r
-reg ie9286b;\r
-reg bn94359;\r
-reg wla1acf;\r
-reg mtd67c;\r
-reg [wy9ddd9 - 1 : 0] me59f26;\r
-reg [wy9ddd9 - 1 : 0] tu7c982;\r
-reg [wy9ddd9 - 1 : 0] qv2609a;\r
-reg [wy9ddd9 - 1 : 0] ou826a2;\r
-reg [wy9ddd9 - 1 : 0] an9a88e;\r
-reg qgd4475;\r
-reg lsa23a9;\r
-reg ba11d4a;\r
-reg tj8ea52;\r
-reg cz75296;\r
-reg oua94b4;\r
-reg jp4a5a1;\r
-reg dm52d0f;\r
-reg ls9687b;\r
-reg yzb43db;\r
-reg [wy9ddd9 - 1 : 0] swf6e4;\r
-reg zx7b721;\r
-reg ykdb90f;\r
-reg czdc879;\r
-reg dme43cc;\r
-reg sw21e63;\r
-reg ecf318;\r
-reg ps798c1;\r
-reg yxcc60b;\r
-reg [cm77643 - 1 : 0] ir182e2;\r
-reg cmc1715;\r
-reg [hoeeec8 - 1 : 0] kq5c542;\r
-reg [3 : 0] uve2a11;\r
-reg [3 : 0] ym1508d;\r
-reg xya8469;\r
-reg by4234b;\r
-reg ng11a5b;\r
-reg ie8d2da;\r
-reg rg696d0;\r
-reg gb4b683;\r
-reg gb5b41d;\r
-reg jcda0ec;\r
-reg hod0762;\r
-reg [2047:0] ng1e1e0;\r
-wire [58:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 59,gd3c088 = 32'hfdffc70b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
- assign zx64db8 = col; assign ksac9b7 = crs;\r
-\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin xy2aaf4 <= 4'b0000; dz557a3 <= 1'b1; end else if (rxmac_clk_en) begin if (!cmc1715 && !xya8469) begin if (ir182e2 < 4'b1011) begin xy2aaf4 <= ir182e2 + 4'b0001; end else begin xy2aaf4 <= 4'b0000; dz557a3 <= 1'b1; end end else if (by4234b) begin xy2aaf4 <= 4'b0000; dz557a3 <= 1'b0; end end\r
-end\r
-\r
-\r
- always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin ls1b285 <= 1'b0; yxd942a <= 1'b0; end else if (rxmac_clk_en) begin ls1b285 <= 1'b1; yxd942a <= sw21e63; end end\r
-\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin byca155 <= 1'b0; th50aab <= 1'b0; end else if (rxmac_clk_en) begin byca155 <= sh44f8a; th50aab <= ps798c1; end\r
-end\r
-\r
-\r
- always @(posedge txmac_clk or negedge reset_n) begin if (!reset_n) begin ay786ca <= 1'b0; enc3650 <= 1'b0; end else if (txmac_clk_en) begin ay786ca <= 1'b1; enc3650 <= czdc879; end end\r
-\r
-\r
-\r
-\r
-always @(negedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin kded44d <= 0; cz6a26d <= 0; fc89b65 <= 0; xw4db2b <= 0; faf47ed <= 0; mga3f6a <= 0; end else if (rxmac_clk_en) begin kded44d <= gq3e2af; cz6a26d <= ng11a5b; fc89b65 <= yz8abca; xw4db2b <= gb4b683; faf47ed <= rvaf2a6; mga3f6a <= uve2a11; end\r
-end\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin mg1fb51 <= 0; kdfda89 <= 0; mr5136c <= 0; sh5e8fd <= 0; end else if (rxmac_clk_en) begin mg1fb51 <= vx27c55; kdfda89 <= xya8469; mr5136c <= dmf1579; sh5e8fd <= rt55e54; end\r
-end\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin kq6d95b <= 0; xw6cad8 <= 0; pf748cc <= 0; an2333d <= 0; kdccf66 <= 0; ls86aa0 <= 0; dm66a7e <= 0; uka9f9a <= 0; fa6c2d4 <= 0; pf7e686 <= 0; zxf3437 <= 0; wl9a1bf <= 0; ks10d54 <= 0; ng86fe2 <= 0; db37f12 <= 0; ie2e869 <= 0; nr74349 <= 0; ana1a4e <= 0; pf616a3 <= 0; tu693a4 <= 0; ui49d23 <= 0; qv9f880 <= 0; rtfc405 <= 0; kde202e <= 0; lsb51f <= 0; cb80ba1 <= 0; uk5d0d <= 0; vk96da5 <= 0; ymb6d2b <= 0; ieb6958 <= 0; vv5a8fb <= 0; wy2b02f <= 0; xla5605 <= 0; end else if (rxmac_clk_en) begin ls86aa0 <= qv2609a; ks10d54 <= ba11d4a; pf616a3 <= bn94359; lsb51f <= qt54d92; vv5a8fb <= dm52d0f; kdccf66 <= tu7c982; wl9a1bf <= lsa23a9; ana1a4e <= ie9286b; kde202e <= lqca9b2; ieb6958 <= jp4a5a1; an2333d <= me59f26; zxf3437 <= qgd4475; nr74349 <= rib250d; rtfc405 <= by79536; ymb6d2b <= oua94b4; if (ecf318) begin pf748cc <= ou826a2; pf7e686 <= tj8ea52; ie2e869 <= wla1acf; qv9f880 <= gqa6c94; vk96da5 <= ls9687b; if (yxcc60b) begin fa6c2d4 <= tj8ea52 & ks10d54; end else begin fa6c2d4 <= ks10d54; end end else begin pf748cc <= an9a88e; pf7e686 <= cz75296; ie2e869 <= mtd67c; qv9f880 <= sj364a1; vk96da5 <= yzb43db; if (yxcc60b) begin fa6c2d4 <= cz75296 & ks10d54; end else begin fa6c2d4 <= ks10d54; end end ng86fe2 <= xya8469; dm66a7e <= kq5c542; tu693a4 <= rg696d0; cb80ba1 <= 0; if ((by4234b == 0) && (xya8469 == 1)) begin xla5605 <= ~cmc1715; end if ((by4234b == 0) && (ie8d2da == 1)) begin kq6d95b <= 0; db37f12 <= xya8469 & ie8d2da; uka9f9a <= {kq5c542[3:0], ym1508d}; ui49d23 <= rg696d0 | gb5b41d; wy2b02f <= ~cmc1715; if ({kq5c542[3:0], ym1508d} == 8'hd5) begin xw6cad8 <= 0; end else begin xw6cad8 <= 1; end end else if ((ie8d2da == 0) && (xya8469 == 1)) begin kq6d95b <= 1; db37f12 <= ng11a5b & xya8469; uka9f9a <= {uve2a11, kq5c542[3:0]}; ui49d23 <= gb4b683 | rg696d0; wy2b02f <= ~cmc1715; if ({uve2a11, kq5c542[3:0]} == 8'hd5) begin xw6cad8 <= 0; end else begin xw6cad8 <= 1; end end else if ((hod0762 == 1) && ({kq5c542[3:0], ym1508d} == 8'hd5)) begin kq6d95b <= 0; uka9f9a <= {kq5c542[3:0], ym1508d}; xw6cad8 <= 0; end else if ((hod0762 == 1) && ({uve2a11, kq5c542[3:0]} == 8'hd5)) begin kq6d95b <= 1; uka9f9a <= {uve2a11, kq5c542[3:0]}; xw6cad8 <= 0; end else if (jcda0ec == 0) begin db37f12 <= xya8469 & ie8d2da; uka9f9a <= {kq5c542[3:0], ym1508d}; ui49d23 <= rg696d0 | gb5b41d; if (cz75296 == 1) begin uk5d0d <= xya8469 != ie8d2da; end end else if (jcda0ec == 1) begin db37f12 <= ng11a5b & xya8469; uka9f9a <= {uve2a11, kq5c542[3:0]}; ui49d23 <= gb4b683 | rg696d0; if (cz75296 == 1) begin uk5d0d <= ng11a5b != xya8469; end end end\r
-end\r
-\r
-\r
-always @(posedge txmac_clk or negedge reset_n) begin if (!reset_n) begin hoc0bc3 <= 0; ie5e1b <= 0; end else if (txmac_clk_en) begin if (ec1513e) begin hoc0bc3 <= fnd8544; ie5e1b <= hbc2a27; end else begin hoc0bc3 <= 0; ie5e1b <= 0; end end\r
-end\r
-\r
-\r
-always @(posedge txmac_clk or negedge reset_n) begin if (!reset_n) begin ri2f0d9 <= 1'b0; end else if (txmac_clk_en) begin ri2f0d9 <= ec1513e; end\r
-end\r
-\r
-\r
-always @(dme43cc or ykdb90f or swf6e4 or zx7b721) begin casex({dme43cc, ykdb90f}) 2'bx0 : begin txd_pos[7:0] = 0; txd_neg[3:0] = 0; tx_er = 0; tx_en = 0; end 2'b11 : begin txd_pos[7:0] = swf6e4[7:0]; txd_neg[3:0] = swf6e4[3:0]; tx_er = zx7b721; tx_en = ykdb90f; end 2'b01 : begin txd_pos[7:0] = {4'h0, swf6e4[3:0]}; txd_neg[3:0] = swf6e4[7:4]; tx_er = zx7b721; tx_en = ykdb90f; end default : begin txd_pos[7:0] = 0; txd_neg[3:0] = 0; tx_er = 0; tx_en = 0; end endcase\r
-end\r
-always@* begin fnd8544<={fncdc51>>1,mef0f02[0]};hbc2a27<=mef0f02[1];ec1513e<=mef0f02[2];twa89f1<=mef0f02[3];sh44f8a<=mef0f02[4];vx27c55<=mef0f02[5];gq3e2af<=mef0f02[6];dmf1579<=mef0f02[7];yz8abca<=mef0f02[8];rt55e54<={rxd_pos>>1,mef0f02[9]};rvaf2a6<={rxd_neg>>1,mef0f02[10]};by79536<=mef0f02[11];lqca9b2<=mef0f02[12];qt54d92<=mef0f02[13];gqa6c94<=mef0f02[14];sj364a1<=mef0f02[15];rib250d<=mef0f02[16];ie9286b<=mef0f02[17];bn94359<=mef0f02[18];wla1acf<=mef0f02[19];mtd67c<=mef0f02[20];me59f26<={pf748cc>>1,mef0f02[21]};tu7c982<={an2333d>>1,mef0f02[22]};qv2609a<={kdccf66>>1,mef0f02[23]};ou826a2<={dm66a7e>>1,mef0f02[24]};an9a88e<={uka9f9a>>1,mef0f02[25]};qgd4475<=mef0f02[26];lsa23a9<=mef0f02[27];ba11d4a<=mef0f02[28];tj8ea52<=mef0f02[29];cz75296<=mef0f02[30];oua94b4<=mef0f02[31];jp4a5a1<=mef0f02[32];dm52d0f<=mef0f02[33];ls9687b<=mef0f02[34];yzb43db<=mef0f02[35];swf6e4<={hoc0bc3>>1,mef0f02[36]};zx7b721<=mef0f02[37];ykdb90f<=mef0f02[38];czdc879<=mef0f02[39];dme43cc<=mef0f02[40];sw21e63<=mef0f02[41];ecf318<=mef0f02[42];ps798c1<=mef0f02[43];yxcc60b<=mef0f02[44];ir182e2<={xy2aaf4>>1,mef0f02[45]};cmc1715<=mef0f02[46];kq5c542<={sh5e8fd>>1,mef0f02[47]};uve2a11<={faf47ed>>1,mef0f02[48]};ym1508d<={mga3f6a>>1,mef0f02[49]};xya8469<=mef0f02[50];by4234b<=mef0f02[51];ng11a5b<=mef0f02[52];ie8d2da<=mef0f02[53];rg696d0<=mef0f02[54];gb4b683<=mef0f02[55];gb5b41d<=mef0f02[56];jcda0ec<=mef0f02[57];hod0762<=mef0f02[58];end\r
-always@* begin ng1e1e0[2047]<=zx6e28f;ng1e1e0[2046]<=pf7147e;ng1e1e0[2044]<=ned0632;ng1e1e0[2040]<=kq53683;ng1e1e0[2032]<=rx_dv_pos;ng1e1e0[2016]<=rx_dv_neg;ng1e1e0[1985]<=rx_er_pos;ng1e1e0[1922]<=rx_er_neg;ng1e1e0[1867]<=tu693a4;ng1e1e0[1804]<=sh5e8fd[0];ng1e1e0[1797]<=rxd_pos[0];ng1e1e0[1761]<=th50aab;ng1e1e0[1686]<=ui49d23;ng1e1e0[1623]<=mr5136c;ng1e1e0[1561]<=faf47ed[0];ng1e1e0[1558]<=wl9a1bf;ng1e1e0[1547]<=rxd_neg[0];ng1e1e0[1542]<=hoc0bc3[0];ng1e1e0[1490]<=nr74349;ng1e1e0[1475]<=xy2aaf4[0];ng1e1e0[1413]<=pf7e686;ng1e1e0[1409]<=xla5605;ng1e1e0[1400]<=xw6cad8;ng1e1e0[1324]<=pf748cc[0];ng1e1e0[1200]<=kdccf66[0];ng1e1e0[1199]<=fc89b65;ng1e1e0[1074]<=mga3f6a[0];ng1e1e0[1068]<=ng86fe2;ng1e1e0[1047]<=qv9f880;ng1e1e0[1037]<=ie5e1b;ng1e1e0[1023]<=fncdc51[0];ng1e1e0[933]<=ana1a4e;ng1e1e0[902]<=dz557a3;ng1e1e0[880]<=byca155;ng1e1e0[811]<=cz6a26d;ng1e1e0[779]<=zxf3437;ng1e1e0[771]<=wy2b02f;ng1e1e0[745]<=ie2e869;ng1e1e0[706]<=uka9f9a[0];ng1e1e0[704]<=ieb6958;ng1e1e0[700]<=kq6d95b;ng1e1e0[600]<=an2333d[0];ng1e1e0[440]<=yxd942a;ng1e1e0[405]<=kded44d;ng1e1e0[372]<=uk5d0d;ng1e1e0[353]<=dm66a7e[0];ng1e1e0[352]<=ymb6d2b;ng1e1e0[350]<=xw4db2b;ng1e1e0[220]<=ls1b285;ng1e1e0[202]<=kdfda89;ng1e1e0[186]<=cb80ba1;ng1e1e0[176]<=vk96da5;ng1e1e0[110]<=enc3650;ng1e1e0[101]<=mg1fb51;ng1e1e0[93]<=kde202e;ng1e1e0[88]<=db37f12;ng1e1e0[55]<=ay786ca;ng1e1e0[46]<=rtfc405;ng1e1e0[27]<=ri2f0d9;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module tsmac3 (\r
-\r
- \r
- hclk,\r
- txmac_clk,\r
- rxmac_clk,\r
- reset_n,\r
-\r
- txmac_clk_en,\r
- rxmac_clk_en,\r
-\r
-\r
- \r
- rxd,\r
- rx_dv,\r
- rx_er,\r
-\r
- col,\r
- crs,\r
-\r
- \r
- haddr,\r
- hdatain,\r
- hcs_n,\r
- hwrite_n,\r
- hread_n,\r
-\r
- \r
-\r
- \r
- tx_fifodata,\r
- tx_fifoavail,\r
- tx_fifoeof,\r
- tx_fifoempty,\r
- tx_sndpaustim,\r
- tx_sndpausreq,\r
- tx_fifoctrl,\r
-\r
- \r
- rx_fifo_full,\r
- ignore_pkt,\r
-\r
- \r
- tx_en,\r
- tx_er,\r
-\r
- txd,\r
-\r
- \r
- hdataout,\r
- hdataout_en_n,\r
- hready_n,\r
- cpu_if_gbit_en,\r
-\r
- \r
-\r
- \r
- tx_macread,\r
- tx_discfrm,\r
- tx_staten,\r
- tx_statvec,\r
- tx_done,\r
-\r
- \r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
-)\r
- \r
- \r
-;\r
-input hclk;\r
-input txmac_clk;\r
-input rxmac_clk;\r
-input reset_n;\r
-\r
-input txmac_clk_en;\r
-input rxmac_clk_en;\r
-\r
-\r
-\r
-input [7:0] rxd;\r
-input rx_dv;\r
-input rx_er;\r
-\r
-\r
-input col;\r
-input crs;\r
-\r
-input [7:0] haddr;\r
-input [7:0] hdatain;\r
-input hcs_n;\r
-input hwrite_n;\r
-input hread_n;\r
-\r
-input [7:0] tx_fifodata;\r
-input tx_fifoavail;\r
-input tx_fifoeof;\r
-input tx_fifoempty;\r
-input [15:0] tx_sndpaustim;\r
-input tx_sndpausreq;\r
-input tx_fifoctrl;\r
-input rx_fifo_full;\r
-input ignore_pkt;\r
-\r
-output [7:0] txd;\r
-\r
-output tx_en;\r
-output tx_er;\r
-output [7:0] hdataout;\r
-output hdataout_en_n;\r
-output hready_n;\r
-output cpu_if_gbit_en;\r
-\r
-output tx_macread;\r
-output tx_discfrm;\r
-output tx_staten;\r
-output tx_done;\r
-output [30:0] tx_statvec;\r
-output rx_fifo_error;\r
-output [31:0] rx_stat_vector;\r
-output [7:0] rx_dbout;\r
-output rx_write;\r
-output rx_stat_en;\r
-output rx_eof;\r
-output rx_error;\r
-\r
-\r
-\r
-\r
-\r
-parameter pdevice_family = "ECP2";\r
-\r
-\r
-\r
-\r
-\r
-wire [15:0] ie2197a;\r
-wire fpcbd0;\r
-wire yx65e87;\r
-wire [8:0] bldd558;\r
-wire ykeaac7;\r
-wire [15:0] ned0f15;\r
-wire ie878aa;\r
-wire oh3c550;\r
-wire [7:0] mre2a84;\r
-wire mg15425;\r
-wire hdaa129;\r
-wire bl5094e;\r
-wire tj84a76;\r
-wire ba253b7;\r
-wire [4:0] ep29dbb;\r
-wire cz4eddc;\r
-wire vi76ee4;\r
-wire lsb7722;\r
-wire ohbb913;\r
-wire mrdc89c;\r
-wire fae44e4;\r
-wire lf22723;\r
-wire db1391e;\r
-wire ls9c8f7;\r
-wire [13:0] xwe47ba;\r
-wire [7:0] yz23dd3;\r
-wire [7:0] fc1ee9d;\r
-wire [7:0] gbf74eb;\r
-wire [7:0] bnba75d;\r
-wire [7:0] qtd3aef;\r
-wire [7:0] ks9d77d;\r
-wire [7:0] tuebbe9;\r
-wire [7:0] vi5df4b;\r
-wire [15:0] ykefa5a;\r
-wire [47:0] ic7d2d1;\r
-wire [10:0] rte9688;\r
-wire [15:0] gb4b447;\r
-wire hb5a23d;\r
-wire [7:0] qgd11ee;\r
-wire ks88f71;\r
-wire lq47b89;\r
-wire nt3dc4a;\r
-wire hoee257;\r
-wire bl712ba;\r
-wire hq895d6;\r
-\r
-wire mrd6596;\r
-wire bab2cb4;\r
-wire [7:0] hq965a2;\r
-wire [3:0] ngb2d12;\r
-wire zm96892;\r
-wire gdb4493;\r
-wire vka249c;\r
-wire ep124e2;\r
-wire [7:0] ou92714;\r
-wire [3:0] ri938a0;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg jea77e1;\r
-reg [7 : 0] en51e07;\r
-reg [7 : 0] go781e5;\r
-reg mt3ca1c;\r
-reg yz7943;\r
-reg zkc0f28;\r
-reg [7 : 0] al7a68d;\r
-reg jcda897;\r
-reg ipd346d;\r
-reg wl9a36c;\r
-reg [15 : 0] ay463af;\r
-reg end918e;\r
-reg god1b64;\r
-reg wwde5f9;\r
-reg wwd1063;\r
-reg [15 : 0] ks9259a;\r
-reg ks92cd0;\r
-reg pu96681;\r
-reg [8 : 0] ir29e31;\r
-reg jp4f18c;\r
-reg [15 : 0] vid028c;\r
-reg bn81463;\r
-reg iea31e;\r
-reg [7 : 0] wj518f1;\r
-reg do8c78c;\r
-reg dm63c62;\r
-reg tw1e313;\r
-reg jcf189a;\r
-reg xy8c4d3;\r
-reg [4 : 0] go6269a;\r
-reg ph134d0;\r
-reg an9a686;\r
-reg ofd3434;\r
-reg sj9a1a4;\r
-reg byd0d24;\r
-reg ri86922;\r
-reg gq34912;\r
-reg ana4891;\r
-reg qi2448c;\r
-reg [13 : 0] vx22461;\r
-reg [7 : 0] ep1230e;\r
-reg [7 : 0] rv91874;\r
-reg [7 : 0] pu8c3a6;\r
-reg [7 : 0] xj61d32;\r
-reg [7 : 0] twe996;\r
-reg [7 : 0] dz74cb2;\r
-reg [7 : 0] aaa6597;\r
-reg [7 : 0] tj32cb8;\r
-reg [15 : 0] vk965c6;\r
-reg [47 : 0] vkb2e32;\r
-reg [10 : 0] ks97192;\r
-reg [15 : 0] lsb8c90;\r
-reg shc6483;\r
-reg [7 : 0] vx3241d;\r
-reg ou920ef;\r
-reg sj90778;\r
-reg ba83bc5;\r
-reg kf1de2a;\r
-reg osef154;\r
-reg cm78aa0;\r
-reg xwc5501;\r
-reg do2a80a;\r
-reg [7 : 0] yx54053;\r
-reg [3 : 0] zza029d;\r
-reg ng14ef;\r
-reg aaa77a;\r
-reg ic53bd1;\r
-reg ym9de89;\r
-reg [7 : 0] wwef448;\r
-reg [3 : 0] qt7a240;\r
-reg [2047:0] ng1e1e0;\r
-wire [69:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 70,gd3c088 = 32'hfdffd14b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- assign mrd6596 = txmac_clk_en; assign bab2cb4 = rxmac_clk_en;\r
-\r
-\r
-\r
-\r
-\r
- assign hq965a2 = rxd; assign ngb2d12 = 4'h0; assign zm96892 = rx_dv; assign gdb4493 = 1'b0; assign vka249c = rx_er; assign ep124e2 = 1'b0; assign txd = wwef448;\r
-\r
-\r
-\r
-\r
-\r
-qv835c #(.pdevice_family(pdevice_family))\r
-mt3cb88 ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(do2a80a), .ks10d54(ba83bc5), .fa6c2d4(jr8eff9), .ls86aa0(vx3241d), .pf616a3(sj90778), .lsb51f(ou920ef), .vv5a8fb(kf1de2a), .uv70d29(ep1230e), .hq8694d(rv91874), .ec34a6a(pu8c3a6), .lfa5351(xj61d32), .gd29a8f(twe996), .rg4d47c(dz74cb2), .mr6a3e2(aaa6597), .of51f14(tj32cb8), .sj8f8a4(vkb2e32), .tu7c524(sj9a1a4), .ale2922(byd0d24), .vk14915(gq34912), .ba25a85(vk965c6), .qgcb360(ana4891), .go59b01(ri86922), .ldcd808(vx22461), .tu6c047(ofd3434), .wj6023b(an9a686), .rx_fifo_full(wwde5f9), .ignore_pkt(wwd1063), .gq3baab(yx65e87), .ene2fd7(ie2197a), .cb17ebd(fpcbd0), .bldd558(bldd558), .ykeaac7(ykeaac7), .su780a3(ned0f15), .fa58e7c(ie878aa), .rx_fifo_error(rx_fifo_error), .rx_stat_vector(rx_stat_vector), .rx_dbout(rx_dbout), .rx_write(rx_write), .rx_stat_en(rx_stat_en), .rx_eof(rx_eof), .rx_error(rx_error)\r
-);\r
-uid1f98 #(.pdevice_family(pdevice_family))\r
-wy3e272 ( .txmac_clk(txmac_clk), .ir3994e(jea77e1), .txmac_clk_en(xwc5501), .gof5dd7(tw1e313), .anaeeb9(jcf189a), .phbae69(xy8c4d3), .yk775cd(ph134d0), .vk3f2df(go6269a), .vvf96fb(vkb2e32), .fa69d8e(vk965c6), .tx_fifodata(al7a68d), .tx_fifoeof(ipd346d), .tx_fifoempty(wl9a36c), .tx_fifoavail(jcda897), .tx_sndpaustim(ay463af), .tx_sndpausreq(end918e), .tx_fifoctrl(god1b64), .zk520c4(bn81463), .cb90622(vid028c), .ukb9a76(cm78aa0), .vvd734e(osef154), .suc455c(hdaa129), .tx_macread(tx_macread), .tx_discfrm(tx_discfrm), .tx_staten(tx_staten), .tx_statvec(tx_statvec), .tx_done(tx_done), .ip750ca(oh3c550), .lsa8654(mre2a84), .ic432a3(mg15425) \r
-);\r
- ksbcf57 twa7c2e ( .txmac_clk(txmac_clk), .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(do2a80a), .txmac_clk_en(xwc5501), .fncdc51(wj518f1), .zx6e28f(do8c78c), .pf7147e(iea31e), .rx_dv_pos(ng14ef), .rx_dv_neg(aaa77a), .rx_er_pos(ic53bd1), .rx_er_neg(ym9de89), .rxd_pos(yx54053), .rxd_neg(zza029d),\r
-\r
-\r
- .col(col), .crs(crs),\r
-\r
-\r
-\r
- .ned0632(cpu_if_gbit_en), .kq53683(qi2448c), .lsb51f(ks88f71), .pf616a3(lq47b89), .ks10d54(nt3dc4a), .fa6c2d4(jr8eff9), .ls86aa0(qgd11ee), .vv5a8fb(hoee257), .ksac9b7(bl712ba), .zx64db8(hq895d6), .txd_pos(ou92714), .txd_neg(ri938a0), .tx_en(tx_en), .tx_er(tx_er) );\r
-\r
-fp8b349 vk20026 ( .hclk(hclk), .reset_n(jea77e1), .haddr(en51e07), .hdatain(go781e5), .hread_n(zkc0f28), .hwrite_n(yz7943), .hcs_n(mt3ca1c), .ene2fd7(ks9259a), .cb17ebd(ks92cd0), .gq3baab(pu96681), .bldd558(ir29e31), .ykeaac7(jp4f18c), .aye5ebc(dm63c62), \r
-\r
-\r
-\r
- .hdataout(hdataout), .hready_n(hready_n), .hdataout_en_n(hdataout_en_n), .tx_en(bl5094e), .vvcda9b(tj84a76), .ui6d4df(ba253b7), .vk3f2df(ep29dbb), .ned0632(cpu_if_gbit_en), .yk775cd(cz4eddc),\r
- \r
-\r
-\r
-\r
- .wj6023b(vi76ee4), .tu6c047(lsb7722), .neda0c6(ic7d2d1), .bydf307(ohbb913), .ale2922(mrdc89c), .go59b01(fae44e4), .vk14915(lf22723), .qgcb360(db1391e), .ldcd808(xwe47ba), .kq53683(ls9c8f7), .ba25a85(ykefa5a), .ip60ebc(yz23dd3), .ep75e4(fc1ee9d), .ls3af25(gbf74eb), .pfd792a(bnba75d), .cobc957(qtd3aef), .xwe4ab9(ks9d77d), .tw255ca(tuebbe9), .ri2ae53(vi5df4b)\r
-);\r
-\r
-\r
-\r
-always@* begin jea77e1<=mef0f02[0];en51e07<={haddr>>1,mef0f02[1]};go781e5<={hdatain>>1,mef0f02[2]};mt3ca1c<=mef0f02[3];yz7943<=mef0f02[4];zkc0f28<=mef0f02[5];al7a68d<={tx_fifodata>>1,mef0f02[6]};jcda897<=mef0f02[7];ipd346d<=mef0f02[8];wl9a36c<=mef0f02[9];ay463af<={tx_sndpaustim>>1,mef0f02[10]};end918e<=mef0f02[11];god1b64<=mef0f02[12];wwde5f9<=mef0f02[13];wwd1063<=mef0f02[14];ks9259a<={ie2197a>>1,mef0f02[15]};ks92cd0<=mef0f02[16];pu96681<=mef0f02[17];ir29e31<={bldd558>>1,mef0f02[18]};jp4f18c<=mef0f02[19];vid028c<={ned0f15>>1,mef0f02[20]};bn81463<=mef0f02[21];iea31e<=mef0f02[22];wj518f1<={mre2a84>>1,mef0f02[23]};do8c78c<=mef0f02[24];dm63c62<=mef0f02[25];tw1e313<=mef0f02[26];jcf189a<=mef0f02[27];xy8c4d3<=mef0f02[28];go6269a<={ep29dbb>>1,mef0f02[29]};ph134d0<=mef0f02[30];an9a686<=mef0f02[31];ofd3434<=mef0f02[32];sj9a1a4<=mef0f02[33];byd0d24<=mef0f02[34];ri86922<=mef0f02[35];gq34912<=mef0f02[36];ana4891<=mef0f02[37];qi2448c<=mef0f02[38];vx22461<={xwe47ba>>1,mef0f02[39]};ep1230e<={yz23dd3>>1,mef0f02[40]};rv91874<={fc1ee9d>>1,mef0f02[41]};pu8c3a6<={gbf74eb>>1,mef0f02[42]};xj61d32<={bnba75d>>1,mef0f02[43]};twe996<={qtd3aef>>1,mef0f02[44]};dz74cb2<={ks9d77d>>1,mef0f02[45]};aaa6597<={tuebbe9>>1,mef0f02[46]};tj32cb8<={vi5df4b>>1,mef0f02[47]};vk965c6<={ykefa5a>>1,mef0f02[48]};vkb2e32<={ic7d2d1>>1,mef0f02[49]};ks97192<={rte9688>>1,mef0f02[50]};lsb8c90<={gb4b447>>1,mef0f02[51]};shc6483<=mef0f02[52];vx3241d<={qgd11ee>>1,mef0f02[53]};ou920ef<=mef0f02[54];sj90778<=mef0f02[55];ba83bc5<=mef0f02[56];kf1de2a<=mef0f02[57];osef154<=mef0f02[58];cm78aa0<=mef0f02[59];xwc5501<=mef0f02[60];do2a80a<=mef0f02[61];yx54053<={hq965a2>>1,mef0f02[62]};zza029d<={ngb2d12>>1,mef0f02[63]};ng14ef<=mef0f02[64];aaa77a<=mef0f02[65];ic53bd1<=mef0f02[66];ym9de89<=mef0f02[67];wwef448<={ou92714>>1,mef0f02[68]};qt7a240<={ri938a0>>1,mef0f02[69]};end\r
-always@* begin ng1e1e0[2047]<=haddr[0];ng1e1e0[2046]<=hdatain[0];ng1e1e0[2044]<=hcs_n;ng1e1e0[2040]<=hwrite_n;ng1e1e0[2033]<=hread_n;ng1e1e0[2019]<=tx_fifodata[0];ng1e1e0[1994]<=gbf74eb[0];ng1e1e0[1990]<=tx_fifoavail;ng1e1e0[1981]<=tj84a76;ng1e1e0[1965]<=lsb7722;ng1e1e0[1940]<=bnba75d[0];ng1e1e0[1939]<=bldd558[0];ng1e1e0[1933]<=tx_fifoeof;ng1e1e0[1914]<=ba253b7;ng1e1e0[1883]<=ohbb913;ng1e1e0[1832]<=qtd3aef[0];ng1e1e0[1831]<=ykeaac7;ng1e1e0[1819]<=tx_fifoempty;ng1e1e0[1785]<=xwe47ba[0];ng1e1e0[1781]<=ep29dbb[0];ng1e1e0[1778]<=ie2197a[0];ng1e1e0[1740]<=hoee257;ng1e1e0[1719]<=mrdc89c;ng1e1e0[1634]<=mrd6596;ng1e1e0[1616]<=ks9d77d[0];ng1e1e0[1615]<=ned0f15[0];ng1e1e0[1591]<=tx_sndpaustim[0];ng1e1e0[1579]<=zm96892;ng1e1e0[1522]<=yz23dd3[0];ng1e1e0[1515]<=cz4eddc;ng1e1e0[1508]<=fpcbd0;ng1e1e0[1470]<=db1391e;ng1e1e0[1432]<=bl712ba;ng1e1e0[1406]<=ri938a0[0];ng1e1e0[1391]<=fae44e4;ng1e1e0[1286]<=ic7d2d1[0];ng1e1e0[1271]<=mg15425;ng1e1e0[1221]<=bab2cb4;ng1e1e0[1184]<=tuebbe9[0];ng1e1e0[1182]<=ie878aa;ng1e1e0[1135]<=tx_sndpausreq;ng1e1e0[1111]<=gdb4493;ng1e1e0[1051]<=gb4b447[0];ng1e1e0[1023]<=reset_n;ng1e1e0[997]<=fc1ee9d[0];ng1e1e0[990]<=bl5094e;ng1e1e0[982]<=vi76ee4;ng1e1e0[969]<=yx65e87;ng1e1e0[892]<=ls9c8f7;ng1e1e0[889]<=ignore_pkt;ng1e1e0[870]<=nt3dc4a;ng1e1e0[817]<=hq895d6;ng1e1e0[789]<=ngb2d12[0];ng1e1e0[735]<=lf22723;ng1e1e0[703]<=ou92714[0];ng1e1e0[643]<=ykefa5a[0];ng1e1e0[635]<=mre2a84[0];ng1e1e0[525]<=rte9688[0];ng1e1e0[495]<=hdaa129;ng1e1e0[444]<=rx_fifo_full;ng1e1e0[435]<=lq47b89;ng1e1e0[394]<=hq965a2[0];ng1e1e0[351]<=ep124e2;ng1e1e0[321]<=vi5df4b[0];ng1e1e0[317]<=oh3c550;ng1e1e0[222]<=tx_fifoctrl;ng1e1e0[217]<=ks88f71;ng1e1e0[175]<=vka249c;ng1e1e0[108]<=qgd11ee[0];ng1e1e0[54]<=hb5a23d;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
+++ /dev/null
-Parameters loaded ok.
-No optional files required.
-Parameter values ok.
-Project Directory succussfully created.
-Simulation model successfully created.
-IP template generation completed ok.
-LPF generation completed ok.
-ModelSim do file successfully created.
+++ /dev/null
-GenerateCore within package Core_Generate 1.0.0 in file LatticeIP_generate.tcl
-can't read "env(SYNPLIFY)": no such variable
-
-Total Warnings: 0
-
-
-Total Errors: 0
-
-
-
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress \r
-// Filename: USERNAME_inst.v \r
-// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
- tsmac3 DUT_INST ( \r
-\r
- // clock and reset\r
- .hclk(hclk),\r
- .txmac_clk(txmac_clk),\r
- .rxmac_clk(rxmac_clk),\r
- .reset_n(reset_n),\r
- .txmac_clk_en(txmac_clk_en),\r
- .rxmac_clk_en(rxmac_clk_en),\r
- \r
- // Input signals to the GMII\r
- .rxd(rxd),\r
- .rx_dv(rx_dv),\r
- .rx_er(rx_er),\r
- .col(col),\r
- .crs(crs),\r
- \r
- // Input signals to the CPU Interface\r
- .haddr(haddr),\r
- .hdatain(hdatain),\r
- .hcs_n(hcs_n),\r
- .hwrite_n(hwrite_n),\r
- .hread_n(hread_n),\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- .tx_fifodata(tx_fifodata),\r
- .tx_fifoavail(tx_fifoavail),\r
- .tx_fifoeof(tx_fifoeof),\r
- .tx_fifoempty(tx_fifoempty),\r
- .tx_sndpaustim(tx_sndpaustim),\r
- .tx_sndpausreq(tx_sndpausreq),\r
- .tx_fifoctrl(tx_fifoctrl),\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- .rx_fifo_full(rx_fifo_full),\r
- .ignore_pkt(ignore_pkt),\r
- \r
- // Output signals from the GMII\r
- .txd(txd),\r
- .tx_en(tx_en),\r
- .tx_er(tx_er),\r
- \r
- // Output signals from the CPU Interface\r
- .hdataout(hdataout),\r
- .hdataout_en_n(hdataout_en_n),\r
- .hready_n(hready_n),\r
- .cpu_if_gbit_en(cpu_if_gbit_en),\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- .tx_macread(tx_macread),\r
- .tx_discfrm(tx_discfrm),\r
- .tx_staten(tx_staten),\r
- .tx_statvec(tx_statvec),\r
- .tx_done(tx_done),\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- .rx_fifo_error(rx_fifo_error),\r
- .rx_stat_vector(rx_stat_vector),\r
- .rx_dbout(rx_dbout),\r
- .rx_write(rx_write),\r
- .rx_stat_en(rx_stat_en),\r
- .rx_eof(rx_eof),\r
- .rx_error(rx_error)\r
- );\r
+++ /dev/null
-
-#!/usr/local/bin/wish
-
-set Para(cmd) ""
-if ![catch {set temp $argc} result] {
- if {$argc > 0} {
- for {set i 0} {$i < $argc} {incr i 2} {
- set temp [lindex $argv $i]
- set temp [string range $temp 1 end]
- lappend argv_list $temp
- lappend value_list [lindex $argv [expr $i+1]]
- }
- foreach argument $argv_list value $value_list {
- switch $argument {
- "cmd" {set Para(cmd) $value;}
- }
- }
- }
-}
-
-set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/tsmac34"
-set Para(ModuleName) "tsmac34"
-set Para(lib) "/home/greg/trispeed_mac_v3.4/lib"
-set Para(CoreName) "Tri-Speed Ethernet MAC"
-set Para(arch) "ep5m00"
-set Para(family) "latticeecp2m"
-set Para(Family) "latticeecp2m"
-set Para(design) "VHDL"
-set Para(install_dir) "/opt/lattice/diamond/1.1/bin/lin/../.."
-set Para(Bin) "/opt/lattice/diamond/1.1/bin/lin"
-set Para(SpeedGrade) "Para(spd)"
-set Para(FPGAPath) "/opt/lattice/diamond/1.1/bin/lin/../../ispfpga/bin/sol"
-
-lappend auto_path "/home/greg/trispeed_mac_v3.4/gui"
-
-lappend auto_path "/home/greg/trispeed_mac_v3.4/script"
-package require Core_Generate
-
-lappend auto_path "/opt/lattice/diamond/1.1/tcltk/lib/ipwidgets/ispipbuilder/../runproc"
-package require runcmd
-
-
-set Para(result) [GenerateCore]
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="tsmac34" module="Tri-Speed Ethernet MAC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 21 11:36:16.283" version="3.4" type="IP" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="pmi_ram_dpEbnonessdn208256208256.ngo" type="database" modified="2011 09 21 11:36:13.000"/>
- <File name="pmi_ram_dpEbnonessdn96649664.ngo" type="database" modified="2011 09 21 11:36:13.000"/>
- <File name="tsmac34.lpc" type="lpc" modified="2011 09 21 11:35:51.000"/>
- <File name="tsmac34.ngo" type="database" modified="2011 09 21 11:36:13.000"/>
- <File name="tsmac34_bb.v" type="black_box_verilog" modified="2011 09 21 11:35:51.000"/>
- <File name="tsmac34_beh.v" type="behavioral_verilog" modified="2011 09 21 11:35:51.000"/>
- <File name="tsmac34_inst.v" type="instantiation_verilog" modified="2011 09 21 11:35:51.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=ep5c00
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=IPCFG
-CoreStatus=Demo
-CoreName=Tri-Speed Ethernet MAC
-CoreRevision=3.4
-ModuleName=tsmac34
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/21/2011
-Time=11:35:51
-
-[Parameters]
-MIIM=No
-MODE=SGMII easy connect
-SYNP_TOOL=1
-PREC_TOOL=0
-MODS_TOOL=1
-ALDC_TOOL=0
-MULT_WB=NO
-LOOPBACK=NO
-STAT_REGS=NO
-
-[Files]
-Synthesis=
-Simulation=
-Logical=
-Physical=
-Misc=
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress \r
-// Filename: USERNAME.v \r
-// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
-module tsmac34 (\r
- // clock and reset\r
- hclk,\r
- txmac_clk,\r
- rxmac_clk,\r
- reset_n,\r
- txmac_clk_en,\r
- rxmac_clk_en,\r
-\r
- // Input signals to the GMII\r
- rxd,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
- // Input signals to the CPU Interface\r
- haddr,\r
- hdatain,\r
- hcs_n,\r
- hwrite_n,\r
- hread_n,\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- tx_fifodata,\r
- tx_fifoavail,\r
- tx_fifoeof,\r
- tx_fifoempty,\r
- tx_sndpaustim,\r
- tx_sndpausreq,\r
- tx_fifoctrl,\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- rx_fifo_full,\r
- ignore_pkt,\r
- \r
- // Output signals from the GMII\r
- txd,\r
- tx_en,\r
- tx_er,\r
- \r
- // Output signals from the CPU Interface\r
- hdataout,\r
- hdataout_en_n,\r
- hready_n,\r
- cpu_if_gbit_en,\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- tx_macread,\r
- tx_discfrm,\r
- tx_staten,\r
- tx_statvec,\r
- tx_done,\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
- );\r
- \r
- // ------------------------- clock and reset inputs ---------------------\r
- input hclk; // clock to the CPU I/F\r
- input txmac_clk; // clock to the Tx MAC\r
- input rxmac_clk; // clock to the RX MAC\r
- input reset_n; // Global reset\r
- input txmac_clk_en; // clock enable to the Tx MAC\r
- input rxmac_clk_en; // clock enable to the RX MAC\r
- \r
- // ----------------------- Input signals to the GMII -------------------\r
- input [7:0] rxd; // Receive data\r
- input rx_dv; // Receive data valid\r
- input rx_er; // Receive data error\r
- input col; // Collision detect\r
- input crs; // Carrier Sense\r
- // -------------------- Input signals to the CPU I/F -------------------\r
- input [7:0] haddr; // Address Bus\r
- input [7:0] hdatain; // Input data Bus\r
- input hcs_n; // Chip select\r
- input hwrite_n; // Register write\r
- input hread_n; // Register read\r
- \r
- // -------------------- Input signals to the MII I/F -------------------\r
-\r
- \r
- // ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
- input [7:0] tx_fifodata; // Data Input from FIFO\r
- input tx_fifoavail; // Data Available in FIFO\r
- input tx_fifoeof; // End of Frame\r
- input tx_fifoempty; // FIFO Empty\r
- input [15:0] tx_sndpaustim; // Pause frame parameter\r
- input tx_sndpausreq; // Transmit PAUSE frame\r
- input tx_fifoctrl; // Control frame or Not\r
- \r
- // ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
- input rx_fifo_full; // Receive FIFO Full\r
- input ignore_pkt; // Ignore the frame\r
- \r
- // -------------------- Output signals from the GMII -----------------------\r
- output [7:0] txd; // Transmit data\r
- output tx_en; // Transmit Enable\r
- output tx_er; // Transmit Error\r
- \r
- // -------------------- Output signals from the CPU I/F -------------------\r
- output [7:0] hdataout; // Output data Bus\r
- output hdataout_en_n; // Data Out Enable\r
- output hready_n; // Ready signal\r
- output cpu_if_gbit_en; // Gig or 10/100 mode\r
- \r
- // -------------------- Output signals from the MII I/F -------------------\r
-\r
- \r
- // ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
- output tx_macread; // Read FIFO\r
- output tx_discfrm; // Discard Frame\r
- output tx_staten; // Status Vector Valid\r
- output tx_done; // Transmit of Frame done\r
- output [30:0] tx_statvec; // Tx Status Vector\r
- \r
- // ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
- output rx_fifo_error; // FIFO full detected\r
- output [31:0] rx_stat_vector; // Rx Status Vector\r
- output [7:0] rx_dbout; // Data Output to FIFO\r
- output rx_write; // Write FIFO\r
- output rx_stat_en; // Status Vector Valid\r
- output rx_eof; // Entire frame written\r
- output rx_error; // Erroneous frame\r
- \r
- tsmac_core U1_LSC_ts_mac_core ( \r
-\r
- // clock and reset\r
- .hclk(hclk),\r
- .txmac_clk(txmac_clk),\r
- .rxmac_clk(rxmac_clk),\r
- .reset_n(reset_n),\r
- .txmac_clk_en(txmac_clk_en),\r
- .rxmac_clk_en(rxmac_clk_en),\r
- \r
- // Input signals to the GMII\r
- .rxd(rxd),\r
- .rx_dv(rx_dv),\r
- .rx_er(rx_er),\r
- .col(col),\r
- .crs(crs),\r
- // Input signals to the CPU Interface\r
- .haddr(haddr),\r
- .hdatain(hdatain),\r
- .hcs_n(hcs_n),\r
- .hwrite_n(hwrite_n),\r
- .hread_n(hread_n),\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- .tx_fifodata(tx_fifodata),\r
- .tx_fifoavail(tx_fifoavail),\r
- .tx_fifoeof(tx_fifoeof),\r
- .tx_fifoempty(tx_fifoempty),\r
- .tx_sndpaustim(tx_sndpaustim),\r
- .tx_sndpausreq(tx_sndpausreq),\r
- .tx_fifoctrl(tx_fifoctrl),\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- .rx_fifo_full(rx_fifo_full),\r
- .ignore_pkt(ignore_pkt),\r
- \r
- // Output signals from the GMII\r
- .txd(txd),\r
- .tx_en(tx_en),\r
- .tx_er(tx_er),\r
- \r
- // Output signals from the CPU Interface\r
- .hdataout(hdataout),\r
- .hdataout_en_n(hdataout_en_n),\r
- .hready_n(hready_n),\r
- .cpu_if_gbit_en(cpu_if_gbit_en),\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- .tx_macread(tx_macread),\r
- .tx_discfrm(tx_discfrm),\r
- .tx_staten(tx_staten),\r
- .tx_statvec(tx_statvec),\r
- .tx_done(tx_done),\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- .rx_fifo_error(rx_fifo_error),\r
- .rx_stat_vector(rx_stat_vector),\r
- .rx_dbout(rx_dbout),\r
- .rx_write(rx_write),\r
- .rx_stat_en(rx_stat_en),\r
- .rx_eof(rx_eof),\r
- .rx_error(rx_error)\r
- );\r
-endmodule\r
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress \r
-// Filename: USERNAME_bb.v \r
-// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
-module tsmac34 (\r
- // clock and reset\r
- hclk,\r
- txmac_clk,\r
- rxmac_clk,\r
- reset_n,\r
- txmac_clk_en,\r
- rxmac_clk_en,\r
-\r
- // Input signals to the GMII\r
- rxd,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
- \r
- // Input signals to the CPU Interface\r
- haddr,\r
- hdatain,\r
- hcs_n,\r
- hwrite_n,\r
- hread_n,\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- tx_fifodata,\r
- tx_fifoavail,\r
- tx_fifoeof,\r
- tx_fifoempty,\r
- tx_sndpaustim,\r
- tx_sndpausreq,\r
- tx_fifoctrl,\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- rx_fifo_full,\r
- ignore_pkt,\r
- \r
- // Output signals from the GMII\r
- txd,\r
- tx_en,\r
- tx_er,\r
- \r
- // Output signals from the CPU Interface\r
- hdataout,\r
- hdataout_en_n,\r
- hready_n,\r
- cpu_if_gbit_en,\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- tx_macread,\r
- tx_discfrm,\r
- tx_staten,\r
- tx_statvec,\r
- tx_done,\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
- );\r
- \r
- // ------------------------- clock and reset inputs ---------------------\r
- input hclk; // clock to the CPU I/F\r
- input txmac_clk; // clock to the Tx MAC\r
- input rxmac_clk; // clock to the RX MAC\r
- input reset_n; // Global reset\r
- input txmac_clk_en; // clock enable to the Tx MAC\r
- input rxmac_clk_en; // clock enable to the RX MAC\r
- \r
- // ----------------------- Input signals to the GMII -------------------\r
- input [7:0] rxd; // Receive data\r
- input rx_dv; // Receive data valid\r
- input rx_er; // Receive data error\r
- input col; // Collision detect\r
- input crs; // Carrier Sense\r
- // -------------------- Input signals to the CPU I/F -------------------\r
- input [7:0] haddr; // Address Bus\r
- input [7:0] hdatain; // Input data Bus\r
- input hcs_n; // Chip select\r
- input hwrite_n; // Register write\r
- input hread_n; // Register read\r
- \r
- // -------------------- Input signals to the MII I/F -------------------\r
-\r
- \r
- // ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
- input [7:0] tx_fifodata; // Data Input from FIFO\r
- input tx_fifoavail; // Data Available in FIFO\r
- input tx_fifoeof; // End of Frame\r
- input tx_fifoempty; // FIFO Empty\r
- input [15:0] tx_sndpaustim; // Pause frame parameter\r
- input tx_sndpausreq; // Transmit PAUSE frame\r
- input tx_fifoctrl; // Control frame or Not\r
- \r
- // ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
- input rx_fifo_full; // Receive FIFO Full\r
- input ignore_pkt; // Ignore the frame\r
- \r
- // -------------------- Output signals from the GMII -----------------------\r
- output [7:0] txd; // Transmit data\r
- output tx_en; // Transmit Enable\r
- output tx_er; // Transmit Error\r
- \r
- // -------------------- Output signals from the CPU I/F -------------------\r
- output [7:0] hdataout; // Output data Bus\r
- output hdataout_en_n; // Data Out Enable\r
- output hready_n; // Ready signal\r
- output cpu_if_gbit_en; // Gig or 10/100 mode\r
- \r
- // -------------------- Output signals from the MII I/F -------------------\r
-\r
- \r
- // ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
- output tx_macread; // Read FIFO\r
- output tx_discfrm; // Discard Frame\r
- output tx_staten; // Status Vector Valid\r
- output tx_done; // Transmit of Frame done\r
- output [30:0] tx_statvec; // Tx Status Vector\r
- \r
- // ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
- output rx_fifo_error; // FIFO full detected\r
- output [31:0] rx_stat_vector; // Rx Status Vector\r
- output [7:0] rx_dbout; // Data Output to FIFO\r
- output rx_write; // Write FIFO\r
- output rx_stat_en; // Status Vector Valid\r
- output rx_eof; // Entire frame written\r
- output rx_error; // Erroneous frame\r
- \r
-endmodule\r
+++ /dev/null
-// ts_mac_core_beh.v generated by Lattice IP Model Creator version 1\r
-// created on Wed Mar 23 11:57:00 CST 2011\r
-// Copyright(c) 2007~2011 Lattice Semiconductor Corporation. All rights reserved\r
-// obfuscator_exe version 1.mar0807\r
-\r
-// top\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module hd2df10 (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en, \r
- \r
- \r
- ks10d54, \r
- ls86aa0, \r
- \r
- \r
- ls35502,\r
- lfaa812,\r
- \r
- \r
- kd54097,\r
- rva04bd,\r
- cb25ef,\r
- wl12f7d\r
-);\r
-parameter gq97bed = 8;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input ks10d54;\r
-input ls35502;\r
-input lfaa812;\r
-input [gq97bed-1:0] ls86aa0;\r
-output rva04bd;\r
-output cb25ef;\r
-output wl12f7d;\r
-output [gq97bed-1:0] kd54097;\r
-reg rva04bd;\r
-reg cb25ef;\r
-reg wl12f7d;\r
-reg [gq97bed-1:0] kd54097;\r
-reg wl95504;\r
-parameter jraa825 = 2;\r
-parameter uv5412f = 2'b01;\r
-parameter tja097d = 2'b10;\r
-parameter ng4bee = 0;\r
-parameter fc25f73 = 1;\r
-parameter fc2fb9a = 8'hd5;\r
-parameter me7dcd3 = 8'h55;\r
-wire zkee699;\r
-wire ne734ca;\r
-reg ep9a653;\r
-reg uvd329c;\r
-reg ng994e4;\r
-reg [jraa825-1:0] os5391b;\r
-reg [2:0] vk9c8d9;\r
-reg [jraa825-1:0] oh23653;\r
-reg zm1b29c;\r
-reg [gq97bed - 1 : 0] neca715;\r
-reg ic538ab;\r
-reg zm9c559;\r
-reg kde2acb;\r
-reg wy1565d;\r
-reg irab2e9;\r
-reg go5974c;\r
-reg mecba61;\r
-reg xw5d308;\r
-reg [jraa825 - 1 : 0] go4c21e;\r
-reg [2 : 0] dz610f0;\r
-reg [jraa825 - 1 : 0] ic43c3c;\r
-reg [2047:0] ng1e1e0;\r
-wire [12:0] mef0f02;\r
-\r
-localparam uk87811 = 13,gd3c088 = 32'hfdfff40b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
- \r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin kd54097 <= 0; end else if (rxmac_clk_en) begin if (zm1b29c) begin kd54097 <= neca715; end end\r
-end\r
-\r
-\r
-\r
-\r
-assign zkee699 = neca715[7:0] == fc2fb9a;\r
-assign ne734ca = neca715[7:0] == me7dcd3;\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin oh23653 <= uv5412f; vk9c8d9 <= 3'b0; rva04bd <= 1'b0; wl12f7d <= 1'b0; wl95504 <= 1'b0; cb25ef <= 1'b0; end else if (rxmac_clk_en) begin oh23653 <= go4c21e; wl95504 <= go5974c; cb25ef <= kde2acb; rva04bd <= 1'b0; \r
- vk9c8d9 <= xw5d308 ? 3'h1 : (|dz610f0) ? (dz610f0+3'h1) : ic43c3c[ng4bee] ? 3'h0 : dz610f0;\r
- if (mecba61) begin wl12f7d <= 1'b1; end else if (zm9c559) begin wl12f7d <= 1'b0; end else if (ic538ab) begin wl12f7d <= 1'b0; end end\r
-end\r
-\r
-\r
-always @(ic43c3c or ic538ab or irab2e9 or wy1565d or dz610f0) begin case(ic43c3c) uv5412f : begin if (ic538ab && wy1565d) begin os5391b = uv5412f; ep9a653 = 1'b1; uvd329c = 1'b0; ng994e4 = 1'b0; end else if (ic538ab && irab2e9) begin os5391b = tja097d; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b1; end else if (ic538ab && !wy1565d && !irab2e9) begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b1; ng994e4 = 1'b0; end\r
- else begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b0; end end\r
- tja097d : begin if (wy1565d) begin os5391b = uv5412f; ep9a653 = 1'b1; uvd329c = 1'b0; ng994e4 = 1'b0; end else if (~|dz610f0 & ~irab2e9) begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b1; ng994e4 = 1'b0; end else begin os5391b = tja097d; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b0; end\r
- end\r
- default : begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b0; end endcase\r
-end\r
-\r
-always@* begin zm1b29c<=mef0f02[0];neca715<={ls86aa0>>1,mef0f02[1]};ic538ab<=mef0f02[2];zm9c559<=mef0f02[3];kde2acb<=mef0f02[4];wy1565d<=mef0f02[5];irab2e9<=mef0f02[6];go5974c<=mef0f02[7];mecba61<=mef0f02[8];xw5d308<=mef0f02[9];go4c21e<={os5391b>>1,mef0f02[10]};dz610f0<={vk9c8d9>>1,mef0f02[11]};ic43c3c<={oh23653>>1,mef0f02[12]};end\r
-always@* begin ng1e1e0[2047]<=ls86aa0[0];ng1e1e0[2046]<=ls35502;ng1e1e0[2044]<=lfaa812;ng1e1e0[2040]<=wl95504;ng1e1e0[2032]<=zkee699;ng1e1e0[2016]<=ne734ca;ng1e1e0[1984]<=ep9a653;ng1e1e0[1920]<=uvd329c;ng1e1e0[1793]<=ng994e4;ng1e1e0[1539]<=os5391b[0];ng1e1e0[1030]<=vk9c8d9[0];ng1e1e0[1023]<=ks10d54;ng1e1e0[13]<=oh23653[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module xl8b21c (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- bn1ce70,\r
- cb25ef,\r
-\r
- \r
- lfaa812,\r
- ykce1a5,\r
-\r
- \r
- uv70d29,\r
- hq8694d,\r
- ec34a6a,\r
- lfa5351,\r
- gd29a8f,\r
- rg4d47c,\r
- mr6a3e2,\r
- of51f14,\r
- sj8f8a4,\r
- tu7c524,\r
- ale2922,\r
- vk14915,\r
-\r
- \r
- wla48aa,\r
-\r
- \r
- ks24554,\r
- zz22aa1,\r
- mg1550f,\r
- hdaa879,\r
- en543cf,\r
- uxa1e7d,\r
- ukf3ec\r
-);\r
-parameter gq97bed = 8;\r
-parameter hocfb0b = 48;\r
-parameter ic7d85a = 6;\r
-parameter vvec2d1 = 8;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input cb25ef;\r
-input lfaa812;\r
-input ykce1a5;\r
-input [gq97bed-1:0] bn1ce70;\r
-input [vvec2d1-1:0] uv70d29;\r
-input [vvec2d1-1:0] hq8694d;\r
-input [vvec2d1-1:0] ec34a6a;\r
-input [vvec2d1-1:0] lfa5351;\r
-input [vvec2d1-1:0] gd29a8f;\r
-input [vvec2d1-1:0] rg4d47c;\r
-input [vvec2d1-1:0] mr6a3e2;\r
-input [vvec2d1-1:0] of51f14;\r
-input [hocfb0b-1:0] sj8f8a4;\r
-input tu7c524;\r
-input ale2922;\r
-input vk14915;\r
-input [ic7d85a-1:0] wla48aa;\r
-output zz22aa1;\r
-output mg1550f;\r
-output hdaa879;\r
-output en543cf;\r
-output uxa1e7d;\r
-output ukf3ec;\r
-output ks24554;\r
-reg en543cf;\r
-reg uxa1e7d;\r
-reg ukf3ec;\r
-reg zz22aa1;\r
-localparam zx5f6d5 = 11;\r
-localparam fafb6ae = 11'b00000000001;\r
-localparam uidb573 = 11'b00000000010;\r
-localparam rgdab98 = 11'b00000000100;\r
-localparam xwd5cc3 = 11'b00000001000;\r
-localparam mtae61a = 11'b00000010000;\r
-localparam ne730d4 = 11'b00000100000;\r
-localparam co986a3 = 11'b00001000000;\r
-localparam ipc3519 = 11'b00010000000;\r
-localparam qi1a8cd = 11'b00100000000;\r
-localparam osd4669 = 11'b01000000000;\r
-localparam uka3349 = 11'b10000000000;\r
-localparam ng4bee = 0;\r
-localparam fc25f73 = 1;\r
-localparam lq69236 = 2;\r
-localparam ic491b3 = 3;\r
-localparam rg48d98 = 4;\r
-localparam os46cc3 = 5;\r
-localparam kf36618 = 6;\r
-localparam ecb30c5 = 7;\r
-localparam ie98629 = 8;\r
-localparam enc3149 = 9;\r
-localparam mt18a4d = 10;\r
-wire fac526c;\r
-wire qv29362;\r
-wire ww49b15;\r
-wire dm4d8a9;\r
-wire ho6c54b;\r
-wire cm62a5b;\r
-reg ks152d9;\r
-reg oua96c9;\r
-reg [zx5f6d5-1:0] wj5b24d;\r
-reg [zx5f6d5-1:0] enc9365;\r
-wire kq49b2c;\r
-wire lq4d961;\r
-wire tu6cb0b;\r
-wire sh6585a;\r
-wire gd2c2d4;\r
-wire xj616a5;\r
-reg xyb52f;\r
-reg nr5a97b;\r
-reg [zx5f6d5-1:0] jra5ef8;\r
-reg [zx5f6d5-1:0] hb7be32;\r
-wire hodf196;\r
-reg shf8cb2;\r
-reg [vvec2d1-1:0] bn32cad;\r
-reg hq9656e;\r
-reg ngb2b72;\r
-wire an95b92;\r
-reg jeadc94;\r
-reg rt6e4a2;\r
-reg [zx5f6d5-1:0] co928b1;\r
-reg [zx5f6d5-1:0] baa2c4f;\r
-wire fp1627b;\r
-wire yzb13de;\r
-wire je89ef4;\r
-reg fn4f7a3;\r
-reg zx7bd1f;\r
-reg uide8fe;\r
-reg vif47f1;\r
-reg ksa3f8a;\r
-reg wy1fc51;\r
-reg lqfe289;\r
-reg rgf144b;\r
-reg ks24554;\r
-reg [gq97bed - 1 : 0] je896ad;\r
-reg al4b56a;\r
-reg zm9c559;\r
-reg byd5aaf;\r
-reg [vvec2d1 - 1 : 0] gb6abd3;\r
-reg [vvec2d1 - 1 : 0] ntaf4ee;\r
-reg [vvec2d1 - 1 : 0] czd3bb5;\r
-reg [vvec2d1 - 1 : 0] dmeed68;\r
-reg [vvec2d1 - 1 : 0] dbb5a1a;\r
-reg [vvec2d1 - 1 : 0] go686bb;\r
-reg [vvec2d1 - 1 : 0] ie1aec9;\r
-reg [vvec2d1 - 1 : 0] yzbb24e;\r
-reg [hocfb0b - 1 : 0] gbc93ad;\r
-reg ay49d6c;\r
-reg kd4eb61;\r
-reg ip75b0c;\r
-reg [ic7d85a - 1 : 0] lq6c32a;\r
-reg ld61953;\r
-reg dbca9e;\r
-reg ip654f7;\r
-reg hq2a7bd;\r
-reg yk53dea;\r
-reg zz9ef51;\r
-reg kdf7a8f;\r
-reg babd47c;\r
-reg [zx5f6d5 - 1 : 0] yx51f10;\r
-reg [zx5f6d5 - 1 : 0] jc7c424;\r
-reg yxe2122;\r
-reg aa10914;\r
-reg lf848a0;\r
-reg ou24507;\r
-reg fp22839;\r
-reg je141cf;\r
-reg jra0e7b;\r
-reg mt73de;\r
-reg [zx5f6d5 - 1 : 0] rgcf7ad;\r
-reg [zx5f6d5 - 1 : 0] icdeb5e;\r
-reg cmf5af1;\r
-reg twad789;\r
-reg [vvec2d1 - 1 : 0] cz5e25f;\r
-reg dmf12fc;\r
-reg xy897e2;\r
-reg ip4bf12;\r
-reg th5f894;\r
-reg pffc4a7;\r
-reg [zx5f6d5 - 1 : 0] wl129f4;\r
-reg [zx5f6d5 - 1 : 0] doa7d2e;\r
-reg sw3e973;\r
-reg rgf4b98;\r
-reg lfa5cc3;\r
-reg aa2e61e;\r
-reg vi730f0;\r
-reg ou98783;\r
-reg alc3c19;\r
-reg ba1e0cc;\r
-reg uif0662;\r
-reg do83310;\r
-reg fp19883;\r
-reg [2047:0] ng1e1e0;\r
-wire [57:0] mef0f02;\r
-\r
-localparam uk87811 = 58,gd3c088 = 32'hfdffc68b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-assign fp1627b = (jc7c424[os46cc3] | jc7c424[mt18a4d]) & (ip75b0c | kdf7a8f | jra0e7b | (kd4eb61 & th5f894));\r
-assign je89ef4 = (jc7c424[os46cc3] | jc7c424[mt18a4d]) & ~sw3e973;\r
-assign yzb13de = aa2e61e & ~(vi730f0 | (xy897e2 & ay49d6c & twad789));\r
-\r
-assign mg1550f = ba1e0cc | alc3c19;\r
-\r
-assign hdaa879 = uif0662 | ou98783;\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin vif47f1 <= 1'b0; ksa3f8a <= 1'b0; wy1fc51 <= 1'b0; lqfe289 <= 1'b0; rgf144b <= 1'b0; enc9365 <= fafb6ae; hb7be32 <= fafb6ae; baa2c4f <= fafb6ae; zz22aa1 <= 1'b0; zx7bd1f <= 1'b0; ukf3ec <= 1'b0; en543cf <= 1'b0; uxa1e7d <= 1'b0; hq9656e <= 1'b0; ngb2b72 <= 1'b0; fn4f7a3 <= 1'b0; uide8fe <= 1'b0; end else if (rxmac_clk_en) begin rgf144b <= byd5aaf; vif47f1 <= (xy897e2 & ay49d6c & twad789); ksa3f8a <= vi730f0; wy1fc51 <= rgf4b98; lqfe289 <= al4b56a; if(fp19883) begin enc9365 <= fafb6ae; hb7be32 <= fafb6ae; baa2c4f <= fafb6ae; end else begin enc9365 <= yx51f10; hb7be32 <= rgcf7ad; baa2c4f <= wl129f4; end zx7bd1f <= sw3e973; fn4f7a3 <= lfa5cc3; ngb2b72 <= cmf5af1; if (al4b56a) hq9656e <= je896ad[0]; if (kdf7a8f) zz22aa1 <= kdf7a8f; else if (zm9c559) zz22aa1 <= kdf7a8f; else zz22aa1 <= zz22aa1; if (jra0e7b) ukf3ec <= jra0e7b; else if (zm9c559) ukf3ec <= jra0e7b; else ukf3ec <= ukf3ec; if (rgf4b98 | zm9c559) uide8fe <= rgf4b98; else if (al4b56a) uide8fe <= 1'b0; else uide8fe <= ou98783; if (cmf5af1) en543cf <= (cmf5af1); else if (zm9c559) en543cf <= cmf5af1; else if (al4b56a) en543cf <= 1'b0; else en543cf <= en543cf; if (th5f894) uxa1e7d <= th5f894; else if (zm9c559) uxa1e7d <= th5f894; else if (do83310) uxa1e7d <= 1'b0; else uxa1e7d <= uxa1e7d; end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-assign cm62a5b = gbc93ad[47:40] == je896ad;\r
-\r
-assign ho6c54b = gbc93ad[39:32] == je896ad;\r
-\r
-assign dm4d8a9 = gbc93ad[31:24] == je896ad;\r
-\r
-assign ww49b15 = gbc93ad[23:16] == je896ad;\r
-\r
-assign qv29362 = gbc93ad[15:8] == je896ad;\r
-\r
-assign fac526c = gbc93ad[7:0] == je896ad;\r
-\r
-\r
-always @(jc7c424 or al4b56a or ld61953 or dbca9e or ip654f7 or hq2a7bd or yk53dea or zz9ef51) begin ks24554 = 1'b1; case(jc7c424) fafb6ae : begin if (!al4b56a) begin wj5b24d = fafb6ae; ks152d9 = 1'b0; oua96c9 = 1'b0; ks24554 = 1'b0; end else if (al4b56a) begin if (zz9ef51) begin wj5b24d = uidb573; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = co986a3; ks152d9 = 1'b0; oua96c9 = 1'b0; end end end uidb573 : begin if (yk53dea) begin wj5b24d = rgdab98; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = ipc3519; ks152d9 = 1'b0; oua96c9 = 1'b0; end end rgdab98 : begin if (hq2a7bd) begin wj5b24d = xwd5cc3; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = qi1a8cd; ks152d9 = 1'b0; oua96c9 = 1'b0; end end xwd5cc3 : begin if (ip654f7) begin wj5b24d = mtae61a; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = osd4669; ks152d9 = 1'b0; oua96c9 = 1'b0; end end mtae61a : begin if (dbca9e) begin wj5b24d = ne730d4; ks152d9 = 1'b0; oua96c9 = 1'b0; end else begin wj5b24d = uka3349; ks152d9 = 1'b0; oua96c9 = 1'b0; end end ne730d4 : begin if (ld61953) begin wj5b24d = fafb6ae; ks152d9 = 1'b1; oua96c9 = 1'b0; end else begin wj5b24d = fafb6ae; ks152d9 = 1'b0; oua96c9 = 1'b1; end end co986a3 : begin wj5b24d = ipc3519; ks152d9 = 1'b0; oua96c9 = 1'b0; end ipc3519 : begin wj5b24d = qi1a8cd; ks152d9 = 1'b0; oua96c9 = 1'b0; end qi1a8cd : begin wj5b24d = osd4669; ks152d9 = 1'b0; oua96c9 = 1'b0; end osd4669 : begin wj5b24d = uka3349; ks152d9 = 1'b0; oua96c9 = 1'b0; end uka3349 : begin wj5b24d = fafb6ae; ks152d9 = 1'b0; oua96c9 = 1'b1; end default : begin wj5b24d = fafb6ae; ks152d9 = 1'b0; oua96c9 = 1'b0; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign xj616a5 = 8'h01 == je896ad;\r
-\r
-assign gd2c2d4 = 8'h80 == je896ad;\r
-\r
-assign sh6585a = 8'hc2 == je896ad;\r
-\r
-assign tu6cb0b = 8'h00 == je896ad;\r
-\r
-assign lq4d961 = 8'h00 == je896ad;\r
-\r
-assign kq49b2c = 8'h01 == je896ad;\r
-\r
-\r
-always @(icdeb5e or al4b56a or yxe2122 or aa10914 or lf848a0 or ou24507 or fp22839 or je141cf) begin case(icdeb5e) fafb6ae : begin if (!al4b56a) begin jra5ef8 = fafb6ae; xyb52f = 1'b0; nr5a97b = 1'b0; end else if (al4b56a) begin if (je141cf) begin jra5ef8 = uidb573; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = co986a3; xyb52f = 1'b0; nr5a97b = 1'b0; end end end uidb573 : begin if (fp22839) begin jra5ef8 = rgdab98; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = ipc3519; xyb52f = 1'b0; nr5a97b = 1'b0; end end rgdab98 : begin if (ou24507) begin jra5ef8 = xwd5cc3; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = qi1a8cd; xyb52f = 1'b0; nr5a97b = 1'b0; end end xwd5cc3 : begin if (lf848a0) begin jra5ef8 = mtae61a; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = osd4669; xyb52f = 1'b0; nr5a97b = 1'b0; end end mtae61a : begin if (aa10914) begin jra5ef8 = ne730d4; xyb52f = 1'b0; nr5a97b = 1'b0; end else begin jra5ef8 = uka3349; xyb52f = 1'b0; nr5a97b = 1'b0; end end ne730d4 : begin if (yxe2122) begin jra5ef8 = fafb6ae; xyb52f = 1'b1; nr5a97b = 1'b0; end else begin jra5ef8 = fafb6ae; xyb52f = 1'b0; nr5a97b = 1'b1; end end co986a3 : begin jra5ef8 = ipc3519; xyb52f = 1'b0; nr5a97b = 1'b0; end ipc3519 : begin jra5ef8 = qi1a8cd; xyb52f = 1'b0; nr5a97b = 1'b0; end qi1a8cd : begin jra5ef8 = osd4669; xyb52f = 1'b0; nr5a97b = 1'b0; end osd4669 : begin jra5ef8 = uka3349; xyb52f = 1'b0; nr5a97b = 1'b0; end uka3349 : begin jra5ef8 = fafb6ae; xyb52f = 1'b0; nr5a97b = 1'b1; end default : begin jra5ef8 = fafb6ae; xyb52f = 1'b0; nr5a97b = 1'b0; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign hodf196 = dmf12fc & jc7c424[mt18a4d] & ~th5f894 & ~jra0e7b ;\r
-\r
-always @ (lq6c32a[5:3] or gb6abd3 or ntaf4ee or czd3bb5 or dmeed68 or dbb5a1a or go686bb or ie1aec9 or yzbb24e) begin case (lq6c32a[5:3]) 3'b000 : begin bn32cad = gb6abd3; end 3'b001 : begin bn32cad = ntaf4ee; end 3'b010 : begin bn32cad = czd3bb5; end 3'b011 : begin bn32cad = dmeed68; end 3'b100 : begin bn32cad = dbb5a1a; end 3'b101 : begin bn32cad = go686bb; end 3'b110 : begin bn32cad = ie1aec9; end 3'b111 : begin bn32cad = yzbb24e; end endcase\r
-end\r
-\r
-always @ (lq6c32a[2:0] or cz5e25f) begin case (lq6c32a[2:0]) 3'b000 : begin shf8cb2 = cz5e25f[0]; end 3'b001 : begin shf8cb2 = cz5e25f[1]; end 3'b010 : begin shf8cb2 = cz5e25f[2]; end 3'b011 : begin shf8cb2 = cz5e25f[3]; end 3'b100 : begin shf8cb2 = cz5e25f[4]; end 3'b101 : begin shf8cb2 = cz5e25f[5]; end 3'b110 : begin shf8cb2 = cz5e25f[6]; end 3'b111 : begin shf8cb2 = cz5e25f[7]; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign an95b92 = 8'hff == je896ad;\r
-\r
-\r
-always @(doa7d2e or al4b56a or ip4bf12) begin case(doa7d2e) fafb6ae : begin if (!al4b56a) begin co928b1 = fafb6ae; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else if (al4b56a) begin if (ip4bf12) begin co928b1 = uidb573; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = co986a3; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end end uidb573 : begin if (ip4bf12) begin co928b1 = rgdab98; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = ipc3519; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end rgdab98 : begin if (ip4bf12) begin co928b1 = xwd5cc3; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = qi1a8cd; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end xwd5cc3 : begin if (ip4bf12) begin co928b1 = mtae61a; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = osd4669; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end mtae61a : begin if (ip4bf12) begin co928b1 = ne730d4; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end else begin co928b1 = uka3349; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end end ne730d4 : begin if (ip4bf12) begin co928b1 = fafb6ae; jeadc94 = 1'b1; rt6e4a2 = 1'b0; end else begin co928b1 = fafb6ae; jeadc94 = 1'b0; rt6e4a2 = 1'b1; end end co986a3 : begin co928b1 = ipc3519; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end ipc3519 : begin co928b1 = qi1a8cd; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end qi1a8cd : begin co928b1 = osd4669; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end osd4669 : begin co928b1 = uka3349; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end uka3349 : begin co928b1 = fafb6ae; jeadc94 = 1'b0; rt6e4a2 = 1'b1; end default : begin co928b1 = fafb6ae; jeadc94 = 1'b0; rt6e4a2 = 1'b0; end endcase\r
-end\r
-\r
-always@* begin je896ad<={bn1ce70>>1,mef0f02[0]};al4b56a<=mef0f02[1];zm9c559<=mef0f02[2];byd5aaf<=mef0f02[3];gb6abd3<={uv70d29>>1,mef0f02[4]};ntaf4ee<={hq8694d>>1,mef0f02[5]};czd3bb5<={ec34a6a>>1,mef0f02[6]};dmeed68<={lfa5351>>1,mef0f02[7]};dbb5a1a<={gd29a8f>>1,mef0f02[8]};go686bb<={rg4d47c>>1,mef0f02[9]};ie1aec9<={mr6a3e2>>1,mef0f02[10]};yzbb24e<={of51f14>>1,mef0f02[11]};gbc93ad<={sj8f8a4>>1,mef0f02[12]};ay49d6c<=mef0f02[13];kd4eb61<=mef0f02[14];ip75b0c<=mef0f02[15];lq6c32a<={wla48aa>>1,mef0f02[16]};ld61953<=mef0f02[17];dbca9e<=mef0f02[18];ip654f7<=mef0f02[19];hq2a7bd<=mef0f02[20];yk53dea<=mef0f02[21];zz9ef51<=mef0f02[22];kdf7a8f<=mef0f02[23];babd47c<=mef0f02[24];yx51f10<={wj5b24d>>1,mef0f02[25]};jc7c424<={enc9365>>1,mef0f02[26]};yxe2122<=mef0f02[27];aa10914<=mef0f02[28];lf848a0<=mef0f02[29];ou24507<=mef0f02[30];fp22839<=mef0f02[31];je141cf<=mef0f02[32];jra0e7b<=mef0f02[33];mt73de<=mef0f02[34];rgcf7ad<={jra5ef8>>1,mef0f02[35]};icdeb5e<={hb7be32>>1,mef0f02[36]};cmf5af1<=mef0f02[37];twad789<=mef0f02[38];cz5e25f<={bn32cad>>1,mef0f02[39]};dmf12fc<=mef0f02[40];xy897e2<=mef0f02[41];ip4bf12<=mef0f02[42];th5f894<=mef0f02[43];pffc4a7<=mef0f02[44];wl129f4<={co928b1>>1,mef0f02[45]};doa7d2e<={baa2c4f>>1,mef0f02[46]};sw3e973<=mef0f02[47];rgf4b98<=mef0f02[48];lfa5cc3<=mef0f02[49];aa2e61e<=mef0f02[50];vi730f0<=mef0f02[51];ou98783<=mef0f02[52];alc3c19<=mef0f02[53];ba1e0cc<=mef0f02[54];uif0662<=mef0f02[55];do83310<=mef0f02[56];fp19883<=mef0f02[57];end\r
-always@* begin ng1e1e0[2047]<=cb25ef;ng1e1e0[2046]<=lfaa812;ng1e1e0[2044]<=ykce1a5;ng1e1e0[2040]<=uv70d29[0];ng1e1e0[2032]<=hq8694d[0];ng1e1e0[2017]<=ec34a6a[0];ng1e1e0[1987]<=lfa5351[0];ng1e1e0[1980]<=je89ef4;ng1e1e0[1963]<=xyb52f;ng1e1e0[1942]<=ksa3f8a;ng1e1e0[1926]<=gd29a8f[0];ng1e1e0[1921]<=ks152d9;ng1e1e0[1913]<=fn4f7a3;ng1e1e0[1903]<=an95b92;ng1e1e0[1879]<=nr5a97b;ng1e1e0[1837]<=wy1fc51;ng1e1e0[1805]<=rg4d47c[0];ng1e1e0[1795]<=oua96c9;ng1e1e0[1783]<=baa2c4f[0];ng1e1e0[1778]<=zx7bd1f;ng1e1e0[1758]<=jeadc94;ng1e1e0[1710]<=jra5ef8[0];ng1e1e0[1679]<=wla48aa[0];ng1e1e0[1627]<=lqfe289;ng1e1e0[1562]<=mr6a3e2[0];ng1e1e0[1543]<=wj5b24d[0];ng1e1e0[1519]<=fp1627b;ng1e1e0[1509]<=uide8fe;ng1e1e0[1499]<=hq9656e;ng1e1e0[1469]<=rt6e4a2;ng1e1e0[1398]<=shf8cb2;ng1e1e0[1373]<=hb7be32[0];ng1e1e0[1310]<=fac526c;ng1e1e0[1207]<=rgf144b;ng1e1e0[1144]<=ww49b15;ng1e1e0[1076]<=of51f14[0];ng1e1e0[1039]<=enc9365[0];ng1e1e0[1023]<=bn1ce70[0];ng1e1e0[990]<=yzb13de;ng1e1e0[981]<=xj616a5;ng1e1e0[971]<=vif47f1;ng1e1e0[960]<=cm62a5b;ng1e1e0[951]<=ngb2b72;ng1e1e0[891]<=co928b1[0];ng1e1e0[839]<=vk14915;ng1e1e0[749]<=bn32cad[0];ng1e1e0[699]<=hodf196;ng1e1e0[572]<=qv29362;ng1e1e0[490]<=gd2c2d4;ng1e1e0[480]<=ho6c54b;ng1e1e0[419]<=ale2922;ng1e1e0[245]<=sh6585a;ng1e1e0[240]<=dm4d8a9;ng1e1e0[209]<=tu7c524;ng1e1e0[122]<=tu6cb0b;ng1e1e0[104]<=sj8f8a4[0];ng1e1e0[61]<=lq4d961;ng1e1e0[30]<=kq49b2c;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module uvd3c42 (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- tu42b90,\r
- wy15c82,\r
- epae410,\r
-\r
- \r
- rx_fifo_full,\r
-\r
- \r
- ep90421,\r
-\r
- \r
- sw8210d,\r
- sw10869,\r
- zz84348,\r
- sw21a46,\r
-\r
- \r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
-);\r
-parameter gq97bed = 8;\r
-parameter ofd97a2 = 20;\r
-parameter ykcbd15 = 32;\r
-parameter qt5e8a8 = 8;\r
-parameter psf4545 = 4;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input wy15c82;\r
-input tu42b90;\r
-input [1:0] epae410;\r
-input rx_fifo_full;\r
-input [ofd97a2-1:0] ep90421;\r
-output [qt5e8a8-1:0] sw8210d;\r
-output [qt5e8a8-1:0] sw10869;\r
-output zz84348;\r
-output sw21a46;\r
-output rx_fifo_error;\r
-output [ykcbd15-1:0] rx_stat_vector;\r
-output [gq97bed-1:0] rx_dbout;\r
-output rx_write;\r
-output rx_stat_en;\r
-output rx_eof;\r
-output rx_error;\r
-reg [qt5e8a8:0] of4bc4f;\r
-reg [qt5e8a8:0] vif13e4;\r
-wire zz84348;\r
-wire sw21a46;\r
-reg rx_fifo_error;\r
-reg [ykcbd15-1:0] rx_stat_vector;\r
-reg [gq97bed-1:0] rx_dbout ;\r
-reg [gq97bed-1:0] hd9bdf7;\r
-reg [gq97bed-1:0] wjf7df9;\r
-reg rx_write ;\r
-reg ipf7e64;\r
-reg ntbf324;\r
-reg jpf9927;\r
-reg rx_stat_en;\r
-reg rx_eof;\r
-reg rx_error;\r
-reg [ofd97a2-1:0] tw3fb87;\r
-reg alfdc3a;\r
-wire hoee1d5;\r
-wire al70eaa;\r
-reg co87555;\r
-reg vk3aaa9;\r
-reg psd554a;\r
-wire fpaaa53;\r
-reg [psf4545-1:0] coa94ff;\r
-reg rt4a7f9;\r
-wire [qt5e8a8:0] wl9fe79;\r
-reg [qt5e8a8:0] ldf9e69;\r
-reg rgcf34f;\r
-reg ps79a7b;\r
-reg zxcd3db;\r
-reg xw69ede;\r
-reg zx4f6f2;\r
-reg dz7b797;\r
-reg [1 : 0] eadbcbf;\r
-reg wwde5f9;\r
-reg [ofd97a2 - 1 : 0] ks97e44;\r
-reg [qt5e8a8 : 0] pff910f;\r
-reg [qt5e8a8 : 0] wj443f7;\r
-reg [gq97bed - 1 : 0] ukfde0;\r
-reg [gq97bed - 1 : 0] off7806;\r
-reg gqbc034;\r
-reg yke01a0;\r
-reg ecd01;\r
-reg [ofd97a2 - 1 : 0] aa3404e;\r
-reg bna0270;\r
-reg do1387;\r
-reg bn9c3a;\r
-reg sh4e1d7;\r
-reg yx70ebd;\r
-reg mg875ed;\r
-reg xy3af69;\r
-reg [psf4545 - 1 : 0] ribda57;\r
-reg ofed2bb;\r
-reg [qt5e8a8 : 0] fn4aeeb;\r
-reg [qt5e8a8 : 0] gdbbaf2;\r
-reg bldd794;\r
-reg zkebca7;\r
-reg sh5e53b;\r
-reg czf29dc;\r
-reg [2047:0] ng1e1e0;\r
-wire [27:0] mef0f02;\r
-\r
-localparam uk87811 = 28,gd3c088 = 32'hfdffc68b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-assign sw8210d = pff910f[qt5e8a8-1:0];\r
-assign sw10869 = wj443f7[qt5e8a8-1:0];\r
-assign wl9fe79 = ({(pff910f[qt5e8a8] ^ wj443f7[qt5e8a8]), pff910f[qt5e8a8-1:0]}) - ({1'b0, wj443f7[qt5e8a8-1:0]});\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin alfdc3a <= 0; co87555 <= 0; end else if (rxmac_clk_en) begin co87555 <= bn9c3a; if ((|ribda57) | (do1387)) begin alfdc3a <= 1; end else begin alfdc3a <= 0; end end\r
-end\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin coa94ff <= 4'h0; rt4a7f9 <= 1'b0; psd554a <= 1'b0; of4bc4f <= 9'd0; vif13e4 <= 9'd0; ldf9e69 <= 9'd0; rgcf34f <= 1'b0; ps79a7b <= 1'b0; tw3fb87 <= 1'b0; rx_stat_vector <= 32'b0; rx_dbout <= 8'd0; hd9bdf7 <= 8'd0; wjf7df9 <= 8'd0; rx_write <= 1'b0; ipf7e64 <= 1'b0; ntbf324 <= 1'b0; jpf9927 <= 1'b0; rx_stat_en <= 1'b0; rx_eof <= 1'b0; rx_error <= 1'b0; vk3aaa9 <= 1'b0; zxcd3db <= 1'b0; xw69ede <= 1'b0; rx_fifo_error <= 1'b0; end else if (rxmac_clk_en) begin tw3fb87 <= ks97e44;\r
- rx_fifo_error <= xy3af69 | (rx_fifo_error & ~rx_eof); if ((zx4f6f2 == 1) & (eadbcbf == 3)) begin vk3aaa9 <= 1; end else begin vk3aaa9 <= 0; end zxcd3db <= yx70ebd; xw69ede <= dz7b797; if (mg875ed == 1) begin coa94ff <= 0; end else if (!bn9c3a && sh5e53b) begin coa94ff <= ribda57 + 4'b0001; end else if (bn9c3a && !sh5e53b) begin coa94ff <= ribda57 - 4'b0001; end if ((fn4aeeb[qt5e8a8-1:1] == 0) && ((fn4aeeb[0] == 0) || (zz84348 == 1))) begin psd554a <= 1; end else begin psd554a <= 0; end if (fn4aeeb[qt5e8a8-1:2] == 6'b111111) begin rt4a7f9 <= 1; end else begin rt4a7f9 <= 0; end\r
- if (yx70ebd) ldf9e69 <= pff910f + 8'd1; if (zx4f6f2) of4bc4f <= pff910f + 8'd1; else if (czf29dc) of4bc4f <= gdbbaf2; if (zz84348) vif13e4 <= wj443f7 + 8'd1; \r
- rgcf34f <= zz84348; ps79a7b <= bldd794; if (aa3404e[18]) begin rx_stat_vector <= {aa3404e[15:0], ks97e44[15:0]}; end wjf7df9 <= aa3404e[7:0]; hd9bdf7 <= off7806; rx_dbout <= ukfde0; ntbf324 <= zkebca7 & ~wwde5f9 & ~aa3404e[19]; ipf7e64 <= yke01a0; rx_write <= gqbc034; jpf9927 <= bldd794 & aa3404e[18]; rx_stat_en <= ecd01; rx_eof <= zkebca7 & aa3404e[17]; rx_error <= zkebca7 & aa3404e[16]; end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign hoee1d5 = (fn4aeeb[qt5e8a8-1:0] >= 7'h42);\r
-\r
-\r
-assign sw21a46 = zx4f6f2 & ~ofed2bb;\r
-assign zz84348 = bna0270 & ~mg875ed & ~bn9c3a & ~sh4e1d7;\r
-\r
-\r
-assign al70eaa = bldd794 & aa3404e[18];\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign fpaaa53 = (bna0270 | rx_write) & wwde5f9 & ~mg875ed & ~bn9c3a;\r
-\r
-always@* begin zx4f6f2<=mef0f02[0];dz7b797<=mef0f02[1];eadbcbf<={epae410>>1,mef0f02[2]};wwde5f9<=mef0f02[3];ks97e44<={ep90421>>1,mef0f02[4]};pff910f<={of4bc4f>>1,mef0f02[5]};wj443f7<={vif13e4>>1,mef0f02[6]};ukfde0<={hd9bdf7>>1,mef0f02[7]};off7806<={wjf7df9>>1,mef0f02[8]};gqbc034<=mef0f02[9];yke01a0<=mef0f02[10];ecd01<=mef0f02[11];aa3404e<={tw3fb87>>1,mef0f02[12]};bna0270<=mef0f02[13];do1387<=mef0f02[14];bn9c3a<=mef0f02[15];sh4e1d7<=mef0f02[16];yx70ebd<=mef0f02[17];mg875ed<=mef0f02[18];xy3af69<=mef0f02[19];ribda57<={coa94ff>>1,mef0f02[20]};ofed2bb<=mef0f02[21];fn4aeeb<={wl9fe79>>1,mef0f02[22]};gdbbaf2<={ldf9e69>>1,mef0f02[23]};bldd794<=mef0f02[24];zkebca7<=mef0f02[25];sh5e53b<=mef0f02[26];czf29dc<=mef0f02[27];end\r
-always@* begin ng1e1e0[2047]<=wy15c82;ng1e1e0[2046]<=epae410[0];ng1e1e0[2044]<=rx_fifo_full;ng1e1e0[2040]<=ep90421[0];ng1e1e0[2032]<=of4bc4f[0];ng1e1e0[2017]<=vif13e4[0];ng1e1e0[1987]<=hd9bdf7[0];ng1e1e0[1926]<=wjf7df9[0];ng1e1e0[1921]<=ldf9e69[0];ng1e1e0[1805]<=ipf7e64;ng1e1e0[1795]<=rgcf34f;ng1e1e0[1679]<=co87555;ng1e1e0[1562]<=ntbf324;ng1e1e0[1543]<=ps79a7b;ng1e1e0[1310]<=vk3aaa9;ng1e1e0[1144]<=fpaaa53;ng1e1e0[1076]<=jpf9927;ng1e1e0[1039]<=zxcd3db;ng1e1e0[1023]<=tu42b90;ng1e1e0[960]<=wl9fe79[0];ng1e1e0[839]<=al70eaa;ng1e1e0[572]<=psd554a;ng1e1e0[480]<=rt4a7f9;ng1e1e0[419]<=hoee1d5;ng1e1e0[240]<=coa94ff[0];ng1e1e0[209]<=alfdc3a;ng1e1e0[104]<=tw3fb87[0];ng1e1e0[30]<=xw69ede;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module cm4cad9 (\r
-\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- bn1ce70,\r
-\r
- \r
- lfaa812,\r
- jc4d12d,\r
- ykce1a5,\r
- gb44b50,\r
-\r
- \r
- ba25a85,\r
-\r
- \r
-\r
- ukf3ec,\r
- zz22aa1,\r
-\r
- \r
-\r
- jp50abc,\r
- ep855e6,\r
- hq2af34,\r
- dm579a3,\r
- ksbcd1b,\r
- lde68d9,\r
- ec346cf,\r
- eca3678,\r
- xy1b3c0,\r
- qtd9e02,\r
- lqcf014,\r
- su780a3,\r
- rgc0518,\r
- ir28c2\r
-\r
-);\r
-parameter gq97bed = 8;\r
-parameter mga30a3 = 14;\r
-parameter kf18518 = 16;\r
-parameter vvc28c5 = 16;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input lfaa812;\r
-input jc4d12d;\r
-input ykce1a5;\r
-input gb44b50;\r
-input zz22aa1;\r
-input ukf3ec;\r
-input [gq97bed-1:0] bn1ce70;\r
-input [kf18518-1:0] ba25a85;\r
-output jp50abc;\r
-output ep855e6;\r
-output hq2af34;\r
-output ec346cf;\r
-output eca3678;\r
-output xy1b3c0;\r
-output lqcf014;\r
-output rgc0518;\r
-output ksbcd1b;\r
-output ir28c2;\r
-output [vvc28c5-1:0] qtd9e02;\r
-output [kf18518-1:0] su780a3;\r
-output [mga30a3-1:0] dm579a3;\r
-output [mga30a3-1:0] lde68d9;\r
-reg jp50abc;\r
-reg ep855e6;\r
-reg hq2af34;\r
-reg ec346cf;\r
-reg eca3678;\r
-reg xy1b3c0;\r
-reg rgc0518;\r
-reg ir28c2;\r
-reg [mga30a3-1:0] lde68d9;\r
-reg [mga30a3-1:0] dm579a3;\r
-reg [kf18518-1:0] su780a3;\r
-reg [gq97bed-1:0] gq3eb5e;\r
-wire lqcf014;\r
-wire [vvc28c5-1:0] qtd9e02;\r
-reg ksbcd1b;\r
-localparam ykf02fc = 16'h8808;\r
-localparam lf817e0 = 16'h8100;\r
-localparam lsbf06 = 16'd46;\r
-localparam rt5f832 = 16'd42;\r
-localparam zxfc197 = 9;\r
-localparam uie0cbe = 9'b000000001;\r
-localparam xl65f0 = 9'b000000010;\r
-localparam jr32f87 = 9'b000000100;\r
-localparam sw97c3e = 9'b000001000;\r
-localparam cbbe1f1 = 9'b000010000;\r
-localparam wwf0f8d = 9'b000100000;\r
-localparam wy87c69 = 9'b001000000;\r
-localparam uk3e348 = 9'b010000000;\r
-localparam lqf1a41 = 9'b100000000;\r
-wire mg8d20b;\r
-wire xw69058;\r
-wire by482c3;\r
-wire of4161a;\r
-wire jeb0d4;\r
-wire dm586a3;\r
-wire qtc351b;\r
-wire co1a8dd;\r
-wire god46e9;\r
-reg [zxfc197-1:0] do1ba48;\r
-reg rtdd243;\r
-reg zxe921f;\r
-reg qg490ff;\r
-reg dm487f8;\r
-reg [zxfc197-1:0] qi1fe10;\r
-reg rgf144b;\r
-reg [gq97bed - 1 : 0] je896ad;\r
-reg zm9c559;\r
-reg fp81339;\r
-reg byd5aaf;\r
-reg os4ce77;\r
-reg [kf18518 - 1 : 0] qv39dc8;\r
-reg eacee45;\r
-reg kq77228;\r
-reg [gq97bed - 1 : 0] ldc8a08;\r
-reg vv45047;\r
-reg ph2823e;\r
-reg qt411f7;\r
-reg an8fbc;\r
-reg jc47de5;\r
-reg uk3ef2a;\r
-reg ipf7950;\r
-reg ksbca84;\r
-reg ice5421;\r
-reg [zxfc197 - 1 : 0] bl5084a;\r
-reg tj84256;\r
-reg wy212b6;\r
-reg rv95b1;\r
-reg nr4ad8e;\r
-reg [zxfc197 - 1 : 0] swb63b1;\r
-reg fp19883;\r
-reg [2047:0] ng1e1e0;\r
-wire [24:0] mef0f02;\r
-\r
-localparam uk87811 = 25,gd3c088 = 32'hfdffca8b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign mg8d20b = fp81339 && ({ldc8a08, je896ad} == ykf02fc);\r
-assign xw69058 = fp81339 && ({ldc8a08, je896ad} != ykf02fc);\r
-\r
-\r
-\r
-\r
-assign by482c3 = fp81339 && ({ldc8a08, je896ad} == lf817e0);\r
-\r
-\r
-\r
-\r
-\r
-assign of4161a = ((fp81339 & (vv45047 | (~vv45047 & ~qt411f7 && {ldc8a08, je896ad} < lsbf06))) | (wy212b6 && {ldc8a08, je896ad} < rt5f832));\r
-\r
-\r
-\r
-\r
-\r
-assign co1a8dd = (kq77228 | eacee45) & rv95b1 && ({ldc8a08, je896ad} == qv39dc8);\r
-assign qtc351b = rv95b1 && ({ldc8a08, je896ad} != qv39dc8);\r
-assign god46e9 = eacee45 & ph2823e;\r
-\r
-\r
-\r
-\r
-assign jeb0d4 = ((fp81339 & ~qt411f7) | (wy212b6) && {ldc8a08, je896ad} >= 16'h0600);\r
-\r
-\r
-\r
-assign dm586a3 = fp81339 & ~vv45047;\r
-\r
-assign lqcf014 = tj84256; \r
-assign qtd9e02 = {ldc8a08, je896ad}; \r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin jp50abc <= 1'b0; ep855e6 <= 1'b0; hq2af34 <= 1'b0; ec346cf <= 1'b0; eca3678 <= 1'b0; xy1b3c0 <= 1'b0; dm579a3 <= 14'b0; lde68d9 <= 14'b0; su780a3 <= 16'b0; rgf144b <= 1'b0; qi1fe10 <= uie0cbe; rgc0518 <= 1'b0; ir28c2 <= 1'b0; ksbcd1b <= 1'b0; gq3eb5e <= 0; end else if (rxmac_clk_en) begin\r
- gq3eb5e <= je896ad; rgf144b <= byd5aaf; ksbcd1b <= (fp81339 & ~qt411f7) | wy212b6; if (fp19883) qi1fe10 <= uie0cbe; else begin qi1fe10 <= bl5084a; if (os4ce77) lde68d9 <= lde68d9 - 14'd1; end if (fp81339 && vv45047) lde68d9 <= 14'd46; else if ((fp81339 && !hq2af34) || wy212b6) begin dm579a3 <= {ldc8a08[5:0], je896ad}; lde68d9 <= {ldc8a08[5:0], je896ad}; end if (nr4ad8e) su780a3 <= {ldc8a08, je896ad}; if (uk3ef2a) jp50abc <= uk3ef2a; else if (zm9c559) jp50abc <= 1'b0; else jp50abc <= jp50abc; if (vv45047) ep855e6 <= vv45047; else if (zm9c559) ep855e6 <= 1'b0; else ep855e6 <= ep855e6; if (jc47de5) xy1b3c0 <= jc47de5; else if (zm9c559) xy1b3c0 <= 1'b0; else xy1b3c0 <= xy1b3c0; if (an8fbc) eca3678 <= an8fbc; else if (zm9c559) eca3678 <= 1'b0; else eca3678 <= eca3678; if (ksbca84) ec346cf <= ksbca84; else if (zm9c559) ec346cf <= 1'b0; else ec346cf <= ec346cf; if (ipf7950) rgc0518 <= ipf7950; else if (zm9c559) rgc0518 <= 1'b0; else rgc0518 <= rgc0518; if (ice5421) ir28c2 <= ice5421; else if (zm9c559) ir28c2 <= 1'b0; else ir28c2 <= ir28c2; if (qt411f7) hq2af34 <= qt411f7; else if (zm9c559) hq2af34 <= 1'b0; else hq2af34 <= hq2af34; end\r
-end\r
-\r
-always @ (swb63b1 or fp81339 or qt411f7 or vv45047 or ipf7950) begin case (swb63b1) uie0cbe : begin if (fp81339 && qt411f7) begin do1ba48 = xl65f0; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end else if (fp81339 && vv45047) begin do1ba48 = wwf0f8d; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end else begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end end xl65f0 : begin do1ba48 = jr32f87; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end jr32f87 : begin do1ba48 = sw97c3e; rtdd243 = 1'b1; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end sw97c3e : begin do1ba48 = cbbe1f1; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end cbbe1f1 : begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b1; qg490ff = 1'b0; dm487f8 = 1'b0; end wwf0f8d : begin do1ba48 = wy87c69; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end wy87c69 : begin if (ipf7950) begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b1; dm487f8 = 1'b0; end else begin do1ba48 = uk3e348; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b1; dm487f8 = 1'b0; end end uk3e348 : begin do1ba48 = lqf1a41; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end lqf1a41 : begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b1; end default : begin do1ba48 = uie0cbe; rtdd243 = 1'b0; zxe921f = 1'b0; qg490ff = 1'b0; dm487f8 = 1'b0; end endcase\r
-end\r
-always@* begin je896ad<={bn1ce70>>1,mef0f02[0]};zm9c559<=mef0f02[1];fp81339<=mef0f02[2];byd5aaf<=mef0f02[3];os4ce77<=mef0f02[4];qv39dc8<={ba25a85>>1,mef0f02[5]};eacee45<=mef0f02[6];kq77228<=mef0f02[7];ldc8a08<={gq3eb5e>>1,mef0f02[8]};vv45047<=mef0f02[9];ph2823e<=mef0f02[10];qt411f7<=mef0f02[11];an8fbc<=mef0f02[12];jc47de5<=mef0f02[13];uk3ef2a<=mef0f02[14];ipf7950<=mef0f02[15];ksbca84<=mef0f02[16];ice5421<=mef0f02[17];bl5084a<={do1ba48>>1,mef0f02[18]};tj84256<=mef0f02[19];wy212b6<=mef0f02[20];rv95b1<=mef0f02[21];nr4ad8e<=mef0f02[22];swb63b1<={qi1fe10>>1,mef0f02[23]};fp19883<=mef0f02[24];end\r
-always@* begin ng1e1e0[2047]<=lfaa812;ng1e1e0[2046]<=jc4d12d;ng1e1e0[2044]<=ykce1a5;ng1e1e0[2040]<=gb44b50;ng1e1e0[2032]<=ba25a85[0];ng1e1e0[2017]<=ukf3ec;ng1e1e0[1987]<=zz22aa1;ng1e1e0[1926]<=gq3eb5e[0];ng1e1e0[1804]<=mg8d20b;ng1e1e0[1803]<=qi1fe10[0];ng1e1e0[1560]<=xw69058;ng1e1e0[1558]<=rgf144b;ng1e1e0[1550]<=co1a8dd;ng1e1e0[1072]<=by482c3;ng1e1e0[1052]<=god46e9;ng1e1e0[1023]<=bn1ce70[0];ng1e1e0[901]<=dm487f8;ng1e1e0[775]<=qtc351b;ng1e1e0[450]<=qg490ff;ng1e1e0[387]<=dm586a3;ng1e1e0[225]<=zxe921f;ng1e1e0[193]<=jeb0d4;ng1e1e0[112]<=rtdd243;ng1e1e0[96]<=of4161a;ng1e1e0[56]<=do1ba48[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module oub9ee6 (\r
- pscf731, \r
- bl7b98b, \r
- mrdcc5e,\r
- hbe62f4,\r
- uk317a6,\r
- fp8bd30,\r
- uv5e986,\r
- vif4c35,\r
- oua61ab,\r
- rxmac_clk_en,\r
- vk86ac3\r
- );\r
-output [5:0] pscf731;\r
-output bl7b98b;\r
-input [7:0] mrdcc5e;\r
-input [31:0] vif4c35;\r
-input hbe62f4;\r
-input uk317a6;\r
-input fp8bd30;\r
-input uv5e986;\r
-input oua61ab;\r
-input rxmac_clk_en;\r
-input vk86ac3;\r
-reg [31:0] zm3f362;\r
-reg [5:0] pscf731;\r
-reg bl7b98b;\r
-wire [31:0] ps6c4ff;\r
-wire [31:0] os627fb;\r
-reg [7 : 0] bn13fd8;\r
-reg wl9fec7;\r
-reg kqff63d;\r
-reg jcfb1e9;\r
-reg dzd8f4b;\r
-reg [31 : 0] nrc7a5e;\r
-reg [31 : 0] db3d2f6;\r
-reg [31 : 0] dze97b6;\r
-reg [31 : 0] yx4bdb7;\r
-reg [2047:0] ng1e1e0;\r
-wire [8:0] mef0f02;\r
-\r
-localparam uk87811 = 9,gd3c088 = 32'hfdffe06b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-assign os627fb[0] = ~db3d2f6[0];\r
-assign os627fb[1] = ~db3d2f6[1];\r
-assign os627fb[2] = db3d2f6[2];\r
-assign os627fb[3] = ~db3d2f6[3];\r
-assign os627fb[4] = ~db3d2f6[4];\r
-assign os627fb[5] = ~db3d2f6[5];\r
-assign os627fb[6] = ~db3d2f6[6];\r
-assign os627fb[7] = db3d2f6[7];\r
-assign os627fb[8] = ~db3d2f6[8];\r
-assign os627fb[9] = db3d2f6[9];\r
-assign os627fb[10] = ~db3d2f6[10];\r
-assign os627fb[11] = ~db3d2f6[11];\r
-assign os627fb[12] = ~db3d2f6[12];\r
-assign os627fb[13] = db3d2f6[13];\r
-assign os627fb[14] = ~db3d2f6[14];\r
-assign os627fb[15] = ~db3d2f6[15];\r
-assign os627fb[16] = db3d2f6[16];\r
-assign os627fb[17] = db3d2f6[17];\r
-assign os627fb[18] = ~db3d2f6[18];\r
-assign os627fb[19] = db3d2f6[19];\r
-assign os627fb[20] = db3d2f6[20];\r
-assign os627fb[21] = db3d2f6[21];\r
-assign os627fb[22] = db3d2f6[22];\r
-assign os627fb[23] = db3d2f6[23];\r
-assign os627fb[24] = ~db3d2f6[24];\r
-assign os627fb[25] = ~db3d2f6[25];\r
-assign os627fb[26] = ~db3d2f6[26];\r
-assign os627fb[27] = db3d2f6[27];\r
-assign os627fb[28] = db3d2f6[28];\r
-assign os627fb[29] = db3d2f6[29];\r
-assign os627fb[30] = ~db3d2f6[30];\r
-assign os627fb[31] = ~db3d2f6[31];\r
-\r
-always @ (posedge oua61ab or negedge vk86ac3)\r
-begin if (!vk86ac3) begin zm3f362 <= 32'hffffffff; pscf731 <= 6'b000000; bl7b98b <= 0; end else if (rxmac_clk_en) begin if (wl9fec7) begin zm3f362 <= dze97b6; end else if (dzd8f4b) begin zm3f362 <= nrc7a5e; end if (kqff63d) begin pscf731[5] <= dze97b6[30]; pscf731[4] <= dze97b6[29]; pscf731[3] <= dze97b6[28]; pscf731[2] <= dze97b6[27]; pscf731[1] <= dze97b6[26]; pscf731[0] <= dze97b6[25]; end if (jcfb1e9) begin if (yx4bdb7 == 0) begin bl7b98b <= 0; end else begin bl7b98b <= 1; end end else if (dzd8f4b) begin bl7b98b <= 0; end end\r
-end\r
-\r
-assign ps6c4ff[0] = db3d2f6[30] ^ bn13fd8[7] ^ bn13fd8[1] ^ db3d2f6[24];\r
-assign ps6c4ff[1] = db3d2f6[30] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25];\r
-assign ps6c4ff[2] = db3d2f6[30] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ db3d2f6[26] ^ bn13fd8[5];\r
-assign ps6c4ff[3] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ bn13fd8[6];\r
-assign ps6c4ff[4] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[7];\r
-assign ps6c4ff[5] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[2] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[6] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[7] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[24] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[8] = db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[0];\r
-assign ps6c4ff[9] = db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ db3d2f6[1];\r
-assign ps6c4ff[10] = db3d2f6[24] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[29] ^ bn13fd8[7] ^ db3d2f6[2];\r
-assign ps6c4ff[11] = db3d2f6[3] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ bn13fd8[7];\r
-assign ps6c4ff[12] = db3d2f6[30] ^ db3d2f6[4] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[13] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[5] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[14] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[6] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[28];\r
-assign ps6c4ff[15] = db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[2] ^ db3d2f6[7] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ db3d2f6[29];\r
-assign ps6c4ff[16] = db3d2f6[24] ^ bn13fd8[2] ^ bn13fd8[3] ^ db3d2f6[8] ^ db3d2f6[28] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[17] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[9] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[18] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[26] ^ bn13fd8[5] ^ db3d2f6[10];\r
-assign ps6c4ff[19] = db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[11];\r
-assign ps6c4ff[20] = db3d2f6[12] ^ bn13fd8[3] ^ db3d2f6[28];\r
-assign ps6c4ff[21] = db3d2f6[13] ^ bn13fd8[2] ^ db3d2f6[29];\r
-assign ps6c4ff[22] = db3d2f6[14] ^ db3d2f6[24] ^ bn13fd8[7];\r
-assign ps6c4ff[23] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[15] ^ db3d2f6[25] ^ bn13fd8[6] ^ bn13fd8[7];\r
-assign ps6c4ff[24] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ db3d2f6[16] ^ db3d2f6[26] ^ bn13fd8[5] ^ bn13fd8[6];\r
-assign ps6c4ff[25] = db3d2f6[26] ^ db3d2f6[17] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5];\r
-assign ps6c4ff[26] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[18] ^ db3d2f6[28] ^ bn13fd8[7];\r
-assign ps6c4ff[27] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ bn13fd8[2] ^ bn13fd8[3] ^ db3d2f6[28] ^ db3d2f6[19] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[28] = db3d2f6[30] ^ bn13fd8[1] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[5] ^ db3d2f6[29] ^ db3d2f6[20];\r
-assign ps6c4ff[29] = db3d2f6[30] ^ db3d2f6[21] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ bn13fd8[4] ^ db3d2f6[27];\r
-assign ps6c4ff[30] = db3d2f6[31] ^ db3d2f6[22] ^ bn13fd8[0] ^ bn13fd8[3] ^ db3d2f6[28];\r
-assign ps6c4ff[31] = db3d2f6[23] ^ bn13fd8[2] ^ db3d2f6[29];\r
-always@* begin bn13fd8<={mrdcc5e>>1,mef0f02[0]};wl9fec7<=mef0f02[1];kqff63d<=mef0f02[2];jcfb1e9<=mef0f02[3];dzd8f4b<=mef0f02[4];nrc7a5e<={vif4c35>>1,mef0f02[5]};db3d2f6<={zm3f362>>1,mef0f02[6]};dze97b6<={ps6c4ff>>1,mef0f02[7]};yx4bdb7<={os627fb>>1,mef0f02[8]};end\r
-always@* begin ng1e1e0[2047]<=hbe62f4;ng1e1e0[2046]<=uk317a6;ng1e1e0[2044]<=fp8bd30;ng1e1e0[2041]<=uv5e986;ng1e1e0[2034]<=vif4c35[0];ng1e1e0[2021]<=zm3f362[0];ng1e1e0[1995]<=ps6c4ff[0];ng1e1e0[1943]<=os627fb[0];ng1e1e0[1023]<=mrdcc5e[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module gd33aed (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- ks10d54, \r
- fa6c2d4, \r
- pf616a3, \r
- lsb51f, \r
- vv5a8fb,\r
-\r
- \r
- bn1ce70,\r
- cb25ef,\r
- wl12f7d,\r
- rva04bd,\r
-\r
- \r
- mg1550f,\r
- hdaa879,\r
- en543cf,\r
- uxa1e7d,\r
-\r
- \r
- jp50abc,\r
- ep855e6,\r
- hq2af34,\r
- dm579a3,\r
- ec346cf,\r
- eca3678,\r
- xy1b3c0,\r
- rgc0518,\r
- ksbcd1b,\r
- lde68d9,\r
- yz172cd,\r
-\r
- \r
- ignore_pkt,\r
-\r
- \r
- qgcb360,\r
- go59b01,\r
- ldcd808,\r
- tu6c047,\r
- wj6023b,\r
-\r
- \r
- bl7b98b,\r
-\r
- \r
- lfaa812,\r
- ykce1a5,\r
-\r
- \r
- gq3baab,\r
- bldd558,\r
- ykeaac7,\r
-\r
- \r
- ls35502,\r
- yzab1cf,\r
-\r
- \r
- fa58e7c,\r
-\r
- \r
- jc4d12d,\r
- gb44b50,\r
-\r
- \r
- epae410,\r
- tu42b90,\r
- wy15c82,\r
-\r
- \r
- kf17a95,\r
- ks24554,\r
- fp8bd30,\r
- jc52b50\r
-);\r
-parameter gq97bed = 8;\r
-parameter mga30a3 = 14;\r
-parameter ofd97a2 = 20;\r
-parameter ykcbd15 = 32;\r
-parameter do838e7 = 32;\r
-parameter bn1c73a = 9;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input ks10d54;\r
-input fa6c2d4;\r
-input pf616a3;\r
-input lsb51f;\r
-input vv5a8fb;\r
-input wl12f7d;\r
-input rva04bd;\r
-input cb25ef;\r
-input [gq97bed-1:0] bn1ce70;\r
-input mg1550f;\r
-input hdaa879;\r
-input en543cf;\r
-input uxa1e7d;\r
-input jp50abc;\r
-input ep855e6;\r
-input hq2af34;\r
-input ec346cf;\r
-input yz172cd;\r
-input eca3678;\r
-input xy1b3c0;\r
-input rgc0518;\r
-input ksbcd1b;\r
-input [mga30a3-1:0] lde68d9;\r
-input [mga30a3-1:0] dm579a3;\r
-input ignore_pkt;\r
-input qgcb360;\r
-input go59b01;\r
-input [mga30a3-1:0] ldcd808;\r
-input tu6c047;\r
-input wj6023b;\r
-input bl7b98b;\r
-output lfaa812;\r
-output ls35502;\r
-output yzab1cf;\r
-output jc4d12d;\r
-output tu42b90;\r
-output wy15c82;\r
-output ykce1a5;\r
-output gb44b50;\r
-output [ofd97a2-1:0] epae410;\r
-output gq3baab;\r
-output [bn1c73a-1:0] bldd558;\r
-output ykeaac7;\r
-output fa58e7c;\r
-output [do838e7-1:0] kf17a95;\r
-output ks24554;\r
-output fp8bd30;\r
-output jc52b50;\r
-wire lfaa812;\r
-wire jc4d12d;\r
-wire tu42b90;\r
-wire wy15c82;\r
-wire [ofd97a2-1:0] epae410;\r
-reg gq3baab;\r
-wire [do838e7-1:0] kf17a95;\r
-wire ks24554;\r
-wire jc52b50;\r
-reg fa58e7c;\r
-reg [bn1c73a-1:0] bldd558;\r
-reg ykeaac7;\r
-localparam dzc2fc9 = 8;\r
-localparam an17e4e = 8'b00000001;\r
-localparam phbf275 = 8'b00000010;\r
-localparam zxf93af = 8'b00000100;\r
-localparam wjc9d7e = 8'b00001000;\r
-localparam en4ebf5 = 8'b00010000;\r
-localparam mr75fac = 8'b00100000;\r
-localparam xlafd65 = 8'b01000000;\r
-localparam dz7eb2f = 8'b10000000;\r
-localparam ayf597e = 1'b0;\r
-localparam coacbf1 = 1'b1;\r
-reg [dzc2fc9-1:0] je2fc44;\r
-reg ls35502;\r
-reg tuf111f;\r
-reg uk888fa;\r
-reg of447d1;\r
-reg kf23e8c;\r
-reg ykce1a5;\r
-wire gofa328;\r
-wire gb44b50;\r
-wire zm8ca08;\r
-wire cz65043;\r
-wire nt2821d;\r
-wire al410ef;\r
-wire [mga30a3-1:0] ui43be4;\r
-wire gd1df20;\r
-wire icef904;\r
-reg [dzc2fc9-1:0] rge410b;\r
-reg ba2085b;\r
-reg zm42da;\r
-reg [2:0] sw216d2;\r
-reg jeb691;\r
-reg en5b48b;\r
-reg [mga30a3-1:0] ldd22e2;\r
-reg [mga30a3-1:0] bn8b8b7;\r
-reg me5c5be;\r
-reg kde2df1;\r
-reg zz16f8d;\r
-reg fcb7c6f;\r
-reg [mga30a3-1:0] psf1bd5;\r
-reg sw8deab;\r
-reg yx6f559;\r
-reg gb7aacc;\r
-reg zkd5664;\r
-reg gdab323;\r
-reg [mga30a3-1:0] mrcc8e0;\r
-reg [mga30a3-1:0] ux2382f;\r
-wire bn1c17d;\r
-wire yke0bef;\r
-wire aa5f78;\r
-wire fc2fbc1;\r
-wire me7de0b;\r
-wire ykef059;\r
-wire ea782c8;\r
-reg [ofd97a2-1:0] ngb200;\r
-reg ic59003;\r
-wire fnc8019;\r
-wire vv400ce;\r
-wire [ykcbd15-1:0] vx33b0;\r
-wire yzab1cf;\r
-reg iccec3e;\r
-reg rg761f0;\r
-reg lfb0f83;\r
-reg xw69ede;\r
-reg sw3e0f8;\r
-reg uif07c1;\r
-reg [gq97bed-1:0] ym1f042;\r
-reg yxf8210 ;\r
-reg mec1084;\r
-reg ux8420;\r
-reg jc42104;\r
-reg [4:0] ym10823;\r
-reg vx84118;\r
-reg lqfe289;\r
-wire ri4632;\r
-reg ir23192;\r
-wire fp8bd30;\r
-reg uvc64a4;\r
-wire lf32525;\r
-wire mg9292f;\r
-wire hd94979;\r
-wire oha4bce;\r
-wire zm25e74;\r
-reg je2f3a2;\r
-reg ps79d12;\r
-reg wwce893;\r
-reg bl74498;\r
-reg hqa24c6;\r
-reg wl12632;\r
-reg do93194;\r
-reg gq98ca2;\r
-wire [bn1c73a-1:0] jr32885;\r
-reg [3:0] vx9442e;\r
-reg zma2177;\r
-reg ie10bba;\r
-reg wl85dd0;\r
-reg zm1b29c;\r
-reg ic77429;\r
-reg rvba149;\r
-reg ned0a4f;\r
-reg kf8527a;\r
-reg [gq97bed - 1 : 0] je896ad;\r
-reg al4b56a;\r
-reg qt7a94f;\r
-reg ayd4a7c;\r
-reg lfa53e0;\r
-reg gd29f07;\r
-reg th4f83c;\r
-reg by7c1e6;\r
-reg kqe0f32;\r
-reg ux7990;\r
-reg gd3cc84;\r
-reg [mga30a3 - 1 : 0] hd3212e;\r
-reg ir90977;\r
-reg xl84bbc;\r
-reg hq25de7;\r
-reg uk2ef3a;\r
-reg cm779d1;\r
-reg [mga30a3 - 1 : 0] qte7441;\r
-reg pu3a20c;\r
-reg wwd1063;\r
-reg gq88319;\r
-reg cz418c8;\r
-reg [mga30a3 - 1 : 0] ho6322e;\r
-reg xl19172;\r
-reg vvc8b97;\r
-reg xj45cbf;\r
-reg [dzc2fc9 - 1 : 0] qg72ff8;\r
-reg wy97fc0;\r
-reg jrbfe01;\r
-reg wwff00e;\r
-reg czf8071;\r
-reg tuc038c;\r
-reg xy1c62;\r
-reg hqe313;\r
-reg pf7189b;\r
-reg tw8c4df;\r
-reg [mga30a3 - 1 : 0] tj137d0;\r
-reg hd9be86;\r
-reg vidf437;\r
-reg [dzc2fc9 - 1 : 0] rgd0dd1;\r
-reg pu86e8a;\r
-reg tj37452;\r
-reg [2 : 0] bnba297;\r
-reg osd14bf;\r
-reg wl8a5f9;\r
-reg [mga30a3 - 1 : 0] ks97e6b;\r
-reg [mga30a3 - 1 : 0] pff9acf;\r
-reg zxcd67f;\r
-reg zx6b3fe;\r
-reg me59ff6;\r
-reg facffb0;\r
-reg [mga30a3 - 1 : 0] hofec14;\r
-reg jpf60a2;\r
-reg zzb0517;\r
-reg qi828be;\r
-reg zm145f0;\r
-reg fca2f83;\r
-reg [mga30a3 - 1 : 0] qvbe0dd;\r
-reg [mga30a3 - 1 : 0] fc83768;\r
-reg tw1bb43;\r
-reg pfdda1b;\r
-reg ened0de;\r
-reg ea686f5;\r
-reg ea437a9;\r
-reg ls1bd49;\r
-reg aydea4b;\r
-reg [ofd97a2 - 1 : 0] wya92c8;\r
-reg su49641;\r
-reg uv4b208;\r
-reg me59045;\r
-reg [ykcbd15 - 1 : 0] qt4114e;\r
-reg an8a74;\r
-reg ld453a5;\r
-reg mt29d2e;\r
-reg czf29dc;\r
-reg pf74ba4;\r
-reg vxa5d27;\r
-reg [gq97bed - 1 : 0] rt749f1;\r
-reg kfa4f8f;\r
-reg vx27c7c;\r
-reg gq3e3e7;\r
-reg dmf1f39;\r
-reg [4 : 0] cb8f9cb;\r
-reg vi7ce5c;\r
-reg do83310;\r
-reg wl3971c;\r
-reg wwcb8e4;\r
-reg yk5c720;\r
-reg dze3901;\r
-reg vx1c80f;\r
-reg zke407e;\r
-reg ng203f3;\r
-reg vk1f9b;\r
-reg qifcdb;\r
-reg fn7e6d8;\r
-reg xjf36c7;\r
-reg hd9b63f;\r
-reg qgdb1fe;\r
-reg nrd8ff0;\r
-reg pfc7f86;\r
-reg ri3fc36;\r
-reg [bn1c73a - 1 : 0] ayf0d93;\r
-reg [3 : 0] do86c99;\r
-reg an364ca;\r
-reg dob2655;\r
-reg ba932ab;\r
-reg [2047:0] ng1e1e0;\r
-wire [110:0] mef0f02;\r
-\r
-localparam uk87811 = 111,gd3c088 = 32'hfdffca8b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
-\r
-\r
- \r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin vx9442e <= 4'h0; zma2177 <= ayf597e; ie10bba <= 1'b0; wl85dd0 <= 1'b0; end else if (rxmac_clk_en) begin\r
- wl85dd0 <= dob2655;\r
- case (an364ca) ayf597e : begin ie10bba <= 1'b0; if (al4b56a && vi7ce5c) begin vx9442e <= do86c99 + 1; zma2177 <= coacbf1; end else begin vx9442e <= 4'h0; zma2177 <= ayf597e; end end coacbf1 : begin if (vi7ce5c) begin if (do86c99 <= 4'd12 ) begin vx9442e <= do86c99 + 1; zma2177 <= coacbf1; end else begin zma2177 <= ayf597e; end end else begin if (~cb8f9cb[3] & cb8f9cb[4]) begin zma2177 <= ayf597e; end if (do86c99 <= 4'd12) begin ie10bba <= 1'b1; end else begin ie10bba <= 1'b0; end end end default : begin vx9442e <= 4'h0; ie10bba <= 1'b0; zma2177 <= ayf597e; end\r
- endcase end \r
-\r
-end \r
-\r
-\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin yx6f559 <= 1'b0; gb7aacc <= 1'b0; rge410b <= an17e4e; sw216d2 <= 3'b000; jeb691 <= 1'b0; vx84118 <= 1'b0; yxf8210 <= 1'b0; mec1084 <= 1'b0; kde2df1 <= 1'b0; zz16f8d <= 1'b0; fcb7c6f <= 1'b0; sw8deab <= 1'b0; do93194 <= 1'b0; gq98ca2 <= 1'b0; en5b48b <= 1'b0; end else if (rxmac_clk_en) begin do93194 <= xl19172; gq98ca2 <= pfc7f86; if (jpf60a2) fcb7c6f <= jpf60a2; else if (lfaa812) fcb7c6f <= 1'b0; else if (gd29f07) fcb7c6f <= 1'b0; else fcb7c6f <= facffb0; sw8deab <= lfa53e0; kde2df1 <= wwd1063; zz16f8d <= zx6b3fe; yx6f559 <= gd29f07; gb7aacc <= zzb0517; vx84118 <= zm1b29c; yxf8210 <= vi7ce5c; mec1084 <= kfa4f8f; jeb691 <= lfa53e0 | (osd14bf & ~tuc038c); en5b48b <= wy97fc0; if(xy1c62) sw216d2 <= bnba297 + 2'd1; else if (lfaa812) sw216d2 <= 3'b000; rge410b <= qg72ff8; end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign jc4d12d = wl8a5f9;\r
-\r
-assign zm8ca08 = osd14bf | lfa53e0;\r
-assign gofa328 = bnba297[2] & ~bnba297[1] & bnba297[0];\r
-\r
-always @ (rgd0dd1 or ri3fc36 or zm1b29c or vi7ce5c or al4b56a or qt7a94f or lfa53e0 or gd29f07 or tuc038c or kqe0f32 or ux7990 or me59ff6) begin case (rgd0dd1) an17e4e : begin if (!(ri3fc36 && zm1b29c)) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b1; end else begin if(!me59ff6) kf23e8c = 1'b0; else kf23e8c = 1'b1; je2fc44 = phbf275; ls35502 = 1'b1; tuf111f = 1'b0; of447d1 = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end phbf275 : begin if (qt7a94f) begin je2fc44 = wjc9d7e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b1; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (al4b56a) begin je2fc44 = zxf93af; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (!zm1b29c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else begin je2fc44 = phbf275; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end zxf93af : begin if (lfa53e0) begin je2fc44 = en4ebf5; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (gd29f07) begin je2fc44 = wjc9d7e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (!vi7ce5c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b1; uk888fa = 1'b0; end else begin je2fc44 = zxf93af; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end wjc9d7e : begin if (!zm1b29c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else begin je2fc44 = wjc9d7e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end en4ebf5 : begin if (tuc038c) begin je2fc44 = mr75fac; ls35502 = 1'b0; tuf111f = 1'b1; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (!vi7ce5c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b1; uk888fa = 1'b0; end else begin je2fc44 = en4ebf5; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end mr75fac : begin if(kqe0f32 || ux7990) begin je2fc44 = xlafd65; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else if (!zm1b29c) begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b1; uk888fa = 1'b0; end else begin je2fc44 = mr75fac; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end xlafd65 : begin if (!vi7ce5c) begin je2fc44 = dz7eb2f; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end else begin je2fc44 = xlafd65; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end end dz7eb2f : begin je2fc44 = an17e4e; ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end default : begin je2fc44 = an17e4e;\r
- ls35502 = 1'b0; tuf111f = 1'b0; of447d1 = 1'b0; kf23e8c = 1'b0; ykce1a5 = 1'b0; uk888fa = 1'b0; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign zk5d9f7 = zm1b29c;\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin iccec3e <= 0; rg761f0 <= 0; ba2085b <= 1'b0; zm42da <= 1'b0; ym1f042 <= 8'h00; lfb0f83 <= 1'b0; xw69ede <= 1'b0; sw3e0f8 <= 1'b0; uif07c1 <= 1'b0; jc42104 <= 1'b0; gq3baab <= 1'b0; ym10823[0] <= 1'b0; ym10823[1] <= 1'b0; ym10823[2] <= 1'b0; ym10823[3] <= 1'b0; ym10823[4] <= 1'b0; end else if (rxmac_clk_en) begin ym10823[0] <= kfa4f8f; ym10823[1] <= cb8f9cb[0]; ym10823[2] <= cb8f9cb[1]; ym10823[3] <= cb8f9cb[2]; ym10823[4] <= cb8f9cb[3]; if (uv4b208) jc42104 <= uv4b208; else if (lfaa812) jc42104 <= 1'b0; else jc42104 <= dmf1f39; sw3e0f8 <= ea437a9; uif07c1 <= pf74ba4; gq3baab <= jrbfe01 & ~pf74ba4; lfb0f83 <= lfaa812; xw69ede <= wy15c82; ym1f042 <= je896ad; iccec3e <= zk5d9f7; rg761f0 <= su49641; if (xl84bbc) ba2085b <= cm779d1 | (pu86e8a & su49641); else ba2085b <= cm779d1 | (pu86e8a & an8a74); zm42da <= al4b56a | (tj37452 & tw1bb43 & ~(gd29f07 & ~zzb0517)); end\r
-end\r
-\r
-\r
-\r
-assign gb44b50 = pu86e8a | cm779d1;\r
-assign yke0bef = (qte7441 == 14'd1);\r
-\r
-always @ (zk5d9f7 or gb44b50 or pfdda1b) begin casex ({gb44b50, pfdda1b}) 2'b0x : ic59003 = zk5d9f7; 2'b11 : ic59003 = 0; default : ic59003 = zk5d9f7; endcase\r
-end\r
-\r
-assign bn1c17d = (xl84bbc) ? ld453a5 : ic77429;\r
-assign aa5f78 = ~qifcdb & tj37452;\r
-assign me7de0b = tj37452;\r
-assign fc2fbc1 = (lfaa812 & ~wy15c82) | (mt29d2e & ~czf29dc);\r
-assign tu42b90 = ened0de | ea686f5;\r
-assign ea782c8 = lfaa812 | mt29d2e;\r
-always @ (lfaa812 or mt29d2e or qt4114e or qgdb1fe) begin case({lfaa812, mt29d2e}) 2'b10 : ngb200 = {2'b11,1'b0,1'b0,qt4114e[31:16]}; 2'b01 : ngb200 = {2'b10,1'b1,qgdb1fe,qt4114e[15:0]}; default : ngb200 = 20'bxxxxxxxxxxxxxxxxxxxx; endcase\r
-end\r
-assign epae410[19:0] = aydea4b ? wya92c8[19:0] : {12'h000, rt749f1};\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign fnc8019 = (~kfa4f8f & vx27c7c) & pf74ba4;\r
-assign vv400ce = uv4b208 | dmf1f39;\r
-assign lfaa812 = me59045 ? vxa5d27 & ~pf74ba4 : facffb0 & ~qt7a94f & ~zzb0517 & ~cb8f9cb[3] & cb8f9cb[4];\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign ykef059 = (pff9acf >= 14'd64);\r
-\r
-\r
-\r
-\r
-assign wy15c82 = ((~gq88319) ? (lfaa812 & ~gq3e3e7) : 1'b0) | (zzb0517 & ~qi828be) | (dob2655 & ~ba932ab) | (vvc8b97 & ux7990 & lfaa812) | (pu3a20c & lfaa812);\r
-\r
-assign cz65043 = al4b56a | (zxcd67f & an8a74);\r
-\r
-\r
-assign nt2821d = gb44b50;\r
-assign al410ef = gb44b50 & ea437a9;\r
-\r
-\r
-assign ui43be4 = (~xl84bbc) ? hofec14 -14'd4 : fc83768;\r
-\r
-assign kf17a95 = 32'hffffffff;\r
-\r
-assign jc52b50 = ls35502;\r
-assign fp8bd30 = ~vi7ce5c & kfa4f8f;\r
-\r
-assign ks24554 = al4b56a | yk5c720;\r
-\r
-\r
-\r
-assign ri4632 = cz418c8 & ir90977 & wwcb8e4 & gq3e3e7 & ~(hd9b63f | xj45cbf);\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin gdab323 <= 1'b0; zkd5664 <= 1'b0; mrcc8e0 <= 14'b0; ldd22e2 <= 14'b0; bn8b8b7 <= 14'b0; me5c5be <= 1'b0; ux8420 <= 1'b0; uvc64a4 <= 1'b0; ps79d12 <= 1'b0; wwce893 <= 1'b0; bl74498 <= 1'b0; hqa24c6 <= 1'b0; ir23192 <= 1'b0; fa58e7c <= 1'b0; je2f3a2 <= 1'b0; psf1bd5 <= 14'd0; ux2382f <= 14'd0; bldd558 <= 9'd0; ykeaac7 <= 1'b0; wl12632 <= 1'b0; lqfe289 <= 1'b0; end else if (rxmac_clk_en) begin ykeaac7 <= mt29d2e & ~czf29dc; if (mt29d2e && !czf29dc) bldd558 <= ayf0d93; ir23192 <= fp8bd30; fa58e7c <= wl3971c; if (czf8071) je2f3a2 <= czf8071; else if (ls35502 && !czf8071) je2f3a2 <= 1'b0; else if (zzb0517) je2f3a2 <= 1'b0; else je2f3a2 <= qifcdb; hqa24c6 <= ~vk1f9b; if (rvba149 & zm1b29c) bl74498 <= rvba149; else if (mt29d2e) bl74498 <= 1'b0; else bl74498 <= hd9b63f; if (zke407e) wwce893 <= zke407e; else if (mt29d2e) wwce893 <= 1'b0; else wwce893 <= xjf36c7; lqfe289 <= al4b56a; if (do83310) ps79d12 <= kf8527a; if (yzab1cf) wl12632 <= ayd4a7c; uvc64a4 <= al4b56a | (yk5c720 & zm1b29c); mrcc8e0 <= tj137d0; zkd5664 <= dze3901; gdab323 <= vidf437; if (zxcd67f && !hqe313) ux8420 <= ls1bd49; me5c5be <= hqe313; if (zxcd67f && !hqe313) ldd22e2 <= pff9acf; if (hqe313) begin bn8b8b7 <= pff9acf + 14'd1; end else bn8b8b7 <= 14'd0; if (tw8c4df && xl84bbc && su49641) ux2382f <= fc83768 + 14'd1; if (pf7189b && !xl84bbc && an8a74) psf1bd5 <= hofec14 + 14'd1; else if (jpf60a2) psf1bd5 <= 14'd0; end\r
-end\r
-\r
-\r
-\r
-assign yzab1cf = jpf60a2;\r
-\r
-\r
-assign lf32525 = gd3cc84 ? (ks97e6b > (ho6322e + 14'd4)) : ks97e6b > ho6322e;\r
-assign mg9292f = (ks97e6b < 14'd64);\r
-assign hd94979 = wwff00e;\r
-\r
-assign gd1df20 = (ks97e6b[6:0] != 7'd64);\r
-assign icef904 = (hd3212e != qvbe0dd);\r
-assign oha4bce = vx1c80f ? 1'b0 : ux7990 | xl84bbc ? hd9be86 : hq25de7 ? 1'b0 : fca2f83;\r
-\r
-assign zm25e74 = ~(hd9b63f | xj45cbf | ng203f3);\r
-assign vx33b0[31] = zm145f0; \r
-assign vx33b0[30] = vx1c80f; \r
-assign vx33b0[29] = fn7e6d8; \r
-assign vx33b0[28] = nrd8ff0;\r
-assign vx33b0[27] = xjf36c7; \r
-assign vx33b0[26] = qifcdb; \r
-assign vx33b0[25] = xj45cbf; \r
-assign vx33b0[24] = ng203f3; \r
-assign vx33b0[23] = vk1f9b; \r
-assign vx33b0[22] = th4f83c; \r
-assign vx33b0[21] = by7c1e6; \r
-assign vx33b0[20] = ned0a4f; \r
-assign vx33b0[19] = uk2ef3a; \r
-assign vx33b0[18] = ux7990; \r
-assign vx33b0[17] = ir90977; \r
-assign vx33b0[16] = gd3cc84; \r
-assign vx33b0[15:14] = 2'b00;\r
-assign vx33b0[13:0] = ks97e6b; \r
-\r
-assign jr32885[0] = ir90977;\r
-assign jr32885[1] = xj45cbf;\r
-assign jr32885[2] = hd9b63f;\r
-assign jr32885[3] = zm145f0;\r
-assign jr32885[4] = vx1c80f;\r
-assign jr32885[5] = fn7e6d8;\r
-assign jr32885[6] = th4f83c;\r
-assign jr32885[7] = by7c1e6;\r
-assign jr32885[8] = gd3cc84;\r
-\r
-always@* begin zm1b29c<=mef0f02[0];ic77429<=mef0f02[1];rvba149<=mef0f02[2];ned0a4f<=mef0f02[3];kf8527a<=mef0f02[4];je896ad<={bn1ce70>>1,mef0f02[5]};al4b56a<=mef0f02[6];qt7a94f<=mef0f02[7];ayd4a7c<=mef0f02[8];lfa53e0<=mef0f02[9];gd29f07<=mef0f02[10];th4f83c<=mef0f02[11];by7c1e6<=mef0f02[12];kqe0f32<=mef0f02[13];ux7990<=mef0f02[14];gd3cc84<=mef0f02[15];hd3212e<={dm579a3>>1,mef0f02[16]};ir90977<=mef0f02[17];xl84bbc<=mef0f02[18];hq25de7<=mef0f02[19];uk2ef3a<=mef0f02[20];cm779d1<=mef0f02[21];qte7441<={lde68d9>>1,mef0f02[22]};pu3a20c<=mef0f02[23];wwd1063<=mef0f02[24];gq88319<=mef0f02[25];cz418c8<=mef0f02[26];ho6322e<={ldcd808>>1,mef0f02[27]};xl19172<=mef0f02[28];vvc8b97<=mef0f02[29];xj45cbf<=mef0f02[30];qg72ff8<={je2fc44>>1,mef0f02[31]};wy97fc0<=mef0f02[32];jrbfe01<=mef0f02[33];wwff00e<=mef0f02[34];czf8071<=mef0f02[35];tuc038c<=mef0f02[36];xy1c62<=mef0f02[37];hqe313<=mef0f02[38];pf7189b<=mef0f02[39];tw8c4df<=mef0f02[40];tj137d0<={ui43be4>>1,mef0f02[41]};hd9be86<=mef0f02[42];vidf437<=mef0f02[43];rgd0dd1<={rge410b>>1,mef0f02[44]};pu86e8a<=mef0f02[45];tj37452<=mef0f02[46];bnba297<={sw216d2>>1,mef0f02[47]};osd14bf<=mef0f02[48];wl8a5f9<=mef0f02[49];ks97e6b<={ldd22e2>>1,mef0f02[50]};pff9acf<={bn8b8b7>>1,mef0f02[51]};zxcd67f<=mef0f02[52];zx6b3fe<=mef0f02[53];me59ff6<=mef0f02[54];facffb0<=mef0f02[55];hofec14<={psf1bd5>>1,mef0f02[56]};jpf60a2<=mef0f02[57];zzb0517<=mef0f02[58];qi828be<=mef0f02[59];zm145f0<=mef0f02[60];fca2f83<=mef0f02[61];qvbe0dd<={mrcc8e0>>1,mef0f02[62]};fc83768<={ux2382f>>1,mef0f02[63]};tw1bb43<=mef0f02[64];pfdda1b<=mef0f02[65];ened0de<=mef0f02[66];ea686f5<=mef0f02[67];ea437a9<=mef0f02[68];ls1bd49<=mef0f02[69];aydea4b<=mef0f02[70];wya92c8<={ngb200>>1,mef0f02[71]};su49641<=mef0f02[72];uv4b208<=mef0f02[73];me59045<=mef0f02[74];qt4114e<={vx33b0>>1,mef0f02[75]};an8a74<=mef0f02[76];ld453a5<=mef0f02[77];mt29d2e<=mef0f02[78];czf29dc<=mef0f02[79];pf74ba4<=mef0f02[80];vxa5d27<=mef0f02[81];rt749f1<={ym1f042>>1,mef0f02[82]};kfa4f8f<=mef0f02[83];vx27c7c<=mef0f02[84];gq3e3e7<=mef0f02[85];dmf1f39<=mef0f02[86];cb8f9cb<={ym10823>>1,mef0f02[87]};vi7ce5c<=mef0f02[88];do83310<=mef0f02[89];wl3971c<=mef0f02[90];wwcb8e4<=mef0f02[91];yk5c720<=mef0f02[92];dze3901<=mef0f02[93];vx1c80f<=mef0f02[94];zke407e<=mef0f02[95];ng203f3<=mef0f02[96];vk1f9b<=mef0f02[97];qifcdb<=mef0f02[98];fn7e6d8<=mef0f02[99];xjf36c7<=mef0f02[100];hd9b63f<=mef0f02[101];qgdb1fe<=mef0f02[102];nrd8ff0<=mef0f02[103];pfc7f86<=mef0f02[104];ri3fc36<=mef0f02[105];ayf0d93<={jr32885>>1,mef0f02[106]};do86c99<={vx9442e>>1,mef0f02[107]};an364ca<=mef0f02[108];dob2655<=mef0f02[109];ba932ab<=mef0f02[110];end\r
-always@* begin ng1e1e0[2047]<=fa6c2d4;ng1e1e0[2046]<=pf616a3;ng1e1e0[2044]<=lsb51f;ng1e1e0[2040]<=vv5a8fb;ng1e1e0[2032]<=bn1ce70[0];ng1e1e0[2028]<=uvc64a4;ng1e1e0[2017]<=cb25ef;ng1e1e0[2008]<=lf32525;ng1e1e0[1988]<=vx33b0[0];ng1e1e0[1987]<=wl12f7d;ng1e1e0[1969]<=mg9292f;ng1e1e0[1928]<=iccec3e;ng1e1e0[1926]<=rva04bd;ng1e1e0[1891]<=hd94979;ng1e1e0[1809]<=rg761f0;ng1e1e0[1805]<=kf23e8c;ng1e1e0[1804]<=mg1550f;ng1e1e0[1803]<=yz172cd;ng1e1e0[1761]<=tuf111f;ng1e1e0[1748]<=gdab323;ng1e1e0[1734]<=oha4bce;ng1e1e0[1727]<=ym10823[0];ng1e1e0[1696]<=bn1c17d;ng1e1e0[1668]<=gd1df20;ng1e1e0[1633]<=do93194;ng1e1e0[1587]<=ps79d12;ng1e1e0[1571]<=lfb0f83;ng1e1e0[1562]<=gofa328;ng1e1e0[1560]<=hdaa879;ng1e1e0[1558]<=ignore_pkt;ng1e1e0[1555]<=zma2177;ng1e1e0[1550]<=dm579a3[0];ng1e1e0[1531]<=ri4632;ng1e1e0[1475]<=uk888fa;ng1e1e0[1464]<=bl7b98b;ng1e1e0[1448]<=mrcc8e0[0];ng1e1e0[1420]<=zm25e74;ng1e1e0[1406]<=vx84118;ng1e1e0[1345]<=yke0bef;ng1e1e0[1288]<=icef904;ng1e1e0[1287]<=fc2fbc1;ng1e1e0[1242]<=yx6f559;ng1e1e0[1218]<=gq98ca2;ng1e1e0[1131]<=yxf8210;ng1e1e0[1126]<=wwce893;ng1e1e0[1094]<=xw69ede;ng1e1e0[1076]<=zm8ca08;ng1e1e0[1072]<=en543cf;ng1e1e0[1069]<=qgcb360;ng1e1e0[1063]<=ie10bba;ng1e1e0[1056]<=ba2085b;ng1e1e0[1055]<=ykef059;ng1e1e0[1052]<=ec346cf;ng1e1e0[1028]<=ldd22e2[0];ng1e1e0[1023]<=ks10d54;ng1e1e0[1014]<=ir23192;ng1e1e0[994]<=vv400ce;ng1e1e0[902]<=of447d1;ng1e1e0[901]<=lde68d9[0];ng1e1e0[880]<=je2fc44[0];ng1e1e0[874]<=zkd5664;ng1e1e0[863]<=jc42104;ng1e1e0[848]<=ux2382f[0];ng1e1e0[834]<=ui43be4[0];ng1e1e0[816]<=wl12632;ng1e1e0[793]<=je2f3a2;ng1e1e0[777]<=vx9442e[0];ng1e1e0[775]<=hq2af34;ng1e1e0[765]<=lqfe289;ng1e1e0[732]<=wj6023b;ng1e1e0[643]<=aa5f78;ng1e1e0[621]<=sw8deab;ng1e1e0[565]<=ym1f042[0];ng1e1e0[528]<=rge410b[0];ng1e1e0[527]<=me7de0b;ng1e1e0[514]<=en5b48b;ng1e1e0[497]<=fnc8019;ng1e1e0[450]<=ksbcd1b;ng1e1e0[437]<=gb7aacc;ng1e1e0[431]<=ux8420;ng1e1e0[417]<=al410ef;ng1e1e0[408]<=hqa24c6;ng1e1e0[388]<=jr32885[0];ng1e1e0[387]<=ep855e6;ng1e1e0[366]<=tu6c047;ng1e1e0[310]<=psf1bd5[0];ng1e1e0[282]<=uif07c1;ng1e1e0[257]<=jeb691;ng1e1e0[248]<=ic59003;ng1e1e0[225]<=rgc0518;ng1e1e0[215]<=mec1084;ng1e1e0[208]<=nt2821d;ng1e1e0[204]<=bl74498;ng1e1e0[193]<=jp50abc;ng1e1e0[183]<=ldcd808[0];ng1e1e0[155]<=fcb7c6f;ng1e1e0[141]<=sw3e0f8;ng1e1e0[128]<=sw216d2[0];ng1e1e0[124]<=ngb200[0];ng1e1e0[112]<=xy1b3c0;ng1e1e0[104]<=cz65043;ng1e1e0[96]<=uxa1e7d;ng1e1e0[91]<=go59b01;ng1e1e0[78]<=wl85dd0;ng1e1e0[77]<=zz16f8d;ng1e1e0[64]<=zm42da;ng1e1e0[62]<=ea782c8;ng1e1e0[56]<=eca3678;ng1e1e0[38]<=kde2df1;ng1e1e0[19]<=me5c5be;ng1e1e0[9]<=bn8b8b7[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module qv835c (\r
- \r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- ks10d54, \r
- fa6c2d4, \r
- ls86aa0, \r
- pf616a3,\r
- lsb51f,\r
- vv5a8fb,\r
-\r
- \r
- uv70d29, \r
- hq8694d, \r
- ec34a6a, \r
- lfa5351, \r
- gd29a8f, \r
- rg4d47c, \r
- mr6a3e2, \r
- of51f14, \r
- sj8f8a4, \r
- tu7c524, \r
- ale2922, \r
- vk14915, \r
- ba25a85, \r
- qgcb360, \r
- go59b01, \r
- ldcd808, \r
- \r
- tu6c047, \r
- wj6023b, \r
-\r
- \r
- rx_fifo_full, \r
- ignore_pkt, \r
-\r
- \r
- gq3baab, \r
- ene2fd7, \r
- cb17ebd, \r
- bldd558, \r
- ykeaac7, \r
-\r
- \r
- su780a3, \r
- fa58e7c, \r
-\r
- \r
- rx_fifo_error, \r
- rx_stat_vector, \r
- rx_dbout, \r
- rx_write, \r
- rx_stat_en, \r
- rx_eof, \r
- rx_error \r
-);\r
-parameter gq97bed = 8;\r
-parameter mga30a3 = 14;\r
-parameter kf18518 = 16;\r
-parameter vvc28c5 = 16;\r
-parameter ofd97a2 = 20;\r
-parameter ykcbd15 = 32;\r
-parameter do838e7 = 32;\r
-parameter qt5e8a8 = 8;\r
-parameter psf4545 = 4;\r
-parameter kd44a33 = 8;\r
-parameter hocfb0b = 48;\r
-parameter bn28ceb = 2;\r
-parameter ic7d85a = 6;\r
-parameter vvec2d1 = 8;\r
-parameter bn1c73a = 9;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input ks10d54;\r
-input fa6c2d4;\r
-input pf616a3;\r
-input lsb51f;\r
-input vv5a8fb;\r
-input [gq97bed-1:0] ls86aa0;\r
-input [kd44a33-1:0] uv70d29;\r
-input [kd44a33-1:0] hq8694d;\r
-input [kd44a33-1:0] ec34a6a;\r
-input [kd44a33-1:0] lfa5351;\r
-input [kd44a33-1:0] gd29a8f;\r
-input [kd44a33-1:0] rg4d47c;\r
-input [kd44a33-1:0] mr6a3e2;\r
-input [kd44a33-1:0] of51f14;\r
-input [hocfb0b-1:0] sj8f8a4;\r
-input [kf18518-1:0] ba25a85;\r
-input [mga30a3-1:0] ldcd808;\r
-input tu7c524;\r
-input ale2922;\r
-input vk14915;\r
-input qgcb360;\r
-input go59b01;\r
-input tu6c047;\r
-input wj6023b;\r
-input ignore_pkt;\r
-input rx_fifo_full;\r
-output gq3baab;\r
-output [bn1c73a-1:0] bldd558;\r
-output ykeaac7;\r
-output cb17ebd;\r
-output [vvc28c5-1:0] ene2fd7;\r
-output [kf18518-1:0] su780a3;\r
-output fa58e7c;\r
-output rx_fifo_error;\r
-output [ykcbd15-1:0] rx_stat_vector;\r
-output [gq97bed-1:0] rx_dbout;\r
-output rx_write;\r
-output rx_stat_en;\r
-output rx_eof;\r
-output rx_error;\r
-parameter pdevice_family = "XP2";\r
-wire [gq97bed-1:0] xw791a7;\r
-wire [gq97bed-1:0] me469d7;\r
-wire sw34eb8;\r
-wire ria75c1;\r
-wire xy3ae0a;\r
-wire hbd7052;\r
-wire ngb8296;\r
-wire [mga30a3-1:0] qia590;\r
-wire ho52c81;\r
-wire ri9640b;\r
-wire pub205a;\r
-wire ux902d3;\r
-wire tj8169d;\r
-wire [kf18518-1:0] nr5a773;\r
-wire [vvc28c5-1:0] uk9dcf5;\r
-wire [mga30a3-1:0] by73d42;\r
-wire jr9ea12;\r
-wire kqf5097;\r
-wire baa84b8;\r
-wire ho425c3;\r
-wire kf12e1b;\r
-wire ou970dd;\r
-wire rib86e8;\r
-wire kdc3742;\r
-wire hq1ba15;\r
-wire xjdd0ab;\r
-wire uve855f;\r
-wire dm42afd;\r
-wire ym157ea;\r
-wire yzabf51;\r
-wire [do838e7-1:0] czfd46f;\r
-wire suea37c;\r
-wire kd51be0;\r
-wire [ofd97a2-1:0] mr6f821;\r
-wire rg7c10d;\r
-wire ice086a;\r
-wire gq3baab;\r
-wire ykeaac7;\r
-wire [bn1c73a-1:0] bldd558;\r
-wire [bn28ceb-1:0] sw82127;\r
-wire [ic7d85a-1:0] zz849c8;\r
-wire [qt5e8a8-1:0] nt27238;\r
-wire [qt5e8a8-1:0] thc8e34;\r
-wire fa471a7;\r
-wire vx38d3b;\r
-wire [ofd97a2-1:0] ec34efc;\r
-reg jea77e1;\r
-reg zm1b29c;\r
-reg ic77429;\r
-reg [gq97bed - 1 : 0] neca715;\r
-reg rvba149;\r
-reg ned0a4f;\r
-reg kf8527a;\r
-reg [kd44a33 - 1 : 0] gb6abd3;\r
-reg [kd44a33 - 1 : 0] ntaf4ee;\r
-reg [kd44a33 - 1 : 0] czd3bb5;\r
-reg [kd44a33 - 1 : 0] dmeed68;\r
-reg [kd44a33 - 1 : 0] dbb5a1a;\r
-reg [kd44a33 - 1 : 0] go686bb;\r
-reg [kd44a33 - 1 : 0] ie1aec9;\r
-reg [kd44a33 - 1 : 0] yzbb24e;\r
-reg [hocfb0b - 1 : 0] gbc93ad;\r
-reg ay49d6c;\r
-reg kd4eb61;\r
-reg ip75b0c;\r
-reg [kf18518 - 1 : 0] qv39dc8;\r
-reg gq88319;\r
-reg cz418c8;\r
-reg [mga30a3 - 1 : 0] ho6322e;\r
-reg xl19172;\r
-reg vvc8b97;\r
-reg wwde5f9;\r
-reg wwd1063;\r
-reg [gq97bed - 1 : 0] ym3e93a;\r
-reg [gq97bed - 1 : 0] epa4e83;\r
-reg zz2741c;\r
-reg je3a0e6;\r
-reg byd0733;\r
-reg vk8399b;\r
-reg ph1ccda;\r
-reg [mga30a3 - 1 : 0] gd336b6;\r
-reg bn9b5b5;\r
-reg vidadae;\r
-reg end6d73;\r
-reg swb6b9d;\r
-reg phb5ce8;\r
-reg [kf18518 - 1 : 0] zk73a3c;\r
-reg [vvc28c5 - 1 : 0] qte8f11;\r
-reg [mga30a3 - 1 : 0] yz3c462;\r
-reg ofe2314;\r
-reg zm118a4;\r
-reg ba8c522;\r
-reg me62912;\r
-reg ng14891;\r
-reg kfa448a;\r
-reg zz22455;\r
-reg kf122ae;\r
-reg nt91574;\r
-reg oh8aba7;\r
-reg pf55d3c;\r
-reg anae9e6;\r
-reg bl74f35;\r
-reg lsa79af;\r
-reg [do838e7 - 1 : 0] fne6bdd;\r
-reg je35eef;\r
-reg zzaf77b;\r
-reg [ofd97a2 - 1 : 0] vvddef6;\r
-reg ykef7b6;\r
-reg hb7bdb0;\r
-reg [bn28ceb - 1 : 0] pff6c31;\r
-reg [ic7d85a - 1 : 0] ntb0c71;\r
-reg [qt5e8a8 - 1 : 0] co31c7b;\r
-reg [qt5e8a8 - 1 : 0] xj71ecf;\r
-reg gd8f67f;\r
-reg hb7b3fd;\r
-reg [ofd97a2 - 1 : 0] facff7c;\r
-reg [2047:0] ng1e1e0;\r
-wire [69:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 70,gd3c088 = 32'hfdffd42b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign me469d7 = ym3e93a;\r
-\r
-\r
-assign cb17ebd = phb5ce8;\r
-assign ene2fd7 = qte8f11;\r
-assign su780a3 = zk73a3c;\r
-\r
-\r
-\r
-\r
-assign sw82127 = vvddef6[19:18];\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-hd2df10 #( .gq97bed(gq97bed) ) sh5e340 ( .rxmac_clk(rxmac_clk), .rxmac_clk_en(rxmac_clk_en), .reset_n(jea77e1), .ks10d54(zm1b29c), .ls86aa0(neca715), .ls35502(nt91574), .lfaa812(pf55d3c), .kd54097(xw791a7), .rva04bd(sw34eb8), .cb25ef(ria75c1), .wl12f7d(xy3ae0a) );\r
-\r
-cm4cad9 #( .gq97bed(gq97bed), .mga30a3(mga30a3), .kf18518(kf18518), .vvc28c5(vvc28c5) ) sj3cedd ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(rxmac_clk_en), .bn1ce70(ym3e93a), .jc4d12d(anae9e6), .lfaa812(oh8aba7), .ykce1a5(bl74f35), .gb44b50(lsa79af), .ba25a85(qv39dc8), .ukf3ec(ba8c522), .zz22aa1(kf122ae), .jp50abc(hbd7052), .ep855e6(ec883a1), .hq2af34(ngb8296), .dm579a3(qia590), .ksbcd1b(jr9ea12), .lde68d9(by73d42), .ec346cf(ho52c81), .eca3678(pub205a), .xy1b3c0(ux902d3), .qtd9e02(uk9dcf5), .lqcf014(tj8169d), .su780a3(nr5a773), .rgc0518(kqf5097), .ir28c2(ri9640b) );\r
-\r
-xl8b21c #( .gq97bed(gq97bed), .hocfb0b(hocfb0b), .ic7d85a(ic7d85a), .vvec2d1(vvec2d1) ) kf361ee ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(rxmac_clk_en), .bn1ce70(ym3e93a), .cb25ef(je3a0e6), .lfaa812(oh8aba7), .ykce1a5(bl74f35), .uv70d29(gb6abd3), .hq8694d(ntaf4ee), .ec34a6a(czd3bb5), .lfa5351(dmeed68), .gd29a8f(dbb5a1a), .rg4d47c(go686bb), .mr6a3e2(ie1aec9), .of51f14(yzbb24e), .sj8f8a4(gbc93ad), .tu7c524(ay49d6c), .ale2922(kd4eb61), .vk14915(ip75b0c), .wla48aa(ntb0c71), .ks24554(mr65e50), .mg1550f(ho425c3), .hdaa879(kf12e1b), .en543cf(ou970dd), .uxa1e7d(rib86e8), .ukf3ec(baa84b8), .zz22aa1(kdc3742) );\r
-\r
-\r
-gd33aed #( .gq97bed(gq97bed), .mga30a3(mga30a3), .ofd97a2(ofd97a2), .ykcbd15(ykcbd15), .do838e7(do838e7), .bn1c73a(bn1c73a) ) xya83f4 ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(rxmac_clk_en), .ks10d54(zm1b29c), .fa6c2d4(ic77429), .pf616a3(rvba149), .lsb51f(ned0a4f), .vv5a8fb(kf8527a), .bn1ce70(ym3e93a), .cb25ef(je3a0e6), .wl12f7d(byd0733), .rva04bd(zz2741c), .mg1550f(me62912), .hdaa879(ng14891), .en543cf(kfa448a), .uxa1e7d(zz22455), .jp50abc(vk8399b), .ep855e6(ec883a1), .hq2af34(ph1ccda), .dm579a3(gd336b6), .ec346cf(bn9b5b5), .yz172cd(vidadae), .eca3678(end6d73), .xy1b3c0(swb6b9d), .rgc0518(zm118a4), .ksbcd1b(ofe2314), .lde68d9(yz3c462), .ignore_pkt(wwd1063), .qgcb360(gq88319), .go59b01(cz418c8), .ldcd808(ho6322e), .tu6c047(xl19172), .wj6023b(vvc8b97), .bl7b98b(db815d6), .lfaa812(xjdd0ab), .ykce1a5(ym157ea),\r
- .gq3baab(gq3baab), .bldd558(bldd558), .ykeaac7(ykeaac7), .fa58e7c(fa58e7c), .ls35502(hq1ba15), .yzab1cf(uve855f), .jc4d12d(dm42afd), .gb44b50(yzabf51), .epae410(mr6f821), .tu42b90(rg7c10d), .wy15c82(ice086a), .kf17a95(czfd46f), .ks24554(suea37c), .fp8bd30(qi5f6f), .jc52b50(kd51be0) );\r
-\r
-oub9ee6 mr6f2cc ( .pscf731(zz849c8), .bl7b98b(db815d6), .mrdcc5e(ym3e93a), .hbe62f4(je35eef), .uk317a6(mr65e50), .fp8bd30(qi5f6f), .uv5e986(zzaf77b), .vif4c35(fne6bdd), .oua61ab(rxmac_clk), .vk86ac3(jea77e1), .rxmac_clk_en(rxmac_clk_en) );\r
-\r
-uvd3c42 #( .gq97bed(gq97bed), .ofd97a2(ofd97a2), .ykcbd15(ykcbd15), .qt5e8a8(qt5e8a8), .psf4545(psf4545) ) uk3bde8 ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(rxmac_clk_en), .tu42b90(ykef7b6), .wy15c82(hb7bdb0), .epae410(pff6c31), .rx_fifo_full(wwde5f9), .ep90421(facff7c), .sw8210d(nt27238), .sw10869(thc8e34), .zz84348(fa471a7), .sw21a46(vx38d3b), .rx_fifo_error(rx_fifo_error), .rx_stat_vector(rx_stat_vector), .rx_dbout(rx_dbout), .rx_write(rx_write), .rx_stat_en(rx_stat_en), .rx_eof(rx_eof), .rx_error(rx_error) );\r
-\r
-pmi_ram_dp #(.pmi_wr_addr_depth(256), .pmi_wr_addr_width(8), .pmi_wr_data_width(20), .pmi_rd_addr_depth(256), .pmi_rd_addr_width(8), .pmi_rd_data_width(20), .pmi_regmode("noreg"), .pmi_gsr("disable"), .pmi_resetmode("sync"), .pmi_init_file("none"), .pmi_init_file_format("binary"), .pmi_family(pdevice_family), .module_type("pmi_ram_dp") )\r
-thc75fb (.Data(mr6f821), .WrAddress(nt27238), .RdAddress(thc8e34), .WrClock(rxmac_clk), .RdClock(rxmac_clk), .WrClockEn(1'b1), .RdClockEn(fa471a7 & rxmac_clk_en), .WE(vx38d3b), .Reset(1'b0), .Q(ec34efc) );\r
-always@* begin jea77e1<=mef0f02[0];zm1b29c<=mef0f02[1];ic77429<=mef0f02[2];neca715<={ls86aa0>>1,mef0f02[3]};rvba149<=mef0f02[4];ned0a4f<=mef0f02[5];kf8527a<=mef0f02[6];gb6abd3<={uv70d29>>1,mef0f02[7]};ntaf4ee<={hq8694d>>1,mef0f02[8]};czd3bb5<={ec34a6a>>1,mef0f02[9]};dmeed68<={lfa5351>>1,mef0f02[10]};dbb5a1a<={gd29a8f>>1,mef0f02[11]};go686bb<={rg4d47c>>1,mef0f02[12]};ie1aec9<={mr6a3e2>>1,mef0f02[13]};yzbb24e<={of51f14>>1,mef0f02[14]};gbc93ad<={sj8f8a4>>1,mef0f02[15]};ay49d6c<=mef0f02[16];kd4eb61<=mef0f02[17];ip75b0c<=mef0f02[18];qv39dc8<={ba25a85>>1,mef0f02[19]};gq88319<=mef0f02[20];cz418c8<=mef0f02[21];ho6322e<={ldcd808>>1,mef0f02[22]};xl19172<=mef0f02[23];vvc8b97<=mef0f02[24];wwde5f9<=mef0f02[25];wwd1063<=mef0f02[26];ym3e93a<={xw791a7>>1,mef0f02[27]};epa4e83<={me469d7>>1,mef0f02[28]};zz2741c<=mef0f02[29];je3a0e6<=mef0f02[30];byd0733<=mef0f02[31];vk8399b<=mef0f02[32];ph1ccda<=mef0f02[33];gd336b6<={qia590>>1,mef0f02[34]};bn9b5b5<=mef0f02[35];vidadae<=mef0f02[36];end6d73<=mef0f02[37];swb6b9d<=mef0f02[38];phb5ce8<=mef0f02[39];zk73a3c<={nr5a773>>1,mef0f02[40]};qte8f11<={uk9dcf5>>1,mef0f02[41]};yz3c462<={by73d42>>1,mef0f02[42]};ofe2314<=mef0f02[43];zm118a4<=mef0f02[44];ba8c522<=mef0f02[45];me62912<=mef0f02[46];ng14891<=mef0f02[47];kfa448a<=mef0f02[48];zz22455<=mef0f02[49];kf122ae<=mef0f02[50];nt91574<=mef0f02[51];oh8aba7<=mef0f02[52];pf55d3c<=mef0f02[53];anae9e6<=mef0f02[54];bl74f35<=mef0f02[55];lsa79af<=mef0f02[56];fne6bdd<={czfd46f>>1,mef0f02[57]};je35eef<=mef0f02[58];zzaf77b<=mef0f02[59];vvddef6<={mr6f821>>1,mef0f02[60]};ykef7b6<=mef0f02[61];hb7bdb0<=mef0f02[62];pff6c31<={sw82127>>1,mef0f02[63]};ntb0c71<={zz849c8>>1,mef0f02[64]};co31c7b<={nt27238>>1,mef0f02[65]};xj71ecf<={thc8e34>>1,mef0f02[66]};gd8f67f<=mef0f02[67];hb7b3fd<=mef0f02[68];facff7c<={ec34efc>>1,mef0f02[69]};end\r
-always@* begin ng1e1e0[2047]<=ks10d54;ng1e1e0[2046]<=fa6c2d4;ng1e1e0[2044]<=ls86aa0[0];ng1e1e0[2041]<=pf616a3;ng1e1e0[2035]<=lsb51f;ng1e1e0[2029]<=czfd46f[0];ng1e1e0[2022]<=vv5a8fb;ng1e1e0[2011]<=suea37c;ng1e1e0[1996]<=uv70d29[0];ng1e1e0[1974]<=kd51be0;ng1e1e0[1945]<=hq8694d[0];ng1e1e0[1943]<=rib86e8;ng1e1e0[1922]<=rx_fifo_full;ng1e1e0[1901]<=mr6f821[0];ng1e1e0[1842]<=ec34a6a[0];ng1e1e0[1839]<=kdc3742;ng1e1e0[1797]<=ignore_pkt;ng1e1e0[1791]<=fa471a7;ng1e1e0[1778]<=ho425c3;ng1e1e0[1776]<=ldcd808[0];ng1e1e0[1759]<=zz849c8[0];ng1e1e0[1755]<=rg7c10d;ng1e1e0[1637]<=lfa5351[0];ng1e1e0[1631]<=hq1ba15;ng1e1e0[1622]<=of51f14[0];ng1e1e0[1546]<=xw791a7[0];ng1e1e0[1535]<=vx38d3b;ng1e1e0[1531]<=ym157ea;ng1e1e0[1509]<=kf12e1b;ng1e1e0[1504]<=tu6c047;ng1e1e0[1471]<=nt27238[0];ng1e1e0[1468]<=qgcb360;ng1e1e0[1463]<=ice086a;ng1e1e0[1391]<=vk14915;ng1e1e0[1312]<=qia590[0];ng1e1e0[1226]<=gd29a8f[0];ng1e1e0[1215]<=xjdd0ab;ng1e1e0[1197]<=sj8f8a4[0];ng1e1e0[1153]<=ri9640b;ng1e1e0[1044]<=me469d7[0];ng1e1e0[1037]<=tj8169d;ng1e1e0[1023]<=reset_n;ng1e1e0[1022]<=ec34efc[0];ng1e1e0[1014]<=yzabf51;ng1e1e0[971]<=ou970dd;ng1e1e0[961]<=wj6023b;ng1e1e0[895]<=thc8e34[0];ng1e1e0[889]<=baa84b8;ng1e1e0[888]<=go59b01;ng1e1e0[879]<=sw82127[0];ng1e1e0[811]<=mr6a3e2[0];ng1e1e0[765]<=dm42afd;ng1e1e0[734]<=ba25a85[0];ng1e1e0[695]<=ale2922;ng1e1e0[656]<=ngb8296;ng1e1e0[576]<=ho52c81;ng1e1e0[518]<=ux902d3;ng1e1e0[444]<=kqf5097;ng1e1e0[405]<=rg4d47c[0];ng1e1e0[382]<=uve855f;ng1e1e0[347]<=tu7c524;ng1e1e0[328]<=hbd7052;ng1e1e0[259]<=pub205a;ng1e1e0[222]<=jr9ea12;ng1e1e0[164]<=xy3ae0a;ng1e1e0[111]<=by73d42[0];ng1e1e0[82]<=ria75c1;ng1e1e0[55]<=uk9dcf5[0];ng1e1e0[41]<=sw34eb8;ng1e1e0[27]<=nr5a773[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module osc4e65 ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- of653ad, \r
- ep29d6d, \r
-\r
- cz4eb6c \r
- );\r
-parameter wj75b64 = 4;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input of653ad;\r
-input [wj75b64-1:0] ep29d6d;\r
-output cz4eb6c;\r
-reg aa82cd7;\r
-reg db166b8;\r
-reg [15:0] gqb35c6;\r
-reg [31:0] an9ae31;\r
-wire thd718d = (~aa82cd7 & of653ad);\r
-wire cz4eb6c = db166b8 & (gqb35c6 == 0);\r
-wire [31:0] tu73a4e;\r
-reg uk9d272;\r
-reg [wj75b64 - 1 : 0] ay49c8f;\r
-reg kd4e479;\r
-reg kq723cd;\r
-reg [15 : 0] hd91e69;\r
-reg [31 : 0] oh8f34e;\r
-reg rg79a75;\r
-reg [31 : 0] pfcd3ab;\r
-reg [2047:0] ng1e1e0;\r
-wire [7:0] mef0f02;\r
-\r
-localparam uk87811 = 8,gd3c088 = 32'hfdffd84b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) gqb35c6 <= 0; else if (txmac_clk_en) begin if (rg79a75) begin casex(ay49c8f) 4'h1: begin gqb35c6[15:0] <= {9'b00000000, oh8f34e[0], {6{1'b0}}}; end 4'h2: begin gqb35c6[15:0] <= {8'b00000000, oh8f34e[1:0], {6{1'b0}}}; end 4'h3: begin gqb35c6[15:0] <= {7'b0000000, oh8f34e[2:0], {6{1'b0}}}; end 4'h4: begin gqb35c6[15:0] <= {6'b000000, oh8f34e[3:0], {6{1'b0}}}; end 4'h5: begin gqb35c6[15:0] <= {5'b00000, oh8f34e[4:0], {6{1'b0}}}; end 4'h6: begin gqb35c6[15:0] <= {4'b0000, oh8f34e[5:0], {6{1'b0}}}; end 4'h7: begin gqb35c6[15:0] <= {3'b000, oh8f34e[6:0], {6{1'b0}}}; end 4'h8: begin gqb35c6[15:0] <= {2'b00, oh8f34e[7:0], {6{1'b0}}}; end 4'h9: begin gqb35c6[15:0] <= {1'b0, oh8f34e[8:0], {6{1'b0}}}; end default: begin gqb35c6[15:0] <= {oh8f34e[9:0], {6{1'b0}}}; end endcase end else if (kq723cd) begin gqb35c6 <= hd91e69 - {{15{1'b0}}, 1'b1}; end end end\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin aa82cd7 <= 1'b0; db166b8 <= 1'b0; end else if (txmac_clk_en) begin aa82cd7 <= uk9d272; db166b8 <= kd4e479; end end assign tu73a4e[31:1] = oh8f34e[30:0]; assign tu73a4e[0] = oh8f34e[1]^oh8f34e[5]^oh8f34e[6]^oh8f34e[31];\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin an9ae31 <= {32{1'b1}}; end else if (txmac_clk_en) begin an9ae31 <= pfcd3ab; end end \r
-\r
-always@* begin uk9d272<=mef0f02[0];ay49c8f<={ep29d6d>>1,mef0f02[1]};kd4e479<=mef0f02[2];kq723cd<=mef0f02[3];hd91e69<={gqb35c6>>1,mef0f02[4]};oh8f34e<={an9ae31>>1,mef0f02[5]};rg79a75<=mef0f02[6];pfcd3ab<={tu73a4e>>1,mef0f02[7]};end\r
-always@* begin ng1e1e0[2047]<=ep29d6d[0];ng1e1e0[2046]<=aa82cd7;ng1e1e0[2044]<=db166b8;ng1e1e0[2040]<=gqb35c6[0];ng1e1e0[2033]<=an9ae31[0];ng1e1e0[2019]<=thd718d;ng1e1e0[1991]<=tu73a4e[0];ng1e1e0[1023]<=of653ad;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module mr7f553 (\r
- os627fb, \r
- mrdcc5e,\r
- hbe62f4,\r
- uv5e986,\r
- vif4c35,\r
- oua61ab,\r
- txmac_clk_en,\r
- vk86ac3\r
- );\r
-output [31:0] os627fb;\r
-input [7:0] mrdcc5e;\r
-input [31:0] vif4c35;\r
-input hbe62f4;\r
-input uv5e986;\r
-input oua61ab;\r
-input txmac_clk_en;\r
-input vk86ac3;\r
-reg [31:0] zm3f362;\r
-wire [31:0] ps6c4ff;\r
-wire [31:0] os627fb;\r
-reg [7 : 0] bn13fd8;\r
-reg wl9fec7;\r
-reg dzd8f4b;\r
-reg [31 : 0] nrc7a5e;\r
-reg [31 : 0] db3d2f6;\r
-reg [31 : 0] dze97b6;\r
-reg [2047:0] ng1e1e0;\r
-wire [5:0] mef0f02;\r
-\r
-localparam uk87811 = 6,gd3c088 = 32'hfdffc70b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-assign os627fb[31] = ~db3d2f6[0];\r
-assign os627fb[30] = ~db3d2f6[1];\r
-assign os627fb[29] = ~db3d2f6[2];\r
-assign os627fb[28] = ~db3d2f6[3];\r
-assign os627fb[27] = ~db3d2f6[4];\r
-assign os627fb[26] = ~db3d2f6[5];\r
-assign os627fb[25] = ~db3d2f6[6];\r
-assign os627fb[24] = ~db3d2f6[7];\r
-assign os627fb[23] = ~db3d2f6[8];\r
-assign os627fb[22] = ~db3d2f6[9];\r
-assign os627fb[21] = ~db3d2f6[10];\r
-assign os627fb[20] = ~db3d2f6[11];\r
-assign os627fb[19] = ~db3d2f6[12];\r
-assign os627fb[18] = ~db3d2f6[13];\r
-assign os627fb[17] = ~db3d2f6[14];\r
-assign os627fb[16] = ~db3d2f6[15];\r
-assign os627fb[15] = ~db3d2f6[16];\r
-assign os627fb[14] = ~db3d2f6[17];\r
-assign os627fb[13] = ~db3d2f6[18];\r
-assign os627fb[12] = ~db3d2f6[19];\r
-assign os627fb[11] = ~db3d2f6[20];\r
-assign os627fb[10] = ~db3d2f6[21];\r
-assign os627fb[9] = ~db3d2f6[22];\r
-assign os627fb[8] = ~db3d2f6[23];\r
-assign os627fb[7] = ~db3d2f6[24];\r
-assign os627fb[6] = ~db3d2f6[25];\r
-assign os627fb[5] = ~db3d2f6[26];\r
-assign os627fb[4] = ~db3d2f6[27];\r
-assign os627fb[3] = ~db3d2f6[28];\r
-assign os627fb[2] = ~db3d2f6[29];\r
-assign os627fb[1] = ~db3d2f6[30];\r
-assign os627fb[0] = ~db3d2f6[31];\r
-\r
-always @ (posedge oua61ab or negedge vk86ac3)\r
-begin if (!vk86ac3) begin zm3f362 <= 32'hffffffff; end else if (txmac_clk_en) begin if (wl9fec7) begin zm3f362 <= dze97b6; end else if (dzd8f4b) begin zm3f362 <= nrc7a5e; end end\r
-end\r
-\r
-assign ps6c4ff[0] = db3d2f6[30] ^ bn13fd8[7] ^ bn13fd8[1] ^ db3d2f6[24];\r
-assign ps6c4ff[1] = db3d2f6[30] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25];\r
-assign ps6c4ff[2] = db3d2f6[30] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ db3d2f6[26] ^ bn13fd8[5];\r
-assign ps6c4ff[3] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ bn13fd8[6];\r
-assign ps6c4ff[4] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[7];\r
-assign ps6c4ff[5] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[2] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[6] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[7] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[24] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[8] = db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ bn13fd8[7] ^ db3d2f6[0];\r
-assign ps6c4ff[9] = db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ db3d2f6[1];\r
-assign ps6c4ff[10] = db3d2f6[24] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[29] ^ bn13fd8[7] ^ db3d2f6[2];\r
-assign ps6c4ff[11] = db3d2f6[3] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ bn13fd8[6] ^ bn13fd8[7];\r
-assign ps6c4ff[12] = db3d2f6[30] ^ db3d2f6[4] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[5] ^ db3d2f6[28] ^ bn13fd8[6] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[13] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[5] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[14] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[6] ^ db3d2f6[26] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5] ^ db3d2f6[28];\r
-assign ps6c4ff[15] = db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[2] ^ db3d2f6[7] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[28] ^ db3d2f6[29];\r
-assign ps6c4ff[16] = db3d2f6[24] ^ bn13fd8[2] ^ bn13fd8[3] ^ db3d2f6[8] ^ db3d2f6[28] ^ db3d2f6[29] ^ bn13fd8[7];\r
-assign ps6c4ff[17] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[25] ^ bn13fd8[2] ^ db3d2f6[9] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[18] = db3d2f6[30] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ db3d2f6[26] ^ bn13fd8[5] ^ db3d2f6[10];\r
-assign ps6c4ff[19] = db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[11];\r
-assign ps6c4ff[20] = db3d2f6[12] ^ bn13fd8[3] ^ db3d2f6[28];\r
-assign ps6c4ff[21] = db3d2f6[13] ^ bn13fd8[2] ^ db3d2f6[29];\r
-assign ps6c4ff[22] = db3d2f6[14] ^ db3d2f6[24] ^ bn13fd8[7];\r
-assign ps6c4ff[23] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ db3d2f6[15] ^ db3d2f6[25] ^ bn13fd8[6] ^ bn13fd8[7];\r
-assign ps6c4ff[24] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ db3d2f6[16] ^ db3d2f6[26] ^ bn13fd8[5] ^ bn13fd8[6];\r
-assign ps6c4ff[25] = db3d2f6[26] ^ db3d2f6[17] ^ bn13fd8[4] ^ db3d2f6[27] ^ bn13fd8[5];\r
-assign ps6c4ff[26] = db3d2f6[30] ^ bn13fd8[1] ^ db3d2f6[24] ^ bn13fd8[3] ^ bn13fd8[4] ^ db3d2f6[27] ^ db3d2f6[18] ^ db3d2f6[28] ^ bn13fd8[7];\r
-assign ps6c4ff[27] = db3d2f6[31] ^ bn13fd8[0] ^ db3d2f6[25] ^ bn13fd8[2] ^ bn13fd8[3] ^ db3d2f6[28] ^ db3d2f6[19] ^ bn13fd8[6] ^ db3d2f6[29];\r
-assign ps6c4ff[28] = db3d2f6[30] ^ bn13fd8[1] ^ bn13fd8[2] ^ db3d2f6[26] ^ bn13fd8[5] ^ db3d2f6[29] ^ db3d2f6[20];\r
-assign ps6c4ff[29] = db3d2f6[30] ^ db3d2f6[21] ^ db3d2f6[31] ^ bn13fd8[0] ^ bn13fd8[1] ^ bn13fd8[4] ^ db3d2f6[27];\r
-assign ps6c4ff[30] = db3d2f6[31] ^ db3d2f6[22] ^ bn13fd8[0] ^ bn13fd8[3] ^ db3d2f6[28];\r
-assign ps6c4ff[31] = db3d2f6[23] ^ bn13fd8[2] ^ db3d2f6[29];\r
-always@* begin bn13fd8<={mrdcc5e>>1,mef0f02[0]};wl9fec7<=mef0f02[1];dzd8f4b<=mef0f02[2];nrc7a5e<={vif4c35>>1,mef0f02[3]};db3d2f6<={zm3f362>>1,mef0f02[4]};dze97b6<={ps6c4ff>>1,mef0f02[5]};end\r
-always@* begin ng1e1e0[2047]<=hbe62f4;ng1e1e0[2046]<=uv5e986;ng1e1e0[2044]<=vif4c35[0];ng1e1e0[2040]<=zm3f362[0];ng1e1e0[2032]<=ps6c4ff[0];ng1e1e0[1023]<=mrdcc5e[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ng3abec ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- xjec4b9, \r
- ay625cf, \r
- sj12e78, \r
- aa973c5, \r
- ieb9e28, \r
- tucf141 \r
- );\r
-parameter ea78a0b = 5;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input xjec4b9;\r
-input sj12e78;\r
-input aa973c5;\r
-input [ea78a0b-1:0] ay625cf;\r
-output tucf141;\r
-output ieb9e28;\r
-reg [ea78a0b-1:0] cm531bb;\r
-reg [ea78a0b-1:0] yxc6ec0;\r
-reg nt37604;\r
-reg ieb9e28;\r
-reg pfd813d;\r
-reg hoc09ef;\r
-reg tucf141;\r
-parameter bn27bdb = 1'b0;\r
-parameter fp3dedf = 1'b1;\r
-wire [ea78a0b-1:0] bl7b7f8 = ay625cf - 5'd1;\r
-reg [ea78a0b-1:0] icff1cb;\r
-wire uvf8e59 = xjec4b9 & ~nt37604;\r
-reg ykcb37c;\r
-reg [ea78a0b - 1 : 0] dzcdf08;\r
-reg ip6f847;\r
-reg lq7c23d;\r
-reg [ea78a0b - 1 : 0] wl8f53;\r
-reg [ea78a0b - 1 : 0] bn3d4ea;\r
-reg kqea756;\r
-reg ww53ab0;\r
-reg gq9d581;\r
-reg [ea78a0b - 1 : 0] qg56049;\r
-reg [ea78a0b - 1 : 0] vx81246;\r
-reg ph9236;\r
-reg [2047:0] ng1e1e0;\r
-wire [11:0] mef0f02;\r
-\r
-localparam uk87811 = 12,gd3c088 = 32'hfdffe0cb;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-always @ (wl8f53 or vx81246) begin if(wl8f53 == vx81246) tucf141 = 1'b1; else tucf141 = 1'b0; end\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin pfd813d <= bn27bdb; icff1cb <= 6'b0; end else if (txmac_clk_en) begin pfd813d <= gq9d581; icff1cb <= qg56049; end end always @ (ww53ab0 or ykcb37c or tucf141) begin case(ww53ab0) bn27bdb: begin if(!ykcb37c) begin hoc09ef = bn27bdb; end else begin hoc09ef = fp3dedf; end end fp3dedf: begin if(tucf141) begin hoc09ef = bn27bdb; end else begin hoc09ef = fp3dedf; end end endcase end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin cm531bb <= 5'd0; end else if (txmac_clk_en) begin if(ip6f847) begin cm531bb <= 5'd0; end else if(gq9d581) begin cm531bb <= wl8f53 + 5'd1; end else begin cm531bb <= 5'd0; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin nt37604 <= 1'b0; end else if (txmac_clk_en) begin nt37604 <= ykcb37c; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) yxc6ec0 <= 5'd0; else if (txmac_clk_en) begin if( (ph9236 || ((bn3d4ea != vx81246) && (bn3d4ea != 5'd0)) ) && (ieb9e28 || !lq7c23d) ) yxc6ec0 <= bn3d4ea + 5'd1; else if(!ph9236) begin yxc6ec0 <= 5'd0; end end end\r
- always @ (dzcdf08 or bn3d4ea) begin case(dzcdf08) 5'd24: ieb9e28 = bn3d4ea[4]; 5'd27: ieb9e28 = bn3d4ea[4] & (|bn3d4ea[3:1]); 5'd30: ieb9e28 = bn3d4ea[4] & (|bn3d4ea[3:2]); default: ieb9e28 = 1'b0; endcase end\r
-always@* begin ykcb37c<=mef0f02[0];dzcdf08<={ay625cf>>1,mef0f02[1]};ip6f847<=mef0f02[2];lq7c23d<=mef0f02[3];wl8f53<={cm531bb>>1,mef0f02[4]};bn3d4ea<={yxc6ec0>>1,mef0f02[5]};kqea756<=mef0f02[6];ww53ab0<=mef0f02[7];gq9d581<=mef0f02[8];qg56049<={bl7b7f8>>1,mef0f02[9]};vx81246<={icff1cb>>1,mef0f02[10]};ph9236<=mef0f02[11];end\r
-always@* begin ng1e1e0[2047]<=ay625cf[0];ng1e1e0[2046]<=sj12e78;ng1e1e0[2044]<=aa973c5;ng1e1e0[2040]<=cm531bb[0];ng1e1e0[2033]<=yxc6ec0[0];ng1e1e0[2018]<=nt37604;ng1e1e0[1988]<=pfd813d;ng1e1e0[1929]<=hoc09ef;ng1e1e0[1811]<=bl7b7f8[0];ng1e1e0[1574]<=icff1cb[0];ng1e1e0[1101]<=uvf8e59;ng1e1e0[1023]<=xjec4b9;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module bn91cf5 (txmac_clk,\r
- ir3994e,\r
- txmac_clk_en, \r
- gof5dd7, \r
- anaeeb9, \r
- yk775cd, \r
- phbae69, \r
- vvd734e, \r
- ukb9a76, \r
- nrcd3b1, \r
- fa69d8e, \r
- kd4ec72, \r
- ho76394, \r
- irb1ca3, \r
- tx_fifoavail, \r
- os728ef, \r
- jr94778, \r
- gqa3bc7, \r
- sj1de39, \r
- ayef1cc, \r
- ui78e60, \r
- tucf141, \r
- gd3980f, \r
- encc07d, \r
- mr603ec, \r
- ng1f65, \r
- cz4eb6c, \r
- ieb9e28, \r
- ldecac1, \r
- gb6560e, \r
- qi2b075, \r
- tx_discfrm, \r
- mec1d43, \r
- xyea19, \r
- ip750ca, \r
- lsa8654, \r
- ic432a3, \r
- tj19519, \r
- neca8cf, \r
- xjec4b9, \r
- iea33d5, \r
- of653ad, \r
- bycf546, \r
- sh7aa33, \r
- rgd519c, \r
- twa8ce3, \r
- qg4671a, \r
- ep338d1, \r
- fc9c68c, \r
- hbe3463, \r
- uk1a31e, \r
- qgd18f0, \r
- hq8c780, \r
- jc63c02, \r
- pu1e013, \r
- cmf009a, \r
- qv804d0, \r
- ep29d6d, \r
- hd13425, \r
- oh9a12e, \r
- vid0974, \r
- xl84ba2, \r
- hq25d17, \r
- sj12e78, \r
- aa973c5, \r
- nga2e8e \r
- );\r
-parameter wl17473 = 48;\r
-parameter fpba39c = 16;\r
-parameter uid1ce7 = 8;\r
-parameter ph8e738 = 16;\r
-parameter zk739c7 = 32;\r
-parameter ri9ce3a = 14;\r
-parameter wj75b64 = 4;\r
-parameter xl38e94 = 22;\r
-parameter ldc74a7 = 13;\r
-parameter pu3a53f = 13'd6072;\r
-parameter zxd29fb = 8'h55;\r
-parameter hd94fdf = 8'hd5;\r
-parameter nga7efe = 8'h00;\r
-parameter vk3f7f3 = 8'h01;\r
-parameter tufbf9b = 8'h80;\r
-parameter zkdfcda = 8'hc2;\r
-parameter jcfe6d3 = 8'h00;\r
-parameter dzf369b = 8'h00;\r
-parameter db9b4df = 8'h01;\r
-parameter lqda6fe = 8'h88;\r
-parameter yxd37f2 = 8'h08;\r
-parameter vx9bf94 = 8'h00;\r
-input txmac_clk;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input gof5dd7;\r
-input anaeeb9;\r
-input yk775cd;\r
-input phbae69;\r
-input vvd734e;\r
-input ukb9a76;\r
-input [wl17473-1:0] nrcd3b1;\r
-input [fpba39c-1:0] fa69d8e;\r
-input [uid1ce7-1:0] kd4ec72;\r
-input ho76394;\r
-input irb1ca3;\r
-input tx_fifoavail;\r
-input os728ef;\r
-input gqa3bc7;\r
-input sj1de39;\r
-input [ph8e738-1:0] ayef1cc;\r
-input ui78e60;\r
-input tucf141;\r
-input [zk739c7-1:0] gd3980f;\r
-input encc07d;\r
-input mr603ec;\r
-input [uid1ce7:0] jr94778;\r
-input ng1f65;\r
-input cz4eb6c;\r
-input ieb9e28;\r
-input ldecac1;\r
-input gb6560e;\r
-output qi2b075;\r
-output tx_discfrm;\r
-output mec1d43;\r
-output xyea19;\r
-output ip750ca;\r
-output [uid1ce7-1:0] lsa8654;\r
-output ic432a3;\r
-output [uid1ce7-1:0] tj19519;\r
-output neca8cf;\r
-output xjec4b9;\r
-output iea33d5;\r
-output of653ad;\r
-output bycf546;\r
-output sh7aa33;\r
-output rgd519c;\r
-output twa8ce3;\r
-output qg4671a;\r
-output ep338d1;\r
-output fc9c68c;\r
-output hbe3463;\r
-output uk1a31e;\r
-output qgd18f0;\r
-output hq8c780;\r
-output jc63c02;\r
-output pu1e013;\r
-output cmf009a;\r
-output qv804d0;\r
-output [wj75b64-1:0] ep29d6d;\r
-output hd13425;\r
-output oh9a12e;\r
-output vid0974;\r
-output xl84ba2;\r
-output hq25d17;\r
-output sj12e78;\r
-output aa973c5;\r
-output nga2e8e;\r
-reg [4:0] pfd813d ;\r
-reg [4:0] hoc09ef;\r
-reg xjec4b9;\r
-reg mt236ce;\r
-reg je1b674;\r
-reg [uid1ce7-1:0] kdd9d10;\r
-reg [uid1ce7-1:0] pf74420;\r
-reg [uid1ce7-1:0] gq10832;\r
-reg [uid1ce7-1:0] lsa8654;\r
-reg qi2b075;\r
-reg lf32197;\r
-reg oh90cbf;\r
-reg ri865fc;\r
-reg ip750ca;\r
-reg ym97f1e;\r
-reg zzbf8f1;\r
-reg xjfc78e;\r
-reg [1:0] hbe3c76;\r
-reg [1:0] zm1e3b7;\r
-reg faf1dba;\r
-reg tj8edd3;\r
-reg mec1d43;\r
-reg xyea19;\r
-reg tx_discfrm;\r
-reg czd3c9f;\r
-reg fp9e4fd;\r
-reg czf27ee;\r
-reg ic432a3;\r
-reg iea33d5;\r
-reg vid0974;\r
-reg hd13425;\r
-reg oh9a12e;\r
-reg nga2e8e;\r
-reg [wj75b64-1:0] ep29d6d;\r
-reg cmf009a;\r
-reg pu1e013;\r
-reg qv804d0;\r
-reg of653ad;\r
-reg ld55e0b;\r
-reg [ldc74a7-1:0] go782f6;\r
-reg xl84ba2;\r
-reg hq25d17;\r
-reg sj12e78;\r
-reg rtf6015;\r
-reg lfb00af;\r
-reg kf8057e;\r
-reg aa973c5;\r
-reg [3:0] gq15fa4;\r
-reg hdafd20;\r
-reg fn7e907;\r
-reg [1:0] rgf483e;\r
-reg kfa41f3;\r
-reg xy20f9d;\r
-reg ux7cea;\r
-reg ec3e754;\r
-parameter pff3aa1 = 5'd0;\r
-parameter ou9d50e = 5'd1;\r
-parameter ykea871 = 5'd2;\r
-parameter kd54389 = 5'd3;\r
-parameter qva1c4d = 5'd4;\r
-parameter pue26c = 5'd5;\r
-parameter bl71363 = 5'd6;\r
-parameter hq89b1e = 5'd7;\r
-parameter ne4d8f3 = 5'd8;\r
-parameter jc6c79b = 5'd9;\r
-parameter tu63cdb = 5'd10;\r
-parameter ri1e6db = 5'd11;\r
-parameter vvf36da = 5'd12;\r
-parameter rv9b6d7 = 5'd13;\r
-parameter sudb6be = 5'd14;\r
-parameter aydb5f0 = 5'd15;\r
-parameter nedaf80 = 5'd16;\r
-parameter thd7c03 = 5'd17;\r
-parameter kfbe01f = 5'd18;\r
-parameter icf00fd = 5'd19;\r
-parameter mt807e8 = 5'd20;\r
-parameter vx3f44 = 5'd21;\r
-wire bycf546 = (pfd813d == pff3aa1) ? 1 : 0;\r
-wire sh7aa33 = (pfd813d == ou9d50e) ? 1 : 0;\r
-wire rgd519c = (pfd813d == ykea871) ? 1 : 0;\r
-wire twa8ce3 = (pfd813d == kd54389) ? 1 : 0;\r
-wire qg4671a = (pfd813d == qva1c4d) ? 1 : 0;\r
-wire fc9c68c = (pfd813d == pue26c) ? 1 : 0;\r
-wire ep338d1 = (pfd813d == bl71363) ? 1 : 0;\r
-wire hbe3463 = (pfd813d == hq89b1e) ? 1 : 0;\r
-wire uk1a31e = (pfd813d == ne4d8f3) ? 1 : 0;\r
-wire qgd18f0 = (pfd813d == jc6c79b) ? 1 : 0;\r
-wire qv90c78 = (pfd813d == tu63cdb) ? 1 : 0;\r
-wire hq8c780 = (pfd813d == ri1e6db) ? 1 : 0;\r
-wire sj23348 = (pfd813d == vvf36da) ? 1 : 0;\r
-wire by69136 = (pfd813d == rv9b6d7) ? 1 : 0;\r
-wire jc63c02 = (pfd813d == sudb6be) ? 1 : 0;\r
-wire rv9bb69 = (pfd813d == aydb5f0) ? 1 : 0;\r
-wire qg6d3f4 = (pfd813d == nedaf80) ? 1 : 0;\r
-wire zx7e856 = (pfd813d == thd7c03) ? 1 : 0;\r
-wire mgad95 = (go782f6 == pu3a53f);\r
-wire [uid1ce7-1:0] tj19519 = pf74420[7:0];\r
-wire neca8cf = tj8edd3;\r
-reg [2:0] xj4aae6;\r
-reg [5:0] jp55736;\r
-reg [7:0] irab9b7;\r
-reg kq5cdbd;\r
-reg rte6de8;\r
-reg cb36f47;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg pub7a3c;\r
-reg pubd1e2;\r
-reg uve8f12;\r
-reg zk47894;\r
-reg ux3c4a2;\r
-reg ipe2514;\r
-reg [wl17473 - 1 : 0] vx94525;\r
-reg [fpba39c - 1 : 0] ng1497b;\r
-reg [uid1ce7 - 1 : 0] tw25ed4;\r
-reg ng2f6a2;\r
-reg xj7b512;\r
-reg jcda897;\r
-reg kqd44bb;\r
-reg [uid1ce7 : 0] ir12eca;\r
-reg ym97655;\r
-reg uxbb2a8;\r
-reg [ph8e738 - 1 : 0] jccaa2d;\r
-reg bl5516a;\r
-reg vka8b57;\r
-reg [zk739c7 - 1 : 0] bn2d5d7;\r
-reg ip6aebf;\r
-reg lq575fd;\r
-reg vxbafea;\r
-reg rtd7f56;\r
-reg vxbfab7;\r
-reg qtfd5be;\r
-reg ayeadf4;\r
-reg [4 : 0] ww53ab0;\r
-reg [4 : 0] gq9d581;\r
-reg cbbe84a;\r
-reg tuf4254;\r
-reg [uid1ce7 - 1 : 0] rv9515;\r
-reg [uid1ce7 - 1 : 0] gb54576;\r
-reg [uid1ce7 - 1 : 0] ou15dab;\r
-reg sjaed58;\r
-reg ne76ac5;\r
-reg bnb562a;\r
-reg irab156;\r
-reg ho58ab4;\r
-reg rgc55a2;\r
-reg [1 : 0] hq2ad12;\r
-reg [1 : 0] cm56893;\r
-reg epb4499;\r
-reg fca24cc;\r
-reg gd12662;\r
-reg fc93314;\r
-reg xy998a2;\r
-reg qtcc512;\r
-reg [ldc74a7 - 1 : 0] ls144a1;\r
-reg xya250b;\r
-reg ux1285a;\r
-reg tj942d5;\r
-reg [3 : 0] kfa16af;\r
-reg xyb57d;\r
-reg nr5abeb;\r
-reg [1 : 0] rgd5f5f;\r
-reg rvafafa;\r
-reg ea7d7d7;\r
-reg jcebeb8;\r
-reg vv5f5c3;\r
-reg ykfae1e;\r
-reg pfd70f0;\r
-reg zmb8786;\r
-reg wjc3c32;\r
-reg vk1e194;\r
-reg [2 : 0] ykf0ca2;\r
-reg [5 : 0] ng86511;\r
-reg [7 : 0] hd3288b;\r
-reg fp9445e;\r
-reg baa22f7;\r
-reg zm117ba;\r
-reg [2047:0] ng1e1e0;\r
-wire [70:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 71,gd3c088 = 32'hfdffd48b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin pfd813d <= pff3aa1; cb36f47 <= 0; pf74420 <= 0; oh90cbf <= 0; fp9e4fd <= 0; tj8edd3 <= 0; xjfc78e <= 0; zm1e3b7 <= 0; gq10832 <= 0; ri865fc <= 0; czf27ee <= 0; lsa8654 <= 0; ip750ca <= 0; ic432a3 <= 0; iea33d5 <= 0; end else if (txmac_clk_en) begin iea33d5 <= uxbb2a8 & (bycf546 | sh7aa33) ? 1'b1 : ~uxbb2a8 ? 1'b0 : iea33d5; pfd813d <= gq9d581; cb36f47 <= ym97655; pf74420 <= rv9515; oh90cbf <= sjaed58; fp9e4fd <= gd12662; tj8edd3 <= epb4499; xjfc78e <= ho58ab4; zm1e3b7 <= hq2ad12; ri865fc <= ne76ac5 | irab156; czf27ee <= fc93314; if (rgc55a2 == 1) begin case (cm56893) 3: begin gq10832 <= bn2d5d7[7:0]; end 2: begin gq10832 <= bn2d5d7[15:8]; end 1: begin gq10832 <= bn2d5d7[23:16]; end 0: begin gq10832 <= bn2d5d7[31:24]; end endcase end else begin gq10832 <= gb54576; end lsa8654 <= ou15dab; ip750ca <= bnb562a; ic432a3 <= xy998a2; end end always @ (ww53ab0 or jcda897 or tw25ed4 or ng2f6a2 or zm117ba or pub7a3c or zk47894 or pubd1e2 or vka8b57 or uxbb2a8 or lq575fd or vxbafea or bl5516a or aa973c5 or uve8f12 or cbbe84a or kqd44bb or ip6aebf or tj942d5 or ir12eca or ep29d6d or vxbfab7 or qtfd5be or rvafafa or tuf4254 or ec3e754 or ux7cea or nr5abeb or oh9a12e or hd13425 or ayeadf4 or ykf0ca2 or baa22f7 or hd3288b) begin xjec4b9 = 0; kdd9d10 = 0; qi2b075 = 0; lf32197 = 0; ym97f1e = 0; cmf009a = 0; faf1dba = 0; hbe3c76 = 0; zzbf8f1 = 0; xyea19 = 0; tx_discfrm = 0; czd3c9f = 0; pu1e013 = 0; qv804d0 = 0; ld55e0b = 0; of653ad = 0; mec1d43 = 0; hq25d17 = 0; sj12e78 = 0; hdafd20 = 0; xy20f9d = 0;\r
- case (ww53ab0) pff3aa1: begin if(vka8b57) begin hoc09ef = ou9d50e; xjec4b9 = 1'b0; end else begin\r
-\r
-\r
- if(aa973c5 && !vxbfab7 && uve8f12) begin if(jcda897) begin hoc09ef = aydb5f0; end else begin hoc09ef = pff3aa1; end xjec4b9 = 1'b0; sj12e78 = 1'b1; end else begin hoc09ef = pff3aa1; xjec4b9 = 1'b1; end\r
-\r
-\r
- end end ou9d50e: begin\r
-\r
-\r
- if(pub7a3c) begin if(uve8f12) begin if (jcda897) begin if(!aa973c5 || vxbfab7) begin hoc09ef = ykea871; end else begin hoc09ef = aydb5f0; end end else begin hoc09ef = ou9d50e; end end else begin if( (jcda897 && (!uxbb2a8 || zm117ba)) || (pubd1e2 && bl5516a) ) begin hoc09ef = ykea871; end else begin hoc09ef = ou9d50e; end end end else begin hoc09ef = ou9d50e; end \r
-\r
-\r
-\r
- end \r
-\r
-\r
- aydb5f0: begin if(aa973c5) begin hoc09ef = aydb5f0; ld55e0b = 1'b1; sj12e78 = 1'b1; end else begin hoc09ef = nedaf80; end end\r
-\r
-\r
-\r
- nedaf80: begin if(vka8b57) begin hoc09ef = ykea871; xjec4b9 = 1'b0; end else begin\r
-\r
-\r
- if(!aa973c5 || vxbfab7) begin hoc09ef = nedaf80; xjec4b9 = 1'b1; end else begin hoc09ef = aydb5f0; xjec4b9 = 1'b0; sj12e78 = 1'b1; end\r
-\r
-\r
- end end\r
- ykea871: begin kdd9d10 = zxd29fb; lf32197 = 1; if(ykf0ca2 == 0) begin hoc09ef = kd54389; end else begin hoc09ef = ykea871; end end kd54389: begin kdd9d10 = hd94fdf; lf32197 = 1;\r
-\r
-\r
- if(uve8f12) begin if(tj942d5 || tuf4254) begin if(ep29d6d == 4'hf) hoc09ef = thd7c03; else begin hoc09ef = tu63cdb; end end else begin if(kqd44bb) begin hoc09ef = qva1c4d; end else begin pu1e013 = 1; hoc09ef = sudb6be; end end end else begin if(bl5516a && pubd1e2) hoc09ef = pue26c; else begin hoc09ef = qva1c4d; end end \r
-\r
-\r
- end qva1c4d: begin qi2b075 = 1; lf32197 = 1'b1; kdd9d10 = tw25ed4[7:0]; faf1dba = 1;\r
-\r
-\r
- if(qtfd5be) begin if(lq575fd) begin hoc09ef = bl71363; end else begin hoc09ef = ne4d8f3; end end else if(uve8f12) begin if(ip6aebf) begin cmf009a = 1'b1; end if(tj942d5 || cbbe84a) begin if(ip6aebf && (ep29d6d == 4'hf) ) begin hoc09ef = thd7c03; end else if(ip6aebf) begin hq25d17 = 1'b1; hoc09ef = tu63cdb; end else begin hoc09ef = jc6c79b; end end else if (ng2f6a2 && !zk47894) begin if(lq575fd && !vxbafea) begin hoc09ef = bl71363; end else begin hoc09ef = hq89b1e; end end else if (ng2f6a2 && zk47894) begin hoc09ef = kfbe01f; end else begin hoc09ef = qva1c4d; end end else begin if(ng2f6a2 && !zk47894) begin if(lq575fd && !vxbafea) begin hoc09ef = bl71363; end else begin hoc09ef = hq89b1e; end end else if(ng2f6a2 && zk47894) begin hoc09ef = kfbe01f; end else begin hoc09ef = qva1c4d; end end \r
-\r
-\r
- end \r
- pue26c: begin kdd9d10 = hd3288b; lf32197 = 1; faf1dba = 1; if(baa22f7) begin hoc09ef = hq89b1e; end else begin hoc09ef = pue26c; end end \r
- bl71363: begin lf32197 = 1; faf1dba = 1; kdd9d10 = nga7efe; \r
-\r
-\r
- if(uve8f12 && (tj942d5 || cbbe84a)) begin if(ep29d6d == 4'hf) begin hoc09ef = thd7c03; end else begin if(!qtfd5be) begin hq25d17 = 1'b1; hoc09ef = tu63cdb; end else begin hoc09ef = ne4d8f3; end end end else if(zk47894 && qtfd5be && ayeadf4) begin hoc09ef = jc6c79b; end else if(vxbafea) begin if(qtfd5be) begin hoc09ef = ne4d8f3; end else begin hoc09ef = hq89b1e; end end else begin hoc09ef = bl71363; end\r
-\r
-\r
- end hq89b1e: begin lf32197 = 1; zzbf8f1 = 1; case (ykf0ca2[1:0]) 3: begin hbe3c76 = 2'h3; end 2: begin hbe3c76 = 2'h2; end 1: begin hbe3c76 = 2'h1; end 0: begin hbe3c76 = 2'h0; end endcase\r
-\r
-\r
- if(uve8f12 && (tj942d5 || cbbe84a)) begin hoc09ef = jc6c79b; end else if (ykf0ca2[1:0] == 2'b00) begin hoc09ef = kfbe01f; end else begin hoc09ef = hq89b1e; end\r
-\r
-\r
- end\r
- kfbe01f: begin ym97f1e = 1;\r
-\r
-\r
- if(uve8f12 && (tj942d5 || cbbe84a)) begin hoc09ef = icf00fd; xy20f9d = 1; end else begin hoc09ef = vx3f44; end \r
-\r
-\r
- end \r
- vx3f44: begin\r
-\r
-\r
- if(uve8f12 && (tj942d5 || cbbe84a)) begin hoc09ef = icf00fd; xy20f9d = 1; ym97f1e = 1; end else begin xyea19 = 1; qv804d0 = 1; mec1d43 = 1; hoc09ef = pff3aa1; end \r
-\r
-\r
- end \r
-\r
-\r
-\r
- icf00fd: begin ym97f1e = 1; xy20f9d = 1; if(rvafafa) begin hoc09ef = mt807e8; end else begin hoc09ef = icf00fd; end end mt807e8: begin ym97f1e = 1; hoc09ef = pff3aa1; tx_discfrm = 1; mec1d43 = 1; qv804d0 = 1; end \r
-\r
-\r
-\r
- ne4d8f3: begin lf32197 = 1; zzbf8f1 = 1; hbe3c76 = 2'h3; czd3c9f = 1; if (ykf0ca2[1:0] == 2'b01) begin hoc09ef = jc6c79b; end else begin hoc09ef = ne4d8f3; end end\r
-\r
-\r
-\r
- thd7c03: begin lf32197 = 1; zzbf8f1 = 1; hbe3c76 = 2; czd3c9f = 0; hoc09ef = jc6c79b; end\r
-\r
-\r
-\r
- jc6c79b: begin lf32197 = 1;\r
-\r
-\r
- if(oh9a12e || hd13425) begin hdafd20 = 1; if(nr5abeb) begin czd3c9f = 0; tx_discfrm = 1; qv804d0 = 1; mec1d43 = 1; hoc09ef = pff3aa1; end else begin hoc09ef = jc6c79b; end end else begin zzbf8f1 = 1; hbe3c76 = 1; czd3c9f = 1; tx_discfrm = 1; qv804d0 = 1; mec1d43 = 1; hoc09ef = pff3aa1; end\r
-\r
-\r
- end\r
-\r
-\r
- tu63cdb: begin lf32197 = 1; hdafd20 = 1; if(nr5abeb) begin hoc09ef = ri1e6db; end else begin hoc09ef = tu63cdb; end end\r
- ri1e6db: begin case ({ec3e754, ux7cea}) 2'b00: begin xjec4b9 = 1; of653ad = 1; hoc09ef = ri1e6db; end 2'b01: begin xjec4b9 = 1; of653ad = 0; hoc09ef = ri1e6db; end 2'b10: begin xjec4b9 = 0; of653ad = 1; hoc09ef = ri1e6db; end 2'b11: begin xjec4b9 = 0; of653ad = 0; if(aa973c5) begin hoc09ef = vvf36da; ld55e0b = 1; end else begin hoc09ef = ykea871; end end endcase end vvf36da: begin if(aa973c5) begin hoc09ef = vvf36da; ld55e0b = 1; end else begin hoc09ef = rv9b6d7; xjec4b9 = 1; end end\r
-\r
-\r
-\r
- rv9b6d7: begin if(vka8b57) begin hoc09ef = ykea871; xjec4b9 = 0; end else begin\r
-\r
-\r
- if(aa973c5 && !vxbfab7 && uve8f12) begin hoc09ef = vvf36da; xjec4b9 = 0; sj12e78 = 1; end else begin hoc09ef = rv9b6d7; xjec4b9 = 1; end\r
-\r
-\r
- end end sudb6be: begin pu1e013 = 1; lf32197 = 1; kdd9d10 = ir12eca[7:0];\r
-\r
-\r
- if(cbbe84a) begin if(ep29d6d == 4'hf) hoc09ef = thd7c03; else begin hoc09ef = tu63cdb; hq25d17 = 1'b1; end end else if(kqd44bb) begin pu1e013 = 0; if(ir12eca[8]) hoc09ef = bl71363; else begin hoc09ef = qva1c4d; end end else begin hoc09ef = sudb6be; end\r
-\r
-\r
- end default: hoc09ef = pff3aa1;\r
- endcase end \r
-\r
-\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin mt236ce <= 0; end else if (txmac_clk_en) begin if(tj942d5 && (rgd519c || twa8ce3 || qg4671a || ep338d1 || hbe3463 || jc63c02)) begin mt236ce <= 1; end else if(bycf546 || hq8c780) begin mt236ce <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin je1b674 <= 0; end else if (txmac_clk_en) begin if(tj942d5 && rgd519c) begin je1b674 <= 1; end else if(bycf546 || hq8c780) begin je1b674 <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin ep29d6d <= 4'h0; end else if (txmac_clk_en) begin if( nr5abeb ) begin ep29d6d <= ep29d6d + 4'h1; end else if(bycf546) begin ep29d6d <= 4'h0; end end end\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin hd13425 <= 0; end else if (txmac_clk_en) begin if(tj942d5 && !ip6aebf && uve8f12) begin hd13425 <= 1; end else if(bycf546) begin hd13425 <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin vid0974 <= 0; end else if (txmac_clk_en) begin if(pfd70f0 || vv5f5c3) begin vid0974 <= 1; end else if(bycf546) begin vid0974 <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin oh9a12e <= 0; end else if (txmac_clk_en) begin if(wjc3c32) begin oh9a12e <= 1; end else if(bycf546) begin oh9a12e <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin xl84ba2 <= 0; end else if (txmac_clk_en) begin if(vk1e194) begin xl84ba2 <= 1; end else if(bycf546) begin xl84ba2 <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin go782f6 <= 13'd0; end else if (txmac_clk_en) begin if(qtcc512) begin go782f6 <= ls144a1 + 13'd1; end else begin go782f6 <= 13'd0; end end end\r
-\r
-\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin nga2e8e <= 0; end else if (txmac_clk_en) begin if(uk1a31e) begin nga2e8e <= 1; end else if(bycf546) begin nga2e8e <= 0; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin xj4aae6 <= 0; end else if (txmac_clk_en) begin if ((sh7aa33) || (zmb8786) || (hq8c780) || (ykfae1e)) begin xj4aae6 <= 6; end else if ((qg4671a) || (fc9c68c) || (ep338d1)) begin xj4aae6 <= 3; end else if (ykf0ca2 != 0) begin xj4aae6 <= ykf0ca2 - 1; end end end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin irab9b7 <= 0; jp55736 <= 0; kq5cdbd <= 0; rte6de8 <= 0; end else if (txmac_clk_en) begin if (rgd519c) begin jp55736 <= 0; kq5cdbd <= 0; rte6de8 <= 0; end else begin jp55736 <= ng86511 + 1; if (ng86511 == 18) begin kq5cdbd <= 1; end if (ng86511 == 59) begin rte6de8 <= 1; end end case ({fp9445e,ng86511}) 0: begin irab9b7 <= vk3f7f3; end 1: begin irab9b7 <= tufbf9b; end 2: begin irab9b7 <= zkdfcda; end 3: begin irab9b7 <= jcfe6d3; end 4: begin irab9b7 <= dzf369b; end 5: begin irab9b7 <= db9b4df; end 6: begin irab9b7 <= vx94525[47:40]; end 7: begin irab9b7 <= vx94525[39:32]; end 8: begin irab9b7 <= vx94525[31:24]; end 9: begin irab9b7 <= vx94525[23:16]; end 10: begin irab9b7 <= vx94525[15:8]; end 11: begin irab9b7 <= vx94525[7:0]; end 12: begin irab9b7 <= lqda6fe; end 13: begin irab9b7 <= yxd37f2; end 14: begin irab9b7 <= ng1497b[15:8]; end 15: begin irab9b7 <= ng1497b[7:0]; end 16: begin irab9b7 <= jccaa2d[15:8]; end 17: begin irab9b7 <= jccaa2d[7:0]; end default: begin irab9b7 <= vx9bf94; end endcase end end\r
-\r
-\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin rgf483e <= 0; end else if (txmac_clk_en) begin if(ea7d7d7) begin rgf483e <= rgd5f5f + 1; end else begin rgf483e <= 0; end end end always @ (rgd5f5f) begin if(rgd5f5f == 2'b11) begin kfa41f3 = 1; end else begin kfa41f3 = 0; end end\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin gq15fa4 <= 4'h0; end else if (txmac_clk_en) begin if(xyb57d) begin gq15fa4 <= kfa16af + 4'h1; end else begin gq15fa4 <= 4'h0; end end end always @ (kfa16af) begin fn7e907 = (kfa16af == 4'h3) ? 1'b1 : 1'b0; end\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin rtf6015 <= 0; lfb00af <= 0; kf8057e <= 0; aa973c5 <= 0; end else if (txmac_clk_en) begin rtf6015 <= ipe2514; lfb00af <= ux3c4a2; kf8057e <= xya250b; aa973c5 <= ux1285a; end end \r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin ec3e754 = 0; end else if (txmac_clk_en) begin if(hq8c780 && vka8b57) begin ec3e754 = 1; end else if(rgd519c || vv5f5c3) begin ec3e754 = 0; end end end\r
- always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin ux7cea = 0; end else if (txmac_clk_en) begin if(hq8c780 && rtd7f56) begin ux7cea = 1; end else if(rgd519c || vv5f5c3) begin ux7cea = 0; end end end\r
-\r
-\r
-\r
-\r
-always@* begin pub7a3c<=mef0f02[0];pubd1e2<=mef0f02[1];uve8f12<=mef0f02[2];zk47894<=mef0f02[3];ux3c4a2<=mef0f02[4];ipe2514<=mef0f02[5];vx94525<={nrcd3b1>>1,mef0f02[6]};ng1497b<={fa69d8e>>1,mef0f02[7]};tw25ed4<={kd4ec72>>1,mef0f02[8]};ng2f6a2<=mef0f02[9];xj7b512<=mef0f02[10];jcda897<=mef0f02[11];kqd44bb<=mef0f02[12];ir12eca<={jr94778>>1,mef0f02[13]};ym97655<=mef0f02[14];uxbb2a8<=mef0f02[15];jccaa2d<={ayef1cc>>1,mef0f02[16]};bl5516a<=mef0f02[17];vka8b57<=mef0f02[18];bn2d5d7<={gd3980f>>1,mef0f02[19]};ip6aebf<=mef0f02[20];lq575fd<=mef0f02[21];vxbafea<=mef0f02[22];rtd7f56<=mef0f02[23];vxbfab7<=mef0f02[24];qtfd5be<=mef0f02[25];ayeadf4<=mef0f02[26];ww53ab0<={pfd813d>>1,mef0f02[27]};gq9d581<={hoc09ef>>1,mef0f02[28]};cbbe84a<=mef0f02[29];tuf4254<=mef0f02[30];rv9515<={kdd9d10>>1,mef0f02[31]};gb54576<={pf74420>>1,mef0f02[32]};ou15dab<={gq10832>>1,mef0f02[33]};sjaed58<=mef0f02[34];ne76ac5<=mef0f02[35];bnb562a<=mef0f02[36];irab156<=mef0f02[37];ho58ab4<=mef0f02[38];rgc55a2<=mef0f02[39];hq2ad12<={hbe3c76>>1,mef0f02[40]};cm56893<={zm1e3b7>>1,mef0f02[41]};epb4499<=mef0f02[42];fca24cc<=mef0f02[43];gd12662<=mef0f02[44];fc93314<=mef0f02[45];xy998a2<=mef0f02[46];qtcc512<=mef0f02[47];ls144a1<={go782f6>>1,mef0f02[48]};xya250b<=mef0f02[49];ux1285a<=mef0f02[50];tj942d5<=mef0f02[51];kfa16af<={gq15fa4>>1,mef0f02[52]};xyb57d<=mef0f02[53];nr5abeb<=mef0f02[54];rgd5f5f<={rgf483e>>1,mef0f02[55]};rvafafa<=mef0f02[56];ea7d7d7<=mef0f02[57];jcebeb8<=mef0f02[58];vv5f5c3<=mef0f02[59];ykfae1e<=mef0f02[60];pfd70f0<=mef0f02[61];zmb8786<=mef0f02[62];wjc3c32<=mef0f02[63];vk1e194<=mef0f02[64];ykf0ca2<={xj4aae6>>1,mef0f02[65]};ng86511<={jp55736>>1,mef0f02[66]};hd3288b<={irab9b7>>1,mef0f02[67]};fp9445e<=mef0f02[68];baa22f7<=mef0f02[69];zm117ba<=mef0f02[70];end\r
-always@* begin ng1e1e0[2047]<=anaeeb9;ng1e1e0[2046]<=yk775cd;ng1e1e0[2044]<=phbae69;ng1e1e0[2040]<=vvd734e;ng1e1e0[2032]<=ukb9a76;ng1e1e0[2018]<=faf1dba;ng1e1e0[2017]<=nrcd3b1[0];ng1e1e0[1989]<=tj8edd3;ng1e1e0[1987]<=fa69d8e[0];ng1e1e0[1931]<=czd3c9f;ng1e1e0[1927]<=kd4ec72[0];ng1e1e0[1865]<=ayef1cc[0];ng1e1e0[1859]<=gq10832[0];ng1e1e0[1844]<=hdafd20;ng1e1e0[1815]<=fp9e4fd;ng1e1e0[1806]<=ho76394;ng1e1e0[1682]<=ui78e60;ng1e1e0[1674]<=qv90c78;ng1e1e0[1671]<=lf32197;ng1e1e0[1640]<=fn7e907;ng1e1e0[1582]<=czf27ee;ng1e1e0[1565]<=irb1ca3;ng1e1e0[1488]<=kdd9d10[0];ng1e1e0[1485]<=kf8057e;ng1e1e0[1326]<=gb6560e;ng1e1e0[1317]<=tucf141;ng1e1e0[1300]<=sj23348;ng1e1e0[1297]<=xj4aae6[0];ng1e1e0[1295]<=oh90cbf;ng1e1e0[1233]<=rgf483e[0];ng1e1e0[1210]<=hoc09ef[0];ng1e1e0[1189]<=cz4eb6c;ng1e1e0[1172]<=encc07d;ng1e1e0[1116]<=ld55e0b;ng1e1e0[1105]<=rv9bb69;ng1e1e0[1092]<=irab9b7[0];ng1e1e0[1087]<=ym97f1e;ng1e1e0[1082]<=tx_fifoavail;ng1e1e0[1023]<=gof5dd7;ng1e1e0[1009]<=zm1e3b7[0];ng1e1e0[932]<=sj1de39;ng1e1e0[929]<=pf74420[0];ng1e1e0[922]<=gq15fa4[0];ng1e1e0[837]<=xy20f9d;ng1e1e0[744]<=je1b674;ng1e1e0[742]<=lfb00af;ng1e1e0[663]<=ldecac1;ng1e1e0[648]<=mgad95;ng1e1e0[605]<=pfd813d[0];ng1e1e0[594]<=ng1f65;ng1e1e0[586]<=gd3980f[0];ng1e1e0[552]<=by69136;ng1e1e0[547]<=cb36f47;ng1e1e0[546]<=jp55736[0];ng1e1e0[543]<=ri865fc;ng1e1e0[504]<=hbe3c76[0];ng1e1e0[466]<=gqa3bc7;ng1e1e0[418]<=kfa41f3;ng1e1e0[372]<=mt236ce;ng1e1e0[371]<=rtf6015;ng1e1e0[331]<=ieb9e28;ng1e1e0[324]<=zx7e856;ng1e1e0[297]<=mr603ec;ng1e1e0[273]<=rte6de8;ng1e1e0[252]<=xjfc78e;ng1e1e0[233]<=jr94778[0];ng1e1e0[185]<=go782f6[0];ng1e1e0[162]<=qg6d3f4;ng1e1e0[136]<=kq5cdbd;ng1e1e0[126]<=zzbf8f1;ng1e1e0[116]<=os728ef;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module pf61d16 ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- gof5dd7, \r
- anaeeb9, \r
- tx_sndpausreq, \r
- tx_sndpaustim, \r
- wyb3e52, \r
- ux9f290, \r
- tj19519, \r
- ho76394, \r
- by52133, \r
- bycf546, \r
- qg4671a, \r
- ep338d1,\r
- uk1a31e,\r
- hbe3463,\r
- hq8c780,\r
- jc63c02, \r
- fc9c68c,\r
- nga2e8e,\r
- qi2b075,\r
- xyea19,\r
- tx_discfrm,\r
- mec1d43,\r
- ep29d6d,\r
- hd13425,\r
- oh9a12e,\r
- xjc8b1c,\r
- vid0974,\r
- gd2c73f, \r
- vi639fd, \r
- ui78e60, \r
- ayef1cc, \r
- sj1de39, \r
- encc07d, \r
- mr603ec, \r
- ng1f65, \r
- tx_statvec, \r
- tx_staten, \r
- tx_done, \r
- qia3a3d, \r
- gb6560e, \r
- ldecac1 \r
- );\r
-parameter ph8e738 = 16;\r
-parameter uid1ce7 = 8;\r
-parameter wj75b64 = 4;\r
-parameter ri9ce3a = 14;\r
-parameter ho6c5b3 = 31;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input gof5dd7;\r
-input anaeeb9;\r
-input tx_sndpausreq;\r
-input [ph8e738-1:0] tx_sndpaustim;\r
-input wyb3e52;\r
-input ux9f290;\r
-input [uid1ce7-1:0] tj19519;\r
-input ho76394;\r
-input by52133;\r
-input bycf546;\r
-input qg4671a;\r
-input ep338d1;\r
-input uk1a31e;\r
-input hbe3463;\r
-input hq8c780;\r
-input jc63c02;\r
-input fc9c68c;\r
-input nga2e8e;\r
-input qi2b075;\r
-input xyea19;\r
-input tx_discfrm;\r
-input mec1d43;\r
-input [wj75b64-1:0] ep29d6d;\r
-input hd13425;\r
-input oh9a12e;\r
-input xjc8b1c;\r
-input vid0974;\r
-output gd2c73f;\r
-output vi639fd;\r
-output ui78e60;\r
-output [ph8e738-1:0] ayef1cc;\r
-output sj1de39;\r
-output encc07d;\r
-output mr603ec;\r
-output ng1f65;\r
-output [ho6c5b3-1:0] tx_statvec;\r
-output tx_staten;\r
-output tx_done;\r
-output qia3a3d;\r
-output gb6560e;\r
-output ldecac1;\r
-reg [ho6c5b3-1:0] tx_statvec;\r
-reg ui78e60;\r
-reg [ph8e738-1:0] ayef1cc;\r
-reg sj1de39;\r
-reg ps5d2df;\r
-reg [ri9ce3a-1:0] uv4b7df;\r
-reg of5befd;\r
-reg [uid1ce7-1:0] fafbf6a;\r
-reg gd2c73f;\r
-reg vi639fd;\r
-reg shed49d ;\r
-reg of6a4ed ;\r
-reg tx_done ;\r
-reg qia3a3d;\r
-reg qi9db13 ;\r
-reg mred898;\r
-reg tx_staten ;\r
-reg yk62623;\r
-reg db13118;\r
-reg gq988c6;\r
-reg ldecac1;\r
-reg oh23180;\r
-reg an18c04;\r
-reg ofc6024;\r
-reg ng30125;\r
-reg an8092a;\r
-reg fc4955;\r
-reg sw24aab;\r
-reg fc25558;\r
-reg je2aac3;\r
-reg ng1f65;\r
-reg gb6560e;\r
-reg mr603ec;\r
-wire encc07d = mr603ec;\r
-wire bydf8eb;\r
-wire blfc75b = &tj19519;\r
-wire wl1d6f7 = ofc6024 & ng30125 & an8092a & fc4955 & sw24aab & fc25558;\r
-wire dz55311 = ~(|uv4b7df[13:6]);\r
-wire ww4c478 = ldecac1 | nga2e8e;\r
-wire [ho6c5b3-1:0] ww78015 = {dz55311, ep29d6d[3:0], oh9a12e, hd13425, xjc8b1c, vid0974, uv4b7df[13:0], gq988c6, oh23180 | je2aac3, ldecac1, bydf8eb, ww4c478, wl1d6f7, db13118 | an18c04, yk62623};\r
-wire je35187 = qg4671a | ep338d1 | fc9c68c;\r
-wire aa8748b = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & ~uv4b7df[2] & ~uv4b7df[1] & uv4b7df[0];\r
-wire gb5efc8 = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & ~uv4b7df[2] & uv4b7df[1] & ~uv4b7df[0];\r
-wire ui67dfc = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & ~uv4b7df[2] & uv4b7df[1] & uv4b7df[0];\r
-wire wj44d9d = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & uv4b7df[2] & ~uv4b7df[1] & ~uv4b7df[0];\r
-wire ww6d020 = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & uv4b7df[2] & ~uv4b7df[1] & uv4b7df[0];\r
-wire bl4f4d7 = je35187 & (~(|uv4b7df[13:4])) & ~uv4b7df[3] & uv4b7df[2] & uv4b7df[1] & ~uv4b7df[0];\r
-wire vvecbf5 = je35187 & (~(|uv4b7df[13:4])) & uv4b7df[3] & uv4b7df[2] & uv4b7df[1] & ~uv4b7df[0];\r
-wire yma3c6e = ~gq988c6 & ((|uv4b7df[13:11]) | (&uv4b7df[10:9]) | (uv4b7df[10] & uv4b7df[8] & (&uv4b7df[7:5]) & (uv4b7df[4] | (&uv4b7df[3:0]))));\r
-wire icced42 = (|uv4b7df[13:11]) | (&uv4b7df[10:9]) | (uv4b7df[10] & uv4b7df[8] & (&uv4b7df[7:4]) & ((|uv4b7df[3:2]) | (&uv4b7df[1:0])));\r
-reg pub7a3c;\r
-reg pubd1e2;\r
-reg end918e;\r
-reg [ph8e738 - 1 : 0] ay463af;\r
-reg ec31d79;\r
-reg lf8ebc9;\r
-reg [uid1ce7 - 1 : 0] dbaf275;\r
-reg ng2f6a2;\r
-reg alc9d72;\r
-reg kd4eb95;\r
-reg ip75cac;\r
-reg qvae565;\r
-reg su72b2c;\r
-reg oh95960;\r
-reg qiacb04;\r
-reg uv65820;\r
-reg wl2c104;\r
-reg uv60825;\r
-reg vk412c;\r
-reg ng20962;\r
-reg ri4b12;\r
-reg ls25893;\r
-reg [wj75b64 - 1 : 0] ay49c8f;\r
-reg an126a8;\r
-reg je93544;\r
-reg ep9aa22;\r
-reg xwd5115;\r
-reg pua88ab;\r
-reg [ri9ce3a - 1 : 0] vx22ad4;\r
-reg gq156a7;\r
-reg [uid1ce7 - 1 : 0] zx5a9cc;\r
-reg icd4e67;\r
-reg vka7338;\r
-reg ep399c2;\r
-reg ofcce15;\r
-reg qg670ad;\r
-reg rv38568;\r
-reg ldc2b46;\r
-reg ks15a36;\r
-reg lsad1b0;\r
-reg ic68d83;\r
-reg go46c18;\r
-reg yz360c0;\r
-reg phb0605;\r
-reg pu8302e;\r
-reg wl18173;\r
-reg lqc0b9d;\r
-reg ou5ceb;\r
-reg mg2e759;\r
-reg ne73ac8;\r
-reg ym9d642;\r
-reg byeb211;\r
-reg [ho6c5b3 - 1 : 0] jpc8451;\r
-reg zk4228e;\r
-reg xy11473;\r
-reg qv8a39b;\r
-reg ip51cdd;\r
-reg xl8e6ec;\r
-reg lq73767;\r
-reg ph9bb3b;\r
-reg jpdd9df;\r
-reg jpecefe;\r
-reg os677f6;\r
-reg [2047:0] ng1e1e0;\r
-wire [62:0] mef0f02;\r
-\r
-localparam uk87811 = 63,gd3c088 = 32'hfdffe44b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
- \r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin shed49d <= 1'b0; of6a4ed <= 1'b0; tx_done <= 1'b0; qia3a3d <= 1'b0; qi9db13 <= 1'b0; mred898 <= 1'b0; tx_staten <= 1'b0; end else if (txmac_clk_en) begin tx_done <= vka7338; of6a4ed <= icd4e67; shed49d <= ng20962; qia3a3d <= ri4b12; tx_staten <= ofcce15; mred898 <= ep399c2; qi9db13 <= ls25893; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin sj1de39 <= 1'b0; end else if (txmac_clk_en) begin if(lf8ebc9) begin sj1de39 <= 1'b0; end else if(pua88ab) begin sj1de39 <= pua88ab; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin uv4b7df <= 14'd0; ng1f65 <= 0; gb6560e <= 0; mr603ec <= 1; end else if (txmac_clk_en) begin if (vx22ad4[13:0] == 14'd58) begin ng1f65 <= 1; end else begin ng1f65 <= 0; end if (vx22ad4[13:0] == 14'd63) begin gb6560e <= 1; end else begin gb6560e <= 0; end if (ng1f65 == 1) begin mr603ec <= 0; end if(su72b2c) begin uv4b7df <= vx22ad4 + 14'd4; end else if(ip75cac || uv65820 || oh95960 || wl2c104 || qvae565) begin uv4b7df <= vx22ad4 + 14'd1; end else if(kd4eb95 || qiacb04) begin uv4b7df <= 14'd0; mr603ec <= 1; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin yk62623 <= 1'b0; db13118 <= 1'b0; end else if (txmac_clk_en) begin if (xy11473) begin if(dbaf275[0]) begin yk62623 <= 1'b0; db13118 <= 1'b1; end else begin yk62623 <= 1'b1; db13118 <= 1'b0; end end else if(kd4eb95) begin yk62623 <= 1'b0; db13118 <= 1'b0; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) ofc6024 <= 1'b0; else if (txmac_clk_en) begin if (xy11473) begin if(mg2e759) ofc6024 <= 1'b1; else ofc6024 <= 1'b0; end else if(kd4eb95) ofc6024 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) ng30125 <= 1'b0; else if (txmac_clk_en) begin if (qv8a39b) begin if(mg2e759) ng30125 <= 1'b1; else ng30125 <= 1'b0; end else if(kd4eb95) ng30125 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) an8092a <= 1'b0; else if (txmac_clk_en) begin if (ip51cdd) begin if(mg2e759) an8092a <= 1'b1; else an8092a <= 1'b0; end else if(kd4eb95) an8092a <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) fc4955 <= 1'b0; else if (txmac_clk_en) begin if (xl8e6ec) begin if(mg2e759) fc4955 <= 1'b1; else fc4955 <= 1'b0; end else if(kd4eb95) fc4955 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) sw24aab <= 1'b0; else if (txmac_clk_en) begin if (lq73767) begin if(mg2e759) sw24aab <= 1'b1; else sw24aab <= 1'b0; end else if(kd4eb95) sw24aab <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) fc25558 <= 1'b0; else if (txmac_clk_en) begin if (ph9bb3b) begin if(mg2e759) fc25558 <= 1'b1; else fc25558 <= 1'b0; end else if(kd4eb95) fc25558 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin gq988c6 <= 1'b0; je2aac3 <= 1'b0; end else if (txmac_clk_en) begin if(jpdd9df) begin if ((zx5a9cc == 8'h81) && (dbaf275 == 8'h00)) begin gq988c6 <= 1'b1; je2aac3 <= 1'b0; end else if ((zx5a9cc == 8'h88) && (dbaf275 == 8'h08)) begin gq988c6 <= 1'b0; je2aac3 <= 1'b1; end else begin gq988c6 <= 1'b0; je2aac3 <= 1'b0; end end else if(kd4eb95) begin gq988c6 <= 1'b0; je2aac3 <= 1'b0; end end end \r
- assign bydf8eb = jpecefe | os677f6;\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) ldecac1 <= 1'b0; else if (txmac_clk_en) begin if(ip75cac && alc9d72 && !(gq156a7 || ng2f6a2)) begin ldecac1 <= 1'b1; end else if(kd4eb95) ldecac1 <= 1'b0; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) oh23180 <= 1'b0; else if (txmac_clk_en) begin if(wl2c104) oh23180 <= 1'b1; else if(kd4eb95) oh23180 <= 1'b0 ; end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) an18c04 <= 1'b0; else if (txmac_clk_en) begin if (oh95960 || su72b2c) begin an18c04 <= ks15a36; end end end \r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin gd2c73f <= 1'b0; vi639fd <= 1'b0; ps5d2df <= 1'b0; tx_statvec <= 31'd0; end else if (txmac_clk_en) begin gd2c73f <= pub7a3c; vi639fd <= pubd1e2; ps5d2df <= ec31d79; if (ls25893 == 1) begin tx_statvec <= jpc8451; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin of5befd <= 0; fafbf6a <= 0; end else if (txmac_clk_en) begin fafbf6a <= dbaf275; if(vk412c) begin of5befd <= ng2f6a2; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin ui78e60 <= 1'b0; ayef1cc <= 16'h0000; end else if (txmac_clk_en) begin if(wl2c104) ui78e60 <= 1'b0; else if(end918e) begin ui78e60 <= end918e; ayef1cc <= ay463af; end end end\r
-always@* begin pub7a3c<=mef0f02[0];pubd1e2<=mef0f02[1];end918e<=mef0f02[2];ay463af<={tx_sndpaustim>>1,mef0f02[3]};ec31d79<=mef0f02[4];lf8ebc9<=mef0f02[5];dbaf275<={tj19519>>1,mef0f02[6]};ng2f6a2<=mef0f02[7];alc9d72<=mef0f02[8];kd4eb95<=mef0f02[9];ip75cac<=mef0f02[10];qvae565<=mef0f02[11];su72b2c<=mef0f02[12];oh95960<=mef0f02[13];qiacb04<=mef0f02[14];uv65820<=mef0f02[15];wl2c104<=mef0f02[16];uv60825<=mef0f02[17];vk412c<=mef0f02[18];ng20962<=mef0f02[19];ri4b12<=mef0f02[20];ls25893<=mef0f02[21];ay49c8f<={ep29d6d>>1,mef0f02[22]};an126a8<=mef0f02[23];je93544<=mef0f02[24];ep9aa22<=mef0f02[25];xwd5115<=mef0f02[26];pua88ab<=mef0f02[27];vx22ad4<={uv4b7df>>1,mef0f02[28]};gq156a7<=mef0f02[29];zx5a9cc<={fafbf6a>>1,mef0f02[30]};icd4e67<=mef0f02[31];vka7338<=mef0f02[32];ep399c2<=mef0f02[33];ofcce15<=mef0f02[34];qg670ad<=mef0f02[35];rv38568<=mef0f02[36];ldc2b46<=mef0f02[37];ks15a36<=mef0f02[38];lsad1b0<=mef0f02[39];ic68d83<=mef0f02[40];go46c18<=mef0f02[41];yz360c0<=mef0f02[42];phb0605<=mef0f02[43];pu8302e<=mef0f02[44];wl18173<=mef0f02[45];lqc0b9d<=mef0f02[46];ou5ceb<=mef0f02[47];mg2e759<=mef0f02[48];ne73ac8<=mef0f02[49];ym9d642<=mef0f02[50];byeb211<=mef0f02[51];jpc8451<={ww78015>>1,mef0f02[52]};zk4228e<=mef0f02[53];xy11473<=mef0f02[54];qv8a39b<=mef0f02[55];ip51cdd<=mef0f02[56];xl8e6ec<=mef0f02[57];lq73767<=mef0f02[58];ph9bb3b<=mef0f02[59];jpdd9df<=mef0f02[60];jpecefe<=mef0f02[61];os677f6<=mef0f02[62];end\r
-always@* begin ng1e1e0[2047]<=anaeeb9;ng1e1e0[2046]<=tx_sndpausreq;ng1e1e0[2044]<=tx_sndpaustim[0];ng1e1e0[2040]<=wyb3e52;ng1e1e0[2033]<=ux9f290;ng1e1e0[2019]<=tj19519[0];ng1e1e0[1991]<=ho76394;ng1e1e0[1934]<=by52133;ng1e1e0[1929]<=bydf8eb;ng1e1e0[1898]<=jc63c02;ng1e1e0[1821]<=bycf546;ng1e1e0[1810]<=blfc75b;ng1e1e0[1749]<=fc9c68c;ng1e1e0[1707]<=xyea19;ng1e1e0[1666]<=uv4b7df[0];ng1e1e0[1630]<=ng30125;ng1e1e0[1595]<=qg4671a;ng1e1e0[1572]<=wl1d6f7;ng1e1e0[1506]<=fc25558;ng1e1e0[1450]<=nga2e8e;ng1e1e0[1440]<=vid0974;ng1e1e0[1384]<=oh9a12e;ng1e1e0[1370]<=ep29d6d[0];ng1e1e0[1366]<=tx_discfrm;ng1e1e0[1284]<=of5befd;ng1e1e0[1212]<=an8092a;ng1e1e0[1202]<=vvecbf5;ng1e1e0[1174]<=wj44d9d;ng1e1e0[1170]<=aa8748b;ng1e1e0[1142]<=ep338d1;ng1e1e0[1125]<=gq988c6;ng1e1e0[1097]<=dz55311;ng1e1e0[1041]<=shed49d;ng1e1e0[1023]<=gof5dd7;ng1e1e0[964]<=je2aac3;ng1e1e0[949]<=hq8c780;ng1e1e0[853]<=qi2b075;ng1e1e0[833]<=ps5d2df;ng1e1e0[815]<=ofc6024;ng1e1e0[753]<=sw24aab;ng1e1e0[720]<=xjc8b1c;ng1e1e0[714]<=icced42;ng1e1e0[692]<=hd13425;ng1e1e0[685]<=mec1d43;ng1e1e0[601]<=bl4f4d7;ng1e1e0[587]<=ui67dfc;ng1e1e0[585]<=je35187;ng1e1e0[562]<=db13118;ng1e1e0[520]<=fafbf6a[0];ng1e1e0[474]<=hbe3463;ng1e1e0[407]<=an18c04;ng1e1e0[376]<=fc4955;ng1e1e0[357]<=yma3c6e;ng1e1e0[300]<=ww6d020;ng1e1e0[293]<=gb5efc8;ng1e1e0[292]<=ww78015[0];ng1e1e0[281]<=yk62623;ng1e1e0[237]<=uk1a31e;ng1e1e0[203]<=oh23180;ng1e1e0[146]<=ww4c478;ng1e1e0[140]<=mred898;ng1e1e0[70]<=qi9db13;ng1e1e0[35]<=of6a4ed;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module su77480 ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
- yz803f5, \r
- ls1fac, \r
- oufd63, \r
- ux9f290 \r
- );\r
-parameter ph8e738 = 16;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input yz803f5;\r
-input ls1fac;\r
-input [ph8e738-1:0] oufd63;\r
-output ux9f290;\r
-reg [ph8e738-1:0] xl285a7;\r
-reg [5:0] by42d3f;\r
-reg pfd813d;\r
-reg hoc09ef;\r
-reg ux9f290;\r
-reg vk3f5eb;\r
-parameter bn27bdb = 1'b0;\r
-parameter fp3dedf = 1'b1;\r
-reg jebd6c7;\r
-reg xweb63a;\r
-reg [ph8e738 - 1 : 0] zxd8e94;\r
-reg [ph8e738 - 1 : 0] je3a537;\r
-reg [5 : 0] dzd29bb;\r
-reg ww53ab0;\r
-reg gq9d581;\r
-reg jr377f1;\r
-reg [2047:0] ng1e1e0;\r
-wire [7:0] mef0f02;\r
-\r
-localparam uk87811 = 8,gd3c088 = 32'hfdffd14b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin pfd813d <= bn27bdb; end else if (txmac_clk_en) begin pfd813d <= gq9d581; end end always @ (ww53ab0 or jebd6c7 or ux9f290) begin case(ww53ab0) bn27bdb: begin if(jebd6c7) begin hoc09ef = fp3dedf; end else begin hoc09ef = bn27bdb; end end fp3dedf: begin if(ux9f290) begin hoc09ef = bn27bdb; end else begin hoc09ef = fp3dedf; end end endcase end always @ (posedge ph27329 or negedge ir3994e) begin if (!ir3994e) begin xl285a7 <= 0; ux9f290 <= 0; end else if (txmac_clk_en) begin if (xweb63a == 1) begin xl285a7 <= zxd8e94; end else if(ww53ab0 == fp3dedf) begin if (jr377f1 == 1) begin xl285a7 <= je3a537 - 1; end end else begin xl285a7 <= zxd8e94; end if (je3a537 == 0) begin ux9f290 <= 1; end else begin ux9f290 <= 0; end end end always @ (posedge ph27329 or negedge ir3994e) begin if (!ir3994e) begin by42d3f <= 0; vk3f5eb <= 0; end else if (txmac_clk_en) begin if (jebd6c7 && !xweb63a) begin by42d3f <= dzd29bb + 1; end else begin by42d3f <= 0; end if ((dzd29bb == 6'h3e) && (!xweb63a)) begin vk3f5eb <= 1; end else begin vk3f5eb <= 0; end end end\r
-always@* begin jebd6c7<=mef0f02[0];xweb63a<=mef0f02[1];zxd8e94<={oufd63>>1,mef0f02[2]};je3a537<={xl285a7>>1,mef0f02[3]};dzd29bb<={by42d3f>>1,mef0f02[4]};ww53ab0<=mef0f02[5];gq9d581<=mef0f02[6];jr377f1<=mef0f02[7];end\r
-always@* begin ng1e1e0[2047]<=ls1fac;ng1e1e0[2046]<=oufd63[0];ng1e1e0[2044]<=xl285a7[0];ng1e1e0[2040]<=by42d3f[0];ng1e1e0[2033]<=pfd813d;ng1e1e0[2019]<=hoc09ef;ng1e1e0[1990]<=vk3f5eb;ng1e1e0[1023]<=yz803f5;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ntb5e33 (txmac_clk,\r
- ir3994e,\r
- txmac_clk_en,\r
- tx_discfrm,\r
- tx_fifodata, \r
- tx_fifoeof, \r
- tx_fifoempty, \r
- tx_fifoctrl, \r
- tx_macread, \r
- kd4ec72, \r
- ho76394, \r
- by52133, \r
- gqa3bc7, \r
- irb1ca3, \r
- qi2b075 \r
- );\r
-parameter uid1ce7 = 8;\r
-input txmac_clk;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input tx_discfrm;\r
-input [uid1ce7-1:0] tx_fifodata;\r
-input tx_fifoeof;\r
-input tx_fifoempty;\r
-input tx_fifoctrl;\r
-output tx_macread;\r
-output [uid1ce7-1:0] kd4ec72;\r
-output ho76394;\r
-output by52133;\r
-output gqa3bc7;\r
-output irb1ca3;\r
-input qi2b075;\r
-reg [uid1ce7+2:0] ym9de6f;\r
-reg [uid1ce7+2:0] ps79bc0;\r
-reg [uid1ce7+2:0] cz6f01f;\r
-reg [uid1ce7+2:0] fac07e0;\r
-reg [uid1ce7+2:0] gq1f816;\r
-reg [uid1ce7+2:0] sue058e;\r
-reg [uid1ce7+2:0] fp1638c;\r
-reg [uid1ce7+2:0] ph8e335;\r
-reg [uid1ce7+2:0] ls8cd7f;\r
-reg [uid1ce7+2:0] ri35fdb;\r
-reg [uid1ce7+2:0] kd7f6df;\r
-reg [uid1ce7+2:0] aydb7eb;\r
-reg [uid1ce7+2:0] jcdfac1;\r
-reg [uid1ce7+2:0] vieb05c;\r
-reg [uid1ce7+2:0] uic1713;\r
-reg fcb898;\r
-reg su5c4c2;\r
-wire [uid1ce7-1:0] kd4ec72;\r
-wire tx_macread;\r
-wire ho76394;\r
-wire by52133;\r
-wire gqa3bc7;\r
-wire irb1ca3;\r
-reg ri4b12;\r
-reg [uid1ce7 - 1 : 0] al7a68d;\r
-reg ipd346d;\r
-reg wl9a36c;\r
-reg god1b64;\r
-reg vk412c;\r
-reg [uid1ce7 + 2 : 0] dm6c808;\r
-reg [uid1ce7 + 2 : 0] hq20217;\r
-reg [uid1ce7 + 2 : 0] ux85da;\r
-reg [uid1ce7 + 2 : 0] wl176a2;\r
-reg [uid1ce7 + 2 : 0] neda8a5;\r
-reg [uid1ce7 + 2 : 0] lsa2959;\r
-reg [uid1ce7 + 2 : 0] zza565a;\r
-reg [uid1ce7 + 2 : 0] me596b8;\r
-reg [uid1ce7 + 2 : 0] xj5ae09;\r
-reg [uid1ce7 + 2 : 0] vkb827e;\r
-reg [uid1ce7 + 2 : 0] lf9f90;\r
-reg [uid1ce7 + 2 : 0] th7e43e;\r
-reg [uid1ce7 + 2 : 0] kf90fbd;\r
-reg [uid1ce7 + 2 : 0] co3ef60;\r
-reg [uid1ce7 + 2 : 0] dobd804;\r
-reg hbec023;\r
-reg en6011f;\r
-reg [2047:0] ng1e1e0;\r
-wire [22:0] mef0f02;\r
-\r
-localparam uk87811 = 23,gd3c088 = 32'hfdffd48b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-assign tx_macread = hbec023 & ~wl9a36c;\r
-assign kd4ec72 = dm6c808[uid1ce7-1:0];\r
-assign ho76394 = dm6c808[uid1ce7];\r
-assign by52133 = ~(hq20217[uid1ce7+2] | dobd804[uid1ce7+2]);\r
-assign gqa3bc7 = dm6c808[uid1ce7+1];\r
-assign irb1ca3 = dm6c808[uid1ce7+2];\r
-always @ (dm6c808 or hq20217 or ux85da or wl176a2 or neda8a5 or lsa2959 or zza565a or dobd804 or vk412c) begin casex ({zza565a[uid1ce7+2],lsa2959[uid1ce7+2], neda8a5[uid1ce7+2],wl176a2[uid1ce7+2], ux85da[uid1ce7+2],hq20217[uid1ce7+2], dm6c808[uid1ce7+2],vk412c}) 8'bxxxxxx0x, 8'bxxxxx011: begin ph8e335 = dobd804; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bxxxxx010, 8'bxxxx0111: begin ph8e335 = hq20217; ls8cd7f = dobd804; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bxxxx0110, 8'bxxx01111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = dobd804; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bxxx01110, 8'bxx011111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = dobd804; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bxx011110, 8'bx0111111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = dobd804; jcdfac1 = zza565a; vieb05c = 11'h000; end 8'bx0111110, 8'b01111111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = dobd804; vieb05c = 11'h000; end 8'bx1111110, 8'b11111111: begin ph8e335 = hq20217; ls8cd7f = ux85da; ri35fdb = wl176a2; kd7f6df = neda8a5; aydb7eb = lsa2959; jcdfac1 = zza565a; vieb05c = dobd804; end endcase\r
-end always @ (posedge txmac_clk or negedge ir3994e) begin if(!ir3994e) begin ym9de6f <= 11'h000; ps79bc0 <= 11'h000; cz6f01f <= 11'h000; fac07e0 <= 11'h000; gq1f816 <= 11'h000; sue058e <= 11'h000; fp1638c <= 11'h000; uic1713 <= 11'h000; fcb898 <= 0; su5c4c2 <= 0; end else if (txmac_clk_en) begin uic1713 <= {en6011f, god1b64, ipd346d, al7a68d}; if ((dm6c808[uid1ce7+2] == 0) || (vk412c == 1)) begin ym9de6f <= me596b8; end if ((hq20217[uid1ce7+2] == 0) || (vk412c == 1)) begin ps79bc0 <= xj5ae09; end if ((ux85da[uid1ce7+2] == 0) || (vk412c == 1)) begin cz6f01f <= vkb827e; end if ((wl176a2[uid1ce7+2] == 0) || (vk412c == 1)) begin fac07e0 <= lf9f90; end if ((neda8a5[uid1ce7+2] == 0) || (vk412c == 1)) begin gq1f816 <= th7e43e; end if ((lsa2959[uid1ce7+2] == 0) || (vk412c == 1)) begin sue058e <= kf90fbd; end if ((zza565a[uid1ce7+2] == 0) || (vk412c == 1)) begin fp1638c <= co3ef60; end case (hbec023) 1: begin if ((wl176a2[uid1ce7+2] == 1) || (neda8a5[uid1ce7+2] == 1) || (lsa2959[uid1ce7+2] == 1) || (zza565a[uid1ce7+2] == 1)) begin fcb898 <= 0; end end 0: begin if ((neda8a5[uid1ce7+2] == 0) && (lsa2959[uid1ce7+2] == 0) && (zza565a[uid1ce7+2] == 0)) begin fcb898 <= 1; end end endcase su5c4c2 <= tx_macread; if (ri4b12 == 1) begin uic1713[uid1ce7+2] <= 0; fp1638c[uid1ce7+2] <= 0; sue058e[uid1ce7+2] <= 0; gq1f816[uid1ce7+2] <= 0; fac07e0[uid1ce7+2] <= 0; cz6f01f[uid1ce7+2] <= 0; ps79bc0[uid1ce7+2] <= 0; ym9de6f[uid1ce7+2] <= 0; su5c4c2 <= 0; fcb898 <= 0; end end end\r
-always@* begin ri4b12<=mef0f02[0];al7a68d<={tx_fifodata>>1,mef0f02[1]};ipd346d<=mef0f02[2];wl9a36c<=mef0f02[3];god1b64<=mef0f02[4];vk412c<=mef0f02[5];dm6c808<={ym9de6f>>1,mef0f02[6]};hq20217<={ps79bc0>>1,mef0f02[7]};ux85da<={cz6f01f>>1,mef0f02[8]};wl176a2<={fac07e0>>1,mef0f02[9]};neda8a5<={gq1f816>>1,mef0f02[10]};lsa2959<={sue058e>>1,mef0f02[11]};zza565a<={fp1638c>>1,mef0f02[12]};me596b8<={ph8e335>>1,mef0f02[13]};xj5ae09<={ls8cd7f>>1,mef0f02[14]};vkb827e<={ri35fdb>>1,mef0f02[15]};lf9f90<={kd7f6df>>1,mef0f02[16]};th7e43e<={aydb7eb>>1,mef0f02[17]};kf90fbd<={jcdfac1>>1,mef0f02[18]};co3ef60<={vieb05c>>1,mef0f02[19]};dobd804<={uic1713>>1,mef0f02[20]};hbec023<=mef0f02[21];en6011f<=mef0f02[22];end\r
-always@* begin ng1e1e0[2047]<=tx_fifodata[0];ng1e1e0[2046]<=tx_fifoeof;ng1e1e0[2044]<=tx_fifoempty;ng1e1e0[2040]<=tx_fifoctrl;ng1e1e0[2032]<=qi2b075;ng1e1e0[2017]<=ym9de6f[0];ng1e1e0[1987]<=ps79bc0[0];ng1e1e0[1927]<=cz6f01f[0];ng1e1e0[1865]<=kd7f6df[0];ng1e1e0[1806]<=fac07e0[0];ng1e1e0[1682]<=aydb7eb[0];ng1e1e0[1565]<=gq1f816[0];ng1e1e0[1317]<=jcdfac1[0];ng1e1e0[1172]<=uic1713[0];ng1e1e0[1082]<=sue058e[0];ng1e1e0[1023]<=tx_discfrm;ng1e1e0[932]<=ri35fdb[0];ng1e1e0[594]<=su5c4c2;ng1e1e0[586]<=vieb05c[0];ng1e1e0[466]<=ls8cd7f[0];ng1e1e0[297]<=fcb898;ng1e1e0[233]<=ph8e335[0];ng1e1e0[116]<=fp1638c[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ep1d3ac ( ph27329,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- ksacba5, \r
- yx65d28, \r
- aa2e944, \r
- bl74a21, \r
-\r
- nta510f, \r
- xl2887f, \r
- yx443fe \r
- );\r
-parameter ks21ff4 = 6;\r
-input ph27329;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input ksacba5;\r
-input yx65d28;\r
-input aa2e944;\r
-input bl74a21;\r
-output [ks21ff4-1:0] nta510f;\r
-output [ks21ff4-1:0] xl2887f;\r
-output yx443fe;\r
-reg [ks21ff4-1:0] nta510f;\r
-reg [ks21ff4-1:0] xl2887f;\r
-wire yx443fe = (nta510f == xl2887f);\r
-reg ho73d57;\r
-reg fp9eaba;\r
-reg eaf55d7;\r
-reg hdaaeb8;\r
-reg [2047:0] ng1e1e0;\r
-wire [3:0] mef0f02;\r
-\r
-localparam uk87811 = 4,gd3c088 = 32'hfdffd30b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
- always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin nta510f <= 5'd0; end else if (txmac_clk_en) begin if(ho73d57 || fp9eaba) begin nta510f <= 5'd0; end else if(eaf55d7) begin nta510f <= nta510f + 5'd1; end end end always @ (posedge ph27329 or negedge ir3994e) begin if(!ir3994e) begin xl2887f <= 5'd0; end else if (txmac_clk_en) begin if(ho73d57) begin xl2887f <= 5'd0; end else if(hdaaeb8) begin xl2887f <= xl2887f + 5'd1; end end end\r
-always@* begin ho73d57<=mef0f02[0];fp9eaba<=mef0f02[1];eaf55d7<=mef0f02[2];hdaaeb8<=mef0f02[3];end\r
-always@* begin ng1e1e0[2047]<=yx65d28;ng1e1e0[2046]<=aa2e944;ng1e1e0[2044]<=bl74a21;ng1e1e0[1023]<=ksacba5;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module uid1f98 ( txmac_clk,\r
- ir3994e,\r
- txmac_clk_en,\r
-\r
- \r
- gof5dd7, \r
- anaeeb9, \r
- phbae69, \r
- yk775cd, \r
- vk3f2df, \r
- vvf96fb, \r
- fa69d8e, \r
-\r
- \r
- tx_fifodata, \r
- tx_fifoeof, \r
- tx_fifoempty, \r
- tx_fifoavail, \r
- tx_sndpaustim, \r
- tx_sndpausreq, \r
- tx_fifoctrl, \r
-\r
- \r
- zk520c4, \r
- cb90622, \r
-\r
- \r
- ukb9a76, \r
- vvd734e, \r
-\r
- \r
- suc455c, \r
- \r
- \r
- tx_macread, \r
- tx_discfrm, \r
- tx_staten, \r
- tx_statvec, \r
- tx_done, \r
-\r
- \r
- ip750ca, \r
- lsa8654, \r
- ic432a3 \r
- );\r
-parameter pdevice_family = "XP2";\r
-parameter ea78a0b = 5;\r
-parameter wl17473 = 48;\r
-parameter fpba39c = 16;\r
-parameter uid1ce7 = 8;\r
-parameter ph8e738 = 16;\r
-parameter ho6c5b3 = 31;\r
-parameter zk739c7 = 32;\r
-parameter ri9ce3a = 14;\r
-parameter wj75b64 = 4;\r
-parameter ks21ff4 = 6;\r
-parameter xl38e94 = 22;\r
-parameter ldc74a7 = 13;\r
-parameter pu3a53f = 13'd6072;\r
-parameter zxd29fb = 8'h55;\r
-parameter hd94fdf = 8'hd5;\r
-parameter nga7efe = 8'h00;\r
-parameter vk3f7f3 = 8'h01;\r
-parameter tufbf9b = 8'h80;\r
-parameter zkdfcda = 8'hc2;\r
-parameter jcfe6d3 = 8'h00;\r
-parameter dzf369b = 8'h00;\r
-parameter db9b4df = 8'h01;\r
-parameter lqda6fe = 8'h88;\r
-parameter yxd37f2 = 8'h08;\r
-parameter vx9bf94 = 8'h00;\r
-input txmac_clk;\r
-input ir3994e;\r
-input txmac_clk_en;\r
-input gof5dd7;\r
-input anaeeb9;\r
-input phbae69;\r
-input yk775cd;\r
-input [ea78a0b-1:0] vk3f2df;\r
-input [wl17473-1:0] vvf96fb;\r
-input [fpba39c-1:0] fa69d8e;\r
-input [uid1ce7-1:0] tx_fifodata;\r
-input tx_fifoeof;\r
-input tx_fifoempty;\r
-input tx_fifoavail;\r
-input [ph8e738-1:0] tx_sndpaustim;\r
-input tx_sndpausreq;\r
-input tx_fifoctrl;\r
-input zk520c4;\r
-input [ph8e738-1:0] cb90622;\r
-input ukb9a76;\r
-input vvd734e;\r
-output suc455c;\r
-output tx_macread;\r
-output tx_discfrm;\r
-output tx_staten;\r
-output [ho6c5b3-1:0] tx_statvec;\r
-output tx_done;\r
-output ip750ca;\r
-output [uid1ce7-1:0] lsa8654;\r
-output ic432a3;\r
-wire [uid1ce7-1:0] kd4ec72;\r
-wire [ph8e738-1:0] ayef1cc;\r
-wire [zk739c7-1:0] gd3980f;\r
-wire encc07d;\r
-wire [uid1ce7-1:0] tj19519;\r
-wire [uid1ce7-1:0] lsa8654;\r
-wire [uid1ce7:0] jr94778;\r
-wire [wj75b64-1:0] ep29d6d;\r
-wire bycf546;\r
-wire sh7aa33;\r
-wire [ks21ff4-1:0] nr5a6ca;\r
-wire [ks21ff4-1:0] tj9b2b4;\r
-wire suc455c = bycf546 | sh7aa33;\r
-reg ohb4d51;\r
-reg pub7a3c;\r
-reg pubd1e2;\r
-reg zk47894;\r
-reg uve8f12;\r
-reg [ea78a0b - 1 : 0] xw695a0;\r
-reg [wl17473 - 1 : 0] cm5681e;\r
-reg [fpba39c - 1 : 0] ng1497b;\r
-reg [uid1ce7 - 1 : 0] al7a68d;\r
-reg ipd346d;\r
-reg wl9a36c;\r
-reg jcda897;\r
-reg [ph8e738 - 1 : 0] ay463af;\r
-reg end918e;\r
-reg god1b64;\r
-reg ipd9356;\r
-reg [ph8e738 - 1 : 0] ps4d5ad;\r
-reg ipe2514;\r
-reg ux3c4a2;\r
-reg [uid1ce7 - 1 : 0] tw25ed4;\r
-reg [ph8e738 - 1 : 0] jccaa2d;\r
-reg [zk739c7 - 1 : 0] bn2d5d7;\r
-reg ip6aebf;\r
-reg [uid1ce7 - 1 : 0] dbaf275;\r
-reg [uid1ce7 : 0] ir12eca;\r
-reg [wj75b64 - 1 : 0] ay49c8f;\r
-reg kd4eb95;\r
-reg lf81c3e;\r
-reg [ks21ff4 - 1 : 0] al70fbb;\r
-reg [ks21ff4 - 1 : 0] qi3eee8;\r
-reg [2047:0] ng1e1e0;\r
-wire [29:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 30,gd3c088 = 32'hfdffca8b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-ntb5e33 #( .uid1ce7(uid1ce7) ) lfb036d ( .txmac_clk (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .tx_discfrm (qia3a3d), .tx_fifodata (al7a68d), .tx_fifoeof (ipd346d), .tx_fifoempty (wl9a36c), .tx_fifoctrl (god1b64), .tx_macread (tx_macread), .kd4ec72 (kd4ec72), .ho76394 (ho76394), .by52133 (by52133), .gqa3bc7 (gqa3bc7), .irb1ca3 (irb1ca3), .qi2b075 (qi2b075) );\r
-bn91cf5 #( .wl17473( wl17473), .fpba39c(fpba39c), .uid1ce7(uid1ce7), .ph8e738(ph8e738), .zk739c7(zk739c7), .ri9ce3a(ri9ce3a), .wj75b64(wj75b64), .xl38e94(xl38e94), .ldc74a7(ldc74a7), .pu3a53f(pu3a53f), .zxd29fb(zxd29fb), .hd94fdf(hd94fdf), .nga7efe(nga7efe), .vk3f7f3(vk3f7f3), .tufbf9b(tufbf9b), .zkdfcda(zkdfcda), .jcfe6d3(jcfe6d3), .dzf369b(dzf369b), .db9b4df(db9b4df), .lqda6fe(lqda6fe), .yxd37f2(yxd37f2), .vx9bf94(vx9bf94) ) ph813b7 ( .txmac_clk (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .gof5dd7 (gd2c73f), .anaeeb9 (vi639fd), .yk775cd (uve8f12), .phbae69 (zk47894), .vvd734e (ux3c4a2), .ukb9a76 (ipe2514), .nrcd3b1 (cm5681e), .fa69d8e (ng1497b), .kd4ec72 (tw25ed4), .ho76394 (ho76394), .irb1ca3 (irb1ca3), .tx_fifoavail (jcda897), .os728ef (os728ef), .jr94778 (ir12eca), .gqa3bc7 (gqa3bc7), .sj1de39 (sj1de39), .ayef1cc (jccaa2d), .ui78e60 (ui78e60), .tucf141 (tucf141), .gd3980f (bn2d5d7), .encc07d (ip6aebf), .mr603ec (mr603ec), .ng1f65 (ng1f65), .cz4eb6c (cz4eb6c), .ieb9e28 (ieb9e28), .gb6560e (gb6560e), .ldecac1 (ldecac1), .qi2b075 (qi2b075), .tx_discfrm (tx_discfrm), .mec1d43 (mec1d43), .xyea19 (xyea19), .ip750ca (ip750ca), .lsa8654 (lsa8654), .ic432a3 (ic432a3), .tj19519 (tj19519), .neca8cf (neca8cf), .xjec4b9 (xjec4b9), .iea33d5 (iea33d5), .of653ad (of653ad), .bycf546 (bycf546), .sh7aa33 (sh7aa33), .rgd519c (rgd519c), .twa8ce3 (twa8ce3), .qg4671a (qg4671a), .ep338d1 (ep338d1), .fc9c68c (fc9c68c), .hbe3463 (hbe3463), .uk1a31e (uk1a31e), .qgd18f0 (qgd18f0), .hq8c780 (hq8c780), .jc63c02 (jc63c02), .pu1e013 (pu1e013), .cmf009a (cmf009a), .qv804d0 (qv804d0), .ep29d6d (ep29d6d), .hd13425 (hd13425), .oh9a12e (oh9a12e), .vid0974 (vid0974), .xl84ba2 (xl84ba2), .hq25d17 (hq25d17), .sj12e78 (sj12e78), .aa973c5 (aa973c5), .nga2e8e (nga2e8e) );\r
-\r
-pf61d16 #( .ph8e738(ph8e738), .uid1ce7(uid1ce7), .wj75b64(wj75b64), .ri9ce3a(ri9ce3a), .ho6c5b3(ho6c5b3) ) hbc8756 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en),\r
- .gof5dd7 (pub7a3c), .anaeeb9 (pubd1e2), .tx_sndpausreq (end918e), .tx_sndpaustim (ay463af), .wyb3e52 (ipd9356), .ux9f290 (ux9f290), .hq8c780 (hq8c780), .ep29d6d (ay49c8f), .hd13425 (hd13425), .oh9a12e (oh9a12e), .xjc8b1c (xl84ba2), .vid0974 (vid0974), .nga2e8e (nga2e8e), .bycf546 (kd4eb95), .qg4671a (qg4671a), .jc63c02 (jc63c02), .ep338d1 (ep338d1), .uk1a31e (uk1a31e), .hbe3463 (hbe3463), .fc9c68c (fc9c68c), .qi2b075 (qi2b075), .xyea19 (xyea19), .tx_discfrm (tx_discfrm), .mec1d43 (mec1d43), .tj19519 (dbaf275), .ho76394 (ho76394), .by52133 (by52133), .gd2c73f (gd2c73f), .vi639fd (vi639fd), .ui78e60 (ui78e60), .ayef1cc (ayef1cc), .sj1de39 (sj1de39), .encc07d (encc07d), .mr603ec (mr603ec), .ng1f65 (ng1f65), .tx_statvec (tx_statvec), .tx_staten (tx_staten), .tx_done (tx_done), .qia3a3d (qia3a3d), .gb6560e (gb6560e), .ldecac1 (ldecac1) );\r
-osc4e65 #( .wj75b64(wj75b64) ) ls11f27 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .of653ad (of653ad), .ep29d6d (ay49c8f), .cz4eb6c (cz4eb6c) );\r
-\r
-ng3abec #( .ea78a0b(ea78a0b) ) wy1f173 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .ay625cf (xw695a0), .xjec4b9 (xjec4b9), .sj12e78 (sj12e78), .aa973c5 (aa973c5), .ieb9e28 (ieb9e28), .tucf141 (tucf141) );\r
-su77480 #( .ph8e738(ph8e738) ) jr22521 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .yz803f5 (iea33d5), .ls1fac (ipd9356), .oufd63 (ps4d5ad), .ux9f290 (ux9f290) );\r
-mr7f553 byd04d0 ( .os627fb(gd3980f), .mrdcc5e (dbaf275), .hbe62f4 (neca8cf), .uv5e986 (kd4eb95), .vif4c35 (32'hffffffff), .oua61ab (txmac_clk), .vk86ac3 (ohb4d51), .txmac_clk_en (txmac_clk_en) ); ep1d3ac #( .ks21ff4(ks21ff4) ) dz5a743 ( .ph27329 (txmac_clk), .ir3994e (ohb4d51), .txmac_clk_en (txmac_clk_en), .ksacba5 (qv804d0), .yx65d28 (hq25d17), .aa2e944 (pu1e013), .bl74a21 (cmf009a), .nta510f (tj9b2b4), .xl2887f (nr5a6ca), .yx443fe (os728ef) );\r
-pmi_ram_dp #(.pmi_wr_addr_depth(64), .pmi_wr_addr_width(6), .pmi_wr_data_width(9), .pmi_rd_addr_depth(64), .pmi_rd_addr_width(6), .pmi_rd_data_width(9), .pmi_regmode("noreg"), .pmi_gsr("disable"), .pmi_resetmode("sync"), .pmi_init_file("none"), .pmi_init_file_format("binary"), .pmi_family(pdevice_family), .module_type("pmi_ram_dp") )\r
-thc75fb (.Data({ho76394, kd4ec72}), .WrAddress(nr5a6ca), .RdAddress(tj9b2b4), .WrClock(txmac_clk), .RdClock(txmac_clk), .WrClockEn(1'b1), .RdClockEn(txmac_clk_en), .WE(cmf009a), .Reset(1'b0), .Q(jr94778) );\r
-\r
- always@* begin ohb4d51<=mef0f02[0];pub7a3c<=mef0f02[1];pubd1e2<=mef0f02[2];zk47894<=mef0f02[3];uve8f12<=mef0f02[4];xw695a0<={vk3f2df>>1,mef0f02[5]};cm5681e<={vvf96fb>>1,mef0f02[6]};ng1497b<={fa69d8e>>1,mef0f02[7]};al7a68d<={tx_fifodata>>1,mef0f02[8]};ipd346d<=mef0f02[9];wl9a36c<=mef0f02[10];jcda897<=mef0f02[11];ay463af<={tx_sndpaustim>>1,mef0f02[12]};end918e<=mef0f02[13];god1b64<=mef0f02[14];ipd9356<=mef0f02[15];ps4d5ad<={cb90622>>1,mef0f02[16]};ipe2514<=mef0f02[17];ux3c4a2<=mef0f02[18];tw25ed4<={kd4ec72>>1,mef0f02[19]};jccaa2d<={ayef1cc>>1,mef0f02[20]};bn2d5d7<={gd3980f>>1,mef0f02[21]};ip6aebf<=mef0f02[22];dbaf275<={tj19519>>1,mef0f02[23]};ir12eca<={jr94778>>1,mef0f02[24]};ay49c8f<={ep29d6d>>1,mef0f02[25]};kd4eb95<=mef0f02[26];lf81c3e<=mef0f02[27];al70fbb<={nr5a6ca>>1,mef0f02[28]};qi3eee8<={tj9b2b4>>1,mef0f02[29]};end\r
-always@* begin ng1e1e0[2047]<=gof5dd7;ng1e1e0[2046]<=anaeeb9;ng1e1e0[2044]<=phbae69;ng1e1e0[2040]<=yk775cd;ng1e1e0[2032]<=vk3f2df[0];ng1e1e0[2017]<=vvf96fb[0];ng1e1e0[1987]<=fa69d8e[0];ng1e1e0[1926]<=tx_fifodata[0];ng1e1e0[1804]<=tx_fifoeof;ng1e1e0[1803]<=tj19519[0];ng1e1e0[1560]<=tx_fifoempty;ng1e1e0[1558]<=jr94778[0];ng1e1e0[1550]<=cb90622[0];ng1e1e0[1072]<=tx_fifoavail;ng1e1e0[1069]<=ep29d6d[0];ng1e1e0[1052]<=ukb9a76;ng1e1e0[1023]<=ir3994e;ng1e1e0[901]<=encc07d;ng1e1e0[775]<=zk520c4;ng1e1e0[732]<=tj9b2b4[0];ng1e1e0[450]<=gd3980f[0];ng1e1e0[387]<=tx_fifoctrl;ng1e1e0[366]<=nr5a6ca[0];ng1e1e0[225]<=ayef1cc[0];ng1e1e0[193]<=tx_sndpausreq;ng1e1e0[183]<=sh7aa33;ng1e1e0[112]<=kd4ec72[0];ng1e1e0[96]<=tx_sndpaustim[0];ng1e1e0[91]<=bycf546;ng1e1e0[56]<=vvd734e;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module fp8b349(\r
- \r
- hclk, \r
- reset_n, \r
-\r
- \r
- haddr, \r
- hdatain, \r
- hread_n, \r
- hwrite_n, \r
- hcs_n, \r
-\r
- \r
- hdataout, \r
- hready_n, \r
- hdataout_en_n, \r
-\r
- \r
- tx_en, \r
- vvcda9b, \r
- ui6d4df, \r
- vk3f2df, \r
-\r
- \r
- wj6023b, \r
- tu6c047, \r
- bydf307, \r
- go59b01, \r
- vk14915, \r
- ip60ebc, \r
- ep75e4,\r
- ls3af25,\r
- pfd792a,\r
- cobc957,\r
- xwe4ab9,\r
- tw255ca,\r
- ri2ae53, \r
- ale2922, \r
- qgcb360, \r
- ldcd808, \r
- kq53683, \r
-\r
- \r
- ba25a85, \r
- neda0c6, \r
- ned0632, \r
- yk775cd, \r
-\r
- \r
- aye5ebc, \r
-\r
- \r
- ene2fd7, \r
- cb17ebd, \r
- bldd558, \r
- ykeaac7, \r
- gq3baab \r
-);\r
-\r
-parameter oh29c1 = 8;\r
-\r
-parameter doa7062 = 8;\r
-parameter rv38312 = 15;\r
-parameter icc1896 = 15;\r
-parameter tjc4b1 = 15;\r
-parameter ay6258e = 8;\r
-parameter sj12c70 = 3;\r
-parameter ba96385 = 7;\r
-parameter sjb1c2a = 7;\r
-parameter tj8e155 = 15;\r
-parameter gb70aaf = 10;\r
-parameter an8557d = 4;\r
-parameter ba2abec = 10;\r
-parameter jp55f63 = 15;\r
-parameter bn1c73a = 8;\r
-parameter me7d8f7 = 47;\r
-input hclk;\r
-input reset_n;\r
-input [doa7062 - 1:0] haddr;\r
-input [oh29c1 - 1:0] hdatain;\r
-input hread_n;\r
-input hwrite_n;\r
-input hcs_n;\r
-output [oh29c1 - 1:0] hdataout;\r
-output hready_n;\r
-output hdataout_en_n;\r
-output yk775cd;\r
-output ale2922;\r
-output qgcb360;\r
-output [icc1896-2:0] ldcd808;\r
-output kq53683;\r
-output tx_en;\r
-output vvcda9b;\r
-output ui6d4df;\r
-output [an8557d:0] vk3f2df;\r
-input aye5ebc;\r
-input gq3baab;\r
-input [rv38312:0] ene2fd7;\r
-input cb17ebd;\r
-input [bn1c73a:0] bldd558;\r
-input ykeaac7;\r
-output wj6023b;\r
-output tu6c047;\r
-output [me7d8f7:0] neda0c6;\r
-output bydf307;\r
-output go59b01;\r
-output vk14915;\r
-output ned0632;\r
-output [sjb1c2a:0] ip60ebc;\r
-output [sjb1c2a:0] ep75e4;\r
-output [sjb1c2a:0] ls3af25;\r
-output [sjb1c2a:0] pfd792a;\r
-output [sjb1c2a:0] cobc957;\r
-output [sjb1c2a:0] xwe4ab9;\r
-output [sjb1c2a:0] tw255ca;\r
-output [sjb1c2a:0] ri2ae53;\r
-output [tjc4b1:0] ba25a85;\r
-\r
-reg xw734fa;\r
-reg gd9a7d3;\r
-reg kdd3e9c;\r
-reg qv9f4e5;\r
-reg [doa7062 - 1:0] kdd3961;\r
-reg [doa7062 - 1:0] cme586a;\r
-reg [doa7062 - 1:0] nr61a85;\r
-reg [doa7062 - 1:0] uv6a174;\r
-reg [tjc4b1:0] ba25a85;\r
-reg hready_n;\r
-reg [oh29c1 - 1:0] hdataout;\r
-reg hdataout_en_n;\r
-reg pu353e5;\r
-reg [oh29c1 - 1:0] fn4f950;\r
-reg [oh29c1 - 1:0] cme5433;\r
-reg [oh29c1 - 1:0] hb50cca;\r
-reg [oh29c1 - 1:0] gd332b3;\r
-reg [oh29c1 - 1:0] jccaceb;\r
-reg [1:0] yk5675a;\r
-reg swb3ad0;\r
-reg [ba96385:0] jceb401;\r
-reg [ba96385:0] tud0056;\r
-reg [ba96385:0] do159c;\r
-reg [ba96385:0] os56710;\r
-reg [ba96385:0] xy9c400;\r
-reg [ba96385:0] uk1001c;\r
-reg [ba96385:0] ou70c;\r
-reg [ba96385:0] nt1c306;\r
-reg rge1837;\r
-reg zzc1ba;\r
-reg [bn1c73a:0] db6eb4;\r
-reg [an8557d:0] ntbad37;\r
-reg [sj12c70:0] uxb4df5;\r
-reg [ay6258e:0] tj37d69;\r
-reg [icc1896:0] wwf5a74;\r
-reg [tj8e155:0] by69d0b;\r
-reg [tj8e155:0] nr742d4;\r
-reg [tj8e155:0] vkb535;\r
-wire [15:0] xj5a9ab;\r
-reg [rv38312:0] wya6af8;\r
-reg [rv38312:0] qvabe0a;\r
-reg zx5f055;\r
-reg gbf82ae;\r
-reg ykc1574;\r
-reg [oh29c1 - 1:0] jp55d00;\r
-reg epae806;\r
-reg hb74035;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg [doa7062 - 1 : 0] en51e07;\r
-reg [oh29c1 - 1 : 0] go781e5;\r
-reg zkc0f28;\r
-reg yz7943;\r
-reg mt3ca1c;\r
-reg yke50e5;\r
-reg [rv38312 : 0] cm4394f;\r
-reg tj1ca78;\r
-reg [bn1c73a : 0] ir29e31;\r
-reg jp4f18c;\r
-reg cm78c67;\r
-reg yxc6339;\r
-reg ou319cd;\r
-reg ls8ce69;\r
-reg su6734b;\r
-reg [doa7062 - 1 : 0] fncd2c5;\r
-reg [doa7062 - 1 : 0] wj4b173;\r
-reg [doa7062 - 1 : 0] lqc5cea;\r
-reg [doa7062 - 1 : 0] dm73a98;\r
-reg wy9d4c2;\r
-reg [oh29c1 - 1 : 0] ww53088;\r
-reg [oh29c1 - 1 : 0] jpc2201;\r
-reg [oh29c1 - 1 : 0] ec8807b;\r
-reg [oh29c1 - 1 : 0] ba1ec6;\r
-reg [oh29c1 - 1 : 0] dz7b199;\r
-reg [1 : 0] hbd8ccf;\r
-reg shc667e;\r
-reg [ba96385 : 0] hq99fad;\r
-reg [ba96385 : 0] nr7eb52;\r
-reg [ba96385 : 0] twad4b1;\r
-reg [ba96385 : 0] ps52c5c;\r
-reg [ba96385 : 0] irb171a;\r
-reg [ba96385 : 0] ea5c6a6;\r
-reg [ba96385 : 0] ie1a98e;\r
-reg [ba96385 : 0] yma6388;\r
-reg aa31c40;\r
-reg fp8e201;\r
-reg [bn1c73a : 0] qi8807e;\r
-reg [an8557d : 0] pu1f86;\r
-reg [sj12c70 : 0] ld7e198;\r
-reg [ay6258e : 0] ba86639;\r
-reg [icc1896 : 0] ks98e5d;\r
-reg [tj8e155 : 0] mt39747;\r
-reg [tj8e155 : 0] jc5d1e0;\r
-reg [tj8e155 : 0] ne4781c;\r
-reg [15 : 0] cb3c0e2;\r
-reg [rv38312 : 0] lf38a1;\r
-reg [rv38312 : 0] she2877;\r
-reg je143bd;\r
-reg ira1deb;\r
-reg doef5c;\r
-reg [oh29c1 - 1 : 0] pubd710;\r
-reg tueb882;\r
-reg ui5c413;\r
-reg [2047:0] ng1e1e0;\r
-wire [53:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 54,gd3c088 = 32'hfdffe30b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign ip60ebc = hq99fad[7:0];\r
-assign ep75e4 = nr7eb52[7:0];\r
-assign ls3af25 = twad4b1[7:0];\r
-assign pfd792a = ps52c5c[7:0];\r
-assign cobc957 = irb171a[7:0];\r
-assign xwe4ab9 = ea5c6a6[7:0];\r
-assign tw255ca = ie1a98e[7:0];\r
-assign ri2ae53 = yma6388[7:0];\r
-assign tx_en = ld7e198[3];\r
-assign vvcda9b = ld7e198[1];\r
-assign tu6c047 = ld7e198[2];\r
-assign neda0c6 = {mt39747,jc5d1e0,ne4781c};\r
-assign vk14915 = ba86639[0];\r
-assign kq53683 = ba86639[1];\r
-assign ui6d4df = ba86639[2];\r
-assign go59b01 = ba86639[3];\r
-assign bydf307 = ba86639[4];\r
-assign wj6023b = ba86639[6];\r
-assign ale2922 = ba86639[7];\r
-assign qgcb360 = ba86639[8];\r
-assign ldcd808 = ks98e5d[13:0];\r
-assign vk3f2df = (pu1f86 < 4) ? 1 : pu1f86 - 3;\r
-assign xj5a9ab = {5'b00000,ou319cd,qi8807e[8:0],su6734b};\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- assign yk775cd = ld7e198[0] ? 1'b0 : ba86639[5]; assign ned0632 = ld7e198[0];\r
-\r
-\r
-\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin kdd3961 <= 8'h0; cme586a <= 8'h0; nr61a85 <= 8'h0; uv6a174 <= 8'h0; zx5f055 <= 1'b1; gbf82ae <= 1'b1; ykc1574 <= 1'b1; jp55d00 <= 0; end else begin kdd3961 <= en51e07; cme586a <= fncd2c5; nr61a85 <= wj4b173; uv6a174 <= lqc5cea; zx5f055 <= mt3ca1c; gbf82ae <= zkc0f28; ykc1574 <= yz7943; jp55d00 <= go781e5; end\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) xw734fa <= 1'b0; else xw734fa <= cm78c67;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) gd9a7d3 <= 1'b0; else gd9a7d3 <= yxc6339;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) kdd3e9c <= 1'b0; else kdd3e9c <= yke50e5;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) qv9f4e5 <= 1'b0; else qv9f4e5 <= ls8ce69;\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) rge1837 <= 1'b0; else rge1837 <= jp4f18c;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) zzc1ba <= 1'b0; else zzc1ba <= aa31c40;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) db6eb4 <= 9'b000000000; else if (fp8e201) db6eb4 <= ir29e31;\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin wya6af8 <= 16'h00; end else if (tj1ca78) begin wya6af8 <= cm4394f; end\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin qvabe0a <= 16'h00; epae806 <= 1'b1; hb74035 <= 1'b1; end else begin qvabe0a <= lf38a1; epae806 <= wy9d4c2; hb74035 <= tueb882; end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin\r
- yk5675a <= 2'b00; jceb401 <= 8'h00; tud0056 <= 8'h00; do159c <= 8'h00; os56710 <= 8'h00; xy9c400 <= 8'h00; uk1001c <= 8'h00; ou70c <= 8'h00; nt1c306 <= 8'h00; ntbad37 <= 5'b01100; uxb4df5 <= 4'h0; tj37d69 <= 8'h0; wwf5a74 <= 16'd1518; by69d0b <= 16'h00; nr742d4 <= 16'h00; vkb535 <= 16'h00; hready_n <= 1'b1; ba25a85 <= 16'h0001; hdataout <= 0; hdataout_en_n <= 1; swb3ad0 <= 1; fn4f950 <= 0; cme5433 <= 0; hb50cca <= 0; gd332b3 <= 0; jccaceb <= 0; pu353e5 <= 1'b1; end else begin hdataout <= ww53088; hdataout_en_n <= shc667e; hready_n <= wy9d4c2; if (!wy9d4c2 || !tueb882) begin pu353e5 <= 1'b1; swb3ad0 <= 1'b1; end else if (!mt3ca1c && !je143bd && !yz7943 && !doef5c && wy9d4c2 && ui5c413 && tueb882) begin pu353e5 <= 1'b0; if (fncd2c5 == 8'h00) begin uxb4df5 <= pubd710; end else if (!ld7e198[3] && !ld7e198[2]) begin case(fncd2c5) 8'h02 : tj37d69[7:0] <= pubd710[7:0]; 8'h04 : wwf5a74[7:0] <= pubd710; 8'h08 : ntbad37[4:0] <= pubd710; 8'h0A : by69d0b[7:0] <= pubd710; 8'h0C : nr742d4[7:0] <= pubd710; 8'h0E : vkb535[7:0] <= pubd710; 8'h22 : jceb401[7:0] <= pubd710; 8'h24 : tud0056[7:0] <= pubd710; 8'h26 : do159c[7:0] <= pubd710; 8'h28 : os56710[7:0] <= pubd710; 8'h2A : xy9c400[7:0] <= pubd710; 8'h2C : uk1001c[7:0] <= pubd710; 8'h2E : ou70c[7:0] <= pubd710; 8'h30 : nt1c306[7:0] <= pubd710; 8'h34 : ba25a85[7:0] <= pubd710; 8'h03 : tj37d69[8] <= pubd710[0]; 8'h05 : wwf5a74[15:8] <= pubd710; 8'h0B : by69d0b[15:8] <= pubd710; 8'h0D : nr742d4[15:8] <= pubd710; 8'h0F : vkb535[15:8] <= pubd710; 8'h35 : ba25a85[15:8] <= pubd710; default : uxb4df5 <= ld7e198; endcase end end else if (!mt3ca1c && !je143bd && !zkc0f28 && !ira1deb && wy9d4c2 && fncd2c5[0] && ui5c413) begin swb3ad0 <= 1'b0; pu353e5 <= 1'b0; case(fncd2c5) 8'h03 : fn4f950 <= {7'h0,ba86639[8]}; 8'h05 : fn4f950 <= ks98e5d[15:8]; 8'h0B : fn4f950 <= mt39747[15:8]; 8'h0D : fn4f950 <= jc5d1e0[15:8]; 8'h0F : fn4f950 <= ne4781c[15:8]; 8'h13 : fn4f950 <= cb3c0e2[15:8]; default : fn4f950 <= 8'h0; endcase end else if (!mt3ca1c && !je143bd && !zkc0f28 && !ira1deb && wy9d4c2 && !fncd2c5[0] && ui5c413) begin swb3ad0 <= 1'b0; pu353e5 <= 1'b0; case(fncd2c5) 8'h00 : fn4f950 <= {4'b0000,ld7e198};\r
-\r
-\r
- 8'h02 : fn4f950 <= ba86639[7:0];\r
-\r
-\r
- 8'h04 : fn4f950 <= ks98e5d[7:0]; 8'h08 : fn4f950 <= {3'b000,pu1f86[4:0]}; 8'h0A : fn4f950 <= mt39747[7:0]; 8'h0C : fn4f950 <= jc5d1e0[7:0]; 8'h0E : fn4f950 <= ne4781c[7:0]; 8'h12 : fn4f950 <= cb3c0e2[7:0]; 8'h22 : fn4f950 <= hq99fad[7:0]; 8'h24 : fn4f950 <= nr7eb52[7:0]; 8'h26 : fn4f950 <= twad4b1[7:0]; 8'h28 : fn4f950 <= ps52c5c[7:0]; 8'h2A : fn4f950 <= irb171a[7:0]; 8'h2C : fn4f950 <= ea5c6a6[7:0]; 8'h2E : fn4f950 <= ie1a98e[7:0]; 8'h30 : fn4f950 <= yma6388[7:0]; 8'h32 : fn4f950 <= she2877[7:0]; 8'h34 : fn4f950 <= ba25a85[7:0]; default : fn4f950 <= 8'h0; endcase end end\r
-\r
-\r
-\r
-\r
-\r
-always@* begin en51e07<={haddr>>1,mef0f02[0]};go781e5<={hdatain>>1,mef0f02[1]};zkc0f28<=mef0f02[2];yz7943<=mef0f02[3];mt3ca1c<=mef0f02[4];yke50e5<=mef0f02[5];cm4394f<={ene2fd7>>1,mef0f02[6]};tj1ca78<=mef0f02[7];ir29e31<={bldd558>>1,mef0f02[8]};jp4f18c<=mef0f02[9];cm78c67<=mef0f02[10];yxc6339<=mef0f02[11];ou319cd<=mef0f02[12];ls8ce69<=mef0f02[13];su6734b<=mef0f02[14];fncd2c5<={kdd3961>>1,mef0f02[15]};wj4b173<={cme586a>>1,mef0f02[16]};lqc5cea<={nr61a85>>1,mef0f02[17]};dm73a98<={uv6a174>>1,mef0f02[18]};wy9d4c2<=mef0f02[19];ww53088<={fn4f950>>1,mef0f02[20]};jpc2201<={cme5433>>1,mef0f02[21]};ec8807b<={hb50cca>>1,mef0f02[22]};ba1ec6<={gd332b3>>1,mef0f02[23]};dz7b199<={jccaceb>>1,mef0f02[24]};hbd8ccf<={yk5675a>>1,mef0f02[25]};shc667e<=mef0f02[26];hq99fad<={jceb401>>1,mef0f02[27]};nr7eb52<={tud0056>>1,mef0f02[28]};twad4b1<={do159c>>1,mef0f02[29]};ps52c5c<={os56710>>1,mef0f02[30]};irb171a<={xy9c400>>1,mef0f02[31]};ea5c6a6<={uk1001c>>1,mef0f02[32]};ie1a98e<={ou70c>>1,mef0f02[33]};yma6388<={nt1c306>>1,mef0f02[34]};aa31c40<=mef0f02[35];fp8e201<=mef0f02[36];qi8807e<={db6eb4>>1,mef0f02[37]};pu1f86<={ntbad37>>1,mef0f02[38]};ld7e198<={uxb4df5>>1,mef0f02[39]};ba86639<={tj37d69>>1,mef0f02[40]};ks98e5d<={wwf5a74>>1,mef0f02[41]};mt39747<={by69d0b>>1,mef0f02[42]};jc5d1e0<={nr742d4>>1,mef0f02[43]};ne4781c<={vkb535>>1,mef0f02[44]};cb3c0e2<={xj5a9ab>>1,mef0f02[45]};lf38a1<={wya6af8>>1,mef0f02[46]};she2877<={qvabe0a>>1,mef0f02[47]};je143bd<=mef0f02[48];ira1deb<=mef0f02[49];doef5c<=mef0f02[50];pubd710<={jp55d00>>1,mef0f02[51]};tueb882<=mef0f02[52];ui5c413<=mef0f02[53];end\r
-always@* begin ng1e1e0[2047]<=hdatain[0];ng1e1e0[2046]<=hread_n;ng1e1e0[2044]<=hwrite_n;ng1e1e0[2040]<=hcs_n;ng1e1e0[2032]<=aye5ebc;ng1e1e0[2016]<=ene2fd7[0];ng1e1e0[1985]<=cb17ebd;ng1e1e0[1925]<=wwf5a74[0];ng1e1e0[1922]<=bldd558[0];ng1e1e0[1802]<=by69d0b[0];ng1e1e0[1796]<=ykeaac7;ng1e1e0[1556]<=nr742d4[0];ng1e1e0[1544]<=gq3baab;ng1e1e0[1505]<=uxb4df5[0];ng1e1e0[1324]<=gbf82ae;ng1e1e0[1316]<=jceb401[0];ng1e1e0[1200]<=jp55d00[0];ng1e1e0[1169]<=do159c[0];ng1e1e0[1163]<=uk1001c[0];ng1e1e0[1118]<=rge1837;ng1e1e0[1106]<=gd332b3[0];ng1e1e0[1065]<=vkb535[0];ng1e1e0[1041]<=nr61a85[0];ng1e1e0[1040]<=xw734fa;ng1e1e0[1023]<=haddr[0];ng1e1e0[962]<=tj37d69[0];ng1e1e0[752]<=ntbad37[0];ng1e1e0[707]<=hb74035;ng1e1e0[662]<=zx5f055;ng1e1e0[658]<=swb3ad0;ng1e1e0[600]<=ykc1574;ng1e1e0[584]<=tud0056[0];ng1e1e0[581]<=xy9c400[0];ng1e1e0[559]<=nt1c306[0];ng1e1e0[553]<=hb50cca[0];ng1e1e0[520]<=cme586a[0];ng1e1e0[376]<=db6eb4[0];ng1e1e0[353]<=epae806;ng1e1e0[331]<=qvabe0a[0];ng1e1e0[329]<=yk5675a[0];ng1e1e0[290]<=os56710[0];ng1e1e0[279]<=ou70c[0];ng1e1e0[276]<=cme5433[0];ng1e1e0[260]<=kdd3961[0];ng1e1e0[188]<=zzc1ba;ng1e1e0[165]<=wya6af8[0];ng1e1e0[164]<=jccaceb[0];ng1e1e0[138]<=fn4f950[0];ng1e1e0[130]<=qv9f4e5;ng1e1e0[82]<=xj5a9ab[0];ng1e1e0[69]<=pu353e5;ng1e1e0[65]<=kdd3e9c;ng1e1e0[34]<=uv6a174[0];ng1e1e0[32]<=gd9a7d3;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module mefacfd(\r
-gd18c9b, \r
-kdc64dc, \r
-jr326e5, \r
-xy9372f, \r
-nt9b97a, \r
-shdcbd7, \r
-reset_n, \r
-mdc, \r
-mdi, \r
-mdo, \r
-mdio_en \r
-);\r
-localparam bn22331 = 14'b00000000000001;\r
-localparam zm1198e = 14'b00000000000010;\r
-localparam ba8cc72 = 14'b00000000000100;\r
-localparam rg66393 = 14'b00000000001000;\r
-localparam wy31c9a = 14'b00000000010000;\r
-localparam zz8e4d1 = 14'b00000000100000;\r
-localparam ay7268f = 14'b00000001000000;\r
-localparam do93479 = 14'b00000010000000;\r
-localparam ir9a3ca = 14'b00000100000000;\r
-localparam ykd1e54 = 14'b00001000000000;\r
-localparam ux8f2a0 = 14'b00010000000000;\r
-localparam ne79505 = 14'b00100000000000;\r
-localparam dmca82a = 14'b01000000000000;\r
-localparam en54152 = 14'b10000000000000;\r
-parameter vxa0a95 = 10;\r
-parameter co54ae = 15;\r
-parameter ri2a570 = 4;\r
-parameter by52b82 = 2;\r
-parameter wl95c13 = 3;\r
-parameter epae09c = 13;\r
-input reset_n;\r
-input mdc;\r
-input [vxa0a95:0] gd18c9b;\r
-input [co54ae:0] kdc64dc;\r
-input xy9372f;\r
-input mdi;\r
-output mdo;\r
-output mdio_en;\r
-output shdcbd7;\r
-output nt9b97a;\r
-output [co54ae:0] jr326e5;\r
-reg [co54ae:0] jr326e5;\r
-reg nt9b97a;\r
-reg mdio_en;\r
-reg lf2de5b;\r
-reg mdo;\r
-reg [co54ae:0] iccb7a2;\r
-reg [co54ae:0] kqde88d;\r
-reg [co54ae:0] vka234a;\r
-reg [ri2a570:0] gq8d292;\r
-reg [by52b82:0] jp4a483;\r
-reg [by52b82:0] gq920fa;\r
-reg [wl95c13:0] je83e85;\r
-reg [wl95c13:0] qgfa150;\r
-reg [epae09c:0] yz8540a;\r
-reg [epae09c:0] hb502a2;\r
-reg tj81517;\r
-reg wya8be;\r
-reg al545f0;\r
-reg nga2f85;\r
-reg wl17c2b;\r
-reg shdcbd7;\r
-reg [vxa0a95 : 0] sj85769;\r
-reg [co54ae : 0] ho5da61;\r
-reg shed30a;\r
-reg ne69855;\r
-reg ui4c2aa;\r
-reg [co54ae : 0] ecaa87;\r
-reg [co54ae : 0] phaa1c7;\r
-reg [co54ae : 0] ie871f6;\r
-reg [ri2a570 : 0] fnc7d8f;\r
-reg [by52b82 : 0] nrf63f0;\r
-reg [by52b82 : 0] kf8fc3d;\r
-reg [wl95c13 : 0] ayf0f67;\r
-reg [wl95c13 : 0] tj3d9c8;\r
-reg [epae09c : 0] ic6723e;\r
-reg [epae09c : 0] ldc8f84;\r
-reg tu47c27;\r
-reg wy3e13a;\r
-reg ayf09d1;\r
-reg fp84e89;\r
-reg vx2744f;\r
-reg [2047:0] ng1e1e0;\r
-wire [19:0] mef0f02;\r
-\r
-localparam uk87811 = 20,gd3c088 = 32'hfdffd28b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin nga2f85 <= 1'b0; end else begin nga2f85 <= shed30a; end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin wl17c2b <= 1'b0; end else begin wl17c2b <= fp84e89; end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin al545f0 <= 1'b0; tj81517 <= 1'b0; wya8be <= 1'b0; vka234a <= 16'h0; kqde88d <= 16'h0; end else if (nt9b97a) begin al545f0 <= 1'b0; tj81517 <= 1'b0; wya8be <= 1'b0; end else if (vx2744f && !ayf09d1) begin al545f0 <= 1'b1; vka234a <= {3'b000,sj85769,2'b00}; kqde88d <= ho5da61; if (sj85769[10]) tj81517 <= 1'b1; else wya8be <= 1'b1; end\r
-\r
-\r
-always @(negedge mdc or negedge reset_n) begin if (!reset_n) begin mdo <= 1'b0; end else begin mdo <= ui4c2aa; end\r
-end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin gq8d292 <= 5'b00000; lf2de5b <= 1'b0; mdio_en <= 1'b0; nt9b97a <= 1'b0; jr326e5 <= 16'h0; iccb7a2 <= 16'h0; jp4a483 <= 3'b000; gq920fa <= 3'b110; je83e85 <= 4'b1011; qgfa150 <= 4'b1111; end else if (ic6723e == bn22331) begin nt9b97a <= 1'b0; gq8d292 <= 5'b00000; lf2de5b <= 1'b0; mdio_en <= 1'b0; jp4a483 <= 3'b000; gq920fa <= 3'b110; je83e85 <= 4'b1011; qgfa150 <= 4'b1111; end else if (ic6723e == zm1198e) begin gq8d292 <= fnc7d8f + 5'b00001; lf2de5b <= 1'b1; mdio_en <= 1'b1; end else if (ic6723e == rg66393) begin gq8d292 <= 5'b00000; lf2de5b <= 1'b1; mdio_en <= 1'b1; end else if (ic6723e == ba8cc72) begin gq8d292 <= 5'b00000; lf2de5b <= 1'b0; mdio_en <= 1'b1; end else if (ic6723e == ykd1e54) begin if (tu47c27) begin mdio_en <= 1'b1; lf2de5b <= 1'b1; end else begin mdio_en <= 1'b0; lf2de5b <= 1'b0; end end else if (ic6723e == wy31c9a) begin lf2de5b <= 1'b0; mdio_en <= 1'b1; end else if (ic6723e == zz8e4d1) begin lf2de5b <= 1'b1; mdio_en <= 1'b1; end else if (ic6723e == ir9a3ca) begin if (tu47c27) begin lf2de5b <= 1'b0; mdio_en <= 1'b1; end else lf2de5b <= 1'b0; end else if (ic6723e == ne79505) begin if (tu47c27) begin lf2de5b <= phaa1c7[tj3d9c8]; qgfa150 <= tj3d9c8 - 4'b0001; mdio_en <= 1'b1; end else begin lf2de5b <= 1'b0; mdio_en <= 1'b0; iccb7a2[tj3d9c8] <= ne69855; qgfa150 <= tj3d9c8 - 4'b0001; end gq8d292 <= fnc7d8f + 5'b00001; end else if (ic6723e == ay7268f) begin mdio_en <= 1'b1; lf2de5b <= ie871f6[ayf0f67]; je83e85 <= ayf0f67 - 4'b0001; gq8d292 <= fnc7d8f + 5'b00001; end else if (ic6723e == do93479) begin mdio_en <= 1'b1; lf2de5b <= ie871f6[kf8fc3d]; gq920fa <= kf8fc3d - 3'b001; jp4a483 <= nrf63f0 + 3'b001; gq8d292 <= 5'b00000; end else if (ic6723e == dmca82a) begin mdio_en <= 1'b0; lf2de5b <= 1'b0; gq8d292 <= 5'b00000; nt9b97a <= 1'b1; jr326e5 <= ecaa87; end else if (ic6723e == en54152) begin mdio_en <= 1'b0; lf2de5b <= 1'b0; gq8d292 <= 5'b00000; nt9b97a <= 1'b1; jr326e5 <= ecaa87; end\r
-\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin shdcbd7 <= 1'b1; end else if (ic6723e == bn22331 && !vx2744f) begin shdcbd7 <= 1'b1; end else begin shdcbd7 <= 1'b0; end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin yz8540a <= bn22331; end else begin yz8540a <= ldc8f84; end\r
-always @(ic6723e or tu47c27 or wy3e13a or fnc7d8f or nrf63f0) begin case(ic6723e) bn22331 : begin if (tu47c27 || wy3e13a) begin hb502a2 = zm1198e; end else begin hb502a2 = bn22331; end end zm1198e : begin if (fnc7d8f < 5'b11111) begin hb502a2 = zm1198e; end else begin hb502a2 = ba8cc72; end end ba8cc72 : begin hb502a2 = rg66393; end rg66393 : begin if (tu47c27) begin hb502a2 = wy31c9a; end else begin hb502a2 = zz8e4d1; end end wy31c9a : begin if (tu47c27) begin hb502a2 = zz8e4d1; end else begin hb502a2 = ay7268f; end end zz8e4d1 : begin if (wy3e13a) begin hb502a2 = wy31c9a; end else begin hb502a2 = ay7268f; end end ay7268f : begin if (fnc7d8f < 5'b00100) begin hb502a2 = ay7268f; end else begin hb502a2 = do93479; end end do93479 : begin if (nrf63f0 < 3'b100) begin hb502a2 = do93479; end else begin hb502a2 = ykd1e54; end end\r
- ykd1e54 : begin hb502a2 = ir9a3ca; end ir9a3ca : begin if (tu47c27) hb502a2 = ne79505; else hb502a2 = ux8f2a0; end ux8f2a0 : begin hb502a2 = ne79505; end\r
- ne79505 : begin if (fnc7d8f < 5'b01111) begin hb502a2 = ne79505; end else begin hb502a2 = dmca82a; end end dmca82a : begin hb502a2 = en54152; end\r
- en54152 : begin hb502a2 = bn22331; end default : begin hb502a2 = bn22331; end endcase end\r
-always@* begin sj85769<={gd18c9b>>1,mef0f02[0]};ho5da61<={kdc64dc>>1,mef0f02[1]};shed30a<=mef0f02[2];ne69855<=mef0f02[3];ui4c2aa<=mef0f02[4];ecaa87<={iccb7a2>>1,mef0f02[5]};phaa1c7<={kqde88d>>1,mef0f02[6]};ie871f6<={vka234a>>1,mef0f02[7]};fnc7d8f<={gq8d292>>1,mef0f02[8]};nrf63f0<={jp4a483>>1,mef0f02[9]};kf8fc3d<={gq920fa>>1,mef0f02[10]};ayf0f67<={je83e85>>1,mef0f02[11]};tj3d9c8<={qgfa150>>1,mef0f02[12]};ic6723e<={yz8540a>>1,mef0f02[13]};ldc8f84<={hb502a2>>1,mef0f02[14]};tu47c27<=mef0f02[15];wy3e13a<=mef0f02[16];ayf09d1<=mef0f02[17];fp84e89<=mef0f02[18];vx2744f<=mef0f02[19];end\r
-always@* begin ng1e1e0[2047]<=kdc64dc[0];ng1e1e0[2046]<=xy9372f;ng1e1e0[2044]<=mdi;ng1e1e0[2040]<=lf2de5b;ng1e1e0[2032]<=iccb7a2[0];ng1e1e0[2017]<=kqde88d[0];ng1e1e0[1987]<=vka234a[0];ng1e1e0[1926]<=gq8d292[0];ng1e1e0[1804]<=jp4a483[0];ng1e1e0[1614]<=wya8be;ng1e1e0[1561]<=gq920fa[0];ng1e1e0[1180]<=al545f0;ng1e1e0[1074]<=je83e85[0];ng1e1e0[1023]<=gd18c9b[0];ng1e1e0[807]<=tj81517;ng1e1e0[625]<=wl17c2b;ng1e1e0[403]<=hb502a2[0];ng1e1e0[312]<=nga2f85;ng1e1e0[201]<=yz8540a[0];ng1e1e0[100]<=qgfa150[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ksbcf57(\r
-\r
- \r
-txmac_clk, \r
-rxmac_clk, \r
-reset_n, \r
-rxmac_clk_en, \r
-txmac_clk_en, \r
-\r
- \r
-fncdc51, \r
-zx6e28f, \r
-pf7147e, \r
-\r
- \r
-lsb51f, \r
-pf616a3, \r
-ks10d54, \r
-fa6c2d4, \r
-ls86aa0, \r
-vv5a8fb, \r
-\r
- \r
-ksac9b7, \r
-zx64db8, \r
-\r
- crs, \r
- col, \r
-\r
-\r
- \r
-txd_pos, \r
- \r
- \r
-txd_neg, \r
- \r
-tx_en, \r
-tx_er, \r
-\r
-\r
-ned0632, \r
-kq53683, \r
-\r
- \r
-rx_dv_pos, \r
-rx_dv_neg, \r
-rx_er_pos, \r
-rx_er_neg, \r
-rxd_pos, \r
-rxd_neg \r
-);\r
-parameter wy9ddd9 = 8;\r
-parameter hoeeec8 = 8;\r
-parameter cm77643 = 4;\r
-input txmac_clk;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input txmac_clk_en;\r
-input [wy9ddd9-1:0] fncdc51;\r
-input zx6e28f;\r
-input pf7147e;\r
-output lsb51f;\r
-output pf616a3;\r
-output ks10d54;\r
-output fa6c2d4;\r
-output [wy9ddd9-1:0] ls86aa0;\r
-output ksac9b7;\r
-output zx64db8;\r
-input ned0632;\r
-input kq53683;\r
-\r
-input col;\r
-input crs;\r
-\r
-output [7:0] txd_pos;\r
-output [3:0] txd_neg;\r
-output tx_en;\r
-output tx_er;\r
-output vv5a8fb;\r
-input rx_dv_pos;\r
-input rx_dv_neg;\r
-input rx_er_pos;\r
-input rx_er_neg;\r
-input [7:0] rxd_pos;\r
-input [3:0] rxd_neg;\r
-reg qv9f880;\r
-reg rtfc405;\r
-reg kde202e;\r
-reg lsb51f ;\r
-reg cb80ba1;\r
-reg uk5d0d;\r
-reg ie2e869 ;\r
-reg nr74349 ;\r
-reg ana1a4e ;\r
-reg pf616a3 ;\r
-reg tu693a4;\r
-reg ui49d23;\r
-reg [wy9ddd9-1:0] pf748cc;\r
-reg [wy9ddd9-1:0] an2333d;\r
-reg [wy9ddd9-1:0] kdccf66;\r
-reg [wy9ddd9-1:0] ls86aa0 ;\r
-reg [wy9ddd9-1:0] dm66a7e;\r
-reg [wy9ddd9-1:0] uka9f9a;\r
-reg fa6c2d4 ;\r
-reg pf7e686 ;\r
-reg zxf3437 ;\r
-reg wl9a1bf ;\r
-reg ks10d54 ;\r
-reg ng86fe2;\r
-reg db37f12;\r
-reg [7:0] txd_pos;\r
-reg [3:0] txd_neg;\r
-reg tx_en;\r
-reg tx_er;\r
-reg vk96da5;\r
-reg ymb6d2b;\r
-reg ieb6958;\r
-reg vv5a8fb ;\r
-reg xla5605;\r
-reg wy2b02f;\r
-reg [wy9ddd9-1:0] hoc0bc3;\r
-reg ie5e1b;\r
-reg ri2f0d9;\r
-reg ay786ca;\r
-reg enc3650;\r
-reg ls1b285;\r
-reg yxd942a;\r
-reg byca155;\r
-reg th50aab;\r
-reg [cm77643-1:0] xy2aaf4;\r
-reg dz557a3;\r
-reg [hoeeec8-1:0] sh5e8fd;\r
-reg [3:0] faf47ed;\r
-reg [3:0] mga3f6a;\r
-reg mg1fb51;\r
-reg kdfda89;\r
-reg kded44d;\r
-reg cz6a26d;\r
-reg mr5136c;\r
-reg fc89b65;\r
-reg xw4db2b;\r
-reg kq6d95b;\r
-reg xw6cad8;\r
-wire ksac9b7;\r
-wire zx64db8;\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg [wy9ddd9 - 1 : 0] fnd8544;\r
-reg hbc2a27;\r
-reg ec1513e;\r
-reg twa89f1;\r
-reg sh44f8a;\r
-reg vx27c55;\r
-reg gq3e2af;\r
-reg dmf1579;\r
-reg yz8abca;\r
-reg [7 : 0] rt55e54;\r
-reg [3 : 0] rvaf2a6;\r
-reg by79536;\r
-reg lqca9b2;\r
-reg qt54d92;\r
-reg gqa6c94;\r
-reg sj364a1;\r
-reg rib250d;\r
-reg ie9286b;\r
-reg bn94359;\r
-reg wla1acf;\r
-reg mtd67c;\r
-reg [wy9ddd9 - 1 : 0] me59f26;\r
-reg [wy9ddd9 - 1 : 0] tu7c982;\r
-reg [wy9ddd9 - 1 : 0] qv2609a;\r
-reg [wy9ddd9 - 1 : 0] ou826a2;\r
-reg [wy9ddd9 - 1 : 0] an9a88e;\r
-reg qgd4475;\r
-reg lsa23a9;\r
-reg ba11d4a;\r
-reg tj8ea52;\r
-reg cz75296;\r
-reg oua94b4;\r
-reg jp4a5a1;\r
-reg dm52d0f;\r
-reg ls9687b;\r
-reg yzb43db;\r
-reg [wy9ddd9 - 1 : 0] swf6e4;\r
-reg zx7b721;\r
-reg ykdb90f;\r
-reg czdc879;\r
-reg dme43cc;\r
-reg sw21e63;\r
-reg ecf318;\r
-reg ps798c1;\r
-reg yxcc60b;\r
-reg [cm77643 - 1 : 0] ir182e2;\r
-reg cmc1715;\r
-reg [hoeeec8 - 1 : 0] kq5c542;\r
-reg [3 : 0] uve2a11;\r
-reg [3 : 0] ym1508d;\r
-reg xya8469;\r
-reg by4234b;\r
-reg ng11a5b;\r
-reg ie8d2da;\r
-reg rg696d0;\r
-reg gb4b683;\r
-reg gb5b41d;\r
-reg jcda0ec;\r
-reg hod0762;\r
-reg [2047:0] ng1e1e0;\r
-wire [58:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 59,gd3c088 = 32'hfdffc70b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
- assign zx64db8 = col; assign ksac9b7 = crs;\r
-\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin xy2aaf4 <= 4'b0000; dz557a3 <= 1'b1; end else if (rxmac_clk_en) begin if (!cmc1715 && !xya8469) begin if (ir182e2 < 4'b1011) begin xy2aaf4 <= ir182e2 + 4'b0001; end else begin xy2aaf4 <= 4'b0000; dz557a3 <= 1'b1; end end else if (by4234b) begin xy2aaf4 <= 4'b0000; dz557a3 <= 1'b0; end end\r
-end\r
-\r
-\r
- always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin ls1b285 <= 1'b0; yxd942a <= 1'b0; end else if (rxmac_clk_en) begin ls1b285 <= 1'b1; yxd942a <= sw21e63; end end\r
-\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin byca155 <= 1'b0; th50aab <= 1'b0; end else if (rxmac_clk_en) begin byca155 <= sh44f8a; th50aab <= ps798c1; end\r
-end\r
-\r
-\r
- always @(posedge txmac_clk or negedge reset_n) begin if (!reset_n) begin ay786ca <= 1'b0; enc3650 <= 1'b0; end else if (txmac_clk_en) begin ay786ca <= 1'b1; enc3650 <= czdc879; end end\r
-\r
-\r
-\r
-\r
-always @(negedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin kded44d <= 0; cz6a26d <= 0; fc89b65 <= 0; xw4db2b <= 0; faf47ed <= 0; mga3f6a <= 0; end else if (rxmac_clk_en) begin kded44d <= gq3e2af; cz6a26d <= ng11a5b; fc89b65 <= yz8abca; xw4db2b <= gb4b683; faf47ed <= rvaf2a6; mga3f6a <= uve2a11; end\r
-end\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin mg1fb51 <= 0; kdfda89 <= 0; mr5136c <= 0; sh5e8fd <= 0; end else if (rxmac_clk_en) begin mg1fb51 <= vx27c55; kdfda89 <= xya8469; mr5136c <= dmf1579; sh5e8fd <= rt55e54; end\r
-end\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin kq6d95b <= 0; xw6cad8 <= 0; pf748cc <= 0; an2333d <= 0; kdccf66 <= 0; ls86aa0 <= 0; dm66a7e <= 0; uka9f9a <= 0; fa6c2d4 <= 0; pf7e686 <= 0; zxf3437 <= 0; wl9a1bf <= 0; ks10d54 <= 0; ng86fe2 <= 0; db37f12 <= 0; ie2e869 <= 0; nr74349 <= 0; ana1a4e <= 0; pf616a3 <= 0; tu693a4 <= 0; ui49d23 <= 0; qv9f880 <= 0; rtfc405 <= 0; kde202e <= 0; lsb51f <= 0; cb80ba1 <= 0; uk5d0d <= 0; vk96da5 <= 0; ymb6d2b <= 0; ieb6958 <= 0; vv5a8fb <= 0; wy2b02f <= 0; xla5605 <= 0; end else if (rxmac_clk_en) begin ls86aa0 <= qv2609a; ks10d54 <= ba11d4a; pf616a3 <= bn94359; lsb51f <= qt54d92; vv5a8fb <= dm52d0f; kdccf66 <= tu7c982; wl9a1bf <= lsa23a9; ana1a4e <= ie9286b; kde202e <= lqca9b2; ieb6958 <= jp4a5a1; an2333d <= me59f26; zxf3437 <= qgd4475; nr74349 <= rib250d; rtfc405 <= by79536; ymb6d2b <= oua94b4; if (ecf318) begin pf748cc <= ou826a2; pf7e686 <= tj8ea52; ie2e869 <= wla1acf; qv9f880 <= gqa6c94; vk96da5 <= ls9687b; if (yxcc60b) begin fa6c2d4 <= tj8ea52 & ks10d54; end else begin fa6c2d4 <= ks10d54; end end else begin pf748cc <= an9a88e; pf7e686 <= cz75296; ie2e869 <= mtd67c; qv9f880 <= sj364a1; vk96da5 <= yzb43db; if (yxcc60b) begin fa6c2d4 <= cz75296 & ks10d54; end else begin fa6c2d4 <= ks10d54; end end ng86fe2 <= xya8469; dm66a7e <= kq5c542; tu693a4 <= rg696d0; cb80ba1 <= 0; if ((by4234b == 0) && (xya8469 == 1)) begin xla5605 <= ~cmc1715; end if ((by4234b == 0) && (ie8d2da == 1)) begin kq6d95b <= 0; db37f12 <= xya8469 & ie8d2da; uka9f9a <= {kq5c542[3:0], ym1508d}; ui49d23 <= rg696d0 | gb5b41d; wy2b02f <= ~cmc1715; if ({kq5c542[3:0], ym1508d} == 8'hd5) begin xw6cad8 <= 0; end else begin xw6cad8 <= 1; end end else if ((ie8d2da == 0) && (xya8469 == 1)) begin kq6d95b <= 1; db37f12 <= ng11a5b & xya8469; uka9f9a <= {uve2a11, kq5c542[3:0]}; ui49d23 <= gb4b683 | rg696d0; wy2b02f <= ~cmc1715; if ({uve2a11, kq5c542[3:0]} == 8'hd5) begin xw6cad8 <= 0; end else begin xw6cad8 <= 1; end end else if ((hod0762 == 1) && ({kq5c542[3:0], ym1508d} == 8'hd5)) begin kq6d95b <= 0; uka9f9a <= {kq5c542[3:0], ym1508d}; xw6cad8 <= 0; end else if ((hod0762 == 1) && ({uve2a11, kq5c542[3:0]} == 8'hd5)) begin kq6d95b <= 1; uka9f9a <= {uve2a11, kq5c542[3:0]}; xw6cad8 <= 0; end else if (jcda0ec == 0) begin db37f12 <= xya8469 & ie8d2da; uka9f9a <= {kq5c542[3:0], ym1508d}; ui49d23 <= rg696d0 | gb5b41d; if (cz75296 == 1) begin uk5d0d <= xya8469 != ie8d2da; end end else if (jcda0ec == 1) begin db37f12 <= ng11a5b & xya8469; uka9f9a <= {uve2a11, kq5c542[3:0]}; ui49d23 <= gb4b683 | rg696d0; if (cz75296 == 1) begin uk5d0d <= ng11a5b != xya8469; end end end\r
-end\r
-\r
-\r
-always @(posedge txmac_clk or negedge reset_n) begin if (!reset_n) begin hoc0bc3 <= 0; ie5e1b <= 0; end else if (txmac_clk_en) begin if (ec1513e) begin hoc0bc3 <= fnd8544; ie5e1b <= hbc2a27; end else begin hoc0bc3 <= 0; ie5e1b <= 0; end end\r
-end\r
-\r
-\r
-always @(posedge txmac_clk or negedge reset_n) begin if (!reset_n) begin ri2f0d9 <= 1'b0; end else if (txmac_clk_en) begin ri2f0d9 <= ec1513e; end\r
-end\r
-\r
-\r
-always @(dme43cc or ykdb90f or swf6e4 or zx7b721) begin casex({dme43cc, ykdb90f}) 2'bx0 : begin txd_pos[7:0] = 0; txd_neg[3:0] = 0; tx_er = 0; tx_en = 0; end 2'b11 : begin txd_pos[7:0] = swf6e4[7:0]; txd_neg[3:0] = swf6e4[3:0]; tx_er = zx7b721; tx_en = ykdb90f; end 2'b01 : begin txd_pos[7:0] = {4'h0, swf6e4[3:0]}; txd_neg[3:0] = swf6e4[7:4]; tx_er = zx7b721; tx_en = ykdb90f; end default : begin txd_pos[7:0] = 0; txd_neg[3:0] = 0; tx_er = 0; tx_en = 0; end endcase\r
-end\r
-always@* begin fnd8544<={fncdc51>>1,mef0f02[0]};hbc2a27<=mef0f02[1];ec1513e<=mef0f02[2];twa89f1<=mef0f02[3];sh44f8a<=mef0f02[4];vx27c55<=mef0f02[5];gq3e2af<=mef0f02[6];dmf1579<=mef0f02[7];yz8abca<=mef0f02[8];rt55e54<={rxd_pos>>1,mef0f02[9]};rvaf2a6<={rxd_neg>>1,mef0f02[10]};by79536<=mef0f02[11];lqca9b2<=mef0f02[12];qt54d92<=mef0f02[13];gqa6c94<=mef0f02[14];sj364a1<=mef0f02[15];rib250d<=mef0f02[16];ie9286b<=mef0f02[17];bn94359<=mef0f02[18];wla1acf<=mef0f02[19];mtd67c<=mef0f02[20];me59f26<={pf748cc>>1,mef0f02[21]};tu7c982<={an2333d>>1,mef0f02[22]};qv2609a<={kdccf66>>1,mef0f02[23]};ou826a2<={dm66a7e>>1,mef0f02[24]};an9a88e<={uka9f9a>>1,mef0f02[25]};qgd4475<=mef0f02[26];lsa23a9<=mef0f02[27];ba11d4a<=mef0f02[28];tj8ea52<=mef0f02[29];cz75296<=mef0f02[30];oua94b4<=mef0f02[31];jp4a5a1<=mef0f02[32];dm52d0f<=mef0f02[33];ls9687b<=mef0f02[34];yzb43db<=mef0f02[35];swf6e4<={hoc0bc3>>1,mef0f02[36]};zx7b721<=mef0f02[37];ykdb90f<=mef0f02[38];czdc879<=mef0f02[39];dme43cc<=mef0f02[40];sw21e63<=mef0f02[41];ecf318<=mef0f02[42];ps798c1<=mef0f02[43];yxcc60b<=mef0f02[44];ir182e2<={xy2aaf4>>1,mef0f02[45]};cmc1715<=mef0f02[46];kq5c542<={sh5e8fd>>1,mef0f02[47]};uve2a11<={faf47ed>>1,mef0f02[48]};ym1508d<={mga3f6a>>1,mef0f02[49]};xya8469<=mef0f02[50];by4234b<=mef0f02[51];ng11a5b<=mef0f02[52];ie8d2da<=mef0f02[53];rg696d0<=mef0f02[54];gb4b683<=mef0f02[55];gb5b41d<=mef0f02[56];jcda0ec<=mef0f02[57];hod0762<=mef0f02[58];end\r
-always@* begin ng1e1e0[2047]<=zx6e28f;ng1e1e0[2046]<=pf7147e;ng1e1e0[2044]<=ned0632;ng1e1e0[2040]<=kq53683;ng1e1e0[2032]<=rx_dv_pos;ng1e1e0[2016]<=rx_dv_neg;ng1e1e0[1985]<=rx_er_pos;ng1e1e0[1922]<=rx_er_neg;ng1e1e0[1867]<=tu693a4;ng1e1e0[1804]<=sh5e8fd[0];ng1e1e0[1797]<=rxd_pos[0];ng1e1e0[1761]<=th50aab;ng1e1e0[1686]<=ui49d23;ng1e1e0[1623]<=mr5136c;ng1e1e0[1561]<=faf47ed[0];ng1e1e0[1558]<=wl9a1bf;ng1e1e0[1547]<=rxd_neg[0];ng1e1e0[1542]<=hoc0bc3[0];ng1e1e0[1490]<=nr74349;ng1e1e0[1475]<=xy2aaf4[0];ng1e1e0[1413]<=pf7e686;ng1e1e0[1409]<=xla5605;ng1e1e0[1400]<=xw6cad8;ng1e1e0[1324]<=pf748cc[0];ng1e1e0[1200]<=kdccf66[0];ng1e1e0[1199]<=fc89b65;ng1e1e0[1074]<=mga3f6a[0];ng1e1e0[1068]<=ng86fe2;ng1e1e0[1047]<=qv9f880;ng1e1e0[1037]<=ie5e1b;ng1e1e0[1023]<=fncdc51[0];ng1e1e0[933]<=ana1a4e;ng1e1e0[902]<=dz557a3;ng1e1e0[880]<=byca155;ng1e1e0[811]<=cz6a26d;ng1e1e0[779]<=zxf3437;ng1e1e0[771]<=wy2b02f;ng1e1e0[745]<=ie2e869;ng1e1e0[706]<=uka9f9a[0];ng1e1e0[704]<=ieb6958;ng1e1e0[700]<=kq6d95b;ng1e1e0[600]<=an2333d[0];ng1e1e0[440]<=yxd942a;ng1e1e0[405]<=kded44d;ng1e1e0[372]<=uk5d0d;ng1e1e0[353]<=dm66a7e[0];ng1e1e0[352]<=ymb6d2b;ng1e1e0[350]<=xw4db2b;ng1e1e0[220]<=ls1b285;ng1e1e0[202]<=kdfda89;ng1e1e0[186]<=cb80ba1;ng1e1e0[176]<=vk96da5;ng1e1e0[110]<=enc3650;ng1e1e0[101]<=mg1fb51;ng1e1e0[93]<=kde202e;ng1e1e0[88]<=db37f12;ng1e1e0[55]<=ay786ca;ng1e1e0[46]<=rtfc405;ng1e1e0[27]<=ri2f0d9;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module tsmac34 (\r
-\r
- \r
- hclk,\r
- txmac_clk,\r
- rxmac_clk,\r
- reset_n,\r
-\r
- txmac_clk_en,\r
- rxmac_clk_en,\r
-\r
-\r
- \r
- rxd,\r
- rx_dv,\r
- rx_er,\r
-\r
- col,\r
- crs,\r
-\r
- \r
- haddr,\r
- hdatain,\r
- hcs_n,\r
- hwrite_n,\r
- hread_n,\r
-\r
- \r
-\r
- \r
- tx_fifodata,\r
- tx_fifoavail,\r
- tx_fifoeof,\r
- tx_fifoempty,\r
- tx_sndpaustim,\r
- tx_sndpausreq,\r
- tx_fifoctrl,\r
-\r
- \r
- rx_fifo_full,\r
- ignore_pkt,\r
-\r
- \r
- tx_en,\r
- tx_er,\r
-\r
- txd,\r
-\r
- \r
- hdataout,\r
- hdataout_en_n,\r
- hready_n,\r
- cpu_if_gbit_en,\r
-\r
- \r
-\r
- \r
- tx_macread,\r
- tx_discfrm,\r
- tx_staten,\r
- tx_statvec,\r
- tx_done,\r
-\r
- \r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
-)\r
- \r
- \r
-;\r
-input hclk;\r
-input txmac_clk;\r
-input rxmac_clk;\r
-input reset_n;\r
-\r
-input txmac_clk_en;\r
-input rxmac_clk_en;\r
-\r
-\r
-\r
-input [7:0] rxd;\r
-input rx_dv;\r
-input rx_er;\r
-\r
-\r
-input col;\r
-input crs;\r
-\r
-input [7:0] haddr;\r
-input [7:0] hdatain;\r
-input hcs_n;\r
-input hwrite_n;\r
-input hread_n;\r
-\r
-input [7:0] tx_fifodata;\r
-input tx_fifoavail;\r
-input tx_fifoeof;\r
-input tx_fifoempty;\r
-input [15:0] tx_sndpaustim;\r
-input tx_sndpausreq;\r
-input tx_fifoctrl;\r
-input rx_fifo_full;\r
-input ignore_pkt;\r
-\r
-output [7:0] txd;\r
-\r
-output tx_en;\r
-output tx_er;\r
-output [7:0] hdataout;\r
-output hdataout_en_n;\r
-output hready_n;\r
-output cpu_if_gbit_en;\r
-\r
-output tx_macread;\r
-output tx_discfrm;\r
-output tx_staten;\r
-output tx_done;\r
-output [30:0] tx_statvec;\r
-output rx_fifo_error;\r
-output [31:0] rx_stat_vector;\r
-output [7:0] rx_dbout;\r
-output rx_write;\r
-output rx_stat_en;\r
-output rx_eof;\r
-output rx_error;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-parameter pdevice_family = "ECP3";\r
-\r
-wire [15:0] ie2197a;\r
-wire fpcbd0;\r
-wire yx65e87;\r
-wire [8:0] bldd558;\r
-wire ykeaac7;\r
-wire [15:0] ned0f15;\r
-wire ie878aa;\r
-wire oh3c550;\r
-wire [7:0] mre2a84;\r
-wire mg15425;\r
-wire hdaa129;\r
-wire bl5094e;\r
-wire tj84a76;\r
-wire ba253b7;\r
-wire [4:0] ep29dbb;\r
-wire cz4eddc;\r
-wire vi76ee4;\r
-wire lsb7722;\r
-wire ohbb913;\r
-wire mrdc89c;\r
-wire fae44e4;\r
-wire lf22723;\r
-wire db1391e;\r
-wire ls9c8f7;\r
-wire [13:0] xwe47ba;\r
-wire [7:0] yz23dd3;\r
-wire [7:0] fc1ee9d;\r
-wire [7:0] gbf74eb;\r
-wire [7:0] bnba75d;\r
-wire [7:0] qtd3aef;\r
-wire [7:0] ks9d77d;\r
-wire [7:0] tuebbe9;\r
-wire [7:0] vi5df4b;\r
-wire [15:0] ykefa5a;\r
-wire [47:0] ic7d2d1;\r
-wire [10:0] rte9688;\r
-wire [15:0] gb4b447;\r
-wire hb5a23d;\r
-wire [7:0] qgd11ee;\r
-wire ks88f71;\r
-wire lq47b89;\r
-wire nt3dc4a;\r
-wire hoee257;\r
-wire bl712ba;\r
-wire hq895d6;\r
-\r
-wire mrd6596;\r
-wire bab2cb4;\r
-wire [7:0] hq965a2;\r
-wire [3:0] ngb2d12;\r
-wire zm96892;\r
-wire gdb4493;\r
-wire vka249c;\r
-wire ep124e2;\r
-wire [7:0] ou92714;\r
-wire [3:0] ri938a0;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg jea77e1;\r
-reg [7 : 0] en51e07;\r
-reg [7 : 0] go781e5;\r
-reg mt3ca1c;\r
-reg yz7943;\r
-reg zkc0f28;\r
-reg [7 : 0] al7a68d;\r
-reg jcda897;\r
-reg ipd346d;\r
-reg wl9a36c;\r
-reg [15 : 0] ay463af;\r
-reg end918e;\r
-reg god1b64;\r
-reg wwde5f9;\r
-reg wwd1063;\r
-reg [15 : 0] ks9259a;\r
-reg ks92cd0;\r
-reg pu96681;\r
-reg [8 : 0] ir29e31;\r
-reg jp4f18c;\r
-reg [15 : 0] vid028c;\r
-reg bn81463;\r
-reg iea31e;\r
-reg [7 : 0] wj518f1;\r
-reg do8c78c;\r
-reg dm63c62;\r
-reg tw1e313;\r
-reg jcf189a;\r
-reg xy8c4d3;\r
-reg [4 : 0] go6269a;\r
-reg ph134d0;\r
-reg an9a686;\r
-reg ofd3434;\r
-reg sj9a1a4;\r
-reg byd0d24;\r
-reg ri86922;\r
-reg gq34912;\r
-reg ana4891;\r
-reg qi2448c;\r
-reg [13 : 0] vx22461;\r
-reg [7 : 0] ep1230e;\r
-reg [7 : 0] rv91874;\r
-reg [7 : 0] pu8c3a6;\r
-reg [7 : 0] xj61d32;\r
-reg [7 : 0] twe996;\r
-reg [7 : 0] dz74cb2;\r
-reg [7 : 0] aaa6597;\r
-reg [7 : 0] tj32cb8;\r
-reg [15 : 0] vk965c6;\r
-reg [47 : 0] vkb2e32;\r
-reg [10 : 0] ks97192;\r
-reg [15 : 0] lsb8c90;\r
-reg shc6483;\r
-reg [7 : 0] vx3241d;\r
-reg ou920ef;\r
-reg sj90778;\r
-reg ba83bc5;\r
-reg kf1de2a;\r
-reg osef154;\r
-reg cm78aa0;\r
-reg xwc5501;\r
-reg do2a80a;\r
-reg [7 : 0] yx54053;\r
-reg [3 : 0] zza029d;\r
-reg ng14ef;\r
-reg aaa77a;\r
-reg ic53bd1;\r
-reg ym9de89;\r
-reg [7 : 0] wwef448;\r
-reg [3 : 0] qt7a240;\r
-reg [2047:0] ng1e1e0;\r
-wire [69:0] mef0f02;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam uk87811 = 70,gd3c088 = 32'hfdffd14b;\r
-localparam [31:0] yke0444 = gd3c088;\r
-localparam ba1110d = gd3c088 & 4'hf;\r
-localparam [11:0] of44359 = 'h7ff;\r
-wire [(1 << ba1110d) -1:0] epd660;\r
-reg [uk87811-1:0] ui59826;\r
-reg [ba1110d-1:0] uv60984 [0:1];\r
-reg [ba1110d-1:0] sj26123;\r
-reg fc3091c;\r
-integer tj848e3;\r
-integer aa2471f;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- assign mrd6596 = txmac_clk_en; assign bab2cb4 = rxmac_clk_en;\r
-\r
-\r
-\r
-\r
-\r
- assign hq965a2 = rxd; assign ngb2d12 = 4'h0; assign zm96892 = rx_dv; assign gdb4493 = 1'b0; assign vka249c = rx_er; assign ep124e2 = 1'b0; assign txd = wwef448;\r
-\r
-\r
-\r
-\r
-\r
-qv835c #(.pdevice_family(pdevice_family))\r
-mt3cb88 ( .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(do2a80a), .ks10d54(ba83bc5), .fa6c2d4(jr8eff9), .ls86aa0(vx3241d), .pf616a3(sj90778), .lsb51f(ou920ef), .vv5a8fb(kf1de2a), .uv70d29(ep1230e), .hq8694d(rv91874), .ec34a6a(pu8c3a6), .lfa5351(xj61d32), .gd29a8f(twe996), .rg4d47c(dz74cb2), .mr6a3e2(aaa6597), .of51f14(tj32cb8), .sj8f8a4(vkb2e32), .tu7c524(sj9a1a4), .ale2922(byd0d24), .vk14915(gq34912), .ba25a85(vk965c6), .qgcb360(ana4891), .go59b01(ri86922), .ldcd808(vx22461), .tu6c047(ofd3434), .wj6023b(an9a686), .rx_fifo_full(wwde5f9), .ignore_pkt(wwd1063), .gq3baab(yx65e87), .ene2fd7(ie2197a), .cb17ebd(fpcbd0), .bldd558(bldd558), .ykeaac7(ykeaac7), .su780a3(ned0f15), .fa58e7c(ie878aa), .rx_fifo_error(rx_fifo_error), .rx_stat_vector(rx_stat_vector), .rx_dbout(rx_dbout), .rx_write(rx_write), .rx_stat_en(rx_stat_en), .rx_eof(rx_eof), .rx_error(rx_error)\r
-);\r
-uid1f98 #(.pdevice_family(pdevice_family))\r
-wy3e272 ( .txmac_clk(txmac_clk), .ir3994e(jea77e1), .txmac_clk_en(xwc5501), .gof5dd7(tw1e313), .anaeeb9(jcf189a), .phbae69(xy8c4d3), .yk775cd(ph134d0), .vk3f2df(go6269a), .vvf96fb(vkb2e32), .fa69d8e(vk965c6), .tx_fifodata(al7a68d), .tx_fifoeof(ipd346d), .tx_fifoempty(wl9a36c), .tx_fifoavail(jcda897), .tx_sndpaustim(ay463af), .tx_sndpausreq(end918e), .tx_fifoctrl(god1b64), .zk520c4(bn81463), .cb90622(vid028c), .ukb9a76(cm78aa0), .vvd734e(osef154), .suc455c(hdaa129), .tx_macread(tx_macread), .tx_discfrm(tx_discfrm), .tx_staten(tx_staten), .tx_statvec(tx_statvec), .tx_done(tx_done), .ip750ca(oh3c550), .lsa8654(mre2a84), .ic432a3(mg15425) \r
-);\r
- ksbcf57 twa7c2e ( .txmac_clk(txmac_clk), .rxmac_clk(rxmac_clk), .reset_n(jea77e1), .rxmac_clk_en(do2a80a), .txmac_clk_en(xwc5501), .fncdc51(wj518f1), .zx6e28f(do8c78c), .pf7147e(iea31e), .rx_dv_pos(ng14ef), .rx_dv_neg(aaa77a), .rx_er_pos(ic53bd1), .rx_er_neg(ym9de89), .rxd_pos(yx54053), .rxd_neg(zza029d),\r
-\r
-\r
- .col(col), .crs(crs),\r
-\r
-\r
-\r
- .ned0632(cpu_if_gbit_en), .kq53683(qi2448c), .lsb51f(ks88f71), .pf616a3(lq47b89), .ks10d54(nt3dc4a), .fa6c2d4(jr8eff9), .ls86aa0(qgd11ee), .vv5a8fb(hoee257), .ksac9b7(bl712ba), .zx64db8(hq895d6), .txd_pos(ou92714), .txd_neg(ri938a0), .tx_en(tx_en), .tx_er(tx_er) );\r
-\r
-fp8b349 vk20026 ( .hclk(hclk), .reset_n(jea77e1), .haddr(en51e07), .hdatain(go781e5), .hread_n(zkc0f28), .hwrite_n(yz7943), .hcs_n(mt3ca1c), .ene2fd7(ks9259a), .cb17ebd(ks92cd0), .gq3baab(pu96681), .bldd558(ir29e31), .ykeaac7(jp4f18c), .aye5ebc(dm63c62), \r
-\r
-\r
-\r
- .hdataout(hdataout), .hready_n(hready_n), .hdataout_en_n(hdataout_en_n), .tx_en(bl5094e), .vvcda9b(tj84a76), .ui6d4df(ba253b7), .vk3f2df(ep29dbb), .ned0632(cpu_if_gbit_en), .yk775cd(cz4eddc),\r
- \r
-\r
-\r
-\r
- .wj6023b(vi76ee4), .tu6c047(lsb7722), .neda0c6(ic7d2d1), .bydf307(ohbb913), .ale2922(mrdc89c), .go59b01(fae44e4), .vk14915(lf22723), .qgcb360(db1391e), .ldcd808(xwe47ba), .kq53683(ls9c8f7), .ba25a85(ykefa5a), .ip60ebc(yz23dd3), .ep75e4(fc1ee9d), .ls3af25(gbf74eb), .pfd792a(bnba75d), .cobc957(qtd3aef), .xwe4ab9(ks9d77d), .tw255ca(tuebbe9), .ri2ae53(vi5df4b)\r
-);\r
-\r
-\r
-\r
-always@* begin jea77e1<=mef0f02[0];en51e07<={haddr>>1,mef0f02[1]};go781e5<={hdatain>>1,mef0f02[2]};mt3ca1c<=mef0f02[3];yz7943<=mef0f02[4];zkc0f28<=mef0f02[5];al7a68d<={tx_fifodata>>1,mef0f02[6]};jcda897<=mef0f02[7];ipd346d<=mef0f02[8];wl9a36c<=mef0f02[9];ay463af<={tx_sndpaustim>>1,mef0f02[10]};end918e<=mef0f02[11];god1b64<=mef0f02[12];wwde5f9<=mef0f02[13];wwd1063<=mef0f02[14];ks9259a<={ie2197a>>1,mef0f02[15]};ks92cd0<=mef0f02[16];pu96681<=mef0f02[17];ir29e31<={bldd558>>1,mef0f02[18]};jp4f18c<=mef0f02[19];vid028c<={ned0f15>>1,mef0f02[20]};bn81463<=mef0f02[21];iea31e<=mef0f02[22];wj518f1<={mre2a84>>1,mef0f02[23]};do8c78c<=mef0f02[24];dm63c62<=mef0f02[25];tw1e313<=mef0f02[26];jcf189a<=mef0f02[27];xy8c4d3<=mef0f02[28];go6269a<={ep29dbb>>1,mef0f02[29]};ph134d0<=mef0f02[30];an9a686<=mef0f02[31];ofd3434<=mef0f02[32];sj9a1a4<=mef0f02[33];byd0d24<=mef0f02[34];ri86922<=mef0f02[35];gq34912<=mef0f02[36];ana4891<=mef0f02[37];qi2448c<=mef0f02[38];vx22461<={xwe47ba>>1,mef0f02[39]};ep1230e<={yz23dd3>>1,mef0f02[40]};rv91874<={fc1ee9d>>1,mef0f02[41]};pu8c3a6<={gbf74eb>>1,mef0f02[42]};xj61d32<={bnba75d>>1,mef0f02[43]};twe996<={qtd3aef>>1,mef0f02[44]};dz74cb2<={ks9d77d>>1,mef0f02[45]};aaa6597<={tuebbe9>>1,mef0f02[46]};tj32cb8<={vi5df4b>>1,mef0f02[47]};vk965c6<={ykefa5a>>1,mef0f02[48]};vkb2e32<={ic7d2d1>>1,mef0f02[49]};ks97192<={rte9688>>1,mef0f02[50]};lsb8c90<={gb4b447>>1,mef0f02[51]};shc6483<=mef0f02[52];vx3241d<={qgd11ee>>1,mef0f02[53]};ou920ef<=mef0f02[54];sj90778<=mef0f02[55];ba83bc5<=mef0f02[56];kf1de2a<=mef0f02[57];osef154<=mef0f02[58];cm78aa0<=mef0f02[59];xwc5501<=mef0f02[60];do2a80a<=mef0f02[61];yx54053<={hq965a2>>1,mef0f02[62]};zza029d<={ngb2d12>>1,mef0f02[63]};ng14ef<=mef0f02[64];aaa77a<=mef0f02[65];ic53bd1<=mef0f02[66];ym9de89<=mef0f02[67];wwef448<={ou92714>>1,mef0f02[68]};qt7a240<={ri938a0>>1,mef0f02[69]};end\r
-always@* begin ng1e1e0[2047]<=haddr[0];ng1e1e0[2046]<=hdatain[0];ng1e1e0[2044]<=hcs_n;ng1e1e0[2040]<=hwrite_n;ng1e1e0[2033]<=hread_n;ng1e1e0[2019]<=tx_fifodata[0];ng1e1e0[1994]<=gbf74eb[0];ng1e1e0[1990]<=tx_fifoavail;ng1e1e0[1981]<=tj84a76;ng1e1e0[1965]<=lsb7722;ng1e1e0[1940]<=bnba75d[0];ng1e1e0[1939]<=bldd558[0];ng1e1e0[1933]<=tx_fifoeof;ng1e1e0[1914]<=ba253b7;ng1e1e0[1883]<=ohbb913;ng1e1e0[1832]<=qtd3aef[0];ng1e1e0[1831]<=ykeaac7;ng1e1e0[1819]<=tx_fifoempty;ng1e1e0[1785]<=xwe47ba[0];ng1e1e0[1781]<=ep29dbb[0];ng1e1e0[1778]<=ie2197a[0];ng1e1e0[1740]<=hoee257;ng1e1e0[1719]<=mrdc89c;ng1e1e0[1634]<=mrd6596;ng1e1e0[1616]<=ks9d77d[0];ng1e1e0[1615]<=ned0f15[0];ng1e1e0[1591]<=tx_sndpaustim[0];ng1e1e0[1579]<=zm96892;ng1e1e0[1522]<=yz23dd3[0];ng1e1e0[1515]<=cz4eddc;ng1e1e0[1508]<=fpcbd0;ng1e1e0[1470]<=db1391e;ng1e1e0[1432]<=bl712ba;ng1e1e0[1406]<=ri938a0[0];ng1e1e0[1391]<=fae44e4;ng1e1e0[1286]<=ic7d2d1[0];ng1e1e0[1271]<=mg15425;ng1e1e0[1221]<=bab2cb4;ng1e1e0[1184]<=tuebbe9[0];ng1e1e0[1182]<=ie878aa;ng1e1e0[1135]<=tx_sndpausreq;ng1e1e0[1111]<=gdb4493;ng1e1e0[1051]<=gb4b447[0];ng1e1e0[1023]<=reset_n;ng1e1e0[997]<=fc1ee9d[0];ng1e1e0[990]<=bl5094e;ng1e1e0[982]<=vi76ee4;ng1e1e0[969]<=yx65e87;ng1e1e0[892]<=ls9c8f7;ng1e1e0[889]<=ignore_pkt;ng1e1e0[870]<=nt3dc4a;ng1e1e0[817]<=hq895d6;ng1e1e0[789]<=ngb2d12[0];ng1e1e0[735]<=lf22723;ng1e1e0[703]<=ou92714[0];ng1e1e0[643]<=ykefa5a[0];ng1e1e0[635]<=mre2a84[0];ng1e1e0[525]<=rte9688[0];ng1e1e0[495]<=hdaa129;ng1e1e0[444]<=rx_fifo_full;ng1e1e0[435]<=lq47b89;ng1e1e0[394]<=hq965a2[0];ng1e1e0[351]<=ep124e2;ng1e1e0[321]<=vi5df4b[0];ng1e1e0[317]<=oh3c550;ng1e1e0[222]<=tx_fifoctrl;ng1e1e0[217]<=ks88f71;ng1e1e0[175]<=vka249c;ng1e1e0[108]<=qgd11ee[0];ng1e1e0[54]<=hb5a23d;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f<uk87811; aa2471f=aa2471f+1) begin ui59826[aa2471f] = epd660[sj26123]; fc3091c = ^(sj26123 & uv60984[0]); sj26123 = {sj26123, fc3091c}; end end \r
-endmodule\r
-\r
+++ /dev/null
-=============================================================================
-Filelist generated by IPexpress 09/21/2011 11:36:13
-Filename: tsmac34_filelist.log
-Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-=============================================================================
-
------------------------------------------------------------------------------
-Basic IP Core Files
-Output Directory: /home/greg/projects/trb3/trb3_gbe/ipcores
------------------------------------------------------------------------------
- tsmac34.lpc
- : IP ispLEVER LPC File
- tsmac34.ngo
- : IP ispLEVER Database File
- tsmac34_bb.v
- : IP Verilog Blackbox Module
- tsmac34_inst.v
- : IP Verilog Instantiation Template
- tsmac34_beh.v
- : IP Verilog Behaviorial Sim Model
- tsmac34_gen.log
- : IP Status Log
- tsmac34_generate.log
- : IP Generate Log
-
------------------------------------------------------------------------------
-Supplemental Implementation and Simulation Files:
-
-Testbench files common to all Tri-Speed MAC configurations
- ../ts_mac_eval/testbench/top
- ../ts_mac_eval/testbench/tests
-
-Models common to all Tri-Speed MAC configurations
- ../ts_mac_eval/models/ecp3
-
-Evaluation source files specific to tsmac34 configuration
- ../ts_mac_eval/tsmac34/src/rtl/top
- ../ts_mac_eval/tsmac34/src/rtl/templates
- ../ts_mac_eval/tsmac34/src/params
-
-Simulation files specific to tsmac34 configuration
- ../ts_mac_eval/tsmac34/sim/modelsim
-
-Implementation files specific to tsmac34 configuration
- ../ts_mac_eval/tsmac34/impl/synplify
-
+++ /dev/null
-Parameters loaded ok.
-No optional files required.
-Parameter values ok.
-Project Directory succussfully created.
-Simulation model successfully created.
-IP template generation completed ok.
-LPF generation completed ok.
-ModelSim do file successfully created.
-IP core generation completed ok.
-Generation completed ok.
+++ /dev/null
-Starting process: IPCFG
-
-GenerateCore within package Core_Generate 1.0.0 in file LatticeIP_generate.tcl
-Starting process: '"/opt/lattice/diamond/1.3/bin/lin/synpwrap" -rem -e tsmac34 -target lattice-ecp3'
-
-Warning: You are running on an unsupported platform
-End process: completed successfully.
-
-Starting process: '"/opt/lattice/diamond/1.3/bin/lin/../../ispfpga/bin/lin/edif2ngd" -ip "/home/greg/trispeed_mac_v3.4/lib/../.." -ic trispeed_mac_v3.4 -l LatticeECP3 -nopropwarn "tsmac34.edi" "tsmac34.ngo"'
-edif2ngd: version Diamond_1.3_Production (92)
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
- Copyright (c) 1995 AT&T Corp. All rights reserved.
- Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
- Copyright (c) 2001 Agere Systems All rights reserved.
- Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-No device specified. Will use default.
-Writing the design to tsmac34.ngo...
-Generating edif netlist for IP cell pmi_ram_dpEbnonessdn96649664.edn
-SCUBA, Version Diamond_1.3_Production (92)
-Wed Sep 21 11:36:13 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -data_width 9 -num_rows 64 -rdata_width 9 -gsr DISABLED -sync_reset -memformat bin -cascade -1 -n pmi_ram_dpEbnonessdn96649664 -pmi
- Circuit name : pmi_ram_dpEbnonessdn96649664
- Module type : RAM_DP
- Module Version : 6.1
- Ports :
- Inputs : WrAddress[5:0], RdAddress[5:0], Data[8:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
- Outputs : Q[8:0]
- I/O buffer : not inserted
- EDIF output : pmi_ram_dpEbnonessdn96649664.edn
- Bus notation : big endian
- Report output : pmi_ram_dpEbnonessdn96649664.srp
- Estimated Resource Usage:
- EBR : 1
-
-END SCUBA Module Synthesis
-Writing the design to pmi_ram_dpEbnonessdn96649664.ngo...
-Generating edif netlist for IP cell pmi_ram_dpEbnonessdn208256208256.edn
-SCUBA, Version Diamond_1.3_Production (92)
-Wed Sep 21 11:36:13 2011
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -data_width 20 -num_rows 256 -rdata_width 20 -gsr DISABLED -sync_reset -memformat bin -cascade -1 -n pmi_ram_dpEbnonessdn208256208256 -pmi
- Circuit name : pmi_ram_dpEbnonessdn208256208256
- Module type : RAM_DP
- Module Version : 6.1
- Ports :
- Inputs : WrAddress[7:0], RdAddress[7:0], Data[19:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
- Outputs : Q[19:0]
- I/O buffer : not inserted
- EDIF output : pmi_ram_dpEbnonessdn208256208256.edn
- Bus notation : big endian
- Report output : pmi_ram_dpEbnonessdn208256208256.srp
- Estimated Resource Usage:
- EBR : 1
-
-END SCUBA Module Synthesis
-Writing the design to pmi_ram_dpEbnonessdn208256208256.ngo...
-End process: completed successfully.
-
-=============================================================================
-Filelist generated by IPexpress 09/21/2011 11:36:13
-Filename: tsmac34_filelist.log
-Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-=============================================================================
------------------------------------------------------------------------------
-Basic IP Core Files
-Output Directory: /home/greg/projects/trb3/trb3_gbe/ipcores
------------------------------------------------------------------------------
- tsmac34.lpc
- : IP ispLEVER LPC File
- tsmac34.ngo
- : IP ispLEVER Database File
- tsmac34_bb.v
- : IP Verilog Blackbox Module
- tsmac34_inst.v
- : IP Verilog Instantiation Template
- tsmac34_beh.v
- : IP Verilog Behaviorial Sim Model
- tsmac34_gen.log
- : IP Status Log
- tsmac34_generate.log
- : IP Generate Log
------------------------------------------------------------------------------
-Supplemental Implementation and Simulation Files:
-
-Testbench files common to all Tri-Speed MAC configurations
- ../ts_mac_eval/testbench/top
- ../ts_mac_eval/testbench/tests
-
-Models common to all Tri-Speed MAC configurations
- ../ts_mac_eval/models/ecp3
-
-Evaluation source files specific to tsmac34 configuration
- ../ts_mac_eval/tsmac34/src/rtl/top
- ../ts_mac_eval/tsmac34/src/rtl/templates
- ../ts_mac_eval/tsmac34/src/params
-
-Simulation files specific to tsmac34 configuration
- ../ts_mac_eval/tsmac34/sim/modelsim
-
-Implementation files specific to tsmac34 configuration
- ../ts_mac_eval/tsmac34/impl/synplify
-
-Total Warnings: 1
-
-
-Total Errors: 0
-
-
-
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress \r
-// Filename: USERNAME_inst.v \r
-// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
- tsmac34 DUT_INST ( \r
-\r
- // clock and reset\r
- .hclk(hclk),\r
- .txmac_clk(txmac_clk),\r
- .rxmac_clk(rxmac_clk),\r
- .reset_n(reset_n),\r
- .txmac_clk_en(txmac_clk_en),\r
- .rxmac_clk_en(rxmac_clk_en),\r
- \r
- // Input signals to the GMII\r
- .rxd(rxd),\r
- .rx_dv(rx_dv),\r
- .rx_er(rx_er),\r
- .col(col),\r
- .crs(crs),\r
- \r
- // Input signals to the CPU Interface\r
- .haddr(haddr),\r
- .hdatain(hdatain),\r
- .hcs_n(hcs_n),\r
- .hwrite_n(hwrite_n),\r
- .hread_n(hread_n),\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- .tx_fifodata(tx_fifodata),\r
- .tx_fifoavail(tx_fifoavail),\r
- .tx_fifoeof(tx_fifoeof),\r
- .tx_fifoempty(tx_fifoempty),\r
- .tx_sndpaustim(tx_sndpaustim),\r
- .tx_sndpausreq(tx_sndpausreq),\r
- .tx_fifoctrl(tx_fifoctrl),\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- .rx_fifo_full(rx_fifo_full),\r
- .ignore_pkt(ignore_pkt),\r
- \r
- // Output signals from the GMII\r
- .txd(txd),\r
- .tx_en(tx_en),\r
- .tx_er(tx_er),\r
- \r
- // Output signals from the CPU Interface\r
- .hdataout(hdataout),\r
- .hdataout_en_n(hdataout_en_n),\r
- .hready_n(hready_n),\r
- .cpu_if_gbit_en(cpu_if_gbit_en),\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- .tx_macread(tx_macread),\r
- .tx_discfrm(tx_discfrm),\r
- .tx_staten(tx_staten),\r
- .tx_statvec(tx_statvec),\r
- .tx_done(tx_done),\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- .rx_fifo_error(rx_fifo_error),\r
- .rx_stat_vector(rx_stat_vector),\r
- .rx_dbout(rx_dbout),\r
- .rx_write(rx_write),\r
- .rx_stat_en(rx_stat_en),\r
- .rx_eof(rx_eof),\r
- .rx_error(rx_error)\r
- );\r
+++ /dev/null
-
-#!/usr/local/bin/wish
-
-set Para(cmd) ""
-if ![catch {set temp $argc} result] {
- if {$argc > 0} {
- for {set i 0} {$i < $argc} {incr i 2} {
- set temp [lindex $argv $i]
- set temp [string range $temp 1 end]
- lappend argv_list $temp
- lappend value_list [lindex $argv [expr $i+1]]
- }
- foreach argument $argv_list value $value_list {
- switch $argument {
- "cmd" {set Para(cmd) $value;}
- }
- }
- }
-}
-
-set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35"
-set Para(ModuleName) "tsmac35"
-set Para(lib) "/home/greg/trispeed_mac_v3.5/lib"
-set Para(CoreName) "Tri-Speed Ethernet MAC"
-set Para(arch) "ep5c00"
-set Para(family) "latticeecp3"
-set Para(Family) "latticeecp3"
-set Para(design) "VHDL"
-set Para(install_dir) "/opt/lattice/diamond/1.4.2.105/bin/lin/../.."
-set Para(Bin) "/opt/lattice/diamond/1.4.2.105/bin/lin"
-set Para(SpeedGrade) "Para(spd)"
-set Para(FPGAPath) "/opt/lattice/diamond/1.4.2.105/bin/lin/../../ispfpga/bin/sol"
-
-lappend auto_path "/home/greg/trispeed_mac_v3.5/gui"
-
-lappend auto_path "/home/greg/trispeed_mac_v3.5/script"
-package require Core_Generate
-
-lappend auto_path "/opt/lattice/diamond/1.4.2.105/tcltk/lib/ipwidgets/ispipbuilder/../runproc"
-package require runcmd
-
-
-set Para(result) [GenerateCore]
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="tsmac35" module="Tri-Speed Ethernet MAC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 06 19 10:00:57.050" version="3.5" type="IP" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="pmi_ram_dpEbnonessdn208256208256.ngo" type="database" modified="2012 06 19 09:58:40.000"/>
- <File name="pmi_ram_dpEbnonessdn96649664.ngo" type="database" modified="2012 06 19 09:58:40.000"/>
- <File name="tsmac35.lpc" type="lpc" modified="2012 06 19 09:58:20.000"/>
- <File name="tsmac35.ngo" type="database" modified="2012 06 19 09:58:39.000"/>
- <File name="tsmac35_bb.v" type="black_box_verilog" modified="2012 06 19 09:58:20.000"/>
- <File name="tsmac35_beh.v" type="behavioral_verilog" modified="2012 06 19 09:58:20.000"/>
- <File name="tsmac35_inst.v" type="instantiation_verilog" modified="2012 06 19 09:58:20.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=ep5c00
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=IPCFG
-CoreStatus=Demo
-CoreName=Tri-Speed Ethernet MAC
-CoreRevision=3.5
-ModuleName=tsmac35
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=06/19/2012
-Time=09:58:20
-
-[Parameters]
-MIIM=No
-MODE=SGMII easy connect
-SYNP_TOOL=1
-PREC_TOOL=0
-MODS_TOOL=1
-ALDC_TOOL=0
-MULT_WB=NO
-LOOPBACK=NO
-STAT_REGS=NO
-
-[Files]
-Synthesis=
-Simulation=
-Logical=
-Physical=
-Misc=
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress \r
-// Filename: USERNAME.v \r
-// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
-module tsmac35 (\r
- // clock and reset\r
- hclk,\r
- txmac_clk,\r
- rxmac_clk,\r
- reset_n,\r
- txmac_clk_en,\r
- rxmac_clk_en,\r
-\r
- // Input signals to the GMII\r
- rxd,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
- // Input signals to the CPU Interface\r
- haddr,\r
- hdatain,\r
- hcs_n,\r
- hwrite_n,\r
- hread_n,\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- tx_fifodata,\r
- tx_fifoavail,\r
- tx_fifoeof,\r
- tx_fifoempty,\r
- tx_sndpaustim,\r
- tx_sndpausreq,\r
- tx_fifoctrl,\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- rx_fifo_full,\r
- ignore_pkt,\r
- \r
- // Output signals from the GMII\r
- txd,\r
- tx_en,\r
- tx_er,\r
- \r
- // Output signals from the CPU Interface\r
- hdataout,\r
- hdataout_en_n,\r
- hready_n,\r
- cpu_if_gbit_en,\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- tx_macread,\r
- tx_discfrm,\r
- tx_staten,\r
- tx_statvec,\r
- tx_done,\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
- );\r
- \r
- // ------------------------- clock and reset inputs ---------------------\r
- input hclk; // clock to the CPU I/F\r
- input txmac_clk; // clock to the Tx MAC\r
- input rxmac_clk; // clock to the RX MAC\r
- input reset_n; // Global reset\r
- input txmac_clk_en; // clock enable to the Tx MAC\r
- input rxmac_clk_en; // clock enable to the RX MAC\r
- \r
- // ----------------------- Input signals to the GMII -------------------\r
- input [7:0] rxd; // Receive data\r
- input rx_dv; // Receive data valid\r
- input rx_er; // Receive data error\r
- input col; // Collision detect\r
- input crs; // Carrier Sense\r
- // -------------------- Input signals to the CPU I/F -------------------\r
- input [7:0] haddr; // Address Bus\r
- input [7:0] hdatain; // Input data Bus\r
- input hcs_n; // Chip select\r
- input hwrite_n; // Register write\r
- input hread_n; // Register read\r
- \r
- // -------------------- Input signals to the MII I/F -------------------\r
-\r
- \r
- // ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
- input [7:0] tx_fifodata; // Data Input from FIFO\r
- input tx_fifoavail; // Data Available in FIFO\r
- input tx_fifoeof; // End of Frame\r
- input tx_fifoempty; // FIFO Empty\r
- input [15:0] tx_sndpaustim; // Pause frame parameter\r
- input tx_sndpausreq; // Transmit PAUSE frame\r
- input tx_fifoctrl; // Control frame or Not\r
- \r
- // ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
- input rx_fifo_full; // Receive FIFO Full\r
- input ignore_pkt; // Ignore the frame\r
- \r
- // -------------------- Output signals from the GMII -----------------------\r
- output [7:0] txd; // Transmit data\r
- output tx_en; // Transmit Enable\r
- output tx_er; // Transmit Error\r
- \r
- // -------------------- Output signals from the CPU I/F -------------------\r
- output [7:0] hdataout; // Output data Bus\r
- output hdataout_en_n; // Data Out Enable\r
- output hready_n; // Ready signal\r
- output cpu_if_gbit_en; // Gig or 10/100 mode\r
- \r
- // -------------------- Output signals from the MII I/F -------------------\r
-\r
- \r
- // ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
- output tx_macread; // Read FIFO\r
- output tx_discfrm; // Discard Frame\r
- output tx_staten; // Status Vector Valid\r
- output tx_done; // Transmit of Frame done\r
- output [30:0] tx_statvec; // Tx Status Vector\r
- \r
- // ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
- output rx_fifo_error; // FIFO full detected\r
- output [31:0] rx_stat_vector; // Rx Status Vector\r
- output [7:0] rx_dbout; // Data Output to FIFO\r
- output rx_write; // Write FIFO\r
- output rx_stat_en; // Status Vector Valid\r
- output rx_eof; // Entire frame written\r
- output rx_error; // Erroneous frame\r
- \r
- tsmac_core U1_LSC_ts_mac_core ( \r
-\r
- // clock and reset\r
- .hclk(hclk),\r
- .txmac_clk(txmac_clk),\r
- .rxmac_clk(rxmac_clk),\r
- .reset_n(reset_n),\r
- .txmac_clk_en(txmac_clk_en),\r
- .rxmac_clk_en(rxmac_clk_en),\r
- \r
- // Input signals to the GMII\r
- .rxd(rxd),\r
- .rx_dv(rx_dv),\r
- .rx_er(rx_er),\r
- .col(col),\r
- .crs(crs),\r
- // Input signals to the CPU Interface\r
- .haddr(haddr),\r
- .hdatain(hdatain),\r
- .hcs_n(hcs_n),\r
- .hwrite_n(hwrite_n),\r
- .hread_n(hread_n),\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- .tx_fifodata(tx_fifodata),\r
- .tx_fifoavail(tx_fifoavail),\r
- .tx_fifoeof(tx_fifoeof),\r
- .tx_fifoempty(tx_fifoempty),\r
- .tx_sndpaustim(tx_sndpaustim),\r
- .tx_sndpausreq(tx_sndpausreq),\r
- .tx_fifoctrl(tx_fifoctrl),\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- .rx_fifo_full(rx_fifo_full),\r
- .ignore_pkt(ignore_pkt),\r
- \r
- // Output signals from the GMII\r
- .txd(txd),\r
- .tx_en(tx_en),\r
- .tx_er(tx_er),\r
- \r
- // Output signals from the CPU Interface\r
- .hdataout(hdataout),\r
- .hdataout_en_n(hdataout_en_n),\r
- .hready_n(hready_n),\r
- .cpu_if_gbit_en(cpu_if_gbit_en),\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- .tx_macread(tx_macread),\r
- .tx_discfrm(tx_discfrm),\r
- .tx_staten(tx_staten),\r
- .tx_statvec(tx_statvec),\r
- .tx_done(tx_done),\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- .rx_fifo_error(rx_fifo_error),\r
- .rx_stat_vector(rx_stat_vector),\r
- .rx_dbout(rx_dbout),\r
- .rx_write(rx_write),\r
- .rx_stat_en(rx_stat_en),\r
- .rx_eof(rx_eof),\r
- .rx_error(rx_error)\r
- );\r
-endmodule\r
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress \r
-// Filename: USERNAME_bb.v \r
-// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
-module tsmac35 (\r
- // clock and reset\r
- hclk,\r
- txmac_clk,\r
- rxmac_clk,\r
- reset_n,\r
- txmac_clk_en,\r
- rxmac_clk_en,\r
-\r
- // Input signals to the GMII\r
- rxd,\r
- rx_dv,\r
- rx_er,\r
- col,\r
- crs,\r
- \r
- // Input signals to the CPU Interface\r
- haddr,\r
- hdatain,\r
- hcs_n,\r
- hwrite_n,\r
- hread_n,\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- tx_fifodata,\r
- tx_fifoavail,\r
- tx_fifoeof,\r
- tx_fifoempty,\r
- tx_sndpaustim,\r
- tx_sndpausreq,\r
- tx_fifoctrl,\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- rx_fifo_full,\r
- ignore_pkt,\r
- \r
- // Output signals from the GMII\r
- txd,\r
- tx_en,\r
- tx_er,\r
- \r
- // Output signals from the CPU Interface\r
- hdataout,\r
- hdataout_en_n,\r
- hready_n,\r
- cpu_if_gbit_en,\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- tx_macread,\r
- tx_discfrm,\r
- tx_staten,\r
- tx_statvec,\r
- tx_done,\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
- );\r
- \r
- // ------------------------- clock and reset inputs ---------------------\r
- input hclk; // clock to the CPU I/F\r
- input txmac_clk; // clock to the Tx MAC\r
- input rxmac_clk; // clock to the RX MAC\r
- input reset_n; // Global reset\r
- input txmac_clk_en; // clock enable to the Tx MAC\r
- input rxmac_clk_en; // clock enable to the RX MAC\r
- \r
- // ----------------------- Input signals to the GMII -------------------\r
- input [7:0] rxd; // Receive data\r
- input rx_dv; // Receive data valid\r
- input rx_er; // Receive data error\r
- input col; // Collision detect\r
- input crs; // Carrier Sense\r
- // -------------------- Input signals to the CPU I/F -------------------\r
- input [7:0] haddr; // Address Bus\r
- input [7:0] hdatain; // Input data Bus\r
- input hcs_n; // Chip select\r
- input hwrite_n; // Register write\r
- input hread_n; // Register read\r
- \r
- // -------------------- Input signals to the MII I/F -------------------\r
-\r
- \r
- // ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
- input [7:0] tx_fifodata; // Data Input from FIFO\r
- input tx_fifoavail; // Data Available in FIFO\r
- input tx_fifoeof; // End of Frame\r
- input tx_fifoempty; // FIFO Empty\r
- input [15:0] tx_sndpaustim; // Pause frame parameter\r
- input tx_sndpausreq; // Transmit PAUSE frame\r
- input tx_fifoctrl; // Control frame or Not\r
- \r
- // ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
- input rx_fifo_full; // Receive FIFO Full\r
- input ignore_pkt; // Ignore the frame\r
- \r
- // -------------------- Output signals from the GMII -----------------------\r
- output [7:0] txd; // Transmit data\r
- output tx_en; // Transmit Enable\r
- output tx_er; // Transmit Error\r
- \r
- // -------------------- Output signals from the CPU I/F -------------------\r
- output [7:0] hdataout; // Output data Bus\r
- output hdataout_en_n; // Data Out Enable\r
- output hready_n; // Ready signal\r
- output cpu_if_gbit_en; // Gig or 10/100 mode\r
- \r
- // -------------------- Output signals from the MII I/F -------------------\r
-\r
- \r
- // ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
- output tx_macread; // Read FIFO\r
- output tx_discfrm; // Discard Frame\r
- output tx_staten; // Status Vector Valid\r
- output tx_done; // Transmit of Frame done\r
- output [30:0] tx_statvec; // Tx Status Vector\r
- \r
- // ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
- output rx_fifo_error; // FIFO full detected\r
- output [31:0] rx_stat_vector; // Rx Status Vector\r
- output [7:0] rx_dbout; // Data Output to FIFO\r
- output rx_write; // Write FIFO\r
- output rx_stat_en; // Status Vector Valid\r
- output rx_eof; // Entire frame written\r
- output rx_error; // Erroneous frame\r
- \r
-endmodule\r
+++ /dev/null
-// ts_mac_core_beh.v generated by Lattice IP Model Creator version 1\r
-// created on Wed Aug 24 16:57:02 CST 2011\r
-// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved\r
-// obfuscator_exe version 1.mar0807\r
-\r
-// top\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module uk979bb (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en, \r
- \r
- \r
- mtbb27f, \r
- ald93fd, \r
- \r
- \r
- shc9fed,\r
- zx4ff6d,\r
- \r
- \r
- yx7fb6e,\r
- offdb74,\r
- qtedba5,\r
- su6dd2c\r
-);\r
-parameter ld6e960 = 8;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input mtbb27f;\r
-input shc9fed;\r
-input zx4ff6d;\r
-input [ld6e960-1:0] ald93fd;\r
-output offdb74;\r
-output qtedba5;\r
-output su6dd2c;\r
-output [ld6e960-1:0] yx7fb6e;\r
-reg offdb74;\r
-reg qtedba5;\r
-reg su6dd2c;\r
-reg [ld6e960-1:0] yx7fb6e;\r
-reg kf3941a;\r
-parameter faca0d4 = 2;\r
-parameter zx506a3 = 2'b01;\r
-parameter fc8351f = 2'b10;\r
-parameter sw1a8fb = 0;\r
-parameter ead47d9 = 1;\r
-parameter swa3ec9 = 8'hd5;\r
-parameter ie1f649 = 8'h55;\r
-wire zkfb248;\r
-wire ald9243;\r
-reg shc921d;\r
-reg su490ec;\r
-reg tu48760;\r
-reg [faca0d4-1:0] cb1d810;\r
-reg [2:0] fnec084;\r
-reg [faca0d4-1:0] ep213d;\r
-reg ks109ed;\r
-reg [ld6e960 - 1 : 0] hd27b47;\r
-reg bn3da3f;\r
-reg qted1ff;\r
-reg ww68ffd;\r
-reg ps47fe8;\r
-reg ri3ff42;\r
-reg icffa12;\r
-reg qtfd090;\r
-reg cze8484;\r
-reg [faca0d4 - 1 : 0] wl1212b;\r
-reg [2 : 0] ep9095c;\r
-reg [faca0d4 - 1 : 0] ls25727;\r
-reg [2047:0] ec2b93b;\r
-wire [12:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 13,ph27642 = 32'hfdfff40b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
- \r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin yx7fb6e <= 0; end else if (rxmac_clk_en) begin if (ks109ed) begin yx7fb6e <= hd27b47; end end\r
-end\r
-\r
-\r
-\r
-\r
-assign zkfb248 = hd27b47[7:0] == swa3ec9;\r
-assign ald9243 = hd27b47[7:0] == ie1f649;\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin ep213d <= zx506a3; fnec084 <= 3'b0; offdb74 <= 1'b0; su6dd2c <= 1'b0; kf3941a <= 1'b0; qtedba5 <= 1'b0; end else if (rxmac_clk_en) begin ep213d <= wl1212b; kf3941a <= icffa12; qtedba5 <= ww68ffd; offdb74 <= 1'b0; \r
- fnec084 <= cze8484 ? 3'h1 : (|ep9095c) ? (ep9095c+3'h1) : ls25727[sw1a8fb] ? 3'h0 : ep9095c;\r
- if (qtfd090) begin su6dd2c <= 1'b1; end else if (qted1ff) begin su6dd2c <= 1'b0; end else if (bn3da3f) begin su6dd2c <= 1'b0; end end\r
-end\r
-\r
-\r
-always @(ls25727 or bn3da3f or ri3ff42 or ps47fe8 or ep9095c) begin case(ls25727) zx506a3 : begin if (bn3da3f && ps47fe8) begin cb1d810 = zx506a3; shc921d = 1'b1; su490ec = 1'b0; tu48760 = 1'b0; end else if (bn3da3f && ri3ff42) begin cb1d810 = fc8351f; shc921d = 1'b0; su490ec = 1'b0; tu48760 = 1'b1; end else if (bn3da3f && !ps47fe8 && !ri3ff42) begin cb1d810 = zx506a3; shc921d = 1'b0; su490ec = 1'b1; tu48760 = 1'b0; end\r
- else begin cb1d810 = zx506a3; shc921d = 1'b0; su490ec = 1'b0; tu48760 = 1'b0; end end\r
- fc8351f : begin if (ps47fe8) begin cb1d810 = zx506a3; shc921d = 1'b1; su490ec = 1'b0; tu48760 = 1'b0; end else if (~|ep9095c & ~ri3ff42) begin cb1d810 = zx506a3; shc921d = 1'b0; su490ec = 1'b1; tu48760 = 1'b0; end else begin cb1d810 = fc8351f; shc921d = 1'b0; su490ec = 1'b0; tu48760 = 1'b0; end\r
- end\r
- default : begin cb1d810 = zx506a3; shc921d = 1'b0; su490ec = 1'b0; tu48760 = 1'b0; end endcase\r
-end\r
-\r
-always@* begin ks109ed<=ea5c9d9[0];hd27b47<={ald93fd>>1,ea5c9d9[1]};bn3da3f<=ea5c9d9[2];qted1ff<=ea5c9d9[3];ww68ffd<=ea5c9d9[4];ps47fe8<=ea5c9d9[5];ri3ff42<=ea5c9d9[6];icffa12<=ea5c9d9[7];qtfd090<=ea5c9d9[8];cze8484<=ea5c9d9[9];wl1212b<={cb1d810>>1,ea5c9d9[10]};ep9095c<={fnec084>>1,ea5c9d9[11]};ls25727<={ep213d>>1,ea5c9d9[12]};end\r
-always@* begin ec2b93b[2047]<=ald93fd[0];ec2b93b[2046]<=shc9fed;ec2b93b[2044]<=zx4ff6d;ec2b93b[2040]<=kf3941a;ec2b93b[2032]<=zkfb248;ec2b93b[2016]<=ald9243;ec2b93b[1984]<=shc921d;ec2b93b[1920]<=su490ec;ec2b93b[1793]<=tu48760;ec2b93b[1539]<=cb1d810[0];ec2b93b[1030]<=fnec084[0];ec2b93b[1023]<=mtbb27f;ec2b93b[13]<=ep213d[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module zmbda32 (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- nt32741,\r
- qtedba5,\r
-\r
- \r
- zx4ff6d,\r
- uve83d9,\r
-\r
- \r
- en41ecd,\r
- ksf66d,\r
- nr7b369,\r
- ipd9b4f,\r
- blcda7c,\r
- qg6d3e7,\r
- xw69f39,\r
- zx4f9ca,\r
- xw7ce56,\r
- kde72b3,\r
- ux3959c,\r
- hocace4,\r
-\r
- \r
- ic56722,\r
-\r
- \r
- ukb3910,\r
- do9c880,\r
- lqe4402,\r
- hd22013,\r
- uk1009e,\r
- sj804f1,\r
- qv278c\r
-);\r
-parameter ld6e960 = 8;\r
-parameter db9e32f = 48;\r
-parameter lqf197e = 6;\r
-parameter ng8cbf3 = 8;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input qtedba5;\r
-input zx4ff6d;\r
-input uve83d9;\r
-input [ld6e960-1:0] nt32741;\r
-input [ng8cbf3-1:0] en41ecd;\r
-input [ng8cbf3-1:0] ksf66d;\r
-input [ng8cbf3-1:0] nr7b369;\r
-input [ng8cbf3-1:0] ipd9b4f;\r
-input [ng8cbf3-1:0] blcda7c;\r
-input [ng8cbf3-1:0] qg6d3e7;\r
-input [ng8cbf3-1:0] xw69f39;\r
-input [ng8cbf3-1:0] zx4f9ca;\r
-input [db9e32f-1:0] xw7ce56;\r
-input kde72b3;\r
-input ux3959c;\r
-input hocace4;\r
-input [lqf197e-1:0] ic56722;\r
-output do9c880;\r
-output lqe4402;\r
-output hd22013;\r
-output uk1009e;\r
-output sj804f1;\r
-output qv278c;\r
-output ukb3910;\r
-reg uk1009e;\r
-reg sj804f1;\r
-reg qv278c;\r
-reg do9c880;\r
-localparam xje6095 = 11;\r
-localparam tw304ae = 11'b00000000001;\r
-localparam uk82572 = 11'b00000000010;\r
-localparam kf12b91 = 11'b00000000100;\r
-localparam qv95c8d = 11'b00000001000;\r
-localparam irae46c = 11'b00000010000;\r
-localparam go72364 = 11'b00000100000;\r
-localparam bn91b21 = 11'b00001000000;\r
-localparam qi8d90e = 11'b00010000000;\r
-localparam ho6c871 = 11'b00100000000;\r
-localparam bl6438a = 11'b01000000000;\r
-localparam co21c57 = 11'b10000000000;\r
-localparam sw1a8fb = 0;\r
-localparam ead47d9 = 1;\r
-localparam qv8ae1e = 2;\r
-localparam dm570f4 = 3;\r
-localparam hqb87a2 = 4;\r
-localparam ipc3d12 = 5;\r
-localparam ng1e894 = 6;\r
-localparam rgf44a3 = 7;\r
-localparam fca251a = 8;\r
-localparam gd128d2 = 9;\r
-localparam lf94695 = 10;\r
-wire wya34af;\r
-wire ks1a578;\r
-wire rtd2bc0;\r
-wire ux95e07;\r
-wire phaf03c;\r
-wire kq781e6;\r
-reg fac0f30;\r
-reg ux7983;\r
-reg [xje6095-1:0] fne60e5;\r
-reg [xje6095-1:0] ng83972;\r
-wire db1cb92;\r
-wire kqe5c96;\r
-wire sw2e4b0;\r
-wire ic72580;\r
-wire ou92c01;\r
-wire vk96009;\r
-reg xlb004a;\r
-reg cb80256;\r
-reg [xje6095-1:0] jr95a2;\r
-reg [xje6095-1:0] me568b6;\r
-wire gdb45b1;\r
-reg vka2d8c;\r
-reg [ng8cbf3-1:0] gqb631f;\r
-reg anb18f9;\r
-reg do8c7cd;\r
-wire dm63e6a;\r
-reg sw1f353;\r
-reg dzf9a98;\r
-reg [xje6095-1:0] kd6a63e;\r
-reg [xje6095-1:0] co98fa0;\r
-wire fnc7d00;\r
-wire ou3e806;\r
-wire lqf4030;\r
-reg lfa0182;\r
-reg ecc17;\r
-reg nt60b9;\r
-reg fc305cf;\r
-reg mg82e7a;\r
-reg ux173d0;\r
-reg mgb9e84;\r
-reg zkcf421;\r
-reg ukb3910;\r
-reg [ld6e960 - 1 : 0] nt842ea;\r
-reg aa21756;\r
-reg qted1ff;\r
-reg rg5d58a;\r
-reg [ng8cbf3 - 1 : 0] su56299;\r
-reg [ng8cbf3 - 1 : 0] kf8a644;\r
-reg [ng8cbf3 - 1 : 0] ls99128;\r
-reg [ng8cbf3 - 1 : 0] ip44a1f;\r
-reg [ng8cbf3 - 1 : 0] db287eb;\r
-reg [ng8cbf3 - 1 : 0] uk1faf8;\r
-reg [ng8cbf3 - 1 : 0] xwebe0c;\r
-reg [ng8cbf3 - 1 : 0] mrf831e;\r
-reg [db9e32f - 1 : 0] lfc7a1;\r
-reg ps63d0e;\r
-reg ls1e873;\r
-reg byf439b;\r
-reg [lqf197e - 1 : 0] doe6d4;\r
-reg ho736a3;\r
-reg jr9b51b;\r
-reg hoda8de;\r
-reg uid46f3;\r
-reg qia3799;\r
-reg pu1bcc8;\r
-reg gode643;\r
-reg ldf3218;\r
-reg [xje6095 - 1 : 0] thc863b;\r
-reg [xje6095 - 1 : 0] gd18ef1;\r
-reg ldc778c;\r
-reg ou3bc67;\r
-reg kqde338;\r
-reg psf19c0;\r
-reg tw8ce03;\r
-reg ea6701b;\r
-reg zz380d8;\r
-reg vic06c6;\r
-reg [xje6095 - 1 : 0] vk1b197;\r
-reg [xje6095 - 1 : 0] wjc65d6;\r
-reg bn32eb5;\r
-reg gq975ae;\r
-reg [ng8cbf3 - 1 : 0] ipd6b86;\r
-reg bnb5c35;\r
-reg mtae1af;\r
-reg of70d7c;\r
-reg ls86be5;\r
-reg ls35f2a;\r
-reg [xje6095 - 1 : 0] ps7ca9f;\r
-reg [xje6095 - 1 : 0] pu2a7d9;\r
-reg kq53eca;\r
-reg qv9f651;\r
-reg lqfb28c;\r
-reg shd9463;\r
-reg faca31d;\r
-reg yx518eb;\r
-reg tw8c75c;\r
-reg by63ae2;\r
-reg ep1d713;\r
-reg xweb89d;\r
-reg ay5c4eb;\r
-reg [2047:0] ec2b93b;\r
-wire [57:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 58,ph27642 = 32'hfdffc68b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-assign fnc7d00 = (gd18ef1[ipc3d12] | gd18ef1[lf94695]) & (byf439b | gode643 | zz380d8 | (ls1e873 & ls86be5));\r
-assign lqf4030 = (gd18ef1[ipc3d12] | gd18ef1[lf94695]) & ~kq53eca;\r
-assign ou3e806 = shd9463 & ~(faca31d | (mtae1af & ps63d0e & gq975ae));\r
-\r
-assign lqe4402 = by63ae2 | tw8c75c;\r
-\r
-assign hd22013 = ep1d713 | yx518eb;\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin fc305cf <= 1'b0; mg82e7a <= 1'b0; ux173d0 <= 1'b0; mgb9e84 <= 1'b0; zkcf421 <= 1'b0; ng83972 <= tw304ae; me568b6 <= tw304ae; co98fa0 <= tw304ae; do9c880 <= 1'b0; ecc17 <= 1'b0; qv278c <= 1'b0; uk1009e <= 1'b0; sj804f1 <= 1'b0; anb18f9 <= 1'b0; do8c7cd <= 1'b0; lfa0182 <= 1'b0; nt60b9 <= 1'b0; end else if (rxmac_clk_en) begin zkcf421 <= rg5d58a; fc305cf <= (mtae1af & ps63d0e & gq975ae); mg82e7a <= faca31d; ux173d0 <= qv9f651; mgb9e84 <= aa21756; if(ay5c4eb) begin ng83972 <= tw304ae; me568b6 <= tw304ae; co98fa0 <= tw304ae; end else begin ng83972 <= thc863b; me568b6 <= vk1b197; co98fa0 <= ps7ca9f; end ecc17 <= kq53eca; lfa0182 <= lqfb28c; do8c7cd <= bn32eb5; if (aa21756) anb18f9 <= nt842ea[0]; if (gode643) do9c880 <= gode643; else if (qted1ff) do9c880 <= gode643; else do9c880 <= do9c880; if (zz380d8) qv278c <= zz380d8; else if (qted1ff) qv278c <= zz380d8; else qv278c <= qv278c; if (qv9f651 | qted1ff) nt60b9 <= qv9f651; else if (aa21756) nt60b9 <= 1'b0; else nt60b9 <= yx518eb; if (bn32eb5) uk1009e <= (bn32eb5); else if (qted1ff) uk1009e <= bn32eb5; else if (aa21756) uk1009e <= 1'b0; else uk1009e <= uk1009e; if (ls86be5) sj804f1 <= ls86be5; else if (qted1ff) sj804f1 <= ls86be5; else if (xweb89d) sj804f1 <= 1'b0; else sj804f1 <= sj804f1; end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-assign kq781e6 = lfc7a1[47:40] == nt842ea;\r
-\r
-assign phaf03c = lfc7a1[39:32] == nt842ea;\r
-\r
-assign ux95e07 = lfc7a1[31:24] == nt842ea;\r
-\r
-assign rtd2bc0 = lfc7a1[23:16] == nt842ea;\r
-\r
-assign ks1a578 = lfc7a1[15:8] == nt842ea;\r
-\r
-assign wya34af = lfc7a1[7:0] == nt842ea;\r
-\r
-\r
-always @(gd18ef1 or aa21756 or ho736a3 or jr9b51b or hoda8de or uid46f3 or qia3799 or pu1bcc8) begin ukb3910 = 1'b1; case(gd18ef1) tw304ae : begin if (!aa21756) begin fne60e5 = tw304ae; fac0f30 = 1'b0; ux7983 = 1'b0; ukb3910 = 1'b0; end else if (aa21756) begin if (pu1bcc8) begin fne60e5 = uk82572; fac0f30 = 1'b0; ux7983 = 1'b0; end else begin fne60e5 = bn91b21; fac0f30 = 1'b0; ux7983 = 1'b0; end end end uk82572 : begin if (qia3799) begin fne60e5 = kf12b91; fac0f30 = 1'b0; ux7983 = 1'b0; end else begin fne60e5 = qi8d90e; fac0f30 = 1'b0; ux7983 = 1'b0; end end kf12b91 : begin if (uid46f3) begin fne60e5 = qv95c8d; fac0f30 = 1'b0; ux7983 = 1'b0; end else begin fne60e5 = ho6c871; fac0f30 = 1'b0; ux7983 = 1'b0; end end qv95c8d : begin if (hoda8de) begin fne60e5 = irae46c; fac0f30 = 1'b0; ux7983 = 1'b0; end else begin fne60e5 = bl6438a; fac0f30 = 1'b0; ux7983 = 1'b0; end end irae46c : begin if (jr9b51b) begin fne60e5 = go72364; fac0f30 = 1'b0; ux7983 = 1'b0; end else begin fne60e5 = co21c57; fac0f30 = 1'b0; ux7983 = 1'b0; end end go72364 : begin if (ho736a3) begin fne60e5 = tw304ae; fac0f30 = 1'b1; ux7983 = 1'b0; end else begin fne60e5 = tw304ae; fac0f30 = 1'b0; ux7983 = 1'b1; end end bn91b21 : begin fne60e5 = qi8d90e; fac0f30 = 1'b0; ux7983 = 1'b0; end qi8d90e : begin fne60e5 = ho6c871; fac0f30 = 1'b0; ux7983 = 1'b0; end ho6c871 : begin fne60e5 = bl6438a; fac0f30 = 1'b0; ux7983 = 1'b0; end bl6438a : begin fne60e5 = co21c57; fac0f30 = 1'b0; ux7983 = 1'b0; end co21c57 : begin fne60e5 = tw304ae; fac0f30 = 1'b0; ux7983 = 1'b1; end default : begin fne60e5 = tw304ae; fac0f30 = 1'b0; ux7983 = 1'b0; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign vk96009 = 8'h01 == nt842ea;\r
-\r
-assign ou92c01 = 8'h80 == nt842ea;\r
-\r
-assign ic72580 = 8'hc2 == nt842ea;\r
-\r
-assign sw2e4b0 = 8'h00 == nt842ea;\r
-\r
-assign kqe5c96 = 8'h00 == nt842ea;\r
-\r
-assign db1cb92 = 8'h01 == nt842ea;\r
-\r
-\r
-always @(wjc65d6 or aa21756 or ldc778c or ou3bc67 or kqde338 or psf19c0 or tw8ce03 or ea6701b) begin case(wjc65d6) tw304ae : begin if (!aa21756) begin jr95a2 = tw304ae; xlb004a = 1'b0; cb80256 = 1'b0; end else if (aa21756) begin if (ea6701b) begin jr95a2 = uk82572; xlb004a = 1'b0; cb80256 = 1'b0; end else begin jr95a2 = bn91b21; xlb004a = 1'b0; cb80256 = 1'b0; end end end uk82572 : begin if (tw8ce03) begin jr95a2 = kf12b91; xlb004a = 1'b0; cb80256 = 1'b0; end else begin jr95a2 = qi8d90e; xlb004a = 1'b0; cb80256 = 1'b0; end end kf12b91 : begin if (psf19c0) begin jr95a2 = qv95c8d; xlb004a = 1'b0; cb80256 = 1'b0; end else begin jr95a2 = ho6c871; xlb004a = 1'b0; cb80256 = 1'b0; end end qv95c8d : begin if (kqde338) begin jr95a2 = irae46c; xlb004a = 1'b0; cb80256 = 1'b0; end else begin jr95a2 = bl6438a; xlb004a = 1'b0; cb80256 = 1'b0; end end irae46c : begin if (ou3bc67) begin jr95a2 = go72364; xlb004a = 1'b0; cb80256 = 1'b0; end else begin jr95a2 = co21c57; xlb004a = 1'b0; cb80256 = 1'b0; end end go72364 : begin if (ldc778c) begin jr95a2 = tw304ae; xlb004a = 1'b1; cb80256 = 1'b0; end else begin jr95a2 = tw304ae; xlb004a = 1'b0; cb80256 = 1'b1; end end bn91b21 : begin jr95a2 = qi8d90e; xlb004a = 1'b0; cb80256 = 1'b0; end qi8d90e : begin jr95a2 = ho6c871; xlb004a = 1'b0; cb80256 = 1'b0; end ho6c871 : begin jr95a2 = bl6438a; xlb004a = 1'b0; cb80256 = 1'b0; end bl6438a : begin jr95a2 = co21c57; xlb004a = 1'b0; cb80256 = 1'b0; end co21c57 : begin jr95a2 = tw304ae; xlb004a = 1'b0; cb80256 = 1'b1; end default : begin jr95a2 = tw304ae; xlb004a = 1'b0; cb80256 = 1'b0; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign gdb45b1 = bnb5c35 & gd18ef1[lf94695] & ~ls86be5 & ~zz380d8 ;\r
-\r
-always @ (doe6d4[5:3] or su56299 or kf8a644 or ls99128 or ip44a1f or db287eb or uk1faf8 or xwebe0c or mrf831e) begin case (doe6d4[5:3]) 3'b000 : begin gqb631f = su56299; end 3'b001 : begin gqb631f = kf8a644; end 3'b010 : begin gqb631f = ls99128; end 3'b011 : begin gqb631f = ip44a1f; end 3'b100 : begin gqb631f = db287eb; end 3'b101 : begin gqb631f = uk1faf8; end 3'b110 : begin gqb631f = xwebe0c; end 3'b111 : begin gqb631f = mrf831e; end endcase\r
-end\r
-\r
-always @ (doe6d4[2:0] or ipd6b86) begin case (doe6d4[2:0]) 3'b000 : begin vka2d8c = ipd6b86[0]; end 3'b001 : begin vka2d8c = ipd6b86[1]; end 3'b010 : begin vka2d8c = ipd6b86[2]; end 3'b011 : begin vka2d8c = ipd6b86[3]; end 3'b100 : begin vka2d8c = ipd6b86[4]; end 3'b101 : begin vka2d8c = ipd6b86[5]; end 3'b110 : begin vka2d8c = ipd6b86[6]; end 3'b111 : begin vka2d8c = ipd6b86[7]; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign dm63e6a = 8'hff == nt842ea;\r
-\r
-\r
-always @(pu2a7d9 or aa21756 or of70d7c) begin case(pu2a7d9) tw304ae : begin if (!aa21756) begin kd6a63e = tw304ae; sw1f353 = 1'b0; dzf9a98 = 1'b0; end else if (aa21756) begin if (of70d7c) begin kd6a63e = uk82572; sw1f353 = 1'b0; dzf9a98 = 1'b0; end else begin kd6a63e = bn91b21; sw1f353 = 1'b0; dzf9a98 = 1'b0; end end end uk82572 : begin if (of70d7c) begin kd6a63e = kf12b91; sw1f353 = 1'b0; dzf9a98 = 1'b0; end else begin kd6a63e = qi8d90e; sw1f353 = 1'b0; dzf9a98 = 1'b0; end end kf12b91 : begin if (of70d7c) begin kd6a63e = qv95c8d; sw1f353 = 1'b0; dzf9a98 = 1'b0; end else begin kd6a63e = ho6c871; sw1f353 = 1'b0; dzf9a98 = 1'b0; end end qv95c8d : begin if (of70d7c) begin kd6a63e = irae46c; sw1f353 = 1'b0; dzf9a98 = 1'b0; end else begin kd6a63e = bl6438a; sw1f353 = 1'b0; dzf9a98 = 1'b0; end end irae46c : begin if (of70d7c) begin kd6a63e = go72364; sw1f353 = 1'b0; dzf9a98 = 1'b0; end else begin kd6a63e = co21c57; sw1f353 = 1'b0; dzf9a98 = 1'b0; end end go72364 : begin if (of70d7c) begin kd6a63e = tw304ae; sw1f353 = 1'b1; dzf9a98 = 1'b0; end else begin kd6a63e = tw304ae; sw1f353 = 1'b0; dzf9a98 = 1'b1; end end bn91b21 : begin kd6a63e = qi8d90e; sw1f353 = 1'b0; dzf9a98 = 1'b0; end qi8d90e : begin kd6a63e = ho6c871; sw1f353 = 1'b0; dzf9a98 = 1'b0; end ho6c871 : begin kd6a63e = bl6438a; sw1f353 = 1'b0; dzf9a98 = 1'b0; end bl6438a : begin kd6a63e = co21c57; sw1f353 = 1'b0; dzf9a98 = 1'b0; end co21c57 : begin kd6a63e = tw304ae; sw1f353 = 1'b0; dzf9a98 = 1'b1; end default : begin kd6a63e = tw304ae; sw1f353 = 1'b0; dzf9a98 = 1'b0; end endcase\r
-end\r
-\r
-always@* begin nt842ea<={nt32741>>1,ea5c9d9[0]};aa21756<=ea5c9d9[1];qted1ff<=ea5c9d9[2];rg5d58a<=ea5c9d9[3];su56299<={en41ecd>>1,ea5c9d9[4]};kf8a644<={ksf66d>>1,ea5c9d9[5]};ls99128<={nr7b369>>1,ea5c9d9[6]};ip44a1f<={ipd9b4f>>1,ea5c9d9[7]};db287eb<={blcda7c>>1,ea5c9d9[8]};uk1faf8<={qg6d3e7>>1,ea5c9d9[9]};xwebe0c<={xw69f39>>1,ea5c9d9[10]};mrf831e<={zx4f9ca>>1,ea5c9d9[11]};lfc7a1<={xw7ce56>>1,ea5c9d9[12]};ps63d0e<=ea5c9d9[13];ls1e873<=ea5c9d9[14];byf439b<=ea5c9d9[15];doe6d4<={ic56722>>1,ea5c9d9[16]};ho736a3<=ea5c9d9[17];jr9b51b<=ea5c9d9[18];hoda8de<=ea5c9d9[19];uid46f3<=ea5c9d9[20];qia3799<=ea5c9d9[21];pu1bcc8<=ea5c9d9[22];gode643<=ea5c9d9[23];ldf3218<=ea5c9d9[24];thc863b<={fne60e5>>1,ea5c9d9[25]};gd18ef1<={ng83972>>1,ea5c9d9[26]};ldc778c<=ea5c9d9[27];ou3bc67<=ea5c9d9[28];kqde338<=ea5c9d9[29];psf19c0<=ea5c9d9[30];tw8ce03<=ea5c9d9[31];ea6701b<=ea5c9d9[32];zz380d8<=ea5c9d9[33];vic06c6<=ea5c9d9[34];vk1b197<={jr95a2>>1,ea5c9d9[35]};wjc65d6<={me568b6>>1,ea5c9d9[36]};bn32eb5<=ea5c9d9[37];gq975ae<=ea5c9d9[38];ipd6b86<={gqb631f>>1,ea5c9d9[39]};bnb5c35<=ea5c9d9[40];mtae1af<=ea5c9d9[41];of70d7c<=ea5c9d9[42];ls86be5<=ea5c9d9[43];ls35f2a<=ea5c9d9[44];ps7ca9f<={kd6a63e>>1,ea5c9d9[45]};pu2a7d9<={co98fa0>>1,ea5c9d9[46]};kq53eca<=ea5c9d9[47];qv9f651<=ea5c9d9[48];lqfb28c<=ea5c9d9[49];shd9463<=ea5c9d9[50];faca31d<=ea5c9d9[51];yx518eb<=ea5c9d9[52];tw8c75c<=ea5c9d9[53];by63ae2<=ea5c9d9[54];ep1d713<=ea5c9d9[55];xweb89d<=ea5c9d9[56];ay5c4eb<=ea5c9d9[57];end\r
-always@* begin ec2b93b[2047]<=qtedba5;ec2b93b[2046]<=zx4ff6d;ec2b93b[2044]<=uve83d9;ec2b93b[2040]<=en41ecd[0];ec2b93b[2032]<=ksf66d[0];ec2b93b[2017]<=nr7b369[0];ec2b93b[1987]<=ipd9b4f[0];ec2b93b[1980]<=lqf4030;ec2b93b[1963]<=xlb004a;ec2b93b[1942]<=mg82e7a;ec2b93b[1926]<=blcda7c[0];ec2b93b[1921]<=fac0f30;ec2b93b[1913]<=lfa0182;ec2b93b[1903]<=dm63e6a;ec2b93b[1879]<=cb80256;ec2b93b[1837]<=ux173d0;ec2b93b[1805]<=qg6d3e7[0];ec2b93b[1795]<=ux7983;ec2b93b[1783]<=co98fa0[0];ec2b93b[1778]<=ecc17;ec2b93b[1758]<=sw1f353;ec2b93b[1710]<=jr95a2[0];ec2b93b[1679]<=ic56722[0];ec2b93b[1627]<=mgb9e84;ec2b93b[1562]<=xw69f39[0];ec2b93b[1543]<=fne60e5[0];ec2b93b[1519]<=fnc7d00;ec2b93b[1509]<=nt60b9;ec2b93b[1499]<=anb18f9;ec2b93b[1469]<=dzf9a98;ec2b93b[1398]<=vka2d8c;ec2b93b[1373]<=me568b6[0];ec2b93b[1310]<=wya34af;ec2b93b[1207]<=zkcf421;ec2b93b[1144]<=rtd2bc0;ec2b93b[1076]<=zx4f9ca[0];ec2b93b[1039]<=ng83972[0];ec2b93b[1023]<=nt32741[0];ec2b93b[990]<=ou3e806;ec2b93b[981]<=vk96009;ec2b93b[971]<=fc305cf;ec2b93b[960]<=kq781e6;ec2b93b[951]<=do8c7cd;ec2b93b[891]<=kd6a63e[0];ec2b93b[839]<=hocace4;ec2b93b[749]<=gqb631f[0];ec2b93b[699]<=gdb45b1;ec2b93b[572]<=ks1a578;ec2b93b[490]<=ou92c01;ec2b93b[480]<=phaf03c;ec2b93b[419]<=ux3959c;ec2b93b[245]<=ic72580;ec2b93b[240]<=ux95e07;ec2b93b[209]<=kde72b3;ec2b93b[122]<=sw2e4b0;ec2b93b[104]<=xw7ce56[0];ec2b93b[61]<=kqe5c96;ec2b93b[30]<=db1cb92;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module fa63a6e (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- pf6e773,\r
- lq73b9e,\r
- ie9dcf2,\r
-\r
- \r
- rx_fifo_full,\r
-\r
- \r
- ne73c82,\r
-\r
- \r
- bn9e412,\r
- wjf2096,\r
- yz904b5,\r
- wy825ad,\r
-\r
- \r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
-);\r
-parameter ld6e960 = 8;\r
-parameter xwfb4be = 20;\r
-parameter jcda5f3 = 32;\r
-parameter jpd2f9a = 8;\r
-parameter gq97cd7 = 4;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input lq73b9e;\r
-input pf6e773;\r
-input [1:0] ie9dcf2;\r
-input rx_fifo_full;\r
-input [xwfb4be-1:0] ne73c82;\r
-output [jpd2f9a-1:0] bn9e412;\r
-output [jpd2f9a-1:0] wjf2096;\r
-output yz904b5;\r
-output wy825ad;\r
-output rx_fifo_error;\r
-output [jcda5f3-1:0] rx_stat_vector;\r
-output [ld6e960-1:0] rx_dbout;\r
-output rx_write;\r
-output rx_stat_en;\r
-output rx_eof;\r
-output rx_error;\r
-reg [jpd2f9a:0] zk79681;\r
-reg [jpd2f9a:0] pf5a051;\r
-wire yz904b5;\r
-wire wy825ad;\r
-reg rx_fifo_error;\r
-reg [jcda5f3-1:0] rx_stat_vector;\r
-reg [ld6e960-1:0] rx_dbout ;\r
-reg [ld6e960-1:0] vk8ceb3;\r
-reg [ld6e960-1:0] vk3acd8;\r
-reg rx_write ;\r
-reg gqb3614;\r
-reg bn9b0a1;\r
-reg xjd850e;\r
-reg rx_stat_en;\r
-reg rx_eof;\r
-reg rx_error;\r
-reg [xwfb4be-1:0] ww77ce2;\r
-reg uxbe710;\r
-wire nrf3885;\r
-wire zm9c42e;\r
-reg kde2173;\r
-reg sw10b9c;\r
-reg yz85ce0;\r
-wire ou2e705;\r
-reg [gq97cd7-1:0] xy9c142;\r
-reg sue0a13;\r
-wire [jpd2f9a:0] jr284c0;\r
-reg [jpd2f9a:0] db1303b;\r
-reg gq981de;\r
-reg nec0ef1;\r
-reg gd778b;\r
-reg aa3bc5d;\r
-reg cmde2e8;\r
-reg dmf1740;\r
-reg [1 : 0] zz8ba02;\r
-reg xw5d016;\r
-reg [xwfb4be - 1 : 0] fn4059d;\r
-reg [jpd2f9a : 0] bn16774;\r
-reg [jpd2f9a : 0] wy9dd30;\r
-reg [ld6e960 - 1 : 0] fn74c03;\r
-reg [ld6e960 - 1 : 0] pu300f8;\r
-reg qv807c2;\r
-reg bn3e14;\r
-reg ie1f0a6;\r
-reg [xwfb4be - 1 : 0] fnc2984;\r
-reg pu14c26;\r
-reg yma6132;\r
-reg ba30990;\r
-reg nt84c83;\r
-reg gd2641f;\r
-reg ph320fc;\r
-reg ux907e7;\r
-reg [gq97cd7 - 1 : 0] gq1f9ea;\r
-reg pffcf51;\r
-reg [jpd2f9a : 0] hd3d47d;\r
-reg [jpd2f9a : 0] sh51f70;\r
-reg yz8fb84;\r
-reg os7dc24;\r
-reg psee121;\r
-reg mr7090a;\r
-reg [2047:0] ec2b93b;\r
-wire [27:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 28,ph27642 = 32'hfdffc68b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-assign bn9e412 = bn16774[jpd2f9a-1:0];\r
-assign wjf2096 = wy9dd30[jpd2f9a-1:0];\r
-assign jr284c0 = ({(bn16774[jpd2f9a] ^ wy9dd30[jpd2f9a]), bn16774[jpd2f9a-1:0]}) - ({1'b0, wy9dd30[jpd2f9a-1:0]});\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin uxbe710 <= 0; kde2173 <= 0; end else if (rxmac_clk_en) begin kde2173 <= ba30990; if ((|gq1f9ea) | (yma6132)) begin uxbe710 <= 1; end else begin uxbe710 <= 0; end end\r
-end\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin xy9c142 <= 4'h0; sue0a13 <= 1'b0; yz85ce0 <= 1'b0; zk79681 <= 9'd0; pf5a051 <= 9'd0; db1303b <= 9'd0; gq981de <= 1'b0; nec0ef1 <= 1'b0; ww77ce2 <= 1'b0; rx_stat_vector <= 32'b0; rx_dbout <= 8'd0; vk8ceb3 <= 8'd0; vk3acd8 <= 8'd0; rx_write <= 1'b0; gqb3614 <= 1'b0; bn9b0a1 <= 1'b0; xjd850e <= 1'b0; rx_stat_en <= 1'b0; rx_eof <= 1'b0; rx_error <= 1'b0; sw10b9c <= 1'b0; gd778b <= 1'b0; aa3bc5d <= 1'b0; rx_fifo_error <= 1'b0; end else if (rxmac_clk_en) begin ww77ce2 <= fn4059d;\r
- rx_fifo_error <= ux907e7 | (rx_fifo_error & ~rx_eof); if ((cmde2e8 == 1) & (zz8ba02 == 3)) begin sw10b9c <= 1; end else begin sw10b9c <= 0; end gd778b <= gd2641f; aa3bc5d <= dmf1740; if (ph320fc == 1) begin xy9c142 <= 0; end else if (!ba30990 && psee121) begin xy9c142 <= gq1f9ea + 4'b0001; end else if (ba30990 && !psee121) begin xy9c142 <= gq1f9ea - 4'b0001; end if ((hd3d47d[jpd2f9a-1:1] == 0) && ((hd3d47d[0] == 0) || (yz904b5 == 1))) begin yz85ce0 <= 1; end else begin yz85ce0 <= 0; end if (hd3d47d[jpd2f9a-1:2] == 6'b111111) begin sue0a13 <= 1; end else begin sue0a13 <= 0; end\r
- if (gd2641f) db1303b <= bn16774 + 8'd1; if (cmde2e8) zk79681 <= bn16774 + 8'd1; else if (mr7090a) zk79681 <= sh51f70; if (yz904b5) pf5a051 <= wy9dd30 + 8'd1; \r
- gq981de <= yz904b5; nec0ef1 <= yz8fb84; if (fnc2984[18]) begin rx_stat_vector <= {fnc2984[15:0], fn4059d[15:0]}; end vk3acd8 <= fnc2984[7:0]; vk8ceb3 <= pu300f8; rx_dbout <= fn74c03; bn9b0a1 <= os7dc24 & ~xw5d016 & ~fnc2984[19]; gqb3614 <= bn3e14; rx_write <= qv807c2; xjd850e <= yz8fb84 & fnc2984[18]; rx_stat_en <= ie1f0a6; rx_eof <= os7dc24 & fnc2984[17]; rx_error <= os7dc24 & fnc2984[16]; end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign nrf3885 = (hd3d47d[jpd2f9a-1:0] >= 7'h42);\r
-\r
-\r
-assign wy825ad = cmde2e8 & ~pffcf51;\r
-assign yz904b5 = pu14c26 & ~ph320fc & ~ba30990 & ~nt84c83;\r
-\r
-\r
-assign zm9c42e = yz8fb84 & fnc2984[18];\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign ou2e705 = (pu14c26 | rx_write) & xw5d016 & ~ph320fc & ~ba30990;\r
-\r
-always@* begin cmde2e8<=ea5c9d9[0];dmf1740<=ea5c9d9[1];zz8ba02<={ie9dcf2>>1,ea5c9d9[2]};xw5d016<=ea5c9d9[3];fn4059d<={ne73c82>>1,ea5c9d9[4]};bn16774<={zk79681>>1,ea5c9d9[5]};wy9dd30<={pf5a051>>1,ea5c9d9[6]};fn74c03<={vk8ceb3>>1,ea5c9d9[7]};pu300f8<={vk3acd8>>1,ea5c9d9[8]};qv807c2<=ea5c9d9[9];bn3e14<=ea5c9d9[10];ie1f0a6<=ea5c9d9[11];fnc2984<={ww77ce2>>1,ea5c9d9[12]};pu14c26<=ea5c9d9[13];yma6132<=ea5c9d9[14];ba30990<=ea5c9d9[15];nt84c83<=ea5c9d9[16];gd2641f<=ea5c9d9[17];ph320fc<=ea5c9d9[18];ux907e7<=ea5c9d9[19];gq1f9ea<={xy9c142>>1,ea5c9d9[20]};pffcf51<=ea5c9d9[21];hd3d47d<={jr284c0>>1,ea5c9d9[22]};sh51f70<={db1303b>>1,ea5c9d9[23]};yz8fb84<=ea5c9d9[24];os7dc24<=ea5c9d9[25];psee121<=ea5c9d9[26];mr7090a<=ea5c9d9[27];end\r
-always@* begin ec2b93b[2047]<=lq73b9e;ec2b93b[2046]<=ie9dcf2[0];ec2b93b[2044]<=rx_fifo_full;ec2b93b[2040]<=ne73c82[0];ec2b93b[2032]<=zk79681[0];ec2b93b[2017]<=pf5a051[0];ec2b93b[1987]<=vk8ceb3[0];ec2b93b[1926]<=vk3acd8[0];ec2b93b[1921]<=db1303b[0];ec2b93b[1805]<=gqb3614;ec2b93b[1795]<=gq981de;ec2b93b[1679]<=kde2173;ec2b93b[1562]<=bn9b0a1;ec2b93b[1543]<=nec0ef1;ec2b93b[1310]<=sw10b9c;ec2b93b[1144]<=ou2e705;ec2b93b[1076]<=xjd850e;ec2b93b[1039]<=gd778b;ec2b93b[1023]<=pf6e773;ec2b93b[960]<=jr284c0[0];ec2b93b[839]<=zm9c42e;ec2b93b[572]<=yz85ce0;ec2b93b[480]<=sue0a13;ec2b93b[419]<=nrf3885;ec2b93b[240]<=xy9c142[0];ec2b93b[209]<=uxbe710;ec2b93b[104]<=ww77ce2[0];ec2b93b[30]<=aa3bc5d;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module shc9dff (\r
-\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- nt32741,\r
-\r
- \r
- zx4ff6d,\r
- thec185,\r
- uve83d9,\r
- nt617c,\r
-\r
- \r
- fc30be7,\r
-\r
- \r
-\r
- qv278c,\r
- do9c880,\r
-\r
- \r
-\r
- vi7ceeb,\r
- uve775b,\r
- uk3badc,\r
- jpdd6e0,\r
- lqeb707,\r
- gb5b83a,\r
- ofdc1d5,\r
- yke0ead,\r
- cb7568,\r
- vk3ab45,\r
- psd5a2a,\r
- zmad152,\r
- qg68a93,\r
- vv45498\r
-\r
-);\r
-parameter ld6e960 = 8;\r
-parameter vi52632 = 14;\r
-parameter vk93192 = 16;\r
-parameter uk98c92 = 16;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input zx4ff6d;\r
-input thec185;\r
-input uve83d9;\r
-input nt617c;\r
-input do9c880;\r
-input qv278c;\r
-input [ld6e960-1:0] nt32741;\r
-input [vk93192-1:0] fc30be7;\r
-output vi7ceeb;\r
-output uve775b;\r
-output uk3badc;\r
-output ofdc1d5;\r
-output yke0ead;\r
-output cb7568;\r
-output psd5a2a;\r
-output qg68a93;\r
-output lqeb707;\r
-output vv45498;\r
-output [uk98c92-1:0] vk3ab45;\r
-output [vk93192-1:0] zmad152;\r
-output [vi52632-1:0] jpdd6e0;\r
-output [vi52632-1:0] gb5b83a;\r
-reg vi7ceeb;\r
-reg uve775b;\r
-reg uk3badc;\r
-reg ofdc1d5;\r
-reg yke0ead;\r
-reg cb7568;\r
-reg qg68a93;\r
-reg vv45498;\r
-reg [vi52632-1:0] gb5b83a;\r
-reg [vi52632-1:0] jpdd6e0;\r
-reg [vk93192-1:0] zmad152;\r
-reg [ld6e960-1:0] osfa629;\r
-wire psd5a2a;\r
-wire [uk98c92-1:0] vk3ab45;\r
-reg lqeb707;\r
-localparam su49815 = 16'h8808;\r
-localparam ww4c0a9 = 16'h8100;\r
-localparam al60548 = 16'd46;\r
-localparam wl2a45 = 16'd42;\r
-localparam uk1522c = 9;\r
-localparam qia9161 = 9'b000000001;\r
-localparam xw48b09 = 9'b000000010;\r
-localparam nr4584b = 9'b000000100;\r
-localparam gd2c25f = 9'b000001000;\r
-localparam xj612fd = 9'b000010000;\r
-localparam zz97ef = 9'b000100000;\r
-localparam yx4bf7e = 9'b001000000;\r
-localparam rt5fbf4 = 9'b010000000;\r
-localparam yxfdfa7 = 9'b100000000;\r
-wire qgefd3d;\r
-wire zx7e9e9;\r
-wire vif4f4e;\r
-wire pua7a73;\r
-wire nt3d39b;\r
-wire fne9cde;\r
-wire kd4e6f6;\r
-wire lq737b5;\r
-wire ph9bdab;\r
-reg [uk1522c-1:0] pff6af9;\r
-reg rvb57ce;\r
-reg gdabe76;\r
-reg xj5f3b5;\r
-reg rtf9dae;\r
-reg [uk1522c-1:0] xw76bb8;\r
-reg zkcf421;\r
-reg [ld6e960 - 1 : 0] nt842ea;\r
-reg qted1ff;\r
-reg pfc2f4a;\r
-reg rg5d58a;\r
-reg babd2b5;\r
-reg [vk93192 - 1 : 0] bl4ad57;\r
-reg me56abe;\r
-reg hdb55f1;\r
-reg [ld6e960 - 1 : 0] ne57c77;\r
-reg ohbe3bb;\r
-reg psf1ddd;\r
-reg vx8eeeb;\r
-reg qg7775e;\r
-reg cbbbaf1;\r
-reg vvdd78c;\r
-reg dmebc67;\r
-reg yx5e33b;\r
-reg xwf19dc;\r
-reg [uk1522c - 1 : 0] ww6771b;\r
-reg ks3b8d8;\r
-reg gbdc6c0;\r
-reg pfe3605;\r
-reg hq1b02e;\r
-reg [uk1522c - 1 : 0] nec0b97;\r
-reg ay5c4eb;\r
-reg [2047:0] ec2b93b;\r
-wire [24:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 25,ph27642 = 32'hfdffca8b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign qgefd3d = pfc2f4a && ({ne57c77, nt842ea} == su49815);\r
-assign zx7e9e9 = pfc2f4a && ({ne57c77, nt842ea} != su49815);\r
-\r
-\r
-\r
-\r
-assign vif4f4e = pfc2f4a && ({ne57c77, nt842ea} == ww4c0a9);\r
-\r
-\r
-\r
-\r
-\r
-assign pua7a73 = ((pfc2f4a & (ohbe3bb | (~ohbe3bb & ~vx8eeeb && {ne57c77, nt842ea} < al60548))) | (gbdc6c0 && {ne57c77, nt842ea} < wl2a45));\r
-\r
-\r
-\r
-\r
-\r
-assign lq737b5 = (hdb55f1 | me56abe) & pfe3605 && ({ne57c77, nt842ea} == bl4ad57);\r
-assign kd4e6f6 = pfe3605 && ({ne57c77, nt842ea} != bl4ad57);\r
-assign ph9bdab = me56abe & psf1ddd;\r
-\r
-\r
-\r
-\r
-assign nt3d39b = ((pfc2f4a & ~vx8eeeb) | (gbdc6c0) && {ne57c77, nt842ea} >= 16'h0600);\r
-\r
-\r
-\r
-assign fne9cde = pfc2f4a & ~ohbe3bb;\r
-\r
-assign psd5a2a = ks3b8d8; \r
-assign vk3ab45 = {ne57c77, nt842ea}; \r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin vi7ceeb <= 1'b0; uve775b <= 1'b0; uk3badc <= 1'b0; ofdc1d5 <= 1'b0; yke0ead <= 1'b0; cb7568 <= 1'b0; jpdd6e0 <= 14'b0; gb5b83a <= 14'b0; zmad152 <= 16'b0; zkcf421 <= 1'b0; xw76bb8 <= qia9161; qg68a93 <= 1'b0; vv45498 <= 1'b0; lqeb707 <= 1'b0; osfa629 <= 0; end else if (rxmac_clk_en) begin\r
- osfa629 <= nt842ea; zkcf421 <= rg5d58a; lqeb707 <= (pfc2f4a & ~vx8eeeb) | gbdc6c0; if (ay5c4eb) xw76bb8 <= qia9161; else begin xw76bb8 <= ww6771b; if (babd2b5) gb5b83a <= gb5b83a - 14'd1; end if (pfc2f4a && ohbe3bb) gb5b83a <= 14'd46; else if ((pfc2f4a && !uk3badc) || gbdc6c0) begin jpdd6e0 <= {ne57c77[5:0], nt842ea}; gb5b83a <= {ne57c77[5:0], nt842ea}; end if (hq1b02e) zmad152 <= {ne57c77, nt842ea}; if (vvdd78c) vi7ceeb <= vvdd78c; else if (qted1ff) vi7ceeb <= 1'b0; else vi7ceeb <= vi7ceeb; if (ohbe3bb) uve775b <= ohbe3bb; else if (qted1ff) uve775b <= 1'b0; else uve775b <= uve775b; if (cbbbaf1) cb7568 <= cbbbaf1; else if (qted1ff) cb7568 <= 1'b0; else cb7568 <= cb7568; if (qg7775e) yke0ead <= qg7775e; else if (qted1ff) yke0ead <= 1'b0; else yke0ead <= yke0ead; if (yx5e33b) ofdc1d5 <= yx5e33b; else if (qted1ff) ofdc1d5 <= 1'b0; else ofdc1d5 <= ofdc1d5; if (dmebc67) qg68a93 <= dmebc67; else if (qted1ff) qg68a93 <= 1'b0; else qg68a93 <= qg68a93; if (xwf19dc) vv45498 <= xwf19dc; else if (qted1ff) vv45498 <= 1'b0; else vv45498 <= vv45498; if (vx8eeeb) uk3badc <= vx8eeeb; else if (qted1ff) uk3badc <= 1'b0; else uk3badc <= uk3badc; end\r
-end\r
-\r
-always @ (nec0b97 or pfc2f4a or vx8eeeb or ohbe3bb or dmebc67) begin case (nec0b97) qia9161 : begin if (pfc2f4a && vx8eeeb) begin pff6af9 = xw48b09; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end else if (pfc2f4a && ohbe3bb) begin pff6af9 = zz97ef; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end else begin pff6af9 = qia9161; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end end xw48b09 : begin pff6af9 = nr4584b; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end nr4584b : begin pff6af9 = gd2c25f; rvb57ce = 1'b1; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end gd2c25f : begin pff6af9 = xj612fd; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end xj612fd : begin pff6af9 = qia9161; rvb57ce = 1'b0; gdabe76 = 1'b1; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end zz97ef : begin pff6af9 = yx4bf7e; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end yx4bf7e : begin if (dmebc67) begin pff6af9 = qia9161; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b1; rtf9dae = 1'b0; end else begin pff6af9 = rt5fbf4; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b1; rtf9dae = 1'b0; end end rt5fbf4 : begin pff6af9 = yxfdfa7; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end yxfdfa7 : begin pff6af9 = qia9161; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b1; end default : begin pff6af9 = qia9161; rvb57ce = 1'b0; gdabe76 = 1'b0; xj5f3b5 = 1'b0; rtf9dae = 1'b0; end endcase\r
-end\r
-always@* begin nt842ea<={nt32741>>1,ea5c9d9[0]};qted1ff<=ea5c9d9[1];pfc2f4a<=ea5c9d9[2];rg5d58a<=ea5c9d9[3];babd2b5<=ea5c9d9[4];bl4ad57<={fc30be7>>1,ea5c9d9[5]};me56abe<=ea5c9d9[6];hdb55f1<=ea5c9d9[7];ne57c77<={osfa629>>1,ea5c9d9[8]};ohbe3bb<=ea5c9d9[9];psf1ddd<=ea5c9d9[10];vx8eeeb<=ea5c9d9[11];qg7775e<=ea5c9d9[12];cbbbaf1<=ea5c9d9[13];vvdd78c<=ea5c9d9[14];dmebc67<=ea5c9d9[15];yx5e33b<=ea5c9d9[16];xwf19dc<=ea5c9d9[17];ww6771b<={pff6af9>>1,ea5c9d9[18]};ks3b8d8<=ea5c9d9[19];gbdc6c0<=ea5c9d9[20];pfe3605<=ea5c9d9[21];hq1b02e<=ea5c9d9[22];nec0b97<={xw76bb8>>1,ea5c9d9[23]};ay5c4eb<=ea5c9d9[24];end\r
-always@* begin ec2b93b[2047]<=zx4ff6d;ec2b93b[2046]<=thec185;ec2b93b[2044]<=uve83d9;ec2b93b[2040]<=nt617c;ec2b93b[2032]<=fc30be7[0];ec2b93b[2017]<=qv278c;ec2b93b[1987]<=do9c880;ec2b93b[1926]<=osfa629[0];ec2b93b[1804]<=qgefd3d;ec2b93b[1803]<=xw76bb8[0];ec2b93b[1560]<=zx7e9e9;ec2b93b[1558]<=zkcf421;ec2b93b[1550]<=lq737b5;ec2b93b[1072]<=vif4f4e;ec2b93b[1052]<=ph9bdab;ec2b93b[1023]<=nt32741[0];ec2b93b[901]<=rtf9dae;ec2b93b[775]<=kd4e6f6;ec2b93b[450]<=xj5f3b5;ec2b93b[387]<=fne9cde;ec2b93b[225]<=gdabe76;ec2b93b[193]<=nt3d39b;ec2b93b[112]<=rvb57ce;ec2b93b[96]<=pua7a73;ec2b93b[56]<=pff6af9[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module icce60c (\r
- vi73061, \r
- ou9830b, \r
- ykc1859,\r
- rvc2c9,\r
- nr6164e,\r
- vkb277,\r
- ui593bb,\r
- wjc9dd9,\r
- en4eecd,\r
- rxmac_clk_en,\r
- gdbb361\r
- );\r
-output [5:0] vi73061;\r
-output ou9830b;\r
-input [7:0] ykc1859;\r
-input [31:0] wjc9dd9;\r
-input rvc2c9;\r
-input nr6164e;\r
-input vkb277;\r
-input ui593bb;\r
-input en4eecd;\r
-input rxmac_clk_en;\r
-input gdbb361;\r
-reg [31:0] jp50046;\r
-reg [5:0] vi73061;\r
-reg ou9830b;\r
-wire [31:0] cb8de2;\r
-wire [31:0] yk46f15;\r
-reg [7 : 0] nt378a8;\r
-reg ymbc546;\r
-reg ofe2a30;\r
-reg co15185;\r
-reg doa8c29;\r
-reg [31 : 0] su4614a;\r
-reg [31 : 0] tw30a51;\r
-reg [31 : 0] an8528b;\r
-reg [31 : 0] cb2945c;\r
-reg [2047:0] ec2b93b;\r
-wire [8:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 9,ph27642 = 32'hfdffe06b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-assign yk46f15[0] = ~tw30a51[0];\r
-assign yk46f15[1] = ~tw30a51[1];\r
-assign yk46f15[2] = tw30a51[2];\r
-assign yk46f15[3] = ~tw30a51[3];\r
-assign yk46f15[4] = ~tw30a51[4];\r
-assign yk46f15[5] = ~tw30a51[5];\r
-assign yk46f15[6] = ~tw30a51[6];\r
-assign yk46f15[7] = tw30a51[7];\r
-assign yk46f15[8] = ~tw30a51[8];\r
-assign yk46f15[9] = tw30a51[9];\r
-assign yk46f15[10] = ~tw30a51[10];\r
-assign yk46f15[11] = ~tw30a51[11];\r
-assign yk46f15[12] = ~tw30a51[12];\r
-assign yk46f15[13] = tw30a51[13];\r
-assign yk46f15[14] = ~tw30a51[14];\r
-assign yk46f15[15] = ~tw30a51[15];\r
-assign yk46f15[16] = tw30a51[16];\r
-assign yk46f15[17] = tw30a51[17];\r
-assign yk46f15[18] = ~tw30a51[18];\r
-assign yk46f15[19] = tw30a51[19];\r
-assign yk46f15[20] = tw30a51[20];\r
-assign yk46f15[21] = tw30a51[21];\r
-assign yk46f15[22] = tw30a51[22];\r
-assign yk46f15[23] = tw30a51[23];\r
-assign yk46f15[24] = ~tw30a51[24];\r
-assign yk46f15[25] = ~tw30a51[25];\r
-assign yk46f15[26] = ~tw30a51[26];\r
-assign yk46f15[27] = tw30a51[27];\r
-assign yk46f15[28] = tw30a51[28];\r
-assign yk46f15[29] = tw30a51[29];\r
-assign yk46f15[30] = ~tw30a51[30];\r
-assign yk46f15[31] = ~tw30a51[31];\r
-\r
-always @ (posedge en4eecd or negedge gdbb361)\r
-begin if (!gdbb361) begin jp50046 <= 32'hffffffff; vi73061 <= 6'b000000; ou9830b <= 0; end else if (rxmac_clk_en) begin if (ymbc546) begin jp50046 <= an8528b; end else if (doa8c29) begin jp50046 <= su4614a; end if (ofe2a30) begin vi73061[5] <= an8528b[30]; vi73061[4] <= an8528b[29]; vi73061[3] <= an8528b[28]; vi73061[2] <= an8528b[27]; vi73061[1] <= an8528b[26]; vi73061[0] <= an8528b[25]; end if (co15185) begin if (cb2945c == 0) begin ou9830b <= 0; end else begin ou9830b <= 1; end end else if (doa8c29) begin ou9830b <= 0; end end\r
-end\r
-\r
-assign cb8de2[0] = tw30a51[30] ^ nt378a8[7] ^ nt378a8[1] ^ tw30a51[24];\r
-assign cb8de2[1] = tw30a51[30] ^ nt378a8[6] ^ nt378a8[7] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[25];\r
-assign cb8de2[2] = tw30a51[30] ^ nt378a8[6] ^ nt378a8[7] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[25] ^ tw30a51[26] ^ nt378a8[5];\r
-assign cb8de2[3] = tw30a51[31] ^ nt378a8[0] ^ tw30a51[25] ^ tw30a51[26] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ nt378a8[6];\r
-assign cb8de2[4] = tw30a51[30] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ tw30a51[28] ^ nt378a8[7];\r
-assign cb8de2[5] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[25] ^ nt378a8[2] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[28] ^ nt378a8[6] ^ tw30a51[29] ^ nt378a8[7];\r
-assign cb8de2[6] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[25] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[5] ^ tw30a51[28] ^ nt378a8[6] ^ tw30a51[29];\r
-assign cb8de2[7] = tw30a51[31] ^ nt378a8[0] ^ tw30a51[24] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ tw30a51[29] ^ nt378a8[7];\r
-assign cb8de2[8] = tw30a51[24] ^ tw30a51[25] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[28] ^ nt378a8[6] ^ nt378a8[7] ^ tw30a51[0];\r
-assign cb8de2[9] = tw30a51[25] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[5] ^ tw30a51[28] ^ nt378a8[6] ^ tw30a51[29] ^ tw30a51[1];\r
-assign cb8de2[10] = tw30a51[24] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ tw30a51[29] ^ nt378a8[7] ^ tw30a51[2];\r
-assign cb8de2[11] = tw30a51[3] ^ tw30a51[24] ^ tw30a51[25] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[28] ^ nt378a8[6] ^ nt378a8[7];\r
-assign cb8de2[12] = tw30a51[30] ^ tw30a51[4] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[25] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[5] ^ tw30a51[28] ^ nt378a8[6] ^ tw30a51[29] ^ nt378a8[7];\r
-assign cb8de2[13] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ tw30a51[5] ^ nt378a8[1] ^ tw30a51[25] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ nt378a8[6] ^ tw30a51[29];\r
-assign cb8de2[14] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[6] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ tw30a51[28];\r
-assign cb8de2[15] = tw30a51[31] ^ nt378a8[0] ^ nt378a8[2] ^ tw30a51[7] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[28] ^ tw30a51[29];\r
-assign cb8de2[16] = tw30a51[24] ^ nt378a8[2] ^ nt378a8[3] ^ tw30a51[8] ^ tw30a51[28] ^ tw30a51[29] ^ nt378a8[7];\r
-assign cb8de2[17] = tw30a51[30] ^ nt378a8[1] ^ tw30a51[25] ^ nt378a8[2] ^ tw30a51[9] ^ nt378a8[6] ^ tw30a51[29];\r
-assign cb8de2[18] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[26] ^ nt378a8[5] ^ tw30a51[10];\r
-assign cb8de2[19] = tw30a51[31] ^ nt378a8[0] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[11];\r
-assign cb8de2[20] = tw30a51[12] ^ nt378a8[3] ^ tw30a51[28];\r
-assign cb8de2[21] = tw30a51[13] ^ nt378a8[2] ^ tw30a51[29];\r
-assign cb8de2[22] = tw30a51[14] ^ tw30a51[24] ^ nt378a8[7];\r
-assign cb8de2[23] = tw30a51[30] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[15] ^ tw30a51[25] ^ nt378a8[6] ^ nt378a8[7];\r
-assign cb8de2[24] = tw30a51[31] ^ nt378a8[0] ^ tw30a51[25] ^ tw30a51[16] ^ tw30a51[26] ^ nt378a8[5] ^ nt378a8[6];\r
-assign cb8de2[25] = tw30a51[26] ^ tw30a51[17] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5];\r
-assign cb8de2[26] = tw30a51[30] ^ nt378a8[1] ^ tw30a51[24] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[18] ^ tw30a51[28] ^ nt378a8[7];\r
-assign cb8de2[27] = tw30a51[31] ^ nt378a8[0] ^ tw30a51[25] ^ nt378a8[2] ^ nt378a8[3] ^ tw30a51[28] ^ tw30a51[19] ^ nt378a8[6] ^ tw30a51[29];\r
-assign cb8de2[28] = tw30a51[30] ^ nt378a8[1] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[5] ^ tw30a51[29] ^ tw30a51[20];\r
-assign cb8de2[29] = tw30a51[30] ^ tw30a51[21] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ nt378a8[4] ^ tw30a51[27];\r
-assign cb8de2[30] = tw30a51[31] ^ tw30a51[22] ^ nt378a8[0] ^ nt378a8[3] ^ tw30a51[28];\r
-assign cb8de2[31] = tw30a51[23] ^ nt378a8[2] ^ tw30a51[29];\r
-always@* begin nt378a8<={ykc1859>>1,ea5c9d9[0]};ymbc546<=ea5c9d9[1];ofe2a30<=ea5c9d9[2];co15185<=ea5c9d9[3];doa8c29<=ea5c9d9[4];su4614a<={wjc9dd9>>1,ea5c9d9[5]};tw30a51<={jp50046>>1,ea5c9d9[6]};an8528b<={cb8de2>>1,ea5c9d9[7]};cb2945c<={yk46f15>>1,ea5c9d9[8]};end\r
-always@* begin ec2b93b[2047]<=rvc2c9;ec2b93b[2046]<=nr6164e;ec2b93b[2044]<=vkb277;ec2b93b[2041]<=ui593bb;ec2b93b[2034]<=wjc9dd9[0];ec2b93b[2021]<=jp50046[0];ec2b93b[1995]<=cb8de2[0];ec2b93b[1943]<=yk46f15[0];ec2b93b[1023]<=ykc1859[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ri351a3 (\r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- mtbb27f, \r
- ou1a400, \r
- xjd2000, \r
- mt90006, \r
- gd80035,\r
-\r
- \r
- nt32741,\r
- qtedba5,\r
- su6dd2c,\r
- offdb74,\r
-\r
- \r
- lqe4402,\r
- hd22013,\r
- uk1009e,\r
- sj804f1,\r
-\r
- \r
- vi7ceeb,\r
- uve775b,\r
- uk3badc,\r
- jpdd6e0,\r
- ofdc1d5,\r
- yke0ead,\r
- cb7568,\r
- qg68a93,\r
- lqeb707,\r
- gb5b83a,\r
- fpa0744,\r
-\r
- \r
- ignore_pkt,\r
-\r
- \r
- mt1d13e,\r
- kde89f5,\r
- yx44fac,\r
- rv27d65,\r
- aa3eb2f,\r
- cmf5978,\r
-\r
- \r
- ou9830b,\r
-\r
- \r
- zx4ff6d,\r
- uve83d9,\r
-\r
- \r
- qg78222,\r
- ayc1110,\r
- cb8880,\r
-\r
- \r
- shc9fed,\r
- db2202c,\r
-\r
- \r
- ou10166,\r
-\r
- \r
- thec185,\r
- nt617c,\r
-\r
- \r
- ie9dcf2,\r
- pf6e773,\r
- lq73b9e,\r
-\r
- \r
- uk8d311,\r
- ukb3910,\r
- vkb277,\r
- me62210\r
-);\r
-parameter ld6e960 = 8;\r
-parameter vi52632 = 14;\r
-parameter xwfb4be = 20;\r
-parameter jcda5f3 = 32;\r
-parameter gd80619 = 32;\r
-parameter zz30cc = 9;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input mtbb27f;\r
-input ou1a400;\r
-input xjd2000;\r
-input mt90006;\r
-input gd80035;\r
-input su6dd2c;\r
-input offdb74;\r
-input qtedba5;\r
-input [ld6e960-1:0] nt32741;\r
-input lqe4402;\r
-input hd22013;\r
-input uk1009e;\r
-input sj804f1;\r
-input vi7ceeb;\r
-input uve775b;\r
-input uk3badc;\r
-input ofdc1d5;\r
-input fpa0744;\r
-input yke0ead;\r
-input cb7568;\r
-input qg68a93;\r
-input lqeb707;\r
-input [vi52632-1:0] gb5b83a;\r
-input [vi52632-1:0] jpdd6e0;\r
-input ignore_pkt;\r
-input mt1d13e;\r
-input kde89f5;\r
-input [vi52632-1:0] yx44fac;\r
-input rv27d65;\r
-input aa3eb2f;\r
-input cmf5978;\r
-input ou9830b;\r
-output zx4ff6d;\r
-output shc9fed;\r
-output db2202c;\r
-output thec185;\r
-output pf6e773;\r
-output lq73b9e;\r
-output uve83d9;\r
-output nt617c;\r
-output [xwfb4be-1:0] ie9dcf2;\r
-output qg78222;\r
-output [zz30cc-1:0] ayc1110;\r
-output cb8880;\r
-output ou10166;\r
-output [gd80619-1:0] uk8d311;\r
-output ukb3910;\r
-output vkb277;\r
-output me62210;\r
-wire zx4ff6d;\r
-wire thec185;\r
-wire pf6e773;\r
-wire lq73b9e;\r
-wire [xwfb4be-1:0] ie9dcf2;\r
-reg qg78222;\r
-wire [gd80619-1:0] uk8d311;\r
-wire ukb3910;\r
-wire me62210;\r
-reg ou10166;\r
-reg [zz30cc-1:0] ayc1110;\r
-reg cb8880;\r
-localparam cme53cb = 8;\r
-localparam mt29e59 = 8'b00000001;\r
-localparam pf4f2cc = 8'b00000010;\r
-localparam zk79667 = 8'b00000100;\r
-localparam uicb33a = 8'b00001000;\r
-localparam me599d1 = 8'b00010000;\r
-localparam gbcce88 = 8'b00100000;\r
-localparam ea67445 = 8'b01000000;\r
-localparam xy3a228 = 8'b10000000;\r
-localparam icd1143 = 1'b0;\r
-localparam ym88a19 = 1'b1;\r
-reg [cme53cb-1:0] ph2864e;\r
-reg shc9fed;\r
-reg ph193b9;\r
-reg ipc9dcf;\r
-reg wj4ee7d;\r
-reg yk773ec;\r
-reg uve83d9;\r
-wire zkcfb09;\r
-wire nt617c;\r
-wire dzec251;\r
-wire zx6128f;\r
-wire ph947f;\r
-wire xj4a3fe;\r
-wire [vi52632-1:0] cb8ffbc;\r
-wire wj7fde4;\r
-wire xwfef24;\r
-reg [cme53cb-1:0] ukbc914;\r
-reg lqe48a1;\r
-reg aa2450a;\r
-reg [2:0] xl22851;\r
-reg xy1428f;\r
-reg qva147b;\r
-reg [vi52632-1:0] yx51ee9;\r
-reg [vi52632-1:0] pf7ba65;\r
-reg vvdd32e;\r
-reg fne9977;\r
-reg ic4cbbe;\r
-reg wj65df1;\r
-reg [vi52632-1:0] ay77c61;\r
-reg anbe308;\r
-reg hof1845;\r
-reg hq8c22b;\r
-reg ld6115a;\r
-reg gd8ad7;\r
-reg [vi52632-1:0] ec2b5ee;\r
-reg [vi52632-1:0] rtd7b87;\r
-wire twbdc3f;\r
-wire dmee1fb;\r
-wire uv70fda;\r
-wire gq87ed5;\r
-wire xy3f6a8;\r
-wire jcfb543;\r
-wire bydaa1b;\r
-reg [xwfb4be-1:0] fca86db;\r
-reg me436db;\r
-wire xy1b6d9;\r
-wire osdb6ca;\r
-wire [jcda5f3-1:0] qgdb280;\r
-wire db2202c;\r
-reg jcca005;\r
-reg fn5002b;\r
-reg cb8015f;\r
-reg aa3bc5d;\r
-reg co57e1;\r
-reg qi2bf08;\r
-reg [ld6e960-1:0] ldfc20f;\r
-reg nee107e ;\r
-reg wl83f3;\r
-reg al41f9c;\r
-reg ecfce5;\r
-reg [4:0] nr7e728;\r
-reg jpf3947;\r
-reg mgb9e84;\r
-wire ice51f2;\r
-reg jr28f91;\r
-wire vkb277;\r
-reg qi3e472;\r
-wire gbf2391;\r
-wire bn91c8d;\r
-wire tj8e46e;\r
-wire ea72377;\r
-wire lf91bb9;\r
-reg sw8ddce;\r
-reg zx6ee71;\r
-reg qg7738f;\r
-reg aab9c79;\r
-reg goce3c9;\r
-reg hb71e49;\r
-reg ir8f24f;\r
-reg vi7927d;\r
-wire [zz30cc-1:0] cm49f54;\r
-reg [3:0] bl4faa1;\r
-reg me7d50e;\r
-reg uiea870;\r
-reg en54381;\r
-reg ks109ed;\r
-reg vke06c;\r
-reg wj70363;\r
-reg vx81b1c;\r
-reg sjd8e7;\r
-reg [ld6e960 - 1 : 0] nt842ea;\r
-reg aa21756;\r
-reg cze7ade;\r
-reg nt3d6f5;\r
-reg dmeb7ae;\r
-reg uv5bd72;\r
-reg uideb95;\r
-reg uif5ca9;\r
-reg irae549;\r
-reg go72a4c;\r
-reg wl95260;\r
-reg [vi52632 - 1 : 0] ui49829;\r
-reg me4c149;\r
-reg yx60a48;\r
-reg aa5244;\r
-reg cb29220;\r
-reg os49105;\r
-reg [vi52632 - 1 : 0] kd44143;\r
-reg do20a1c;\r
-reg ou50e2;\r
-reg lf28710;\r
-reg ic43887;\r
-reg [vi52632 - 1 : 0] ipe21c7;\r
-reg co10e3c;\r
-reg ym871e0;\r
-reg rv38f01;\r
-reg pfc780f;\r
-reg [cme53cb - 1 : 0] qge03f4;\r
-reg tw1fa1;\r
-reg aafd0b;\r
-reg hb7e858;\r
-reg hof42c6;\r
-reg epa1632;\r
-reg bab195;\r
-reg rg58cab;\r
-reg uvc655a;\r
-reg lf32ad5;\r
-reg [vi52632 - 1 : 0] qvab575;\r
-reg vv5abac;\r
-reg dmd5d67;\r
-reg [cme53cb - 1 : 0] mr759d5;\r
-reg ukacead;\r
-reg yk67568;\r
-reg [2 : 0] ba3ab40;\r
-reg lqd5a02;\r
-reg twad012;\r
-reg [vi52632 - 1 : 0] fn40499;\r
-reg [vi52632 - 1 : 0] ep12675;\r
-reg pu933ac;\r
-reg zm99d62;\r
-reg eaceb12;\r
-reg mr75890;\r
-reg [vi52632 - 1 : 0] cm62429;\r
-reg ir12148;\r
-reg wl90a44;\r
-reg ep85224;\r
-reg ir29124;\r
-reg lq48925;\r
-reg [vi52632 - 1 : 0] ie2495d;\r
-reg [vi52632 - 1 : 0] hq25740;\r
-reg ym2ba03;\r
-reg jc5d019;\r
-reg mre80cb;\r
-reg th4065d;\r
-reg zz32ee;\r
-reg zz19777;\r
-reg iccbbbf;\r
-reg [xwfb4be - 1 : 0] tueefc2;\r
-reg ui77e13;\r
-reg fpbf098;\r
-reg wjf84c7;\r
-reg [jcda5f3 - 1 : 0] zz131e7;\r
-reg aa98f3e;\r
-reg pfc79f0;\r
-reg sj3cf86;\r
-reg mr7090a;\r
-reg ou3e1ad;\r
-reg osf0d69;\r
-reg [ld6e960 - 1 : 0] ls35a4a;\r
-reg ngad253;\r
-reg zk6929b;\r
-reg qg494db;\r
-reg fn4a6d8;\r
-reg [4 : 0] ww536c7;\r
-reg fp9b638;\r
-reg xweb89d;\r
-reg pfd8e30;\r
-reg fnc7186;\r
-reg vx38c37;\r
-reg uvc61bf;\r
-reg je30dfd;\r
-reg xy86feb;\r
-reg fp37f5a;\r
-reg phbfad6;\r
-reg uvfd6b6;\r
-reg hoeb5b4;\r
-reg bl5ada2;\r
-reg ald6d17;\r
-reg mgb68bd;\r
-reg sjb45e8;\r
-reg nga2f44;\r
-reg wl17a23;\r
-reg [zz30cc - 1 : 0] ipe88ea;\r
-reg [3 : 0] ip44754;\r
-reg oh23aa4;\r
-reg ep1d525;\r
-reg wwea92d;\r
-reg [2047:0] ec2b93b;\r
-wire [111:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 112,ph27642 = 32'hfdffca8b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
-\r
-\r
- \r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
- \r
- \r
- \r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin bl4faa1 <= 4'h0; me7d50e <= icd1143; uiea870 <= 1'b0; en54381 <= 1'b0; end else if (rxmac_clk_en) begin\r
- en54381 <= ep1d525;\r
- case (oh23aa4) icd1143 : begin uiea870 <= 1'b0; if (aa21756 && fp9b638) begin bl4faa1 <= ip44754 + 1; me7d50e <= ym88a19; end else begin bl4faa1 <= 4'h0; me7d50e <= icd1143; end end ym88a19 : begin if (fp9b638) begin if (ip44754 <= 4'd12 ) begin bl4faa1 <= ip44754 + 1; me7d50e <= ym88a19; end else begin me7d50e <= icd1143; end end else begin if (~ww536c7[3] & ww536c7[4]) begin me7d50e <= icd1143; end if (ip44754 <= 4'd12) begin uiea870 <= 1'b1; end else begin uiea870 <= 1'b0; end end end default : begin bl4faa1 <= 4'h0; uiea870 <= 1'b0; me7d50e <= icd1143; end\r
- endcase end \r
-\r
-end \r
-\r
-\r
-\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin hof1845 <= 1'b0; hq8c22b <= 1'b0; ukbc914 <= mt29e59; xl22851 <= 3'b000; xy1428f <= 1'b0; jpf3947 <= 1'b0; nee107e <= 1'b0; wl83f3 <= 1'b0; fne9977 <= 1'b0; ic4cbbe <= 1'b0; wj65df1 <= 1'b0; anbe308 <= 1'b0; ir8f24f <= 1'b0; vi7927d <= 1'b0; qva147b <= 1'b0; end else if (rxmac_clk_en) begin ir8f24f <= ym871e0; vi7927d <= nga2f44; if (ir12148) wj65df1 <= ir12148; else if (zx4ff6d) wj65df1 <= 1'b0; else if (uv5bd72) wj65df1 <= 1'b0; else wj65df1 <= mr75890; anbe308 <= dmeb7ae; fne9977 <= ou50e2; ic4cbbe <= zm99d62; hof1845 <= uv5bd72; hq8c22b <= wl90a44; jpf3947 <= ks109ed; nee107e <= fp9b638; wl83f3 <= ngad253; xy1428f <= dmeb7ae | (lqd5a02 & ~epa1632); qva147b <= tw1fa1; if(bab195) xl22851 <= ba3ab40 + 2'd1; else if (zx4ff6d) xl22851 <= 3'b000; ukbc914 <= qge03f4; end\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign thec185 = twad012;\r
-\r
-assign dzec251 = lqd5a02 | dmeb7ae;\r
-assign zkcfb09 = ba3ab40[2] & ~ba3ab40[1] & ba3ab40[0];\r
-\r
-always @ (mr759d5 or wl17a23 or ks109ed or fp9b638 or aa21756 or cze7ade or dmeb7ae or uv5bd72 or epa1632 or irae549 or go72a4c or eaceb12) begin case (mr759d5) mt29e59 : begin if (!(wl17a23 && ks109ed)) begin ph2864e = mt29e59; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b1; end else begin if(!eaceb12) yk773ec = 1'b0; else yk773ec = 1'b1; ph2864e = pf4f2cc; shc9fed = 1'b1; ph193b9 = 1'b0; wj4ee7d = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end end pf4f2cc : begin if (cze7ade) begin ph2864e = uicb33a; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b1; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end else if (aa21756) begin ph2864e = zk79667; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end else if (!ks109ed) begin ph2864e = mt29e59; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end else begin ph2864e = pf4f2cc; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end end zk79667 : begin if (dmeb7ae) begin ph2864e = me599d1; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end else if (uv5bd72) begin ph2864e = uicb33a; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end else if (!fp9b638) begin ph2864e = mt29e59; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b1; ipc9dcf = 1'b0; end else begin ph2864e = zk79667; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end end uicb33a : begin if (!ks109ed) begin ph2864e = mt29e59; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end else begin ph2864e = uicb33a; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end end me599d1 : begin if (epa1632) begin ph2864e = gbcce88; shc9fed = 1'b0; ph193b9 = 1'b1; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end else if (!fp9b638) begin ph2864e = mt29e59; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b1; ipc9dcf = 1'b0; end else begin ph2864e = me599d1; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end end gbcce88 : begin if(irae549 || go72a4c) begin ph2864e = ea67445; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end else if (!ks109ed) begin ph2864e = mt29e59; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b1; ipc9dcf = 1'b0; end else begin ph2864e = gbcce88; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end end ea67445 : begin if (!fp9b638) begin ph2864e = xy3a228; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end else begin ph2864e = ea67445; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end end xy3a228 : begin ph2864e = mt29e59; shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end default : begin ph2864e = mt29e59;\r
- shc9fed = 1'b0; ph193b9 = 1'b0; wj4ee7d = 1'b0; yk773ec = 1'b0; uve83d9 = 1'b0; ipc9dcf = 1'b0; end endcase\r
-end\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign suef5cd = ks109ed;\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin jcca005 <= 0; fn5002b <= 0; lqe48a1 <= 1'b0; aa2450a <= 1'b0; ldfc20f <= 8'h00; cb8015f <= 1'b0; aa3bc5d <= 1'b0; co57e1 <= 1'b0; qi2bf08 <= 1'b0; ecfce5 <= 1'b0; qg78222 <= 1'b0; nr7e728[0] <= 1'b0; nr7e728[1] <= 1'b0; nr7e728[2] <= 1'b0; nr7e728[3] <= 1'b0; nr7e728[4] <= 1'b0; end else if (rxmac_clk_en) begin nr7e728[0] <= ngad253; nr7e728[1] <= ww536c7[0]; nr7e728[2] <= ww536c7[1]; nr7e728[3] <= ww536c7[2]; nr7e728[4] <= ww536c7[3]; if (fpbf098) ecfce5 <= fpbf098; else if (zx4ff6d) ecfce5 <= 1'b0; else ecfce5 <= fn4a6d8; co57e1 <= zz32ee; qi2bf08 <= ou3e1ad; qg78222 <= aafd0b & ~ou3e1ad; cb8015f <= zx4ff6d; aa3bc5d <= lq73b9e; ldfc20f <= nt842ea; jcca005 <= suef5cd; fn5002b <= ui77e13; if (yx60a48) lqe48a1 <= os49105 | (ukacead & ui77e13); else lqe48a1 <= os49105 | (ukacead & aa98f3e); aa2450a <= aa21756 | (yk67568 & ym2ba03 & ~(uv5bd72 & ~wl90a44)); end\r
-end\r
-\r
-\r
-\r
-assign nt617c = ukacead | os49105;\r
-assign dmee1fb = (kd44143 == 14'd1);\r
-\r
-always @ (suef5cd or nt617c or jc5d019) begin casex ({nt617c, (jc5d019 & co10e3c)}) 2'b0x : me436db = suef5cd; 2'b11 : me436db = 0; default : me436db = suef5cd; endcase\r
-end\r
-\r
-assign twbdc3f = (yx60a48) ? pfc79f0 : vke06c;\r
-assign uv70fda = ~uvfd6b6 & yk67568;\r
-assign xy3f6a8 = yk67568;\r
-assign gq87ed5 = (zx4ff6d & ~lq73b9e) | (sj3cf86 & ~mr7090a);\r
-assign pf6e773 = mre80cb | th4065d;\r
-assign bydaa1b = zx4ff6d | sj3cf86;\r
-always @ (zx4ff6d or sj3cf86 or zz131e7 or mgb68bd) begin case({zx4ff6d, sj3cf86}) 2'b10 : fca86db = {2'b11,1'b0,1'b0,zz131e7[31:16]}; 2'b01 : fca86db = {2'b10,1'b1,mgb68bd,zz131e7[15:0]}; default : fca86db = 20'bxxxxxxxxxxxxxxxxxxxx; endcase\r
-end\r
-assign ie9dcf2[19:0] = iccbbbf ? tueefc2[19:0] : {12'h000, ls35a4a};\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign xy1b6d9 = (~ngad253 & zk6929b) & ou3e1ad;\r
-assign osdb6ca = fpbf098 | fn4a6d8;\r
-assign zx4ff6d = wjf84c7 ? osf0d69 & ~ou3e1ad : mr75890 & ~cze7ade & ~wl90a44 & ~ww536c7[3] & ww536c7[4];\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign jcfb543 = (ep12675 >= 14'd64);\r
-\r
-\r
-\r
-\r
-assign lq73b9e = ((~lf28710) ? (zx4ff6d & ~qg494db) : 1'b0) | (wl90a44 & ~ep85224) | (ep1d525 & ~wwea92d) | (rv38f01 & go72a4c & zx4ff6d) | (do20a1c & zx4ff6d);\r
-\r
-assign zx6128f = aa21756 | (pu933ac & aa98f3e);\r
-\r
-\r
-assign ph947f = nt617c;\r
-assign xj4a3fe = nt617c & zz32ee;\r
-\r
-\r
-assign cb8ffbc = (~yx60a48) ? cm62429 -14'd4 : hq25740;\r
-\r
-assign uk8d311 = 32'hffffffff;\r
-\r
-assign me62210 = shc9fed;\r
-assign vkb277 = ~fp9b638 & ngad253;\r
-\r
-assign ukb3910 = aa21756 | vx38c37;\r
-\r
-\r
-\r
-assign ice51f2 = ic43887 & me4c149 & fnc7186 & qg494db & ~(ald6d17 | pfc780f);\r
-\r
-always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin gd8ad7 <= 1'b0; ld6115a <= 1'b0; ec2b5ee <= 14'b0; yx51ee9 <= 14'b0; pf7ba65 <= 14'b0; vvdd32e <= 1'b0; al41f9c <= 1'b0; qi3e472 <= 1'b0; zx6ee71 <= 1'b0; qg7738f <= 1'b0; aab9c79 <= 1'b0; goce3c9 <= 1'b0; jr28f91 <= 1'b0; ou10166 <= 1'b0; sw8ddce <= 1'b0; ay77c61 <= 14'd0; rtd7b87 <= 14'd0; ayc1110 <= 9'd0; cb8880 <= 1'b0; hb71e49 <= 1'b0; mgb9e84 <= 1'b0; end else if (rxmac_clk_en) begin cb8880 <= sj3cf86 & ~mr7090a; if (sj3cf86 && !mr7090a) ayc1110 <= ipe88ea; jr28f91 <= vkb277; ou10166 <= pfd8e30; if (hof42c6) sw8ddce <= hof42c6; else if (shc9fed && !hof42c6) sw8ddce <= 1'b0; else if (wl90a44) sw8ddce <= 1'b0; else sw8ddce <= uvfd6b6; goce3c9 <= ~phbfad6; if (wj70363 & ks109ed) aab9c79 <= wj70363; else if (sj3cf86) aab9c79 <= 1'b0; else aab9c79 <= ald6d17; if (xy86feb) qg7738f <= xy86feb; else if (sj3cf86) qg7738f <= 1'b0; else qg7738f <= bl5ada2; mgb9e84 <= aa21756; if (xweb89d) zx6ee71 <= sjd8e7; if (db2202c) hb71e49 <= nt3d6f5; qi3e472 <= aa21756 | (vx38c37 & ks109ed); ec2b5ee <= qvab575; ld6115a <= uvc61bf; gd8ad7 <= dmd5d67; if (pu933ac && !rg58cab) al41f9c <= zz19777; vvdd32e <= rg58cab; if (pu933ac && !rg58cab) yx51ee9 <= ep12675; if (rg58cab) begin pf7ba65 <= ep12675 + 14'd1; end else pf7ba65 <= 14'd0; if (lf32ad5 && yx60a48 && ui77e13) rtd7b87 <= hq25740 + 14'd1; if (uvc655a && !yx60a48 && aa98f3e) ay77c61 <= cm62429 + 14'd1; else if (ir12148) ay77c61 <= 14'd0; end\r
-end\r
-\r
-\r
-\r
-assign db2202c = ir12148;\r
-\r
-\r
-assign gbf2391 = wl95260 ? (fn40499 > (ipe21c7 + 14'd4)) : fn40499 > ipe21c7;\r
-assign bn91c8d = (fn40499 < 14'd64);\r
-assign tj8e46e = hb7e858;\r
-\r
-assign wj7fde4 = (fn40499[6:0] != 7'd64);\r
-assign xwfef24 = (ui49829 != ie2495d);\r
-assign ea72377 = je30dfd ? 1'b0 : go72a4c | yx60a48 ? vv5abac : aa5244 ? 1'b0 : lq48925;\r
-\r
-assign lf91bb9 = ~(ald6d17 | pfc780f | fp37f5a);\r
-assign qgdb280[31] = ir29124; \r
-assign qgdb280[30] = je30dfd; \r
-assign qgdb280[29] = hoeb5b4; \r
-assign qgdb280[28] = sjb45e8;\r
-assign qgdb280[27] = bl5ada2; \r
-assign qgdb280[26] = uvfd6b6; \r
-assign qgdb280[25] = pfc780f; \r
-assign qgdb280[24] = fp37f5a; \r
-assign qgdb280[23] = phbfad6; \r
-assign qgdb280[22] = uideb95; \r
-assign qgdb280[21] = uif5ca9; \r
-assign qgdb280[20] = vx81b1c; \r
-assign qgdb280[19] = cb29220; \r
-assign qgdb280[18] = go72a4c; \r
-assign qgdb280[17] = me4c149; \r
-assign qgdb280[16] = wl95260; \r
-assign qgdb280[15:14] = 2'b00;\r
-assign qgdb280[13:0] = fn40499; \r
-\r
-assign cm49f54[0] = me4c149;\r
-assign cm49f54[1] = pfc780f;\r
-assign cm49f54[2] = ald6d17;\r
-assign cm49f54[3] = ir29124;\r
-assign cm49f54[4] = je30dfd;\r
-assign cm49f54[5] = hoeb5b4;\r
-assign cm49f54[6] = uideb95;\r
-assign cm49f54[7] = uif5ca9;\r
-assign cm49f54[8] = wl95260;\r
-\r
-always@* begin ks109ed<=ea5c9d9[0];vke06c<=ea5c9d9[1];wj70363<=ea5c9d9[2];vx81b1c<=ea5c9d9[3];sjd8e7<=ea5c9d9[4];nt842ea<={nt32741>>1,ea5c9d9[5]};aa21756<=ea5c9d9[6];cze7ade<=ea5c9d9[7];nt3d6f5<=ea5c9d9[8];dmeb7ae<=ea5c9d9[9];uv5bd72<=ea5c9d9[10];uideb95<=ea5c9d9[11];uif5ca9<=ea5c9d9[12];irae549<=ea5c9d9[13];go72a4c<=ea5c9d9[14];wl95260<=ea5c9d9[15];ui49829<={jpdd6e0>>1,ea5c9d9[16]};me4c149<=ea5c9d9[17];yx60a48<=ea5c9d9[18];aa5244<=ea5c9d9[19];cb29220<=ea5c9d9[20];os49105<=ea5c9d9[21];kd44143<={gb5b83a>>1,ea5c9d9[22]};do20a1c<=ea5c9d9[23];ou50e2<=ea5c9d9[24];lf28710<=ea5c9d9[25];ic43887<=ea5c9d9[26];ipe21c7<={yx44fac>>1,ea5c9d9[27]};co10e3c<=ea5c9d9[28];ym871e0<=ea5c9d9[29];rv38f01<=ea5c9d9[30];pfc780f<=ea5c9d9[31];qge03f4<={ph2864e>>1,ea5c9d9[32]};tw1fa1<=ea5c9d9[33];aafd0b<=ea5c9d9[34];hb7e858<=ea5c9d9[35];hof42c6<=ea5c9d9[36];epa1632<=ea5c9d9[37];bab195<=ea5c9d9[38];rg58cab<=ea5c9d9[39];uvc655a<=ea5c9d9[40];lf32ad5<=ea5c9d9[41];qvab575<={cb8ffbc>>1,ea5c9d9[42]};vv5abac<=ea5c9d9[43];dmd5d67<=ea5c9d9[44];mr759d5<={ukbc914>>1,ea5c9d9[45]};ukacead<=ea5c9d9[46];yk67568<=ea5c9d9[47];ba3ab40<={xl22851>>1,ea5c9d9[48]};lqd5a02<=ea5c9d9[49];twad012<=ea5c9d9[50];fn40499<={yx51ee9>>1,ea5c9d9[51]};ep12675<={pf7ba65>>1,ea5c9d9[52]};pu933ac<=ea5c9d9[53];zm99d62<=ea5c9d9[54];eaceb12<=ea5c9d9[55];mr75890<=ea5c9d9[56];cm62429<={ay77c61>>1,ea5c9d9[57]};ir12148<=ea5c9d9[58];wl90a44<=ea5c9d9[59];ep85224<=ea5c9d9[60];ir29124<=ea5c9d9[61];lq48925<=ea5c9d9[62];ie2495d<={ec2b5ee>>1,ea5c9d9[63]};hq25740<={rtd7b87>>1,ea5c9d9[64]};ym2ba03<=ea5c9d9[65];jc5d019<=ea5c9d9[66];mre80cb<=ea5c9d9[67];th4065d<=ea5c9d9[68];zz32ee<=ea5c9d9[69];zz19777<=ea5c9d9[70];iccbbbf<=ea5c9d9[71];tueefc2<={fca86db>>1,ea5c9d9[72]};ui77e13<=ea5c9d9[73];fpbf098<=ea5c9d9[74];wjf84c7<=ea5c9d9[75];zz131e7<={qgdb280>>1,ea5c9d9[76]};aa98f3e<=ea5c9d9[77];pfc79f0<=ea5c9d9[78];sj3cf86<=ea5c9d9[79];mr7090a<=ea5c9d9[80];ou3e1ad<=ea5c9d9[81];osf0d69<=ea5c9d9[82];ls35a4a<={ldfc20f>>1,ea5c9d9[83]};ngad253<=ea5c9d9[84];zk6929b<=ea5c9d9[85];qg494db<=ea5c9d9[86];fn4a6d8<=ea5c9d9[87];ww536c7<={nr7e728>>1,ea5c9d9[88]};fp9b638<=ea5c9d9[89];xweb89d<=ea5c9d9[90];pfd8e30<=ea5c9d9[91];fnc7186<=ea5c9d9[92];vx38c37<=ea5c9d9[93];uvc61bf<=ea5c9d9[94];je30dfd<=ea5c9d9[95];xy86feb<=ea5c9d9[96];fp37f5a<=ea5c9d9[97];phbfad6<=ea5c9d9[98];uvfd6b6<=ea5c9d9[99];hoeb5b4<=ea5c9d9[100];bl5ada2<=ea5c9d9[101];ald6d17<=ea5c9d9[102];mgb68bd<=ea5c9d9[103];sjb45e8<=ea5c9d9[104];nga2f44<=ea5c9d9[105];wl17a23<=ea5c9d9[106];ipe88ea<={cm49f54>>1,ea5c9d9[107]};ip44754<={bl4faa1>>1,ea5c9d9[108]};oh23aa4<=ea5c9d9[109];ep1d525<=ea5c9d9[110];wwea92d<=ea5c9d9[111];end\r
-always@* begin ec2b93b[2047]<=ou1a400;ec2b93b[2046]<=xjd2000;ec2b93b[2044]<=mt90006;ec2b93b[2040]<=gd80035;ec2b93b[2032]<=nt32741[0];ec2b93b[2028]<=jr28f91;ec2b93b[2017]<=qtedba5;ec2b93b[2008]<=qi3e472;ec2b93b[1988]<=osdb6ca;ec2b93b[1987]<=su6dd2c;ec2b93b[1969]<=gbf2391;ec2b93b[1928]<=qgdb280[0];ec2b93b[1926]<=offdb74;ec2b93b[1891]<=bn91c8d;ec2b93b[1809]<=jcca005;ec2b93b[1805]<=wj4ee7d;ec2b93b[1804]<=lqe4402;ec2b93b[1803]<=fpa0744;ec2b93b[1761]<=ph2864e[0];ec2b93b[1748]<=ld6115a;ec2b93b[1734]<=tj8e46e;ec2b93b[1727]<=ecfce5;ec2b93b[1696]<=rtd7b87[0];ec2b93b[1668]<=cb8ffbc[0];ec2b93b[1633]<=hb71e49;ec2b93b[1587]<=sw8ddce;ec2b93b[1571]<=fn5002b;ec2b93b[1562]<=yk773ec;ec2b93b[1560]<=hd22013;ec2b93b[1558]<=ignore_pkt;ec2b93b[1555]<=bl4faa1[0];ec2b93b[1550]<=jpdd6e0[0];ec2b93b[1531]<=mgb9e84;ec2b93b[1475]<=ph193b9;ec2b93b[1464]<=cmf5978;ec2b93b[1448]<=gd8ad7;ec2b93b[1420]<=ea72377;ec2b93b[1406]<=nr7e728[0];ec2b93b[1345]<=twbdc3f;ec2b93b[1288]<=wj7fde4;ec2b93b[1287]<=uv70fda;ec2b93b[1242]<=anbe308;ec2b93b[1218]<=ir8f24f;ec2b93b[1131]<=ldfc20f[0];ec2b93b[1126]<=zx6ee71;ec2b93b[1094]<=cb8015f;ec2b93b[1076]<=zkcfb09;ec2b93b[1072]<=uk1009e;ec2b93b[1069]<=mt1d13e;ec2b93b[1063]<=me7d50e;ec2b93b[1056]<=ukbc914[0];ec2b93b[1055]<=xy3f6a8;ec2b93b[1052]<=ofdc1d5;ec2b93b[1028]<=qva147b;ec2b93b[1023]<=mtbb27f;ec2b93b[1014]<=ice51f2;ec2b93b[994]<=xy1b6d9;ec2b93b[902]<=ipc9dcf;ec2b93b[901]<=gb5b83a[0];ec2b93b[880]<=ou9830b;ec2b93b[874]<=hq8c22b;ec2b93b[863]<=al41f9c;ec2b93b[848]<=ec2b5ee[0];ec2b93b[834]<=xj4a3fe;ec2b93b[816]<=goce3c9;ec2b93b[793]<=lf91bb9;ec2b93b[777]<=cm49f54[0];ec2b93b[775]<=uk3badc;ec2b93b[765]<=jpf3947;ec2b93b[732]<=aa3eb2f;ec2b93b[643]<=dmee1fb;ec2b93b[621]<=ay77c61[0];ec2b93b[565]<=qi2bf08;ec2b93b[528]<=xwfef24;ec2b93b[527]<=gq87ed5;ec2b93b[514]<=xy1428f;ec2b93b[497]<=me436db;ec2b93b[450]<=lqeb707;ec2b93b[437]<=hof1845;ec2b93b[431]<=wl83f3;ec2b93b[417]<=ph947f;ec2b93b[408]<=aab9c79;ec2b93b[388]<=vi7927d;ec2b93b[387]<=uve775b;ec2b93b[366]<=rv27d65;ec2b93b[310]<=wj65df1;ec2b93b[282]<=co57e1;ec2b93b[257]<=xl22851[0];ec2b93b[248]<=fca86db[0];ec2b93b[225]<=qg68a93;ec2b93b[215]<=nee107e;ec2b93b[208]<=zx6128f;ec2b93b[204]<=qg7738f;ec2b93b[193]<=vi7ceeb;ec2b93b[183]<=yx44fac[0];ec2b93b[157]<=en54381;ec2b93b[155]<=ic4cbbe;ec2b93b[141]<=aa3bc5d;ec2b93b[128]<=aa2450a;ec2b93b[124]<=bydaa1b;ec2b93b[112]<=cb7568;ec2b93b[104]<=dzec251;ec2b93b[96]<=sj804f1;ec2b93b[91]<=kde89f5;ec2b93b[78]<=uiea870;ec2b93b[77]<=fne9977;ec2b93b[64]<=lqe48a1;ec2b93b[62]<=jcfb543;ec2b93b[56]<=yke0ead;ec2b93b[38]<=vvdd32e;ec2b93b[19]<=pf7ba65[0];ec2b93b[9]<=yx51ee9[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module xlbf10b (\r
- \r
- rxmac_clk,\r
- reset_n,\r
- rxmac_clk_en,\r
-\r
- \r
- mtbb27f, \r
- ou1a400, \r
- ald93fd, \r
- xjd2000,\r
- mt90006,\r
- gd80035,\r
-\r
- \r
- en41ecd, \r
- ksf66d, \r
- nr7b369, \r
- ipd9b4f, \r
- blcda7c, \r
- qg6d3e7, \r
- xw69f39, \r
- zx4f9ca, \r
- xw7ce56, \r
- kde72b3, \r
- ux3959c, \r
- hocace4, \r
- fc30be7, \r
- mt1d13e, \r
- kde89f5, \r
- yx44fac, \r
- rv27d65, \r
- aa3eb2f, \r
- cmf5978, \r
-\r
- \r
- rx_fifo_full, \r
- ignore_pkt, \r
-\r
- \r
- qg78222, \r
- lq4d15b, \r
- os68ada, \r
- ayc1110, \r
- cb8880, \r
-\r
- \r
- zmad152, \r
- ou10166, \r
-\r
- \r
- rx_fifo_error, \r
- rx_stat_vector, \r
- rx_dbout, \r
- rx_write, \r
- rx_stat_en, \r
- rx_eof, \r
- rx_error \r
-);\r
-parameter ld6e960 = 8;\r
-parameter vi52632 = 14;\r
-parameter vk93192 = 16;\r
-parameter uk98c92 = 16;\r
-parameter xwfb4be = 20;\r
-parameter jcda5f3 = 32;\r
-parameter gd80619 = 32;\r
-parameter jpd2f9a = 8;\r
-parameter gq97cd7 = 4;\r
-parameter gqa3846 = 8;\r
-parameter db9e32f = 48;\r
-parameter nee118f = 2;\r
-parameter lqf197e = 6;\r
-parameter ng8cbf3 = 8;\r
-parameter zz30cc = 9;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input mtbb27f;\r
-input ou1a400;\r
-input xjd2000;\r
-input mt90006;\r
-input gd80035;\r
-input [ld6e960-1:0] ald93fd;\r
-input [gqa3846-1:0] en41ecd;\r
-input [gqa3846-1:0] ksf66d;\r
-input [gqa3846-1:0] nr7b369;\r
-input [gqa3846-1:0] ipd9b4f;\r
-input [gqa3846-1:0] blcda7c;\r
-input [gqa3846-1:0] qg6d3e7;\r
-input [gqa3846-1:0] xw69f39;\r
-input [gqa3846-1:0] zx4f9ca;\r
-input [db9e32f-1:0] xw7ce56;\r
-input [vk93192-1:0] fc30be7;\r
-input [vi52632-1:0] yx44fac;\r
-input kde72b3;\r
-input ux3959c;\r
-input hocace4;\r
-input mt1d13e;\r
-input kde89f5;\r
-input rv27d65;\r
-input aa3eb2f;\r
-input cmf5978;\r
-input ignore_pkt;\r
-input rx_fifo_full;\r
-output qg78222;\r
-output [zz30cc-1:0] ayc1110;\r
-output cb8880;\r
-output os68ada;\r
-output [uk98c92-1:0] lq4d15b;\r
-output [vk93192-1:0] zmad152;\r
-output ou10166;\r
-output rx_fifo_error;\r
-output [jcda5f3-1:0] rx_stat_vector;\r
-output [ld6e960-1:0] rx_dbout;\r
-output rx_write;\r
-output rx_stat_en;\r
-output rx_eof;\r
-output rx_error;\r
-parameter pdevice_family = "XP2";\r
-wire [ld6e960-1:0] pfcd085;\r
-wire [ld6e960-1:0] dm42171;\r
-wire co10b8b;\r
-wire an85c58;\r
-wire ec2e2c5;\r
-wire dz71628;\r
-wire zz8b146;\r
-wire [vi52632-1:0] vic51ba;\r
-wire ph28dd2;\r
-wire kq46e96;\r
-wire fp374b0;\r
-wire tjba587;\r
-wire fnd2c3f;\r
-wire [vk93192-1:0] tjb0ffa;\r
-wire [uk98c92-1:0] ls3feb8;\r
-wire [vi52632-1:0] ykfae11;\r
-wire pfd7088;\r
-wire zmb8446;\r
-wire xjc2232;\r
-wire hq11197;\r
-wire qi88cbb;\r
-wire go465d9;\r
-wire db32ec9;\r
-wire wy9764e;\r
-wire epbb270;\r
-wire ofd9385;\r
-wire alc9c2d;\r
-wire kd4e16d;\r
-wire mr70b6d;\r
-wire wl85b6d;\r
-wire [gd80619-1:0] cm6db6e;\r
-wire kq6db70;\r
-wire ww6db80;\r
-wire [xwfb4be-1:0] fn6e000;\r
-wire kd70006;\r
-wire cb80034;\r
-wire qg78222;\r
-wire cb8880;\r
-wire [zz30cc-1:0] ayc1110;\r
-wire [nee118f-1:0] vk2038d;\r
-wire [lqf197e-1:0] jee35b;\r
-wire [jpd2f9a-1:0] qi8d6df;\r
-wire [jpd2f9a-1:0] kd5b7c6;\r
-wire osdbe34;\r
-wire zkdf1a1;\r
-wire [xwfb4be-1:0] enc6855;\r
-reg gq342ac;\r
-reg ks109ed;\r
-reg vke06c;\r
-reg [ld6e960 - 1 : 0] hd27b47;\r
-reg wj70363;\r
-reg vx81b1c;\r
-reg sjd8e7;\r
-reg [gqa3846 - 1 : 0] su56299;\r
-reg [gqa3846 - 1 : 0] kf8a644;\r
-reg [gqa3846 - 1 : 0] ls99128;\r
-reg [gqa3846 - 1 : 0] ip44a1f;\r
-reg [gqa3846 - 1 : 0] db287eb;\r
-reg [gqa3846 - 1 : 0] uk1faf8;\r
-reg [gqa3846 - 1 : 0] xwebe0c;\r
-reg [gqa3846 - 1 : 0] mrf831e;\r
-reg [db9e32f - 1 : 0] lfc7a1;\r
-reg ps63d0e;\r
-reg ls1e873;\r
-reg byf439b;\r
-reg [vk93192 - 1 : 0] bl4ad57;\r
-reg lf28710;\r
-reg ic43887;\r
-reg [vi52632 - 1 : 0] ipe21c7;\r
-reg co10e3c;\r
-reg ym871e0;\r
-reg rv38f01;\r
-reg xw5d016;\r
-reg ou50e2;\r
-reg [ld6e960 - 1 : 0] rg76258;\r
-reg [ld6e960 - 1 : 0] ba8961c;\r
-reg of4b0e2;\r
-reg rg58715;\r
-reg yxc38ab;\r
-reg nt1c55c;\r
-reg she2ae7;\r
-reg [vi52632 - 1 : 0] anab9e9;\r
-reg yk5cf4d;\r
-reg yxe7a68;\r
-reg hd3d345;\r
-reg jpe9a2e;\r
-reg ps4d176;\r
-reg [vk93192 - 1 : 0] bl45d90;\r
-reg [uk98c92 - 1 : 0] rg76439;\r
-reg [vi52632 - 1 : 0] yz90e5b;\r
-reg sw872dc;\r
-reg ux396e1;\r
-reg gocb70c;\r
-reg gb5b861;\r
-reg ofdc30d;\r
-reg zke186d;\r
-reg lfc36a;\r
-reg rt61b56;\r
-reg yzdab6;\r
-reg su6d5b5;\r
-reg of6ada9;\r
-reg go56d4d;\r
-reg ieb6a69;\r
-reg ntb5348;\r
-reg [gd80619 - 1 : 0] fa4d230;\r
-reg tu69182;\r
-reg vi48c13;\r
-reg [xwfb4be - 1 : 0] je304d9;\r
-reg sw826ca;\r
-reg vx13651;\r
-reg [nee118f - 1 : 0] qtd9476;\r
-reg [lqf197e - 1 : 0] al51dab;\r
-reg [jpd2f9a - 1 : 0] ps76ae6;\r
-reg [jpd2f9a - 1 : 0] gdab996;\r
-reg ui5ccb5;\r
-reg the65a8;\r
-reg [xwfb4be - 1 : 0] pu96a36;\r
-reg [2047:0] ec2b93b;\r
-wire [70:0] ea5c9d9;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam tue4ec8 = 71,ph27642 = 32'hfdffd42b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign dm42171 = rg76258;\r
-\r
-\r
-assign os68ada = ps4d176;\r
-assign lq4d15b = rg76439;\r
-assign zmad152 = bl45d90;\r
-\r
-\r
-\r
-\r
-assign vk2038d = je304d9[19:18];\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-uk979bb #( .ld6e960(ld6e960) ) qv3cf17 ( .rxmac_clk(rxmac_clk), .rxmac_clk_en(rxmac_clk_en), .reset_n(gq342ac), .mtbb27f(ks109ed), .ald93fd(hd27b47), .shc9fed(yzdab6), .zx4ff6d(of6ada9), .yx7fb6e(pfcd085), .offdb74(co10b8b), .qtedba5(an85c58), .su6dd2c(ec2e2c5) );\r
-\r
-shc9dff #( .ld6e960(ld6e960), .vi52632(vi52632), .vk93192(vk93192), .uk98c92(uk98c92) ) dz4aef1 ( .rxmac_clk(rxmac_clk), .reset_n(gq342ac), .rxmac_clk_en(rxmac_clk_en), .nt32741(rg76258), .thec185(go56d4d), .zx4ff6d(su6d5b5), .uve83d9(ieb6a69), .nt617c(ntb5348), .fc30be7(bl4ad57), .qv278c(gocb70c), .do9c880(rt61b56), .vi7ceeb(dz71628), .uve775b(hq9630b), .uk3badc(zz8b146), .jpdd6e0(vic51ba), .lqeb707(pfd7088), .gb5b83a(ykfae11), .ofdc1d5(ph28dd2), .yke0ead(fp374b0), .cb7568(tjba587), .vk3ab45(ls3feb8), .psd5a2a(fnd2c3f), .zmad152(tjb0ffa), .qg68a93(zmb8446), .vv45498(kq46e96) );\r
-\r
-zmbda32 #( .ld6e960(ld6e960), .db9e32f(db9e32f), .lqf197e(lqf197e), .ng8cbf3(ng8cbf3) ) aa31fc1 ( .rxmac_clk(rxmac_clk), .reset_n(gq342ac), .rxmac_clk_en(rxmac_clk_en), .nt32741(rg76258), .qtedba5(rg58715), .zx4ff6d(su6d5b5), .uve83d9(ieb6a69), .en41ecd(su56299), .ksf66d(kf8a644), .nr7b369(ls99128), .ipd9b4f(ip44a1f), .blcda7c(db287eb), .qg6d3e7(uk1faf8), .xw69f39(xwebe0c), .zx4f9ca(mrf831e), .xw7ce56(lfc7a1), .kde72b3(ps63d0e), .ux3959c(ls1e873), .hocace4(byf439b), .ic56722(al51dab), .ukb3910(faeb246), .lqe4402(hq11197), .hd22013(qi88cbb), .uk1009e(go465d9), .sj804f1(db32ec9), .qv278c(xjc2232), .do9c880(wy9764e) );\r
-\r
-\r
-ri351a3 #( .ld6e960(ld6e960), .vi52632(vi52632), .xwfb4be(xwfb4be), .jcda5f3(jcda5f3), .gd80619(gd80619), .zz30cc(zz30cc) ) xjd78f8 ( .rxmac_clk(rxmac_clk), .reset_n(gq342ac), .rxmac_clk_en(rxmac_clk_en), .mtbb27f(ks109ed), .ou1a400(vke06c), .xjd2000(wj70363), .mt90006(vx81b1c), .gd80035(sjd8e7), .nt32741(rg76258), .qtedba5(rg58715), .su6dd2c(yxc38ab), .offdb74(of4b0e2), .lqe4402(gb5b861), .hd22013(ofdc30d), .uk1009e(zke186d), .sj804f1(lfc36a), .vi7ceeb(nt1c55c), .uve775b(hq9630b), .uk3badc(she2ae7), .jpdd6e0(anab9e9), .ofdc1d5(yk5cf4d), .fpa0744(yxe7a68), .yke0ead(hd3d345), .cb7568(jpe9a2e), .qg68a93(ux396e1), .lqeb707(sw872dc), .gb5b83a(yz90e5b), .ignore_pkt(ou50e2), .mt1d13e(lf28710), .kde89f5(ic43887), .yx44fac(ipe21c7), .rv27d65(co10e3c), .aa3eb2f(ym871e0), .cmf5978(rv38f01), .ou9830b(cob3f9f), .zx4ff6d(ofd9385), .uve83d9(mr70b6d),\r
- .qg78222(qg78222), .ayc1110(ayc1110), .cb8880(cb8880), .ou10166(ou10166), .shc9fed(epbb270), .db2202c(alc9c2d), .thec185(kd4e16d), .nt617c(wl85b6d), .ie9dcf2(fn6e000), .pf6e773(kd70006), .lq73b9e(cb80034), .uk8d311(cm6db6e), .ukb3910(kq6db70), .vkb277(pf6b57b), .me62210(ww6db80) );\r
-\r
-icce60c dz7bdd6 ( .vi73061(jee35b), .ou9830b(cob3f9f), .ykc1859(rg76258), .rvc2c9(tu69182), .nr6164e(faeb246), .vkb277(pf6b57b), .ui593bb(vi48c13), .wjc9dd9(fa4d230), .en4eecd(rxmac_clk), .gdbb361(gq342ac), .rxmac_clk_en(rxmac_clk_en) );\r
-\r
-fa63a6e #( .ld6e960(ld6e960), .xwfb4be(xwfb4be), .jcda5f3(jcda5f3), .jpd2f9a(jpd2f9a), .gq97cd7(gq97cd7) ) qtc6650 ( .rxmac_clk(rxmac_clk), .reset_n(gq342ac), .rxmac_clk_en(rxmac_clk_en), .pf6e773(sw826ca), .lq73b9e(vx13651), .ie9dcf2(qtd9476), .rx_fifo_full(xw5d016), .ne73c82(pu96a36), .bn9e412(qi8d6df), .wjf2096(kd5b7c6), .yz904b5(osdbe34), .wy825ad(zkdf1a1), .rx_fifo_error(rx_fifo_error), .rx_stat_vector(rx_stat_vector), .rx_dbout(rx_dbout), .rx_write(rx_write), .rx_stat_en(rx_stat_en), .rx_eof(rx_eof), .rx_error(rx_error) );\r
-\r
-pmi_ram_dp #(.pmi_wr_addr_depth(256), .pmi_wr_addr_width(8), .pmi_wr_data_width(20), .pmi_rd_addr_depth(256), .pmi_rd_addr_width(8), .pmi_rd_data_width(20), .pmi_regmode("noreg"), .pmi_gsr("disable"), .pmi_resetmode("sync"), .pmi_init_file("none"), .pmi_init_file_format("binary"), .pmi_family(pdevice_family), .module_type("pmi_ram_dp") )\r
-lf13e8f (.Data(fn6e000), .WrAddress(qi8d6df), .RdAddress(kd5b7c6), .WrClock(rxmac_clk), .RdClock(rxmac_clk), .WrClockEn(1'b1), .RdClockEn(osdbe34 & rxmac_clk_en), .WE(zkdf1a1), .Reset(1'b0), .Q(enc6855) );\r
-always@* begin gq342ac<=ea5c9d9[0];ks109ed<=ea5c9d9[1];vke06c<=ea5c9d9[2];hd27b47<={ald93fd>>1,ea5c9d9[3]};wj70363<=ea5c9d9[4];vx81b1c<=ea5c9d9[5];sjd8e7<=ea5c9d9[6];su56299<={en41ecd>>1,ea5c9d9[7]};kf8a644<={ksf66d>>1,ea5c9d9[8]};ls99128<={nr7b369>>1,ea5c9d9[9]};ip44a1f<={ipd9b4f>>1,ea5c9d9[10]};db287eb<={blcda7c>>1,ea5c9d9[11]};uk1faf8<={qg6d3e7>>1,ea5c9d9[12]};xwebe0c<={xw69f39>>1,ea5c9d9[13]};mrf831e<={zx4f9ca>>1,ea5c9d9[14]};lfc7a1<={xw7ce56>>1,ea5c9d9[15]};ps63d0e<=ea5c9d9[16];ls1e873<=ea5c9d9[17];byf439b<=ea5c9d9[18];bl4ad57<={fc30be7>>1,ea5c9d9[19]};lf28710<=ea5c9d9[20];ic43887<=ea5c9d9[21];ipe21c7<={yx44fac>>1,ea5c9d9[22]};co10e3c<=ea5c9d9[23];ym871e0<=ea5c9d9[24];rv38f01<=ea5c9d9[25];xw5d016<=ea5c9d9[26];ou50e2<=ea5c9d9[27];rg76258<={pfcd085>>1,ea5c9d9[28]};ba8961c<={dm42171>>1,ea5c9d9[29]};of4b0e2<=ea5c9d9[30];rg58715<=ea5c9d9[31];yxc38ab<=ea5c9d9[32];nt1c55c<=ea5c9d9[33];she2ae7<=ea5c9d9[34];anab9e9<={vic51ba>>1,ea5c9d9[35]};yk5cf4d<=ea5c9d9[36];yxe7a68<=ea5c9d9[37];hd3d345<=ea5c9d9[38];jpe9a2e<=ea5c9d9[39];ps4d176<=ea5c9d9[40];bl45d90<={tjb0ffa>>1,ea5c9d9[41]};rg76439<={ls3feb8>>1,ea5c9d9[42]};yz90e5b<={ykfae11>>1,ea5c9d9[43]};sw872dc<=ea5c9d9[44];ux396e1<=ea5c9d9[45];gocb70c<=ea5c9d9[46];gb5b861<=ea5c9d9[47];ofdc30d<=ea5c9d9[48];zke186d<=ea5c9d9[49];lfc36a<=ea5c9d9[50];rt61b56<=ea5c9d9[51];yzdab6<=ea5c9d9[52];su6d5b5<=ea5c9d9[53];of6ada9<=ea5c9d9[54];go56d4d<=ea5c9d9[55];ieb6a69<=ea5c9d9[56];ntb5348<=ea5c9d9[57];fa4d230<={cm6db6e>>1,ea5c9d9[58]};tu69182<=ea5c9d9[59];vi48c13<=ea5c9d9[60];je304d9<={fn6e000>>1,ea5c9d9[61]};sw826ca<=ea5c9d9[62];vx13651<=ea5c9d9[63];qtd9476<={vk2038d>>1,ea5c9d9[64]};al51dab<={jee35b>>1,ea5c9d9[65]};ps76ae6<={qi8d6df>>1,ea5c9d9[66]};gdab996<={kd5b7c6>>1,ea5c9d9[67]};ui5ccb5<=ea5c9d9[68];the65a8<=ea5c9d9[69];pu96a36<={enc6855>>1,ea5c9d9[70]};end\r
-always@* begin ec2b93b[2047]<=mtbb27f;ec2b93b[2046]<=ou1a400;ec2b93b[2045]<=enc6855[0];ec2b93b[2044]<=ald93fd[0];ec2b93b[2041]<=xjd2000;ec2b93b[2035]<=mt90006;ec2b93b[2029]<=wl85b6d;ec2b93b[2022]<=gd80035;ec2b93b[2011]<=cm6db6e[0];ec2b93b[1996]<=en41ecd[0];ec2b93b[1974]<=kq6db70;ec2b93b[1945]<=ksf66d[0];ec2b93b[1943]<=go465d9;ec2b93b[1922]<=cmf5978;ec2b93b[1901]<=ww6db80;ec2b93b[1842]<=nr7b369[0];ec2b93b[1839]<=db32ec9;ec2b93b[1797]<=rx_fifo_full;ec2b93b[1791]<=kd5b7c6[0];ec2b93b[1778]<=xjc2232;ec2b93b[1776]<=yx44fac[0];ec2b93b[1759]<=vk2038d[0];ec2b93b[1755]<=fn6e000[0];ec2b93b[1637]<=ipd9b4f[0];ec2b93b[1631]<=wy9764e;ec2b93b[1622]<=zx4f9ca[0];ec2b93b[1546]<=ignore_pkt;ec2b93b[1535]<=osdbe34;ec2b93b[1531]<=kd4e16d;ec2b93b[1509]<=hq11197;ec2b93b[1504]<=rv27d65;ec2b93b[1471]<=jee35b[0];ec2b93b[1468]<=mt1d13e;ec2b93b[1463]<=kd70006;ec2b93b[1391]<=hocace4;ec2b93b[1312]<=zz8b146;ec2b93b[1226]<=blcda7c[0];ec2b93b[1215]<=epbb270;ec2b93b[1197]<=xw7ce56[0];ec2b93b[1153]<=ph28dd2;ec2b93b[1044]<=pfcd085[0];ec2b93b[1037]<=tjba587;ec2b93b[1023]<=reset_n;ec2b93b[1022]<=zkdf1a1;ec2b93b[1014]<=mr70b6d;ec2b93b[971]<=qi88cbb;ec2b93b[961]<=aa3eb2f;ec2b93b[895]<=qi8d6df[0];ec2b93b[889]<=zmb8446;ec2b93b[888]<=kde89f5;ec2b93b[879]<=cb80034;ec2b93b[811]<=xw69f39[0];ec2b93b[765]<=alc9c2d;ec2b93b[734]<=fc30be7[0];ec2b93b[695]<=ux3959c;ec2b93b[656]<=dz71628;ec2b93b[576]<=vic51ba[0];ec2b93b[518]<=fp374b0;ec2b93b[444]<=pfd7088;ec2b93b[405]<=qg6d3e7[0];ec2b93b[382]<=ofd9385;ec2b93b[347]<=kde72b3;ec2b93b[328]<=ec2e2c5;ec2b93b[259]<=kq46e96;ec2b93b[222]<=ykfae11[0];ec2b93b[164]<=an85c58;ec2b93b[111]<=ls3feb8[0];ec2b93b[82]<=co10b8b;ec2b93b[55]<=tjb0ffa[0];ec2b93b[41]<=dm42171[0];ec2b93b[27]<=fnd2c3f;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module kdd69ed ( qvb4f6d,\r
- baa7b6d,\r
- txmac_clk_en,\r
-\r
- wjedb5f, \r
- os6dafc, \r
-\r
- cm6d7e0 \r
- );\r
-parameter rt6bf01 = 4;\r
-input qvb4f6d;\r
-input baa7b6d;\r
-input txmac_clk_en;\r
-input wjedb5f;\r
-input [rt6bf01-1:0] os6dafc;\r
-output cm6d7e0;\r
-reg hof1623;\r
-reg fp8b11a;\r
-reg [15:0] xw588d7;\r
-reg [31:0] osc46ba;\r
-wire kf235d0 = (~hof1623 & wjedb5f);\r
-wire cm6d7e0 = fp8b11a & (xw588d7 == 0);\r
-wire [31:0] aa21dd6;\r
-reg rieeb0;\r
-reg [rt6bf01 - 1 : 0] hdbac11;\r
-reg ipd608e;\r
-reg xlb0474;\r
-reg [15 : 0] aa823a6;\r
-reg [31 : 0] fc11d31;\r
-reg zz8e98a;\r
-reg [31 : 0] zx74c56;\r
-reg [2047:0] ec2b93b;\r
-wire [7:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 8,ph27642 = 32'hfdffd84b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
- always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) xw588d7 <= 0; else if (txmac_clk_en) begin if (zz8e98a) begin casex(hdbac11) 4'h1: begin xw588d7[15:0] <= {9'b00000000, fc11d31[0], {6{1'b0}}}; end 4'h2: begin xw588d7[15:0] <= {8'b00000000, fc11d31[1:0], {6{1'b0}}}; end 4'h3: begin xw588d7[15:0] <= {7'b0000000, fc11d31[2:0], {6{1'b0}}}; end 4'h4: begin xw588d7[15:0] <= {6'b000000, fc11d31[3:0], {6{1'b0}}}; end 4'h5: begin xw588d7[15:0] <= {5'b00000, fc11d31[4:0], {6{1'b0}}}; end 4'h6: begin xw588d7[15:0] <= {4'b0000, fc11d31[5:0], {6{1'b0}}}; end 4'h7: begin xw588d7[15:0] <= {3'b000, fc11d31[6:0], {6{1'b0}}}; end 4'h8: begin xw588d7[15:0] <= {2'b00, fc11d31[7:0], {6{1'b0}}}; end 4'h9: begin xw588d7[15:0] <= {1'b0, fc11d31[8:0], {6{1'b0}}}; end default: begin xw588d7[15:0] <= {fc11d31[9:0], {6{1'b0}}}; end endcase end else if (xlb0474) begin xw588d7 <= aa823a6 - {{15{1'b0}}, 1'b1}; end end end\r
- always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin hof1623 <= 1'b0; fp8b11a <= 1'b0; end else if (txmac_clk_en) begin hof1623 <= rieeb0; fp8b11a <= ipd608e; end end assign aa21dd6[31:1] = fc11d31[30:0]; assign aa21dd6[0] = fc11d31[1]^fc11d31[5]^fc11d31[6]^fc11d31[31];\r
- always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin osc46ba <= {32{1'b1}}; end else if (txmac_clk_en) begin osc46ba <= zx74c56; end end \r
-\r
-always@* begin rieeb0<=ea5c9d9[0];hdbac11<={os6dafc>>1,ea5c9d9[1]};ipd608e<=ea5c9d9[2];xlb0474<=ea5c9d9[3];aa823a6<={xw588d7>>1,ea5c9d9[4]};fc11d31<={osc46ba>>1,ea5c9d9[5]};zz8e98a<=ea5c9d9[6];zx74c56<={aa21dd6>>1,ea5c9d9[7]};end\r
-always@* begin ec2b93b[2047]<=os6dafc[0];ec2b93b[2046]<=hof1623;ec2b93b[2044]<=fp8b11a;ec2b93b[2040]<=xw588d7[0];ec2b93b[2033]<=osc46ba[0];ec2b93b[2019]<=kf235d0;ec2b93b[1991]<=aa21dd6[0];ec2b93b[1023]<=wjedb5f;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ip41424 (\r
- yk46f15, \r
- ykc1859,\r
- rvc2c9,\r
- ui593bb,\r
- wjc9dd9,\r
- en4eecd,\r
- txmac_clk_en,\r
- gdbb361\r
- );\r
-output [31:0] yk46f15;\r
-input [7:0] ykc1859;\r
-input [31:0] wjc9dd9;\r
-input rvc2c9;\r
-input ui593bb;\r
-input en4eecd;\r
-input txmac_clk_en;\r
-input gdbb361;\r
-reg [31:0] jp50046;\r
-wire [31:0] cb8de2;\r
-wire [31:0] yk46f15;\r
-reg [7 : 0] nt378a8;\r
-reg ymbc546;\r
-reg doa8c29;\r
-reg [31 : 0] su4614a;\r
-reg [31 : 0] tw30a51;\r
-reg [31 : 0] an8528b;\r
-reg [2047:0] ec2b93b;\r
-wire [5:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 6,ph27642 = 32'hfdffc70b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-assign yk46f15[31] = ~tw30a51[0];\r
-assign yk46f15[30] = ~tw30a51[1];\r
-assign yk46f15[29] = ~tw30a51[2];\r
-assign yk46f15[28] = ~tw30a51[3];\r
-assign yk46f15[27] = ~tw30a51[4];\r
-assign yk46f15[26] = ~tw30a51[5];\r
-assign yk46f15[25] = ~tw30a51[6];\r
-assign yk46f15[24] = ~tw30a51[7];\r
-assign yk46f15[23] = ~tw30a51[8];\r
-assign yk46f15[22] = ~tw30a51[9];\r
-assign yk46f15[21] = ~tw30a51[10];\r
-assign yk46f15[20] = ~tw30a51[11];\r
-assign yk46f15[19] = ~tw30a51[12];\r
-assign yk46f15[18] = ~tw30a51[13];\r
-assign yk46f15[17] = ~tw30a51[14];\r
-assign yk46f15[16] = ~tw30a51[15];\r
-assign yk46f15[15] = ~tw30a51[16];\r
-assign yk46f15[14] = ~tw30a51[17];\r
-assign yk46f15[13] = ~tw30a51[18];\r
-assign yk46f15[12] = ~tw30a51[19];\r
-assign yk46f15[11] = ~tw30a51[20];\r
-assign yk46f15[10] = ~tw30a51[21];\r
-assign yk46f15[9] = ~tw30a51[22];\r
-assign yk46f15[8] = ~tw30a51[23];\r
-assign yk46f15[7] = ~tw30a51[24];\r
-assign yk46f15[6] = ~tw30a51[25];\r
-assign yk46f15[5] = ~tw30a51[26];\r
-assign yk46f15[4] = ~tw30a51[27];\r
-assign yk46f15[3] = ~tw30a51[28];\r
-assign yk46f15[2] = ~tw30a51[29];\r
-assign yk46f15[1] = ~tw30a51[30];\r
-assign yk46f15[0] = ~tw30a51[31];\r
-\r
-always @ (posedge en4eecd or negedge gdbb361)\r
-begin if (!gdbb361) begin jp50046 <= 32'hffffffff; end else if (txmac_clk_en) begin if (ymbc546) begin jp50046 <= an8528b; end else if (doa8c29) begin jp50046 <= su4614a; end end\r
-end\r
-\r
-assign cb8de2[0] = tw30a51[30] ^ nt378a8[7] ^ nt378a8[1] ^ tw30a51[24];\r
-assign cb8de2[1] = tw30a51[30] ^ nt378a8[6] ^ nt378a8[7] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[25];\r
-assign cb8de2[2] = tw30a51[30] ^ nt378a8[6] ^ nt378a8[7] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[25] ^ tw30a51[26] ^ nt378a8[5];\r
-assign cb8de2[3] = tw30a51[31] ^ nt378a8[0] ^ tw30a51[25] ^ tw30a51[26] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ nt378a8[6];\r
-assign cb8de2[4] = tw30a51[30] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ tw30a51[28] ^ nt378a8[7];\r
-assign cb8de2[5] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[25] ^ nt378a8[2] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[28] ^ nt378a8[6] ^ tw30a51[29] ^ nt378a8[7];\r
-assign cb8de2[6] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[25] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[5] ^ tw30a51[28] ^ nt378a8[6] ^ tw30a51[29];\r
-assign cb8de2[7] = tw30a51[31] ^ nt378a8[0] ^ tw30a51[24] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ tw30a51[29] ^ nt378a8[7];\r
-assign cb8de2[8] = tw30a51[24] ^ tw30a51[25] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[28] ^ nt378a8[6] ^ nt378a8[7] ^ tw30a51[0];\r
-assign cb8de2[9] = tw30a51[25] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[5] ^ tw30a51[28] ^ nt378a8[6] ^ tw30a51[29] ^ tw30a51[1];\r
-assign cb8de2[10] = tw30a51[24] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ tw30a51[29] ^ nt378a8[7] ^ tw30a51[2];\r
-assign cb8de2[11] = tw30a51[3] ^ tw30a51[24] ^ tw30a51[25] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[28] ^ nt378a8[6] ^ nt378a8[7];\r
-assign cb8de2[12] = tw30a51[30] ^ tw30a51[4] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[25] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[5] ^ tw30a51[28] ^ nt378a8[6] ^ tw30a51[29] ^ nt378a8[7];\r
-assign cb8de2[13] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ tw30a51[5] ^ nt378a8[1] ^ tw30a51[25] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ nt378a8[6] ^ tw30a51[29];\r
-assign cb8de2[14] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[6] ^ tw30a51[26] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5] ^ tw30a51[28];\r
-assign cb8de2[15] = tw30a51[31] ^ nt378a8[0] ^ nt378a8[2] ^ tw30a51[7] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[28] ^ tw30a51[29];\r
-assign cb8de2[16] = tw30a51[24] ^ nt378a8[2] ^ nt378a8[3] ^ tw30a51[8] ^ tw30a51[28] ^ tw30a51[29] ^ nt378a8[7];\r
-assign cb8de2[17] = tw30a51[30] ^ nt378a8[1] ^ tw30a51[25] ^ nt378a8[2] ^ tw30a51[9] ^ nt378a8[6] ^ tw30a51[29];\r
-assign cb8de2[18] = tw30a51[30] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ tw30a51[26] ^ nt378a8[5] ^ tw30a51[10];\r
-assign cb8de2[19] = tw30a51[31] ^ nt378a8[0] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[11];\r
-assign cb8de2[20] = tw30a51[12] ^ nt378a8[3] ^ tw30a51[28];\r
-assign cb8de2[21] = tw30a51[13] ^ nt378a8[2] ^ tw30a51[29];\r
-assign cb8de2[22] = tw30a51[14] ^ tw30a51[24] ^ nt378a8[7];\r
-assign cb8de2[23] = tw30a51[30] ^ nt378a8[1] ^ tw30a51[24] ^ tw30a51[15] ^ tw30a51[25] ^ nt378a8[6] ^ nt378a8[7];\r
-assign cb8de2[24] = tw30a51[31] ^ nt378a8[0] ^ tw30a51[25] ^ tw30a51[16] ^ tw30a51[26] ^ nt378a8[5] ^ nt378a8[6];\r
-assign cb8de2[25] = tw30a51[26] ^ tw30a51[17] ^ nt378a8[4] ^ tw30a51[27] ^ nt378a8[5];\r
-assign cb8de2[26] = tw30a51[30] ^ nt378a8[1] ^ tw30a51[24] ^ nt378a8[3] ^ nt378a8[4] ^ tw30a51[27] ^ tw30a51[18] ^ tw30a51[28] ^ nt378a8[7];\r
-assign cb8de2[27] = tw30a51[31] ^ nt378a8[0] ^ tw30a51[25] ^ nt378a8[2] ^ nt378a8[3] ^ tw30a51[28] ^ tw30a51[19] ^ nt378a8[6] ^ tw30a51[29];\r
-assign cb8de2[28] = tw30a51[30] ^ nt378a8[1] ^ nt378a8[2] ^ tw30a51[26] ^ nt378a8[5] ^ tw30a51[29] ^ tw30a51[20];\r
-assign cb8de2[29] = tw30a51[30] ^ tw30a51[21] ^ tw30a51[31] ^ nt378a8[0] ^ nt378a8[1] ^ nt378a8[4] ^ tw30a51[27];\r
-assign cb8de2[30] = tw30a51[31] ^ tw30a51[22] ^ nt378a8[0] ^ nt378a8[3] ^ tw30a51[28];\r
-assign cb8de2[31] = tw30a51[23] ^ nt378a8[2] ^ tw30a51[29];\r
-always@* begin nt378a8<={ykc1859>>1,ea5c9d9[0]};ymbc546<=ea5c9d9[1];doa8c29<=ea5c9d9[2];su4614a<={wjc9dd9>>1,ea5c9d9[3]};tw30a51<={jp50046>>1,ea5c9d9[4]};an8528b<={cb8de2>>1,ea5c9d9[5]};end\r
-always@* begin ec2b93b[2047]<=rvc2c9;ec2b93b[2046]<=ui593bb;ec2b93b[2044]<=wjc9dd9[0];ec2b93b[2040]<=jp50046[0];ec2b93b[2032]<=cb8de2[0];ec2b93b[1023]<=ykc1859[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module hq8ca24 ( qvb4f6d,\r
- baa7b6d,\r
- txmac_clk_en,\r
-\r
- gq24775, \r
- sj23ba9, \r
- kf1dd4d, \r
- pseea6c, \r
- qt75363, \r
- wya9b1c \r
- );\r
-parameter ps4d8e0 = 5;\r
-input qvb4f6d;\r
-input baa7b6d;\r
-input txmac_clk_en;\r
-input gq24775;\r
-input kf1dd4d;\r
-input pseea6c;\r
-input [ps4d8e0-1:0] sj23ba9;\r
-output wya9b1c;\r
-output qt75363;\r
-reg [ps4d8e0-1:0] osd15dd;\r
-reg [ps4d8e0-1:0] zk5774c;\r
-reg cbbba62;\r
-reg qt75363;\r
-reg fne98a7;\r
-reg ic4c53e;\r
-reg wya9b1c;\r
-parameter tw14f81 = 1'b0;\r
-parameter fca7c0a = 1'b1;\r
-wire [ps4d8e0-1:0] suf0299 = sj23ba9 - 5'd1;\r
-reg [ps4d8e0-1:0] go53231;\r
-wire fc99188 = gq24775 & ~cbbba62;\r
-reg wy310f9;\r
-reg [ps4d8e0 - 1 : 0] su43e40;\r
-reg ou1f200;\r
-reg xjf9000;\r
-reg [ps4d8e0 - 1 : 0] ld40036;\r
-reg [ps4d8e0 - 1 : 0] codb0;\r
-reg xl6d81;\r
-reg ep36c0e;\r
-reg ecb6074;\r
-reg [ps4d8e0 - 1 : 0] lf81d0e;\r
-reg [ps4d8e0 - 1 : 0] xj743ba;\r
-reg cba1dd6;\r
-reg [2047:0] ec2b93b;\r
-wire [11:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 12,ph27642 = 32'hfdffe0cb;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-always @ (ld40036 or xj743ba) begin if(ld40036 == xj743ba) wya9b1c = 1'b1; else wya9b1c = 1'b0; end\r
- always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin fne98a7 <= tw14f81; go53231 <= 6'b0; end else if (txmac_clk_en) begin fne98a7 <= ecb6074; go53231 <= lf81d0e; end end always @ (ep36c0e or wy310f9 or wya9b1c) begin case(ep36c0e) tw14f81: begin if(!wy310f9) begin ic4c53e = tw14f81; end else begin ic4c53e = fca7c0a; end end fca7c0a: begin if(wya9b1c) begin ic4c53e = tw14f81; end else begin ic4c53e = fca7c0a; end end endcase end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin osd15dd <= 5'd0; end else if (txmac_clk_en) begin if(ou1f200) begin osd15dd <= 5'd0; end else if(ecb6074) begin osd15dd <= ld40036 + 5'd1; end else begin osd15dd <= 5'd0; end end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin cbbba62 <= 1'b0; end else if (txmac_clk_en) begin cbbba62 <= wy310f9; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) zk5774c <= 5'd0; else if (txmac_clk_en) begin if( (cba1dd6 || ((codb0 != xj743ba) && (codb0 != 5'd0)) ) && (qt75363 || !xjf9000) ) zk5774c <= codb0 + 5'd1; else if(!cba1dd6) begin zk5774c <= 5'd0; end end end\r
- always @ (su43e40 or codb0) begin case(su43e40) 5'd24: qt75363 = codb0[4]; 5'd27: qt75363 = codb0[4] & (|codb0[3:1]); 5'd30: qt75363 = codb0[4] & (|codb0[3:2]); default: qt75363 = 1'b0; endcase end\r
-always@* begin wy310f9<=ea5c9d9[0];su43e40<={sj23ba9>>1,ea5c9d9[1]};ou1f200<=ea5c9d9[2];xjf9000<=ea5c9d9[3];ld40036<={osd15dd>>1,ea5c9d9[4]};codb0<={zk5774c>>1,ea5c9d9[5]};xl6d81<=ea5c9d9[6];ep36c0e<=ea5c9d9[7];ecb6074<=ea5c9d9[8];lf81d0e<={suf0299>>1,ea5c9d9[9]};xj743ba<={go53231>>1,ea5c9d9[10]};cba1dd6<=ea5c9d9[11];end\r
-always@* begin ec2b93b[2047]<=sj23ba9[0];ec2b93b[2046]<=kf1dd4d;ec2b93b[2044]<=pseea6c;ec2b93b[2040]<=osd15dd[0];ec2b93b[2033]<=zk5774c[0];ec2b93b[2018]<=cbbba62;ec2b93b[1988]<=fne98a7;ec2b93b[1929]<=ic4c53e;ec2b93b[1811]<=suf0299[0];ec2b93b[1574]<=go53231[0];ec2b93b[1101]<=fc99188;ec2b93b[1023]<=gq24775;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module uved7f1 (txmac_clk,\r
- baa7b6d,\r
- txmac_clk_en, \r
- lqf1bfb, \r
- mg8dfdb, \r
- cz6fed9, \r
- qt7f6cd, \r
- fafb66d, \r
- uidb36b, \r
- shd9b58, \r
- dzcdac4, \r
- go6d627, \r
- xj6b139, \r
- xw589ce, \r
- tx_fifoavail, \r
- ph27391, \r
- ir39c8e, \r
- suce475, \r
- ww723a9, \r
- zz91d49, \r
- db8ea4e, \r
- wya9b1c, \r
- eca93b4, \r
- ea49da1, \r
- qt4ed09, \r
- dm7684c, \r
- cm6d7e0, \r
- qt75363, \r
- zz98a5, \r
- ay4c52f, \r
- ea62978, \r
- tx_discfrm, \r
- tja5e0a, \r
- ng2f056, \r
- ui782b2, \r
- goc1590, \r
- wyac80, \r
- yk56400, \r
- twb2000, \r
- gq24775, \r
- oh8001d, \r
- wjedb5f, \r
- mg760, \r
- vx3b00, \r
- oh1d806, \r
- xjec034, \r
- cz601a7, \r
- ksd3d, \r
- jr69e9, \r
- uk34f4e, \r
- hqa7a71, \r
- bn3d38b, \r
- nre9c5e, \r
- wj4e2f6, \r
- fn717b5, \r
- ph8bdae, \r
- wj5ed76, \r
- os6dafc, \r
- bnb5dae, \r
- mtaed77, \r
- rg76bbd, \r
- hdb5dea, \r
- iraef57, \r
- kf1dd4d, \r
- pseea6c, \r
- kqeaf42 \r
- );\r
-parameter by57a11 = 48;\r
-parameter vkbd08b = 16;\r
-parameter qte845a = 8;\r
-parameter xw422d5 = 16;\r
-parameter hq116ab = 32;\r
-parameter tj8b55b = 14;\r
-parameter rt6bf01 = 4;\r
-parameter vid56ff = 22;\r
-parameter anab7fb = 13;\r
-parameter wj5bfdc = 13'd6072;\r
-parameter lqdfee5 = 8'h55;\r
-parameter ayff72b = 8'hd5;\r
-parameter hofb959 = 8'h00;\r
-parameter ipdcaca = 8'h01;\r
-parameter yke5654 = 8'h80;\r
-parameter ec2b2a1 = 8'hc2;\r
-parameter ay59508 = 8'h00;\r
-parameter rgca841 = 8'h00;\r
-parameter mr5420a = 8'h01;\r
-parameter gda1055 = 8'h88;\r
-parameter sj82ad = 8'h08;\r
-parameter uv4156c = 8'h00;\r
-input txmac_clk;\r
-input baa7b6d;\r
-input txmac_clk_en;\r
-input lqf1bfb;\r
-input mg8dfdb;\r
-input cz6fed9;\r
-input qt7f6cd;\r
-input fafb66d;\r
-input uidb36b;\r
-input [by57a11-1:0] shd9b58;\r
-input [vkbd08b-1:0] dzcdac4;\r
-input [qte845a-1:0] go6d627;\r
-input xj6b139;\r
-input xw589ce;\r
-input tx_fifoavail;\r
-input ph27391;\r
-input suce475;\r
-input ww723a9;\r
-input [xw422d5-1:0] zz91d49;\r
-input db8ea4e;\r
-input wya9b1c;\r
-input [hq116ab-1:0] eca93b4;\r
-input ea49da1;\r
-input qt4ed09;\r
-input [qte845a:0] ir39c8e;\r
-input dm7684c;\r
-input cm6d7e0;\r
-input qt75363;\r
-input zz98a5;\r
-input ay4c52f;\r
-output ea62978;\r
-output tx_discfrm;\r
-output tja5e0a;\r
-output ng2f056;\r
-output ui782b2;\r
-output [qte845a-1:0] goc1590;\r
-output wyac80;\r
-output [qte845a-1:0] yk56400;\r
-output twb2000;\r
-output gq24775;\r
-output oh8001d;\r
-output wjedb5f;\r
-output mg760;\r
-output vx3b00;\r
-output oh1d806;\r
-output xjec034;\r
-output cz601a7;\r
-output ksd3d;\r
-output jr69e9;\r
-output uk34f4e;\r
-output hqa7a71;\r
-output bn3d38b;\r
-output nre9c5e;\r
-output wj4e2f6;\r
-output fn717b5;\r
-output ph8bdae;\r
-output wj5ed76;\r
-output [rt6bf01-1:0] os6dafc;\r
-output bnb5dae;\r
-output mtaed77;\r
-output rg76bbd;\r
-output hdb5dea;\r
-output iraef57;\r
-output kf1dd4d;\r
-output pseea6c;\r
-output kqeaf42;\r
-reg [4:0] fne98a7 ;\r
-reg [4:0] ic4c53e;\r
-reg gq24775;\r
-reg xwe447a;\r
-reg zz223d3;\r
-reg [qte845a-1:0] ep8f4f2;\r
-reg [qte845a-1:0] gbd3cad;\r
-reg [qte845a-1:0] yxf2b6e;\r
-reg [qte845a-1:0] goc1590;\r
-reg ea62978;\r
-reg dz6e910;\r
-reg zx74887;\r
-reg wla443f;\r
-reg ui782b2;\r
-reg wy10fee;\r
-reg co87f70;\r
-reg ri3fb80;\r
-reg [1:0] kdfdc02;\r
-reg [1:0] jcee015;\r
-reg qt700aa;\r
-reg yz80554;\r
-reg tja5e0a;\r
-reg ng2f056;\r
-reg tx_discfrm;\r
-reg yx5490f;\r
-reg uxa487c;\r
-reg uk243e4;\r
-reg wyac80;\r
-reg oh8001d;\r
-reg rg76bbd;\r
-reg bnb5dae;\r
-reg mtaed77;\r
-reg kqeaf42;\r
-reg [rt6bf01-1:0] os6dafc;\r
-reg ph8bdae;\r
-reg fn717b5;\r
-reg wj5ed76;\r
-reg wjedb5f;\r
-reg db3752b;\r
-reg [anab7fb-1:0] ayd4afe;\r
-reg hdb5dea;\r
-reg iraef57;\r
-reg kf1dd4d;\r
-reg vife1cf;\r
-reg suf0e7b;\r
-reg qi873d9;\r
-reg pseea6c;\r
-reg [3:0] necf64d;\r
-reg ld7b26b;\r
-reg shd935f;\r
-reg [1:0] gbc9afd;\r
-reg fa4d7ed;\r
-reg vv6bf6a;\r
-reg nr5fb57;\r
-reg shfdabf;\r
-parameter wjed5fd = 5'd0;\r
-parameter uv6afed = 5'd1;\r
-parameter dm57f6d = 5'd2;\r
-parameter ntbfb6b = 5'd3;\r
-parameter enfdb5e = 5'd4;\r
-parameter ofedaf5 = 5'd5;\r
-parameter cm6d7ac = 5'd6;\r
-parameter rt6bd61 = 5'd7;\r
-parameter gb5eb0f = 5'd8;\r
-parameter mef587d = 5'd9;\r
-parameter ukac3e9 = 5'd10;\r
-parameter fn61f49 = 5'd11;\r
-parameter ecfa4e = 5'd12;\r
-parameter kq7d270 = 5'd13;\r
-parameter hbe9380 = 5'd14;\r
-parameter cm49c07 = 5'd15;\r
-parameter al4e039 = 5'd16;\r
-parameter kd701cd = 5'd17;\r
-parameter cb80e6c = 5'd18;\r
-parameter wl7365 = 5'd19;\r
-parameter an39b2d = 5'd20;\r
-parameter jpcd96d = 5'd21;\r
-wire mg760 = (fne98a7 == wjed5fd) ? 1 : 0;\r
-wire vx3b00 = (fne98a7 == uv6afed) ? 1 : 0;\r
-wire oh1d806 = (fne98a7 == dm57f6d) ? 1 : 0;\r
-wire xjec034 = (fne98a7 == ntbfb6b) ? 1 : 0;\r
-wire cz601a7 = (fne98a7 == enfdb5e) ? 1 : 0;\r
-wire jr69e9 = (fne98a7 == ofedaf5) ? 1 : 0;\r
-wire ksd3d = (fne98a7 == cm6d7ac) ? 1 : 0;\r
-wire uk34f4e = (fne98a7 == rt6bd61) ? 1 : 0;\r
-wire hqa7a71 = (fne98a7 == gb5eb0f) ? 1 : 0;\r
-wire bn3d38b = (fne98a7 == mef587d) ? 1 : 0;\r
-wire lqe4c7d = (fne98a7 == ukac3e9) ? 1 : 0;\r
-wire nre9c5e = (fne98a7 == fn61f49) ? 1 : 0;\r
-wire mr54301 = (fne98a7 == ecfa4e) ? 1 : 0;\r
-wire wj60366 = (fne98a7 == kq7d270) ? 1 : 0;\r
-wire wj4e2f6 = (fne98a7 == hbe9380) ? 1 : 0;\r
-wire gdaba9a = (fne98a7 == cm49c07) ? 1 : 0;\r
-wire kq53558 = (fne98a7 == al4e039) ? 1 : 0;\r
-wire irab02b = (fne98a7 == kd701cd) ? 1 : 0;\r
-wire qi571b = (ayd4afe == wj5bfdc);\r
-wire [qte845a-1:0] yk56400 = gbd3cad[7:0];\r
-wire twb2000 = yz80554;\r
-reg [2:0] uv4e5c7;\r
-reg [5:0] me72e3d;\r
-reg [7:0] qi971e8;\r
-reg hqb8f40;\r
-reg nrc7a03;\r
-reg db3d01e;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg cze80f6;\r
-reg rt407b5;\r
-reg jr3dae;\r
-reg vk1ed76;\r
-reg fnf6bb3;\r
-reg phb5d9e;\r
-reg [by57a11 - 1 : 0] dm767bd;\r
-reg [vkbd08b - 1 : 0] bn9ef58;\r
-reg [qte845a - 1 : 0] zmbd63c;\r
-reg vieb1e2;\r
-reg ho58f12;\r
-reg thc7892;\r
-reg yz3c496;\r
-reg [qte845a : 0] an125a4;\r
-reg ie92d24;\r
-reg zm96921;\r
-reg [xw422d5 - 1 : 0] ana485d;\r
-reg qi242ec;\r
-reg sw21761;\r
-reg [hq116ab - 1 : 0] zk5d84a;\r
-reg hbec252;\r
-reg fn61297;\r
-reg lf94bf;\r
-reg rt4a5fe;\r
-reg ps52ff7;\r
-reg co97fbb;\r
-reg fpbfdd9;\r
-reg [4 : 0] ep36c0e;\r
-reg [4 : 0] ecb6074;\r
-reg gdbb395;\r
-reg end9cad;\r
-reg [qte845a - 1 : 0] ww72b61;\r
-reg [qte845a - 1 : 0] ngad844;\r
-reg [qte845a - 1 : 0] nr61113;\r
-reg wl889f;\r
-reg en444fd;\r
-reg jr227ec;\r
-reg nt13f66;\r
-reg oh9fb37;\r
-reg alfd9bd;\r
-reg [1 : 0] jpecded;\r
-reg [1 : 0] ps66f6e;\r
-reg nt37b73;\r
-reg zmbdb9e;\r
-reg aledcf3;\r
-reg xj6e79c;\r
-reg xw73ce6;\r
-reg db9e732;\r
-reg [anab7fb - 1 : 0] zm9ccb6;\r
-reg hbe65b2;\r
-reg xl32d96;\r
-reg ba96cb6;\r
-reg [3 : 0] ukb65b3;\r
-reg hqb2d99;\r
-reg do96cca;\r
-reg [1 : 0] ksb6653;\r
-reg ecb3299;\r
-reg je994c9;\r
-reg lqca64b;\r
-reg su5325b;\r
-reg xy992d8;\r
-reg uvc96c3;\r
-reg kd4b61c;\r
-reg mr5b0e5;\r
-reg hbd872c;\r
-reg [2 : 0] wjc3967;\r
-reg [5 : 0] xl1cb3c;\r
-reg [7 : 0] ose59e6;\r
-reg an2cf30;\r
-reg ui67984;\r
-reg an3cc21;\r
-reg [2047:0] ec2b93b;\r
-wire [70:0] ea5c9d9;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam tue4ec8 = 71,ph27642 = 32'hfdffd48b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin fne98a7 <= wjed5fd; db3d01e <= 0; gbd3cad <= 0; zx74887 <= 0; uxa487c <= 0; yz80554 <= 0; ri3fb80 <= 0; jcee015 <= 0; yxf2b6e <= 0; wla443f <= 0; uk243e4 <= 0; goc1590 <= 0; ui782b2 <= 0; wyac80 <= 0; oh8001d <= 0; end else if (txmac_clk_en) begin oh8001d <= zm96921 & (mg760 | vx3b00) ? 1'b1 : ~zm96921 ? 1'b0 : oh8001d; fne98a7 <= ecb6074; db3d01e <= ie92d24; gbd3cad <= ww72b61; zx74887 <= wl889f; uxa487c <= aledcf3; yz80554 <= nt37b73; ri3fb80 <= oh9fb37; jcee015 <= jpecded; wla443f <= en444fd | nt13f66; uk243e4 <= xj6e79c; if (alfd9bd == 1) begin case (ps66f6e) 3: begin yxf2b6e <= zk5d84a[7:0]; end 2: begin yxf2b6e <= zk5d84a[15:8]; end 1: begin yxf2b6e <= zk5d84a[23:16]; end 0: begin yxf2b6e <= zk5d84a[31:24]; end endcase end else begin yxf2b6e <= ngad844; end goc1590 <= nr61113; ui782b2 <= jr227ec; wyac80 <= xw73ce6; end end always @ (ep36c0e or thc7892 or zmbd63c or vieb1e2 or an3cc21 or cze80f6 or vk1ed76 or rt407b5 or sw21761 or zm96921 or fn61297 or lf94bf or qi242ec or pseea6c or jr3dae or gdbb395 or yz3c496 or hbec252 or ba96cb6 or an125a4 or os6dafc or ps52ff7 or co97fbb or ecb3299 or end9cad or shfdabf or nr5fb57 or do96cca or mtaed77 or bnb5dae or fpbfdd9 or wjc3967 or ui67984 or ose59e6) begin gq24775 = 0; ep8f4f2 = 0; ea62978 = 0; dz6e910 = 0; wy10fee = 0; ph8bdae = 0; qt700aa = 0; kdfdc02 = 0; co87f70 = 0; ng2f056 = 0; tx_discfrm = 0; yx5490f = 0; fn717b5 = 0; wj5ed76 = 0; db3752b = 0; wjedb5f = 0; tja5e0a = 0; iraef57 = 0; kf1dd4d = 0; ld7b26b = 0; vv6bf6a = 0;\r
- case (ep36c0e) wjed5fd: begin if(sw21761) begin ic4c53e = uv6afed; gq24775 = 1'b0; end else begin\r
-\r
-\r
- if(pseea6c && !ps52ff7 && jr3dae) begin if(thc7892) begin ic4c53e = cm49c07; end else begin ic4c53e = wjed5fd; end gq24775 = 1'b0; kf1dd4d = 1'b1; end else begin ic4c53e = wjed5fd; gq24775 = 1'b1; end\r
-\r
-\r
- end end uv6afed: begin\r
-\r
-\r
- if(cze80f6) begin if(jr3dae) begin if (thc7892) begin if(!pseea6c || ps52ff7) begin ic4c53e = dm57f6d; end else begin ic4c53e = cm49c07; end end else begin ic4c53e = uv6afed; end end else begin if( (thc7892 && (!zm96921 || an3cc21)) || (rt407b5 && qi242ec) ) begin ic4c53e = dm57f6d; end else begin ic4c53e = uv6afed; end end end else begin ic4c53e = uv6afed; end \r
-\r
-\r
-\r
- end \r
-\r
-\r
- cm49c07: begin if(pseea6c) begin ic4c53e = cm49c07; db3752b = 1'b1; kf1dd4d = 1'b1; end else begin ic4c53e = al4e039; end end\r
-\r
-\r
-\r
- al4e039: begin if(sw21761) begin ic4c53e = dm57f6d; gq24775 = 1'b0; end else begin\r
-\r
-\r
- if(!pseea6c || ps52ff7) begin ic4c53e = al4e039; gq24775 = 1'b1; end else begin ic4c53e = cm49c07; gq24775 = 1'b0; kf1dd4d = 1'b1; end\r
-\r
-\r
- end end\r
- dm57f6d: begin ep8f4f2 = lqdfee5; dz6e910 = 1; if(wjc3967 == 0) begin ic4c53e = ntbfb6b; end else begin ic4c53e = dm57f6d; end end ntbfb6b: begin ep8f4f2 = ayff72b; dz6e910 = 1;\r
-\r
-\r
- if(jr3dae) begin if(ba96cb6 || end9cad) begin if(os6dafc == 4'hf) ic4c53e = kd701cd; else begin ic4c53e = ukac3e9; end end else begin if(yz3c496) begin ic4c53e = enfdb5e; end else begin fn717b5 = 1; ic4c53e = hbe9380; end end end else begin if(qi242ec && rt407b5) ic4c53e = ofedaf5; else begin ic4c53e = enfdb5e; end end \r
-\r
-\r
- end enfdb5e: begin ea62978 = 1; dz6e910 = 1'b1; ep8f4f2 = zmbd63c[7:0]; qt700aa = 1;\r
-\r
-\r
- if(co97fbb) begin if(fn61297) begin ic4c53e = cm6d7ac; end else begin ic4c53e = gb5eb0f; end end else if(jr3dae) begin if(hbec252) begin ph8bdae = 1'b1; end if(ba96cb6 || gdbb395) begin if(hbec252 && (os6dafc == 4'hf) ) begin ic4c53e = kd701cd; end else if(hbec252) begin iraef57 = 1'b1; ic4c53e = ukac3e9; end else begin ic4c53e = mef587d; end end else if (vieb1e2 && !vk1ed76) begin if(fn61297 && !lf94bf) begin ic4c53e = cm6d7ac; end else begin ic4c53e = rt6bd61; end end else if (vieb1e2 && vk1ed76) begin ic4c53e = cb80e6c; end else begin ic4c53e = enfdb5e; end end else begin if(vieb1e2 && !vk1ed76) begin if(fn61297 && !lf94bf) begin ic4c53e = cm6d7ac; end else begin ic4c53e = rt6bd61; end end else if(vieb1e2 && vk1ed76) begin ic4c53e = cb80e6c; end else begin ic4c53e = enfdb5e; end end \r
-\r
-\r
- end \r
- ofedaf5: begin ep8f4f2 = ose59e6; dz6e910 = 1; qt700aa = 1; if(ui67984) begin ic4c53e = rt6bd61; end else begin ic4c53e = ofedaf5; end end \r
- cm6d7ac: begin dz6e910 = 1; qt700aa = 1; ep8f4f2 = hofb959; \r
-\r
-\r
- if(jr3dae && (ba96cb6 || gdbb395)) begin if(os6dafc == 4'hf) begin ic4c53e = kd701cd; end else begin if(!co97fbb) begin iraef57 = 1'b1; ic4c53e = ukac3e9; end else begin ic4c53e = gb5eb0f; end end end else if(vk1ed76 && co97fbb && fpbfdd9) begin ic4c53e = mef587d; end else if(lf94bf) begin if(co97fbb) begin ic4c53e = gb5eb0f; end else begin ic4c53e = rt6bd61; end end else begin ic4c53e = cm6d7ac; end\r
-\r
-\r
- end rt6bd61: begin dz6e910 = 1; co87f70 = 1; case (wjc3967[1:0]) 3: begin kdfdc02 = 2'h3; end 2: begin kdfdc02 = 2'h2; end 1: begin kdfdc02 = 2'h1; end 0: begin kdfdc02 = 2'h0; end endcase\r
-\r
-\r
- if(jr3dae && (ba96cb6 || gdbb395)) begin ic4c53e = mef587d; end else if (wjc3967[1:0] == 2'b00) begin ic4c53e = cb80e6c; end else begin ic4c53e = rt6bd61; end\r
-\r
-\r
- end\r
- cb80e6c: begin wy10fee = 1;\r
-\r
-\r
- if(jr3dae && (ba96cb6 || gdbb395)) begin ic4c53e = wl7365; vv6bf6a = 1; end else begin ic4c53e = jpcd96d; end \r
-\r
-\r
- end \r
- jpcd96d: begin\r
-\r
-\r
- if(jr3dae && (ba96cb6 || gdbb395)) begin ic4c53e = wl7365; vv6bf6a = 1; wy10fee = 1; end else begin ng2f056 = 1; wj5ed76 = 1; tja5e0a = 1; ic4c53e = wjed5fd; end \r
-\r
-\r
- end \r
-\r
-\r
-\r
- wl7365: begin wy10fee = 1; vv6bf6a = 1; if(ecb3299) begin ic4c53e = an39b2d; end else begin ic4c53e = wl7365; end end an39b2d: begin wy10fee = 1; ic4c53e = wjed5fd; tx_discfrm = 1; tja5e0a = 1; wj5ed76 = 1; end \r
-\r
-\r
-\r
- gb5eb0f: begin dz6e910 = 1; co87f70 = 1; kdfdc02 = 2'h3; yx5490f = 1; if (wjc3967[1:0] == 2'b01) begin ic4c53e = mef587d; end else begin ic4c53e = gb5eb0f; end end\r
-\r
-\r
-\r
- kd701cd: begin dz6e910 = 1; co87f70 = 1; kdfdc02 = 2; yx5490f = 0; ic4c53e = mef587d; end\r
-\r
-\r
-\r
- mef587d: begin dz6e910 = 1;\r
-\r
-\r
- if(mtaed77 || bnb5dae) begin ld7b26b = 1; if(do96cca) begin yx5490f = 0; tx_discfrm = 1; wj5ed76 = 1; tja5e0a = 1; ic4c53e = wjed5fd; end else begin ic4c53e = mef587d; end end else begin co87f70 = 1; kdfdc02 = 1; yx5490f = 1; tx_discfrm = 1; wj5ed76 = 1; tja5e0a = 1; ic4c53e = wjed5fd; end\r
-\r
-\r
- end\r
-\r
-\r
- ukac3e9: begin dz6e910 = 1; ld7b26b = 1; if(do96cca) begin ic4c53e = fn61f49; end else begin ic4c53e = ukac3e9; end end\r
- fn61f49: begin case ({shfdabf, nr5fb57}) 2'b00: begin gq24775 = 1; wjedb5f = 1; ic4c53e = fn61f49; end 2'b01: begin gq24775 = 1; wjedb5f = 0; ic4c53e = fn61f49; end 2'b10: begin gq24775 = 0; wjedb5f = 1; ic4c53e = fn61f49; end 2'b11: begin gq24775 = 0; wjedb5f = 0; if(pseea6c) begin ic4c53e = ecfa4e; db3752b = 1; end else begin ic4c53e = dm57f6d; end end endcase end ecfa4e: begin if(pseea6c) begin ic4c53e = ecfa4e; db3752b = 1; end else begin ic4c53e = kq7d270; gq24775 = 1; end end\r
-\r
-\r
-\r
- kq7d270: begin if(sw21761) begin ic4c53e = dm57f6d; gq24775 = 0; end else begin\r
-\r
-\r
- if(pseea6c && !ps52ff7 && jr3dae) begin ic4c53e = ecfa4e; gq24775 = 0; kf1dd4d = 1; end else begin ic4c53e = kq7d270; gq24775 = 1; end\r
-\r
-\r
- end end hbe9380: begin fn717b5 = 1; dz6e910 = 1; ep8f4f2 = an125a4[7:0];\r
-\r
-\r
- if(gdbb395) begin if(os6dafc == 4'hf) ic4c53e = kd701cd; else begin ic4c53e = ukac3e9; iraef57 = 1'b1; end end else if(yz3c496) begin fn717b5 = 0; if(an125a4[8]) ic4c53e = cm6d7ac; else begin ic4c53e = enfdb5e; end end else begin ic4c53e = hbe9380; end\r
-\r
-\r
- end default: ic4c53e = wjed5fd;\r
- endcase end \r
-\r
-\r
-\r
- always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin xwe447a <= 0; end else if (txmac_clk_en) begin if(ba96cb6 && (oh1d806 || xjec034 || cz601a7 || ksd3d || uk34f4e || wj4e2f6)) begin xwe447a <= 1; end else if(mg760 || nre9c5e) begin xwe447a <= 0; end end end always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin zz223d3 <= 0; end else if (txmac_clk_en) begin if(ba96cb6 && oh1d806) begin zz223d3 <= 1; end else if(mg760 || nre9c5e) begin zz223d3 <= 0; end end end always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin os6dafc <= 4'h0; end else if (txmac_clk_en) begin if( do96cca ) begin os6dafc <= os6dafc + 4'h1; end else if(mg760) begin os6dafc <= 4'h0; end end end\r
-\r
- always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin bnb5dae <= 0; end else if (txmac_clk_en) begin if(ba96cb6 && !hbec252 && jr3dae) begin bnb5dae <= 1; end else if(mg760) begin bnb5dae <= 0; end end end always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin rg76bbd <= 0; end else if (txmac_clk_en) begin if(uvc96c3 || su5325b) begin rg76bbd <= 1; end else if(mg760) begin rg76bbd <= 0; end end end always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin mtaed77 <= 0; end else if (txmac_clk_en) begin if(mr5b0e5) begin mtaed77 <= 1; end else if(mg760) begin mtaed77 <= 0; end end end always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin hdb5dea <= 0; end else if (txmac_clk_en) begin if(hbd872c) begin hdb5dea <= 1; end else if(mg760) begin hdb5dea <= 0; end end end always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin ayd4afe <= 13'd0; end else if (txmac_clk_en) begin if(db9e732) begin ayd4afe <= zm9ccb6 + 13'd1; end else begin ayd4afe <= 13'd0; end end end\r
-\r
-\r
-\r
- always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin kqeaf42 <= 0; end else if (txmac_clk_en) begin if(hqa7a71) begin kqeaf42 <= 1; end else if(mg760) begin kqeaf42 <= 0; end end end always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin uv4e5c7 <= 0; end else if (txmac_clk_en) begin if ((vx3b00) || (kd4b61c) || (nre9c5e) || (xy992d8)) begin uv4e5c7 <= 6; end else if ((cz601a7) || (jr69e9) || (ksd3d)) begin uv4e5c7 <= 3; end else if (wjc3967 != 0) begin uv4e5c7 <= wjc3967 - 1; end end end always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin qi971e8 <= 0; me72e3d <= 0; hqb8f40 <= 0; nrc7a03 <= 0; end else if (txmac_clk_en) begin if (oh1d806) begin me72e3d <= 0; hqb8f40 <= 0; nrc7a03 <= 0; end else begin me72e3d <= xl1cb3c + 1; if (xl1cb3c == 18) begin hqb8f40 <= 1; end if (xl1cb3c == 59) begin nrc7a03 <= 1; end end case ({an2cf30,xl1cb3c}) 0: begin qi971e8 <= ipdcaca; end 1: begin qi971e8 <= yke5654; end 2: begin qi971e8 <= ec2b2a1; end 3: begin qi971e8 <= ay59508; end 4: begin qi971e8 <= rgca841; end 5: begin qi971e8 <= mr5420a; end 6: begin qi971e8 <= dm767bd[47:40]; end 7: begin qi971e8 <= dm767bd[39:32]; end 8: begin qi971e8 <= dm767bd[31:24]; end 9: begin qi971e8 <= dm767bd[23:16]; end 10: begin qi971e8 <= dm767bd[15:8]; end 11: begin qi971e8 <= dm767bd[7:0]; end 12: begin qi971e8 <= gda1055; end 13: begin qi971e8 <= sj82ad; end 14: begin qi971e8 <= bn9ef58[15:8]; end 15: begin qi971e8 <= bn9ef58[7:0]; end 16: begin qi971e8 <= ana485d[15:8]; end 17: begin qi971e8 <= ana485d[7:0]; end default: begin qi971e8 <= uv4156c; end endcase end end\r
-\r
-\r
- always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin gbc9afd <= 0; end else if (txmac_clk_en) begin if(je994c9) begin gbc9afd <= ksb6653 + 1; end else begin gbc9afd <= 0; end end end always @ (ksb6653) begin if(ksb6653 == 2'b11) begin fa4d7ed = 1; end else begin fa4d7ed = 0; end end\r
- always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin necf64d <= 4'h0; end else if (txmac_clk_en) begin if(hqb2d99) begin necf64d <= ukb65b3 + 4'h1; end else begin necf64d <= 4'h0; end end end always @ (ukb65b3) begin shd935f = (ukb65b3 == 4'h3) ? 1'b1 : 1'b0; end\r
- always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin vife1cf <= 0; suf0e7b <= 0; qi873d9 <= 0; pseea6c <= 0; end else if (txmac_clk_en) begin vife1cf <= phb5d9e; suf0e7b <= fnf6bb3; qi873d9 <= hbe65b2; pseea6c <= xl32d96; end end \r
- always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin shfdabf = 0; end else if (txmac_clk_en) begin if(nre9c5e && sw21761) begin shfdabf = 1; end else if(oh1d806 || su5325b) begin shfdabf = 0; end end end\r
- always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin nr5fb57 = 0; end else if (txmac_clk_en) begin if(nre9c5e && rt4a5fe) begin nr5fb57 = 1; end else if(oh1d806 || su5325b) begin nr5fb57 = 0; end end end\r
-\r
-\r
-\r
-\r
-always@* begin cze80f6<=ea5c9d9[0];rt407b5<=ea5c9d9[1];jr3dae<=ea5c9d9[2];vk1ed76<=ea5c9d9[3];fnf6bb3<=ea5c9d9[4];phb5d9e<=ea5c9d9[5];dm767bd<={shd9b58>>1,ea5c9d9[6]};bn9ef58<={dzcdac4>>1,ea5c9d9[7]};zmbd63c<={go6d627>>1,ea5c9d9[8]};vieb1e2<=ea5c9d9[9];ho58f12<=ea5c9d9[10];thc7892<=ea5c9d9[11];yz3c496<=ea5c9d9[12];an125a4<={ir39c8e>>1,ea5c9d9[13]};ie92d24<=ea5c9d9[14];zm96921<=ea5c9d9[15];ana485d<={zz91d49>>1,ea5c9d9[16]};qi242ec<=ea5c9d9[17];sw21761<=ea5c9d9[18];zk5d84a<={eca93b4>>1,ea5c9d9[19]};hbec252<=ea5c9d9[20];fn61297<=ea5c9d9[21];lf94bf<=ea5c9d9[22];rt4a5fe<=ea5c9d9[23];ps52ff7<=ea5c9d9[24];co97fbb<=ea5c9d9[25];fpbfdd9<=ea5c9d9[26];ep36c0e<={fne98a7>>1,ea5c9d9[27]};ecb6074<={ic4c53e>>1,ea5c9d9[28]};gdbb395<=ea5c9d9[29];end9cad<=ea5c9d9[30];ww72b61<={ep8f4f2>>1,ea5c9d9[31]};ngad844<={gbd3cad>>1,ea5c9d9[32]};nr61113<={yxf2b6e>>1,ea5c9d9[33]};wl889f<=ea5c9d9[34];en444fd<=ea5c9d9[35];jr227ec<=ea5c9d9[36];nt13f66<=ea5c9d9[37];oh9fb37<=ea5c9d9[38];alfd9bd<=ea5c9d9[39];jpecded<={kdfdc02>>1,ea5c9d9[40]};ps66f6e<={jcee015>>1,ea5c9d9[41]};nt37b73<=ea5c9d9[42];zmbdb9e<=ea5c9d9[43];aledcf3<=ea5c9d9[44];xj6e79c<=ea5c9d9[45];xw73ce6<=ea5c9d9[46];db9e732<=ea5c9d9[47];zm9ccb6<={ayd4afe>>1,ea5c9d9[48]};hbe65b2<=ea5c9d9[49];xl32d96<=ea5c9d9[50];ba96cb6<=ea5c9d9[51];ukb65b3<={necf64d>>1,ea5c9d9[52]};hqb2d99<=ea5c9d9[53];do96cca<=ea5c9d9[54];ksb6653<={gbc9afd>>1,ea5c9d9[55]};ecb3299<=ea5c9d9[56];je994c9<=ea5c9d9[57];lqca64b<=ea5c9d9[58];su5325b<=ea5c9d9[59];xy992d8<=ea5c9d9[60];uvc96c3<=ea5c9d9[61];kd4b61c<=ea5c9d9[62];mr5b0e5<=ea5c9d9[63];hbd872c<=ea5c9d9[64];wjc3967<={uv4e5c7>>1,ea5c9d9[65]};xl1cb3c<={me72e3d>>1,ea5c9d9[66]};ose59e6<={qi971e8>>1,ea5c9d9[67]};an2cf30<=ea5c9d9[68];ui67984<=ea5c9d9[69];an3cc21<=ea5c9d9[70];end\r
-always@* begin ec2b93b[2047]<=mg8dfdb;ec2b93b[2046]<=cz6fed9;ec2b93b[2044]<=qt7f6cd;ec2b93b[2040]<=fafb66d;ec2b93b[2032]<=uidb36b;ec2b93b[2018]<=qt700aa;ec2b93b[2017]<=shd9b58[0];ec2b93b[1989]<=yz80554;ec2b93b[1987]<=dzcdac4[0];ec2b93b[1931]<=yx5490f;ec2b93b[1927]<=go6d627[0];ec2b93b[1865]<=zz91d49[0];ec2b93b[1859]<=yxf2b6e[0];ec2b93b[1844]<=ld7b26b;ec2b93b[1815]<=uxa487c;ec2b93b[1806]<=xj6b139;ec2b93b[1682]<=db8ea4e;ec2b93b[1674]<=lqe4c7d;ec2b93b[1671]<=dz6e910;ec2b93b[1640]<=shd935f;ec2b93b[1582]<=uk243e4;ec2b93b[1565]<=xw589ce;ec2b93b[1488]<=ep8f4f2[0];ec2b93b[1485]<=qi873d9;ec2b93b[1326]<=ay4c52f;ec2b93b[1317]<=wya9b1c;ec2b93b[1300]<=mr54301;ec2b93b[1297]<=uv4e5c7[0];ec2b93b[1295]<=zx74887;ec2b93b[1233]<=gbc9afd[0];ec2b93b[1210]<=ic4c53e[0];ec2b93b[1189]<=cm6d7e0;ec2b93b[1172]<=ea49da1;ec2b93b[1116]<=db3752b;ec2b93b[1105]<=gdaba9a;ec2b93b[1092]<=qi971e8[0];ec2b93b[1087]<=wy10fee;ec2b93b[1082]<=tx_fifoavail;ec2b93b[1023]<=lqf1bfb;ec2b93b[1009]<=jcee015[0];ec2b93b[932]<=ww723a9;ec2b93b[929]<=gbd3cad[0];ec2b93b[922]<=necf64d[0];ec2b93b[837]<=vv6bf6a;ec2b93b[744]<=zz223d3;ec2b93b[742]<=suf0e7b;ec2b93b[663]<=zz98a5;ec2b93b[648]<=qi571b;ec2b93b[605]<=fne98a7[0];ec2b93b[594]<=dm7684c;ec2b93b[586]<=eca93b4[0];ec2b93b[552]<=wj60366;ec2b93b[547]<=db3d01e;ec2b93b[546]<=me72e3d[0];ec2b93b[543]<=wla443f;ec2b93b[504]<=kdfdc02[0];ec2b93b[466]<=suce475;ec2b93b[418]<=fa4d7ed;ec2b93b[372]<=xwe447a;ec2b93b[371]<=vife1cf;ec2b93b[331]<=qt75363;ec2b93b[324]<=irab02b;ec2b93b[297]<=qt4ed09;ec2b93b[273]<=nrc7a03;ec2b93b[252]<=ri3fb80;ec2b93b[233]<=ir39c8e[0];ec2b93b[185]<=ayd4afe[0];ec2b93b[162]<=kq53558;ec2b93b[136]<=hqb8f40;ec2b93b[126]<=co87f70;ec2b93b[116]<=ph27391;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module ww53ba7 ( qvb4f6d,\r
- baa7b6d,\r
- txmac_clk_en,\r
-\r
- lqf1bfb, \r
- mg8dfdb, \r
- tx_sndpausreq, \r
- tx_sndpaustim, \r
- co1f530, \r
- cmfa980, \r
- yk56400, \r
- xj6b139, \r
- ls30000, \r
- mg760, \r
- cz601a7, \r
- ksd3d,\r
- hqa7a71,\r
- uk34f4e,\r
- nre9c5e,\r
- wj4e2f6, \r
- jr69e9,\r
- kqeaf42,\r
- ea62978,\r
- ng2f056,\r
- tx_discfrm,\r
- tja5e0a,\r
- os6dafc,\r
- bnb5dae,\r
- mtaed77,\r
- jea8807,\r
- rg76bbd,\r
- zm201d4, \r
- mgea3, \r
- db8ea4e, \r
- zz91d49, \r
- ww723a9, \r
- ea49da1, \r
- qt4ed09, \r
- dm7684c, \r
- tx_statvec, \r
- tx_staten, \r
- tx_done, \r
- go46d29, \r
- ay4c52f, \r
- zz98a5 \r
- );\r
-parameter xw422d5 = 16;\r
-parameter qte845a = 8;\r
-parameter rt6bf01 = 4;\r
-parameter tj8b55b = 14;\r
-parameter vk25f5d = 31;\r
-input qvb4f6d;\r
-input baa7b6d;\r
-input txmac_clk_en;\r
-input lqf1bfb;\r
-input mg8dfdb;\r
-input tx_sndpausreq;\r
-input [xw422d5-1:0] tx_sndpaustim;\r
-input co1f530;\r
-input cmfa980;\r
-input [qte845a-1:0] yk56400;\r
-input xj6b139;\r
-input ls30000;\r
-input mg760;\r
-input cz601a7;\r
-input ksd3d;\r
-input hqa7a71;\r
-input uk34f4e;\r
-input nre9c5e;\r
-input wj4e2f6;\r
-input jr69e9;\r
-input kqeaf42;\r
-input ea62978;\r
-input ng2f056;\r
-input tx_discfrm;\r
-input tja5e0a;\r
-input [rt6bf01-1:0] os6dafc;\r
-input bnb5dae;\r
-input mtaed77;\r
-input jea8807;\r
-input rg76bbd;\r
-output zm201d4;\r
-output mgea3;\r
-output db8ea4e;\r
-output [xw422d5-1:0] zz91d49;\r
-output ww723a9;\r
-output ea49da1;\r
-output qt4ed09;\r
-output dm7684c;\r
-output [vk25f5d-1:0] tx_statvec;\r
-output tx_staten;\r
-output tx_done;\r
-output go46d29;\r
-output ay4c52f;\r
-output zz98a5;\r
-reg [vk25f5d-1:0] tx_statvec;\r
-reg db8ea4e;\r
-reg [xw422d5-1:0] zz91d49;\r
-reg ww723a9;\r
-reg os49028;\r
-reg [tj8b55b-1:0] hb40a02;\r
-reg ie5017;\r
-reg [qte845a-1:0] rt405c7;\r
-reg zm201d4;\r
-reg mgea3;\r
-reg rib8fa4 ;\r
-reg pfc7d23 ;\r
-reg tx_done ;\r
-reg go46d29;\r
-reg mta4783 ;\r
-reg oh23c1d;\r
-reg tx_staten ;\r
-reg kqf076a;\r
-reg ba83b50;\r
-reg kf1da82;\r
-reg zz98a5;\r
-reg yx6a0a5;\r
-reg hb5052c;\r
-reg qi82967;\r
-reg zm14b38;\r
-reg dba59c2;\r
-reg qv2ce16;\r
-reg su670b4;\r
-reg hd385a0;\r
-reg jpc2d06;\r
-reg dm7684c;\r
-reg ay4c52f;\r
-reg qt4ed09;\r
-wire ea49da1 = qt4ed09;\r
-wire rib79b4;\r
-wire ecbcda2 = &yk56400;\r
-wire mt3688f = qi82967 & zm14b38 & dba59c2 & qv2ce16 & su670b4 & hd385a0;\r
-wire lf2251b = ~(|hb40a02[13:6]);\r
-wire fp946f5 = zz98a5 | kqeaf42;\r
-wire [vk25f5d-1:0] kqf5e19 = {lf2251b, os6dafc[3:0], mtaed77, bnb5dae, jea8807, rg76bbd, hb40a02[13:0], kf1da82, yx6a0a5 | jpc2d06, zz98a5, rib79b4, fp946f5, mt3688f, ba83b50 | hb5052c, kqf076a};\r
-wire ng1c25 = cz601a7 | ksd3d | jr69e9;\r
-wire vk256ef = ng1c25 & (~(|hb40a02[13:4])) & ~hb40a02[3] & ~hb40a02[2] & ~hb40a02[1] & hb40a02[0];\r
-wire zkc5c3e = ng1c25 & (~(|hb40a02[13:4])) & ~hb40a02[3] & ~hb40a02[2] & hb40a02[1] & ~hb40a02[0];\r
-wire hoc5078 = ng1c25 & (~(|hb40a02[13:4])) & ~hb40a02[3] & ~hb40a02[2] & hb40a02[1] & hb40a02[0];\r
-wire jebd235 = ng1c25 & (~(|hb40a02[13:4])) & ~hb40a02[3] & hb40a02[2] & ~hb40a02[1] & ~hb40a02[0];\r
-wire uxbb0ba = ng1c25 & (~(|hb40a02[13:4])) & ~hb40a02[3] & hb40a02[2] & ~hb40a02[1] & hb40a02[0];\r
-wire jp7e997 = ng1c25 & (~(|hb40a02[13:4])) & ~hb40a02[3] & hb40a02[2] & hb40a02[1] & ~hb40a02[0];\r
-wire ks98c6f = ng1c25 & (~(|hb40a02[13:4])) & hb40a02[3] & hb40a02[2] & hb40a02[1] & ~hb40a02[0];\r
-wire cb2930a = ~kf1da82 & ((|hb40a02[13:11]) | (&hb40a02[10:9]) | (hb40a02[10] & hb40a02[8] & (&hb40a02[7:5]) & (hb40a02[4] | (&hb40a02[3:0]))));\r
-wire db38e5b = (|hb40a02[13:11]) | (&hb40a02[10:9]) | (hb40a02[10] & hb40a02[8] & (&hb40a02[7:4]) & ((|hb40a02[3:2]) | (&hb40a02[1:0])));\r
-reg cze80f6;\r
-reg rt407b5;\r
-reg xj6b194;\r
-reg [xw422d5 - 1 : 0] qtc6532;\r
-reg fp32995;\r
-reg ph94cae;\r
-reg [qte845a - 1 : 0] db32bb0;\r
-reg vieb1e2;\r
-reg uxaec34;\r
-reg dm761a5;\r
-reg dbb0d2b;\r
-reg ba8695f;\r
-reg ie34afa;\r
-reg rva57d1;\r
-reg aa2be8f;\r
-reg bl5f479;\r
-reg uifa3ce;\r
-reg kqd1e71;\r
-reg mt8f388;\r
-reg by79c45;\r
-reg osce22b;\r
-reg th71159;\r
-reg [rt6bf01 - 1 : 0] hdbac11;\r
-reg qi2b38e;\r
-reg su59c70;\r
-reg ayce380;\r
-reg ld71c01;\r
-reg ph8e00f;\r
-reg [tj8b55b - 1 : 0] an803fc;\r
-reg ba1fe4;\r
-reg [qte845a - 1 : 0] yx7f918;\r
-reg pffc8c4;\r
-reg xwe4627;\r
-reg yz2313b;\r
-reg cb189dc;\r
-reg cmc4ee4;\r
-reg xl27721;\r
-reg sw3b90e;\r
-reg shdc870;\r
-reg bye4384;\r
-reg co21c23;\r
-reg hqe118;\r
-reg of708c3;\r
-reg nt8461d;\r
-reg cb230ee;\r
-reg ir18774;\r
-reg enc3ba5;\r
-reg ir1dd2c;\r
-reg zkee964;\r
-reg th74b23;\r
-reg bna591f;\r
-reg an2c8fe;\r
-reg [vk25f5d - 1 : 0] yz23fa7;\r
-reg ec1fd3d;\r
-reg xwfe9e9;\r
-reg faf4f4a;\r
-reg ria7a53;\r
-reg db3d29b;\r
-reg dze94de;\r
-reg zx4a6f7;\r
-reg ay537bf;\r
-reg lf9bdf8;\r
-reg aydefc7;\r
-reg [2047:0] ec2b93b;\r
-wire [62:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 63,ph27642 = 32'hfdffe44b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
- \r
- always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin rib8fa4 <= 1'b0; pfc7d23 <= 1'b0; tx_done <= 1'b0; go46d29 <= 1'b0; mta4783 <= 1'b0; oh23c1d <= 1'b0; tx_staten <= 1'b0; end else if (txmac_clk_en) begin tx_done <= xwe4627; pfc7d23 <= pffc8c4; rib8fa4 <= by79c45; go46d29 <= osce22b; tx_staten <= cb189dc; oh23c1d <= yz2313b; mta4783 <= th71159; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin ww723a9 <= 1'b0; end else if (txmac_clk_en) begin if(ph94cae) begin ww723a9 <= 1'b0; end else if(ph8e00f) begin ww723a9 <= ph8e00f; end end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin hb40a02 <= 14'd0; dm7684c <= 0; ay4c52f <= 0; qt4ed09 <= 1; end else if (txmac_clk_en) begin if (an803fc[13:0] == 14'd58) begin dm7684c <= 1; end else begin dm7684c <= 0; end if (an803fc[13:0] == 14'd63) begin ay4c52f <= 1; end else begin ay4c52f <= 0; end if (dm7684c == 1) begin qt4ed09 <= 0; end if(ie34afa) begin hb40a02 <= an803fc + 14'd4; end else if(dbb0d2b || bl5f479 || rva57d1 || uifa3ce || ba8695f) begin hb40a02 <= an803fc + 14'd1; end else if(dm761a5 || aa2be8f) begin hb40a02 <= 14'd0; qt4ed09 <= 1; end end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin kqf076a <= 1'b0; ba83b50 <= 1'b0; end else if (txmac_clk_en) begin if (xwfe9e9) begin if(db32bb0[0]) begin kqf076a <= 1'b0; ba83b50 <= 1'b1; end else begin kqf076a <= 1'b1; ba83b50 <= 1'b0; end end else if(dm761a5) begin kqf076a <= 1'b0; ba83b50 <= 1'b0; end end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) qi82967 <= 1'b0; else if (txmac_clk_en) begin if (xwfe9e9) begin if(zkee964) qi82967 <= 1'b1; else qi82967 <= 1'b0; end else if(dm761a5) qi82967 <= 1'b0; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) zm14b38 <= 1'b0; else if (txmac_clk_en) begin if (faf4f4a) begin if(zkee964) zm14b38 <= 1'b1; else zm14b38 <= 1'b0; end else if(dm761a5) zm14b38 <= 1'b0; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) dba59c2 <= 1'b0; else if (txmac_clk_en) begin if (ria7a53) begin if(zkee964) dba59c2 <= 1'b1; else dba59c2 <= 1'b0; end else if(dm761a5) dba59c2 <= 1'b0; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) qv2ce16 <= 1'b0; else if (txmac_clk_en) begin if (db3d29b) begin if(zkee964) qv2ce16 <= 1'b1; else qv2ce16 <= 1'b0; end else if(dm761a5) qv2ce16 <= 1'b0; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) su670b4 <= 1'b0; else if (txmac_clk_en) begin if (dze94de) begin if(zkee964) su670b4 <= 1'b1; else su670b4 <= 1'b0; end else if(dm761a5) su670b4 <= 1'b0; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) hd385a0 <= 1'b0; else if (txmac_clk_en) begin if (zx4a6f7) begin if(zkee964) hd385a0 <= 1'b1; else hd385a0 <= 1'b0; end else if(dm761a5) hd385a0 <= 1'b0; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin kf1da82 <= 1'b0; jpc2d06 <= 1'b0; end else if (txmac_clk_en) begin if(ay537bf) begin if ((yx7f918 == 8'h81) && (db32bb0 == 8'h00)) begin kf1da82 <= 1'b1; jpc2d06 <= 1'b0; end else if ((yx7f918 == 8'h88) && (db32bb0 == 8'h08)) begin kf1da82 <= 1'b0; jpc2d06 <= 1'b1; end else begin kf1da82 <= 1'b0; jpc2d06 <= 1'b0; end end else if(dm761a5) begin kf1da82 <= 1'b0; jpc2d06 <= 1'b0; end end end \r
- assign rib79b4 = lf9bdf8 | aydefc7;\r
- always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) zz98a5 <= 1'b0; else if (txmac_clk_en) begin if(dbb0d2b && uxaec34 && !(ba1fe4 || vieb1e2)) begin zz98a5 <= 1'b1; end else if(dm761a5) zz98a5 <= 1'b0; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) yx6a0a5 <= 1'b0; else if (txmac_clk_en) begin if(uifa3ce) yx6a0a5 <= 1'b1; else if(dm761a5) yx6a0a5 <= 1'b0 ; end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) hb5052c <= 1'b0; else if (txmac_clk_en) begin if (rva57d1 || ie34afa) begin hb5052c <= shdc870; end end end \r
- always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin zm201d4 <= 1'b0; mgea3 <= 1'b0; os49028 <= 1'b0; tx_statvec <= 31'd0; end else if (txmac_clk_en) begin zm201d4 <= cze80f6; mgea3 <= rt407b5; os49028 <= fp32995; if (th71159 == 1) begin tx_statvec <= yz23fa7; end end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin ie5017 <= 0; rt405c7 <= 0; end else if (txmac_clk_en) begin rt405c7 <= db32bb0; if(mt8f388) begin ie5017 <= vieb1e2; end end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin db8ea4e <= 1'b0; zz91d49 <= 16'h0000; end else if (txmac_clk_en) begin if(uifa3ce) db8ea4e <= 1'b0; else if(xj6b194) begin db8ea4e <= xj6b194; zz91d49 <= qtc6532; end end end\r
-always@* begin cze80f6<=ea5c9d9[0];rt407b5<=ea5c9d9[1];xj6b194<=ea5c9d9[2];qtc6532<={tx_sndpaustim>>1,ea5c9d9[3]};fp32995<=ea5c9d9[4];ph94cae<=ea5c9d9[5];db32bb0<={yk56400>>1,ea5c9d9[6]};vieb1e2<=ea5c9d9[7];uxaec34<=ea5c9d9[8];dm761a5<=ea5c9d9[9];dbb0d2b<=ea5c9d9[10];ba8695f<=ea5c9d9[11];ie34afa<=ea5c9d9[12];rva57d1<=ea5c9d9[13];aa2be8f<=ea5c9d9[14];bl5f479<=ea5c9d9[15];uifa3ce<=ea5c9d9[16];kqd1e71<=ea5c9d9[17];mt8f388<=ea5c9d9[18];by79c45<=ea5c9d9[19];osce22b<=ea5c9d9[20];th71159<=ea5c9d9[21];hdbac11<={os6dafc>>1,ea5c9d9[22]};qi2b38e<=ea5c9d9[23];su59c70<=ea5c9d9[24];ayce380<=ea5c9d9[25];ld71c01<=ea5c9d9[26];ph8e00f<=ea5c9d9[27];an803fc<={hb40a02>>1,ea5c9d9[28]};ba1fe4<=ea5c9d9[29];yx7f918<={rt405c7>>1,ea5c9d9[30]};pffc8c4<=ea5c9d9[31];xwe4627<=ea5c9d9[32];yz2313b<=ea5c9d9[33];cb189dc<=ea5c9d9[34];cmc4ee4<=ea5c9d9[35];xl27721<=ea5c9d9[36];sw3b90e<=ea5c9d9[37];shdc870<=ea5c9d9[38];bye4384<=ea5c9d9[39];co21c23<=ea5c9d9[40];hqe118<=ea5c9d9[41];of708c3<=ea5c9d9[42];nt8461d<=ea5c9d9[43];cb230ee<=ea5c9d9[44];ir18774<=ea5c9d9[45];enc3ba5<=ea5c9d9[46];ir1dd2c<=ea5c9d9[47];zkee964<=ea5c9d9[48];th74b23<=ea5c9d9[49];bna591f<=ea5c9d9[50];an2c8fe<=ea5c9d9[51];yz23fa7<={kqf5e19>>1,ea5c9d9[52]};ec1fd3d<=ea5c9d9[53];xwfe9e9<=ea5c9d9[54];faf4f4a<=ea5c9d9[55];ria7a53<=ea5c9d9[56];db3d29b<=ea5c9d9[57];dze94de<=ea5c9d9[58];zx4a6f7<=ea5c9d9[59];ay537bf<=ea5c9d9[60];lf9bdf8<=ea5c9d9[61];aydefc7<=ea5c9d9[62];end\r
-always@* begin ec2b93b[2047]<=mg8dfdb;ec2b93b[2046]<=tx_sndpausreq;ec2b93b[2044]<=tx_sndpaustim[0];ec2b93b[2040]<=co1f530;ec2b93b[2033]<=cmfa980;ec2b93b[2019]<=yk56400[0];ec2b93b[1991]<=xj6b139;ec2b93b[1934]<=ls30000;ec2b93b[1929]<=rib79b4;ec2b93b[1898]<=wj4e2f6;ec2b93b[1821]<=mg760;ec2b93b[1810]<=ecbcda2;ec2b93b[1749]<=jr69e9;ec2b93b[1707]<=ng2f056;ec2b93b[1666]<=hb40a02[0];ec2b93b[1630]<=zm14b38;ec2b93b[1595]<=cz601a7;ec2b93b[1572]<=mt3688f;ec2b93b[1506]<=hd385a0;ec2b93b[1450]<=kqeaf42;ec2b93b[1440]<=rg76bbd;ec2b93b[1384]<=mtaed77;ec2b93b[1370]<=os6dafc[0];ec2b93b[1366]<=tx_discfrm;ec2b93b[1284]<=ie5017;ec2b93b[1212]<=dba59c2;ec2b93b[1202]<=ks98c6f;ec2b93b[1174]<=jebd235;ec2b93b[1170]<=vk256ef;ec2b93b[1142]<=ksd3d;ec2b93b[1125]<=kf1da82;ec2b93b[1097]<=lf2251b;ec2b93b[1041]<=rib8fa4;ec2b93b[1023]<=lqf1bfb;ec2b93b[964]<=jpc2d06;ec2b93b[949]<=nre9c5e;ec2b93b[853]<=ea62978;ec2b93b[833]<=os49028;ec2b93b[815]<=qi82967;ec2b93b[753]<=su670b4;ec2b93b[720]<=jea8807;ec2b93b[714]<=db38e5b;ec2b93b[692]<=bnb5dae;ec2b93b[685]<=tja5e0a;ec2b93b[601]<=jp7e997;ec2b93b[587]<=hoc5078;ec2b93b[585]<=ng1c25;ec2b93b[562]<=ba83b50;ec2b93b[520]<=rt405c7[0];ec2b93b[474]<=uk34f4e;ec2b93b[407]<=hb5052c;ec2b93b[376]<=qv2ce16;ec2b93b[357]<=cb2930a;ec2b93b[300]<=uxbb0ba;ec2b93b[293]<=zkc5c3e;ec2b93b[292]<=kqf5e19[0];ec2b93b[281]<=kqf076a;ec2b93b[237]<=hqa7a71;ec2b93b[203]<=yx6a0a5;ec2b93b[146]<=fp946f5;ec2b93b[140]<=oh23c1d;ec2b93b[70]<=mta4783;ec2b93b[35]<=pfc7d23;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module uk13d ( qvb4f6d,\r
- baa7b6d,\r
- txmac_clk_en,\r
- db3d05f, \r
- cze82fe, \r
- qt417f5, \r
- cmfa980 \r
- );\r
-parameter xw422d5 = 16;\r
-input qvb4f6d;\r
-input baa7b6d;\r
-input txmac_clk_en;\r
-input db3d05f;\r
-input cze82fe;\r
-input [xw422d5-1:0] qt417f5;\r
-output cmfa980;\r
-reg [xw422d5-1:0] su4ce51;\r
-reg [5:0] ww67289;\r
-reg fne98a7;\r
-reg ic4c53e;\r
-reg cmfa980;\r
-reg hq8911d;\r
-parameter tw14f81 = 1'b0;\r
-parameter fca7c0a = 1'b1;\r
-reg ir23a9c;\r
-reg ir1d4e5;\r
-reg [xw422d5 - 1 : 0] kq53968;\r
-reg [xw422d5 - 1 : 0] cme5a0a;\r
-reg [5 : 0] jr2d050;\r
-reg ep36c0e;\r
-reg ecb6074;\r
-reg iea1cc;\r
-reg [2047:0] ec2b93b;\r
-wire [7:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 8,ph27642 = 32'hfdffd14b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
- always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin fne98a7 <= tw14f81; end else if (txmac_clk_en) begin fne98a7 <= ecb6074; end end always @ (ep36c0e or ir23a9c or cmfa980) begin case(ep36c0e) tw14f81: begin if(ir23a9c) begin ic4c53e = fca7c0a; end else begin ic4c53e = tw14f81; end end fca7c0a: begin if(cmfa980) begin ic4c53e = tw14f81; end else begin ic4c53e = fca7c0a; end end endcase end always @ (posedge qvb4f6d or negedge baa7b6d) begin if (!baa7b6d) begin su4ce51 <= 0; cmfa980 <= 0; end else if (txmac_clk_en) begin if (ir1d4e5 == 1) begin su4ce51 <= kq53968; end else if(ep36c0e == fca7c0a) begin if (iea1cc == 1) begin su4ce51 <= cme5a0a - 1; end end else begin su4ce51 <= kq53968; end if (cme5a0a == 0) begin cmfa980 <= 1; end else begin cmfa980 <= 0; end end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if (!baa7b6d) begin ww67289 <= 0; hq8911d <= 0; end else if (txmac_clk_en) begin if (ir23a9c && !ir1d4e5) begin ww67289 <= jr2d050 + 1; end else begin ww67289 <= 0; end if ((jr2d050 == 6'h3e) && (!ir1d4e5)) begin hq8911d <= 1; end else begin hq8911d <= 0; end end end\r
-always@* begin ir23a9c<=ea5c9d9[0];ir1d4e5<=ea5c9d9[1];kq53968<={qt417f5>>1,ea5c9d9[2]};cme5a0a<={su4ce51>>1,ea5c9d9[3]};jr2d050<={ww67289>>1,ea5c9d9[4]};ep36c0e<=ea5c9d9[5];ecb6074<=ea5c9d9[6];iea1cc<=ea5c9d9[7];end\r
-always@* begin ec2b93b[2047]<=cze82fe;ec2b93b[2046]<=qt417f5[0];ec2b93b[2044]<=su4ce51[0];ec2b93b[2040]<=ww67289[0];ec2b93b[2033]<=fne98a7;ec2b93b[2019]<=ic4c53e;ec2b93b[1990]<=hq8911d;ec2b93b[1023]<=db3d05f;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module yz8a39d (txmac_clk,\r
- baa7b6d,\r
- txmac_clk_en,\r
- tx_discfrm,\r
- tx_fifodata, \r
- tx_fifoeof, \r
- tx_fifoempty, \r
- tx_fifoctrl, \r
- tx_macread, \r
- go6d627, \r
- xj6b139, \r
- ls30000, \r
- suce475, \r
- xw589ce, \r
- ea62978 \r
- );\r
-parameter qte845a = 8;\r
-input txmac_clk;\r
-input baa7b6d;\r
-input txmac_clk_en;\r
-input tx_discfrm;\r
-input [qte845a-1:0] tx_fifodata;\r
-input tx_fifoeof;\r
-input tx_fifoempty;\r
-input tx_fifoctrl;\r
-output tx_macread;\r
-output [qte845a-1:0] go6d627;\r
-output xj6b139;\r
-output ls30000;\r
-output suce475;\r
-output xw589ce;\r
-input ea62978;\r
-reg [qte845a+2:0] ho57372;\r
-reg [qte845a+2:0] blcdc91;\r
-reg [qte845a+2:0] qg7247e;\r
-reg [qte845a+2:0] lf91f88;\r
-reg [qte845a+2:0] ld7e234;\r
-reg [qte845a+2:0] ec88d3a;\r
-reg [qte845a+2:0] ie34e88;\r
-reg [qte845a+2:0] hq3a20a;\r
-reg [qte845a+2:0] ou88299;\r
-reg [qte845a+2:0] iea644;\r
-reg [qte845a+2:0] ng99108;\r
-reg [qte845a+2:0] gb4421f;\r
-reg [qte845a+2:0] qv87e1;\r
-reg [qte845a+2:0] qi1f860;\r
-reg [qte845a+2:0] jce180e;\r
-reg ntc072;\r
-reg gb60396;\r
-wire [qte845a-1:0] go6d627;\r
-wire tx_macread;\r
-wire xj6b139;\r
-wire ls30000;\r
-wire suce475;\r
-wire xw589ce;\r
-reg osce22b;\r
-reg [qte845a - 1 : 0] je1e93c;\r
-reg lqf49e3;\r
-reg oha4f1b;\r
-reg bn278dc;\r
-reg mt8f388;\r
-reg [qte845a + 2 : 0] ba1b9e6;\r
-reg [qte845a + 2 : 0] ofe799c;\r
-reg [qte845a + 2 : 0] pfe672d;\r
-reg [qte845a + 2 : 0] ls9cb74;\r
-reg [qte845a + 2 : 0] nt2dd10;\r
-reg [qte845a + 2 : 0] dz74437;\r
-reg [qte845a + 2 : 0] sw10df2;\r
-reg [qte845a + 2 : 0] fp37c82;\r
-reg [qte845a + 2 : 0] qtf20b5;\r
-reg [qte845a + 2 : 0] co82d6d;\r
-reg [qte845a + 2 : 0] lfb5b47;\r
-reg [qte845a + 2 : 0] ui6d1fa;\r
-reg [qte845a + 2 : 0] lq47e88;\r
-reg [qte845a + 2 : 0] qgfa213;\r
-reg [qte845a + 2 : 0] sw884c9;\r
-reg tu42648;\r
-reg db13243;\r
-reg [2047:0] ec2b93b;\r
-wire [22:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 23,ph27642 = 32'hfdffd48b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-assign tx_macread = tu42648 & ~oha4f1b;\r
-assign go6d627 = ba1b9e6[qte845a-1:0];\r
-assign xj6b139 = ba1b9e6[qte845a];\r
-assign ls30000 = ~(ofe799c[qte845a+2] | sw884c9[qte845a+2]);\r
-assign suce475 = ba1b9e6[qte845a+1];\r
-assign xw589ce = ba1b9e6[qte845a+2];\r
-always @ (ba1b9e6 or ofe799c or pfe672d or ls9cb74 or nt2dd10 or dz74437 or sw10df2 or sw884c9 or mt8f388) begin casex ({sw10df2[qte845a+2],dz74437[qte845a+2], nt2dd10[qte845a+2],ls9cb74[qte845a+2], pfe672d[qte845a+2],ofe799c[qte845a+2], ba1b9e6[qte845a+2],mt8f388}) 8'bxxxxxx0x, 8'bxxxxx011: begin hq3a20a = sw884c9; ou88299 = pfe672d; iea644 = ls9cb74; ng99108 = nt2dd10; gb4421f = dz74437; qv87e1 = sw10df2; qi1f860 = 11'h000; end 8'bxxxxx010, 8'bxxxx0111: begin hq3a20a = ofe799c; ou88299 = sw884c9; iea644 = ls9cb74; ng99108 = nt2dd10; gb4421f = dz74437; qv87e1 = sw10df2; qi1f860 = 11'h000; end 8'bxxxx0110, 8'bxxx01111: begin hq3a20a = ofe799c; ou88299 = pfe672d; iea644 = sw884c9; ng99108 = nt2dd10; gb4421f = dz74437; qv87e1 = sw10df2; qi1f860 = 11'h000; end 8'bxxx01110, 8'bxx011111: begin hq3a20a = ofe799c; ou88299 = pfe672d; iea644 = ls9cb74; ng99108 = sw884c9; gb4421f = dz74437; qv87e1 = sw10df2; qi1f860 = 11'h000; end 8'bxx011110, 8'bx0111111: begin hq3a20a = ofe799c; ou88299 = pfe672d; iea644 = ls9cb74; ng99108 = nt2dd10; gb4421f = sw884c9; qv87e1 = sw10df2; qi1f860 = 11'h000; end 8'bx0111110, 8'b01111111: begin hq3a20a = ofe799c; ou88299 = pfe672d; iea644 = ls9cb74; ng99108 = nt2dd10; gb4421f = dz74437; qv87e1 = sw884c9; qi1f860 = 11'h000; end 8'bx1111110, 8'b11111111: begin hq3a20a = ofe799c; ou88299 = pfe672d; iea644 = ls9cb74; ng99108 = nt2dd10; gb4421f = dz74437; qv87e1 = sw10df2; qi1f860 = sw884c9; end endcase\r
-end always @ (posedge txmac_clk or negedge baa7b6d) begin if(!baa7b6d) begin ho57372 <= 11'h000; blcdc91 <= 11'h000; qg7247e <= 11'h000; lf91f88 <= 11'h000; ld7e234 <= 11'h000; ec88d3a <= 11'h000; ie34e88 <= 11'h000; jce180e <= 11'h000; ntc072 <= 0; gb60396 <= 0; end else if (txmac_clk_en) begin jce180e <= {db13243, bn278dc, lqf49e3, je1e93c}; if ((ba1b9e6[qte845a+2] == 0) || (mt8f388 == 1)) begin ho57372 <= fp37c82; end if ((ofe799c[qte845a+2] == 0) || (mt8f388 == 1)) begin blcdc91 <= qtf20b5; end if ((pfe672d[qte845a+2] == 0) || (mt8f388 == 1)) begin qg7247e <= co82d6d; end if ((ls9cb74[qte845a+2] == 0) || (mt8f388 == 1)) begin lf91f88 <= lfb5b47; end if ((nt2dd10[qte845a+2] == 0) || (mt8f388 == 1)) begin ld7e234 <= ui6d1fa; end if ((dz74437[qte845a+2] == 0) || (mt8f388 == 1)) begin ec88d3a <= lq47e88; end if ((sw10df2[qte845a+2] == 0) || (mt8f388 == 1)) begin ie34e88 <= qgfa213; end case (tu42648) 1: begin if ((ls9cb74[qte845a+2] == 1) || (nt2dd10[qte845a+2] == 1) || (dz74437[qte845a+2] == 1) || (sw10df2[qte845a+2] == 1)) begin ntc072 <= 0; end end 0: begin if ((nt2dd10[qte845a+2] == 0) && (dz74437[qte845a+2] == 0) && (sw10df2[qte845a+2] == 0)) begin ntc072 <= 1; end end endcase gb60396 <= tx_macread; if (osce22b == 1) begin jce180e[qte845a+2] <= 0; ie34e88[qte845a+2] <= 0; ec88d3a[qte845a+2] <= 0; ld7e234[qte845a+2] <= 0; lf91f88[qte845a+2] <= 0; qg7247e[qte845a+2] <= 0; blcdc91[qte845a+2] <= 0; ho57372[qte845a+2] <= 0; gb60396 <= 0; ntc072 <= 0; end end end\r
-always@* begin osce22b<=ea5c9d9[0];je1e93c<={tx_fifodata>>1,ea5c9d9[1]};lqf49e3<=ea5c9d9[2];oha4f1b<=ea5c9d9[3];bn278dc<=ea5c9d9[4];mt8f388<=ea5c9d9[5];ba1b9e6<={ho57372>>1,ea5c9d9[6]};ofe799c<={blcdc91>>1,ea5c9d9[7]};pfe672d<={qg7247e>>1,ea5c9d9[8]};ls9cb74<={lf91f88>>1,ea5c9d9[9]};nt2dd10<={ld7e234>>1,ea5c9d9[10]};dz74437<={ec88d3a>>1,ea5c9d9[11]};sw10df2<={ie34e88>>1,ea5c9d9[12]};fp37c82<={hq3a20a>>1,ea5c9d9[13]};qtf20b5<={ou88299>>1,ea5c9d9[14]};co82d6d<={iea644>>1,ea5c9d9[15]};lfb5b47<={ng99108>>1,ea5c9d9[16]};ui6d1fa<={gb4421f>>1,ea5c9d9[17]};lq47e88<={qv87e1>>1,ea5c9d9[18]};qgfa213<={qi1f860>>1,ea5c9d9[19]};sw884c9<={jce180e>>1,ea5c9d9[20]};tu42648<=ea5c9d9[21];db13243<=ea5c9d9[22];end\r
-always@* begin ec2b93b[2047]<=tx_fifodata[0];ec2b93b[2046]<=tx_fifoeof;ec2b93b[2044]<=tx_fifoempty;ec2b93b[2040]<=tx_fifoctrl;ec2b93b[2032]<=ea62978;ec2b93b[2017]<=ho57372[0];ec2b93b[1987]<=blcdc91[0];ec2b93b[1927]<=qg7247e[0];ec2b93b[1865]<=ng99108[0];ec2b93b[1806]<=lf91f88[0];ec2b93b[1682]<=gb4421f[0];ec2b93b[1565]<=ld7e234[0];ec2b93b[1317]<=qv87e1[0];ec2b93b[1172]<=jce180e[0];ec2b93b[1082]<=ec88d3a[0];ec2b93b[1023]<=tx_discfrm;ec2b93b[932]<=iea644[0];ec2b93b[594]<=gb60396;ec2b93b[586]<=qi1f860[0];ec2b93b[466]<=ou88299[0];ec2b93b[297]<=ntc072;ec2b93b[233]<=hq3a20a[0];ec2b93b[116]<=ie34e88[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module uxbbc00 ( qvb4f6d,\r
- baa7b6d,\r
- txmac_clk_en,\r
-\r
- sw804, \r
- tw4021, \r
- xy2010a, \r
- wy853, \r
-\r
- zm4299, \r
- sw214ca, \r
- iea651 \r
- );\r
-parameter ui53289 = 6;\r
-input qvb4f6d;\r
-input baa7b6d;\r
-input txmac_clk_en;\r
-input sw804;\r
-input tw4021;\r
-input xy2010a;\r
-input wy853;\r
-output [ui53289-1:0] zm4299;\r
-output [ui53289-1:0] sw214ca;\r
-output iea651;\r
-reg [ui53289-1:0] zm4299;\r
-reg [ui53289-1:0] sw214ca;\r
-wire iea651 = (zm4299 == sw214ca);\r
-reg gqa6b35;\r
-reg ri359a9;\r
-reg ieacd4b;\r
-reg ho66a58;\r
-reg [2047:0] ec2b93b;\r
-wire [3:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 4,ph27642 = 32'hfdffd30b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
- always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin zm4299 <= 5'd0; end else if (txmac_clk_en) begin if(gqa6b35 || ri359a9) begin zm4299 <= 5'd0; end else if(ieacd4b) begin zm4299 <= zm4299 + 5'd1; end end end always @ (posedge qvb4f6d or negedge baa7b6d) begin if(!baa7b6d) begin sw214ca <= 5'd0; end else if (txmac_clk_en) begin if(gqa6b35) begin sw214ca <= 5'd0; end else if(ho66a58) begin sw214ca <= sw214ca + 5'd1; end end end\r
-always@* begin gqa6b35<=ea5c9d9[0];ri359a9<=ea5c9d9[1];ieacd4b<=ea5c9d9[2];ho66a58<=ea5c9d9[3];end\r
-always@* begin ec2b93b[2047]<=tw4021;ec2b93b[2046]<=xy2010a;ec2b93b[2044]<=wy853;ec2b93b[1023]<=sw804;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module icfab90 ( txmac_clk,\r
- baa7b6d,\r
- txmac_clk_en,\r
-\r
- \r
- lqf1bfb, \r
- mg8dfdb, \r
- qt7f6cd, \r
- cz6fed9, \r
- uxa1b23, \r
- wld91c, \r
- dzcdac4, \r
-\r
- \r
- tx_fifodata, \r
- tx_fifoeof, \r
- tx_fifoempty, \r
- tx_fifoavail, \r
- tx_sndpaustim, \r
- tx_sndpausreq, \r
- tx_fifoctrl, \r
-\r
- \r
- psee2db, \r
- nr716da, \r
-\r
- \r
- uidb36b, \r
- fafb66d, \r
-\r
- \r
- aydb5bc, \r
- \r
- \r
- tx_macread, \r
- tx_discfrm, \r
- tx_staten, \r
- tx_statvec, \r
- tx_done, \r
-\r
- \r
- ui782b2, \r
- goc1590, \r
- wyac80 \r
- );\r
-parameter pdevice_family = "XP2";\r
-parameter ps4d8e0 = 5;\r
-parameter by57a11 = 48;\r
-parameter vkbd08b = 16;\r
-parameter qte845a = 8;\r
-parameter xw422d5 = 16;\r
-parameter vk25f5d = 31;\r
-parameter hq116ab = 32;\r
-parameter tj8b55b = 14;\r
-parameter rt6bf01 = 4;\r
-parameter ui53289 = 6;\r
-parameter vid56ff = 22;\r
-parameter anab7fb = 13;\r
-parameter wj5bfdc = 13'd6072;\r
-parameter lqdfee5 = 8'h55;\r
-parameter ayff72b = 8'hd5;\r
-parameter hofb959 = 8'h00;\r
-parameter ipdcaca = 8'h01;\r
-parameter yke5654 = 8'h80;\r
-parameter ec2b2a1 = 8'hc2;\r
-parameter ay59508 = 8'h00;\r
-parameter rgca841 = 8'h00;\r
-parameter mr5420a = 8'h01;\r
-parameter gda1055 = 8'h88;\r
-parameter sj82ad = 8'h08;\r
-parameter uv4156c = 8'h00;\r
-input txmac_clk;\r
-input baa7b6d;\r
-input txmac_clk_en;\r
-input lqf1bfb;\r
-input mg8dfdb;\r
-input qt7f6cd;\r
-input cz6fed9;\r
-input [ps4d8e0-1:0] uxa1b23;\r
-input [by57a11-1:0] wld91c;\r
-input [vkbd08b-1:0] dzcdac4;\r
-input [qte845a-1:0] tx_fifodata;\r
-input tx_fifoeof;\r
-input tx_fifoempty;\r
-input tx_fifoavail;\r
-input [xw422d5-1:0] tx_sndpaustim;\r
-input tx_sndpausreq;\r
-input tx_fifoctrl;\r
-input psee2db;\r
-input [xw422d5-1:0] nr716da;\r
-input uidb36b;\r
-input fafb66d;\r
-output aydb5bc;\r
-output tx_macread;\r
-output tx_discfrm;\r
-output tx_staten;\r
-output [vk25f5d-1:0] tx_statvec;\r
-output tx_done;\r
-output ui782b2;\r
-output [qte845a-1:0] goc1590;\r
-output wyac80;\r
-wire [qte845a-1:0] go6d627;\r
-wire [xw422d5-1:0] zz91d49;\r
-wire [hq116ab-1:0] eca93b4;\r
-wire ea49da1;\r
-wire [qte845a-1:0] yk56400;\r
-wire [qte845a-1:0] goc1590;\r
-wire [qte845a:0] ir39c8e;\r
-wire [rt6bf01-1:0] os6dafc;\r
-wire mg760;\r
-wire vx3b00;\r
-wire [ui53289-1:0] aye0014;\r
-wire [ui53289-1:0] ec508;\r
-wire aydb5bc = mg760 | vx3b00;\r
-reg ep811d;\r
-reg cze80f6;\r
-reg rt407b5;\r
-reg vk1ed76;\r
-reg jr3dae;\r
-reg [ps4d8e0 - 1 : 0] qg67566;\r
-reg [by57a11 - 1 : 0] tud5982;\r
-reg [vkbd08b - 1 : 0] bn9ef58;\r
-reg [qte845a - 1 : 0] je1e93c;\r
-reg lqf49e3;\r
-reg oha4f1b;\r
-reg thc7892;\r
-reg [xw422d5 - 1 : 0] qtc6532;\r
-reg xj6b194;\r
-reg bn278dc;\r
-reg an2999d;\r
-reg [xw422d5 - 1 : 0] ne66761;\r
-reg phb5d9e;\r
-reg fnf6bb3;\r
-reg [qte845a - 1 : 0] zmbd63c;\r
-reg [xw422d5 - 1 : 0] ana485d;\r
-reg [hq116ab - 1 : 0] zk5d84a;\r
-reg hbec252;\r
-reg [qte845a - 1 : 0] db32bb0;\r
-reg [qte845a : 0] an125a4;\r
-reg [rt6bf01 - 1 : 0] hdbac11;\r
-reg dm761a5;\r
-reg ui59c6a;\r
-reg [ui53289 - 1 : 0] jp71a81;\r
-reg [ui53289 - 1 : 0] al6a078;\r
-reg [2047:0] ec2b93b;\r
-wire [29:0] ea5c9d9;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam tue4ec8 = 30,ph27642 = 32'hfdffca8b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-yz8a39d #( .qte845a(qte845a) ) med4baa ( .txmac_clk (txmac_clk), .baa7b6d (ep811d), .txmac_clk_en (txmac_clk_en), .tx_discfrm (go46d29), .tx_fifodata (je1e93c), .tx_fifoeof (lqf49e3), .tx_fifoempty (oha4f1b), .tx_fifoctrl (bn278dc), .tx_macread (tx_macread), .go6d627 (go6d627), .xj6b139 (xj6b139), .ls30000 (ls30000), .suce475 (suce475), .xw589ce (xw589ce), .ea62978 (ea62978) );\r
-uved7f1 #( .by57a11( by57a11), .vkbd08b(vkbd08b), .qte845a(qte845a), .xw422d5(xw422d5), .hq116ab(hq116ab), .tj8b55b(tj8b55b), .rt6bf01(rt6bf01), .vid56ff(vid56ff), .anab7fb(anab7fb), .wj5bfdc(wj5bfdc), .lqdfee5(lqdfee5), .ayff72b(ayff72b), .hofb959(hofb959), .ipdcaca(ipdcaca), .yke5654(yke5654), .ec2b2a1(ec2b2a1), .ay59508(ay59508), .rgca841(rgca841), .mr5420a(mr5420a), .gda1055(gda1055), .sj82ad(sj82ad), .uv4156c(uv4156c) ) co1aaff ( .txmac_clk (txmac_clk), .baa7b6d (ep811d), .txmac_clk_en (txmac_clk_en), .lqf1bfb (zm201d4), .mg8dfdb (mgea3), .cz6fed9 (jr3dae), .qt7f6cd (vk1ed76), .fafb66d (fnf6bb3), .uidb36b (phb5d9e), .shd9b58 (tud5982), .dzcdac4 (bn9ef58), .go6d627 (zmbd63c), .xj6b139 (xj6b139), .xw589ce (xw589ce), .tx_fifoavail (thc7892), .ph27391 (ph27391), .ir39c8e (an125a4), .suce475 (suce475), .ww723a9 (ww723a9), .zz91d49 (ana485d), .db8ea4e (db8ea4e), .wya9b1c (wya9b1c), .eca93b4 (zk5d84a), .ea49da1 (hbec252), .qt4ed09 (qt4ed09), .dm7684c (dm7684c), .cm6d7e0 (cm6d7e0), .qt75363 (qt75363), .ay4c52f (ay4c52f), .zz98a5 (zz98a5), .ea62978 (ea62978), .tx_discfrm (tx_discfrm), .tja5e0a (tja5e0a), .ng2f056 (ng2f056), .ui782b2 (ui782b2), .goc1590 (goc1590), .wyac80 (wyac80), .yk56400 (yk56400), .twb2000 (twb2000), .gq24775 (gq24775), .oh8001d (oh8001d), .wjedb5f (wjedb5f), .mg760 (mg760), .vx3b00 (vx3b00), .oh1d806 (oh1d806), .xjec034 (xjec034), .cz601a7 (cz601a7), .ksd3d (ksd3d), .jr69e9 (jr69e9), .uk34f4e (uk34f4e), .hqa7a71 (hqa7a71), .bn3d38b (bn3d38b), .nre9c5e (nre9c5e), .wj4e2f6 (wj4e2f6), .fn717b5 (fn717b5), .ph8bdae (ph8bdae), .wj5ed76 (wj5ed76), .os6dafc (os6dafc), .bnb5dae (bnb5dae), .mtaed77 (mtaed77), .rg76bbd (rg76bbd), .hdb5dea (hdb5dea), .iraef57 (iraef57), .kf1dd4d (kf1dd4d), .pseea6c (pseea6c), .kqeaf42 (kqeaf42) );\r
-\r
-ww53ba7 #( .xw422d5(xw422d5), .qte845a(qte845a), .rt6bf01(rt6bf01), .tj8b55b(tj8b55b), .vk25f5d(vk25f5d) ) shf87f9 ( .qvb4f6d (txmac_clk), .baa7b6d (ep811d), .txmac_clk_en (txmac_clk_en),\r
- .lqf1bfb (cze80f6), .mg8dfdb (rt407b5), .tx_sndpausreq (xj6b194), .tx_sndpaustim (qtc6532), .co1f530 (an2999d), .cmfa980 (cmfa980), .nre9c5e (nre9c5e), .os6dafc (hdbac11), .bnb5dae (bnb5dae), .mtaed77 (mtaed77), .jea8807 (hdb5dea), .rg76bbd (rg76bbd), .kqeaf42 (kqeaf42), .mg760 (dm761a5), .cz601a7 (cz601a7), .wj4e2f6 (wj4e2f6), .ksd3d (ksd3d), .hqa7a71 (hqa7a71), .uk34f4e (uk34f4e), .jr69e9 (jr69e9), .ea62978 (ea62978), .ng2f056 (ng2f056), .tx_discfrm (tx_discfrm), .tja5e0a (tja5e0a), .yk56400 (db32bb0), .xj6b139 (xj6b139), .ls30000 (ls30000), .zm201d4 (zm201d4), .mgea3 (mgea3), .db8ea4e (db8ea4e), .zz91d49 (zz91d49), .ww723a9 (ww723a9), .ea49da1 (ea49da1), .qt4ed09 (qt4ed09), .dm7684c (dm7684c), .tx_statvec (tx_statvec), .tx_staten (tx_staten), .tx_done (tx_done), .go46d29 (go46d29), .ay4c52f (ay4c52f), .zz98a5 (zz98a5) );\r
-kdd69ed #( .rt6bf01(rt6bf01) ) wlae7d0 ( .qvb4f6d (txmac_clk), .baa7b6d (ep811d), .txmac_clk_en (txmac_clk_en), .wjedb5f (wjedb5f), .os6dafc (hdbac11), .cm6d7e0 (cm6d7e0) );\r
-\r
-hq8ca24 #( .ps4d8e0(ps4d8e0) ) ngb9ec ( .qvb4f6d (txmac_clk), .baa7b6d (ep811d), .txmac_clk_en (txmac_clk_en), .sj23ba9 (qg67566), .gq24775 (gq24775), .kf1dd4d (kf1dd4d), .pseea6c (pseea6c), .qt75363 (qt75363), .wya9b1c (wya9b1c) );\r
-uk13d #( .xw422d5(xw422d5) ) rgd5016 ( .qvb4f6d (txmac_clk), .baa7b6d (ep811d), .txmac_clk_en (txmac_clk_en), .db3d05f (oh8001d), .cze82fe (an2999d), .qt417f5 (ne66761), .cmfa980 (cmfa980) );\r
-ip41424 ird459 ( .yk46f15(eca93b4), .ykc1859 (db32bb0), .rvc2c9 (twb2000), .ui593bb (dm761a5), .wjc9dd9 (32'hffffffff), .en4eecd (txmac_clk), .gdbb361 (ep811d), .txmac_clk_en (txmac_clk_en) ); uxbbc00 #( .ui53289(ui53289) ) vi47ec5 ( .qvb4f6d (txmac_clk), .baa7b6d (ep811d), .txmac_clk_en (txmac_clk_en), .sw804 (wj5ed76), .tw4021 (iraef57), .xy2010a (fn717b5), .wy853 (ph8bdae), .zm4299 (ec508), .sw214ca (aye0014), .iea651 (ph27391) );\r
-pmi_ram_dp #(.pmi_wr_addr_depth(64), .pmi_wr_addr_width(6), .pmi_wr_data_width(9), .pmi_rd_addr_depth(64), .pmi_rd_addr_width(6), .pmi_rd_data_width(9), .pmi_regmode("noreg"), .pmi_gsr("disable"), .pmi_resetmode("sync"), .pmi_init_file("none"), .pmi_init_file_format("binary"), .pmi_family(pdevice_family), .module_type("pmi_ram_dp") )\r
-lf13e8f (.Data({xj6b139, go6d627}), .WrAddress(aye0014), .RdAddress(ec508), .WrClock(txmac_clk), .RdClock(txmac_clk), .WrClockEn(1'b1), .RdClockEn(txmac_clk_en), .WE(ph8bdae), .Reset(1'b0), .Q(ir39c8e) );\r
-\r
- always@* begin ep811d<=ea5c9d9[0];cze80f6<=ea5c9d9[1];rt407b5<=ea5c9d9[2];vk1ed76<=ea5c9d9[3];jr3dae<=ea5c9d9[4];qg67566<={uxa1b23>>1,ea5c9d9[5]};tud5982<={wld91c>>1,ea5c9d9[6]};bn9ef58<={dzcdac4>>1,ea5c9d9[7]};je1e93c<={tx_fifodata>>1,ea5c9d9[8]};lqf49e3<=ea5c9d9[9];oha4f1b<=ea5c9d9[10];thc7892<=ea5c9d9[11];qtc6532<={tx_sndpaustim>>1,ea5c9d9[12]};xj6b194<=ea5c9d9[13];bn278dc<=ea5c9d9[14];an2999d<=ea5c9d9[15];ne66761<={nr716da>>1,ea5c9d9[16]};phb5d9e<=ea5c9d9[17];fnf6bb3<=ea5c9d9[18];zmbd63c<={go6d627>>1,ea5c9d9[19]};ana485d<={zz91d49>>1,ea5c9d9[20]};zk5d84a<={eca93b4>>1,ea5c9d9[21]};hbec252<=ea5c9d9[22];db32bb0<={yk56400>>1,ea5c9d9[23]};an125a4<={ir39c8e>>1,ea5c9d9[24]};hdbac11<={os6dafc>>1,ea5c9d9[25]};dm761a5<=ea5c9d9[26];ui59c6a<=ea5c9d9[27];jp71a81<={aye0014>>1,ea5c9d9[28]};al6a078<={ec508>>1,ea5c9d9[29]};end\r
-always@* begin ec2b93b[2047]<=lqf1bfb;ec2b93b[2046]<=mg8dfdb;ec2b93b[2044]<=qt7f6cd;ec2b93b[2040]<=cz6fed9;ec2b93b[2032]<=uxa1b23[0];ec2b93b[2017]<=wld91c[0];ec2b93b[1987]<=dzcdac4[0];ec2b93b[1926]<=tx_fifodata[0];ec2b93b[1804]<=tx_fifoeof;ec2b93b[1803]<=yk56400[0];ec2b93b[1560]<=tx_fifoempty;ec2b93b[1558]<=ir39c8e[0];ec2b93b[1550]<=nr716da[0];ec2b93b[1072]<=tx_fifoavail;ec2b93b[1069]<=os6dafc[0];ec2b93b[1052]<=uidb36b;ec2b93b[1023]<=baa7b6d;ec2b93b[901]<=ea49da1;ec2b93b[775]<=psee2db;ec2b93b[732]<=ec508[0];ec2b93b[450]<=eca93b4[0];ec2b93b[387]<=tx_fifoctrl;ec2b93b[366]<=aye0014[0];ec2b93b[225]<=zz91d49[0];ec2b93b[193]<=tx_sndpausreq;ec2b93b[183]<=vx3b00;ec2b93b[112]<=go6d627[0];ec2b93b[96]<=tx_sndpaustim[0];ec2b93b[91]<=mg760;ec2b93b[56]<=fafb66d;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module pf4a32c(\r
- \r
- hclk, \r
- reset_n, \r
-\r
- \r
- haddr, \r
- hdatain, \r
- hread_n, \r
- hwrite_n, \r
- hcs_n, \r
-\r
- \r
- hdataout, \r
- hready_n, \r
- hdataout_en_n, \r
-\r
- \r
- tx_en, \r
- go67cc7, \r
- qi3e639, \r
- uxa1b23, \r
-\r
- \r
- cmf5978, \r
- aa3eb2f, \r
- qv393c7, \r
- kde89f5, \r
- hocace4, \r
- qg78f2f, \r
- hbc7979,\r
- gd3cbce,\r
- cme5e75,\r
- hq2f3a8,\r
- zk79d42,\r
- ykcea13,\r
- qt75098, \r
- ux3959c, \r
- mt1d13e, \r
- yx44fac, \r
- rv27d65, \r
-\r
- \r
- fc30be7, \r
- wl23780, \r
- ls1bc04, \r
- cz6fed9, \r
-\r
- \r
- ie552b, \r
-\r
- \r
- lq4d15b, \r
- os68ada, \r
- ayc1110, \r
- cb8880, \r
- qg78222 \r
-);\r
-\r
-parameter alc39c3 = 8;\r
-\r
-parameter mre70e6 = 8;\r
-parameter lf38734 = 15;\r
-parameter ofc39a6 = 15;\r
-parameter lf1cd34 = 15;\r
-parameter zxe69a6 = 8;\r
-parameter mg34d37 = 3;\r
-parameter uka69b9 = 7;\r
-parameter ym34dc9 = 7;\r
-parameter mga6e49 = 15;\r
-parameter ph37249 = 10;\r
-parameter swb924f = 4;\r
-parameter shc9278 = 10;\r
-parameter su493c4 = 15;\r
-parameter zz30cc = 8;\r
-parameter zx4f101 = 47;\r
-input hclk;\r
-input reset_n;\r
-input [mre70e6 - 1:0] haddr;\r
-input [alc39c3 - 1:0] hdatain;\r
-input hread_n;\r
-input hwrite_n;\r
-input hcs_n;\r
-output [alc39c3 - 1:0] hdataout;\r
-output hready_n;\r
-output hdataout_en_n;\r
-output cz6fed9;\r
-output ux3959c;\r
-output mt1d13e;\r
-output [ofc39a6-2:0] yx44fac;\r
-output rv27d65;\r
-output tx_en;\r
-output go67cc7;\r
-output qi3e639;\r
-output [swb924f:0] uxa1b23;\r
-input ie552b;\r
-input qg78222;\r
-input [lf38734:0] lq4d15b;\r
-input os68ada;\r
-input [zz30cc:0] ayc1110;\r
-input cb8880;\r
-output cmf5978;\r
-output aa3eb2f;\r
-output [zx4f101:0] wl23780;\r
-output qv393c7;\r
-output kde89f5;\r
-output hocace4;\r
-output ls1bc04;\r
-output [ym34dc9:0] qg78f2f;\r
-output [ym34dc9:0] hbc7979;\r
-output [ym34dc9:0] gd3cbce;\r
-output [ym34dc9:0] cme5e75;\r
-output [ym34dc9:0] hq2f3a8;\r
-output [ym34dc9:0] zk79d42;\r
-output [ym34dc9:0] ykcea13;\r
-output [ym34dc9:0] qt75098;\r
-output [lf1cd34:0] fc30be7;\r
-\r
-reg of7a6e5;\r
-reg qtd372d;\r
-reg jr9b96c;\r
-reg mrdcb67;\r
-reg [mre70e6 - 1:0] zz2d9e0;\r
-reg [mre70e6 - 1:0] ui67832;\r
-reg [mre70e6 - 1:0] cme0c8c;\r
-reg [mre70e6 - 1:0] bn32307;\r
-reg [lf1cd34:0] fc30be7;\r
-reg hready_n;\r
-reg [alc39c3 - 1:0] hdataout;\r
-reg hdataout_en_n;\r
-reg enf2913;\r
-reg [alc39c3 - 1:0] oha44e6;\r
-reg [alc39c3 - 1:0] hd139ae;\r
-reg [alc39c3 - 1:0] vve6bba;\r
-reg [alc39c3 - 1:0] iraeebb;\r
-reg [alc39c3 - 1:0] hdbaee9;\r
-reg [1:0] jpd774e;\r
-reg epbba76;\r
-reg [uka69b9:0] dze9da7;\r
-reg [uka69b9:0] jc769f4;\r
-reg [uka69b9:0] hqa7d15;\r
-reg [uka69b9:0] nef4558;\r
-reg [uka69b9:0] mg15613;\r
-reg [uka69b9:0] rg584cc;\r
-reg [uka69b9:0] zz1331f;\r
-reg [uka69b9:0] wjcc7f2;\r
-reg zk63f94;\r
-reg mg1fca3;\r
-reg [zz30cc:0] czf28cb;\r
-reg [swb924f:0] swa32e7;\r
-reg [mg34d37:0] uicb9c7;\r
-reg [zxe69a6:0] ale71c0;\r
-reg [ofc39a6:0] fnc7027;\r
-reg [mga6e49:0] psc09fe;\r
-reg [mga6e49:0] tj27f9b;\r
-reg [mga6e49:0] jcfe6fa;\r
-wire [15:0] dzf37d3;\r
-reg [lf38734:0] psdf4ff;\r
-reg [lf38734:0] yxd3fd1;\r
-reg yz9fe8d;\r
-reg ayff46d;\r
-reg gofa369;\r
-reg [alc39c3 - 1:0] ym8da48;\r
-reg su6d241;\r
-reg ne69209;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg [mre70e6 - 1 : 0] cb8ab2f;\r
-reg [alc39c3 - 1 : 0] ksacbe6;\r
-reg yx65f30;\r
-reg ba2f984;\r
-reg ho7cc23;\r
-reg nre611b;\r
-reg [lf38734 : 0] lf846f3;\r
-reg mt2379e;\r
-reg [zz30cc : 0] kqde7a3;\r
-reg rtf3d18;\r
-reg hd9e8c6;\r
-reg vif4637;\r
-reg ksa31ba;\r
-reg ux18dd0;\r
-reg shc6e84;\r
-reg [mre70e6 - 1 : 0] lfba127;\r
-reg [mre70e6 - 1 : 0] rv849fa;\r
-reg [mre70e6 - 1 : 0] vx27eb8;\r
-reg [mre70e6 - 1 : 0] kqfae3b;\r
-reg hbd71d8;\r
-reg [alc39c3 - 1 : 0] jpc7633;\r
-reg [alc39c3 - 1 : 0] thd8cf9;\r
-reg [alc39c3 - 1 : 0] ir33e75;\r
-reg [alc39c3 - 1 : 0] hbf9d64;\r
-reg [alc39c3 - 1 : 0] ip75938;\r
-reg [1 : 0] ouac9c5;\r
-reg fn64e28;\r
-reg [uka69b9 : 0] xl38a36;\r
-reg [uka69b9 : 0] xl28dba;\r
-reg [uka69b9 : 0] wl36eb0;\r
-reg [uka69b9 : 0] bnbac23;\r
-reg [uka69b9 : 0] dbb08f4;\r
-reg [uka69b9 : 0] an23d3e;\r
-reg [uka69b9 : 0] dmf4fab;\r
-reg [uka69b9 : 0] co3eadb;\r
-reg suf56d8;\r
-reg ohab6c0;\r
-reg [zz30cc : 0] sudb024;\r
-reg [swb924f : 0] psc0907;\r
-reg [mg34d37 : 0] qi241db;\r
-reg [zxe69a6 : 0] oh76ca;\r
-reg [ofc39a6 : 0] ykdb2a9;\r
-reg [mga6e49 : 0] bycaa45;\r
-reg [mga6e49 : 0] coa9157;\r
-reg [mga6e49 : 0] bl455cb;\r
-reg [15 : 0] je2ae5e;\r
-reg [lf38734 : 0] ecb979a;\r
-reg [lf38734 : 0] sh5e680;\r
-reg dzf3404;\r
-reg cb9a027;\r
-reg dmd013c;\r
-reg [alc39c3 - 1 : 0] xy4f1d;\r
-reg jr278eb;\r
-reg qv3c75f;\r
-reg [2047:0] ec2b93b;\r
-wire [53:0] ea5c9d9;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam tue4ec8 = 54,ph27642 = 32'hfdffe30b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-assign qg78f2f = xl38a36[7:0];\r
-assign hbc7979 = xl28dba[7:0];\r
-assign gd3cbce = wl36eb0[7:0];\r
-assign cme5e75 = bnbac23[7:0];\r
-assign hq2f3a8 = dbb08f4[7:0];\r
-assign zk79d42 = an23d3e[7:0];\r
-assign ykcea13 = dmf4fab[7:0];\r
-assign qt75098 = co3eadb[7:0];\r
-assign tx_en = qi241db[3];\r
-assign go67cc7 = qi241db[1];\r
-assign aa3eb2f = qi241db[2];\r
-assign wl23780 = {bycaa45,coa9157,bl455cb};\r
-assign hocace4 = oh76ca[0];\r
-assign rv27d65 = oh76ca[1];\r
-assign qi3e639 = oh76ca[2];\r
-assign kde89f5 = oh76ca[3];\r
-assign qv393c7 = oh76ca[4];\r
-assign cmf5978 = oh76ca[6];\r
-assign ux3959c = oh76ca[7];\r
-assign mt1d13e = oh76ca[8];\r
-assign yx44fac = ykdb2a9[13:0];\r
-assign uxa1b23 = (psc0907 < 4) ? 1 : psc0907 - 3;\r
-assign dzf37d3 = {5'b00000,ksa31ba,sudb024[8:0],shc6e84};\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- assign cz6fed9 = qi241db[0] ? 1'b0 : oh76ca[5]; assign ls1bc04 = qi241db[0];\r
-\r
-\r
-\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin zz2d9e0 <= 8'h0; ui67832 <= 8'h0; cme0c8c <= 8'h0; bn32307 <= 8'h0; yz9fe8d <= 1'b1; ayff46d <= 1'b1; gofa369 <= 1'b1; ym8da48 <= 0; end else begin zz2d9e0 <= cb8ab2f; ui67832 <= lfba127; cme0c8c <= rv849fa; bn32307 <= vx27eb8; yz9fe8d <= ho7cc23; ayff46d <= yx65f30; gofa369 <= ba2f984; ym8da48 <= ksacbe6; end\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) of7a6e5 <= 1'b0; else of7a6e5 <= hd9e8c6;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) qtd372d <= 1'b0; else qtd372d <= vif4637;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) jr9b96c <= 1'b0; else jr9b96c <= nre611b;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) mrdcb67 <= 1'b0; else mrdcb67 <= ux18dd0;\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) zk63f94 <= 1'b0; else zk63f94 <= rtf3d18;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) mg1fca3 <= 1'b0; else mg1fca3 <= suf56d8;\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) czf28cb <= 9'b000000000; else if (ohab6c0) czf28cb <= kqde7a3;\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin psdf4ff <= 16'h00; end else if (mt2379e) begin psdf4ff <= lf846f3; end\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin yxd3fd1 <= 16'h00; su6d241 <= 1'b1; ne69209 <= 1'b1; end else begin yxd3fd1 <= ecb979a; su6d241 <= hbd71d8; ne69209 <= jr278eb; end\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge hclk or negedge reset_n) if (!reset_n) begin\r
- jpd774e <= 2'b00; dze9da7 <= 8'h00; jc769f4 <= 8'h00; hqa7d15 <= 8'h00; nef4558 <= 8'h00; mg15613 <= 8'h00; rg584cc <= 8'h00; zz1331f <= 8'h00; wjcc7f2 <= 8'h00; swa32e7 <= 5'b01100; uicb9c7 <= 4'h0; ale71c0 <= 8'h0; fnc7027 <= 16'd1518; psc09fe <= 16'h00; tj27f9b <= 16'h00; jcfe6fa <= 16'h00; hready_n <= 1'b1; fc30be7 <= 16'h0001; hdataout <= 0; hdataout_en_n <= 1; epbba76 <= 1; oha44e6 <= 0; hd139ae <= 0; vve6bba <= 0; iraeebb <= 0; hdbaee9 <= 0; enf2913 <= 1'b1; end else begin hdataout <= jpc7633; hdataout_en_n <= fn64e28; hready_n <= hbd71d8; if (!hbd71d8 || !jr278eb) begin enf2913 <= 1'b1; epbba76 <= 1'b1; end else if (!ho7cc23 && !dzf3404 && !ba2f984 && !dmd013c && hbd71d8 && qv3c75f && jr278eb) begin enf2913 <= 1'b0; if (lfba127 == 8'h00) begin uicb9c7 <= xy4f1d; end else if (!qi241db[3] && !qi241db[2]) begin case(lfba127) 8'h02 : ale71c0[7:0] <= xy4f1d[7:0]; 8'h04 : fnc7027[7:0] <= xy4f1d; 8'h08 : swa32e7[4:0] <= xy4f1d; 8'h0A : psc09fe[7:0] <= xy4f1d; 8'h0C : tj27f9b[7:0] <= xy4f1d; 8'h0E : jcfe6fa[7:0] <= xy4f1d; 8'h22 : dze9da7[7:0] <= xy4f1d; 8'h24 : jc769f4[7:0] <= xy4f1d; 8'h26 : hqa7d15[7:0] <= xy4f1d; 8'h28 : nef4558[7:0] <= xy4f1d; 8'h2A : mg15613[7:0] <= xy4f1d; 8'h2C : rg584cc[7:0] <= xy4f1d; 8'h2E : zz1331f[7:0] <= xy4f1d; 8'h30 : wjcc7f2[7:0] <= xy4f1d; 8'h34 : fc30be7[7:0] <= xy4f1d; 8'h03 : ale71c0[8] <= xy4f1d[0]; 8'h05 : fnc7027[15:8] <= xy4f1d; 8'h0B : psc09fe[15:8] <= xy4f1d; 8'h0D : tj27f9b[15:8] <= xy4f1d; 8'h0F : jcfe6fa[15:8] <= xy4f1d; 8'h35 : fc30be7[15:8] <= xy4f1d; default : uicb9c7 <= qi241db; endcase end end else if (!ho7cc23 && !dzf3404 && !yx65f30 && !cb9a027 && hbd71d8 && lfba127[0] && qv3c75f) begin epbba76 <= 1'b0; enf2913 <= 1'b0; case(lfba127) 8'h03 : oha44e6 <= {7'h0,oh76ca[8]}; 8'h05 : oha44e6 <= ykdb2a9[15:8]; 8'h0B : oha44e6 <= bycaa45[15:8]; 8'h0D : oha44e6 <= coa9157[15:8]; 8'h0F : oha44e6 <= bl455cb[15:8]; 8'h13 : oha44e6 <= je2ae5e[15:8]; default : oha44e6 <= 8'h0; endcase end else if (!ho7cc23 && !dzf3404 && !yx65f30 && !cb9a027 && hbd71d8 && !lfba127[0] && qv3c75f) begin epbba76 <= 1'b0; enf2913 <= 1'b0; case(lfba127) 8'h00 : oha44e6 <= {4'b0000,qi241db};\r
-\r
-\r
- 8'h02 : oha44e6 <= oh76ca[7:0];\r
-\r
-\r
- 8'h04 : oha44e6 <= ykdb2a9[7:0]; 8'h08 : oha44e6 <= {3'b000,psc0907[4:0]}; 8'h0A : oha44e6 <= bycaa45[7:0]; 8'h0C : oha44e6 <= coa9157[7:0]; 8'h0E : oha44e6 <= bl455cb[7:0]; 8'h12 : oha44e6 <= je2ae5e[7:0]; 8'h22 : oha44e6 <= xl38a36[7:0]; 8'h24 : oha44e6 <= xl28dba[7:0]; 8'h26 : oha44e6 <= wl36eb0[7:0]; 8'h28 : oha44e6 <= bnbac23[7:0]; 8'h2A : oha44e6 <= dbb08f4[7:0]; 8'h2C : oha44e6 <= an23d3e[7:0]; 8'h2E : oha44e6 <= dmf4fab[7:0]; 8'h30 : oha44e6 <= co3eadb[7:0]; 8'h32 : oha44e6 <= sh5e680[7:0]; 8'h34 : oha44e6 <= fc30be7[7:0]; default : oha44e6 <= 8'h0; endcase end end\r
-\r
-\r
-\r
-\r
-\r
-always@* begin cb8ab2f<={haddr>>1,ea5c9d9[0]};ksacbe6<={hdatain>>1,ea5c9d9[1]};yx65f30<=ea5c9d9[2];ba2f984<=ea5c9d9[3];ho7cc23<=ea5c9d9[4];nre611b<=ea5c9d9[5];lf846f3<={lq4d15b>>1,ea5c9d9[6]};mt2379e<=ea5c9d9[7];kqde7a3<={ayc1110>>1,ea5c9d9[8]};rtf3d18<=ea5c9d9[9];hd9e8c6<=ea5c9d9[10];vif4637<=ea5c9d9[11];ksa31ba<=ea5c9d9[12];ux18dd0<=ea5c9d9[13];shc6e84<=ea5c9d9[14];lfba127<={zz2d9e0>>1,ea5c9d9[15]};rv849fa<={ui67832>>1,ea5c9d9[16]};vx27eb8<={cme0c8c>>1,ea5c9d9[17]};kqfae3b<={bn32307>>1,ea5c9d9[18]};hbd71d8<=ea5c9d9[19];jpc7633<={oha44e6>>1,ea5c9d9[20]};thd8cf9<={hd139ae>>1,ea5c9d9[21]};ir33e75<={vve6bba>>1,ea5c9d9[22]};hbf9d64<={iraeebb>>1,ea5c9d9[23]};ip75938<={hdbaee9>>1,ea5c9d9[24]};ouac9c5<={jpd774e>>1,ea5c9d9[25]};fn64e28<=ea5c9d9[26];xl38a36<={dze9da7>>1,ea5c9d9[27]};xl28dba<={jc769f4>>1,ea5c9d9[28]};wl36eb0<={hqa7d15>>1,ea5c9d9[29]};bnbac23<={nef4558>>1,ea5c9d9[30]};dbb08f4<={mg15613>>1,ea5c9d9[31]};an23d3e<={rg584cc>>1,ea5c9d9[32]};dmf4fab<={zz1331f>>1,ea5c9d9[33]};co3eadb<={wjcc7f2>>1,ea5c9d9[34]};suf56d8<=ea5c9d9[35];ohab6c0<=ea5c9d9[36];sudb024<={czf28cb>>1,ea5c9d9[37]};psc0907<={swa32e7>>1,ea5c9d9[38]};qi241db<={uicb9c7>>1,ea5c9d9[39]};oh76ca<={ale71c0>>1,ea5c9d9[40]};ykdb2a9<={fnc7027>>1,ea5c9d9[41]};bycaa45<={psc09fe>>1,ea5c9d9[42]};coa9157<={tj27f9b>>1,ea5c9d9[43]};bl455cb<={jcfe6fa>>1,ea5c9d9[44]};je2ae5e<={dzf37d3>>1,ea5c9d9[45]};ecb979a<={psdf4ff>>1,ea5c9d9[46]};sh5e680<={yxd3fd1>>1,ea5c9d9[47]};dzf3404<=ea5c9d9[48];cb9a027<=ea5c9d9[49];dmd013c<=ea5c9d9[50];xy4f1d<={ym8da48>>1,ea5c9d9[51]};jr278eb<=ea5c9d9[52];qv3c75f<=ea5c9d9[53];end\r
-always@* begin ec2b93b[2047]<=hdatain[0];ec2b93b[2046]<=hread_n;ec2b93b[2044]<=hwrite_n;ec2b93b[2040]<=hcs_n;ec2b93b[2032]<=ie552b;ec2b93b[2016]<=lq4d15b[0];ec2b93b[1985]<=os68ada;ec2b93b[1925]<=fnc7027[0];ec2b93b[1922]<=ayc1110[0];ec2b93b[1802]<=psc09fe[0];ec2b93b[1796]<=cb8880;ec2b93b[1556]<=tj27f9b[0];ec2b93b[1544]<=qg78222;ec2b93b[1505]<=uicb9c7[0];ec2b93b[1324]<=ayff46d;ec2b93b[1316]<=dze9da7[0];ec2b93b[1200]<=ym8da48[0];ec2b93b[1169]<=hqa7d15[0];ec2b93b[1163]<=rg584cc[0];ec2b93b[1118]<=zk63f94;ec2b93b[1106]<=iraeebb[0];ec2b93b[1065]<=jcfe6fa[0];ec2b93b[1041]<=cme0c8c[0];ec2b93b[1040]<=of7a6e5;ec2b93b[1023]<=haddr[0];ec2b93b[962]<=ale71c0[0];ec2b93b[752]<=swa32e7[0];ec2b93b[707]<=ne69209;ec2b93b[662]<=yz9fe8d;ec2b93b[658]<=epbba76;ec2b93b[600]<=gofa369;ec2b93b[584]<=jc769f4[0];ec2b93b[581]<=mg15613[0];ec2b93b[559]<=wjcc7f2[0];ec2b93b[553]<=vve6bba[0];ec2b93b[520]<=ui67832[0];ec2b93b[376]<=czf28cb[0];ec2b93b[353]<=su6d241;ec2b93b[331]<=yxd3fd1[0];ec2b93b[329]<=jpd774e[0];ec2b93b[290]<=nef4558[0];ec2b93b[279]<=zz1331f[0];ec2b93b[276]<=hd139ae[0];ec2b93b[260]<=zz2d9e0[0];ec2b93b[188]<=mg1fca3;ec2b93b[165]<=psdf4ff[0];ec2b93b[164]<=hdbaee9[0];ec2b93b[138]<=oha44e6[0];ec2b93b[130]<=mrdcb67;ec2b93b[82]<=dzf37d3[0];ec2b93b[69]<=enf2913;ec2b93b[65]<=jr9b96c;ec2b93b[34]<=bn32307[0];ec2b93b[32]<=qtd372d;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module rib863f(\r
-mef0118, \r
-sj808c0, \r
-tw4605, \r
-yz2302a, \r
-cb18154, \r
-hoc0aa5, \r
-reset_n, \r
-mdc, \r
-mdi, \r
-mdo, \r
-mdio_en \r
-);\r
-localparam ou1054f = 14'b00000000000001;\r
-localparam uk82a79 = 14'b00000000000010;\r
-localparam ec153c8 = 14'b00000000000100;\r
-localparam swa9e41 = 14'b00000000001000;\r
-localparam ld4f208 = 14'b00000000010000;\r
-localparam tu79047 = 14'b00000000100000;\r
-localparam blc823a = 14'b00000001000000;\r
-localparam of411d6 = 14'b00000010000000;\r
-localparam kf8eb4 = 14'b00000100000000;\r
-localparam lq475a5 = 14'b00001000000000;\r
-localparam pu3ad2b = 14'b00010000000000;\r
-localparam uvd695a = 14'b00100000000000;\r
-localparam sjb4ad5 = 14'b01000000000000;\r
-localparam tja56ad = 14'b10000000000000;\r
-parameter qi2b56f = 10;\r
-parameter vv5ab78 = 15;\r
-parameter dmd5bc7 = 4;\r
-parameter hqade3a = 2;\r
-parameter al6f1d2 = 3;\r
-parameter ui78e94 = 13;\r
-input reset_n;\r
-input mdc;\r
-input [qi2b56f:0] mef0118;\r
-input [vv5ab78:0] sj808c0;\r
-input yz2302a;\r
-input mdi;\r
-output mdo;\r
-output mdio_en;\r
-output hoc0aa5;\r
-output cb18154;\r
-output [vv5ab78:0] tw4605;\r
-reg [vv5ab78:0] tw4605;\r
-reg cb18154;\r
-reg mdio_en;\r
-reg zxd8bd6;\r
-reg mdo;\r
-reg [vv5ab78:0] sh7ad9a;\r
-reg [vv5ab78:0] aab66a5;\r
-reg [vv5ab78:0] ux9a949;\r
-reg [dmd5bc7:0] pha5268;\r
-reg [hqade3a:0] qg49a3d;\r
-reg [hqade3a:0] ic68f4a;\r
-reg [al6f1d2:0] hd3d282;\r
-reg [al6f1d2:0] vv4a0b7;\r
-reg [ui78e94:0] ou82dff;\r
-reg [ui78e94:0] xyb7fc7;\r
-reg dbbfe3a;\r
-reg ayff1d6;\r
-reg ipf8eb1;\r
-reg vvc758d;\r
-reg ri3ac6f;\r
-reg hoc0aa5;\r
-reg [qi2b56f : 0] uk8dea5;\r
-reg [vv5ab78 : 0] en7a94c;\r
-reg icd4a64;\r
-reg xla5320;\r
-reg yz29907;\r
-reg [vv5ab78 : 0] rt641e1;\r
-reg [vv5ab78 : 0] an787a;\r
-reg [vv5ab78 : 0] tue1ea4;\r
-reg [dmd5bc7 : 0] cz7a911;\r
-reg [hqade3a : 0] yza4460;\r
-reg [hqade3a : 0] vk1182e;\r
-reg [al6f1d2 : 0] sh60b92;\r
-reg [al6f1d2 : 0] ks2e4a1;\r
-reg [ui78e94 : 0] wy92841;\r
-reg [ui78e94 : 0] ira104f;\r
-reg ir827d;\r
-reg sh413ec;\r
-reg rv9f64;\r
-reg rt4fb27;\r
-reg kq7d93e;\r
-reg [2047:0] ec2b93b;\r
-wire [19:0] ea5c9d9;\r
-\r
-localparam tue4ec8 = 20,ph27642 = 32'hfdffd28b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin vvc758d <= 1'b0; end else begin vvc758d <= icd4a64; end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin ri3ac6f <= 1'b0; end else begin ri3ac6f <= rt4fb27; end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin ipf8eb1 <= 1'b0; dbbfe3a <= 1'b0; ayff1d6 <= 1'b0; ux9a949 <= 16'h0; aab66a5 <= 16'h0; end else if (cb18154) begin ipf8eb1 <= 1'b0; dbbfe3a <= 1'b0; ayff1d6 <= 1'b0; end else if (kq7d93e && !rv9f64) begin ipf8eb1 <= 1'b1; ux9a949 <= {3'b000,uk8dea5,2'b00}; aab66a5 <= en7a94c; if (uk8dea5[10]) dbbfe3a <= 1'b1; else ayff1d6 <= 1'b1; end\r
-\r
-\r
-always @(negedge mdc or negedge reset_n) begin if (!reset_n) begin mdo <= 1'b0; end else begin mdo <= yz29907; end\r
-end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin pha5268 <= 5'b00000; zxd8bd6 <= 1'b0; mdio_en <= 1'b0; cb18154 <= 1'b0; tw4605 <= 16'h0; sh7ad9a <= 16'h0; qg49a3d <= 3'b000; ic68f4a <= 3'b110; hd3d282 <= 4'b1011; vv4a0b7 <= 4'b1111; end else if (wy92841 == ou1054f) begin cb18154 <= 1'b0; pha5268 <= 5'b00000; zxd8bd6 <= 1'b0; mdio_en <= 1'b0; qg49a3d <= 3'b000; ic68f4a <= 3'b110; hd3d282 <= 4'b1011; vv4a0b7 <= 4'b1111; end else if (wy92841 == uk82a79) begin pha5268 <= cz7a911 + 5'b00001; zxd8bd6 <= 1'b1; mdio_en <= 1'b1; end else if (wy92841 == swa9e41) begin pha5268 <= 5'b00000; zxd8bd6 <= 1'b1; mdio_en <= 1'b1; end else if (wy92841 == ec153c8) begin pha5268 <= 5'b00000; zxd8bd6 <= 1'b0; mdio_en <= 1'b1; end else if (wy92841 == lq475a5) begin if (ir827d) begin mdio_en <= 1'b1; zxd8bd6 <= 1'b1; end else begin mdio_en <= 1'b0; zxd8bd6 <= 1'b0; end end else if (wy92841 == ld4f208) begin zxd8bd6 <= 1'b0; mdio_en <= 1'b1; end else if (wy92841 == tu79047) begin zxd8bd6 <= 1'b1; mdio_en <= 1'b1; end else if (wy92841 == kf8eb4) begin if (ir827d) begin zxd8bd6 <= 1'b0; mdio_en <= 1'b1; end else zxd8bd6 <= 1'b0; end else if (wy92841 == uvd695a) begin if (ir827d) begin zxd8bd6 <= an787a[ks2e4a1]; vv4a0b7 <= ks2e4a1 - 4'b0001; mdio_en <= 1'b1; end else begin zxd8bd6 <= 1'b0; mdio_en <= 1'b0; sh7ad9a[ks2e4a1] <= xla5320; vv4a0b7 <= ks2e4a1 - 4'b0001; end pha5268 <= cz7a911 + 5'b00001; end else if (wy92841 == blc823a) begin mdio_en <= 1'b1; zxd8bd6 <= tue1ea4[sh60b92]; hd3d282 <= sh60b92 - 4'b0001; pha5268 <= cz7a911 + 5'b00001; end else if (wy92841 == of411d6) begin mdio_en <= 1'b1; zxd8bd6 <= tue1ea4[vk1182e]; ic68f4a <= vk1182e - 3'b001; qg49a3d <= yza4460 + 3'b001; pha5268 <= 5'b00000; end else if (wy92841 == sjb4ad5) begin mdio_en <= 1'b0; zxd8bd6 <= 1'b0; pha5268 <= 5'b00000; cb18154 <= 1'b1; tw4605 <= rt641e1; end else if (wy92841 == tja56ad) begin mdio_en <= 1'b0; zxd8bd6 <= 1'b0; pha5268 <= 5'b00000; cb18154 <= 1'b1; tw4605 <= rt641e1; end\r
-\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin hoc0aa5 <= 1'b1; end else if (wy92841 == ou1054f && !kq7d93e) begin hoc0aa5 <= 1'b1; end else begin hoc0aa5 <= 1'b0; end\r
-\r
-always @(posedge mdc or negedge reset_n) if (!reset_n) begin ou82dff <= ou1054f; end else begin ou82dff <= ira104f; end\r
-always @(wy92841 or ir827d or sh413ec or cz7a911 or yza4460) begin case(wy92841) ou1054f : begin if (ir827d || sh413ec) begin xyb7fc7 = uk82a79; end else begin xyb7fc7 = ou1054f; end end uk82a79 : begin if (cz7a911 < 5'b11111) begin xyb7fc7 = uk82a79; end else begin xyb7fc7 = ec153c8; end end ec153c8 : begin xyb7fc7 = swa9e41; end swa9e41 : begin if (ir827d) begin xyb7fc7 = ld4f208; end else begin xyb7fc7 = tu79047; end end ld4f208 : begin if (ir827d) begin xyb7fc7 = tu79047; end else begin xyb7fc7 = blc823a; end end tu79047 : begin if (sh413ec) begin xyb7fc7 = ld4f208; end else begin xyb7fc7 = blc823a; end end blc823a : begin if (cz7a911 < 5'b00100) begin xyb7fc7 = blc823a; end else begin xyb7fc7 = of411d6; end end of411d6 : begin if (yza4460 < 3'b100) begin xyb7fc7 = of411d6; end else begin xyb7fc7 = lq475a5; end end\r
- lq475a5 : begin xyb7fc7 = kf8eb4; end kf8eb4 : begin if (ir827d) xyb7fc7 = uvd695a; else xyb7fc7 = pu3ad2b; end pu3ad2b : begin xyb7fc7 = uvd695a; end\r
- uvd695a : begin if (cz7a911 < 5'b01111) begin xyb7fc7 = uvd695a; end else begin xyb7fc7 = sjb4ad5; end end sjb4ad5 : begin xyb7fc7 = tja56ad; end\r
- tja56ad : begin xyb7fc7 = ou1054f; end default : begin xyb7fc7 = ou1054f; end endcase end\r
-always@* begin uk8dea5<={mef0118>>1,ea5c9d9[0]};en7a94c<={sj808c0>>1,ea5c9d9[1]};icd4a64<=ea5c9d9[2];xla5320<=ea5c9d9[3];yz29907<=ea5c9d9[4];rt641e1<={sh7ad9a>>1,ea5c9d9[5]};an787a<={aab66a5>>1,ea5c9d9[6]};tue1ea4<={ux9a949>>1,ea5c9d9[7]};cz7a911<={pha5268>>1,ea5c9d9[8]};yza4460<={qg49a3d>>1,ea5c9d9[9]};vk1182e<={ic68f4a>>1,ea5c9d9[10]};sh60b92<={hd3d282>>1,ea5c9d9[11]};ks2e4a1<={vv4a0b7>>1,ea5c9d9[12]};wy92841<={ou82dff>>1,ea5c9d9[13]};ira104f<={xyb7fc7>>1,ea5c9d9[14]};ir827d<=ea5c9d9[15];sh413ec<=ea5c9d9[16];rv9f64<=ea5c9d9[17];rt4fb27<=ea5c9d9[18];kq7d93e<=ea5c9d9[19];end\r
-always@* begin ec2b93b[2047]<=sj808c0[0];ec2b93b[2046]<=yz2302a;ec2b93b[2044]<=mdi;ec2b93b[2040]<=zxd8bd6;ec2b93b[2032]<=sh7ad9a[0];ec2b93b[2017]<=aab66a5[0];ec2b93b[1987]<=ux9a949[0];ec2b93b[1926]<=pha5268[0];ec2b93b[1804]<=qg49a3d[0];ec2b93b[1614]<=ayff1d6;ec2b93b[1561]<=ic68f4a[0];ec2b93b[1180]<=ipf8eb1;ec2b93b[1074]<=hd3d282[0];ec2b93b[1023]<=mef0118[0];ec2b93b[807]<=dbbfe3a;ec2b93b[625]<=ri3ac6f;ec2b93b[403]<=xyb7fc7[0];ec2b93b[312]<=vvc758d;ec2b93b[201]<=ou82dff[0];ec2b93b[100]<=vv4a0b7[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module pu96d5c(\r
-\r
- \r
-txmac_clk, \r
-rxmac_clk, \r
-reset_n, \r
-rxmac_clk_en, \r
-txmac_clk_en, \r
-\r
- \r
-ux18d4e, \r
-shc6a74, \r
-pu353a4, \r
-\r
- \r
-mt90006, \r
-xjd2000, \r
-mtbb27f, \r
-ou1a400, \r
-ald93fd, \r
-gd80035, \r
-\r
- \r
-tj84f70, \r
-db27b87, \r
-\r
- crs, \r
- col, \r
-\r
-\r
- \r
-txd_pos, \r
- \r
- \r
-txd_neg, \r
- \r
-tx_en, \r
-tx_er, \r
-\r
-\r
-ls1bc04, \r
-rv27d65, \r
-\r
- \r
-rx_dv_pos, \r
-rx_dv_neg, \r
-rx_er_pos, \r
-rx_er_neg, \r
-rxd_pos, \r
-rxd_neg \r
-);\r
-parameter aydb60a = 8;\r
-parameter medb050 = 8;\r
-parameter hbd8280 = 4;\r
-input txmac_clk;\r
-input rxmac_clk;\r
-input reset_n;\r
-input rxmac_clk_en;\r
-input txmac_clk_en;\r
-input [aydb60a-1:0] ux18d4e;\r
-input shc6a74;\r
-input pu353a4;\r
-output mt90006;\r
-output xjd2000;\r
-output mtbb27f;\r
-output ou1a400;\r
-output [aydb60a-1:0] ald93fd;\r
-output tj84f70;\r
-output db27b87;\r
-input ls1bc04;\r
-input rv27d65;\r
-\r
-input col;\r
-input crs;\r
-\r
-output [7:0] txd_pos;\r
-output [3:0] txd_neg;\r
-output tx_en;\r
-output tx_er;\r
-output gd80035;\r
-input rx_dv_pos;\r
-input rx_dv_neg;\r
-input rx_er_pos;\r
-input rx_er_neg;\r
-input [7:0] rxd_pos;\r
-input [3:0] rxd_neg;\r
-reg ui4c131;\r
-reg kd60988;\r
-reg tw4c44;\r
-reg mt90006 ;\r
-reg gq3111c;\r
-reg uk888e0;\r
-reg of44701 ;\r
-reg kf2380c ;\r
-reg zz1c065 ;\r
-reg xjd2000 ;\r
-reg hq1979;\r
-reg lfcbcb;\r
-reg [aydb60a-1:0] vk2f2fc;\r
-reg [aydb60a-1:0] gocbf12;\r
-reg [aydb60a-1:0] rtfc487;\r
-reg [aydb60a-1:0] ald93fd ;\r
-reg [aydb60a-1:0] qi87d24;\r
-reg [aydb60a-1:0] nef4900;\r
-reg ou1a400 ;\r
-reg wy2401c ;\r
-reg pu200e1 ;\r
-reg ks70b ;\r
-reg mtbb27f ;\r
-reg rv1c2c6;\r
-reg xwe1637;\r
-reg [7:0] txd_pos;\r
-reg [3:0] txd_neg;\r
-reg tx_en;\r
-reg tx_er;\r
-reg epbb6a7;\r
-reg medb53d;\r
-reg fada9e8;\r
-reg gd80035 ;\r
-reg pua7a18;\r
-reg nt3d0c3;\r
-reg [aydb60a-1:0] ea430f5;\r
-reg mt187a9;\r
-reg kdc3d4d;\r
-reg do1ea6c;\r
-reg osf5363;\r
-reg gqa9b18;\r
-reg rg4d8c0;\r
-reg ps6c603;\r
-reg ps6301b;\r
-reg [hbd8280-1:0] dmc06d5;\r
-reg bn36aa;\r
-reg [medb050-1:0] nedaaba;\r
-reg [3:0] rgd55d3;\r
-reg [3:0] vxaae9b;\r
-reg lq574df;\r
-reg vxba6fa;\r
-reg uvd37d7;\r
-reg ph9bebc;\r
-reg hodf5e7;\r
-reg qgfaf3a;\r
-reg dzd79d0;\r
-reg ksbce87;\r
-reg kde7439;\r
-wire tj84f70;\r
-wire db27b87;\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg [aydb60a - 1 : 0] cb398d1;\r
-reg yxcc68d;\r
-reg ps6346c;\r
-reg gq1a362;\r
-reg co10e3c;\r
-reg uk8d880;\r
-reg ne6c401;\r
-reg yk6200b;\r
-reg aa10058;\r
-reg [7 : 0] oh802c1;\r
-reg [3 : 0] je160c;\r
-reg vkb062;\r
-reg vi58313;\r
-reg cmc189b;\r
-reg xlc4d9;\r
-reg go626ce;\r
-reg ph13670;\r
-reg bn9b386;\r
-reg wjd9c36;\r
-reg goce1b4;\r
-reg gb70da1;\r
-reg [aydb60a - 1 : 0] ux3686a;\r
-reg [aydb60a - 1 : 0] gda1aa4;\r
-reg [aydb60a - 1 : 0] of6a924;\r
-reg [aydb60a - 1 : 0] wla492c;\r
-reg [aydb60a - 1 : 0] sw24b20;\r
-reg fc25900;\r
-reg gd2c802;\r
-reg th64014;\r
-reg ri200a7;\r
-reg aa53b;\r
-reg cb29d8;\r
-reg ri14ec4;\r
-reg pua7622;\r
-reg gq3b112;\r
-reg fnd8891;\r
-reg [aydb60a - 1 : 0] db22470;\r
-reg qv12386;\r
-reg jr91c34;\r
-reg fp8e1a6;\r
-reg yx70d37;\r
-reg ng869bd;\r
-reg aa34dea;\r
-reg coa6f51;\r
-reg nt37a89;\r
-reg [hbd8280 - 1 : 0] uiea272;\r
-reg al51390;\r
-reg [medb050 - 1 : 0] kd4e42b;\r
-reg [3 : 0] kq7215d;\r
-reg [3 : 0] gd90ae9;\r
-reg gd8574c;\r
-reg wy2ba64;\r
-reg tu5d321;\r
-reg pfe990b;\r
-reg kq4c85e;\r
-reg nr642f1;\r
-reg uk2178f;\r
-reg zmbc79;\r
-reg yx5e3ca;\r
-reg [2047:0] ec2b93b;\r
-wire [58:0] ea5c9d9;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam tue4ec8 = 59,ph27642 = 32'hfdffc70b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
- assign db27b87 = col; assign tj84f70 = crs;\r
-\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin dmc06d5 <= 4'b0000; bn36aa <= 1'b1; end else if (rxmac_clk_en) begin if (!al51390 && !gd8574c) begin if (uiea272 < 4'b1011) begin dmc06d5 <= uiea272 + 4'b0001; end else begin dmc06d5 <= 4'b0000; bn36aa <= 1'b1; end end else if (wy2ba64) begin dmc06d5 <= 4'b0000; bn36aa <= 1'b0; end end\r
-end\r
-\r
-\r
- always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin gqa9b18 <= 1'b0; rg4d8c0 <= 1'b0; end else if (rxmac_clk_en) begin gqa9b18 <= 1'b1; rg4d8c0 <= ng869bd; end end\r
-\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin ps6c603 <= 1'b0; ps6301b <= 1'b0; end else if (rxmac_clk_en) begin ps6c603 <= co10e3c; ps6301b <= coa6f51; end\r
-end\r
-\r
-\r
- always @(posedge txmac_clk or negedge reset_n) begin if (!reset_n) begin do1ea6c <= 1'b0; osf5363 <= 1'b0; end else if (txmac_clk_en) begin do1ea6c <= 1'b1; osf5363 <= fp8e1a6; end end\r
-\r
-\r
-\r
-\r
-always @(negedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin uvd37d7 <= 0; ph9bebc <= 0; qgfaf3a <= 0; dzd79d0 <= 0; rgd55d3 <= 0; vxaae9b <= 0; end else if (rxmac_clk_en) begin uvd37d7 <= ne6c401; ph9bebc <= tu5d321; qgfaf3a <= aa10058; dzd79d0 <= nr642f1; rgd55d3 <= je160c; vxaae9b <= kq7215d; end\r
-end\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin lq574df <= 0; vxba6fa <= 0; hodf5e7 <= 0; nedaaba <= 0; end else if (rxmac_clk_en) begin lq574df <= uk8d880; vxba6fa <= gd8574c; hodf5e7 <= yk6200b; nedaaba <= oh802c1; end\r
-end\r
-\r
-\r
-\r
-always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin ksbce87 <= 0; kde7439 <= 0; vk2f2fc <= 0; gocbf12 <= 0; rtfc487 <= 0; ald93fd <= 0; qi87d24 <= 0; nef4900 <= 0; ou1a400 <= 0; wy2401c <= 0; pu200e1 <= 0; ks70b <= 0; mtbb27f <= 0; rv1c2c6 <= 0; xwe1637 <= 0; of44701 <= 0; kf2380c <= 0; zz1c065 <= 0; xjd2000 <= 0; hq1979 <= 0; lfcbcb <= 0; ui4c131 <= 0; kd60988 <= 0; tw4c44 <= 0; mt90006 <= 0; gq3111c <= 0; uk888e0 <= 0; epbb6a7 <= 0; medb53d <= 0; fada9e8 <= 0; gd80035 <= 0; nt3d0c3 <= 0; pua7a18 <= 0; end else if (rxmac_clk_en) begin ald93fd <= of6a924; mtbb27f <= th64014; xjd2000 <= wjd9c36; mt90006 <= cmc189b; gd80035 <= pua7622; rtfc487 <= gda1aa4; ks70b <= gd2c802; zz1c065 <= bn9b386; tw4c44 <= vi58313; fada9e8 <= ri14ec4; gocbf12 <= ux3686a; pu200e1 <= fc25900; kf2380c <= ph13670; kd60988 <= vkb062; medb53d <= cb29d8; if (aa34dea) begin vk2f2fc <= wla492c; wy2401c <= ri200a7; of44701 <= goce1b4; ui4c131 <= xlc4d9; epbb6a7 <= gq3b112; if (nt37a89) begin ou1a400 <= ri200a7 & mtbb27f; end else begin ou1a400 <= mtbb27f; end end else begin vk2f2fc <= sw24b20; wy2401c <= aa53b; of44701 <= gb70da1; ui4c131 <= go626ce; epbb6a7 <= fnd8891; if (nt37a89) begin ou1a400 <= aa53b & mtbb27f; end else begin ou1a400 <= mtbb27f; end end rv1c2c6 <= gd8574c; qi87d24 <= kd4e42b; hq1979 <= kq4c85e; gq3111c <= 0; if ((wy2ba64 == 0) && (gd8574c == 1)) begin pua7a18 <= ~al51390; end if ((wy2ba64 == 0) && (pfe990b == 1)) begin ksbce87 <= 0; xwe1637 <= gd8574c & pfe990b; nef4900 <= {kd4e42b[3:0], gd90ae9}; lfcbcb <= kq4c85e | uk2178f; nt3d0c3 <= ~al51390; if ({kd4e42b[3:0], gd90ae9} == 8'hd5) begin kde7439 <= 0; end else begin kde7439 <= 1; end end else if ((pfe990b == 0) && (gd8574c == 1)) begin ksbce87 <= 1; xwe1637 <= tu5d321 & gd8574c; nef4900 <= {kq7215d, kd4e42b[3:0]}; lfcbcb <= nr642f1 | kq4c85e; nt3d0c3 <= ~al51390; if ({kq7215d, kd4e42b[3:0]} == 8'hd5) begin kde7439 <= 0; end else begin kde7439 <= 1; end end else if ((yx5e3ca == 1) && ({kd4e42b[3:0], gd90ae9} == 8'hd5)) begin ksbce87 <= 0; nef4900 <= {kd4e42b[3:0], gd90ae9}; kde7439 <= 0; end else if ((yx5e3ca == 1) && ({kq7215d, kd4e42b[3:0]} == 8'hd5)) begin ksbce87 <= 1; nef4900 <= {kq7215d, kd4e42b[3:0]}; kde7439 <= 0; end else if (zmbc79 == 0) begin xwe1637 <= gd8574c & pfe990b; nef4900 <= {kd4e42b[3:0], gd90ae9}; lfcbcb <= kq4c85e | uk2178f; if (aa53b == 1) begin uk888e0 <= gd8574c != pfe990b; end end else if (zmbc79 == 1) begin xwe1637 <= tu5d321 & gd8574c; nef4900 <= {kq7215d, kd4e42b[3:0]}; lfcbcb <= nr642f1 | kq4c85e; if (aa53b == 1) begin uk888e0 <= tu5d321 != gd8574c; end end end\r
-end\r
-\r
-\r
-always @(posedge txmac_clk or negedge reset_n) begin if (!reset_n) begin ea430f5 <= 0; mt187a9 <= 0; end else if (txmac_clk_en) begin if (ps6346c) begin ea430f5 <= cb398d1; mt187a9 <= yxcc68d; end else begin ea430f5 <= 0; mt187a9 <= 0; end end\r
-end\r
-\r
-\r
-always @(posedge txmac_clk or negedge reset_n) begin if (!reset_n) begin kdc3d4d <= 1'b0; end else if (txmac_clk_en) begin kdc3d4d <= ps6346c; end\r
-end\r
-\r
-\r
-always @(yx70d37 or jr91c34 or db22470 or qv12386) begin casex({yx70d37, jr91c34}) 2'bx0 : begin txd_pos[7:0] = 0; txd_neg[3:0] = 0; tx_er = 0; tx_en = 0; end 2'b11 : begin txd_pos[7:0] = db22470[7:0]; txd_neg[3:0] = db22470[3:0]; tx_er = qv12386; tx_en = jr91c34; end 2'b01 : begin txd_pos[7:0] = {4'h0, db22470[3:0]}; txd_neg[3:0] = db22470[7:4]; tx_er = qv12386; tx_en = jr91c34; end default : begin txd_pos[7:0] = 0; txd_neg[3:0] = 0; tx_er = 0; tx_en = 0; end endcase\r
-end\r
-always@* begin cb398d1<={ux18d4e>>1,ea5c9d9[0]};yxcc68d<=ea5c9d9[1];ps6346c<=ea5c9d9[2];gq1a362<=ea5c9d9[3];co10e3c<=ea5c9d9[4];uk8d880<=ea5c9d9[5];ne6c401<=ea5c9d9[6];yk6200b<=ea5c9d9[7];aa10058<=ea5c9d9[8];oh802c1<={rxd_pos>>1,ea5c9d9[9]};je160c<={rxd_neg>>1,ea5c9d9[10]};vkb062<=ea5c9d9[11];vi58313<=ea5c9d9[12];cmc189b<=ea5c9d9[13];xlc4d9<=ea5c9d9[14];go626ce<=ea5c9d9[15];ph13670<=ea5c9d9[16];bn9b386<=ea5c9d9[17];wjd9c36<=ea5c9d9[18];goce1b4<=ea5c9d9[19];gb70da1<=ea5c9d9[20];ux3686a<={vk2f2fc>>1,ea5c9d9[21]};gda1aa4<={gocbf12>>1,ea5c9d9[22]};of6a924<={rtfc487>>1,ea5c9d9[23]};wla492c<={qi87d24>>1,ea5c9d9[24]};sw24b20<={nef4900>>1,ea5c9d9[25]};fc25900<=ea5c9d9[26];gd2c802<=ea5c9d9[27];th64014<=ea5c9d9[28];ri200a7<=ea5c9d9[29];aa53b<=ea5c9d9[30];cb29d8<=ea5c9d9[31];ri14ec4<=ea5c9d9[32];pua7622<=ea5c9d9[33];gq3b112<=ea5c9d9[34];fnd8891<=ea5c9d9[35];db22470<={ea430f5>>1,ea5c9d9[36]};qv12386<=ea5c9d9[37];jr91c34<=ea5c9d9[38];fp8e1a6<=ea5c9d9[39];yx70d37<=ea5c9d9[40];ng869bd<=ea5c9d9[41];aa34dea<=ea5c9d9[42];coa6f51<=ea5c9d9[43];nt37a89<=ea5c9d9[44];uiea272<={dmc06d5>>1,ea5c9d9[45]};al51390<=ea5c9d9[46];kd4e42b<={nedaaba>>1,ea5c9d9[47]};kq7215d<={rgd55d3>>1,ea5c9d9[48]};gd90ae9<={vxaae9b>>1,ea5c9d9[49]};gd8574c<=ea5c9d9[50];wy2ba64<=ea5c9d9[51];tu5d321<=ea5c9d9[52];pfe990b<=ea5c9d9[53];kq4c85e<=ea5c9d9[54];nr642f1<=ea5c9d9[55];uk2178f<=ea5c9d9[56];zmbc79<=ea5c9d9[57];yx5e3ca<=ea5c9d9[58];end\r
-always@* begin ec2b93b[2047]<=shc6a74;ec2b93b[2046]<=pu353a4;ec2b93b[2044]<=ls1bc04;ec2b93b[2040]<=rv27d65;ec2b93b[2032]<=rx_dv_pos;ec2b93b[2016]<=rx_dv_neg;ec2b93b[1985]<=rx_er_pos;ec2b93b[1922]<=rx_er_neg;ec2b93b[1867]<=hq1979;ec2b93b[1804]<=nedaaba[0];ec2b93b[1797]<=rxd_pos[0];ec2b93b[1761]<=ps6301b;ec2b93b[1686]<=lfcbcb;ec2b93b[1623]<=hodf5e7;ec2b93b[1561]<=rgd55d3[0];ec2b93b[1558]<=ks70b;ec2b93b[1547]<=rxd_neg[0];ec2b93b[1542]<=ea430f5[0];ec2b93b[1490]<=kf2380c;ec2b93b[1475]<=dmc06d5[0];ec2b93b[1413]<=wy2401c;ec2b93b[1409]<=pua7a18;ec2b93b[1400]<=kde7439;ec2b93b[1324]<=vk2f2fc[0];ec2b93b[1200]<=rtfc487[0];ec2b93b[1199]<=qgfaf3a;ec2b93b[1074]<=vxaae9b[0];ec2b93b[1068]<=rv1c2c6;ec2b93b[1047]<=ui4c131;ec2b93b[1037]<=mt187a9;ec2b93b[1023]<=ux18d4e[0];ec2b93b[933]<=zz1c065;ec2b93b[902]<=bn36aa;ec2b93b[880]<=ps6c603;ec2b93b[811]<=ph9bebc;ec2b93b[779]<=pu200e1;ec2b93b[771]<=nt3d0c3;ec2b93b[745]<=of44701;ec2b93b[706]<=nef4900[0];ec2b93b[704]<=fada9e8;ec2b93b[700]<=ksbce87;ec2b93b[600]<=gocbf12[0];ec2b93b[440]<=rg4d8c0;ec2b93b[405]<=uvd37d7;ec2b93b[372]<=uk888e0;ec2b93b[353]<=qi87d24[0];ec2b93b[352]<=medb53d;ec2b93b[350]<=dzd79d0;ec2b93b[220]<=gqa9b18;ec2b93b[202]<=vxba6fa;ec2b93b[186]<=gq3111c;ec2b93b[176]<=epbb6a7;ec2b93b[110]<=osf5363;ec2b93b[101]<=lq574df;ec2b93b[93]<=tw4c44;ec2b93b[88]<=xwe1637;ec2b93b[55]<=do1ea6c;ec2b93b[46]<=kd60988;ec2b93b[27]<=kdc3d4d;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-`timescale 1 ns / 100 ps\r
-module tsmac35 (\r
-\r
- \r
- hclk,\r
- txmac_clk,\r
- rxmac_clk,\r
- reset_n,\r
-\r
- txmac_clk_en,\r
- rxmac_clk_en,\r
-\r
-\r
- \r
- rxd,\r
- rx_dv,\r
- rx_er,\r
-\r
- col,\r
- crs,\r
-\r
- \r
- haddr,\r
- hdatain,\r
- hcs_n,\r
- hwrite_n,\r
- hread_n,\r
-\r
- \r
-\r
- \r
- tx_fifodata,\r
- tx_fifoavail,\r
- tx_fifoeof,\r
- tx_fifoempty,\r
- tx_sndpaustim,\r
- tx_sndpausreq,\r
- tx_fifoctrl,\r
-\r
- \r
- rx_fifo_full,\r
- ignore_pkt,\r
-\r
- \r
- tx_en,\r
- tx_er,\r
-\r
- txd,\r
-\r
- \r
- hdataout,\r
- hdataout_en_n,\r
- hready_n,\r
- cpu_if_gbit_en,\r
-\r
- \r
-\r
- \r
- tx_macread,\r
- tx_discfrm,\r
- tx_staten,\r
- tx_statvec,\r
- tx_done,\r
-\r
- \r
- rx_fifo_error,\r
- rx_stat_vector,\r
- rx_dbout,\r
- rx_write,\r
- rx_stat_en,\r
- rx_eof,\r
- rx_error\r
-)\r
- \r
- \r
-;\r
-input hclk;\r
-input txmac_clk;\r
-input rxmac_clk;\r
-input reset_n;\r
-\r
-input txmac_clk_en;\r
-input rxmac_clk_en;\r
-\r
-\r
-\r
-input [7:0] rxd;\r
-input rx_dv;\r
-input rx_er;\r
-\r
-\r
-input col;\r
-input crs;\r
-\r
-input [7:0] haddr;\r
-input [7:0] hdatain;\r
-input hcs_n;\r
-input hwrite_n;\r
-input hread_n;\r
-\r
-input [7:0] tx_fifodata;\r
-input tx_fifoavail;\r
-input tx_fifoeof;\r
-input tx_fifoempty;\r
-input [15:0] tx_sndpaustim;\r
-input tx_sndpausreq;\r
-input tx_fifoctrl;\r
-input rx_fifo_full;\r
-input ignore_pkt;\r
-\r
-output [7:0] txd;\r
-\r
-output tx_en;\r
-output tx_er;\r
-output [7:0] hdataout;\r
-output hdataout_en_n;\r
-output hready_n;\r
-output cpu_if_gbit_en;\r
-\r
-output tx_macread;\r
-output tx_discfrm;\r
-output tx_staten;\r
-output tx_done;\r
-output [30:0] tx_statvec;\r
-output rx_fifo_error;\r
-output [31:0] rx_stat_vector;\r
-output [7:0] rx_dbout;\r
-output rx_write;\r
-output rx_stat_en;\r
-output rx_eof;\r
-output rx_error;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-parameter pdevice_family = "ECP3";\r
-\r
-wire [15:0] ls1f5e;\r
-wire oufaf3;\r
-wire me7d798;\r
-wire [8:0] ayc1110;\r
-wire cb8880;\r
-wire [15:0] hbf301c;\r
-wire gq980e7;\r
-wire nec0739;\r
-wire [7:0] db39ca;\r
-wire bn1ce56;\r
-wire wje72b6;\r
-wire mt395b4;\r
-wire vicada4;\r
-wire qg56d22;\r
-wire [4:0] ksb6911;\r
-wire cbb4888;\r
-wire uxa4445;\r
-wire bn2222d;\r
-wire zm1116e;\r
-wire ec88b73;\r
-wire rt45b99;\r
-wire nt2dccf;\r
-wire xj6e67e;\r
-wire xw733f6;\r
-wire [13:0] fc99fb3;\r
-wire [7:0] bycfd9a;\r
-wire [7:0] pf7ecd2;\r
-wire [7:0] vvf6696;\r
-wire [7:0] oub34b7;\r
-wire [7:0] mt9a5b9;\r
-wire [7:0] hbd2dcc;\r
-wire [7:0] ri96e67;\r
-wire [7:0] twb733b;\r
-wire [15:0] ymb99db;\r
-wire [47:0] shcced9;\r
-wire [10:0] ww676cd;\r
-wire [15:0] ks3b668;\r
-wire icdb341;\r
-wire [7:0] ald9a08;\r
-wire pfcd044;\r
-wire ui68226;\r
-wire en41131;\r
-wire ir898c;\r
-wire wj44c65;\r
-wire an2632d;\r
-\r
-wire hd2d85c;\r
-wire zk6c2e6;\r
-wire [7:0] th61733;\r
-wire [3:0] rib99f;\r
-wire kq5ccfa;\r
-wire rte67d0;\r
-wire yz33e86;\r
-wire kf9f434;\r
-wire [7:0] osfa1a4;\r
-wire [3:0] psd0d21;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-reg gq342ac;\r
-reg [7 : 0] cb8ab2f;\r
-reg [7 : 0] ksacbe6;\r
-reg ho7cc23;\r
-reg ba2f984;\r
-reg yx65f30;\r
-reg [7 : 0] je1e93c;\r
-reg thc7892;\r
-reg lqf49e3;\r
-reg oha4f1b;\r
-reg [15 : 0] qtc6532;\r
-reg xj6b194;\r
-reg bn278dc;\r
-reg xw5d016;\r
-reg ou50e2;\r
-reg [15 : 0] hq8672b;\r
-reg kf3395b;\r
-reg ba9cadc;\r
-reg [8 : 0] kqde7a3;\r
-reg rtf3d18;\r
-reg [15 : 0] gb5b888;\r
-reg ofdc445;\r
-reg ale222d;\r
-reg [7 : 0] ri1116c;\r
-reg sw88b63;\r
-reg zx45b19;\r
-reg zz2d8cf;\r
-reg ne6c67e;\r
-reg zk633f3;\r
-reg [4 : 0] lf19f9a;\r
-reg xwcfcd6;\r
-reg jp7e6b2;\r
-reg dzf3597;\r
-reg cb9acbf;\r
-reg ipd65fd;\r
-reg vkb2fec;\r
-reg ks97f62;\r
-reg rvbfb11;\r
-reg kdfd88e;\r
-reg [13 : 0] ldec475;\r
-reg [7 : 0] ic623af;\r
-reg [7 : 0] do11d78;\r
-reg [7 : 0] jr8ebc2;\r
-reg [7 : 0] al75e16;\r
-reg [7 : 0] fpaf0b5;\r
-reg [7 : 0] ic785ae;\r
-reg [7 : 0] rtc2d70;\r
-reg [7 : 0] jr16b86;\r
-reg [15 : 0] jrb5c37;\r
-reg [47 : 0] yzae1bf;\r
-reg [10 : 0] gb70dfc;\r
-reg [15 : 0] zm86fe5;\r
-reg vx37f2a;\r
-reg [7 : 0] ntbf956;\r
-reg fnfcab6;\r
-reg uie55b7;\r
-reg zm2adb9;\r
-reg qg56dcb;\r
-reg ksb6e59;\r
-reg bab72c8;\r
-reg ksb9643;\r
-reg eacb218;\r
-reg [7 : 0] os590c1;\r
-reg [3 : 0] blc8609;\r
-reg me4304e;\r
-reg yz18271;\r
-reg ayc138d;\r
-reg db9c68;\r
-reg [7 : 0] ip4e347;\r
-reg [3 : 0] xj71a3d;\r
-reg [2047:0] ec2b93b;\r
-wire [69:0] ea5c9d9;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-localparam tue4ec8 = 70,ph27642 = 32'hfdffd14b;\r
-localparam [31:0] gq3b216 = ph27642;\r
-localparam zxc858d = ph27642 & 4'hf;\r
-localparam [11:0] fp16372 = 'h7ff;\r
-wire [(1 << zxc858d) -1:0] mg8dcb5;\r
-reg [tue4ec8-1:0] su72d4e;\r
-reg [zxc858d-1:0] phb5383 [0:1];\r
-reg [zxc858d-1:0] en4e0f0;\r
-reg qt70785;\r
-integer xy83c2c;\r
-integer do1e162;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- assign hd2d85c = txmac_clk_en; assign zk6c2e6 = rxmac_clk_en;\r
-\r
-\r
-\r
-\r
-\r
- assign th61733 = rxd; assign rib99f = 4'h0; assign kq5ccfa = rx_dv; assign rte67d0 = 1'b0; assign yz33e86 = rx_er; assign kf9f434 = 1'b0; assign txd = ip4e347;\r
-\r
-\r
-\r
-\r
-\r
-xlbf10b #(.pdevice_family(pdevice_family))\r
-psf12d8 ( .rxmac_clk(rxmac_clk), .reset_n(gq342ac), .rxmac_clk_en(eacb218), .mtbb27f(zm2adb9), .ou1a400(do3fb01), .ald93fd(ntbf956), .xjd2000(uie55b7), .mt90006(fnfcab6), .gd80035(qg56dcb), .en41ecd(ic623af), .ksf66d(do11d78), .nr7b369(jr8ebc2), .ipd9b4f(al75e16), .blcda7c(fpaf0b5), .qg6d3e7(ic785ae), .xw69f39(rtc2d70), .zx4f9ca(jr16b86), .xw7ce56(yzae1bf), .kde72b3(cb9acbf), .ux3959c(ipd65fd), .hocace4(ks97f62), .fc30be7(jrb5c37), .mt1d13e(rvbfb11), .kde89f5(vkb2fec), .yx44fac(ldec475), .rv27d65(kdfd88e), .aa3eb2f(dzf3597), .cmf5978(jp7e6b2), .rx_fifo_full(xw5d016), .ignore_pkt(ou50e2), .qg78222(me7d798), .lq4d15b(ls1f5e), .os68ada(oufaf3), .ayc1110(ayc1110), .cb8880(cb8880), .zmad152(hbf301c), .ou10166(gq980e7), .rx_fifo_error(rx_fifo_error), .rx_stat_vector(rx_stat_vector), .rx_dbout(rx_dbout), .rx_write(rx_write), .rx_stat_en(rx_stat_en), .rx_eof(rx_eof), .rx_error(rx_error)\r
-);\r
-icfab90 #(.pdevice_family(pdevice_family))\r
-vv5fd6e ( .txmac_clk(txmac_clk), .baa7b6d(gq342ac), .txmac_clk_en(ksb9643), .lqf1bfb(zz2d8cf), .mg8dfdb(ne6c67e), .qt7f6cd(zk633f3), .cz6fed9(xwcfcd6), .uxa1b23(lf19f9a), .wld91c(yzae1bf), .dzcdac4(jrb5c37), .tx_fifodata(je1e93c), .tx_fifoeof(lqf49e3), .tx_fifoempty(oha4f1b), .tx_fifoavail(thc7892), .tx_sndpaustim(qtc6532), .tx_sndpausreq(xj6b194), .tx_fifoctrl(bn278dc), .psee2db(ofdc445), .nr716da(gb5b888), .uidb36b(bab72c8), .fafb66d(ksb6e59), .aydb5bc(wje72b6), .tx_macread(tx_macread), .tx_discfrm(tx_discfrm), .tx_staten(tx_staten), .tx_statvec(tx_statvec), .tx_done(tx_done), .ui782b2(nec0739), .goc1590(db39ca), .wyac80(bn1ce56) \r
-);\r
- pu96d5c pfd21ab ( .txmac_clk(txmac_clk), .rxmac_clk(rxmac_clk), .reset_n(gq342ac), .rxmac_clk_en(eacb218), .txmac_clk_en(ksb9643), .ux18d4e(ri1116c), .shc6a74(sw88b63), .pu353a4(ale222d), .rx_dv_pos(me4304e), .rx_dv_neg(yz18271), .rx_er_pos(ayc138d), .rx_er_neg(db9c68), .rxd_pos(os590c1), .rxd_neg(blc8609),\r
-\r
-\r
- .col(col), .crs(crs),\r
-\r
-\r
-\r
- .ls1bc04(cpu_if_gbit_en), .rv27d65(kdfd88e), .mt90006(pfcd044), .xjd2000(ui68226), .mtbb27f(en41131), .ou1a400(do3fb01), .ald93fd(ald9a08), .gd80035(ir898c), .tj84f70(wj44c65), .db27b87(an2632d), .txd_pos(osfa1a4), .txd_neg(psd0d21), .tx_en(tx_en), .tx_er(tx_er) );\r
-\r
-pf4a32c ohb1f76 ( .hclk(hclk), .reset_n(gq342ac), .haddr(cb8ab2f), .hdatain(ksacbe6), .hread_n(yx65f30), .hwrite_n(ba2f984), .hcs_n(ho7cc23), .lq4d15b(hq8672b), .os68ada(kf3395b), .qg78222(ba9cadc), .ayc1110(kqde7a3), .cb8880(rtf3d18), .ie552b(zx45b19), \r
-\r
-\r
-\r
- .hdataout(hdataout), .hready_n(hready_n), .hdataout_en_n(hdataout_en_n), .tx_en(mt395b4), .go67cc7(vicada4), .qi3e639(qg56d22), .uxa1b23(ksb6911), .ls1bc04(cpu_if_gbit_en), .cz6fed9(cbb4888),\r
- \r
-\r
-\r
-\r
- .cmf5978(uxa4445), .aa3eb2f(bn2222d), .wl23780(shcced9), .qv393c7(zm1116e), .ux3959c(ec88b73), .kde89f5(rt45b99), .hocace4(nt2dccf), .mt1d13e(xj6e67e), .yx44fac(fc99fb3), .rv27d65(xw733f6), .fc30be7(ymb99db), .qg78f2f(bycfd9a), .hbc7979(pf7ecd2), .gd3cbce(vvf6696), .cme5e75(oub34b7), .hq2f3a8(mt9a5b9), .zk79d42(hbd2dcc), .ykcea13(ri96e67), .qt75098(twb733b)\r
-);\r
-\r
-\r
-\r
-always@* begin gq342ac<=ea5c9d9[0];cb8ab2f<={haddr>>1,ea5c9d9[1]};ksacbe6<={hdatain>>1,ea5c9d9[2]};ho7cc23<=ea5c9d9[3];ba2f984<=ea5c9d9[4];yx65f30<=ea5c9d9[5];je1e93c<={tx_fifodata>>1,ea5c9d9[6]};thc7892<=ea5c9d9[7];lqf49e3<=ea5c9d9[8];oha4f1b<=ea5c9d9[9];qtc6532<={tx_sndpaustim>>1,ea5c9d9[10]};xj6b194<=ea5c9d9[11];bn278dc<=ea5c9d9[12];xw5d016<=ea5c9d9[13];ou50e2<=ea5c9d9[14];hq8672b<={ls1f5e>>1,ea5c9d9[15]};kf3395b<=ea5c9d9[16];ba9cadc<=ea5c9d9[17];kqde7a3<={ayc1110>>1,ea5c9d9[18]};rtf3d18<=ea5c9d9[19];gb5b888<={hbf301c>>1,ea5c9d9[20]};ofdc445<=ea5c9d9[21];ale222d<=ea5c9d9[22];ri1116c<={db39ca>>1,ea5c9d9[23]};sw88b63<=ea5c9d9[24];zx45b19<=ea5c9d9[25];zz2d8cf<=ea5c9d9[26];ne6c67e<=ea5c9d9[27];zk633f3<=ea5c9d9[28];lf19f9a<={ksb6911>>1,ea5c9d9[29]};xwcfcd6<=ea5c9d9[30];jp7e6b2<=ea5c9d9[31];dzf3597<=ea5c9d9[32];cb9acbf<=ea5c9d9[33];ipd65fd<=ea5c9d9[34];vkb2fec<=ea5c9d9[35];ks97f62<=ea5c9d9[36];rvbfb11<=ea5c9d9[37];kdfd88e<=ea5c9d9[38];ldec475<={fc99fb3>>1,ea5c9d9[39]};ic623af<={bycfd9a>>1,ea5c9d9[40]};do11d78<={pf7ecd2>>1,ea5c9d9[41]};jr8ebc2<={vvf6696>>1,ea5c9d9[42]};al75e16<={oub34b7>>1,ea5c9d9[43]};fpaf0b5<={mt9a5b9>>1,ea5c9d9[44]};ic785ae<={hbd2dcc>>1,ea5c9d9[45]};rtc2d70<={ri96e67>>1,ea5c9d9[46]};jr16b86<={twb733b>>1,ea5c9d9[47]};jrb5c37<={ymb99db>>1,ea5c9d9[48]};yzae1bf<={shcced9>>1,ea5c9d9[49]};gb70dfc<={ww676cd>>1,ea5c9d9[50]};zm86fe5<={ks3b668>>1,ea5c9d9[51]};vx37f2a<=ea5c9d9[52];ntbf956<={ald9a08>>1,ea5c9d9[53]};fnfcab6<=ea5c9d9[54];uie55b7<=ea5c9d9[55];zm2adb9<=ea5c9d9[56];qg56dcb<=ea5c9d9[57];ksb6e59<=ea5c9d9[58];bab72c8<=ea5c9d9[59];ksb9643<=ea5c9d9[60];eacb218<=ea5c9d9[61];os590c1<={th61733>>1,ea5c9d9[62]};blc8609<={rib99f>>1,ea5c9d9[63]};me4304e<=ea5c9d9[64];yz18271<=ea5c9d9[65];ayc138d<=ea5c9d9[66];db9c68<=ea5c9d9[67];ip4e347<={osfa1a4>>1,ea5c9d9[68]};xj71a3d<={psd0d21>>1,ea5c9d9[69]};end\r
-always@* begin ec2b93b[2047]<=haddr[0];ec2b93b[2046]<=hdatain[0];ec2b93b[2044]<=hcs_n;ec2b93b[2040]<=hwrite_n;ec2b93b[2033]<=hread_n;ec2b93b[2019]<=tx_fifodata[0];ec2b93b[1994]<=vvf6696[0];ec2b93b[1990]<=tx_fifoavail;ec2b93b[1981]<=vicada4;ec2b93b[1965]<=bn2222d;ec2b93b[1940]<=oub34b7[0];ec2b93b[1939]<=ayc1110[0];ec2b93b[1933]<=tx_fifoeof;ec2b93b[1914]<=qg56d22;ec2b93b[1883]<=zm1116e;ec2b93b[1832]<=mt9a5b9[0];ec2b93b[1831]<=cb8880;ec2b93b[1819]<=tx_fifoempty;ec2b93b[1785]<=fc99fb3[0];ec2b93b[1781]<=ksb6911[0];ec2b93b[1778]<=ls1f5e[0];ec2b93b[1740]<=ir898c;ec2b93b[1719]<=ec88b73;ec2b93b[1634]<=hd2d85c;ec2b93b[1616]<=hbd2dcc[0];ec2b93b[1615]<=hbf301c[0];ec2b93b[1591]<=tx_sndpaustim[0];ec2b93b[1579]<=kq5ccfa;ec2b93b[1522]<=bycfd9a[0];ec2b93b[1515]<=cbb4888;ec2b93b[1508]<=oufaf3;ec2b93b[1470]<=xj6e67e;ec2b93b[1432]<=wj44c65;ec2b93b[1406]<=psd0d21[0];ec2b93b[1391]<=rt45b99;ec2b93b[1286]<=shcced9[0];ec2b93b[1271]<=bn1ce56;ec2b93b[1221]<=zk6c2e6;ec2b93b[1184]<=ri96e67[0];ec2b93b[1182]<=gq980e7;ec2b93b[1135]<=tx_sndpausreq;ec2b93b[1111]<=rte67d0;ec2b93b[1051]<=ks3b668[0];ec2b93b[1023]<=reset_n;ec2b93b[997]<=pf7ecd2[0];ec2b93b[990]<=mt395b4;ec2b93b[982]<=uxa4445;ec2b93b[969]<=me7d798;ec2b93b[892]<=xw733f6;ec2b93b[889]<=ignore_pkt;ec2b93b[870]<=en41131;ec2b93b[817]<=an2632d;ec2b93b[789]<=rib99f[0];ec2b93b[735]<=nt2dccf;ec2b93b[703]<=osfa1a4[0];ec2b93b[643]<=ymb99db[0];ec2b93b[635]<=db39ca[0];ec2b93b[525]<=ww676cd[0];ec2b93b[495]<=wje72b6;ec2b93b[444]<=rx_fifo_full;ec2b93b[435]<=ui68226;ec2b93b[394]<=th61733[0];ec2b93b[351]<=kf9f434;ec2b93b[321]<=twb733b[0];ec2b93b[317]<=nec0739;ec2b93b[222]<=tx_fifoctrl;ec2b93b[217]<=pfcd044;ec2b93b[175]<=yz33e86;ec2b93b[108]<=ald9a08[0];ec2b93b[54]<=icdb341;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162<tue4ec8; do1e162=do1e162+1) begin su72d4e[do1e162] = mg8dcb5[en4e0f0]; qt70785 = ^(en4e0f0 & phb5383[0]); en4e0f0 = {en4e0f0, qt70785}; end end \r
-endmodule\r
-\r
+++ /dev/null
-=============================================================================
-Filelist generated by IPexpress 06/19/2012 09:58:40
-Filename: tsmac35_filelist.log
-Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-=============================================================================
-
------------------------------------------------------------------------------
-Basic IP Core Files
-Output Directory: /home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35
------------------------------------------------------------------------------
- tsmac35.lpc
- : IP ispLEVER LPC File
- tsmac35.ngo
- : IP ispLEVER Database File
- tsmac35_bb.v
- : IP Verilog Blackbox Module
- tsmac35_inst.v
- : IP Verilog Instantiation Template
- tsmac35_beh.v
- : IP Verilog Behaviorial Sim Model
- tsmac35_gen.log
- : IP Status Log
- tsmac35_generate.log
- : IP Generate Log
-
------------------------------------------------------------------------------
-Supplemental Implementation and Simulation Files:
-
-Testbench files common to all Tri-Speed MAC configurations
- ../ts_mac_eval/testbench/top
- ../ts_mac_eval/testbench/tests
-
-Models common to all Tri-Speed MAC configurations
- ../ts_mac_eval/models/ecp3
-
-Evaluation source files specific to tsmac35 configuration
- ../ts_mac_eval/tsmac35/src/rtl/top
- ../ts_mac_eval/tsmac35/src/rtl/templates
- ../ts_mac_eval/tsmac35/src/params
-
-Simulation files specific to tsmac35 configuration
- ../ts_mac_eval/tsmac35/sim/modelsim
-
-Implementation files specific to tsmac35 configuration
- ../ts_mac_eval/tsmac35/impl/synplify
-
+++ /dev/null
-Parameters loaded ok.
-No optional files required.
-Parameter values ok.
-Project Directory succussfully created.
-Simulation model successfully created.
-IP template generation completed ok.
-LPF generation completed ok.
-ModelSim do file successfully created.
-IP core generation completed ok.
-Generation completed ok.
+++ /dev/null
-Starting process: IPCFG
-
-GenerateCore within package Core_Generate 1.0.0 in file LatticeIP_generate.tcl
-Starting process: '"/opt/lattice/diamond/1.4.2.105/bin/lin/synpwrap" -rem -e tsmac35 -target lattice-ecp3'
-
-Warning: You are running on an unsupported platform
-End process: completed successfully.
-
-Starting process: '"/opt/lattice/diamond/1.4.2.105/bin/lin/../../ispfpga/bin/lin/edif2ngd" -ip "/home/greg/trispeed_mac_v3.5/lib/../.." -ic trispeed_mac_v3.5 -l LatticeECP3 -nopropwarn "tsmac35.edi" "tsmac35.ngo"'
-edif2ngd: version Diamond_1.4_Production (87)
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
- Copyright (c) 1995 AT&T Corp. All rights reserved.
- Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
- Copyright (c) 2001 Agere Systems All rights reserved.
- Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-No device specified. Will use default.
-Writing the design to tsmac35.ngo...
-Generating edif netlist for IP cell pmi_ram_dpEbnonessdn96649664.edn
-SCUBA, Version Diamond_1.4_Production (87)
-Tue Jun 19 09:58:39 2012
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -data_width 9 -num_rows 64 -rdata_width 9 -gsr DISABLED -sync_reset -memformat bin -cascade -1 -n pmi_ram_dpEbnonessdn96649664 -pmi
- Circuit name : pmi_ram_dpEbnonessdn96649664
- Module type : RAM_DP
- Module Version : 6.1
- Ports :
- Inputs : WrAddress[5:0], RdAddress[5:0], Data[8:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
- Outputs : Q[8:0]
- I/O buffer : not inserted
- EDIF output : pmi_ram_dpEbnonessdn96649664.edn
- Bus notation : big endian
- Report output : pmi_ram_dpEbnonessdn96649664.srp
- Estimated Resource Usage:
- EBR : 1
-
-END SCUBA Module Synthesis
-Writing the design to pmi_ram_dpEbnonessdn96649664.ngo...
-Generating edif netlist for IP cell pmi_ram_dpEbnonessdn208256208256.edn
-SCUBA, Version Diamond_1.4_Production (87)
-Tue Jun 19 09:58:40 2012
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -data_width 20 -num_rows 256 -rdata_width 20 -gsr DISABLED -sync_reset -memformat bin -cascade -1 -n pmi_ram_dpEbnonessdn208256208256 -pmi
- Circuit name : pmi_ram_dpEbnonessdn208256208256
- Module type : RAM_DP
- Module Version : 6.1
- Ports :
- Inputs : WrAddress[7:0], RdAddress[7:0], Data[19:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
- Outputs : Q[19:0]
- I/O buffer : not inserted
- EDIF output : pmi_ram_dpEbnonessdn208256208256.edn
- Bus notation : big endian
- Report output : pmi_ram_dpEbnonessdn208256208256.srp
- Estimated Resource Usage:
- EBR : 1
-
-END SCUBA Module Synthesis
-Writing the design to pmi_ram_dpEbnonessdn208256208256.ngo...
-End process: completed successfully.
-
-=============================================================================
-Filelist generated by IPexpress 06/19/2012 09:58:40
-Filename: tsmac35_filelist.log
-Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
-=============================================================================
------------------------------------------------------------------------------
-Basic IP Core Files
-Output Directory: /home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35
------------------------------------------------------------------------------
- tsmac35.lpc
- : IP ispLEVER LPC File
- tsmac35.ngo
- : IP ispLEVER Database File
- tsmac35_bb.v
- : IP Verilog Blackbox Module
- tsmac35_inst.v
- : IP Verilog Instantiation Template
- tsmac35_beh.v
- : IP Verilog Behaviorial Sim Model
- tsmac35_gen.log
- : IP Status Log
- tsmac35_generate.log
- : IP Generate Log
------------------------------------------------------------------------------
-Supplemental Implementation and Simulation Files:
-
-Testbench files common to all Tri-Speed MAC configurations
- ../ts_mac_eval/testbench/top
- ../ts_mac_eval/testbench/tests
-
-Models common to all Tri-Speed MAC configurations
- ../ts_mac_eval/models/ecp3
-
-Evaluation source files specific to tsmac35 configuration
- ../ts_mac_eval/tsmac35/src/rtl/top
- ../ts_mac_eval/tsmac35/src/rtl/templates
- ../ts_mac_eval/tsmac35/src/params
-
-Simulation files specific to tsmac35 configuration
- ../ts_mac_eval/tsmac35/sim/modelsim
-
-Implementation files specific to tsmac35 configuration
- ../ts_mac_eval/tsmac35/impl/synplify
-
-Total Warnings: 1
-
-
-Total Errors: 0
-
-
-
+++ /dev/null
-//=============================================================================\r
-// Verilog module generated by IPExpress \r
-// Filename: USERNAME_inst.v \r
-// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. \r
-//=============================================================================\r
-\r
-/* WARNING - Changes to this file should be performed by re-running IPexpress\r
-or modifying the .LPC file and regenerating the core. Other changes may lead\r
-to inconsistent simulation and/or implemenation results */\r
- tsmac35 DUT_INST ( \r
-\r
- // clock and reset\r
- .hclk(hclk),\r
- .txmac_clk(txmac_clk),\r
- .rxmac_clk(rxmac_clk),\r
- .reset_n(reset_n),\r
- .txmac_clk_en(txmac_clk_en),\r
- .rxmac_clk_en(rxmac_clk_en),\r
- \r
- // Input signals to the GMII\r
- .rxd(rxd),\r
- .rx_dv(rx_dv),\r
- .rx_er(rx_er),\r
- .col(col),\r
- .crs(crs),\r
- \r
- // Input signals to the CPU Interface\r
- .haddr(haddr),\r
- .hdatain(hdatain),\r
- .hcs_n(hcs_n),\r
- .hwrite_n(hwrite_n),\r
- .hread_n(hread_n),\r
- \r
- // Input signals to the MII Management Interface\r
- \r
- // Input signals to the Tx MAC FIFO Interface\r
- .tx_fifodata(tx_fifodata),\r
- .tx_fifoavail(tx_fifoavail),\r
- .tx_fifoeof(tx_fifoeof),\r
- .tx_fifoempty(tx_fifoempty),\r
- .tx_sndpaustim(tx_sndpaustim),\r
- .tx_sndpausreq(tx_sndpausreq),\r
- .tx_fifoctrl(tx_fifoctrl),\r
- \r
- // Input signals to the Rx MAC FIFO Interface\r
- .rx_fifo_full(rx_fifo_full),\r
- .ignore_pkt(ignore_pkt),\r
- \r
- // Output signals from the GMII\r
- .txd(txd),\r
- .tx_en(tx_en),\r
- .tx_er(tx_er),\r
- \r
- // Output signals from the CPU Interface\r
- .hdataout(hdataout),\r
- .hdataout_en_n(hdataout_en_n),\r
- .hready_n(hready_n),\r
- .cpu_if_gbit_en(cpu_if_gbit_en),\r
- \r
- // Output signals from the MII Management Interface\r
- \r
- // Output signals from the Tx MAC FIFO Interface\r
- .tx_macread(tx_macread),\r
- .tx_discfrm(tx_discfrm),\r
- .tx_staten(tx_staten),\r
- .tx_statvec(tx_statvec),\r
- .tx_done(tx_done),\r
- \r
- // Output signals from the Rx MAC FIFO Interface\r
- .rx_fifo_error(rx_fifo_error),\r
- .rx_stat_vector(rx_stat_vector),\r
- .rx_dbout(rx_dbout),\r
- .rx_write(rx_write),\r
- .rx_stat_en(rx_stat_en),\r
- .rx_eof(rx_eof),\r
- .rx_error(rx_error)\r
- );\r
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-use IEEE.std_logic_arith.all;\r
-\r
-library work;\r
---use work.trb_net_std.all;\r
---use work.trb_net_components.all;\r
---use work.trb_net16_hub_func.all;\r
-\r
-entity mb_mac_sim is\r
-port (\r
- --------------------------------------------------------------------------\r
- --------------- clock, reset, clock enable -------------------------------\r
- HCLK : in std_logic;\r
- TX_MAC_CLK : in std_logic;\r
- RX_MAC_CLK : in std_logic;\r
- RESET_N : in std_logic;\r
- TXMAC_CLK_EN : in std_logic;\r
- RXMAC_CLK_EN : in std_logic;\r
- --------------------------------------------------------------------------\r
- --------------- SGMII receive interface ----------------------------------\r
- RXD : in std_logic_vector(7 downto 0);\r
- RX_DV : in std_logic;\r
- RX_ER : in std_logic;\r
- COL : in std_logic;\r
- CRS : in std_logic;\r
- --------------------------------------------------------------------------\r
- --------------- SGMII transmit interface ---------------------------------\r
- TXD : out std_logic_vector(7 downto 0);\r
- TX_EN : out std_logic;\r
- TX_ER : out std_logic;\r
- --------------------------------------------------------------------------\r
- --------------- CPU configuration interface ------------------------------\r
- HADDR : in std_logic_vector(7 downto 0);\r
- HDATAIN : in std_logic_vector(7 downto 0);\r
- HCS_N : in std_logic;\r
- HWRITE_N : in std_logic;\r
- HREAD_N : in std_logic;\r
- HDATAOUT : out std_logic_vector(7 downto 0);\r
- HDATAOUT_EN_N : out std_logic;\r
- HREADY_N : out std_logic;\r
- CPU_IF_GBIT_EN : out std_logic;\r
- --------------------------------------------------------------------------\r
- --------------- Transmit FIFO interface ----------------------------------\r
- TX_FIFODATA : in std_logic_vector(7 downto 0);\r
- TX_FIFOAVAIL : in std_logic;\r
- TX_FIFOEOF : in std_logic;\r
- TX_FIFOEMPTY : in std_logic;\r
- TX_MACREAD : out std_logic;\r
- TX_DONE : out std_logic;\r
- TX_SNDPAUSTIM : in std_logic_vector(15 downto 0);\r
- TX_SNDPAUSREQ : in std_logic;\r
- TX_FIFOCTRL : in std_logic;\r
- TX_DISCFRM : out std_logic;\r
- TX_STATEN : out std_logic;\r
- TX_STATVEC : out std_logic_vector(30 downto 0);\r
- --------------------------------------------------------------------------\r
- --------------- Receive FIFO interface -----------------------------------\r
- RX_DBOUT : out std_logic_vector(7 downto 0);\r
- RX_FIFO_FULL : in std_logic;\r
- IGNORE_PKT : in std_logic; \r
- RX_FIFO_ERROR : out std_logic;\r
- RX_STAT_VECTOR : out std_logic_vector(31 downto 0);\r
- RX_STAT_EN : out std_logic;\r
- RX_WRITE : out std_logic;\r
- RX_EOF : out std_logic;\r
- RX_ERROR : out std_logic\r
-);\r
-end mb_mac_sim;\r
-\r
-architecture mb_mac_sim of mb_mac_sim is\r
-\r
-\r
--- CPU interface stuff\r
-type HC_STATES is (HC_SLEEP, HC_READ, HC_WRITE, HC_RACK, HC_WACK);\r
-signal HC_CURRENT_STATE, HC_NEXT_STATE: HC_STATES;\r
-\r
-signal hready_n_comb : std_logic;\r
-signal hready_n_buf : std_logic;\r
-signal hdataout_en_n_comb : std_logic;\r
-signal hdataout_en_n_buf : std_logic;\r
-\r
--- TX stuff\r
-type TX_STATES is (TX_SLEEP, TX_READ, TX_DELAY, TX_TRANS, TX_CHECK);\r
-signal TX_CURRENT_STATE, TX_NEXT_STATE: TX_STATES;\r
-\r
-signal tx_bsm : std_logic_vector(3 downto 0);\r
-signal tx_macread_comb : std_logic;\r
-signal tx_done_comb : std_logic;\r
-signal tx_done_buf : std_logic;\r
-\r
-signal preread_ctr : std_logic_vector(3 downto 0); -- preread counter for TX\r
-signal preread_ce_comb : std_logic;\r
-signal preread_rst_comb : std_logic;\r
-signal preread_done_comb : std_logic;\r
-signal read_on_comb : std_logic;\r
-\r
-\r
-begin\r
-\r
-------------------------------------------------------------------------------\r
--- state machine for configuration interface\r
-------------------------------------------------------------------------------\r
--- BUG: no register simulated here!\r
-\r
--- state registers\r
-HC_STATE_MEM: process( HCLK ) \r
-begin\r
- if ( RESET_N = '0' ) then\r
- HC_CURRENT_STATE <= HC_SLEEP;\r
- hready_n_buf <= '1';\r
- hdataout_en_n_buf <= '1';\r
- elsif( rising_edge(HCLK) ) then\r
- HC_CURRENT_STATE <= HC_NEXT_STATE;\r
- hready_n_buf <= hready_n_comb;\r
- hdataout_en_n_buf <= hdataout_en_n_comb;\r
- end if;\r
-end process HC_STATE_MEM;\r
-\r
--- state transitions\r
-HC_STATE_TRANSFORM: process( HC_CURRENT_STATE, HCS_N, HREAD_N, HWRITE_N )\r
-begin\r
- HC_NEXT_STATE <= HC_SLEEP; -- avoid latches\r
- hready_n_comb <= '1';\r
- hdataout_en_n_comb <= '1';\r
- case HC_CURRENT_STATE is\r
- when HC_SLEEP => if ( (HCS_N = '0') and (HREAD_N = '0') ) then\r
- HC_NEXT_STATE <= HC_READ;\r
- elsif( (HCS_N = '0') and (HWRITE_N = '0') ) then\r
- HC_NEXT_STATE <= HC_WRITE;\r
- else\r
- HC_NEXT_STATE <= HC_SLEEP;\r
- end if;\r
- when HC_READ => HC_NEXT_STATE <= HC_RACK;\r
- hdataout_en_n_comb <= '0';\r
- hready_n_comb <= '0';\r
- when HC_RACK => HC_NEXT_STATE <= HC_SLEEP;\r
- when HC_WRITE => HC_NEXT_STATE <= HC_WACK;\r
- hready_n_comb <= '0';\r
- when HC_WACK => HC_NEXT_STATE <= HC_SLEEP;\r
- when others => HC_NEXT_STATE <= HC_SLEEP;\r
- end case;\r
-end process HC_STATE_TRANSFORM; \r
-\r
-HREADY_N <= hready_n_buf;\r
-HDATAOUT_EN_N <= hdataout_en_n_buf;\r
-\r
-------------------------------------------------------------------------------\r
--- state machine for "transmission"\r
-------------------------------------------------------------------------------\r
-\r
--- preread counter\r
-THE_PREREAD_CTR: process( TX_MAC_CLK )\r
-begin\r
- if ( RESET_N = '0' ) then\r
- preread_ctr <= (others => '0');\r
- elsif( rising_edge(TX_MAC_CLK) ) then\r
- if ( preread_rst_comb = '1' ) then\r
- preread_ctr <= (others => '0');\r
- elsif( preread_ce_comb = '1' ) then\r
- preread_ctr <= preread_ctr + 1; \r
- end if;\r
- end if; \r
-end process THE_PREREAD_CTR;\r
-preread_done_comb <= '1' when (preread_ctr = x"6") \r
- else '0';\r
-\r
--- state registers\r
-TX_STATE_MEM: process( TX_MAC_CLK, RESET_N ) \r
-begin\r
- if ( RESET_N = '0' ) then\r
- TX_CURRENT_STATE <= TX_SLEEP;\r
- tx_done_buf <= '0';\r
- elsif( rising_edge(TX_MAC_CLK) ) then\r
- TX_CURRENT_STATE <= TX_NEXT_STATE;\r
- tx_done_buf <= tx_done_comb;\r
- end if;\r
-end process TX_STATE_MEM;\r
-\r
-tx_macread_comb <= preread_ce_comb or read_on_comb;\r
-\r
--- state transitions\r
-TX_STATE_TRANSFORM: process( TX_CURRENT_STATE, TX_FIFOEMPTY, TX_FIFOAVAIL, TX_FIFOEOF, preread_done_comb )\r
-begin\r
- TX_NEXT_STATE <= TX_SLEEP; -- avoid latches\r
- preread_ce_comb <= '0';\r
- preread_rst_comb <= '0';\r
- read_on_comb <= '0';\r
- tx_done_comb <= '0';\r
- case TX_CURRENT_STATE is\r
- when TX_SLEEP => tx_bsm <= x"0";\r
- if( TX_FIFOEMPTY = '0' ) then\r
- TX_NEXT_STATE <= TX_READ;\r
- preread_ce_comb <= '1';\r
- else\r
- TX_NEXT_STATE <= TX_SLEEP;\r
- end if;\r
- when TX_READ => tx_bsm <= x"1";\r
- if ( TX_FIFOEMPTY = '1' ) then\r
- TX_NEXT_STATE <= TX_DELAY;\r
- preread_rst_comb <= '1';\r
- elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '0') ) then\r
- TX_NEXT_STATE <= TX_DELAY;\r
- preread_rst_comb <= '1';\r
- elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '1') ) then\r
- TX_NEXT_STATE <= TX_TRANS;\r
- preread_rst_comb <= '1';\r
- read_on_comb <= '1';\r
- else\r
- TX_NEXT_STATE <= TX_READ;\r
- preread_ce_comb <= '1';\r
- end if;\r
- when TX_DELAY => tx_bsm <= x"2";\r
- if( TX_FIFOAVAIL = '1' ) then\r
- TX_NEXT_STATE <= TX_TRANS;\r
- read_on_comb <= '1';\r
- else\r
- TX_NEXT_STATE <= TX_DELAY;\r
- end if;\r
- when TX_TRANS => tx_bsm <= x"3";\r
- if( TX_FIFOEOF = '1' ) then\r
- TX_NEXT_STATE <= TX_CHECK;\r
- tx_done_comb <= '1'; -- don't know if this is realistic\r
- else\r
- TX_NEXT_STATE <= TX_TRANS;\r
- read_on_comb <= '1';\r
- end if;\r
- when TX_CHECK => tx_bsm <= x"4";\r
- if( (TX_FIFOEMPTY = '0') and (TX_FIFOAVAIL = '1') ) then\r
- TX_NEXT_STATE <= TX_READ;\r
- preread_ce_comb <= '1';\r
- else\r
- TX_NEXT_STATE <= TX_SLEEP;\r
- end if;\r
- when others => tx_bsm <= x"f";\r
- TX_NEXT_STATE <= TX_SLEEP;\r
- end case;\r
-end process TX_STATE_TRANSFORM;\r
-\r
-\r
-\r
-\r
-------------------------------------------------------------------------------\r
--- Fake signals\r
-------------------------------------------------------------------------------\r
-RX_DBOUT <= preread_ctr & tx_bsm; -- x"00";\r
-RX_FIFO_ERROR <= '0';\r
-RX_STAT_VECTOR <= x"0000_0000";\r
-RX_STAT_EN <= '0';\r
-RX_WRITE <= '0';\r
-RX_EOF <= '0';\r
-RX_ERROR <= '0';\r
-\r
-TX_DISCFRM <= '0';\r
-TX_EN <= '0';\r
-TX_ER <= '0';\r
-TX_STATVEC <= (others => '0');\r
-TX_STATEN <= '0';\r
-TXD <= x"00";\r
-\r
-CPU_IF_GBIT_EN <= '0';\r
-\r
-TX_DONE <= tx_done_buf;\r
-TX_MACREAD <= tx_macread_comb;\r
-\r
-HDATAOUT <= x"00";\r
-\r
-\r
-end mb_mac_sim;\r
-\r
-\r
---port map(\r
--- --------------------------------------------------------------------------\r
--- --------------- clock, reset, clock enable -------------------------------\r
--- hclk => CLK, -- (in) host clock (100MHz)\r
--- txmac_clk => TX_MAC_CLK, -- (in) GbE clock (125MHz)\r
--- rxmac_clk => '0', -- (in) not used (no receiving on GbE)\r
--- reset_n => GSR_N, -- (in) global set/reset\r
--- txmac_clk_en => TSM_TX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation\r
--- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation\r
--- --------------------------------------------------------------------------\r
--- --------------- SGMII receive interface ----------------------------------\r
--- rxd => x"00", -- (in) receive data from SGMII core\r
--- rx_dv => '0', -- (in) data valid from SGMII core\r
--- rx_er => '0', -- (in) receive data error \r
--- col => TSM_COL_IN, -- (in) collision from SGMII core\r
--- crs => TSM_CRS_IN, -- (in) carrier sense from SGMII core\r
--- --------------------------------------------------------------------------\r
--- --------------- SGMII transmit interface ---------------------------------\r
--- txd => CH_TXD_OUT, -- (out) transmit data to SGMII core\r
--- tx_en => CH_TX_EN_OUT, -- (out) transmit enable\r
--- tx_er => CH_TX_ER_OUT, -- (out) transmit error\r
--- --------------------------------------------------------------------------\r
--- --------------- CPU configuration interface ------------------------------\r
--- haddr => haddr, -- (in) host address bus for configuration\r
--- hdatain => hdataout, -- (in) host data bus for write accesses\r
--- hcs_n => hcs, -- (in) host chip select signal\r
--- hwrite_n => hwrite, -- (in) host write strobe signal\r
--- hread_n => hread, -- (in) host read strobe signal\r
--- hdataout => hdatain, -- (out) host data bus for read accesses\r
--- hdataout_en_n => hdataout_en, -- (out) read data valid signal\r
--- hready_n => hready, -- (out) data acknowledge signal \r
--- cpu_if_gbit_en => open, -- (out) status bit \r
--- --------------------------------------------------------------------------\r
--- --------------- Transmit FIFO interface ----------------------------------\r
--- tx_fifodata => ft_data(7 downto 0), -- (in) transmit FIFO data bus\r
--- tx_fifoavail => mac_fifoavail, -- (in) transmit FIFO data available\r
--- tx_fifoeof => mac_fifoeof, -- (in) transmit FIFO end of frame \r
--- tx_fifoempty => mac_fifoempty, -- (in) transmit FIFO empty\r
--- tx_macread => mac_tx_rd_en, -- (out) transmit FIFO read\r
--- tx_done => mac_tx_done, -- (out) transmit done (without errors)\r
--- tx_sndpaustim => x"0000", -- (in) PAUSE frame timer\r
--- tx_sndpausreq => '0', -- (in) PAUSE frame request\r
--- tx_fifoctrl => '0', -- (in) FIFO control frame ('0' = data, '1' = control)\r
--- tx_discfrm => open, -- (out) discard frame\r
--- tx_staten => open, -- (out) transmit statistics vector enable \r
--- tx_statvec => open, -- (out) transmit statistics vector\r
--- --------------------------------------------------------------------------\r
--- --------------- Receive FIFO interface -----------------------------------\r
--- rx_dbout => open, -- (out) receive FIFO data output\r
--- rx_fifo_full => '0', -- (in) receive FIFO full\r
--- ignore_pkt => '0', -- (in) ignore next packet\r
--- rx_fifo_error => open, -- (out) receive FIFO error\r
--- rx_stat_vector => open, -- (out) receive statistics vector\r
--- rx_stat_en => open, -- (out) receive statistics vector enable\r
--- rx_write => open, -- (out) receive FIFO write\r
--- rx_eof => open, -- (out) end of frame\r
--- rx_error => open -- (out) receive packet error\r
---);\r
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-
-entity slv_mac_memory is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- BUSY_IN : in std_logic;
- -- Slave bus
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- I/O to the backend
- MEM_CLK_IN : in std_logic;
- MEM_ADDR_IN : in std_logic_vector(7 downto 0);
- MEM_DATA_OUT : out std_logic_vector(31 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
-);
-end entity;
-
-architecture Behavioral of slv_mac_memory is
-
-component ip_mem is
-port(
- DataInA : in std_logic_vector(31 downto 0);
- DataInB : in std_logic_vector(31 downto 0);
- AddressA : in std_logic_vector(7 downto 0);
- AddressB : in std_logic_vector(7 downto 0);
- ClockA : in std_logic;
- ClockB : in std_logic;
- ClockEnA : in std_logic;
- ClockEnB : in std_logic;
- WrA : in std_logic;
- WrB : in std_logic;
- ResetA : in std_logic;
- ResetB : in std_logic;
- QA : out std_logic_vector(31 downto 0);
- QB : out std_logic_vector(31 downto 0)
-);
-end component ip_mem;
-
--- Signals
-type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
-signal CURRENT_STATE, NEXT_STATE: STATES;
-
--- slave bus signals
-signal slv_busy_x : std_logic;
-signal slv_busy : std_logic;
-signal slv_ack_x : std_logic;
-signal slv_ack : std_logic;
-signal store_wr_x : std_logic;
-signal store_wr : std_logic;
-signal store_rd_x : std_logic;
-signal store_rd : std_logic;
-
-signal reg_busy : std_logic;
-
-begin
-
--- Fake
-reg_busy <= busy_in;
-stat <= (others => '0');
-
----------------------------------------------------------
--- Statemachine --
----------------------------------------------------------
--- State memory process
-STATE_MEM: process( clk )
-begin
- if( rising_edge(clk) ) then
- if( reset = '1' ) then
- CURRENT_STATE <= SLEEP;
- slv_busy <= '0';
- slv_ack <= '0';
- store_wr <= '0';
- store_rd <= '0';
- else
- CURRENT_STATE <= NEXT_STATE;
- slv_busy <= slv_busy_x;
- slv_ack <= slv_ack_x;
- store_wr <= store_wr_x;
- store_rd <= store_rd_x;
- end if;
- end if;
-end process STATE_MEM;
-
--- Transition matrix
-TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy )
-begin
- NEXT_STATE <= SLEEP;
- slv_busy_x <= '0';
- slv_ack_x <= '0';
- store_wr_x <= '0';
- store_rd_x <= '0';
- case CURRENT_STATE is
- when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then
- NEXT_STATE <= RD_RDY;
- store_rd_x <= '1';
- elsif( (reg_busy = '0') and (slv_write_in = '1') ) then
- NEXT_STATE <= WR_RDY;
- store_wr_x <= '1';
- elsif( (reg_busy = '1') and (slv_read_in = '1') ) then
- NEXT_STATE <= RD_BSY;
- elsif( (reg_busy = '1') and (slv_write_in = '1') ) then
- NEXT_STATE <= WR_BSY;
- else
- NEXT_STATE <= SLEEP;
- end if;
- when RD_RDY => NEXT_STATE <= RD_ACK;
- when WR_RDY => NEXT_STATE <= WR_ACK;
- when RD_ACK => if( slv_read_in = '0' ) then
- NEXT_STATE <= DONE;
- slv_ack_x <= '1';
- else
- NEXT_STATE <= RD_ACK;
- slv_ack_x <= '1';
- end if;
- when WR_ACK => if( slv_write_in = '0' ) then
- NEXT_STATE <= DONE;
- slv_ack_x <= '1';
- else
- NEXT_STATE <= WR_ACK;
- slv_ack_x <= '1';
- end if;
- when RD_BSY => if( slv_read_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= RD_BSY;
- slv_busy_x <= '1';
- end if;
- when WR_BSY => if( slv_write_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= WR_BSY;
- slv_busy_x <= '1';
- end if;
- when DONE => NEXT_STATE <= SLEEP;
-
- when others => NEXT_STATE <= SLEEP;
- end case;
-end process TRANSFORM;
-
----------------------------------------------------------
--- data handling --
----------------------------------------------------------
-
-THE_MAC_MEM: ip_mem
-port map(
- DataInA => slv_data_in,
- AddressA => slv_addr_in,
- ClockA => clk,
- ClockEnA => '1',
- QA => slv_data_out,
- WrA => store_wr,
- ResetA => reset,
- DataInB => x"0000_0000",
- AddressB => mem_addr_in,
- ClockB => mem_clk_in,
- ClockEnB => '1',
- WrB => '0', -- never write
- ResetB => reset,
- QB => mem_data_out
-);
-
--- output signals
-slv_ack_out <= slv_ack;
-slv_busy_out <= slv_busy;
-
-end Behavioral;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
---use work.adcmv3_components.all;
-
-
-entity slv_register is
-generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" );
-port( CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- BUSY_IN : in std_logic;
- -- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- I/O to the backend
- REG_DATA_IN : in std_logic_vector(31 downto 0);
- REG_DATA_OUT : out std_logic_vector(31 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
- );
-end entity;
-
-architecture Behavioral of slv_register is
-
--- Signals
-
- type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
- signal CURRENT_STATE, NEXT_STATE: STATES;
-
- -- slave bus signals
- signal slv_busy_x : std_logic;
- signal slv_busy : std_logic;
- signal slv_ack_x : std_logic;
- signal slv_ack : std_logic;
- signal store_wr_x : std_logic;
- signal store_wr : std_logic;
- signal store_rd_x : std_logic;
- signal store_rd : std_logic;
-
- signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input
- signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data
- signal reg_busy : std_logic;
-
-begin
-
--- Fake
-reg_busy <= busy_in;
-stat <= (others => '0');
-
----------------------------------------------------------
--- Statemachine --
----------------------------------------------------------
--- State memory process
-STATE_MEM: process( clk_in )
-begin
- if( rising_edge(clk_in) ) then
- if( reset_in = '1' ) then
- CURRENT_STATE <= SLEEP;
- slv_busy <= '0';
- slv_ack <= '0';
- store_wr <= '0';
- store_rd <= '0';
- else
- CURRENT_STATE <= NEXT_STATE;
- slv_busy <= slv_busy_x;
- slv_ack <= slv_ack_x;
- store_wr <= store_wr_x;
- store_rd <= store_rd_x;
- end if;
- end if;
-end process STATE_MEM;
-
--- Transition matrix
-TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy )
-begin
- NEXT_STATE <= SLEEP;
- slv_busy_x <= '0';
- slv_ack_x <= '0';
- store_wr_x <= '0';
- store_rd_x <= '0';
- case CURRENT_STATE is
- when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then
- NEXT_STATE <= RD_RDY;
- store_rd_x <= '1';
- elsif( (reg_busy = '0') and (slv_write_in = '1') ) then
- NEXT_STATE <= WR_RDY;
- store_wr_x <= '1';
- elsif( (reg_busy = '1') and (slv_read_in = '1') ) then
- NEXT_STATE <= RD_BSY;
- slv_busy_x <= '1'; -- added 23022009
- elsif( (reg_busy = '1') and (slv_write_in = '1') ) then
- NEXT_STATE <= WR_BSY;
- slv_busy_x <= '1'; -- added 23022009
- else
- NEXT_STATE <= SLEEP;
- end if;
- when RD_RDY => NEXT_STATE <= RD_ACK;
- slv_ack_x <= '1';
- when WR_RDY => NEXT_STATE <= WR_ACK;
- slv_ack_x <= '1';
- when RD_ACK => if( slv_read_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= RD_ACK;
- slv_ack_x <= '1';
- end if;
- when WR_ACK => if( slv_write_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= WR_ACK;
- slv_ack_x <= '1';
- end if;
- when RD_BSY => if( slv_read_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= RD_BSY;
- slv_busy_x <= '1';
- end if;
- when WR_BSY => if( slv_write_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= WR_BSY;
- slv_busy_x <= '1';
- end if;
- when DONE => NEXT_STATE <= SLEEP;
-
- when others => NEXT_STATE <= SLEEP;
- end case;
-end process TRANSFORM;
-
----------------------------------------------------------
--- data handling --
----------------------------------------------------------
-
--- register write
-THE_WRITE_REG_PROC: process( clk_in )
-begin
- if( rising_edge(clk_in) ) then
- if ( reset_in = '1' ) then
- reg_slv_data_in <= RESET_VALUE;
- elsif( store_wr = '1' ) then
- reg_slv_data_in <= slv_data_in;
- end if;
- end if;
-end process THE_WRITE_REG_PROC;
-
--- register read
-THE_READ_REG_PROC: process( clk_in )
-begin
- if( rising_edge(clk_in) ) then
- if ( reset_in = '1' ) then
- reg_slv_data_out <= (others => '0');
- elsif( store_rd = '1' ) then
- reg_slv_data_out <= reg_data_in;
- end if;
- end if;
-end process THE_READ_REG_PROC;
-
--- output signals
-slv_ack_out <= slv_ack;
-slv_busy_out <= slv_busy;
-slv_data_out <= reg_slv_data_out;
-
----------------------------------------------------------
--- signals to backend --
----------------------------------------------------------
-
-reg_data_out <= reg_slv_data_in;
-
-end Behavioral;
+++ /dev/null
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT feeder\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
- CTS_CODE_IN : IN std_logic_vector(7 downto 0);\r
- CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
- CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);\r
- CTS_START_READOUT_IN : IN std_logic;\r
- CTS_READ_IN : IN std_logic;\r
- FEE_DATA_IN : IN std_logic_vector(15 downto 0);\r
- FEE_DATAREADY_IN : IN std_logic;\r
- FEE_BUSY_IN : IN std_logic;\r
- FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);\r
- PC_READY_IN : IN std_logic; \r
- CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- CTS_DATAREADY_OUT : OUT std_logic;\r
- CTS_READOUT_FINISHED_OUT : OUT std_logic;\r
- CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
- CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
- FEE_READ_OUT : OUT std_logic;\r
- PC_WR_EN_OUT : OUT std_logic;\r
- PC_DATA_OUT : OUT std_logic_vector(7 downto 0);\r
- PC_SOS_OUT : OUT std_logic;\r
- PC_EOD_OUT : OUT std_logic;\r
- PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_PADDING_OUT : OUT std_logic;\r
- BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0);\r
- BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0);\r
- DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0);\r
- DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RD_EN_OUT : OUT std_logic;\r
- DBG_SF_WR_EN_OUT : OUT std_logic;\r
- DBG_SF_EMPTY_OUT : OUT std_logic;\r
- DBG_SF_FULL_OUT : OUT std_logic;\r
- DBG_SF_AFULL_OUT : OUT std_logic;\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);\r
- SIGNAL CTS_START_READOUT_IN : std_logic;\r
- SIGNAL CTS_READ_IN : std_logic;\r
- SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL CTS_DATAREADY_OUT : std_logic;\r
- SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;\r
- SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);\r
- SIGNAL FEE_DATAREADY_IN : std_logic;\r
- SIGNAL FEE_READ_OUT : std_logic;\r
- SIGNAL FEE_BUSY_IN : std_logic;\r
- SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);\r
- SIGNAL PC_WR_EN_OUT : std_logic;\r
- SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL PC_READY_IN : std_logic;\r
- SIGNAL PC_SOS_OUT : std_logic;\r
- SIGNAL PC_EOD_OUT : std_logic;\r
- SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_PADDING_OUT : std_logic;\r
- SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0);\r
- SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0);\r
- SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RD_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_WR_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_EMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_FULL_OUT : std_logic;\r
- SIGNAL DBG_SF_AFULL_OUT : std_logic;\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: feeder PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- CTS_NUMBER_IN => CTS_NUMBER_IN,\r
- CTS_CODE_IN => CTS_CODE_IN,\r
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,\r
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,\r
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,\r
- CTS_READ_IN => CTS_READ_IN,\r
- CTS_DATA_OUT => CTS_DATA_OUT,\r
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,\r
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,\r
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,\r
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,\r
- FEE_DATA_IN => FEE_DATA_IN,\r
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,\r
- FEE_READ_OUT => FEE_READ_OUT,\r
- FEE_BUSY_IN => FEE_BUSY_IN,\r
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,\r
- PC_WR_EN_OUT => PC_WR_EN_OUT,\r
- PC_DATA_OUT => PC_DATA_OUT,\r
- PC_READY_IN => PC_READY_IN,\r
- PC_SOS_OUT => PC_SOS_OUT,\r
- PC_EOD_OUT => PC_EOD_OUT,\r
- PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT,\r
- PC_TRIG_NR_OUT => PC_TRIG_NR_OUT,\r
- PC_PADDING_OUT => PC_PADDING_OUT,\r
- BSM_SAVE_OUT => BSM_SAVE_OUT,\r
- BSM_LOAD_OUT => BSM_LOAD_OUT,\r
- DBG_REM_CTR_OUT => DBG_REM_CTR_OUT,\r
- DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT,\r
- DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT,\r
- DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT,\r
- DBG_SF_DATA_OUT => DBG_SF_DATA_OUT,\r
- DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT,\r
- DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT,\r
- DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT,\r
- DBG_SF_FULL_OUT => DBG_SF_FULL_OUT,\r
- DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
-\r
-CLOCK_GEN: process\r
-begin\r
- clk <= '1'; wait for 5.0 ns;\r
- clk <= '0'; wait for 5.0 ns;\r
-end process CLOCK_GEN;\r
-\r
--- Testbench\r
-TESTBENCH_PROC: process\r
-variable test_data_len : integer range 0 to 65535 := 49;\r
-variable test_loop_len : integer range 0 to 65535 := 0;\r
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";\r
-variable test_evt_len : unsigned(15 downto 0) := x"0000";\r
-variable test_data : unsigned(15 downto 0) := x"ffff";\r
-\r
-variable trigger_counter : unsigned(15 downto 0) := x"4710";\r
-variable trigger_loop : integer range 0 to 65535 := 15;\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- cts_number_in <= x"0000";\r
- cts_code_in <= x"00";\r
- cts_information_in <= x"00";\r
- cts_readout_type_in <= x"0";\r
- cts_start_readout_in <= '0';\r
- cts_read_in <= '0';\r
- fee_data_in <= x"0000";\r
- fee_dataready_in <= '0';\r
- fee_status_bits_in <= x"0000_0000";\r
- fee_busy_in <= '0';\r
- pc_ready_in <= '0';\r
-\r
- wait for 22 ns;\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- wait for 200 ns;\r
-\r
-\r
--------------------------------------------------------------------------------\r
--- Loop the transmissions\r
--------------------------------------------------------------------------------\r
- trigger_counter := x"4710";\r
- trigger_loop := 9;\r
- test_data_len := 14;\r
-\r
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop\r
- -- IPU transmission starts\r
- wait until rising_edge(clk);\r
- cts_number_in <= std_logic_vector( trigger_counter );\r
- cts_code_in <= x"aa";\r
- cts_information_in <= x"de";\r
- cts_readout_type_in <= x"1";\r
- cts_start_readout_in <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- fee_busy_in <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- -- ONE DATA TRANSMISSION\r
- -- calculate the needed variables\r
--- test_data_len := 4096;\r
- test_loop_len := 2*(test_data_len - 1) + 1;\r
- test_hdr_len := to_unsigned( test_data_len + 1, 16 );\r
- test_evt_len := to_unsigned( test_data_len, 16 );\r
-\r
- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)\r
- fee_dataready_in <= '1';\r
- fee_data_in <= x"10aa";\r
- wait until rising_edge(clk);\r
- fee_data_in <= std_logic_vector( trigger_counter );\r
- wait until rising_edge(clk);\r
- fee_data_in <= std_logic_vector( test_hdr_len );\r
- wait until rising_edge(clk);\r
- fee_data_in <= x"ff21";\r
- wait until rising_edge(clk);\r
- fee_data_in <= std_logic_vector( test_evt_len );\r
- wait until rising_edge(clk);\r
- fee_data_in <= x"ff22"; \r
-\r
- test_data := x"ffff";\r
- MY_DATA_LOOP: for J in 0 to test_loop_len loop\r
- test_data := test_data + 1;\r
- wait until rising_edge(clk);\r
- fee_data_in <= std_logic_vector(test_data); \r
- end loop MY_DATA_LOOP;\r
- \r
- fee_busy_in <= '0'; -- correct?\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '0';\r
- fee_data_in <= x"0000"; \r
-\r
- trigger_loop := trigger_loop + 1;\r
- trigger_counter := trigger_counter + 1;\r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_read_in <= '1';\r
- wait until rising_edge(clk);\r
- cts_read_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_start_readout_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk); \r
- end loop MY_TRIGGER_LOOP;\r
--------------------------------------------------------------------------------\r
--------------------------------------------------------------------------------\r
--------------------------------------------------------------------------------\r
-\r
-\r
- wait for 300 ns;\r
-\r
- -- Start packet_constructor\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_ready_in <= '1';\r
- wait until rising_edge(clk);\r
-\r
- wait;\r
-\r
- wait until rising_edge(clk);\r
- wait until pc_eod_out = '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_ready_in <= '0';\r
-\r
- -- Stay a while... stay forever!!!\r
- wait; \r
- \r
-end process TESTBENCH_PROC;\r
-\r
-\r
-END;\r
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-USE ieee.math_real.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-entity tb_frame_receiver is
-end tb_frame_receiver;
-
-architecture behavior of tb_frame_receiver is
-
-component trb_net16_hub_streaming_port_sctrl is
- generic(
- --hub control
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E";
- CLOCK_FREQUENCY : integer range 1 to 200 := 100;
- USE_ONEWIRE : integer range 0 to 2 := c_YES;
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
- --media interfaces
- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
- MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
- MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES);
- MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO)
- );
-
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- --Media Interface
- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
-
- --Event information coming from CTS
- CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
- CTS_CODE_OUT : out std_logic_vector (7 downto 0);
- CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
- CTS_START_READOUT_OUT : out std_logic;
-
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_IN : in std_logic_vector (31 downto 0);
- CTS_DATAREADY_IN : in std_logic;
- CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
- CTS_READ_OUT : out std_logic;
- CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
- CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
-
- -- Data from Frontends
- FEE_DATA_OUT : out std_logic_vector (15 downto 0);
- FEE_DATAREADY_OUT : out std_logic;
- FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
- FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
- FEE_BUSY_OUT : out std_logic;
-
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
-
- COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
- COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
- ONEWIRE : inout std_logic;
- ONEWIRE_MONITOR_IN : in std_logic;
- ONEWIRE_MONITOR_OUT : out std_logic;
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- UNIQUE_ID_OUT : out std_logic_vector (63 downto 0);
-
- --REGIO INTERFACE
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- REGIO_READ_ENABLE_OUT : out std_logic;
- REGIO_WRITE_ENABLE_OUT : out std_logic;
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- REGIO_DATAREADY_IN : in std_logic := '0';
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';
- REGIO_WRITE_ACK_IN : in std_logic := '0';
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
- REGIO_TIMEOUT_OUT : out std_logic;
-
-
- --Gbe Sctrl Input
- GSC_INIT_DATAREADY_IN : in std_logic;
- GSC_INIT_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_INIT_READ_OUT : out std_logic;
- GSC_REPLY_DATAREADY_OUT : out std_logic;
- GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_REPLY_READ_IN : in std_logic;
- GSC_BUSY_OUT : out std_logic;
-
- --status and control ports
- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
- HUB_STAT_GEN : out std_logic_vector (31 downto 0);
- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
- STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
- --Debugging registers
- STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
- CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
- );
-end component;
-
-signal CLK : std_logic;
-signal RESET : std_logic;
-signal LINK_OK_IN : std_logic;
-signal ALLOW_RX_IN : std_logic;
-signal RX_MAC_CLK : std_logic;
-signal MAC_RX_EOF_IN : std_logic;
-signal MAC_RX_ER_IN : std_logic;
-signal MAC_RXD_IN : std_logic_vector(7 downto 0);
-signal MAC_RX_EN_IN : std_logic;
-signal MAC_RX_FIFO_ERR_IN : std_logic;
-signal MAC_RX_FIFO_FULL_OUT : std_logic;
-signal MAC_RX_STAT_EN_IN : std_logic;
-signal MAC_RX_STAT_VEC_IN : std_logic_vector(31 downto 0);
-signal FR_Q_OUT : std_logic_vector(8 downto 0);
-signal FR_RD_EN_IN : std_logic;
-signal FR_FRAME_VALID_OUT : std_logic;
-signal FR_GET_FRAME_IN : std_logic;
-signal FR_FRAME_SIZE_OUT : std_logic_vector(15 downto 0);
-signal FR_FRAME_PROTO_OUT : std_logic_vector(15 downto 0);
-signal DEBUG_OUT : std_logic_vector(95 downto 0);
-signal FR_ALLOWED_TYPES_IN : std_logic_vector(31 downto 0);
-
-signal RC_RD_EN_IN : std_logic;
-signal RC_Q_OUT : std_logic_vector(8 downto 0);
-signal RC_FRAME_WAITING_OUT : std_logic;
-signal RC_LOADING_DONE_IN : std_logic;
-signal RC_FRAME_SIZE_OUT : std_logic_vector(15 downto 0);
-signal FRAMES_RECEIVED_OUT : std_logic_vector(31 downto 0);
-signal BYTES_RECEIVED_OUT : std_logic_vector(31 downto 0);
-
-signal MC_TRANSMIT_CTRL_OUT : std_logic;
-signal MC_TRANSMIT_DATA_OUT : std_logic;
-signal MC_DATA_OUT : std_logic_vector(8 downto 0);
-signal MC_RD_EN_IN : std_logic;
-signal MC_FRAME_SIZE_OUT : std_logic_vector(15 downto 0);
-signal MC_BUSY_IN : std_logic;
-signal MC_TRANSMIT_DONE_IN : std_logic;
-signal RC_FRAME_PROTO_OUT : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
-signal fc_data : std_logic_vector(7 downto 0);
-signal fc_wr_en : std_logic;
-signal fc_sod : std_logic;
-signal fc_eod : std_logic;
-signal fc_h_ready : std_logic;
-signal fc_ip_size : std_logic_vector(15 downto 0);
-signal fc_udp_size : std_logic_vector(15 downto 0);
-signal fc_ready : std_logic;
-signal fc_dest_mac : std_logic_vector(47 downto 0);
-signal fc_dest_ip : std_logic_vector(31 downto 0);
-signal fc_dest_udp : std_logic_vector(15 downto 0);
-signal fc_src_mac : std_logic_vector(47 downto 0);
-signal fc_src_ip : std_logic_vector(31 downto 0);
-signal fc_src_udp : std_logic_vector(15 downto 0);
-signal fc_type : std_logic_vector(15 downto 0);
-signal mc_type : std_logic_vector(15 downto 0);
-signal fc_ihl : std_logic_vector(7 downto 0);
-signal fc_tos : std_logic_vector(7 downto 0);
-signal fc_ident : std_logic_vector(15 downto 0);
-signal fc_flags : std_logic_vector(15 downto 0);
-signal fc_ttl : std_logic_vector(7 downto 0);
-signal fc_proto : std_logic_vector(7 downto 0);
-signal fr_src_mac : std_logic_vector(47 downto 0);
-signal fr_dest_mac : std_logic_vector(47 downto 0);
-signal fr_src_ip : std_logic_vector(31 downto 0);
-signal fr_dest_ip : std_logic_vector(31 downto 0);
-signal fr_src_udp : std_logic_vector(15 downto 0);
-signal fr_dest_udp : std_logic_vector(15 downto 0);
-signal rc_src_mac : std_logic_vector(47 downto 0);
-signal rc_dest_mac : std_logic_vector(47 downto 0);
-signal rc_src_ip : std_logic_vector(31 downto 0);
-signal rc_dest_ip : std_logic_vector(31 downto 0);
-signal rc_src_udp : std_logic_vector(15 downto 0);
-signal rc_dest_udp : std_logic_vector(15 downto 0);
-
-signal mc_dest_mac : std_logic_vector(47 downto 0);
-signal mc_dest_ip : std_logic_vector(31 downto 0);
-signal mc_dest_udp : std_logic_vector(15 downto 0);
-signal mc_src_mac : std_logic_vector(47 downto 0);
-signal mc_src_ip : std_logic_vector(31 downto 0);
-signal mc_src_udp : std_logic_vector(15 downto 0);
-
-signal fr_allowed_ip : std_logic_vector(31 downto 0);
-signal fr_allowed_udp : std_logic_vector(31 downto 0);
-
-signal fr_ip_proto : std_logic_vector(7 downto 0);
-signal mc_ip_proto : std_logic_vector(7 downto 0);
-
-signal additional_rand_pause : std_logic;
-
-signal pc_ready, pc_sos, pc_transmit_on, pc_wr_en, pc_sod, pc_eod, pc_fc_h_ready, pc_fc_ready : std_logic;
-signal pc_data : std_logic_vector(7 downto 0);
-signal pc_ip_size, pc_udp_size : std_logic_vector(15 downto 0);
-signal gsc_init_read, gsc_init_dataready : std_logic;
-signal gsc_reply_read, gsc_reply_dataready : std_logic;
-signal gsc_reply_data, gsc_init_data : std_logic_vector(15 downto 0);
-signal gsc_busy : std_logic;
-signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0);
-signal mc_flags, mc_ip_size, mc_udp_size : std_logic_vector(15 downto 0);
-
-begin
-
-HUB_STR : trb_net16_hub_streaming_port_sctrl
- generic map(
- --media interfaces
- MII_NUMBER => 5,
- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0),
- MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0),
- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0)
- )
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => '1',
-
- --Media Interface
- MED_DATAREADY_OUT => open,
- MED_DATA_OUT => open,
- MED_PACKET_NUM_OUT => open,
- MED_READ_IN => (others => '0'),
- MED_DATAREADY_IN => (others => '0'),
- MED_DATA_IN => (others => '0'),
- MED_PACKET_NUM_IN => (others => '0'),
- MED_READ_OUT => open,
- MED_STAT_OP => x"0007_0007_0007_0007_0007",
- MED_CTRL_OP => open,
-
- --Event information coming from CTS
- CTS_NUMBER_OUT => open,
- CTS_CODE_OUT => open,
- CTS_INFORMATION_OUT => open,
- CTS_READOUT_TYPE_OUT => open,
- CTS_START_READOUT_OUT => open,
-
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_IN => (others => '0'),
- CTS_DATAREADY_IN => '0',
- CTS_READOUT_FINISHED_IN => '0',
- CTS_READ_OUT => open,
- CTS_LENGTH_IN => (others => '0'),
- CTS_STATUS_BITS_IN => (others => '0'),
-
- -- Data from Frontends
- FEE_DATA_OUT => open,
- FEE_DATAREADY_OUT => open,
- FEE_READ_IN => '0',
- FEE_STATUS_BITS_OUT => open,
- FEE_BUSY_OUT => open,
-
- MY_ADDRESS_IN => (others => '0'),
-
- COMMON_STAT_REGS => open,
- COMMON_CTRL_REGS => open,
- ONEWIRE => open,
- ONEWIRE_MONITOR_IN => '0',
- ONEWIRE_MONITOR_OUT => open,
- MY_ADDRESS_OUT => open,
- UNIQUE_ID_OUT => open,
-
- --REGIO INTERFACE
- REGIO_ADDR_OUT => open,
- REGIO_READ_ENABLE_OUT => open,
- REGIO_WRITE_ENABLE_OUT => open,
- REGIO_DATA_OUT => open,
- REGIO_DATA_IN => (others => '0'),
- REGIO_DATAREADY_IN => '0',
- REGIO_NO_MORE_DATA_IN => '0',
- REGIO_WRITE_ACK_IN => '0',
- REGIO_UNKNOWN_ADDR_IN => '0',
- REGIO_TIMEOUT_OUT => open,
-
-
- --Gbe Sctrl Input
- GSC_INIT_DATAREADY_IN => gsc_init_dataready,
- GSC_INIT_DATA_IN => gsc_init_data,
- GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
- GSC_INIT_READ_OUT => gsc_init_read,
- GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
- GSC_REPLY_DATA_OUT => gsc_reply_data,
- GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
- GSC_REPLY_READ_IN => gsc_reply_read,
- GSC_BUSY_OUT => gsc_busy,
-
- --status and control ports
- HUB_STAT_CHANNEL => open,
- HUB_STAT_GEN => open,
- MPLEX_CTRL => (others => '0'),
- MPLEX_STAT => open,
- STAT_REGS => open,
- STAT_CTRL_REGS => open,
- --Debugging registers
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-
-packet_constr : trb_net16_gbe_packet_constr
-port map(
- RESET => RESET,
- CLK => CLK,
- MULT_EVT_ENABLE_IN => '0',
- -- ports for user logic
- PC_WR_EN_IN => '0',
- PC_DATA_IN => (others => '0'),
- PC_READY_OUT => pc_ready,
- PC_START_OF_SUB_IN => pc_sos,
- PC_END_OF_SUB_IN => '0',
- PC_END_OF_DATA_IN => '0',
- PC_TRANSMIT_ON_OUT => pc_transmit_on,
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN => (others => '0'),
- PC_PADDING_IN => '0',
- PC_DECODING_IN => (others => '0'),
- PC_EVENT_ID_IN => (others => '0'),
- PC_TRIG_NR_IN => (others => '0'),
- PC_QUEUE_DEC_IN => (others => '0'),
- PC_MAX_FRAME_SIZE_IN => (others => '0'),
- PC_DELAY_IN => (others => '0'),
- -- FrameConstructor ports
- TC_WR_EN_OUT => pc_wr_en,
- TC_DATA_OUT => pc_data,
- TC_H_READY_IN => pc_fc_h_ready,
- TC_READY_IN => pc_fc_ready,
- TC_IP_SIZE_OUT => pc_ip_size,
- TC_UDP_SIZE_OUT => pc_udp_size,
- TC_FLAGS_OFFSET_OUT => open,
- TC_SOD_OUT => pc_sod,
- TC_EOD_OUT => pc_eod,
- DEBUG_OUT => open
-);
-
-receiver : trb_net16_gbe_frame_receiver
-port map (
- CLK => CLK,
- RESET => RESET,
- LINK_OK_IN => LINK_OK_IN,
- ALLOW_RX_IN => ALLOW_RX_IN,
- RX_MAC_CLK => RX_MAC_CLK,
-
- MAC_RX_EOF_IN => MAC_RX_EOF_IN,
- MAC_RX_ER_IN => MAC_RX_ER_IN,
- MAC_RXD_IN => MAC_RXD_IN,
- MAC_RX_EN_IN => MAC_RX_EN_IN,
- MAC_RX_FIFO_ERR_IN => MAC_RX_FIFO_ERR_IN,
- MAC_RX_FIFO_FULL_OUT => MAC_RX_FIFO_FULL_OUT,
- MAC_RX_STAT_EN_IN => MAC_RX_STAT_EN_IN,
- MAC_RX_STAT_VEC_IN => MAC_RX_STAT_VEC_IN,
-
- FR_Q_OUT => FR_Q_OUT,
- FR_RD_EN_IN => FR_RD_EN_IN,
- FR_FRAME_VALID_OUT => FR_FRAME_VALID_OUT,
- FR_GET_FRAME_IN => FR_GET_FRAME_IN,
- FR_FRAME_SIZE_OUT => FR_FRAME_SIZE_OUT,
- FR_FRAME_PROTO_OUT => FR_FRAME_PROTO_OUT,
- FR_IP_PROTOCOL_OUT => fr_ip_proto,
- FR_ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN,
- FR_ALLOWED_IP_IN => fr_allowed_ip,
- FR_ALLOWED_UDP_IN => fr_allowed_udp,
- FR_VLAN_ID_IN => x"aabb_0000",
-
- FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
- FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
- FR_SRC_IP_ADDRESS_OUT => fr_src_ip,
- FR_DEST_IP_ADDRESS_OUT => fr_dest_ip,
- FR_SRC_UDP_PORT_OUT => fr_src_udp,
- FR_DEST_UDP_PORT_OUT => fr_dest_udp,
-
- DEBUG_OUT => DEBUG_OUT
-);
-
-receive_controler : trb_net16_gbe_receive_control
-port map(
- CLK => CLK,
- RESET => RESET,
-
--- signals to/from frame_receiver
- RC_DATA_IN => FR_Q_OUT,
- FR_RD_EN_OUT => FR_RD_EN_IN,
- FR_FRAME_VALID_IN => FR_FRAME_VALID_OUT,
- FR_GET_FRAME_OUT => FR_GET_FRAME_IN,
- FR_FRAME_SIZE_IN => FR_FRAME_SIZE_OUT,
- FR_FRAME_PROTO_IN => FR_FRAME_PROTO_OUT,
- FR_IP_PROTOCOL_IN => fr_ip_proto,
-
- FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
- FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
- FR_SRC_IP_ADDRESS_IN => fr_src_ip,
- FR_DEST_IP_ADDRESS_IN => fr_dest_ip,
- FR_SRC_UDP_PORT_IN => fr_src_udp,
- FR_DEST_UDP_PORT_IN => fr_dest_udp,
-
--- signals to/from main controller
- RC_RD_EN_IN => RC_RD_EN_IN,
- RC_Q_OUT => RC_Q_OUT,
- RC_FRAME_WAITING_OUT => RC_FRAME_WAITING_OUT,
- RC_LOADING_DONE_IN => RC_LOADING_DONE_IN,
- RC_FRAME_SIZE_OUT => RC_FRAME_SIZE_OUT,
- RC_FRAME_PROTO_OUT => RC_FRAME_PROTO_OUT,
-
- RC_SRC_MAC_ADDRESS_OUT => rc_src_mac,
- RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
- RC_SRC_IP_ADDRESS_OUT => rc_src_ip,
- RC_DEST_IP_ADDRESS_OUT => rc_dest_ip,
- RC_SRC_UDP_PORT_OUT => rc_src_udp,
- RC_DEST_UDP_PORT_OUT => rc_dest_udp,
-
--- statistics
- FRAMES_RECEIVED_OUT => open,
- BYTES_RECEIVED_OUT => open,
-
- DEBUG_OUT => open
-);
-
-main_controller : trb_net16_gbe_main_control
-port map (
- CLK => CLK,
- CLK_125 => RX_MAC_CLK,
- RESET => RESET,
-
- MC_LINK_OK_OUT => open,
- MC_RESET_LINK_IN => '0',
-
--- signals to/from receive controller
- RC_FRAME_WAITING_IN => RC_FRAME_WAITING_OUT,
- RC_LOADING_DONE_OUT => RC_LOADING_DONE_IN,
- RC_DATA_IN => RC_Q_OUT,
- RC_RD_EN_OUT => RC_RD_EN_IN,
- RC_FRAME_SIZE_IN => RC_FRAME_SIZE_OUT,
- RC_FRAME_PROTO_IN => RC_FRAME_PROTO_OUT,
-
- RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
- RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
- RC_SRC_IP_ADDRESS_IN => rc_src_ip,
- RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
- RC_SRC_UDP_PORT_IN => rc_src_udp,
- RC_DEST_UDP_PORT_IN => rc_dest_udp,
-
--- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT => MC_TRANSMIT_CTRL_OUT,
- TC_TRANSMIT_DATA_OUT => MC_TRANSMIT_DATA_OUT,
- TC_DATA_OUT => MC_DATA_OUT,
- TC_RD_EN_IN => MC_RD_EN_IN,
- TC_FRAME_SIZE_OUT => MC_FRAME_SIZE_OUT,
- TC_FRAME_TYPE_OUT => mc_type,
- TC_IP_PROTOCOL_OUT => mc_ip_proto,
-
- TC_DEST_MAC_OUT => mc_dest_mac,
- TC_DEST_IP_OUT => mc_dest_ip,
- TC_DEST_UDP_OUT => mc_dest_udp,
- TC_SRC_MAC_OUT => mc_src_mac,
- TC_SRC_IP_OUT => mc_src_ip,
- TC_SRC_UDP_OUT => mc_src_udp,
-
- TC_IP_SIZE_OUT => mc_ip_size,
- TC_UDP_SIZE_OUT => mc_udp_size,
- TC_FLAGS_OFFSET_OUT => mc_flags,
-
- TC_BUSY_IN => MC_BUSY_IN,
- TC_TRANSMIT_DONE_IN => MC_TRANSMIT_DONE_IN,
-
--- signals to/from packet constructor
- PC_READY_IN => pc_ready,
- PC_TRANSMIT_ON_IN => pc_transmit_on,
- PC_SOD_IN => pc_sod,
-
--- signals to/from sgmii/gbe pcs_an_complete
- PCS_AN_COMPLETE_IN => '1',
-
--- signals to/from hub
- MC_UNIQUE_ID_IN => (others => '0'),
-
- GSC_CLK_IN => CLK,
- GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
- GSC_INIT_DATA_OUT => gsc_init_data,
- GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
- GSC_INIT_READ_IN => gsc_init_read,
- GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
- GSC_REPLY_DATA_IN => gsc_reply_data,
- GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
- GSC_REPLY_READ_OUT => gsc_reply_read,
- GSC_BUSY_IN => gsc_busy,
-
--- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT => open,
- TSM_HDATA_OUT => open,
- TSM_HCS_N_OUT => open,
- TSM_HWRITE_N_OUT => open,
- TSM_HREAD_N_OUT => open,
- TSM_HREADY_N_IN => '0',
- TSM_HDATA_EN_N_IN => '1',
- TSM_RX_STAT_VEC_IN => (others => '0'),
- TSM_RX_STAT_EN_IN => '0',
-
- DEBUG_OUT => open
-);
-
-transmit_controller : trb_net16_gbe_transmit_control
-port map(
- CLK => CLK,
- RESET => RESET,
-
--- signals to/from packet constructor
- PC_READY_IN => pc_ready, --'1',
- PC_DATA_IN => pc_data, --(others => '0'),
- PC_WR_EN_IN => pc_wr_en, --'0',
- PC_IP_SIZE_IN => pc_ip_size,
- PC_UDP_SIZE_IN => pc_udp_size,
- PC_FLAGS_OFFSET_IN => (others => '0'),
- PC_SOD_IN => pc_sod,
- PC_EOD_IN => pc_eod,
- PC_FC_READY_OUT => pc_fc_ready,
- PC_FC_H_READY_OUT => pc_fc_h_ready,
- PC_TRANSMIT_ON_IN => '0',
-
- -- signals from ip_configurator used by packet constructor
- IC_DEST_MAC_ADDRESS_IN => x"112233445566",
- IC_DEST_IP_ADDRESS_IN => x"aabbccdd",
- IC_DEST_UDP_PORT_IN => x"0101",
- IC_SRC_MAC_ADDRESS_IN => x"665544332211",
- IC_SRC_IP_ADDRESS_IN => x"ddccbbaa",
- IC_SRC_UDP_PORT_IN => x"0202",
-
--- signal to/from main controller
- MC_TRANSMIT_CTRL_IN => MC_TRANSMIT_CTRL_OUT,
- MC_TRANSMIT_DATA_IN => MC_TRANSMIT_DATA_OUT,
- MC_DATA_IN => MC_DATA_OUT,
- MC_RD_EN_OUT => MC_RD_EN_IN,
- MC_FRAME_SIZE_IN => MC_FRAME_SIZE_OUT,
- MC_FRAME_TYPE_IN => mc_type,
- MC_IP_PROTOCOL_IN => mc_ip_proto,
-
- MC_DEST_MAC_IN => mc_dest_mac,
- MC_DEST_IP_IN => mc_dest_ip,
- MC_DEST_UDP_IN => mc_dest_udp,
- MC_SRC_MAC_IN => mc_src_mac,
- MC_SRC_IP_IN => mc_src_ip,
- MC_SRC_UDP_IN => mc_src_udp,
-
- MC_IP_SIZE_IN => mc_ip_size,
- MC_UDP_SIZE_IN => mc_udp_size,
- MC_FLAGS_OFFSET_IN => mc_flags,
-
- MC_BUSY_OUT => MC_BUSY_IN,
- MC_TRANSMIT_DONE_OUT => MC_TRANSMIT_DONE_IN,
-
--- signal to/from frame constructor
- FC_DATA_OUT => fc_data,
- FC_WR_EN_OUT => fc_wr_en,
- FC_READY_IN => fc_ready,
- FC_H_READY_IN => fc_h_ready,
- FC_FRAME_TYPE_OUT => fc_type,
- FC_IP_SIZE_OUT => fc_ip_size,
- FC_UDP_SIZE_OUT => fc_udp_size,
- FC_IDENT_OUT => fc_ident,
- FC_FLAGS_OFFSET_OUT => fc_flags,
- FC_SOD_OUT => fc_sod,
- FC_EOD_OUT => fc_eod,
- FC_IP_PROTOCOL_OUT => fc_proto,
-
- DEST_MAC_ADDRESS_OUT => fc_dest_mac,
- DEST_IP_ADDRESS_OUT => fc_dest_ip,
- DEST_UDP_PORT_OUT => fc_dest_udp,
- SRC_MAC_ADDRESS_OUT => fc_src_mac,
- SRC_IP_ADDRESS_OUT => fc_src_ip,
- SRC_UDP_PORT_OUT => fc_src_udp,
-
- DEBUG_OUT => open
-);
-
-frame_constructor : trb_net16_gbe_frame_constr
-port map(
- -- ports for user logic
- RESET => RESET,
- CLK => CLK,
- LINK_OK_IN => '1',
- --
- WR_EN_IN => fc_wr_en,
- DATA_IN => fc_data,
- START_OF_DATA_IN => fc_sod,
- END_OF_DATA_IN => fc_eod,
- IP_F_SIZE_IN => fc_ip_size,
- UDP_P_SIZE_IN => fc_udp_size,
- HEADERS_READY_OUT => fc_h_ready,
- READY_OUT => fc_ready,
- DEST_MAC_ADDRESS_IN => fc_dest_mac,
- DEST_IP_ADDRESS_IN => fc_dest_ip,
- DEST_UDP_PORT_IN => fc_dest_udp,
- SRC_MAC_ADDRESS_IN => fc_src_mac,
- SRC_IP_ADDRESS_IN => fc_src_ip,
- SRC_UDP_PORT_IN => fc_src_udp,
- FRAME_TYPE_IN => fc_type,
- IHL_VERSION_IN => fc_ihl,
- TOS_IN => fc_tos,
- IDENTIFICATION_IN => fc_ident,
- FLAGS_OFFSET_IN => fc_flags,
- TTL_IN => fc_ttl,
- PROTOCOL_IN => fc_proto,
- FRAME_DELAY_IN => x"0000_0000",
- -- ports for packetTransmitter
- RD_CLK => RX_MAC_CLK,
- FT_DATA_OUT => open,
- FT_TX_EMPTY_OUT => open,
- FT_TX_RD_EN_IN => '1',
- FT_START_OF_PACKET_OUT => open,
- FT_TX_DONE_IN => '1',
- FT_TX_DISCFRM_IN => '0',
- -- debug ports
- BSM_CONSTR_OUT => open,
- BSM_TRANS_OUT => open,
- DEBUG_OUT => open
-);
-
--- 100 MHz system clock
-CLOCK_GEN_PROC: process
-begin
- CLK <= '1'; wait for 5.0 ns;
- CLK <= '0'; wait for 5.0 ns;
-end process CLOCK_GEN_PROC;
-
--- 125 MHz MAC clock
-CLOCK2_GEN_PROC: process
-begin
- RX_MAC_CLK <= '1'; wait for 3.0 ns;
- RX_MAC_CLK <= '0'; wait for 4.0 ns;
-end process CLOCK2_GEN_PROC;
-
-CHECK_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- assert DEBUG_OUT(1) = '0' and DEBUG_OUT(3) = '0' report "FIFO FULL" severity error;
- end if;
-end process CHECK_PROC;
-
-
-TESTBENCH_PROC : process
-
-variable seed1 : positive; -- seed for random generator
-variable seed2 : positive; -- seed for random generator
-variable rand : real; -- random value (0.0 ... 1.0)
-variable int_rand : integer; -- random value, scaled to your needs
-
-begin
-
- wait for 50 ns;
- RESET <= '1';
-
- LINK_OK_IN <= '1';
- ALLOW_RX_IN <= '1';
-
- MAC_RX_EOF_IN <= '0';
- MAC_RX_ER_IN <= '0';
- MAC_RXD_IN <= x"00";
- MAC_RX_EN_IN <= '0';
- MAC_RX_FIFO_ERR_IN <= '0';
- FR_ALLOWED_TYPES_IN <= x"0000_000f";
- fr_allowed_ip <= x"0000_000f";
- fr_allowed_udp <= x"0000_000f";
- additional_rand_pause <= '0';
- pc_sos <= '0';
--- gsc_init_read <= '0';
--- gsc_busy <= '0';
--- gsc_reply_data <= (others => '0');
--- gsc_reply_dataready <= '0';
---
- wait for 10 ns;
- RESET <= '0';
- wait for 50 ns;
-
- --for i in 0 to 1000 loop
-
- wait for 400 ns;
-
- -- FIRST FRAME UDP - DHCP Offer
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- ip headers
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"5a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"49";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11"; -- udp
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
--- udp headers
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"43";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"2c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
--- dhcp data
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"de";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ad";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"fa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ce";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
-
- for i in 0 to 219 loop
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- end loop;
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"35";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
- wait for 1 us;
-
- -- FIRST FRAME UDP - DHCP Offer
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- ip headers
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"5a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"49";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11"; -- udp
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
--- udp headers
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"43";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"2c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
--- dhcp data
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"de";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ad";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"fa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ce";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
-
- for i in 0 to 219 loop
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- end loop;
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"35";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"05";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
-
-
- wait;
-
-
- -- FIRST FRAME (ARP Request)
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- arp frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
--- hardware type
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- protocol type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- hardware size
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
--- protocol size
- MAC_RXD_IN <= x"04";
- wait until rising_edge(RX_MAC_CLK);
--- opcode (request)
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- sender mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- sender ip
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a9";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- target mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- target ip
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"65";
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
-
- -- FIRST FRAME UDP - SCTRL READ REQUEST
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RX_EN_IN <= '1';
----- dest mac
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
----- src mac
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"aa";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"bb";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"cc";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"dd";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ee";
--- wait until rising_edge(RX_MAC_CLK);
----- frame type
--- MAC_RXD_IN <= x"08";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
----- ip headers
--- MAC_RXD_IN <= x"45";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"10";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"01";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"5a";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"49";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"11"; -- udp
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"cc";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"cc";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"c0";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"a8";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"01";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"c0";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"a8";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"02";
----- udp headers
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"43";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"61";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"a8";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"02";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"2c";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"aa";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"bb";
----- sctrl data
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00"; --MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"31";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ff";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"08";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"30";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"50";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"af";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"fe";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"de";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"ad";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"33";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"08";
--- MAC_RX_EOF_IN <= '1';
--- wait until rising_edge(RX_MAC_CLK);
---
--- MAC_RX_EN_IN <='0';
--- MAC_RX_EOF_IN <= '0';
-
-
--- wait until rising_edge(gsc_init_dataready);
--- wait until rising_edge(CLK);
--- gsc_init_read <= '1';
---
--- wait until falling_edge(gsc_init_dataready);
--- wait until rising_edge(CLK);
--- gsc_init_read <= '0';
---
--- --wait for 100 ns;
--- --wait until rising_edge(gsc_reply_read);
--- wait until rising_edge(CLK);
--- wait until rising_edge(CLK);
--- wait until rising_edge(CLK);
--- wait until rising_edge(CLK);
--- gsc_reply_data <= x"0101";
--- gsc_reply_dataready <= '1';
--- wait until rising_edge(CLK);
--- gsc_reply_data <= x"0202";
--- wait until rising_edge(CLK);
--- gsc_reply_data <= x"0303";
--- wait until rising_edge(CLK);
--- gsc_reply_data <= x"0404";
--- wait until rising_edge(CLK);
--- gsc_reply_data <= x"0505";
--- wait until rising_edge(CLK);
--- gsc_reply_data <= x"0606";
--- wait until rising_edge(CLK);
--- gsc_reply_data <= x"0707";
--- wait until rising_edge(CLK);
--- gsc_reply_data <= x"0808";
--- wait until rising_edge(CLK);
--- gsc_reply_dataready <= '0';
-
-
- -- STOP HERE
- wait;
-
-
- -- FIRST FRAME (ARP Request)
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- arp frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
--- hardware type
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- protocol type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- hardware size
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
--- protocol size
- MAC_RXD_IN <= x"04";
- wait until rising_edge(RX_MAC_CLK);
--- opcode (request)
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- sender mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- sender ip
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a9";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- target mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- target ip
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"65";
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
-
- wait;
-
-
-
-
--- FIRST FRAME UDP - DHCP Offer
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ef";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ef";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- ip headers
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"5a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"49";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11"; -- udp
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
--- udp headers
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"43";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"2c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
--- dhcp data
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"de";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ad";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"fa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ce";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
-
- for i in 0 to 219 loop
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- end loop;
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"35";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
- wait for 100 us;
-
-
-
- wait;
-
-
-
-
-
-
-
-
-
-
-
-
-
- -- FIRST FRAME IP - ICMP Ping request
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ef";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ef";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- ip headers
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"5a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"49";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
--- ping headers
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"47";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"d3";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0d";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"3c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- ping data
- MAC_RXD_IN <= x"8c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"da";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"e7";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"4d";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"36";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c4";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0d";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"09";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0b";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0d";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0e";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0f";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EOF_IN <= '1';
- MAC_RXD_IN <= x"aa";
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
- wait for 1500 ns;
-
-
-
- wait;
-
-
-
-
-
- -- FIRST FRAME IP - ICMP Ping request
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ef";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ef";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- ip headers
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"5a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"49";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01"; -- icmp
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
--- ping headers
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"47";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"d3";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0d";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"3c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- ping data
- MAC_RXD_IN <= x"8c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"da";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"e7";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"4d";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"36";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c4";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0d";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"09";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0b";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0d";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0e";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"0f";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EOF_IN <= '1';
- MAC_RXD_IN <= x"aa";
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
--- end loop;
-
- wait for 1500 ns;
-
-
- -- FIRST FRAME (ARP Request)
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- arp frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
--- hardware type
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- protocol type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- hardware size
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
--- protocol size
- MAC_RXD_IN <= x"04";
- wait until rising_edge(RX_MAC_CLK);
--- opcode (request)
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- sender mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- sender ip
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a9";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- target mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- target ip
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"65";
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
-
-
-
-
-
--- FIRST FRAME UDP - DHCP Offer
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ef";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ef";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- ip headers
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"5a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"49";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11"; -- udp
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
--- udp headers
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"43";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"2c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
--- dhcp data
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"de";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ad";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"fa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ce";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
-
- for i in 0 to 219 loop
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- end loop;
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"35";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
- wait for 100 us;
-
-
--- FIRST FRAME UDP
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"22";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"33";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"55";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- ip headers
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ab";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"40";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
--- udp headers
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"2c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
--- few data words
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"03";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"04";
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
-
- wait for 100 ns;
-
- -- FIRST FRAME (ARP Request)
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"22";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"33";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"55";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- arp frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"07";
- wait until rising_edge(RX_MAC_CLK);
--- hardware type
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- protocol type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- hardware size
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
--- protocol size
- MAC_RXD_IN <= x"04";
- wait until rising_edge(RX_MAC_CLK);
--- opcode (request)
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- sender mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- sender ip
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a9";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
--- target mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- target ip
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a9";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
--- cs
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"03";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"04";
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
-
- wait for 100 ns;
-
--- SECOND FRAME
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"22";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"33";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"55";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"22";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"33";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"55";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
--- data
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
--- cs
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"03";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"04";
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
-
- wait for 50 ns;
-
--- THIRD FRAME
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"22";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"33";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"55";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"22";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"33";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"55";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
--- data
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
--- cs
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"03";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"04";
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
- wait for 100 ns;
-
-
- wait;
-
- FRAMES_LOOP : for i in 0 to 100 loop
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
- -- dest mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"22";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"33";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"55";
- wait until rising_edge(RX_MAC_CLK);
- -- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"22";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"33";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"55";
- wait until rising_edge(RX_MAC_CLK);
- -- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- -- data
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- -- cs
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"03";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"04";
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
-
- wait for 100 ns;
- end loop FRAMES_LOOP;
-
- wait for 1000 ns;
-
-end process;
-
-
-end architecture;
+++ /dev/null
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.math_real.all;
-USE ieee.numeric_std.ALL;
-
-use work.trb_net_gbe_components.all;
-
-ENTITY testbench IS
-END testbench;
-
-ARCHITECTURE behavior OF testbench IS
--- component trb_net16_gbe_buf is
--- generic(
--- DO_SIMULATION : integer range 0 to 1 := 1;
--- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
--- );
--- port(
--- CLK : in std_logic;
--- TEST_CLK : in std_logic; -- only for simulation!
--- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
--- RESET : in std_logic;
--- GSR_N : in std_logic;
--- -- Debug
--- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);
--- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);
--- -- configuration interface
--- IP_CFG_START_IN : in std_logic;
--- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);
--- IP_CFG_DONE_OUT : out std_logic;
--- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);
--- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);
--- IP_CFG_MEM_CLK_OUT : out std_logic;
--- MR_RESET_IN : in std_logic;
--- MR_MODE_IN : in std_logic;
--- MR_RESTART_IN : in std_logic;
--- -- gk 29.03.10
--- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
--- SLV_READ_IN : in std_logic;
--- SLV_WRITE_IN : in std_logic;
--- SLV_BUSY_OUT : out std_logic;
--- SLV_ACK_OUT : out std_logic;
--- SLV_DATA_IN : in std_logic_vector(31 downto 0);
--- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
--- -- gk 22.04.10
--- -- registers setup interface
--- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
--- BUS_DATA_IN : in std_logic_vector(31 downto 0);
--- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
--- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
--- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
--- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
--- -- gk 23.04.10
--- LED_PACKET_SENT_OUT : out std_logic;
--- LED_AN_DONE_N_OUT : out std_logic;
--- -- CTS interface
--- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
--- CTS_CODE_IN : in std_logic_vector (7 downto 0);
--- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
--- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
--- CTS_START_READOUT_IN : in std_logic;
--- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
--- CTS_DATAREADY_OUT : out std_logic;
--- CTS_READOUT_FINISHED_OUT : out std_logic;
--- CTS_READ_IN : in std_logic;
--- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
--- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
--- -- Data payload interface
--- FEE_DATA_IN : in std_logic_vector (15 downto 0);
--- FEE_DATAREADY_IN : in std_logic;
--- FEE_READ_OUT : out std_logic;
--- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
--- FEE_BUSY_IN : in std_logic;
--- --SFP Connection
--- SFP_RXD_P_IN : in std_logic;
--- SFP_RXD_N_IN : in std_logic;
--- SFP_TXD_P_OUT : out std_logic;
--- SFP_TXD_N_OUT : out std_logic;
--- SFP_REFCLK_P_IN : in std_logic;
--- SFP_REFCLK_N_IN : in std_logic;
--- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
--- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
--- SFP_TXDIS_OUT : out std_logic; -- SFP disable
---
--- -- interface between main_controller and hub logic
--- MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
--- GSC_CLK_IN : in std_logic;
--- GSC_INIT_DATAREADY_OUT : out std_logic;
--- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
--- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
--- GSC_INIT_READ_IN : in std_logic;
--- GSC_REPLY_DATAREADY_IN : in std_logic;
--- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
--- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
--- GSC_REPLY_READ_OUT : out std_logic;
--- GSC_BUSY_IN : in std_logic;
---
--- MAKE_RESET_OUT : out std_logic;
---
--- -- for simulation of receiving part only
--- MAC_RX_EOF_IN : in std_logic;
--- MAC_RXD_IN : in std_logic_vector(7 downto 0);
--- MAC_RX_EN_IN : in std_logic;
---
---
--- -- debug ports
--- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)
---);
--- END COMPONENT;
-
- SIGNAL CLK : std_logic;
- SIGNAL TEST_CLK : std_logic;
- SIGNAL RESET : std_logic;
- SIGNAL GSR_N : std_logic;
- SIGNAL STAGE_STAT_REGS_OUT : std_logic_vector(31 downto 0);
- SIGNAL STAGE_CTRL_REGS_IN : std_logic_vector(31 downto 0);
- SIGNAL IP_CFG_START_IN : std_logic;
- SIGNAL IP_CFG_BANK_SEL_IN : std_logic_vector(3 downto 0);
- SIGNAL IP_CFG_MEM_DATA_IN : std_logic_vector(31 downto 0);
- SIGNAL MR_RESET_IN : std_logic;
- SIGNAL MR_MODE_IN : std_logic;
- SIGNAL MR_RESTART_IN : std_logic;
- SIGNAL IP_CFG_MEM_CLK_OUT : std_logic;
- SIGNAL IP_CFG_DONE_OUT : std_logic;
- SIGNAL IP_CFG_MEM_ADDR_OUT : std_logic_vector(7 downto 0);
- SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);
- SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);
- SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);
- SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);
- SIGNAL CTS_START_READOUT_IN : std_logic;
- SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);
- SIGNAL CTS_DATAREADY_OUT : std_logic;
- SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;
- SIGNAL CTS_READ_IN : std_logic;
- SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);
- SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);
- SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);
- SIGNAL FEE_DATAREADY_IN : std_logic;
- SIGNAL FEE_READ_OUT : std_logic;
- SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);
- SIGNAL FEE_BUSY_IN : std_logic;
- SIGNAL SFP_RXD_P_IN : std_logic;
- SIGNAL SFP_RXD_N_IN : std_logic;
- SIGNAL SFP_TXD_P_OUT : std_logic;
- SIGNAL SFP_TXD_N_OUT : std_logic;
- SIGNAL SFP_REFCLK_P_IN : std_logic;
- SIGNAL SFP_REFCLK_N_IN : std_logic;
- SIGNAL SFP_PRSNT_N_IN : std_logic;
- SIGNAL SFP_LOS_IN : std_logic;
- SIGNAL SFP_TXDIS_OUT : std_logic;
- SIGNAL ANALYZER_DEBUG_OUT : std_logic_vector(63 downto 0);
- --gk 29.03.10
- signal SLV_ADDR_IN : std_logic_vector(7 downto 0);
- signal SLV_READ_IN : std_logic;
- signal SLV_WRITE_IN : std_logic;
- signal SLV_BUSY_OUT : std_logic;
- signal SLV_ACK_OUT : std_logic;
- signal SLV_DATA_IN : std_logic_vector(31 downto 0);
- signal SLV_DATA_OUT : std_logic_vector(31 downto 0);
- -- for simulation of receiving part only
- signal MAC_RX_EOF_IN : std_logic;
- signal MAC_RXD_IN : std_logic_vector(7 downto 0);
- signal MAC_RX_EN_IN : std_logic;
-
- signal reply_busy, reply_dataready : std_logic;
- signal reply_data : std_logic_vector(15 downto 0);
-
- signal RX_MAC_CLK : std_logic;
-
-
-BEGIN
-
-RX_MAC_CLK <= test_clk;
-
--- Please check and add your generic clause manually
- uut: trb_net16_gbe_buf
- GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 )
- PORT MAP(
- CLK => CLK,
- CLK_125_IN => '0',
- TEST_CLK => TEST_CLK,
- RESET => RESET,
- GSR_N => GSR_N,
- STAGE_STAT_REGS_OUT => STAGE_STAT_REGS_OUT,
- STAGE_CTRL_REGS_IN => STAGE_CTRL_REGS_IN,
- IP_CFG_START_IN => IP_CFG_START_IN,
- IP_CFG_BANK_SEL_IN => IP_CFG_BANK_SEL_IN,
- IP_CFG_MEM_DATA_IN => IP_CFG_MEM_DATA_IN,
- MR_RESET_IN => MR_RESET_IN,
- MR_MODE_IN => MR_MODE_IN,
- MR_RESTART_IN => MR_RESTART_IN,
- IP_CFG_MEM_CLK_OUT => IP_CFG_MEM_CLK_OUT,
- IP_CFG_DONE_OUT => IP_CFG_DONE_OUT,
- IP_CFG_MEM_ADDR_OUT => IP_CFG_MEM_ADDR_OUT,
- -- gk 29.03.10
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
- -- gk 22.04.10
- -- registers setup interface
- BUS_ADDR_IN => x"00",
- BUS_DATA_IN => x"0000_0000",
- BUS_DATA_OUT => open,
- BUS_WRITE_EN_IN => '0',
- BUS_READ_EN_IN => '0',
- BUS_ACK_OUT => open,
- -- gk 23.04.10
- LED_PACKET_SENT_OUT => open,
- LED_AN_DONE_N_OUT => open,
- --------------------------
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- SFP_RXD_P_IN => SFP_RXD_P_IN,
- SFP_RXD_N_IN => SFP_RXD_N_IN,
- SFP_TXD_P_OUT => SFP_TXD_P_OUT,
- SFP_TXD_N_OUT => SFP_TXD_N_OUT,
- SFP_REFCLK_P_IN => SFP_REFCLK_P_IN,
- SFP_REFCLK_N_IN => SFP_REFCLK_N_IN,
- SFP_PRSNT_N_IN => SFP_PRSNT_N_IN,
- SFP_LOS_IN => SFP_LOS_IN,
- SFP_TXDIS_OUT => SFP_TXDIS_OUT,
-
- MC_UNIQUE_ID_IN => (others => '0'),
- GSC_CLK_IN => test_clk,
- GSC_INIT_DATAREADY_OUT => open,
- GSC_INIT_DATA_OUT => open,
- GSC_INIT_PACKET_NUM_OUT => open,
- GSC_INIT_READ_IN => '0',
- GSC_REPLY_DATAREADY_IN => reply_dataready,
- GSC_REPLY_DATA_IN => reply_data, --(others => '0'),
- GSC_REPLY_PACKET_NUM_IN => (others => '0'),
- GSC_REPLY_READ_OUT => open,
- GSC_BUSY_IN => reply_busy,
-
- MAKE_RESET_OUT => open,
-
-
- -- for simulation of receiving part only
- MAC_RX_EOF_IN => MAC_RX_EOF_IN,
- MAC_RXD_IN => MAC_RXD_IN,
- MAC_RX_EN_IN => MAC_RX_EN_IN,
- ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT
- );
-
-
-
--- 100 MHz system clock
-CLOCK_GEN_PROC: process
-begin
- clk <= '1'; wait for 5.0 ns;
- clk <= '0'; wait for 5.0 ns;
-end process CLOCK_GEN_PROC;
-
--- 125 MHz MAC clock
-CLOCK2_GEN_PROC: process
-begin
- test_clk <= '1'; wait for 4.0 ns;
- test_clk <= '0'; wait for 4.0 ns;
-end process CLOCK2_GEN_PROC;
-
-
---SCTRL_TESTBENCH_PROC : process
---begin
---
---for j in 0 to 5000 loop
---
--- reply_dataready <= '0';
--- reply_busy <= '0';
--- reply_data <= (others => '0');
---
--- wait for 76 us;
---
--- for i in 0 to 1000 loop
---
--- wait until rising_edge(clk);
--- reply_dataready <= '1';
--- reply_busy <= '1';
--- reply_data <= std_logic_vector(to_unsigned(i, 16));
---
--- end loop;
--- wait until rising_edge(clk);
--- reply_dataready <= '0';
--- reply_busy <= '0';
---
--- wait for 13 us;
---end loop;
---
---end process SCTRL_TESTBENCH_PROC;
-
-
-
-
-
-
-
--- Testbench
-TESTBENCH_PROC: process
--- test data from TRBnet
-variable test_data_len : integer range 0 to 65535 := 1;
-variable test_loop_len : integer range 0 to 65535 := 0;
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";
-variable test_evt_len : unsigned(15 downto 0) := x"0000";
-variable test_data : unsigned(15 downto 0) := x"ffff";
-variable test_data2 : unsigned(7 downto 0) := x"ff";
-
-variable trigger_counter : unsigned(15 downto 0) := x"4710";
-variable trigger_loop : integer range 0 to 65535 := 15;
-
--- 1400 bytes MTU => 350 as limit for fragmentation
-variable max_event_size : real := 512.0;
-
-variable seed1 : positive; -- seed for random generator
-variable seed2 : positive; -- seed for random generator
-variable rand : real; -- random value (0.0 ... 1.0)
-variable int_rand : integer; -- random value, scaled to your needs
-variable cts_random_number : std_logic_vector(7 downto 0);
-variable up_down_switch : integer := 0;
-variable stim : std_logic_vector(15 downto 0);
-variable random_size : integer := 1;
--- RND test
---UNIFORM(seed1, seed2, rand);
---int_rand := INTEGER(TRUNC(rand*65536.0));
---stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
-
-begin
- -- Setup signals
- reset <= '0';
- gsr_n <= '1';
-
- stage_ctrl_regs_in <= x"0000_0000";
-
- --ip_cfg_start_in <= '0';
- --ip_cfg_bank_sel_in <= x"0";
- --ip_cfg_mem_data_in <= x"0000_0000";
- mr_reset_in <= '0';
- mr_mode_in <= '0';
- mr_restart_in <= '0';
- SLV_ADDR_IN <= x"00";
- SLV_READ_IN <= '0';
- SLV_WRITE_IN <= '0';
- SLV_DATA_IN <= x"0000_0000";
-
- sfp_los_in <= '0'; -- signal from SFP is present
- sfp_prsnt_n_in <= '0'; -- SFP itself is present
- sfp_refclk_n_in <= '0';
- sfp_refclk_p_in <= '1';
-
- cts_number_in <= x"0000";
- cts_code_in <= x"00";
- cts_information_in <= x"00";
- cts_readout_type_in <= x"0";
- cts_start_readout_in <= '0';
- cts_read_in <= '0';
-
- fee_data_in <= x"0000";
- fee_dataready_in <= '0';
- fee_status_bits_in <= x"1234_5678";
- fee_busy_in <= '0';
-
- MAC_RX_EN_IN <= '0';
- MAC_RX_EOF_IN <= '0';
- MAC_RXD_IN <= (others => '0');
-
-
- wait for 22 ns;
-
- -- Reset the whole stuff
- wait until rising_edge(clk);
- reset <= '1';
- gsr_n <= '0';
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- reset <= '0';
- gsr_n <= '1';
- wait until rising_edge(clk);
- --wait for 100 ns;
-
- -- Tests may start here
--- wait until ft_bsm_init_tst = x"7";
-
- --ip_cfg_start_in <= '1';
-
- wait for 700 us;
-
-
--------------------------------------------------------------------------------
--- Loop the transmissions
--------------------------------------------------------------------------------
- trigger_counter := x"4710";
- trigger_loop := 5000;
-
- wait until rising_edge(test_clk);
-
- -- FIRST FRAME UDP - DHCP Offer
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
--- MAC_RXD_IN <= x"02";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"be";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
--- MAC_RXD_IN <= x"00";
--- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- ip headers
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"5a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"49";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11"; -- udp
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
--- udp headers
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"43";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"2c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
--- dhcp data
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"fa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ce";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
-
- for i in 0 to 219 loop
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- end loop;
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"35";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
- wait for 1 us;
-
-
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <= '1';
--- dest mac
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"be";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- src mac
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"dd";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ee";
- wait until rising_edge(RX_MAC_CLK);
--- frame type
- MAC_RXD_IN <= x"08";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
--- ip headers
- MAC_RXD_IN <= x"45";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"5a";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"49";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ff";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"11"; -- udp
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"cc";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
--- udp headers
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"43";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"44";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"2c";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"aa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"bb";
--- dhcp data
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"06";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"fa";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"ce";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"c0";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"a8";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"10";
-
- for i in 0 to 219 loop
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- end loop;
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"35";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"01";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"02";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RXD_IN <= x"00";
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EOF_IN <= '1';
-
- wait until rising_edge(RX_MAC_CLK);
- MAC_RX_EN_IN <='0';
- MAC_RX_EOF_IN <= '0';
-
-
-
-
--- RECEIVE_LOOP: for J in 0 to 1 loop
---
--- wait for 200 ns;
---
--- -- IPU transmission starts
--- wait until rising_edge(test_clk);
---
--- test_data2 := x"ff";
--- MY_DATA_LOOP2: for k in 0 to 200 + (J * 10) loop
--- test_data2 := test_data2 + 1;
--- wait until rising_edge(test_clk);
--- MAC_RXD_IN <= std_logic_vector(test_data2);
--- MAC_RX_EN_IN <= '1';
--- end loop MY_DATA_LOOP2;
---
--- MAC_RX_EN_IN <= '0';
--- MAC_RXD_IN <= "00000000";
--- MAC_RX_EOF_IN <= '1';
--- wait until rising_edge(test_clk);
--- MAC_RX_EOF_IN <= '0';
---
--- --wait for 3 us;
---
--- end loop RECEIVE_LOOP;
- test_data_len := 20; -- + (1 - J) * 200;
-
--- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop
--- -- generate a real random byte for CTS
--- UNIFORM(seed1, seed2, rand);
--- int_rand := INTEGER(TRUNC(rand*256.0));
--- cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));
---
--- -- IPU transmission starts
--- wait until rising_edge(clk);
--- cts_number_in <= std_logic_vector( trigger_counter );
--- cts_code_in <= cts_random_number;
--- cts_information_in <= x"d2"; -- cts_information_in <= x"de"; -- gk 29.03.10
--- cts_readout_type_in <= x"1";
--- cts_start_readout_in <= '1';
--- wait until rising_edge(clk);
--- wait for 400 ns;
---
--- wait until rising_edge(clk);
--- fee_busy_in <= '1';
--- wait for 300 ns;
--- wait until rising_edge(clk);
---
--- -- ONE DATA TRANSMISSION
--- -- dice a length
--- UNIFORM(seed1, seed2, rand);
--- --test_data_len := INTEGER(TRUNC(rand * 800.0)) + 1;
---
--- --test_data_len := 9685;
----- test_data_len := 2000; -- + (1 - J) * 200;
---
--- --test_data_len := INTEGER(TRUNC(rand*7500.0)); --20; -- + (1 - J) * 200;
--- test_data_len := 349;
---
--- -- calculate the needed variables
--- test_loop_len := 2*(test_data_len - 1) + 1;
--- test_hdr_len := to_unsigned( test_data_len + 1, 16 );
--- test_evt_len := to_unsigned( test_data_len, 16 );
---
--- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)
--- fee_dataready_in <= '1';
--- fee_data_in <= x"1111"; --x"10" & cts_random_number;
--- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word
--- fee_dataready_in <= '0';
--- wait until rising_edge(clk); -- BLA
--- wait until rising_edge(clk); -- BLA
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- fee_dataready_in <= '1';
--- fee_data_in <= x"2222"; --std_logic_vector( trigger_counter );
--- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word
--- fee_dataready_in <= '0';
--- wait until rising_edge(clk); -- BLA
--- wait until rising_edge(clk); -- BLA
--- wait until rising_edge(clk); -- BLA
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- fee_dataready_in <= '1';
--- fee_data_in <= std_logic_vector( test_hdr_len );
--- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word
--- fee_data_in <= x"3333"; --x"ff21";
--- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word
--- fee_dataready_in <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- fee_dataready_in <= '1';
--- fee_data_in <= std_logic_vector( test_evt_len );
--- wait until rising_edge(clk) and (fee_read_out = '1');
--- fee_data_in <= x"ff22";
--- wait until rising_edge(clk) and (fee_read_out = '1');
--- fee_dataready_in <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
---
--- test_data := x"ffff";
--- MY_DATA_LOOP: for J in 0 to test_loop_len loop
--- test_data := test_data + 1;
--- wait until rising_edge(clk) and (fee_read_out = '1');
--- fee_data_in <= std_logic_vector(test_data);
----- if( (test_data MOD 5) = 0 ) then
----- fee_dataready_in <= '0';
----- wait until rising_edge(clk);
----- wait until rising_edge(clk);
----- wait until rising_edge(clk);
----- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
------- wait until rising_edge(clk);
----- fee_dataready_in <= '1';
----- else
----- fee_dataready_in <= '1';
----- end if;
--- fee_dataready_in <= '1';
--- end loop MY_DATA_LOOP;
--- -- there must be padding words to get multiple of four LWs
---
--- wait until rising_edge(clk);
--- fee_dataready_in <= '0';
--- fee_data_in <= x"0000";
---
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- fee_busy_in <= '0';
---
---
--- trigger_loop := trigger_loop + 1;
--- trigger_counter := trigger_counter + 1;
---
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- cts_read_in <= '1';
--- wait until rising_edge(clk);
--- cts_read_in <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- cts_start_readout_in <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
---
--- test_data_len := test_data_len + 111;
---
--- --wait for 8 us;
---
--- end loop MY_TRIGGER_LOOP;
-
-
-
-
-
-
-
-
-
--- wait for 8 us;
--------------------------------------------------------------------------------
--- end of loop
--------------------------------------------------------------------------------
- -- Stay a while... stay forever!!!
- wait;
-
-end process TESTBENCH_PROC;
-
-END;
-
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT ip_configurator\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- START_CONFIG_IN : IN std_logic;\r
- BANK_SELECT_IN : IN std_logic_vector(3 downto 0);\r
- MEM_DATA_IN : IN std_logic_vector(31 downto 0); \r
- CONFIG_DONE_OUT : OUT std_logic;\r
- MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0);\r
- MEM_CLK_OUT : OUT std_logic;\r
- DEST_MAC_OUT : OUT std_logic_vector(47 downto 0);\r
- DEST_IP_OUT : OUT std_logic_vector(31 downto 0);\r
- DEST_UDP_OUT : OUT std_logic_vector(15 downto 0);\r
- SRC_MAC_OUT : OUT std_logic_vector(47 downto 0);\r
- SRC_IP_OUT : OUT std_logic_vector(31 downto 0);\r
- SRC_UDP_OUT : OUT std_logic_vector(15 downto 0);\r
- MTU_OUT : OUT std_logic_vector(15 downto 0);\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL START_CONFIG_IN : std_logic;\r
- SIGNAL BANK_SELECT_IN : std_logic_vector(3 downto 0);\r
- SIGNAL CONFIG_DONE_OUT : std_logic;\r
- SIGNAL MEM_ADDR_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL MEM_DATA_IN : std_logic_vector(31 downto 0);\r
- SIGNAL MEM_CLK_OUT : std_logic;\r
- SIGNAL DEST_MAC_OUT : std_logic_vector(47 downto 0);\r
- SIGNAL DEST_IP_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL DEST_UDP_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL SRC_MAC_OUT : std_logic_vector(47 downto 0);\r
- SIGNAL SRC_IP_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL SRC_UDP_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL MTU_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: ip_configurator PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- START_CONFIG_IN => START_CONFIG_IN,\r
- BANK_SELECT_IN => BANK_SELECT_IN,\r
- CONFIG_DONE_OUT => CONFIG_DONE_OUT,\r
- MEM_ADDR_OUT => MEM_ADDR_OUT,\r
- MEM_DATA_IN => MEM_DATA_IN,\r
- MEM_CLK_OUT => MEM_CLK_OUT,\r
- DEST_MAC_OUT => DEST_MAC_OUT,\r
- DEST_IP_OUT => DEST_IP_OUT,\r
- DEST_UDP_OUT => DEST_UDP_OUT,\r
- SRC_MAC_OUT => SRC_MAC_OUT,\r
- SRC_IP_OUT => SRC_IP_OUT,\r
- SRC_UDP_OUT => SRC_UDP_OUT,\r
- MTU_OUT => MTU_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
-\r
-\r
-CLK_GEN_PROC: process\r
-begin\r
- clk <= '0'; wait for 5.0 ns;\r
- clk <= '1'; wait for 5.0 ns;\r
-end process CLK_GEN_PROC;\r
-\r
-THE_TESTBENCH: process\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- start_config_in <= '0';\r
- bank_select_in <= x"0";\r
- mem_data_in <= x"0000_0000";\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait for 100 ns;\r
- wait until rising_edge(clk);\r
- \r
- -- Tests may start now\r
- wait until rising_edge(clk);\r
- start_config_in <= '1';\r
- wait until mem_addr_out(3 downto 0) = x"1";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"4902d745"; -- dest MAC low\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"00006cf0"; -- dest MAC high\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"c0a80002"; -- dest IP\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"0000c350"; -- dest port\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"eeeeeeee"; -- src MAC low\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"0000eeee"; -- src MAC high\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"c0a80005"; -- src IP\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"0000c350"; -- src port\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"00000578"; -- MTU\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"99999999";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"aaaaaaaa";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"bbbbbbbb";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"cccccccc";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"dddddddd";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"eeeeeeee";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"ffffffff";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"00000000";\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- start_config_in <= '0';\r
- \r
- -- Stay a while... stay forever!!! Muahahaha!!!!!\r
- wait;\r
-end process THE_TESTBENCH;\r
-\r
-\r
-END;\r
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.math_real.all;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT trb_net16_ipu2gbe\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- START_CONFIG_OUT : OUT std_logic;\r
- BANK_SELECT_OUT : OUT std_logic_vector(3 downto 0);\r
- CONFIG_DONE_IN : IN std_logic;\r
- DATA_GBE_ENABLE_IN : IN std_logic;\r
- DATA_IPU_ENABLE_IN : IN std_logic;\r
- MULTI_EVT_ENABLE_IN : IN std_logic;\r
- CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
- CTS_CODE_IN : IN std_logic_vector(7 downto 0);\r
- CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
- CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);\r
- CTS_START_READOUT_IN : IN std_logic;\r
- CTS_READ_IN : IN std_logic;\r
- FEE_DATA_IN : IN std_logic_vector(15 downto 0);\r
- FEE_DATAREADY_IN : IN std_logic;\r
- FEE_BUSY_IN : IN std_logic;\r
- FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);\r
- PC_READY_IN : IN std_logic; \r
- CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- CTS_DATAREADY_OUT : OUT std_logic;\r
- CTS_READOUT_FINISHED_OUT : OUT std_logic;\r
- CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
- CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
- FEE_READ_OUT : OUT std_logic;\r
- PC_WR_EN_OUT : OUT std_logic;\r
- PC_DATA_OUT : OUT std_logic_vector(7 downto 0);\r
- PC_SOS_OUT : OUT std_logic;\r
- PC_EOD_OUT : OUT std_logic;\r
- PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_PADDING_OUT : OUT std_logic;\r
- BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0);\r
- BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0);\r
- DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0);\r
- DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RD_EN_OUT : OUT std_logic;\r
- DBG_SF_WR_EN_OUT : OUT std_logic;\r
- DBG_SF_EMPTY_OUT : OUT std_logic;\r
- DBG_SF_AEMPTY_OUT : OUT std_logic;\r
- DBG_SF_FULL_OUT : OUT std_logic;\r
- DBG_SF_AFULL_OUT : OUT std_logic;\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL START_CONFIG_OUT : std_logic;\r
- SIGNAL BANK_SELECT_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL CONFIG_DONE_IN : std_logic;\r
- SIGNAL DATA_GBE_ENABLE_IN : std_logic;\r
- SIGNAL DATA_IPU_ENABLE_IN : std_logic;\r
- SIGNAL MULTI_EVT_ENABLE_IN : std_logic;\r
- SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);\r
- SIGNAL CTS_START_READOUT_IN : std_logic;\r
- SIGNAL CTS_READ_IN : std_logic;\r
- SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL CTS_DATAREADY_OUT : std_logic;\r
- SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;\r
- SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);\r
- SIGNAL FEE_DATAREADY_IN : std_logic;\r
- SIGNAL FEE_READ_OUT : std_logic;\r
- SIGNAL FEE_BUSY_IN : std_logic;\r
- SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);\r
- SIGNAL PC_WR_EN_OUT : std_logic;\r
- SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL PC_READY_IN : std_logic;\r
- SIGNAL PC_SOS_OUT : std_logic;\r
- SIGNAL PC_EOD_OUT : std_logic;\r
- SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_PADDING_OUT : std_logic;\r
- SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0);\r
- SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0);\r
- SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RD_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_WR_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_EMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_AEMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_FULL_OUT : std_logic;\r
- SIGNAL DBG_SF_AFULL_OUT : std_logic;\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: trb_net16_ipu2gbe PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- START_CONFIG_OUT => START_CONFIG_OUT,\r
- BANK_SELECT_OUT => BANK_SELECT_OUT,\r
- CONFIG_DONE_IN => CONFIG_DONE_IN,\r
- DATA_GBE_ENABLE_IN => DATA_GBE_ENABLE_IN,\r
- DATA_IPU_ENABLE_IN => DATA_IPU_ENABLE_IN,\r
- MULTI_EVT_ENABLE_IN => MULTI_EVT_ENABLE_IN,\r
- CTS_NUMBER_IN => CTS_NUMBER_IN,\r
- CTS_CODE_IN => CTS_CODE_IN,\r
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,\r
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,\r
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,\r
- CTS_READ_IN => CTS_READ_IN,\r
- CTS_DATA_OUT => CTS_DATA_OUT,\r
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,\r
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,\r
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,\r
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,\r
- FEE_DATA_IN => FEE_DATA_IN,\r
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,\r
- FEE_READ_OUT => FEE_READ_OUT,\r
- FEE_BUSY_IN => FEE_BUSY_IN,\r
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,\r
- PC_WR_EN_OUT => PC_WR_EN_OUT,\r
- PC_DATA_OUT => PC_DATA_OUT,\r
- PC_READY_IN => PC_READY_IN,\r
- PC_SOS_OUT => PC_SOS_OUT,\r
- PC_EOD_OUT => PC_EOD_OUT,\r
- PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT,\r
- PC_TRIG_NR_OUT => PC_TRIG_NR_OUT,\r
- PC_PADDING_OUT => PC_PADDING_OUT,\r
- BSM_SAVE_OUT => BSM_SAVE_OUT,\r
- BSM_LOAD_OUT => BSM_LOAD_OUT,\r
- DBG_REM_CTR_OUT => DBG_REM_CTR_OUT,\r
- DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT,\r
- DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT,\r
- DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT,\r
- DBG_SF_DATA_OUT => DBG_SF_DATA_OUT,\r
- DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT,\r
- DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT,\r
- DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT,\r
- DBG_SF_AEMPTY_OUT => DBG_SF_AEMPTY_OUT,\r
- DBG_SF_FULL_OUT => DBG_SF_FULL_OUT,\r
- DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
-\r
-CLOCK_GEN: process\r
-begin\r
- clk <= '1'; wait for 5.0 ns;\r
- clk <= '0'; wait for 5.0 ns;\r
-end process CLOCK_GEN;\r
-\r
-PC_READY_PROC: process\r
-begin\r
- pc_ready_in <= '0';\r
- wait for 500 ns;\r
- pc_ready_in <= '1';\r
- wait for 500 ns;\r
- pc_ready_in <= '0';\r
- wait for 99 us;\r
-end process PC_READY_PROC;\r
-\r
--- Testbench\r
-TESTBENCH_PROC: process\r
--- test data from TRBnet\r
-variable test_data_len : integer range 0 to 65535 := 1;\r
-variable test_loop_len : integer range 0 to 65535 := 0;\r
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";\r
-variable test_evt_len : unsigned(15 downto 0) := x"0000";\r
-variable test_data : unsigned(15 downto 0) := x"ffff";\r
-\r
-variable trigger_counter : unsigned(15 downto 0) := x"4710";\r
-variable trigger_loop : integer range 0 to 65535 := 15;\r
-\r
--- 1400 bytes MTU => 350 as limit for fragmentation\r
---variable max_event_size : real := 512.0;\r
-variable max_event_size : real := 17.0;\r
-\r
-variable seed1 : positive; -- seed for random generator\r
-variable seed2 : positive; -- seed for random generator\r
-variable rand : real; -- random value (0.0 ... 1.0)\r
-variable int_rand : integer; -- random value, scaled to your needs\r
-variable cts_random_number : std_logic_vector(7 downto 0);\r
-\r
-variable stim : std_logic_vector(15 downto 0);\r
-\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- cts_number_in <= x"0000";\r
- cts_code_in <= x"00";\r
- cts_information_in <= x"00";\r
- cts_readout_type_in <= x"0";\r
- cts_start_readout_in <= '0';\r
- cts_read_in <= '0';\r
- fee_data_in <= x"0000";\r
- fee_dataready_in <= '0';\r
- fee_status_bits_in <= x"0000_0000";\r
- fee_busy_in <= '0';\r
--- pc_ready_in <= '0';\r
-\r
- config_done_in <= '1';\r
- data_gbe_enable_in <= '1';\r
- data_ipu_enable_in <= '0';\r
- multi_evt_enable_in <= '0';\r
-\r
- wait for 22 ns;\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- wait for 200 ns;\r
-\r
----------------------------\r
-\r
--------------------------------------------------------------------------------\r
--- Loop the transmissions\r
--------------------------------------------------------------------------------\r
- trigger_counter := x"4710";\r
- trigger_loop := 2;\r
-\r
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop\r
- -- generate a real random byte for CTS\r
- UNIFORM(seed1, seed2, rand);\r
- int_rand := INTEGER(TRUNC(rand*256.0));\r
- cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));\r
- \r
- -- IPU transmission starts\r
- wait until rising_edge(clk);\r
- cts_number_in <= std_logic_vector( trigger_counter );\r
- cts_code_in <= cts_random_number;\r
- cts_information_in <= x"de";\r
- cts_readout_type_in <= x"1";\r
- cts_start_readout_in <= '1';\r
- wait until rising_edge(clk);\r
- wait for 400 ns;\r
-\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '1';\r
- wait for 300 ns;\r
- wait until rising_edge(clk);\r
-\r
- -- ONE DATA TRANSMISSION\r
- -- dice a length\r
- UNIFORM(seed1, seed2, rand);\r
- test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;\r
- \r
--- test_data_len := 9685;\r
- \r
- -- calculate the needed variables\r
- test_loop_len := 2*(test_data_len - 1) + 1;\r
- test_hdr_len := to_unsigned( test_data_len + 1, 16 );\r
- test_evt_len := to_unsigned( test_data_len, 16 );\r
-\r
- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)\r
- fee_dataready_in <= '1';\r
- fee_data_in <= x"10" & cts_random_number;\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( trigger_counter );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_hdr_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word\r
- fee_data_in <= x"ff21";\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_evt_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_data_in <= x"ff22"; \r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- test_data := x"ffff";\r
- MY_DATA_LOOP: for J in 0 to test_loop_len loop\r
- test_data := test_data + 1;\r
- wait until rising_edge(clk) and (fee_read_out = '1'); --\r
- fee_data_in <= std_logic_vector(test_data); \r
- if( (test_data MOD 5) = 0 ) then\r
- fee_dataready_in <= '0';\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- else\r
- fee_dataready_in <= '1';\r
- end if;\r
- end loop MY_DATA_LOOP;\r
- -- there must be padding words to get multiple of four LWs\r
- \r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '0';\r
- fee_data_in <= x"0000"; \r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '0';\r
-\r
-\r
- trigger_loop := trigger_loop + 1;\r
- trigger_counter := trigger_counter + 1;\r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_read_in <= '1';\r
- wait until rising_edge(clk);\r
- cts_read_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_start_readout_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk); \r
- \r
- --wait for 8 us;\r
-\r
- end loop MY_TRIGGER_LOOP;\r
-\r
-\r
-\r
----------------------------\r
----------------------------\r
- wait for 300 ns;\r
-\r
- wait;\r
-\r
- -- Start packet_constructor\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
--- pc_ready_in <= '1';\r
- wait until rising_edge(clk);\r
-\r
- wait until rising_edge(clk);\r
- wait until pc_eod_out = '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
--- pc_ready_in <= '0';\r
-\r
- -- Stay a while... stay forever!!!\r
- wait; \r
- \r
-end process TESTBENCH_PROC;\r
-\r
-\r
-END;\r
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.math_real.all;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT trb_net16_ipu2gbe_new\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- START_CONFIG_OUT : OUT std_logic;\r
- BANK_SELECT_OUT : OUT std_logic_vector(3 downto 0);\r
- CONFIG_DONE_IN : IN std_logic;\r
- DATA_GBE_ENABLE_IN : IN std_logic;\r
- DATA_IPU_ENABLE_IN : IN std_logic;\r
- MULTI_EVT_ENABLE_IN : IN std_logic;\r
- CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
- CTS_CODE_IN : IN std_logic_vector(7 downto 0);\r
- CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
- CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);\r
- CTS_START_READOUT_IN : IN std_logic;\r
- CTS_READ_IN : IN std_logic;\r
- FEE_DATA_IN : IN std_logic_vector(15 downto 0);\r
- FEE_DATAREADY_IN : IN std_logic;\r
- FEE_BUSY_IN : IN std_logic;\r
- FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);\r
- PC_READY_IN : IN std_logic; \r
- CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- CTS_DATAREADY_OUT : OUT std_logic;\r
- CTS_READOUT_FINISHED_OUT : OUT std_logic;\r
- CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
- CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
- FEE_READ_OUT : OUT std_logic;\r
- PC_WR_EN_OUT : OUT std_logic;\r
- PC_DATA_OUT : OUT std_logic_vector(7 downto 0);\r
- PC_SOS_OUT : OUT std_logic;\r
- PC_EOD_OUT : OUT std_logic;\r
- PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_PADDING_OUT : OUT std_logic;\r
- BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0);\r
- BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0);\r
- DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0);\r
- DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RD_EN_OUT : OUT std_logic;\r
- DBG_SF_WR_EN_OUT : OUT std_logic;\r
- DBG_SF_EMPTY_OUT : OUT std_logic;\r
- DBG_SF_AEMPTY_OUT : OUT std_logic;\r
- DBG_SF_FULL_OUT : OUT std_logic;\r
- DBG_SF_AFULL_OUT : OUT std_logic;\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL START_CONFIG_OUT : std_logic;\r
- SIGNAL BANK_SELECT_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL CONFIG_DONE_IN : std_logic;\r
- SIGNAL DATA_GBE_ENABLE_IN : std_logic;\r
- SIGNAL DATA_IPU_ENABLE_IN : std_logic;\r
- SIGNAL MULTI_EVT_ENABLE_IN : std_logic;\r
- SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);\r
- SIGNAL CTS_START_READOUT_IN : std_logic;\r
- SIGNAL CTS_READ_IN : std_logic;\r
- SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL CTS_DATAREADY_OUT : std_logic;\r
- SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;\r
- SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);\r
- SIGNAL FEE_DATAREADY_IN : std_logic;\r
- SIGNAL FEE_READ_OUT : std_logic;\r
- SIGNAL FEE_BUSY_IN : std_logic;\r
- SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);\r
- SIGNAL PC_WR_EN_OUT : std_logic;\r
- SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL PC_READY_IN : std_logic;\r
- SIGNAL PC_SOS_OUT : std_logic;\r
- SIGNAL PC_EOD_OUT : std_logic;\r
- SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_PADDING_OUT : std_logic;\r
- SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0);\r
- SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0);\r
- SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RD_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_WR_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_EMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_AEMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_FULL_OUT : std_logic;\r
- SIGNAL DBG_SF_AFULL_OUT : std_logic;\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: trb_net16_ipu2gbe_new PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- START_CONFIG_OUT => START_CONFIG_OUT,\r
- BANK_SELECT_OUT => BANK_SELECT_OUT,\r
- CONFIG_DONE_IN => CONFIG_DONE_IN,\r
- DATA_GBE_ENABLE_IN => DATA_GBE_ENABLE_IN,\r
- DATA_IPU_ENABLE_IN => DATA_IPU_ENABLE_IN,\r
- MULTI_EVT_ENABLE_IN => MULTI_EVT_ENABLE_IN,\r
- CTS_NUMBER_IN => CTS_NUMBER_IN,\r
- CTS_CODE_IN => CTS_CODE_IN,\r
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,\r
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,\r
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,\r
- CTS_READ_IN => CTS_READ_IN,\r
- CTS_DATA_OUT => CTS_DATA_OUT,\r
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,\r
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,\r
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,\r
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,\r
- FEE_DATA_IN => FEE_DATA_IN,\r
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,\r
- FEE_READ_OUT => FEE_READ_OUT,\r
- FEE_BUSY_IN => FEE_BUSY_IN,\r
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,\r
- PC_WR_EN_OUT => PC_WR_EN_OUT,\r
- PC_DATA_OUT => PC_DATA_OUT,\r
- PC_READY_IN => PC_READY_IN,\r
- PC_SOS_OUT => PC_SOS_OUT,\r
- PC_EOD_OUT => PC_EOD_OUT,\r
- PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT,\r
- PC_TRIG_NR_OUT => PC_TRIG_NR_OUT,\r
- PC_PADDING_OUT => PC_PADDING_OUT,\r
- BSM_SAVE_OUT => BSM_SAVE_OUT,\r
- BSM_LOAD_OUT => BSM_LOAD_OUT,\r
- DBG_REM_CTR_OUT => DBG_REM_CTR_OUT,\r
- DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT,\r
- DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT,\r
- DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT,\r
- DBG_SF_DATA_OUT => DBG_SF_DATA_OUT,\r
- DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT,\r
- DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT,\r
- DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT,\r
- DBG_SF_AEMPTY_OUT => DBG_SF_AEMPTY_OUT,\r
- DBG_SF_FULL_OUT => DBG_SF_FULL_OUT,\r
- DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
-\r
-CLOCK_GEN: process\r
-begin\r
- clk <= '1'; wait for 5.0 ns;\r
- clk <= '0'; wait for 5.0 ns;\r
-end process CLOCK_GEN;\r
-\r
-PC_READY_PROC: process\r
-begin\r
- pc_ready_in <= '0';\r
- wait for 500 ns;\r
- pc_ready_in <= '1';\r
- wait for 500 ns;\r
- pc_ready_in <= '0';\r
- wait for 99 us;\r
-end process PC_READY_PROC;\r
-\r
--- Testbench\r
-TESTBENCH_PROC: process\r
--- test data from TRBnet\r
-variable test_data_len : integer range 0 to 65535 := 1;\r
-variable test_loop_len : integer range 0 to 65535 := 0;\r
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";\r
-variable test_evt_len : unsigned(15 downto 0) := x"0000";\r
-variable test_data : unsigned(15 downto 0) := x"ffff";\r
-\r
-variable trigger_counter : unsigned(15 downto 0) := x"4710";\r
-variable trigger_loop : integer range 0 to 65535 := 15;\r
-\r
--- 1400 bytes MTU => 350 as limit for fragmentation\r
---variable max_event_size : real := 512.0;\r
-variable max_event_size : real := 17.0;\r
-\r
-variable seed1 : positive; -- seed for random generator\r
-variable seed2 : positive; -- seed for random generator\r
-variable rand : real; -- random value (0.0 ... 1.0)\r
-variable int_rand : integer; -- random value, scaled to your needs\r
-variable cts_random_number : std_logic_vector(7 downto 0);\r
-\r
-variable stim : std_logic_vector(15 downto 0);\r
-\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- cts_number_in <= x"0000";\r
- cts_code_in <= x"00";\r
- cts_information_in <= x"00";\r
- cts_readout_type_in <= x"0";\r
- cts_start_readout_in <= '0';\r
- cts_read_in <= '0';\r
- fee_data_in <= x"0000";\r
- fee_dataready_in <= '0';\r
- fee_status_bits_in <= x"0000_0000";\r
- fee_busy_in <= '0';\r
--- pc_ready_in <= '0';\r
-\r
- config_done_in <= '1';\r
- data_gbe_enable_in <= '1';\r
- data_ipu_enable_in <= '0';\r
- multi_evt_enable_in <= '0';\r
-\r
- wait for 22 ns;\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- wait for 200 ns;\r
-\r
----------------------------\r
-\r
--------------------------------------------------------------------------------\r
--- Loop the transmissions\r
--------------------------------------------------------------------------------\r
- trigger_counter := x"4710";\r
- trigger_loop := 2;\r
-\r
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop\r
- -- generate a real random byte for CTS\r
- UNIFORM(seed1, seed2, rand);\r
- int_rand := INTEGER(TRUNC(rand*256.0));\r
- cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));\r
- \r
- -- IPU transmission starts\r
- wait until rising_edge(clk);\r
- cts_number_in <= std_logic_vector( trigger_counter );\r
- cts_code_in <= cts_random_number;\r
- cts_information_in <= x"de";\r
- cts_readout_type_in <= x"1";\r
- cts_start_readout_in <= '1';\r
- wait until rising_edge(clk);\r
- wait for 400 ns;\r
-\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '1';\r
- wait for 300 ns;\r
- wait until rising_edge(clk);\r
-\r
- -- ONE DATA TRANSMISSION\r
- -- dice a length\r
- UNIFORM(seed1, seed2, rand);\r
- test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;\r
- \r
--- test_data_len := 9685;\r
- \r
- -- calculate the needed variables\r
- test_loop_len := 2*(test_data_len - 1) + 1;\r
- test_hdr_len := to_unsigned( test_data_len + 1, 16 );\r
- test_evt_len := to_unsigned( test_data_len, 16 );\r
-\r
- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)\r
- fee_dataready_in <= '1';\r
- fee_data_in <= x"10" & cts_random_number;\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word\r
--- fee_dataready_in <= '0';\r
--- wait until rising_edge(clk); -- BLA\r
--- wait until rising_edge(clk); -- BLA\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( trigger_counter );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_hdr_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word\r
- fee_data_in <= x"ff21";\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_evt_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_data_in <= x"ff22"; \r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- test_data := x"ffff";\r
- MY_DATA_LOOP: for J in 0 to test_loop_len loop\r
- test_data := test_data + 1;\r
- wait until rising_edge(clk) and (fee_read_out = '1'); --\r
- fee_data_in <= std_logic_vector(test_data); \r
- if( (test_data MOD 5) = 0 ) then\r
- fee_dataready_in <= '0';\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- else\r
- fee_dataready_in <= '1';\r
- end if;\r
- end loop MY_DATA_LOOP;\r
- -- there must be padding words to get multiple of four LWs\r
- \r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '0';\r
- fee_data_in <= x"0000"; \r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '0';\r
-\r
-\r
- trigger_loop := trigger_loop + 1;\r
- trigger_counter := trigger_counter + 1;\r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_read_in <= '1';\r
- wait until rising_edge(clk);\r
- cts_read_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_start_readout_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk); \r
- \r
- --wait for 8 us;\r
-\r
- end loop MY_TRIGGER_LOOP;\r
-\r
-\r
-\r
----------------------------\r
----------------------------\r
- wait for 300 ns;\r
-\r
- wait;\r
-\r
- -- Start packet_constructor\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
--- pc_ready_in <= '1';\r
- wait until rising_edge(clk);\r
-\r
- wait until rising_edge(clk);\r
- wait until pc_eod_out = '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
--- pc_ready_in <= '0';\r
-\r
- -- Stay a while... stay forever!!!\r
- wait; \r
- \r
-end process TESTBENCH_PROC;\r
-\r
-\r
-END;\r
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.math_real.all;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT trb_net16_ipu2gbe\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- START_CONFIG_OUT : OUT std_logic;\r
- BANK_SELECT_OUT : OUT std_logic_vector(3 downto 0);\r
- CONFIG_DONE_IN : IN std_logic;\r
- DATA_GBE_ENABLE_IN : IN std_logic;\r
- DATA_IPU_ENABLE_IN : IN std_logic;\r
- MULTI_EVT_ENABLE_IN : IN std_logic;\r
- CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
- CTS_CODE_IN : IN std_logic_vector(7 downto 0);\r
- CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
- CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);\r
- CTS_START_READOUT_IN : IN std_logic;\r
- CTS_READ_IN : IN std_logic;\r
- FEE_DATA_IN : IN std_logic_vector(15 downto 0);\r
- FEE_DATAREADY_IN : IN std_logic;\r
- FEE_BUSY_IN : IN std_logic;\r
- FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);\r
- PC_READY_IN : IN std_logic; \r
- CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- CTS_DATAREADY_OUT : OUT std_logic;\r
- CTS_READOUT_FINISHED_OUT : OUT std_logic;\r
- CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
- CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
- FEE_READ_OUT : OUT std_logic;\r
- PC_WR_EN_OUT : OUT std_logic;\r
- PC_DATA_OUT : OUT std_logic_vector(7 downto 0);\r
- PC_SOS_OUT : OUT std_logic;\r
- PC_EOD_OUT : OUT std_logic;\r
- PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_PADDING_OUT : OUT std_logic;\r
- BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0);\r
- BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0);\r
- DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0);\r
- DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RD_EN_OUT : OUT std_logic;\r
- DBG_SF_WR_EN_OUT : OUT std_logic;\r
- DBG_SF_EMPTY_OUT : OUT std_logic;\r
- DBG_SF_AEMPTY_OUT : OUT std_logic;\r
- DBG_SF_FULL_OUT : OUT std_logic;\r
- DBG_SF_AFULL_OUT : OUT std_logic;\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL START_CONFIG_OUT : std_logic;\r
- SIGNAL BANK_SELECT_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL CONFIG_DONE_IN : std_logic;\r
- SIGNAL DATA_GBE_ENABLE_IN : std_logic;\r
- SIGNAL DATA_IPU_ENABLE_IN : std_logic;\r
- SIGNAL MULTI_EVT_ENABLE_IN : std_logic;\r
- SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);\r
- SIGNAL CTS_START_READOUT_IN : std_logic;\r
- SIGNAL CTS_READ_IN : std_logic;\r
- SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL CTS_DATAREADY_OUT : std_logic;\r
- SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;\r
- SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);\r
- SIGNAL FEE_DATAREADY_IN : std_logic;\r
- SIGNAL FEE_READ_OUT : std_logic;\r
- SIGNAL FEE_BUSY_IN : std_logic;\r
- SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);\r
- SIGNAL PC_WR_EN_OUT : std_logic;\r
- SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL PC_READY_IN : std_logic;\r
- SIGNAL PC_SOS_OUT : std_logic;\r
- SIGNAL PC_EOD_OUT : std_logic;\r
- SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_PADDING_OUT : std_logic;\r
- SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0);\r
- SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0);\r
- SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RD_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_WR_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_EMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_AEMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_FULL_OUT : std_logic;\r
- SIGNAL DBG_SF_AFULL_OUT : std_logic;\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: trb_net16_ipu2gbe PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- START_CONFIG_OUT => START_CONFIG_OUT,\r
- BANK_SELECT_OUT => BANK_SELECT_OUT,\r
- CONFIG_DONE_IN => CONFIG_DONE_IN,\r
- DATA_GBE_ENABLE_IN => DATA_GBE_ENABLE_IN,\r
- DATA_IPU_ENABLE_IN => DATA_IPU_ENABLE_IN,\r
- MULTI_EVT_ENABLE_IN => MULTI_EVT_ENABLE_IN,\r
- CTS_NUMBER_IN => CTS_NUMBER_IN,\r
- CTS_CODE_IN => CTS_CODE_IN,\r
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,\r
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,\r
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,\r
- CTS_READ_IN => CTS_READ_IN,\r
- CTS_DATA_OUT => CTS_DATA_OUT,\r
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,\r
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,\r
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,\r
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,\r
- FEE_DATA_IN => FEE_DATA_IN,\r
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,\r
- FEE_READ_OUT => FEE_READ_OUT,\r
- FEE_BUSY_IN => FEE_BUSY_IN,\r
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,\r
- PC_WR_EN_OUT => PC_WR_EN_OUT,\r
- PC_DATA_OUT => PC_DATA_OUT,\r
- PC_READY_IN => PC_READY_IN,\r
- PC_SOS_OUT => PC_SOS_OUT,\r
- PC_EOD_OUT => PC_EOD_OUT,\r
- PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT,\r
- PC_TRIG_NR_OUT => PC_TRIG_NR_OUT,\r
- PC_PADDING_OUT => PC_PADDING_OUT,\r
- BSM_SAVE_OUT => BSM_SAVE_OUT,\r
- BSM_LOAD_OUT => BSM_LOAD_OUT,\r
- DBG_REM_CTR_OUT => DBG_REM_CTR_OUT,\r
- DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT,\r
- DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT,\r
- DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT,\r
- DBG_SF_DATA_OUT => DBG_SF_DATA_OUT,\r
- DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT,\r
- DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT,\r
- DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT,\r
- DBG_SF_AEMPTY_OUT => DBG_SF_AEMPTY_OUT,\r
- DBG_SF_FULL_OUT => DBG_SF_FULL_OUT,\r
- DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
-\r
-CLOCK_GEN: process\r
-begin\r
- clk <= '1'; wait for 5.0 ns;\r
- clk <= '0'; wait for 5.0 ns;\r
-end process CLOCK_GEN;\r
-\r
-PC_READY_PROC: process\r
-begin\r
- pc_ready_in <= '0';\r
- wait for 500 ns;\r
- pc_ready_in <= '1';\r
- wait for 500 ns;\r
- pc_ready_in <= '0';\r
- wait for 99 us;\r
-end process PC_READY_PROC;\r
-\r
--- Testbench\r
-TESTBENCH_PROC: process\r
--- test data from TRBnet\r
-variable test_data_len : integer range 0 to 65535 := 1;\r
-variable test_loop_len : integer range 0 to 65535 := 0;\r
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";\r
-variable test_evt_len : unsigned(15 downto 0) := x"0000";\r
-variable test_data : unsigned(15 downto 0) := x"ffff";\r
-\r
-variable trigger_counter : unsigned(15 downto 0) := x"4710";\r
-variable trigger_loop : integer range 0 to 65535 := 15;\r
-\r
--- 1400 bytes MTU => 350 as limit for fragmentation\r
-variable max_event_size : real := 512.0;\r
---variable max_event_size : real := 1024.0;\r
-\r
-variable seed1 : positive; -- seed for random generator\r
-variable seed2 : positive; -- seed for random generator\r
-variable rand : real; -- random value (0.0 ... 1.0)\r
-variable int_rand : integer; -- random value, scaled to your needs\r
-variable cts_random_number : std_logic_vector(7 downto 0);\r
-\r
-variable stim : std_logic_vector(15 downto 0);\r
-\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- cts_number_in <= x"0000";\r
- cts_code_in <= x"00";\r
- cts_information_in <= x"00";\r
- cts_readout_type_in <= x"0";\r
- cts_start_readout_in <= '0';\r
- cts_read_in <= '0';\r
- fee_data_in <= x"0000";\r
- fee_dataready_in <= '0';\r
- fee_status_bits_in <= x"0000_0000";\r
- fee_busy_in <= '0';\r
--- pc_ready_in <= '0';\r
-\r
- config_done_in <= '1';\r
- data_gbe_enable_in <= '1';\r
- data_ipu_enable_in <= '0';\r
- multi_evt_enable_in <= '0';\r
-\r
- wait for 22 ns;\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- wait for 200 ns;\r
-\r
----------------------------\r
-\r
--------------------------------------------------------------------------------\r
--- Loop the transmissions\r
--------------------------------------------------------------------------------\r
- trigger_counter := x"4710";\r
- trigger_loop := 40;\r
-\r
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop\r
- -- generate a real random byte for CTS\r
- UNIFORM(seed1, seed2, rand);\r
- int_rand := INTEGER(TRUNC(rand*256.0));\r
- cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));\r
- \r
- -- IPU transmission starts\r
- wait until rising_edge(clk);\r
- cts_number_in <= std_logic_vector( trigger_counter );\r
- cts_code_in <= cts_random_number;\r
- cts_information_in <= x"de";\r
- cts_readout_type_in <= x"1";\r
- cts_start_readout_in <= '1';\r
- wait until rising_edge(clk);\r
- wait for 400 ns;\r
-\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '1';\r
- wait for 300 ns;\r
- wait until rising_edge(clk);\r
-\r
- -- ONE DATA TRANSMISSION\r
- -- dice a length\r
- UNIFORM(seed1, seed2, rand);\r
- test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;\r
- \r
--- test_data_len := 9685;\r
- \r
- -- calculate the needed variables\r
- test_loop_len := 2*(test_data_len - 1) + 1;\r
- test_hdr_len := to_unsigned( test_data_len + 1, 16 );\r
- test_evt_len := to_unsigned( test_data_len, 16 );\r
-\r
- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)\r
- fee_dataready_in <= '1';\r
- fee_data_in <= x"10" & cts_random_number;\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( trigger_counter );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_hdr_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word\r
- fee_data_in <= x"ff21";\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_evt_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_data_in <= x"ff22"; \r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- test_data := x"ffff";\r
- MY_DATA_LOOP: for J in 0 to test_loop_len loop\r
- test_data := test_data + 1;\r
- wait until rising_edge(clk) and (fee_read_out = '1'); --\r
- fee_data_in <= std_logic_vector(test_data); \r
- if( (test_data MOD 5) = 0 ) then\r
- fee_dataready_in <= '0';\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- else\r
- fee_dataready_in <= '1';\r
- end if;\r
- end loop MY_DATA_LOOP;\r
- -- there must be padding words to get multiple of four LWs\r
- \r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '0';\r
- fee_data_in <= x"0000"; \r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '0';\r
-\r
-\r
- trigger_loop := trigger_loop + 1;\r
- trigger_counter := trigger_counter + 1;\r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_read_in <= '1';\r
- wait until rising_edge(clk);\r
- cts_read_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_start_readout_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk); \r
- \r
- --wait for 8 us;\r
-\r
- end loop MY_TRIGGER_LOOP;\r
-\r
-\r
-\r
----------------------------\r
----------------------------\r
- wait for 300 ns;\r
-\r
- wait;\r
-\r
- -- Start packet_constructor\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
--- pc_ready_in <= '1';\r
- wait until rising_edge(clk);\r
-\r
- wait until rising_edge(clk);\r
- wait until pc_eod_out = '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
--- pc_ready_in <= '0';\r
-\r
- -- Stay a while... stay forever!!!\r
- wait; \r
- \r
-end process TESTBENCH_PROC;\r
-\r
-\r
-END;\r
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT trb_net16_lsm_sfp_gbe\r
- PORT(\r
- SYSCLK : IN std_logic;\r
- RESET : IN std_logic;\r
- CLEAR : IN std_logic;\r
- SFP_MISSING_IN : IN std_logic;\r
- SFP_LOS_IN : IN std_logic;\r
- SD_LINK_OK_IN : IN std_logic;\r
- SD_LOS_IN : IN std_logic;\r
- SD_TXCLK_BAD_IN : IN std_logic;\r
- SD_RXCLK_BAD_IN : IN std_logic; \r
- FULL_RESET_OUT : OUT std_logic;\r
- LANE_RESET_OUT : OUT std_logic;\r
- USER_RESET_OUT : OUT std_logic;\r
- TIMING_CTR_OUT : OUT std_logic_vector(18 downto 0);\r
- BSM_OUT : OUT std_logic_vector(3 downto 0);\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL SYSCLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL CLEAR : std_logic;\r
- SIGNAL SFP_MISSING_IN : std_logic;\r
- SIGNAL SFP_LOS_IN : std_logic;\r
- SIGNAL SD_LINK_OK_IN : std_logic;\r
- SIGNAL SD_LOS_IN : std_logic;\r
- SIGNAL SD_TXCLK_BAD_IN : std_logic;\r
- SIGNAL SD_RXCLK_BAD_IN : std_logic;\r
- SIGNAL FULL_RESET_OUT : std_logic;\r
- SIGNAL LANE_RESET_OUT : std_logic;\r
- SIGNAL USER_RESET_OUT : std_logic;\r
- SIGNAL TIMING_CTR_OUT : std_logic_vector(18 downto 0);\r
- SIGNAL BSM_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: trb_net16_lsm_sfp_gbe PORT MAP(\r
- SYSCLK => SYSCLK,\r
- RESET => RESET,\r
- CLEAR => CLEAR,\r
- SFP_MISSING_IN => SFP_MISSING_IN,\r
- SFP_LOS_IN => SFP_LOS_IN,\r
- SD_LINK_OK_IN => SD_LINK_OK_IN,\r
- SD_LOS_IN => SD_LOS_IN,\r
- SD_TXCLK_BAD_IN => SD_TXCLK_BAD_IN,\r
- SD_RXCLK_BAD_IN => SD_RXCLK_BAD_IN,\r
- FULL_RESET_OUT => FULL_RESET_OUT,\r
- LANE_RESET_OUT => LANE_RESET_OUT,\r
- USER_RESET_OUT => USER_RESET_OUT,\r
- TIMING_CTR_OUT => TIMING_CTR_OUT,\r
- BSM_OUT => BSM_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
- \r
-\r
-CLOCK_GEN: process\r
-begin\r
- sysclk <= '1'; wait for 4.0 ns;\r
- sysclk <= '0'; wait for 4.0 ns;\r
-end process CLOCK_GEN;\r
-\r
-THE_TESTBENCH: process\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- clear <= '0';\r
- sfp_missing_in <= '0';\r
- sfp_los_in <= '0';\r
- sd_link_ok_in <= '0';\r
- sd_los_in <= '0';\r
- sd_txclk_bad_in <= '1';\r
- sd_rxclk_bad_in <= '1';\r
- wait for 100 ns;\r
- \r
- -- Reset\r
- clear <= '1';\r
- wait for 100 ns;\r
- clear <= '0';\r
- wait for 10 ns;\r
- \r
- -- Tests may start now\r
- wait until falling_edge(full_reset_out);\r
- wait for 123 ns;\r
- sd_txclk_bad_in <= '0';\r
- wait for 433 ns;\r
- sd_rxclk_bad_in <= '0';\r
-\r
- wait for 1.1 us;\r
- sd_rxclk_bad_in <= '1';\r
- wait for 33 ns;\r
- sd_rxclk_bad_in <= '0';\r
-\r
- \r
- wait until rising_edge(sysclk); \r
- \r
- -- Stay a while.... stay forever!!! Muahahaha!!!!\r
- wait;\r
-\r
-end process THE_TESTBENCH;\r
- \r
-END;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee; \r
-USE ieee.std_logic_1164.ALL; \r
-USE ieee.numeric_std.ALL; \r
- \r
-ENTITY testbench IS \r
-END testbench; \r
- \r
-ARCHITECTURE behavior OF testbench IS \r
- \r
- COMPONENT trb_net16_gbe_packet_constr \r
- PORT( \r
- RESET : IN std_logic; \r
- CLK : IN std_logic; \r
- PC_WR_EN_IN : IN std_logic; \r
- PC_DATA_IN : IN std_logic_vector(7 downto 0); \r
- PC_START_OF_SUB_IN : IN std_logic; \r
- PC_END_OF_DATA_IN : IN std_logic; \r
- PC_SUB_SIZE_IN : IN std_logic_vector(31 downto 0); \r
- PC_DECODING_IN : IN std_logic_vector(31 downto 0); \r
- PC_EVENT_ID_IN : IN std_logic_vector(31 downto 0); \r
- PC_TRIG_NR_IN : IN std_logic_vector(31 downto 0); \r
- PC_QUEUE_DEC_IN : IN std_logic_vector(31 downto 0); \r
- PC_MAX_FRAME_SIZE_IN : IN std_logic_vector(15 downto 0);\r
- FC_H_READY_IN : IN std_logic; \r
- FC_READY_IN : IN std_logic; \r
- PC_READY_OUT : OUT std_logic; \r
- FC_WR_EN_OUT : OUT std_logic; \r
- FC_DATA_OUT : OUT std_logic_vector(7 downto 0); \r
- FC_IP_SIZE_OUT : OUT std_logic_vector(15 downto 0); \r
- FC_UDP_SIZE_OUT : OUT std_logic_vector(15 downto 0); \r
- FC_IDENT_OUT : OUT std_logic_vector(15 downto 0); \r
- FC_FLAGS_OFFSET_OUT : OUT std_logic_vector(15 downto 0);\r
- FC_SOD_OUT : OUT std_logic; \r
- FC_EOD_OUT : OUT std_logic; \r
- BSM_CONSTR_OUT : OUT std_logic_vector(3 downto 0); \r
- BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); \r
- BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); \r
- DBG_SHF_EMPTY : OUT std_logic;\r
- DBG_SHF_FULL : OUT std_logic;\r
- DBG_SHF_WR_EN : OUT std_logic;\r
- DBG_SHF_RD_EN : OUT std_logic;\r
- DBG_DF_EMPTY : OUT std_logic;\r
- DBG_DF_FULL : OUT std_logic;\r
- DBG_DF_WR_EN : OUT std_logic;\r
- DBG_DF_RD_EN : OUT std_logic;\r
- DBG_ALL_CTR : OUT std_logic_vector(4 downto 0);\r
- DBG_SUB_CTR : OUT std_logic_vector(4 downto 0);\r
- DBG_MY_CTR : OUT std_logic_vector(1 downto 0);\r
- DBG_BYTES_LOADED : OUT std_logic_vector(15 downto 0);\r
- DBG_SIZE_LEFT : OUT std_logic_vector(31 downto 0);\r
- DBG_SUB_SIZE_TO_SAVE : OUT std_logic_vector(31 downto 0);\r
- DBG_SUB_SIZE_LOADED : OUT std_logic_vector(31 downto 0);\r
- DBG_SUB_BYTES_LOADED : OUT std_logic_vector(31 downto 0);\r
- DBG_QUEUE_SIZE : OUT std_logic_vector(31 downto 0);\r
- DBG_ACT_QUEUE_SIZE : OUT std_logic_vector(31 downto 0);\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0) \r
- ); \r
- END COMPONENT; \r
-\r
- SIGNAL RESET : std_logic; \r
- SIGNAL CLK : std_logic; \r
- SIGNAL PC_WR_EN_IN : std_logic; \r
- SIGNAL PC_DATA_IN : std_logic_vector(7 downto 0); \r
- SIGNAL PC_READY_OUT : std_logic; \r
- SIGNAL PC_START_OF_SUB_IN : std_logic; \r
- SIGNAL PC_END_OF_DATA_IN : std_logic; \r
- SIGNAL PC_SUB_SIZE_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_DECODING_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_EVENT_ID_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_TRIG_NR_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_QUEUE_DEC_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_MAX_FRAME_SIZE_IN : std_logic_vector(15 downto 0);\r
- SIGNAL FC_WR_EN_OUT : std_logic; \r
- SIGNAL FC_DATA_OUT : std_logic_vector(7 downto 0); \r
- SIGNAL FC_H_READY_IN : std_logic; \r
- SIGNAL FC_READY_IN : std_logic; \r
- SIGNAL FC_IP_SIZE_OUT : std_logic_vector(15 downto 0); \r
- SIGNAL FC_UDP_SIZE_OUT : std_logic_vector(15 downto 0); \r
- SIGNAL FC_IDENT_OUT : std_logic_vector(15 downto 0); \r
- SIGNAL FC_FLAGS_OFFSET_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL FC_SOD_OUT : std_logic; \r
- SIGNAL FC_EOD_OUT : std_logic; \r
- SIGNAL BSM_CONSTR_OUT : std_logic_vector(3 downto 0); \r
- SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); \r
- SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); \r
- SIGNAL DBG_SHF_EMPTY : std_logic;\r
- SIGNAL DBG_SHF_FULL : std_logic;\r
- SIGNAL DBG_SHF_WR_EN : std_logic;\r
- SIGNAL DBG_SHF_RD_EN : std_logic;\r
- SIGNAL DBG_DF_EMPTY : std_logic;\r
- SIGNAL DBG_DF_FULL : std_logic;\r
- SIGNAL DBG_DF_WR_EN : std_logic;\r
- SIGNAL DBG_DF_RD_EN : std_logic;\r
- SIGNAL DBG_ALL_CTR : std_logic_vector(4 downto 0);\r
- SIGNAL DBG_SUB_CTR : std_logic_vector(4 downto 0);\r
- SIGNAL DBG_MY_CTR : std_logic_vector(1 downto 0);\r
- SIGNAL DBG_BYTES_LOADED : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SIZE_LEFT : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_SUB_SIZE_TO_SAVE : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_SUB_SIZE_LOADED : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_SUB_BYTES_LOADED : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_QUEUE_SIZE : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_ACT_QUEUE_SIZE : std_logic_vector(31 downto 0);\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); \r
- \r
-BEGIN \r
- \r
--- Please check and add your generic clause manually \r
- uut: trb_net16_gbe_packet_constr PORT MAP( \r
- RESET => RESET, \r
- CLK => CLK, \r
- PC_WR_EN_IN => PC_WR_EN_IN, \r
- PC_DATA_IN => PC_DATA_IN, \r
- PC_READY_OUT => PC_READY_OUT, \r
- PC_START_OF_SUB_IN => PC_START_OF_SUB_IN, \r
- PC_END_OF_DATA_IN => PC_END_OF_DATA_IN, \r
- PC_SUB_SIZE_IN => PC_SUB_SIZE_IN, \r
- PC_DECODING_IN => PC_DECODING_IN, \r
- PC_EVENT_ID_IN => PC_EVENT_ID_IN, \r
- PC_TRIG_NR_IN => PC_TRIG_NR_IN, \r
- PC_QUEUE_DEC_IN => PC_QUEUE_DEC_IN,\r
- PC_MAX_FRAME_SIZE_IN => PC_MAX_FRAME_SIZE_IN, \r
- FC_WR_EN_OUT => FC_WR_EN_OUT, \r
- FC_DATA_OUT => FC_DATA_OUT, \r
- FC_H_READY_IN => FC_H_READY_IN, \r
- FC_READY_IN => FC_READY_IN, \r
- FC_IP_SIZE_OUT => FC_IP_SIZE_OUT, \r
- FC_UDP_SIZE_OUT => FC_UDP_SIZE_OUT, \r
- FC_IDENT_OUT => FC_IDENT_OUT, \r
- FC_FLAGS_OFFSET_OUT => FC_FLAGS_OFFSET_OUT, \r
- FC_SOD_OUT => FC_SOD_OUT, \r
- FC_EOD_OUT => FC_EOD_OUT, \r
- BSM_CONSTR_OUT => BSM_CONSTR_OUT, \r
- BSM_LOAD_OUT => BSM_LOAD_OUT, \r
- BSM_SAVE_OUT => BSM_SAVE_OUT, \r
- DBG_SHF_EMPTY => DBG_SHF_EMPTY,\r
- DBG_SHF_FULL => DBG_SHF_FULL,\r
- DBG_SHF_WR_EN => DBG_SHF_WR_EN,\r
- DBG_SHF_RD_EN => DBG_SHF_RD_EN,\r
- DBG_DF_EMPTY => DBG_DF_EMPTY,\r
- DBG_DF_FULL => DBG_DF_FULL,\r
- DBG_DF_WR_EN => DBG_DF_WR_EN,\r
- DBG_DF_RD_EN => DBG_DF_RD_EN,\r
- DBG_ALL_CTR => DBG_ALL_CTR,\r
- DBG_SUB_CTR => DBG_SUB_CTR,\r
- DBG_MY_CTR => DBG_MY_CTR,\r
- DBG_BYTES_LOADED => DBG_BYTES_LOADED, \r
- DBG_SIZE_LEFT => DBG_SIZE_LEFT, \r
- DBG_SUB_SIZE_TO_SAVE => DBG_SUB_SIZE_TO_SAVE,\r
- DBG_SUB_SIZE_LOADED => DBG_SUB_SIZE_LOADED,\r
- DBG_SUB_BYTES_LOADED => DBG_SUB_BYTES_LOADED,\r
- DBG_QUEUE_SIZE => DBG_QUEUE_SIZE,\r
- DBG_ACT_QUEUE_SIZE => DBG_ACT_QUEUE_SIZE,\r
- DEBUG_OUT => DEBUG_OUT\r
- ); \r
- \r
-CLK_GEN: process\r
-begin\r
- clk <= '1'; wait for 5.0 ns;\r
- clk <= '0'; wait for 5.0 ns;\r
-end process CLK_GEN;\r
-\r
-THE_TESTBENCH: process\r
-variable test_data_len : integer range 0 to 65535 := 1;\r
-variable test_loop_len : integer range 0 to 65535 := 0;\r
-variable test_evt_len : unsigned(15 downto 0) := x"0000";\r
-variable test_evt_len_vec : std_logic_vector(15 downto 0);\r
-variable test_sub_len : unsigned(15 downto 0) := x"0000";\r
-variable test_sub_len_vec : std_logic_vector(15 downto 0);\r
-variable test_data : unsigned(15 downto 0) := x"ffff";\r
-variable test_data_vec : std_logic_vector(15 downto 0);\r
-\r
-variable trigger_counter : unsigned(15 downto 0) := x"4710";\r
-variable trigger_loop : integer range 0 to 65535 := 15;\r
-begin\r
- -- Set up signals\r
- reset <= '0';\r
- pc_wr_en_in <= '0';\r
- pc_data_in <= x"00";\r
- pc_start_of_sub_in <= '0';\r
- pc_end_of_data_in <= '0';\r
- pc_sub_size_in <= x"0000_0000";\r
- pc_trig_nr_in <= x"0000_0000";\r
- pc_decoding_in <= x"0002_0001"; -- static\r
- pc_event_id_in <= x"0000_00ca"; -- static\r
- pc_queue_dec_in <= x"0003_0062"; -- static\r
- pc_max_frame_size_in <= x"0578"; -- static\r
- fc_h_ready_in <= '0';\r
- fc_ready_in <= '0';\r
- wait until rising_edge(clk);\r
-\r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- wait for 200 ns;\r
- wait until rising_edge(clk);\r
- \r
- -- Tests may start now\r
-\r
--------------------------------------------------------------------------------\r
--- Loop the transmissions\r
--------------------------------------------------------------------------------\r
- trigger_counter := x"4710";\r
- trigger_loop := 0;\r
-\r
- test_data_len := 14;\r
-\r
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop\r
-\r
- -- calculate the needed variables\r
- test_loop_len := 2*(test_data_len - 1) + 1;\r
- test_evt_len := to_unsigned( test_data_len, 16 );\r
- test_evt_len_vec := std_logic_vector(test_evt_len);\r
- test_sub_len := test_evt_len + 1;\r
- test_sub_len_vec := std_logic_vector(test_sub_len);\r
-\r
- -- start of subevent marker\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_trig_nr_in <= x"0000" & std_logic_vector(trigger_counter);\r
- pc_sub_size_in <= b"0000_0000_0000_00" & test_sub_len_vec & b"00";\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_start_of_sub_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_start_of_sub_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_data_in <= test_evt_len_vec(15 downto 8);\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_data_in <= test_evt_len_vec(7 downto 0);\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_wr_en_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_data_in <= x"ff"; -- source address high byte\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_data_in <= x"22"; -- source address low byte\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_wr_en_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- \r
- test_data := x"ffff";\r
- MY_DATA_LOOP: for J in 0 to test_loop_len loop\r
- test_data := test_data + 1;\r
- test_data_vec := std_logic_vector(test_data);\r
- wait until rising_edge(clk);\r
- pc_data_in <= test_data_vec(15 downto 8);\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_data_in <= test_data_vec(7 downto 0);\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_wr_en_in <= '0';\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk); \r
- end loop MY_DATA_LOOP;\r
-\r
- -- end of subevent marker\r
--- wait until rising_edge(clk);\r
- pc_end_of_data_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_end_of_data_in <= '0';\r
- pc_sub_size_in <= x"0000_0000";\r
- pc_trig_nr_in <= x"0000_0000";\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- trigger_loop := trigger_loop + 1;\r
- trigger_counter := trigger_counter + 1;\r
-\r
- wait for 500 ns;\r
- wait until rising_edge(clk);\r
- end loop MY_TRIGGER_LOOP;\r
-\r
--- wait for 8 us;\r
--------------------------------------------------------------------------------\r
--- end of loop\r
--------------------------------------------------------------------------------\r
-\r
- wait until rising_edge(clk);\r
- fc_ready_in <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fc_h_ready_in <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- \r
- -- Stay a while... stay forever!!!Muahahah!!!\r
- wait;\r
-\r
-end process THE_TESTBENCH; \r
- \r
-END;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT slv_mac_memory\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- BUSY_IN : IN std_logic;\r
- SLV_ADDR_IN : IN std_logic_vector(7 downto 0);\r
- SLV_READ_IN : IN std_logic;\r
- SLV_WRITE_IN : IN std_logic;\r
- SLV_DATA_IN : IN std_logic_vector(31 downto 0);\r
- MEM_CLK_IN : IN std_logic;\r
- MEM_ADDR_IN : IN std_logic_vector(7 downto 0); \r
- SLV_BUSY_OUT : OUT std_logic;\r
- SLV_ACK_OUT : OUT std_logic;\r
- SLV_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- MEM_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- STAT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL BUSY_IN : std_logic;\r
- SIGNAL SLV_ADDR_IN : std_logic_vector(7 downto 0);\r
- SIGNAL SLV_READ_IN : std_logic;\r
- SIGNAL SLV_WRITE_IN : std_logic;\r
- SIGNAL SLV_BUSY_OUT : std_logic;\r
- SIGNAL SLV_ACK_OUT : std_logic;\r
- SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0);\r
- SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL MEM_CLK_IN : std_logic;\r
- SIGNAL MEM_ADDR_IN : std_logic_vector(7 downto 0);\r
- SIGNAL MEM_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL STAT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: slv_mac_memory PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- BUSY_IN => BUSY_IN,\r
- SLV_ADDR_IN => SLV_ADDR_IN,\r
- SLV_READ_IN => SLV_READ_IN,\r
- SLV_WRITE_IN => SLV_WRITE_IN,\r
- SLV_BUSY_OUT => SLV_BUSY_OUT,\r
- SLV_ACK_OUT => SLV_ACK_OUT,\r
- SLV_DATA_IN => SLV_DATA_IN,\r
- SLV_DATA_OUT => SLV_DATA_OUT,\r
- MEM_CLK_IN => MEM_CLK_IN,\r
- MEM_ADDR_IN => MEM_ADDR_IN,\r
- MEM_DATA_OUT => MEM_DATA_OUT,\r
- STAT => STAT\r
- );\r
-\r
-CLK_GEN_PROC: process\r
-begin\r
- clk <= '0'; mem_clk_in <= '0'; wait for 5.0 ns;\r
- clk <= '1'; mem_clk_in <= '1'; wait for 5.0 ns;\r
-end process CLK_GEN_PROC;\r
-\r
-THE_TESTBENCH: process\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- busy_in <= '0';\r
- slv_addr_in <= x"00";\r
- slv_read_in <= '0';\r
- slv_write_in <= '0';\r
- slv_data_in <= x"dead_beef";\r
- mem_addr_in <= x"f0";\r
- wait until rising_edge(clk);\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- \r
- -- Tests may start now\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"00";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"01";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"02";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"03";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"04";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"05";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"06";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"07";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"08";\r
- \r
- -- Stay a while... stay forever!!! Muahahaha!!!!!\r
- wait;\r
-end process THE_TESTBENCH;\r
-\r
-END;\r
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
---use work.version.all;
-
-
-entity trb_net16_gbe_buf is
-generic(
- DO_SIMULATION : integer range 0 to 1 := 1;
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0;
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1;
-
- FIXED_SIZE_MODE : integer range 0 to 1 := 1;
- INCREMENTAL_MODE : integer range 0 to 1 := 0;
- FIXED_SIZE : integer range 0 to 65535 := 10;
- FIXED_DELAY_MODE : integer range 0 to 1 := 1;
- UP_DOWN_MODE : integer range 0 to 1 := 0;
- UP_DOWN_LIMIT : integer range 0 to 16777215 := 0;
- FIXED_DELAY : integer range 0 to 16777215 := 16777215
-);
-port(
- CLK : in std_logic;
- TEST_CLK : in std_logic; -- only for simulation!
- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
- RESET : in std_logic;
- GSR_N : in std_logic;
- -- Debug
- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);
- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);
- -- configuration interface
- IP_CFG_START_IN : in std_logic;
- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);
- IP_CFG_DONE_OUT : out std_logic;
- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);
- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);
- IP_CFG_MEM_CLK_OUT : out std_logic;
- MR_RESET_IN : in std_logic;
- MR_MODE_IN : in std_logic;
- MR_RESTART_IN : in std_logic;
- -- gk 29.03.10
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- gk 22.04.10
- -- registers setup interface
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
- -- gk 23.04.10
- LED_PACKET_SENT_OUT : out std_logic;
- LED_AN_DONE_N_OUT : out std_logic;
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- --SFP Connection
- SFP_RXD_P_IN : in std_logic;
- SFP_RXD_N_IN : in std_logic;
- SFP_TXD_P_OUT : out std_logic;
- SFP_TXD_N_OUT : out std_logic;
- SFP_REFCLK_P_IN : in std_logic;
- SFP_REFCLK_N_IN : in std_logic;
- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SFP_TXDIS_OUT : out std_logic; -- SFP disable
-
- -- interface between main_controller and hub logic
- MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
-
- MAKE_RESET_OUT : out std_logic;
-
- -- for simulation of receiving part only
- MAC_RX_EOF_IN : in std_logic;
- MAC_RXD_IN : in std_logic_vector(7 downto 0);
- MAC_RX_EN_IN : in std_logic;
-
-
- -- debug ports
- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end entity trb_net16_gbe_buf;
-
-architecture trb_net16_gbe_buf of trb_net16_gbe_buf is
-
--- Placer Directives
---attribute HGROUP : string;
--- for whole architecture
---attribute HGROUP of trb_net16_gbe_buf : architecture is "GBE_BUF_group";
-
-
-component tsmac35 --tsmac36 --tsmac35
-port(
- --------------- clock and reset port declarations ------------------
- hclk : in std_logic;
- txmac_clk : in std_logic;
- rxmac_clk : in std_logic;
- reset_n : in std_logic;
- txmac_clk_en : in std_logic;
- rxmac_clk_en : in std_logic;
- ------------------- Input signals to the GMII ----------------
- rxd : in std_logic_vector(7 downto 0);
- rx_dv : in std_logic;
- rx_er : in std_logic;
- col : in std_logic;
- crs : in std_logic;
- -------------------- Input signals to the CPU I/F -------------------
- haddr : in std_logic_vector(7 downto 0);
- hdatain : in std_logic_vector(7 downto 0);
- hcs_n : in std_logic;
- hwrite_n : in std_logic;
- hread_n : in std_logic;
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata : in std_logic_vector(7 downto 0);
- tx_fifoavail : in std_logic;
- tx_fifoeof : in std_logic;
- tx_fifoempty : in std_logic;
- tx_sndpaustim : in std_logic_vector(15 downto 0);
- tx_sndpausreq : in std_logic;
- tx_fifoctrl : in std_logic;
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
- rx_fifo_full : in std_logic;
- ignore_pkt : in std_logic;
- -------------------- Output signals from the GMII -----------------------
- txd : out std_logic_vector(7 downto 0);
- tx_en : out std_logic;
- tx_er : out std_logic;
- -------------------- Output signals from the CPU I/F -------------------
- hdataout : out std_logic_vector(7 downto 0);
- hdataout_en_n : out std_logic;
- hready_n : out std_logic;
- cpu_if_gbit_en : out std_logic;
- ---------------- Output signals from the Tx MAC FIFO I/F ---------------
- tx_macread : out std_logic;
- tx_discfrm : out std_logic;
- tx_staten : out std_logic;
- tx_done : out std_logic;
- tx_statvec : out std_logic_vector(30 downto 0);
- ---------------- Output signals from the Rx MAC FIFO I/F ---------------
- rx_fifo_error : out std_logic;
- rx_stat_vector : out std_logic_vector(31 downto 0);
- rx_dbout : out std_logic_vector(7 downto 0);
- rx_write : out std_logic;
- rx_stat_en : out std_logic;
- rx_eof : out std_logic;
- rx_error : out std_logic
-);
-end component;
-
-component mb_mac_sim is
-port (
- --------------------------------------------------------------------------
- --------------- clock, reset, clock enable -------------------------------
- HCLK : in std_logic;
- TX_MAC_CLK : in std_logic;
- RX_MAC_CLK : in std_logic;
- RESET_N : in std_logic;
- TXMAC_CLK_EN : in std_logic;
- RXMAC_CLK_EN : in std_logic;
- --------------------------------------------------------------------------
- --------------- SGMII receive interface ----------------------------------
- RXD : in std_logic_vector(7 downto 0);
- RX_DV : in std_logic;
- RX_ER : in std_logic;
- COL : in std_logic;
- CRS : in std_logic;
- --------------------------------------------------------------------------
- --------------- SGMII transmit interface ---------------------------------
- TXD : out std_logic_vector(7 downto 0);
- TX_EN : out std_logic;
- TX_ER : out std_logic;
- --------------------------------------------------------------------------
- --------------- CPU configuration interface ------------------------------
- HADDR : in std_logic_vector(7 downto 0);
- HDATAIN : in std_logic_vector(7 downto 0);
- HCS_N : in std_logic;
- HWRITE_N : in std_logic;
- HREAD_N : in std_logic;
- HDATAOUT : out std_logic_vector(7 downto 0);
- HDATAOUT_EN_N : out std_logic;
- HREADY_N : out std_logic;
- CPU_IF_GBIT_EN : out std_logic;
- --------------------------------------------------------------------------
- --------------- Transmit FIFO interface ----------------------------------
- TX_FIFODATA : in std_logic_vector(7 downto 0);
- TX_FIFOAVAIL : in std_logic;
- TX_FIFOEOF : in std_logic;
- TX_FIFOEMPTY : in std_logic;
- TX_MACREAD : out std_logic;
- TX_DONE : out std_logic;
- TX_SNDPAUSTIM : in std_logic_vector(15 downto 0);
- TX_SNDPAUSREQ : in std_logic;
- TX_FIFOCTRL : in std_logic;
- TX_DISCFRM : out std_logic;
- TX_STATEN : out std_logic;
- TX_STATVEC : out std_logic_vector(30 downto 0);
- --------------------------------------------------------------------------
- --------------- Receive FIFO interface -----------------------------------
- RX_DBOUT : out std_logic_vector(7 downto 0);
- RX_FIFO_FULL : in std_logic;
- IGNORE_PKT : in std_logic;
- RX_FIFO_ERROR : out std_logic;
- RX_STAT_VECTOR : out std_logic_vector(31 downto 0);
- RX_STAT_EN : out std_logic;
- RX_WRITE : out std_logic;
- RX_EOF : out std_logic;
- RX_ERROR : out std_logic
-);
-end component;
-
-signal pc_decoding : std_logic_vector(31 downto 0);
-signal pc_event_id : std_logic_vector(31 downto 0);
-signal pc_queue_dec : std_logic_vector(31 downto 0);
-signal pc_max_frame_size : std_logic_vector(15 downto 0);
-signal cts_readout_finished : std_logic;
-signal cts_dataready : std_logic;
-signal cts_length : std_logic_vector(15 downto 0);
-signal cts_data : std_logic_vector(31 downto 0); -- DHDR of rest packet
-signal cts_error_pattern : std_logic_vector(31 downto 0);
-signal fc_dest_mac : std_logic_vector(47 downto 0);
-signal fc_dest_ip : std_logic_vector(31 downto 0);
-signal fc_dest_udp : std_logic_vector(15 downto 0);
-signal fc_src_mac : std_logic_vector(47 downto 0);
-signal fc_src_ip : std_logic_vector(31 downto 0);
-signal fc_src_udp : std_logic_vector(15 downto 0);
-signal fc_type : std_logic_vector(15 downto 0);
-signal fc_ihl_version : std_logic_vector(7 downto 0);
-signal fc_tos : std_logic_vector(7 downto 0);
-signal fc_ttl : std_logic_vector(7 downto 0);
-signal fc_protocol : std_logic_vector(7 downto 0);
-
-signal ft_data : std_logic_vector(8 downto 0);-- gk 04.05.10
-signal ft_tx_empty : std_logic;
-signal ft_start_of_packet : std_logic;
-signal ft_bsm_init : std_logic_vector(3 downto 0);
-signal ft_bsm_mac : std_logic_vector(3 downto 0);
-signal ft_bsm_trans : std_logic_vector(3 downto 0);
-
-signal mac_haddr : std_logic_vector(7 downto 0);
-signal mac_hdataout : std_logic_vector(7 downto 0);
-signal mac_hcs : std_logic;
-signal mac_hwrite : std_logic;
-signal mac_hread : std_logic;
-signal mac_fifoavail : std_logic;
-signal mac_fifoempty : std_logic;
-signal mac_fifoeof : std_logic;
-signal mac_hready : std_logic;
-signal mac_hdata_en : std_logic;
-signal mac_tx_done : std_logic;
-signal mac_tx_read : std_logic;
-
-signal serdes_clk_125 : std_logic;
-signal mac_tx_clk_en : std_logic;
-signal mac_rx_clk_en : std_logic;
-signal mac_col : std_logic;
-signal mac_crs : std_logic;
-signal pcs_txd : std_logic_vector(7 downto 0);
-signal pcs_tx_en : std_logic;
-signal pcs_tx_er : std_logic;
-signal pcs_an_lp_ability : std_logic_vector(15 downto 0);
-signal pcs_an_complete : std_logic;
-signal pcs_an_page_rx : std_logic;
-
-signal pcs_stat_debug : std_logic_vector(63 downto 0);
-
-signal stage_stat_regs : std_logic_vector(31 downto 0);
-signal stage_ctrl_regs : std_logic_vector(31 downto 0);
-signal use_gbe : std_logic;
-signal use_trbnet : std_logic;
-signal use_multievents : std_logic;
--- gk 26.04.10
-signal readout_ctr : std_logic_vector(23 downto 0);
-signal readout_ctr_valid : std_logic;
-signal dbg_pc1 : std_logic_vector(31 downto 0);
-signal dbg_fc1 : std_logic_vector(31 downto 0);
-signal dbg_ft1 : std_logic_vector(31 downto 0);
--- gk 08.06.10
-signal mac_tx_staten : std_logic;
-signal mac_tx_statevec : std_logic_vector(30 downto 0);
-signal mac_tx_discfrm : std_logic;
-
-signal dbg_q : std_logic_vector(15 downto 0);
-
--- gk 21.07.10
-signal allow_large : std_logic;
-
--- gk 28.07.10
-signal bytes_sent_ctr : std_logic_vector(31 downto 0);
-signal monitor_dropped : std_logic_vector(31 downto 0);
-signal monitor_fifos : std_logic_vector(31 downto 0);
-signal monitor_fifos_q : std_logic_vector(31 downto 0);
-
--- gk 02.08.10
-signal discfrm_ctr : std_logic_vector(31 downto 0);
-
--- gk 13.02.11
-signal pcs_rxd : std_logic_vector(7 downto 0);
-signal pcs_rx_en : std_logic;
-signal pcs_rx_er : std_logic;
-signal mac_rx_eof : std_logic;
-signal mac_rx_er : std_logic;
-signal mac_rxd : std_logic_vector(7 downto 0);
-signal mac_rx_fifo_err : std_logic;
-signal mac_rx_fifo_full : std_logic;
-signal mac_rx_en : std_logic;
-signal mac_rx_stat_en : std_logic;
-signal mac_rx_stat_vec : std_logic_vector(31 downto 0);
-signal fr_q : std_logic_vector(8 downto 0);
-signal fr_rd_en : std_logic;
-signal fr_frame_valid : std_logic;
-signal rc_rd_en : std_logic;
-signal rc_q : std_logic_vector(8 downto 0);
-signal rc_frames_rec_ctr : std_logic_vector(31 downto 0);
-signal mc_data : std_logic_vector(8 downto 0);
-signal mc_wr_en : std_logic;
-signal fc_wr_en : std_logic;
-signal fc_data : std_logic_vector(7 downto 0);
-signal fc_ip_size : std_logic_vector(15 downto 0);
-signal fc_udp_size : std_logic_vector(15 downto 0);
-signal fc_ident : std_logic_vector(15 downto 0);
-signal fc_flags_offset : std_logic_vector(15 downto 0);
-signal fc_sod : std_logic;
-signal fc_eod : std_logic;
-signal fc_h_ready : std_logic;
-signal fc_ready : std_logic;
-signal rc_frame_ready : std_logic;
-signal allow_rx : std_logic;
-signal fr_frame_size : std_logic_vector(15 downto 0);
-signal rc_frame_size : std_logic_vector(15 downto 0);
-signal mc_frame_size : std_logic_vector(15 downto 0);
-signal rc_bytes_rec : std_logic_vector(31 downto 0);
-signal rc_debug : std_logic_vector(63 downto 0);
-signal tsmac_gbit_en : std_logic;
-signal mc_transmit_ctrl : std_logic;
-signal rc_loading_done : std_logic;
-signal fr_get_frame : std_logic;
-signal mc_transmit_done : std_logic;
-
-signal fr_frame_proto : std_logic_vector(15 downto 0);
-signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
-signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal dbg_select_rec_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal dbg_select_sent_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal dbg_select_drop_in : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal dbg_select_drop_out : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal dbg_select_gen : std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
-signal serdes_rx_clk : std_logic;
-
-signal mc_type : std_logic_vector(15 downto 0);
-signal fr_src_mac : std_logic_vector(47 downto 0);
-signal fr_dest_mac : std_logic_vector(47 downto 0);
-signal fr_src_ip : std_logic_vector(31 downto 0);
-signal fr_dest_ip : std_logic_vector(31 downto 0);
-signal fr_src_udp : std_logic_vector(15 downto 0);
-signal fr_dest_udp : std_logic_vector(15 downto 0);
-signal rc_src_mac : std_logic_vector(47 downto 0);
-signal rc_dest_mac : std_logic_vector(47 downto 0);
-signal rc_src_ip : std_logic_vector(31 downto 0);
-signal rc_dest_ip : std_logic_vector(31 downto 0);
-signal rc_src_udp : std_logic_vector(15 downto 0);
-signal rc_dest_udp : std_logic_vector(15 downto 0);
-
-signal mc_dest_mac : std_logic_vector(47 downto 0);
-signal mc_dest_ip : std_logic_vector(31 downto 0);
-signal mc_dest_udp : std_logic_vector(15 downto 0);
-signal mc_src_mac : std_logic_vector(47 downto 0);
-signal mc_src_ip : std_logic_vector(31 downto 0);
-signal mc_src_udp : std_logic_vector(15 downto 0);
-
-signal dbg_ft : std_logic_vector(63 downto 0);
-
-signal fr_ip_proto : std_logic_vector(7 downto 0);
-signal mc_ip_proto : std_logic_vector(7 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
-attribute syn_preserve of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
-
-signal pcs_txd_q, pcs_rxd_q : std_logic_vector(7 downto 0);
-signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q : std_logic;
-
-signal pcs_txd_qq, pcs_rxd_qq : std_logic_vector(7 downto 0);
-signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq : std_logic;
-
-signal timeout_ctr : std_logic_vector(31 downto 0);
-signal timeout_noticed : std_Logic;
-attribute syn_keep of timeout_noticed : signal is true;
-attribute syn_preserve of timeout_noticed : signal is true;
-
-signal make_reset : std_logic;
-signal idle_too_long : std_logic;
-signal mc_ident : std_logic_vector(15 downto 0);
-
-signal monitor_tx_packets : std_logic_vector(31 downto 0);
-signal monitor_rx_bytes, monitor_rx_frames, monitor_tx_bytes, monitor_tx_frames : std_logic_vector(31 downto 0);
-signal insert_ttype, additional_hdr : std_logic;
-signal dbg_hist, dbg_hist2 : hist_array;
-signal mac_reset : std_logic;
-signal global_reset, rst_n, ff : std_logic;
-
- signal gbe_cts_number : std_logic_vector(15 downto 0);
- signal gbe_cts_code : std_logic_vector(7 downto 0);
- signal gbe_cts_information : std_logic_vector(7 downto 0);
- signal gbe_cts_start_readout : std_logic;
- signal gbe_cts_readout_type : std_logic_vector(3 downto 0);
- signal gbe_cts_readout_finished : std_logic;
- signal gbe_cts_status_bits : std_logic_vector(31 downto 0);
- signal gbe_fee_data : std_logic_vector(15 downto 0);
- signal gbe_fee_dataready : std_logic;
- signal gbe_fee_read : std_logic;
- signal gbe_fee_status_bits : std_logic_vector(31 downto 0);
- signal gbe_fee_busy : std_logic;
-
- signal max_sub, max_queue, max_subs_in_queue, max_single_sub : std_logic_vector(15 downto 0);
- signal dhcp_done, link_ok, soft_rst : std_logic;
-
-signal dum_busy, dum_read, dum_dataready, dum_rd_en, dum_frame_ready : std_logic;
-signal dum_data, dum_frame_size : std_logic_vector(15 downto 0);
-signal dum_frame_proto : std_logic_vector(4 downto 0);
-signal dum_q : std_logic_vector(8 downto 0);
-
-begin
-
-stage_ctrl_regs <= STAGE_CTRL_REGS_IN;
-
-reset_sync : process(GSR_N, CLK)
-begin
- if (GSR_N = '0') then
- ff <= '0';
- rst_n <= '0';
- elsif rising_edge(CLK) then
- ff <= '1';
- rst_n <= ff;
- end if;
-end process reset_sync;
-
-global_reset <= not rst_n; -- or soft_rst;
-
--- gk 23.04.10
-LED_PACKET_SENT_OUT <= '0'; --timeout_noticed; --pc_ready;
-LED_AN_DONE_N_OUT <= dhcp_done; --not pcs_an_complete;
-
-fc_ihl_version <= x"45";
-fc_tos <= x"10";
-fc_ttl <= x"ff";
-
---reset_dhcp <= not GSR_N;
-
---soft_gbe_reset <= '1' when soft_rst = '1' or (dhcp_done = '0' and rst_ctr(24) = '1') else '0';
-
-main_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate
- MAIN_CONTROL : trb_net16_gbe_main_control
- generic map(
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- DO_SIMULATION => DO_SIMULATION
- )
- port map(
- CLK => CLK,
- CLK_125 => serdes_clk_125,
- RESET => RESET,
-
- MC_LINK_OK_OUT => link_ok,
- MC_RESET_LINK_IN => global_reset,
- MC_IDLE_TOO_LONG_OUT => idle_too_long,
- MC_DHCP_DONE_OUT => dhcp_done,
-
- -- signals to/from receive controller
- RC_FRAME_WAITING_IN => rc_frame_ready,
- RC_LOADING_DONE_OUT => rc_loading_done,
- RC_DATA_IN => rc_q,
- RC_RD_EN_OUT => rc_rd_en,
- RC_FRAME_SIZE_IN => rc_frame_size,
- RC_FRAME_PROTO_IN => rc_frame_proto,
-
- RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
- RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
- RC_SRC_IP_ADDRESS_IN => rc_src_ip,
- RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
- RC_SRC_UDP_PORT_IN => rc_src_udp,
- RC_DEST_UDP_PORT_IN => rc_dest_udp,
-
- -- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
- TC_DATA_OUT => mc_data,
- TC_RD_EN_IN => mc_wr_en,
- --TC_DATA_NOT_VALID_OUT => tc_data_not_valid,
- TC_FRAME_SIZE_OUT => mc_frame_size,
- TC_FRAME_TYPE_OUT => mc_type,
- TC_IP_PROTOCOL_OUT => mc_ip_proto,
- TC_IDENT_OUT => mc_ident,
-
- TC_DEST_MAC_OUT => mc_dest_mac,
- TC_DEST_IP_OUT => mc_dest_ip,
- TC_DEST_UDP_OUT => mc_dest_udp,
- TC_SRC_MAC_OUT => mc_src_mac,
- TC_SRC_IP_OUT => mc_src_ip,
- TC_SRC_UDP_OUT => mc_src_udp,
- TC_TRANSMIT_DONE_IN => mc_transmit_done,
-
- -- signals to/from sgmii/gbe pcs_an_complete
- PCS_AN_COMPLETE_IN => pcs_an_complete,
-
- -- signals to/from hub
- MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN,
- GSC_CLK_IN => GSC_CLK_IN,
- GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => GSC_INIT_READ_IN,
- GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
- GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
- GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
- GSC_BUSY_IN => GSC_BUSY_IN,
-
- MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT,
-
- -- CTS interface
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data payload interface
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
-
- CFG_GBE_ENABLE_IN => use_gbe,
- CFG_IPU_ENABLE_IN => use_trbnet,
- CFG_MULT_ENABLE_IN => use_multievents,
- CFG_SUBEVENT_ID_IN => pc_event_id,
- CFG_SUBEVENT_DEC_IN => pc_decoding,
- CFG_QUEUE_DEC_IN => pc_queue_dec,
- CFG_READOUT_CTR_IN => readout_ctr,
- CFG_READOUT_CTR_VALID_IN => readout_ctr_valid,
- CFG_INSERT_TTYPE_IN => insert_ttype,
- CFG_MAX_SUB_IN => max_sub,
- CFG_MAX_QUEUE_IN => max_queue,
- CFG_MAX_SUBS_IN_QUEUE_IN => max_subs_in_queue,
- CFG_MAX_SINGLE_SUB_IN => max_single_sub,
-
- CFG_ADDITIONAL_HDR_IN => additional_hdr,
-
- -- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT => mac_haddr,
- TSM_HDATA_OUT => mac_hdataout,
- TSM_HCS_N_OUT => mac_hcs,
- TSM_HWRITE_N_OUT => mac_hwrite,
- TSM_HREAD_N_OUT => mac_hread,
- TSM_HREADY_N_IN => mac_hready,
- TSM_HDATA_EN_N_IN => mac_hdata_en,
- TSM_RX_STAT_VEC_IN => mac_rx_stat_vec,
- TSM_RX_STAT_EN_IN => mac_rx_stat_en,
-
- MONITOR_SELECT_REC_OUT => dbg_select_rec,
- MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes,
- MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes,
- MONITOR_SELECT_SENT_OUT => dbg_select_sent,
- MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in,
- MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out,
- MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen,
-
- DATA_HIST_OUT => dbg_hist,
- SCTRL_HIST_OUT => dbg_hist2
- );
-end generate main_gen;
-
-main_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate
- MAIN_CONTROL : trb_net16_gbe_main_control
- generic map(
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- DO_SIMULATION => DO_SIMULATION
- )
- port map(
- CLK => CLK,
- CLK_125 => serdes_clk_125,
- RESET => RESET,
-
- MC_LINK_OK_OUT => link_ok,
- MC_RESET_LINK_IN => global_reset,
- MC_IDLE_TOO_LONG_OUT => idle_too_long,
- MC_DHCP_DONE_OUT => dhcp_done,
-
- -- signals to/from receive controller
- RC_FRAME_WAITING_IN => rc_frame_ready,
- RC_LOADING_DONE_OUT => rc_loading_done,
- RC_DATA_IN => rc_q,
- RC_RD_EN_OUT => rc_rd_en,
- RC_FRAME_SIZE_IN => rc_frame_size,
- RC_FRAME_PROTO_IN => rc_frame_proto,
-
- RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
- RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
- RC_SRC_IP_ADDRESS_IN => rc_src_ip,
- RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
- RC_SRC_UDP_PORT_IN => rc_src_udp,
- RC_DEST_UDP_PORT_IN => rc_dest_udp,
-
- -- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
- TC_DATA_OUT => mc_data,
- TC_RD_EN_IN => mc_wr_en,
- --TC_DATA_NOT_VALID_OUT => tc_data_not_valid,
- TC_FRAME_SIZE_OUT => mc_frame_size,
- TC_FRAME_TYPE_OUT => mc_type,
- TC_IP_PROTOCOL_OUT => mc_ip_proto,
- TC_IDENT_OUT => mc_ident,
-
- TC_DEST_MAC_OUT => mc_dest_mac,
- TC_DEST_IP_OUT => mc_dest_ip,
- TC_DEST_UDP_OUT => mc_dest_udp,
- TC_SRC_MAC_OUT => mc_src_mac,
- TC_SRC_IP_OUT => mc_src_ip,
- TC_SRC_UDP_OUT => mc_src_udp,
- TC_TRANSMIT_DONE_IN => mc_transmit_done,
-
- -- signals to/from sgmii/gbe pcs_an_complete
- PCS_AN_COMPLETE_IN => pcs_an_complete,
-
- -- signals to/from hub
- MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN,
- GSC_CLK_IN => GSC_CLK_IN,
- GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => '1', --GSC_INIT_READ_IN,
- GSC_REPLY_DATAREADY_IN => dum_dataready, --GSC_REPLY_DATAREADY_IN,
- GSC_REPLY_DATA_IN => dum_data, --GSC_REPLY_DATA_IN,
- GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => dum_read, --GSC_REPLY_READ_OUT,
- GSC_BUSY_IN => dum_busy, --GSC_BUSY_IN,
-
- MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT,
-
- -- CTS interface
- CTS_NUMBER_IN => gbe_cts_number,
- CTS_CODE_IN => gbe_cts_code,
- CTS_INFORMATION_IN => gbe_cts_information,
- CTS_READOUT_TYPE_IN => gbe_cts_readout_type,
- CTS_START_READOUT_IN => gbe_cts_start_readout,
- CTS_DATA_OUT => open,
- CTS_DATAREADY_OUT => open,
- CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished,
- CTS_READ_IN => '1',
- CTS_LENGTH_OUT => open,
- CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits,
- --Data payload interface
- FEE_DATA_IN => gbe_fee_data,
- FEE_DATAREADY_IN => gbe_fee_dataready,
- FEE_READ_OUT => gbe_fee_read,
- FEE_STATUS_BITS_IN => gbe_fee_status_bits,
- FEE_BUSY_IN => gbe_fee_busy,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
-
- CFG_GBE_ENABLE_IN => '1',
- CFG_IPU_ENABLE_IN => '0',
- CFG_MULT_ENABLE_IN => '0',
- CFG_SUBEVENT_ID_IN => x"0000_00cf",
- CFG_SUBEVENT_DEC_IN => x"0002_0001",
- CFG_QUEUE_DEC_IN => x"0003_0062",
- CFG_READOUT_CTR_IN => x"00_0000",
- CFG_READOUT_CTR_VALID_IN => '0',
- CFG_INSERT_TTYPE_IN => '0',
- CFG_MAX_SUB_IN => x"e998", -- 59800
- CFG_MAX_QUEUE_IN => x"ea60", -- 60000
- CFG_MAX_SUBS_IN_QUEUE_IN => x"00c8", -- 200
- CFG_MAX_SINGLE_SUB_IN => x"e998", --x"7d00", -- 32000
-
- CFG_ADDITIONAL_HDR_IN => '0',
-
- -- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT => mac_haddr,
- TSM_HDATA_OUT => mac_hdataout,
- TSM_HCS_N_OUT => mac_hcs,
- TSM_HWRITE_N_OUT => mac_hwrite,
- TSM_HREAD_N_OUT => mac_hread,
- TSM_HREADY_N_IN => mac_hready,
- TSM_HDATA_EN_N_IN => mac_hdata_en,
- TSM_RX_STAT_VEC_IN => mac_rx_stat_vec,
- TSM_RX_STAT_EN_IN => mac_rx_stat_en,
-
- MONITOR_SELECT_REC_OUT => dbg_select_rec,
- MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes,
- MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes,
- MONITOR_SELECT_SENT_OUT => dbg_select_sent,
- MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in,
- MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out,
- MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen,
-
- DATA_HIST_OUT => dbg_hist,
- SCTRL_HIST_OUT => dbg_hist2
- );
-
- dummy : gbe_ipu_dummy
- generic map(
- DO_SIMULATION => DO_SIMULATION,
- FIXED_SIZE_MODE => FIXED_SIZE_MODE,
- INCREMENTAL_MODE => INCREMENTAL_MODE,
- FIXED_SIZE => FIXED_SIZE,
- UP_DOWN_MODE => UP_DOWN_MODE,
- UP_DOWN_LIMIT => UP_DOWN_LIMIT,
- FIXED_DELAY_MODE => FIXED_DELAY_MODE,
- FIXED_DELAY => FIXED_DELAY
- )
- port map(
- clk => CLK,
- rst => global_reset,
- GBE_READY_IN => dhcp_done,
-
- CTS_NUMBER_OUT =>gbe_cts_number,
- CTS_CODE_OUT =>gbe_cts_code,
- CTS_INFORMATION_OUT =>gbe_cts_information,
- CTS_READOUT_TYPE_OUT =>gbe_cts_readout_type,
- CTS_START_READOUT_OUT =>gbe_cts_start_readout,
- CTS_DATA_IN =>(others => '0'),
- CTS_DATAREADY_IN =>'0',
- CTS_READOUT_FINISHED_IN =>gbe_cts_readout_finished,
- CTS_READ_OUT =>open,
- CTS_LENGTH_IN =>(others => '0'),
- CTS_ERROR_PATTERN_IN =>gbe_cts_status_bits,
- -- Data payload interfac =>
- FEE_DATA_OUT =>gbe_fee_data,
- FEE_DATAREADY_OUT =>gbe_fee_dataready,
- FEE_READ_IN =>gbe_fee_read,
- FEE_STATUS_BITS_OUT =>gbe_fee_status_bits,
- FEE_BUSY_OUT =>gbe_fee_busy
- );
-
--- sctrl_dummy : gbe_sctrl_dummy
--- generic map(
--- DO_SIMULATION => DO_SIMULATION,
--- FIXED_DELAY_MODE => 0,
--- FIXED_DELAY => 4096
--- )
--- port map(
--- clk => clk,
--- rst => global_reset,
---
--- RC_RD_EN_IN => dum_rd_en,
--- RC_Q_OUT => dum_q,
--- RC_FRAME_WAITING_OUT => dum_frame_ready,
--- RC_LOADING_DONE_IN => '0',
--- RC_FRAME_SIZE_OUT => dum_frame_size,
--- RC_FRAME_PROTO_OUT => dum_frame_proto,
---
--- RC_SRC_MAC_ADDRESS_OUT => open,
--- RC_DEST_MAC_ADDRESS_OUT => open,
--- RC_SRC_IP_ADDRESS_OUT => open,
--- RC_DEST_IP_ADDRESS_OUT => open,
--- RC_SRC_UDP_PORT_OUT => open,
--- RC_DEST_UDP_PORT_OUT => open,
---
--- GSC_REPLY_DATAREADY_OUT => dum_dataready,
--- GSC_REPLY_DATA_OUT => dum_data,
--- GSC_REPLY_PACKET_NUM_OUT => open,
--- GSC_REPLY_READ_IN => dum_read,
--- GSC_BUSY_OUT => dum_busy
--- );
-
-
- end generate main_with_dummy_gen;
-
- MAKE_RESET_OUT <= make_reset; -- or idle_too_long;
-
-transmit_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate
-
- TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
- port map(
- CLK => CLK,
- RESET => global_reset, --RESET,
-
- -- signal to/from main controller
- TC_DATAREADY_IN => mc_transmit_ctrl,
- TC_RD_EN_OUT => mc_wr_en,
- TC_DATA_IN => mc_data(7 downto 0),
- TC_FRAME_SIZE_IN => mc_frame_size,
- TC_FRAME_TYPE_IN => mc_type,
- TC_IP_PROTOCOL_IN => mc_ip_proto,
- TC_DEST_MAC_IN => mc_dest_mac,
- TC_DEST_IP_IN => mc_dest_ip,
- TC_DEST_UDP_IN => mc_dest_udp,
- TC_SRC_MAC_IN => mc_src_mac,
- TC_SRC_IP_IN => mc_src_ip,
- TC_SRC_UDP_IN => mc_src_udp,
- TC_TRANSMISSION_DONE_OUT => mc_transmit_done,
- TC_IDENT_IN => mc_ident,
- TC_MAX_FRAME_IN => pc_max_frame_size,
-
- -- signal to/from frame constructor
- FC_DATA_OUT => fc_data,
- FC_WR_EN_OUT => fc_wr_en,
- FC_READY_IN => fc_ready,
- FC_H_READY_IN => fc_h_ready,
- FC_FRAME_TYPE_OUT => fc_type,
- FC_IP_SIZE_OUT => fc_ip_size,
- FC_UDP_SIZE_OUT => fc_udp_size,
- FC_IDENT_OUT => fc_ident,
- FC_FLAGS_OFFSET_OUT => fc_flags_offset,
- FC_SOD_OUT => fc_sod,
- FC_EOD_OUT => fc_eod,
- FC_IP_PROTOCOL_OUT => fc_protocol,
-
- DEST_MAC_ADDRESS_OUT => fc_dest_mac,
- DEST_IP_ADDRESS_OUT => fc_dest_ip,
- DEST_UDP_PORT_OUT => fc_dest_udp,
- SRC_MAC_ADDRESS_OUT => fc_src_mac,
- SRC_IP_ADDRESS_OUT => fc_src_ip,
- SRC_UDP_PORT_OUT => fc_src_udp,
-
- MONITOR_TX_PACKETS_OUT => monitor_tx_packets
- );
-end generate transmit_gen;
-
-transmit_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate
- TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
-port map(
- CLK => CLK,
- RESET => global_reset, --RESET,
-
--- signal to/from main controller
- TC_DATAREADY_IN => mc_transmit_ctrl,
- TC_RD_EN_OUT => mc_wr_en,
- TC_DATA_IN => mc_data(7 downto 0),
- TC_FRAME_SIZE_IN => mc_frame_size,
- TC_FRAME_TYPE_IN => mc_type,
- TC_IP_PROTOCOL_IN => mc_ip_proto,
- TC_DEST_MAC_IN => mc_dest_mac,
- TC_DEST_IP_IN => mc_dest_ip,
- TC_DEST_UDP_IN => mc_dest_udp,
- TC_SRC_MAC_IN => mc_src_mac,
- TC_SRC_IP_IN => mc_src_ip,
- TC_SRC_UDP_IN => mc_src_udp,
- TC_TRANSMISSION_DONE_OUT => mc_transmit_done,
- TC_IDENT_IN => mc_ident,
- TC_MAX_FRAME_IN => x"0578",
-
--- signal to/from frame constructor
- FC_DATA_OUT => fc_data,
- FC_WR_EN_OUT => fc_wr_en,
- FC_READY_IN => fc_ready,
- FC_H_READY_IN => fc_h_ready,
- FC_FRAME_TYPE_OUT => fc_type,
- FC_IP_SIZE_OUT => fc_ip_size,
- FC_UDP_SIZE_OUT => fc_udp_size,
- FC_IDENT_OUT => fc_ident,
- FC_FLAGS_OFFSET_OUT => fc_flags_offset,
- FC_SOD_OUT => fc_sod,
- FC_EOD_OUT => fc_eod,
- FC_IP_PROTOCOL_OUT => fc_protocol,
-
- DEST_MAC_ADDRESS_OUT => fc_dest_mac,
- DEST_IP_ADDRESS_OUT => fc_dest_ip,
- DEST_UDP_PORT_OUT => fc_dest_udp,
- SRC_MAC_ADDRESS_OUT => fc_src_mac,
- SRC_IP_ADDRESS_OUT => fc_src_ip,
- SRC_UDP_PORT_OUT => fc_src_udp,
-
- MONITOR_TX_PACKETS_OUT => monitor_tx_packets
-);
-end generate transmit_with_dummy_gen;
-
-
-setup_imp_gen : if (DO_SIMULATION = 0) generate
-SETUP : gbe_setup
-port map(
- CLK => CLK,
- RESET => global_reset, --RESET,
-
- -- interface to regio bus
- BUS_ADDR_IN => BUS_ADDR_IN,
- BUS_DATA_IN => BUS_DATA_IN,
- BUS_DATA_OUT => BUS_DATA_OUT,
- BUS_WRITE_EN_IN => BUS_WRITE_EN_IN,
- BUS_READ_EN_IN => BUS_READ_EN_IN,
- BUS_ACK_OUT => BUS_ACK_OUT,
-
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT => pc_event_id,
- GBE_SUBEVENT_DEC_OUT => pc_decoding,
- GBE_QUEUE_DEC_OUT => pc_queue_dec,
- GBE_MAX_FRAME_OUT => pc_max_frame_size,
- GBE_USE_GBE_OUT => use_gbe,
- GBE_USE_TRBNET_OUT => use_trbnet,
- GBE_USE_MULTIEVENTS_OUT => use_multievents,
- GBE_READOUT_CTR_OUT => readout_ctr,
- GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid,
- GBE_ALLOW_RX_OUT => allow_rx,
- GBE_ADDITIONAL_HDR_OUT => additional_hdr,
- GBE_INSERT_TTYPE_OUT => insert_ttype,
- GBE_SOFT_RESET_OUT => soft_rst,
-
- GBE_MAX_SUB_OUT => max_sub,
- GBE_MAX_QUEUE_OUT => max_queue,
- GBE_MAX_SUBS_IN_QUEUE_OUT => max_subs_in_queue,
- GBE_MAX_SINGLE_SUB_OUT => max_single_sub,
-
- MONITOR_RX_BYTES_IN => monitor_rx_bytes,
- MONITOR_RX_FRAMES_IN => monitor_rx_frames,
- MONITOR_TX_BYTES_IN => monitor_tx_bytes,
- MONITOR_TX_FRAMES_IN => monitor_tx_frames,
- MONITOR_TX_PACKETS_IN => monitor_tx_packets,
- MONITOR_DROPPED_IN => monitor_dropped,
-
- MONITOR_SELECT_REC_IN => dbg_select_rec,
- MONITOR_SELECT_REC_BYTES_IN => dbg_select_rec_bytes,
- MONITOR_SELECT_SENT_BYTES_IN => dbg_select_sent_bytes,
- MONITOR_SELECT_SENT_IN => dbg_select_sent,
- MONITOR_SELECT_DROP_IN_IN => dbg_select_drop_in,
- MONITOR_SELECT_DROP_OUT_IN => dbg_select_drop_out,
- MONITOR_SELECT_GEN_DBG_IN => dbg_select_gen,
-
- DATA_HIST_IN => dbg_hist,
- SCTRL_HIST_IN => dbg_hist2
-);
-end generate;
-
-setup_sim_gen : if (DO_SIMULATION = 1) generate
- use_gbe <= '1';
- allow_rx <= '1';
- allow_large <= '0';
-end generate;
-
--- Third stage: Frame Constructor
-FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
-port map(
- -- ports for user logic
- RESET => global_reset, --RESET,
- CLK => CLK,
- LINK_OK_IN => '1', --link_ok,
- --
- WR_EN_IN => fc_wr_en,
- DATA_IN => fc_data,
- START_OF_DATA_IN => fc_sod,
- END_OF_DATA_IN => fc_eod,
- IP_F_SIZE_IN => fc_ip_size,
- UDP_P_SIZE_IN => fc_udp_size,
- HEADERS_READY_OUT => fc_h_ready,
- READY_OUT => fc_ready,
- DEST_MAC_ADDRESS_IN => fc_dest_mac,
- DEST_IP_ADDRESS_IN => fc_dest_ip,
- DEST_UDP_PORT_IN => fc_dest_udp,
- SRC_MAC_ADDRESS_IN => fc_src_mac,
- SRC_IP_ADDRESS_IN => fc_src_ip,
- SRC_UDP_PORT_IN => fc_src_udp,
- FRAME_TYPE_IN => fc_type,
- IHL_VERSION_IN => fc_ihl_version,
- TOS_IN => fc_tos,
- IDENTIFICATION_IN => fc_ident,
- FLAGS_OFFSET_IN => fc_flags_offset,
- TTL_IN => fc_ttl,
- PROTOCOL_IN => fc_protocol,
- FRAME_DELAY_IN => (others => '0'),
-
- RD_CLK => serdes_clk_125,
- FT_DATA_OUT => ft_data,
- FT_TX_EMPTY_OUT => ft_tx_empty,
- FT_TX_RD_EN_IN => mac_tx_read,
- FT_START_OF_PACKET_OUT => ft_start_of_packet,
- FT_TX_DONE_IN => mac_tx_done,
- FT_TX_DISCFRM_IN => mac_tx_discfrm,
-
- MONITOR_TX_BYTES_OUT => monitor_tx_bytes,
- MONITOR_TX_FRAMES_OUT => monitor_tx_frames
-);
-
-dbg_q(15 downto 9) <= (others => '0');
-
-FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
-port map(
- CLK => CLK,
- RESET => global_reset, --RESET,
- LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
- TX_MAC_CLK => serdes_clk_125,
- TX_EMPTY_IN => ft_tx_empty,
- START_OF_PACKET_IN => ft_start_of_packet,
- DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10
-
- TX_FIFOAVAIL_OUT => mac_fifoavail,
- TX_FIFOEOF_OUT => mac_fifoeof,
- TX_FIFOEMPTY_OUT => mac_fifoempty,
- TX_DONE_IN => mac_tx_done,
- TX_STAT_EN_IN => mac_tx_staten,
- TX_STATVEC_IN => mac_tx_statevec,
- TX_DISCFRM_IN => mac_tx_discfrm,
- -- Debug
- BSM_INIT_OUT => ft_bsm_init,
- BSM_MAC_OUT => ft_bsm_mac,
- BSM_TRANS_OUT => ft_bsm_trans,
- DBG_RD_DONE_OUT => open,
- DBG_INIT_DONE_OUT => open,
- DBG_ENABLED_OUT => open,
- DEBUG_OUT => dbg_ft
- --DEBUG_OUT(31 downto 0) => open,
- --DEBUG_OUT(63 downto 32) => open
-);
-
-rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
-
- RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
- port map(
- CLK => CLK,
- RESET => global_reset, --RESET,
-
- -- signals to/from frame_receiver
- RC_DATA_IN => fr_q,
- FR_RD_EN_OUT => fr_rd_en,
- FR_FRAME_VALID_IN => fr_frame_valid,
- FR_GET_FRAME_OUT => fr_get_frame,
- FR_FRAME_SIZE_IN => fr_frame_size,
- FR_FRAME_PROTO_IN => fr_frame_proto,
- FR_IP_PROTOCOL_IN => fr_ip_proto,
-
- FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
- FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
- FR_SRC_IP_ADDRESS_IN => fr_src_ip,
- FR_DEST_IP_ADDRESS_IN => fr_dest_ip,
- FR_SRC_UDP_PORT_IN => fr_src_udp,
- FR_DEST_UDP_PORT_IN => fr_dest_udp,
-
- -- signals to/from main controller
- RC_RD_EN_IN => rc_rd_en,
- RC_Q_OUT => rc_q,
- RC_FRAME_WAITING_OUT => rc_frame_ready,
- RC_LOADING_DONE_IN => rc_loading_done,
- RC_FRAME_SIZE_OUT => rc_frame_size,
- RC_FRAME_PROTO_OUT => rc_frame_proto,
-
- RC_SRC_MAC_ADDRESS_OUT => rc_src_mac,
- RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
- RC_SRC_IP_ADDRESS_OUT => rc_src_ip,
- RC_DEST_IP_ADDRESS_OUT => rc_dest_ip,
- RC_SRC_UDP_PORT_OUT => rc_src_udp,
- RC_DEST_UDP_PORT_OUT => rc_dest_udp,
-
- -- statistics
- FRAMES_RECEIVED_OUT => rc_frames_rec_ctr,
- BYTES_RECEIVED_OUT => rc_bytes_rec,
-
-
- DEBUG_OUT => rc_debug
- );
-
- FRAME_RECEIVER : trb_net16_gbe_frame_receiver
- port map(
- CLK => CLK,
- RESET => global_reset, --RESET,
- LINK_OK_IN => link_ok,
- ALLOW_RX_IN => allow_rx,
- RX_MAC_CLK => serdes_rx_clk, --serdes_clk_125,
-
- -- input signals from TS_MAC
- MAC_RX_EOF_IN => mac_rx_eof,
- MAC_RX_ER_IN => mac_rx_er,
- MAC_RXD_IN => mac_rxd,
- MAC_RX_EN_IN => mac_rx_en,
- MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err,
- MAC_RX_FIFO_FULL_OUT => mac_rx_fifo_full,
- MAC_RX_STAT_EN_IN => mac_rx_stat_en,
- MAC_RX_STAT_VEC_IN => mac_rx_stat_vec,
- -- output signal to control logic
- FR_Q_OUT => fr_q,
- FR_RD_EN_IN => fr_rd_en,
- FR_FRAME_VALID_OUT => fr_frame_valid,
- FR_GET_FRAME_IN => fr_get_frame,
- FR_FRAME_SIZE_OUT => fr_frame_size,
- FR_FRAME_PROTO_OUT => fr_frame_proto,
- FR_IP_PROTOCOL_OUT => fr_ip_proto,
- FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types,
- FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip,
- FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp,
- FR_VLAN_ID_IN => (others => '0'), --vlan_id,
-
- FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
- FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
- FR_SRC_IP_ADDRESS_OUT => fr_src_ip,
- FR_DEST_IP_ADDRESS_OUT => fr_dest_ip,
- FR_SRC_UDP_PORT_OUT => fr_src_udp,
- FR_DEST_UDP_PORT_OUT => fr_dest_udp,
-
- MONITOR_RX_BYTES_OUT => monitor_rx_bytes,
- MONITOR_RX_FRAMES_OUT => monitor_rx_frames,
- MONITOR_DROPPED_OUT => monitor_dropped
- );
-
-end generate rx_enable_gen;
-
-rx_disable_gen : if (RX_PATH_ENABLE = 0) generate
-
-
- rc_q <= (others => '0');
- rc_frame_ready <= '0';
- rc_frame_size <= (others => '0');
- rc_frame_proto <= (others => '0');
-
- rc_src_mac <= (others => '0');
- rc_dest_mac <= (others => '0');
- rc_src_ip <= (others => '0');
- rc_dest_ip <= (others => '0');
- rc_src_udp <= (others => '0');
- rc_dest_udp <= (others => '0');
-
- rc_frames_rec_ctr <= (others => '0');
- rc_bytes_rec <= (others => '0');
- rc_debug <= (others => '0');
-
- monitor_rx_bytes <= (others => '0');
- monitor_rx_frames <= (others => '0');
- monitor_dropped <= (others => '0');
-
- mac_rx_fifo_full <= '0';
-
-end generate rx_disable_gen;
-
-
--- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in
-imp_gen: if (DO_SIMULATION = 0) generate
- --------------------------------------------------------------------------------------------
- --------------------------------------------------------------------------------------------
- -- Implementation
- --------------------------------------------------------------------------------------------
- --------------------------------------------------------------------------------------------
-
-
- TIMEOUT_CTR_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1' or mac_tx_done = '1') then
- timeout_ctr <= (others => '0');
- else
- timeout_ctr <= timeout_ctr + x"1";
- end if;
- end if;
- end process TIMEOUT_CTR_PROC;
-
- TIMEOUT_NOTICED_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- timeout_noticed <= '0';
- elsif (timeout_ctr(30) = '1') then
- timeout_noticed <= '1';
- end if;
- end if;
- end process TIMEOUT_NOTICED_PROC;
-
- mac_reset <= not RESET;
-
- -- MAC part
- MAC: tsmac35 --tsmac36 --tsmac35
- port map(
- ----------------- clock and reset port declarations ------------------
- hclk => CLK,
- txmac_clk => serdes_clk_125,
- rxmac_clk => serdes_rx_clk, --serdes_clk_125,
- reset_n => GSR_N,
- txmac_clk_en => mac_tx_clk_en,
- rxmac_clk_en => mac_rx_clk_en,
- ------------------- Input signals to the GMII ---------------- NOT USED
- rxd => pcs_rxd_qq, --x"00",
- rx_dv => pcs_rx_en_qq, --'0',
- rx_er => pcs_rx_er_qq, --'0',
- col => mac_col,
- crs => mac_crs,
- -------------------- Input signals to the CPU I/F -------------------
- haddr => mac_haddr,
- hdatain => mac_hdataout,
- hcs_n => mac_hcs,
- hwrite_n => mac_hwrite,
- hread_n => mac_hread,
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata => ft_data(7 downto 0),
- tx_fifoavail => mac_fifoavail,
- tx_fifoeof => mac_fifoeof,
- tx_fifoempty => mac_fifoempty,
- tx_sndpaustim => x"0000",
- tx_sndpausreq => '0',
- tx_fifoctrl => '0', -- always data frame
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
- rx_fifo_full => mac_rx_fifo_full, --'0',
- ignore_pkt => '0',
- ---------------- Output signals from the GMII -----------------------
- txd => pcs_txd,
- tx_en => pcs_tx_en,
- tx_er => pcs_tx_er,
- ----------------- Output signals from the CPU I/F -------------------
- hdataout => open,
- hdataout_en_n => mac_hdata_en,
- hready_n => mac_hready,
- cpu_if_gbit_en => tsmac_gbit_en,
- ------------- Output signals from the Tx MAC FIFO I/F ---------------
- tx_macread => mac_tx_read,
- tx_discfrm => mac_tx_discfrm,
- tx_staten => mac_tx_staten, -- gk 08.06.10
- tx_statvec => mac_tx_statevec, -- gk 08.06.10
- tx_done => mac_tx_done,
- ------------- Output signals from the Rx MAC FIFO I/F ---------------
- rx_fifo_error => mac_rx_fifo_err, --open,
- rx_stat_vector => mac_rx_stat_vec, --open,
- rx_dbout => mac_rxd, --open,
- rx_write => mac_rx_en, --open,
- rx_stat_en => mac_rx_stat_en, --open,
- rx_eof => mac_rx_eof, --open,
- rx_error => mac_rx_er --open
- );
-
- SYNC_GMII_RX_PROC : process(serdes_rx_clk)
- begin
- if rising_edge(serdes_rx_clk) then
- pcs_rxd_q <= pcs_rxd;
- pcs_rx_en_q <= pcs_rx_en;
- pcs_rx_er_q <= pcs_rx_er;
-
- pcs_rxd_qq <= pcs_rxd_q;
- pcs_rx_en_qq <= pcs_rx_en_q;
- pcs_rx_er_qq <= pcs_rx_er_q;
- --mac_col_q <= mac_col;
- --mac_crs_q <= mac_crs;
- end if;
- end process SYNC_GMII_RX_PROC;
-
- SYNC_GMII_TX_PROC : process(serdes_clk_125)
- begin
- if rising_edge(serdes_clk_125) then
- pcs_txd_q <= pcs_txd;
- pcs_tx_en_q <= pcs_tx_en;
- pcs_tx_er_q <= pcs_tx_er;
-
- pcs_txd_qq <= pcs_txd_q;
- pcs_tx_en_qq <= pcs_tx_en_q;
- pcs_tx_er_qq <= pcs_tx_er_q;
- end if;
- end process SYNC_GMII_TX_PROC;
-
- -- gk 08.06.10
- dbg_statevec_proc : process(serdes_clk_125)
- begin
- if rising_edge(serdes_clk_125) then
- if (RESET = '1') then
- dbg_ft1 <= (others => '0');
- elsif (mac_tx_staten = '1') then
- dbg_ft1(30 downto 0) <= mac_tx_statevec;
- dbg_ft1(31) <= mac_tx_discfrm;
- end if;
- end if;
- end process dbg_statevec_proc;
-
- serdes_intclk_gen: if (USE_125MHZ_EXTCLK = 0) generate
- -- PHY part
- PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b
- generic map(
- USE_125MHZ_EXTCLK => 0
- )
- port map(
- RESET => global_reset, --soft_gbe_reset, --RESET,
- GSR_N => GSR_N,
- CLK_125_OUT => serdes_clk_125,
- CLK_125_RX_OUT => serdes_rx_clk, --open,
- CLK_125_IN => CLK_125_IN,
- FT_TX_CLK_EN_OUT => mac_tx_clk_en,
- FT_RX_CLK_EN_OUT => mac_rx_clk_en,
- --connection to frame transmitter (tsmac)
- FT_COL_OUT => mac_col,
- FT_CRS_OUT => mac_crs,
- FT_TXD_IN => pcs_txd_qq,
- FT_TX_EN_IN => pcs_tx_en_qq,
- FT_TX_ER_IN => pcs_tx_er_qq,
- FT_RXD_OUT => pcs_rxd,
- FT_RX_EN_OUT => pcs_rx_en,
- FT_RX_ER_OUT => pcs_rx_er,
- --SFP Connection
- SD_RXD_P_IN => SFP_RXD_P_IN,
- SD_RXD_N_IN => SFP_RXD_N_IN,
- SD_TXD_P_OUT => SFP_TXD_P_OUT,
- SD_TXD_N_OUT => SFP_TXD_N_OUT,
- SD_REFCLK_P_IN => SFP_REFCLK_P_IN,
- SD_REFCLK_N_IN => SFP_REFCLK_N_IN,
- SD_PRSNT_N_IN => SFP_PRSNT_N_IN,
- SD_LOS_IN => SFP_LOS_IN,
- SD_TXDIS_OUT => SFP_TXDIS_OUT,
- -- Autonegotiation stuff
- MR_ADV_ABILITY_IN => x"0020", -- full duplex only
- MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability,
- MR_AN_PAGE_RX_OUT => pcs_an_page_rx,
- MR_AN_COMPLETE_OUT => pcs_an_complete,
- MR_RESET_IN => RESET,
- MR_MODE_IN => '0', --MR_MODE_IN,
- MR_AN_ENABLE_IN => '1', -- do autonegotiation
- MR_RESTART_AN_IN => '0', --MR_RESTART_IN,
- -- Status and control port
- STAT_OP => open,
- CTRL_OP => x"0000",
- STAT_DEBUG => pcs_stat_debug, --open,
- CTRL_DEBUG => x"0000_0000_0000_0000"
- );
- end generate serdes_intclk_gen;
-
- serdes_extclk_gen: if (USE_125MHZ_EXTCLK = 1) generate
- -- PHY part
- PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b
- generic map(
- USE_125MHZ_EXTCLK => 1
- )
- port map(
- RESET => global_reset, --soft_gbe_reset, --RESET,
- GSR_N => GSR_N,
- CLK_125_OUT => serdes_clk_125,
- CLK_125_RX_OUT => serdes_rx_clk,
- CLK_125_IN => '0', -- not used
- FT_TX_CLK_EN_OUT => mac_tx_clk_en,
- FT_RX_CLK_EN_OUT => mac_rx_clk_en,
- --connection to frame transmitter (tsmac)
- FT_COL_OUT => mac_col,
- FT_CRS_OUT => mac_crs,
- FT_TXD_IN => pcs_txd,
- FT_TX_EN_IN => pcs_tx_en,
- FT_TX_ER_IN => pcs_tx_er,
- FT_RXD_OUT => pcs_rxd,
- FT_RX_EN_OUT => pcs_rx_en,
- FT_RX_ER_OUT => pcs_rx_er,
- --SFP Connection
- SD_RXD_P_IN => SFP_RXD_P_IN,
- SD_RXD_N_IN => SFP_RXD_N_IN,
- SD_TXD_P_OUT => SFP_TXD_P_OUT,
- SD_TXD_N_OUT => SFP_TXD_N_OUT,
- SD_REFCLK_P_IN => SFP_REFCLK_P_IN,
- SD_REFCLK_N_IN => SFP_REFCLK_N_IN,
- SD_PRSNT_N_IN => SFP_PRSNT_N_IN,
- SD_LOS_IN => SFP_LOS_IN,
- SD_TXDIS_OUT => SFP_TXDIS_OUT,
- -- Autonegotiation stuff
- MR_ADV_ABILITY_IN => x"0020", -- full duplex only
- MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability,
- MR_AN_PAGE_RX_OUT => pcs_an_page_rx,
- MR_AN_COMPLETE_OUT => pcs_an_complete,
- MR_RESET_IN => MR_RESET_IN,
- MR_MODE_IN => MR_MODE_IN,
- MR_AN_ENABLE_IN => '1', -- do autonegotiation
- MR_RESTART_AN_IN => MR_RESTART_IN,
- -- Status and control port
- STAT_OP => open,
- CTRL_OP => x"0000",
- STAT_DEBUG => pcs_stat_debug, --open,
- CTRL_DEBUG => x"0000_0000_0000_0000"
- );
- end generate serdes_extclk_gen;
-
- stage_stat_regs(31 downto 28) <= x"e";
- stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link s-tatus
- stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm
- stage_stat_regs(19) <= '0';
- stage_stat_regs(18) <= link_ok; -- gk 30.09.10
- stage_stat_regs(17) <= pcs_an_complete;
- stage_stat_regs(16) <= pcs_an_page_rx;
- stage_stat_regs(15 downto 0) <= pcs_an_lp_ability;
-
-end generate imp_gen;
-
--- in case of simulation we include a fake MAC and no PHY/SerDes.
-sim_gen: if (DO_SIMULATION = 1) generate
- --------------------------------------------------------------------------------------------
- --------------------------------------------------------------------------------------------
- -- Simulation
- --------------------------------------------------------------------------------------------
- --------------------------------------------------------------------------------------------
- MAC: mb_mac_sim
- port map( --------------------------------------------------------------------------
- --------------- clock, reset, clock enable -------------------------------
- HCLK => CLK,
- TX_MAC_CLK => serdes_clk_125,
- RX_MAC_CLK => serdes_rx_clk, --serdes_clk_125,
- RESET_N => GSR_N,
- TXMAC_CLK_EN => mac_tx_clk_en,
- RXMAC_CLK_EN => mac_rx_clk_en,
- --------------------------------------------------------------------------
- --------------- SGMII receive interface ----------------------------------
- RXD => x"00",
- RX_DV => '0',
- RX_ER => '0',
- COL => mac_col,
- CRS => mac_crs,
- --------------------------------------------------------------------------
- --------------- SGMII transmit interface ---------------------------------
- TXD => pcs_txd,
- TX_EN => pcs_tx_en,
- TX_ER => pcs_tx_er,
- --------------------------------------------------------------------------
- --------------- CPU configuration interface ------------------------------
- HADDR => mac_haddr,
- HDATAIN => mac_hdataout,
- HCS_N => mac_hcs,
- HWRITE_N => mac_hwrite,
- HREAD_N => mac_hread,
- HDATAOUT => open,
- HDATAOUT_EN_N => mac_hdata_en,
- HREADY_N => mac_hready,
- CPU_IF_GBIT_EN => open,
- --------------------------------------------------------------------------
- --------------- Transmit FIFO interface ----------------------------------
- TX_FIFODATA => ft_data(7 downto 0),
- TX_FIFOAVAIL => mac_fifoavail,
- TX_FIFOEOF => mac_fifoeof,
- TX_FIFOEMPTY => mac_fifoempty,
- TX_MACREAD => mac_tx_read,
- TX_DONE => mac_tx_done,
- TX_SNDPAUSTIM => x"0000",
- TX_SNDPAUSREQ => '0',
- TX_FIFOCTRL => '0',
- TX_DISCFRM => open,
- TX_STATEN => open,
- TX_STATVEC => open,
- --------------------------------------------------------------------------
- --------------- Receive FIFO interface -----------------------------------
- RX_DBOUT => open,
- RX_FIFO_FULL => '0',
- IGNORE_PKT => '0',
- RX_FIFO_ERROR => open,
- RX_STAT_VECTOR => open,
- RX_STAT_EN => open,
- RX_WRITE => open,
- RX_EOF => open,
- RX_ERROR => open
- );
-
- -- add external test clock for the MAC part
- serdes_clk_125 <= TEST_CLK;
-
- -- fake signals
- pcs_an_lp_ability <= x"4060";
- pcs_an_page_rx <= '0';
- pcs_an_complete <= '1';
- mac_tx_clk_en <= '1';
- mac_rx_clk_en <= '1';
-
- stage_stat_regs(31 downto 0) <= (others => '0');
-
- pcs_stat_debug(63 downto 0) <= (others => '0');
-
- SFP_TXD_P_OUT <= '1';
- SFP_TXD_N_OUT <= '0';
- SFP_TXDIS_OUT <= '0';
-
- mac_rxd <= MAC_RXD_IN;
- mac_rx_eof <= MAC_RX_EOF_IN;
- mac_rx_en <= MAC_RX_EN_IN;
-
- serdes_rx_clk <= TEST_CLK;
-
-end generate sim_gen;
-
-
---***********************
--- MONITORING & DEBUG
---***********************
-
-
-
-
--- gk 04.08.10
---MON_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0);
--- if (dbg_pc1(28) = '1') then
--- monitor_fifos_q(5 downto 4) <= b"11";
--- else
--- monitor_fifos_q(5 downto 4) <= b"00";
--- end if;
--- if (dbg_pc1(30) = '1') then
--- monitor_fifos_q(7 downto 6) <= b"11";
--- else
--- monitor_fifos_q(7 downto 6) <= b"00";
--- end if;
--- if (dbg_fc1(28) = '1') then
--- monitor_fifos_q(11 downto 8) <= b"1111";
--- else
--- monitor_fifos_q(11 downto 8) <= b"0000";
--- end if;
--- if (pcs_an_complete = '0') then
--- monitor_fifos_q(15 downto 12) <= b"1111";
--- else
--- monitor_fifos_q(15 downto 12) <= b"0000";
--- end if;
--- end if;
---end process MON_PROC;
-
----- gk 28.07.10
---BYTES_SENT_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- bytes_sent_ctr <= (others => '0');
--- elsif (fc_wr_en = '1') then
--- bytes_sent_ctr <= bytes_sent_ctr + x"1";
--- end if;
--- end if;
---end process BYTES_SENT_CTR_PROC;
---
----- gk 02.08.10
---DISCFRM_PROC : process(serdes_clk_125)
---begin
--- if rising_edge(serdes_clk_125) then
--- if (RESET = '1') then
--- discfrm_ctr <= (others => '0');
--- elsif (mac_tx_discfrm = '1') then
--- discfrm_ctr <= discfrm_ctr + x"1";
--- end if;
--- end if;
---end process DISCFRM_PROC;
---
---discfrm_sync : signal_sync
--- generic map(
--- DEPTH => 2,
--- WIDTH => 32
--- )
--- port map(
--- RESET => RESET,
--- D_IN => discfrm_ctr,
--- CLK0 => serdes_clk_125,
--- CLK1 => CLK,
--- D_OUT => monitor_discfrm
--- );
-
-
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-
---***************
--- LOGIC ANALYZER SIGNALS
---***************
---ANALYZER_DEBUG_OUT <= dbg_mc or dbg_tc or (dbg_fc1 & dbg_fc2) or rc_debug or dbg_ft or dbg_fr(63 downto 0) or (dbg_fr(95 downto 64) & x"00000000");
---ANALYZER_DEBUG_OUT(3 downto 0) <= dbg_select_protos(99 downto 96);
---ANALYZER_DEBUG_OUT(63 downto 4) <= (others => '0');
-
--- Outputs
---FEE_READ_OUT <= fee_read;
-
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
-CTS_DATAREADY_OUT <= cts_dataready;
-CTS_DATA_OUT <= cts_data;
-CTS_LENGTH_OUT <= cts_length;
-CTS_ERROR_PATTERN_OUT <= cts_error_pattern;
-
-STAGE_STAT_REGS_OUT <= stage_stat_regs;
-
-
-end architecture;
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-entity trb_net16_gbe_event_constr is
-port(
- RESET : in std_logic;
- CLK : in std_logic;
- -- ports for user logic
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
- PC_DATA_IN : in std_logic_vector(7 downto 0);
- PC_READY_OUT : out std_logic;
- PC_START_OF_SUB_IN : in std_logic;
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10
- PC_END_OF_QUEUE_IN : in std_logic;
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
- PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
- PC_INSERT_TTYPE_IN : in std_logic;
- -- FrameConstructor ports
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_SOD_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end entity trb_net16_gbe_event_constr;
-
-architecture RTL of trb_net16_gbe_event_constr is
-
-attribute syn_encoding : string;
-
-type loadStates is (IDLE, GET_Q_SIZE, START_TRANSFER, LOAD_Q_HEADERS, LOAD_DATA, LOAD_SUB, LOAD_PADDING, LOAD_TERM, CLEANUP);
-signal load_current_state, load_next_state : loadStates;
-attribute syn_encoding of load_current_state : signal is "onehot";
-
-type saveSubHdrStates is (IDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRG_NR);
-signal save_sub_hdr_current_state, save_sub_hdr_next_state : saveSubHdrStates;
-attribute syn_encoding of save_sub_hdr_current_state : signal is "onehot";
-
-signal df_eos, df_wr_en, df_rd_en, df_empty, df_full, load_eod : std_logic;
-signal df_q, df_qq : std_logic_vector(7 downto 0);
-
-signal header_ctr : integer range 0 to 31;
-
-signal shf_data, shf_q, shf_qq : std_logic_vector(7 downto 0);
-signal shf_wr_en, shf_rd_en, shf_empty, shf_full : std_logic;
-signal sub_int_ctr : integer range 0 to 3;
-signal sub_size_to_save : std_logic_vector(31 downto 0);
-
-signal qsf_data : std_logic_vector(31 downto 0);
-signal qsf_q : std_logic_vector(7 downto 0);
-signal qsf_wr, qsf_wr_en, qsf_wr_en_q, qsf_wr_en_qq, qsf_wr_en_qqq, qsf_rd_en, qsf_rd_en_q, qsf_empty : std_logic;
-
-signal queue_size : std_logic_vector(31 downto 0);
-
-signal termination : std_logic_vector(255 downto 0);
-signal term_ctr : integer range 0 to 33;
-
-signal actual_q_size : std_logic_vector(15 downto 0);
-signal tc_data : std_logic_vector(7 downto 0);
-signal df_data : std_logic_vector(7 downto 0);
-signal df_eos_q, df_eos_qq : std_logic;
-signal df_wr_en_q, df_wr_en_qq : std_logic;
-signal qsf_full : std_logic;
-
-signal padding_needed, insert_padding : std_logic;
-signal load_eod_q : std_logic;
-signal loaded_queue_bytes : std_logic_vector(15 downto 0);
-signal shf_padding : std_logic;
-signal block_shf_after_divide, previous_tc_rd : std_logic;
-signal block_term_after_divide : std_logic;
-
-begin
-
---*******
--- SAVING PART
---*******
-
-DF_EOD_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (PC_END_OF_SUB_IN = '1') then
- df_eos <= '1';
- else
- df_eos <= '0';
- end if;
-
- df_eos_q <= df_eos;
- df_eos_qq <= df_eos_q;
- end if;
-end process DF_EOD_PROC;
-
-DF_WR_EN_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (PC_WR_EN_IN = '1') then
- df_wr_en <= '1';
- else
- df_wr_en <= '0';
- end if;
-
- df_wr_en_q <= df_wr_en;
- df_wr_en_qq <= df_wr_en_q;
-
- df_data <= PC_DATA_IN;
- end if;
-end process DF_WR_EN_PROC;
-
-DATA_FIFO : fifo_64kx9
-port map(
- Data(7 downto 0) => df_data,
- Data(8) => df_eos_q,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => df_wr_en_qq,
- RdEn => df_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q(7 downto 0) => df_q,
- Q(8) => load_eod,
- Empty => df_empty,
- Full => df_full
-);
-
-DF_QQ_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- df_qq <= df_q;
- end if;
-end process DF_QQ_PROC;
-
-READY_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- PC_READY_OUT <= not df_full;
- end if;
-end process READY_PROC;
-
---*****
--- subevent headers
-SUBEVENT_HEADERS_FIFO : fifo_4096x9 --fifo_4kx8_ecp3
-port map(
- Data(7 downto 0) => shf_data,
- Data(8) => PC_SUB_SIZE_IN(2),
- WrClock => CLK,
- RdClock => CLK,
- WrEn => shf_wr_en,
- RdEn => shf_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q(7 downto 0) => shf_q,
- Q(8) => shf_padding,
- Empty => shf_empty,
- Full => shf_full
-);
-
-SHF_WR_EN_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (save_sub_hdr_current_state = IDLE) then
- shf_wr_en <= '0';
- else
- shf_wr_en <= '1';
- end if;
- end if;
-end process SHF_WR_EN_PROC;
-
-VARIOUS_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- shf_qq <= shf_q;
- end if;
-end process VARIOUS_SYNC;
-
-SAVE_SUB_HDR_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- save_sub_hdr_current_state <= IDLE;
- elsif rising_edge(CLK) then
- save_sub_hdr_current_state <= save_sub_hdr_next_state;
- end if;
-end process SAVE_SUB_HDR_MACHINE_PROC;
-
-SAVE_SUB_HDR_MACHINE : process(save_sub_hdr_current_state, PC_START_OF_SUB_IN, sub_int_ctr)
-begin
- case (save_sub_hdr_current_state) is
-
- when IDLE =>
- if (PC_START_OF_SUB_IN = '1') then
- save_sub_hdr_next_state <= SAVE_SIZE;
- else
- save_sub_hdr_next_state <= IDLE;
- end if;
-
- when SAVE_SIZE =>
- if (sub_int_ctr = 0) then
- save_sub_hdr_next_state <= SAVE_DECODING;
- else
- save_sub_hdr_next_state <= SAVE_SIZE;
- end if;
-
- when SAVE_DECODING =>
- if (sub_int_ctr = 0) then
- save_sub_hdr_next_state <= SAVE_ID;
- else
- save_sub_hdr_next_state <= SAVE_DECODING;
- end if;
-
- when SAVE_ID =>
- if (sub_int_ctr = 0) then
- save_sub_hdr_next_state <= SAVE_TRG_NR;
- else
- save_sub_hdr_next_state <= SAVE_ID;
- end if;
-
- when SAVE_TRG_NR =>
- if (sub_int_ctr = 0) then
- save_sub_hdr_next_state <= IDLE;
- else
- save_sub_hdr_next_state <= SAVE_TRG_NR;
- end if;
-
- when others => save_sub_hdr_next_state <= IDLE;
-
- end case;
-end process SAVE_SUB_HDR_MACHINE;
-
-SUB_INT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (save_sub_hdr_current_state = IDLE) then
- sub_int_ctr <= 3;
- else
- if (sub_int_ctr = 0) then
- sub_int_ctr <= 3;
- else
- sub_int_ctr <= sub_int_ctr - 1;
- end if;
- end if;
- end if;
-end process SUB_INT_CTR_PROC;
-
-SUB_SIZE_TO_SAVE_PROC : process (CLK)
-begin
- if rising_edge(CLK) then
- sub_size_to_save <= PC_SUB_SIZE_IN + x"10" + x"8"; -- addition for subevent headers and subsubevent
- end if;
-end process SUB_SIZE_TO_SAVE_PROC;
-
-SHF_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- case (save_sub_hdr_current_state) is
-
- when IDLE =>
- shf_data <= x"ac";
-
- when SAVE_SIZE =>
- shf_data <= sub_size_to_save(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
-
- when SAVE_DECODING =>
- if (PC_INSERT_TTYPE_IN = '0') then
- shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
- else
- if (sub_int_ctr = 0) then
- shf_data(3 downto 0) <= PC_DECODING_IN(3 downto 0);
- shf_data(7 downto 4) <= PC_TRIGGER_TYPE_IN;
- else
- shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
- end if;
- end if;
-
- when SAVE_ID =>
- shf_data <= PC_EVENT_ID_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
-
- when SAVE_TRG_NR =>
- shf_data <= PC_TRIG_NR_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
-
- when others => shf_data <= x"00";
-
- end case;
- end if;
-end process SHF_DATA_PROC;
-
---*******
--- queue sizes
-
-QUEUE_SIZE_FIFO : fifo_512x32x8
-port map(
- Data => qsf_data,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => qsf_wr,
- RdEn => qsf_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q => qsf_q,
- Empty => qsf_empty,
- Full => qsf_full
-);
-
-qsf_wr <= qsf_wr_en_qqq or qsf_wr_en_qq or qsf_wr_en_q;
-
-QSF_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- -- queue size is saved twice in a row to facilitate readout and packet construction
- if (qsf_wr_en = '1' or qsf_wr_en_q = '1') then
- if (qsf_wr_en = '1' and qsf_wr_en_q = '0') then
- qsf_data(7) <= padding_needed;
- qsf_data(6 downto 0) <= (others => '0');
- else
- qsf_data(7 downto 0) <= queue_size(31 downto 24);
- end if;
- qsf_data(15 downto 8) <= queue_size(23 downto 16);
- qsf_data(23 downto 16) <= queue_size(15 downto 8);
- qsf_data(31 downto 24) <= queue_size(7 downto 0);
- elsif (qsf_wr_en_qq = '1') then
- qsf_data(7 downto 0) <= PC_QUEUE_DEC_IN(31 downto 24);
- qsf_data(15 downto 8) <= PC_QUEUE_DEC_IN(23 downto 16);
- qsf_data(23 downto 16) <= PC_QUEUE_DEC_IN(15 downto 8);
- qsf_data(31 downto 24) <= PC_QUEUE_DEC_IN(7 downto 0);
- else
- qsf_data <= (others => '1');
- end if;
- end if;
-end process QSF_DATA_PROC;
-
-QSF_WR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- qsf_wr_en_q <= qsf_wr_en;
- qsf_wr_en_qq <= qsf_wr_en_q;
- qsf_wr_en_qqq <= qsf_wr_en_qq;
-
- qsf_wr_en <= PC_END_OF_QUEUE_IN;
- end if;
-end process QSF_WR_PROC;
-
-QUEUE_SIZE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- queue_size <= x"0000_0008"; -- queue headers
- elsif rising_edge(CLK) then
- if (qsf_wr_en_qqq = '1') then
- queue_size <= x"0000_0008";
- elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then
- if (PC_SUB_SIZE_IN(2) = '1') then
- queue_size <= queue_size + PC_SUB_SIZE_IN + x"4" + x"10" + x"8"; -- subevent data size + padding + subevent headers + subsubevent
- else
- queue_size <= queue_size + PC_SUB_SIZE_IN + x"10" + x"8"; -- subevent data size + subevent headers + subsubevent
- end if;
- else
- queue_size <= queue_size;
- end if;
- end if;
-end process QUEUE_SIZE_PROC;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (PC_START_OF_SUB_IN = '1') then
- padding_needed <= '0';
- elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then
- if (PC_SUB_SIZE_IN(2) = '1') then
- padding_needed <= '1';
- else
- padding_needed <= '0';
- end if;
- else
- padding_needed <= padding_needed;
- end if;
- end if;
-end process;
-
---*******
--- LOADING PART
---*******
-
-LOAD_MACHINE_PROC : process(RESET, CLK) is
-begin
- if RESET = '1' then
- load_current_state <= IDLE;
- elsif rising_edge(CLK) then
- load_current_state <= load_next_state;
- end if;
-end process LOAD_MACHINE_PROC;
-
-LOAD_MACHINE : process(load_current_state, qsf_empty, header_ctr, load_eod_q, term_ctr, insert_padding, loaded_queue_bytes, actual_q_size)
-begin
- case (load_current_state) is
-
- when IDLE =>
- if (qsf_empty = '0') then -- something in queue sizes fifo means entire queue is waiting
- load_next_state <= GET_Q_SIZE;
- else
- load_next_state <= IDLE;
- end if;
-
- when GET_Q_SIZE =>
- if (header_ctr = 0) then
- load_next_state <= START_TRANSFER;
- else
- load_next_state <= GET_Q_SIZE;
- end if;
-
- when START_TRANSFER =>
- load_next_state <= LOAD_Q_HEADERS;
-
- when LOAD_Q_HEADERS =>
- if (header_ctr = 0) then
- load_next_state <= LOAD_SUB;
- else
- load_next_state <= LOAD_Q_HEADERS;
- end if;
-
- when LOAD_SUB =>
- if (header_ctr = 0) then
- load_next_state <= LOAD_DATA;
- else
- load_next_state <= LOAD_SUB;
- end if;
-
- when LOAD_DATA =>
- if (load_eod_q = '1' and term_ctr = 33) then
- if (insert_padding = '1') then
- load_next_state <= LOAD_PADDING;
- else
- if (loaded_queue_bytes = actual_q_size) then
- load_next_state <= LOAD_TERM;
- else
- load_next_state <= LOAD_SUB;
- end if;
- end if;
- else
- load_next_state <= LOAD_DATA;
- end if;
-
- when LOAD_PADDING =>
- if (header_ctr = 0) then
- if (loaded_queue_bytes = actual_q_size) then
- load_next_state <= LOAD_TERM;
- else
- load_next_state <= LOAD_SUB;
- end if;
- else
- load_next_state <= LOAD_PADDING;
- end if;
-
- when LOAD_TERM =>
- if (header_ctr = 0) then
- load_next_state <= CLEANUP;
- else
- load_next_state <= LOAD_TERM;
- end if;
-
- when CLEANUP =>
- load_next_state <= IDLE;
-
- end case;
-end process LOAD_MACHINE;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- load_eod_q <= load_eod;
- end if;
-end process;
-
-HEADER_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = IDLE) then
- header_ctr <= 3;
- elsif (load_current_state = GET_Q_SIZE and header_ctr = 0) then
- header_ctr <= 8;
- elsif (load_current_state = LOAD_Q_HEADERS and header_ctr = 0) then
- header_ctr <= 15;
- elsif (load_current_state = LOAD_SUB and header_ctr = 0) then
- if (insert_padding = '1') then
- header_ctr <= 3;
- else
- header_ctr <= 31;
- end if;
- elsif (load_current_state = LOAD_PADDING and header_ctr = 0) then
- if (loaded_queue_bytes = actual_q_size) then
- header_ctr <= 31;
- else
- header_ctr <= 15;
- end if;
- elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes = actual_q_size and insert_padding = '0') then
- header_ctr <= 31;
- elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes /= actual_q_size and insert_padding = '0') then
- header_ctr <= 15;
- elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes /= actual_q_size and insert_padding = '1') then
- header_ctr <= 3;
- elsif (load_current_state = LOAD_TERM and header_ctr = 0) then
- header_ctr <= 3;
- elsif (TC_RD_EN_IN = '1') then
- if (load_current_state = LOAD_Q_HEADERS or load_current_state = LOAD_TERM or load_current_state = LOAD_PADDING) then
- if (load_current_state = LOAD_TERM) then
- if (block_term_after_divide = '1') then
- header_ctr <= 31;
- else
- header_ctr <= header_ctr - 1;
- end if;
- else
- header_ctr <= header_ctr - 1;
- end if;
- elsif (load_current_state = LOAD_SUB and block_shf_after_divide = '0') then
- header_ctr <= header_ctr - 1;
- else
- header_ctr <= header_ctr;
- end if;
- elsif (load_current_state = GET_Q_SIZE) then
- header_ctr <= header_ctr - 1;
- else
- header_ctr <= header_ctr;
- end if;
- end if;
-end process HEADER_CTR_PROC;
-
-SIZE_FOR_PADDING_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = IDLE) then
- insert_padding <= '0';
- elsif (load_current_state = LOAD_SUB and header_ctr = 12) then
- insert_padding <= shf_padding;
- else
- insert_padding <= insert_padding;
- end if;
- end if;
-end process SIZE_FOR_PADDING_PROC;
-
-TC_SOD_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = START_TRANSFER) then
- TC_SOD_OUT <= '1';
- else
- TC_SOD_OUT <= '0';
- end if;
- end if;
-end process TC_SOD_PROC;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = IDLE) then
- loaded_queue_bytes <= (others => '0');
- elsif (TC_RD_EN_IN = '1') then
- loaded_queue_bytes <= loaded_queue_bytes + x"1";
- else
- loaded_queue_bytes <= loaded_queue_bytes;
- end if;
- end if;
-end process;
-
---*****
--- read from fifos
-
-df_rd_en <= '1' when (load_current_state = LOAD_DATA and TC_RD_EN_IN = '1' and load_eod_q = '0') or
- (load_current_state = LOAD_SUB and header_ctr = 0 and TC_RD_EN_IN = '1')
- else '0';
-
-shf_rd_en <= '1' when (load_current_state = LOAD_SUB and TC_RD_EN_IN = '1' and header_ctr /= 0 and block_shf_after_divide = '0') or
- (load_current_state = LOAD_Q_HEADERS and header_ctr = 0 and TC_RD_EN_IN = '1') or
- (load_current_state = LOAD_DATA and load_eod_q = '1' and (loaded_queue_bytes /= actual_q_size) and (loaded_queue_bytes + x"4" /= actual_q_size))
- else '0';
-
-
--- nasty workaround for the case when the packet is divided on LOAD_SUB state
-process(CLK)
-begin
- if rising_edge(CLK) then
- previous_tc_rd <= TC_RD_EN_IN;
- end if;
-end process;
-block_shf_after_divide <= '1' when previous_tc_rd = '0' and TC_RD_EN_IN = '1' and header_ctr = 15 else '0';
-block_term_after_divide <= '1' when previous_tc_rd = '0' and TC_RD_EN_IN = '1' and header_ctr = 31 else '0';
-
-QUEUE_FIFO_RD_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = GET_Q_SIZE and header_ctr /= 0) then
- qsf_rd_en_q <= '1';
- elsif (load_current_state = IDLE and qsf_empty = '0') then
- qsf_rd_en_q <= '1';
- else
- qsf_rd_en_q <= '0';
- end if;
- end if;
-end process QUEUE_FIFO_RD_PROC;
-
-qsf_rd_en <= '1' when load_current_state = LOAD_Q_HEADERS and TC_RD_EN_IN = '1' and header_ctr /= 0 else qsf_rd_en_q;
-
-ACTUAL_Q_SIZE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = START_TRANSFER) then
- actual_q_size(7 downto 0) <= qsf_q;
- elsif (load_current_state = GET_Q_SIZE and header_ctr = 0) then
- actual_q_size(15 downto 8) <= qsf_q;
- end if;
- end if;
-end process ACTUAL_Q_SIZE_PROC;
-
-TC_EVENT_SIZE_OUT <= actual_q_size; -- queue size without termination
-
-TERMINATION_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = IDLE) then
- termination(255 downto 8) <= (others => '0');
- elsif (TC_RD_EN_IN = '1' and term_ctr /= 33 and term_ctr /= 0) then
- termination(255 downto 8) <= termination(247 downto 0);
- else
- termination(255 downto 8) <= termination(255 downto 8);
- end if;
- end if;
-end process TERMINATION_PROC;
-
-term_bits_gen : for I in 0 to 7 generate
- process(CLK)
- begin
- if rising_edge(CLK) then
- if (TC_RD_EN_IN = '1' and term_ctr /= 33 and term_ctr /= 0) then
- case (load_current_state) is
- when LOAD_Q_HEADERS => termination(I) <= qsf_q(I);
- when LOAD_SUB => termination(I) <= shf_q(I);
- when LOAD_DATA => termination(I) <= df_q(I);
- when others => termination(I) <= '0';
- end case;
- else
- termination(I) <= termination(I);
- end if;
- end if;
- end process;
-end generate term_bits_gen;
-
-TERM_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = IDLE) then
- term_ctr <= 0;
- elsif (TC_RD_EN_IN = '1' and term_ctr /= 33) then
- term_ctr <= term_ctr + 1;
- end if;
- end if;
-end process TERM_CTR_PROC;
-
-TC_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- case (load_current_state) is
- when LOAD_Q_HEADERS => tc_data <= qsf_q;
- when LOAD_SUB => tc_data <= shf_q;
- when LOAD_DATA => tc_data <= df_q;
- when LOAD_PADDING => tc_data <= x"aa";
- when LOAD_TERM => tc_data <= termination((header_ctr + 1) * 8 - 1 downto header_ctr * 8);
- when others => tc_data <= x"cc";
- end case;
- end if;
-end process TC_DATA_PROC;
-
-TC_DATA_OUT(7 downto 0) <= tc_data;
-TC_DATA_8_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = LOAD_TERM and header_ctr = 0) then
- TC_DATA_OUT(8) <= '1';
- else
- TC_DATA_OUT(8) <= '0';
- end if;
- end if;
-end process TC_DATA_8_PROC;
-
---*****
--- outputs
-
-
-
-DEBUG_OUT <= (others => '0');
-
-end architecture RTL;
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.trb_net16_hub_func.all;\r
-\r
-entity trb_net16_gbe_frame_constr is\r
-port( \r
- -- ports for user logic\r
- RESET : in std_logic;\r
- CLK : in std_logic;\r
- LINK_OK_IN : in std_logic; -- gk 03.08.10\r
- --\r
- WR_EN_IN : in std_logic;\r
- DATA_IN : in std_logic_vector(7 downto 0);\r
- START_OF_DATA_IN : in std_logic;\r
- END_OF_DATA_IN : in std_logic;\r
- IP_F_SIZE_IN : in std_logic_vector(15 downto 0);\r
- UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation\r
- HEADERS_READY_OUT : out std_logic;\r
- READY_OUT : out std_logic;\r
- DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
- DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
- DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
- SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
- SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
- SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0);\r
- IHL_VERSION_IN : in std_logic_vector(7 downto 0);\r
- TOS_IN : in std_logic_vector(7 downto 0);\r
- IDENTIFICATION_IN : in std_logic_vector(15 downto 0);\r
- FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);\r
- TTL_IN : in std_logic_vector(7 downto 0);\r
- PROTOCOL_IN : in std_logic_vector(7 downto 0);\r
- FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10\r
- -- ports for packetTransmitter\r
- RD_CLK : in std_logic; -- 125MHz clock!!!\r
- FT_DATA_OUT : out std_logic_vector(8 downto 0);\r
- FT_TX_EMPTY_OUT : out std_logic;\r
- FT_TX_RD_EN_IN : in std_logic;\r
- FT_START_OF_PACKET_OUT : out std_logic;\r
- FT_TX_DONE_IN : in std_logic;\r
- FT_TX_DISCFRM_IN : in std_logic;\r
- \r
- MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0);\r
- MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0)\r
-);\r
-end trb_net16_gbe_frame_constr;\r
-\r
-architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is\r
-\r
---attribute HGROUP : string;\r
---attribute HGROUP of trb_net16_gbe_frame_constr : architecture is "GBE_LINK_group";\r
-\r
-component fifo_4096x9 is\r
-port( \r
- Data : in std_logic_vector(8 downto 0);\r
- WrClock : in std_logic;\r
- RdClock : in std_logic;\r
- WrEn : in std_logic;\r
- RdEn : in std_logic;\r
- Reset : in std_logic;\r
- RPReset : in std_logic;\r
- Q : out std_logic_vector(8 downto 0);\r
- Empty : out std_logic;\r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
-attribute syn_encoding : string;\r
-\r
-type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION,\r
- TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS,\r
- SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH,\r
- UDP_CS, SAVE_DATA, CLEANUP, DELAY);\r
-signal constructCurrentState, constructNextState : constructStates;\r
-signal bsm_constr : std_logic_vector(7 downto 0);\r
-attribute syn_encoding of constructCurrentState: signal is "onehot";\r
-\r
-type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP);\r
-signal transmitCurrentState, transmitNextState : transmitStates;\r
-attribute syn_encoding of transmitCurrentState : signal is "onehot";\r
-\r
-signal bsm_trans : std_logic_vector(3 downto 0);\r
-\r
-signal headers_int_counter : integer range 0 to 6;\r
-signal fpf_data : std_logic_vector(7 downto 0);\r
-signal fpf_empty : std_logic;\r
-signal fpf_full : std_logic;\r
-signal fpf_wr_en : std_logic;\r
-signal fpf_rd_en : std_logic;\r
-signal fpf_q : std_logic_vector(8 downto 0);\r
-signal ip_size : std_logic_vector(15 downto 0);\r
-signal ip_checksum : std_logic_vector(31 downto 0);\r
-signal udp_size : std_logic_vector(15 downto 0);\r
-signal udp_checksum : std_logic_vector(15 downto 0);\r
-signal ft_sop : std_logic;\r
-signal put_udp_headers : std_logic;\r
-signal ready_frames_ctr : std_logic_vector(15 downto 0);\r
-signal sent_frames_ctr : std_logic_vector(15 downto 0);\r
-signal debug : std_logic_vector(63 downto 0);\r
-signal ready : std_logic;\r
-signal headers_ready : std_logic;\r
-\r
-signal cur_max : integer range 0 to 10;\r
-\r
-signal ready_frames_ctr_q : std_logic_vector(15 downto 0);\r
-signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10\r
-\r
-signal fpf_reset : std_logic; -- gk 01.01.01\r
-signal link_ok_125, link_ok_q : std_logic;\r
-\r
--- gk 09.12.10\r
-signal delay_ctr : std_logic_vector(31 downto 0);\r
-signal frame_delay_reg : std_logic_vector(31 downto 0);\r
-signal fpf_data_q : std_logic_vector(7 downto 0);\r
-signal fpf_wr_en_q, fpf_eod : std_logic;\r
-\r
-signal mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0);\r
-\r
-begin\r
-\r
--- Fakes\r
-udp_checksum <= x"0000"; -- no checksum test needed\r
---debug <= (others => '0');\r
-\r
-process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if constructCurrentState = IDLE then\r
- ready <= '1';\r
- else\r
- ready <= '0';\r
- end if;\r
- \r
- if (constructCurrentState = SAVE_DATA) then\r
- headers_ready <= '1';\r
- else\r
- headers_ready <= '0';\r
- end if;\r
- end if;\r
-end process;\r
---ready <= '1' when (constructCurrentState = IDLE)\r
--- else '0';\r
---headers_ready <= '1' when (constructCurrentState = SAVE_DATA)\r
--- else '0';\r
- \r
-sizeProc: process(CLK) -- put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN, DEST_UDP_PORT_IN)\r
-begin\r
- if rising_edge(CLK) then\r
- if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then\r
- ip_size <= IP_F_SIZE_IN + x"14" + x"8";\r
- udp_size <= UDP_P_SIZE_IN + x"8";\r
- else\r
- ip_size <= IP_F_SIZE_IN + x"14";\r
- udp_size <= UDP_P_SIZE_IN;\r
- end if;\r
- end if;\r
-end process sizeProc;\r
-\r
-ipCsProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (constructCurrentState = IDLE) then\r
- ip_checksum <= x"00000000";\r
- else\r
- case constructCurrentState is\r
- when DEST_MAC_ADDR =>\r
- case headers_int_counter is\r
- when 0 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(7 downto 0);\r
- when 1 =>\r
- ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(15 downto 8);\r
- when 2 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(23 downto 16);\r
- when 3 =>\r
- ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(31 downto 24);\r
- when 4 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(7 downto 0);\r
- when 5 =>\r
- ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(15 downto 8);\r
- when others => null;\r
- end case;\r
- when SRC_MAC_ADDR =>\r
- case headers_int_counter is\r
- when 0 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(23 downto 16);\r
- when 1 =>\r
- ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(31 downto 24);\r
- when 2 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IHL_VERSION_IN;\r
- when 3 =>\r
- ip_checksum <= ip_checksum + TOS_IN;\r
- when 4 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + ip_size(15 downto 8);\r
- when 5 =>\r
- ip_checksum <= ip_checksum + ip_size(7 downto 0);\r
- when others => null;\r
- end case;\r
- when VERSION =>\r
- if headers_int_counter = 0 then\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IDENTIFICATION_IN(7 downto 0);\r
- end if;\r
- when TOS_S =>\r
- if headers_int_counter = 0 then\r
- ip_checksum <= ip_checksum + IDENTIFICATION_IN(15 downto 8);\r
- end if;\r
- when IP_LENGTH =>\r
- if headers_int_counter = 0 then\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + FLAGS_OFFSET_IN(15 downto 8);\r
- elsif headers_int_counter = 1 then\r
- ip_checksum <= ip_checksum + FLAGS_OFFSET_IN(7 downto 0);\r
- end if;\r
- when IDENT =>\r
- if headers_int_counter = 0 then\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + TTL_IN;\r
- elsif headers_int_counter = 1 then\r
- ip_checksum <= ip_checksum + PROTOCOL_IN;\r
- end if;\r
- -- gk 29.03.10 corrected the bug with bad checksums when sum larger than 16b\r
- when FLAGS =>\r
- if headers_int_counter = 0 then\r
- ip_cs_temp_right <= ip_checksum(31 downto 16);\r
- elsif headers_int_counter = 1 then\r
- ip_checksum(31 downto 16) <= (others => '0');\r
- end if;\r
- when TTL_S =>\r
- if headers_int_counter = 0 then\r
- ip_checksum <= ip_checksum + ip_cs_temp_right;\r
- end if;\r
- when PROTO =>\r
- if headers_int_counter = 0 then\r
- ip_checksum(15 downto 0) <= ip_checksum(15 downto 0) + ip_checksum(31 downto 16);\r
- end if;\r
- when others => null;\r
- end case;\r
- end if;\r
- end if;\r
-end process ipCsProc;\r
-\r
-\r
-constructMachineProc: process(RESET, CLK )\r
-begin\r
- if RESET = '1' then\r
- constructCurrentState <= IDLE;\r
- elsif( rising_edge(CLK) ) then\r
- constructCurrentState <= constructNextState;\r
- end if;\r
-end process constructMachineProc;\r
-\r
---find next state of construct machine\r
-constructMachine: process( constructCurrentState, delay_ctr, FRAME_DELAY_IN, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, FRAME_TYPE_IN, DEST_UDP_PORT_IN)\r
-begin\r
- constructNextState <= constructCurrentState;\r
- if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0\r
- case constructCurrentState is\r
- when IDLE =>\r
- if( START_OF_DATA_IN = '1' ) then\r
- constructNextState <= DEST_MAC_ADDR;\r
- end if;\r
- when DEST_MAC_ADDR =>\r
- constructNextState <= SRC_MAC_ADDR;\r
- when SRC_MAC_ADDR =>\r
- constructNextState <= FRAME_TYPE_S;\r
- when FRAME_TYPE_S =>\r
- --if (DEST_IP_ADDRESS_IN /= x"0000_0000") then -- in case of ip frame continue with ip/udp headers\r
- if (FRAME_TYPE_IN = x"0008") then \r
- constructNextState <= VERSION;\r
- else -- otherwise transmit data as pure ethernet frame\r
- constructNextState <= SAVE_DATA;\r
- end if;\r
- when VERSION =>\r
- constructNextState <= TOS_S;\r
- when TOS_S =>\r
- constructNextState <= IP_LENGTH;\r
- when IP_LENGTH =>\r
- constructNextState <= IDENT;\r
- when IDENT =>\r
- constructNextState <= FLAGS;\r
- when FLAGS =>\r
- constructNextState <= TTL_S;\r
- when TTL_S =>\r
- constructNextState <= PROTO;\r
- when PROTO =>\r
- constructNextState <= HEADER_CS;\r
- when HEADER_CS =>\r
- constructNextState <= SRC_IP_ADDR;\r
- when SRC_IP_ADDR =>\r
- constructNextState <= DEST_IP_ADDR;\r
- when DEST_IP_ADDR =>\r
- if (put_udp_headers = '1') and (DEST_UDP_PORT_IN /= x"0000") then\r
- constructNextState <= SRC_PORT;\r
- else\r
- constructNextState <= SAVE_DATA;\r
- end if;\r
- when SRC_PORT =>\r
- constructNextState <= DEST_PORT;\r
- when DEST_PORT =>\r
- constructNextState <= UDP_LENGTH;\r
- when UDP_LENGTH =>\r
- constructNextState <= UDP_CS;\r
- when UDP_CS =>\r
- constructNextState <= SAVE_DATA;\r
- when SAVE_DATA =>\r
- if (END_OF_DATA_IN = '1') then\r
- constructNextState <= CLEANUP;\r
- end if;\r
- when CLEANUP =>\r
- --constructNextState <= IDLE;\r
- constructNextState <= DELAY; -- gk 10.12.10 IDLE;\r
- -- gk 09.12.10\r
- when DELAY =>\r
- if (delay_ctr = FRAME_DELAY_IN) then\r
- constructNextState <= IDLE;\r
- else\r
- constructNextState <= DELAY;\r
- end if;\r
-\r
- when others =>\r
- constructNextState <= IDLE;\r
- end case;\r
- end if;\r
-end process constructMachine;\r
-\r
--- gk 09.12.10\r
-delayCtrProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (constructCurrentState = IDLE) or (constructCurrentState = CLEANUP) then\r
- delay_ctr <= (others => '0');\r
- elsif (constructCurrentState = DELAY) then\r
- delay_ctr <= delay_ctr + x"1";\r
- end if;\r
-\r
- frame_delay_reg <= FRAME_DELAY_IN;\r
- end if;\r
-end process delayCtrProc;\r
-\r
-\r
-bsmConstrProc : process(constructCurrentState)\r
-begin\r
---find maximum time in each state & set state bits\r
- case constructCurrentState is\r
- when IDLE => cur_max <= 0; bsm_constr <= x"01";\r
- when DEST_MAC_ADDR => cur_max <= 5; bsm_constr <= x"02";\r
- when SRC_MAC_ADDR => cur_max <= 5; bsm_constr <= x"03";\r
- when FRAME_TYPE_S => cur_max <= 1; bsm_constr <= x"04";\r
- when VERSION => cur_max <= 0; bsm_constr <= x"05";\r
- when TOS_S => cur_max <= 0; bsm_constr <= x"06";\r
- when IP_LENGTH => cur_max <= 1; bsm_constr <= x"07";\r
- when IDENT => cur_max <= 1; bsm_constr <= x"08";\r
- when FLAGS => cur_max <= 1; bsm_constr <= x"09";\r
- when TTL_S => cur_max <= 0; bsm_constr <= x"0a";\r
- when PROTO => cur_max <= 0; bsm_constr <= x"0b";\r
- when HEADER_CS => cur_max <= 1; bsm_constr <= x"0c";\r
- when SRC_IP_ADDR => cur_max <= 3; bsm_constr <= x"0d";\r
- when DEST_IP_ADDR => cur_max <= 3; bsm_constr <= x"0e";\r
- when SRC_PORT => cur_max <= 1; bsm_constr <= x"0f";\r
- when DEST_PORT => cur_max <= 1; bsm_constr <= x"10";\r
- when UDP_LENGTH => cur_max <= 1; bsm_constr <= x"11";\r
- when UDP_CS => cur_max <= 1; bsm_constr <= x"12";\r
- when SAVE_DATA => cur_max <= 0; bsm_constr <= x"13";\r
- when CLEANUP => cur_max <= 0; bsm_constr <= x"14";\r
- when DELAY => cur_max <= 0; bsm_constr <= x"15";\r
- when others => cur_max <= 0; bsm_constr <= x"1f";\r
- end case;\r
-end process;\r
-\r
-\r
-headersIntProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (constructCurrentState = IDLE) then\r
- headers_int_counter <= 0;\r
- else\r
- if (headers_int_counter = cur_max) then\r
- headers_int_counter <= 0;\r
- else\r
- headers_int_counter <= headers_int_counter + 1;\r
- end if;\r
- end if;\r
- end if;\r
-end process headersIntProc;\r
-\r
-\r
-\r
-putUdpHeadersProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (FLAGS_OFFSET_IN(12 downto 0) = "0000000000000") then\r
- put_udp_headers <= '1';\r
- else\r
- put_udp_headers <= '0';\r
- end if;\r
- end if;\r
-end process putUdpHeadersProc;\r
-\r
-fpfWrEnProc : process(constructCurrentState, WR_EN_IN, LINK_OK_IN)\r
-begin\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- fpf_wr_en <= '0';\r
- elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) and (constructCurrentState /= DELAY) then\r
- fpf_wr_en <= '1';\r
- elsif (constructCurrentState = SAVE_DATA) and (WR_EN_IN = '1') then\r
- fpf_wr_en <= '1';\r
- else\r
- fpf_wr_en <= '0';\r
- end if;\r
-end process fpfWrEnProc;\r
-\r
-fpfDataProc : process(constructCurrentState, DEST_MAC_ADDRESS_IN, SRC_MAC_ADDRESS_IN, FRAME_TYPE_IN, IHL_VERSION_IN,\r
- TOS_IN, ip_size, IDENTIFICATION_IN, FLAGS_OFFSET_IN, TTL_IN, PROTOCOL_IN,\r
- ip_checksum, SRC_IP_ADDRESS_IN, DEST_IP_ADDRESS_IN,\r
- SRC_UDP_PORT_IN, DEST_UDP_PORT_IN, udp_size, udp_checksum, headers_int_counter, DATA_IN)\r
-begin\r
- case constructCurrentState is\r
- when IDLE => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when DEST_MAC_ADDR => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when SRC_MAC_ADDR => fpf_data <= SRC_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when FRAME_TYPE_S => fpf_data <= FRAME_TYPE_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when VERSION => fpf_data <= IHL_VERSION_IN;\r
- when TOS_S => fpf_data <= TOS_IN;\r
- when IP_LENGTH => fpf_data <= ip_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when IDENT => fpf_data <= IDENTIFICATION_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when FLAGS => fpf_data <= FLAGS_OFFSET_IN(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when TTL_S => fpf_data <= TTL_IN;\r
- when PROTO => fpf_data <= PROTOCOL_IN;\r
- when HEADER_CS => fpf_data <= x"ff" - ip_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when SRC_IP_ADDR => fpf_data <= SRC_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when DEST_IP_ADDR => fpf_data <= DEST_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when SRC_PORT => fpf_data <= SRC_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when DEST_PORT => fpf_data <= DEST_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when UDP_LENGTH => fpf_data <= udp_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when UDP_CS => fpf_data <= udp_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when SAVE_DATA => fpf_data <= DATA_IN;\r
- when CLEANUP => fpf_data <= x"ab";\r
- when DELAY => fpf_data <= x"ac";\r
- when others => fpf_data <= x"00";\r
- end case;\r
-end process fpfDataProc;\r
-\r
-syncProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- fpf_data_q <= fpf_data;\r
- fpf_wr_en_q <= fpf_wr_en;\r
- fpf_eod <= END_OF_DATA_IN;\r
- end if;\r
-end process syncProc;\r
- \r
-\r
-\r
-readyFramesCtrProc: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- ready_frames_ctr <= (others => '0');\r
- elsif (constructCurrentState = CLEANUP) then\r
- ready_frames_ctr <= ready_frames_ctr + 1;\r
- else\r
- ready_frames_ctr <= ready_frames_ctr;\r
- end if;\r
- end if;\r
-end process readyFramesCtrProc;\r
-\r
-fpfResetProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (LINK_OK_IN = '0') then\r
- fpf_reset <= '1';\r
- else\r
- fpf_reset <= '0';\r
- end if;\r
- end if;\r
-end process fpfResetProc;\r
---fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10\r
-\r
-FINAL_PACKET_FIFO: fifo_4096x9\r
-port map( \r
- Data(7 downto 0) => fpf_data_q,\r
- Data(8) => fpf_eod, --END_OF_DATA_IN,\r
- WrClock => CLK,\r
- RdClock => RD_CLK,\r
- WrEn => fpf_wr_en_q,\r
- RdEn => fpf_rd_en, --FT_TX_RD_EN_IN,\r
- Reset => fpf_reset,\r
- RPReset => fpf_reset,\r
- Q => fpf_q,\r
- Empty => fpf_empty,\r
- Full => fpf_full\r
-);\r
-\r
---fpf_rd_en <= FT_TX_RD_EN_IN;\r
-fpf_rd_en <= '1' when ((link_ok_125 = '1') and (FT_TX_RD_EN_IN = '1'))\r
- or (link_ok_125 = '0') -- clear the fifo if link is down\r
- else '0';\r
-\r
-transferToRdClock : signal_sync\r
- generic map(\r
- DEPTH => 2,\r
- WIDTH => 16\r
- )\r
- port map(\r
- RESET => RESET,\r
- D_IN => ready_frames_ctr,\r
- CLK0 => RD_CLK, --CLK,\r
- CLK1 => RD_CLK,\r
- D_OUT => ready_frames_ctr_q\r
- );\r
-\r
-process(RD_CLK)\r
-begin\r
- if rising_edge(RD_CLK) then\r
- link_ok_q <= LINK_OK_IN;\r
- link_ok_125 <= link_ok_q;\r
- end if;\r
-end process;\r
-\r
-transmitMachineProc: process( RD_CLK )\r
-begin\r
- if RESET = '1' then\r
- transmitCurrentState <= T_IDLE;\r
- elsif( rising_edge(RD_CLK) ) then\r
- if (link_ok_125 = '0') then -- gk 01.10.10\r
- transmitCurrentState <= T_IDLE;\r
- else\r
- transmitCurrentState <= transmitNextState;\r
- end if;\r
- end if;\r
-end process transmitMachineProc;\r
-\r
-transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, link_ok_125, ready_frames_ctr_q, FT_TX_DISCFRM_IN )\r
-begin\r
- case transmitCurrentState is\r
- when T_IDLE =>\r
- bsm_trans <= x"0";\r
- if( (sent_frames_ctr /= ready_frames_ctr_q) ) then\r
- transmitNextState <= T_LOAD;\r
- else\r
- transmitNextState <= T_IDLE;\r
- end if;\r
- when T_LOAD =>\r
- bsm_trans <= x"1";\r
- if( fpf_q(8) = '1' ) then\r
- transmitNextState <= T_TRANSMIT;\r
- else\r
- transmitNextState <= T_LOAD;\r
- end if;\r
- when T_TRANSMIT =>\r
- bsm_trans <= x"2";\r
- -- gk 03.08.10\r
- if ((link_ok_125 = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then\r
- transmitNextState <= T_CLEANUP;\r
- elsif (link_ok_125 = '0') then\r
- transmitNextState <= T_PAUSE;\r
- else\r
- transmitNextState <= T_TRANSMIT;\r
- end if;\r
- when T_PAUSE =>\r
- transmitNextState <= T_CLEANUP;\r
- when T_CLEANUP =>\r
- bsm_trans <= x"3";\r
- transmitNextState <= T_IDLE;\r
- when others =>\r
- bsm_trans <= x"f";\r
- transmitNextState <= T_IDLE;\r
- end case;\r
-end process transmitMachine;\r
-\r
-\r
-\r
-sopProc: process( RD_CLK )\r
-begin\r
- if rising_edge(RD_CLK) then\r
- if (link_ok_125 = '0') then -- gk 01.10.10\r
- ft_sop <= '0';\r
- elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then\r
- ft_sop <= '1';\r
- else\r
- ft_sop <= '0';\r
- end if;\r
- end if;\r
-end process sopProc;\r
-\r
-sentFramesCtrProc: process( RD_CLK )\r
-begin\r
- if rising_edge(RD_CLK) then\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- sent_frames_ctr <= (others => '0');\r
- mon_sent_frames <= (others => '0');\r
- elsif( FT_TX_DONE_IN = '1' ) or (FT_TX_DISCFRM_IN = '1') then\r
- sent_frames_ctr <= sent_frames_ctr + 1;\r
- mon_sent_frames <= mon_sent_frames + x"1";\r
- else\r
- sent_frames_ctr <= sent_frames_ctr;\r
- mon_sent_frames <= mon_sent_frames;\r
- end if;\r
- end if;\r
-end process sentFramesCtrProc;\r
-\r
-\r
-\r
-FT_DATA_OUT <= fpf_q;\r
-FT_TX_EMPTY_OUT <= fpf_empty;\r
-FT_START_OF_PACKET_OUT <= ft_sop;\r
-READY_OUT <= ready;\r
-HEADERS_READY_OUT <= headers_ready;\r
-\r
- \r
-MONITOR_TX_BYTES_OUT <= mon_sent_bytes;\r
-MONITOR_TX_FRAMES_OUT <= mon_sent_frames;\r
-\r
-process(RD_CLK)\r
-begin\r
- if rising_edge(RD_CLK) then\r
- if (LINK_OK_IN = '0') then\r
- mon_sent_bytes <= (others => '0');\r
- elsif (fpf_rd_en = '1') then\r
- mon_sent_bytes <= mon_sent_bytes + x"1";\r
- else\r
- mon_sent_bytes <= mon_sent_bytes;\r
- end if;\r
- end if;\r
-end process;\r
-\r
-end trb_net16_gbe_frame_constr;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
--- here all frame checking has to be done, if the frame fits into protocol standards
--- if so FR_FRAME_VALID_OUT is asserted after having received all bytes of a frame
--- otherwise, after receiving all bytes, FR_FRAME_VALID_OUT keeps low and the fifo is cleared
--- also a part of addresses assignemt has to be done here
-
-entity trb_net16_gbe_frame_receiver is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
- LINK_OK_IN : in std_logic;
- ALLOW_RX_IN : in std_logic;
- RX_MAC_CLK : in std_logic; -- receiver serdes clock
-
--- input signals from TS_MAC
- MAC_RX_EOF_IN : in std_logic;
- MAC_RX_ER_IN : in std_logic;
- MAC_RXD_IN : in std_logic_vector(7 downto 0);
- MAC_RX_EN_IN : in std_logic;
- MAC_RX_FIFO_ERR_IN : in std_logic;
- MAC_RX_FIFO_FULL_OUT : out std_logic;
- MAC_RX_STAT_EN_IN : in std_logic;
- MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0);
-
--- output signal to control logic
- FR_Q_OUT : out std_logic_vector(8 downto 0);
- FR_RD_EN_IN : in std_logic;
- FR_FRAME_VALID_OUT : out std_logic;
- FR_GET_FRAME_IN : in std_logic;
- FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0);
- FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0);
- FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0);
- FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0);
- FR_VLAN_ID_IN : in std_logic_vector(31 downto 0);
-
- FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
- MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_frame_receiver;
-
-
-architecture trb_net16_gbe_frame_receiver of trb_net16_gbe_frame_receiver is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_frame_receiver : architecture is "GBE_LINK_group";
-
-attribute syn_encoding : string;
-type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME, REMOVE_VID, REMOVE_VTYPE, REMOVE_IP, REMOVE_UDP, DECIDE, CLEANUP);
-signal filter_current_state, filter_next_state : filter_states;
-attribute syn_encoding of filter_current_state : signal is "onehot";
-
-signal fifo_wr_en : std_logic;
-signal rx_bytes_ctr : std_logic_vector(15 downto 0);
-signal frame_valid_q : std_logic;
-signal delayed_frame_valid : std_logic;
-signal delayed_frame_valid_q : std_logic;
-
-signal rec_fifo_empty : std_logic;
-signal rec_fifo_full : std_logic;
-signal sizes_fifo_full : std_logic;
-signal sizes_fifo_empty : std_logic;
-
-signal remove_ctr : std_logic_vector(7 downto 0);
-signal new_frame : std_logic;
-signal new_frame_lock : std_logic := '0';
-signal saved_frame_type : std_logic_vector(15 downto 0);
-signal saved_vid : std_logic_vector(15 downto 0) := (others => '0');
-signal saved_src_mac : std_logic_vector(47 downto 0);
-signal saved_dest_mac : std_logic_vector(47 downto 0);
-signal frame_type_valid : std_logic;
-signal saved_proto : std_logic_vector(7 downto 0);
-signal saved_src_ip : std_logic_vector(31 downto 0);
-signal saved_dest_ip : std_logic_vector(31 downto 0);
-signal saved_src_udp : std_logic_vector(15 downto 0);
-signal saved_dest_udp : std_logic_vector(15 downto 0);
-
-signal dump : std_logic_vector(7 downto 0);
-signal dump2 : std_logic_vector(7 downto 0);
-
-signal error_frames_ctr : std_logic_vector(15 downto 0);
-
--- debug signals
-signal dbg_rec_frames : std_logic_vector(31 downto 0);
-signal dbg_drp_frames : std_logic_vector(31 downto 0);
-signal state : std_logic_vector(3 downto 0);
-
-signal rx_data, fr_q : std_logic_vector(8 downto 0);
-
-signal fr_src_ip, fr_dest_ip : std_logic_vector(31 downto 0);
-signal fr_dest_udp, fr_src_udp, fr_frame_size, fr_frame_proto : std_logic_vector(15 downto 0);
-signal fr_dest_mac, fr_src_mac : std_logic_vector(47 downto 0);
-signal fr_ip_proto : std_logic_vector(7 downto 0);
-signal mon_rec_bytes : std_logic_vector(31 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true;
-attribute syn_preserve of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true;
-
-begin
-
--- new_frame is asserted when first byte of the frame arrives
-NEW_FRAME_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (LINK_OK_IN = '0' or MAC_RX_EOF_IN = '1') then
- new_frame <= '0';
- new_frame_lock <= '0';
- elsif (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') then
- new_frame <= '1';
- new_frame_lock <= '1';
- else
- new_frame <= '0';
- new_frame_lock <= new_frame_lock;
- end if;
- end if;
-end process NEW_FRAME_PROC;
-
-
-FILTER_MACHINE_PROC : process(RX_MAC_CLK, RESET)
-begin
- if RESET = '1' then
- filter_current_state <= IDLE;
- elsif rising_edge(RX_MAC_CLK) then
--- if (RESET = '1') then
--- filter_current_state <= IDLE;
--- else
- filter_current_state <= filter_next_state;
--- end if;
- end if;
-end process FILTER_MACHINE_PROC;
-
-FILTER_MACHINE : process(filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, g_MY_MAC, saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)
-begin
-
- case filter_current_state is
-
- when IDLE =>
- state <= x"1";
- if (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') then
- filter_next_state <= REMOVE_DEST;
- else
- filter_next_state <= IDLE;
- end if;
-
- -- frames arrive without preamble!
- when REMOVE_DEST =>
- state <= x"3";
- if (remove_ctr = x"03") then -- counter starts with a delay that's why only 3
- -- destination MAC address filtering here
- if (saved_dest_mac = g_MY_MAC) or (saved_dest_mac = x"ffffffffffff") then -- must accept broadcasts for ARP
- filter_next_state <= REMOVE_SRC;
- else
- filter_next_state <= DECIDE;
- end if;
- else
- filter_next_state <= REMOVE_DEST;
- end if;
-
- when REMOVE_SRC =>
- state <= x"4";
- if (remove_ctr = x"09") then
- filter_next_state <= REMOVE_TYPE;
- else
- filter_next_state <= REMOVE_SRC;
- end if;
-
- when REMOVE_TYPE =>
- state <= x"5";
- if (remove_ctr = x"0b") then
- if (saved_frame_type = x"8100") then -- VLAN tagged frame
- filter_next_state <= REMOVE_VID;
- else -- no VLAN tag
- if (saved_frame_type = x"0800") then -- in case of IP continue removing headers
- filter_next_state <= REMOVE_IP;
- else
- filter_next_state <= DECIDE;
- end if;
- end if;
- else
- filter_next_state <= REMOVE_TYPE;
- end if;
-
- when REMOVE_VID =>
- state <= x"a";
- if (remove_ctr = x"0d") then
- filter_next_state <= REMOVE_VTYPE;
- else
- filter_next_state <= REMOVE_VID;
- end if;
-
- when REMOVE_VTYPE =>
- state <= x"b";
- if (remove_ctr = x"0f") then
- if (saved_frame_type = x"0800") then -- in case of IP continue removing headers
- filter_next_state <= REMOVE_IP;
- else
- filter_next_state <= DECIDE;
- end if;
- else
- filter_next_state <= REMOVE_VTYPE;
- end if;
-
- when REMOVE_IP =>
- state <= x"c";
- if (remove_ctr = x"11") then
- if (saved_proto = x"11") then -- forced to recognize udp only, TODO check all protocols
- filter_next_state <= REMOVE_UDP;
- else
- filter_next_state <= DECIDE; -- changed from drop
- end if;
- else
- filter_next_state <= REMOVE_IP;
- end if;
-
- when REMOVE_UDP =>
- state <= x"d";
- if (remove_ctr = x"19") then
- filter_next_state <= DECIDE;
- else
- filter_next_state <= REMOVE_UDP;
- end if;
-
- when DECIDE =>
- state <= x"6";
- if (frame_type_valid = '1') then
- filter_next_state <= SAVE_FRAME;
- elsif (saved_frame_type = x"0806") then
- filter_next_state <= SAVE_FRAME;
- else
- filter_next_state <= DROP_FRAME;
- end if;
-
- when SAVE_FRAME =>
- state <= x"7";
- if (MAC_RX_EOF_IN = '1') then
- filter_next_state <= CLEANUP;
- else
- filter_next_state <= SAVE_FRAME;
- end if;
-
- when DROP_FRAME =>
- state <= x"8";
- if (MAC_RX_EOF_IN = '1') then
- filter_next_state <= CLEANUP;
- else
- filter_next_state <= DROP_FRAME;
- end if;
-
- when CLEANUP =>
- state <= x"9";
- filter_next_state <= IDLE;
-
- when others => null;
-
- end case;
-end process;
-
--- counts the bytes to be removed from the ethernet headers fields
-REMOVE_CTR_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = IDLE) or
- (filter_current_state = REMOVE_VTYPE and remove_ctr = x"0f") or
- (filter_current_state = REMOVE_TYPE and remove_ctr = x"0b") then
-
- remove_ctr <= (others => '1');
- elsif (MAC_RX_EN_IN = '1') and (filter_current_state /= IDLE) then --and (filter_current_state /= CLEANUP) then
- remove_ctr <= remove_ctr + x"1";
- else
- remove_ctr <= remove_ctr;
- end if;
- end if;
-end process REMOVE_CTR_PROC;
-
-SAVED_PROTO_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = CLEANUP) then
- saved_proto <= (others => '0');
- elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"07") then
- saved_proto <= MAC_RXD_IN;
- else
- saved_proto <= saved_proto;
- end if;
- end if;
-end process SAVED_PROTO_PROC;
-
-SAVED_SRC_IP_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = CLEANUP) then
- saved_src_ip <= (others => '0');
- elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0a") then
- saved_src_ip(7 downto 0) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0b") then
- saved_src_ip(15 downto 8) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0c") then
- saved_src_ip(23 downto 16) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0d") then
- saved_src_ip(31 downto 24) <= MAC_RXD_IN;
- else
- saved_src_ip <= saved_src_ip;
- end if;
- end if;
-end process SAVED_SRC_IP_PROC;
-
-SAVED_DEST_IP_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = CLEANUP) then
- saved_dest_ip <= (others => '0');
- elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0e") then
- saved_dest_ip(7 downto 0) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0f") then
- saved_dest_ip(15 downto 8) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"10") then
- saved_dest_ip(23 downto 16) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"11") then
- saved_dest_ip(31 downto 24) <= MAC_RXD_IN;
- else
- saved_dest_ip <= saved_dest_ip;
- end if;
- end if;
-end process SAVED_DEST_IP_PROC;
-
-SAVED_SRC_UDP_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = CLEANUP) then
- saved_src_udp <= (others => '0');
- elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"12") then
- saved_src_udp(15 downto 8) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"13") then
- saved_src_udp(7 downto 0) <= MAC_RXD_IN;
- else
- saved_src_udp <= saved_src_udp;
- end if;
- end if;
-end process SAVED_SRC_UDP_PROC;
-
-SAVED_DEST_UDP_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = CLEANUP) then
- saved_dest_udp <= (others => '0');
- elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"14") then
- saved_dest_udp(15 downto 8) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"15") then
- saved_dest_udp(7 downto 0) <= MAC_RXD_IN;
- else
- saved_dest_udp <= saved_dest_udp;
- end if;
- end if;
-end process SAVED_DEST_UDP_PROC;
-
--- saves the destination mac address of the incoming frame
-SAVED_DEST_MAC_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = CLEANUP) then
- saved_dest_mac <= (others => '0');
- elsif (filter_current_state = IDLE) and (MAC_RX_EN_IN = '1') and (new_frame = '0') then
- saved_dest_mac(7 downto 0) <= MAC_RXD_IN;
- elsif (filter_current_state = IDLE) and (new_frame = '1') and (ALLOW_RX_IN = '1') then
- saved_dest_mac(15 downto 8) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"FF") then
- saved_dest_mac(23 downto 16) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"00") then
- saved_dest_mac(31 downto 24) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"01") then
- saved_dest_mac(39 downto 32) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"02") then
- saved_dest_mac(47 downto 40) <= MAC_RXD_IN;
- else
- saved_dest_mac <= saved_dest_mac;
- end if;
- end if;
-end process SAVED_DEST_MAC_PROC;
-
--- saves the source mac address of the incoming frame
-SAVED_SRC_MAC_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = CLEANUP) then
- saved_src_mac <= (others => '0');
- elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"03") then
- saved_src_mac(7 downto 0) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"04") then
- saved_src_mac(15 downto 8) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"05") then
- saved_src_mac(23 downto 16) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"06") then
- saved_src_mac(31 downto 24) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"07") then
- saved_src_mac(39 downto 32) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"08") then
- saved_src_mac(47 downto 40) <= MAC_RXD_IN;
- else
- saved_src_mac <= saved_src_mac;
- end if;
- end if;
-end process SAVED_SRC_MAC_PROC;
-
--- saves the frame type of the incoming frame for futher check
-SAVED_FRAME_TYPE_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = CLEANUP) then
- saved_frame_type <= (others => '0');
- elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"09") then
- saved_frame_type(15 downto 8) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0a") then
- saved_frame_type(7 downto 0) <= MAC_RXD_IN;
- -- two more cases for VLAN tagged frame
- elsif (filter_current_state = REMOVE_VID) and (remove_ctr = x"0d") then
- saved_frame_type(15 downto 8) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0e") then
- saved_frame_type(7 downto 0) <= MAC_RXD_IN;
- else
- saved_frame_type <= saved_frame_type;
- end if;
- end if;
-end process SAVED_FRAME_TYPE_PROC;
-
--- saves VLAN id when tagged frame spotted
-SAVED_VID_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (filter_current_state = CLEANUP) then
- saved_vid <= (others => '0');
- elsif (filter_current_state = REMOVE_TYPE and remove_ctr = x"0b" and saved_frame_type = x"8100") then
- saved_vid(15 downto 8) <= MAC_RXD_IN;
- elsif (filter_current_state = REMOVE_VID and remove_ctr = x"0c") then
- saved_vid(7 downto 0) <= MAC_RXD_IN;
- else
- saved_vid <= saved_vid;
- end if;
- end if;
-end process SAVED_VID_PROC;
-
-type_validator : trb_net16_gbe_type_validator
-port map(
- CLK => RX_MAC_CLK,
- RESET => RESET,
- FRAME_TYPE_IN => saved_frame_type,
- SAVED_VLAN_ID_IN => saved_vid,
- ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN,
- VLAN_ID_IN => FR_VLAN_ID_IN,
-
- -- IP level
- IP_PROTOCOLS_IN => saved_proto,
- ALLOWED_IP_PROTOCOLS_IN => FR_ALLOWED_IP_IN,
-
- -- UDP level
- UDP_PROTOCOL_IN => saved_dest_udp,
- ALLOWED_UDP_PROTOCOLS_IN => FR_ALLOWED_UDP_IN,
-
- VALID_OUT => frame_type_valid
-);
-
-receive_fifo : fifo_4096x9
-port map(
--- Data(7 downto 0) => MAC_RXD_IN,
--- Data(8) => MAC_RX_EOF_IN,
- Data => rx_data,
- WrClock => RX_MAC_CLK,
- RdClock => CLK,
- WrEn => fifo_wr_en,
- RdEn => FR_RD_EN_IN,
- Reset => RESET,
- RPReset => RESET,
- Q => fr_q, --FR_Q_OUT,
- Empty => rec_fifo_empty,
- Full => rec_fifo_full
-);
-
--- BUG HERE, probably more lost bytes in the fifo in other conditions
---fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FRAME) or
--- --( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or
--- ((filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or
--- (filter_current_state = DECIDE and frame_type_valid = '1')))
--- else '0';
-
-RX_FIFO_SYNC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
-
- rx_data(8) <= MAC_RX_EOF_IN;
- rx_data(7 downto 0) <= MAC_RXD_IN;
-
- if (MAC_RX_EN_IN = '1') then
- if (filter_current_state = SAVE_FRAME) then
- fifo_wr_en <= '1';
- elsif (filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") then
- fifo_wr_en <= '1';
- elsif (filter_current_state = DECIDE and frame_type_valid = '1') then
- fifo_wr_en <= '1';
- else
- fifo_wr_en <= '0';
- end if;
- else
- fifo_wr_en <= '0';
- end if;
-
- MAC_RX_FIFO_FULL_OUT <= rec_fifo_full;
- end if;
-end process RX_FIFO_SYNC;
-
-
-
-sizes_fifo : fifo_512x32
-port map(
- Data(15 downto 0) => rx_bytes_ctr,
- Data(31 downto 16) => saved_frame_type,
- WrClock => RX_MAC_CLK,
- RdClock => CLK,
- WrEn => frame_valid_q,
- RdEn => FR_GET_FRAME_IN,
- Reset => RESET,
- RPReset => RESET,
- Q(15 downto 0) => fr_frame_size, --FR_FRAME_SIZE_OUT,
- Q(31 downto 16) => fr_frame_proto, --FR_FRAME_PROTO_OUT,
- Empty => sizes_fifo_empty,
- Full => sizes_fifo_full
-);
-
-macs_fifo : fifo_512x72
-port map(
- Data(47 downto 0) => saved_src_mac,
- Data(63 downto 48) => saved_src_udp,
- Data(71 downto 64) => (others => '0'),
- WrClock => RX_MAC_CLK,
- RdClock => CLK,
- WrEn => frame_valid_q,
- RdEn => FR_GET_FRAME_IN,
- Reset => RESET,
- RPReset => RESET,
- Q(47 downto 0) => fr_src_mac, --FR_SRC_MAC_ADDRESS_OUT,
- Q(63 downto 48) => fr_src_udp, --FR_SRC_UDP_PORT_OUT,
- Q(71 downto 64) => dump2,
- Empty => open,
- Full => open
-);
-
-macd_fifo : fifo_512x72
-port map(
- Data(47 downto 0) => saved_dest_mac,
- Data(63 downto 48) => saved_dest_udp,
- Data(71 downto 64) => (others => '0'),
- WrClock => RX_MAC_CLK,
- RdClock => CLK,
- WrEn => frame_valid_q,
- RdEn => FR_GET_FRAME_IN,
- Reset => RESET,
- RPReset => RESET,
- Q(47 downto 0) => fr_dest_mac, --FR_DEST_MAC_ADDRESS_OUT,
- Q(63 downto 48) => fr_dest_udp, --FR_DEST_UDP_PORT_OUT,
- Q(71 downto 64) => dump,
- Empty => open,
- Full => open
-);
-
-ip_fifo : fifo_512x72
-port map(
- Data(31 downto 0) => saved_src_ip,
- Data(63 downto 32) => saved_dest_ip,
- Data(71 downto 64) => saved_proto,
- WrClock => RX_MAC_CLK,
- RdClock => CLK,
- WrEn => frame_valid_q,
- RdEn => FR_GET_FRAME_IN,
- Reset => RESET,
- RPReset => RESET,
- Q(31 downto 0) => fr_src_ip, --FR_SRC_IP_ADDRESS_OUT,
- Q(63 downto 32) => fr_dest_ip, --FR_DEST_IP_ADDRESS_OUT,
- Q(71 downto 64) => fr_ip_proto, --FR_IP_PROTOCOL_OUT,
- Empty => open,
- Full => open
-);
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- FR_SRC_IP_ADDRESS_OUT <= fr_src_ip;
- FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip;
- FR_IP_PROTOCOL_OUT <= fr_ip_proto;
- FR_DEST_UDP_PORT_OUT <= fr_dest_udp;
- FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac;
- FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac;
- FR_SRC_UDP_PORT_OUT <= fr_src_udp;
- FR_FRAME_PROTO_OUT <= fr_frame_proto;
- FR_FRAME_SIZE_OUT <= fr_frame_size;
- FR_Q_OUT <= fr_q;
- end if;
-end process;
-
-FRAME_VALID_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (MAC_RX_EOF_IN = '1' and ALLOW_RX_IN = '1' and frame_type_valid = '1') then
- frame_valid_q <= '1';
- else
- frame_valid_q <= '0';
- end if;
- end if;
-end process FRAME_VALID_PROC;
-
-RX_BYTES_CTR_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (RESET = '1') or (delayed_frame_valid_q = '1') then
- rx_bytes_ctr <= x"0001";
- elsif (fifo_wr_en = '1') then
- rx_bytes_ctr <= rx_bytes_ctr + x"1";
- end if;
- end if;
-end process;
-
-ERROR_FRAMES_CTR_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (RESET = '1') then
- error_frames_ctr <= (others => '0');
- elsif (MAC_RX_ER_IN = '1') then
- error_frames_ctr <= error_frames_ctr + x"1";
- end if;
- end if;
-end process ERROR_FRAMES_CTR_PROC;
-
-
-SYNC_PROC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- delayed_frame_valid <= MAC_RX_EOF_IN;
- delayed_frame_valid_q <= delayed_frame_valid;
- end if;
-end process SYNC_PROC;
-
---*****************
--- synchronization between 125MHz receive clock and 100MHz system clock
-FRAME_VALID_SYNC : pulse_sync
-port map(
- CLK_A_IN => RX_MAC_CLK,
- RESET_A_IN => RESET,
- PULSE_A_IN => frame_valid_q,
- CLK_B_IN => CLK,
- RESET_B_IN => RESET,
- PULSE_B_OUT => FR_FRAME_VALID_OUT
-);
-
-
--- ****
--- debug counters, to be removed later
-RECEIVED_FRAMES_CTR : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (RESET = '1') then
- dbg_rec_frames <= (others => '0');
- elsif (MAC_RX_EOF_IN = '1') then
- dbg_rec_frames <= dbg_rec_frames + x"1";
- end if;
- end if;
-end process RECEIVED_FRAMES_CTR;
-
-DROPPED_FRAMES_CTR : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (RESET = '1') then
- dbg_drp_frames <= (others => '0');
- elsif (filter_current_state = DECIDE and frame_type_valid = '0') then
- dbg_drp_frames <= dbg_drp_frames + x"1";
- end if;
- end if;
-end process DROPPED_FRAMES_CTR;
-
-sync1 : signal_sync
-generic map (
- WIDTH => 32,
- DEPTH => 2
-)
-port map (
- RESET => RESET,
- CLK0 => CLK,
- CLK1 => CLK,
- D_IN => dbg_drp_frames,
- D_OUT => MONITOR_DROPPED_OUT
-);
-
-sync3 : signal_sync
-generic map (
- WIDTH => 32,
- DEPTH => 2
-)
-port map (
- RESET => RESET,
- CLK0 => CLK,
- CLK1 => CLK,
- D_IN => dbg_rec_frames,
- D_OUT => MONITOR_RX_FRAMES_OUT
-);
-
-sync4 : signal_sync
-generic map (
- WIDTH => 32,
- DEPTH => 2
-)
-port map (
- RESET => RESET,
- CLK0 => CLK,
- CLK1 => CLK,
- D_IN => mon_rec_bytes,
- D_OUT => MONITOR_RX_BYTES_OUT
-);
-
-process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
- if (RESET = '1') then
- mon_rec_bytes <= (others => '0');
- elsif (fifo_wr_en = '1') then
- mon_rec_bytes <= mon_rec_bytes + x"1";
- else
- mon_rec_bytes <= mon_rec_bytes;
- end if;
- end if;
-end process;
-
--- end of debug counters
--- ****
-
-end trb_net16_gbe_frame_receiver;
-
-
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.trb_net16_hub_func.all;\r
-\r
-entity trb_net16_gbe_frame_trans is\r
-port (\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- LINK_OK_IN : in std_logic; -- gk 03.08.10\r
- TX_MAC_CLK : in std_logic;\r
- TX_EMPTY_IN : in std_logic;\r
- START_OF_PACKET_IN : in std_logic;\r
- DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC\r
-\r
- TX_FIFOAVAIL_OUT : out std_logic;\r
- TX_FIFOEOF_OUT : out std_logic;\r
- TX_FIFOEMPTY_OUT : out std_logic;\r
- TX_DONE_IN : in std_logic;\r
- TX_STAT_EN_IN : in std_logic;\r
- TX_STATVEC_IN : in std_logic_vector(30 downto 0);\r
- TX_DISCFRM_IN : in std_logic;\r
- -- Debug\r
- BSM_INIT_OUT : out std_logic_vector(3 downto 0);\r
- BSM_MAC_OUT : out std_logic_vector(3 downto 0);\r
- BSM_TRANS_OUT : out std_logic_vector(3 downto 0);\r
- DBG_RD_DONE_OUT : out std_logic;\r
- DBG_INIT_DONE_OUT : out std_logic;\r
- DBG_ENABLED_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
-);\r
-end trb_net16_gbe_frame_trans;\r
-\r
--- FifoRd ?!?\r
-\r
-architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is\r
-\r
---attribute HGROUP : string;\r
---attribute HGROUP of trb_net16_gbe_frame_trans : architecture is "GBE_BUF_group";\r
-\r
-component mac_init_mem is\r
-port (\r
- Address : in std_logic_vector(5 downto 0); \r
- OutClock : in std_logic; \r
- OutClockEn : in std_logic; \r
- Reset : in std_logic; \r
- Q : out std_logic_vector(7 downto 0)\r
-);\r
-end component;\r
-\r
-attribute syn_encoding : string;\r
-\r
-type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED);\r
-signal macInitState, macInitNextState : macInitStates;\r
-attribute syn_encoding of macInitState: signal is "onehot";\r
-signal bsm_init : std_logic_vector(3 downto 0);\r
- \r
-type macStates is (M_RESETING, M_IDLE, M_INIT);\r
-signal macCurrentState, macNextState : macStates;\r
-attribute syn_encoding of macCurrentState : signal is "onehot";\r
-signal bsm_mac : std_logic_vector(3 downto 0);\r
- \r
-type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO);\r
-signal transmitCurrentState, transmitNextState : transmitStates;\r
-attribute syn_encoding of transmitCurrentState: signal is "onehot";\r
-signal bsm_trans : std_logic_vector(3 downto 0);\r
-\r
-signal tx_fifoavail_i : std_logic;\r
-signal tx_fifoeof_i : std_logic;\r
-\r
--- host interface signals\r
-signal hcs_n_i : std_logic;\r
-signal hwrite_n_i : std_logic;\r
-signal hread_n_i : std_logic;\r
-\r
--- MAC INITIALIZATION signals\r
-signal macInitMemAddr : std_logic_vector(5 downto 0);\r
-signal macInitMemQ : std_logic_vector(7 downto 0);\r
-signal macInitMemEn : std_logic;\r
-signal reading_done : std_logic;\r
-signal init_done : std_logic;\r
-signal enabled : std_logic;\r
-signal addrSig : std_logic_vector(5 downto 0);\r
-signal addr2 : std_logic_vector(5 downto 0);\r
-signal resetAddr : std_logic;\r
-\r
-signal FifoEmpty : std_logic;\r
-signal debug : std_logic_vector(63 downto 0);\r
-signal sent_ctr : std_logic_vector(31 downto 0);\r
-signal link_ok_125 : std_logic;\r
-\r
-begin\r
-\r
-linkOkSync : pulse_sync\r
-port map(\r
- CLK_A_IN => CLK,\r
- RESET_A_IN => RESET,\r
- PULSE_A_IN => LINK_OK_IN,\r
- CLK_B_IN => TX_MAC_CLK,\r
- RESET_B_IN => RESET,\r
- PULSE_B_OUT => link_ok_125\r
-);\r
-\r
--- Fakes\r
-debug(63 downto 32) <= (others => '0');\r
---debug(31 downto 0) <= sent_ctr;\r
-\r
-\r
-TransmitStateMachineProc : process (TX_MAC_CLK)\r
-begin\r
- if RESET = '1' then\r
- transmitCurrentState <= T_IDLE;\r
- elsif rising_edge(TX_MAC_CLK) then\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- transmitCurrentState <= T_IDLE;\r
- else\r
- transmitCurrentState <= transmitNextState;\r
- end if;\r
- end if;\r
-end process TransmitStatemachineProc;\r
-\r
-TransmitStateMachine : process (transmitCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN)\r
-begin\r
- case transmitCurrentState is\r
- when T_IDLE =>\r
- bsm_trans <= x"0";\r
- if (START_OF_PACKET_IN = '1') then\r
- transmitNextState <= T_TRANSMIT;\r
- else\r
- transmitNextState <= T_IDLE;\r
- end if;\r
- when T_TRANSMIT =>\r
- bsm_trans <= x"1";\r
- if (DATA_ENDFLAG_IN = '1') then\r
- transmitNextState <= T_WAITFORFIFO;\r
- else\r
- transmitNextState <= T_TRANSMIT;\r
- end if;\r
- when T_WAITFORFIFO =>\r
- bsm_trans <= x"2";\r
- if (TX_DONE_IN = '1') then\r
- transmitNextState <= T_IDLE;\r
- else\r
- transmitNextState <= T_WAITFORFIFO;\r
- end if;\r
- when others =>\r
- bsm_trans <= x"f";\r
- transmitNextState <= T_IDLE;\r
- end case;\r
-end process TransmitStateMachine;\r
- \r
-FifoAvailProc : process (TX_MAC_CLK)\r
-begin\r
- if rising_edge(TX_MAC_CLK) then\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- tx_fifoavail_i <= '0';\r
- elsif (transmitCurrentState = T_TRANSMIT) then\r
- tx_fifoavail_i <= '1';\r
- else\r
- tx_fifoavail_i <= '0';\r
- end if;\r
- end if;\r
-end process FifoAvailProc;\r
-\r
-FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, RESET)\r
-begin\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- FifoEmpty <= '1';\r
- elsif (transmitCurrentState = T_WAITFORFIFO) then\r
- FifoEmpty <= '1';\r
- elsif (transmitCurrentState = T_TRANSMIT) then\r
- FifoEmpty <= TX_EMPTY_IN;\r
- elsif (((transmitCurrentState = T_IDLE) or (transmitCurrentState = T_WAITFORFIFO)) and (START_OF_PACKET_IN = '1')) then\r
- FifoEmpty <= '0';\r
- else\r
- FifoEmpty <= '1';\r
- end if;\r
-end process FifoEmptyProc;\r
-\r
-tx_fifoeof_i <= '1' when ((DATA_ENDFLAG_IN = '1') and (transmitCurrentState = T_TRANSMIT)) \r
- else '0';\r
- \r
-SENT_CTR_PROC : process(TX_MAC_CLK)\r
-begin\r
- if (RESET = '1') then\r
- sent_ctr <= (others => '0');\r
- elsif rising_edge(TX_MAC_CLK) then\r
- if (TX_DONE_IN = '1') and (TX_STAT_EN_IN = '1') and (TX_STATVEC_IN(0) = '1') then\r
- sent_ctr <= sent_ctr + x"1";\r
- else\r
- sent_ctr <= sent_ctr;\r
- end if;\r
- end if;\r
-end process SENT_CTR_PROC;\r
-\r
-sync1 : signal_sync\r
-generic map(\r
- WIDTH => 32,\r
- DEPTH => 2\r
-)\r
-port map (\r
- RESET => RESET,\r
- CLK0 => CLK,\r
- CLK1 => CLK,\r
- D_IN => sent_ctr,\r
- D_OUT => debug(31 downto 0)\r
-);\r
-\r
-TX_FIFOAVAIL_OUT <= tx_fifoavail_i;\r
-TX_FIFOEOF_OUT <= tx_fifoeof_i;\r
-TX_FIFOEMPTY_OUT <= FifoEmpty;\r
-\r
-BSM_INIT_OUT <= bsm_init;\r
-BSM_MAC_OUT <= bsm_mac;\r
-BSM_TRANS_OUT <= bsm_trans;\r
-DBG_RD_DONE_OUT <= reading_done;\r
-DBG_INIT_DONE_OUT <= init_done;\r
-DBG_ENABLED_OUT <= enabled;\r
-DEBUG_OUT <= debug;\r
-\r
-end trb_net16_gbe_frame_trans;\r
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-
-entity trb_net16_ipu2gbe is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
- MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
-
- SCTRL_DUMMY_SIZE_IN : in std_logic_vector(15 downto 0);
- SCTRL_DUMMY_PAUSE_IN : in std_logic_vector(31 downto 0);
-
- -- PacketConstructor interface
- ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic; -- gk 07.10.10
- PC_EOD_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_PADDING_OUT : out std_logic;
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
-);
-end entity;
-
-architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is
-
--- attribute HGROUP : string;
--- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe";
-
-component fifo_32kx16x8_mb2
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(8 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0);
- Empty : out std_logic;
- AlmostEmpty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
-);
-end component;
-
-type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE, RESET_FIFO);
-signal saveCurrentState, saveNextState : saveStates;
-signal state : std_logic_vector(3 downto 0);
-signal data_req_comb : std_logic;
-signal data_req : std_logic; -- request data signal, will be used for fee_read generation
-signal rst_saved_ctr_comb : std_logic;
-signal rst_saved_ctr : std_logic;
-
-signal fee_read_comb : std_logic;
-signal fee_read : std_logic; -- fee_read signal
-signal saved_ctr : std_logic_vector(16 downto 0);
-signal ce_saved_ctr : std_logic;
-
--- header data
-signal cts_rnd : std_logic_vector(15 downto 0);
-signal cts_rnd_saved : std_logic;
-signal cts_trg : std_logic_vector(15 downto 0);
-signal cts_trg_saved : std_logic;
-signal cts_len : std_logic_vector(16 downto 0);
-signal cts_len_saved : std_logic;
-
--- CTS interface
-signal cts_error_pattern : std_logic_vector(31 downto 0);
-signal cts_length : std_logic_vector(15 downto 0);
-signal cts_readout_finished : std_logic;
-signal cts_dataready : std_logic;
-signal cts_data : std_logic_vector(31 downto 0);
-
--- Split FIFO signals
-signal sf_data : std_logic_vector(15 downto 0);
-signal sf_wr_en_comb : std_logic;
-signal sf_wr_en : std_logic; -- write signal for FIFO
-signal sf_rd_en_comb : std_logic;
-signal sf_rd_en : std_logic; -- read signal for FIFO
-signal sf_wcnt : std_logic_vector(15 downto 0);
-signal sf_rcnt : std_logic_vector(16 downto 0);
-signal sf_empty : std_logic;
-signal sf_aempty : std_logic;
-signal sf_full : std_logic;
-signal sf_afull : std_logic;
-
--------------------------------------------------------------------
-type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2);
-signal loadCurrentState, loadNextState : loadStates;
-signal state2 : std_logic_vector(3 downto 0);
-
-signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data
-signal rst_rem_ctr_comb : std_logic;
-signal rst_rem_ctr : std_logic; -- reset the remove counter
-signal rst_regs_comb : std_logic;
-signal rst_regs : std_logic; -- reset storage registers
-signal rem_phase_comb : std_logic;
-signal rem_phase : std_logic; -- header remove phase
-signal data_phase_comb : std_logic;
-signal data_phase : std_logic; -- data transport phase from split fifo to PC
-signal pad_phase_comb : std_logic;
-signal pad_phase : std_logic; -- padding phase
-signal calc_pad_comb : std_logic;
-signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE
-signal pad_data_comb : std_logic;
-signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value
-
-signal pc_sos_comb : std_logic;
-signal pc_sos : std_logic; -- start of data signal
-signal pc_eod_comb : std_logic;
-signal pc_eod : std_logic; -- end of data signal
-
-signal ce_rem_ctr_comb : std_logic;
-signal ce_rem_ctr : std_logic; -- count enable for remove counter
-signal remove_done_comb : std_logic;
-signal remove_done : std_logic; -- end of header stripping process
-signal read_done_comb : std_logic;
-signal read_done : std_logic; -- end of data phase (read phase from SF)
-
-signal pc_data : std_logic_vector(7 downto 0);
-signal pc_data_q : std_logic_vector(7 downto 0);
-signal pc_trig_nr : std_logic_vector(15 downto 0);
-signal pc_sub_size : std_logic_vector(17 downto 0);
-signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo
-signal padding_needed : std_logic;
-signal pc_wr_en_comb : std_logic;
-signal pc_wr_en_q : std_logic;
-signal pc_wr_en_qq : std_logic;
-signal pc_wr_en_qqq : std_logic;
-signal pc_eod_q : std_logic;
-
-signal debug : std_logic_vector(383 downto 0);
-
--- gk
-signal bank_select : std_logic_vector(3 downto 0);
-signal save_addr_comb : std_logic;
-signal save_addr : std_logic;
-signal addr_saved_comb : std_logic;
-signal addr_saved : std_logic;
-signal start_config : std_logic;
-signal config_done : std_logic;
-signal add_sub_state : std_logic;
-signal add_sub_state_comb : std_logic;
-signal add_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub : std_logic;
-signal load_sub_comb : std_logic;
-signal load_sub_done : std_logic;
-signal load_sub_done_comb : std_logic;
-signal load_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub_ctr_comb : std_logic;
-signal actual_message_size : std_logic_vector(31 downto 0);
-signal more_subevents : std_logic;
-signal trig_random : std_logic_vector(7 downto 0);
-signal readout_ctr : std_logic_vector(23 downto 0);
-signal readout_ctr_lock : std_logic;
-signal pc_trig_nr_q : std_logic_vector(31 downto 0);
-
--- gk 20.07.10
-signal inc_data_ctr : std_logic_vector(31 downto 0);
-signal dropped_sm_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_lr_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_ctr : std_logic_vector(31 downto 0);
--- gk 22.07.10
-signal headers_invalid : std_logic;
-signal headers_invalid_ctr : std_logic_vector(31 downto 0);
-signal cts_len_q : std_logic_vector(15 downto 0);
-signal cts_trg_q : std_logic_vector(15 downto 0);
-signal cts_rnd_q : std_logic_vector(15 downto 0);
-signal first_run_trg : std_logic_vector(15 downto 0);
-signal first_run_addr : std_logic_vector(15 downto 0);
-signal first_run_lock : std_logic;
-signal cts_addr : std_logic_vector(15 downto 0);
-signal cts_addr_q : std_logic_vector(15 downto 0);
-signal cts_addr_saved : std_logic;
-
--- gk 24.07.10
-signal save_eod : std_logic;
-signal save_eod_comb : std_logic;
-
-signal load_eod : std_logic;
-signal endpoint_addr : std_logic_vector(15 downto 0);
-signal endp_addr_lock : std_logic;
-
-signal saved_events_ctr : std_logic_vector(15 downto 0);
-signal loaded_events_ctr : std_logic_vector(15 downto 0);
-signal constr_events_ctr : std_logic_vector(31 downto 0);
-signal event_waiting : std_logic;
-
-signal drop_sub : std_logic;
-signal drop_sub_comb : std_logic;
-signal drop_event : std_logic;
-signal drop_event_comb : std_logic;
-signal drop_small : std_logic;
-signal drop_large : std_logic;
-signal drop_headers : std_logic;
-signal drop_small_comb : std_logic;
-signal drop_large_comb : std_logic;
-signal drop_headers_comb : std_logic;
-signal inc_trg_ctr : std_logic;
-signal inc_trg_ctr_comb : std_logic;
-
-signal invalid_hsize_ctr : std_logic_vector(15 downto 0);
-signal invalid_hsize_lock : std_logic;
-
-signal load_eod_q : std_logic;
-signal read_size_q : std_logic_vector(17 downto 0);
-
--- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked
-signal sf_real_wr_en : std_logic;
-
--- gk 01.10.10
-signal found_empty_evt : std_logic;
-signal found_empty_evt_comb : std_logic;
-signal found_empty_evt_ctr : std_logic_vector(31 downto 0);
-
--- gk 06.10.10
-signal message_size : std_logic_vector(31 downto 0);
-
--- gk 07.12.10
-signal prev_bank_select : std_logic_vector(3 downto 0);
-signal first_event : std_logic;
-
-signal reset_split_fifo : std_logic;
-
-signal input_data_ctr : std_logic_vector(31 downto 0);
-
--- SIMPLE SENDER STUFF
-type gen_states is (IDLE, WAIT_FOR_PC, GENERATE_DATA, CLEANUP);
-signal gen_current_state, gen_next_state : gen_states;
-
-signal gen_data_ctr : std_logic_vector(15 downto 0);
-
-begin
-
-BANK_SELECT_OUT <= bank_select; -- gk 27.03.10
-START_CONFIG_OUT <= start_config; -- gk 27.03.10
-config_done <= CONFIG_DONE_IN; -- gk 29.03.10
-
--- CTS interface signals
-cts_error_pattern <= (others => '0'); -- FAKE
-
-cts_length <= x"0000"; -- length of data payload is always 0
-cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'
-
-cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';
-
-cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE)
- else '0';
-
--- Byte swapping... done here. TAKE CARE!
--- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes
--- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port.
--- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped
--- for GbE inside the packet constructor.
---
--- Long live the Endianess!
-
--- Sync all critical pathes
-THE_SYNC_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below
- sf_wr_en <= sf_wr_en_comb;
- ce_rem_ctr <= ce_rem_ctr_comb;
- sf_rd_en <= sf_rd_en_comb;
- fee_read <= fee_read_comb;
- read_done <= read_done_comb;
- pc_eod_q <= pc_eod;
- pc_wr_en_qqq <= pc_wr_en_qq;
- pc_wr_en_qq <= pc_wr_en_q;
- pc_wr_en_q <= pc_wr_en_comb;
- end if;
-end process THE_SYNC_PROC;
-
--- gk 27.03.10 data selector for sf to write the evt builder address on top of data
-SF_DATA_PROC : process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if (RESET = '1') then -- gk 31.05.10
- sf_data <= (others => '0');
- elsif( save_addr = '1' ) then
- sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address
- sf_data(15 downto 4) <= x"abc";
- -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then
- sf_data <= x"0001"; -- gk 11.06.10
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then
- sf_data <= x"5555"; -- gk 11.06.10
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then
- sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then
- sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
- else
- sf_data <= FEE_DATA_IN;
- end if;
- end if;
-end process SF_DATA_PROC;
-
--- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY
-fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
- else '0';
-
--- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY
-sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
- (save_addr = '1') or
- (add_sub_state = '1') -- gk 29.03.10 save the subsubevent
- else '0';
-
--- gk 06.08.10
-sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0';
-
--- gk 27.03.10 do not count evt builder address as saved ipu bytes
---ce_saved_ctr <= sf_wr_en;
-ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en;
-
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO
-saveMachineProc: process( CLK )
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saveCurrentState <= SIDLE;
- data_req <= '0';
- rst_saved_ctr <= '0';
- save_addr <= '0'; -- gk 27.03.10
- addr_saved <= '0'; -- gk 27.03.10
- add_sub_state <= '0'; -- gk 29.03.10
- save_eod <= '0'; -- gk 25.07.10
- else
- saveCurrentState <= saveNextState;
- data_req <= data_req_comb;
- rst_saved_ctr <= rst_saved_ctr_comb;
- save_addr <= save_addr_comb; -- gk 27.03.10
- addr_saved <= addr_saved_comb; -- gk 27.03.10
- add_sub_state <= add_sub_state_comb; -- gk 29.03.10
- save_eod <= save_eod_comb; -- gk 25.07.10
- end if;
- end if;
-end process saveMachineProc;
-
-saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, input_data_ctr, MAX_MESSAGE_SIZE_IN)
-begin
- saveNextState <= SIDLE;
- data_req_comb <= '0';
- rst_saved_ctr_comb <= '0';
- save_addr_comb <= '0'; -- gk 27.03.10
- addr_saved_comb <= '0'; -- gk 27.03.10
- add_sub_state_comb <= '0'; -- gk 29.03.10
- save_eod_comb <= '0'; -- gk 25.07.10
- case saveCurrentState is
- when SIDLE =>
- state <= x"0";
- if (CTS_START_READOUT_IN = '1') then
- saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10
- data_req_comb <= '1';
- rst_saved_ctr_comb <= '1';
- else
- saveNextState <= SIDLE;
- end if;
- -- gk 27.03.10
- when SAVE_EVT_ADDR =>
- state <= x"5";
- saveNextState <= WAIT_FOR_DATA;
- data_req_comb <= '1';
- save_addr_comb <= '1';
- when WAIT_FOR_DATA =>
- state <= x"1";
- if (FEE_BUSY_IN = '1') then
- saveNextState <= SAVE_DATA;
- data_req_comb <= '1';
- else
- saveNextState <= WAIT_FOR_DATA;
- data_req_comb <= '1';
- end if;
- addr_saved_comb <= '1'; -- gk 27.03.10
- when SAVE_DATA =>
- state <= x"2";
- if (FEE_BUSY_IN = '0') then
- saveNextState <= TERMINATE;
- else
- saveNextState <= SAVE_DATA;
- data_req_comb <= '1';
- end if;
- when TERMINATE =>
- state <= x"3";
- if (CTS_READ_IN = '1') then
- saveNextState <= SCLOSE;
- else
- saveNextState <= TERMINATE;
- end if;
- when SCLOSE =>
- state <= x"4";
- if (CTS_START_READOUT_IN = '0') then
- if (input_data_ctr > MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012
- saveNextState <= RESET_FIFO;
- else
- saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10
- end if;
- else
- saveNextState <= SCLOSE;
- end if;
- -- gk 06.11.2012
- when RESET_FIFO =>
- saveNextState <= SIDLE;
- state <= x"E";
- -- gk 29.03.10 new states during which the subsub bytes are saved
- when ADD_SUBSUB1 =>
- state <= x"6";
- saveNextState <= ADD_SUBSUB2;
- add_sub_state_comb <= '1';
- when ADD_SUBSUB2 =>
- state<= x"7";
- saveNextState <= ADD_SUBSUB3;
- add_sub_state_comb <= '1';
- save_eod_comb <= '1';
- when ADD_SUBSUB3 =>
- state<= x"8";
- saveNextState <= ADD_SUBSUB4;
- add_sub_state_comb <= '1';
- when ADD_SUBSUB4 =>
- state<= x"9";
- saveNextState <= SIDLE;
- add_sub_state_comb <= '1';
- when others =>
- state <= x"f";
- saveNextState <= SIDLE;
- end case;
-end process saveMachine;
-
--- gk 06.11.2012
-INPUT_DATA_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1' or rst_saved_ctr = '1') then
- input_data_ctr <= (others => '0');
- elsif (saveCurrentState = SAVE_DATA and sf_real_wr_en = '1') then
- input_data_ctr(31 downto 1) <= input_data_ctr(31 downto 1) + x"1";
- end if;
- end if;
-end process INPUT_DATA_CTR_PROC;
-
--- gk 29.03.10
-ADD_SUB_CTR_PROC : process( CLK )
-begin
- if( rising_edge( CLK ) ) then
- if( (RESET = '1') or (rst_saved_ctr = '1') ) then
- add_sub_ctr <= (others => '0');
- elsif( add_sub_state = '1' ) then
- add_sub_ctr <= add_sub_ctr + 1;
- end if;
- end if;
-end process ADD_SUB_CTR_PROC;
-
---********
--- SAVE INCOMING EVENT HEADERS
---********
-
--- Counter for header word storage
-THE_CTS_SAVED_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- saved_ctr <= (others => '0');
- elsif( ce_saved_ctr = '1' ) then
- saved_ctr <= saved_ctr + 1;
- end if;
- end if;
-end process THE_CTS_SAVED_CTR;
-
--- save triggerRnd from incoming data for cts response
-CTS_RND_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_rnd <= (others => '0');
- cts_rnd_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then
- cts_rnd <= sf_data;
- cts_rnd_saved <= '1';
- end if;
- end if;
-end process CTS_RND_PROC;
-
--- save triggerNr from incoming data for cts response
-CTS_TRG_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_trg <= (others => '0');
- cts_trg_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then
- cts_trg <= sf_data;
- cts_trg_saved <= '1';
- end if;
- end if;
-end process CTS_TRG_PROC;
-
--- save size from incoming data for cts response (future) and to get rid of padding
---CTS_SIZE_PROC: process( CLK )
---begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
--- cts_len <= (others => '0');
--- cts_len_saved <= '0';
--- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then
--- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words
--- cts_len(0) <= '0';
--- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then
--- cts_len <= cts_len + x"4";
--- cts_len_saved <= '1';
--- end if;
--- end if;
---end process CTS_SIZE_PROC;
-
--- gk 22.07.10
---CTS_ADDR_PROC : process(CLK)
---begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
--- cts_addr <= (others => '0');
--- cts_addr_saved <= '0';
--- elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then
--- cts_addr <= sf_data;
--- cts_addr_saved <= '1';
--- end if;
--- end if;
---end process CTS_ADDR_PROC;
-
---******
--- SAVE FIRST EVENT HEADER VALUES
---******
-
--- gk 22.07.10
---FIRST_RUN_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- first_run_trg <= (others => '0');
--- first_run_addr <= (others => '0');
--- first_run_lock <= '0';
--- elsif (first_run_lock = '0') and (cts_addr_saved = '1') then
--- first_run_trg <= cts_trg;
--- first_run_addr <= cts_addr;
--- first_run_lock <= '1';
--- -- important: value saved by saveMachine but incremented by loadMachine
--- elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then
--- first_run_trg <= first_run_trg + x"1";
--- end if;
--- end if;
---end process FIRST_RUN_PROC;
-
--- gk 25.07.10
-SAVED_EVT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saved_events_ctr <= (others => '0');
- elsif (save_eod = '1') and (input_data_ctr < MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012
- saved_events_ctr <= saved_events_ctr + x"1";
- end if;
- end if;
-end process SAVED_EVT_CTR_PROC;
-
-
----- gk 20.07.10
---INC_DATA_CTR_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (rst_saved_ctr = '1') then
--- inc_data_ctr <= (others => '0');
--- elsif (sf_wr_en = '1') and (data_req = '1') then
--- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1";
--- end if;
--- end if;
---end process INC_DATA_CTR_proc;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Split FIFO
---THE_SPLIT_FIFO: fifo_32kx16x8_mb2
---port map(
--- -- Byte swapping for correct byte order on readout side of FIFO
--- Data(7 downto 0) => sf_data(15 downto 8),
--- Data(8) => '0',
--- Data(16 downto 9) => sf_data(7 downto 0),
--- Data(17) => save_eod,
--- WrClock => CLK,
--- RdClock => CLK,
--- WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en,
--- RdEn => sf_rd_en,
--- Reset => reset_split_fifo, --RESET, -- gk 06.11.2012
--- RPReset => reset_split_fifo, --RESET, -- gk 06.11.2012
--- AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead
--- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751
--- Q(7 downto 0) => pc_data,
--- Q(8) => load_eod,
--- WCNT => sf_wcnt,
--- RCNT => sf_rcnt,
--- Empty => sf_empty,
--- AlmostEmpty => open, --sf_aempty,
--- Full => sf_full,
--- AlmostFull => sf_afull
---);
-
-sf_aempty <= '0';
-
-reset_split_fifo <= '1' when (saveCurrentState = RESET_FIFO or RESET = '1') else '0';
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- gk 25.07.10
-EVENT_WAITING_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- event_waiting <= '0';
- elsif (loaded_events_ctr /= saved_events_ctr) then
- event_waiting <= '1';
- else
- event_waiting <= '0';
- end if;
- end if;
-end process EVENT_WAITING_PROC;
-
--- write signal for PC data
-pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or
- (pad_phase = '1') or
- ((load_sub = '1') and (sf_rd_en = '1')) or
- ((drop_sub = '1') and (sf_rd_en = '1')) or
- ((drop_event = '1') and (sf_rd_en = '1'))
- else '0';
-
-sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or
- --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or
- ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10
- ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10
- ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or
- ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') )
- else '0';
-
-ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') )
- else '0';
-
--- FIFO data delay process (also forces padding bytes to known value)
-THE_DATA_DELAY_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( pad_data = '1' ) then
- pc_data_q <= x"aa"; -- padding for 64bit
- -- gk 21.07.10
- -- set the error flag if a broken packet is sent
- elsif (drop_sub = '1') and (load_sub_ctr = x"3") then
- pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0);
- else
- pc_data_q <= pc_data;
- end if;
- end if;
-end process THE_DATA_DELAY_PROC;
-
--- Statemachine for reading the data payload from the SPLIT_FIFO and feeding
--- it into the packet constructor
-loadMachineProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- loadCurrentState <= LIDLE;
- rst_rem_ctr <= '0';
- rem_phase <= '0';
- calc_pad <= '0';
- data_phase <= '0';
- pad_phase <= '0';
- pc_sos <= '0';
- pc_eod <= '0';
- rst_regs <= '0';
- pad_data <= '0';
- load_sub <= '0'; -- gk 30.03.10
- drop_sub <= '0'; -- gk 25.07.10
- drop_event <= '0'; -- gk 25.07.10
- drop_small <= '0'; -- gk 25.07.10
- drop_large <= '0'; -- gk 25.07.10
- drop_headers <= '0'; -- gk 25.07.10
- inc_trg_ctr <= '0'; -- gk 26.07.10
- found_empty_evt <= '0'; -- gk 01.10.10
- else
- loadCurrentState <= loadNextState;
- rst_rem_ctr <= rst_rem_ctr_comb;
- rem_phase <= rem_phase_comb;
- calc_pad <= calc_pad_comb;
- data_phase <= data_phase_comb;
- pad_phase <= pad_phase_comb;
- pc_sos <= pc_sos_comb;
- pc_eod <= pc_eod_comb;
- rst_regs <= rst_regs_comb;
- pad_data <= pad_data_comb;
- load_sub <= load_sub_comb; -- gk 30.03.1
- drop_sub <= drop_sub_comb; -- gk 25.07.10
- drop_event <= drop_event_comb; -- gk 25.07.10
- drop_small <= drop_small_comb; -- gk 25.07.10
- drop_large <= drop_large_comb; -- gk 25.07.10
- drop_headers <= drop_headers_comb; -- gk 25.07.10
- inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10
- found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10
- end if;
- end if;
-end process loadMachineProc;
-
-loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed,
- PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN,
- MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr,
- first_run_addr, load_eod, event_waiting, MULT_EVT_ENABLE_IN, message_size, DATA_GBE_ENABLE_IN, first_event,
- prev_bank_select, bank_select)
-begin
- loadNextState <= LIDLE;
- rst_rem_ctr_comb <= '0';
- rem_phase_comb <= '0';
- calc_pad_comb <= '0';
- data_phase_comb <= '0';
- pad_phase_comb <= '0';
- pc_sos_comb <= '0';
- pc_eod_comb <= '0';
- rst_regs_comb <= '0';
- pad_data_comb <= '0';
- load_sub_comb <= '0'; -- gk 30.03.10
- drop_sub_comb <= '0'; -- gk 25.07.10
- drop_event_comb <= '0'; -- gk 25.07.10
- drop_small_comb <= '0'; -- gk 25.07.10
- drop_large_comb <= '0'; -- gk 25.07.10
- drop_headers_comb <= '0'; -- gk 25.07.10
- inc_trg_ctr_comb <= '0'; -- gk 26.07.10
- found_empty_evt_comb <= '0'; -- gk 01.10.10
- case loadCurrentState is
- when LIDLE =>
- state2 <= x"0";
- -- gk 23.07.10
- if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 -- and (PC_READY_IN = '1')
- loadNextState <= INIT;
- rst_rem_ctr_comb <= '1';
- rst_regs_comb <= '1';
- else
- loadNextState <= LIDLE;
- end if;
- when INIT =>
- state2 <= x"1";
- loadNextState <= REMOVE;
- rem_phase_comb <= '1';
- when REMOVE =>
- state2 <= x"2";
- if( remove_done = '1' ) then
- -- gk 06.10.10
- if (MULT_EVT_ENABLE_IN = '1') then
- if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then
- --loadNextState <= WAIT_TO_REMOVE;
- -- gk 07.12.10
- if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet
- loadNextState <= WAIT_PC;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
-
- else
- loadNextState <= WAIT_PC;
- end if;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
- inc_trg_ctr_comb <= '1';
- else
- loadNextState <= REMOVE;
- rem_phase_comb <= '1';
- end if;
- when WAIT_TO_REMOVE =>
- if (rem_ctr = x"a") then
- loadNextState <= DECIDE;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
- when DECIDE =>
--- if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then
--- loadNextState <= PAUSE_BEFORE_DROP1;
--- drop_large_comb <= '1';
--- elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10
--- loadNextState <= CALCA;
--- found_empty_evt_comb <= '1';
--- elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then
--- loadNextState <= PAUSE_BEFORE_DROP1;
--- drop_small_comb <= '1';
--- elsif (pc_trig_nr + x"1" /= first_run_trg) then
--- loadNextState <= PAUSE_BEFORE_DROP1;
--- drop_headers_comb <= '1';
--- elsif (endpoint_addr /= first_run_addr) then
--- loadNextState <= PAUSE_BEFORE_DROP1;
--- drop_headers_comb <= '1';
--- else
- loadNextState <= CALCA;
--- end if;
- calc_pad_comb <= '1';
- when CALCA =>
- state2 <= x"3";
- loadNextState <= CALCB;
- pc_sos_comb <= '1';
- when CALCB =>
- -- we need a branch in case of length "0"!!!!
- state2 <= x"4";
- loadNextState <= LOAD;
- data_phase_comb <= '1';
- when LOAD =>
- state2 <= x"5";
- if (load_eod = '1') then
- loadNextState <= LOAD_SUBSUB;
- else
- loadNextState <= LOAD;
- data_phase_comb <= '1';
- end if;
- -- gk 31.03.10
- when LOAD_SUBSUB =>
- state2 <= x"d";
- if( load_sub_done = '1' ) then
- if( padding_needed = '0' ) then
- loadNextState <= CALCC;
- else
- loadNextState <= PAD0;
- pad_phase_comb <= '1';
- end if;
- else
- loadNextState <= LOAD_SUBSUB;
- load_sub_comb <= '1';
- end if;
- when PAD0 =>
- state2 <= x"6";
- loadNextState <= PAD1;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD1 =>
- state2 <= x"7";
- loadNextState <= PAD2;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD2 =>
- state2 <= x"8";
- loadNextState <= PAD3;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD3 =>
- state2 <= x"9";
- loadNextState <= CALCC;
- pad_data_comb <= '1';
- when CALCC =>
- state2 <= x"a";
- if (MULT_EVT_ENABLE_IN = '1') then
- loadNextState <= LIDLE;
- else
- loadNextState <= CLOSE;
- end if;
- pc_eod_comb <= '1';
- when CLOSE =>
- state2 <= x"b";
- loadNextState <= WAIT_PC;
- --rst_regs_comb <= '1'; -- gk 07.10.10
- when WAIT_PC =>
- state2 <= x"c";
- if( PC_READY_IN = '1' ) then
- -- gk 06.10.10
- if (MULT_EVT_ENABLE_IN = '1') then
- loadNextState <= WAIT_TO_REMOVE;
- else
- loadNextState <= LIDLE;
- end if;
- else
- loadNextState <= WAIT_PC;
- end if;
- when PAUSE_BEFORE_DROP1 =>
- loadNextState <= PAUSE_BEFORE_DROP2;
- pc_sos_comb <= '1';
- when PAUSE_BEFORE_DROP2 =>
- loadNextState <= DROP;
- drop_event_comb <= '1';
- -- gk 23.07.10
- when DROP =>
- state2 <= x"e";
- -- when data is dropped the eod marker stands as its end
- if (load_eod = '1') then
- loadNextState <= DROP_SUBSUB;
- else
- loadNextState <= DROP;
- drop_event_comb <= '1';
- end if;
- -- gk 25.07.10
- when DROP_SUBSUB =>
- if (load_sub_done = '1') then
- if( padding_needed = '0' ) then
- loadNextState <= CALCC;
- else
- loadNextState <= PAD0;
- pad_phase_comb <= '1';
- end if;
- else
- loadNextState <= DROP_SUBSUB;
- drop_sub_comb <= '1';
- end if;
- when others =>
- state2 <= x"f";
- loadNextState <= LIDLE;
- end case;
-end process loadMachine;
-
--- gk 25.07.10
---INVALID_STATS_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- dropped_lr_events_ctr <= (others => '0');
--- dropped_sm_events_ctr <= (others => '0');
--- headers_invalid_ctr <= (others => '0');
--- dropped_ctr <= (others => '0');
--- invalid_hsize_ctr <= (others => '0');
--- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10
--- elsif (rst_regs = '1') then
--- invalid_hsize_lock <= '0';
--- elsif (drop_small = '1') then
--- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (drop_large = '1') then
--- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (drop_headers = '1') then
--- headers_invalid_ctr <= headers_invalid_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ??
--- invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
--- invalid_hsize_lock <= '1';
--- -- gk 01.10.10
--- elsif (found_empty_evt = '1') then
--- found_empty_evt_ctr <= found_empty_evt_ctr + x"1";
--- end if;
--- end if;
---end process INVALID_STATS_PROC;
-
--- gk 05.08.10
-INVALID_H_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- load_eod_q <= load_eod;
- read_size_q <= read_size;
- end if;
-end process INVALID_H_PROC;
-
--- gk 26.04.10
-READOUT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then
- readout_ctr <= READOUT_CTR_IN;
- readout_ctr_lock <= '0';
- elsif (pc_sos = '1') then
- readout_ctr <= readout_ctr + x"1";
- end if;
- end if;
-end process READOUT_CTR_PROC;
-
---******
--- SELECTION OF EVENT BUILDER
---******
-
--- gk 27.03.10
-bank_select_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- -- gk 29.03.10
- if( (RESET = '1') or (rst_regs = '1') ) then
- bank_select <= "0000";
- -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
- bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
- end if;
- end if;
-end process bank_select_proc;
-
--- gk 07.12.10
-first_event_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = WAIT_PC) then
- first_event <= '1';
- elsif (remove_done = '1') then
- first_event <= '0';
- end if;
- end if;
-end process first_event_proc;
-
--- gk 07.12.10
-prev_bank_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = WAIT_PC) then
- prev_bank_select <= "0000";
- elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then
- prev_bank_select <= bank_select;
- end if;
- end if;
-end process prev_bank_proc;
-
-
--- gk 29.03.10
-start_config_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then
- start_config <= '0';
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1') ) then -- gk 01.06.10
- start_config <= '1';
- end if;
- end if;
-end process start_config_proc;
-
-
---******
--- LOAD SUBSUBEVENT
---******
-
--- gk 30.03.10
-load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') )
- else '0';
-
--- gk 30.03.10
-LOAD_SUB_CTR_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
- load_sub_ctr <= (others => '0');
- elsif( (load_sub_ctr_comb = '1') ) then
- load_sub_ctr <= load_sub_ctr + 1;
- end if;
- end if;
-end process LOAD_SUB_CTR_PROC;
-
--- gk 30.03.10
--- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or
--- ((load_sub_ctr = x"4") and (drop_sub = '1'))
--- else '0';
-load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0';
-
--- gk 30.03.10
-LOAD_SUB_DONE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
- load_sub_done <= '0';
- else
- load_sub_done <= load_sub_done_comb;
- end if;
- end if;
-end process LOAD_SUB_DONE_PROC;
-
---******
--- EXTRACT EVENT HEADERS FROM SPLITFIFO
---******
-
--- Counter for stripping the unneeded parts of the data stream, and saving the important parts
-THE_REMOVE_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
- rem_ctr <= (others => '0');
- elsif( (ce_rem_ctr = '1') ) then
- rem_ctr <= rem_ctr + 1;
- end if;
- end if;
-end process THE_REMOVE_CTR;
-
-remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address
-
-THE_REM_DONE_SYNC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
- remove_done <= '0';
- else
- remove_done <= remove_done_comb;
- end if;
- end if;
-end process THE_REM_DONE_SYNC;
-
--- gk 26.04.10
-TRIG_RANDOM_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (rst_regs = '1')) then
- trig_random <= (others => '0');
- elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then
- trig_random <= pc_data;
- end if;
- end if;
-end process TRIG_RANDOM_PROC;
-
--- extract the trigger number from splitfifo data
-THE_TRG_NR_PROC: process( CLK )
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- pc_trig_nr <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10
- pc_trig_nr(7 downto 0) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10
- pc_trig_nr(15 downto 8) <= pc_data;
- end if;
- end if;
-end process THE_TRG_NR_PROC;
-
--- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,
--- and in case of padding needed increase it accordingly
-THE_SUB_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- pc_sub_size <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
- pc_sub_size(9 downto 2) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
- pc_sub_size(17 downto 10) <= pc_data;
- -- gk 20.07.10
- -- gk 30.03.10 bug fixed in the way that is written below
- -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save
- elsif( (calc_pad = '1') and (padding_needed = '1') ) then
- pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!!
- elsif( (calc_pad = '1') and (padding_needed = '0') ) then
- pc_sub_size <= pc_sub_size + x"8";
- end if;
- end if;
-end process THE_SUB_SIZE_PROC;
-
--- gk 06.10.10
-MESSAGE_SIZE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
--- if (RESET = '1') then
--- message_size <= (others => '0');
--- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
--- message_size <= (others => '0');
--- elsif (pc_sos = '1') then
--- message_size <= message_size + pc_sub_size;
--- end if;
- if (RESET = '1') then
- message_size <= x"0000_0028";
- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
- message_size <= x"0000_0028";
- elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then
- message_size <= x"0000_0028";
- elsif (pc_sos = '1') then
- message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers
- end if;
- end if;
-end process MESSAGE_SIZE_PROC;
-
-
--- gk 25.07.10
-ENDP_ADDRESS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (rst_regs = '1') then
- endpoint_addr <= (others => '0');
- endp_addr_lock <= '0';
- elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then
- endpoint_addr(7 downto 0) <= pc_data;
- endp_addr_lock <= '1';
- elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then
- endpoint_addr(15 downto 8) <= pc_data;
- endp_addr_lock <= '0';
- end if;
- end if;
-end process ENDP_ADDRESS_PROC;
-
-
-
--- check for padding
-THE_PADDING_NEEDED_PROC: process( CLK )
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- padding_needed <= '0';
- elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then
- padding_needed <= '1';
- elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then
- padding_needed <= '0';
- end if;
- end if;
-end process THE_PADDING_NEEDED_PROC;
-
--- number of bytes to read from split fifo
-THE_READ_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then
- read_size <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
- read_size(9 downto 2) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
- read_size(17 downto 10) <= pc_data;
- elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then
- read_size <= read_size - 1;
- -- gk 25.07.10
- elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then
- read_size <= read_size - 1;
- end if;
- end if;
-end process THE_READ_SIZE_PROC;
-
-read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2"
-
---******
--- EVENTS COUNTERS
---******
-
--- gk 25.07.10
-LOADED_EVT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- loaded_events_ctr <= (others => '0');
- elsif (remove_done = '1') then
- loaded_events_ctr <= loaded_events_ctr + x"1";
- end if;
- end if;
-end process LOADED_EVT_CTR_PROC;
-
----- gk 25.07.10
---CONSTR_EVENTS_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- constr_events_ctr <= (others => '0');
--- elsif (pc_eod = '1') then
--- constr_events_ctr <= constr_events_ctr + x"1";
--- end if;
--- end if;
---end process CONSTR_EVENTS_CTR_PROC;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Debug signals
---debug(0) <= sf_full;
---debug(1) <= sf_empty;
---debug(2) <= sf_afull;
---debug(3) <= sf_aempty;
---
---debug(7 downto 4) <= state2;
---
---debug(11 downto 8) <= state;
---
---dbg_bs_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(15 downto 12) <= (others => '0');
--- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
--- debug(15 downto 12) <= bank_select;
--- end if;
--- end if;
---end process dbg_bs_proc;
---
---debug(16) <= config_done;
---debug(17) <= '0'; --remove_done;
---debug(18) <= read_done;
---debug(19) <= padding_needed;
---
---debug(20) <= load_sub_done;
---
---dbg_cts_inf_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(39 downto 32) <= (others => '0');
--- elsif ( save_addr = '1' ) then
--- debug(39 downto 32) <= CTS_INFORMATION_IN;
--- end if;
--- end if;
---end process dbg_cts_inf_proc;
---
---debug(47 downto 40) <= (others => '0');
---
---
---debug(63 downto 48) <= actual_message_size(15 downto 0);
---
---dbg_pc_sub_size_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(81 downto 64) <= (others => '0');
--- elsif (loadCurrentState = DECIDE) then
--- debug(81 downto 64) <= pc_sub_size;
--- end if;
--- end if;
---end process dbg_pc_sub_size_proc;
---
---dbg_empty_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (rst_regs = '1') then
--- debug(84 downto 82) <= (others => '0');
--- elsif (read_size = 2) then
--- debug(82) <= sf_empty;
--- elsif (read_size = 1) then
--- debug(83) <= sf_empty;
--- elsif (read_size = 0) then
--- debug(84) <= sf_empty;
--- end if;
--- end if;
---end process dbg_empty_proc;
---
---debug(95 downto 85) <= (others => '0');
---
---dbg_inc_ctr_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(127 downto 96) <= (others => '1');
--- elsif (saveCurrentState = SCLOSE) then
--- debug(127 downto 96) <= inc_data_ctr;
--- end if;
--- end if;
---end process dbg_inc_ctr_proc;
---
---debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0);
---debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0);
---
---debug(175 downto 160) <= headers_invalid_ctr(15 downto 0);
---debug(191 downto 176) <= (others => '0');
---
---dbg_cts_q_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- cts_len_q <= (others => '0');
--- cts_rnd_q <= (others => '0');
--- cts_trg_q <= (others => '0');
--- cts_addr_q <= (others => '0');
--- elsif (cts_len_saved = '1') then
--- cts_len_q <= cts_len(16 downto 1);
--- cts_addr_q <= cts_addr;
--- cts_rnd_q <= cts_rnd;
--- cts_trg_q <= cts_trg;
--- end if;
--- end if;
---end process dbg_cts_q_proc;
---
---debug(207 downto 192) <= cts_trg_q;
---debug(223 downto 208) <= cts_rnd_q;
---debug(239 downto 224) <= cts_addr_q;
---debug(255 downto 240) <= cts_len_q;
---debug(271 downto 256) <= first_run_trg;
---debug(287 downto 272) <= first_run_addr;
---
---debug(303 downto 288) <= saved_events_ctr;
---debug(319 downto 304) <= loaded_events_ctr;
---
---debug(335 downto 320) <= constr_events_ctr(15 downto 0);
---debug(351 downto 336) <= dropped_ctr(15 downto 0);
---
---debug(367 downto 352) <= invalid_hsize_ctr;
---debug(383 downto 368) <= (others => '0');
---
---MONITOR_OUT(31 downto 0) <= constr_events_ctr;
---MONITOR_OUT(63 downto 32) <= dropped_ctr;
---MONITOR_OUT(95 downto 64) <= headers_invalid_ctr;
---MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr;
---MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
---MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000";
---MONITOR_OUT(191 downto 164) <= (others => '0');
---MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10
-
--- Outputs
-FEE_READ_OUT <= fee_read;
-CTS_ERROR_PATTERN_OUT <= cts_error_pattern;
-CTS_DATA_OUT <= cts_data;
-CTS_DATAREADY_OUT <= cts_dataready;
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
-CTS_LENGTH_OUT <= cts_length;
-
---PC_SOS_OUT <= pc_sos;
---PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1'))
--- or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1'))
--- -- gk 07.12.10
--- or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1'))
--- else '0'; -- gk 07.10.10
---PC_DATA_OUT <= pc_data_q;
---PC_WR_EN_OUT <= pc_wr_en_qq;
-
-PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random;
-
---PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size;
---PC_PADDING_OUT <= padding_needed;
--- gk 07.10.10
---PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0';
-
-DEBUG_OUT <= debug;
-
--- SIMPLE SENDER STUFF
-
-
-
-PC_SOS_OUT <= '0'; --'1' when gen_current_state = WAIT_FOR_PC and PC_READY_IN = '1' else '0';
-PC_EOS_OUT <= '0';
-PC_EOD_OUT <= '0'; --'1' when gen_current_state = GENERATE_DATA and gen_data_ctr = SCTRL_DUMMY_SIZE_IN else '0';
-PC_DATA_OUT <= gen_data_ctr(7 downto 0);
-PC_WR_EN_OUT <= '0'; --'1' when gen_current_state = GENERATE_DATA else '0';
-PC_SUB_SIZE_OUT <= x"0000" & SCTRL_DUMMY_SIZE_IN + x"1";
-PC_PADDING_OUT <= '0';
-
-GEN_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- gen_current_state <= IDLE;
- else
- gen_current_state <= gen_next_state;
- end if;
- end if;
-end process GEN_MACHINE_PROC;
-
-GEN_MACHINE : process(gen_current_state, gen_data_ctr, event_waiting, DATA_GBE_ENABLE_IN, SCTRL_DUMMY_SIZE_IN, PC_READY_IN)
-begin
- case (gen_current_state) is
-
- when IDLE =>
- if (event_waiting = '1' and DATA_GBE_ENABLE_IN = '1') then
- gen_next_state <= WAIT_FOR_PC;
- else
- gen_next_state <= IDLE;
- end if;
-
- when WAIT_FOR_PC =>
- if (PC_READY_IN = '1') then
- gen_next_state <= GENERATE_DATA;
- else
- gen_next_state <= WAIT_FOR_PC;
- end if;
-
- when GENERATE_DATA =>
- if (gen_data_ctr = SCTRL_DUMMY_SIZE_IN) then
- gen_next_state <= CLEANUP;
- else
- gen_next_state <= GENERATE_DATA;
- end if;
-
- when CLEANUP =>
- gen_next_state <= IDLE;
-
- end case;
-end process GEN_MACHINE;
-
-GEN_DATA_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (gen_current_state = IDLE) then
- gen_data_ctr <= (others => '0');
- elsif (gen_current_state = GENERATE_DATA) then
- gen_data_ctr <= gen_data_ctr + x"1";
- end if;
- end if;
-end process GEN_DATA_CTR_PROC;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;
-
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-
-entity trb_net16_gbe_ipu_interface is
-port (
- CLK_IPU : in std_logic;
- CLK_GBE : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_SUBEVENT_SIZE_IN : in std_logic_vector(15 downto 0);
- MAX_QUEUE_SIZE_IN : in std_logic_vector(15 downto 0);
- MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- MAX_SINGLE_SUB_SIZE_IN : in std_logic_vector(15 downto 0);
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- -- PacketConstructor interface
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic;
- PC_EOQ_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0);
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
- );
-end entity trb_net16_gbe_ipu_interface;
-
-architecture RTL of trb_net16_gbe_ipu_interface is
-
-attribute syn_encoding : string;
-
-type saveStates is (IDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, CLOSE, FINISH_4_WORDS, CLEANUP);
-signal save_current_state, save_next_state : saveStates;
-attribute syn_encoding of save_current_state : signal is "onehot";
-
-type loadStates is (IDLE, WAIT_FOR_SUBS, REMOVE, WAIT_ONE, WAIT_TWO, DECIDE, PREPARE_TO_LOAD_SUB, WAIT_FOR_LOAD, LOAD, CLOSE_PACKET, CLOSE_SUB, CLOSE_QUEUE, CLOSE_QUEUE_IMMEDIATELY);
-signal load_current_state, load_next_state : loadStates;
-attribute syn_encoding of load_current_state : signal is "onehot";
-
-signal sf_data : std_Logic_vector(15 downto 0);
-signal save_eod, sf_wr_en, sf_rd_en, sf_reset, sf_empty, sf_full, sf_afull, sf_eos : std_logic;
-signal sf_q, pc_data : std_logic_vector(7 downto 0);
-
-signal cts_rnd, cts_trg : std_logic_vector(15 downto 0);
-signal save_ctr : std_logic_vector(15 downto 0);
-
-signal saved_events_ctr, loaded_events_ctr, saved_events_ctr_gbe : std_logic_vector(7 downto 0);
-signal loaded_bytes_ctr : std_Logic_vector(15 downto 0);
-
-signal trigger_random : std_logic_vector(7 downto 0);
-signal trigger_number : std_logic_vector(15 downto 0);
-signal subevent_size : std_logic_vector(17 downto 0);
-signal trigger_type : std_logic_vector(3 downto 0);
-
-signal bank_select : std_logic_vector(3 downto 0);
-signal readout_ctr : std_logic_vector(23 downto 0) := x"000000";
-signal pc_ready_q : std_logic;
-signal sf_afull_q : std_logic;
-signal sf_aempty : std_logic;
-signal rec_state, load_state : std_logic_vector(3 downto 0);
-signal queue_size : std_logic_vector(17 downto 0);
-signal number_of_subs : std_logic_vector(15 downto 0);
-signal size_check_ctr : integer range 0 to 7;
-signal sf_data_q, sf_data_qq, sf_data_qqq, sf_data_qqqq, sf_data_qqqqq : std_logic_vector(15 downto 0);
-signal sf_wr_q, sf_wr_lock : std_logic;
-signal save_eod_q, save_eod_qq, save_eod_qqq, save_eod_qqqq, save_eod_qqqqq : std_logic;
-signal too_large_dropped : std_logic_vector(31 downto 0);
-signal previous_ttype, previous_bank : std_logic_vector(3 downto 0);
-
-begin
-
---*********
--- RECEIVING PART
---*********
-
-SAVE_MACHINE_PROC : process(RESET, CLK_IPU)
-begin
- if RESET = '1' then
- save_current_state <= IDLE;
- elsif rising_edge(CLK_IPU) then
- save_current_state <= save_next_state;
- end if;
-end process SAVE_MACHINE_PROC;
-
-SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, size_check_ctr)
-begin
- case (save_current_state) is
-
- when IDLE =>
- rec_state <= x"1";
- if (CTS_START_READOUT_IN = '1') then
- save_next_state <= SAVE_EVT_ADDR;
- else
- save_next_state <= IDLE;
- end if;
-
- when SAVE_EVT_ADDR =>
- rec_state <= x"2";
- save_next_state <= WAIT_FOR_DATA;
-
- when WAIT_FOR_DATA =>
- rec_state <= x"3";
- if (FEE_BUSY_IN = '1') then
- save_next_state <= SAVE_DATA;
- else
- save_next_state <= WAIT_FOR_DATA;
- end if;
-
- when SAVE_DATA =>
- rec_state <= x"4";
- if (FEE_BUSY_IN = '0') then
- save_next_state <= TERMINATE;
- else
- save_next_state <= SAVE_DATA;
- end if;
-
- when TERMINATE =>
- rec_state <= x"5";
- if (CTS_READ_IN = '1') then
- save_next_state <= CLOSE;
- else
- save_next_state <= TERMINATE;
- end if;
-
- when CLOSE =>
- rec_state <= x"6";
- if (CTS_START_READOUT_IN = '0') then
- save_next_state <= ADD_SUBSUB1;
- else
- save_next_state <= CLOSE;
- end if;
-
- when ADD_SUBSUB1 =>
- rec_state <= x"7";
- save_next_state <= ADD_SUBSUB2;
-
- when ADD_SUBSUB2 =>
- rec_state <= x"8";
- save_next_state <= ADD_SUBSUB3;
-
- when ADD_SUBSUB3 =>
- rec_state <= x"9";
- save_next_state <= ADD_SUBSUB4;
-
- when ADD_SUBSUB4 =>
- rec_state <= x"a";
- save_next_state <= FINISH_4_WORDS;
-
- when FINISH_4_WORDS =>
- rec_state <= x"b";
- if (size_check_ctr = 1) then
- save_next_state <= CLEANUP;
- else
- save_next_state <= FINISH_4_WORDS;
- end if;
-
- when CLEANUP =>
- rec_state <= x"c";
- save_next_state <= IDLE;
-
- end case;
-end process SAVE_MACHINE;
-
-SF_WR_EN_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- sf_afull_q <= sf_afull;
-
- if (sf_afull_q = '0' and save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and FEE_BUSY_IN = '1') then
- sf_wr_en <= '1';
- elsif (save_current_state = SAVE_EVT_ADDR) then
- sf_wr_en <= '1';
- elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then
- sf_wr_en <= '1';
- elsif (save_current_state = FINISH_4_WORDS) then
- sf_wr_en <= '1';
- else
- sf_wr_en <= '0';
- end if;
- end if;
-end process SF_WR_EN_PROC;
-
-SF_DATA_EOD_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- case (save_current_state) is
-
- when SAVE_EVT_ADDR =>
- sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0);
- sf_data(7 downto 4) <= CTS_READOUT_TYPE_IN;
- sf_data(15 downto 8) <= x"ab";
- save_eod <= '0';
-
- when SAVE_DATA =>
- sf_data <= FEE_DATA_IN;
- save_eod <= '0';
-
- when ADD_SUBSUB1 =>
- sf_data <= x"0001";
- save_eod <= '0';
-
- when ADD_SUBSUB2 =>
- sf_data <= x"5555";
- save_eod <= '0';
-
- when ADD_SUBSUB3 =>
- sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
- save_eod <= '1';
-
- when ADD_SUBSUB4 =>
- sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
- save_eod <= '0';
-
- when others => sf_data <= (others => '0'); save_eod <= '0';
-
- end case;
- end if;
-end process SF_DATA_EOD_PROC;
-
-process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (sf_wr_en = '1') then
- sf_data_q <= sf_data;
- sf_data_qq <= sf_data_q;
- sf_data_qqq <= sf_data_qq;
- sf_data_qqqq <= sf_data_qqq;
- sf_data_qqqqq <= sf_data_qqqq;
-
- save_eod_q <= save_eod;
- save_eod_qq <= save_eod_q;
- save_eod_qqq <= save_eod_qq;
- save_eod_qqqq <= save_eod_qqq;
- save_eod_qqqqq <= save_eod_qqqq;
- else
- sf_data_q <= sf_data_q;
- sf_data_qq <= sf_data_qq;
- sf_data_qqq <= sf_data_qqq;
- sf_data_qqqq <= sf_data_qqqq;
- sf_data_qqqqq <= sf_data_qqqqq;
-
- save_eod_q <= save_eod_q;
- save_eod_qq <= save_eod_qq;
- save_eod_qqq <= save_eod_qqq;
- save_eod_qqqq <= save_eod_qqqq;
- save_eod_qqqqq <= save_eod_qqqq;
- end if;
-
-sf_wr_q <= sf_wr_en and not sf_wr_lock;
-
- end if;
-end process;
-
-process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (save_current_state = IDLE) then
- size_check_ctr <= 0;
- elsif (save_current_state = SAVE_DATA and sf_wr_en = '1' and size_check_ctr /= 4) then
- size_check_ctr <= size_check_ctr + 1;
- elsif (save_current_state = FINISH_4_WORDS and size_check_ctr /= 0) then
- size_check_ctr <= size_check_ctr - 1;
- else
- size_check_ctr <= size_check_ctr;
- end if;
-
- if (save_current_state = IDLE) then
- sf_wr_lock <= '1';
- elsif (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") < ("00" & MAX_SUBEVENT_SIZE_IN)) then -- condition to ALLOW an event to be passed forward
- sf_wr_lock <= '0';
- else
- sf_wr_lock <= sf_wr_lock;
- end if;
-
- end if;
-end process;
-
-process(RESET, CLK_IPU)
-begin
- if (RESET = '1') then
- too_large_dropped <= (others => '0');
- elsif rising_edge(CLK_IPU) then
- if (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") >= ("00" & MAX_SUBEVENT_SIZE_IN)) then
- too_large_dropped <= too_large_dropped + x"1";
- else
- too_large_dropped <= too_large_dropped;
- end if;
- end if;
-end process;
-
-
-SAVED_EVENTS_CTR_PROC : process(RESET, CLK_IPU)
-begin
- if (RESET = '1') then
- saved_events_ctr <= (others => '0');
- elsif rising_edge(CLK_IPU) then
- if (save_current_state = ADD_SUBSUB4 and sf_wr_lock = '0') then
- saved_events_ctr <= saved_events_ctr + x"1";
- else
- saved_events_ctr <= saved_events_ctr;
- end if;
- end if;
-end process SAVED_EVENTS_CTR_PROC;
-
-CTS_DATAREADY_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then
- CTS_DATAREADY_OUT <= '1';
- elsif (save_current_state = TERMINATE) then
- CTS_DATAREADY_OUT <= '1';
- else
- CTS_DATAREADY_OUT <= '0';
- end if;
- end if;
-end process CTS_DATAREADY_PROC;
-
-CTS_READOUT_FINISHED_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (save_current_state = CLOSE) then
- CTS_READOUT_FINISHED_OUT <= '1';
- else
- CTS_READOUT_FINISHED_OUT <= '0';
- end if;
- end if;
-end process CTS_READOUT_FINISHED_PROC;
-
-CTS_LENGTH_OUT <= (others => '0');
-CTS_ERROR_PATTERN_OUT <= (others => '0');
-
-CTS_DATA_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- CTS_DATA_OUT <= "0001" & cts_rnd(11 downto 0) & cts_trg;
- end if;
-end process CTS_DATA_PROC;
-
-CTS_RND_TRG_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (save_current_state = SAVE_DATA and save_ctr = x"0000") then
- cts_rnd <= sf_data;
- cts_trg <= cts_trg;
- elsif (save_current_state = SAVE_DATA and save_ctr = x"0001") then
- cts_rnd <= cts_rnd;
- cts_trg <= sf_data;
- else
- cts_rnd <= cts_rnd;
- cts_trg <= cts_trg;
- end if;
- end if;
-end process CTS_RND_TRG_PROC;
-
-SAVE_CTR_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (save_current_state = IDLE) then
- save_ctr <= (others => '0');
- elsif (save_current_state = SAVE_DATA and sf_wr_en = '1') then
- save_ctr <= save_ctr + x"1";
- else
- save_ctr <= save_ctr;
- end if;
- end if;
-end process SAVE_CTR_PROC;
-
-FEE_READ_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (sf_afull = '0') then
- if (save_current_state = IDLE or save_current_state = SAVE_EVT_ADDR or save_current_state = WAIT_FOR_DATA or save_current_state = SAVE_DATA) then
- FEE_READ_OUT <= '1';
- else
- FEE_READ_OUT <= '0';
- end if;
- else
- FEE_READ_OUT <= '0';
- end if;
- end if;
-end process FEE_READ_PROC;
-
-
-THE_SPLIT_FIFO: fifo_32kx16x8_mb2 --fifo_16kx18x9
-port map(
- -- Byte swapping for correct byte order on readout side of FIFO
- Data(7 downto 0) => sf_data_qqqqq(15 downto 8),
- Data(8) => '0',
- Data(16 downto 9) => sf_data_qqqqq(7 downto 0),
- Data(17) => save_eod_qqqqq,
- WrClock => CLK_IPU,
- RdClock => CLK_GBE,
- WrEn => sf_wr_q, -- sf_wr_en
- RdEn => sf_rd_en,
- Reset => sf_reset,
- RPReset => sf_reset,
- AmEmptyThresh => b"0000_0000_0000_0010", --b"0000_0000_0000_0010", -- one byte ahead
- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 -- b"001_0011_1000_1000"
- Q(7 downto 0) => sf_q,
- Q(8) => sf_eos,
- --WCNT => open,
- --RCNT => open,
- Empty => sf_empty,
- AlmostEmpty => sf_aempty,
- Full => sf_full, -- WARNING, JUST FOR DEBUG
- AlmostFull => sf_afull
-);
-
-sf_reset <= RESET;
-
---*********
--- LOADING PART
---*********
-
-PC_DATA_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- pc_data <= sf_q;
- end if;
-end process PC_DATA_PROC;
-
-LOAD_MACHINE_PROC : process(RESET, CLK_GBE)
-begin
- if RESET = '1' then
- load_current_state <= IDLE;
- elsif rising_edge(CLK_GBE) then
- load_current_state <= load_next_state;
- end if;
-end process LOAD_MACHINE_PROC;
-
-LOAD_MACHINE : process(load_current_state, saved_events_ctr_gbe, loaded_events_ctr, loaded_bytes_ctr, PC_READY_IN, sf_eos, queue_size, number_of_subs,
- subevent_size, MAX_QUEUE_SIZE_IN, MAX_SUBS_IN_QUEUE_IN, MAX_SINGLE_SUB_SIZE_IN, previous_bank, previous_ttype, trigger_type,
- bank_select, MULT_EVT_ENABLE_IN
-)
-begin
- case (load_current_state) is
-
- when IDLE =>
- load_state <= x"1";
- load_next_state <= WAIT_FOR_SUBS;
-
- when WAIT_FOR_SUBS =>
- load_state <= x"2";
- if (saved_events_ctr_gbe /= loaded_events_ctr) then
- load_next_state <= REMOVE;
- else
- load_next_state <= WAIT_FOR_SUBS;
- end if;
-
- when REMOVE =>
- load_state <= x"3";
- if (loaded_bytes_ctr = x"0008") then
- load_next_state <= WAIT_ONE;
- else
- load_next_state <= REMOVE;
- end if;
-
- when WAIT_ONE =>
- load_state <= x"4";
- load_next_state <= WAIT_TWO;
-
- when WAIT_TWO =>
- load_state <= x"4";
- load_next_state <= DECIDE;
-
- --TODO: all queue split conditions here and also in the size process
- when DECIDE =>
- load_state <= x"5";
- if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then -- max udp packet exceeded
- load_next_state <= CLOSE_QUEUE;
- elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then
- load_next_state <= CLOSE_QUEUE;
- elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then
- load_next_state <= CLOSE_QUEUE;
- elsif (trigger_type /= previous_ttype and number_of_subs /= x"0000") then
- load_next_state <= CLOSE_QUEUE;
- elsif (bank_select /= previous_bank and number_of_subs /= x"0000") then
- load_next_state <= CLOSE_QUEUE;
- else
- load_next_state <= PREPARE_TO_LOAD_SUB;
- end if;
-
- when PREPARE_TO_LOAD_SUB =>
- load_state <= x"6";
- load_next_state <= WAIT_FOR_LOAD;
-
- when WAIT_FOR_LOAD =>
- load_state <= x"7";
- if (PC_READY_IN = '1') then
- load_next_state <= LOAD;
- else
- load_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD =>
- load_state <= x"8";
- if (sf_eos = '1') then
- load_next_state <= CLOSE_SUB;
- else
- load_next_state <= LOAD;
- end if;
-
- when CLOSE_SUB =>
- load_state <= x"9";
- if (subevent_size > ("00" & MAX_SINGLE_SUB_SIZE_IN) and queue_size = (subevent_size + x"10" + x"8" + x"4")) then
- load_next_state <= CLOSE_QUEUE_IMMEDIATELY;
- else
- load_next_state <= WAIT_FOR_SUBS;
- end if;
-
- when CLOSE_QUEUE =>
- load_state <= x"a";
- load_next_state <= PREPARE_TO_LOAD_SUB;
-
- when CLOSE_QUEUE_IMMEDIATELY =>
- load_state <= x"b";
- load_next_state <= WAIT_FOR_SUBS;
-
-
- when others => load_next_state <= IDLE;
-
- end case;
-end process LOAD_MACHINE;
-
-saved_ctr_sync : signal_sync
-generic map(
- WIDTH => 8,
- DEPTH => 2
-)
-port map(
- RESET => RESET,
- CLK0 => CLK_GBE,
- CLK1 => CLK_GBE,
- D_IN => saved_events_ctr,
- D_OUT => saved_events_ctr_gbe
-);
-
-
---TODO: all queue split conditions here
--- the queue size counter used only for closing current queue
--- sums up all subevent sizes with their headers and stuff
-process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- queue_size <= (others => '0');
- elsif (load_current_state = CLOSE_QUEUE_IMMEDIATELY) then
- queue_size <= (others => '0');
- elsif (load_current_state = WAIT_TWO) then
- queue_size <= queue_size + subevent_size + x"10" + x"8" + x"4";
- elsif (load_current_state = DECIDE) then
- if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then
- queue_size <= subevent_size + x"10" + x"8" + x"4";
- elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then
- queue_size <= subevent_size + x"10" + x"8" + x"4";
- elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then
- queue_size <= subevent_size + x"10" + x"8" + x"4";
- elsif (trigger_type /= previous_ttype and number_of_subs /= x"0000") then
- queue_size <= subevent_size + x"10" + x"8" + x"4";
- elsif (bank_select /= previous_bank and number_of_subs /= x"0000") then
- queue_size <= subevent_size + x"10" + x"8" + x"4";
- else
- queue_size <= queue_size;
- end if;
- else
- queue_size <= queue_size;
- end if;
- end if;
-end process;
-
-process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE or load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY) then
- number_of_subs <= (others => '0');
- elsif (load_current_state = PREPARE_TO_LOAD_SUB) then
- number_of_subs <= number_of_subs + x"1";
- else
- number_of_subs <= number_of_subs;
- end if;
- end if;
-end process;
-
-
-SF_RD_EN_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (PC_READY_IN = '1') then
- if (load_current_state = REMOVE) then
- sf_rd_en <= '1';
- elsif (load_current_state = LOAD) then
- sf_rd_en <= '1';
- else
- sf_rd_en <= '0';
- end if;
- else
- sf_rd_en <= '0';
- end if;
- end if;
-end process SF_RD_EN_PROC;
-
---*****
--- information extraction
-
-process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- previous_bank <= x"0";
- previous_ttype <= x"0";
- elsif (load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY or load_current_state = CLOSE_SUB) then
- previous_bank <= bank_select;
- previous_ttype <= trigger_type;
- else
- previous_bank <= previous_bank;
- previous_ttype <= previous_ttype;
- end if;
- end if;
-end process;
-
-TRIGGER_RANDOM_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- trigger_random <= (others => '0');
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0005") then
- trigger_random <= pc_data;
- else
- trigger_random <= trigger_random;
- end if;
- end if;
-end process TRIGGER_RANDOM_PROC;
-
-TRIGGER_NUMBER_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- trigger_number <= (others => '0');
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0007") then
- trigger_number(7 downto 0) <= pc_data;
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0006") then
- trigger_number(15 downto 8) <= pc_data;
- else
- trigger_number <= trigger_number;
- end if;
- end if;
-end process TRIGGER_NUMBER_PROC;
-
-SUBEVENT_SIZE_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- subevent_size <= (others => '0');
- elsif (load_current_state = WAIT_ONE and sf_rd_en = '1' and loaded_bytes_ctr = x"0009") then
- subevent_size(9 downto 2) <= pc_data;
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0008") then
- subevent_size(17 downto 10) <= pc_data;
- else
- subevent_size <= subevent_size;
- end if;
- end if;
-end process SUBEVENT_SIZE_PROC;
-
-TRIGGER_TYPE_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- trigger_type <= x"0";
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then
- trigger_type <= pc_data(7 downto 4);
- else
- trigger_type <= trigger_type;
- end if;
- end if;
-end process TRIGGER_TYPE_PROC;
-
--- end of extraction
---*****
-
---*****
--- counters
-
-LOADED_EVENTS_CTR_PROC : process(RESET, CLK_GBE)
-begin
- if (RESET = '1') then
- loaded_events_ctr <= (others => '0');
- elsif rising_edge(CLK_GBE) then
- if (load_current_state = CLOSE_SUB) then
- loaded_events_ctr <= loaded_events_ctr + x"1";
- else
- loaded_events_ctr <= loaded_events_ctr;
- end if;
- end if;
-end process LOADED_EVENTS_CTR_PROC;
-
-LOADED_BYTES_CTR_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = WAIT_FOR_SUBS) then
- loaded_bytes_ctr <= (others => '0');
- elsif (sf_rd_en = '1') then
- if (load_current_state = REMOVE) then
- loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
- else
- loaded_bytes_ctr <= loaded_bytes_ctr;
- end if;
- else
- loaded_bytes_ctr <= loaded_bytes_ctr;
- end if;
- end if;
-end process LOADED_BYTES_CTR_PROC;
-
-READOUT_CTR_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (READOUT_CTR_VALID_IN = '1') then
- readout_ctr <= READOUT_CTR_IN;
- elsif (load_current_state = DECIDE) then
- readout_ctr <= readout_ctr + x"1";
- else
- readout_ctr <= readout_ctr;
- end if;
- end if;
-end process READOUT_CTR_PROC;
-
--- end of counters
---*****
-
---*****
--- event builder selection
-
-
-BANK_SELECT_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- bank_select <= x"0";
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then
- bank_select <= pc_data(3 downto 0);
- else
- bank_select <= bank_select;
- end if;
- end if;
-end process BANK_SELECT_PROC;
-
-BANK_SELECT_OUT <= bank_select;
-
-START_CONFIG_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then
- START_CONFIG_OUT <= '1';
- elsif (CONFIG_DONE_IN = '1') then
- START_CONFIG_OUT <= '0';
- else
- START_CONFIG_OUT <= '0';
- end if;
- end if;
-end process START_CONFIG_PROC;
-
--- end of event builder selection
---*****
-
-
-PC_WR_EN_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- pc_ready_q <= PC_READY_IN;
- if (pc_ready_q = '1') then
- if (load_current_state = LOAD) then
- PC_WR_EN_OUT <= '1';
- else
- PC_WR_EN_OUT <= '0';
- end if;
- else
- PC_WR_EN_OUT <= '0';
- end if;
- end if;
-end process PC_WR_EN_PROC;
-
-PC_SOS_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = PREPARE_TO_LOAD_SUB) then
- PC_SOS_OUT <= '1';
- else
- PC_SOS_OUT <= '0';
- end if;
- end if;
-end process PC_SOS_PROC;
-
-PC_EOD_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- PC_EOS_OUT <= sf_eos;
- end if;
-end process PC_EOD_PROC;
-
-PC_EOQ_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY) then
- PC_EOQ_OUT <= '1';
- else
- PC_EOQ_OUT <= '0';
- end if;
- end if;
-end process PC_EOQ_PROC;
-
---*******
--- outputs
-
-PC_DATA_OUT <= pc_data;
-
-PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & subevent_size;
-
-PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & trigger_number & trigger_random;
-
-PC_TRIGGER_TYPE_OUT <= trigger_type;
-
-
-process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- DEBUG_OUT(3 downto 0) <= rec_state;
- DEBUG_OUT(7 downto 4) <= load_state;
- DEBUG_OUT(8) <= sf_empty;
- DEBUG_OUT(9) <= sf_aempty;
- DEBUG_OUT(10) <= sf_full;
- DEBUG_OUT(11) <= sf_afull;
- end if;
-end process;
-
-DEBUG_OUT(383 downto 12) <= (others => '0');
-MONITOR_OUT(31 downto 0) <= too_large_dropped;
-MONITOR_OUT(223 downto 32) <= (others => '0');
-
-end architecture RTL;
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
---********
--- configures TriSpeed MAC and signalizes when it's ready
--- used also to filter out frames with different addresses
--- after main configuration (by setting TsMAC filtering accordingly)
-
-
-
-entity trb_net16_gbe_mac_control is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- signals to/from main controller
- MC_TSMAC_READY_OUT : out std_logic;
- MC_RECONF_IN : in std_logic;
- MC_GBE_EN_IN : in std_logic;
- MC_RX_DISCARD_FCS : in std_logic;
- MC_PROMISC_IN : in std_logic;
- MC_MAC_ADDR_IN : in std_logic_vector(47 downto 0);
-
--- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
- TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
- TSM_HCS_N_OUT : out std_logic;
- TSM_HWRITE_N_OUT : out std_logic;
- TSM_HREAD_N_OUT : out std_logic;
- TSM_HREADY_N_IN : in std_logic;
- TSM_HDATA_EN_N_IN : in std_logic;
-
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_mac_control;
-
-
-architecture trb_net16_gbe_mac_control of trb_net16_gbe_mac_control is
-
-attribute syn_encoding : string;
-
-type mac_conf_states is (IDLE, DISABLE, WRITE_TX_RX_CTRL1, WRITE_TX_RX_CTRL2, ENABLE, READY);
-signal mac_conf_current_state, mac_conf_next_state : mac_conf_states;
-attribute syn_encoding of mac_conf_current_state : signal is "onehot";
-
-signal tsmac_ready : std_logic;
-signal reg_mode : std_logic_vector(7 downto 0);
-signal reg_tx_rx_ctrl1, reg_tx_rx_ctrl2 : std_logic_vector(7 downto 0);
-signal reg_max_pkt_size : std_logic_vector(15 downto 0);
-signal reg_ipg : std_logic_vector(15 downto 0);
-signal reg_mac0 : std_logic_vector(15 downto 0);
-signal reg_mac1 : std_logic_vector(15 downto 0);
-signal reg_mac2 : std_logic_vector(15 downto 0);
-
-signal haddr : std_logic_vector(7 downto 0);
-signal hcs_n : std_logic;
-signal hwrite_n : std_logic;
-signal hdata_pointer : integer range 0 to 1;
-signal state : std_logic_vector(3 downto 0);
-signal hready_n_q : std_logic;
-
-begin
-
-reg_mode(7 downto 4) <= x"0";
-reg_mode(3) <= '1'; -- tx_en
-reg_mode(2) <= '1'; -- rx_en
-reg_mode(1) <= '1'; -- flow_control en
-reg_mode(0) <= MC_GBE_EN_IN; -- gbe en
-
-reg_tx_rx_ctrl2(7 downto 1) <= (others => '0'); -- reserved
-reg_tx_rx_ctrl2(0) <= '1'; -- receive short
-reg_tx_rx_ctrl1(7) <= '1'; -- receive broadcast
-reg_tx_rx_ctrl1(6) <= '1'; -- drop control
-reg_tx_rx_ctrl1(5) <= '0'; -- half_duplex en
-reg_tx_rx_ctrl1(4) <= '1'; -- receive multicast
-reg_tx_rx_ctrl1(3) <= '1'; -- receive pause
-reg_tx_rx_ctrl1(2) <= '0'; -- transmit disable FCS
-reg_tx_rx_ctrl1(1) <= '1'; -- receive discard FCS and padding
-reg_tx_rx_ctrl1(0) <= MC_PROMISC_IN; -- promiscuous mode
-
-
-MAC_CONF_MACHINE_PROC : process(CLK)
-begin
- if RESET = '1' then
- mac_conf_current_state <= IDLE;
- elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- mac_conf_current_state <= IDLE;
--- else
- mac_conf_current_state <= mac_conf_next_state;
--- end if;
- end if;
-end process MAC_CONF_MACHINE_PROC;
-
-MAC_CONF_MACHINE : process(mac_conf_current_state, MC_RECONF_IN, TSM_HREADY_N_IN)
-begin
-
- case mac_conf_current_state is
-
- when IDLE =>
- if (MC_RECONF_IN = '1') then
- mac_conf_next_state <= DISABLE;
- else
- mac_conf_next_state <= IDLE;
- end if;
-
- when DISABLE =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= WRITE_TX_RX_CTRL1;
- else
- mac_conf_next_state <= DISABLE;
- end if;
-
- when WRITE_TX_RX_CTRL1 =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= WRITE_TX_RX_CTRL2;
- else
- mac_conf_next_state <= WRITE_TX_RX_CTRL1;
- end if;
-
- when WRITE_TX_RX_CTRL2 =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= ENABLE;
- else
- mac_conf_next_state <= WRITE_TX_RX_CTRL2;
- end if;
-
- when ENABLE =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= READY;
- else
- mac_conf_next_state <= ENABLE;
- end if;
-
- when READY =>
- if (MC_RECONF_IN = '1') then
- mac_conf_next_state <= DISABLE;
- else
- mac_conf_next_state <= READY;
- end if;
-
- end case;
-
-end process MAC_CONF_MACHINE;
-
-HADDR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- case mac_conf_current_state is
- when IDLE =>
- TSM_HADDR_OUT <= x"00";
- when DISABLE =>
- TSM_HADDR_OUT <= x"00";
- when WRITE_TX_RX_CTRL1 =>
- TSM_HADDR_OUT <= x"02";
- when WRITE_TX_RX_CTRL2 =>
- TSM_HADDR_OUT <= x"03";
- when ENABLE =>
- TSM_HADDR_OUT <= x"00";
- when READY =>
- TSM_HADDR_OUT <= x"00";
- end case;
- end if;
-end process HADDR_PROC;
-
-HDATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- case mac_conf_current_state is
- when IDLE =>
- TSM_HDATA_OUT <= x"00";
- when DISABLE =>
- TSM_HDATA_OUT <= x"00";
- when WRITE_TX_RX_CTRL1 =>
- TSM_HDATA_OUT <= reg_tx_rx_ctrl1;
- when WRITE_TX_RX_CTRL2 =>
- TSM_HDATA_OUT <= reg_tx_rx_ctrl2;
- when ENABLE =>
- TSM_HDATA_OUT <= reg_mode;
- when READY =>
- TSM_HDATA_OUT <= x"00";
- end case;
- end if;
-end process HDATA_PROC;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (mac_conf_current_state = IDLE or mac_conf_current_state = READY) then
- hcs_n <= '1';
- hwrite_n <= '1';
- elsif (TSM_HREADY_N_IN = '1') then
- hcs_n <= '0';
- hwrite_n <= '0';
- else
- hcs_n <= '1';
- hwrite_n <= '1';
- end if;
-
- if (mac_conf_current_state = READY) then
- tsmac_ready <= '1';
- else
- tsmac_ready <= '0';
- end if;
- end if;
-end process;
-
-TSM_HCS_N_OUT <= hcs_n;
-TSM_HWRITE_N_OUT <= hwrite_n;
-TSM_HREAD_N_OUT <= '1';
-MC_TSMAC_READY_OUT <= tsmac_ready;
-
-
-end trb_net16_gbe_mac_control;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
--- controls the work of the whole gbe in both directions
--- multiplexes the output between data stream and output slow control packets based on priority
--- reacts to incoming gbe slow control commands
---
-
-
-entity trb_net16_gbe_main_control is
- generic(
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- DO_SIMULATION : integer range 0 to 1 := 0
- );
-port (
- CLK : in std_logic; -- system clock
- CLK_125 : in std_logic;
- RESET : in std_logic;
-
- MC_LINK_OK_OUT : out std_logic;
- MC_RESET_LINK_IN : in std_logic;
- MC_IDLE_TOO_LONG_OUT : out std_logic;
- MC_DHCP_DONE_OUT : out std_logic;
-
--- signals to/from receive controller
- RC_FRAME_WAITING_IN : in std_logic;
- RC_LOADING_DONE_OUT : out std_logic;
- RC_DATA_IN : in std_logic_vector(8 downto 0);
- RC_RD_EN_OUT : out std_logic;
- RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
- RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
--- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_RD_EN_IN : in std_logic;
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_TRANSMIT_DONE_IN : in std_logic;
-
--- signals to/from sgmii/gbe pcs_an_complete
- PCS_AN_COMPLETE_IN : in std_logic;
-
--- signals to/from hub
- MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
-
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
-
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
- CFG_READOUT_CTR_VALID_IN : in std_logic;
- CFG_INSERT_TTYPE_IN : in std_logic;
- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
-
- CFG_ADDITIONAL_HDR_IN : in std_logic;
-
- MAKE_RESET_OUT : out std_logic;
-
--- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
- TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
- TSM_HCS_N_OUT : out std_logic;
- TSM_HWRITE_N_OUT : out std_logic;
- TSM_HREAD_N_OUT : out std_logic;
- TSM_HREADY_N_IN : in std_logic;
- TSM_HDATA_EN_N_IN : in std_logic;
- TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0);
- TSM_RX_STAT_EN_IN : in std_logic;
-
-
- MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
- DATA_HIST_OUT : out hist_array;
- SCTRL_HIST_OUT : out hist_array
-);
-end trb_net16_gbe_main_control;
-
-
-architecture trb_net16_gbe_main_control of trb_net16_gbe_main_control is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group";
-
-attribute syn_encoding : string;
-
-signal tsm_ready : std_logic;
-signal tsm_reconf : std_logic;
-signal tsm_haddr : std_logic_vector(7 downto 0);
-signal tsm_hdata : std_logic_vector(7 downto 0);
-signal tsm_hcs_n : std_logic;
-signal tsm_hwrite_n : std_logic;
-signal tsm_hread_n : std_logic;
-
-type link_states is (INACTIVE, ACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS);
-signal link_current_state, link_next_state : link_states;
-attribute syn_encoding of link_current_state : signal is "onehot";
-
-signal link_down_ctr : std_logic_vector(15 downto 0);
-signal link_down_ctr_lock : std_logic;
-signal link_ok : std_logic;
-signal link_ok_timeout_ctr : std_logic_vector(15 downto 0);
-
-signal mac_control_debug : std_logic_vector(63 downto 0);
-
-type flow_states is (IDLE, TRANSMIT_CTRL, WAIT_FOR_FC, CLEANUP);
-signal flow_current_state, flow_next_state : flow_states;
-attribute syn_encoding of flow_current_state : signal is "onehot";
-
-signal state : std_logic_vector(3 downto 0);
-signal link_state : std_logic_vector(3 downto 0);
-signal redirect_state : std_logic_vector(3 downto 0);
-
-signal ps_wr_en : std_logic;
-signal ps_response_ready : std_logic;
-signal ps_busy : std_logic_vector(c_MAX_PROTOCOLS -1 downto 0);
-signal rc_rd_en : std_logic;
-signal first_byte : std_logic;
-signal first_byte_q : std_logic;
-signal first_byte_qq : std_logic;
-signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal loaded_bytes_ctr : std_Logic_vector(15 downto 0);
-
-signal dhcp_start : std_logic;
-signal dhcp_done : std_logic;
-signal wait_ctr : std_logic_vector(31 downto 0);
-
-signal rc_data_local : std_logic_vector(8 downto 0);
-
--- debug
-signal frame_waiting_ctr : std_logic_vector(15 downto 0);
-signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
-type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, WAIT_ONE, FINISH, CLEANUP);
-signal redirect_current_state, redirect_next_state : redirect_states;
-attribute syn_encoding of redirect_current_state : signal is "onehot";
-
-signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic;
-
-type stats_states is (IDLE, LOAD_VECTOR, CLEANUP);
-signal stats_current_state, stats_next_state : stats_states;
-
-signal stat_rdy, stat_ack : std_logic;
-signal rx_stat_en_q : std_logic;
-signal rx_stat_vec_q : std_logic_vector(31 downto 0);
-
-type array_of_ctrs is array(15 downto 0) of std_logic_vector(31 downto 0);
-signal arr : array_of_ctrs;
-signal stats_ctr : integer range 0 to 15;
-signal stat_data : std_logic_vector(31 downto 0);
-signal stat_addr : std_logic_vector(7 downto 0);
-
-signal unique_id : std_logic_vector(63 downto 0);
-
-
-signal nothing_sent : std_logic;
-signal nothing_sent_ctr : std_logic_vector(31 downto 0);
-
-signal dbg_ps : std_Logic_vector(63 downto 0);
-
-signal tc_data : std_logic_vector(8 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
-attribute syn_preserve of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
-
-signal mc_busy : std_logic;
-
-begin
-
-unique_id <= MC_UNIQUE_ID_IN;
-
-protocol_selector : trb_net16_gbe_protocol_selector
-generic map(
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- DO_SIMULATION => DO_SIMULATION
- )
-port map(
- CLK => CLK,
- RESET => RESET,
- RESET_FOR_DHCP => MC_RESET_LINK_IN,
-
- PS_DATA_IN => rc_data_local, -- RC_DATA_IN,
- PS_WR_EN_IN => ps_wr_en_qq, --ps_wr_en,
- PS_PROTO_SELECT_IN => proto_select,
- PS_BUSY_OUT => ps_busy,
- PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN,
- PS_RESPONSE_READY_OUT => ps_response_ready,
-
- PS_SRC_MAC_ADDRESS_IN => RC_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => RC_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => RC_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => RC_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => RC_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => RC_DEST_UDP_PORT_IN,
-
- TC_DATA_OUT => tc_data,
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_FRAME_SIZE_OUT => TC_FRAME_SIZE_OUT,
- TC_FRAME_TYPE_OUT => TC_FRAME_TYPE_OUT,
- TC_IP_PROTOCOL_OUT => TC_IP_PROTOCOL_OUT,
- TC_IDENT_OUT => TC_IDENT_OUT,
- TC_DEST_MAC_OUT => TC_DEST_MAC_OUT,
- TC_DEST_IP_OUT => TC_DEST_IP_OUT,
- TC_DEST_UDP_OUT => TC_DEST_UDP_OUT,
- TC_SRC_MAC_OUT => TC_SRC_MAC_OUT,
- TC_SRC_IP_OUT => TC_SRC_IP_OUT,
- TC_SRC_UDP_OUT => TC_SRC_UDP_OUT,
-
- MC_BUSY_IN => mc_busy,
-
- DHCP_START_IN => dhcp_start,
- DHCP_DONE_OUT => dhcp_done,
-
- GSC_CLK_IN => GSC_CLK_IN,
- GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => GSC_INIT_READ_IN,
- GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
- GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
- GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
- GSC_BUSY_IN => GSC_BUSY_IN,
-
- MAKE_RESET_OUT => MAKE_RESET_OUT,
-
- -- CTS interface
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data payload interface
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
-
- CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
- CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
- CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
- CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN,
- CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN,
- CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
- CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN,
- CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
- CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
- CFG_MAX_SUB_IN => CFG_MAX_SUB_IN,
- CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN,
- CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
- CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN,
-
- CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN,
-
- -- input for statistics from outside
- STAT_DATA_IN => stat_data,
- STAT_ADDR_IN => stat_addr,
- STAT_DATA_RDY_IN => stat_rdy,
- STAT_DATA_ACK_OUT => stat_ack,
-
- MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT,
- MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT,
- MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT,
- MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT,
- MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT,
- MONITOR_SELECT_DROP_IN_OUT => MONITOR_SELECT_DROP_IN_OUT,
- MONITOR_SELECT_GEN_DBG_OUT => MONITOR_SELECT_GEN_DBG_OUT,
-
- DATA_HIST_OUT => DATA_HIST_OUT,
- SCTRL_HIST_OUT => SCTRL_HIST_OUT
-);
-
-TC_DATA_OUT <= tc_data;
-
--- gk 07.11.11
--- do not select any response constructors when dropping a frame
-proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0');
-
--- gk 07.11.11
-DISABLE_REDIRECT_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- disable_redirect <= '0';
- elsif (redirect_current_state = CHECK_TYPE) then
- if (link_current_state /= ACTIVE and link_current_state /= GET_ADDRESS) then
- disable_redirect <= '1';
- elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN /= "10") then
- disable_redirect <= '1';
- else
- disable_redirect <= '0';
- end if;
- else
- disable_redirect <= disable_redirect;
- end if;
- end if;
-end process DISABLE_REDIRECT_PROC;
-
--- warning
-SYNC_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- rc_data_local <= RC_DATA_IN;
- end if;
-end process SYNC_PROC;
-
-REDIRECT_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- redirect_current_state <= IDLE;
- elsif rising_edge(CLK) then
- if RX_PATH_ENABLE = 1 then
- redirect_current_state <= redirect_next_state;
- else
- redirect_current_state <= IDLE;
- end if;
- end if;
-end process REDIRECT_MACHINE_PROC;
-
-REDIRECT_MACHINE : process(redirect_current_state, link_current_state, RC_FRAME_WAITING_IN, ps_busy, RC_FRAME_PROTO_IN, loaded_bytes_ctr, RC_FRAME_SIZE_IN)
-begin
- case redirect_current_state is
-
- when IDLE =>
- redirect_state <= x"1";
- if (RC_FRAME_WAITING_IN = '1') then
- redirect_next_state <= CHECK_TYPE;
- else
- redirect_next_state <= IDLE;
- end if;
-
- when CHECK_TYPE =>
- if (link_current_state = ACTIVE) then
- redirect_next_state <= CHECK_BUSY;
- elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then
- redirect_next_state <= CHECK_BUSY;
- else
- redirect_next_state <= DROP;
- end if;
-
- when DROP =>
- redirect_state <= x"7";
- if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= WAIT_ONE;
- else
- redirect_next_state <= DROP;
- end if;
-
- when CHECK_BUSY =>
- redirect_state <= x"6";
- if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
- redirect_next_state <= LOAD;
- else
- redirect_next_state <= BUSY;
- end if;
-
- when LOAD =>
- redirect_state <= x"2";
- if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= WAIT_ONE;
- else
- redirect_next_state <= LOAD;
- end if;
-
- when BUSY =>
- redirect_state <= x"3";
- if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
- redirect_next_state <= LOAD;
- else
- redirect_next_state <= BUSY;
- end if;
-
- when WAIT_ONE =>
- redirect_state <= x"f";
- redirect_next_state <= FINISH;
-
- when FINISH =>
- redirect_state <= x"4";
- redirect_next_state <= CLEANUP;
-
- when CLEANUP =>
- redirect_state <= x"5";
- redirect_next_state <= IDLE;
-
- end case;
-end process REDIRECT_MACHINE;
-
-rc_rd_en <= '1' when redirect_current_state = LOAD or redirect_current_state = DROP else '0';
-RC_RD_EN_OUT <= rc_rd_en;
-
-LOADING_DONE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RC_DATA_IN(8) = '1' and ps_wr_en_q = '1') then
- RC_LOADING_DONE_OUT <= '1';
- else
- RC_LOADING_DONE_OUT <= '0';
- end if;
- end if;
-end process LOADING_DONE_PROC;
-
-PS_WR_EN_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- ps_wr_en <= rc_rd_en;
- ps_wr_en_q <= ps_wr_en;
- ps_wr_en_qq <= ps_wr_en_q;
- end if;
-end process PS_WR_EN_PROC;
-
-LOADED_BYTES_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (redirect_current_state = IDLE) then
- loaded_bytes_ctr <= (others => '0');
- elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then
- loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
- else
- loaded_bytes_ctr <= loaded_bytes_ctr;
- end if;
- end if;
-end process LOADED_BYTES_CTR_PROC;
-
-FIRST_BYTE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- first_byte_q <= first_byte;
- first_byte_qq <= first_byte_q;
-
- if (redirect_current_state = IDLE) then
- first_byte <= '1';
- else
- first_byte <= '0';
- end if;
- end if;
-end process FIRST_BYTE_PROC;
-
---*********************
--- DATA FLOW CONTROL
-
-FLOW_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- flow_current_state <= IDLE;
- elsif rising_edge(CLK) then
- flow_current_state <= flow_next_state;
- end if;
-end process FLOW_MACHINE_PROC;
-
-FLOW_MACHINE : process(flow_current_state, TC_TRANSMIT_DONE_IN, ps_response_ready, tc_data)
-begin
- case flow_current_state is
-
- when IDLE =>
- if (ps_response_ready = '1') then
- flow_next_state <= TRANSMIT_CTRL;
- else
- flow_next_state <= IDLE;
- end if;
-
- when TRANSMIT_CTRL =>
- if (tc_data(8) = '1') then
- flow_next_state <= WAIT_FOR_FC;
- else
- flow_next_state <= TRANSMIT_CTRL;
- end if;
-
- when WAIT_FOR_FC =>
- if (TC_TRANSMIT_DONE_IN = '1') then
- flow_next_state <= CLEANUP;
- else
- flow_next_state <= WAIT_FOR_FC;
- end if;
-
- when CLEANUP =>
- flow_next_state <= IDLE;
-
- end case;
-end process FLOW_MACHINE;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (flow_current_state = IDLE and ps_response_ready = '1') then
- TC_TRANSMIT_CTRL_OUT <= '1';
- else
- TC_TRANSMIT_CTRL_OUT <= '0';
- end if;
-
- if (flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC) then
- mc_busy <= '1';
- else
- mc_busy <= '0';
- end if;
- end if;
-end process;
-
---***********************
--- LINK STATE CONTROL
-
-lsm_impl_gen : if DO_SIMULATION = 0 generate
- LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK)
- begin
- if MC_RESET_LINK_IN = '1' then
- link_current_state <= INACTIVE;
- elsif rising_edge(CLK) then
- if RX_PATH_ENABLE = 1 then
- link_current_state <= link_next_state;
- else
- link_current_state <= INACTIVE;
- end if;
- end if;
- end process;
-end generate lsm_impl_gen;
-
-lsm_sim_gen : if DO_SIMULATION = 1 generate
- LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK)
- begin
- if MC_RESET_LINK_IN = '1' then
- link_current_state <= GET_ADDRESS;
- elsif rising_edge(CLK) then
- if RX_PATH_ENABLE = 1 then
- link_current_state <= link_next_state;
- else
- link_current_state <= ACTIVE;
- end if;
- end if;
- end process;
-end generate lsm_sim_gen;
-
-LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, tsm_ready, link_ok_timeout_ctr)
-begin
- case link_current_state is
-
- when INACTIVE =>
- link_state <= x"2";
- if (PCS_AN_COMPLETE_IN = '1') then
- link_next_state <= TIMEOUT;
- else
- link_next_state <= INACTIVE;
- end if;
-
- when TIMEOUT =>
- link_state <= x"3";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- if (link_ok_timeout_ctr = x"ffff") then
- link_next_state <= ENABLE_MAC; --FINALIZE;
- else
- link_next_state <= TIMEOUT;
- end if;
- end if;
-
- when ENABLE_MAC =>
- link_state <= x"4";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- elsif (tsm_ready = '1') then
- link_next_state <= FINALIZE; --INACTIVE;
- else
- link_next_state <= ENABLE_MAC;
- end if;
-
- when FINALIZE =>
- link_state <= x"5";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- link_next_state <= WAIT_FOR_BOOT; --ACTIVE;
- end if;
-
- when WAIT_FOR_BOOT =>
- link_state <= x"6";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- if (wait_ctr = x"0000_1000") then
- link_next_state <= GET_ADDRESS;
- else
- link_next_state <= WAIT_FOR_BOOT;
- end if;
- end if;
-
- when GET_ADDRESS =>
- link_state <= x"7";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- if (dhcp_done = '1') then
- link_next_state <= ACTIVE;
- else
- link_next_state <= GET_ADDRESS;
- end if;
- end if;
-
- when ACTIVE =>
- link_state <= x"1";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- link_next_state <= ACTIVE;
- end if;
-
- end case;
-end process LINK_STATE_MACHINE;
-
-MC_DHCP_DONE_OUT <= '1' when link_current_state = ACTIVE else '0';
-
-LINK_OK_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- --if (RESET = '1') or (link_current_state /= TIMEOUT) then
- if (link_current_state /= TIMEOUT) then
- link_ok_timeout_ctr <= (others => '0');
- elsif (link_current_state = TIMEOUT) then
- link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1";
- end if;
-
- if (link_current_state = ACTIVE or link_current_state = GET_ADDRESS) then
- link_ok <= '1';
- else
- link_ok <= '0';
- end if;
-
- if (link_current_state = GET_ADDRESS) then
- dhcp_start <= '1';
- else
- dhcp_start <= '0';
- end if;
- end if;
-end process LINK_OK_CTR_PROC;
-
---link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) else '0';
-
-WAIT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (link_current_state = WAIT_FOR_BOOT) then
- wait_ctr <= wait_ctr + x"1";
- else
- wait_ctr <= (others => '0');
- end if;
- end if;
-end process WAIT_CTR_PROC;
-
---dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0';
-
---LINK_DOWN_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- link_down_ctr <= (others => '0');
--- link_down_ctr_lock <= '0';
--- elsif (PCS_AN_COMPLETE_IN = '1') then
--- link_down_ctr_lock <= '0';
--- elsif ((PCS_AN_COMPLETE_IN = '0') and (link_down_ctr_lock = '0')) then
--- link_down_ctr <= link_down_ctr + x"1";
--- link_down_ctr_lock <= '1';
--- end if;
--- end if;
---end process LINK_DOWN_CTR_PROC;
-
-MC_LINK_OK_OUT <= link_ok; -- or nothing_sent;
-
--- END OF LINK STATE CONTROL
---*************
-
---*************
--- GENERATE MAC_ADDRESS
-g_MY_MAC <= unique_id(31 downto 8) & x"be0002";
-
---*************
-
---****************
--- TRI SPEED MAC CONTROLLER
-
-TSMAC_CONTROLLER : trb_net16_gbe_mac_control
-port map(
- CLK => CLK,
- RESET => MC_RESET_LINK_IN,
-
--- signals to/from main controller
- MC_TSMAC_READY_OUT => tsm_ready,
- MC_RECONF_IN => tsm_reconf,
- MC_GBE_EN_IN => '1',
- MC_RX_DISCARD_FCS => '0',
- MC_PROMISC_IN => '1',
- MC_MAC_ADDR_IN => g_MY_MAC, --x"001122334455",
-
--- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT => tsm_haddr,
- TSM_HDATA_OUT => tsm_hdata,
- TSM_HCS_N_OUT => tsm_hcs_n,
- TSM_HWRITE_N_OUT => tsm_hwrite_n,
- TSM_HREAD_N_OUT => tsm_hread_n,
- TSM_HREADY_N_IN => TSM_HREADY_N_IN,
- TSM_HDATA_EN_N_IN => TSM_HDATA_EN_N_IN,
-
- DEBUG_OUT => open
-);
-
---DEBUG_OUT <= mac_control_debug;
-process(CLK)
-begin
- if rising_edge(CLK) then
- if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then
- tsm_reconf <= '1';
- else
- tsm_reconf <= '0';
- end if;
- end if;
-end process;
---tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '0') else '0';
-
-TSM_HADDR_OUT <= tsm_haddr;
-TSM_HCS_N_OUT <= tsm_hcs_n;
-TSM_HDATA_OUT <= tsm_hdata;
-TSM_HREAD_N_OUT <= tsm_hread_n;
-TSM_HWRITE_N_OUT <= tsm_hwrite_n;
-
--- END OF TRI SPEED MAC CONTROLLER
---***************
-
-
--- *****
--- STATISTICS
--- *****
-
---
---CTRS_GEN : for n in 0 to 15 generate
---
--- CTR_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- arr(n) <= (others => '0');
--- elsif (rx_stat_en_q = '1' and rx_stat_vec_q(16 + n) = '1') then
--- arr(n) <= arr(n) + x"1";
--- end if;
--- end if;
--- end process CTR_PROC;
---
---end generate CTRS_GEN;
---
---STAT_VEC_SYNC : signal_sync
---generic map (
--- WIDTH => 32,
--- DEPTH => 2
---)
---port map (
--- RESET => RESET,
--- CLK0 => CLK,
--- CLK1 => CLK,
--- D_IN => TSM_RX_STAT_VEC_IN,
--- D_OUT => rx_stat_vec_q
---);
---
---
---STAT_VEC_EN_SYNC : pulse_sync
---port map(
--- CLK_A_IN => CLK_125,
--- RESET_A_IN => RESET,
--- PULSE_A_IN => TSM_RX_STAT_EN_IN,
--- CLK_B_IN => CLK,
--- RESET_B_IN => RESET,
--- PULSE_B_OUT => rx_stat_en_q
---);
---
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, rx_stat_en_q, stats_ctr)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (rx_stat_en_q = '1') then
--- stats_next_state <= LOAD_VECTOR;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_VECTOR =>
--- --if (stat_ack = '1') then
--- if (stats_ctr = 15) then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_VECTOR;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---STATS_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (stats_current_state = IDLE) then
--- stats_ctr <= 0;
--- elsif (stats_current_state = LOAD_VECTOR and stat_ack ='1') then
--- stats_ctr <= stats_ctr + 1;
--- end if;
--- end if;
---end process STATS_CTR_PROC;
---
-----stat_data <= arr(stats_ctr);
---
---stat_addr <= x"0c" + std_logic_vector(to_unsigned(stats_ctr, 8));
---
---stat_rdy <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
---
---stat_data(7 downto 0) <= arr(stats_ctr)(31 downto 24);
---stat_data(15 downto 8) <= arr(stats_ctr)(23 downto 16);
---stat_data(23 downto 16) <= arr(stats_ctr)(15 downto 8);
---stat_data(31 downto 24) <= arr(stats_ctr)(7 downto 0);
-
-
--- **** debug
---FRAME_WAITING_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- frame_waiting_ctr <= (others => '0');
--- elsif (RC_FRAME_WAITING_IN = '1') then
--- frame_waiting_ctr <= frame_waiting_ctr + x"1";
--- end if;
--- end if;
---end process FRAME_WAITING_CTR_PROC;
---
---SAVE_VALUES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- ps_busy_q <= (others => '0');
--- rc_frame_proto_q <= (others => '0');
--- elsif (redirect_current_state = IDLE and RC_FRAME_WAITING_IN = '1') then
--- ps_busy_q <= ps_busy;
--- rc_frame_proto_q <= RC_FRAME_PROTO_IN;
--- end if;
--- end if;
---end process SAVE_VALUES_PROC;
-
-
--- ****
-
-
-
-end trb_net16_gbe_main_control;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb_net_gbe_components.all;
-
-entity trb_net16_gbe_packet_constr is
-port(
- RESET : in std_logic;
- CLK : in std_logic;
- MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10
- -- ports for user logic
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
- PC_DATA_IN : in std_logic_vector(7 downto 0);
- PC_READY_OUT : out std_logic;
- PC_START_OF_SUB_IN : in std_logic;
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10
- PC_END_OF_DATA_IN : in std_logic;
- PC_TRANSMIT_ON_OUT : out std_logic;
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
- PC_PADDING_IN : in std_logic; -- gk 29.03.10
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10
- -- FrameConstructor ports
- TC_WR_EN_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(7 downto 0);
- TC_H_READY_IN : in std_logic;
- TC_READY_IN : in std_logic;
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- TC_SOD_OUT : out std_logic;
- TC_EOD_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_packet_constr;
-
-architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_GBE_group";
-
-component fifo_64kx9
-port (
- Data : in std_logic_vector(8 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
--- FIFO for SubEventHeader information
-component fifo_16kx8 is
-port (
- Data : in std_logic_vector(7 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-signal df_wr_en : std_logic;
-signal df_rd_en : std_logic;
-signal df_q : std_logic_vector(7 downto 0);
-signal df_q_reg : std_logic_vector(7 downto 0);
-signal df_empty : std_logic;
-signal df_full : std_logic;
-
-signal fc_data : std_logic_vector(7 downto 0);
-signal fc_wr_en : std_logic;
-signal fc_sod : std_logic;
-signal fc_eod : std_logic;
-signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter!
-signal fc_flags_offset : std_logic_vector(15 downto 0);
-
-signal shf_data : std_logic_vector(7 downto 0);
-signal shf_wr_en : std_logic;
-signal shf_rd_en : std_logic;
-signal shf_q : std_logic_vector(7 downto 0);
-signal shf_empty : std_logic;
-signal shf_full : std_logic;
-
-type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD);
-signal constructCurrentState, constructNextState : constructStates;
-signal constr_state : std_logic_vector(3 downto 0);
-signal all_int_ctr : integer range 0 to 31;
-signal all_ctr : std_logic_vector(4 downto 0);
-
-type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM);
-signal saveSubCurrentState, saveSubNextState : saveSubStates;
-signal save_state : std_logic_vector(3 downto 0);
-signal sub_int_ctr : integer range 0 to 31;
-signal sub_ctr : std_logic_vector(4 downto 0);
-signal my_int_ctr : integer range 0 to 3;
-signal my_ctr : std_logic_vector(1 downto 0);
-
-type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY);
-signal loadCurrentState, loadNextState: loadStates;
-signal load_state : std_logic_vector(3 downto 0);
-
-signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination
-signal queue_size_temp : std_logic_vector(31 downto 0);
-signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid
-signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame
-signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf
-signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted
-signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent
-signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet
-signal size_left : std_logic_vector(31 downto 0);
-signal fc_ip_size : std_logic_vector(15 downto 0);
-signal fc_udp_size : std_logic_vector(15 downto 0);
-signal max_frame_size : std_logic_vector(15 downto 0);
-signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term
-signal debug : std_logic_vector(63 downto 0);
-signal pc_ready : std_logic;
-
-signal pc_sub_size : std_logic_vector(31 downto 0);
-signal pc_trig_nr : std_logic_vector(31 downto 0);
-signal rst_after_sub_comb : std_logic; -- gk 08.04.10
-signal rst_after_sub : std_logic; -- gk 08.04.10
-signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10
-signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10
-signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10
-
--- gk 26.07.10
-signal load_eod : std_logic;
-signal load_eod_q : std_logic;
-
--- gk 07.10.10
-signal df_eod : std_logic;
-
--- gk 04.12.10
-signal first_sub_in_multi : std_logic;
-signal from_divide_state : std_logic;
-signal disable_prep : std_logic;
-
-begin
-
-
-PC_TRANSMIT_ON_OUT <= '1' when constructCurrentState = WAIT_FOR_LOAD else '0';
-
-my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order
-load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10
-
-all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging
-sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging
-my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging
-
-max_frame_size <= PC_MAX_FRAME_SIZE_IN;
-
--- Ready signal for PacketConstructor
-pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0';
-
--- store event information on Start_of_Subevent
-THE_EVT_INFO_STORE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( PC_START_OF_SUB_IN = '1' ) then
- pc_sub_size <= PC_SUB_SIZE_IN;
- pc_trig_nr <= PC_TRIG_NR_IN;
- else
- pc_sub_size <= pc_sub_size;
- pc_trig_nr <= pc_trig_nr;
- end if;
- end if;
-end process;
-
--- gk 07.10.10
-df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1'))
- or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1'))
- else '0';
-
--- Data FIFO for incoming packet data from IPU buffer
--- gk 26.07.10
-DATA_FIFO : fifo_64kx9
-port map(
- Data(7 downto 0) => PC_DATA_IN,
- Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 07.10.10
- WrClock => CLK,
- RdClock => CLK,
- WrEn => df_wr_en,
- RdEn => df_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q(7 downto 0) => df_q,
- Q(8) => load_eod,
- Empty => df_empty,
- Full => df_full
-);
-
-LOAD_EOD_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- load_eod_q <= load_eod;
- end if;
-end process LOAD_EOD_PROC;
-
--- Write enable for the data FIFO
--- !!!combinatorial signal!!!
--- could be avoided as IPU2GBE does only send data in case of PC_READY.
-df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD))
- else '0';
-
--- Output register for data FIFO
-dfQProc : process(CLK)
-begin
- if rising_edge(CLK) then
- df_q_reg <= df_q;
- end if;
-end process dfQProc;
-
--- Construction state machine
-constructMachineProc : process(RESET, CLK)
-begin
- if RESET = '1' then
- constructCurrentState <= CIDLE;
- elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- constructCurrentState <= CIDLE;
--- else
- constructCurrentState <= constructNextState;
--- end if;
- end if;
-end process constructMachineProc;
-
-constructMachine : process(constructCurrentState, df_empty, PC_START_OF_SUB_IN, PC_END_OF_DATA_IN, loadCurrentState)
-begin
- case constructCurrentState is
- when CIDLE =>
- constr_state <= x"1";
- --if( PC_WR_EN_IN = '1' ) then
- -- gk 04.12.10
- if (PC_START_OF_SUB_IN = '1') then
-
- constructNextState <= SAVE_DATA;
- else
- constructNextState <= CIDLE;
- end if;
- when SAVE_DATA =>
- constr_state <= x"2";
- if( PC_END_OF_DATA_IN = '1') then
- constructNextState <= WAIT_FOR_LOAD;
- else
- constructNextState <= SAVE_DATA;
- end if;
- when WAIT_FOR_LOAD =>
- constr_state <= x"3";
- if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted
- constructNextState <= CIDLE;
- else
- constructNextState <= WAIT_FOR_LOAD;
- end if;
- when others =>
- constr_state <= x"f";
- constructNextState <= CIDLE;
- end case;
-end process constructMachine;
-
---***********************
--- SIZE COUNTERS FOR SAVING SIDE
---***********************
-
--- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size
--- that's why they are removed if pc_padding flag is asserted
-sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0')
- else (x"c" + pc_sub_size); -- subevent headers + data
-
--- BUG HERE BUG HERE BUG HERE BUG HERE
--- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents
-queueSizeProc : process(RESET, CLK)
-begin
- if (RESET = '1') then
- queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination
- elsif rising_edge(CLK) then
- --if (RESET = '1') or (loadCurrentState = PUT_Q_DEC) then -- gk 07.10.10 -- (loadCurrentState = CLEANUP) then
- if (loadCurrentState = CLEANUP) then
- queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination
- elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then
- queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers
- else
- queue_size <= queue_size;
- end if;
- end if;
-end process queueSizeProc;
-
-
---***********************
--- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION
---***********************
-
-loadMachineProc : process(RESET, CLK)
-begin
- if RESET = '1' then
- loadCurrentState <= LIDLE;
- elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- loadCurrentState <= LIDLE;
--- else
- loadCurrentState <= loadNextState;
--- end if;
- end if;
-end process loadMachineProc;
-
-loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty,
- size_left, TC_H_READY_IN,
- max_frame_size, bytes_loaded, divide_position, PC_DELAY_IN,
- delay_ctr, load_eod_q, MULT_EVT_ENABLE_IN)
-begin
- case loadCurrentState is
- when LIDLE =>
- load_state <= x"1";
- if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then
- loadNextState <= WAIT_FOR_FC;
- else
- loadNextState <= LIDLE;
- end if;
- when WAIT_FOR_FC =>
- load_state <= x"2";
- if (TC_H_READY_IN = '1') then
- loadNextState <= PUT_Q_LEN;
- else
- loadNextState <= WAIT_FOR_FC;
- end if;
- when PUT_Q_LEN =>
- load_state <= x"3";
- if (all_int_ctr = 3) then
- loadNextState <= PUT_Q_DEC;
- else
- loadNextState <= PUT_Q_LEN;
- end if;
- when PUT_Q_DEC =>
- load_state <= x"4";
- if (all_int_ctr = 3) then
- loadNextState <= LOAD_SUB;
- else
- loadNextState <= PUT_Q_DEC;
- end if;
- when LOAD_SUB =>
- load_state <= x"5";
- if (bytes_loaded = max_frame_size - 1) then
- loadNextState <= DIVIDE;
- elsif (all_int_ctr = 15) then
- loadNextState <= PREP_DATA;
- else
- loadNextState <= LOAD_SUB;
- end if;
- when PREP_DATA =>
- load_state <= x"6";
- loadNextState <= LOAD_DATA;
- when LOAD_DATA =>
- load_state <= x"7";
--- if (bytes_loaded = max_frame_size - 1) then
--- loadNextState <= DIVIDE;
--- -- gk 07.10.10
--- elsif (MULT_EVT_ENABLE_IN = '1') then
--- if (size_left = x"0000_0023") then
--- loadNextState <= LOAD_TERM;
--- elsif (load_eod_q = '1') then
--- loadNextState <= LOAD_SUB;
--- else
--- loadNextState <= LOAD_DATA;
--- end if;
--- else
--- if (load_eod_q = '1') then
--- loadNextState <= LOAD_TERM;
--- else
--- loadNextState <= LOAD_DATA;
--- end if;
--- end if;
- if (bytes_loaded = max_frame_size - 1) then
- loadNextState <= DIVIDE;
- -- gk 07.10.10
- elsif (load_eod_q = '1') then
- if (MULT_EVT_ENABLE_IN = '1') then
- if (size_left < x"0000_0030") then
- loadNextState <= LOAD_TERM;
- else
- loadNextState <= LOAD_SUB;
- end if;
- else
- loadNextState <= LOAD_TERM;
- end if;
- else
- loadNextState <= LOAD_DATA;
- end if;
- when DIVIDE =>
- load_state <= x"8";
- if (TC_H_READY_IN = '1') then
- if (divide_position = "00") then
- loadNextState <= PREP_DATA;
- elsif (divide_position = "01") then
- loadNextState <= LOAD_SUB;
- else
- loadNextState <= LOAD_TERM;
- end if;
- else
- loadNextState <= DIVIDE;
- end if;
- when LOAD_TERM =>
- load_state <= x"9";
- if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then
- loadNextState <= DIVIDE;
- elsif (all_int_ctr = 31) then
- loadNextState <= CLEANUP;
- else
- loadNextState <= LOAD_TERM;
- end if;
- -- gk 28.04.10
- when CLEANUP =>
- load_state <= x"a";
- if (PC_DELAY_IN = x"0000_0000") then
- loadNextState <= LIDLE;
- else
- loadNextState <= DELAY;
- end if;
- -- gk 28.04.10
- when DELAY =>
- load_state <= x"b";
- if (delay_ctr = x"0000_0000") then
- loadNextState <= LIDLE;
- else
- loadNextState <= DELAY;
- end if;
- when others =>
- load_state <= x"f";
- loadNextState <= LIDLE;
- end case;
-end process loadMachine;
-
--- gk 04.12.10
-firstSubInMultiProc : process(RESET, CLK)
-begin
- if (RESET = '1') then
- first_sub_in_multi <= '1';
- elsif rising_edge(CLK) then
- if (loadCurrentState = LOAD_TERM) then
- first_sub_in_multi <= '1';
- elsif (loadCurrentState = LOAD_DATA) then
- first_sub_in_multi <= '0';
- else
- first_sub_in_multi <= first_sub_in_multi;
- end if;
- end if;
-end process;
-
--- gk 04.12.10
-fromDivideStateProc : process(RESET, CLK)
-begin
- if (RESET = '1') then
- from_divide_state <= '0';
- elsif rising_edge(CLK) then
- if (loadCurrentState = DIVIDE) then
- from_divide_state <= '1';
- elsif (loadCurrentState = PREP_DATA) then
- from_divide_state <= '0';
- else
- from_divide_state <= from_divide_state;
- end if;
- end if;
-end process fromDivideStateProc;
-
-
-dividePositionProc : process(RESET, CLK)
-begin
- if (RESET = '1') then
- divide_position <= "00";
- disable_prep <= '0';
- elsif rising_edge(CLK) then
- if (bytes_loaded = max_frame_size - 1) then
- if (loadCurrentState = LIDLE) then
- divide_position <= "00";
- disable_prep <= '0'; -- gk 05.12.10
- elsif (loadCurrentState = LOAD_DATA) then
- -- gk 05.12.10
- -- gk 26.07.10
- if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term
- divide_position <= "11";
- disable_prep <= '0'; -- gk 05.12.10
- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then
- if (size_left > x"0000_0028") then
- divide_position <= "01";
- disable_prep <= '0'; -- gk 05.12.10
- else
- divide_position <= "11";
- disable_prep <= '0'; -- gk 05.12.10
- end if;
- else
- divide_position <= "00"; -- still data loaded divide on data
- disable_prep <= '1'; -- gk 05.12.10
- end if;
- elsif (loadCurrentState = LOAD_SUB) then
- if (all_int_ctr = 15) then
- divide_position <= "00";
- disable_prep <= '1'; -- gk 05.12.10
- else
- divide_position <= "01";
- disable_prep <= '0'; -- gk 05.12.10
- end if;
- elsif (loadCurrentState = LOAD_TERM) then
- divide_position <= "11";
- disable_prep <= '0'; -- gk 05.12.10
- else
- divide_position <= divide_position;
- disable_prep <= disable_prep;
- end if;
- elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep
- disable_prep <= '0';
- divide_position <= divide_position;
- else
- divide_position <= divide_position;
- disable_prep <= disable_prep;
- end if;
-
- end if;
-end process dividePositionProc;
-
-allIntCtrProc : process(CLK)
-begin
- if rising_edge(CLK) then
- case loadCurrentState is
-
- when LIDLE => all_int_ctr <= 0;
-
- when WAIT_FOR_FC => all_int_ctr <= 0;
-
- when PUT_Q_LEN =>
- if (all_int_ctr = 3) then
- all_int_ctr <= 0;
- else
- all_int_ctr <= all_int_ctr + 1;
- end if;
-
- when PUT_Q_DEC =>
- if (all_int_ctr = 3) then
- all_int_ctr <= 0;
- else
- all_int_ctr <= all_int_ctr + 1;
- end if;
-
- when LOAD_SUB =>
- if (all_int_ctr = 15) then
- all_int_ctr <= 0;
- else
- all_int_ctr <= all_int_ctr + 1;
- end if;
-
- when LOAD_DATA => all_int_ctr <= 0;
-
- when LOAD_TERM =>
- if (all_int_ctr = 31) then
- all_int_ctr <= 0;
- else
- all_int_ctr <= all_int_ctr + 1;
- end if;
-
- when DIVIDE => null;
-
- when CLEANUP => all_int_ctr <= 0;
-
- when PREP_DATA => all_int_ctr <= 0;
-
- when DELAY => all_int_ctr <= 0;
- end case;
- end if;
-end process allIntCtrProc;
-
-dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, all_int_ctr, load_eod_q)
-begin
- if (loadCurrentState = LOAD_DATA) then
--- if (bytes_loaded = max_frame_size - x"1") then
--- df_rd_en <= '0';
--- -- gk 07.10.10
--- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then
--- df_rd_en <= '0';
--- -- gk 07.10.10
--- elsif (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then
--- df_rd_en <= '0';
--- else
--- df_rd_en <= '1';
--- end if;
- if (bytes_loaded = max_frame_size - x"1") then
- df_rd_en <= '0';
- -- gk 26.07.10
- --elsif (load_eod = '1') or (load_eod_q = '1') then
- elsif (load_eod_q = '1') then
- df_rd_en <= '0';
--- elsif (sub_bytes_loaded = sub_size_loaded) then
--- df_rd_en <= '0';
- else
- df_rd_en <= '1';
- end if;
-
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then
- df_rd_en <= '1';
- elsif (loadCurrentState = PREP_DATA) then
- df_rd_en <= '1';
- else
- df_rd_en <= '0';
- end if;
-end process dfRdEnProc;
-
-shfRdEnProc : process(loadCurrentState, all_int_ctr)
-begin
- if (loadCurrentState = LOAD_SUB) then
- shf_rd_en <= '1';
- elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then
- shf_rd_en <= '1';
- elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then
- shf_rd_en <= '1';
- else
- shf_rd_en <= '0';
- end if;
-end process shfRdEnProc;
-
-
-fcWrEnProc : process(loadCurrentState, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep)
-begin
- if (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then
- fc_wr_en <= '1';
- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then
- fc_wr_en <= '1';
- -- gk 04.12.10
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then
- fc_wr_en <= '1';
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then
- fc_wr_en <= '1';
- else
- fc_wr_en <= '0';
- end if;
-end process fcWrEnProc;
-
-
--- was all_int_ctr
-fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr)
-begin
- case loadCurrentState is
- when LIDLE => fc_data <= x"af";
- when WAIT_FOR_FC => fc_data <= x"bf";
- -- gk 08.04.10 my_int_ctr changed to load_int_ctr
- when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8);
- when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8);
- when LOAD_SUB => fc_data <= shf_q;
- when PREP_DATA => fc_data <= df_q_reg;
- when LOAD_DATA => fc_data <= df_q_reg;
- when LOAD_TERM => fc_data <= shf_q;
- when DIVIDE => fc_data <= x"cf";
- when CLEANUP => fc_data <= x"df";
- when others => fc_data <= x"00";
- end case;
-end process fcDataProc;
-
--- delay counters
--- gk 28.04.10
-DELAY_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = LIDLE) then
- delay_ctr <= PC_DELAY_IN;
- elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then
- delay_ctr <= delay_ctr - x"1";
- else
- delay_ctr <= delay_ctr;
- end if;
- end if;
-end process DELAY_CTR_PROC;
-
--- gk 28.04.10
-TICKS_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then
- ticks_ctr <= x"00";
- elsif (loadCurrentState = DELAY) then
- ticks_ctr <= ticks_ctr + x"1";
- else
- ticks_ctr <= ticks_ctr;
- end if;
- end if;
-end process TICKS_CTR_PROC;
-
-
---***********************
--- SIZE COUNTERS FOR LOADING SIDE
---***********************
-
-queue_size_temp <= queue_size - x"20"; -- size of data without termination
-
--- gk 08.04.10
-rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or
- ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded)
- else '0';
-
--- gk 08.04.10
-RST_AFTER_SUB_PROC : process(CLK)
-begin
- if(rising_edge(CLK)) then
- rst_after_sub <= rst_after_sub_comb;
- end if;
-end process RST_AFTER_SUB_PROC;
-
--- counts all bytes loaded to divide data into frames
-bytesLoadedProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then
- bytes_loaded <= x"0000";
- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then
- bytes_loaded <= bytes_loaded + x"1";
- -- gk 05.12.10
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then
--- bytes_loaded <= bytes_loaded + x"1";
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then
- bytes_loaded <= bytes_loaded + x"1";
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then
- bytes_loaded <= bytes_loaded + x"1";
- else
- bytes_loaded <= bytes_loaded;
- end if;
- end if;
-end process bytesLoadedProc;
-
--- size of subevent loaded from memory
-subSizeLoadedProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10
- sub_size_loaded <= x"00000000";
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then
- -- was all_int_ctr
- -- gk 08.04.10 my_int_ctr changed to load_int_ctr
- sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q;
- -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then
- sub_size_loaded <= sub_size_loaded + x"4";
- else
- sub_size_loaded <= sub_size_loaded;
- end if;
- end if;
-end process subSizeLoadedProc;
-
--- counts only raw data bytes being loaded
-subBytesLoadedProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10
- sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count
- elsif (loadCurrentState = LOAD_DATA) then
- sub_bytes_loaded <= sub_bytes_loaded + x"1";
- else
- sub_bytes_loaded <= sub_bytes_loaded;
- end if;
- end if;
-end process subBytesLoadedProc;
-
--- counts the size of the large udp packet
-actualPacketProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then
- actual_packet_size <= x"0008";
- elsif (fc_wr_en = '1') then
- actual_packet_size <= actual_packet_size + x"1";
- else
- actual_packet_size <= actual_packet_size;
- end if;
- end if;
-end process actualPacketProc;
-
-actualQueueSizeProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = CLEANUP) then
- actual_queue_size <= (others => '0');
- elsif (loadCurrentState = LIDLE) then
- actual_queue_size <= queue_size;
- else
- actual_queue_size <= actual_queue_size;
- end if;
- end if;
-end process actualQueueSizeProc;
-
--- amount of bytes left to send in current packet
-sizeLeftProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = CLEANUP) then
- size_left <= (others => '0');
- elsif (loadCurrentState = LIDLE) then
- size_left <= queue_size;
- elsif (fc_wr_en = '1') then
- size_left <= size_left - 1;
- else
- size_left <= size_left;
- end if;
- end if;
-end process sizeLeftProc;
-
--- HOT FIX: don't rely on CTS information, count the packets on your own.
--- In this case, we increment the fragmented packet ID with EOD from ipu2gbe.
-THE_FC_IDENT_COUNTER_PROC: process(RESET, CLK)
-begin
- if (RESET = '1') then
- fc_ident <= (others => '0');
- elsif rising_edge(CLK) then
- if (PC_END_OF_DATA_IN = '1') then
- fc_ident <= fc_ident + 1;
- else
- fc_ident <= fc_ident;
- end if;
- end if;
-end process THE_FC_IDENT_COUNTER_PROC;
-
-fc_flags_offset(15 downto 14) <= "00";
-
-moreFragmentsProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then
- fc_flags_offset(13) <= '0';
- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then
- if ((actual_queue_size - actual_packet_size) < max_frame_size) then
- fc_flags_offset(13) <= '0'; -- no more fragments
- else
- fc_flags_offset(13) <= '1'; -- more fragments
- end if;
- else
- fc_flags_offset(13) <= fc_flags_offset(13);
- end if;
- end if;
-end process moreFragmentsProc;
-
-eodProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then
- fc_eod <= '1';
- elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then
- fc_eod <= '1';
- elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then
- fc_eod <= '1';
- else
- fc_eod <= '0';
- end if;
- end if;
-end process eodProc;
-
-sodProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then
- fc_sod <= '1';
- elsif (loadCurrentState = DIVIDE) and (TC_READY_IN = '1') then
- fc_sod <= '1';
- else
- fc_sod <= '0';
- end if;
- end if;
-end process sodProc;
-
-offsetProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then
- fc_flags_offset(12 downto 0) <= (others => '0');
- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) then
- fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3);
- else
- fc_flags_offset(12 downto 0) <= fc_flags_offset(12 downto 0);
- end if;
- end if;
-end process offsetProc;
-
-fcIPSizeProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then
- if (size_left >= max_frame_size) then
- fc_ip_size <= max_frame_size;
- else
- fc_ip_size <= size_left(15 downto 0);
- end if;
- else
- fc_ip_size <= fc_ip_size;
- end if;
- end if;
-end process fcIPSizeProc;
-
-fcUDPSizeProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then
- fc_udp_size <= queue_size(15 downto 0);
- else
- fc_udp_size <= fc_udp_size;
- end if;
- end if;
-end process fcUDPSizeProc;
-
-
---***********************
--- SUBEVENT HEADERS WRITE AND READ
---***********************
-
-SUBEVENT_HEADERS_FIFO : fifo_4kx8_ecp3 --fifo_16kx8
-port map(
- Data => shf_data,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => shf_wr_en,
- RdEn => shf_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q => shf_q,
- Empty => shf_empty,
- Full => shf_full
-);
-
--- write enable for SHF
-shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA))
- else '0';
-
--- data multiplexing for SHF (convert 32bit LWs to 8bit)
--- CHANGED.
--- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC.
-shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN,
- pc_trig_nr, my_int_ctr, fc_data)
-begin
- case saveSubCurrentState is
- when SIDLE => shf_data <= x"ac";
- when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
- when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
- when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
- when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
- when SAVE_TERM => shf_data <= fc_data;
- when others => shf_data <= x"00";
- end case;
-end process shfDataProc;
-
-saveSubMachineProc : process(RESET, CLK)
-begin
- if RESET = '1' then
- saveSubCurrentState <= SIDLE;
- elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- saveSubCurrentState <= SIDLE;
--- else
- saveSubCurrentState <= saveSubNextState;
--- end if;
- end if;
-end process saveSubMachineProc;
-
-saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, TC_H_READY_IN)
-begin
- case saveSubCurrentState is
- when SIDLE =>
- save_state <= x"1";
- if (PC_START_OF_SUB_IN = '1') then
- saveSubNextState <= SAVE_SIZE;
- -- this branch is dangerous!
- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len
- saveSubNextState <= SAVE_TERM;
- else
- saveSubNextState <= SIDLE;
- end if;
- when SAVE_SIZE =>
- save_state <= x"2";
- if (sub_int_ctr = 3) then
- saveSubNextState <= SAVE_DECODING;
- else
- saveSubNextState <= SAVE_SIZE;
- end if;
- when SAVE_DECODING =>
- save_state <= x"3";
- if (sub_int_ctr = 3) then
- saveSubNextState <= SAVE_ID;
- else
- saveSubNextState <= SAVE_DECODING;
- end if;
- when SAVE_ID =>
- save_state <= x"4";
- if (sub_int_ctr = 3) then
- saveSubNextState <= SAVE_TRIG_NR;
- else
- saveSubNextState <= SAVE_ID;
- end if;
- when SAVE_TRIG_NR =>
- save_state <= x"5";
- if (sub_int_ctr = 3) then
- saveSubNextState <= SIDLE;
- else
- saveSubNextState <= SAVE_TRIG_NR;
- end if;
- when SAVE_TERM =>
- save_state <= x"6";
- if (sub_int_ctr = 31) then
- saveSubNextState <= SIDLE;
- else
- saveSubNextState <= SAVE_TERM;
- end if;
- when others =>
- save_state <= x"f";
- saveSubNextState <= SIDLE;
- end case;
-end process;
-
--- This counter is used for breaking down 32bit information words into 8bit bytes for
--- storing them in the SHF.
--- It is also used for the termination 32byte sequence.
-subIntProc: process( CLK )
-begin
- if rising_edge(CLK) then
- if (saveSubCurrentState = SIDLE) then
- sub_int_ctr <= 0;
- elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then
- sub_int_ctr <= 0;
- elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then
- sub_int_ctr <= 0;
- elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then
- sub_int_ctr <= sub_int_ctr + 1;
- else
- sub_int_ctr <= sub_int_ctr;
- end if;
- end if;
-end process subIntProc;
-
---debug(3 downto 0) <= constr_state;
---debug(7 downto 4) <= save_state;
---debug(11 downto 8) <= load_state;
---debug(27 downto 12) <= queue_size(15 downto 0);
---debug(28) <= df_full;
---debug(29) <= df_empty;
---debug(30) <= shf_full;
---debug(31) <= shf_empty;
---
---debug(47 downto 32) <= size_left(15 downto 0);
---debug(52 downto 48) <= all_ctr;
---debug(53) <= pc_ready;
-
--- outputs
-PC_READY_OUT <= pc_ready;
-TC_WR_EN_OUT <= fc_wr_en;
-TC_DATA_OUT <= fc_data;
-TC_IP_SIZE_OUT <= fc_ip_size;
-TC_UDP_SIZE_OUT <= fc_udp_size;
--- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0);
--- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8);
-TC_FLAGS_OFFSET_OUT <= fc_flags_offset;
-TC_SOD_OUT <= fc_sod;
-TC_EOD_OUT <= fc_eod;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- DEBUG_OUT(3 downto 0) <= constr_state;
- DEBUG_OUT(7 downto 4) <= load_state;
- DEBUG_OUT(11 downto 8) <= save_state;
- DEBUG_OUT(12) <= df_full;
- DEBUG_OUT(13) <= df_empty;
- DEBUG_OUT(14) <= shf_full;
- DEBUG_OUT(15) <= shf_empty;
- end if;
-end process;
-DEBUG_OUT(63 downto 16) <= (others => '0');
-
-end trb_net16_gbe_packet_constr;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-use IEEE.std_logic_arith.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.trb_net16_hub_func.all;\r
-\r
-entity trb_net16_gbe_packet_constr is\r
-port(\r
- RESET : in std_logic;\r
- CLK : in std_logic;\r
- -- ports for user logic\r
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic\r
- PC_DATA_IN : in std_logic_vector(7 downto 0);\r
- PC_READY_OUT : out std_logic;\r
- PC_START_OF_SUB_IN : in std_logic;\r
- PC_END_OF_DATA_IN : in std_logic;\r
- -- queue and subevent layer headers\r
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap\r
- PC_PADDING_IN : in std_logic; -- gk 29.03.10\r
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap\r
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap\r
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!\r
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap\r
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP\r
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10\r
- -- FrameConstructor ports\r
- FC_WR_EN_OUT : out std_logic;\r
- FC_DATA_OUT : out std_logic_vector(7 downto 0);\r
- FC_H_READY_IN : in std_logic;\r
- FC_READY_IN : in std_logic;\r
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);\r
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);\r
- FC_IDENT_OUT : out std_logic_vector(15 downto 0);\r
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);\r
- FC_SOD_OUT : out std_logic;\r
- FC_EOD_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
-);\r
-end trb_net16_gbe_packet_constr;\r
-\r
-architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is\r
-\r
--- -- Placer Directives\r
--- attribute HGROUP : string;\r
--- -- for whole architecture\r
--- attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_packet_constr_group";\r
-\r
-component fifo_64kx9\r
-port (\r
- Data : in std_logic_vector(8 downto 0); \r
- WrClock : in std_logic; \r
- RdClock : in std_logic; \r
- WrEn : in std_logic; \r
- RdEn : in std_logic; \r
- Reset : in std_logic; \r
- RPReset : in std_logic; \r
- Q : out std_logic_vector(8 downto 0); \r
- Empty : out std_logic; \r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
--- FIFO for SubEventHeader information\r
-component fifo_2048x8 is\r
-port (\r
- Data : in std_logic_vector(7 downto 0); \r
- WrClock : in std_logic; \r
- RdClock : in std_logic; \r
- WrEn : in std_logic; \r
- RdEn : in std_logic; \r
- Reset : in std_logic; \r
- RPReset : in std_logic; \r
- Q : out std_logic_vector(7 downto 0); \r
- Empty : out std_logic; \r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
-signal df_wr_en : std_logic;\r
-signal df_rd_en : std_logic;\r
-signal df_q : std_logic_vector(7 downto 0);\r
-signal df_q_reg : std_logic_vector(7 downto 0);\r
-signal df_empty : std_logic;\r
-signal df_full : std_logic;\r
-\r
-signal fc_data : std_logic_vector(7 downto 0);\r
-signal fc_wr_en : std_logic;\r
-signal fc_sod : std_logic;\r
-signal fc_eod : std_logic;\r
-signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter!\r
-signal fc_flags_offset : std_logic_vector(15 downto 0);\r
-\r
-signal shf_data : std_logic_vector(7 downto 0);\r
-signal shf_wr_en : std_logic;\r
-signal shf_rd_en : std_logic;\r
-signal shf_q : std_logic_vector(7 downto 0);\r
-signal shf_empty : std_logic;\r
-signal shf_full : std_logic;\r
-\r
-type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD);\r
-signal constructCurrentState, constructNextState : constructStates;\r
-signal constr_state : std_logic_vector(3 downto 0);\r
-signal all_int_ctr : integer range 0 to 31;\r
-signal all_ctr : std_logic_vector(4 downto 0);\r
-\r
-type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM);\r
-signal saveSubCurrentState, saveSubNextState : saveSubStates;\r
-signal save_state : std_logic_vector(3 downto 0);\r
-signal sub_int_ctr : integer range 0 to 31;\r
-signal sub_ctr : std_logic_vector(4 downto 0);\r
-signal my_int_ctr : integer range 0 to 3;\r
-signal my_ctr : std_logic_vector(1 downto 0);\r
-\r
-type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY);\r
-signal loadCurrentState, loadNextState: loadStates;\r
-signal load_state : std_logic_vector(3 downto 0);\r
-\r
-signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination\r
-signal queue_size_temp : std_logic_vector(31 downto 0);\r
-signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid\r
-signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame\r
-signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf\r
-signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted\r
-signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent \r
-signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet\r
-signal size_left : std_logic_vector(31 downto 0);\r
-signal fc_ip_size : std_logic_vector(15 downto 0);\r
-signal fc_udp_size : std_logic_vector(15 downto 0);\r
-signal max_frame_size : std_logic_vector(15 downto 0);\r
-signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term\r
-signal debug : std_logic_vector(63 downto 0);\r
-signal pc_ready : std_logic;\r
-\r
-signal pc_sub_size : std_logic_vector(31 downto 0);\r
-signal pc_trig_nr : std_logic_vector(31 downto 0);\r
-signal rst_after_sub_comb : std_logic; -- gk 08.04.10\r
-signal rst_after_sub : std_logic; -- gk 08.04.10\r
-signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10\r
-signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10\r
-signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10\r
-\r
--- gk 26.07.10\r
-signal load_eod : std_logic;\r
-signal load_eod_q : std_logic;\r
-\r
-begin\r
-\r
--- Fakes\r
---debug <= (others => '0');\r
-\r
-my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order\r
-load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10\r
-\r
-all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging\r
-sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging\r
-my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging\r
-\r
-max_frame_size <= PC_MAX_FRAME_SIZE_IN;\r
-\r
--- Ready signal for PacketConstructor\r
-pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0';\r
-\r
--- store event information on Start_of_Subevent\r
-THE_EVT_INFO_STORE_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if (RESET = '1') then -- gk 31.05.10\r
- pc_sub_size <= (others => '0');\r
- pc_trig_nr <= (others => '0');\r
- elsif( PC_START_OF_SUB_IN = '1' ) then\r
- pc_sub_size <= PC_SUB_SIZE_IN;\r
- pc_trig_nr <= PC_TRIG_NR_IN;\r
- end if;\r
- end if;\r
-end process;\r
-\r
--- Data FIFO for incoming packet data from IPU buffer\r
--- gk 26.07.10\r
-DATA_FIFO : fifo_64kx9\r
-port map(\r
- Data(7 downto 0) => PC_DATA_IN,\r
- Data(8) => PC_END_OF_DATA_IN,\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => df_wr_en,\r
- RdEn => df_rd_en,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q(7 downto 0) => df_q,\r
- Q(8) => load_eod,\r
- Empty => df_empty,\r
- Full => df_full\r
-);\r
-\r
-LOAD_EOD_PROC : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- load_eod_q <= '0';\r
- else\r
- load_eod_q <= load_eod;\r
- end if;\r
- end if;\r
-end process LOAD_EOD_PROC;\r
-\r
--- Write enable for the data FIFO\r
--- !!!combinatorial signal!!!\r
--- could be avoided as IPU2GBE does only send data in case of PC_READY.\r
-df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) \r
- else '0';\r
-\r
--- Output register for data FIFO\r
-dfQProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- df_q_reg <= df_q;\r
- end if;\r
-end process dfQProc;\r
-\r
--- Construction state machine\r
-constructMachineProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- constructCurrentState <= CIDLE;\r
- else\r
- constructCurrentState <= constructNextState;\r
- end if;\r
- end if;\r
-end process constructMachineProc;\r
-\r
-constructMachine : process(constructCurrentState, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr)\r
-begin\r
- case constructCurrentState is\r
- when CIDLE =>\r
- constr_state <= x"0";\r
- if( PC_WR_EN_IN = '1' ) then\r
- constructNextState <= SAVE_DATA;\r
- else\r
- constructNextState <= CIDLE;\r
- end if;\r
- when SAVE_DATA =>\r
- constr_state <= x"1";\r
- if( PC_END_OF_DATA_IN = '1' ) then\r
- constructNextState <= WAIT_FOR_LOAD;\r
- else\r
- constructNextState <= SAVE_DATA;\r
- end if;\r
- when WAIT_FOR_LOAD =>\r
- constr_state <= x"2";\r
- if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted\r
- constructNextState <= CIDLE;\r
- else\r
- constructNextState <= WAIT_FOR_LOAD;\r
- end if;\r
- when others =>\r
- constr_state <= x"f";\r
- constructNextState <= CIDLE;\r
- end case;\r
-end process constructMachine;\r
-\r
---***********************\r
--- SIZE COUNTERS FOR SAVING SIDE\r
---***********************\r
-\r
--- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size\r
--- that's why they are removed if pc_padding flag is asserted\r
-sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0')\r
- else (x"c" + pc_sub_size); -- subevent headers + data\r
-\r
--- BUG HERE BUG HERE BUG HERE BUG HERE\r
--- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents\r
-queueSizeProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
- queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination\r
- elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then\r
- queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers\r
- end if;\r
- end if;\r
-end process queueSizeProc;\r
-\r
-\r
---***********************\r
--- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION\r
---***********************\r
-\r
-loadMachineProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- loadCurrentState <= LIDLE;\r
- else\r
- loadCurrentState <= loadNextState;\r
- end if;\r
- end if;\r
-end process loadMachineProc;\r
-\r
-loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty,\r
- sub_bytes_loaded, sub_size_loaded, size_left, FC_H_READY_IN, max_frame_size, \r
- bytes_loaded, divide_position, PC_DELAY_IN, delay_ctr, load_eod_q)\r
-begin\r
- case loadCurrentState is\r
- when LIDLE =>\r
- load_state <= x"0";\r
- if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then\r
- loadNextState <= WAIT_FOR_FC;\r
- else\r
- loadNextState <= LIDLE;\r
- end if;\r
- when WAIT_FOR_FC =>\r
- load_state <= x"1";\r
- if (FC_H_READY_IN = '1') then\r
- loadNextState <= PUT_Q_LEN;\r
- else\r
- loadNextState <= WAIT_FOR_FC;\r
- end if;\r
- when PUT_Q_LEN =>\r
- load_state <= x"2";\r
- if (all_int_ctr = 3) then\r
- loadNextState <= PUT_Q_DEC;\r
- else\r
- loadNextState <= PUT_Q_LEN;\r
- end if;\r
- when PUT_Q_DEC =>\r
- load_state <= x"3";\r
- if (all_int_ctr = 3) then\r
- loadNextState <= LOAD_SUB;\r
- else\r
- loadNextState <= PUT_Q_DEC;\r
- end if;\r
- when LOAD_SUB =>\r
- load_state <= x"4";\r
- if (bytes_loaded = max_frame_size - 1) then\r
- loadNextState <= DIVIDE;\r
- elsif (all_int_ctr = 15) then\r
- loadNextState <= PREP_DATA;\r
- else\r
- loadNextState <= LOAD_SUB;\r
- end if;\r
- when PREP_DATA =>\r
- load_state <= x"5";\r
- loadNextState <= LOAD_DATA;\r
- when LOAD_DATA =>\r
- load_state <= x"6";\r
- if (bytes_loaded = max_frame_size - 1) then\r
- loadNextState <= DIVIDE;\r
- -- gk 26.07.10\r
- -- close packet after one event loaded\r
- elsif (load_eod_q = '1') then\r
- loadNextState <= LOAD_TERM;\r
--- elsif (sub_bytes_loaded = sub_size_loaded) then -- if all subevent bytes are loaded\r
--- if (size_left = x"00000021") then -- and there is no more data, only termination left\r
--- -- gk 21.07.10\r
--- if (PC_SKIP_TERM_IN = '0') then\r
--- loadNextState <= LOAD_TERM; -- add termination and close packet\r
--- else\r
--- loadNextState <= CLEANUP;\r
--- end if;\r
--- else -- there is more data in fifo\r
--- loadNextState <= LOAD_SUB; -- add another subevent\r
--- end if;\r
- else\r
- loadNextState <= LOAD_DATA;\r
- end if;\r
- when DIVIDE =>\r
- load_state <= x"7";\r
- if (FC_H_READY_IN = '1') then\r
- if (divide_position = "00") then\r
- loadNextState <= PREP_DATA;\r
- elsif (divide_position = "01") then\r
- loadNextState <= LOAD_SUB;\r
- else\r
- loadNextState <= LOAD_TERM;\r
- end if;\r
- else\r
- loadNextState <= DIVIDE;\r
- end if;\r
- when LOAD_TERM =>\r
- load_state <= x"8";\r
- if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then\r
- loadNextState <= DIVIDE;\r
- elsif (all_int_ctr = 31) then\r
- loadNextState <= CLEANUP;\r
- else\r
- loadNextState <= LOAD_TERM;\r
- end if;\r
- -- gk 28.04.10\r
- when CLEANUP =>\r
- load_state <= x"9";\r
- if (PC_DELAY_IN = x"0000_0000") then\r
- loadNextState <= LIDLE;\r
- else\r
- loadNextState <= DELAY;\r
- end if;\r
- -- gk 28.04.10\r
- when DELAY =>\r
- load_state <= x"a";\r
- if (delay_ctr = x"0000_0000") then\r
- loadNextState <= LIDLE;\r
- else\r
- loadNextState <= DELAY;\r
- end if;\r
- when others =>\r
- load_state <= x"f";\r
- loadNextState <= LIDLE;\r
- end case;\r
-end process loadMachine;\r
-\r
-dividePositionProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- divide_position <= "00";\r
- elsif (bytes_loaded = max_frame_size - 1) then\r
- if (loadCurrentState = LIDLE) then\r
- divide_position <= "00";\r
- elsif (loadCurrentState = LOAD_DATA) then\r
- -- gk 26.07.10\r
- if (load_eod_q = '1') then -- if termination is about to be loaded divide on term\r
- divide_position <= "11";\r
- else\r
- divide_position <= "00"; -- still data loaded divide on data\r
--- if (sub_bytes_loaded = sub_size_loaded) and (size_left = x"00000021") then\r
--- divide_position <= "11";\r
--- elsif (sub_bytes_loaded = sub_size_loaded) and (size_left /= x"00000021") then\r
--- divide_position <= "01";\r
--- else\r
--- divide_position <= "00";\r
- end if;\r
- elsif (loadCurrentState = LOAD_SUB) then\r
- if (all_int_ctr = 15) then\r
- divide_position <= "00";\r
- else\r
- divide_position <= "01";\r
- end if;\r
- elsif (loadCurrentState = LOAD_TERM) then\r
- divide_position <= "11";\r
- end if;\r
- end if;\r
- end if;\r
-end process dividePositionProc;\r
-\r
-allIntCtrProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then -- gk 31.05.10\r
- all_int_ctr <= 0;\r
- else\r
- case loadCurrentState is\r
- \r
- when LIDLE => all_int_ctr <= 0;\r
- \r
- when WAIT_FOR_FC => all_int_ctr <= 0;\r
- \r
- when PUT_Q_LEN =>\r
- if (all_int_ctr = 3) then\r
- all_int_ctr <= 0;\r
- else\r
- all_int_ctr <= all_int_ctr + 1;\r
- end if;\r
- \r
- when PUT_Q_DEC =>\r
- if (all_int_ctr = 3) then\r
- all_int_ctr <= 0;\r
- else\r
- all_int_ctr <= all_int_ctr + 1;\r
- end if;\r
- \r
- when LOAD_SUB =>\r
- if (all_int_ctr = 15) then\r
- all_int_ctr <= 0;\r
- else\r
- all_int_ctr <= all_int_ctr + 1;\r
- end if;\r
- \r
- when LOAD_DATA => all_int_ctr <= 0;\r
- \r
- when LOAD_TERM =>\r
- if (all_int_ctr = 31) then\r
- all_int_ctr <= 0;\r
- else\r
- all_int_ctr <= all_int_ctr + 1;\r
- end if;\r
- \r
- when DIVIDE => null; --all_int_ctr <= all_int_ctr;\r
- \r
- when CLEANUP => all_int_ctr <= 0;\r
- \r
- when PREP_DATA => all_int_ctr <= 0;\r
- \r
- when DELAY => all_int_ctr <= 0;\r
- end case;\r
- end if;\r
- end if;\r
-end process allIntCtrProc;\r
-\r
-dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, \r
- sub_size_loaded, all_int_ctr, RESET, load_eod, load_eod_q)\r
-begin\r
- if (RESET = '1') then -- gk 31.05.10\r
- df_rd_en <= '0';\r
- elsif (loadCurrentState = LOAD_DATA) then\r
--- if (bytes_loaded >= max_frame_size - x"1") then\r
--- df_rd_en <= '0';\r
--- elsif (sub_bytes_loaded >= sub_size_loaded) then\r
--- df_rd_en <= '0';\r
- if (bytes_loaded = max_frame_size - x"1") then\r
- df_rd_en <= '0';\r
- -- gk 26.07.10\r
- --elsif (load_eod = '1') or (load_eod_q = '1') then\r
- elsif (load_eod_q = '1') then\r
- df_rd_en <= '0';\r
--- elsif (sub_bytes_loaded = sub_size_loaded) then\r
--- df_rd_en <= '0';\r
- else\r
- df_rd_en <= '1';\r
- end if;\r
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then\r
- df_rd_en <= '1';\r
- elsif (loadCurrentState = PREP_DATA) then\r
- df_rd_en <= '1';\r
- else\r
- df_rd_en <= '0';\r
- end if;\r
-end process dfRdEnProc;\r
-\r
-shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET)\r
-begin\r
- if (RESET = '1') then -- gk 31.05.10\r
- shf_rd_en <= '0';\r
- elsif (loadCurrentState = LOAD_SUB) then\r
- shf_rd_en <= '1';\r
- elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then\r
- shf_rd_en <= '1';\r
- elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then\r
- shf_rd_en <= '1';\r
- else\r
- shf_rd_en <= '0';\r
- end if;\r
-end process shfRdEnProc;\r
-\r
-\r
-fcWrEnProc : process(loadCurrentState, RESET)\r
-begin\r
- if (RESET = '1') then -- gk 31.05.10\r
- fc_wr_en <= '0';\r
- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then\r
- fc_wr_en <= '1';\r
- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then\r
- fc_wr_en <= '1';\r
- else\r
- fc_wr_en <= '0';\r
- end if;\r
-end process fcWrEnProc;\r
-\r
--- was all_int_ctr\r
-fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr)\r
-begin\r
- case loadCurrentState is\r
- when LIDLE => fc_data <= x"af";\r
- when WAIT_FOR_FC => fc_data <= x"bf";\r
- -- gk 08.04.10 my_int_ctr changed to load_int_ctr\r
- when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8);\r
- when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8);\r
- when LOAD_SUB => fc_data <= shf_q;\r
- when PREP_DATA => fc_data <= df_q_reg;\r
- when LOAD_DATA => fc_data <= df_q_reg;\r
- when LOAD_TERM => fc_data <= shf_q;\r
- when DIVIDE => fc_data <= x"cf";\r
- when CLEANUP => fc_data <= x"df";\r
- when others => fc_data <= x"00";\r
- end case;\r
-end process fcDataProc;\r
-\r
--- delay counters\r
--- gk 28.04.10\r
-DELAY_CTR_PROC : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if ((RESET = '1') or (loadCurrentState = LIDLE)) then\r
- delay_ctr <= PC_DELAY_IN;\r
- elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then\r
- delay_ctr <= delay_ctr - x"1";\r
- end if;\r
- end if;\r
-end process DELAY_CTR_PROC;\r
-\r
--- gk 28.04.10\r
-TICKS_CTR_PROC : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then\r
- ticks_ctr <= x"00";\r
- elsif (loadCurrentState = DELAY) then\r
- ticks_ctr <= ticks_ctr + x"1";\r
- end if;\r
- end if;\r
-end process TICKS_CTR_PROC;\r
-\r
-\r
---***********************\r
--- SIZE COUNTERS FOR LOADING SIDE\r
---***********************\r
-\r
-queue_size_temp <= queue_size - x"20"; -- size of data without termination\r
-\r
--- gk 08.04.10\r
-rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or\r
- ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) \r
- else '0';\r
-\r
--- gk 08.04.10\r
-RST_AFTER_SUB_PROC : process(CLK)\r
-begin\r
- if(rising_edge(CLK)) then\r
- if(RESET = '1') then\r
- rst_after_sub <= '0';\r
- else\r
- rst_after_sub <= rst_after_sub_comb;\r
- end if;\r
- end if;\r
-end process RST_AFTER_SUB_PROC;\r
-\r
--- counts all bytes loaded to divide data into frames\r
-bytesLoadedProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then\r
- bytes_loaded <= x"0000";\r
- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then\r
- bytes_loaded <= bytes_loaded + x"1";\r
- end if;\r
- end if;\r
-end process bytesLoadedProc;\r
-\r
--- size of subevent loaded from memory\r
-subSizeLoadedProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10\r
- sub_size_loaded <= x"00000000";\r
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then\r
- -- was all_int_ctr\r
- -- gk 08.04.10 my_int_ctr changed to load_int_ctr\r
- sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q;\r
- -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo\r
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then\r
- sub_size_loaded <= sub_size_loaded + x"4";\r
- end if;\r
- end if;\r
-end process subSizeLoadedProc;\r
-\r
--- counts only raw data bytes being loaded\r
-subBytesLoadedProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10\r
- sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count\r
- elsif (loadCurrentState = LOAD_DATA) then\r
- sub_bytes_loaded <= sub_bytes_loaded + x"1";\r
- end if;\r
- end if;\r
-end process subBytesLoadedProc;\r
-\r
--- counts the size of the large udp packet\r
-actualPacketProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
- actual_packet_size <= x"0008";\r
- elsif (fc_wr_en = '1') then\r
- actual_packet_size <= actual_packet_size + x"1";\r
- end if;\r
- end if;\r
-end process actualPacketProc;\r
-\r
-actualQueueSizeProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
- actual_queue_size <= (others => '0');\r
- elsif (loadCurrentState = LIDLE) then\r
- actual_queue_size <= queue_size;\r
- end if;\r
- end if;\r
-end process actualQueueSizeProc;\r
-\r
--- amount of bytes left to send in current packet\r
-sizeLeftProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
- size_left <= (others => '0');\r
- elsif (loadCurrentState = LIDLE) then\r
- size_left <= queue_size;\r
- elsif (fc_wr_en = '1') then\r
- size_left <= size_left - 1;\r
- end if;\r
- end if;\r
-end process sizeLeftProc;\r
-\r
--- HOT FIX: don't rely on CTS information, count the packets on your own.\r
--- In this case, we increment the fragmented packet ID with EOD from ipu2gbe.\r
-THE_FC_IDENT_COUNTER_PROC: process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- fc_ident <= (others => '0');\r
- elsif (PC_END_OF_DATA_IN = '1') then\r
- fc_ident <= fc_ident + 1;\r
- end if;\r
- end if;\r
-end process THE_FC_IDENT_COUNTER_PROC;\r
-\r
-fc_flags_offset(15 downto 14) <= "00";\r
-\r
-moreFragmentsProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
- fc_flags_offset(13) <= '0';\r
- elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then\r
- if ((actual_queue_size - actual_packet_size) < max_frame_size) then\r
- fc_flags_offset(13) <= '0'; -- no more fragments\r
- else\r
- fc_flags_offset(13) <= '1'; -- more fragments\r
- end if;\r
- end if;\r
- end if;\r
-end process moreFragmentsProc;\r
-\r
-eodProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- fc_eod <= '0';\r
- elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then\r
- fc_eod <= '1';\r
- elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then\r
- fc_eod <= '1';\r
- elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then\r
- fc_eod <= '1';\r
- else\r
- fc_eod <= '0';\r
- end if;\r
- end if;\r
-end process eodProc;\r
-\r
-sodProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- fc_sod <= '0';\r
- elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then\r
- fc_sod <= '1';\r
- elsif (loadCurrentState = DIVIDE) and (FC_READY_IN = '1') then\r
- fc_sod <= '1';\r
- else\r
- fc_sod <= '0';\r
- end if;\r
- end if;\r
-end process sodProc;\r
-\r
-offsetProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
- fc_flags_offset(12 downto 0) <= (others => '0');\r
- elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) then\r
- fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3);\r
- end if;\r
- end if;\r
-end process offsetProc;\r
-\r
-fcIPSizeProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET= '1') then\r
- fc_ip_size <= (others => '0');\r
- elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then\r
- if (size_left >= max_frame_size) then\r
- fc_ip_size <= max_frame_size;\r
- else\r
- fc_ip_size <= size_left(15 downto 0);\r
- end if;\r
- end if;\r
- end if;\r
-end process fcIPSizeProc;\r
-\r
-fcUDPSizeProc : process(CLK)\r
- begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- fc_udp_size <= (others => '0');\r
- elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then\r
- fc_udp_size <= queue_size(15 downto 0);\r
- end if;\r
- end if;\r
-end process fcUDPSizeProc;\r
-\r
-\r
---***********************\r
--- SUBEVENT HEADERS WRITE AND READ\r
---***********************\r
-\r
-SUBEVENT_HEADERS_FIFO : fifo_2048x8\r
-port map(\r
- Data => shf_data,\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => shf_wr_en,\r
- RdEn => shf_rd_en,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q => shf_q,\r
- Empty => shf_empty,\r
- Full => shf_full\r
-);\r
-\r
--- write enable for SHF \r
-shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA))\r
- else '0';\r
-\r
--- data multiplexing for SHF (convert 32bit LWs to 8bit)\r
--- CHANGED. \r
--- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC.\r
-shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, \r
- pc_trig_nr, my_int_ctr, fc_data)\r
-begin\r
- case saveSubCurrentState is\r
- when SIDLE => shf_data <= x"ac";\r
- when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
- when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
- when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
- when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
- when SAVE_TERM => shf_data <= fc_data;\r
- when others => shf_data <= x"00";\r
- end case;\r
-end process shfDataProc;\r
-\r
-saveSubMachineProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- saveSubCurrentState <= SIDLE;\r
- else\r
- saveSubCurrentState <= saveSubNextState;\r
- end if;\r
- end if;\r
-end process saveSubMachineProc;\r
-\r
-saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, FC_H_READY_IN)\r
-begin\r
- case saveSubCurrentState is\r
- when SIDLE =>\r
- save_state <= x"0";\r
- if (PC_START_OF_SUB_IN = '1') then\r
- saveSubNextState <= SAVE_SIZE;\r
- -- this branch is dangerous!\r
- elsif (loadCurrentState = WAIT_FOR_FC) and (FC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len\r
- saveSubNextState <= SAVE_TERM;\r
- else\r
- saveSubNextState <= SIDLE;\r
- end if;\r
- when SAVE_SIZE =>\r
- save_state <= x"1";\r
- if (sub_int_ctr = 3) then\r
- saveSubNextState <= SAVE_DECODING;\r
- else\r
- saveSubNextState <= SAVE_SIZE;\r
- end if;\r
- when SAVE_DECODING =>\r
- save_state <= x"2";\r
- if (sub_int_ctr = 3) then\r
- saveSubNextState <= SAVE_ID;\r
- else\r
- saveSubNextState <= SAVE_DECODING;\r
- end if;\r
- when SAVE_ID =>\r
- save_state <= x"3";\r
- if (sub_int_ctr = 3) then\r
- saveSubNextState <= SAVE_TRIG_NR;\r
- else\r
- saveSubNextState <= SAVE_ID;\r
- end if;\r
- when SAVE_TRIG_NR =>\r
- save_state <= x"4";\r
- if (sub_int_ctr = 3) then\r
- saveSubNextState <= SIDLE;\r
- else\r
- saveSubNextState <= SAVE_TRIG_NR;\r
- end if;\r
- when SAVE_TERM =>\r
- save_state <= x"5";\r
- if (sub_int_ctr = 31) then\r
- saveSubNextState <= SIDLE;\r
- else\r
- saveSubNextState <= SAVE_TERM;\r
- end if;\r
- when others =>\r
- save_state <= x"f";\r
- saveSubNextState <= SIDLE;\r
- end case;\r
-end process;\r
-\r
--- This counter is used for breaking down 32bit information words into 8bit bytes for \r
--- storing them in the SHF.\r
--- It is also used for the termination 32byte sequence.\r
-subIntProc: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (saveSubCurrentState = SIDLE) then\r
- sub_int_ctr <= 0;\r
- elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then\r
- sub_int_ctr <= 0;\r
- elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then\r
- sub_int_ctr <= 0;\r
- elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then\r
- sub_int_ctr <= sub_int_ctr + 1;\r
- end if;\r
- end if;\r
-end process subIntProc;\r
-\r
-debug(3 downto 0) <= constr_state;\r
-debug(7 downto 4) <= save_state;\r
-debug(11 downto 8) <= load_state;\r
-debug(27 downto 12) <= queue_size(15 downto 0);\r
-debug(28) <= df_full;\r
-debug(29) <= df_empty;\r
-debug(30) <= shf_full;\r
-debug(31) <= shf_empty;\r
-\r
-debug(47 downto 32) <= size_left(15 downto 0);\r
-debug(52 downto 48) <= all_ctr;\r
-debug(53) <= pc_ready;\r
-\r
--- outputs\r
-PC_READY_OUT <= pc_ready;\r
-FC_WR_EN_OUT <= fc_wr_en;\r
-FC_DATA_OUT <= fc_data;\r
-FC_IP_SIZE_OUT <= fc_ip_size;\r
-FC_UDP_SIZE_OUT <= fc_udp_size;\r
-FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0);\r
-FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8);\r
-FC_FLAGS_OFFSET_OUT <= fc_flags_offset;\r
-FC_SOD_OUT <= fc_sod;\r
-FC_EOD_OUT <= fc_eod;\r
-\r
-DEBUG_OUT <= debug;\r
-\r
-end trb_net16_gbe_packet_constr;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-use IEEE.std_logic_arith.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.trb_net16_hub_func.all;\r
-\r
-entity trb_net16_gbe_packet_constr is\r
-port(\r
- RESET : in std_logic;\r
- CLK : in std_logic;\r
- MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10\r
- -- ports for user logic\r
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic\r
- PC_DATA_IN : in std_logic_vector(7 downto 0);\r
- PC_READY_OUT : out std_logic;\r
- PC_START_OF_SUB_IN : in std_logic;\r
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10\r
- PC_END_OF_DATA_IN : in std_logic;\r
- PC_TRANSMIT_ON_OUT : out std_logic;\r
- -- queue and subevent layer headers\r
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap\r
- PC_PADDING_IN : in std_logic; -- gk 29.03.10\r
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap\r
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap\r
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!\r
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap\r
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP\r
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10\r
- -- FrameConstructor ports\r
- TC_WR_EN_OUT : out std_logic;\r
- TC_DATA_OUT : out std_logic_vector(7 downto 0);\r
- TC_H_READY_IN : in std_logic;\r
- TC_READY_IN : in std_logic;\r
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);\r
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);\r
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);\r
- TC_SOD_OUT : out std_logic;\r
- TC_EOD_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
-);\r
-end trb_net16_gbe_packet_constr;\r
-\r
-architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is\r
-\r
--- attribute HGROUP : string;\r
--- attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_packet_constr";\r
-\r
-component fifo_64kx9\r
-port (\r
- Data : in std_logic_vector(8 downto 0); \r
- WrClock : in std_logic; \r
- RdClock : in std_logic; \r
- WrEn : in std_logic; \r
- RdEn : in std_logic; \r
- Reset : in std_logic; \r
- RPReset : in std_logic; \r
- Q : out std_logic_vector(8 downto 0); \r
- Empty : out std_logic; \r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
--- FIFO for SubEventHeader information\r
-component fifo_16kx8 is\r
-port (\r
- Data : in std_logic_vector(7 downto 0); \r
- WrClock : in std_logic; \r
- RdClock : in std_logic; \r
- WrEn : in std_logic; \r
- RdEn : in std_logic; \r
- Reset : in std_logic; \r
- RPReset : in std_logic; \r
- Q : out std_logic_vector(7 downto 0); \r
- Empty : out std_logic; \r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
-signal df_wr_en : std_logic;\r
-signal df_rd_en : std_logic;\r
-signal df_q : std_logic_vector(7 downto 0);\r
-signal df_q_reg : std_logic_vector(7 downto 0);\r
-signal df_empty : std_logic;\r
-signal df_full : std_logic;\r
-\r
-signal fc_data : std_logic_vector(7 downto 0);\r
-signal fc_wr_en : std_logic;\r
-signal fc_sod : std_logic;\r
-signal fc_eod : std_logic;\r
-signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter!\r
-signal fc_flags_offset : std_logic_vector(15 downto 0);\r
-\r
-signal shf_data : std_logic_vector(7 downto 0);\r
-signal shf_wr_en : std_logic;\r
-signal shf_rd_en : std_logic;\r
-signal shf_q : std_logic_vector(7 downto 0);\r
-signal shf_empty : std_logic;\r
-signal shf_full : std_logic;\r
-\r
-type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD);\r
-signal constructCurrentState, constructNextState : constructStates;\r
-signal constr_state : std_logic_vector(3 downto 0);\r
-signal all_int_ctr : integer range 0 to 31;\r
-signal all_ctr : std_logic_vector(4 downto 0);\r
-\r
-type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM);\r
-signal saveSubCurrentState, saveSubNextState : saveSubStates;\r
-signal save_state : std_logic_vector(3 downto 0);\r
-signal sub_int_ctr : integer range 0 to 31;\r
-signal sub_ctr : std_logic_vector(4 downto 0);\r
-signal my_int_ctr : integer range 0 to 3;\r
-signal my_ctr : std_logic_vector(1 downto 0);\r
-\r
-type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY);\r
-signal loadCurrentState, loadNextState: loadStates;\r
-signal load_state : std_logic_vector(3 downto 0);\r
-\r
-signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination\r
-signal queue_size_temp : std_logic_vector(31 downto 0);\r
-signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid\r
-signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame\r
-signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf\r
-signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted\r
-signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent \r
-signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet\r
-signal size_left : std_logic_vector(31 downto 0);\r
-signal fc_ip_size : std_logic_vector(15 downto 0);\r
-signal fc_udp_size : std_logic_vector(15 downto 0);\r
-signal max_frame_size : std_logic_vector(15 downto 0);\r
-signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term\r
-signal debug : std_logic_vector(63 downto 0);\r
-signal pc_ready : std_logic;\r
-\r
-signal pc_sub_size : std_logic_vector(31 downto 0);\r
-signal pc_trig_nr : std_logic_vector(31 downto 0);\r
-signal rst_after_sub_comb : std_logic; -- gk 08.04.10\r
-signal rst_after_sub : std_logic; -- gk 08.04.10\r
-signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10\r
-signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10\r
-signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10\r
-\r
--- gk 26.07.10\r
-signal load_eod : std_logic;\r
-signal load_eod_q : std_logic;\r
-\r
--- gk 07.10.10\r
-signal df_eod : std_logic;\r
-\r
--- gk 04.12.10\r
-signal first_sub_in_multi : std_logic;\r
-signal from_divide_state : std_logic;\r
-signal disable_prep : std_logic;\r
-\r
-begin\r
-\r
-\r
---PC_TRANSMIT_ON_OUT <= '1' when constructCurrentState = WAIT_FOR_LOAD else '0';\r
-PC_TRANSMIT_ON_OUT <= '0';\r
-\r
--- my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order\r
--- load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10\r
--- \r
--- all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging\r
--- sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging\r
--- my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging\r
--- \r
--- max_frame_size <= PC_MAX_FRAME_SIZE_IN;\r
--- \r
--- -- Ready signal for PacketConstructor\r
--- pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0';\r
-pc_ready <= '0';\r
-\r
--- store event information on Start_of_Subevent\r
--- THE_EVT_INFO_STORE_PROC: process( CLK )\r
--- begin\r
--- if( rising_edge(CLK) ) then\r
--- if (RESET = '1') then -- gk 31.05.10\r
--- pc_sub_size <= (others => '0');\r
--- pc_trig_nr <= (others => '0');\r
--- elsif( PC_START_OF_SUB_IN = '1' ) then\r
--- pc_sub_size <= PC_SUB_SIZE_IN;\r
--- pc_trig_nr <= PC_TRIG_NR_IN;\r
--- end if;\r
--- end if;\r
--- end process;\r
--- \r
--- -- gk 07.10.10\r
--- df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1'))\r
--- or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1'))\r
--- else '0';\r
-\r
--- Data FIFO for incoming packet data from IPU buffer\r
--- gk 26.07.10\r
--- DATA_FIFO : fifo_64kx9\r
--- port map(\r
--- Data(7 downto 0) => PC_DATA_IN,\r
--- Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 07.10.10\r
--- WrClock => CLK,\r
--- RdClock => CLK,\r
--- WrEn => df_wr_en,\r
--- RdEn => df_rd_en,\r
--- Reset => RESET,\r
--- RPReset => RESET,\r
--- Q(7 downto 0) => df_q,\r
--- Q(8) => load_eod,\r
--- Empty => df_empty,\r
--- Full => df_full\r
--- );\r
-\r
--- LOAD_EOD_PROC : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- load_eod_q <= '0';\r
--- else\r
--- load_eod_q <= load_eod;\r
--- end if;\r
--- end if;\r
--- end process LOAD_EOD_PROC;\r
--- \r
--- -- Write enable for the data FIFO\r
--- -- !!!combinatorial signal!!!\r
--- -- could be avoided as IPU2GBE does only send data in case of PC_READY.\r
--- df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) \r
--- else '0';\r
--- \r
--- -- Output register for data FIFO\r
--- dfQProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- df_q_reg <= df_q;\r
--- end if;\r
--- end process dfQProc;\r
--- \r
--- -- Construction state machine\r
--- constructMachineProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- constructCurrentState <= CIDLE;\r
--- else\r
--- constructCurrentState <= constructNextState;\r
--- end if;\r
--- end if;\r
--- end process constructMachineProc;\r
--- \r
--- constructMachine : process(constructCurrentState, PC_START_OF_SUB_IN, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr)\r
--- begin\r
--- case constructCurrentState is\r
--- when CIDLE =>\r
--- constr_state <= x"0";\r
--- --if( PC_WR_EN_IN = '1' ) then\r
--- -- gk 04.12.10\r
--- if (PC_START_OF_SUB_IN = '1') then\r
--- \r
--- constructNextState <= SAVE_DATA;\r
--- else\r
--- constructNextState <= CIDLE;\r
--- end if;\r
--- when SAVE_DATA =>\r
--- constr_state <= x"1";\r
--- if( PC_END_OF_DATA_IN = '1' ) then\r
--- constructNextState <= WAIT_FOR_LOAD;\r
--- else\r
--- constructNextState <= SAVE_DATA;\r
--- end if;\r
--- when WAIT_FOR_LOAD =>\r
--- constr_state <= x"2";\r
--- if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted\r
--- constructNextState <= CIDLE;\r
--- else\r
--- constructNextState <= WAIT_FOR_LOAD;\r
--- end if;\r
--- when others =>\r
--- constr_state <= x"f";\r
--- constructNextState <= CIDLE;\r
--- end case;\r
--- end process constructMachine;\r
-\r
---***********************\r
--- SIZE COUNTERS FOR SAVING SIDE\r
---***********************\r
-\r
--- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size\r
--- that's why they are removed if pc_padding flag is asserted\r
--- sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0')\r
--- else (x"c" + pc_sub_size); -- subevent headers + data\r
--- \r
--- -- BUG HERE BUG HERE BUG HERE BUG HERE\r
--- -- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents\r
--- queueSizeProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- --if (RESET = '1') or (loadCurrentState = PUT_Q_DEC) then -- gk 07.10.10 -- (loadCurrentState = CLEANUP) then\r
--- if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
--- queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination\r
--- elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then\r
--- queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers\r
--- end if;\r
--- end if;\r
--- end process queueSizeProc;\r
-\r
-\r
---***********************\r
--- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION\r
---***********************\r
-\r
--- loadMachineProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- loadCurrentState <= LIDLE;\r
--- else\r
--- loadCurrentState <= loadNextState;\r
--- end if;\r
--- end if;\r
--- end process loadMachineProc;\r
--- \r
--- loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty,\r
--- sub_bytes_loaded, sub_size_loaded, size_left, TC_H_READY_IN,\r
--- max_frame_size, bytes_loaded, divide_position, PC_DELAY_IN,\r
--- delay_ctr, load_eod_q, MULT_EVT_ENABLE_IN)\r
--- begin\r
--- case loadCurrentState is\r
--- when LIDLE =>\r
--- load_state <= x"0";\r
--- if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then\r
--- loadNextState <= WAIT_FOR_FC;\r
--- else\r
--- loadNextState <= LIDLE;\r
--- end if;\r
--- when WAIT_FOR_FC =>\r
--- load_state <= x"1";\r
--- if (TC_H_READY_IN = '1') then\r
--- loadNextState <= PUT_Q_LEN;\r
--- else\r
--- loadNextState <= WAIT_FOR_FC;\r
--- end if;\r
--- when PUT_Q_LEN =>\r
--- load_state <= x"2";\r
--- if (all_int_ctr = 3) then\r
--- loadNextState <= PUT_Q_DEC;\r
--- else\r
--- loadNextState <= PUT_Q_LEN;\r
--- end if;\r
--- when PUT_Q_DEC =>\r
--- load_state <= x"3";\r
--- if (all_int_ctr = 3) then\r
--- loadNextState <= LOAD_SUB;\r
--- else\r
--- loadNextState <= PUT_Q_DEC;\r
--- end if;\r
--- when LOAD_SUB =>\r
--- load_state <= x"4";\r
--- if (bytes_loaded = max_frame_size - 1) then\r
--- loadNextState <= DIVIDE;\r
--- elsif (all_int_ctr = 15) then\r
--- loadNextState <= PREP_DATA;\r
--- else\r
--- loadNextState <= LOAD_SUB;\r
--- end if;\r
--- when PREP_DATA =>\r
--- load_state <= x"5";\r
--- loadNextState <= LOAD_DATA;\r
--- when LOAD_DATA =>\r
--- load_state <= x"6";\r
--- -- if (bytes_loaded = max_frame_size - 1) then\r
--- -- loadNextState <= DIVIDE;\r
--- -- -- gk 07.10.10\r
--- -- elsif (MULT_EVT_ENABLE_IN = '1') then\r
--- -- if (size_left = x"0000_0023") then\r
--- -- loadNextState <= LOAD_TERM;\r
--- -- elsif (load_eod_q = '1') then\r
--- -- loadNextState <= LOAD_SUB;\r
--- -- else\r
--- -- loadNextState <= LOAD_DATA;\r
--- -- end if;\r
--- -- else\r
--- -- if (load_eod_q = '1') then\r
--- -- loadNextState <= LOAD_TERM;\r
--- -- else\r
--- -- loadNextState <= LOAD_DATA;\r
--- -- end if;\r
--- -- end if;\r
--- if (bytes_loaded = max_frame_size - 1) then\r
--- loadNextState <= DIVIDE;\r
--- -- gk 07.10.10\r
--- elsif (load_eod_q = '1') then\r
--- if (MULT_EVT_ENABLE_IN = '1') then\r
--- if (size_left < x"0000_0030") then\r
--- loadNextState <= LOAD_TERM;\r
--- else\r
--- loadNextState <= LOAD_SUB;\r
--- end if;\r
--- else\r
--- loadNextState <= LOAD_TERM;\r
--- end if;\r
--- else\r
--- loadNextState <= LOAD_DATA;\r
--- end if;\r
--- when DIVIDE =>\r
--- load_state <= x"7";\r
--- if (TC_H_READY_IN = '1') then\r
--- if (divide_position = "00") then\r
--- loadNextState <= PREP_DATA;\r
--- elsif (divide_position = "01") then\r
--- loadNextState <= LOAD_SUB;\r
--- else\r
--- loadNextState <= LOAD_TERM;\r
--- end if;\r
--- else\r
--- loadNextState <= DIVIDE;\r
--- end if;\r
--- when LOAD_TERM =>\r
--- load_state <= x"8";\r
--- if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then\r
--- loadNextState <= DIVIDE;\r
--- elsif (all_int_ctr = 31) then\r
--- loadNextState <= CLEANUP;\r
--- else\r
--- loadNextState <= LOAD_TERM;\r
--- end if;\r
--- -- gk 28.04.10\r
--- when CLEANUP =>\r
--- load_state <= x"9";\r
--- if (PC_DELAY_IN = x"0000_0000") then\r
--- loadNextState <= LIDLE;\r
--- else\r
--- loadNextState <= DELAY;\r
--- end if;\r
--- -- gk 28.04.10\r
--- when DELAY =>\r
--- load_state <= x"a";\r
--- if (delay_ctr = x"0000_0000") then\r
--- loadNextState <= LIDLE;\r
--- else\r
--- loadNextState <= DELAY;\r
--- end if;\r
--- when others =>\r
--- load_state <= x"f";\r
--- loadNextState <= LIDLE;\r
--- end case;\r
--- end process loadMachine;\r
--- \r
--- -- gk 04.12.10\r
--- firstSubInMultiProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (loadCurrentState = LOAD_TERM) then\r
--- first_sub_in_multi <= '1';\r
--- elsif (loadCurrentState = LOAD_DATA) then\r
--- first_sub_in_multi <= '0';\r
--- end if;\r
--- end if;\r
--- end process;\r
--- \r
--- -- gk 04.12.10\r
--- fromDivideStateProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- from_divide_state <= '0';\r
--- elsif (loadCurrentState = DIVIDE) then\r
--- from_divide_state <= '1';\r
--- elsif (loadCurrentState = PREP_DATA) then\r
--- from_divide_state <= '0';\r
--- end if;\r
--- end if;\r
--- end process fromDivideStateProc;\r
--- \r
--- \r
--- dividePositionProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- divide_position <= "00";\r
--- -- elsif (bytes_loaded = max_frame_size - 1) then\r
--- -- if (loadCurrentState = LIDLE) then\r
--- -- divide_position <= "00";\r
--- -- elsif (loadCurrentState = LOAD_DATA) then\r
--- -- -- gk 07.10.10\r
--- -- if (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then\r
--- -- divide_position <= "11";\r
--- -- -- gk 07.10.10\r
--- -- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then\r
--- -- divide_position <= "01";\r
--- -- -- gk 26.07.10\r
--- -- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term\r
--- -- divide_position <= "11";\r
--- -- else\r
--- -- divide_position <= "00"; -- still data loaded divide on data\r
--- -- end if;\r
--- -- elsif (loadCurrentState = LOAD_SUB) then\r
--- -- if (all_int_ctr = 15) then\r
--- -- divide_position <= "00";\r
--- -- else\r
--- -- divide_position <= "01";\r
--- -- end if;\r
--- -- elsif (loadCurrentState = LOAD_TERM) then\r
--- -- divide_position <= "11";\r
--- -- end if;\r
--- -- end if;\r
--- elsif (bytes_loaded = max_frame_size - 1) then\r
--- if (loadCurrentState = LIDLE) then\r
--- divide_position <= "00";\r
--- disable_prep <= '0'; -- gk 05.12.10\r
--- elsif (loadCurrentState = LOAD_DATA) then\r
--- -- gk 05.12.10\r
--- -- gk 26.07.10\r
--- if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term\r
--- divide_position <= "11";\r
--- disable_prep <= '0'; -- gk 05.12.10\r
--- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then\r
--- if (size_left > x"0000_0028") then\r
--- divide_position <= "01";\r
--- disable_prep <= '0'; -- gk 05.12.10\r
--- else\r
--- divide_position <= "11";\r
--- disable_prep <= '0'; -- gk 05.12.10\r
--- end if;\r
--- else\r
--- divide_position <= "00"; -- still data loaded divide on data\r
--- disable_prep <= '1'; -- gk 05.12.10\r
--- end if;\r
--- elsif (loadCurrentState = LOAD_SUB) then\r
--- if (all_int_ctr = 15) then\r
--- divide_position <= "00";\r
--- disable_prep <= '1'; -- gk 05.12.10\r
--- else\r
--- divide_position <= "01";\r
--- disable_prep <= '0'; -- gk 05.12.10\r
--- end if;\r
--- elsif (loadCurrentState = LOAD_TERM) then\r
--- divide_position <= "11";\r
--- disable_prep <= '0'; -- gk 05.12.10\r
--- end if;\r
--- elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep\r
--- disable_prep <= '0';\r
--- end if;\r
--- \r
--- end if;\r
--- end process dividePositionProc;\r
--- \r
--- allIntCtrProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then -- gk 31.05.10\r
--- all_int_ctr <= 0;\r
--- else\r
--- case loadCurrentState is\r
--- \r
--- when LIDLE => all_int_ctr <= 0;\r
--- \r
--- when WAIT_FOR_FC => all_int_ctr <= 0;\r
--- \r
--- when PUT_Q_LEN =>\r
--- if (all_int_ctr = 3) then\r
--- all_int_ctr <= 0;\r
--- else\r
--- all_int_ctr <= all_int_ctr + 1;\r
--- end if;\r
--- \r
--- when PUT_Q_DEC =>\r
--- if (all_int_ctr = 3) then\r
--- all_int_ctr <= 0;\r
--- else\r
--- all_int_ctr <= all_int_ctr + 1;\r
--- end if;\r
--- \r
--- when LOAD_SUB =>\r
--- if (all_int_ctr = 15) then\r
--- all_int_ctr <= 0;\r
--- else\r
--- all_int_ctr <= all_int_ctr + 1;\r
--- end if;\r
--- \r
--- when LOAD_DATA => all_int_ctr <= 0;\r
--- \r
--- when LOAD_TERM =>\r
--- if (all_int_ctr = 31) then\r
--- all_int_ctr <= 0;\r
--- else\r
--- all_int_ctr <= all_int_ctr + 1;\r
--- end if;\r
--- \r
--- when DIVIDE => null;\r
--- \r
--- when CLEANUP => all_int_ctr <= 0;\r
--- \r
--- when PREP_DATA => all_int_ctr <= 0;\r
--- \r
--- when DELAY => all_int_ctr <= 0;\r
--- end case;\r
--- end if;\r
--- end if;\r
--- end process allIntCtrProc;\r
--- \r
--- dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, \r
--- sub_size_loaded, all_int_ctr, RESET, size_left, load_eod_q)\r
--- begin\r
--- if (RESET = '1') then\r
--- df_rd_en <= '0';\r
--- elsif (loadCurrentState = LOAD_DATA) then\r
--- -- if (bytes_loaded = max_frame_size - x"1") then\r
--- -- df_rd_en <= '0';\r
--- -- -- gk 07.10.10\r
--- -- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then\r
--- -- df_rd_en <= '0';\r
--- -- -- gk 07.10.10\r
--- -- elsif (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then\r
--- -- df_rd_en <= '0';\r
--- -- else\r
--- -- df_rd_en <= '1';\r
--- -- end if;\r
--- if (bytes_loaded = max_frame_size - x"1") then\r
--- df_rd_en <= '0';\r
--- -- gk 26.07.10\r
--- --elsif (load_eod = '1') or (load_eod_q = '1') then\r
--- elsif (load_eod_q = '1') then\r
--- df_rd_en <= '0';\r
--- -- elsif (sub_bytes_loaded = sub_size_loaded) then\r
--- -- df_rd_en <= '0';\r
--- else\r
--- df_rd_en <= '1';\r
--- end if;\r
--- \r
--- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then\r
--- df_rd_en <= '1';\r
--- elsif (loadCurrentState = PREP_DATA) then\r
--- df_rd_en <= '1';\r
--- else\r
--- df_rd_en <= '0';\r
--- end if;\r
--- end process dfRdEnProc;\r
--- \r
--- shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET)\r
--- begin\r
--- if (RESET = '1') then -- gk 31.05.10\r
--- shf_rd_en <= '0';\r
--- elsif (loadCurrentState = LOAD_SUB) then\r
--- shf_rd_en <= '1';\r
--- elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then\r
--- shf_rd_en <= '1';\r
--- elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then\r
--- shf_rd_en <= '1';\r
--- else\r
--- shf_rd_en <= '0';\r
--- end if;\r
--- end process shfRdEnProc;\r
--- \r
--- \r
--- -- fcWrEnProc : process(loadCurrentState, RESET)\r
--- -- begin\r
--- -- if (RESET = '1') then -- gk 31.05.10\r
--- -- fc_wr_en <= '0';\r
--- -- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then\r
--- -- fc_wr_en <= '1';\r
--- -- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then\r
--- -- fc_wr_en <= '1';\r
--- -- else\r
--- -- fc_wr_en <= '0';\r
--- -- end if;\r
--- -- end process fcWrEnProc;\r
--- fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep)\r
--- begin\r
--- if (RESET = '1') then -- gk 31.05.10\r
--- fc_wr_en <= '0';\r
--- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then\r
--- fc_wr_en <= '1';\r
--- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then\r
--- fc_wr_en <= '1';\r
--- -- gk 04.12.10\r
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then\r
--- fc_wr_en <= '1';\r
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then\r
--- fc_wr_en <= '1';\r
--- else\r
--- fc_wr_en <= '0';\r
--- end if;\r
--- end process fcWrEnProc;\r
--- \r
--- \r
--- -- was all_int_ctr\r
--- fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr)\r
--- begin\r
--- case loadCurrentState is\r
--- when LIDLE => fc_data <= x"af";\r
--- when WAIT_FOR_FC => fc_data <= x"bf";\r
--- -- gk 08.04.10 my_int_ctr changed to load_int_ctr\r
--- when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8);\r
--- when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8);\r
--- when LOAD_SUB => fc_data <= shf_q;\r
--- when PREP_DATA => fc_data <= df_q_reg;\r
--- when LOAD_DATA => fc_data <= df_q_reg;\r
--- when LOAD_TERM => fc_data <= shf_q;\r
--- when DIVIDE => fc_data <= x"cf";\r
--- when CLEANUP => fc_data <= x"df";\r
--- when others => fc_data <= x"00";\r
--- end case;\r
--- end process fcDataProc;\r
--- \r
--- -- delay counters\r
--- -- gk 28.04.10\r
--- DELAY_CTR_PROC : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if ((RESET = '1') or (loadCurrentState = LIDLE)) then\r
--- delay_ctr <= PC_DELAY_IN;\r
--- elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then\r
--- delay_ctr <= delay_ctr - x"1";\r
--- end if;\r
--- end if;\r
--- end process DELAY_CTR_PROC;\r
--- \r
--- -- gk 28.04.10\r
--- TICKS_CTR_PROC : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then\r
--- ticks_ctr <= x"00";\r
--- elsif (loadCurrentState = DELAY) then\r
--- ticks_ctr <= ticks_ctr + x"1";\r
--- end if;\r
--- end if;\r
--- end process TICKS_CTR_PROC;\r
-\r
-\r
---***********************\r
--- SIZE COUNTERS FOR LOADING SIDE\r
---***********************\r
-\r
--- queue_size_temp <= queue_size - x"20"; -- size of data without termination\r
--- \r
--- -- gk 08.04.10\r
--- rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or\r
--- ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) \r
--- else '0';\r
--- \r
--- -- gk 08.04.10\r
--- RST_AFTER_SUB_PROC : process(CLK)\r
--- begin\r
--- if(rising_edge(CLK)) then\r
--- if(RESET = '1') then\r
--- rst_after_sub <= '0';\r
--- else\r
--- rst_after_sub <= rst_after_sub_comb;\r
--- end if;\r
--- end if;\r
--- end process RST_AFTER_SUB_PROC;\r
--- \r
--- -- counts all bytes loaded to divide data into frames\r
--- bytesLoadedProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then\r
--- bytes_loaded <= x"0000";\r
--- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then\r
--- bytes_loaded <= bytes_loaded + x"1";\r
--- -- gk 05.12.10\r
--- -- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then\r
--- -- bytes_loaded <= bytes_loaded + x"1";\r
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then\r
--- bytes_loaded <= bytes_loaded + x"1";\r
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then\r
--- bytes_loaded <= bytes_loaded + x"1";\r
--- end if;\r
--- end if;\r
--- end process bytesLoadedProc;\r
--- \r
--- -- size of subevent loaded from memory\r
--- subSizeLoadedProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10\r
--- sub_size_loaded <= x"00000000";\r
--- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then\r
--- -- was all_int_ctr\r
--- -- gk 08.04.10 my_int_ctr changed to load_int_ctr\r
--- sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q;\r
--- -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo\r
--- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then\r
--- sub_size_loaded <= sub_size_loaded + x"4";\r
--- end if;\r
--- end if;\r
--- end process subSizeLoadedProc;\r
--- \r
--- -- counts only raw data bytes being loaded\r
--- subBytesLoadedProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10\r
--- sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count\r
--- elsif (loadCurrentState = LOAD_DATA) then\r
--- sub_bytes_loaded <= sub_bytes_loaded + x"1";\r
--- end if;\r
--- end if;\r
--- end process subBytesLoadedProc;\r
--- \r
--- -- counts the size of the large udp packet\r
--- actualPacketProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
--- actual_packet_size <= x"0008";\r
--- elsif (fc_wr_en = '1') then\r
--- actual_packet_size <= actual_packet_size + x"1";\r
--- end if;\r
--- end if;\r
--- end process actualPacketProc;\r
--- \r
--- actualQueueSizeProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
--- actual_queue_size <= (others => '0');\r
--- elsif (loadCurrentState = LIDLE) then\r
--- actual_queue_size <= queue_size;\r
--- end if;\r
--- end if;\r
--- end process actualQueueSizeProc;\r
--- \r
--- -- amount of bytes left to send in current packet\r
--- sizeLeftProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
--- size_left <= (others => '0');\r
--- elsif (loadCurrentState = LIDLE) then\r
--- size_left <= queue_size;\r
--- elsif (fc_wr_en = '1') then\r
--- size_left <= size_left - 1;\r
--- end if;\r
--- end if;\r
--- end process sizeLeftProc;\r
--- \r
--- -- HOT FIX: don't rely on CTS information, count the packets on your own.\r
--- -- In this case, we increment the fragmented packet ID with EOD from ipu2gbe.\r
--- THE_FC_IDENT_COUNTER_PROC: process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- fc_ident <= (others => '0');\r
--- elsif (PC_END_OF_DATA_IN = '1') then\r
--- fc_ident <= fc_ident + 1;\r
--- end if;\r
--- end if;\r
--- end process THE_FC_IDENT_COUNTER_PROC;\r
--- \r
--- fc_flags_offset(15 downto 14) <= "00";\r
--- \r
--- moreFragmentsProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
--- fc_flags_offset(13) <= '0';\r
--- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then\r
--- if ((actual_queue_size - actual_packet_size) < max_frame_size) then\r
--- fc_flags_offset(13) <= '0'; -- no more fragments\r
--- else\r
--- fc_flags_offset(13) <= '1'; -- more fragments\r
--- end if;\r
--- end if;\r
--- end if;\r
--- end process moreFragmentsProc;\r
--- \r
--- eodProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- fc_eod <= '0';\r
--- elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then\r
--- fc_eod <= '1';\r
--- elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then\r
--- fc_eod <= '1';\r
--- elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then\r
--- fc_eod <= '1';\r
--- else\r
--- fc_eod <= '0';\r
--- end if;\r
--- end if;\r
--- end process eodProc;\r
--- \r
--- sodProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- fc_sod <= '0';\r
--- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then\r
--- fc_sod <= '1';\r
--- elsif (loadCurrentState = DIVIDE) and (TC_READY_IN = '1') then\r
--- fc_sod <= '1';\r
--- else\r
--- fc_sod <= '0';\r
--- end if;\r
--- end if;\r
--- end process sodProc;\r
--- \r
--- offsetProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
--- fc_flags_offset(12 downto 0) <= (others => '0');\r
--- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) then\r
--- fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3);\r
--- end if;\r
--- end if;\r
--- end process offsetProc;\r
--- \r
--- fcIPSizeProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET= '1') then\r
--- fc_ip_size <= (others => '0');\r
--- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then\r
--- if (size_left >= max_frame_size) then\r
--- fc_ip_size <= max_frame_size;\r
--- else\r
--- fc_ip_size <= size_left(15 downto 0);\r
--- end if;\r
--- end if;\r
--- end if;\r
--- end process fcIPSizeProc;\r
--- \r
--- fcUDPSizeProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- fc_udp_size <= (others => '0');\r
--- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then\r
--- fc_udp_size <= queue_size(15 downto 0);\r
--- end if;\r
--- end if;\r
--- end process fcUDPSizeProc;\r
-\r
-\r
---***********************\r
--- SUBEVENT HEADERS WRITE AND READ\r
---***********************\r
-\r
--- SUBEVENT_HEADERS_FIFO : fifo_16kx8\r
--- port map(\r
--- Data => shf_data,\r
--- WrClock => CLK,\r
--- RdClock => CLK,\r
--- WrEn => shf_wr_en,\r
--- RdEn => shf_rd_en,\r
--- Reset => RESET,\r
--- RPReset => RESET,\r
--- Q => shf_q,\r
--- Empty => shf_empty,\r
--- Full => shf_full\r
--- );\r
--- \r
--- -- write enable for SHF \r
--- shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA))\r
--- else '0';\r
--- \r
--- -- data multiplexing for SHF (convert 32bit LWs to 8bit)\r
--- -- CHANGED. \r
--- -- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC.\r
--- shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, \r
--- pc_trig_nr, my_int_ctr, fc_data)\r
--- begin\r
--- case saveSubCurrentState is\r
--- when SIDLE => shf_data <= x"ac";\r
--- when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
--- when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
--- when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
--- when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
--- when SAVE_TERM => shf_data <= fc_data;\r
--- when others => shf_data <= x"00";\r
--- end case;\r
--- end process shfDataProc;\r
--- \r
--- saveSubMachineProc : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') then\r
--- saveSubCurrentState <= SIDLE;\r
--- else\r
--- saveSubCurrentState <= saveSubNextState;\r
--- end if;\r
--- end if;\r
--- end process saveSubMachineProc;\r
--- \r
--- saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, TC_H_READY_IN)\r
--- begin\r
--- case saveSubCurrentState is\r
--- when SIDLE =>\r
--- save_state <= x"0";\r
--- if (PC_START_OF_SUB_IN = '1') then\r
--- saveSubNextState <= SAVE_SIZE;\r
--- -- this branch is dangerous!\r
--- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len\r
--- saveSubNextState <= SAVE_TERM;\r
--- else\r
--- saveSubNextState <= SIDLE;\r
--- end if;\r
--- when SAVE_SIZE =>\r
--- save_state <= x"1";\r
--- if (sub_int_ctr = 3) then\r
--- saveSubNextState <= SAVE_DECODING;\r
--- else\r
--- saveSubNextState <= SAVE_SIZE;\r
--- end if;\r
--- when SAVE_DECODING =>\r
--- save_state <= x"2";\r
--- if (sub_int_ctr = 3) then\r
--- saveSubNextState <= SAVE_ID;\r
--- else\r
--- saveSubNextState <= SAVE_DECODING;\r
--- end if;\r
--- when SAVE_ID =>\r
--- save_state <= x"3";\r
--- if (sub_int_ctr = 3) then\r
--- saveSubNextState <= SAVE_TRIG_NR;\r
--- else\r
--- saveSubNextState <= SAVE_ID;\r
--- end if;\r
--- when SAVE_TRIG_NR =>\r
--- save_state <= x"4";\r
--- if (sub_int_ctr = 3) then\r
--- saveSubNextState <= SIDLE;\r
--- else\r
--- saveSubNextState <= SAVE_TRIG_NR;\r
--- end if;\r
--- when SAVE_TERM =>\r
--- save_state <= x"5";\r
--- if (sub_int_ctr = 31) then\r
--- saveSubNextState <= SIDLE;\r
--- else\r
--- saveSubNextState <= SAVE_TERM;\r
--- end if;\r
--- when others =>\r
--- save_state <= x"f";\r
--- saveSubNextState <= SIDLE;\r
--- end case;\r
--- end process;\r
--- \r
--- -- This counter is used for breaking down 32bit information words into 8bit bytes for \r
--- -- storing them in the SHF.\r
--- -- It is also used for the termination 32byte sequence.\r
--- subIntProc: process( CLK )\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if (RESET = '1') or (saveSubCurrentState = SIDLE) then\r
--- sub_int_ctr <= 0;\r
--- elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then\r
--- sub_int_ctr <= 0;\r
--- elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then\r
--- sub_int_ctr <= 0;\r
--- elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then\r
--- sub_int_ctr <= sub_int_ctr + 1;\r
--- end if;\r
--- end if;\r
--- end process subIntProc;\r
--- \r
--- debug(3 downto 0) <= constr_state;\r
--- debug(7 downto 4) <= save_state;\r
--- debug(11 downto 8) <= load_state;\r
--- debug(27 downto 12) <= queue_size(15 downto 0);\r
--- debug(28) <= df_full;\r
--- debug(29) <= df_empty;\r
--- debug(30) <= shf_full;\r
--- debug(31) <= shf_empty;\r
--- \r
--- debug(47 downto 32) <= size_left(15 downto 0);\r
--- debug(52 downto 48) <= all_ctr;\r
--- debug(53) <= pc_ready;\r
-\r
--- outputs\r
--- PC_READY_OUT <= pc_ready;\r
--- TC_WR_EN_OUT <= fc_wr_en;\r
--- TC_DATA_OUT <= fc_data;\r
--- TC_IP_SIZE_OUT <= fc_ip_size;\r
--- TC_UDP_SIZE_OUT <= fc_udp_size;\r
--- -- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0);\r
--- -- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8);\r
--- TC_FLAGS_OFFSET_OUT <= fc_flags_offset;\r
--- TC_SOD_OUT <= fc_sod;\r
--- TC_EOD_OUT <= fc_eod;\r
-\r
-PC_READY_OUT <= '1';\r
-TC_IP_SIZE_OUT <= (others => '0');\r
-TC_UDP_SIZE_OUT <= (others => '0');\r
--- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0);\r
--- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8);\r
--- TC_FLAGS_OFFSET_OUT <= fc_flags_offset;\r
--- TC_SOD_OUT <= fc_sod;\r
--- TC_EOD_OUT <= fc_eod;\r
-\r
-DEBUG_OUT <= debug;\r
-\r
-end trb_net16_gbe_packet_constr;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-entity trb_net16_gbe_packet_constr is
-port(
- RESET : in std_logic;
- CLK : in std_logic;
- MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10
- -- ports for user logic
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
- PC_DATA_IN : in std_logic_vector(7 downto 0);
- PC_READY_OUT : out std_logic;
- PC_START_OF_SUB_IN : in std_logic; -- CHANGED TO SLOW CONTROL PULSE
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10
- PC_END_OF_DATA_IN : in std_logic;
- PC_TRANSMIT_ON_OUT : out std_logic;
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
- PC_PADDING_IN : in std_logic; -- gk 29.03.10
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10
- -- FrameConstructor ports
- TC_WR_EN_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(7 downto 0);
- TC_H_READY_IN : in std_logic;
- TC_READY_IN : in std_logic;
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- TC_SOD_OUT : out std_logic;
- TC_EOD_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_packet_constr;
-
-architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is
-
--- attribute HGROUP : string;
--- attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_packet_constr";
-
-component fifo_64kx9
-port (
- Data : in std_logic_vector(8 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
--- FIFO for SubEventHeader information
-component fifo_16kx8 is
-port (
- Data : in std_logic_vector(7 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-signal df_wr_en : std_logic;
-signal df_rd_en : std_logic;
-signal df_q : std_logic_vector(7 downto 0);
-signal df_q_reg : std_logic_vector(7 downto 0);
-signal df_empty : std_logic;
-signal df_full : std_logic;
-
-signal fc_data : std_logic_vector(7 downto 0);
-signal fc_wr_en : std_logic;
-signal fc_sod : std_logic;
-signal fc_eod : std_logic;
-signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter!
-signal fc_flags_offset : std_logic_vector(15 downto 0);
-
-signal shf_data : std_logic_vector(7 downto 0);
-signal shf_wr_en : std_logic;
-signal shf_rd_en : std_logic;
-signal shf_q : std_logic_vector(7 downto 0);
-signal shf_empty : std_logic;
-signal shf_full : std_logic;
-
-type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD);
-signal constructCurrentState, constructNextState : constructStates;
-signal constr_state : std_logic_vector(3 downto 0);
-signal all_int_ctr : integer range 0 to 31;
-signal all_ctr : std_logic_vector(4 downto 0);
-
-type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM);
-signal saveSubCurrentState, saveSubNextState : saveSubStates;
-signal save_state : std_logic_vector(3 downto 0);
-signal sub_int_ctr : integer range 0 to 31;
-signal sub_ctr : std_logic_vector(4 downto 0);
-signal my_int_ctr : integer range 0 to 3;
-signal my_ctr : std_logic_vector(1 downto 0);
-
-type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY);
-signal loadCurrentState, loadNextState: loadStates;
-signal load_state : std_logic_vector(3 downto 0);
-
-signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination
-signal queue_size_temp : std_logic_vector(31 downto 0);
-signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid
-signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame
-signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf
-signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted
-signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent
-signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet
-signal size_left : std_logic_vector(31 downto 0);
-signal fc_ip_size : std_logic_vector(15 downto 0);
-signal fc_udp_size : std_logic_vector(15 downto 0);
-signal max_frame_size : std_logic_vector(15 downto 0);
-signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term
-signal debug : std_logic_vector(63 downto 0);
-signal pc_ready : std_logic;
-
-signal pc_sub_size : std_logic_vector(31 downto 0);
-signal pc_trig_nr : std_logic_vector(31 downto 0);
-signal rst_after_sub_comb : std_logic; -- gk 08.04.10
-signal rst_after_sub : std_logic; -- gk 08.04.10
-signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10
-signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10
-signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10
-
--- gk 26.07.10
-signal load_eod : std_logic;
-signal load_eod_q : std_logic;
-
--- gk 07.10.10
-signal df_eod : std_logic;
-
--- gk 04.12.10
-signal first_sub_in_multi : std_logic;
-signal from_divide_state : std_logic;
-signal disable_prep : std_logic;
-
--- gk 02.08.11
-type constructSimpleFrameStates is (IDLE, WAIT_FOR_HEADERS, PUT_DATA, FINISH);
-signal constrSimpleFrameCurrentState, constrSimpleFrameNextState : constructSimpleFrameStates;
-
-signal gen_data_ctr : std_logic_vector(15 downto 0);
-
-signal state : std_logic_vector(3 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of state : signal is true;
-attribute syn_preserve of state : signal is true;
-
-begin
-
-costrSimpleFrameMachineProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- constrSimpleFrameCurrentState <= IDLE;
- else
- constrSimpleFrameCurrentState <= constrSimpleFrameNextState;
- end if;
- end if;
-end process costrSimpleFrameMachineProc;
-
-constrSimpleFrameMachine : process(constrSimpleFrameCurrentState, PC_START_OF_SUB_IN, TC_H_READY_IN, gen_data_ctr, TC_READY_IN)
-begin
- case constrSimpleFrameCurrentState is
-
- when IDLE =>
- state <= x"1";
- if (PC_START_OF_SUB_IN = '1') then
- constrSimpleFrameNextState <= WAIT_FOR_HEADERS;
- else
- constrSimpleFrameNextState <= IDLE;
- end if;
-
- when WAIT_FOR_HEADERS =>
- state <= x"2";
- if (TC_H_READY_IN = '1') then
- constrSimpleFrameNextState <= PUT_DATA;
- else
- constrSimpleFrameNextState <= WAIT_FOR_HEADERS;
- end if;
-
- when PUT_DATA =>
- state <= x"3";
- if (gen_data_ctr = x"0100") then
- constrSimpleFrameNextState <= FINISH;
- else
- constrSimpleFrameNextState <= PUT_DATA;
- end if;
-
- when FINISH =>
- state <= x"4";
- if (TC_READY_IN = '1') then
- constrSimpleFrameNextState <= IDLE;
- else
- constrSimpleFrameNextState <= FINISH;
- end if;
-
- end case;
-end process constrSimpleFrameMachine;
-
-GEN_DATA_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (constrSimpleFrameCurrentState = IDLE) then
- gen_data_ctr <= (others => '0');
- elsif (constrSimpleFrameCurrentState = PUT_DATA) then
- gen_data_ctr <= gen_data_ctr + x"1";
- end if;
- end if;
-end process;
-
-TC_DATA_OUT <= gen_data_ctr(7 downto 0);
-TC_WR_EN_OUT <= '1' when constrSimpleFrameCurrentState = PUT_DATA else '0';
-TC_SOD_OUT <= '1' when (constrSimpleFrameCurrentState = IDLE and PC_START_OF_SUB_IN = '1') or (constrSimpleFrameCurrentState = WAIT_FOR_HEADERS and TC_H_READY_IN = '0') else '0';
-TC_EOD_OUT <= '1' when constrSimpleFrameCurrentState = PUT_DATA and gen_data_ctr = x"0100" else '0';
-PC_READY_OUT <= '1' when constrSimpleFrameCurrentState = IDLE else '0';
-PC_TRANSMIT_ON_OUT <= '0' when constrSimpleFrameCurrentState = IDLE and PC_START_OF_SUB_IN = '0' else '1';
-TC_IP_SIZE_OUT <= x"0100";
-TC_UDP_SIZE_OUT <= x"0100";
-TC_FLAGS_OFFSET_OUT <= (others => '0');
-
---PC_TRANSMIT_ON_OUT <= '1' when constructCurrentState = WAIT_FOR_LOAD else '0';
---PC_TRANSMIT_ON_OUT <= '0';
-
--- my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order
--- load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10
---
--- all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging
--- sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging
--- my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging
---
--- max_frame_size <= PC_MAX_FRAME_SIZE_IN;
---
--- -- Ready signal for PacketConstructor
- --pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0';
---pc_ready <= '0';
-
--- store event information on Start_of_Subevent
--- THE_EVT_INFO_STORE_PROC: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if (RESET = '1') then -- gk 31.05.10
--- pc_sub_size <= (others => '0');
--- pc_trig_nr <= (others => '0');
--- elsif( PC_START_OF_SUB_IN = '1' ) then
--- pc_sub_size <= PC_SUB_SIZE_IN;
--- pc_trig_nr <= PC_TRIG_NR_IN;
--- end if;
--- end if;
--- end process;
---
--- -- gk 07.10.10
--- df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1'))
--- or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1'))
--- else '0';
-
--- Data FIFO for incoming packet data from IPU buffer
--- gk 26.07.10
--- DATA_FIFO : fifo_64kx9
--- port map(
--- Data(7 downto 0) => PC_DATA_IN,
--- Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 07.10.10
--- WrClock => CLK,
--- RdClock => CLK,
--- WrEn => df_wr_en,
--- RdEn => df_rd_en,
--- Reset => RESET,
--- RPReset => RESET,
--- Q(7 downto 0) => df_q,
--- Q(8) => load_eod,
--- Empty => df_empty,
--- Full => df_full
--- );
-
--- LOAD_EOD_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- load_eod_q <= '0';
--- else
--- load_eod_q <= load_eod;
--- end if;
--- end if;
--- end process LOAD_EOD_PROC;
---
--- -- Write enable for the data FIFO
--- -- !!!combinatorial signal!!!
--- -- could be avoided as IPU2GBE does only send data in case of PC_READY.
--- df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD))
--- else '0';
---
--- -- Output register for data FIFO
--- dfQProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- df_q_reg <= df_q;
--- end if;
--- end process dfQProc;
---
--- -- Construction state machine
--- constructMachineProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- constructCurrentState <= CIDLE;
--- else
--- constructCurrentState <= constructNextState;
--- end if;
--- end if;
--- end process constructMachineProc;
---
--- constructMachine : process(constructCurrentState, PC_START_OF_SUB_IN, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr)
--- begin
--- case constructCurrentState is
--- when CIDLE =>
--- constr_state <= x"0";
--- --if( PC_WR_EN_IN = '1' ) then
--- -- gk 04.12.10
--- if (PC_START_OF_SUB_IN = '1') then
---
--- constructNextState <= SAVE_DATA;
--- else
--- constructNextState <= CIDLE;
--- end if;
--- when SAVE_DATA =>
--- constr_state <= x"1";
--- if( PC_END_OF_DATA_IN = '1' ) then
--- constructNextState <= WAIT_FOR_LOAD;
--- else
--- constructNextState <= SAVE_DATA;
--- end if;
--- when WAIT_FOR_LOAD =>
--- constr_state <= x"2";
--- if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted
--- constructNextState <= CIDLE;
--- else
--- constructNextState <= WAIT_FOR_LOAD;
--- end if;
--- when others =>
--- constr_state <= x"f";
--- constructNextState <= CIDLE;
--- end case;
--- end process constructMachine;
-
---***********************
--- SIZE COUNTERS FOR SAVING SIDE
---***********************
-
--- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size
--- that's why they are removed if pc_padding flag is asserted
--- sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0')
--- else (x"c" + pc_sub_size); -- subevent headers + data
---
--- -- BUG HERE BUG HERE BUG HERE BUG HERE
--- -- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents
--- queueSizeProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- --if (RESET = '1') or (loadCurrentState = PUT_Q_DEC) then -- gk 07.10.10 -- (loadCurrentState = CLEANUP) then
--- if (RESET = '1') or (loadCurrentState = CLEANUP) then
--- queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination
--- elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then
--- queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers
--- end if;
--- end if;
--- end process queueSizeProc;
-
-
---***********************
--- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION
---***********************
-
--- loadMachineProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- loadCurrentState <= LIDLE;
--- else
--- loadCurrentState <= loadNextState;
--- end if;
--- end if;
--- end process loadMachineProc;
---
--- loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty,
--- sub_bytes_loaded, sub_size_loaded, size_left, TC_H_READY_IN,
--- max_frame_size, bytes_loaded, divide_position, PC_DELAY_IN,
--- delay_ctr, load_eod_q, MULT_EVT_ENABLE_IN)
--- begin
--- case loadCurrentState is
--- when LIDLE =>
--- load_state <= x"0";
--- if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then
--- loadNextState <= WAIT_FOR_FC;
--- else
--- loadNextState <= LIDLE;
--- end if;
--- when WAIT_FOR_FC =>
--- load_state <= x"1";
--- if (TC_H_READY_IN = '1') then
--- loadNextState <= PUT_Q_LEN;
--- else
--- loadNextState <= WAIT_FOR_FC;
--- end if;
--- when PUT_Q_LEN =>
--- load_state <= x"2";
--- if (all_int_ctr = 3) then
--- loadNextState <= PUT_Q_DEC;
--- else
--- loadNextState <= PUT_Q_LEN;
--- end if;
--- when PUT_Q_DEC =>
--- load_state <= x"3";
--- if (all_int_ctr = 3) then
--- loadNextState <= LOAD_SUB;
--- else
--- loadNextState <= PUT_Q_DEC;
--- end if;
--- when LOAD_SUB =>
--- load_state <= x"4";
--- if (bytes_loaded = max_frame_size - 1) then
--- loadNextState <= DIVIDE;
--- elsif (all_int_ctr = 15) then
--- loadNextState <= PREP_DATA;
--- else
--- loadNextState <= LOAD_SUB;
--- end if;
--- when PREP_DATA =>
--- load_state <= x"5";
--- loadNextState <= LOAD_DATA;
--- when LOAD_DATA =>
--- load_state <= x"6";
--- -- if (bytes_loaded = max_frame_size - 1) then
--- -- loadNextState <= DIVIDE;
--- -- -- gk 07.10.10
--- -- elsif (MULT_EVT_ENABLE_IN = '1') then
--- -- if (size_left = x"0000_0023") then
--- -- loadNextState <= LOAD_TERM;
--- -- elsif (load_eod_q = '1') then
--- -- loadNextState <= LOAD_SUB;
--- -- else
--- -- loadNextState <= LOAD_DATA;
--- -- end if;
--- -- else
--- -- if (load_eod_q = '1') then
--- -- loadNextState <= LOAD_TERM;
--- -- else
--- -- loadNextState <= LOAD_DATA;
--- -- end if;
--- -- end if;
--- if (bytes_loaded = max_frame_size - 1) then
--- loadNextState <= DIVIDE;
--- -- gk 07.10.10
--- elsif (load_eod_q = '1') then
--- if (MULT_EVT_ENABLE_IN = '1') then
--- if (size_left < x"0000_0030") then
--- loadNextState <= LOAD_TERM;
--- else
--- loadNextState <= LOAD_SUB;
--- end if;
--- else
--- loadNextState <= LOAD_TERM;
--- end if;
--- else
--- loadNextState <= LOAD_DATA;
--- end if;
--- when DIVIDE =>
--- load_state <= x"7";
--- if (TC_H_READY_IN = '1') then
--- if (divide_position = "00") then
--- loadNextState <= PREP_DATA;
--- elsif (divide_position = "01") then
--- loadNextState <= LOAD_SUB;
--- else
--- loadNextState <= LOAD_TERM;
--- end if;
--- else
--- loadNextState <= DIVIDE;
--- end if;
--- when LOAD_TERM =>
--- load_state <= x"8";
--- if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then
--- loadNextState <= DIVIDE;
--- elsif (all_int_ctr = 31) then
--- loadNextState <= CLEANUP;
--- else
--- loadNextState <= LOAD_TERM;
--- end if;
--- -- gk 28.04.10
--- when CLEANUP =>
--- load_state <= x"9";
--- if (PC_DELAY_IN = x"0000_0000") then
--- loadNextState <= LIDLE;
--- else
--- loadNextState <= DELAY;
--- end if;
--- -- gk 28.04.10
--- when DELAY =>
--- load_state <= x"a";
--- if (delay_ctr = x"0000_0000") then
--- loadNextState <= LIDLE;
--- else
--- loadNextState <= DELAY;
--- end if;
--- when others =>
--- load_state <= x"f";
--- loadNextState <= LIDLE;
--- end case;
--- end process loadMachine;
---
--- -- gk 04.12.10
--- firstSubInMultiProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (loadCurrentState = LOAD_TERM) then
--- first_sub_in_multi <= '1';
--- elsif (loadCurrentState = LOAD_DATA) then
--- first_sub_in_multi <= '0';
--- end if;
--- end if;
--- end process;
---
--- -- gk 04.12.10
--- fromDivideStateProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- from_divide_state <= '0';
--- elsif (loadCurrentState = DIVIDE) then
--- from_divide_state <= '1';
--- elsif (loadCurrentState = PREP_DATA) then
--- from_divide_state <= '0';
--- end if;
--- end if;
--- end process fromDivideStateProc;
---
---
--- dividePositionProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- divide_position <= "00";
--- -- elsif (bytes_loaded = max_frame_size - 1) then
--- -- if (loadCurrentState = LIDLE) then
--- -- divide_position <= "00";
--- -- elsif (loadCurrentState = LOAD_DATA) then
--- -- -- gk 07.10.10
--- -- if (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then
--- -- divide_position <= "11";
--- -- -- gk 07.10.10
--- -- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then
--- -- divide_position <= "01";
--- -- -- gk 26.07.10
--- -- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term
--- -- divide_position <= "11";
--- -- else
--- -- divide_position <= "00"; -- still data loaded divide on data
--- -- end if;
--- -- elsif (loadCurrentState = LOAD_SUB) then
--- -- if (all_int_ctr = 15) then
--- -- divide_position <= "00";
--- -- else
--- -- divide_position <= "01";
--- -- end if;
--- -- elsif (loadCurrentState = LOAD_TERM) then
--- -- divide_position <= "11";
--- -- end if;
--- -- end if;
--- elsif (bytes_loaded = max_frame_size - 1) then
--- if (loadCurrentState = LIDLE) then
--- divide_position <= "00";
--- disable_prep <= '0'; -- gk 05.12.10
--- elsif (loadCurrentState = LOAD_DATA) then
--- -- gk 05.12.10
--- -- gk 26.07.10
--- if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term
--- divide_position <= "11";
--- disable_prep <= '0'; -- gk 05.12.10
--- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then
--- if (size_left > x"0000_0028") then
--- divide_position <= "01";
--- disable_prep <= '0'; -- gk 05.12.10
--- else
--- divide_position <= "11";
--- disable_prep <= '0'; -- gk 05.12.10
--- end if;
--- else
--- divide_position <= "00"; -- still data loaded divide on data
--- disable_prep <= '1'; -- gk 05.12.10
--- end if;
--- elsif (loadCurrentState = LOAD_SUB) then
--- if (all_int_ctr = 15) then
--- divide_position <= "00";
--- disable_prep <= '1'; -- gk 05.12.10
--- else
--- divide_position <= "01";
--- disable_prep <= '0'; -- gk 05.12.10
--- end if;
--- elsif (loadCurrentState = LOAD_TERM) then
--- divide_position <= "11";
--- disable_prep <= '0'; -- gk 05.12.10
--- end if;
--- elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep
--- disable_prep <= '0';
--- end if;
---
--- end if;
--- end process dividePositionProc;
---
--- allIntCtrProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then -- gk 31.05.10
--- all_int_ctr <= 0;
--- else
--- case loadCurrentState is
---
--- when LIDLE => all_int_ctr <= 0;
---
--- when WAIT_FOR_FC => all_int_ctr <= 0;
---
--- when PUT_Q_LEN =>
--- if (all_int_ctr = 3) then
--- all_int_ctr <= 0;
--- else
--- all_int_ctr <= all_int_ctr + 1;
--- end if;
---
--- when PUT_Q_DEC =>
--- if (all_int_ctr = 3) then
--- all_int_ctr <= 0;
--- else
--- all_int_ctr <= all_int_ctr + 1;
--- end if;
---
--- when LOAD_SUB =>
--- if (all_int_ctr = 15) then
--- all_int_ctr <= 0;
--- else
--- all_int_ctr <= all_int_ctr + 1;
--- end if;
---
--- when LOAD_DATA => all_int_ctr <= 0;
---
--- when LOAD_TERM =>
--- if (all_int_ctr = 31) then
--- all_int_ctr <= 0;
--- else
--- all_int_ctr <= all_int_ctr + 1;
--- end if;
---
--- when DIVIDE => null;
---
--- when CLEANUP => all_int_ctr <= 0;
---
--- when PREP_DATA => all_int_ctr <= 0;
---
--- when DELAY => all_int_ctr <= 0;
--- end case;
--- end if;
--- end if;
--- end process allIntCtrProc;
---
--- dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded,
--- sub_size_loaded, all_int_ctr, RESET, size_left, load_eod_q)
--- begin
--- if (RESET = '1') then
--- df_rd_en <= '0';
--- elsif (loadCurrentState = LOAD_DATA) then
--- -- if (bytes_loaded = max_frame_size - x"1") then
--- -- df_rd_en <= '0';
--- -- -- gk 07.10.10
--- -- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then
--- -- df_rd_en <= '0';
--- -- -- gk 07.10.10
--- -- elsif (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then
--- -- df_rd_en <= '0';
--- -- else
--- -- df_rd_en <= '1';
--- -- end if;
--- if (bytes_loaded = max_frame_size - x"1") then
--- df_rd_en <= '0';
--- -- gk 26.07.10
--- --elsif (load_eod = '1') or (load_eod_q = '1') then
--- elsif (load_eod_q = '1') then
--- df_rd_en <= '0';
--- -- elsif (sub_bytes_loaded = sub_size_loaded) then
--- -- df_rd_en <= '0';
--- else
--- df_rd_en <= '1';
--- end if;
---
--- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then
--- df_rd_en <= '1';
--- elsif (loadCurrentState = PREP_DATA) then
--- df_rd_en <= '1';
--- else
--- df_rd_en <= '0';
--- end if;
--- end process dfRdEnProc;
---
--- shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET)
--- begin
--- if (RESET = '1') then -- gk 31.05.10
--- shf_rd_en <= '0';
--- elsif (loadCurrentState = LOAD_SUB) then
--- shf_rd_en <= '1';
--- elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then
--- shf_rd_en <= '1';
--- elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then
--- shf_rd_en <= '1';
--- else
--- shf_rd_en <= '0';
--- end if;
--- end process shfRdEnProc;
---
---
--- -- fcWrEnProc : process(loadCurrentState, RESET)
--- -- begin
--- -- if (RESET = '1') then -- gk 31.05.10
--- -- fc_wr_en <= '0';
--- -- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then
--- -- fc_wr_en <= '1';
--- -- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then
--- -- fc_wr_en <= '1';
--- -- else
--- -- fc_wr_en <= '0';
--- -- end if;
--- -- end process fcWrEnProc;
--- fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep)
--- begin
--- if (RESET = '1') then -- gk 31.05.10
--- fc_wr_en <= '0';
--- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then
--- fc_wr_en <= '1';
--- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then
--- fc_wr_en <= '1';
--- -- gk 04.12.10
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then
--- fc_wr_en <= '1';
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then
--- fc_wr_en <= '1';
--- else
--- fc_wr_en <= '0';
--- end if;
--- end process fcWrEnProc;
---
---
--- -- was all_int_ctr
--- fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr)
--- begin
--- case loadCurrentState is
--- when LIDLE => fc_data <= x"af";
--- when WAIT_FOR_FC => fc_data <= x"bf";
--- -- gk 08.04.10 my_int_ctr changed to load_int_ctr
--- when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8);
--- when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8);
--- when LOAD_SUB => fc_data <= shf_q;
--- when PREP_DATA => fc_data <= df_q_reg;
--- when LOAD_DATA => fc_data <= df_q_reg;
--- when LOAD_TERM => fc_data <= shf_q;
--- when DIVIDE => fc_data <= x"cf";
--- when CLEANUP => fc_data <= x"df";
--- when others => fc_data <= x"00";
--- end case;
--- end process fcDataProc;
---
--- -- delay counters
--- -- gk 28.04.10
--- DELAY_CTR_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if ((RESET = '1') or (loadCurrentState = LIDLE)) then
--- delay_ctr <= PC_DELAY_IN;
--- elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then
--- delay_ctr <= delay_ctr - x"1";
--- end if;
--- end if;
--- end process DELAY_CTR_PROC;
---
--- -- gk 28.04.10
--- TICKS_CTR_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then
--- ticks_ctr <= x"00";
--- elsif (loadCurrentState = DELAY) then
--- ticks_ctr <= ticks_ctr + x"1";
--- end if;
--- end if;
--- end process TICKS_CTR_PROC;
-
-
---***********************
--- SIZE COUNTERS FOR LOADING SIDE
---***********************
-
--- queue_size_temp <= queue_size - x"20"; -- size of data without termination
---
--- -- gk 08.04.10
--- rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or
--- ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded)
--- else '0';
---
--- -- gk 08.04.10
--- RST_AFTER_SUB_PROC : process(CLK)
--- begin
--- if(rising_edge(CLK)) then
--- if(RESET = '1') then
--- rst_after_sub <= '0';
--- else
--- rst_after_sub <= rst_after_sub_comb;
--- end if;
--- end if;
--- end process RST_AFTER_SUB_PROC;
---
--- -- counts all bytes loaded to divide data into frames
--- bytesLoadedProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then
--- bytes_loaded <= x"0000";
--- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then
--- bytes_loaded <= bytes_loaded + x"1";
--- -- gk 05.12.10
--- -- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then
--- -- bytes_loaded <= bytes_loaded + x"1";
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then
--- bytes_loaded <= bytes_loaded + x"1";
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then
--- bytes_loaded <= bytes_loaded + x"1";
--- end if;
--- end if;
--- end process bytesLoadedProc;
---
--- -- size of subevent loaded from memory
--- subSizeLoadedProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10
--- sub_size_loaded <= x"00000000";
--- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then
--- -- was all_int_ctr
--- -- gk 08.04.10 my_int_ctr changed to load_int_ctr
--- sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q;
--- -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo
--- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then
--- sub_size_loaded <= sub_size_loaded + x"4";
--- end if;
--- end if;
--- end process subSizeLoadedProc;
---
--- -- counts only raw data bytes being loaded
--- subBytesLoadedProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10
--- sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count
--- elsif (loadCurrentState = LOAD_DATA) then
--- sub_bytes_loaded <= sub_bytes_loaded + x"1";
--- end if;
--- end if;
--- end process subBytesLoadedProc;
---
--- -- counts the size of the large udp packet
--- actualPacketProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then
--- actual_packet_size <= x"0008";
--- elsif (fc_wr_en = '1') then
--- actual_packet_size <= actual_packet_size + x"1";
--- end if;
--- end if;
--- end process actualPacketProc;
---
--- actualQueueSizeProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (loadCurrentState = CLEANUP) then
--- actual_queue_size <= (others => '0');
--- elsif (loadCurrentState = LIDLE) then
--- actual_queue_size <= queue_size;
--- end if;
--- end if;
--- end process actualQueueSizeProc;
---
--- -- amount of bytes left to send in current packet
--- sizeLeftProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (loadCurrentState = CLEANUP) then
--- size_left <= (others => '0');
--- elsif (loadCurrentState = LIDLE) then
--- size_left <= queue_size;
--- elsif (fc_wr_en = '1') then
--- size_left <= size_left - 1;
--- end if;
--- end if;
--- end process sizeLeftProc;
---
--- -- HOT FIX: don't rely on CTS information, count the packets on your own.
--- -- In this case, we increment the fragmented packet ID with EOD from ipu2gbe.
--- THE_FC_IDENT_COUNTER_PROC: process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- fc_ident <= (others => '0');
--- elsif (PC_END_OF_DATA_IN = '1') then
--- fc_ident <= fc_ident + 1;
--- end if;
--- end if;
--- end process THE_FC_IDENT_COUNTER_PROC;
---
--- fc_flags_offset(15 downto 14) <= "00";
---
--- moreFragmentsProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then
--- fc_flags_offset(13) <= '0';
--- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then
--- if ((actual_queue_size - actual_packet_size) < max_frame_size) then
--- fc_flags_offset(13) <= '0'; -- no more fragments
--- else
--- fc_flags_offset(13) <= '1'; -- more fragments
--- end if;
--- end if;
--- end if;
--- end process moreFragmentsProc;
---
--- eodProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- fc_eod <= '0';
--- elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then
--- fc_eod <= '1';
--- elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then
--- fc_eod <= '1';
--- elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then
--- fc_eod <= '1';
--- else
--- fc_eod <= '0';
--- end if;
--- end if;
--- end process eodProc;
---
--- sodProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- fc_sod <= '0';
--- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then
--- fc_sod <= '1';
--- elsif (loadCurrentState = DIVIDE) and (TC_READY_IN = '1') then
--- fc_sod <= '1';
--- else
--- fc_sod <= '0';
--- end if;
--- end if;
--- end process sodProc;
---
--- offsetProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then
--- fc_flags_offset(12 downto 0) <= (others => '0');
--- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) then
--- fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3);
--- end if;
--- end if;
--- end process offsetProc;
---
--- fcIPSizeProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET= '1') then
--- fc_ip_size <= (others => '0');
--- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then
--- if (size_left >= max_frame_size) then
--- fc_ip_size <= max_frame_size;
--- else
--- fc_ip_size <= size_left(15 downto 0);
--- end if;
--- end if;
--- end if;
--- end process fcIPSizeProc;
---
--- fcUDPSizeProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- fc_udp_size <= (others => '0');
--- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then
--- fc_udp_size <= queue_size(15 downto 0);
--- end if;
--- end if;
--- end process fcUDPSizeProc;
-
-
---***********************
--- SUBEVENT HEADERS WRITE AND READ
---***********************
-
--- SUBEVENT_HEADERS_FIFO : fifo_16kx8
--- port map(
--- Data => shf_data,
--- WrClock => CLK,
--- RdClock => CLK,
--- WrEn => shf_wr_en,
--- RdEn => shf_rd_en,
--- Reset => RESET,
--- RPReset => RESET,
--- Q => shf_q,
--- Empty => shf_empty,
--- Full => shf_full
--- );
---
--- -- write enable for SHF
--- shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA))
--- else '0';
---
--- -- data multiplexing for SHF (convert 32bit LWs to 8bit)
--- -- CHANGED.
--- -- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC.
--- shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN,
--- pc_trig_nr, my_int_ctr, fc_data)
--- begin
--- case saveSubCurrentState is
--- when SIDLE => shf_data <= x"ac";
--- when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
--- when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
--- when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
--- when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
--- when SAVE_TERM => shf_data <= fc_data;
--- when others => shf_data <= x"00";
--- end case;
--- end process shfDataProc;
---
--- saveSubMachineProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- saveSubCurrentState <= SIDLE;
--- else
--- saveSubCurrentState <= saveSubNextState;
--- end if;
--- end if;
--- end process saveSubMachineProc;
---
--- saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, TC_H_READY_IN)
--- begin
--- case saveSubCurrentState is
--- when SIDLE =>
--- save_state <= x"0";
--- if (PC_START_OF_SUB_IN = '1') then
--- saveSubNextState <= SAVE_SIZE;
--- -- this branch is dangerous!
--- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len
--- saveSubNextState <= SAVE_TERM;
--- else
--- saveSubNextState <= SIDLE;
--- end if;
--- when SAVE_SIZE =>
--- save_state <= x"1";
--- if (sub_int_ctr = 3) then
--- saveSubNextState <= SAVE_DECODING;
--- else
--- saveSubNextState <= SAVE_SIZE;
--- end if;
--- when SAVE_DECODING =>
--- save_state <= x"2";
--- if (sub_int_ctr = 3) then
--- saveSubNextState <= SAVE_ID;
--- else
--- saveSubNextState <= SAVE_DECODING;
--- end if;
--- when SAVE_ID =>
--- save_state <= x"3";
--- if (sub_int_ctr = 3) then
--- saveSubNextState <= SAVE_TRIG_NR;
--- else
--- saveSubNextState <= SAVE_ID;
--- end if;
--- when SAVE_TRIG_NR =>
--- save_state <= x"4";
--- if (sub_int_ctr = 3) then
--- saveSubNextState <= SIDLE;
--- else
--- saveSubNextState <= SAVE_TRIG_NR;
--- end if;
--- when SAVE_TERM =>
--- save_state <= x"5";
--- if (sub_int_ctr = 31) then
--- saveSubNextState <= SIDLE;
--- else
--- saveSubNextState <= SAVE_TERM;
--- end if;
--- when others =>
--- save_state <= x"f";
--- saveSubNextState <= SIDLE;
--- end case;
--- end process;
---
--- -- This counter is used for breaking down 32bit information words into 8bit bytes for
--- -- storing them in the SHF.
--- -- It is also used for the termination 32byte sequence.
--- subIntProc: process( CLK )
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (saveSubCurrentState = SIDLE) then
--- sub_int_ctr <= 0;
--- elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then
--- sub_int_ctr <= 0;
--- elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then
--- sub_int_ctr <= 0;
--- elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then
--- sub_int_ctr <= sub_int_ctr + 1;
--- end if;
--- end if;
--- end process subIntProc;
---
--- debug(3 downto 0) <= constr_state;
--- debug(7 downto 4) <= save_state;
--- debug(11 downto 8) <= load_state;
--- debug(27 downto 12) <= queue_size(15 downto 0);
--- debug(28) <= df_full;
--- debug(29) <= df_empty;
--- debug(30) <= shf_full;
--- debug(31) <= shf_empty;
---
--- debug(47 downto 32) <= size_left(15 downto 0);
--- debug(52 downto 48) <= all_ctr;
--- debug(53) <= pc_ready;
-
--- outputs
--- PC_READY_OUT <= pc_ready;
--- TC_WR_EN_OUT <= fc_wr_en;
--- TC_DATA_OUT <= fc_data;
--- TC_IP_SIZE_OUT <= fc_ip_size;
--- TC_UDP_SIZE_OUT <= fc_udp_size;
--- -- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0);
--- -- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8);
--- TC_FLAGS_OFFSET_OUT <= fc_flags_offset;
--- TC_SOD_OUT <= fc_sod;
--- TC_EOD_OUT <= fc_eod;
-
---PC_READY_OUT <= '1';
---TC_IP_SIZE_OUT <= (others => '0');
---TC_UDP_SIZE_OUT <= (others => '0');
--- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0);
--- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8);
--- TC_FLAGS_OFFSET_OUT <= fc_flags_offset;
--- TC_SOD_OUT <= fc_sod;
--- TC_EOD_OUT <= fc_eod;
-
-DEBUG_OUT <= debug;
-
-end trb_net16_gbe_packet_constr;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
--- maps the frame type and protocol code into internal value which sets the priority
-
-entity trb_net16_gbe_protocol_prioritizer is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
-
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type
- PROTOCOL_CODE_IN : in std_logic_vector(7 downto 0); -- ip protocol
- UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0);
-
- CODE_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0)
-);
-end trb_net16_gbe_protocol_prioritizer;
-
-
-architecture trb_net16_gbe_protocol_prioritizer of trb_net16_gbe_protocol_prioritizer is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_protocol_prioritizer : architecture is "GBE_MAIN_group";
-
-begin
-
-PRIORITIZE : process(RESET, CLK)
-begin
- if RESET = '1' then
- CODE_OUT <= (others => '0');
- elsif rising_edge(CLK) then
-
- CODE_OUT <= (others => '0');
-
- --**** HERE ADD YOU PROTOCOL RECOGNITION AT WANTED PRIORITY LEVEL
- -- priority level is the bit position in the CODE_OUT vector
- -- less significant bit has the higher priority
- case FRAME_TYPE_IN is
-
- -- IPv4
- when x"0800" =>
- if (PROTOCOL_CODE_IN = x"11") then -- UDP
- -- No. 2 = DHCP
- if (UDP_PROTOCOL_IN = x"0044") then -- DHCP Client
- CODE_OUT(1) <= '1';
- -- No. 4 = SCTRL
- elsif (UDP_PROTOCOL_IN = x"6590") then -- SCTRL module
- CODE_OUT(2) <= '1';
- else
- -- branch for pure IPv4
- CODE_OUT <= (others => '0');
- end if;
- -- No. 3 = ICMP
- elsif (PROTOCOL_CODE_IN = x"01") then -- ICMP
- CODE_OUT(4) <= '1';
- else
- CODE_OUT <= (others => '0');
- end if;
-
- -- No. 1 = ARP
- when x"0806" =>
- CODE_OUT(0) <= '1';
-
- -- last slot is reserved for Trash
- when others =>
- CODE_OUT <= (others => '0');
-
- end case;
-
- end if;
-
-end process PRIORITIZE;
-
-end trb_net16_gbe_protocol_prioritizer;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
--- multiplexes between different protocols and manages the responses
---
---
-
-
-entity trb_net16_gbe_protocol_selector is
- generic(
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- DO_SIMULATION : integer range 0 to 1 := 0
- );
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
- RESET_FOR_DHCP : in std_logic;
-
--- signals to/from main controller
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- PS_RESPONSE_READY_OUT : out std_logic;
-
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
--- singals to/from transmit controller with constructed response
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_RD_EN_IN : in std_logic;
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- MC_BUSY_IN : in std_logic;
-
- -- misc signals for response constructors
- DHCP_START_IN : in std_logic;
- DHCP_DONE_OUT : out std_logic;
-
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
-
- MAKE_RESET_OUT : out std_logic;
-
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
- CFG_READOUT_CTR_VALID_IN : in std_logic;
- CFG_INSERT_TTYPE_IN : in std_logic;
- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
-
- CFG_ADDITIONAL_HDR_IN : in std_logic;
-
- -- input for statistics from outside
- STAT_DATA_IN : in std_logic_vector(31 downto 0);
- STAT_ADDR_IN : in std_logic_vector(7 downto 0);
- STAT_DATA_RDY_IN : in std_logic;
- STAT_DATA_ACK_OUT : out std_logic;
-
- MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
- DATA_HIST_OUT : out hist_array;
- SCTRL_HIST_OUT : out hist_array
-);
-end trb_net16_gbe_protocol_selector;
-
-
-architecture trb_net16_gbe_protocol_selector of trb_net16_gbe_protocol_selector is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_protocol_selector : architecture is "GBE_MAIN_group";
-
-attribute syn_encoding : string;
-
-signal rd_en : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal resp_ready : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal tc_wr : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal tc_data : std_logic_vector(c_MAX_PROTOCOLS * 9 - 1 downto 0);
-signal tc_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal tc_type : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal busy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal selected : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal tc_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0);
-signal tc_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal tc_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal tc_src_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0);
-signal tc_src_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal tc_src_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal tc_ip_proto : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0);
-
--- plus 1 is for the outside
-signal stat_data : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal stat_addr : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0);
-signal stat_rdy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal stat_ack : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal tc_ip_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal tc_udp_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal tc_size_left : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal tc_flags_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-
-signal tc_data_not_valid : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
-type select_states is (IDLE, LOOP_OVER, SELECT_ONE, PROCESS_REQUEST, CLEANUP);
-signal select_current_state, select_next_state : select_states;
-attribute syn_encoding of select_current_state : signal is "onehot";
-
-signal state : std_logic_vector(3 downto 0);
-signal index : integer range 0 to c_MAX_PROTOCOLS - 1;
-
-signal mult : std_logic;
-
-signal tc_ident : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal zeros : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of state, mult : signal is true;
-attribute syn_preserve of state, mult : signal is true;
-
-
-begin
-
-zeros <= (others => '0');
-
--- protocol Nr. 1 ARP
-ARP : trb_net16_gbe_response_constructor_ARP
-generic map( STAT_ADDRESS_BASE => 6
-)
-port map (
- CLK => CLK,
- RESET => RESET,
-
--- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(0),
- PS_RESPONSE_READY_OUT => resp_ready(0),
- PS_BUSY_OUT => busy(0),
- PS_SELECTED_IN => selected(0),
-
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
-
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(1 * 9 - 1 downto 0 * 9),
- TC_FRAME_SIZE_OUT => tc_size(1 * 16 - 1 downto 0 * 16),
- TC_FRAME_TYPE_OUT => tc_type(1 * 16 - 1 downto 0 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(1 * 8 - 1 downto 0 * 8),
- TC_IDENT_OUT => tc_ident(1 * 16 - 1 downto 0 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(1 * 48 - 1 downto 0 * 48),
- TC_DEST_IP_OUT => tc_ip(1 * 32 - 1 downto 0 * 32),
- TC_DEST_UDP_OUT => tc_udp(1 * 16 - 1 downto 0 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(1 * 48 - 1 downto 0 * 48),
- TC_SRC_IP_OUT => tc_src_ip(1 * 32 - 1 downto 0 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(1 * 16 - 1 downto 0 * 16),
-
- STAT_DATA_OUT => stat_data(1 * 32 - 1 downto 0 * 32),
- STAT_ADDR_OUT => stat_addr(1 * 8 - 1 downto 0 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(0),
- STAT_DATA_ACK_IN => stat_ack(0),
- RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
- SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(1 * 64 - 1 downto 0 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
--- END OF INTERFACE
-);
-
--- protocol No. 2 DHCP
-DHCP : trb_net16_gbe_response_constructor_DHCP
-generic map( STAT_ADDRESS_BASE => 0
-)
-port map (
- CLK => CLK,
- RESET => RESET_FOR_DHCP, --RESET,
-
--- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(1),
- PS_RESPONSE_READY_OUT => resp_ready(1),
- PS_BUSY_OUT => busy(1),
- PS_SELECTED_IN => selected(1),
-
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
-
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(2 * 9 - 1 downto 1 * 9),
- TC_FRAME_SIZE_OUT => tc_size(2 * 16 - 1 downto 1 * 16),
- TC_FRAME_TYPE_OUT => tc_type(2 * 16 - 1 downto 1 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(2 * 8 - 1 downto 1 * 8),
- TC_IDENT_OUT => tc_ident(2 * 16 - 1 downto 1 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(2 * 48 - 1 downto 1 * 48),
- TC_DEST_IP_OUT => tc_ip(2 * 32 - 1 downto 1 * 32),
- TC_DEST_UDP_OUT => tc_udp(2 * 16 - 1 downto 1 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(2 * 48 - 1 downto 1 * 48),
- TC_SRC_IP_OUT => tc_src_ip(2 * 32 - 1 downto 1 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(2 * 16 - 1 downto 1 * 16),
-
- STAT_DATA_OUT => stat_data(2 * 32 - 1 downto 1 * 32),
- STAT_ADDR_OUT => stat_addr(2 * 8 - 1 downto 1 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(1),
- STAT_DATA_ACK_IN => stat_ack(1),
- RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
- SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
--- END OF INTERFACE
-
- DHCP_START_IN => DHCP_START_IN,
- DHCP_DONE_OUT => DHCP_DONE_OUT,
-
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
- );
-
- --protocol No. 3 Ping
-Ping : trb_net16_gbe_response_constructor_Ping
-generic map( STAT_ADDRESS_BASE => 3
-)
-port map (
- CLK => CLK,
- RESET => RESET,
-
----- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4),
- PS_RESPONSE_READY_OUT => resp_ready(4),
- PS_BUSY_OUT => busy(4),
- PS_SELECTED_IN => selected(4),
-
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
-
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9),
- TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16),
- TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8),
- TC_IDENT_OUT => tc_ident(5 * 16 - 1 downto 4 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48),
- TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32),
- TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48),
- TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16),
-
- STAT_DATA_OUT => open,
- STAT_ADDR_OUT => open,
- STAT_DATA_RDY_OUT => open,
- STAT_DATA_ACK_IN => '0',
- RECEIVED_FRAMES_OUT => open,
- SENT_FRAMES_OUT => open,
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(5 * 64 - 1 downto 4 * 64)
--- END OF INTERFACE
-);
-
-SCTRL : trb_net16_gbe_response_constructor_SCTRL
-generic map( STAT_ADDRESS_BASE => 8
-)
-port map (
- CLK => CLK,
- RESET => RESET,
-
--- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2),
- PS_RESPONSE_READY_OUT => resp_ready(2),
- PS_BUSY_OUT => busy(2),
- PS_SELECTED_IN => selected(2),
-
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
-
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9),
- TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16),
- TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8),
- TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48),
- TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32),
- TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48),
- TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16),
-
- STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32),
- STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(2),
- STAT_DATA_ACK_IN => stat_ack(2),
-
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(3 * 64 - 1 downto 2 * 64),
- -- END OF INTERFACE
-
- GSC_CLK_IN => GSC_CLK_IN,
- GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => GSC_INIT_READ_IN,
- GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
- GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
- GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
- GSC_BUSY_IN => GSC_BUSY_IN,
- CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN,
- MAKE_RESET_OUT => MAKE_RESET_OUT,
-
- MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(3 * 32 - 1 downto 2 * 32),
- MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(3 * 32 - 1 downto 2 * 32),
- MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(3 * 32 - 1 downto 2 * 32),
- MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(3 * 32 - 1 downto 2 * 32),
-
- DATA_HIST_OUT => SCTRL_HIST_OUT
-);
-
-TrbNetData : trb_net16_gbe_response_constructor_TrbNetData
-generic map(
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- DO_SIMULATION => DO_SIMULATION
- )
-port map (
- CLK => CLK,
- RESET => RESET,
-
--- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3),
- PS_RESPONSE_READY_OUT => resp_ready(3),
- PS_BUSY_OUT => busy(3),
- PS_SELECTED_IN => selected(3),
-
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
-
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9),
- TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16),
- TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8),
- TC_IDENT_OUT => tc_ident(4 * 16 - 1 downto 3 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48),
- TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32),
- TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48),
- TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16),
-
- STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32),
- STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(3),
- STAT_DATA_ACK_IN => stat_ack(3),
-
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64),
--- END OF INTERFACE
-
- -- CTS interface
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data payload interface
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
-
- CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
- CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
- CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
- CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN,
- CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN,
- CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
- CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN,
- CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
- CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
- CFG_MAX_SUB_IN => CFG_MAX_SUB_IN,
- CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN,
- CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
- CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN,
-
- MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_DROP_IN_OUT => open,
-
- DATA_HIST_OUT => DATA_HIST_OUT
-);
-
---stat_gen : if g_SIMULATE = 0 generate
---Stat : trb_net16_gbe_response_constructor_Stat
---generic map( STAT_ADDRESS_BASE => 10
---)
---port map (
--- CLK => CLK,
--- RESET => RESET,
---
----- INTERFACE
--- PS_DATA_IN => PS_DATA_IN,
--- PS_WR_EN_IN => PS_WR_EN_IN,
--- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4),
--- PS_RESPONSE_READY_OUT => resp_ready(4),
--- PS_BUSY_OUT => busy(4),
--- PS_SELECTED_IN => selected(4),
---
--- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
--- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
--- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
--- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
--- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
--- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
---
--- TC_WR_EN_OUT => TC_WR_EN_OUT,
--- TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9),
--- TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16),
--- TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16),
--- TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8),
---
--- TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48),
--- TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32),
--- TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16),
--- TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48),
--- TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32),
--- TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16),
---
--- TC_IP_SIZE_OUT => tc_ip_size(5 * 16 - 1 downto 4 * 16),
--- TC_UDP_SIZE_OUT => tc_udp_size(5 * 16 - 1 downto 4 * 16),
--- TC_FLAGS_OFFSET_OUT => tc_flags_size(5 * 16 - 1 downto 4 * 16),
---
--- TC_BUSY_IN => TC_BUSY_IN,
---
--- STAT_DATA_OUT => stat_data(5 * 32 - 1 downto 4 * 32),
--- STAT_ADDR_OUT => stat_addr(5 * 8 - 1 downto 4 * 8),
--- STAT_DATA_RDY_OUT => stat_rdy(4),
--- STAT_DATA_ACK_IN => stat_ack(4),
---
--- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
--- SENT_FRAMES_OUT => SENT_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
--- DEBUG_OUT => PROTOS_DEBUG_OUT(5 * 32 - 1 downto 4 * 32),
---
--- STAT_DATA_IN => stat_data,
--- STAT_ADDR_IN => stat_addr,
--- STAT_DATA_RDY_IN => stat_rdy,
--- STAT_DATA_ACK_OUT => stat_ack
---);
---end generate;
-
---***************
--- DO NOT TOUCH, response selection logic
-
---stat_data((c_MAX_PROTOCOLS + 1) * 32 - 1 downto c_MAX_PROTOCOLS * 32) <= STAT_DATA_IN;
---stat_addr((c_MAX_PROTOCOLS + 1) * 8 - 1 downto c_MAX_PROTOCOLS * 8) <= STAT_ADDR_IN;
---stat_rdy(c_MAX_PROTOCOLS) <= STAT_DATA_RDY_IN;
---STAT_DATA_ACK_OUT <= stat_ack(c_MAX_PROTOCOLS);
-
---mult <= or_all(resp_ready(2 downto 0)); --or_all(resp_ready(2 downto 0)) and or_all(resp_ready(4 downto 3));
-
-PS_BUSY_OUT <= busy;
-
-SELECT_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- select_current_state <= IDLE;
- elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- select_current_state <= IDLE;
--- else
- select_current_state <= select_next_state;
--- end if;
- end if;
-end process SELECT_MACHINE_PROC;
-
-SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index, zeros, busy)
-begin
-
- case (select_current_state) is
-
- when IDLE =>
- if (MC_BUSY_IN = '0') then
- select_next_state <= LOOP_OVER;
- else
- select_next_state <= IDLE;
- end if;
-
- when LOOP_OVER =>
- if (resp_ready /= zeros) then
- if (resp_ready(index) = '1') then
- select_next_state <= SELECT_ONE;
- elsif (index = c_MAX_PROTOCOLS) then
- select_next_state <= CLEANUP;
- else
- select_next_state <= LOOP_OVER;
- end if;
- else
- select_next_state <= CLEANUP;
- end if;
-
- when SELECT_ONE =>
- if (MC_BUSY_IN = '1') then
- select_next_state <= PROCESS_REQUEST;
- else
- select_next_state <= SELECT_ONE;
- end if;
-
- when PROCESS_REQUEST =>
- if (busy(index) = '0') then --if (MC_BUSY_IN = '0') then
- select_next_state <= CLEANUP;
- else
- select_next_state <= PROCESS_REQUEST;
- end if;
-
- when CLEANUP =>
- select_next_state <= IDLE;
-
- end case;
-
-end process SELECT_MACHINE;
-
-INDEX_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (select_current_state = IDLE) then
- index <= 0;
- elsif (select_current_state = LOOP_OVER and resp_ready(index) = '0') then
- index <= index + 1;
- else
- index <= index;
- end if;
- end if;
-end process INDEX_PROC;
-
-SELECTOR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (select_current_state = SELECT_ONE or select_current_state = PROCESS_REQUEST) then
- TC_DATA_OUT <= tc_data((index + 1) * 9 - 1 downto index * 9);
- TC_FRAME_SIZE_OUT <= tc_size((index + 1) * 16 - 1 downto index * 16);
- TC_FRAME_TYPE_OUT <= tc_type((index + 1) * 16 - 1 downto index * 16);
- TC_DEST_MAC_OUT <= tc_mac((index + 1) * 48 - 1 downto index * 48);
- TC_DEST_IP_OUT <= tc_ip((index + 1) * 32 - 1 downto index * 32);
- TC_DEST_UDP_OUT <= tc_udp((index + 1) * 16 - 1 downto index * 16);
- TC_SRC_MAC_OUT <= tc_src_mac((index + 1) * 48 - 1 downto index * 48);
- TC_SRC_IP_OUT <= tc_src_ip((index + 1) * 32 - 1 downto index * 32);
- TC_SRC_UDP_OUT <= tc_src_udp((index + 1) * 16 - 1 downto index * 16);
- TC_IP_PROTOCOL_OUT <= tc_ip_proto((index + 1) * 8 - 1 downto index * 8);
- TC_IDENT_OUT <= tc_ident((index + 1) * 16 - 1 downto index * 16);
- if (select_current_state = SELECT_ONE) then
- PS_RESPONSE_READY_OUT <= '1';
- selected(index) <= '0';
- else
- PS_RESPONSE_READY_OUT <= '0';
- selected(index) <= '1';
- end if;
- else
- TC_DATA_OUT <= (others => '0');
- TC_FRAME_SIZE_OUT <= (others => '0');
- TC_FRAME_TYPE_OUT <= (others => '0');
- TC_DEST_MAC_OUT <= (others => '0');
- TC_DEST_IP_OUT <= (others => '0');
- TC_DEST_UDP_OUT <= (others => '0');
- TC_SRC_MAC_OUT <= (others => '0');
- TC_SRC_IP_OUT <= (others => '0');
- TC_SRC_UDP_OUT <= (others => '0');
- TC_IP_PROTOCOL_OUT <= (others => '0');
- TC_IDENT_OUT <= (others => '0');
- PS_RESPONSE_READY_OUT <= '0';
- selected <= (others => '0');
- end if;
- end if;
-end process SELECTOR_PROC;
-
-end trb_net16_gbe_protocol_selector;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
--- controller has to control the rest of the logic (TX part, TS_MAC, HUB) accordingly to
--- the message received from receiver, frame checking is already done
---
-
-
-entity trb_net16_gbe_receive_control is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- signals to/from frame_receiver
- RC_DATA_IN : in std_logic_vector(8 downto 0);
- FR_RD_EN_OUT : out std_logic;
- FR_FRAME_VALID_IN : in std_logic;
- FR_GET_FRAME_OUT : out std_logic;
- FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0);
- FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
-
- FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
-
--- signals to/from main controller
- RC_RD_EN_IN : in std_logic;
- RC_Q_OUT : out std_logic_vector(8 downto 0);
- RC_FRAME_WAITING_OUT : out std_logic;
- RC_LOADING_DONE_IN : in std_logic;
- RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
- RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
--- statistics
- FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
- BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
-
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_receive_control;
-
-
-architecture trb_net16_gbe_receive_control of trb_net16_gbe_receive_control is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_receive_control : architecture is "GBE_MAIN_group";
-attribute syn_encoding : string;
-
-type load_states is (IDLE, PREPARE, WAIT_ONE, READY);
-signal load_current_state, load_next_state : load_states;
-attribute syn_encoding of load_current_state : signal is "onehot";
-
-signal frames_received_ctr : std_logic_vector(31 downto 0);
-signal frames_readout_ctr : std_logic_vector(31 downto 0);
-signal bytes_rec_ctr : std_logic_vector(31 downto 0);
-
-signal state : std_logic_vector(3 downto 0);
-signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal reset_prioritizer : std_logic;
-signal frame_waiting : std_logic;
-
--- debug only
-signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
-begin
-
-FR_RD_EN_OUT <= RC_RD_EN_IN;
-RC_Q_OUT <= RC_DATA_IN;
-RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN;
-RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN;
-RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN;
-RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN;
-RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN;
-RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN;
-RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN;
-
-protocol_prioritizer : trb_net16_gbe_protocol_prioritizer
-port map(
- CLK => CLK,
- RESET => reset_prioritizer,
-
- FRAME_TYPE_IN => FR_FRAME_PROTO_IN,
- PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN,
- UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN,
-
- CODE_OUT => proto_code
-);
-
-reset_prioritizer <= '1' when load_current_state = IDLE else '0';
-
---RC_FRAME_PROTO_OUT <= proto_code when (and_all(proto_code) = '0') else (others => '0');
-RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash
-
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(11 downto 4) <= frames_received_ctr(7 downto 0);
---DEBUG_OUT(19 downto 12) <= frames_readout_ctr(7 downto 0);
---DEBUG_OUT(31 downto 20) <= bytes_rec_ctr(11 downto 0);
-
-LOAD_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- load_current_state <= IDLE;
- elsif rising_edge(CLK) then
- load_current_state <= load_next_state;
- end if;
-end process LOAD_MACHINE_PROC;
-
-LOAD_MACHINE : process(load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN)
-begin
- case load_current_state is
-
- when IDLE =>
- state <= x"1";
- if (frames_readout_ctr /= frames_received_ctr) then -- frame is still waiting in frame_receiver
- load_next_state <= PREPARE;
- else
- load_next_state <= IDLE;
- end if;
-
- when PREPARE => -- prepare frame size
- state <= x"2";
- load_next_state <= WAIT_ONE; --READY;
-
- when WAIT_ONE =>
- load_next_state <= READY;
-
- when READY => -- wait for reading out the whole frame
- state <= x"3";
- if (RC_LOADING_DONE_IN = '1') then
- load_next_state <= IDLE;
- else
- load_next_state <= READY;
- end if;
-
- end case;
-end process LOAD_MACHINE;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = PREPARE) then
- FR_GET_FRAME_OUT <= '1';
- else
- FR_GET_FRAME_OUT <= '0';
- end if;
-
- if (load_current_state = READY and RC_LOADING_DONE_IN = '0') then
- RC_FRAME_WAITING_OUT <= '1';
- else
- RC_FRAME_WAITING_OUT <= '0';
- end if;
-
- --RC_FRAME_WAITING_OUT <= frame_waiting;
- end if;
-end process;
-
---FR_GET_FRAME_OUT <= '1' when (load_current_state = PREPARE)
--- else '0';
---
---RC_FRAME_WAITING_OUT <= '1' when (load_current_state = READY)
--- else '0';
-
---SYNC_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- FRAMES_RECEIVED_OUT <= frames_received_ctr;
--- --BYTES_RECEIVED_OUT <= bytes_rec_ctr;
--- BYTES_RECEIVED_OUT(15 downto 0) <= bytes_rec_ctr(15 downto 0);
--- BYTES_RECEIVED_OUT(16 + c_MAX_PROTOCOLS - 1 downto 16) <= saved_proto;
--- BYTES_RECEIVED_OUT(31 downto 16 + c_MAX_PROTOCOLS) <= (others => '0');
--- end if;
---end process SYNC_PROC;
-
-FRAMES_REC_CTR_PROC : process(RESET, CLK)
-begin
- if (RESET = '1') then
- frames_received_ctr <= (others => '0');
- elsif rising_edge(CLK) then
- if (FR_FRAME_VALID_IN = '1') then
- frames_received_ctr <= frames_received_ctr + x"1";
- else
- frames_received_ctr <= frames_received_ctr;
- end if;
- end if;
-end process FRAMES_REC_CTR_PROC;
-
-FRAMES_READOUT_CTR_PROC : process(RESET, CLK)
-begin
- if (RESET = '1') then
- frames_readout_ctr <= (others => '0');
- elsif rising_edge(CLK) then
- if (RC_LOADING_DONE_IN = '1') then
- frames_readout_ctr <= frames_readout_ctr + x"1";
- else
- frames_readout_ctr <= frames_readout_ctr;
- end if;
- end if;
-end process FRAMES_READOUT_CTR_PROC;
-
--- debug only
-BYTES_REC_CTR_PROC : process(RESET, CLK)
-begin
- if (RESET = '1') then
- bytes_rec_ctr <= (others => '0');
- elsif rising_edge(CLK) then
- if (FR_FRAME_VALID_IN = '1') then
- bytes_rec_ctr <= bytes_rec_ctr + FR_FRAME_SIZE_IN;
- else
- bytes_rec_ctr <= bytes_rec_ctr;
- end if;
- end if;
-end process BYTES_REC_CTR_PROC;
-
-SAVED_PROTO_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = READY) then
- if (and_all(proto_code) = '0') then
- saved_proto <= proto_code;
- else
- saved_proto <= (others => '0');
- end if;
- else
- saved_proto <= saved_proto;
- end if;
- end if;
-end process SAVED_PROTO_PROC;
--- end of debug
-
-
-end trb_net16_gbe_receive_control;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
--- creates a reply for an incoming ARP request
-
-entity trb_net16_gbe_response_constructor_ARP is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_response_constructor_ARP;
-
-
-architecture trb_net16_gbe_response_constructor_ARP of trb_net16_gbe_response_constructor_ARP is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_response_constructor_ARP : architecture is "GBE_MAIN_group";
-
-attribute syn_encoding : string;
-
-type dissect_states is (IDLE, READ_FRAME, DECIDE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "onehot";
-
-type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP);
-signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "onehot";
-
-signal saved_opcode : std_logic_vector(15 downto 0);
-signal saved_sender_ip : std_logic_vector(31 downto 0);
-signal saved_target_ip : std_logic_vector(31 downto 0);
-signal data_ctr : integer range 0 to 30;
-signal values : std_logic_vector(223 downto 0);
-signal tc_data : std_logic_vector(8 downto 0);
-
-signal state : std_logic_vector(3 downto 0);
-signal rec_frames : std_logic_vector(15 downto 0);
-signal sent_frames : std_logic_vector(15 downto 0);
-signal stat_data_temp : std_logic_vector(31 downto 0);
-
-signal tc_wr : std_logic;
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of state : signal is true;
-attribute syn_preserve of state : signal is true;
-
-begin
-
-values(15 downto 0) <= x"0100"; -- hardware type
-values(31 downto 16) <= x"0008"; -- protocol type
-values(39 downto 32) <= x"06"; -- hardware size
-values(47 downto 40) <= x"04"; -- protocol size
-values(63 downto 48) <= x"0200"; --opcode (reply)
-values(111 downto 64) <= g_MY_MAC; -- sender (my) mac
-values(143 downto 112) <= g_MY_IP;
-values(191 downto 144) <= PS_SRC_MAC_ADDRESS_IN; -- target mac
-values(223 downto 192) <= saved_sender_ip; -- target ip
-
-DISSECT_MACHINE_PROC : process(CLK)
-begin
- if RESET = '1' then
- dissect_current_state <= IDLE;
- elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- dissect_current_state <= IDLE;
--- else
- dissect_current_state <= dissect_next_state;
--- end if;
- end if;
-end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, g_MY_IP, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, PS_SELECTED_IN, saved_target_ip)
-begin
- case dissect_current_state is
-
- when IDLE =>
- state <= x"1";
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- dissect_next_state <= READ_FRAME;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when READ_FRAME =>
- state <= x"2";
- if (PS_DATA_IN(8) = '1') then
- dissect_next_state <= DECIDE;
- else
- dissect_next_state <= READ_FRAME;
- end if;
-
- when DECIDE =>
- state <= x"3";
- if (saved_target_ip = g_MY_IP or g_SIMULATE = 1) then
- dissect_next_state <= WAIT_FOR_LOAD;
- -- in case the request is not for me, drop it
- else
- dissect_next_state <= IDLE;
- end if;
-
- when WAIT_FOR_LOAD =>
- state <= x"4";
- if (PS_SELECTED_IN = '1') then
- dissect_next_state <= LOAD_FRAME;
- else
- dissect_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD_FRAME =>
- state <= x"5";
- if (data_ctr = 28) then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= LOAD_FRAME;
- end if;
-
- when CLEANUP =>
- state <= x"e";
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
-DATA_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (dissect_current_state = IDLE and PS_WR_EN_IN = '0') then
- data_ctr <= 1;
- elsif (dissect_current_state = WAIT_FOR_LOAD) then
- data_ctr <= 1;
- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- data_ctr <= data_ctr + 1;
- elsif (dissect_current_state = READ_FRAME and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- in case of saving data from incoming frame
- data_ctr <= data_ctr + 1;
- elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then -- in case of constructing response
- data_ctr <= data_ctr + 1;
- end if;
- end if;
-end process DATA_CTR_PROC;
-
---TC_WR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1') then
--- tc_wr <= '1';
--- else
--- tc_wr <= '0';
--- end if;
--- end if;
---end process TC_WR_PROC;
-
-SAVE_VALUES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saved_opcode <= (others => '0');
- saved_sender_ip <= (others => '0');
- saved_target_ip <= (others => '0');
- elsif (dissect_current_state = READ_FRAME) then
- case (data_ctr) is
-
- when 6 =>
- saved_opcode(7 downto 0) <= PS_DATA_IN(7 downto 0);
- when 7 =>
- saved_opcode(15 downto 8) <= PS_DATA_IN(7 downto 0);
-
-
- when 13 =>
- saved_sender_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
- when 14 =>
- saved_sender_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
- when 15 =>
- saved_sender_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
- when 16 =>
- saved_sender_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);
-
- when 23 =>
- saved_target_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
- when 24 =>
- saved_target_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
- when 25 =>
- saved_target_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
- when 26 =>
- saved_target_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);
-
- when others => null;
- end case;
- end if;
- end if;
-end process SAVE_VALUES_PROC;
-
-TC_DATA_PROC : process(dissect_current_state, data_ctr, values)
-begin
- if rising_edge(CLK) then
- tc_data(8) <= '0';
-
- if (dissect_current_state = LOAD_FRAME) then
- for i in 0 to 7 loop
- tc_data(i) <= values((data_ctr - 1) * 8 + i);
- end loop;
- -- mark the last byte
- if (data_ctr = 28) then
- tc_data(8) <= '1';
- end if;
- else
- tc_data(7 downto 0) <= (others => '0');
- end if;
-
- TC_DATA_OUT <= tc_data;
-
- end if;
-end process TC_DATA_PROC;
-
---TC_WR_EN_OUT <= tc_wr;
-
-PS_RESPONSE_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then
- PS_RESPONSE_READY_OUT <= '1';
- else
- PS_RESPONSE_READY_OUT <= '0';
- end if;
-
- if (dissect_current_state = IDLE) then
- PS_BUSY_OUT <= '0';
- else
- PS_BUSY_OUT <= '1';
- end if;
- end if;
-end process PS_RESPONSE_SYNC;
-
-
-
-TC_FRAME_SIZE_OUT <= x"001c"; -- fixed frame size
-
-TC_FRAME_TYPE_OUT <= x"0608";
-TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;
-TC_DEST_IP_OUT <= x"00000000"; -- doesnt matter
-TC_DEST_UDP_OUT <= x"0000"; -- doesnt matter
-TC_SRC_MAC_OUT <= g_MY_MAC;
-TC_SRC_IP_OUT <= x"00000000"; -- doesnt matter
-TC_SRC_UDP_OUT <= x"0000"; -- doesnt matter
-TC_IP_PROTOCOL_OUT <= x"00"; -- doesnt matter
-TC_IDENT_OUT <= (others => '0'); -- doesn't matter
-
-
--- **** statistice
---REC_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rec_frames <= (others => '0');
--- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
--- rec_frames <= rec_frames + x"1";
--- end if;
--- end if;
---end process REC_FRAMES_PROC;
---
---SENT_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- sent_frames <= (others => '0');
--- elsif (dissect_current_state = CLEANUP) then
--- sent_frames <= sent_frames + x"1";
--- end if;
--- end if;
---end process SENT_FRAMES_PROC;
---
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then
--- stats_next_state <= LOAD_SENT;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_SENT =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= LOAD_SENT;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_SENT =>
--- stat_data_temp <= x"0601" & sent_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0602" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
-----STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
---
----- **** debug
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(4) <= '0';
---DEBUG_OUT(7 downto 5) <= "000";
---DEBUG_OUT(8) <= '0';
---DEBUG_OUT(11 downto 9) <= "000";
---DEBUG_OUT(31 downto 12) <= (others => '0');
----- ****
-
-end trb_net16_gbe_response_constructor_ARP;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
---
-
-entity trb_net16_gbe_response_constructor_DHCP is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
- DHCP_START_IN : in std_logic;
- DHCP_DONE_OUT : out std_logic;
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_response_constructor_DHCP;
-
-
-architecture trb_net16_gbe_response_constructor_DHCP of trb_net16_gbe_response_constructor_DHCP is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_response_constructor_DHCP : architecture is "GBE_MAIN_group";
-
-attribute syn_encoding : string;
-
-type main_states is (BOOTING, DELAY, SENDING_DISCOVER, WAITING_FOR_OFFER, SENDING_REQUEST, WAITING_FOR_ACK, ESTABLISHED);
-signal main_current_state, main_next_state : main_states;
-attribute syn_encoding of main_current_state: signal is "onehot";
-
-type receive_states is (IDLE, DISCARD, CLEANUP, SAVE_VALUES);
-signal receive_current_state, receive_next_state : receive_states;
-attribute syn_encoding of receive_current_state: signal is "onehot";
-
-type discover_states is (IDLE, WAIT_FOR_LOAD, BOOTP_HEADERS, CLIENT_IP, YOUR_IP, ZEROS1, MY_MAC, ZEROS2, VENDOR_VALS, VENDOR_VALS2, TERMINATION, CLEANUP);
-signal construct_current_state, construct_next_state : discover_states;
-attribute syn_encoding of construct_current_state: signal is "onehot";
-
-
-type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, LOAD_DISCARDED, CLEANUP);
-signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "onehot";
-
-signal state : std_logic_vector(3 downto 0);
-signal rec_frames : std_logic_vector(15 downto 0);
-signal sent_frames : std_logic_vector(15 downto 0);
-
-signal wait_ctr : std_logic_vector(31 downto 0); -- wait for 5 sec before sending request
-signal load_ctr : integer range 0 to 600 := 0;
-
-signal bootp_hdr : std_logic_vector(95 downto 0);
-
-signal tc_data : std_logic_vector(8 downto 0);
-signal vendor_values : std_logic_vector(175 downto 0);
-signal save_ctr : integer range 0 to 600 := 0;
-signal saved_transaction_id : std_logic_vector(31 downto 0);
-signal saved_proposed_ip : std_logic_vector(31 downto 0);
-signal saved_dhcp_type : std_logic_vector(23 downto 0);
-signal saved_true_ip : std_logic_vector(31 downto 0);
-signal transaction_id : std_logic_vector(31 downto 0);
-signal client_ip_reg : std_logic_vector(31 downto 0);
-signal your_ip_reg : std_logic_vector(31 downto 0);
-signal saved_server_mac : std_logic_vector(47 downto 0);
-signal saved_server_ip : std_logic_vector(31 downto 0);
-signal state2 : std_logic_vector(3 downto 0);
-signal state3 : std_logic_vector(3 downto 0);
-signal vendor_values2 : std_logic_vector(47 downto 0);
-
-signal discarded_ctr : std_logic_vector(15 downto 0);
-
-signal stat_data_temp : std_logic_vector(31 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of state, state2 : signal is true;
-attribute syn_preserve of state, state2 : signal is true;
-
-begin
-
-
--- ****
--- fixing the constant values for DHCP request headers
-TC_DEST_MAC_OUT <= x"ffffffffffff" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else saved_server_mac;
-TC_DEST_IP_OUT <= x"ffffffff" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else saved_server_ip;
-TC_DEST_UDP_OUT <= x"4300";
-TC_SRC_MAC_OUT <= g_MY_MAC;
-TC_SRC_IP_OUT <= x"00000000" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else saved_proposed_ip;
-TC_SRC_UDP_OUT <= x"4400";
-TC_IP_PROTOCOL_OUT <= x"11"; -- udp
-bootp_hdr(7 downto 0) <= x"01"; -- message type(request)
-bootp_hdr(15 downto 8) <= x"01"; -- hardware type (eth)
-bootp_hdr(23 downto 16) <= x"06"; -- hardware address length
-bootp_hdr(31 downto 24) <= x"00"; -- hops
-bootp_hdr(63 downto 32) <= transaction_id; -- transaction id;
-bootp_hdr(95 downto 64) <= x"0000_0000"; -- seconds elapsed/flags
-transaction_id <= x"cefa" & g_MY_MAC(47 downto 32);
-vendor_values(31 downto 0) <= x"63538263"; -- magic cookie (dhcp message)
-vendor_values(55 downto 32) <= x"010135" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else x"030135"; -- dhcp discover, then dhcp request
-vendor_values(79 downto 56) <= x"01073d"; -- client identifier
-vendor_values(127 downto 80) <= g_MY_MAC; -- client identifier
-vendor_values(143 downto 128) <= x"040c"; -- client name
-vendor_values(175 downto 144) <= x"33425254"; -- client name (TRB3)
-vendor_values2(15 downto 0) <= x"0436"; -- server identifier
-vendor_values2(47 downto 16) <= saved_server_ip;
-
---*****************
--- setting of global variable for IP address
-g_MY_IP <= saved_true_ip when main_current_state = ESTABLISHED else (others => '0');
---
---*****************
-
-SAVE_SERVER_ADDR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (main_current_state = BOOTING) then
- saved_server_mac <= (others => '0');
- saved_server_ip <= (others => '0');
- elsif (main_current_state = WAITING_FOR_OFFER) and (receive_current_state = SAVE_VALUES and save_ctr = 1) then
- saved_server_mac <= PS_SRC_MAC_ADDRESS_IN;
- saved_server_ip <= PS_SRC_IP_ADDRESS_IN;
- else
- saved_server_mac <= saved_server_mac;
- saved_server_ip <= saved_server_ip;
- end if;
- end if;
-end process SAVE_SERVER_ADDR_PROC;
-
-
--- **** MAIN MACHINE PART
-
-MAIN_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- main_current_state <= BOOTING;
- elsif rising_edge(CLK) then
- main_current_state <= main_next_state;
- end if;
-end process MAIN_MACHINE_PROC;
-
-MAIN_MACHINE : process(main_current_state, DHCP_START_IN, construct_current_state, wait_ctr, receive_current_state, PS_DATA_IN)
-begin
-
- case (main_current_state) is
-
- when BOOTING =>
- state2 <= x"1";
- if (DHCP_START_IN = '1') then
- main_next_state <= DELAY;
- else
- main_next_state <= BOOTING;
- end if;
-
- when DELAY =>
- if (wait_ctr = x"2000_0000") then
- main_next_state <= SENDING_DISCOVER;
- else
- main_next_state <= DELAY;
- end if;
-
- when SENDING_DISCOVER =>
- state2 <= x"2";
- if (construct_current_state = CLEANUP) then
- main_next_state <= WAITING_FOR_OFFER;
- else
- main_next_state <= SENDING_DISCOVER;
- end if;
-
- when WAITING_FOR_OFFER =>
- state2 <= x"3";
- if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then
- main_next_state <= SENDING_REQUEST;
- elsif (wait_ctr = x"2000_0000") then
- main_next_state <= BOOTING;
- else
- main_next_state <= WAITING_FOR_OFFER;
- end if;
-
- when SENDING_REQUEST =>
- state2 <= x"4";
- if (construct_current_state = CLEANUP) then
- main_next_state <= WAITING_FOR_ACK;
- else
- main_next_state <= SENDING_REQUEST;
- end if;
-
- when WAITING_FOR_ACK =>
- state2 <= x"5";
- if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then
- main_next_state <= ESTABLISHED;
- elsif (wait_ctr = x"2000_0000") then
- main_next_state <= BOOTING;
- else
- main_next_state <= WAITING_FOR_ACK;
- end if;
-
- when ESTABLISHED =>
- state2 <= x"6";
- main_next_state <= ESTABLISHED;
-
- end case;
-
-end process MAIN_MACHINE;
-
-WAIT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (main_current_state = SENDING_DISCOVER or main_current_state = SENDING_REQUEST or main_current_state = BOOTING) then
- wait_ctr <= (others => '0');
- elsif (main_current_state = WAITING_FOR_ACK or main_current_state = WAITING_FOR_OFFER or main_current_state = DELAY) then
- wait_ctr <= wait_ctr + x"1";
- else
- wait_ctr <= wait_ctr;
- end if;
- end if;
-end process WAIT_CTR_PROC;
-
-DHCP_DONE_OUT <= '1' when main_current_state = ESTABLISHED else '0';
-
-
--- **** MESSAGES RECEIVING PART
-
-RECEIVE_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- receive_current_state <= IDLE;
- elsif rising_edge(CLK) then
- receive_current_state <= receive_next_state;
- end if;
-end process RECEIVE_MACHINE_PROC;
-
-RECEIVE_MACHINE : process(receive_current_state, main_current_state, bootp_hdr, saved_dhcp_type, saved_transaction_id, PS_DATA_IN, PS_DEST_MAC_ADDRESS_IN, g_MY_MAC, PS_ACTIVATE_IN, PS_WR_EN_IN, save_ctr)
-begin
- case receive_current_state is
-
- when IDLE =>
- state3 <= x"1";
- if (PS_ACTIVATE_IN = '1' and PS_WR_EN_IN = '1') then
- if (main_current_state = WAITING_FOR_OFFER or main_current_state = WAITING_FOR_ACK) then -- ready to receive dhcp frame
- if (PS_DEST_MAC_ADDRESS_IN = g_MY_MAC) then -- check if i'm the addressee (discards broadcasts also)
- receive_next_state <= SAVE_VALUES;
- else
- receive_next_state <= DISCARD; -- discard if the frame is not for me
- end if;
- else
- receive_next_state <= DISCARD; -- discard if the frame arrived at wrong time
- end if;
- else
- receive_next_state <= IDLE;
- end if;
-
- when SAVE_VALUES =>
- state3 <= x"2";
- if (PS_DATA_IN(8) = '1') then
- receive_next_state <= CLEANUP;
- -- check if the same transaction
- elsif (save_ctr = 9) and (saved_transaction_id /= bootp_hdr(63 downto 32)) then
- receive_next_state <= DISCARD;
- -- if the wrong message at the wrong time
- elsif (main_current_state = WAITING_FOR_OFFER) and (save_ctr = 242) and (saved_dhcp_type /= x"020135") then
- receive_next_state <= DISCARD;
- -- if the wrong message at the wrong time
- elsif (main_current_state = WAITING_FOR_ACK) and (save_ctr = 242) and (saved_dhcp_type /= x"050135") then
- receive_next_state <= DISCARD;
- else
- receive_next_state <= SAVE_VALUES;
- end if;
-
- when DISCARD =>
- state3 <= x"3";
- if (PS_DATA_IN(8) = '1') then
- receive_next_state <= CLEANUP;
- else
- receive_next_state <= DISCARD;
- end if;
-
- when CLEANUP =>
- state3 <= x"4";
- receive_next_state <= IDLE;
-
- end case;
-
-end process RECEIVE_MACHINE;
-
-SAVE_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (receive_current_state = IDLE) then
- save_ctr <= 0;
- elsif (receive_current_state = SAVE_VALUES and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- save_ctr <= save_ctr + 1;
- else
- save_ctr <= save_ctr;
- end if;
- end if;
-end process SAVE_CTR_PROC;
-
-SAVE_VALUES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (main_current_state = BOOTING) then
- saved_transaction_id <= (others => '0');
- saved_proposed_ip <= (others => '0');
- saved_true_ip <= (others => '0');
- saved_dhcp_type <= (others => '0');
- -- dissection of DHCP Offer message
- elsif (main_current_state = WAITING_FOR_OFFER and receive_current_state = SAVE_VALUES) then
-
- saved_true_ip <= saved_true_ip;
-
- case save_ctr is
-
- when 3 =>
- saved_transaction_id(7 downto 0) <= PS_DATA_IN(7 downto 0);
-
- when 4 =>
- saved_transaction_id(15 downto 8) <= PS_DATA_IN(7 downto 0);
-
- when 5 =>
- saved_transaction_id(23 downto 16) <= PS_DATA_IN(7 downto 0);
-
- when 6 =>
- saved_transaction_id(31 downto 24) <= PS_DATA_IN(7 downto 0);
-
-
- when 15 =>
- saved_proposed_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
-
- when 16 =>
- saved_proposed_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
-
- when 17 =>
- saved_proposed_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
-
- when 18 =>
- saved_proposed_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);
-
-
- when 239 =>
- saved_dhcp_type(7 downto 0) <= PS_DATA_IN(7 downto 0);
-
- when 240 =>
- saved_dhcp_type(15 downto 8) <= PS_DATA_IN(7 downto 0);
-
- when 241 =>
- saved_dhcp_type(23 downto 16) <= PS_DATA_IN(7 downto 0);
-
- when others => null;
-
- end case;
- -- dissection on DHCP Ack message
- elsif (main_current_state = WAITING_FOR_ACK and receive_current_state = SAVE_VALUES) then
-
- saved_proposed_ip <= saved_proposed_ip;
-
- case save_ctr is
-
- when 3 =>
- saved_transaction_id(7 downto 0) <= PS_DATA_IN(7 downto 0);
-
- when 4 =>
- saved_transaction_id(15 downto 8) <= PS_DATA_IN(7 downto 0);
-
- when 5 =>
- saved_transaction_id(23 downto 16) <= PS_DATA_IN(7 downto 0);
-
- when 6 =>
- saved_transaction_id(31 downto 24) <= PS_DATA_IN(7 downto 0);
-
-
- when 15 =>
- saved_true_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
-
- when 16 =>
- saved_true_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
-
- when 17 =>
- saved_true_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
-
- when 18 =>
- saved_true_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);
-
-
- when 239 =>
- saved_dhcp_type(7 downto 0) <= PS_DATA_IN(7 downto 0);
-
- when 240 =>
- saved_dhcp_type(15 downto 8) <= PS_DATA_IN(7 downto 0);
-
- when 241 =>
- saved_dhcp_type(23 downto 16) <= PS_DATA_IN(7 downto 0);
-
- when others => null;
-
- end case;
- else
- saved_transaction_id <= saved_transaction_id;
- saved_proposed_ip <= saved_proposed_ip;
- saved_true_ip <= saved_true_ip;
- saved_dhcp_type <= saved_dhcp_type;
- end if;
- end if;
-end process SAVE_VALUES_PROC;
-
-
--- **** MESSAGES CONSTRUCTING PART
-
-CONSTRUCT_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- construct_current_state <= IDLE;
- elsif rising_edge(CLK) then
- if (main_current_state = BOOTING) then
- construct_current_state <= IDLE;
- else
- construct_current_state <= construct_next_state;
- end if;
- end if;
-end process CONSTRUCT_MACHINE_PROC;
-
-CONSTRUCT_MACHINE : process(construct_current_state, main_current_state, load_ctr, PS_SELECTED_IN)
-begin
- case construct_current_state is
-
- when IDLE =>
- state <= x"1";
- if (main_current_state = SENDING_DISCOVER) or (main_current_state = SENDING_REQUEST) then
- construct_next_state <= WAIT_FOR_LOAD;
- else
- construct_next_state <= IDLE;
- end if;
-
- when WAIT_FOR_LOAD =>
- state <= x"2";
- if (PS_SELECTED_IN = '1') then
- construct_next_state <= BOOTP_HEADERS;
- else
- construct_next_state <= WAIT_FOR_LOAD;
- end if;
-
-
- when BOOTP_HEADERS =>
- state <= x"3";
- if (load_ctr = 11) then
- construct_next_state <= CLIENT_IP;
- else
- construct_next_state <= BOOTP_HEADERS;
- end if;
-
- when CLIENT_IP =>
- state <= x"5";
- if (load_ctr = 15) then
- construct_next_state <= YOUR_IP;
- else
- construct_next_state <= CLIENT_IP;
- end if;
-
- when YOUR_IP =>
- state <= x"b";
- if (load_ctr = 19) then
- construct_next_state <= ZEROS1;
- else
- construct_next_state <= YOUR_IP;
- end if;
-
- when ZEROS1 =>
- state <= x"c";
- if (load_ctr = 27) then
- construct_next_state <= MY_MAC;
- else
- construct_next_state <= ZEROS1;
- end if;
-
- when MY_MAC =>
- state <= x"6";
- if (load_ctr = 33) then
- construct_next_state <= ZEROS2;
- else
- construct_next_state <= MY_MAC;
- end if;
-
- when ZEROS2 =>
- state <= x"7";
- if (load_ctr = 235) then
- construct_next_state <= VENDOR_VALS;
- else
- construct_next_state <= ZEROS2;
- end if;
-
- when VENDOR_VALS =>
- state <= x"8";
- if (load_ctr = 257) then
- -- for discover it's enough of values
- if (main_current_state = SENDING_DISCOVER) then
- construct_next_state <= TERMINATION;
- -- for request there is some more values needed
- else
- construct_next_state <= VENDOR_VALS2;
- end if;
- else
- construct_next_state <= VENDOR_VALS;
- end if;
-
- when VENDOR_VALS2 =>
- state <= x"d";
- if (load_ctr = 263) then
- construct_next_state <= TERMINATION;
- else
- construct_next_state <= VENDOR_VALS2;
- end if;
-
- when TERMINATION =>
- state <= x"e";
- construct_next_state <= CLEANUP;
-
- when CLEANUP =>
- state <= x"9";
- construct_next_state <= IDLE;
-
- end case;
-end process CONSTRUCT_MACHINE;
-
-LOAD_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (construct_current_state = IDLE) then
- load_ctr <= 0;
- elsif (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') then
- load_ctr <= load_ctr + 1;
- else
- load_ctr <= load_ctr;
- end if;
- end if;
-end process LOAD_CTR_PROC;
-
-TC_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- case (construct_current_state) is
-
- when BOOTP_HEADERS =>
- for i in 0 to 7 loop
- tc_data(i) <= bootp_hdr(load_ctr * 8 + i);
- end loop;
- tc_data(8) <= '0';
-
- when CLIENT_IP =>
- if (main_current_state = SENDING_DISCOVER) then
- tc_data(7 downto 0) <= x"00";
- elsif (main_current_state = SENDING_REQUEST) then
- for i in 0 to 7 loop
- tc_data(i) <= saved_proposed_ip((load_ctr - 12) * 8 + i);
- end loop;
- end if;
- tc_data(8) <= '0';
-
- when YOUR_IP =>
- tc_data(7 downto 0) <= x"00";
- tc_data(8) <= '0';
-
- when ZEROS1 =>
- tc_data(7 downto 0) <= x"00";
- tc_data(8) <= '0';
-
- when MY_MAC =>
- for i in 0 to 7 loop
- tc_data(i) <= g_MY_MAC((load_ctr - 28) * 8 + i);
- end loop;
- tc_data(8) <= '0';
-
- when ZEROS2 =>
- tc_data(7 downto 0) <= x"00";
- tc_data(8) <= '0';
-
- when VENDOR_VALS =>
- for i in 0 to 7 loop
- tc_data(i) <= vendor_values((load_ctr - 236) * 8 + i);
- end loop;
- tc_data(8) <= '0';
-
- -- needed only for DHCP Request message
- when VENDOR_VALS2 =>
- for i in 0 to 7 loop
- tc_data(i) <= vendor_values2((load_ctr - 258) * 8 + i);
- end loop;
- tc_data(8) <= '0';
-
- when TERMINATION =>
- tc_data(7 downto 0) <= x"ff";
- tc_data(8) <= '1';
-
- when others =>
- tc_data(7 downto 0) <= x"00";
- tc_data(8) <= '0';
-
- end case;
-
- TC_DATA_OUT <= tc_data;
-
- end if;
-end process;
-
-PS_RESPONSE_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (construct_current_state = IDLE or construct_current_state = CLEANUP) then
- PS_RESPONSE_READY_OUT <= '0';
- else
- PS_RESPONSE_READY_OUT <= '1';
- end if;
-
- if (construct_current_state = IDLE) then
- PS_BUSY_OUT <= '0';
- else
- PS_BUSY_OUT <= '1';
- end if;
- end if;
-end process PS_RESPONSE_SYNC;
-
--- fixed sizes for discover and request messages
-TC_FRAME_SIZE_OUT <= x"0103" when (main_current_state = SENDING_DISCOVER) else x"0109";
-
-TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip
-
-TC_IDENT_OUT <= x"1" & sent_frames(11 downto 0);
-
-
--- **** statistics
---REC_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rec_frames <= (others => '0');
--- elsif (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') then
--- rec_frames <= rec_frames + x"1";
--- end if;
--- end if;
---end process REC_FRAMES_PROC;
---
--- needed for identification
-SENT_FRAMES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- sent_frames <= (others => '0');
- elsif (construct_current_state = CLEANUP) then
- sent_frames <= sent_frames + x"1";
- end if;
- end if;
-end process SENT_FRAMES_PROC;
---
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, STAT_DATA_ACK_IN, PS_DATA_IN, construct_current_state, receive_current_state)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') or (construct_current_state = CLEANUP) or (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then
--- stats_next_state <= LOAD_SENT;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_SENT =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= LOAD_SENT;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_DISCARDED;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when LOAD_DISCARDED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_DISCARDED;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_SENT =>
--- stat_data_temp <= x"0101" & sent_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0102" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when LOAD_DISCARDED =>
--- stat_data_temp <= x"0103" & discarded_ctr;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 2, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
--- ****
-
-
--- **** debug
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(7 downto 4) <= state2;
---DEBUG_OUT(11 downto 8) <= state3;
---DEBUG_OUT(15 downto 12) <= (others => '0');
---DEBUG_OUT(31 downto 16) <= discarded_ctr;
---
---DISCARDED_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- discarded_ctr <= (others => '0');
--- elsif (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then
--- discarded_ctr <= discarded_ctr + x"1";
--- end if;
--- end if;
---end process DISCARDED_CTR_PROC;
--- ****
-
-end trb_net16_gbe_response_constructor_DHCP;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-
---********
--- Response Constructor which forwards received frame back ceating a loopback
---
-
-entity trb_net16_gbe_response_constructor_Forward is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- TC_BUSY_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_response_constructor_Forward;
-
-
-architecture trb_net16_gbe_response_constructor_Forward of trb_net16_gbe_response_constructor_Forward is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_response_constructor_Forward : architecture is "GBE_MAIN_group";
-
-attribute syn_encoding : string;
-
-type dissect_states is (IDLE, SAVE, WAIT_FOR_LOAD, LOAD, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "safe,gray";
-
-signal ff_wr_en : std_logic;
-signal ff_rd_en : std_logic;
-signal resp_bytes_ctr : std_logic_vector(15 downto 0);
-signal ff_empty : std_logic;
-signal ff_full : std_logic;
-signal ff_q : std_logic_vector(8 downto 0);
-signal ff_rd_lock : std_logic;
-
-signal state : std_logic_vector(3 downto 0);
-signal rec_frames : std_logic_vector(15 downto 0);
-signal sent_frames : std_logic_vector(15 downto 0);
-
-begin
-
-DISSECT_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- dissect_current_state <= IDLE;
- else
- dissect_current_state <= dissect_next_state;
- end if;
- end if;
-end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, ff_q, ff_rd_lock, TC_BUSY_IN)
-begin
- case dissect_current_state is
-
- when IDLE =>
- state <= x"1";
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- dissect_next_state <= SAVE;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when SAVE =>
- state <= x"2";
- if (PS_DATA_IN(8) = '1') then
- dissect_next_state <= WAIT_FOR_LOAD;
- else
- dissect_next_state <= SAVE;
- end if;
-
- when WAIT_FOR_LOAD =>
- state <= x"3";
- if (TC_BUSY_IN = '0') then
- dissect_next_state <= LOAD;
- else
- dissect_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD =>
- state <= x"4";
- if (ff_q(8) = '1') and (ff_rd_lock = '0') then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= LOAD;
- end if;
-
- when CLEANUP =>
- state <= x"5";
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
---PS_BUSY_OUT <= '1' when ff_wr_en = '1' else '0';
-PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1';
-
-ff_wr_en <= '1' when (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') else '0';
-
-FF_RD_LOCK_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- ff_rd_lock <= '1';
- elsif (dissect_current_state = LOAD and ff_rd_en = '1') then
- ff_rd_lock <= '0';
- else
- ff_rd_lock <= '1';
- end if;
- end if;
-end process FF_RD_LOCK_PROC;
-
-FRAME_FIFO: fifo_4096x9
-port map(
- Data => PS_DATA_IN,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => ff_wr_en,
- RdEn => ff_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q => ff_q,
- Empty => ff_empty,
- Full => ff_full
-);
-
-ff_rd_en <= '1' when (TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') else '0';
-
-TC_DATA_OUT <= ff_q;
-
-PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) else '0';
-
-TC_FRAME_SIZE_OUT <= resp_bytes_ctr + x"1";
-
-TC_FRAME_TYPE_OUT <= x"0008";
-TC_DEST_MAC_OUT <= x"9a680f201300";
-TC_DEST_IP_OUT <= x"0100a8c0";
-TC_DEST_UDP_OUT <= x"50c3";
-TC_SRC_MAC_OUT <= x"efbeefbe0000";
-TC_SRC_IP_OUT <= x"0b00a8c0";
-TC_SRC_UDP_OUT <= x"50c3";
-TC_IP_PROTOCOL_OUT <= x"11";
-
-RESP_BYTES_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (dissect_current_state = IDLE) then
- resp_bytes_ctr <= (others => '0');
- elsif (dissect_current_state = SAVE) then
- resp_bytes_ctr <= resp_bytes_ctr + x"1";
- end if;
- end if;
-end process RESP_BYTES_CTR_PROC;
-
-REC_FRAMES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- rec_frames <= (others => '0');
- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- rec_frames <= rec_frames + x"1";
- end if;
- end if;
-end process REC_FRAMES_PROC;
-
-SENT_FRAMES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- sent_frames <= (others => '0');
- elsif (dissect_current_state = WAIT_FOR_LOAD and TC_BUSY_IN = '0') then
- sent_frames <= sent_frames + x"1";
- end if;
- end if;
-end process SENT_FRAMES_PROC;
-
-RECEIVED_FRAMES_OUT <= rec_frames;
-SENT_FRAMES_OUT <= sent_frames;
-
--- **** debug
-DEBUG_OUT(3 downto 0) <= state;
-DEBUG_OUT(4) <= ff_empty;
-DEBUG_OUT(7 downto 5) <= "000";
-DEBUG_OUT(8) <= ff_full;
-DEBUG_OUT(11 downto 9) <= "000";
-DEBUG_OUT(31 downto 12) <= (others => '0');
--- ****
-
-end trb_net16_gbe_response_constructor_Forward;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
--- Response Constructor which responds to Ping messages
---
-
-entity trb_net16_gbe_response_constructor_Ping is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_response_constructor_Ping;
-
-
-architecture trb_net16_gbe_response_constructor_Ping of trb_net16_gbe_response_constructor_Ping is
-
-attribute syn_encoding : string;
-
-type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "onehot";
-
-type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP);
-signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "onehot";
-
-signal sent_frames : std_logic_vector(15 downto 0);
-
-signal saved_data : std_logic_vector(447 downto 0);
-signal saved_headers : std_logic_vector(63 downto 0);
-
-signal data_ctr : integer range 1 to 1500;
-signal data_length : integer range 1 to 1500;
-signal tc_data : std_logic_vector(8 downto 0);
-
-signal checksum : std_logic_vector(15 downto 0);
-
-signal checksum_l, checksum_r : std_logic_vector(19 downto 0);
-signal checksum_ll, checksum_rr : std_logic_vector(15 downto 0);
-signal checksum_lll, checksum_rrr : std_logic_vector(15 downto 0);
-
-begin
-
-DISSECT_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- dissect_current_state <= IDLE;
- elsif rising_edge(CLK) then
- dissect_current_state <= dissect_next_state;
- end if;
-end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_SELECTED_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length)
-begin
- case dissect_current_state is
-
- when IDLE =>
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- dissect_next_state <= READ_FRAME;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when READ_FRAME =>
- if (PS_DATA_IN(8) = '1') then
- dissect_next_state <= WAIT_FOR_LOAD;
- else
- dissect_next_state <= READ_FRAME;
- end if;
-
- when WAIT_FOR_LOAD =>
- if (PS_SELECTED_IN = '1') then
- dissect_next_state <= LOAD_FRAME;
- else
- dissect_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD_FRAME =>
- if (data_ctr = data_length + 1) then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= LOAD_FRAME;
- end if;
-
- when CLEANUP =>
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
-DATA_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (dissect_current_state = IDLE) or (dissect_current_state = WAIT_FOR_LOAD) then
- data_ctr <= 2;
- elsif (dissect_current_state = READ_FRAME and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- in case of saving data from incoming frame
- data_ctr <= data_ctr + 1;
- elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then -- in case of constructing response
- data_ctr <= data_ctr + 1;
- end if;
- end if;
-end process DATA_CTR_PROC;
-
-DATA_LENGTH_PROC: process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- data_length <= 1;
- elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then
- data_length <= data_ctr;
- end if;
- end if;
-end process DATA_LENGTH_PROC;
-
-SAVE_VALUES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (dissect_current_state = IDLE) then
- saved_headers <= (others => '0');
- saved_data <= (others => '0');
- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- saved_headers(7 downto 0) <= PS_DATA_IN(7 downto 0);
- elsif (dissect_current_state = READ_FRAME) then
- if (data_ctr < 9) then -- headers
- saved_headers(data_ctr * 8 - 1 downto (data_ctr - 1) * 8) <= PS_DATA_IN(7 downto 0);
- elsif (data_ctr > 8) then -- data
- saved_data((data_ctr - 8) * 8 - 1 downto (data_ctr - 8 - 1) * 8) <= PS_DATA_IN(7 downto 0);
- end if;
- elsif (dissect_current_state = LOAD_FRAME) then
- saved_headers(7 downto 0) <= x"00";
- saved_headers(23 downto 16) <= checksum(7 downto 0);
- saved_headers(31 downto 24) <= checksum(15 downto 8);
- end if;
- end if;
-end process SAVE_VALUES_PROC;
-
-CS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (dissect_current_state = IDLE) then
- checksum_l(19 downto 0) <= (others => '0');
- checksum_r(19 downto 0) <= (others => '0');
- checksum_ll(15 downto 0) <= (others => '0');
- checksum_rr(15 downto 0) <= (others => '0');
- checksum_lll(15 downto 0) <= (others => '0');
- checksum_rrr(15 downto 0) <= (others => '0');
- elsif (dissect_current_state = READ_FRAME and data_ctr > 4) then
- if (std_logic_vector(to_unsigned(data_ctr, 1)) = "0") then
- checksum_l <= checksum_l + PS_DATA_IN(7 downto 0);
- else
- checksum_r <= checksum_r + PS_DATA_IN(7 downto 0);
- end if;
- checksum_ll <= checksum_ll;
- checksum_lll <= checksum_lll;
- checksum_rr <= checksum_rr;
- checksum_rrr <= checksum_rrr;
- elsif (dissect_current_state = WAIT_FOR_LOAD) then
- checksum_ll <= x"0000" + checksum_l(7 downto 0) + checksum_r(19 downto 8);
- checksum_rr <= x"0000" + checksum_r(7 downto 0) + checksum_l(19 downto 8);
- checksum_l <= checksum_l;
- checksum_lll <= checksum_lll;
- checksum_r <= checksum_r;
- checksum_rrr <= checksum_rrr;
- elsif (dissect_current_state = LOAD_FRAME and data_ctr = 2) then
- checksum_lll <= x"0000" + checksum_ll(7 downto 0) + checksum_rr(15 downto 8);
- checksum_rrr <= x"0000" + checksum_rr(7 downto 0) + checksum_ll(15 downto 8);
- checksum_l <= checksum_l;
- checksum_ll <= checksum_ll;
- checksum_r <= checksum_r;
- checksum_rr <= checksum_rr;
- else
- checksum_l <= checksum_l;
- checksum_ll <= checksum_ll;
- checksum_lll <= checksum_lll;
- checksum_r <= checksum_r;
- checksum_rr <= checksum_rr;
- checksum_rrr <= checksum_rrr;
- end if;
- end if;
-end process CS_PROC;
-checksum(7 downto 0) <= not (checksum_rrr(7 downto 0) + checksum_lll(15 downto 8));
-checksum(15 downto 8) <= not (checksum_lll(7 downto 0) + checksum_rrr(15 downto 8));
-
-TC_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- tc_data(8) <= '0';
-
- if (dissect_current_state = LOAD_FRAME) then
- if (data_ctr < 10) then -- headers
- for i in 0 to 7 loop
- tc_data(i) <= saved_headers((data_ctr - 2) * 8 + i);
- end loop;
- else -- data
- for i in 0 to 7 loop
- tc_data(i) <= saved_data((data_ctr - 8 - 2) * 8 + i);
- end loop;
-
- -- mark the last byte
- if (data_ctr = data_length + 1) then
- tc_data(8) <= '1';
- end if;
- end if;
- else
- tc_data(7 downto 0) <= (others => '0');
- end if;
-
- TC_DATA_OUT <= tc_data;
-
- end if;
-end process TC_DATA_PROC;
-
-PS_RESPONSE_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then
- PS_RESPONSE_READY_OUT <= '1';
- else
- PS_RESPONSE_READY_OUT <= '0';
- end if;
-
- if (dissect_current_state = IDLE) then
- PS_BUSY_OUT <= '0';
- else
- PS_BUSY_OUT <= '1';
- end if;
- end if;
-end process PS_RESPONSE_SYNC;
-
-TC_FRAME_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16));
-TC_FRAME_TYPE_OUT <= x"0008";
-TC_DEST_UDP_OUT <= x"0000"; -- not used
-TC_SRC_MAC_OUT <= g_MY_MAC;
-TC_SRC_IP_OUT <= g_MY_IP;
-TC_SRC_UDP_OUT <= x"0000"; -- not used
-TC_IP_PROTOCOL_OUT <= X"01"; -- ICMP
-TC_IDENT_OUT <= x"2" & sent_frames(11 downto 0);
-
-ADDR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = READ_FRAME) then
- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;
- TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN;
- end if;
- end if;
-end process ADDR_PROC;
-
--- statistics
---
---REC_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rec_frames <= (others => '0');
--- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
--- rec_frames <= rec_frames + x"1";
--- end if;
--- end if;
---end process REC_FRAMES_PROC;
---
--- needed for identification
-SENT_FRAMES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- sent_frames <= (others => '0');
- elsif (dissect_current_state = CLEANUP) then
- sent_frames <= sent_frames + x"1";
- end if;
- end if;
-end process SENT_FRAMES_PROC;
---
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, STAT_DATA_ACK_IN, PS_DATA_IN, dissect_current_state)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then
--- stats_next_state <= LOAD_SENT;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_SENT =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= LOAD_SENT;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_SENT =>
--- stat_data_temp <= x"0401" & sent_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0402" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
---STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
-
--- **** debug
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(4) <= '0';
---DEBUG_OUT(7 downto 5) <= "000";
---DEBUG_OUT(8) <= '0';
---DEBUG_OUT(11 downto 9) <= "000";
---DEBUG_OUT(31 downto 12) <= (others => '0');
--- ****
-
-end trb_net16_gbe_response_constructor_Ping;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-
-entity trb_net16_gbe_response_constructor_SCTRL is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
- port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
- -- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- DEBUG_OUT : out std_logic_vector(63 downto 0);
- -- END OF INTERFACE
-
- -- protocol specific ports
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
- MAKE_RESET_OUT : out std_logic;
- CFG_ADDITIONAL_HDR_IN : in std_logic;
- -- end of protocol specific ports
-
- MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0);
-
- DATA_HIST_OUT : out hist_array
- );
-end entity trb_net16_gbe_response_constructor_SCTRL;
-
-architecture RTL of trb_net16_gbe_response_constructor_SCTRL is
-
-attribute syn_encoding : string;
-
---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
-type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);
---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_A_WORD, WAIT_ONE, WAIT_TWO, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "onehot";
-
-type stats_states is (IDLE, LOAD_RECEIVED, LOAD_REPLY, CLEANUP);
-signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "onehot";
-
-signal saved_target_ip : std_logic_vector(31 downto 0);
-signal data_ctr : integer range 0 to 30;
-
-
-signal stat_data_temp : std_logic_vector(31 downto 0);
-signal rec_frames : std_logic_vector(15 downto 0);
-
-signal rx_fifo_q : std_logic_vector(17 downto 0);
-signal rx_fifo_qq : std_logic_vector(17 downto 0);
-signal rx_fifo_wr, rx_fifo_rd : std_logic;
-signal tx_eod, rx_eod : std_logic;
-
-signal tx_fifo_q : std_logic_vector(8 downto 0);
-signal tx_fifo_wr, tx_fifo_rd : std_logic;
-signal tx_fifo_reset : std_logic;
-signal gsc_reply_read : std_logic;
-signal gsc_init_dataready : std_logic;
-signal gsc_init_dataready_q : std_logic;
-
-signal tx_data_ctr : std_logic_vector(15 downto 0);
-signal tx_loaded_ctr : std_logic_vector(15 downto 0);
-signal tx_frame_loaded : std_logic_vector(15 downto 0);
-
-signal packet_num : std_logic_vector(2 downto 0);
-
-signal init_ctr, reply_ctr : std_logic_vector(15 downto 0);
-signal rx_empty, tx_empty : std_logic;
-
-signal rx_full, tx_full : std_logic;
-
-signal size_left : std_logic_vector(15 downto 0);
-
-signal reset_detected : std_logic := '0';
-signal make_reset : std_logic := '0';
-
-
-signal fifo_rd_q : std_logic;
-
-signal too_much_data : std_logic;
-
-signal rx_fifo_data : std_logic_vector(8 downto 0);
-signal tx_fifo_data : std_logic_vector(17 downto 0);
-
-signal tc_wr : std_logic;
-signal state : std_logic_vector(3 downto 0);
-signal saved_hdr_1 : std_logic_vector(7 downto 0) := x"ab";
-signal saved_hdr_2 : std_logic_vector(7 downto 0) := x"cd";
-signal saved_hdr_ctr : std_logic_vector(3 downto 0);
-
-signal mon_rec_frames, mon_rec_bytes, mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true;
-attribute syn_preserve of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true;
-
-signal hist_inst : hist_array;
-signal reset_all_hist : std_logic_vector(31 downto 0);
-
-begin
-
-MAKE_RESET_OUT <= make_reset;
-
-receive_fifo : fifo_2048x8x16
- PORT map(
- Reset => RESET,
- RPReset => RESET,
- WrClock => CLK,
- RdClock => CLK,
- Data => rx_fifo_data,
- WrEn => rx_fifo_wr,
- RdEn => rx_fifo_rd,
- Q => rx_fifo_q,
- Full => rx_full,
- Empty => rx_empty
- );
-
---TODO: change to synchronous
-rx_fifo_rd <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or
- (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or
- (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1')
- else '0'; -- preload first word
-
-RX_FIFO_WR_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
-
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and (saved_hdr_ctr = "0100" or saved_hdr_ctr = "1000")) then
- rx_fifo_wr <= '1';
- else
- rx_fifo_wr <= '0';
- end if;
-
- rx_fifo_data <= PS_DATA_IN;
- end if;
-end process RX_FIFO_WR_SYNC;
-
-SAVED_HDR_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = IDLE and PS_WR_EN_IN = '0' and PS_ACTIVATE_IN = '0') then
- saved_hdr_ctr <= "0001";
- elsif (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr /= "1000") then
- saved_hdr_ctr(3 downto 0) <= saved_hdr_ctr(2 downto 0) & '0';
- else
- saved_hdr_ctr <= saved_hdr_ctr;
- end if;
- end if;
-end process SAVED_HDR_CTR_PROC;
-
-SAVED_HDR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- if (saved_hdr_ctr = "0001") then
- saved_hdr_1 <= PS_DATA_IN(7 downto 0);
- saved_hdr_2 <= saved_hdr_2;
- elsif (saved_hdr_ctr = "0010") then
- saved_hdr_2 <= PS_DATA_IN(7 downto 0);
- saved_hdr_1 <= saved_hdr_1;
- else
- saved_hdr_1 <= saved_hdr_1;
- saved_hdr_2 <= saved_hdr_2;
- end if;
- else
- saved_hdr_1 <= saved_hdr_1;
- saved_hdr_2 <= saved_hdr_2;
- end if;
- end if;
-end process SAVED_HDR_PROC;
-
---RX_FIFO_RD_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
---
--- if (dissect_current_state = LOAD_A_WORD) then
--- rx_fifo_rd <= '1';
--- else
--- rx_fifo_rd <= '0';
--- end if;
---
----- if (dissect_current_state = WAIT_ONE) then
----- gsc_init_dataready <= '1';
----- elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '0') then
----- gsc_init_dataready <= '1';
----- else
----- gsc_init_dataready <= '0';
----- end if;
---
----- if (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then -- preload the first byte
----- rx_fifo_rd <= '1';
----- elsif (dissect_current_state = LOAD_TO_HUB) then
----- rx_fifo_rd <= '1';
----- elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') then
----- rx_fifo_rd <= '1';
----- else
----- rx_fifo_rd <= '0';
----- end if;
-----
----- if (dissect_current_state = WAIT_FOR_HUB) then
----- gsc_init_dataready <= '1';
----- elsif (dissect_current_state = LOAD_TO_HUB and GSC_INIT_READ_IN = '1') then
----- gsc_init_dataready <= '1';
----- else
----- gsc_init_dataready <= '0';
----- end if;
-----
----- if (dissect_current_state = WAIT_FOR_HUB) then
----- packet_num <= "100";
----- elsif (dissect_current_state = LOAD_TO_HUB) then
----- if (gsc_init_dataready = '1' and packet_num = "100") then
----- packet_num <= "000";
----- elsif (gsc_init_dataready = '1' and packet_num /= "100") then
----- packet_num <= packet_num + "1";
----- else
----- packet_num <= packet_num;
----- end if;
----- else
----- packet_num <= packet_num;
----- end if;
---
--- if (dissect_current_state = READ_FRAME) then
--- packet_num <= "011";
--- elsif (dissect_current_state = LOAD_A_WORD) then
--- if (packet_num = "100") then
--- packet_num <= "000";
--- else
--- packet_num <= packet_num + "1";
--- end if;
--- else
--- packet_num <= packet_num;
--- end if;
---
--- GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9);
--- GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0);
---
--- --GSC_INIT_DATAREADY_OUT <= gsc_init_dataready;
---
----- GSC_INIT_PACKET_NUM_OUT <= packet_num;
---
--- end if;
---end process RX_FIFO_RD_SYNC;
---
---GSC_INIT_DATAREADY_OUT <= '1' when dissect_current_state = WAIT_FOR_HUB else '0';
-
-----TODO: add a register
-GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9);
-GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0);
-
------- TODO: change it to synchronous
-GSC_INIT_PACKET_NUM_OUT <= packet_num;
-GSC_INIT_DATAREADY_OUT <= gsc_init_dataready;
-gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or
- (dissect_current_state = WAIT_FOR_HUB) else '0';
-
-PACKET_NUM_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = IDLE) then
- packet_num <= "100";
- elsif (GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100") then
- packet_num <= "000";
- elsif (rx_fifo_rd = '1' and packet_num /= "100") then
- packet_num <= packet_num + "1";
- end if;
- end if;
-end process PACKET_NUM_PROC;
-
---temporairly changed to a smaller fifo
-transmit_fifo : fifo_65536x18x9 --fifo_4kx18x9 --fifo_65536x18x9
- PORT map(
- Reset => tx_fifo_reset,
- RPReset => tx_fifo_reset,
- WrClock => CLK,
- RdClock => CLK,
- Data => tx_fifo_data,
- WrEn => tx_fifo_wr,
- RdEn => tx_fifo_rd,
- Q => tx_fifo_q,
- Full => tx_full,
- Empty => tx_empty
- );
-
-TX_FIFO_WR_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') then
- tx_fifo_wr <= '1';
- elsif (saved_hdr_ctr = "0010") then
- tx_fifo_wr <= '1';
- else
- tx_fifo_wr <= '0';
- end if;
-
- if (saved_hdr_ctr = "010") then
- tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02";
- else
- tx_fifo_data(7 downto 0) <= GSC_REPLY_DATA_IN(15 downto 8);
- tx_fifo_data(8) <= '0';
- tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0);
- tx_fifo_data(17) <= '0';
- end if;
- end if;
-end process TX_FIFO_WR_SYNC;
-
---TX_FIFO_RD_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and tx_frame_loaded /= g_MAX_FRAME_SIZE) then
--- tx_fifo_rd <= '1';
--- else
--- tx_fifo_rd <= '0';
--- end if;
--- end if;
---end process TX_FIFO_RD_SYNC;
-tx_fifo_rd <= '1' when TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' else '0';
-
-TX_FIFO_SYNC_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (too_much_data = '1' and dissect_current_state = CLEANUP) then
- tx_fifo_reset <= '1';
- else
- tx_fifo_reset <= '0';
- end if;
- end if;
-end process TX_FIFO_SYNC_PROC;
-
-TC_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
-
- TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0);
-
- --if (tx_loaded_ctr = tx_data_ctr + x"1" or tx_frame_loaded = g_MAX_FRAME_SIZE - x"1") then
- if (tx_loaded_ctr = tx_data_ctr) then
- TC_DATA_OUT(8) <= '1';
- else
- TC_DATA_OUT(8) <= '0';
- end if;
- end if;
-end process TC_DATA_PROC;
-
-GSC_REPLY_READ_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE) then
- gsc_reply_read <= '1';
- else
- gsc_reply_read <= '0';
- end if;
- end if;
-end process GSC_REPLY_READ_PROC;
-GSC_REPLY_READ_OUT <= gsc_reply_read;
-
--- counter of data received from TRBNet hub
-TX_DATA_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = IDLE) then
- tx_data_ctr <= (others => '0');
- elsif (tx_fifo_wr = '1') then
- tx_data_ctr <= tx_data_ctr + x"2";
- end if;
- end if;
-end process TX_DATA_CTR_PROC;
-
-TOO_MUCH_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = IDLE) then
- too_much_data <= '0';
- elsif (dissect_current_state = SAVE_RESPONSE) and (tx_data_ctr = x"fa00") then
- too_much_data <= '1';
- end if;
- end if;
-end process TOO_MUCH_DATA_PROC;
-
--- total counter of data transported to frame constructor
-TX_LOADED_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = IDLE) then
- tx_loaded_ctr <= x"0000";
- elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then
- tx_loaded_ctr <= tx_loaded_ctr + x"1";
- end if;
- end if;
-end process TX_LOADED_CTR_PROC;
-
-PS_RESPONSE_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (too_much_data = '0') then
- if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then
- PS_RESPONSE_READY_OUT <= '1';
- else
- PS_RESPONSE_READY_OUT <= '0';
- end if;
- end if;
-
- if (dissect_current_state = IDLE or dissect_current_state = WAIT_FOR_RESPONSE) then
- PS_BUSY_OUT <= '0';
- else
- PS_BUSY_OUT <= '1';
- end if;
- end if;
-end process PS_RESPONSE_SYNC;
-
-TC_FRAME_TYPE_OUT <= x"0008";
-TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;
-TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN;
-TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8);
-TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0);
-TC_SRC_MAC_OUT <= g_MY_MAC;
-TC_SRC_IP_OUT <= g_MY_IP;
-TC_SRC_UDP_OUT <= x"9065"; --x"a861";
-TC_IP_PROTOCOL_OUT <= x"11";
-TC_IDENT_OUT <= x"3" & reply_ctr(11 downto 0);
-
-TC_FRAME_SIZE_OUT <= tx_data_ctr;
-
-DISSECT_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- dissect_current_state <= IDLE;
- elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- if (g_SIMULATE = 0) then
--- dissect_current_state <= IDLE;
--- else
--- dissect_current_state <= WAIT_FOR_RESPONSE;
--- end if;
--- else
- dissect_current_state <= dissect_next_state;
--- end if;
- end if;
-end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_data_ctr, rx_fifo_q, GSC_BUSY_IN)
-begin
- case dissect_current_state is
-
- when IDLE =>
- state <= x"0";
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- dissect_next_state <= READ_FRAME;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when READ_FRAME =>
- state <= x"1";
- if (PS_DATA_IN(8) = '1') then
- dissect_next_state <= WAIT_FOR_HUB;
- else
- dissect_next_state <= READ_FRAME;
- end if;
-
- when WAIT_FOR_HUB =>
- state <= x"2";
- if (GSC_INIT_READ_IN = '1') then
- dissect_next_state <= LOAD_TO_HUB;
- else
- dissect_next_state <= WAIT_FOR_HUB;
- end if;
-
- when LOAD_TO_HUB =>
- state <= x"3";
- if (rx_fifo_q(17) = '1') then
- if (reset_detected = '1') then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= WAIT_FOR_RESPONSE;
- end if;
- else
- dissect_next_state <= LOAD_TO_HUB;
- end if;
-
- when WAIT_FOR_RESPONSE =>
- state <= x"4";
- if (GSC_REPLY_DATAREADY_IN = '1') then
- dissect_next_state <= SAVE_RESPONSE;
- else
- dissect_next_state <= WAIT_FOR_RESPONSE;
- end if;
-
- when SAVE_RESPONSE =>
- state <= x"5";
- if (GSC_REPLY_DATAREADY_IN = '0' and GSC_BUSY_IN = '0') then
- if (too_much_data = '0') then
- dissect_next_state <= WAIT_FOR_LOAD;
- else
- dissect_next_state <= CLEANUP;
- end if;
- else
- dissect_next_state <= SAVE_RESPONSE;
- end if;
-
- when WAIT_FOR_LOAD =>
- state <= x"6";
- if (PS_SELECTED_IN = '1') then
- dissect_next_state <= LOAD_FRAME;
- else
- dissect_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD_FRAME =>
- state <= x"7";
- if (tx_loaded_ctr = tx_data_ctr) then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= LOAD_FRAME;
- end if;
-
- when CLEANUP =>
- state <= x"8";
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
--- reset request packet detection
- RESET_DETECTED_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (dissect_current_state = IDLE) then
- reset_detected <= '0';
- elsif (PS_DATA_IN(7 downto 0) = x"80" and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr = "0100") then
- reset_detected <= '1';
- else
- reset_detected <= reset_detected;
- end if;
- end if;
- end process RESET_DETECTED_PROC;
-
- MAKE_RESET_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (dissect_current_state = IDLE) then
- make_reset <= '0';
- elsif (dissect_current_state = CLEANUP and reset_detected = '1') then
- make_reset <= '1';
- else
- make_reset <= make_reset;
- end if;
- end if;
- end process MAKE_RESET_PROC;
-
-
--- monitoring
-
-hist_ctrs_gen : for i in 0 to 31 generate
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- reset_all_hist(i) <= '1';
- elsif (hist_inst(i) = x"ffff_ffff") then
- reset_all_hist(i) <= '1';
- else
- reset_all_hist(i) <= '0';
- end if;
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if (reset_all_hist /= x"0000_0000") then
- hist_inst(i) <= (others => '0');
- elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr and i = to_integer(unsigned(tx_data_ctr(15 downto 11)))) then
- hist_inst(i) <= hist_inst(i) + x"1";
- else
- hist_inst(i) <= hist_inst(i);
- end if;
- end if;
- end process;
-
-end generate hist_ctrs_gen;
-
-DATA_HIST_OUT <= hist_inst;
-
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- DEBUG_OUT(0) <= rx_full;
- DEBUG_OUT(1) <= rx_empty;
- DEBUG_OUT(2) <= tx_full;
- DEBUG_OUT(3) <= tx_empty;
- DEBUG_OUT(7 downto 4) <= state;
- end if;
-end process;
-
-DEBUG_OUT(63 downto 8) <= (others => '0');
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- mon_rec_frames <= (others => '0');
- elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then
- mon_rec_frames <= mon_rec_frames + x"1";
- else
- mon_rec_frames <= mon_rec_frames;
- end if;
- end if;
-end process;
-MONITOR_SELECT_REC_OUT <= mon_rec_frames;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- mon_rec_bytes <= (others => '0');
- elsif (rx_fifo_wr = '1') then
- mon_rec_bytes <= mon_rec_bytes + x"1";
- else
- mon_rec_bytes <= mon_rec_bytes;
- end if;
- end if;
-end process;
-MONITOR_SELECT_REC_BYTES_OUT <= mon_rec_bytes;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- mon_sent_frames <= (others => '0');
- elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then
- mon_sent_frames <= mon_sent_frames + x"1";
- else
- mon_sent_frames <= mon_sent_frames;
- end if;
- end if;
-end process;
-MONITOR_SELECT_SENT_OUT <= mon_sent_frames;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- mon_sent_bytes <= (others => '0');
- elsif (tx_fifo_rd = '1') then
- mon_sent_bytes <= mon_sent_bytes + x"1";
- else
- mon_sent_bytes <= mon_sent_bytes;
- end if;
- end if;
-end process;
-MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes;
-
--- statistics
---REC_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rec_frames <= (others => '0');
--- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
--- rec_frames <= rec_frames + x"1";
--- end if;
--- end if;
---end process REC_FRAMES_PROC;
---
--- needed for identification
-REPLY_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- reply_ctr <= (others => '0');
- elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then
- reply_ctr <= reply_ctr + x"1";
- end if;
- end if;
-end process REPLY_CTR_PROC;
---
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state, tx_loaded_ctr, tx_data_ctr)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if ((dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr)) then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_REPLY;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when LOAD_REPLY =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_REPLY;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0502" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_REPLY =>
--- stat_data_temp <= x"0503" & reply_ctr;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
-----STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
---
----- end of statistics
-
-
-end architecture RTL;
+++ /dev/null
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:10:12 11/18/2011
--- Design Name:
--- Module Name: trb_net16_gbe_response_constructor_Stat - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-entity trb_net16_gbe_response_constructor_Stat is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
-
- TC_BUSY_IN : in std_logic;
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
- STAT_DATA_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0);
- STAT_ADDR_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0);
- STAT_DATA_RDY_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
- STAT_DATA_ACK_OUT : out std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_response_constructor_Stat;
-
-architecture Behavioral of trb_net16_gbe_response_constructor_Stat is
-
-attribute syn_encoding : string;
-
-type construct_states is (IDLE, WAIT_FOR_LOAD, LOAD_DATA, TERMINATION, CLEANUP);
-signal construct_current_state, construct_next_state : construct_states;
-attribute syn_encoding of construct_current_state: signal is "safe,gray";
-
-signal timer : unsigned(28 downto 0);
-signal state : std_logic_vector(3 downto 0);
-signal load_ctr : integer range 0 to 255;
-signal tc_data : std_logic_vector(8 downto 0);
-signal tc_data_t : std_logic_vector(7 downto 0);
-signal timer_lock : std_logic;
-
-signal mem_din : std_logic_vector(31 downto 0);
-signal mem_dout, mem_wr_addr : std_logic_vector(7 downto 0);
-signal mem_rd_addr : std_logic_vector(9 downto 0);
-signal mem_wr_en : std_logic;
-signal selected : std_logic_vector(c_MAX_PROTOCOLS downto 0);
-
-signal pause : integer range 0 to 28;
-
-signal stat_data_temp : std_logic_vector(31 downto 0);
-
-begin
-pause <= 10 when g_SIMULATE = 1 else 28;
-
-
-mem : statts_mem
- PORT map(
- WrClock => CLK,
- Reset => RESET,
- WrClockEn => '1',
- WE => mem_wr_en,
- WrAddress => mem_wr_addr,
- Data => mem_din,
- RdClock => CLK,
- RdAddress => mem_rd_addr,
- Q => mem_dout,
- RdClockEn => '1'
- );
-
-mem_wr_en <= or_all(selected);
-STAT_DATA_ACK_OUT <= selected;
-
-SELECTOR_PROC : process(CLK)
- variable found : boolean := false;
-begin
- if rising_edge(CLK) then
-
- selected <= (others => '0');
-
- if (RESET = '1') then
- mem_wr_addr <= (others => '0');
- mem_din <= (others => '0');
- found := false;
- else
- if (or_all(STAT_DATA_RDY_IN) = '1') then
- for i in 0 to c_MAX_PROTOCOLS loop
- if (STAT_DATA_RDY_IN(i) = '1') then
- mem_wr_addr <= STAT_ADDR_IN((i + 1) * 8 - 1 downto i * 8);
- mem_din <= STAT_DATA_IN((i + 1) * 32 - 1 downto i * 32);
- selected(i) <= '1';
- found := true;
- elsif (i = c_MAX_PROTOCOLS) and (STAT_DATA_RDY_IN(i) = '0') and (found = false) then
- found := false;
- end if;
- end loop;
- else
- mem_wr_addr <= (others => '0');
- mem_din <= (others => '0');
- found := false;
- end if;
- end if;
-
- end if;
-end process SELECTOR_PROC;
-
-
-
-
-
-TIMER_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- timer <= (others => '0');
- timer_lock <= '0';
- elsif (timer(pause) = '0') then
- timer_lock <= '0';
- timer <= timer + 1;
- elsif (timer(pause) = '1') then
- timer_lock <= '1';
- timer <= timer + 1;
- else
- timer <= timer + 1;
- end if;
- end if;
-end process TIMER_PROC;
-
--- **** MESSAGES CONSTRUCTING PART
-
-CONSTRUCT_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- construct_current_state <= IDLE;
- else
- if (g_SIMULATE = 1) then
- construct_current_state <= IDLE;
- else
- construct_current_state <= construct_next_state;
- end if;
- end if;
- end if;
-end process CONSTRUCT_MACHINE_PROC;
-
-CONSTRUCT_MACHINE : process(construct_current_state, timer_lock, TC_BUSY_IN, PS_SELECTED_IN, timer, load_ctr)
-begin
- case construct_current_state is
-
- when IDLE =>
- state <= x"1";
- if (timer(pause) = '1' and timer_lock = '0') then
- construct_next_state <= WAIT_FOR_LOAD;
- else
- construct_next_state <= IDLE;
- end if;
-
- when WAIT_FOR_LOAD =>
- state <= x"4";
- if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
- construct_next_state <= LOAD_DATA;
- else
- construct_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD_DATA =>
- state <= x"2";
- if (load_ctr = 255) then
- construct_next_state <= TERMINATION;
- else
- construct_next_state <= LOAD_DATA;
- end if;
-
- when TERMINATION =>
- state <= x"e";
- construct_next_state <= CLEANUP;
-
- when CLEANUP =>
- state <= x"9";
- construct_next_state <= IDLE;
-
- end case;
-end process CONSTRUCT_MACHINE;
-
-LOAD_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (construct_current_state = IDLE) then
- load_ctr <= 1;
- elsif (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') then
- load_ctr <= load_ctr + 1;
- end if;
- end if;
-end process LOAD_CTR_PROC;
-
-mem_rd_addr <= std_logic_vector(to_unsigned(load_ctr, 10));
-
-TC_DATA_PROC : process(construct_current_state, tc_data_t)
-begin
-
- tc_data(8) <= '0';
-
- case (construct_current_state) is
-
- when LOAD_DATA =>
- for i in 0 to 7 loop
- tc_data(i) <= mem_dout(i);
- end loop;
-
- when TERMINATION =>
- tc_data(7 downto 0) <= x"ff";
- tc_data(8) <= '1';
-
- when others => tc_data(7 downto 0) <= x"00";
-
- end case;
-
-end process;
-
-TC_DATA_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- TC_DATA_OUT <= tc_data;
- end if;
-end process TC_DATA_SYNC;
-
-
---PS_BUSY_OUT <= '0' when (construct_current_state = IDLE) else '1';
---PS_RESPONSE_READY_OUT <= '0' when (construct_current_state = IDLE) else '1';
-
-PS_RESPONSE_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (construct_current_state = IDLE) then
- PS_RESPONSE_READY_OUT <= '0';
- else
- PS_RESPONSE_READY_OUT <= '1';
- end if;
-
- if (construct_current_state = IDLE) then
- PS_BUSY_OUT <= '0';
- else
- PS_BUSY_OUT <= '1';
- end if;
- end if;
-end process PS_RESPONSE_SYNC;
-
-TC_FRAME_SIZE_OUT <= x"0100";
-TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip
-
-TC_DEST_MAC_OUT <= x"ffffffffffff";
-TC_DEST_IP_OUT <= x"ff" & g_MY_IP(23 downto 0); --x"ff00a8c0";
-TC_DEST_UDP_OUT <= x"51c3";
-TC_SRC_MAC_OUT <= g_MY_MAC;
-TC_SRC_IP_OUT <= g_MY_IP;
-TC_SRC_UDP_OUT <= x"51c3";
-TC_IP_PROTOCOL_OUT <= x"11"; -- udp
-
-TC_IP_SIZE_OUT <= x"0100";
-TC_UDP_SIZE_OUT <= x"0100";
-TC_FLAGS_OFFSET_OUT <= (others => '0');
-
--- **** debug
-DEBUG_OUT(3 downto 0) <= state;
-DEBUG_OUT(4) <= '0';
-DEBUG_OUT(7 downto 5) <= "000";
-DEBUG_OUT(8) <= '0';
-DEBUG_OUT(11 downto 9) <= "000";
-DEBUG_OUT(31 downto 12) <= (others => '0');
--- ****
-
-end Behavioral;
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-
---********
--- Response Constructor which forwards received frame back ceating a loopback
---
-
-entity trb_net16_gbe_response_constructor_Test is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- TC_BUSY_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_response_constructor_Test;
-
-
-architecture trb_net16_gbe_response_constructor_Test of trb_net16_gbe_response_constructor_Test is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_response_constructor_Test: architecture is "GBE_MAIN_group";
-
-attribute syn_encoding : string;
-
-type dissect_states is (IDLE, SAVE, WAIT_FOR_LOAD, LOAD, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "safe,gray";
-
-signal ff_wr_en : std_logic;
-signal ff_rd_en : std_logic;
-signal resp_bytes_ctr : std_logic_vector(15 downto 0);
-signal ff_empty : std_logic;
-signal ff_full : std_logic;
-signal ff_q : std_logic_vector(8 downto 0);
-signal ff_rd_lock : std_logic;
-
-signal state : std_logic_vector(3 downto 0);
-signal rec_frames : std_logic_vector(15 downto 0);
-signal sent_frames : std_logic_vector(15 downto 0);
-
-begin
-
-DISSECT_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- dissect_current_state <= IDLE;
- else
- dissect_current_state <= dissect_next_state;
- end if;
- end if;
-end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, ff_q, ff_rd_lock, TC_BUSY_IN)
-begin
- case dissect_current_state is
-
- when IDLE =>
- state <= x"1";
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- dissect_next_state <= SAVE;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when SAVE =>
- state <= x"2";
- if (PS_DATA_IN(8) = '1') then
- dissect_next_state <= WAIT_FOR_LOAD;
- else
- dissect_next_state <= SAVE;
- end if;
-
- when WAIT_FOR_LOAD =>
- state <= x"3";
- if (TC_BUSY_IN = '0') then
- dissect_next_state <= LOAD;
- else
- dissect_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD =>
- state <= x"4";
- if (ff_q(8) = '1') and (ff_rd_lock = '0') then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= LOAD;
- end if;
-
- when CLEANUP =>
- state <= x"5";
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
-PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1';
-
-ff_wr_en <= '1' when (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') else '0';
-
-FF_RD_LOCK_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- ff_rd_lock <= '1';
- elsif (dissect_current_state = LOAD and ff_rd_en = '1') then
- ff_rd_lock <= '0';
- else
- ff_rd_lock <= '1';
- end if;
- end if;
-end process FF_RD_LOCK_PROC;
-
--- TODO: put a smaller fifo here
-FRAME_FIFO: fifo_4096x9
-port map(
- Data => PS_DATA_IN,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => ff_wr_en,
- RdEn => ff_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q => ff_q,
- Empty => ff_empty,
- Full => ff_full
-);
-
-ff_rd_en <= '1' when (TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') else '0';
-
-TC_DATA_OUT <= ff_q;
-
-PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) else '0';
-
-TC_FRAME_SIZE_OUT <= resp_bytes_ctr + x"1";
-
-TC_FRAME_TYPE_OUT <= x"aa08";
-TC_DEST_MAC_OUT <= x"9a680f201300";
-TC_DEST_IP_OUT <= x"0100a8c0";
-TC_DEST_UDP_OUT <= x"51c3";
-TC_SRC_MAC_OUT <= x"efbeefbe0000";
-TC_SRC_IP_OUT <= x"0b00a8c0";
-TC_SRC_UDP_OUT <= x"51c3";
-TC_IP_PROTOCOL_OUT <= x"11";
-
-RESP_BYTES_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (dissect_current_state = IDLE) then
- resp_bytes_ctr <= (others => '0');
- elsif (dissect_current_state = SAVE) then
- resp_bytes_ctr <= resp_bytes_ctr + x"1";
- end if;
- end if;
-end process RESP_BYTES_CTR_PROC;
-
-REC_FRAMES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- rec_frames <= (others => '0');
- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- rec_frames <= rec_frames + x"1";
- end if;
- end if;
-end process REC_FRAMES_PROC;
-
-SENT_FRAMES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- sent_frames <= (others => '0');
- elsif (dissect_current_state = WAIT_FOR_LOAD and TC_BUSY_IN = '0') then
- sent_frames <= sent_frames + x"1";
- end if;
- end if;
-end process SENT_FRAMES_PROC;
-
-RECEIVED_FRAMES_OUT <= rec_frames;
-SENT_FRAMES_OUT <= sent_frames;
-
--- **** debug
-DEBUG_OUT(3 downto 0) <= state;
-DEBUG_OUT(4) <= ff_empty;
-DEBUG_OUT(7 downto 5) <= "000";
-DEBUG_OUT(8) <= ff_full;
-DEBUG_OUT(11 downto 9) <= "000";
-DEBUG_OUT(31 downto 12) <= (others => '0');
--- ****
-
-end trb_net16_gbe_response_constructor_Test;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-
---********
--- Response Constructor which recevies data and does nothing except counting incoming packets
---
-
-entity trb_net16_gbe_response_constructor_Test1 is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- TC_BUSY_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_response_constructor_Test1;
-
-
-architecture trb_net16_gbe_response_constructor_Test1 of trb_net16_gbe_response_constructor_Test1 is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_response_constructor_Forward : architecture is "GBE_MAIN_group";
-
-attribute syn_encoding : string;
-
-type dissect_states is (IDLE, SAVE, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "safe,gray";
-
-signal ff_wr_en : std_logic;
-signal ff_rd_en : std_logic;
-signal resp_bytes_ctr : std_logic_vector(15 downto 0);
-signal ff_empty : std_logic;
-signal ff_full : std_logic;
-signal ff_q : std_logic_vector(8 downto 0);
-signal ff_rd_lock : std_logic;
-
-signal state : std_logic_vector(3 downto 0);
-signal rec_frames : std_logic_vector(15 downto 0);
-signal sent_frames : std_logic_vector(15 downto 0);
-
-begin
-
-DISSECT_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- dissect_current_state <= IDLE;
- else
- dissect_current_state <= dissect_next_state;
- end if;
- end if;
-end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN)
-begin
- case dissect_current_state is
-
- when IDLE =>
- state <= x"1";
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- dissect_next_state <= SAVE;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when SAVE =>
- state <= x"2";
- if (PS_DATA_IN(8) = '1') then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= SAVE;
- end if;
-
- when CLEANUP =>
- state <= x"5";
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
-PS_BUSY_OUT <= '0';
-
-TC_DATA_OUT <= (others => '0');
-
-PS_RESPONSE_READY_OUT <= '0';
-
-TC_FRAME_SIZE_OUT <= (others => '0');
-
-TC_FRAME_TYPE_OUT <= x"0008";
-TC_DEST_MAC_OUT <= x"9a680f201300";
-TC_DEST_IP_OUT <= x"0100a8c0";
-TC_DEST_UDP_OUT <= x"50c3";
-TC_SRC_MAC_OUT <= x"efbeefbe0000";
-TC_SRC_IP_OUT <= x"0b00a8c0";
-TC_SRC_UDP_OUT <= x"50c3";
-TC_IP_PROTOCOL_OUT <= x"11";
-
-REC_FRAMES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- rec_frames <= (others => '0');
- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- rec_frames <= rec_frames + x"1";
- end if;
- end if;
-end process REC_FRAMES_PROC;
-
-RECEIVED_FRAMES_OUT <= rec_frames;
-SENT_FRAMES_OUT <= (others => '0');
-
--- **** debug
-DEBUG_OUT(31 downto 0) <= (others => '0');
--- ****
-
-end trb_net16_gbe_response_constructor_Test1;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-
---********
--- gets all the data which is not supposed to be received by other protocols
--- simply clears the fifo from garbage
-
-entity trb_net16_gbe_response_constructor_Trash is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_SIZE_LEFT_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- TC_BUSY_IN : in std_logic;
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_response_constructor_Trash;
-
-
-architecture trb_net16_gbe_response_constructor_Trash of trb_net16_gbe_response_constructor_Trash is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_response_constructor_Trash : architecture is "GBE_MAIN_group";
-
-attribute syn_encoding : string;
-
-type dissect_states is (IDLE, SAVE, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "safe,gray";
-
-signal state : std_logic_vector(3 downto 0);
-signal rec_frames : std_logic_vector(15 downto 0);
-signal sent_frames : std_logic_vector(15 downto 0);
-
-begin
-
-DISSECT_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- dissect_current_state <= IDLE;
- else
- dissect_current_state <= dissect_next_state;
- end if;
- end if;
-end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN)
-begin
- case dissect_current_state is
-
- when IDLE =>
- state <= x"1";
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- dissect_next_state <= SAVE;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when SAVE =>
- state <= x"2";
- if (PS_DATA_IN(8) = '1') then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= SAVE;
- end if;
-
- when CLEANUP =>
- state <= x"5";
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
-PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1';
-
-TC_DATA_OUT <= '0' & x"ab";
-
-PS_RESPONSE_READY_OUT <= '0';
-
-TC_FRAME_SIZE_OUT <= (others => '0');
-
-TC_FRAME_TYPE_OUT <= (others => '0');
-TC_DEST_MAC_OUT <= (others => '0');
-TC_DEST_IP_OUT <= (others => '0');
-TC_DEST_UDP_OUT <= (others => '0');
-TC_SRC_MAC_OUT <= (others => '0');
-TC_SRC_IP_OUT <= (others => '0');
-TC_SRC_UDP_OUT <= (others => '0');
-TC_IP_PROTOCOL_OUT <= (others => '0');
-
-REC_FRAMES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- rec_frames <= (others => '0');
- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- rec_frames <= rec_frames + x"1";
- end if;
- end if;
-end process REC_FRAMES_PROC;
-
-RECEIVED_FRAMES_OUT <= rec_frames;
-SENT_FRAMES_OUT <= (others => '0');
-
--- **** debug
-DEBUG_OUT(3 downto 0) <= state;
-DEBUG_OUT(31 downto 4) <= (others => '0');
--- ****
-
-end trb_net16_gbe_response_constructor_Trash;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-entity trb_net16_gbe_response_constructor_TrbNetData is
-generic (
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- DO_SIMULATION : integer range 0 to 1 := 0
- );
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- DEBUG_OUT : out std_logic_vector(63 downto 0);
--- END OF INTERFACE
-
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
- CFG_READOUT_CTR_VALID_IN : in std_logic;
- CFG_INSERT_TTYPE_IN : in std_logic;
- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
-
- MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(31 downto 0);
-
- DATA_HIST_OUT : out hist_array
-);
-end trb_net16_gbe_response_constructor_TrbNetData;
-
-
-architecture trb_net16_gbe_response_constructor_TrbNetData of trb_net16_gbe_response_constructor_TrbNetData is
-
-attribute syn_encoding : string;
-
-signal ip_cfg_start : std_logic;
-signal ip_cfg_bank : std_logic_vector(3 downto 0);
-signal ip_cfg_done : std_logic;
-signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);
-signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
-signal ip_cfg_mem_clk : std_logic;
-
-signal ic_dest_mac, ic_dest_mac_shift : std_logic_vector(47 downto 0);
-signal ic_dest_ip, ic_dest_ip_shift : std_logic_vector(31 downto 0);
-signal ic_dest_udp, ic_dest_udp_shift : std_logic_vector(15 downto 0);
-signal ic_src_mac, ic_src_mac_shift : std_logic_vector(47 downto 0);
-signal ic_src_ip, ic_src_ip_shift : std_logic_vector(31 downto 0);
-signal ic_src_udp, ic_src_udp_shift : std_logic_vector(15 downto 0);
-
-signal pc_wr_en : std_logic;
-signal pc_data : std_logic_vector(7 downto 0);
-signal pc_eoq : std_logic;
-signal pc_sos : std_logic;
-signal pc_ready : std_logic;
-signal pc_sub_size : std_logic_vector(31 downto 0);
-signal pc_trig_nr : std_logic_vector(31 downto 0);
-signal pc_eos : std_logic;
-
-signal tc_rd_en : std_logic;
-signal tc_data : std_logic_vector(8 downto 0);
-signal tc_size : std_logic_vector(15 downto 0);
-signal tc_sod : std_logic;
-signal pc_trig_type, pc_trig_type_shift : std_logic_vector(3 downto 0);
-
-type dissect_states is (IDLE, WAIT_FOR_LOAD, LOAD, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state : signal is "onehot";
-
-signal event_bytes : std_logic_vector(15 downto 0);
-signal loaded_bytes : std_logic_vector(15 downto 0);
-signal sent_packets : std_logic_vector(15 downto 0);
-
-signal mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0);
-signal ipu_dbg : std_logic_vector(383 downto 0);
-signal constr_dbg : std_logic_vector(63 downto 0);
-
-signal hist_inst : hist_array;
-signal tc_sod_flag : std_logic;
-signal reset_all_hist : std_logic_vector(31 downto 0);
-signal ipu_monitor : std_logic_vector(223 downto 0);
-
--- JUST FOR DEBUGING PURPOSE
-type sim_check_states is (IDLE, SAVE_HDR, GO_OVER_DATA, SAVE_TLR, GET_ONE_MORE, GET_SECOND_MORE, CLEANUP);
-signal sim_check_current, sim_check_next : sim_check_states;
-
-signal hdr, tlr : std_logic_vector(255 downto 0);
-
-
-
-begin
-
-
-sim_check_gen : if DO_SIMULATION = 1 generate
-
- process(RESET, CLK)
- begin
- if RESET = '1' then
- sim_check_current <= IDLE;
- elsif rising_edge(CLK) then
- sim_check_current <= sim_check_next;
- end if;
- end process;
-
- process(sim_check_current, tc_sod, loaded_bytes, tc_size, hdr, tlr, event_bytes)
- begin
- case (sim_check_current) is
-
- when IDLE =>
- if (tc_sod = '1') then
- sim_check_next <= SAVE_HDR;
- else
- sim_check_next <= IDLE;
- end if;
-
- when SAVE_HDR =>
- if (loaded_bytes = x"001f" + x"0002") then
- sim_check_next <= GO_OVER_DATA;
- else
- sim_check_next <= SAVE_HDR;
- end if;
-
- when GO_OVER_DATA =>
- if (loaded_bytes = tc_size + x"0001") then
- sim_check_next <= SAVE_TLR;
- else
- sim_check_next <= GO_OVER_DATA;
- end if;
-
- when SAVE_TLR =>
- if (loaded_bytes = event_bytes) then
- sim_check_next <= GET_ONE_MORE;
- else
- sim_check_next <= SAVE_TLR;
- end if;
-
- when GET_ONE_MORE =>
- sim_check_next <= GET_SECOND_MORE;
-
- when GET_SECOND_MORE =>
- sim_check_next <= CLEANUP;
-
- when CLEANUP =>
-
- --assert (hdr = tlr) report "--------- >>>> Header Trailer mismatch" severity failure;
-
- sim_check_next <= IDLE;
-
- end case;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if (sim_check_current = SAVE_HDR and loaded_bytes > x"0001") then
- hdr((to_integer(unsigned(loaded_bytes - x"0002") * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - x"0002")) * 8)) <= tc_data(7 downto 0);
- else
- hdr <= hdr;
- end if;
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if (sim_check_current = SAVE_TLR) then
- tlr((to_integer(unsigned(loaded_bytes - tc_size - 2) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 2)) * 8)) <= tc_data(7 downto 0);
- elsif (sim_check_current = GET_ONE_MORE) then
- tlr((to_integer(unsigned(loaded_bytes - tc_size - 1) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 1)) * 8)) <= tc_data(7 downto 0);
- elsif (sim_check_current = GET_ONE_MORE) then
- tlr((to_integer(unsigned(loaded_bytes - tc_size) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size)) * 8)) <= tc_data(7 downto 0);
- else
- tlr <= tlr;
- end if;
- end if;
- end process;
-
-
-end generate sim_check_gen;
-
-
-
-
-THE_IP_CONFIGURATOR: ip_configurator
-port map(
- CLK => CLK,
- RESET => RESET,
- -- configuration interface
- START_CONFIG_IN => ip_cfg_start,
- BANK_SELECT_IN => ip_cfg_bank,
- CONFIG_DONE_OUT => ip_cfg_done,
- MEM_ADDR_OUT => ip_cfg_mem_addr,
- MEM_DATA_IN => ip_cfg_mem_data,
- MEM_CLK_OUT => ip_cfg_mem_clk,
- -- information for IP cores
- DEST_MAC_OUT => ic_dest_mac,
- DEST_IP_OUT => ic_dest_ip,
- DEST_UDP_OUT => ic_dest_udp,
- SRC_MAC_OUT => ic_src_mac,
- SRC_IP_OUT => ic_src_ip,
- SRC_UDP_OUT => ic_src_udp,
- MTU_OUT => open,
- -- Debug
- DEBUG_OUT => open
-);
-
-MB_IP_CONFIG: slv_mac_memory
-port map(
- CLK => CLK,
- RESET => RESET,
- BUSY_IN => '0',
- -- Slave bus
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
- -- I/O to the backend
- MEM_CLK_IN => ip_cfg_mem_clk,
- MEM_ADDR_IN => ip_cfg_mem_addr,
- MEM_DATA_OUT => ip_cfg_mem_data,
- -- Status lines
- STAT => open
-);
-
-THE_IPU_INTERFACE: trb_net16_gbe_ipu_interface --ipu2gbe
-port map(
- CLK_IPU => CLK,
- CLK_GBE => CLK,
- RESET => RESET,
- --Event information coming from CTS
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data from Frontends
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- slow control interface
- START_CONFIG_OUT => ip_cfg_start,
- BANK_SELECT_OUT => ip_cfg_bank,
- CONFIG_DONE_IN => ip_cfg_done,
- DATA_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
- DATA_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
- MULT_EVT_ENABLE_IN => CFG_MULT_ENABLE_IN,
- MAX_SUBEVENT_SIZE_IN => CFG_MAX_SUB_IN,
- MAX_QUEUE_SIZE_IN => CFG_MAX_QUEUE_IN,
- MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
- MAX_SINGLE_SUB_SIZE_IN => CFG_MAX_SINGLE_SUB_IN,
- READOUT_CTR_IN => CFG_READOUT_CTR_IN,
- READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
- -- PacketConstructor interface
- PC_WR_EN_OUT => pc_wr_en,
- PC_DATA_OUT => pc_data,
- PC_READY_IN => pc_ready,
- PC_SOS_OUT => pc_sos,
- PC_EOS_OUT => pc_eos,
- PC_EOQ_OUT => pc_eoq,
- PC_SUB_SIZE_OUT => pc_sub_size,
- PC_TRIG_NR_OUT => pc_trig_nr,
- PC_TRIGGER_TYPE_OUT => pc_trig_type,
- MONITOR_OUT => ipu_monitor,
- DEBUG_OUT => ipu_dbg
-);
-
-MONITOR_SELECT_DROP_OUT_OUT <= ipu_monitor(31 downto 0);
-
-PACKET_CONSTRUCTOR : trb_net16_gbe_event_constr
-port map(
- CLK => CLK,
- RESET => RESET,
- PC_WR_EN_IN => pc_wr_en,
- PC_DATA_IN => pc_data,
- PC_READY_OUT => pc_ready,
- PC_START_OF_SUB_IN => pc_sos,
- PC_END_OF_SUB_IN => pc_eos,
- PC_END_OF_QUEUE_IN => pc_eoq,
- PC_SUB_SIZE_IN => pc_sub_size,
- PC_DECODING_IN => CFG_SUBEVENT_DEC_IN,
- PC_EVENT_ID_IN => CFG_SUBEVENT_ID_IN,
- PC_TRIG_NR_IN => pc_trig_nr,
- PC_TRIGGER_TYPE_IN => pc_trig_type_shift,
- PC_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
- PC_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
- TC_RD_EN_IN => tc_rd_en,
- TC_DATA_OUT => tc_data,
- TC_EVENT_SIZE_OUT => tc_size,
- TC_SOD_OUT => tc_sod,
- DEBUG_OUT => constr_dbg
-);
-
-tc_rd_en <= '1' when PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' else '0';
-
-DISSECT_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- dissect_current_state <= IDLE;
- elsif rising_edge(CLK) then
- dissect_current_state <= dissect_next_state;
- end if;
-end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, tc_sod, event_bytes, loaded_bytes, PS_SELECTED_IN)
-begin
- case dissect_current_state is
-
- when IDLE =>
- if (tc_sod = '1') then
- dissect_next_state <= WAIT_FOR_LOAD;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when WAIT_FOR_LOAD =>
- if (PS_SELECTED_IN = '1') then
- dissect_next_state <= LOAD;
- else
- dissect_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD =>
- if (event_bytes = loaded_bytes) then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= LOAD;
- end if;
-
- when CLEANUP =>
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
-PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1';
-PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) or (dissect_current_state = WAIT_FOR_LOAD) else '0';
-
-TC_DATA_OUT <= tc_data;
-
-EVENT_BYTES_PROC : process (clk) is
-begin
- if rising_edge(clk) then
- if dissect_current_state = IDLE and tc_sod = '1' then
- event_bytes <= tc_size + x"20"; -- adding termination bytes
- else
- event_bytes <= event_bytes;
- end if;
- end if;
-end process EVENT_BYTES_PROC;
-
-LOADED_BYTES_PROC : process (clk) is
-begin
- if rising_edge(clk) then
- if (dissect_current_state = IDLE) then
- loaded_bytes <= (others => '0');
- elsif (dissect_current_state = LOAD and TC_RD_EN_IN = '1') then
- loaded_bytes <= loaded_bytes + x"1";
- else
- loaded_bytes <= loaded_bytes;
- end if;
- end if;
-end process LOADED_BYTES_PROC;
-
-TC_FRAME_SIZE_OUT <= event_bytes;
-TC_FRAME_TYPE_OUT <= x"0008";
-
-TC_DEST_MAC_OUT <= ic_dest_mac_shift; --x"c4e870211b00"; --ic_dest_mac;
-TC_DEST_IP_OUT <= ic_dest_ip_shift; --x"0300a8c0"; --ic_dest_ip;
-TC_DEST_UDP_OUT <= ic_dest_udp_shift; --x"c35c"; --ic_dest_udp;
-
---TC_DEST_MAC_OUT <= x"87883c290c00"; --ic_dest_mac;
---TC_DEST_IP_OUT <= x"0188a8c0"; --ic_dest_ip;
---TC_DEST_UDP_OUT <= x"c35b"; --ic_dest_udp;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (ip_cfg_start = '1') then
- ic_dest_mac_shift <= ic_dest_mac;
- ic_dest_ip_shift <= ic_dest_ip;
- ic_dest_udp_shift <= ic_dest_udp;
- pc_trig_type_shift <= pc_trig_type;
- else
- ic_dest_mac_shift <= ic_dest_mac_shift;
- ic_dest_ip_shift <= ic_dest_ip_shift;
- ic_dest_udp_shift <= ic_dest_udp_shift;
- pc_trig_type_shift <= pc_trig_type_shift;
- end if;
- end if;
-end process;
-
-
-
-rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
- TC_SRC_MAC_OUT <= g_MY_MAC;
- TC_SRC_IP_OUT <= g_MY_IP;
-end generate rx_enable_gen;
-
-rx_disable_gen : if (RX_PATH_ENABLE = 0) generate
- TC_SRC_MAC_OUT <= g_MY_MAC;
- TC_SRC_IP_OUT <= ic_src_ip;
-end generate rx_disable_gen;
-
---TC_SRC_MAC_OUT <= x"99883c290c00";
---TC_SRC_IP_OUT <= x"0288a8c0";
-
-TC_SRC_UDP_OUT <= ic_src_udp;
-TC_IP_PROTOCOL_OUT <= x"11";
-TC_IDENT_OUT <= x"4" & sent_packets(11 downto 0);
-
-SENT_PACKETS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- sent_packets <= (others => '0');
- elsif (dissect_current_state = IDLE and tc_sod = '1') then
- sent_packets <= sent_packets + x"1";
- end if;
- end if;
-end process SENT_PACKETS_PROC;
-
--- monitoring
-
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (tc_sod = '1' and tc_sod_flag = '0') then
- tc_sod_flag <= '1';
- elsif (tc_sod = '0') then
- tc_sod_flag <= '0';
- else
- tc_sod_flag <= tc_sod_flag;
- end if;
- end if;
-end process;
-
-hist_ctrs_gen : for i in 0 to 31 generate
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- reset_all_hist(i) <= '1';
- elsif (hist_inst(i) = x"ffff_ffff") then
- reset_all_hist(i) <= '1';
- else
- reset_all_hist(i) <= '0';
- end if;
- end if;
- end process;
-
- HIST_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1') or (reset_all_hist /= x"0000_0000") then
- hist_inst(i) <= (others => '0');
- elsif (tc_sod = '1' and tc_sod_flag = '0' and i = to_integer(unsigned(event_bytes(15 downto 11)))) then
- hist_inst(i) <= hist_inst(i) + x"1";
- else
- hist_inst(i) <= hist_inst(i);
- end if;
- end if;
- end process;
-end generate hist_ctrs_gen;
-
-DATA_HIST_OUT <= hist_inst;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- mon_sent_frames <= (others => '0');
- elsif (dissect_current_state = LOAD and event_bytes = loaded_bytes) then
- mon_sent_frames <= mon_sent_frames + x"1";
- else
- mon_sent_frames <= mon_sent_frames;
- end if;
- end if;
-end process;
-MONITOR_SELECT_SENT_OUT <= mon_sent_frames;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- mon_sent_bytes <= (others => '0');
- elsif (tc_rd_en = '1') then
- mon_sent_bytes <= mon_sent_bytes + x"1";
- else
- mon_sent_bytes <= mon_sent_bytes;
- end if;
- end if;
-end process;
-
-MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes;
-
-
-MONITOR_SELECT_REC_BYTES_OUT <= (others => '0');
-MONITOR_SELECT_REC_OUT <= (others => '0');
-
-DEBUG_OUT(31 downto 0) <= ipu_dbg(31 downto 0);
-DEBUG_OUT(63 downto 32) <= constr_dbg(31 downto 0);
-
-
-
-end trb_net16_gbe_response_constructor_TrbNetData;
-
-
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
---use work.version.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-entity gbe_setup is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
-
- -- interface to regio bus
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);
- BUS_WRITE_EN_IN : in std_logic;
- BUS_READ_EN_IN : in std_logic;
- BUS_ACK_OUT : out std_logic;
-
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0);
- GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0);
- GBE_USE_GBE_OUT : out std_logic;
- GBE_USE_TRBNET_OUT : out std_logic;
- GBE_USE_MULTIEVENTS_OUT : out std_logic;
- GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0);
- GBE_READOUT_CTR_VALID_OUT : out std_logic;
- GBE_ALLOW_RX_OUT : out std_logic;
- GBE_ADDITIONAL_HDR_OUT : out std_logic;
- GBE_INSERT_TTYPE_OUT : out std_logic;
- GBE_SOFT_RESET_OUT : out std_logic;
-
- GBE_MAX_SUB_OUT : out std_logic_vector(15 downto 0);
- GBE_MAX_QUEUE_OUT : out std_logic_vector(15 downto 0);
- GBE_MAX_SUBS_IN_QUEUE_OUT : out std_logic_vector(15 downto 0);
- GBE_MAX_SINGLE_SUB_OUT : out std_logic_vector(15 downto 0);
-
- MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0);
- MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0);
- MONITOR_TX_BYTES_IN : in std_logic_vector(31 downto 0);
- MONITOR_TX_FRAMES_IN : in std_logic_vector(31 downto 0);
- MONITOR_TX_PACKETS_IN : in std_logic_vector(31 downto 0);
- MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0);
-
- MONITOR_SELECT_REC_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_REC_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_IN_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_OUT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_GEN_DBG_IN : in std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
- DATA_HIST_IN : in hist_array;
- SCTRL_HIST_IN : in hist_array
-);
-end entity;
-
-architecture gbe_setup of gbe_setup is
-
-signal reset_values : std_logic;
-signal subevent_id : std_logic_vector(31 downto 0);
-signal subevent_dec : std_logic_vector(31 downto 0);
-signal queue_dec : std_logic_vector(31 downto 0);
-signal max_frame : std_logic_vector(15 downto 0);
-signal use_gbe : std_logic;
-signal use_trbnet : std_logic;
-signal use_multievents : std_logic;
-signal readout_ctr : std_logic_vector(23 downto 0);
-signal readout_ctr_valid : std_logic;
-signal ack : std_logic;
-signal ack_q : std_logic;
-signal data_out : std_logic_vector(31 downto 0);
-signal allow_rx : std_logic;
-signal additional_hdr : std_logic;
-signal insert_ttype : std_logic;
- signal max_sub, max_queue, max_subs_in_queue, max_single_sub : std_logic_vector(15 downto 0);
-
-begin
-
-OUT_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- GBE_SUBEVENT_ID_OUT <= subevent_id;
- GBE_SUBEVENT_DEC_OUT <= subevent_dec;
- GBE_QUEUE_DEC_OUT <= queue_dec;
- GBE_MAX_FRAME_OUT <= max_frame;
- GBE_USE_GBE_OUT <= use_gbe;
- GBE_USE_TRBNET_OUT <= use_trbnet;
- GBE_USE_MULTIEVENTS_OUT <= use_multievents;
- GBE_READOUT_CTR_OUT <= readout_ctr;
- GBE_READOUT_CTR_VALID_OUT <= readout_ctr_valid;
- BUS_ACK_OUT <= ack_q;
- ack_q <= ack;
- BUS_DATA_OUT <= data_out;
- GBE_ALLOW_RX_OUT <= '1'; --allow_rx;
- GBE_INSERT_TTYPE_OUT <= insert_ttype;
- GBE_ADDITIONAL_HDR_OUT <= additional_hdr;
- GBE_MAX_SUB_OUT <= max_sub;
- GBE_MAX_QUEUE_OUT <= max_queue;
- GBE_MAX_SUBS_IN_QUEUE_OUT <= max_subs_in_queue;
- GBE_MAX_SINGLE_SUB_OUT <= max_single_sub;
- end if;
-end process OUT_PROC;
-
-ACK_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- ack <= '0';
- elsif ((BUS_WRITE_EN_IN = '1') or (BUS_READ_EN_IN = '1')) then
- ack <= '1';
- else
- ack <= '0';
- end if;
- end if;
-end process ACK_PROC;
-
-WRITE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (reset_values = '1') ) then
- subevent_id <= x"0000_00cf";
- subevent_dec <= x"0002_0001";
- queue_dec <= x"0003_0062";
- max_frame <= x"0578";
- use_gbe <= '0';
- use_trbnet <= '0';
- use_multievents <= '0';
- reset_values <= '0';
- readout_ctr <= x"00_0000";
- readout_ctr_valid <= '0';
- allow_rx <= '1';
- insert_ttype <= '0';
- additional_hdr <= '1';
- GBE_SOFT_RESET_OUT <= '0';
- max_sub <= x"e998"; -- 59800
- max_queue <= x"ea60"; -- 60000
- max_subs_in_queue <= x"00c8"; -- 200
- max_single_sub <= x"7d00"; -- 32000
-
- elsif (BUS_WRITE_EN_IN = '1') then
-
- GBE_SOFT_RESET_OUT <= '0';
-
- case BUS_ADDR_IN is
-
- when x"00" =>
- subevent_id <= BUS_DATA_IN;
-
- when x"01" =>
- subevent_dec <= BUS_DATA_IN;
-
- when x"02" =>
- queue_dec <= BUS_DATA_IN;
-
- when x"04" =>
- max_frame <= BUS_DATA_IN(15 downto 0);
-
- when x"05" =>
- if (BUS_DATA_IN = x"0000_0000") then
- use_gbe <= '0';
- else
- use_gbe <= '1';
- end if;
-
- when x"06" =>
- if (BUS_DATA_IN = x"0000_0000") then
- use_trbnet <= '0';
- else
- use_trbnet <= '1';
- end if;
-
- when x"07" =>
- if (BUS_DATA_IN = x"0000_0000") then
- use_multievents <= '0';
- else
- use_multievents <= '1';
- end if;
-
- when x"08" =>
- readout_ctr <= BUS_DATA_IN(23 downto 0);
- readout_ctr_valid <= '1';
-
- when x"09" =>
- allow_rx <= BUS_DATA_IN(0);
-
- when x"0a" =>
- additional_hdr <= BUS_DATA_IN(0);
-
- when x"0b" =>
- insert_ttype <= BUS_DATA_IN(0);
-
- when x"0c" =>
- max_sub <= BUS_DATA_IN(15 downto 0);
-
- when x"10" =>
- max_queue <= BUS_DATA_IN(15 downto 0);
-
- when x"0e" =>
- max_subs_in_queue <= BUS_DATA_IN(15 downto 0);
-
- when x"0f" =>
- max_single_sub <= BUS_DATA_IN(15 downto 0);
-
-
- when x"ff" =>
- if (BUS_DATA_IN = x"ffff_ffff") then
- reset_values <= '0';
- GBE_SOFT_RESET_OUT <= '1';
- else
- reset_values <= '0';
- GBE_SOFT_RESET_OUT <= '0';
- end if;
-
- when others =>
- subevent_id <= subevent_id;
- subevent_dec <= subevent_dec;
- queue_dec <= queue_dec;
- max_frame <= max_frame;
- use_gbe <= use_gbe;
- use_trbnet <= use_trbnet;
- use_multievents <= use_multievents;
- reset_values <= reset_values;
- readout_ctr <= readout_ctr;
- readout_ctr_valid <= readout_ctr_valid;
- allow_rx <= allow_rx;
- additional_hdr <= additional_hdr;
- insert_ttype <= insert_ttype;
- max_sub <= max_sub;
- max_queue <= max_queue;
- max_subs_in_queue <= max_subs_in_queue;
- max_single_sub <= max_single_sub;
- end case;
- else
- reset_values <= '0';
- readout_ctr_valid <= '0';
- GBE_SOFT_RESET_OUT <= '0';
- end if;
- end if;
-end process WRITE_PROC;
-
-READ_PROC : process(CLK)
- variable address : integer range 0 to 255;
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- data_out <= (others => '0');
- elsif (BUS_READ_EN_IN = '1') then
-
- address := to_integer(unsigned(BUS_ADDR_IN));
-
- case address is
-
- when 0 =>
- data_out <= subevent_id;
-
- when 1 =>
- data_out <= subevent_dec;
-
- when 2 =>
- data_out <= queue_dec;
-
- when 4 =>
- data_out(15 downto 0) <= max_frame;
- data_out(31 downto 16) <= (others => '0');
-
- when 5 =>
- if (use_gbe = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- when 6 =>
- if (use_trbnet = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- when 7 =>
- if (use_multievents = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- when 9 =>
- data_out(0) <= allow_rx;
- data_out(31 downto 1) <= (others => '0');
-
- when 10 =>
- data_out(0) <= additional_hdr;
- data_out(31 downto 1) <= (others => '0');
-
- when 11 =>
- data_out(0) <= insert_ttype;
- data_out(31 downto 1) <= (others => '0');
-
- when 12 =>
- data_out(15 downto 0) <= max_sub;
- data_out(31 downto 16) <= (others => '0');
-
- when 14 =>
- data_out(15 downto 0) <= max_subs_in_queue;
- data_out(31 downto 16) <= (others => '0');
-
- when 15 =>
- data_out(15 downto 0) <= max_single_sub;
- data_out(31 downto 16) <= (others => '0');
-
- when 16 =>
- data_out(15 downto 0) <= max_queue;
- data_out(31 downto 16) <= (others => '0');
-
- -- Histogram of sctrl data sizes
- when 96 to 127 =>
- data_out <= SCTRL_HIST_IN(address - 96);
-
- -- Histogram of TrbNetData data sizes
- when 128 to 159 =>
- data_out <= DATA_HIST_IN(address - 128);
-
- -- General statistics
- when 224 =>
- data_out <= MONITOR_RX_BYTES_IN;
-
- when 225 =>
- data_out <= MONITOR_RX_FRAMES_IN;
-
- when 226 =>
- data_out <= MONITOR_TX_BYTES_IN;
-
- when 227 =>
- data_out <= MONITOR_TX_FRAMES_IN;
-
- when 228 =>
- data_out <= MONITOR_TX_PACKETS_IN;
-
- when 229 =>
- data_out <= MONITOR_DROPPED_IN;
-
- -- Sctrl
- when 160 =>
- data_out <= MONITOR_SELECT_REC_IN(3 * 32 - 1 downto 2 * 32);
- when 161 =>
- data_out <= MONITOR_SELECT_REC_BYTES_IN(3 * 32 - 1 downto 2 * 32);
- when 162 =>
- data_out <= MONITOR_SELECT_SENT_IN(3 * 32 - 1 downto 2 * 32);
- when 163 =>
- data_out <= MONITOR_SELECT_SENT_BYTES_IN(3 * 32 - 1 downto 2 * 32);
- when 164 =>
- data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 - 32 downto 2 * 64);
- when 165 =>
- data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 downto 2 * 64 + 32);
- when 166 =>
- data_out <= MONITOR_SELECT_DROP_IN_IN(3 * 32 - 1 downto 2 * 32);
- when 167 =>
- data_out <= MONITOR_SELECT_DROP_OUT_IN(3 * 32 - 1 downto 2 * 32);
-
- -- TrbnetData
- when 176 =>
- data_out <= MONITOR_SELECT_REC_IN(4 * 32 - 1 downto 3 * 32);
- when 177 =>
- data_out <= MONITOR_SELECT_REC_BYTES_IN(4 * 32 - 1 downto 3 * 32);
- when 178 =>
- data_out <= MONITOR_SELECT_SENT_IN(4 * 32 - 1 downto 3 * 32);
- when 179 =>
- data_out <= MONITOR_SELECT_SENT_BYTES_IN(4 * 32 - 1 downto 3 * 32);
- when 180 =>
- data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 - 32 downto 3 * 64);
- when 181 =>
- data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 downto 3 * 64 + 32);
- when 182 =>
- data_out <= MONITOR_SELECT_DROP_IN_IN(4 * 32 - 1 downto 3 * 32);
- when 183 =>
- data_out <= MONITOR_SELECT_DROP_OUT_IN(4 * 32 - 1 downto 3 * 32);
-
- -- for older network monitors
- when 243 =>
- data_out <= MONITOR_TX_BYTES_IN;
-
- when 244 =>
- data_out <= MONITOR_TX_FRAMES_IN;
-
- when others =>
- data_out <= (others => '0');
- end case;
- end if;
- end if;
-end process READ_PROC;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
---use work.version.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-entity gbe_setup is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
-
- -- interface to regio bus
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
-
- -- gk 26.04.10
- -- input from gbe_buf (only to return the whole trigger number via regio)
- GBE_TRIG_NR_IN : in std_logic_vector(31 downto 0);
-
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0);
- GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_MAX_PACKET_OUT : out std_logic_vector(31 downto 0);
- GBE_MIN_PACKET_OUT : out std_logic_vector(31 downto 0);
- GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0);
- GBE_USE_GBE_OUT : out std_logic;
- GBE_USE_TRBNET_OUT : out std_logic;
- GBE_USE_MULTIEVENTS_OUT : out std_logic;
- GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10
- GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10
- GBE_DELAY_OUT : out std_logic_vector(31 downto 0);
- GBE_ALLOW_LARGE_OUT : out std_logic;
- GBE_ALLOW_RX_OUT : out std_logic;
- GBE_ALLOW_BRDCST_ETH_OUT : out std_logic;
- GBE_ALLOW_BRDCST_IP_OUT : out std_logic;
- GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10
- GBE_ALLOWED_TYPES_OUT : out std_logic_vector(31 downto 0);
- GBE_ALLOWED_IP_OUT : out std_logic_vector(31 downto 0);
- GBE_ALLOWED_UDP_OUT : out std_logic_vector(31 downto 0);
- GBE_VLAN_ID_OUT : out std_logic_vector(31 downto 0);
- -- gk 28.07.10
- MONITOR_BYTES_IN : in std_logic_vector(31 downto 0);
- MONITOR_SENT_IN : in std_logic_vector(31 downto 0);
- MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0);
- MONITOR_SM_IN : in std_logic_vector(31 downto 0);
- MONITOR_LR_IN : in std_logic_vector(31 downto 0);
- MONITOR_HDR_IN : in std_logic_vector(31 downto 0);
- MONITOR_FIFOS_IN : in std_logic_vector(31 downto 0);
- MONITOR_DISCFRM_IN : in std_logic_vector(31 downto 0);
- MONITOR_LINK_DWN_IN : in std_logic_vector(31 downto 0); -- gk 30.09.10
- MONITOR_EMPTY_IN : in std_logic_vector(31 downto 0); -- gk 01.10.10
- MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0);
- MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0);
- MONITOR_RX_BYTES_R_IN : in std_logic_vector(31 downto 0);
- -- gk 01.06.10
- DBG_IPU2GBE1_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE2_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE3_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE4_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE5_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE6_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE7_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE8_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE9_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE10_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE11_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE12_IN : in std_logic_vector(31 downto 0);
- DBG_PC1_IN : in std_logic_vector(31 downto 0);
- DBG_PC2_IN : in std_logic_vector(31 downto 0);
- DBG_FC1_IN : in std_logic_vector(31 downto 0);
- DBG_FC2_IN : in std_logic_vector(31 downto 0);
- DBG_FT1_IN : in std_logic_vector(31 downto 0);
- DBG_FT2_IN : in std_logic_vector(31 downto 0);
- DBG_FR_IN : in std_logic_vector(95 downto 0);
- DBG_RC_IN : in std_logic_vector(63 downto 0);
- DBG_MC_IN : in std_logic_vector(63 downto 0);
- DBG_TC_IN : in std_logic_vector(31 downto 0);
- DBG_FIFO_RD_EN_OUT : out std_logic;
-
- DBG_SELECT_REC_IN : in std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- DBG_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- DBG_SELECT_PROTOS_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
- DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0)
- --DBG_RESET_FIFO_OUT : out std_logic -- gk 28.09.10
-);
-end entity;
-
-architecture gbe_setup of gbe_setup is
-
--- attribute HGROUP : string;
--- attribute HGROUP of gbe_setup : architecture is "GBE_conf";
-
-signal reset_values : std_logic;
-
-signal subevent_id : std_logic_vector(31 downto 0);
-signal subevent_dec : std_logic_vector(31 downto 0);
-signal queue_dec : std_logic_vector(31 downto 0);
-signal max_packet : std_logic_vector(31 downto 0);
-signal min_packet : std_logic_vector(31 downto 0); -- gk 07.20.10
-signal max_frame : std_logic_vector(15 downto 0);
-signal use_gbe : std_logic;
-signal use_trbnet : std_logic;
-signal use_multievents : std_logic;
-signal readout_ctr : std_logic_vector(23 downto 0); -- gk 26.04.10
-signal readout_ctr_valid : std_logic; -- gk 26.04.10
-signal ack : std_logic; -- gk 26.04.10
-signal ack_q : std_logic; -- gk 26.04.10
-signal data_out : std_logic_vector(31 downto 0); -- gk 26.04.10
-signal delay : std_logic_vector(31 downto 0); -- gk 28.04.10
-signal allow_large : std_logic; -- gk 21.07.10
-signal reset_fifo : std_logic; -- gk 28.09.10
-signal allow_rx : std_logic;
-signal frame_delay : std_logic_vector(31 downto 0); -- gk 09.12.10
-signal allowed_types : std_logic_vector(31 downto 0);
-signal allowed_ip : std_logic_vector(31 downto 0);
-signal allowed_udp : std_logic_vector(31 downto 0);
-signal vlan_id : std_logic_vector(31 downto 0);
-
-begin
-
-OUT_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- GBE_SUBEVENT_ID_OUT <= subevent_id;
- GBE_SUBEVENT_DEC_OUT <= subevent_dec;
- GBE_QUEUE_DEC_OUT <= queue_dec;
- GBE_MAX_PACKET_OUT <= max_packet;
- GBE_MIN_PACKET_OUT <= min_packet;
- GBE_MAX_FRAME_OUT <= max_frame;
- GBE_USE_GBE_OUT <= use_gbe;
- GBE_USE_TRBNET_OUT <= use_trbnet;
- GBE_USE_MULTIEVENTS_OUT <= use_multievents;
- GBE_READOUT_CTR_OUT <= readout_ctr; -- gk 26.04.10
- GBE_READOUT_CTR_VALID_OUT <= readout_ctr_valid; -- gk 26.04.10
- BUS_ACK_OUT <= ack_q; -- gk 26.04.10
- ack_q <= ack; -- gk 26.04.10
- BUS_DATA_OUT <= data_out; -- gk 26.04.10
- GBE_DELAY_OUT <= delay; -- gk 28.04.10
- GBE_ALLOW_LARGE_OUT <= allow_large; -- gk 21.07.10
- GBE_ALLOW_RX_OUT <= allow_rx;
- --DBG_RESET_FIFO_OUT <= reset_fifo; -- gk 28.09.10
- GBE_FRAME_DELAY_OUT <= frame_delay; -- gk 09.12.10
- GBE_ALLOWED_TYPES_OUT <= allowed_types;
- GBE_ALLOWED_IP_OUT <= allowed_ip;
- GBE_ALLOWED_UDP_OUT <= allowed_udp;
- GBE_VLAN_ID_OUT <= vlan_id;
- end if;
-end process OUT_PROC;
-
--- gk 26.04.10
-ACK_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- ack <= '0';
- elsif ((BUS_WRITE_EN_IN = '1') or (BUS_READ_EN_IN = '1')) then
- ack <= '1';
- else
- ack <= '0';
- end if;
- end if;
-end process ACK_PROC;
-
-WRITE_PROC : process(CLK)
-begin
- DBG_FIFO_RD_EN_OUT <= '0';
-
- if rising_edge(CLK) then
- if ( (RESET = '1') or (reset_values = '1') ) then
- subevent_id <= x"0000_00cf";
- subevent_dec <= x"0002_0001";
- queue_dec <= x"0003_0062";
- max_packet <= x"0000_0fd0"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester
- min_packet <= x"0000_0007"; -- gk 20.07.10
- max_frame <= x"0578";
- use_gbe <= '0'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured
- use_trbnet <= '0';
- use_multievents <= '0';
- reset_values <= '0';
- readout_ctr <= x"00_0000"; -- gk 26.04.10 -- gk 07.06.10 corrected bug found by Sergey
- readout_ctr_valid <= '0'; -- gk 26.04.10
- delay <= x"0000_0000"; -- gk 28.04.10
- DBG_FIFO_RD_EN_OUT <= '0';
- allow_large <= '0'; -- gk 21.07.10
- reset_fifo <= '0'; -- gk 28.09.10
- allow_rx <= '1';
- frame_delay <= x"0000_0000"; -- gk 09.12.10
- allowed_types <= x"0000_00ff"; -- only test protocol allowed
- allowed_ip <= x"0000_00ff";
- allowed_udp <= x"0000_00ff";
- vlan_id <= x"0000_0000"; -- no vlan id by default
-
- elsif (BUS_WRITE_EN_IN = '1') then
- case BUS_ADDR_IN is
-
- when x"00" =>
- subevent_id <= BUS_DATA_IN;
-
- when x"01" =>
- subevent_dec <= BUS_DATA_IN;
-
- when x"02" =>
- queue_dec <= BUS_DATA_IN;
-
- when x"03" =>
- max_packet <= BUS_DATA_IN;
-
- when x"04" =>
- max_frame <= BUS_DATA_IN(15 downto 0);
-
- when x"05" =>
- if (BUS_DATA_IN = x"0000_0000") then
- use_gbe <= '0';
- else
- use_gbe <= '1';
- end if;
-
- when x"06" =>
- if (BUS_DATA_IN = x"0000_0000") then
- use_trbnet <= '0';
- else
- use_trbnet <= '1';
- end if;
-
- when x"07" =>
- if (BUS_DATA_IN = x"0000_0000") then
- use_multievents <= '0';
- else
- use_multievents <= '1';
- end if;
-
- -- gk 26.04.10
- when x"08" =>
- readout_ctr <= BUS_DATA_IN(23 downto 0);
- readout_ctr_valid <= '1';
-
- -- gk 28.04.10
- when x"09" =>
- delay <= BUS_DATA_IN;
-
- when x"0a" =>
- DBG_FIFO_RD_EN_OUT <= '1';
-
- -- gk 20.07.10
- when x"0b" =>
- min_packet <= BUS_DATA_IN;
-
- -- gk 21.07.10
- when x"0c" =>
- if (BUS_DATA_IN = x"0000_0000") then
- allow_large <= '0';
- else
- allow_large <= '1';
- end if;
-
- -- gk 09.12.10
- when x"0d" =>
- frame_delay <= BUS_DATA_IN;
-
- when x"0e" =>
- allow_rx <= BUS_DATA_IN(0);
-
- when x"0f" =>
- allowed_types <= BUS_DATA_IN;
-
- when x"10" =>
- vlan_id <= BUS_DATA_IN;
-
- when x"11" =>
- allowed_ip <= BUS_DATA_IN;
-
- when x"12" =>
- allowed_udp <= BUS_DATA_IN;
-
- -- gk 28.09.10
- when x"fe" =>
- if (BUS_DATA_IN = x"ffff_ffff") then
- reset_fifo <= '1';
- else
- reset_fifo <= '0';
- end if;
-
- when x"ff" =>
- if (BUS_DATA_IN = x"ffff_ffff") then
- reset_values <= '1';
- else
- reset_values <= '0';
- end if;
-
- when others =>
- subevent_id <= subevent_id;
- subevent_dec <= subevent_dec;
- queue_dec <= queue_dec;
- max_packet <= max_packet;
- min_packet <= min_packet;
- max_frame <= max_frame;
- use_gbe <= use_gbe;
- use_trbnet <= use_trbnet;
- use_multievents <= use_multievents;
- reset_values <= reset_values;
- readout_ctr <= readout_ctr; -- gk 26.04.10
- readout_ctr_valid <= readout_ctr_valid; -- gk 26.04.10
- delay <= delay; -- gk 28.04.10
- DBG_FIFO_RD_EN_OUT <= '0';
- allow_large <= allow_large;
- reset_fifo <= reset_fifo; -- gk 28.09.10
- allow_rx <= allow_rx;
- frame_delay <= frame_delay;
- allowed_types <= allowed_types;
- vlan_id <= vlan_id;
- allowed_ip <= allowed_ip;
- allowed_udp <= allowed_udp;
-
- end case;
- else
- reset_values <= '0';
- readout_ctr_valid <= '0'; -- gk 26.04.10
- --reset_fifo <= '0'; -- gk 28.09.10
- end if;
- end if;
-end process WRITE_PROC;
-
--- gk 26.04.10
-READ_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- data_out <= (others => '0');
- elsif (BUS_READ_EN_IN = '1') then
- case BUS_ADDR_IN is
-
- when x"00" =>
- data_out <= subevent_id;
-
- when x"01" =>
- data_out <= subevent_dec;
-
- when x"02" =>
- data_out <= queue_dec;
-
- when x"03" =>
- data_out <= max_packet;
-
- when x"04" =>
- data_out(15 downto 0) <= max_frame;
- data_out(31 downto 16) <= (others => '0');
-
- when x"05" =>
- if (use_gbe = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- when x"06" =>
- if (use_trbnet = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- when x"07" =>
- if (use_multievents = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- when x"08" =>
- data_out <= GBE_TRIG_NR_IN;
-
- when x"09" =>
- data_out <= delay;
-
- when x"0b" =>
- data_out <= min_packet;
-
- -- gk 21.07.10
- when x"0c" =>
- if (allow_large = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- -- gk 09.12.10
- when x"0d" =>
- data_out <= frame_delay;
-
-
- when x"0e" =>
- data_out(0) <= allow_rx;
- data_out(31 downto 1) <= (others => '0');
-
- when x"0f" =>
- data_out <= allowed_types;
-
- when x"10" =>
- data_out <= vlan_id;
-
- when x"11" =>
- data_out <= allowed_ip;
-
- when x"12" =>
- data_out <= allowed_udp;
-
- -- gk 01.06.10
- --when x"e0" =>
- -- data_out <= DBG_IPU2GBE1_IN;
-
- --when x"e1" =>
- -- data_out <= DBG_IPU2GBE2_IN;
-
- --when x"e2" =>
- -- data_out <= DBG_PC1_IN;
-
- --when x"e3" =>
- -- data_out <= DBG_PC2_IN;
-
- --when x"e4" =>
- -- data_out <= DBG_FC1_IN;
-
- --when x"e5" =>
- -- data_out <= DBG_FC2_IN;
-
- --when x"e6" =>
- -- data_out <= DBG_FT1_IN;
-
- --when x"e7" =>
- -- data_out <= DBG_FT2_IN;
-
- --when x"e8" =>
- -- data_out(15 downto 0) <= DBG_FIFO_Q_IN;
- -- data_out(31 downto 16) <= (others => '0');
-
- --when x"e9" =>
- -- data_out <= DBG_IPU2GBE3_IN;
-
- --when x"ea" =>
- -- data_out <= DBG_IPU2GBE4_IN;
-
- --when x"eb" =>
- -- data_out <= DBG_IPU2GBE5_IN;
-
- --when x"ec" =>
- -- data_out <= DBG_IPU2GBE6_IN;
-
- --when x"ed" =>
- -- data_out <= DBG_IPU2GBE7_IN;
-
- --when x"ee" =>
- -- data_out <= DBG_IPU2GBE8_IN;
-
- --when x"ef" =>
- -- data_out <= DBG_IPU2GBE9_IN;
-
- --when x"f0" =>
- -- data_out <= DBG_IPU2GBE10_IN;
-
- --when x"f1" =>
- -- data_out <= DBG_IPU2GBE11_IN;
-
- --when x"f2" =>
- -- data_out <= DBG_IPU2GBE12_IN;
-
- --when x"f3" =>
- -- data_out <= MONITOR_BYTES_IN;
-
- --when x"f4" =>
- -- data_out <= MONITOR_SENT_IN;
-
- --when x"f5" =>
- -- data_out <= MONITOR_DROPPED_IN;
-
- --when x"f6" =>
- -- data_out <= MONITOR_SM_IN;
-
- --when x"f7" =>
- -- data_out <= MONITOR_LR_IN;
-
- --when x"f8" =>
- -- data_out <= MONITOR_HDR_IN;
-
- --when x"f9" =>
- -- data_out <= MONITOR_FIFOS_IN;
-
- --when x"fa" =>
- -- data_out <= MONITOR_DISCFRM_IN;
-
- --when x"fb" =>
- -- data_out <= MONITOR_LINK_DWN_IN;
-
- --when x"fc" =>
- -- data_out <= MONITOR_EMPTY_IN;
-
- --when x"d1" =>
- -- data_out <= DBG_FR_IN;
-
- --when x"d2" =>
- -- data_out <= DBG_RC_IN;
-
- --when x"d4" =>
- -- data_out <= DBG_TC_IN;
-
- -- **** transmit section
-
- when x"90" =>
- data_out <= DBG_FT2_IN;
-
- -- **** receive debug section
-
- when x"a0" =>
- data_out <= DBG_FR_IN(31 downto 0); -- received frames from tsmac | state machine | fifos status
-
- when x"a1" =>
- data_out <= DBG_FR_IN(63 downto 32); -- dropped | accepted frames
-
- when x"a2" =>
- data_out <= MONITOR_RX_FRAMES_IN;
-
- when x"a3" =>
- data_out <= MONITOR_RX_BYTES_IN;
-
- when x"a4" =>
- data_out <= MONITOR_RX_BYTES_R_IN;
-
- when x"a5" =>
- data_out <= DBG_MC_IN(31 downto 0);
-
- when x"a6" =>
- data_out <= g_MY_IP;
-
- when x"a7" =>
- data_out <= DBG_FR_IN(95 downto 64); -- ok | error frames
-
-
- -- *** debug of response constructors
-
- -- ARP
- when x"b0" =>
- data_out(15 downto 0) <= DBG_SELECT_REC_IN(1 * 16 - 1 downto 0 * 16);
- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(1 * 16 - 1 downto 0 * 16);
- when x"b1" =>
- data_out <= DBG_SELECT_PROTOS_IN(1 * 32 - 1 downto 0 * 32);
-
- -- DHCP
- when x"b2" =>
- data_out(15 downto 0) <= DBG_SELECT_REC_IN(2 * 16 - 1 downto 1 * 16);
- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(2 * 16 - 1 downto 1 * 16);
- when x"b3" =>
- data_out <= DBG_SELECT_PROTOS_IN(1 * 32 - 1 downto 0 * 32);
-
- -- PING
- when x"b4" =>
- data_out(15 downto 0) <= DBG_SELECT_REC_IN(3 * 16 - 1 downto 2 * 16);
- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(3 * 16 - 1 downto 2 * 16);
- when x"b5" =>
- data_out <= DBG_SELECT_PROTOS_IN(3 * 32 - 1 downto 2 * 32);
-
- -- Test1a
- when x"b6" =>
- data_out(15 downto 0) <= DBG_SELECT_REC_IN(4 * 16 - 1 downto 3 * 16);
- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(4 * 16 - 1 downto 3 * 16);
- when x"b7" =>
- data_out <= DBG_SELECT_PROTOS_IN(4 * 32 - 1 downto 3 * 32);
-
- -- Test1b
- when x"b8" =>
- data_out(15 downto 0) <= DBG_SELECT_REC_IN(5 * 16 - 1 downto 4 * 16);
- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(5 * 16 - 1 downto 4 * 16);
- when x"b9" =>
- data_out <= DBG_SELECT_PROTOS_IN(5 * 32 - 1 downto 4 * 32);
-
- -- **** end of received debug section
-
- when others =>
- data_out <= (others => '0');
- end case;
- end if;
- end if;
-end process READ_PROC;
-
-end architecture;
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_protocols.all;
-
---********
--- doing shit right now
-
-entity trb_net16_gbe_transmit_control is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
-
--- signal to/from main controller
- MC_TRANSMIT_CTRL_IN : in std_logic;
- MC_DATA_IN : in std_logic_vector(8 downto 0);
- MC_WR_EN_IN : in std_logic;
- MC_DATA_NOT_VALID_IN : in std_logic;
- MC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- MC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
-
- MC_DEST_MAC_IN : in std_logic_vector(47 downto 0);
- MC_DEST_IP_IN : in std_logic_vector(31 downto 0);
- MC_DEST_UDP_IN : in std_logic_vector(15 downto 0);
- MC_SRC_MAC_IN : in std_logic_vector(47 downto 0);
- MC_SRC_IP_IN : in std_logic_vector(31 downto 0);
- MC_SRC_UDP_IN : in std_logic_vector(15 downto 0);
-
- MC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- MC_IDENT_IN : in std_logic_vector(15 downto 0);
-
- MC_IP_SIZE_IN : in std_logic_vector(15 downto 0);
- MC_UDP_SIZE_IN : in std_logic_vector(15 downto 0);
- MC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
-
- MC_FC_H_READY_OUT : out std_logic;
- MC_FC_READY_OUT : out std_logic;
- MC_FC_WR_EN_IN : in std_logic;
-
- MC_BUSY_OUT : out std_logic;
- MC_TRANSMIT_DONE_OUT : out std_logic;
-
--- signal to/from frame constructor
- FC_DATA_OUT : out std_logic_vector(7 downto 0);
- FC_WR_EN_OUT : out std_logic;
- FC_READY_IN : in std_logic;
- FC_H_READY_IN : in std_logic;
- FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- FC_SOD_OUT : out std_logic;
- FC_EOD_OUT : out std_logic;
- FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
-
- DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_transmit_control;
-
-
-architecture trb_net16_gbe_transmit_control of trb_net16_gbe_transmit_control is
-
-begin
-
-SYNC_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
-
- MC_FC_H_READY_OUT <= FC_H_READY_IN;
- MC_FC_READY_OUT <= FC_READY_IN;
-
- FC_FRAME_TYPE_OUT <= MC_FRAME_TYPE_IN;
-
- FC_DATA_OUT <= MC_DATA_IN(7 downto 0);
- FC_IP_PROTOCOL_OUT <= MC_IP_PROTOCOL_IN;
-
- if (MC_TRANSMIT_CTRL_IN = '1') then
- FC_SOD_OUT <= '1';
- else
- FC_SOD_OUT <= '0';
- end if;
-
- if (MC_DATA_IN(8) = '1') then
- FC_EOD_OUT <= '1';
- else
- FC_EOD_OUT <= '0';
- end if;
-
- if (MC_FRAME_TYPE_IN = x"0008") then
- FC_IP_SIZE_OUT <= MC_IP_SIZE_IN;
- FC_UDP_SIZE_OUT <= MC_UDP_SIZE_IN;
- else
- FC_IP_SIZE_OUT <= MC_FRAME_SIZE_IN;
- FC_UDP_SIZE_OUT <= MC_FRAME_SIZE_IN;
- end if;
-
-
- if (MC_DATA_NOT_VALID_IN = '0' and MC_WR_EN_IN = '1') then
- FC_WR_EN_OUT <= '1';
- else
- FC_WR_EN_OUT <= '0';
- end if;
-
- FC_FLAGS_OFFSET_OUT <= MC_FLAGS_OFFSET_IN;
-
- DEST_MAC_ADDRESS_OUT <= MC_DEST_MAC_IN;
- DEST_IP_ADDRESS_OUT <= MC_DEST_IP_IN;
- DEST_UDP_PORT_OUT <= MC_DEST_UDP_IN;
- SRC_MAC_ADDRESS_OUT <= MC_SRC_MAC_IN;
- SRC_IP_ADDRESS_OUT <= MC_SRC_IP_IN;
- SRC_UDP_PORT_OUT <= MC_SRC_UDP_IN;
-
- FC_IDENT_OUT <= MC_IDENT_IN;
- end if;
-end process SYNC_PROC;
-
-end trb_net16_gbe_transmit_control;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_protocols.all;
-
---********
--- performs response constructors readout and splitting into frames
-
-entity trb_net16_gbe_transmit_control2 is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
-
--- signal to/from main controller
- TC_DATAREADY_IN : in std_logic;
- TC_RD_EN_OUT : out std_logic;
- TC_DATA_IN : in std_logic_vector(7 downto 0);
- TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- TC_DEST_MAC_IN : in std_logic_vector(47 downto 0);
- TC_DEST_IP_IN : in std_logic_vector(31 downto 0);
- TC_DEST_UDP_IN : in std_logic_vector(15 downto 0);
- TC_SRC_MAC_IN : in std_logic_vector(47 downto 0);
- TC_SRC_IP_IN : in std_logic_vector(31 downto 0);
- TC_SRC_UDP_IN : in std_logic_vector(15 downto 0);
- TC_TRANSMISSION_DONE_OUT : out std_logic;
- TC_IDENT_IN : in std_logic_vector(15 downto 0);
- TC_MAX_FRAME_IN : in std_logic_vector(15 downto 0);
-
--- signal to/from frame constructor
- FC_DATA_OUT : out std_logic_vector(7 downto 0);
- FC_WR_EN_OUT : out std_logic;
- FC_READY_IN : in std_logic;
- FC_H_READY_IN : in std_logic;
- FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- FC_SOD_OUT : out std_logic;
- FC_EOD_OUT : out std_logic;
- FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
-
- DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
- MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_transmit_control2;
-
-
-architecture trb_net16_gbe_transmit_control2 of trb_net16_gbe_transmit_control2 is
-
-attribute syn_encoding : string;
-
-type transmit_states is (IDLE, PREPARE_HEADERS, WAIT_FOR_H, TRANSMIT, SEND_ONE, SEND_TWO, CLOSE, WAIT_FOR_TRANS, DIVIDE, CLEANUP);
-signal transmit_current_state, transmit_next_state : transmit_states;
-attribute syn_encoding of transmit_current_state : signal is "onehot";
-
-signal tc_rd, tc_rd_q, tc_rd_qq : std_logic;
-signal local_end : std_logic_vector(15 downto 0);
-
-signal actual_frame_bytes, full_packet_size, ip_size, packet_loaded_bytes : std_logic_vector(15 downto 0);
-signal go_to_divide, more_fragments : std_logic;
-signal first_frame : std_logic;
-signal mon_packets_sent_ctr : std_logic_vector(31 downto 0);
-
-begin
-
-TRANSMIT_MACHINE_PROC : process(RESET, CLK)
-begin
- if RESET = '1' then
- transmit_current_state <= IDLE;
- elsif rising_edge(CLK) then
- transmit_current_state <= transmit_next_state;
- end if;
-end process TRANSMIT_MACHINE_PROC;
-
-TRANSMIT_MACHINE : process(transmit_current_state, FC_H_READY_IN, TC_DATAREADY_IN, FC_READY_IN, local_end, TC_MAX_FRAME_IN, actual_frame_bytes, go_to_divide)
-begin
- case transmit_current_state is
-
- when IDLE =>
- if (TC_DATAREADY_IN = '1') then
- transmit_next_state <= PREPARE_HEADERS;
- else
- transmit_next_state <= IDLE;
- end if;
-
- when PREPARE_HEADERS =>
- transmit_next_state<= WAIT_FOR_H;
-
- when WAIT_FOR_H =>
- if (FC_H_READY_IN = '1') then
- transmit_next_state <= TRANSMIT;
- else
- transmit_next_state <= WAIT_FOR_H;
- end if;
-
- when TRANSMIT =>
- if (local_end = x"0000") then
- transmit_next_state <= SEND_ONE;
- else
- if (actual_frame_bytes = TC_MAX_FRAME_IN - x"1") then
- transmit_next_state <= SEND_ONE;
- else
- transmit_next_state <= TRANSMIT;
- end if;
- end if;
-
- when SEND_ONE =>
- transmit_next_state <= SEND_TWO;
-
- when SEND_TWO =>
- transmit_next_state <= CLOSE;
-
- when CLOSE =>
- transmit_next_state <= WAIT_FOR_TRANS;
-
- when WAIT_FOR_TRANS =>
- if (FC_READY_IN = '1') then
- if (go_to_divide = '1') then
- transmit_next_state <= DIVIDE;
- else
- transmit_next_state <= CLEANUP;
- end if;
- else
- transmit_next_state <= WAIT_FOR_TRANS;
- end if;
-
- when DIVIDE =>
- transmit_next_state <= PREPARE_HEADERS;
-
- when CLEANUP =>
- transmit_next_state <= IDLE;
-
- end case;
-end process TRANSMIT_MACHINE;
-
-tc_rd <= '1' when transmit_current_state = TRANSMIT else '0';
-TC_RD_EN_OUT <= tc_rd;
-
-SYNC_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- tc_rd_q <= tc_rd;
- tc_rd_qq <= tc_rd_q;
- FC_WR_EN_OUT <= tc_rd_qq;
- end if;
-end process SYNC_PROC;
-
-ACTUAL_FRAME_BYTES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE or transmit_current_state = DIVIDE) then
- actual_frame_bytes <= (others => '0');
- elsif (transmit_current_state = TRANSMIT) then
- actual_frame_bytes <= actual_frame_bytes + x"1";
- else
- actual_frame_bytes <= actual_frame_bytes;
- end if;
- end if;
-end process ACTUAL_FRAME_BYTES_PROC;
-
-GO_TO_DIVIDE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE or transmit_current_state = DIVIDE) then
- go_to_divide <= '0';
- elsif (transmit_current_state = TRANSMIT and actual_frame_bytes = TC_MAX_FRAME_IN - x"1") then
- go_to_divide <= '1';
--- elsif (transmit_current_state = SEND_ONE and full_packet_size < packet_loaded_bytes - x"1") then
--- go_to_divide <= '1';
--- elsif (transmit_current_state = SEND_TWO and full_packet_size < packet_loaded_bytes - x"1") then
--- go_to_divide <= '1';
- elsif (transmit_current_state = SEND_ONE and full_packet_size = packet_loaded_bytes) then
- go_to_divide <= '0';
- else
- go_to_divide <= go_to_divide;
- end if;
- end if;
-end process GO_TO_DIVIDE_PROC;
-
-LOCAL_END_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE and TC_DATAREADY_IN = '1') then
- local_end <= TC_FRAME_SIZE_IN - x"1";
- full_packet_size <= TC_FRAME_SIZE_IN;
- elsif (transmit_current_state = TRANSMIT) then
- local_end <= local_end - x"1";
- full_packet_size <= full_packet_size;
- else
- local_end <= local_end;
- full_packet_size <= full_packet_size;
- end if;
- end if;
-end process LOCAL_END_PROC;
-
-FC_DATA_OUT <= TC_DATA_IN;
-FC_SOD_OUT <= '1' when transmit_current_state = WAIT_FOR_H else '0';
-FC_EOD_OUT <= '1' when transmit_current_state = CLOSE else '0';
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = PREPARE_HEADERS) then
- if (local_end >= TC_MAX_FRAME_IN) then
- ip_size <= TC_MAX_FRAME_IN;
- else
- ip_size <= local_end + x"1";
- end if;
- else
- ip_size <= ip_size;
- end if;
- end if;
-end process;
-FC_IP_SIZE_OUT <= ip_size;
-FC_UDP_SIZE_OUT <= full_packet_size; --TC_FRAME_SIZE_IN;
-
-FC_FLAGS_OFFSET_OUT(15 downto 14) <= "00";
-FC_FLAGS_OFFSET_OUT(13) <= more_fragments;
-MORE_FRAGMENTS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = PREPARE_HEADERS) then
- if (local_end >= TC_MAX_FRAME_IN) then
- more_fragments <= '1';
- else
- more_fragments <= '0';
- end if;
- else
- more_fragments <= more_fragments;
- end if;
- end if;
-end process MORE_FRAGMENTS_PROC;
-FC_FLAGS_OFFSET_OUT(12 downto 0) <= ('0' & x"000") when first_frame = '1' else (packet_loaded_bytes(15 downto 3) + x"1");
-
-PACKET_LOADED_BYTES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE) then
- packet_loaded_bytes <= x"0000";
- elsif (transmit_current_state = TRANSMIT) then
- packet_loaded_bytes <= packet_loaded_bytes + x"1";
--- elsif (transmit_current_state = DIVIDE and first_frame = '1') then
--- packet_loaded_bytes <= packet_loaded_bytes + x"8"; -- 8bytes for udp headers added for the first offset
- else
- packet_loaded_bytes <= packet_loaded_bytes;
- end if;
- end if;
-end process PACKET_LOADED_BYTES_PROC;
-
-FIRST_FRAME_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE) then
- first_frame <= '1';
- elsif (transmit_current_state = DIVIDE) then
- first_frame <= '0';
- else
- first_frame <= first_frame;
- end if;
- end if;
-end process FIRST_FRAME_PROC;
-
-
-TC_TRANSMISSION_DONE_OUT <= '1' when transmit_current_state = CLEANUP else '0';
-
-FC_FRAME_TYPE_OUT <= TC_FRAME_TYPE_IN;
-FC_IP_PROTOCOL_OUT <= TC_IP_PROTOCOL_IN;
-DEST_MAC_ADDRESS_OUT <= TC_DEST_MAC_IN;
-DEST_IP_ADDRESS_OUT <= TC_DEST_IP_IN;
-DEST_UDP_PORT_OUT <= TC_DEST_UDP_IN;
-SRC_MAC_ADDRESS_OUT <= TC_SRC_MAC_IN;
-SRC_IP_ADDRESS_OUT <= TC_SRC_IP_IN;
-SRC_UDP_PORT_OUT <= TC_SRC_UDP_IN;
-FC_IDENT_OUT <= TC_IDENT_IN;
-
--- monitoring
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- mon_packets_sent_ctr <= (others => '0');
- elsif (transmit_current_state = CLEANUP) then
- mon_packets_sent_ctr <= mon_packets_sent_ctr + x"1";
- else
- mon_packets_sent_ctr <= mon_packets_sent_ctr;
- end if;
- end if;
-end process;
-
-MONITOR_TX_PACKETS_OUT <= mon_packets_sent_ctr;
-
-end trb_net16_gbe_transmit_control2;
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-
---********
--- contains valid frame types codes and performs checking of type and vlan id
--- by default there is place for 32 frame type which is hardcoded value
--- due to allow register which is set by slow control
-
-entity trb_net16_gbe_type_validator is
-port (
- CLK : in std_logic; -- 125MHz clock input
- RESET : in std_logic;
- -- ethernet level
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type
- SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id
- ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup
- VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup
-
- -- IP level
- IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0);
- ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
-
- -- UDP level
- UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0);
- ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
-
- VALID_OUT : out std_logic
-);
-end trb_net16_gbe_type_validator;
-
-
-architecture trb_net16_gbe_type_validator of trb_net16_gbe_type_validator is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_type_validator : architecture is "GBE_MAIN_group";
-
-signal result : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0);
-signal ip_result : std_logic_vector(c_MAX_IP_PROTOCOLS - 1 downto 0);
-signal udp_result : std_logic_vector(c_MAX_UDP_PROTOCOLS - 1 downto 0);
-signal partially_valid : std_logic; -- only protocols, vlan to be checked
-signal zeros : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0);
-
-begin
-
- zeros <= (others => '0');
-
--- DO NOT TOUCH
-IP_RESULTS_GEN : for i in 0 to c_MAX_IP_PROTOCOLS - 1 generate
-process(CLK)
-begin
- if rising_edge(CLK) then
- if IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and ALLOWED_IP_PROTOCOLS_IN(i) = '1' then
- ip_result(i) <= '1';
- else
- ip_result(i) <= '0';
- end if;
- end if;
-end process;
-end generate IP_RESULTS_GEN;
-
-UDP_RESULTS_GEN : for i in 0 to c_MAX_UDP_PROTOCOLS - 1 generate
-process(CLK)
-begin
- if rising_edge(CLK) then
- if UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and ALLOWED_UDP_PROTOCOLS_IN(i) = '1' then
- udp_result(i) <= '1';
- else
- udp_result(i) <= '0';
- end if;
- end if;
-end process;
-end generate UDP_RESULTS_GEN;
-
-
-RESULT_GEN : for i in 0 to c_MAX_FRAME_TYPES - 1 generate
-process(CLK)
-begin
- if rising_edge(CLK) then
- if FRAME_TYPES(i) = FRAME_TYPE_IN and ALLOWED_TYPES_IN(i) = '1' then
- result(i) <= '1';
- else
- result(i) <= '0';
- end if;
- end if;
-end process;
-end generate RESULT_GEN;
-
-PARTIALLY_VALID_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- partially_valid <= '0';
- elsif (FRAME_TYPE_IN = x"0800") then -- ip frame
- if (IP_PROTOCOLS_IN = x"11") then -- in case of udp inside ip
- partially_valid <= or_all(udp_result);
- elsif (IP_PROTOCOLS_IN = x"01" or IP_PROTOCOLS_IN = x"dd" or IP_PROTOCOLS_IN = x"ee") then -- in case of ICMP
- partially_valid <= '1';
- else -- do not accept other protocols than udp and icmp inside ip
- partially_valid <= '0';
- end if;
- elsif (result /= zeros) then-- other frame
- partially_valid <= '1';
- else
- partially_valid <= '0';
- end if;
- end if;
-end process PARTIALLY_VALID_PROC;
-
-VALID_OUT_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (partially_valid = '1') then
- if (SAVED_VLAN_ID_IN = x"0000") then
- VALID_OUT <= '1';
- elsif (VLAN_ID_IN = x"0000_0000") then
- VALID_OUT <= '0';
- elsif (SAVED_VLAN_ID_IN = VLAN_ID_IN(15 downto 0) or SAVED_VLAN_ID_IN = VLAN_ID_IN(31 downto 16)) then
- VALID_OUT <= '1';
- else
- VALID_OUT <= '0';
- end if;
- else
- VALID_OUT <= '0';
- end if;
- end if;
-end process VALID_OUT_PROC;
-
-end trb_net16_gbe_type_validator;
-
-
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-
-entity trb_net16_ipu2gbe is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
- MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- -- PacketConstructor interface
- ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic; -- gk 07.10.10
- PC_EOD_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_PADDING_OUT : out std_logic;
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
-);
-end entity;
-
-architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is
-
--- attribute HGROUP : string;
--- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe";
-
-component fifo_32kx16x8_mb2
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(8 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0);
- Empty : out std_logic;
- AlmostEmpty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
-);
-end component;
-
-type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE, RESET_FIFO);
-signal saveCurrentState, saveNextState : saveStates;
-signal state : std_logic_vector(3 downto 0);
-signal data_req_comb : std_logic;
-signal data_req : std_logic; -- request data signal, will be used for fee_read generation
-signal rst_saved_ctr_comb : std_logic;
-signal rst_saved_ctr : std_logic;
-
-signal fee_read_comb : std_logic;
-signal fee_read : std_logic; -- fee_read signal
-signal saved_ctr : std_logic_vector(16 downto 0);
-signal ce_saved_ctr : std_logic;
-
--- header data
-signal cts_rnd : std_logic_vector(15 downto 0);
-signal cts_rnd_saved : std_logic;
-signal cts_trg : std_logic_vector(15 downto 0);
-signal cts_trg_saved : std_logic;
-signal cts_len : std_logic_vector(16 downto 0);
-signal cts_len_saved : std_logic;
-
--- CTS interface
-signal cts_error_pattern : std_logic_vector(31 downto 0);
-signal cts_length : std_logic_vector(15 downto 0);
-signal cts_readout_finished : std_logic;
-signal cts_dataready : std_logic;
-signal cts_data : std_logic_vector(31 downto 0);
-
--- Split FIFO signals
-signal sf_data : std_logic_vector(15 downto 0);
-signal sf_wr_en_comb : std_logic;
-signal sf_wr_en : std_logic; -- write signal for FIFO
-signal sf_rd_en_comb : std_logic;
-signal sf_rd_en : std_logic; -- read signal for FIFO
-signal sf_wcnt : std_logic_vector(15 downto 0);
-signal sf_rcnt : std_logic_vector(16 downto 0);
-signal sf_empty : std_logic;
-signal sf_aempty : std_logic;
-signal sf_full : std_logic;
-signal sf_afull : std_logic;
-
--------------------------------------------------------------------
-type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2);
-signal loadCurrentState, loadNextState : loadStates;
-signal state2 : std_logic_vector(3 downto 0);
-
-signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data
-signal rst_rem_ctr_comb : std_logic;
-signal rst_rem_ctr : std_logic; -- reset the remove counter
-signal rst_regs_comb : std_logic;
-signal rst_regs : std_logic; -- reset storage registers
-signal rem_phase_comb : std_logic;
-signal rem_phase : std_logic; -- header remove phase
-signal data_phase_comb : std_logic;
-signal data_phase : std_logic; -- data transport phase from split fifo to PC
-signal pad_phase_comb : std_logic;
-signal pad_phase : std_logic; -- padding phase
-signal calc_pad_comb : std_logic;
-signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE
-signal pad_data_comb : std_logic;
-signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value
-
-signal pc_sos_comb : std_logic;
-signal pc_sos : std_logic; -- start of data signal
-signal pc_eod_comb : std_logic;
-signal pc_eod : std_logic; -- end of data signal
-
-signal ce_rem_ctr_comb : std_logic;
-signal ce_rem_ctr : std_logic; -- count enable for remove counter
-signal remove_done_comb : std_logic;
-signal remove_done : std_logic; -- end of header stripping process
-signal read_done_comb : std_logic;
-signal read_done : std_logic; -- end of data phase (read phase from SF)
-
-signal pc_data : std_logic_vector(7 downto 0);
-signal pc_data_q : std_logic_vector(7 downto 0);
-signal pc_trig_nr : std_logic_vector(15 downto 0);
-signal pc_sub_size : std_logic_vector(17 downto 0);
-signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo
-signal padding_needed : std_logic;
-signal pc_wr_en_comb : std_logic;
-signal pc_wr_en_q : std_logic;
-signal pc_wr_en_qq : std_logic;
-signal pc_wr_en_qqq : std_logic;
-signal pc_eod_q : std_logic;
-
-signal debug : std_logic_vector(383 downto 0);
-
--- gk
-signal bank_select : std_logic_vector(3 downto 0);
-signal save_addr_comb : std_logic;
-signal save_addr : std_logic;
-signal addr_saved_comb : std_logic;
-signal addr_saved : std_logic;
-signal start_config : std_logic;
-signal config_done : std_logic;
-signal add_sub_state : std_logic;
-signal add_sub_state_comb : std_logic;
-signal add_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub : std_logic;
-signal load_sub_comb : std_logic;
-signal load_sub_done : std_logic;
-signal load_sub_done_comb : std_logic;
-signal load_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub_ctr_comb : std_logic;
-signal actual_message_size : std_logic_vector(31 downto 0);
-signal more_subevents : std_logic;
-signal trig_random : std_logic_vector(7 downto 0);
-signal readout_ctr : std_logic_vector(23 downto 0);
-signal readout_ctr_lock : std_logic;
-signal pc_trig_nr_q : std_logic_vector(31 downto 0);
-
--- gk 20.07.10
-signal inc_data_ctr : std_logic_vector(31 downto 0);
-signal dropped_sm_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_lr_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_ctr : std_logic_vector(31 downto 0);
--- gk 22.07.10
-signal headers_invalid : std_logic;
-signal headers_invalid_ctr : std_logic_vector(31 downto 0);
-signal cts_len_q : std_logic_vector(15 downto 0);
-signal cts_trg_q : std_logic_vector(15 downto 0);
-signal cts_rnd_q : std_logic_vector(15 downto 0);
-signal first_run_trg : std_logic_vector(15 downto 0);
-signal first_run_addr : std_logic_vector(15 downto 0);
-signal first_run_lock : std_logic;
-signal cts_addr : std_logic_vector(15 downto 0);
-signal cts_addr_q : std_logic_vector(15 downto 0);
-signal cts_addr_saved : std_logic;
-
--- gk 24.07.10
-signal save_eod : std_logic;
-signal save_eod_comb : std_logic;
-
-signal load_eod : std_logic;
-signal endpoint_addr : std_logic_vector(15 downto 0);
-signal endp_addr_lock : std_logic;
-
-signal saved_events_ctr : std_logic_vector(15 downto 0);
-signal loaded_events_ctr : std_logic_vector(15 downto 0);
-signal constr_events_ctr : std_logic_vector(31 downto 0);
-signal event_waiting : std_logic;
-
-signal drop_sub : std_logic;
-signal drop_sub_comb : std_logic;
-signal drop_event : std_logic;
-signal drop_event_comb : std_logic;
-signal drop_small : std_logic;
-signal drop_large : std_logic;
-signal drop_headers : std_logic;
-signal drop_small_comb : std_logic;
-signal drop_large_comb : std_logic;
-signal drop_headers_comb : std_logic;
-signal inc_trg_ctr : std_logic;
-signal inc_trg_ctr_comb : std_logic;
-
-signal invalid_hsize_ctr : std_logic_vector(15 downto 0);
-signal invalid_hsize_lock : std_logic;
-
-signal load_eod_q : std_logic;
-signal read_size_q : std_logic_vector(17 downto 0);
-
--- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked
-signal sf_real_wr_en : std_logic;
-
--- gk 01.10.10
-signal found_empty_evt : std_logic;
-signal found_empty_evt_comb : std_logic;
-signal found_empty_evt_ctr : std_logic_vector(31 downto 0);
-
--- gk 06.10.10
-signal message_size : std_logic_vector(31 downto 0);
-
--- gk 07.12.10
-signal prev_bank_select : std_logic_vector(3 downto 0);
-signal first_event : std_logic;
-
-signal reset_split_fifo : std_logic;
-
-signal input_data_ctr : std_logic_vector(31 downto 0);
-
-begin
-
-BANK_SELECT_OUT <= bank_select; -- gk 27.03.10
-START_CONFIG_OUT <= start_config; -- gk 27.03.10
-config_done <= CONFIG_DONE_IN; -- gk 29.03.10
-
--- CTS interface signals
-cts_error_pattern <= (others => '0'); -- FAKE
-
-cts_length <= x"0000"; -- length of data payload is always 0
-cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'
-
-cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';
-
-cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE)
- else '0';
-
--- Byte swapping... done here. TAKE CARE!
--- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes
--- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port.
--- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped
--- for GbE inside the packet constructor.
---
--- Long live the Endianess!
-
--- Sync all critical pathes
-THE_SYNC_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below
- sf_wr_en <= sf_wr_en_comb;
- ce_rem_ctr <= ce_rem_ctr_comb;
- sf_rd_en <= sf_rd_en_comb;
- fee_read <= fee_read_comb;
- read_done <= read_done_comb;
- pc_eod_q <= pc_eod;
- pc_wr_en_qqq <= pc_wr_en_qq;
- pc_wr_en_qq <= pc_wr_en_q;
- pc_wr_en_q <= pc_wr_en_comb;
- end if;
-end process THE_SYNC_PROC;
-
--- gk 27.03.10 data selector for sf to write the evt builder address on top of data
-SF_DATA_PROC : process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if (RESET = '1') then -- gk 31.05.10
- sf_data <= (others => '0');
- elsif( save_addr = '1' ) then
- sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address
- sf_data(15 downto 4) <= x"abc";
- -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then
- sf_data <= x"0001"; -- gk 11.06.10
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then
- sf_data <= x"5555"; -- gk 11.06.10
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then
- sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then
- sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
- else
- sf_data <= FEE_DATA_IN;
- end if;
- end if;
-end process SF_DATA_PROC;
-
--- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY
-fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
- else '0';
-
--- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY
-sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
- (save_addr = '1') or
- (add_sub_state = '1') -- gk 29.03.10 save the subsubevent
- else '0';
-
--- gk 06.08.10
-sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0';
-
--- gk 27.03.10 do not count evt builder address as saved ipu bytes
---ce_saved_ctr <= sf_wr_en;
-ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en;
-
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO
-saveMachineProc: process( CLK )
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saveCurrentState <= SIDLE;
- data_req <= '0';
- rst_saved_ctr <= '0';
- save_addr <= '0'; -- gk 27.03.10
- addr_saved <= '0'; -- gk 27.03.10
- add_sub_state <= '0'; -- gk 29.03.10
- save_eod <= '0'; -- gk 25.07.10
- else
- saveCurrentState <= saveNextState;
- data_req <= data_req_comb;
- rst_saved_ctr <= rst_saved_ctr_comb;
- save_addr <= save_addr_comb; -- gk 27.03.10
- addr_saved <= addr_saved_comb; -- gk 27.03.10
- add_sub_state <= add_sub_state_comb; -- gk 29.03.10
- save_eod <= save_eod_comb; -- gk 25.07.10
- end if;
- end if;
-end process saveMachineProc;
-
-saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, input_data_ctr, MAX_MESSAGE_SIZE_IN)
-begin
- saveNextState <= SIDLE;
- data_req_comb <= '0';
- rst_saved_ctr_comb <= '0';
- save_addr_comb <= '0'; -- gk 27.03.10
- addr_saved_comb <= '0'; -- gk 27.03.10
- add_sub_state_comb <= '0'; -- gk 29.03.10
- save_eod_comb <= '0'; -- gk 25.07.10
- case saveCurrentState is
- when SIDLE =>
- state <= x"0";
- if (CTS_START_READOUT_IN = '1') then
- saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10
- data_req_comb <= '1';
- rst_saved_ctr_comb <= '1';
- else
- saveNextState <= SIDLE;
- end if;
- -- gk 27.03.10
- when SAVE_EVT_ADDR =>
- state <= x"5";
- saveNextState <= WAIT_FOR_DATA;
- data_req_comb <= '1';
- save_addr_comb <= '1';
- when WAIT_FOR_DATA =>
- state <= x"1";
- if (FEE_BUSY_IN = '1') then
- saveNextState <= SAVE_DATA;
- data_req_comb <= '1';
- else
- saveNextState <= WAIT_FOR_DATA;
- data_req_comb <= '1';
- end if;
- addr_saved_comb <= '1'; -- gk 27.03.10
- when SAVE_DATA =>
- state <= x"2";
- if (FEE_BUSY_IN = '0') then
- saveNextState <= TERMINATE;
- else
- saveNextState <= SAVE_DATA;
- data_req_comb <= '1';
- end if;
- when TERMINATE =>
- state <= x"3";
- if (CTS_READ_IN = '1') then
- saveNextState <= SCLOSE;
- else
- saveNextState <= TERMINATE;
- end if;
- when SCLOSE =>
- state <= x"4";
- if (CTS_START_READOUT_IN = '0') then
- if (input_data_ctr > MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012
- saveNextState <= RESET_FIFO;
- else
- saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10
- end if;
- else
- saveNextState <= SCLOSE;
- end if;
- -- gk 06.11.2012
- when RESET_FIFO =>
- saveNextState <= SIDLE;
- state <= x"E";
- -- gk 29.03.10 new states during which the subsub bytes are saved
- when ADD_SUBSUB1 =>
- state <= x"6";
- saveNextState <= ADD_SUBSUB2;
- add_sub_state_comb <= '1';
- when ADD_SUBSUB2 =>
- state<= x"7";
- saveNextState <= ADD_SUBSUB3;
- add_sub_state_comb <= '1';
- save_eod_comb <= '1';
- when ADD_SUBSUB3 =>
- state<= x"8";
- saveNextState <= ADD_SUBSUB4;
- add_sub_state_comb <= '1';
- when ADD_SUBSUB4 =>
- state<= x"9";
- saveNextState <= SIDLE;
- add_sub_state_comb <= '1';
- when others =>
- state <= x"f";
- saveNextState <= SIDLE;
- end case;
-end process saveMachine;
-
--- gk 06.11.2012
-INPUT_DATA_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1' or rst_saved_ctr = '1') then
- input_data_ctr <= (others => '0');
- elsif (saveCurrentState = SAVE_DATA and sf_real_wr_en = '1') then
- input_data_ctr(31 downto 1) <= input_data_ctr(31 downto 1) + x"1";
- end if;
- end if;
-end process INPUT_DATA_CTR_PROC;
-
--- gk 29.03.10
-ADD_SUB_CTR_PROC : process( CLK )
-begin
- if( rising_edge( CLK ) ) then
- if( (RESET = '1') or (rst_saved_ctr = '1') ) then
- add_sub_ctr <= (others => '0');
- elsif( add_sub_state = '1' ) then
- add_sub_ctr <= add_sub_ctr + 1;
- end if;
- end if;
-end process ADD_SUB_CTR_PROC;
-
---********
--- SAVE INCOMING EVENT HEADERS
---********
-
--- Counter for header word storage
-THE_CTS_SAVED_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- saved_ctr <= (others => '0');
- elsif( ce_saved_ctr = '1' ) then
- saved_ctr <= saved_ctr + 1;
- end if;
- end if;
-end process THE_CTS_SAVED_CTR;
-
--- save triggerRnd from incoming data for cts response
-CTS_RND_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_rnd <= (others => '0');
- cts_rnd_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then
- cts_rnd <= sf_data;
- cts_rnd_saved <= '1';
- end if;
- end if;
-end process CTS_RND_PROC;
-
--- save triggerNr from incoming data for cts response
-CTS_TRG_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_trg <= (others => '0');
- cts_trg_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then
- cts_trg <= sf_data;
- cts_trg_saved <= '1';
- end if;
- end if;
-end process CTS_TRG_PROC;
-
--- save size from incoming data for cts response (future) and to get rid of padding
-CTS_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_len <= (others => '0');
- cts_len_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then
- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words
- cts_len(0) <= '0';
- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then
- cts_len <= cts_len + x"4";
- cts_len_saved <= '1';
- end if;
- end if;
-end process CTS_SIZE_PROC;
-
--- gk 22.07.10
-CTS_ADDR_PROC : process(CLK)
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_addr <= (others => '0');
- cts_addr_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then
- cts_addr <= sf_data;
- cts_addr_saved <= '1';
- end if;
- end if;
-end process CTS_ADDR_PROC;
-
---******
--- SAVE FIRST EVENT HEADER VALUES
---******
-
--- gk 22.07.10
-FIRST_RUN_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- first_run_trg <= (others => '0');
- first_run_addr <= (others => '0');
- first_run_lock <= '0';
- elsif (first_run_lock = '0') and (cts_addr_saved = '1') then
- first_run_trg <= cts_trg;
- first_run_addr <= cts_addr;
- first_run_lock <= '1';
- -- important: value saved by saveMachine but incremented by loadMachine
- elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then
- first_run_trg <= first_run_trg + x"1";
- end if;
- end if;
-end process FIRST_RUN_PROC;
-
--- gk 25.07.10
-SAVED_EVT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saved_events_ctr <= (others => '0');
- elsif (save_eod = '1') and (input_data_ctr < MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012
- saved_events_ctr <= saved_events_ctr + x"1";
- end if;
- end if;
-end process SAVED_EVT_CTR_PROC;
-
-
--- gk 20.07.10
---INC_DATA_CTR_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (rst_saved_ctr = '1') then
--- inc_data_ctr <= (others => '0');
--- elsif (sf_wr_en = '1') and (data_req = '1') then
--- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1";
--- end if;
--- end if;
---end process INC_DATA_CTR_proc;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Split FIFO
-THE_SPLIT_FIFO: fifo_32kx16x8_mb2
-port map(
- -- Byte swapping for correct byte order on readout side of FIFO
- Data(7 downto 0) => sf_data(15 downto 8),
- Data(8) => '0',
- Data(16 downto 9) => sf_data(7 downto 0),
- Data(17) => save_eod,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en,
- RdEn => sf_rd_en,
- Reset => reset_split_fifo, --RESET, -- gk 06.11.2012
- RPReset => reset_split_fifo, --RESET, -- gk 06.11.2012
- AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead
- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751
- Q(7 downto 0) => pc_data,
- Q(8) => load_eod,
- WCNT => sf_wcnt,
- RCNT => sf_rcnt,
- Empty => sf_empty,
- AlmostEmpty => sf_aempty,
- Full => sf_full,
- AlmostFull => sf_afull
-);
-
-reset_split_fifo <= '1' when (saveCurrentState = RESET_FIFO or RESET = '1') else '0';
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- gk 25.07.10
-EVENT_WAITING_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- event_waiting <= '0';
- elsif (loaded_events_ctr /= saved_events_ctr) then
- event_waiting <= '1';
- else
- event_waiting <= '0';
- end if;
- end if;
-end process EVENT_WAITING_PROC;
-
--- write signal for PC data
-pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or
- (pad_phase = '1') or
- ((load_sub = '1') and (sf_rd_en = '1')) or
- ((drop_sub = '1') and (sf_rd_en = '1')) or
- ((drop_event = '1') and (sf_rd_en = '1'))
- else '0';
-
-sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or
- --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or
- ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10
- ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10
- ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or
- ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') )
- else '0';
-
-ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') )
- else '0';
-
--- FIFO data delay process (also forces padding bytes to known value)
-THE_DATA_DELAY_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( pad_data = '1' ) then
- pc_data_q <= x"aa"; -- padding for 64bit
- -- gk 21.07.10
- -- set the error flag if a broken packet is sent
- elsif (drop_sub = '1') and (load_sub_ctr = x"3") then
- pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0);
- else
- pc_data_q <= pc_data;
- end if;
- end if;
-end process THE_DATA_DELAY_PROC;
-
--- Statemachine for reading the data payload from the SPLIT_FIFO and feeding
--- it into the packet constructor
-loadMachineProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- loadCurrentState <= LIDLE;
- rst_rem_ctr <= '0';
- rem_phase <= '0';
- calc_pad <= '0';
- data_phase <= '0';
- pad_phase <= '0';
- pc_sos <= '0';
- pc_eod <= '0';
- rst_regs <= '0';
- pad_data <= '0';
- load_sub <= '0'; -- gk 30.03.10
- drop_sub <= '0'; -- gk 25.07.10
- drop_event <= '0'; -- gk 25.07.10
- drop_small <= '0'; -- gk 25.07.10
- drop_large <= '0'; -- gk 25.07.10
- drop_headers <= '0'; -- gk 25.07.10
- inc_trg_ctr <= '0'; -- gk 26.07.10
- found_empty_evt <= '0'; -- gk 01.10.10
- else
- loadCurrentState <= loadNextState;
- rst_rem_ctr <= rst_rem_ctr_comb;
- rem_phase <= rem_phase_comb;
- calc_pad <= calc_pad_comb;
- data_phase <= data_phase_comb;
- pad_phase <= pad_phase_comb;
- pc_sos <= pc_sos_comb;
- pc_eod <= pc_eod_comb;
- rst_regs <= rst_regs_comb;
- pad_data <= pad_data_comb;
- load_sub <= load_sub_comb; -- gk 30.03.1
- drop_sub <= drop_sub_comb; -- gk 25.07.10
- drop_event <= drop_event_comb; -- gk 25.07.10
- drop_small <= drop_small_comb; -- gk 25.07.10
- drop_large <= drop_large_comb; -- gk 25.07.10
- drop_headers <= drop_headers_comb; -- gk 25.07.10
- inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10
- found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10
- end if;
- end if;
-end process loadMachineProc;
-
-loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed,
- PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN,
- MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr,
- first_run_addr, load_eod, event_waiting, MULT_EVT_ENABLE_IN, message_size, DATA_GBE_ENABLE_IN, first_event,
- prev_bank_select, bank_select)
-begin
- loadNextState <= LIDLE;
- rst_rem_ctr_comb <= '0';
- rem_phase_comb <= '0';
- calc_pad_comb <= '0';
- data_phase_comb <= '0';
- pad_phase_comb <= '0';
- pc_sos_comb <= '0';
- pc_eod_comb <= '0';
- rst_regs_comb <= '0';
- pad_data_comb <= '0';
- load_sub_comb <= '0'; -- gk 30.03.10
- drop_sub_comb <= '0'; -- gk 25.07.10
- drop_event_comb <= '0'; -- gk 25.07.10
- drop_small_comb <= '0'; -- gk 25.07.10
- drop_large_comb <= '0'; -- gk 25.07.10
- drop_headers_comb <= '0'; -- gk 25.07.10
- inc_trg_ctr_comb <= '0'; -- gk 26.07.10
- found_empty_evt_comb <= '0'; -- gk 01.10.10
- case loadCurrentState is
- when LIDLE =>
- state2 <= x"0";
- -- gk 23.07.10
- if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 -- and (PC_READY_IN = '1')
- loadNextState <= INIT;
- rst_rem_ctr_comb <= '1';
- rst_regs_comb <= '1';
- else
- loadNextState <= LIDLE;
- end if;
- when INIT =>
- state2 <= x"1";
- loadNextState <= REMOVE;
- rem_phase_comb <= '1';
- when REMOVE =>
- state2 <= x"2";
- if( remove_done = '1' ) then
- -- gk 06.10.10
- if (MULT_EVT_ENABLE_IN = '1') then
- if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then
- --loadNextState <= WAIT_TO_REMOVE;
- -- gk 07.12.10
- if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet
- loadNextState <= WAIT_PC;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
-
- else
- loadNextState <= WAIT_PC;
- end if;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
- inc_trg_ctr_comb <= '1';
- else
- loadNextState <= REMOVE;
- rem_phase_comb <= '1';
- end if;
- when WAIT_TO_REMOVE =>
- if (rem_ctr = x"a") then
- loadNextState <= DECIDE;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
- when DECIDE =>
- if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_large_comb <= '1';
- elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10
- loadNextState <= CALCA;
- found_empty_evt_comb <= '1';
- elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_small_comb <= '1';
- elsif (pc_trig_nr + x"1" /= first_run_trg) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_headers_comb <= '1';
- elsif (endpoint_addr /= first_run_addr) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_headers_comb <= '1';
- else
- loadNextState <= CALCA;
- end if;
- calc_pad_comb <= '1';
- when CALCA =>
- state2 <= x"3";
- loadNextState <= CALCB;
- pc_sos_comb <= '1';
- when CALCB =>
- -- we need a branch in case of length "0"!!!!
- state2 <= x"4";
- loadNextState <= LOAD;
- data_phase_comb <= '1';
- when LOAD =>
- state2 <= x"5";
- if (load_eod = '1') then
- loadNextState <= LOAD_SUBSUB;
- else
- loadNextState <= LOAD;
- data_phase_comb <= '1';
- end if;
- -- gk 31.03.10
- when LOAD_SUBSUB =>
- state2 <= x"d";
- if( load_sub_done = '1' ) then
- if( padding_needed = '0' ) then
- loadNextState <= CALCC;
- else
- loadNextState <= PAD0;
- pad_phase_comb <= '1';
- end if;
- else
- loadNextState <= LOAD_SUBSUB;
- load_sub_comb <= '1';
- end if;
- when PAD0 =>
- state2 <= x"6";
- loadNextState <= PAD1;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD1 =>
- state2 <= x"7";
- loadNextState <= PAD2;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD2 =>
- state2 <= x"8";
- loadNextState <= PAD3;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD3 =>
- state2 <= x"9";
- loadNextState <= CALCC;
- pad_data_comb <= '1';
- when CALCC =>
- state2 <= x"a";
- if (MULT_EVT_ENABLE_IN = '1') then
- loadNextState <= LIDLE;
- else
- loadNextState <= CLOSE;
- end if;
- pc_eod_comb <= '1';
- when CLOSE =>
- state2 <= x"b";
- loadNextState <= WAIT_PC;
- --rst_regs_comb <= '1'; -- gk 07.10.10
- when WAIT_PC =>
- state2 <= x"c";
- if( PC_READY_IN = '1' ) then
- -- gk 06.10.10
- if (MULT_EVT_ENABLE_IN = '1') then
- loadNextState <= WAIT_TO_REMOVE;
- else
- loadNextState <= LIDLE;
- end if;
- else
- loadNextState <= WAIT_PC;
- end if;
- when PAUSE_BEFORE_DROP1 =>
- loadNextState <= PAUSE_BEFORE_DROP2;
- pc_sos_comb <= '1';
- when PAUSE_BEFORE_DROP2 =>
- loadNextState <= DROP;
- drop_event_comb <= '1';
- -- gk 23.07.10
- when DROP =>
- state2 <= x"e";
- -- when data is dropped the eod marker stands as its end
- if (load_eod = '1') then
- loadNextState <= DROP_SUBSUB;
- else
- loadNextState <= DROP;
- drop_event_comb <= '1';
- end if;
- -- gk 25.07.10
- when DROP_SUBSUB =>
- if (load_sub_done = '1') then
- if( padding_needed = '0' ) then
- loadNextState <= CALCC;
- else
- loadNextState <= PAD0;
- pad_phase_comb <= '1';
- end if;
- else
- loadNextState <= DROP_SUBSUB;
- drop_sub_comb <= '1';
- end if;
- when others =>
- state2 <= x"f";
- loadNextState <= LIDLE;
- end case;
-end process loadMachine;
-
--- gk 07.10.10
-PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0';
-
--- gk 25.07.10
---INVALID_STATS_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- dropped_lr_events_ctr <= (others => '0');
--- dropped_sm_events_ctr <= (others => '0');
--- headers_invalid_ctr <= (others => '0');
--- dropped_ctr <= (others => '0');
--- invalid_hsize_ctr <= (others => '0');
--- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10
--- elsif (rst_regs = '1') then
--- invalid_hsize_lock <= '0';
--- elsif (drop_small = '1') then
--- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (drop_large = '1') then
--- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (drop_headers = '1') then
--- headers_invalid_ctr <= headers_invalid_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ??
--- invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
--- invalid_hsize_lock <= '1';
--- -- gk 01.10.10
--- elsif (found_empty_evt = '1') then
--- found_empty_evt_ctr <= found_empty_evt_ctr + x"1";
--- end if;
--- end if;
---end process INVALID_STATS_PROC;
-
--- gk 05.08.10
-INVALID_H_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- load_eod_q <= load_eod;
- read_size_q <= read_size;
- end if;
-end process INVALID_H_PROC;
-
--- gk 26.04.10
-READOUT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then
- readout_ctr <= READOUT_CTR_IN;
- readout_ctr_lock <= '0';
- elsif (pc_sos = '1') then
- readout_ctr <= readout_ctr + x"1";
- end if;
- end if;
-end process READOUT_CTR_PROC;
-
---******
--- SELECTION OF EVENT BUILDER
---******
-
--- gk 27.03.10
-bank_select_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- -- gk 29.03.10
- if( (RESET = '1') or (rst_regs = '1') ) then
- bank_select <= "0000";
- -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
- bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
- end if;
- end if;
-end process bank_select_proc;
-
--- gk 07.12.10
-first_event_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = WAIT_PC) then
- first_event <= '1';
- elsif (remove_done = '1') then
- first_event <= '0';
- end if;
- end if;
-end process first_event_proc;
-
--- gk 07.12.10
-prev_bank_proc : process(CLK)
-begin
- if (RESET = '1') or (loadCurrentState = WAIT_PC) then
- prev_bank_select <= "0000";
- elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then
- prev_bank_select <= bank_select;
- end if;
-end process prev_bank_proc;
-
-
--- gk 29.03.10
-start_config_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then
- start_config <= '0';
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1') ) then -- gk 01.06.10
- start_config <= '1';
- end if;
- end if;
-end process start_config_proc;
-
-
---******
--- LOAD SUBSUBEVENT
---******
-
--- gk 30.03.10
-load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') )
- else '0';
-
--- gk 30.03.10
-LOAD_SUB_CTR_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
- load_sub_ctr <= (others => '0');
- elsif( (load_sub_ctr_comb = '1') ) then
- load_sub_ctr <= load_sub_ctr + 1;
- end if;
- end if;
-end process LOAD_SUB_CTR_PROC;
-
--- gk 30.03.10
--- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or
--- ((load_sub_ctr = x"4") and (drop_sub = '1'))
--- else '0';
-load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0';
-
--- gk 30.03.10
-LOAD_SUB_DONE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
- load_sub_done <= '0';
- else
- load_sub_done <= load_sub_done_comb;
- end if;
- end if;
-end process LOAD_SUB_DONE_PROC;
-
---******
--- EXTRACT EVENT HEADERS FROM SPLITFIFO
---******
-
--- Counter for stripping the unneeded parts of the data stream, and saving the important parts
-THE_REMOVE_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
- rem_ctr <= (others => '0');
- elsif( (ce_rem_ctr = '1') ) then
- rem_ctr <= rem_ctr + 1;
- end if;
- end if;
-end process THE_REMOVE_CTR;
-
-remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address
-
-THE_REM_DONE_SYNC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
- remove_done <= '0';
- else
- remove_done <= remove_done_comb;
- end if;
- end if;
-end process THE_REM_DONE_SYNC;
-
--- gk 26.04.10
-TRIG_RANDOM_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (rst_regs = '1')) then
- trig_random <= (others => '0');
- elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then
- trig_random <= pc_data;
- end if;
- end if;
-end process TRIG_RANDOM_PROC;
-
--- extract the trigger number from splitfifo data
-THE_TRG_NR_PROC: process( CLK )
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- pc_trig_nr <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10
- pc_trig_nr(7 downto 0) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10
- pc_trig_nr(15 downto 8) <= pc_data;
- end if;
- end if;
-end process THE_TRG_NR_PROC;
-
--- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,
--- and in case of padding needed increase it accordingly
-THE_SUB_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- pc_sub_size <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
- pc_sub_size(9 downto 2) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
- pc_sub_size(17 downto 10) <= pc_data;
- -- gk 20.07.10
- -- gk 30.03.10 bug fixed in the way that is written below
- -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save
- elsif( (calc_pad = '1') and (padding_needed = '1') ) then
- pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!!
- elsif( (calc_pad = '1') and (padding_needed = '0') ) then
- pc_sub_size <= pc_sub_size + x"8";
- end if;
- end if;
-end process THE_SUB_SIZE_PROC;
-
--- gk 06.10.10
-MESSAGE_SIZE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
--- if (RESET = '1') then
--- message_size <= (others => '0');
--- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
--- message_size <= (others => '0');
--- elsif (pc_sos = '1') then
--- message_size <= message_size + pc_sub_size;
--- end if;
- if (RESET = '1') then
- message_size <= x"0000_0028";
- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
- message_size <= x"0000_0028";
- elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then
- message_size <= x"0000_0028";
- elsif (pc_sos = '1') then
- message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers
- end if;
- end if;
-end process MESSAGE_SIZE_PROC;
-
-
--- gk 25.07.10
-ENDP_ADDRESS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (rst_regs = '1') then
- endpoint_addr <= (others => '0');
- endp_addr_lock <= '0';
- elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then
- endpoint_addr(7 downto 0) <= pc_data;
- endp_addr_lock <= '1';
- elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then
- endpoint_addr(15 downto 8) <= pc_data;
- endp_addr_lock <= '0';
- end if;
- end if;
-end process ENDP_ADDRESS_PROC;
-
-
-
--- check for padding
-THE_PADDING_NEEDED_PROC: process( CLK )
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- padding_needed <= '0';
- elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then
- padding_needed <= '1';
- elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then
- padding_needed <= '0';
- end if;
- end if;
-end process THE_PADDING_NEEDED_PROC;
-
--- number of bytes to read from split fifo
-THE_READ_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then
- read_size <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
- read_size(9 downto 2) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
- read_size(17 downto 10) <= pc_data;
- elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then
- read_size <= read_size - 1;
- -- gk 25.07.10
- elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then
- read_size <= read_size - 1;
- end if;
- end if;
-end process THE_READ_SIZE_PROC;
-
-read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2"
-
---******
--- EVENTS COUNTERS
---******
-
--- gk 25.07.10
-LOADED_EVT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- loaded_events_ctr <= (others => '0');
- elsif (remove_done = '1') then
- loaded_events_ctr <= loaded_events_ctr + x"1";
- end if;
- end if;
-end process LOADED_EVT_CTR_PROC;
-
--- gk 25.07.10
-CONSTR_EVENTS_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- constr_events_ctr <= (others => '0');
- elsif (pc_eod = '1') then
- constr_events_ctr <= constr_events_ctr + x"1";
- end if;
- end if;
-end process CONSTR_EVENTS_CTR_PROC;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Debug signals
---debug(0) <= sf_full;
---debug(1) <= sf_empty;
---debug(2) <= sf_afull;
---debug(3) <= sf_aempty;
---
---debug(7 downto 4) <= state2;
---
---debug(11 downto 8) <= state;
---
---dbg_bs_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(15 downto 12) <= (others => '0');
--- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
--- debug(15 downto 12) <= bank_select;
--- end if;
--- end if;
---end process dbg_bs_proc;
---
---debug(16) <= config_done;
---debug(17) <= '0'; --remove_done;
---debug(18) <= read_done;
---debug(19) <= padding_needed;
---
---debug(20) <= load_sub_done;
---
---dbg_cts_inf_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(39 downto 32) <= (others => '0');
--- elsif ( save_addr = '1' ) then
--- debug(39 downto 32) <= CTS_INFORMATION_IN;
--- end if;
--- end if;
---end process dbg_cts_inf_proc;
---
---debug(47 downto 40) <= (others => '0');
---
---
---debug(63 downto 48) <= actual_message_size(15 downto 0);
---
---dbg_pc_sub_size_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(81 downto 64) <= (others => '0');
--- elsif (loadCurrentState = DECIDE) then
--- debug(81 downto 64) <= pc_sub_size;
--- end if;
--- end if;
---end process dbg_pc_sub_size_proc;
---
---dbg_empty_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (rst_regs = '1') then
--- debug(84 downto 82) <= (others => '0');
--- elsif (read_size = 2) then
--- debug(82) <= sf_empty;
--- elsif (read_size = 1) then
--- debug(83) <= sf_empty;
--- elsif (read_size = 0) then
--- debug(84) <= sf_empty;
--- end if;
--- end if;
---end process dbg_empty_proc;
---
---debug(95 downto 85) <= (others => '0');
---
---dbg_inc_ctr_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(127 downto 96) <= (others => '1');
--- elsif (saveCurrentState = SCLOSE) then
--- debug(127 downto 96) <= inc_data_ctr;
--- end if;
--- end if;
---end process dbg_inc_ctr_proc;
---
---debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0);
---debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0);
---
---debug(175 downto 160) <= headers_invalid_ctr(15 downto 0);
---debug(191 downto 176) <= (others => '0');
---
---dbg_cts_q_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- cts_len_q <= (others => '0');
--- cts_rnd_q <= (others => '0');
--- cts_trg_q <= (others => '0');
--- cts_addr_q <= (others => '0');
--- elsif (cts_len_saved = '1') then
--- cts_len_q <= cts_len(16 downto 1);
--- cts_addr_q <= cts_addr;
--- cts_rnd_q <= cts_rnd;
--- cts_trg_q <= cts_trg;
--- end if;
--- end if;
---end process dbg_cts_q_proc;
-
---debug(207 downto 192) <= cts_trg_q;
---debug(223 downto 208) <= cts_rnd_q;
---debug(239 downto 224) <= cts_addr_q;
---debug(255 downto 240) <= cts_len_q;
---debug(271 downto 256) <= first_run_trg;
---debug(287 downto 272) <= first_run_addr;
---
---debug(303 downto 288) <= saved_events_ctr;
---debug(319 downto 304) <= loaded_events_ctr;
---
---debug(335 downto 320) <= constr_events_ctr(15 downto 0);
---debug(351 downto 336) <= dropped_ctr(15 downto 0);
---
---debug(367 downto 352) <= invalid_hsize_ctr;
---debug(383 downto 368) <= (others => '0');
---
---MONITOR_OUT(31 downto 0) <= constr_events_ctr;
---MONITOR_OUT(63 downto 32) <= dropped_ctr;
---MONITOR_OUT(95 downto 64) <= headers_invalid_ctr;
---MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr;
---MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
---MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000";
---MONITOR_OUT(191 downto 164) <= (others => '0');
---MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10
-
--- Outputs
-FEE_READ_OUT <= fee_read;
-CTS_ERROR_PATTERN_OUT <= cts_error_pattern;
-CTS_DATA_OUT <= cts_data;
-CTS_DATAREADY_OUT <= cts_dataready;
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
-CTS_LENGTH_OUT <= cts_length;
-
-PC_SOS_OUT <= pc_sos;
-PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1'))
- or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1'))
- -- gk 07.12.10
- or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1'))
- else '0'; -- gk 07.10.10
-PC_DATA_OUT <= pc_data_q;
-PC_WR_EN_OUT <= pc_wr_en_qq;
-
-PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random;
-
-PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size;
-PC_PADDING_OUT <= padding_needed;
-
---DEBUG_OUT <= debug;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-
-entity trb_net16_ipu2gbe is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
- MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- -- PacketConstructor interface
- ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOD_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_PADDING_OUT : out std_logic;
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
-);
-end entity;
-
-architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is
-
--- -- Placer Directives
--- attribute HGROUP : string;
--- -- for whole architecture
--- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe_group";
-
-component fifo_32kx16x8_mb2
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(8 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0);
- Empty : out std_logic;
- AlmostEmpty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
-);
-end component;
-
-type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE);
-signal saveCurrentState, saveNextState : saveStates;
-signal state : std_logic_vector(3 downto 0);
-signal data_req_comb : std_logic;
-signal data_req : std_logic; -- request data signal, will be used for fee_read generation
-signal rst_saved_ctr_comb : std_logic;
-signal rst_saved_ctr : std_logic;
-
-signal fee_read_comb : std_logic;
-signal fee_read : std_logic; -- fee_read signal
-signal saved_ctr : std_logic_vector(16 downto 0);
-signal ce_saved_ctr : std_logic;
-
--- header data
-signal cts_rnd : std_logic_vector(15 downto 0);
-signal cts_rnd_saved : std_logic;
-signal cts_trg : std_logic_vector(15 downto 0);
-signal cts_trg_saved : std_logic;
-signal cts_len : std_logic_vector(16 downto 0);
-signal cts_len_saved : std_logic;
-
--- CTS interface
-signal cts_error_pattern : std_logic_vector(31 downto 0);
-signal cts_length : std_logic_vector(15 downto 0);
-signal cts_readout_finished : std_logic;
-signal cts_dataready : std_logic;
-signal cts_data : std_logic_vector(31 downto 0);
-
--- Split FIFO signals
-signal sf_data : std_logic_vector(15 downto 0);
-signal sf_wr_en_comb : std_logic;
-signal sf_wr_en : std_logic; -- write signal for FIFO
-signal sf_rd_en_comb : std_logic;
-signal sf_rd_en : std_logic; -- read signal for FIFO
-signal sf_wcnt : std_logic_vector(15 downto 0);
-signal sf_rcnt : std_logic_vector(16 downto 0);
-signal sf_empty : std_logic;
-signal sf_aempty : std_logic;
-signal sf_full : std_logic;
-signal sf_afull : std_logic;
-
--------------------------------------------------------------------
-type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2);
-signal loadCurrentState, loadNextState : loadStates;
-signal state2 : std_logic_vector(3 downto 0);
-
-signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data
-signal rst_rem_ctr_comb : std_logic;
-signal rst_rem_ctr : std_logic; -- reset the remove counter
-signal rst_regs_comb : std_logic;
-signal rst_regs : std_logic; -- reset storage registers
-signal rem_phase_comb : std_logic;
-signal rem_phase : std_logic; -- header remove phase
-signal data_phase_comb : std_logic;
-signal data_phase : std_logic; -- data transport phase from split fifo to PC
-signal pad_phase_comb : std_logic;
-signal pad_phase : std_logic; -- padding phase
-signal calc_pad_comb : std_logic;
-signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE
-signal pad_data_comb : std_logic;
-signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value
-
-signal pc_sos_comb : std_logic;
-signal pc_sos : std_logic; -- start of data signal
-signal pc_eod_comb : std_logic;
-signal pc_eod : std_logic; -- end of data signal
-
-signal ce_rem_ctr_comb : std_logic;
-signal ce_rem_ctr : std_logic; -- count enable for remove counter
-signal remove_done_comb : std_logic;
-signal remove_done : std_logic; -- end of header stripping process
-signal read_done_comb : std_logic;
-signal read_done : std_logic; -- end of data phase (read phase from SF)
-
-signal pc_data : std_logic_vector(7 downto 0);
-signal pc_data_q : std_logic_vector(7 downto 0);
-signal pc_trig_nr : std_logic_vector(15 downto 0);
-signal pc_sub_size : std_logic_vector(17 downto 0);
-signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo
-signal padding_needed : std_logic;
-signal pc_wr_en_comb : std_logic;
-signal pc_wr_en_q : std_logic;
-signal pc_wr_en_qq : std_logic;
-signal pc_wr_en_qqq : std_logic;
-signal pc_eod_q : std_logic;
-
-signal debug : std_logic_vector(383 downto 0);
-
--- gk
-signal bank_select : std_logic_vector(3 downto 0);
-signal save_addr_comb : std_logic;
-signal save_addr : std_logic;
-signal addr_saved_comb : std_logic;
-signal addr_saved : std_logic;
-signal start_config : std_logic;
-signal config_done : std_logic;
-signal add_sub_state : std_logic;
-signal add_sub_state_comb : std_logic;
-signal add_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub : std_logic;
-signal load_sub_comb : std_logic;
-signal load_sub_done : std_logic;
-signal load_sub_done_comb : std_logic;
-signal load_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub_ctr_comb : std_logic;
-signal actual_message_size : std_logic_vector(31 downto 0);
-signal more_subevents : std_logic;
-signal trig_random : std_logic_vector(7 downto 0);
-signal readout_ctr : std_logic_vector(23 downto 0);
-signal readout_ctr_lock : std_logic;
-signal pc_trig_nr_q : std_logic_vector(31 downto 0);
-
--- gk 20.07.10
-signal inc_data_ctr : std_logic_vector(31 downto 0);
-signal dropped_sm_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_lr_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_ctr : std_logic_vector(31 downto 0);
--- gk 22.07.10
-signal headers_invalid : std_logic;
-signal headers_invalid_ctr : std_logic_vector(31 downto 0);
-signal cts_len_q : std_logic_vector(15 downto 0);
-signal cts_trg_q : std_logic_vector(15 downto 0);
-signal cts_rnd_q : std_logic_vector(15 downto 0);
-signal first_run_trg : std_logic_vector(15 downto 0);
-signal first_run_addr : std_logic_vector(15 downto 0);
-signal first_run_lock : std_logic;
-signal cts_addr : std_logic_vector(15 downto 0);
-signal cts_addr_q : std_logic_vector(15 downto 0);
-signal cts_addr_saved : std_logic;
-
--- gk 24.07.10
-signal save_eod : std_logic;
-signal save_eod_comb : std_logic;
-
-signal load_eod : std_logic;
-signal endpoint_addr : std_logic_vector(15 downto 0);
-signal endp_addr_lock : std_logic;
-
-signal saved_events_ctr : std_logic_vector(15 downto 0);
-signal loaded_events_ctr : std_logic_vector(15 downto 0);
-signal constr_events_ctr : std_logic_vector(31 downto 0);
-signal event_waiting : std_logic;
-
-signal drop_sub : std_logic;
-signal drop_sub_comb : std_logic;
-signal drop_event : std_logic;
-signal drop_event_comb : std_logic;
-signal drop_small : std_logic;
-signal drop_large : std_logic;
-signal drop_headers : std_logic;
-signal drop_small_comb : std_logic;
-signal drop_large_comb : std_logic;
-signal drop_headers_comb : std_logic;
-signal inc_trg_ctr : std_logic;
-signal inc_trg_ctr_comb : std_logic;
-
-signal invalid_hsize_ctr : std_logic_vector(15 downto 0);
-signal invalid_hsize_lock : std_logic;
-
-signal load_eod_q : std_logic;
-signal read_size_q : std_logic_vector(17 downto 0);
-
--- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked
-signal sf_real_wr_en : std_logic;
-
--- gk 01.10.10
-signal found_empty_evt : std_logic;
-signal found_empty_evt_comb : std_logic;
-signal found_empty_evt_ctr : std_logic_vector(31 downto 0);
-
-begin
-
-BANK_SELECT_OUT <= bank_select; -- gk 27.03.10
-START_CONFIG_OUT <= start_config; -- gk 27.03.10
-config_done <= CONFIG_DONE_IN; -- gk 29.03.10
-
--- CTS interface signals
-cts_error_pattern <= (others => '0'); -- FAKE
-
-cts_length <= x"0000"; -- length of data payload is always 0
-cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'
-
-cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';
-
-cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE)
- else '0';
-
--- Byte swapping... done here. TAKE CARE!
--- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes
--- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port.
--- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped
--- for GbE inside the packet constructor.
---
--- Long live the Endianess!
-
--- Sync all critical pathes
-THE_SYNC_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below
- sf_wr_en <= sf_wr_en_comb;
- ce_rem_ctr <= ce_rem_ctr_comb;
- sf_rd_en <= sf_rd_en_comb;
- fee_read <= fee_read_comb;
- read_done <= read_done_comb;
- pc_eod_q <= pc_eod;
- pc_wr_en_qqq <= pc_wr_en_qq;
- pc_wr_en_qq <= pc_wr_en_q;
- pc_wr_en_q <= pc_wr_en_comb;
- end if;
-end process THE_SYNC_PROC;
-
--- gk 27.03.10 data selector for sf to write the evt builder address on top of data
-SF_DATA_PROC : process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if (RESET = '1') then -- gk 31.05.10
- sf_data <= (others => '0');
- elsif( save_addr = '1' ) then
- sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address
- sf_data(15 downto 4) <= x"abc";
- -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then
- sf_data <= x"0001"; -- gk 11.06.10
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then
- sf_data <= x"5555"; -- gk 11.06.10
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then
- sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then
- sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
- else
- sf_data <= FEE_DATA_IN;
- end if;
- end if;
-end process SF_DATA_PROC;
-
--- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY
-fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
- else '0';
-
--- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY
-sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
- (save_addr = '1') or
- (add_sub_state = '1') -- gk 29.03.10 save the subsubevent
- else '0';
-
--- gk 06.08.10
-sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0';
-
--- gk 27.03.10 do not count evt builder address as saved ipu bytes
---ce_saved_ctr <= sf_wr_en;
-ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en;
-
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO
-saveMachineProc: process( CLK )
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saveCurrentState <= SIDLE;
- data_req <= '0';
- rst_saved_ctr <= '0';
- save_addr <= '0'; -- gk 27.03.10
- addr_saved <= '0'; -- gk 27.03.10
- add_sub_state <= '0'; -- gk 29.03.10
- save_eod <= '0'; -- gk 25.07.10
- else
- saveCurrentState <= saveNextState;
- data_req <= data_req_comb;
- rst_saved_ctr <= rst_saved_ctr_comb;
- save_addr <= save_addr_comb; -- gk 27.03.10
- addr_saved <= addr_saved_comb; -- gk 27.03.10
- add_sub_state <= add_sub_state_comb; -- gk 29.03.10
- save_eod <= save_eod_comb; -- gk 25.07.10
- end if;
- end if;
-end process saveMachineProc;
-
-saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN)
-begin
- saveNextState <= SIDLE;
- data_req_comb <= '0';
- rst_saved_ctr_comb <= '0';
- save_addr_comb <= '0'; -- gk 27.03.10
- addr_saved_comb <= '0'; -- gk 27.03.10
- add_sub_state_comb <= '0'; -- gk 29.03.10
- save_eod_comb <= '0'; -- gk 25.07.10
- case saveCurrentState is
- when SIDLE =>
- state <= x"0";
- if (CTS_START_READOUT_IN = '1') then
- saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10
- data_req_comb <= '1';
- rst_saved_ctr_comb <= '1';
- else
- saveNextState <= SIDLE;
- end if;
- -- gk 27.03.10
- when SAVE_EVT_ADDR =>
- state <= x"5";
- saveNextState <= WAIT_FOR_DATA;
- data_req_comb <= '1';
- save_addr_comb <= '1';
- when WAIT_FOR_DATA =>
- state <= x"1";
- if (FEE_BUSY_IN = '1') then
- saveNextState <= SAVE_DATA;
- data_req_comb <= '1';
- else
- saveNextState <= WAIT_FOR_DATA;
- data_req_comb <= '1';
- end if;
- addr_saved_comb <= '1'; -- gk 27.03.10
- when SAVE_DATA =>
- state <= x"2";
- if (FEE_BUSY_IN = '0') then
- saveNextState <= TERMINATE;
- else
- saveNextState <= SAVE_DATA;
- data_req_comb <= '1';
- end if;
- when TERMINATE =>
- state <= x"3";
- if (CTS_READ_IN = '1') then
- saveNextState <= SCLOSE;
- else
- saveNextState <= TERMINATE;
- end if;
- when SCLOSE =>
- state <= x"4";
- if (CTS_START_READOUT_IN = '0') then
- saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10
- else
- saveNextState <= SCLOSE;
- end if;
- -- gk 29.03.10 new states during which the subsub bytes are saved
- when ADD_SUBSUB1 =>
- state <= x"6";
- saveNextState <= ADD_SUBSUB2;
- add_sub_state_comb <= '1';
- when ADD_SUBSUB2 =>
- state<= x"7";
- saveNextState <= ADD_SUBSUB3;
- add_sub_state_comb <= '1';
- save_eod_comb <= '1';
- when ADD_SUBSUB3 =>
- state<= x"8";
- saveNextState <= ADD_SUBSUB4;
- add_sub_state_comb <= '1';
- when ADD_SUBSUB4 =>
- state<= x"9";
- saveNextState <= SIDLE;
- add_sub_state_comb <= '1';
- when others =>
- state <= x"f";
- saveNextState <= SIDLE;
- end case;
-end process saveMachine;
-
--- gk 29.03.10
-ADD_SUB_CTR_PROC : process( CLK )
-begin
- if( rising_edge( CLK ) ) then
- if( (RESET = '1') or (rst_saved_ctr = '1') ) then
- add_sub_ctr <= (others => '0');
- elsif( add_sub_state = '1' ) then
- add_sub_ctr <= add_sub_ctr + 1;
- end if;
- end if;
-end process ADD_SUB_CTR_PROC;
-
---********
--- SAVE INCOMING EVENT HEADERS
---********
-
--- Counter for header word storage
-THE_CTS_SAVED_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- saved_ctr <= (others => '0');
- elsif( ce_saved_ctr = '1' ) then
- saved_ctr <= saved_ctr + 1;
- end if;
- end if;
-end process THE_CTS_SAVED_CTR;
-
--- save triggerRnd from incoming data for cts response
-CTS_RND_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_rnd <= (others => '0');
- cts_rnd_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then
- cts_rnd <= sf_data;
- cts_rnd_saved <= '1';
- end if;
- end if;
-end process CTS_RND_PROC;
-
--- save triggerNr from incoming data for cts response
-CTS_TRG_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_trg <= (others => '0');
- cts_trg_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then
- cts_trg <= sf_data;
- cts_trg_saved <= '1';
- end if;
- end if;
-end process CTS_TRG_PROC;
-
--- save size from incoming data for cts response (future) and to get rid of padding
-CTS_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_len <= (others => '0');
- cts_len_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then
- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words
- cts_len(0) <= '0';
- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then
- cts_len <= cts_len + x"4";
- cts_len_saved <= '1';
- end if;
- end if;
-end process CTS_SIZE_PROC;
-
--- gk 22.07.10
-CTS_ADDR_PROC : process(CLK)
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_addr <= (others => '0');
- cts_addr_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then
- cts_addr <= sf_data;
- cts_addr_saved <= '1';
- end if;
- end if;
-end process CTS_ADDR_PROC;
-
---******
--- SAVE FIRST EVENT HEADER VALUES
---******
-
--- gk 22.07.10
-FIRST_RUN_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- first_run_trg <= (others => '0');
- first_run_addr <= (others => '0');
- first_run_lock <= '0';
- elsif (first_run_lock = '0') and (cts_addr_saved = '1') then
- first_run_trg <= cts_trg;
- first_run_addr <= cts_addr;
- first_run_lock <= '1';
- -- important: value saved by saveMachine but incremented by loadMachine
- elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then
- first_run_trg <= first_run_trg + x"1";
- end if;
- end if;
-end process FIRST_RUN_PROC;
-
--- gk 25.07.10
-SAVED_EVT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saved_events_ctr <= (others => '0');
- elsif (save_eod = '1') then
- saved_events_ctr <= saved_events_ctr + x"1";
- end if;
- end if;
-end process SAVED_EVT_CTR_PROC;
-
-
--- gk 20.07.10
-INC_DATA_CTR_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (rst_saved_ctr = '1') then
- inc_data_ctr <= (others => '0');
- elsif (sf_wr_en = '1') and (data_req = '1') then
- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1";
- end if;
- end if;
-end process INC_DATA_CTR_proc;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Split FIFO
-THE_SPLIT_FIFO: fifo_32kx16x8_mb2
-port map(
- -- Byte swapping for correct byte order on readout side of FIFO
- Data(7 downto 0) => sf_data(15 downto 8),
- Data(8) => '0',
- Data(16 downto 9) => sf_data(7 downto 0),
- Data(17) => save_eod,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en,
- RdEn => sf_rd_en,
- Reset => RESET,
- RPReset => RESET,
- AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead
- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751
- Q(7 downto 0) => pc_data,
- Q(8) => load_eod,
- WCNT => sf_wcnt,
- RCNT => sf_rcnt,
- Empty => sf_empty,
- AlmostEmpty => sf_aempty,
- Full => sf_full,
- AlmostFull => sf_afull
-);
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- gk 25.07.10
-EVENT_WAITING_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- event_waiting <= '0';
- elsif (loaded_events_ctr /= saved_events_ctr) then
- event_waiting <= '1';
- else
- event_waiting <= '0';
- end if;
- end if;
-end process EVENT_WAITING_PROC;
-
--- write signal for PC data
-pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or
- (pad_phase = '1') or
- ((load_sub = '1') and (sf_rd_en = '1')) or
- ((drop_sub = '1') and (sf_rd_en = '1')) or
- ((drop_event = '1') and (sf_rd_en = '1'))
- else '0';
-
-sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or
- --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or
- ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10
- ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10
- ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or
- ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') )
- else '0';
-
-ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') )
- else '0';
-
--- FIFO data delay process (also forces padding bytes to known value)
-THE_DATA_DELAY_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( pad_data = '1' ) then
- pc_data_q <= x"aa"; -- padding for 64bit
- -- gk 21.07.10
- -- set the error flag if a broken packet is sent
- elsif (drop_sub = '1') and (load_sub_ctr = x"3") then
- pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0);
- else
- pc_data_q <= pc_data;
- end if;
- end if;
-end process THE_DATA_DELAY_PROC;
-
--- Statemachine for reading the data payload from the SPLIT_FIFO and feeding
--- it into the packet constructor
-loadMachineProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- loadCurrentState <= LIDLE;
- rst_rem_ctr <= '0';
- rem_phase <= '0';
- calc_pad <= '0';
- data_phase <= '0';
- pad_phase <= '0';
- pc_sos <= '0';
- pc_eod <= '0';
- rst_regs <= '0';
- pad_data <= '0';
- load_sub <= '0'; -- gk 30.03.10
- drop_sub <= '0'; -- gk 25.07.10
- drop_event <= '0'; -- gk 25.07.10
- drop_small <= '0'; -- gk 25.07.10
- drop_large <= '0'; -- gk 25.07.10
- drop_headers <= '0'; -- gk 25.07.10
- inc_trg_ctr <= '0'; -- gk 26.07.10
- found_empty_evt <= '0'; -- gk 01.10.10
- else
- loadCurrentState <= loadNextState;
- rst_rem_ctr <= rst_rem_ctr_comb;
- rem_phase <= rem_phase_comb;
- calc_pad <= calc_pad_comb;
- data_phase <= data_phase_comb;
- pad_phase <= pad_phase_comb;
- pc_sos <= pc_sos_comb;
- pc_eod <= pc_eod_comb;
- rst_regs <= rst_regs_comb;
- pad_data <= pad_data_comb;
- load_sub <= load_sub_comb; -- gk 30.03.1
- drop_sub <= drop_sub_comb; -- gk 25.07.10
- drop_event <= drop_event_comb; -- gk 25.07.10
- drop_small <= drop_small_comb; -- gk 25.07.10
- drop_large <= drop_large_comb; -- gk 25.07.10
- drop_headers <= drop_headers_comb; -- gk 25.07.10
- inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10
- found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10
- end if;
- end if;
-end process loadMachineProc;
-
-loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, first_run_addr, load_eod, event_waiting)
-begin
- loadNextState <= LIDLE;
- rst_rem_ctr_comb <= '0';
- rem_phase_comb <= '0';
- calc_pad_comb <= '0';
- data_phase_comb <= '0';
- pad_phase_comb <= '0';
- pc_sos_comb <= '0';
- pc_eod_comb <= '0';
- rst_regs_comb <= '0';
- pad_data_comb <= '0';
- load_sub_comb <= '0'; -- gk 30.03.10
- drop_sub_comb <= '0'; -- gk 25.07.10
- drop_event_comb <= '0'; -- gk 25.07.10
- drop_small_comb <= '0'; -- gk 25.07.10
- drop_large_comb <= '0'; -- gk 25.07.10
- drop_headers_comb <= '0'; -- gk 25.07.10
- inc_trg_ctr_comb <= '0'; -- gk 26.07.10
- found_empty_evt_comb <= '0'; -- gk 01.10.10
- case loadCurrentState is
- when LIDLE =>
- state2 <= x"0";
- -- gk 23.07.10
- if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10
- loadNextState <= INIT;
- rst_rem_ctr_comb <= '1';
- rst_regs_comb <= '1';
- else
- loadNextState <= LIDLE;
- end if;
- when INIT =>
- state2 <= x"1";
- loadNextState <= REMOVE;
- rem_phase_comb <= '1';
- when REMOVE =>
- state2 <= x"2";
- if( remove_done = '1' ) then
- loadNextState <= WAIT_TO_REMOVE;
- inc_trg_ctr_comb <= '1';
- else
- loadNextState <= REMOVE;
- rem_phase_comb <= '1';
- end if;
- when WAIT_TO_REMOVE =>
- if (rem_ctr = x"a") then
- loadNextState <= DECIDE;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
- when DECIDE =>
- if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_large_comb <= '1';
- elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10
- loadNextState <= CALCA;
- found_empty_evt_comb <= '1';
- elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_small_comb <= '1';
- elsif (pc_trig_nr + x"1" /= first_run_trg) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_headers_comb <= '1';
- elsif (endpoint_addr /= first_run_addr) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_headers_comb <= '1';
- else
- loadNextState <= CALCA;
- end if;
- calc_pad_comb <= '1';
- when CALCA =>
- state2 <= x"3";
- loadNextState <= CALCB;
- pc_sos_comb <= '1';
- when CALCB =>
- -- we need a branch in case of length "0"!!!!
- state2 <= x"4";
- loadNextState <= LOAD;
- data_phase_comb <= '1';
- when LOAD =>
- state2 <= x"5";
- -- gk 31.03.10 after loading subevent data read the subsubevent from sf
- if (load_eod = '1') then
- loadNextState <= LOAD_SUBSUB;
- else
- loadNextState <= LOAD;
- data_phase_comb <= '1';
- end if;
- -- gk 31.03.10
- when LOAD_SUBSUB =>
- state2 <= x"d";
- if( load_sub_done = '1' ) then
- if( padding_needed = '0' ) then
- loadNextState <= CALCC;
- else
- loadNextState <= PAD0;
- pad_phase_comb <= '1';
- end if;
- else
- loadNextState <= LOAD_SUBSUB;
- load_sub_comb <= '1';
- end if;
- when PAD0 =>
- state2 <= x"6";
- loadNextState <= PAD1;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD1 =>
- state2 <= x"7";
- loadNextState <= PAD2;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD2 =>
- state2 <= x"8";
- loadNextState <= PAD3;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD3 =>
- state2 <= x"9";
- loadNextState <= CALCC;
- pad_data_comb <= '1';
- when CALCC =>
- state2 <= x"a";
- loadNextState <= CLOSE;
- pc_eod_comb <= '1';
- when CLOSE =>
- state2 <= x"b";
- loadNextState <= WAIT_PC;
- rst_regs_comb <= '1';
- when WAIT_PC =>
- state2 <= x"c";
- if( PC_READY_IN = '1' ) then
- loadNextState <= LIDLE;
- else
- loadNextState <= WAIT_PC;
- end if;
- when PAUSE_BEFORE_DROP1 =>
- loadNextState <= PAUSE_BEFORE_DROP2;
- pc_sos_comb <= '1';
- when PAUSE_BEFORE_DROP2 =>
- loadNextState <= DROP;
- drop_event_comb <= '1';
- -- gk 23.07.10
- when DROP =>
- state2 <= x"e";
- -- when data is dropped the eod marker stands as its end
- if (load_eod = '1') then
- loadNextState <= DROP_SUBSUB;
- else
- loadNextState <= DROP;
- drop_event_comb <= '1';
- end if;
- -- gk 25.07.10
- when DROP_SUBSUB =>
- if (load_sub_done = '1') then
- if( padding_needed = '0' ) then
- loadNextState <= CALCC;
- else
- loadNextState <= PAD0;
- pad_phase_comb <= '1';
- end if;
- else
- loadNextState <= DROP_SUBSUB;
- drop_sub_comb <= '1';
- end if;
- when others =>
- state2 <= x"f";
- loadNextState <= LIDLE;
- end case;
-end process loadMachine;
-
--- gk 25.07.10
-INVALID_STATS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- dropped_lr_events_ctr <= (others => '0');
- dropped_sm_events_ctr <= (others => '0');
- headers_invalid_ctr <= (others => '0');
- dropped_ctr <= (others => '0');
- invalid_hsize_ctr <= (others => '0');
- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10
- elsif (rst_regs = '1') then
- invalid_hsize_lock <= '0';
- elsif (drop_small = '1') then
- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1";
- dropped_ctr <= dropped_ctr + x"1";
- elsif (drop_large = '1') then
- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1";
- dropped_ctr <= dropped_ctr + x"1";
- elsif (drop_headers = '1') then
- headers_invalid_ctr <= headers_invalid_ctr + x"1";
- dropped_ctr <= dropped_ctr + x"1";
- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ??
- invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
- invalid_hsize_lock <= '1';
- -- gk 01.10.10
- elsif (found_empty_evt = '1') then
- found_empty_evt_ctr <= found_empty_evt_ctr + x"1";
- end if;
- end if;
-end process INVALID_STATS_PROC;
-
--- gk 05.08.10
-INVALID_H_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- load_eod_q <= load_eod;
- read_size_q <= read_size;
- end if;
-end process INVALID_H_PROC;
-
--- gk 26.04.10
-READOUT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then
- readout_ctr <= READOUT_CTR_IN;
- readout_ctr_lock <= '0';
- elsif (pc_sos = '1') then
- readout_ctr <= readout_ctr + x"1";
- end if;
- end if;
-end process READOUT_CTR_PROC;
-
---******
--- SELECTION OF EVENT BUILDER
---******
-
--- gk 27.03.10
-bank_select_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- -- gk 29.03.10
- if( (RESET = '1') or (rst_regs = '1') ) then
- bank_select <= "0000";
- -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
- bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
- end if;
- end if;
-end process bank_select_proc;
-
--- gk 29.03.10
-start_config_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then
- start_config <= '0';
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then -- gk 01.06.10
- start_config <= '1';
- end if;
- end if;
-end process start_config_proc;
-
-
---******
--- LOAD SUBSUBEVENT
---******
-
--- gk 30.03.10
-load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') )
- else '0';
-
--- gk 30.03.10
-LOAD_SUB_CTR_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
- load_sub_ctr <= (others => '0');
- elsif( (load_sub_ctr_comb = '1') ) then
- load_sub_ctr <= load_sub_ctr + 1;
- end if;
- end if;
-end process LOAD_SUB_CTR_PROC;
-
--- gk 30.03.10
--- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or
--- ((load_sub_ctr = x"4") and (drop_sub = '1'))
--- else '0';
-load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0';
-
--- gk 30.03.10
-LOAD_SUB_DONE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
- load_sub_done <= '0';
- else
- load_sub_done <= load_sub_done_comb;
- end if;
- end if;
-end process LOAD_SUB_DONE_PROC;
-
---******
--- EXTRACT EVENT HEADERS FROM SPLITFIFO
---******
-
--- Counter for stripping the unneeded parts of the data stream, and saving the important parts
-THE_REMOVE_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
- rem_ctr <= (others => '0');
- elsif( (ce_rem_ctr = '1') ) then
- rem_ctr <= rem_ctr + 1;
- end if;
- end if;
-end process THE_REMOVE_CTR;
-
-remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address
-
-THE_REM_DONE_SYNC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
- remove_done <= '0';
- else
- remove_done <= remove_done_comb;
- end if;
- end if;
-end process THE_REM_DONE_SYNC;
-
--- gk 26.04.10
-TRIG_RANDOM_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (rst_regs = '1')) then
- trig_random <= (others => '0');
- elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then
- trig_random <= pc_data;
- end if;
- end if;
-end process TRIG_RANDOM_PROC;
-
--- extract the trigger number from splitfifo data
-THE_TRG_NR_PROC: process( CLK )
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- pc_trig_nr <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10
- pc_trig_nr(7 downto 0) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10
- pc_trig_nr(15 downto 8) <= pc_data;
- end if;
- end if;
-end process THE_TRG_NR_PROC;
-
--- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,
--- and in case of padding needed increase it accordingly
-THE_SUB_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- pc_sub_size <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
- pc_sub_size(9 downto 2) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
- pc_sub_size(17 downto 10) <= pc_data;
- -- gk 20.07.10
- -- gk 30.03.10 bug fixed in the way that is written below
- -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save
- elsif( (calc_pad = '1') and (padding_needed = '1') ) then
- pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!!
- elsif( (calc_pad = '1') and (padding_needed = '0') ) then
- pc_sub_size <= pc_sub_size + x"8";
- end if;
- end if;
-end process THE_SUB_SIZE_PROC;
-
--- gk 25.07.10
-ENDP_ADDRESS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (rst_regs = '1') then
- endpoint_addr <= (others => '0');
- endp_addr_lock <= '0';
- elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then
- endpoint_addr(7 downto 0) <= pc_data;
- endp_addr_lock <= '1';
- elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then
- endpoint_addr(15 downto 8) <= pc_data;
- endp_addr_lock <= '0';
- end if;
- end if;
-end process ENDP_ADDRESS_PROC;
-
-
-
--- check for padding
-THE_PADDING_NEEDED_PROC: process( CLK )
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- padding_needed <= '0';
- elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then
- padding_needed <= '1';
- elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then
- padding_needed <= '0';
- end if;
- end if;
-end process THE_PADDING_NEEDED_PROC;
-
--- number of bytes to read from split fifo
-THE_READ_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then
- read_size <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
- read_size(9 downto 2) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
- read_size(17 downto 10) <= pc_data;
- elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then
- read_size <= read_size - 1;
- -- gk 25.07.10
- elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then
- read_size <= read_size - 1;
- end if;
- end if;
-end process THE_READ_SIZE_PROC;
-
-read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2"
-
---******
--- EVENTS COUNTERS
---******
-
--- gk 25.07.10
-LOADED_EVT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- loaded_events_ctr <= (others => '0');
- elsif (remove_done = '1') then
- loaded_events_ctr <= loaded_events_ctr + x"1";
- end if;
- end if;
-end process LOADED_EVT_CTR_PROC;
-
--- gk 25.07.10
-CONSTR_EVENTS_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- constr_events_ctr <= (others => '0');
- elsif (pc_eod = '1') then
- constr_events_ctr <= constr_events_ctr + x"1";
- end if;
- end if;
-end process CONSTR_EVENTS_CTR_PROC;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Debug signals
-debug(0) <= sf_full;
-debug(1) <= sf_empty;
-debug(2) <= sf_afull;
-debug(3) <= sf_aempty;
-
-debug(7 downto 4) <= state2;
-
-debug(11 downto 8) <= state;
-
-dbg_bs_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if RESET = '1' then
- debug(15 downto 12) <= (others => '0');
- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
- debug(15 downto 12) <= bank_select;
- end if;
- end if;
-end process dbg_bs_proc;
-
-debug(16) <= config_done;
-debug(17) <= remove_done;
-debug(18) <= read_done;
-debug(19) <= padding_needed;
-
-debug(20) <= load_sub_done;
-
-dbg_cts_inf_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- debug(39 downto 32) <= (others => '0');
- elsif ( save_addr = '1' ) then
- debug(39 downto 32) <= CTS_INFORMATION_IN;
- end if;
- end if;
-end process dbg_cts_inf_proc;
-
-debug(47 downto 40) <= (others => '0');
-
-
-debug(63 downto 48) <= actual_message_size(15 downto 0);
-
-dbg_pc_sub_size_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- debug(81 downto 64) <= (others => '0');
- elsif (loadCurrentState = DECIDE) then
- debug(81 downto 64) <= pc_sub_size;
- end if;
- end if;
-end process dbg_pc_sub_size_proc;
-
-dbg_empty_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (rst_regs = '1') then
- debug(84 downto 82) <= (others => '0');
- elsif (read_size = 2) then
- debug(82) <= sf_empty;
- elsif (read_size = 1) then
- debug(83) <= sf_empty;
- elsif (read_size = 0) then
- debug(84) <= sf_empty;
- end if;
- end if;
-end process dbg_empty_proc;
-
-debug(95 downto 85) <= (others => '0');
-
-dbg_inc_ctr_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- debug(127 downto 96) <= (others => '1');
- elsif (saveCurrentState = SCLOSE) then
- debug(127 downto 96) <= inc_data_ctr;
- end if;
- end if;
-end process dbg_inc_ctr_proc;
-
-debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0);
-debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0);
-
-debug(175 downto 160) <= headers_invalid_ctr(15 downto 0);
-debug(191 downto 176) <= (others => '0');
-
-dbg_cts_q_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- cts_len_q <= (others => '0');
- cts_rnd_q <= (others => '0');
- cts_trg_q <= (others => '0');
- cts_addr_q <= (others => '0');
- elsif (cts_len_saved = '1') then
- cts_len_q <= cts_len(16 downto 1);
- cts_addr_q <= cts_addr;
- cts_rnd_q <= cts_rnd;
- cts_trg_q <= cts_trg;
- end if;
- end if;
-end process dbg_cts_q_proc;
-
-debug(207 downto 192) <= cts_trg_q;
-debug(223 downto 208) <= cts_rnd_q;
-debug(239 downto 224) <= cts_addr_q;
-debug(255 downto 240) <= cts_len_q;
-debug(271 downto 256) <= first_run_trg;
-debug(287 downto 272) <= first_run_addr;
-
-debug(303 downto 288) <= saved_events_ctr;
-debug(319 downto 304) <= loaded_events_ctr;
-
-debug(335 downto 320) <= constr_events_ctr(15 downto 0);
-debug(351 downto 336) <= dropped_ctr(15 downto 0);
-
-debug(367 downto 352) <= invalid_hsize_ctr;
-debug(383 downto 368) <= (others => '0');
-
-MONITOR_OUT(31 downto 0) <= constr_events_ctr;
-MONITOR_OUT(63 downto 32) <= dropped_ctr;
-MONITOR_OUT(95 downto 64) <= headers_invalid_ctr;
-MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr;
-MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
-MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000";
-MONITOR_OUT(191 downto 164) <= (others => '0');
-MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10
-
--- Outputs
-FEE_READ_OUT <= fee_read;
-CTS_ERROR_PATTERN_OUT <= cts_error_pattern;
-CTS_DATA_OUT <= cts_data;
-CTS_DATAREADY_OUT <= cts_dataready;
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
-CTS_LENGTH_OUT <= cts_length;
-
-PC_SOS_OUT <= pc_sos;
-PC_EOD_OUT <= pc_eod; -- gk 26.07.10 --pc_eod_q;
-PC_DATA_OUT <= pc_data_q;
-PC_WR_EN_OUT <= pc_wr_en_qq;
-
-PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random;
-
-PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size;
-PC_PADDING_OUT <= padding_needed;
-
-DEBUG_OUT <= debug;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-
-entity trb_net16_ipu2gbe is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
- MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- -- PacketConstructor interface
- ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic; -- gk 07.10.10
- PC_EOD_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_PADDING_OUT : out std_logic;
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
-);
-end entity;
-
-architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is
-
--- attribute HGROUP : string;
--- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe";
-
-component fifo_32kx16x8_mb2
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(8 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0);
- Empty : out std_logic;
- AlmostEmpty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
-);
-end component;
-
-type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE);
-signal saveCurrentState, saveNextState : saveStates;
-signal state : std_logic_vector(3 downto 0);
-signal data_req_comb : std_logic;
-signal data_req : std_logic; -- request data signal, will be used for fee_read generation
-signal rst_saved_ctr_comb : std_logic;
-signal rst_saved_ctr : std_logic;
-
-signal fee_read_comb : std_logic;
-signal fee_read : std_logic; -- fee_read signal
-signal saved_ctr : std_logic_vector(16 downto 0);
-signal ce_saved_ctr : std_logic;
-
--- header data
-signal cts_rnd : std_logic_vector(15 downto 0);
-signal cts_rnd_saved : std_logic;
-signal cts_trg : std_logic_vector(15 downto 0);
-signal cts_trg_saved : std_logic;
-signal cts_len : std_logic_vector(16 downto 0);
-signal cts_len_saved : std_logic;
-
--- CTS interface
-signal cts_error_pattern : std_logic_vector(31 downto 0);
-signal cts_length : std_logic_vector(15 downto 0);
-signal cts_readout_finished : std_logic;
-signal cts_dataready : std_logic;
-signal cts_data : std_logic_vector(31 downto 0);
-
--- Split FIFO signals
-signal sf_data : std_logic_vector(15 downto 0);
-signal sf_wr_en_comb : std_logic;
-signal sf_wr_en : std_logic; -- write signal for FIFO
-signal sf_rd_en_comb : std_logic;
-signal sf_rd_en : std_logic; -- read signal for FIFO
-signal sf_wcnt : std_logic_vector(15 downto 0);
-signal sf_rcnt : std_logic_vector(16 downto 0);
-signal sf_empty : std_logic;
-signal sf_aempty : std_logic;
-signal sf_full : std_logic;
-signal sf_afull : std_logic;
-
--------------------------------------------------------------------
-type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2);
-signal loadCurrentState, loadNextState : loadStates;
-signal state2 : std_logic_vector(3 downto 0);
-
-signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data
-signal rst_rem_ctr_comb : std_logic;
-signal rst_rem_ctr : std_logic; -- reset the remove counter
-signal rst_regs_comb : std_logic;
-signal rst_regs : std_logic; -- reset storage registers
-signal rem_phase_comb : std_logic;
-signal rem_phase : std_logic; -- header remove phase
-signal data_phase_comb : std_logic;
-signal data_phase : std_logic; -- data transport phase from split fifo to PC
-signal pad_phase_comb : std_logic;
-signal pad_phase : std_logic; -- padding phase
-signal calc_pad_comb : std_logic;
-signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE
-signal pad_data_comb : std_logic;
-signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value
-
-signal pc_sos_comb : std_logic;
-signal pc_sos : std_logic; -- start of data signal
-signal pc_eod_comb : std_logic;
-signal pc_eod : std_logic; -- end of data signal
-
-signal ce_rem_ctr_comb : std_logic;
-signal ce_rem_ctr : std_logic; -- count enable for remove counter
-signal remove_done_comb : std_logic;
-signal remove_done : std_logic; -- end of header stripping process
-signal read_done_comb : std_logic;
-signal read_done : std_logic; -- end of data phase (read phase from SF)
-
-signal pc_data : std_logic_vector(7 downto 0);
-signal pc_data_q : std_logic_vector(7 downto 0);
-signal pc_trig_nr : std_logic_vector(15 downto 0);
-signal pc_sub_size : std_logic_vector(17 downto 0);
-signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo
-signal padding_needed : std_logic;
-signal pc_wr_en_comb : std_logic;
-signal pc_wr_en_q : std_logic;
-signal pc_wr_en_qq : std_logic;
-signal pc_wr_en_qqq : std_logic;
-signal pc_eod_q : std_logic;
-
-signal debug : std_logic_vector(383 downto 0);
-
--- gk
-signal bank_select : std_logic_vector(3 downto 0);
-signal save_addr_comb : std_logic;
-signal save_addr : std_logic;
-signal addr_saved_comb : std_logic;
-signal addr_saved : std_logic;
-signal start_config : std_logic;
-signal config_done : std_logic;
-signal add_sub_state : std_logic;
-signal add_sub_state_comb : std_logic;
-signal add_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub : std_logic;
-signal load_sub_comb : std_logic;
-signal load_sub_done : std_logic;
-signal load_sub_done_comb : std_logic;
-signal load_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub_ctr_comb : std_logic;
-signal actual_message_size : std_logic_vector(31 downto 0);
-signal more_subevents : std_logic;
-signal trig_random : std_logic_vector(7 downto 0);
-signal readout_ctr : std_logic_vector(23 downto 0);
-signal readout_ctr_lock : std_logic;
-signal pc_trig_nr_q : std_logic_vector(31 downto 0);
-
--- gk 20.07.10
-signal inc_data_ctr : std_logic_vector(31 downto 0);
-signal dropped_sm_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_lr_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_ctr : std_logic_vector(31 downto 0);
--- gk 22.07.10
-signal headers_invalid : std_logic;
-signal headers_invalid_ctr : std_logic_vector(31 downto 0);
-signal cts_len_q : std_logic_vector(15 downto 0);
-signal cts_trg_q : std_logic_vector(15 downto 0);
-signal cts_rnd_q : std_logic_vector(15 downto 0);
-signal first_run_trg : std_logic_vector(15 downto 0);
-signal first_run_addr : std_logic_vector(15 downto 0);
-signal first_run_lock : std_logic;
-signal cts_addr : std_logic_vector(15 downto 0);
-signal cts_addr_q : std_logic_vector(15 downto 0);
-signal cts_addr_saved : std_logic;
-
--- gk 24.07.10
-signal save_eod : std_logic;
-signal save_eod_comb : std_logic;
-
-signal load_eod : std_logic;
-signal endpoint_addr : std_logic_vector(15 downto 0);
-signal endp_addr_lock : std_logic;
-
-signal saved_events_ctr : std_logic_vector(15 downto 0);
-signal loaded_events_ctr : std_logic_vector(15 downto 0);
-signal constr_events_ctr : std_logic_vector(31 downto 0);
-signal event_waiting : std_logic;
-
-signal drop_sub : std_logic;
-signal drop_sub_comb : std_logic;
-signal drop_event : std_logic;
-signal drop_event_comb : std_logic;
-signal drop_small : std_logic;
-signal drop_large : std_logic;
-signal drop_headers : std_logic;
-signal drop_small_comb : std_logic;
-signal drop_large_comb : std_logic;
-signal drop_headers_comb : std_logic;
-signal inc_trg_ctr : std_logic;
-signal inc_trg_ctr_comb : std_logic;
-
-signal invalid_hsize_ctr : std_logic_vector(15 downto 0);
-signal invalid_hsize_lock : std_logic;
-
-signal load_eod_q : std_logic;
-signal read_size_q : std_logic_vector(17 downto 0);
-
--- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked
-signal sf_real_wr_en : std_logic;
-
--- gk 01.10.10
-signal found_empty_evt : std_logic;
-signal found_empty_evt_comb : std_logic;
-signal found_empty_evt_ctr : std_logic_vector(31 downto 0);
-
--- gk 06.10.10
-signal message_size : std_logic_vector(31 downto 0);
-
--- gk 07.12.10
-signal prev_bank_select : std_logic_vector(3 downto 0);
-signal first_event : std_logic;
-
-begin
-
-BANK_SELECT_OUT <= bank_select; -- gk 27.03.10
-START_CONFIG_OUT <= start_config; -- gk 27.03.10
-config_done <= CONFIG_DONE_IN; -- gk 29.03.10
-
--- CTS interface signals
-cts_error_pattern <= (others => '0'); -- FAKE
-
-cts_length <= x"0000"; -- length of data payload is always 0
-cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'
-
-cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';
-
-cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE)
- else '0';
-
--- Byte swapping... done here. TAKE CARE!
--- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes
--- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port.
--- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped
--- for GbE inside the packet constructor.
---
--- Long live the Endianess!
-
--- Sync all critical pathes
-THE_SYNC_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below
- sf_wr_en <= sf_wr_en_comb;
- ce_rem_ctr <= ce_rem_ctr_comb;
- sf_rd_en <= sf_rd_en_comb;
- fee_read <= fee_read_comb;
- read_done <= read_done_comb;
- pc_eod_q <= pc_eod;
- pc_wr_en_qqq <= pc_wr_en_qq;
- pc_wr_en_qq <= pc_wr_en_q;
- pc_wr_en_q <= pc_wr_en_comb;
- end if;
-end process THE_SYNC_PROC;
-
--- -- gk 27.03.10 data selector for sf to write the evt builder address on top of data
--- SF_DATA_PROC : process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if (RESET = '1') then -- gk 31.05.10
--- sf_data <= (others => '0');
--- elsif( save_addr = '1' ) then
--- sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address
--- sf_data(15 downto 4) <= x"abc";
--- -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent
--- elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then
--- sf_data <= x"0001"; -- gk 11.06.10
--- elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then
--- sf_data <= x"5555"; -- gk 11.06.10
--- elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then
--- sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
--- elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then
--- sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
--- else
--- sf_data <= FEE_DATA_IN;
--- end if;
--- end if;
--- end process SF_DATA_PROC;
-
--- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY
-fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
- else '0';
-
--- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY
-sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
- (save_addr = '1') or
- (add_sub_state = '1') -- gk 29.03.10 save the subsubevent
- else '0';
-
--- gk 06.08.10
-sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0';
-
--- gk 27.03.10 do not count evt builder address as saved ipu bytes
---ce_saved_ctr <= sf_wr_en;
-ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en;
-
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO
--- saveMachineProc: process( CLK )
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- saveCurrentState <= SIDLE;
--- data_req <= '0';
--- rst_saved_ctr <= '0';
--- save_addr <= '0'; -- gk 27.03.10
--- addr_saved <= '0'; -- gk 27.03.10
--- add_sub_state <= '0'; -- gk 29.03.10
--- save_eod <= '0'; -- gk 25.07.10
--- else
--- saveCurrentState <= saveNextState;
--- data_req <= data_req_comb;
--- rst_saved_ctr <= rst_saved_ctr_comb;
--- save_addr <= save_addr_comb; -- gk 27.03.10
--- addr_saved <= addr_saved_comb; -- gk 27.03.10
--- add_sub_state <= add_sub_state_comb; -- gk 29.03.10
--- save_eod <= save_eod_comb; -- gk 25.07.10
--- end if;
--- end if;
--- end process saveMachineProc;
---
--- saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN)
--- begin
--- saveNextState <= SIDLE;
--- data_req_comb <= '0';
--- rst_saved_ctr_comb <= '0';
--- save_addr_comb <= '0'; -- gk 27.03.10
--- addr_saved_comb <= '0'; -- gk 27.03.10
--- add_sub_state_comb <= '0'; -- gk 29.03.10
--- save_eod_comb <= '0'; -- gk 25.07.10
--- case saveCurrentState is
--- when SIDLE =>
--- state <= x"0";
--- if (CTS_START_READOUT_IN = '1') then
--- saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10
--- data_req_comb <= '1';
--- rst_saved_ctr_comb <= '1';
--- else
--- saveNextState <= SIDLE;
--- end if;
--- -- gk 27.03.10
--- when SAVE_EVT_ADDR =>
--- state <= x"5";
--- saveNextState <= WAIT_FOR_DATA;
--- data_req_comb <= '1';
--- save_addr_comb <= '1';
--- when WAIT_FOR_DATA =>
--- state <= x"1";
--- if (FEE_BUSY_IN = '1') then
--- saveNextState <= SAVE_DATA;
--- data_req_comb <= '1';
--- else
--- saveNextState <= WAIT_FOR_DATA;
--- data_req_comb <= '1';
--- end if;
--- addr_saved_comb <= '1'; -- gk 27.03.10
--- when SAVE_DATA =>
--- state <= x"2";
--- if (FEE_BUSY_IN = '0') then
--- saveNextState <= TERMINATE;
--- else
--- saveNextState <= SAVE_DATA;
--- data_req_comb <= '1';
--- end if;
--- when TERMINATE =>
--- state <= x"3";
--- if (CTS_READ_IN = '1') then
--- saveNextState <= SCLOSE;
--- else
--- saveNextState <= TERMINATE;
--- end if;
--- when SCLOSE =>
--- state <= x"4";
--- if (CTS_START_READOUT_IN = '0') then
--- saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10
--- else
--- saveNextState <= SCLOSE;
--- end if;
--- -- gk 29.03.10 new states during which the subsub bytes are saved
--- when ADD_SUBSUB1 =>
--- state <= x"6";
--- saveNextState <= ADD_SUBSUB2;
--- add_sub_state_comb <= '1';
--- when ADD_SUBSUB2 =>
--- state<= x"7";
--- saveNextState <= ADD_SUBSUB3;
--- add_sub_state_comb <= '1';
--- save_eod_comb <= '1';
--- when ADD_SUBSUB3 =>
--- state<= x"8";
--- saveNextState <= ADD_SUBSUB4;
--- add_sub_state_comb <= '1';
--- when ADD_SUBSUB4 =>
--- state<= x"9";
--- saveNextState <= SIDLE;
--- add_sub_state_comb <= '1';
--- when others =>
--- state <= x"f";
--- saveNextState <= SIDLE;
--- end case;
--- end process saveMachine;
---
--- -- gk 29.03.10
--- ADD_SUB_CTR_PROC : process( CLK )
--- begin
--- if( rising_edge( CLK ) ) then
--- if( (RESET = '1') or (rst_saved_ctr = '1') ) then
--- add_sub_ctr <= (others => '0');
--- elsif( add_sub_state = '1' ) then
--- add_sub_ctr <= add_sub_ctr + 1;
--- end if;
--- end if;
--- end process ADD_SUB_CTR_PROC;
---
--- --********
--- -- SAVE INCOMING EVENT HEADERS
--- --********
---
--- -- Counter for header word storage
--- THE_CTS_SAVED_CTR: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
--- saved_ctr <= (others => '0');
--- elsif( ce_saved_ctr = '1' ) then
--- saved_ctr <= saved_ctr + 1;
--- end if;
--- end if;
--- end process THE_CTS_SAVED_CTR;
---
--- -- save triggerRnd from incoming data for cts response
--- CTS_RND_PROC: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
--- cts_rnd <= (others => '0');
--- cts_rnd_saved <= '0';
--- elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then
--- cts_rnd <= sf_data;
--- cts_rnd_saved <= '1';
--- end if;
--- end if;
--- end process CTS_RND_PROC;
---
--- -- save triggerNr from incoming data for cts response
--- CTS_TRG_PROC: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
--- cts_trg <= (others => '0');
--- cts_trg_saved <= '0';
--- elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then
--- cts_trg <= sf_data;
--- cts_trg_saved <= '1';
--- end if;
--- end if;
--- end process CTS_TRG_PROC;
---
--- -- save size from incoming data for cts response (future) and to get rid of padding
--- CTS_SIZE_PROC: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
--- cts_len <= (others => '0');
--- cts_len_saved <= '0';
--- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then
--- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words
--- cts_len(0) <= '0';
--- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then
--- cts_len <= cts_len + x"4";
--- cts_len_saved <= '1';
--- end if;
--- end if;
--- end process CTS_SIZE_PROC;
---
--- -- gk 22.07.10
--- CTS_ADDR_PROC : process(CLK)
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
--- cts_addr <= (others => '0');
--- cts_addr_saved <= '0';
--- elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then
--- cts_addr <= sf_data;
--- cts_addr_saved <= '1';
--- end if;
--- end if;
--- end process CTS_ADDR_PROC;
---
--- --******
--- -- SAVE FIRST EVENT HEADER VALUES
--- --******
---
--- -- gk 22.07.10
--- FIRST_RUN_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- first_run_trg <= (others => '0');
--- first_run_addr <= (others => '0');
--- first_run_lock <= '0';
--- elsif (first_run_lock = '0') and (cts_addr_saved = '1') then
--- first_run_trg <= cts_trg;
--- first_run_addr <= cts_addr;
--- first_run_lock <= '1';
--- -- important: value saved by saveMachine but incremented by loadMachine
--- elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then
--- first_run_trg <= first_run_trg + x"1";
--- end if;
--- end if;
--- end process FIRST_RUN_PROC;
---
--- -- gk 25.07.10
--- SAVED_EVT_CTR_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- saved_events_ctr <= (others => '0');
--- elsif (save_eod = '1') then
--- saved_events_ctr <= saved_events_ctr + x"1";
--- end if;
--- end if;
--- end process SAVED_EVT_CTR_PROC;
---
---
--- -- gk 20.07.10
--- INC_DATA_CTR_proc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (rst_saved_ctr = '1') then
--- inc_data_ctr <= (others => '0');
--- elsif (sf_wr_en = '1') and (data_req = '1') then
--- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1";
--- end if;
--- end if;
--- end process INC_DATA_CTR_proc;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Split FIFO
--- THE_SPLIT_FIFO: fifo_32kx16x8_mb2
--- port map(
--- -- Byte swapping for correct byte order on readout side of FIFO
--- Data(7 downto 0) => sf_data(15 downto 8),
--- Data(8) => '0',
--- Data(16 downto 9) => sf_data(7 downto 0),
--- Data(17) => save_eod,
--- WrClock => CLK,
--- RdClock => CLK,
--- WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en,
--- RdEn => sf_rd_en,
--- Reset => RESET,
--- RPReset => RESET,
--- AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead
--- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751
--- Q(7 downto 0) => pc_data,
--- Q(8) => load_eod,
--- WCNT => sf_wcnt,
--- RCNT => sf_rcnt,
--- Empty => sf_empty,
--- AlmostEmpty => sf_aempty,
--- Full => sf_full,
--- AlmostFull => sf_afull
--- );
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- gk 25.07.10
--- EVENT_WAITING_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- event_waiting <= '0';
--- elsif (loaded_events_ctr /= saved_events_ctr) then
--- event_waiting <= '1';
--- else
--- event_waiting <= '0';
--- end if;
--- end if;
--- end process EVENT_WAITING_PROC;
---
--- -- write signal for PC data
--- pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or
--- (pad_phase = '1') or
--- ((load_sub = '1') and (sf_rd_en = '1')) or
--- ((drop_sub = '1') and (sf_rd_en = '1')) or
--- ((drop_event = '1') and (sf_rd_en = '1'))
--- else '0';
---
--- sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or
--- --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or
--- ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10
--- ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10
--- ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or
--- ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') )
--- else '0';
---
--- ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') )
--- else '0';
---
--- -- FIFO data delay process (also forces padding bytes to known value)
--- THE_DATA_DELAY_PROC: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if( pad_data = '1' ) then
--- pc_data_q <= x"aa"; -- padding for 64bit
--- -- gk 21.07.10
--- -- set the error flag if a broken packet is sent
--- elsif (drop_sub = '1') and (load_sub_ctr = x"3") then
--- pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0);
--- else
--- pc_data_q <= pc_data;
--- end if;
--- end if;
--- end process THE_DATA_DELAY_PROC;
---
--- -- Statemachine for reading the data payload from the SPLIT_FIFO and feeding
--- -- it into the packet constructor
--- loadMachineProc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- loadCurrentState <= LIDLE;
--- rst_rem_ctr <= '0';
--- rem_phase <= '0';
--- calc_pad <= '0';
--- data_phase <= '0';
--- pad_phase <= '0';
--- pc_sos <= '0';
--- pc_eod <= '0';
--- rst_regs <= '0';
--- pad_data <= '0';
--- load_sub <= '0'; -- gk 30.03.10
--- drop_sub <= '0'; -- gk 25.07.10
--- drop_event <= '0'; -- gk 25.07.10
--- drop_small <= '0'; -- gk 25.07.10
--- drop_large <= '0'; -- gk 25.07.10
--- drop_headers <= '0'; -- gk 25.07.10
--- inc_trg_ctr <= '0'; -- gk 26.07.10
--- found_empty_evt <= '0'; -- gk 01.10.10
--- else
--- loadCurrentState <= loadNextState;
--- rst_rem_ctr <= rst_rem_ctr_comb;
--- rem_phase <= rem_phase_comb;
--- calc_pad <= calc_pad_comb;
--- data_phase <= data_phase_comb;
--- pad_phase <= pad_phase_comb;
--- pc_sos <= pc_sos_comb;
--- pc_eod <= pc_eod_comb;
--- rst_regs <= rst_regs_comb;
--- pad_data <= pad_data_comb;
--- load_sub <= load_sub_comb; -- gk 30.03.1
--- drop_sub <= drop_sub_comb; -- gk 25.07.10
--- drop_event <= drop_event_comb; -- gk 25.07.10
--- drop_small <= drop_small_comb; -- gk 25.07.10
--- drop_large <= drop_large_comb; -- gk 25.07.10
--- drop_headers <= drop_headers_comb; -- gk 25.07.10
--- inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10
--- found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10
--- end if;
--- end if;
--- end process loadMachineProc;
---
--- loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed,
--- PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN,
--- MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr,
--- first_run_addr, load_eod, event_waiting, MULT_EVT_ENABLE_IN, message_size)
--- begin
--- loadNextState <= LIDLE;
--- rst_rem_ctr_comb <= '0';
--- rem_phase_comb <= '0';
--- calc_pad_comb <= '0';
--- data_phase_comb <= '0';
--- pad_phase_comb <= '0';
--- pc_sos_comb <= '0';
--- pc_eod_comb <= '0';
--- rst_regs_comb <= '0';
--- pad_data_comb <= '0';
--- load_sub_comb <= '0'; -- gk 30.03.10
--- drop_sub_comb <= '0'; -- gk 25.07.10
--- drop_event_comb <= '0'; -- gk 25.07.10
--- drop_small_comb <= '0'; -- gk 25.07.10
--- drop_large_comb <= '0'; -- gk 25.07.10
--- drop_headers_comb <= '0'; -- gk 25.07.10
--- inc_trg_ctr_comb <= '0'; -- gk 26.07.10
--- found_empty_evt_comb <= '0'; -- gk 01.10.10
--- case loadCurrentState is
--- when LIDLE =>
--- state2 <= x"0";
--- -- gk 23.07.10
--- if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 -- and (PC_READY_IN = '1')
--- loadNextState <= INIT;
--- rst_rem_ctr_comb <= '1';
--- rst_regs_comb <= '1';
--- else
--- loadNextState <= LIDLE;
--- end if;
--- when INIT =>
--- state2 <= x"1";
--- loadNextState <= REMOVE;
--- rem_phase_comb <= '1';
--- when REMOVE =>
--- state2 <= x"2";
--- if( remove_done = '1' ) then
--- -- gk 06.10.10
--- if (MULT_EVT_ENABLE_IN = '1') then
--- if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then
--- --loadNextState <= WAIT_TO_REMOVE;
--- -- gk 07.12.10
--- if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet
--- loadNextState <= WAIT_PC;
--- else
--- loadNextState <= WAIT_TO_REMOVE;
--- end if;
---
--- else
--- loadNextState <= WAIT_PC;
--- end if;
--- else
--- loadNextState <= WAIT_TO_REMOVE;
--- end if;
--- inc_trg_ctr_comb <= '1';
--- else
--- loadNextState <= REMOVE;
--- rem_phase_comb <= '1';
--- end if;
--- when WAIT_TO_REMOVE =>
--- if (rem_ctr = x"a") then
--- loadNextState <= DECIDE;
--- else
--- loadNextState <= WAIT_TO_REMOVE;
--- end if;
--- when DECIDE =>
--- if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then
--- loadNextState <= PAUSE_BEFORE_DROP1;
--- drop_large_comb <= '1';
--- elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10
--- loadNextState <= CALCA;
--- found_empty_evt_comb <= '1';
--- elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then
--- loadNextState <= PAUSE_BEFORE_DROP1;
--- drop_small_comb <= '1';
--- elsif (pc_trig_nr + x"1" /= first_run_trg) then
--- loadNextState <= PAUSE_BEFORE_DROP1;
--- drop_headers_comb <= '1';
--- elsif (endpoint_addr /= first_run_addr) then
--- loadNextState <= PAUSE_BEFORE_DROP1;
--- drop_headers_comb <= '1';
--- else
--- loadNextState <= CALCA;
--- end if;
--- calc_pad_comb <= '1';
--- when CALCA =>
--- state2 <= x"3";
--- loadNextState <= CALCB;
--- pc_sos_comb <= '1';
--- when CALCB =>
--- -- we need a branch in case of length "0"!!!!
--- state2 <= x"4";
--- loadNextState <= LOAD;
--- data_phase_comb <= '1';
--- when LOAD =>
--- state2 <= x"5";
--- if (load_eod = '1') then
--- loadNextState <= LOAD_SUBSUB;
--- else
--- loadNextState <= LOAD;
--- data_phase_comb <= '1';
--- end if;
--- -- gk 31.03.10
--- when LOAD_SUBSUB =>
--- state2 <= x"d";
--- if( load_sub_done = '1' ) then
--- if( padding_needed = '0' ) then
--- loadNextState <= CALCC;
--- else
--- loadNextState <= PAD0;
--- pad_phase_comb <= '1';
--- end if;
--- else
--- loadNextState <= LOAD_SUBSUB;
--- load_sub_comb <= '1';
--- end if;
--- when PAD0 =>
--- state2 <= x"6";
--- loadNextState <= PAD1;
--- pad_phase_comb <= '1';
--- pad_data_comb <= '1';
--- when PAD1 =>
--- state2 <= x"7";
--- loadNextState <= PAD2;
--- pad_phase_comb <= '1';
--- pad_data_comb <= '1';
--- when PAD2 =>
--- state2 <= x"8";
--- loadNextState <= PAD3;
--- pad_phase_comb <= '1';
--- pad_data_comb <= '1';
--- when PAD3 =>
--- state2 <= x"9";
--- loadNextState <= CALCC;
--- pad_data_comb <= '1';
--- when CALCC =>
--- state2 <= x"a";
--- if (MULT_EVT_ENABLE_IN = '1') then
--- loadNextState <= LIDLE;
--- else
--- loadNextState <= CLOSE;
--- end if;
--- pc_eod_comb <= '1';
--- when CLOSE =>
--- state2 <= x"b";
--- loadNextState <= WAIT_PC;
--- --rst_regs_comb <= '1'; -- gk 07.10.10
--- when WAIT_PC =>
--- state2 <= x"c";
--- if( PC_READY_IN = '1' ) then
--- -- gk 06.10.10
--- if (MULT_EVT_ENABLE_IN = '1') then
--- loadNextState <= WAIT_TO_REMOVE;
--- else
--- loadNextState <= LIDLE;
--- end if;
--- else
--- loadNextState <= WAIT_PC;
--- end if;
--- when PAUSE_BEFORE_DROP1 =>
--- loadNextState <= PAUSE_BEFORE_DROP2;
--- pc_sos_comb <= '1';
--- when PAUSE_BEFORE_DROP2 =>
--- loadNextState <= DROP;
--- drop_event_comb <= '1';
--- -- gk 23.07.10
--- when DROP =>
--- state2 <= x"e";
--- -- when data is dropped the eod marker stands as its end
--- if (load_eod = '1') then
--- loadNextState <= DROP_SUBSUB;
--- else
--- loadNextState <= DROP;
--- drop_event_comb <= '1';
--- end if;
--- -- gk 25.07.10
--- when DROP_SUBSUB =>
--- if (load_sub_done = '1') then
--- if( padding_needed = '0' ) then
--- loadNextState <= CALCC;
--- else
--- loadNextState <= PAD0;
--- pad_phase_comb <= '1';
--- end if;
--- else
--- loadNextState <= DROP_SUBSUB;
--- drop_sub_comb <= '1';
--- end if;
--- when others =>
--- state2 <= x"f";
--- loadNextState <= LIDLE;
--- end case;
--- end process loadMachine;
---
--- -- gk 07.10.10
--- PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0';
---
--- -- gk 25.07.10
--- INVALID_STATS_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- dropped_lr_events_ctr <= (others => '0');
--- dropped_sm_events_ctr <= (others => '0');
--- headers_invalid_ctr <= (others => '0');
--- dropped_ctr <= (others => '0');
--- invalid_hsize_ctr <= (others => '0');
--- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10
--- elsif (rst_regs = '1') then
--- invalid_hsize_lock <= '0';
--- elsif (drop_small = '1') then
--- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (drop_large = '1') then
--- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (drop_headers = '1') then
--- headers_invalid_ctr <= headers_invalid_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ??
--- invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
--- invalid_hsize_lock <= '1';
--- -- gk 01.10.10
--- elsif (found_empty_evt = '1') then
--- found_empty_evt_ctr <= found_empty_evt_ctr + x"1";
--- end if;
--- end if;
--- end process INVALID_STATS_PROC;
---
--- -- gk 05.08.10
--- INVALID_H_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- load_eod_q <= load_eod;
--- read_size_q <= read_size;
--- end if;
--- end process INVALID_H_PROC;
---
--- -- gk 26.04.10
--- READOUT_CTR_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then
--- readout_ctr <= READOUT_CTR_IN;
--- readout_ctr_lock <= '0';
--- elsif (pc_sos = '1') then
--- readout_ctr <= readout_ctr + x"1";
--- end if;
--- end if;
--- end process READOUT_CTR_PROC;
-
---******
--- SELECTION OF EVENT BUILDER
---******
-
--- gk 27.03.10
-bank_select_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- -- gk 29.03.10
- if( (RESET = '1') or (rst_regs = '1') ) then
- bank_select <= "0000";
- -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
- bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
- end if;
- end if;
-end process bank_select_proc;
-
--- gk 07.12.10
-first_event_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = WAIT_PC) then
- first_event <= '1';
- elsif (remove_done = '1') then
- first_event <= '0';
- end if;
- end if;
-end process first_event_proc;
-
--- gk 07.12.10
-prev_bank_proc : process(CLK)
-begin
- if (RESET = '1') or (loadCurrentState = WAIT_PC) then
- prev_bank_select <= "0000";
- elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then
- prev_bank_select <= bank_select;
- end if;
-end process prev_bank_proc;
-
-
--- gk 29.03.10
-start_config_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then
- start_config <= '0';
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1') ) then -- gk 01.06.10
- start_config <= '1';
- end if;
- end if;
-end process start_config_proc;
-
-
---******
--- LOAD SUBSUBEVENT
---******
-
--- gk 30.03.10
--- load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') )
--- else '0';
---
--- -- gk 30.03.10
--- LOAD_SUB_CTR_PROC: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
--- load_sub_ctr <= (others => '0');
--- elsif( (load_sub_ctr_comb = '1') ) then
--- load_sub_ctr <= load_sub_ctr + 1;
--- end if;
--- end if;
--- end process LOAD_SUB_CTR_PROC;
---
--- -- gk 30.03.10
--- -- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or
--- -- ((load_sub_ctr = x"4") and (drop_sub = '1'))
--- -- else '0';
--- load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0';
---
--- -- gk 30.03.10
--- LOAD_SUB_DONE_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
--- load_sub_done <= '0';
--- else
--- load_sub_done <= load_sub_done_comb;
--- end if;
--- end if;
--- end process LOAD_SUB_DONE_PROC;
---
--- --******
--- -- EXTRACT EVENT HEADERS FROM SPLITFIFO
--- --******
---
--- -- Counter for stripping the unneeded parts of the data stream, and saving the important parts
--- THE_REMOVE_CTR: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
--- rem_ctr <= (others => '0');
--- elsif( (ce_rem_ctr = '1') ) then
--- rem_ctr <= rem_ctr + 1;
--- end if;
--- end if;
--- end process THE_REMOVE_CTR;
---
--- remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address
---
--- THE_REM_DONE_SYNC: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
--- remove_done <= '0';
--- else
--- remove_done <= remove_done_comb;
--- end if;
--- end if;
--- end process THE_REM_DONE_SYNC;
---
--- -- gk 26.04.10
--- TRIG_RANDOM_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if ((RESET = '1') or (rst_regs = '1')) then
--- trig_random <= (others => '0');
--- elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then
--- trig_random <= pc_data;
--- end if;
--- end if;
--- end process TRIG_RANDOM_PROC;
---
--- -- extract the trigger number from splitfifo data
--- THE_TRG_NR_PROC: process( CLK )
--- begin
--- if rising_edge(CLK) then
--- if ( (RESET = '1') or (rst_regs = '1') ) then
--- pc_trig_nr <= (others => '0');
--- elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10
--- pc_trig_nr(7 downto 0) <= pc_data;
--- elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10
--- pc_trig_nr(15 downto 8) <= pc_data;
--- end if;
--- end if;
--- end process THE_TRG_NR_PROC;
---
--- -- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,
--- -- and in case of padding needed increase it accordingly
--- THE_SUB_SIZE_PROC: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_regs = '1') ) then
--- pc_sub_size <= (others => '0');
--- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
--- pc_sub_size(9 downto 2) <= pc_data;
--- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
--- pc_sub_size(17 downto 10) <= pc_data;
--- -- gk 20.07.10
--- -- gk 30.03.10 bug fixed in the way that is written below
--- -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save
--- elsif( (calc_pad = '1') and (padding_needed = '1') ) then
--- pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!!
--- elsif( (calc_pad = '1') and (padding_needed = '0') ) then
--- pc_sub_size <= pc_sub_size + x"8";
--- end if;
--- end if;
--- end process THE_SUB_SIZE_PROC;
---
--- -- gk 06.10.10
--- MESSAGE_SIZE_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- -- if (RESET = '1') then
--- -- message_size <= (others => '0');
--- -- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
--- -- message_size <= (others => '0');
--- -- elsif (pc_sos = '1') then
--- -- message_size <= message_size + pc_sub_size;
--- -- end if;
--- if (RESET = '1') then
--- message_size <= x"0000_0028";
--- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
--- message_size <= x"0000_0028";
--- elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then
--- message_size <= x"0000_0028";
--- elsif (pc_sos = '1') then
--- message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers
--- end if;
--- end if;
--- end process MESSAGE_SIZE_PROC;
---
---
--- -- gk 25.07.10
--- ENDP_ADDRESS_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (rst_regs = '1') then
--- endpoint_addr <= (others => '0');
--- endp_addr_lock <= '0';
--- elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then
--- endpoint_addr(7 downto 0) <= pc_data;
--- endp_addr_lock <= '1';
--- elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then
--- endpoint_addr(15 downto 8) <= pc_data;
--- endp_addr_lock <= '0';
--- end if;
--- end if;
--- end process ENDP_ADDRESS_PROC;
---
---
---
--- -- check for padding
--- THE_PADDING_NEEDED_PROC: process( CLK )
--- begin
--- if rising_edge(CLK) then
--- if ( (RESET = '1') or (rst_regs = '1') ) then
--- padding_needed <= '0';
--- elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then
--- padding_needed <= '1';
--- elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then
--- padding_needed <= '0';
--- end if;
--- end if;
--- end process THE_PADDING_NEEDED_PROC;
---
--- -- number of bytes to read from split fifo
--- THE_READ_SIZE_PROC: process( CLK )
--- begin
--- if( rising_edge(CLK) ) then
--- if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then
--- read_size <= (others => '0');
--- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
--- read_size(9 downto 2) <= pc_data;
--- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
--- read_size(17 downto 10) <= pc_data;
--- elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then
--- read_size <= read_size - 1;
--- -- gk 25.07.10
--- elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then
--- read_size <= read_size - 1;
--- end if;
--- end if;
--- end process THE_READ_SIZE_PROC;
---
--- read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2"
---
--- --******
--- -- EVENTS COUNTERS
--- --******
---
--- -- gk 25.07.10
--- LOADED_EVT_CTR_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- loaded_events_ctr <= (others => '0');
--- elsif (remove_done = '1') then
--- loaded_events_ctr <= loaded_events_ctr + x"1";
--- end if;
--- end if;
--- end process LOADED_EVT_CTR_PROC;
---
--- -- gk 25.07.10
--- CONSTR_EVENTS_CTR_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- constr_events_ctr <= (others => '0');
--- elsif (pc_eod = '1') then
--- constr_events_ctr <= constr_events_ctr + x"1";
--- end if;
--- end if;
--- end process CONSTR_EVENTS_CTR_PROC;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Debug signals
--- debug(0) <= sf_full;
--- debug(1) <= sf_empty;
--- debug(2) <= sf_afull;
--- debug(3) <= sf_aempty;
---
--- debug(7 downto 4) <= state2;
---
--- debug(11 downto 8) <= state;
---
--- dbg_bs_proc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(15 downto 12) <= (others => '0');
--- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
--- debug(15 downto 12) <= bank_select;
--- end if;
--- end if;
--- end process dbg_bs_proc;
---
--- debug(16) <= config_done;
--- debug(17) <= '0'; --remove_done;
--- debug(18) <= read_done;
--- debug(19) <= padding_needed;
---
--- debug(20) <= load_sub_done;
---
--- dbg_cts_inf_proc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(39 downto 32) <= (others => '0');
--- elsif ( save_addr = '1' ) then
--- debug(39 downto 32) <= CTS_INFORMATION_IN;
--- end if;
--- end if;
--- end process dbg_cts_inf_proc;
---
--- debug(47 downto 40) <= (others => '0');
---
---
--- debug(63 downto 48) <= actual_message_size(15 downto 0);
---
--- dbg_pc_sub_size_proc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(81 downto 64) <= (others => '0');
--- elsif (loadCurrentState = DECIDE) then
--- debug(81 downto 64) <= pc_sub_size;
--- end if;
--- end if;
--- end process dbg_pc_sub_size_proc;
---
--- dbg_empty_proc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (rst_regs = '1') then
--- debug(84 downto 82) <= (others => '0');
--- elsif (read_size = 2) then
--- debug(82) <= sf_empty;
--- elsif (read_size = 1) then
--- debug(83) <= sf_empty;
--- elsif (read_size = 0) then
--- debug(84) <= sf_empty;
--- end if;
--- end if;
--- end process dbg_empty_proc;
---
--- debug(95 downto 85) <= (others => '0');
---
--- dbg_inc_ctr_proc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(127 downto 96) <= (others => '1');
--- elsif (saveCurrentState = SCLOSE) then
--- debug(127 downto 96) <= inc_data_ctr;
--- end if;
--- end if;
--- end process dbg_inc_ctr_proc;
---
--- debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0);
--- debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0);
---
--- debug(175 downto 160) <= headers_invalid_ctr(15 downto 0);
--- debug(191 downto 176) <= (others => '0');
---
--- dbg_cts_q_proc : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- cts_len_q <= (others => '0');
--- cts_rnd_q <= (others => '0');
--- cts_trg_q <= (others => '0');
--- cts_addr_q <= (others => '0');
--- elsif (cts_len_saved = '1') then
--- cts_len_q <= cts_len(16 downto 1);
--- cts_addr_q <= cts_addr;
--- cts_rnd_q <= cts_rnd;
--- cts_trg_q <= cts_trg;
--- end if;
--- end if;
--- end process dbg_cts_q_proc;
---
--- debug(207 downto 192) <= cts_trg_q;
--- debug(223 downto 208) <= cts_rnd_q;
--- debug(239 downto 224) <= cts_addr_q;
--- debug(255 downto 240) <= cts_len_q;
--- debug(271 downto 256) <= first_run_trg;
--- debug(287 downto 272) <= first_run_addr;
---
--- debug(303 downto 288) <= saved_events_ctr;
--- debug(319 downto 304) <= loaded_events_ctr;
---
--- debug(335 downto 320) <= constr_events_ctr(15 downto 0);
--- debug(351 downto 336) <= dropped_ctr(15 downto 0);
---
--- debug(367 downto 352) <= invalid_hsize_ctr;
--- debug(383 downto 368) <= (others => '0');
---
--- MONITOR_OUT(31 downto 0) <= constr_events_ctr;
--- MONITOR_OUT(63 downto 32) <= dropped_ctr;
--- MONITOR_OUT(95 downto 64) <= headers_invalid_ctr;
--- MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr;
--- MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
--- MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000";
--- MONITOR_OUT(191 downto 164) <= (others => '0');
--- MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10
-
--- Outputs
-FEE_READ_OUT <= fee_read;
-CTS_ERROR_PATTERN_OUT <= cts_error_pattern;
-CTS_DATA_OUT <= cts_data;
-CTS_DATAREADY_OUT <= cts_dataready;
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
-CTS_LENGTH_OUT <= cts_length;
-
-PC_SOS_OUT <= pc_sos;
-PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1'))
- or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1'))
- -- gk 07.12.10
- or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1'))
- else '0'; -- gk 07.10.10
-PC_DATA_OUT <= pc_data_q;
-PC_WR_EN_OUT <= pc_wr_en_qq;
-
-PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random;
-
-PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size;
-PC_PADDING_OUT <= padding_needed;
-
-DEBUG_OUT <= debug;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
--- LinkStateMachine for SFPs (GigE)\r
-\r
--- Still missing: link reset features, fifo full error handling, signals on stat_op\r
--- Take care: all input signals must be synchronous to SYSCLK,\r
--- all output signals are synchronous to SYSCLK.\r
--- Clock Domain Crossing is in your responsibility!\r
-\r
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.std_logic_ARITH.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-library work;\r
---use work.trb_net_std.all;\r
-\r
-entity trb_net16_lsm_sfp_gbe is\r
-port( SYSCLK : in std_logic; -- fabric clock (100MHz)\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available\r
- -- status signals\r
- SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place)\r
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)\r
- SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)\r
- SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)\r
- SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)\r
- -- control signals\r
- FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset\r
- LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset\r
- USER_RESET_OUT : out std_logic; -- FPGA reset for user logic\r
- -- debug signals\r
- TIMING_CTR_OUT : out std_logic_vector(18 downto 0);\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-end entity;\r
-\r
-architecture lsm_sfp_gbe of trb_net16_lsm_sfp_gbe is\r
-\r
--- state machine signals\r
-type STATES is ( QRST, SLEEP, DELAY, USERRST, LINK );\r
-signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
-signal state_bits : std_logic_vector(3 downto 0);\r
-signal next_ce_tctr : std_logic;\r
-signal ce_tctr : std_logic;\r
-signal next_rst_tctr : std_logic;\r
-signal rst_tctr : std_logic;\r
-signal next_quad_rst : std_logic;\r
-signal quad_rst : std_logic;\r
-signal next_lane_rst : std_logic;\r
-signal lane_rst : std_logic;\r
-signal next_user_rst : std_logic;\r
-signal user_rst : std_logic;\r
-signal sfp_missing_q : std_logic;\r
-signal sfp_missing_qq : std_logic;\r
-signal sfp_los_q : std_logic;\r
-signal sfp_los_qq : std_logic;\r
-signal sd_rxclk_bad_q : std_logic;\r
-signal sd_rxclk_bad_qq : std_logic;\r
-signal sd_rxclk_bad_qqq : std_logic;\r
-signal sd_txclk_bad_q : std_logic;\r
-signal sd_txclk_bad_qq : std_logic;\r
-signal sd_txclk_bad_qqq : std_logic;\r
-signal sd_rxclk_warn_comb : std_logic;\r
-signal sd_rxclk_warn : std_logic; -- rising edge on rlol detected\r
-signal sd_txclk_warn_comb : std_logic;\r
-signal sd_txclk_warn : std_logic; -- rising edge on plol detected\r
-signal timing_ctr : std_logic_vector(18 downto 0);\r
-signal debug : std_logic_vector(31 downto 0);\r
-\r
-begin\r
-\r
--- Debug signals\r
-debug(31 downto 4) <= (others => '0');\r
-debug(3) <= sd_txclk_warn;\r
-debug(2) <= sd_rxclk_warn;\r
-debug(1) <= rst_tctr;\r
-debug(0) <= ce_tctr;\r
-\r
--- synchronize external signals from SFP\r
-THE_SYNC_PROC: process( sysclk )\r
-begin\r
- if( rising_edge(sysclk) ) then\r
- -- SFP input signals\r
- sfp_missing_qq <= sfp_missing_q;\r
- sfp_missing_q <= sfp_missing_in;\r
- sfp_los_qq <= sfp_los_q;\r
- sfp_los_q <= sfp_los_in;\r
- -- SerDes input signals\r
- sd_rxclk_bad_qqq <= sd_rxclk_bad_qq;\r
- sd_rxclk_bad_qq <= sd_rxclk_bad_q;\r
- sd_rxclk_bad_q <= sd_rxclk_bad_in;\r
- sd_txclk_bad_qqq <= sd_txclk_bad_q;\r
- sd_txclk_bad_qq <= sd_txclk_bad_q;\r
- sd_txclk_bad_q <= sd_txclk_bad_in;\r
- -- edge detectors\r
- sd_rxclk_warn <= sd_rxclk_warn_comb;\r
- sd_txclk_warn <= sd_txclk_warn_comb;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
--- combinatorial part of edge detectors (rlol, see remark on page 8-63 in HB1003.pdf)\r
-sd_rxclk_warn_comb <= '1' when ( (sd_rxclk_bad_qqq = '0') and (sd_rxclk_bad_qq = '1') ) else '0';\r
-sd_txclk_warn_comb <= '1' when ( (sd_txclk_bad_qqq = '0') and (sd_txclk_bad_qq = '1') ) else '0';\r
-\r
---------------------------------------------------------------------------\r
--- Main control state machine, startup control for SFP\r
---------------------------------------------------------------------------\r
-\r
--- Timing counter for reset sequencing\r
-THE_TIMING_COUNTER_PROC: process( sysclk, clear )\r
-begin\r
- if( clear = '1' ) then\r
- timing_ctr <= (others => '0');\r
- elsif( rising_edge(sysclk) ) then\r
- if ( (rst_tctr = '1') or (sd_rxclk_warn = '1') or (sd_txclk_warn = '1') ) then\r
- timing_ctr <= (others => '0');\r
- elsif( ce_tctr = '1' ) then\r
- timing_ctr <= timing_ctr + 1;\r
- end if;\r
- end if;\r
-end process THE_TIMING_COUNTER_PROC;\r
-\r
--- State machine\r
--- state registers\r
-STATE_MEM: process( sysclk, clear )\r
-begin\r
- if( clear = '1' ) then\r
- CURRENT_STATE <= QRST;\r
- ce_tctr <= '0';\r
- rst_tctr <= '0';\r
- quad_rst <= '1';\r
- lane_rst <= '1';\r
- user_rst <= '1';\r
- elsif( rising_edge(sysclk) ) then\r
- CURRENT_STATE <= NEXT_STATE;\r
- ce_tctr <= next_ce_tctr;\r
- rst_tctr <= next_rst_tctr;\r
- quad_rst <= next_quad_rst;\r
- lane_rst <= next_lane_rst;\r
- user_rst <= next_user_rst;\r
- end if;\r
-end process STATE_MEM;\r
-\r
--- state transitions\r
-PROC_STATE_TRANSFORM: process( CURRENT_STATE, sfp_missing_qq, sfp_los_qq, sd_txclk_bad_qqq, sd_rxclk_bad_qqq,\r
- timing_ctr(8), timing_ctr(18), timing_ctr(17),\r
- reset )\r
-begin\r
- NEXT_STATE <= QRST; -- avoid latches\r
- next_ce_tctr <= '0';\r
- next_rst_tctr <= '0';\r
- next_quad_rst <= '0';\r
- next_lane_rst <= '0';\r
- next_user_rst <= '0';\r
- case CURRENT_STATE is\r
- when QRST => -- initial state, we stay there unless CLEAR is deasserted.\r
- state_bits <= x"0";\r
- if( (timing_ctr(8) = '1') ) then\r
- NEXT_STATE <= SLEEP; -- release QUAD_RST, wait for lock of RxClock and TxClock\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- next_rst_tctr <= '1';\r
- else\r
- NEXT_STATE <= QRST; -- count delay\r
- next_ce_tctr <= '1';\r
- next_quad_rst <= '1';\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
- when SLEEP => -- we check for SFP presence and signal\r
- state_bits <= x"1";\r
- if( (sfp_missing_qq = '0') and (sfp_los_qq = '0') ) then\r
- NEXT_STATE <= DELAY; -- do a correctly timed QUAD reset (about 150ns)\r
- next_ce_tctr <= '1';\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- else\r
- NEXT_STATE <= SLEEP; -- wait for SFP present signal\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
- when DELAY => -- we wait approx. 4ms and check for PLL lock in the SerDes\r
- state_bits <= x"2";\r
- if( (timing_ctr(18) = '1') and (timing_ctr(17) = '1') and (sd_rxclk_bad_qqq = '0') and (sd_txclk_bad_qqq = '0') ) then\r
- NEXT_STATE <= USERRST; -- we release lane reset\r
- next_ce_tctr <= '1';\r
- next_user_rst <= '1';\r
- else\r
- NEXT_STATE <= DELAY;\r
- next_ce_tctr <= '1';\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
- when USERRST => -- short delay for user reset\r
- state_bits <= x"3";\r
- if( (timing_ctr(18) = '0') and (timing_ctr(17) = '0') ) then\r
- NEXT_STATE <= LINK;\r
- next_rst_tctr <= '1';\r
- else\r
- NEXT_STATE <= USERRST;\r
- next_ce_tctr <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
- when LINK => -- operational\r
- state_bits <= x"4";\r
- NEXT_STATE <= LINK;\r
- when others => \r
- NEXT_STATE <= QRST;\r
- end case;\r
- \r
- -- emergency jumps in case of SFP problems\r
- if( ((sfp_missing_qq = '1') or (sfp_los_qq = '1') or (RESET = '1')) and CURRENT_STATE /= QRST ) then\r
- NEXT_STATE <= SLEEP; -- wait for SFP present signal\r
- next_rst_tctr <= '1';\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
-end process;\r
-\r
---------------------------------------------------------------------------\r
--- Output signals\r
---------------------------------------------------------------------------\r
-full_reset_out <= quad_rst;\r
-lane_reset_out <= lane_rst;\r
-user_reset_out <= user_rst;\r
-\r
---------------------------------------------------------------------------\r
--- Debug output\r
---------------------------------------------------------------------------\r
-timing_ctr_out <= timing_ctr;\r
-bsm_out <= state_bits;\r
-debug_out <= debug;\r
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.std_logic_ARITH.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-\r
-use work.trb_net_gbe_components.all;\r
-\r
-entity trb_net16_med_ecp_sfp_gbe_8b is\r
--- gk 28.04.10\r
-generic (\r
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
-);\r
-port(\r
- RESET : in std_logic;\r
- GSR_N : in std_logic;\r
- CLK_125_OUT : out std_logic;\r
- CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk\r
- CLK_125_RX_OUT : out std_logic;\r
- --SGMII connection to frame transmitter (tsmac)\r
- FT_TX_CLK_EN_OUT : out std_logic;\r
- FT_RX_CLK_EN_OUT : out std_logic;\r
- FT_COL_OUT : out std_logic;\r
- FT_CRS_OUT : out std_logic;\r
- FT_TXD_IN : in std_logic_vector(7 downto 0);\r
- FT_TX_EN_IN : in std_logic;\r
- FT_TX_ER_IN : in std_logic;\r
-\r
- FT_RXD_OUT : out std_logic_vector(7 downto 0);\r
- FT_RX_EN_OUT : out std_logic;\r
- FT_RX_ER_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic; -- SFP disable\r
- -- Autonegotiation stuff \r
- MR_RESET_IN : in std_logic;\r
- MR_MODE_IN : in std_logic;\r
- MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); -- should be x"0020\r
- MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); -- advert page from link partner\r
- MR_AN_PAGE_RX_OUT : out std_logic;\r
- MR_AN_COMPLETE_OUT : out std_logic; \r
- MR_AN_ENABLE_IN : in std_logic;\r
- MR_RESTART_AN_IN : in std_logic;\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
-);\r
-end entity;\r
-\r
-architecture trb_net16_med_ecp_sfp_gbe_8b of trb_net16_med_ecp_sfp_gbe_8b is\r
-\r
--- Placer Directives\r
---attribute HGROUP : string;\r
--- for whole architecture\r
---attribute HGROUP of trb_net16_med_ecp_sfp_gbe_8b : architecture is "media_interface_group";\r
-attribute syn_sharing : string;\r
-attribute syn_sharing of trb_net16_med_ecp_sfp_gbe_8b : architecture is "off";\r
-\r
---component serdes_gbe_0ch is\r
-component serdes_ch4 is\r
- --GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0ch.txt");\r
-GENERIC (USER_CONFIG_FILE : String := "serdes_ch4.txt");\r
- port (\r
-------------------\r
--- CH0 --\r
- hdinp_ch3, hdinn_ch3 : in std_logic;\r
- hdoutp_ch3, hdoutn_ch3 : out std_logic;\r
- rxiclk_ch3 : in std_logic;\r
- txiclk_ch3 : in std_logic;\r
- rx_full_clk_ch3 : out std_logic;\r
- rx_half_clk_ch3 : out std_logic;\r
- tx_full_clk_ch3 : out std_logic;\r
- tx_half_clk_ch3 : out std_logic;\r
- fpga_rxrefclk_ch3 : in std_logic;\r
- txdata_ch3 : in std_logic_vector (7 downto 0);\r
- tx_k_ch3 : in std_logic;\r
- xmit_ch3 : in std_logic;\r
- tx_disp_correct_ch3 : in std_logic;\r
- rxdata_ch3 : out std_logic_vector (7 downto 0);\r
- rx_k_ch3 : out std_logic;\r
- rx_disp_err_ch3 : out std_logic;\r
- rx_cv_err_ch3 : out std_logic;\r
- rx_serdes_rst_ch3_c : in std_logic;\r
- sb_felb_ch3_c : in std_logic;\r
- sb_felb_rst_ch3_c : in std_logic;\r
- tx_pcs_rst_ch3_c : in std_logic;\r
- tx_pwrup_ch3_c : in std_logic;\r
- rx_pcs_rst_ch3_c : in std_logic;\r
- rx_pwrup_ch3_c : in std_logic;\r
- rx_los_low_ch3_s : out std_logic;\r
- lsm_status_ch3_s : out std_logic;\r
- rx_cdr_lol_ch3_s : out std_logic;\r
--- CH1 --\r
--- CH2 --\r
--- CH3 --\r
----- Miscillaneous ports\r
- fpga_txrefclk : in std_logic;\r
- tx_serdes_rst_c : in std_logic;\r
- tx_pll_lol_qd_s : out std_logic;\r
- rst_qd_c : in std_logic;\r
- serdes_rst_qd_c : in std_logic);\r
-\r
-end component;\r
-\r
-component serdes_gbe_0_extclock_8b is\r
-GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt");\r
-port( refclkp : in std_logic;\r
- refclkn : in std_logic;\r
- hdinp0 : in std_logic;\r
- hdinn0 : in std_logic;\r
- hdoutp0 : out std_logic;\r
- hdoutn0 : out std_logic;\r
- ff_rxiclk_ch0 : in std_logic;\r
- ff_txiclk_ch0 : in std_logic;\r
- ff_ebrd_clk_0 : in std_logic;\r
- ff_txdata_ch0 : in std_logic_vector (7 downto 0);\r
- ff_rxdata_ch0 : out std_logic_vector (7 downto 0);\r
- ff_tx_k_cntrl_ch0 : in std_logic;\r
- ff_rx_k_cntrl_ch0 : out std_logic;\r
- ff_rxfullclk_ch0 : out std_logic;\r
- ff_xmit_ch0 : in std_logic;\r
- ff_correct_disp_ch0 : in std_logic;\r
- ff_disp_err_ch0 : out std_logic;\r
- ff_cv_ch0 : out std_logic;\r
- ff_rx_even_ch0 : out std_logic;\r
- ffc_rrst_ch0 : in std_logic;\r
- ffc_lane_tx_rst_ch0 : in std_logic;\r
- ffc_lane_rx_rst_ch0 : in std_logic;\r
- ffc_txpwdnb_ch0 : in std_logic;\r
- ffc_rxpwdnb_ch0 : in std_logic;\r
- ffs_rlos_lo_ch0 : out std_logic;\r
- ffs_ls_sync_status_ch0 : out std_logic;\r
- ffs_rlol_ch0 : out std_logic;\r
- oob_out_ch0 : out std_logic;\r
- ffc_macro_rst : in std_logic;\r
- ffc_quad_rst : in std_logic;\r
- ffc_trst : in std_logic;\r
- ff_txfullclk : out std_logic;\r
- ff_txhalfclk : out std_logic;\r
- refck2core : out std_logic;\r
- ffs_plol : out std_logic\r
- );\r
-end component;\r
-\r
-component serdes_gbe_0_intclock_8b is\r
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt");\r
- port (\r
- core_txrefclk : in std_logic;\r
- core_rxrefclk : in std_logic;\r
- hdinp0, hdinn0 : in std_logic;\r
- hdoutp0, hdoutn0 : out std_logic;\r
- ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;\r
- ff_txdata_ch0 : in std_logic_vector (7 downto 0);\r
- ff_rxdata_ch0 : out std_logic_vector (7 downto 0);\r
- ff_tx_k_cntrl_ch0 : in std_logic;\r
- ff_rx_k_cntrl_ch0 : out std_logic;\r
- ff_rxfullclk_ch0 : out std_logic;\r
- ff_xmit_ch0 : in std_logic;\r
- ff_correct_disp_ch0 : in std_logic;\r
- ff_disp_err_ch0, ff_cv_ch0 : out std_logic;\r
- ff_rx_even_ch0 : out std_logic;\r
- ffc_rrst_ch0 : in std_logic;\r
- ffc_lane_tx_rst_ch0 : in std_logic;\r
- ffc_lane_rx_rst_ch0 : in std_logic;\r
- ffc_txpwdnb_ch0 : in std_logic;\r
- ffc_rxpwdnb_ch0 : in std_logic;\r
- ffs_rlos_lo_ch0 : out std_logic;\r
- ffs_ls_sync_status_ch0 : out std_logic;\r
- ffs_rlol_ch0 : out std_logic;\r
- oob_out_ch0 : out std_logic;\r
- ffc_macro_rst : in std_logic;\r
- ffc_quad_rst : in std_logic;\r
- ffc_trst : in std_logic;\r
- ff_txfullclk : out std_logic;\r
- ff_txhalfclk : out std_logic;\r
- ffs_plol : out std_logic);\r
-\r
-end component;\r
-\r
--- component sgmii_gbe_pcs34\r
--- port( rst_n : in std_logic;\r
--- signal_detect : in std_logic;\r
--- gbe_mode : in std_logic;\r
--- sgmii_mode : in std_logic;\r
--- operational_rate : in std_logic_vector(1 downto 0);\r
--- debug_link_timer_short : in std_logic;\r
--- rx_compensation_err : out std_logic;\r
--- tx_clk_125 : in std_logic; \r
--- tx_clock_enable_source : out std_logic;\r
--- tx_clock_enable_sink : in std_logic; \r
--- tx_d : in std_logic_vector(7 downto 0); \r
--- tx_en : in std_logic; \r
--- tx_er : in std_logic; \r
--- rx_clk_125 : in std_logic; \r
--- rx_clock_enable_source : out std_logic;\r
--- rx_clock_enable_sink : in std_logic; \r
--- rx_d : out std_logic_vector(7 downto 0); \r
--- rx_dv : out std_logic; \r
--- rx_er : out std_logic; \r
--- col : out std_logic; \r
--- crs : out std_logic; \r
--- tx_data : out std_logic_vector(7 downto 0); \r
--- tx_kcntl : out std_logic; \r
--- tx_disparity_cntl : out std_logic; \r
--- serdes_recovered_clk : in std_logic; \r
--- rx_data : in std_logic_vector(7 downto 0); \r
--- rx_even : in std_logic; \r
--- rx_kcntl : in std_logic; \r
--- rx_disp_err : in std_logic; \r
--- rx_cv_err : in std_logic; \r
--- rx_err_decode_mode : in std_logic; \r
--- mr_an_complete : out std_logic; \r
--- mr_page_rx : out std_logic; \r
--- mr_lp_adv_ability : out std_logic_vector(15 downto 0); \r
--- mr_main_reset : in std_logic; \r
--- mr_an_enable : in std_logic; \r
--- mr_restart_an : in std_logic; \r
--- mr_adv_ability : in std_logic_vector(15 downto 0) \r
--- );\r
--- end component;\r
-\r
-component sgmii_gbe_pcs35 --sgmii_gbe_pcs36 -- sgmii_gbe_pcs35\r
-port( rst_n : in std_logic;\r
- signal_detect : in std_logic;\r
- gbe_mode : in std_logic;\r
- sgmii_mode : in std_logic;\r
- operational_rate : in std_logic_vector(1 downto 0);\r
- debug_link_timer_short : in std_logic;\r
-\r
- force_isolate : in std_logic;\r
- force_loopback : in std_logic;\r
- force_unidir : in std_logic;\r
-\r
- rx_compensation_err : out std_logic;\r
-\r
- ctc_drop_flag : out std_logic;\r
- ctc_add_flag : out std_logic;\r
- an_link_ok : out std_logic;\r
-\r
- tx_clk_125 : in std_logic; \r
- tx_clock_enable_source : out std_logic;\r
- tx_clock_enable_sink : in std_logic; \r
- tx_d : in std_logic_vector(7 downto 0); \r
- tx_en : in std_logic; \r
- tx_er : in std_logic; \r
- rx_clk_125 : in std_logic; \r
- rx_clock_enable_source : out std_logic;\r
- rx_clock_enable_sink : in std_logic; \r
- rx_d : out std_logic_vector(7 downto 0); \r
- rx_dv : out std_logic; \r
- rx_er : out std_logic; \r
- col : out std_logic; \r
- crs : out std_logic; \r
- tx_data : out std_logic_vector(7 downto 0); \r
- tx_kcntl : out std_logic; \r
- tx_disparity_cntl : out std_logic; \r
-\r
- xmit_autoneg : out std_logic;\r
-\r
- serdes_recovered_clk : in std_logic; \r
- rx_data : in std_logic_vector(7 downto 0); \r
- rx_even : in std_logic; \r
- rx_kcntl : in std_logic; \r
- rx_disp_err : in std_logic; \r
- rx_cv_err : in std_logic; \r
- rx_err_decode_mode : in std_logic; \r
- mr_an_complete : out std_logic; \r
- mr_page_rx : out std_logic; \r
- mr_lp_adv_ability : out std_logic_vector(15 downto 0); \r
- mr_main_reset : in std_logic; \r
- mr_an_enable : in std_logic; \r
- mr_restart_an : in std_logic; \r
- mr_adv_ability : in std_logic_vector(15 downto 0) \r
- );\r
-end component;\r
-\r
-component trb_net16_lsm_sfp_gbe is\r
-port( SYSCLK : in std_logic; -- fabric clock (100MHz)\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available\r
- -- status signals\r
- SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place)\r
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)\r
- SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)\r
- SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)\r
- SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)\r
- -- control signals\r
- FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset\r
- LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset\r
- USER_RESET_OUT : out std_logic; -- FPGA reset for user logic\r
- -- debug signals\r
- TIMING_CTR_OUT : out std_logic_vector(18 downto 0);\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-component reset_controller_pcs port (\r
- rst_n : in std_logic;\r
- clk : in std_logic;\r
- tx_plol : in std_logic; \r
- rx_cdr_lol : in std_logic; \r
- quad_rst_out : out std_logic; \r
- tx_pcs_rst_out : out std_logic; \r
- rx_pcs_rst_out : out std_logic\r
- );\r
-end component;\r
-component reset_controller_cdr port (\r
- rst_n : in std_logic;\r
- clk : in std_logic;\r
- cdr_lol : in std_logic; \r
- cdr_rst_out : out std_logic\r
- );\r
-end component;\r
-\r
-component rate_resolution port (\r
- gbe_mode : in std_logic;\r
- sgmii_mode : in std_logic;\r
- an_enable : in std_logic; \r
- advertised_rate : in std_logic_vector(1 downto 0);\r
- link_partner_rate : in std_logic_vector(1 downto 0);\r
- non_an_rate : in std_logic_vector(1 downto 0);\r
- operational_rate : out std_logic_vector(1 downto 0) \r
- );\r
-end component;\r
-\r
-component register_interface_hb port (\r
- rst_n : in std_logic;\r
- hclk : in std_logic;\r
- gbe_mode : in std_logic;\r
- sgmii_mode : in std_logic;\r
- hcs_n : in std_logic;\r
- hwrite_n : in std_logic;\r
- haddr : in std_logic_vector(3 downto 0);\r
- hdatain : in std_logic_vector(7 downto 0);\r
- hdataout : out std_logic_vector(7 downto 0); \r
- hready_n : out std_logic;\r
- mr_an_complete : in std_logic; \r
- mr_page_rx : in std_logic; \r
- mr_lp_adv_ability : in std_logic_vector(15 downto 0); \r
- mr_main_reset : out std_logic; \r
- mr_an_enable : out std_logic; \r
- mr_restart_an : out std_logic; \r
- mr_adv_ability : out std_logic_vector(15 downto 0) \r
- );\r
-end component;\r
-\r
-component sgmii33 port (\r
- rst_n : in std_logic;\r
- signal_detect : in std_logic;\r
- gbe_mode : in std_logic;\r
- sgmii_mode : in std_logic;\r
- --force_isolate : in std_logic;\r
- --force_loopback : in std_logic;\r
- --force_unidir : in std_logic;\r
- operational_rate : in std_logic_vector(1 downto 0);\r
- debug_link_timer_short : in std_logic;\r
- rx_compensation_err : out std_logic;\r
- --ctc_drop_flag : out std_logic;\r
- --ctc_add_flag : out std_logic;\r
- --an_link_ok : out std_logic;\r
- tx_clk_125 : in std_logic; \r
- tx_clock_enable_source : out std_logic;\r
- tx_clock_enable_sink : in std_logic; \r
- tx_d : in std_logic_vector(7 downto 0); \r
- tx_en : in std_logic; \r
- tx_er : in std_logic; \r
- rx_clk_125 : in std_logic; \r
- rx_clock_enable_source : out std_logic;\r
- rx_clock_enable_sink : in std_logic; \r
- rx_d : out std_logic_vector(7 downto 0); \r
- rx_dv : out std_logic; \r
- rx_er : out std_logic; \r
- col : out std_logic; \r
- crs : out std_logic; \r
- tx_data : out std_logic_vector(7 downto 0); \r
- tx_kcntl : out std_logic; \r
- tx_disparity_cntl : out std_logic; \r
- --xmit_autoneg : out std_logic; \r
- serdes_recovered_clk : in std_logic; \r
- rx_data : in std_logic_vector(7 downto 0); \r
- rx_even : in std_logic; \r
- rx_kcntl : in std_logic; \r
- rx_disp_err : in std_logic; \r
- rx_cv_err : in std_logic; \r
- rx_err_decode_mode : in std_logic; \r
- mr_an_complete : out std_logic; \r
- mr_page_rx : out std_logic; \r
- mr_lp_adv_ability : out std_logic_vector(15 downto 0); \r
- mr_main_reset : in std_logic; \r
- mr_an_enable : in std_logic; \r
- mr_restart_an : in std_logic; \r
- mr_adv_ability : in std_logic_vector(15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-signal refclkcore : std_logic;\r
-\r
-signal sd_link_ok : std_logic;\r
-signal sd_link_error : std_logic_vector(2 downto 0);\r
-\r
-signal sd_tx_data : std_logic_vector(7 downto 0);\r
-signal sd_tx_kcntl : std_logic;\r
-signal sd_tx_correct_disp : std_logic;\r
-signal sd_tx_clk : std_logic;\r
-\r
-signal sd_rx_data : std_logic_vector(7 downto 0);\r
-signal sd_rx_even : std_logic;\r
-signal sd_rx_kcntl : std_logic;\r
-signal sd_rx_disp_error : std_logic;\r
-signal sd_rx_cv_error : std_logic;\r
-signal sd_rx_clk : std_logic;\r
-\r
-signal sd_tx_data_q : std_logic_vector(7 downto 0);\r
-signal sd_tx_kcntl_q : std_logic;\r
-signal sd_tx_correct_disp_q : std_logic;\r
-\r
-signal sd_rx_data_q : std_logic_vector(7 downto 0);\r
-signal sd_rx_kcntl_q : std_logic;\r
-signal sd_rx_disp_error_q : std_logic;\r
-signal sd_rx_cv_error_q : std_logic;\r
-\r
-signal pcs_mr_an_complete : std_logic;\r
-signal pcs_mr_ability : std_logic_vector(15 downto 0);\r
-signal pcs_mr_page_rx : std_logic;\r
-signal pcs_mr_reset : std_logic;\r
-\r
-signal pcs_tx_clk_en : std_logic;\r
-signal pcs_rx_clk_en : std_logic;\r
-signal pcs_rx_comp_err : std_logic;\r
-\r
-signal pcs_rx_d : std_logic_vector(7 downto 0);\r
-signal pcs_rx_dv : std_logic;\r
-signal pcs_rx_er : std_logic;\r
-\r
-signal sd_rx_debug : std_logic_vector(15 downto 0);\r
-signal sd_tx_debug : std_logic_vector(15 downto 0);\r
-\r
-signal buf_stat_debug : std_logic_vector(63 downto 0);\r
-\r
-signal quad_rst : std_logic;\r
-signal lane_rst : std_logic;\r
-signal user_rst : std_logic;\r
-\r
-signal reset_bsm : std_logic_vector(3 downto 0);\r
-signal reset_debug : std_logic_vector(31 downto 0);\r
-signal test_clk : std_logic;\r
-\r
-signal xmit : std_logic;\r
-signal signal_detected, compensation_err, tx_clk_en, rx_clk_en, rst_n, an_complete : std_logic;\r
-signal tx_pll_lol, rx_cdr_lol, los, tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic;\r
-\r
-signal operational_rate : std_logic_vector(1 downto 0);\r
-\r
-signal mr_an_enable, mr_restart_an, mr_main_reset, mr_page_rx : std_logic;\r
-signal mr_lp_adv_ability, mr_adv_ability : std_logic_vector(15 downto 0);\r
-\r
-\r
- attribute syn_keep : boolean;\r
- attribute syn_preserve : boolean;\r
-\r
- --attribute syn_keep of sd_tx_clk : signal is true;\r
- --attribute syn_preserve of sd_tx_clk : signal is true;\r
- attribute syn_keep of sd_rx_clk : signal is true;\r
- attribute syn_preserve of sd_rx_clk : signal is true;\r
- \r
- attribute syn_keep of sd_tx_correct_disp_q, sd_tx_kcntl_q, sd_tx_data_q, sd_rx_data_q, sd_rx_cv_error_q, sd_rx_disp_error_q, sd_rx_kcntl_q : signal is true;\r
- attribute syn_preserve of sd_tx_correct_disp_q, sd_tx_kcntl_q, sd_tx_data_q, sd_rx_data_q, sd_rx_cv_error_q, sd_rx_disp_error_q, sd_rx_kcntl_q : signal is true;\r
-\r
-begin\r
-\r
--- Reset state machine for SerDes\r
--- THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe\r
--- port map(\r
--- SYSCLK => CLK_125_IN,\r
--- RESET => '0', -- really?\r
--- CLEAR => RESET, -- from 100MHz PLL, includes async part\r
--- -- status signals\r
--- SFP_MISSING_IN => SD_PRSNT_N_IN,\r
--- SFP_LOS_IN => SD_LOS_IN,\r
--- SD_LINK_OK_IN => '1', -- not used\r
--- SD_LOS_IN => '0', -- not used\r
--- SD_TXCLK_BAD_IN => sd_link_error(2), -- plol\r
--- SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol\r
--- -- control signals\r
--- FULL_RESET_OUT => quad_rst,\r
--- LANE_RESET_OUT => lane_rst,\r
--- USER_RESET_OUT => user_rst,\r
--- -- debug signals\r
--- TIMING_CTR_OUT => open,\r
--- BSM_OUT => reset_bsm,\r
--- DEBUG_OUT => reset_debug\r
--- );\r
-\r
--- gk 28.04.10\r
--- SerDes for GbE\r
-clk_int : if (USE_125MHZ_EXTCLK = 0) generate\r
-\r
- refclkcore <= CLK_125_IN; --sd_tx_clk; --CLK_125_IN;\r
-\r
--- SERDES_GBE : serdes_gbe_0_intclock_8b\r
--- port map(\r
--- core_txrefclk => CLK_125_IN,\r
--- core_rxrefclk => CLK_125_IN,\r
--- hdinp0 => SD_RXD_P_IN,\r
--- hdinn0 => SD_RXD_N_IN,\r
--- hdoutp0 => SD_TXD_P_OUT,\r
--- hdoutn0 => SD_TXD_N_OUT,\r
--- ff_rxiclk_ch0 => sd_rx_clk,\r
--- ff_txiclk_ch0 => sd_tx_clk,\r
--- ff_ebrd_clk_0 => sd_rx_clk,\r
--- ff_txdata_ch0 => sd_tx_data,\r
--- ff_rxdata_ch0 => sd_rx_data,\r
--- ff_tx_k_cntrl_ch0 => sd_tx_kcntl,\r
--- ff_rx_k_cntrl_ch0 => sd_rx_kcntl,\r
--- ff_rxfullclk_ch0 => sd_rx_clk,\r
--- ff_xmit_ch0 => '0',\r
--- ff_correct_disp_ch0 => sd_tx_correct_disp,\r
--- ff_disp_err_ch0 => sd_rx_disp_error,\r
--- ff_cv_ch0 => sd_rx_cv_error,\r
--- ff_rx_even_ch0 => sd_rx_even,\r
--- ffc_rrst_ch0 => '0',\r
--- ffc_lane_tx_rst_ch0 => lane_rst,\r
--- ffc_lane_rx_rst_ch0 => lane_rst,\r
--- ffc_txpwdnb_ch0 => '1',\r
--- ffc_rxpwdnb_ch0 => '1',\r
--- ffs_rlos_lo_ch0 => sd_link_error(0),\r
--- ffs_ls_sync_status_ch0 => sd_link_ok,\r
--- ffs_rlol_ch0 => sd_link_error(1),\r
--- oob_out_ch0 => open,\r
--- ffc_macro_rst => '0',\r
--- ffc_quad_rst => quad_rst,\r
--- ffc_trst => '0',\r
--- ff_txfullclk => sd_tx_clk,\r
--- ff_txhalfclk => open,\r
--- ffs_plol => sd_link_error(2)\r
--- );\r
-\r
- --SERDES_GBE : serdes_gbe_0ch\r
- SERDES_GBE : serdes_ch4\r
- port map(\r
- ------------------\r
- -- CH0 --\r
- hdinp_ch3 => SD_RXD_P_IN,\r
- hdinn_ch3 => SD_RXD_N_IN,\r
- hdoutp_ch3 => SD_TXD_P_OUT,\r
- hdoutn_ch3 => SD_TXD_N_OUT,\r
- rxiclk_ch3 => sd_rx_clk,\r
- txiclk_ch3 => CLK_125_IN, --sd_tx_clk,\r
- rx_full_clk_ch3 => sd_rx_clk,\r
- rx_half_clk_ch3 => open,\r
- tx_full_clk_ch3 => open, --sd_tx_clk,\r
- tx_half_clk_ch3 => open,\r
- fpga_rxrefclk_ch3 => CLK_125_IN,\r
- txdata_ch3 => sd_tx_data_q,\r
- tx_k_ch3 => sd_tx_kcntl_q,\r
- xmit_ch3 => xmit, --'0',\r
- tx_disp_correct_ch3 => sd_tx_correct_disp_q,\r
- rxdata_ch3 => sd_rx_data, \r
- rx_k_ch3 => sd_rx_kcntl,\r
- rx_disp_err_ch3 => sd_rx_disp_error,\r
- rx_cv_err_ch3 => sd_rx_cv_error,\r
- rx_serdes_rst_ch3_c => rx_serdes_rst,\r
- sb_felb_ch3_c => '0',\r
- sb_felb_rst_ch3_c => '0',\r
- tx_pcs_rst_ch3_c => tx_pcs_rst,\r
- tx_pwrup_ch3_c => '1',\r
- rx_pcs_rst_ch3_c => rx_pcs_rst,\r
- rx_pwrup_ch3_c => '1',\r
- rx_los_low_ch3_s => los,\r
- lsm_status_ch3_s => signal_detected,\r
- rx_cdr_lol_ch3_s => rx_cdr_lol,\r
- -- CH1 --\r
- -- CH2 --\r
- -- CH3 --\r
- ---- Miscillaneous ports\r
- fpga_txrefclk => CLK_125_IN,\r
- tx_serdes_rst_c => '0',\r
- tx_pll_lol_qd_s => tx_pll_lol,\r
- rst_qd_c => quad_rst,\r
- serdes_rst_qd_c => '0'\r
- );\r
-\r
-\r
-end generate clk_int;\r
-\r
-clk_ext : if (USE_125MHZ_EXTCLK = 1) generate\r
- --SERDES_GBE : serdes_gbe_0_extclock_8b\r
- SERDES_GBE : serdes_gbe_0_extclock_8b \r
- port map( -- SerDes connection to outside world\r
- refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input\r
- refclkn => SD_REFCLK_N_IN,\r
- hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input\r
- hdinn0 => SD_RXD_N_IN,\r
- hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output\r
- hdoutn0 => SD_TXD_N_OUT,\r
- refck2core => refclkcore, -- reference clock from input\r
- -- RX part\r
- ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output\r
- ff_rxiclk_ch0 => sd_rx_clk,\r
- ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice\r
- ff_rxdata_ch0 => sd_rx_data, -- RX data output\r
- ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output\r
- ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output)\r
- ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error\r
- ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error\r
- -- TX part\r
- ff_txfullclk => sd_tx_clk, -- TX full clock output\r
- ff_txiclk_ch0 => sd_tx_clk, \r
- ff_txhalfclk => open,\r
- ff_txdata_ch0 => sd_tx_data, -- TX data input\r
- ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input\r
- ff_xmit_ch0 => '0', -- for autonegotiation (input)\r
- ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input)\r
- -- Resets and power down\r
- ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high)\r
- ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel\r
- ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel\r
- ffc_rrst_ch0 => '0', -- '0' for normal operation\r
- ffc_macro_rst => '0', -- '0' for normal operation\r
- ffc_trst => '0', -- '0' for normal operation\r
- ffc_txpwdnb_ch0 => '1', -- must be '1'\r
- ffc_rxpwdnb_ch0 => '1', -- must be '1'\r
- -- Status outputs\r
- ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas?\r
- ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel\r
- ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL\r
- ffs_plol => sd_link_error(2), -- loss of lock in TX PLL\r
- oob_out_ch0 => open -- not needed\r
- );\r
-end generate clk_ext;\r
-\r
---SD_RX_DATA_PROC: process( sd_rx_clk )\r
---begin\r
--- if( rising_edge(sd_rx_clk) ) then\r
--- sd_rx_debug(15 downto 12) <= (others => '0');\r
--- sd_rx_debug(11) <= sd_rx_disp_error;\r
--- sd_rx_debug(10) <= sd_rx_even;\r
--- sd_rx_debug(9) <= sd_rx_cv_error;\r
--- sd_rx_debug(8) <= sd_rx_kcntl;\r
--- sd_rx_debug(7 downto 0) <= sd_rx_data;\r
--- end if;\r
---end process SD_RX_DATA_PROC;\r
---\r
---SD_TX_DATA_PROC: process( CLK_125_IN) --sd_tx_clk )\r
---begin\r
--- if( rising_edge(CLK_125_IN)) then --sd_tx_clk) ) then\r
--- sd_tx_debug(15 downto 10) <= (others => '0');\r
--- sd_tx_debug(9) <= sd_tx_correct_disp;\r
--- sd_tx_debug(8) <= sd_tx_kcntl;\r
--- sd_tx_debug(7 downto 0) <= sd_tx_data;\r
--- end if;\r
---end process SD_TX_DATA_PROC;\r
-\r
-buf_stat_debug(63 downto 40) <= (others => '0');\r
-buf_stat_debug(39 downto 36) <= reset_debug(3 downto 0);\r
-buf_stat_debug(35 downto 32) <= reset_bsm;\r
--- logic analyzer signals\r
-buf_stat_debug(31) <= pcs_mr_page_rx;\r
-buf_stat_debug(30) <= pcs_mr_reset; --pcs_mr_an_complete;\r
-buf_stat_debug(28 downto 26) <= reset_bsm(2 downto 0);\r
-buf_stat_debug(25 downto 23) <= sd_link_error(2 downto 0);\r
-buf_stat_debug(22) <= sd_link_ok;\r
-buf_stat_debug(21 downto 12) <= sd_tx_debug(9 downto 0);\r
-buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0);\r
-\r
-\r
---SGMII_GBE_PCS : sgmii33 port map (\r
--- rst_n => GSR_N,\r
--- signal_detect => signal_detected,\r
--- gbe_mode => '1',\r
--- sgmii_mode => '0',\r
--- operational_rate => operational_rate,\r
--- debug_link_timer_short => '0',\r
--- rx_compensation_err => compensation_err,\r
--- tx_clk_125 => CLK_125_IN,\r
--- tx_clock_enable_source => tx_clk_en,\r
--- tx_clock_enable_sink => tx_clk_en,\r
--- tx_d => FT_TXD_IN, --pcs_rxd, --pcs_txd,\r
--- tx_en => FT_TX_EN_IN, --pcs_rx_dv, --pcs_tx_en, \r
--- tx_er => FT_TX_ER_IN, --pcs_rx_er, --pcs_tx_er, \r
--- rx_clk_125 => CLK_125_IN,\r
--- rx_clock_enable_source => rx_clk_en,\r
--- rx_clock_enable_sink => rx_clk_en, \r
--- rx_d => pcs_rx_d,\r
--- rx_dv => pcs_rx_dv,\r
--- rx_er => pcs_rx_er, \r
--- col => FT_COL_OUT,\r
--- crs => FT_CRS_OUT,\r
--- tx_data => sd_tx_data,\r
--- tx_kcntl => sd_tx_kcntl,\r
--- tx_disparity_cntl => sd_tx_correct_disp,\r
--- serdes_recovered_clk => sd_rx_clk,\r
--- rx_data => sd_rx_data_q,\r
--- rx_even => '0',\r
--- rx_kcntl => sd_rx_kcntl_q,\r
--- rx_disp_err => sd_rx_disp_error_q,\r
--- rx_cv_err => sd_rx_cv_error_q,\r
--- rx_err_decode_mode => '0',\r
--- mr_an_complete => an_complete,\r
--- mr_page_rx => mr_page_rx,\r
--- mr_lp_adv_ability => mr_lp_adv_ability,\r
--- mr_main_reset => mr_main_reset, --reset_i,\r
--- mr_an_enable => '1', --'1',\r
--- mr_restart_an => mr_restart_an,\r
--- mr_adv_ability => mr_adv_ability --x"0020"\r
--- );\r
- \r
- SYNC_TX_PROC : process(CLK_125_IN)\r
- begin\r
- if rising_edge(CLK_125_IN) then\r
- sd_tx_data_q <= sd_tx_data;\r
- sd_tx_kcntl_q <= sd_tx_kcntl;\r
- sd_tx_correct_disp_q <= sd_tx_correct_disp;\r
- end if;\r
- end process SYNC_TX_PROC;\r
- \r
- SYNC_RX_PROC : process(sd_rx_clk)\r
- begin\r
- if rising_edge(sd_rx_clk) then\r
- sd_rx_data_q <= sd_rx_data;\r
- sd_rx_kcntl_q <= sd_rx_kcntl;\r
- sd_rx_disp_error_q <= sd_rx_disp_error;\r
- sd_rx_cv_error_q <= sd_rx_cv_error;\r
- end if;\r
- end process SYNC_RX_PROC;\r
- \r
- \r
-\r
- \r
- SGMII_GBE_PCS : sgmii_gbe_pcs35 --sgmii_gbe_pcs36 --sgmii_gbe_pcs35\r
- port map(\r
- rst_n => rst_n, --GSR_N,\r
- signal_detect => signal_detected,\r
- gbe_mode => '1',\r
- sgmii_mode => '0',\r
- operational_rate => operational_rate,\r
- debug_link_timer_short => '0',\r
- \r
- force_isolate => '0',\r
- force_loopback => '0',\r
- force_unidir => '0',\r
- \r
- rx_compensation_err => compensation_err,\r
- \r
- ctc_drop_flag => open,\r
- ctc_add_flag => open,\r
- an_link_ok => open,\r
- \r
- -- MAC interface\r
- tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes\r
- tx_clock_enable_source => tx_clk_en,\r
- tx_clock_enable_sink => tx_clk_en,\r
- tx_d => FT_TXD_IN, -- TX data from MAC\r
- tx_en => FT_TX_EN_IN, -- TX data enable from MAC\r
- tx_er => FT_TX_ER_IN, -- TX error from MAC\r
- rx_clk_125 => sd_rx_clk, --CLK_125_IN, --refclkcore, -- original clock from SerDes\r
- rx_clock_enable_source => rx_clk_en,\r
- rx_clock_enable_sink => rx_clk_en,\r
- rx_d => pcs_rx_d, -- RX data to MAC\r
- rx_dv => pcs_rx_dv, -- RX data enable to MAC\r
- rx_er => pcs_rx_er, -- RX error to MAC\r
- col => FT_COL_OUT,\r
- crs => FT_CRS_OUT,\r
- -- SerDes interface\r
- tx_data => sd_tx_data, -- TX data to SerDes\r
- tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes\r
- tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes)\r
- \r
- xmit_autoneg => xmit,\r
- \r
- serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream\r
- rx_data => sd_rx_data_q, -- RX data from SerDes\r
- rx_kcntl => sd_rx_kcntl_q, -- RX komma control from SerDes\r
- rx_err_decode_mode => '0', -- receive error control mode fixed to normal\r
- rx_even => '0', -- unused (receive error control mode = normal, tie to GND)\r
- rx_disp_err => sd_rx_disp_error_q, -- RX disparity error from SerDes\r
- rx_cv_err => sd_rx_cv_error_q, -- RX code violation error from SerDes\r
- -- Autonegotiation stuff\r
- mr_an_complete => an_complete,\r
- mr_page_rx => mr_page_rx,\r
- mr_lp_adv_ability => mr_lp_adv_ability,\r
- mr_main_reset => mr_main_reset,\r
- mr_an_enable => '1',\r
- mr_restart_an => mr_restart_an,\r
- mr_adv_ability => mr_adv_ability\r
- );\r
-\r
-rst_n <= not RESET;\r
-\r
---SYNC_RX_PROC : process(sd_rx_clk)\r
---begin\r
--- if rising_edge(sd_rx_clk) then\r
- FT_RXD_OUT <= pcs_rx_d;\r
- FT_RX_EN_OUT <= pcs_rx_dv;\r
- FT_RX_ER_OUT <= pcs_rx_er;\r
--- end if;\r
---end process SYNC_RX_PROC;\r
-\r
-u0_reset_controller_pcs : reset_controller_pcs port map(\r
- rst_n => rst_n,\r
- clk => CLK_125_IN,\r
- tx_plol => tx_pll_lol,\r
- rx_cdr_lol => rx_cdr_lol,\r
- quad_rst_out => quad_rst,\r
- tx_pcs_rst_out => tx_pcs_rst,\r
- rx_pcs_rst_out => rx_pcs_rst\r
-);\r
-\r
-u0_reset_controller_cdr : reset_controller_cdr port map(\r
- rst_n => rst_n,\r
- clk => CLK_125_IN,\r
- cdr_lol => rx_cdr_lol,\r
- cdr_rst_out => rx_serdes_rst\r
-);\r
-\r
-u0_rate_resolution : rate_resolution port map(\r
- gbe_mode => '1',\r
- sgmii_mode => '0',\r
- an_enable => '1',\r
- advertised_rate => mr_adv_ability(11 downto 10),\r
- link_partner_rate => mr_lp_adv_ability(11 downto 10),\r
- non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled\r
- \r
- operational_rate => operational_rate\r
-);\r
-\r
-u0_ri : register_interface_hb port map(\r
- -- Control Signals\r
- rst_n => rst_n,\r
- hclk => CLK_125_IN,\r
- gbe_mode => '1',\r
- sgmii_mode => '0',\r
- \r
- -- Host Bus\r
- hcs_n => '1',\r
- hwrite_n => '1',\r
- haddr => (others => '0'),\r
- hdatain => (others => '0'),\r
- \r
- hdataout => open,\r
- hready_n => open,\r
-\r
- -- Register Outputs\r
- mr_an_enable => mr_an_enable,\r
- mr_restart_an => mr_restart_an,\r
- mr_main_reset => mr_main_reset,\r
- mr_adv_ability => mr_adv_ability,\r
-\r
- -- Register Inputs\r
- mr_an_complete => an_complete,\r
- mr_page_rx => mr_page_rx,\r
- mr_lp_adv_ability => mr_lp_adv_ability\r
- );\r
-\r
-\r
-\r
-pcs_mr_reset <= MR_RESET_IN or RESET or user_rst;\r
-\r
-FT_TX_CLK_EN_OUT <= tx_clk_en; -- to MAC\r
-FT_RX_CLK_EN_OUT <= rx_clk_en; -- to MAC\r
-\r
-MR_AN_LP_ABILITY_OUT <= pcs_mr_ability;\r
-MR_AN_COMPLETE_OUT <= an_complete;\r
-MR_AN_PAGE_RX_OUT <= pcs_mr_page_rx;\r
-\r
--- Clock games\r
-CLK_125_OUT <= CLK_125_IN; --sd_tx_clk;\r
-CLK_125_RX_OUT <= sd_rx_clk;\r
-\r
--- Fakes\r
-STAT_OP <= (others => '0');\r
-SD_TXDIS_OUT <= '0'; -- enable \r
-STAT_DEBUG <= buf_stat_debug;\r
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-library work;
-use work.trb_net_std.all;
-
-use work.trb_net_gbe_protocols.all;
-
-package trb_net_gbe_components is
-
-
-
-component trb_net16_gbe_transmit_control2 is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
-
--- signal to/from main controller
- TC_DATAREADY_IN : in std_logic;
- TC_RD_EN_OUT : out std_logic;
- TC_DATA_IN : in std_logic_vector(7 downto 0);
- TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- TC_DEST_MAC_IN : in std_logic_vector(47 downto 0);
- TC_DEST_IP_IN : in std_logic_vector(31 downto 0);
- TC_DEST_UDP_IN : in std_logic_vector(15 downto 0);
- TC_SRC_MAC_IN : in std_logic_vector(47 downto 0);
- TC_SRC_IP_IN : in std_logic_vector(31 downto 0);
- TC_SRC_UDP_IN : in std_logic_vector(15 downto 0);
- TC_IDENT_IN : in std_logic_vector(15 downto 0);
- TC_TRANSMISSION_DONE_OUT : out std_logic;
- TC_MAX_FRAME_IN : in std_logic_vector(15 downto 0);
-
--- signal to/from frame constructor
- FC_DATA_OUT : out std_logic_vector(7 downto 0);
- FC_WR_EN_OUT : out std_logic;
- FC_READY_IN : in std_logic;
- FC_H_READY_IN : in std_logic;
- FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- FC_SOD_OUT : out std_logic;
- FC_EOD_OUT : out std_logic;
- FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
-
- DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
- MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0)
-);
-end component;
-
-component trb_net16_gbe_event_constr is
-port(
- RESET : in std_logic;
- CLK : in std_logic;
- -- ports for user logic
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
- PC_DATA_IN : in std_logic_vector(7 downto 0);
- PC_READY_OUT : out std_logic;
- PC_START_OF_SUB_IN : in std_logic;
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10
- PC_END_OF_QUEUE_IN : in std_logic;
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
- PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
- PC_INSERT_TTYPE_IN : in std_logic;
- -- FrameConstructor ports
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_SOD_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_ipu_interface is
- port (
- CLK_IPU : in std_logic;
- CLK_GBE : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_SUBEVENT_SIZE_IN : in std_logic_vector(15 downto 0);
- MAX_QUEUE_SIZE_IN : in std_logic_vector(15 downto 0);
- MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- MAX_SINGLE_SUB_SIZE_IN : in std_logic_vector(15 downto 0);
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- -- PacketConstructor interface
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic;
- PC_EOQ_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0);
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
- );
-end component;
-
-component gbe_ipu_dummy is
- generic (
- DO_SIMULATION : integer range 0 to 1 := 0;
- FIXED_SIZE_MODE : integer range 0 to 1 := 1;
- INCREMENTAL_MODE : integer range 0 to 1 := 0;
- FIXED_SIZE : integer range 0 to 65535 := 10;
- FIXED_DELAY_MODE : integer range 0 to 1 := 1;
- UP_DOWN_MODE : integer range 0 to 1 := 0;
- UP_DOWN_LIMIT : integer range 0 to 16777215 := 0;
- FIXED_DELAY : integer range 0 to 16777215 := 16777215
- );
- port (
- clk : in std_logic;
- rst : in std_logic;
- GBE_READY_IN : in std_logic;
-
- CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
- CTS_CODE_OUT : out std_logic_vector (7 downto 0);
- CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
- CTS_START_READOUT_OUT : out std_logic;
- CTS_DATA_IN : in std_logic_vector (31 downto 0);
- CTS_DATAREADY_IN : in std_logic;
- CTS_READOUT_FINISHED_IN : in std_logic;
- CTS_READ_OUT : out std_logic;
- CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_OUT : out std_logic_vector (15 downto 0);
- FEE_DATAREADY_OUT : out std_logic;
- FEE_READ_IN : in std_logic;
- FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
- FEE_BUSY_OUT : out std_logic
- );
-end component;
-
-component gbe_sctrl_dummy is
- generic (
- DO_SIMULATION : integer range 0 to 1 := 0;
- FIXED_DELAY_MODE : integer range 0 to 1 := 1;
- FIXED_DELAY : integer range 0 to 65535 := 4096
- );
- port (
- clk : in std_logic;
- rst : in std_logic;
-
- RC_RD_EN_IN : in std_logic;
- RC_Q_OUT : out std_logic_vector(8 downto 0);
- RC_FRAME_WAITING_OUT : out std_logic;
- RC_LOADING_DONE_IN : in std_logic;
- RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
- RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
- GSC_REPLY_DATAREADY_OUT : out std_logic;
- GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_REPLY_READ_IN : in std_logic;
- GSC_BUSY_OUT : out std_logic
- );
-end component;
-
-component trb_net16_gbe_buf is
-generic(
- DO_SIMULATION : integer range 0 to 1 := 1;
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0;
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1;
-
- FIXED_SIZE_MODE : integer range 0 to 1 := 1;
- INCREMENTAL_MODE : integer range 0 to 1 := 0;
- FIXED_SIZE : integer range 0 to 65535 := 10;
- UP_DOWN_MODE : integer range 0 to 1 := 0;
- UP_DOWN_LIMIT : integer range 0 to 16777215 := 0;
- FIXED_DELAY_MODE : integer range 0 to 1 := 1;
- FIXED_DELAY : integer range 0 to 16777215 := 16777215
-);
-port(
- CLK : in std_logic;
- TEST_CLK : in std_logic; -- only for simulation!
- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
- RESET : in std_logic;
- GSR_N : in std_logic;
- -- Debug
- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);
- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);
- -- configuration interface
- IP_CFG_START_IN : in std_logic;
- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);
- IP_CFG_DONE_OUT : out std_logic;
- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);
- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);
- IP_CFG_MEM_CLK_OUT : out std_logic;
- MR_RESET_IN : in std_logic;
- MR_MODE_IN : in std_logic;
- MR_RESTART_IN : in std_logic;
- -- gk 29.03.10
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- gk 22.04.10
- -- registers setup interface
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
- -- gk 23.04.10
- LED_PACKET_SENT_OUT : out std_logic;
- LED_AN_DONE_N_OUT : out std_logic;
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- --SFP Connection
- SFP_RXD_P_IN : in std_logic;
- SFP_RXD_N_IN : in std_logic;
- SFP_TXD_P_OUT : out std_logic;
- SFP_TXD_N_OUT : out std_logic;
- SFP_REFCLK_P_IN : in std_logic;
- SFP_REFCLK_N_IN : in std_logic;
- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SFP_TXDIS_OUT : out std_logic; -- SFP disable
-
- -- interface between main_controller and hub logic
- MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
-
- MAKE_RESET_OUT : out std_logic;
-
- -- for simulation of receiving part only
- MAC_RX_EOF_IN : in std_logic;
- MAC_RXD_IN : in std_logic_vector(7 downto 0);
- MAC_RX_EN_IN : in std_logic;
-
-
- -- debug ports
- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-
-component trb_net16_gbe_protocol_prioritizer is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
-
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type
- PROTOCOL_CODE_IN : in std_logic_vector(7 downto 0); -- ip protocol
- UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0);
-
- CODE_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0)
-);
-end component;
-
-component trb_net16_gbe_type_validator is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type
- SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id
- ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup
- VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup
-
- -- IP level
- IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0);
- ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
-
- -- UDP level
- UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0);
- ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
-
- VALID_OUT : out std_logic
-);
-end component;
-
-component trb_net16_gbe_protocol_selector is
-generic(
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- DO_SIMULATION : integer range 0 to 1 := 0
- );
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
- RESET_FOR_DHCP : in std_logic;
-
--- signals to/from main controller
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- PS_RESPONSE_READY_OUT : out std_logic;
-
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
--- singals to/from transmi controller with constructed response
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_RD_EN_IN : in std_logic;
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- MC_BUSY_IN : in std_logic;
-
- -- misc signals for response constructors
- DHCP_START_IN : in std_logic;
- DHCP_DONE_OUT : out std_logic;
-
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
-
- MAKE_RESET_OUT : out std_logic;
-
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
- CFG_READOUT_CTR_VALID_IN : in std_logic;
- CFG_INSERT_TTYPE_IN : in std_logic;
- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
-
- CFG_ADDITIONAL_HDR_IN : in std_logic;
-
- -- input for statistics from outside
- STAT_DATA_IN : in std_logic_vector(31 downto 0);
- STAT_ADDR_IN : in std_logic_vector(7 downto 0);
- STAT_DATA_RDY_IN : in std_logic;
- STAT_DATA_ACK_OUT : out std_logic;
-
- MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
- DATA_HIST_OUT : out hist_array;
- SCTRL_HIST_OUT : out hist_array
-);
-end component;
-
-component trb_net16_gbe_mac_control is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- signals to/from main controller
- MC_TSMAC_READY_OUT : out std_logic;
- MC_RECONF_IN : in std_logic;
- MC_GBE_EN_IN : in std_logic;
- MC_RX_DISCARD_FCS : in std_logic;
- MC_PROMISC_IN : in std_logic;
- MC_MAC_ADDR_IN : in std_logic_vector(47 downto 0);
-
--- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
- TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
- TSM_HCS_N_OUT : out std_logic;
- TSM_HWRITE_N_OUT : out std_logic;
- TSM_HREAD_N_OUT : out std_logic;
- TSM_HREADY_N_IN : in std_logic;
- TSM_HDATA_EN_N_IN : in std_logic;
-
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_main_control is
-generic(
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- DO_SIMULATION : integer range 0 to 1 := 0
- );
-port (
- CLK : in std_logic; -- system clock
- CLK_125 : in std_logic;
- RESET : in std_logic;
-
- MC_LINK_OK_OUT : out std_logic;
- MC_RESET_LINK_IN : in std_logic;
- MC_IDLE_TOO_LONG_OUT : out std_logic;
- MC_DHCP_DONE_OUT : out std_logic;
-
--- signals to/from receive controller
- RC_FRAME_WAITING_IN : in std_logic;
- RC_LOADING_DONE_OUT : out std_logic;
- RC_DATA_IN : in std_logic_vector(8 downto 0);
- RC_RD_EN_OUT : out std_logic;
- RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
- RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
--- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_RD_EN_IN : in std_logic;
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_TRANSMIT_DONE_IN : in std_logic;
-
--- signals to/from sgmii/gbe pcs_an_complete
- PCS_AN_COMPLETE_IN : in std_logic;
-
--- signals to/from hub
- MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
-
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
-
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
- CFG_READOUT_CTR_VALID_IN : in std_logic;
- CFG_INSERT_TTYPE_IN : in std_logic;
- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
-
- CFG_ADDITIONAL_HDR_IN : in std_logic;
-
- MAKE_RESET_OUT : out std_logic;
-
--- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
- TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
- TSM_HCS_N_OUT : out std_logic;
- TSM_HWRITE_N_OUT : out std_logic;
- TSM_HREAD_N_OUT : out std_logic;
- TSM_HREADY_N_IN : in std_logic;
- TSM_HDATA_EN_N_IN : in std_logic;
- TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0);
- TSM_RX_STAT_EN_IN : in std_logic;
-
-
- MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
- DATA_HIST_OUT : out hist_array;
- SCTRL_HIST_OUT : out hist_array
-);
-end component;
-
-component trb_net16_gbe_transmit_control is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- signal to/from main controller
- MC_TRANSMIT_CTRL_IN : in std_logic; -- slow control frame is waiting to be built and sent
- MC_DATA_IN : in std_logic_vector(8 downto 0);
- MC_DATA_NOT_VALID_IN : in std_logic;
- MC_WR_EN_IN : in std_logic;
- MC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- MC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
-
- MC_DEST_MAC_IN : in std_logic_vector(47 downto 0);
- MC_DEST_IP_IN : in std_logic_vector(31 downto 0);
- MC_DEST_UDP_IN : in std_logic_vector(15 downto 0);
- MC_SRC_MAC_IN : in std_logic_vector(47 downto 0);
- MC_SRC_IP_IN : in std_logic_vector(31 downto 0);
- MC_SRC_UDP_IN : in std_logic_vector(15 downto 0);
-
- MC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- MC_IDENT_IN : in std_logic_vector(15 downto 0);
-
- MC_IP_SIZE_IN : in std_logic_vector(15 downto 0);
- MC_UDP_SIZE_IN : in std_logic_vector(15 downto 0);
- MC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
-
- MC_FC_H_READY_OUT : out std_logic;
- MC_FC_READY_OUT : out std_logic;
- MC_FC_WR_EN_IN : in std_logic;
-
- MC_BUSY_OUT : out std_logic;
- MC_TRANSMIT_DONE_OUT : out std_logic;
-
--- signal to/from frame constructor
- FC_DATA_OUT : out std_logic_vector(7 downto 0);
- FC_WR_EN_OUT : out std_logic;
- FC_READY_IN : in std_logic;
- FC_H_READY_IN : in std_logic;
- FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- FC_SOD_OUT : out std_logic;
- FC_EOD_OUT : out std_logic;
- FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
-
- DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_receive_control is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- signals to/from frame_receiver
- RC_DATA_IN : in std_logic_vector(8 downto 0);
- FR_RD_EN_OUT : out std_logic;
- FR_FRAME_VALID_IN : in std_logic;
- FR_GET_FRAME_OUT : out std_logic;
- FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0);
- FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
-
- FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
--- signals to the rest of the logic
- RC_RD_EN_IN : in std_logic;
- RC_Q_OUT : out std_logic_vector(8 downto 0);
- RC_FRAME_WAITING_OUT : out std_logic;
- RC_LOADING_DONE_IN : in std_logic;
- RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
- RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
--- statistics
- FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
- BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
-
-
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_frame_receiver is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
- LINK_OK_IN : in std_logic;
- ALLOW_RX_IN : in std_logic;
- RX_MAC_CLK : in std_logic; -- receiver serdes clock
-
--- input signals from TS_MAC
- MAC_RX_EOF_IN : in std_logic;
- MAC_RX_ER_IN : in std_logic;
- MAC_RXD_IN : in std_logic_vector(7 downto 0);
- MAC_RX_EN_IN : in std_logic;
- MAC_RX_FIFO_ERR_IN : in std_logic;
- MAC_RX_FIFO_FULL_OUT : out std_logic;
- MAC_RX_STAT_EN_IN : in std_logic;
- MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0);
--- output signal to control logic
- FR_Q_OUT : out std_logic_vector(8 downto 0);
- FR_RD_EN_IN : in std_logic;
- FR_FRAME_VALID_OUT : out std_logic;
- FR_GET_FRAME_IN : in std_logic;
- FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0);
- FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0);
- FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0);
- FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0);
- FR_VLAN_ID_IN : in std_logic_vector(31 downto 0);
-
- FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
- MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0)
-);
-end component;
-
--- gk 01.07.10
-component trb_net16_ipu2gbe is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
- MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
-
--- SCTRL_DUMMY_SIZE_IN : in std_logic_vector(15 downto 0);
--- SCTRL_DUMMY_PAUSE_IN : in std_logic_vector(31 downto 0);
-
- -- PacketConstructor interface
- ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic; -- gk 07.10.10
- PC_EOD_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_PADDING_OUT : out std_logic;
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
-);
-end component;
-
-component trb_net16_gbe_packet_constr is
-port(
- RESET : in std_logic;
- CLK : in std_logic;
- MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10
- -- ports for user logic
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
- PC_DATA_IN : in std_logic_vector(7 downto 0);
- PC_READY_OUT : out std_logic;
- PC_START_OF_SUB_IN : in std_logic;
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10
- PC_END_OF_DATA_IN : in std_logic;
- PC_TRANSMIT_ON_OUT : out std_logic;
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
- PC_PADDING_IN : in std_logic; -- gk 29.03.10
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10
- -- FrameConstructor ports
- TC_WR_EN_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(7 downto 0);
- TC_H_READY_IN : in std_logic;
- TC_READY_IN : in std_logic;
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- TC_SOD_OUT : out std_logic;
- TC_EOD_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_frame_constr is
-port(
- -- ports for user logic
- RESET : in std_logic;
- CLK : in std_logic;
- LINK_OK_IN : in std_logic; -- gk 03.08.10
- --
- WR_EN_IN : in std_logic;
- DATA_IN : in std_logic_vector(7 downto 0);
- START_OF_DATA_IN : in std_logic;
- END_OF_DATA_IN : in std_logic;
- IP_F_SIZE_IN : in std_logic_vector(15 downto 0);
- UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation
- HEADERS_READY_OUT : out std_logic;
- READY_OUT : out std_logic;
- DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
- IHL_VERSION_IN : in std_logic_vector(7 downto 0);
- TOS_IN : in std_logic_vector(7 downto 0);
- IDENTIFICATION_IN : in std_logic_vector(15 downto 0);
- FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
- TTL_IN : in std_logic_vector(7 downto 0);
- PROTOCOL_IN : in std_logic_vector(7 downto 0);
- FRAME_DELAY_IN : in std_logic_vector(31 downto 0);
- -- ports for packetTransmitter
- RD_CLK : in std_logic; -- 125MHz clock!!!
- FT_DATA_OUT : out std_logic_vector(8 downto 0);
- FT_TX_EMPTY_OUT : out std_logic;
- FT_TX_RD_EN_IN : in std_logic;
- FT_START_OF_PACKET_OUT : out std_logic;
- FT_TX_DONE_IN : in std_logic;
- FT_TX_DISCFRM_IN : in std_logic;
-
- MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0)
-);
-end component;
-
-component trb_net16_gbe_frame_trans is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
- LINK_OK_IN : in std_logic; -- gk 03.08.10
- TX_MAC_CLK : in std_logic;
- TX_EMPTY_IN : in std_logic;
- START_OF_PACKET_IN : in std_logic;
- DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC
- -- NEW PORTS
--- HADDR_OUT : out std_logic_vector(7 downto 0);
--- HDATA_OUT : out std_logic_vector(7 downto 0);
--- HCS_OUT : out std_logic;
--- HWRITE_OUT : out std_logic;
--- HREAD_OUT : out std_logic;
--- HREADY_IN : in std_logic;
--- HDATA_EN_IN : in std_logic;
- TX_FIFOAVAIL_OUT : out std_logic;
- TX_FIFOEOF_OUT : out std_logic;
- TX_FIFOEMPTY_OUT : out std_logic;
- TX_DONE_IN : in std_logic;
- TX_STAT_EN_IN : in std_logic;
- TX_STATVEC_IN : in std_logic_vector(30 downto 0);
- TX_DISCFRM_IN : in std_logic;
- -- Debug
- BSM_INIT_OUT : out std_logic_vector(3 downto 0);
- BSM_MAC_OUT : out std_logic_vector(3 downto 0);
- BSM_TRANS_OUT : out std_logic_vector(3 downto 0);
- DBG_RD_DONE_OUT : out std_logic;
- DBG_INIT_DONE_OUT : out std_logic;
- DBG_ENABLED_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_med_ecp_sfp_gbe_8b is
--- gk 28.04.10
-generic (
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
-);
-port(
- RESET : in std_logic;
- GSR_N : in std_logic;
- CLK_125_OUT : out std_logic;
- CLK_125_RX_OUT : out std_logic;
- CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk
- --SGMII connection to frame transmitter (tsmac)
- FT_TX_CLK_EN_OUT : out std_logic;
- FT_RX_CLK_EN_OUT : out std_logic;
- FT_COL_OUT : out std_logic;
- FT_CRS_OUT : out std_logic;
- FT_TXD_IN : in std_logic_vector(7 downto 0);
- FT_TX_EN_IN : in std_logic;
- FT_TX_ER_IN : in std_logic;
- FT_RXD_OUT : out std_logic_vector(7 downto 0);
- FT_RX_EN_OUT : out std_logic;
- FT_RX_ER_OUT : out std_logic;
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic;
- SD_REFCLK_N_IN : in std_logic;
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic; -- SFP disable
- -- Autonegotiation stuff
- MR_RESET_IN : in std_logic;
- MR_MODE_IN : in std_logic;
- MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0);
- MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0);
- MR_AN_PAGE_RX_OUT : out std_logic;
- MR_AN_COMPLETE_OUT : out std_logic;
- MR_AN_ENABLE_IN : in std_logic;
- MR_RESTART_AN_IN : in std_logic;
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
-);
-end component;
-
-component gbe_setup is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
-
- -- interface to regio bus
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);
- BUS_WRITE_EN_IN : in std_logic;
- BUS_READ_EN_IN : in std_logic;
- BUS_ACK_OUT : out std_logic;
-
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0);
- GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0);
- GBE_USE_GBE_OUT : out std_logic;
- GBE_USE_TRBNET_OUT : out std_logic;
- GBE_USE_MULTIEVENTS_OUT : out std_logic;
- GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0);
- GBE_READOUT_CTR_VALID_OUT : out std_logic;
- GBE_ALLOW_RX_OUT : out std_logic;
- GBE_ADDITIONAL_HDR_OUT : out std_logic;
- GBE_INSERT_TTYPE_OUT : out std_logic;
- GBE_SOFT_RESET_OUT : out std_logic;
-
- GBE_MAX_SUB_OUT : out std_logic_vector(15 downto 0);
- GBE_MAX_QUEUE_OUT : out std_logic_vector(15 downto 0);
- GBE_MAX_SUBS_IN_QUEUE_OUT : out std_logic_vector(15 downto 0);
- GBE_MAX_SINGLE_SUB_OUT : out std_logic_vector(15 downto 0);
-
- MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0);
- MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0);
- MONITOR_TX_BYTES_IN : in std_logic_vector(31 downto 0);
- MONITOR_TX_FRAMES_IN : in std_logic_vector(31 downto 0);
- MONITOR_TX_PACKETS_IN : in std_logic_vector(31 downto 0);
- MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0);
-
- MONITOR_SELECT_REC_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_REC_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_IN_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_OUT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_GEN_DBG_IN : in std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
- DATA_HIST_IN : in hist_array;
- SCTRL_HIST_IN : in hist_array
-);
-end component;
-
-
-component ip_configurator is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- configuration interface
- START_CONFIG_IN : in std_logic; -- start configuration run
- BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank
- CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used
- MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for
- MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory
- MEM_CLK_OUT : out std_logic; -- clock for BlockRAM
- -- information for IP cores
- DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address
- DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address
- DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port
- SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address
- SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address
- SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port
- MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size)
- -- Debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end component;
-
-component fifo_4096x9 is
-port(
- Data : in std_logic_vector(8 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_2048x8 is
-port(
- Data : in std_logic_vector(7 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_4096x32 is
-port(
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_512x32 is
-port(
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_512x72 is
-port(
- Data : in std_logic_vector(71 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(71 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_1024x16x8 is
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_65536x18x9 is
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_4kx18x9 is
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-
-component fifo_2048x8x16 is
-port(
- Data : in std_logic_vector(8 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(17 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_4kx8_ecp3 is
-port(
- Data : in std_logic_vector(7 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component statts_mem is
- port (
- WrAddress: in std_logic_vector(7 downto 0);
- RdAddress: in std_logic_vector(9 downto 0);
- Data: in std_logic_vector(31 downto 0);
- WE: in std_logic;
- RdClock: in std_logic;
- RdClockEn: in std_logic;
- Reset: in std_logic;
- WrClock: in std_logic;
- WrClockEn: in std_logic;
- Q: out std_logic_vector(7 downto 0));
-end component;
-
---component slv_mac_memory is
---port(
--- CLK : in std_logic;
--- RESET : in std_logic;
--- BUSY_IN : in std_logic;
--- -- Slave bus
--- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
--- SLV_READ_IN : in std_logic;
--- SLV_WRITE_IN : in std_logic;
--- SLV_BUSY_OUT : out std_logic;
--- SLV_ACK_OUT : out std_logic;
--- SLV_DATA_IN : in std_logic_vector(31 downto 0);
--- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
--- -- I/O to the backend
--- MEM_CLK_IN : in std_logic;
--- MEM_ADDR_IN : in std_logic_vector(7 downto 0);
--- MEM_DATA_OUT : out std_logic_vector(31 downto 0);
--- -- Status lines
--- STAT : out std_logic_vector(31 downto 0) -- DEBUG
---);
---end component;
-
-component fifo_32kx16x8_mb2
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(8 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0);
- Empty : out std_logic;
- AlmostEmpty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
-);
-end component;
-
-component fifo_64kx9
-port (
- Data : in std_logic_vector(8 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_16kx18x9 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(14 downto 0);
- AmFullThresh: in std_logic_vector(13 downto 0);
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end component;
-
-component fifo_32kx9_flags is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostFull : out std_logic);
-end component;
-
-
-component fifo_512x32x8
-port (
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_512x8
-port (
- Data : in std_logic_vector(7 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-end package;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-library work;
-use work.trb_net_std.all;
-
-package trb_net_gbe_protocols is
-
-type hist_array is array(31 downto 0) of std_logic_vector(31 downto 0);
-
-signal g_SIMULATE : integer range 0 to 1 := 0;
-
--- g_MY_IP is being set by DHCP Response Constructor
-signal g_MY_IP : std_logic_vector(31 downto 0);
--- g_MY_MAC is being set by Main Controller
-signal g_MY_MAC : std_logic_vector(47 downto 0);
-
-constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 2;
-constant c_MAX_PROTOCOLS : integer range 1 to 16 := 5; --5; --4; --5;
-constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 2;
-constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 4;
-
-type frame_types_a is array(c_MAX_FRAME_TYPES - 1 downto 0) of std_logic_vector(15 downto 0);
-constant FRAME_TYPES : frame_types_a := (x"0800", x"0806");
--- IPv4, ARP
-
-type ip_protos_a is array(c_MAX_IP_PROTOCOLS - 1 downto 0) of std_logic_vector(7 downto 0);
-constant IP_PROTOCOLS : ip_protos_a := (x"11", x"01");
--- UDP, ICMP
-
--- this are the destination ports of the incoming packet
-type udp_protos_a is array(c_MAX_UDP_PROTOCOLS - 1 downto 0) of std_logic_vector(15 downto 0);
-constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"6590", x"7530", x"7531"); --x"6590", x"7530", x"7531"); --x"61a8", x"7530", x"7531");
--- DHCP client, SCTRL, STATs
-
-component trb_net16_gbe_response_constructor_Forward is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_WR_EN_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_BUSY_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_ARP is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_Test is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_WR_EN_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_BUSY_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_Trash is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_SIZE_LEFT_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- TC_BUSY_IN : in std_logic;
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_DHCP is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
- DHCP_START_IN : in std_logic;
- DHCP_DONE_OUT : out std_logic;
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_Ping is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_PseudoPing is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_Test1 is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_WR_EN_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- TC_BUSY_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_SCTRL is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
- port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
- -- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- DEBUG_OUT : out std_logic_vector(63 downto 0);
- -- END OF INTERFACE
-
- -- protocol specific ports
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
- MAKE_RESET_OUT : out std_logic;
- CFG_ADDITIONAL_HDR_IN : in std_logic;
- -- end of protocol specific ports
-
- MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0);
-
- DATA_HIST_OUT : out hist_array
- );
-end component;
-
-component trb_net16_gbe_response_constructor_Stat is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_WR_EN_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- TC_BUSY_IN : in std_logic;
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
- STAT_DATA_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0);
- STAT_ADDR_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0);
- STAT_DATA_RDY_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
- STAT_DATA_ACK_OUT : out std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_TrbNetData is
-generic (
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- DO_SIMULATION : integer range 0 to 1 := 0
- );
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- DEBUG_OUT : out std_logic_vector(63 downto 0);
-
--- END OF INTERFACE
-
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
- CFG_READOUT_CTR_VALID_IN : in std_logic;
- CFG_INSERT_TTYPE_IN : in std_logic;
- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
-
- MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(31 downto 0);
- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(31 downto 0);
-
- DATA_HIST_OUT : out hist_array
-);
-end component;
-
-end package;
+++ /dev/null
-LIBRARY ieee;\r
-use ieee.std_logic_1164.all;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-use IEEE.std_logic_arith.all;\r
-\r
-library work;\r
-\r
-entity feeder is\r
-port( CLK : in std_logic;\r
- RESET : in std_logic;\r
- -- IPU interface directed toward the CTS\r
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
- CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
- CTS_START_READOUT_IN : in std_logic;\r
- CTS_READ_IN : in std_logic;\r
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
- CTS_DATAREADY_OUT : out std_logic;\r
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM\r
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
- -- Data from Frontends\r
- FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
- FEE_DATAREADY_IN : in std_logic;\r
- FEE_READ_OUT : out std_logic;\r
- FEE_BUSY_IN : in std_logic;\r
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); \r
- -- PacketConstructor interface\r
- PC_WR_EN_OUT : out std_logic;\r
- PC_DATA_OUT : out std_logic_vector (7 downto 0);\r
- PC_READY_IN : in std_logic;\r
- PC_SOS_OUT : out std_logic;\r
- PC_EOD_OUT : out std_logic;\r
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);\r
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);\r
- PC_PADDING_OUT : out std_logic;\r
- -- Debug\r
- BSM_SAVE_OUT : out std_logic_vector(3 downto 0);\r
- BSM_LOAD_OUT : out std_logic_vector(3 downto 0);\r
- DBG_REM_CTR_OUT : out std_logic_vector(3 downto 0);\r
- DBG_CTS_CTR_OUT : out std_logic_vector(2 downto 0);\r
- DBG_SF_WCNT_OUT : out std_logic_vector(15 downto 0);\r
- DBG_SF_RCNT_OUT : out std_logic_vector(16 downto 0);\r
- DBG_SF_DATA_OUT : out std_logic_vector(15 downto 0);\r
- DBG_SF_RD_EN_OUT : out std_logic;\r
- DBG_SF_WR_EN_OUT : out std_logic;\r
- DBG_SF_EMPTY_OUT : out std_logic;\r
- DBG_SF_FULL_OUT : out std_logic;\r
- DBG_SF_AFULL_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
-);\r
-end entity;\r
-\r
-architecture feeder of feeder is\r
-\r
-component fifo_32kx16x8_mb\r
-port( Data : in std_logic_vector(15 downto 0); \r
- WrClock : in std_logic;\r
- RdClock : in std_logic; \r
- WrEn : in std_logic;\r
- RdEn : in std_logic;\r
- Reset : in std_logic; \r
- RPReset : in std_logic; \r
- AmFullThresh : in std_logic_vector(14 downto 0); \r
- Q : out std_logic_vector(7 downto 0); \r
- WCNT : out std_logic_vector(15 downto 0); \r
- RCNT : out std_logic_vector(16 downto 0);\r
- Empty : out std_logic; \r
- Full : out std_logic;\r
- AlmostFull : out std_logic\r
- );\r
-end component;\r
-\r
-type saveStates is (SIDLE, WAIT_FOR_DATA, SAVE_DATA, TERMINATE, SCLOSE);\r
-signal saveCurrentState, saveNextState : saveStates;\r
-signal state : std_logic_vector(3 downto 0);\r
-signal data_req_comb : std_logic;\r
-signal data_req : std_logic; -- request data signal, will be used for fee_read generation\r
-signal rst_saved_ctr_comb : std_logic;\r
-signal rst_saved_ctr : std_logic;\r
-\r
-signal fee_read_comb : std_logic;\r
-signal fee_read : std_logic; -- fee_read signal\r
-signal saved_ctr : std_logic_vector(16 downto 0);\r
-signal ce_saved_ctr : std_logic;\r
-\r
--- header data\r
-signal cts_rnd : std_logic_vector(15 downto 0);\r
-signal cts_rnd_saved : std_logic;\r
-signal cts_trg : std_logic_vector(15 downto 0);\r
-signal cts_trg_saved : std_logic;\r
-signal cts_len : std_logic_vector(16 downto 0);\r
-signal cts_len_saved : std_logic;\r
-\r
--- CTS interface\r
-signal cts_error_pattern : std_logic_vector(31 downto 0);\r
-signal cts_length : std_logic_vector(15 downto 0);\r
-signal cts_readout_finished : std_logic;\r
-signal cts_dataready : std_logic;\r
-signal cts_data : std_logic_vector(31 downto 0);\r
-\r
--- Split FIFO signals\r
-signal sf_data : std_logic_vector(15 downto 0);\r
-signal sf_wr_en_comb : std_logic;\r
-signal sf_wr_en : std_logic; -- write signal for FIFO\r
-signal sf_rd_en : std_logic;\r
-signal sf_wcnt : std_logic_vector(15 downto 0);\r
-signal sf_rcnt : std_logic_vector(16 downto 0);\r
-signal sf_empty : std_logic;\r
-signal sf_full : std_logic;\r
-signal sf_afull : std_logic;\r
-\r
--------------------------------------------------------------------\r
-type loadStates is (LIDLE, INIT, REMOVE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, WAIT_PC, CLOSE);\r
-signal loadCurrentState, loadNextState : loadStates;\r
-signal state2 : std_logic_vector(3 downto 0);\r
-\r
-signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data\r
-signal rst_rem_ctr_comb : std_logic;\r
-signal rst_rem_ctr : std_logic;\r
-signal rst_regs_comb : std_logic;\r
-signal rst_regs : std_logic;\r
-signal ce_rem_ctr_comb : std_logic;\r
-signal ce_rem_ctr : std_logic;\r
-signal remove_done_comb : std_logic;\r
-signal remove_done : std_logic; -- end of header stripping process\r
-signal load_done_comb : std_logic;\r
-signal load_done : std_logic; -- end of data transfer into PC\r
-signal calc_pad_comb : std_logic;\r
-signal calc_pad : std_logic; -- add padding bytes, if needed\r
-signal read_data_comb : std_logic;\r
-signal read_data : std_logic; -- fetch data from split fifo\r
-signal data_phase_comb : std_logic;\r
-signal data_phase : std_logic; -- data transport phase from split fifo to PC\r
-signal pc_sos_comb : std_logic;\r
-signal pc_sos : std_logic; -- start of data signal\r
-signal pc_eod_comb : std_logic;\r
-signal pc_eod : std_logic; -- end of data signal\r
-signal pad_data_comb : std_logic;\r
-signal pad_data : std_logic; -- insert padding bytes\r
-\r
-signal pc_data : std_logic_vector(7 downto 0);\r
-signal pc_data_q : std_logic_vector(7 downto 0);\r
-signal pc_trig_nr : std_logic_vector(15 downto 0);\r
-signal pc_sub_size : std_logic_vector(17 downto 0);\r
-signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo\r
-signal padding_needed : std_logic;\r
-signal pc_wr_en_q : std_logic;\r
-signal pc_wr_en_qq : std_logic;\r
-signal pc_eod_q : std_logic;\r
-\r
-signal debug : std_logic_vector(31 downto 0);\r
-\r
-begin\r
-\r
--- CTS interface signals\r
-cts_error_pattern <= (others => '0'); -- FAKE\r
-cts_dataready <= '1'; -- FAKE\r
-\r
-cts_length <= x"0000"; -- length of data payload is always 0\r
-cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'\r
-\r
-cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';\r
-\r
-\r
--- Sync all critical pathes\r
-THE_SYNC_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- sf_data <= FEE_DATA_IN;\r
- sf_wr_en <= sf_wr_en_comb;\r
- fee_read <= fee_read_comb;\r
- load_done <= load_done_comb;\r
- pc_eod_q <= pc_eod;\r
- pc_wr_en_qq <= pc_wr_en_q;\r
- pc_wr_en_q <= data_phase;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
--- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY\r
-fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) \r
- else '0';\r
-\r
--- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY\r
-sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') )\r
- else '0';\r
-\r
--- Counter for header word storage\r
-THE_CTS_SAVED_CTR: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then\r
- saved_ctr <= (others => '0');\r
- elsif( ce_saved_ctr = '1' ) then\r
- saved_ctr <= saved_ctr + 1;\r
- end if;\r
- end if;\r
-end process THE_CTS_SAVED_CTR;\r
-\r
-ce_saved_ctr <= sf_wr_en;\r
-\r
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO\r
-saveMachineProc: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if RESET = '1' then\r
- saveCurrentState <= SIDLE;\r
- data_req <= '0';\r
- rst_saved_ctr <= '0';\r
- else\r
- saveCurrentState <= saveNextState;\r
- data_req <= data_req_comb;\r
- rst_saved_ctr <= rst_saved_ctr_comb;\r
- end if;\r
- end if;\r
-end process saveMachineProc;\r
-\r
-saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN )\r
-begin\r
- saveNextState <= SIDLE;\r
- data_req_comb <= '0';\r
- rst_saved_ctr_comb <= '0';\r
- case saveCurrentState is\r
- when SIDLE =>\r
- state <= x"0";\r
- if (CTS_START_READOUT_IN = '1') then\r
- saveNextState <= WAIT_FOR_DATA;\r
- data_req_comb <= '1';\r
- rst_saved_ctr_comb <= '1';\r
- else\r
- saveNextState <= SIDLE;\r
- end if;\r
- when WAIT_FOR_DATA =>\r
- state <= x"1";\r
- if (FEE_BUSY_IN = '1') then\r
- saveNextState <= SAVE_DATA;\r
- data_req_comb <= '1';\r
- else\r
- saveNextState <= WAIT_FOR_DATA;\r
- data_req_comb <= '1';\r
- end if;\r
- when SAVE_DATA =>\r
- state <= x"2";\r
- if (FEE_BUSY_IN = '0') then\r
- saveNextState <= TERMINATE;\r
- else\r
- saveNextState <= SAVE_DATA;\r
- data_req_comb <= '1';\r
- end if;\r
- when TERMINATE =>\r
- state <= x"3";\r
- if (CTS_READ_IN = '1') then\r
- saveNextState <= SCLOSE;\r
- else\r
- saveNextState <= TERMINATE;\r
- end if;\r
- when SCLOSE =>\r
- state <= x"4";\r
- if (CTS_START_READOUT_IN = '0') then\r
- saveNextState <= SIDLE;\r
- else\r
- saveNextState <= SCLOSE;\r
- end if;\r
- when others =>\r
- state <= x"f";\r
- saveNextState <= SIDLE;\r
- end case;\r
-end process saveMachine;\r
-\r
--- save triggerRnd from incoming data for cts response\r
-CTS_RND_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then\r
- cts_rnd <= (others => '0');\r
- cts_rnd_saved <= '0';\r
- elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then\r
- cts_rnd <= sf_data;\r
- cts_rnd_saved <= '1';\r
- end if;\r
- end if;\r
-end process CTS_RND_PROC;\r
-\r
--- save triggerNr from incoming data for cts response\r
-CTS_TRG_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then\r
- cts_trg <= (others => '0');\r
- cts_trg_saved <= '0';\r
- elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then\r
- cts_trg <= sf_data;\r
- cts_trg_saved <= '1';\r
- end if;\r
- end if;\r
-end process CTS_TRG_PROC;\r
-\r
--- save size from incoming data for cts response (future) and to get rid of padding\r
-CTS_SIZE_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then\r
- cts_len <= (others => '0');\r
- cts_len_saved <= '0';\r
- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then\r
- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words\r
- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then\r
- cts_len <= cts_len + x"4";\r
- cts_len_saved <= '1';\r
- end if;\r
- end if;\r
-end process CTS_SIZE_PROC;\r
-\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-\r
--- Split FIFO\r
-THE_SPLIT_FIFO: fifo_32kx16x8_mb\r
-port map( Data => sf_data,\r
- WrClock => CLK,\r
- RdClock => CLK, \r
- WrEn => sf_wr_en,\r
- RdEn => sf_rd_en,\r
- Reset => RESET, \r
- RPReset => RESET, \r
- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751\r
- Q => pc_data, --open,\r
- WCNT => sf_wcnt,\r
- RCNT => sf_rcnt,\r
- Empty => sf_empty,\r
- Full => sf_full,\r
- AlmostFull => sf_afull\r
- );\r
-\r
-sf_rd_en <= read_data;\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-\r
--- FIFO data delay process (also forces padding bytes to known value)\r
-THE_DATA_DELAY_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if( pad_data = '1' ) then\r
- pc_data_q <= x"ee";\r
- else\r
- pc_data_q <= pc_data;\r
- end if;\r
- end if;\r
-end process THE_DATA_DELAY_PROC;\r
-\r
--- Statemachine for reading the data payload from the SPLIT_FIFO and feeding\r
--- it into the packet constructor\r
-loadMachineProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if RESET = '1' then\r
- loadCurrentState <= LIDLE;\r
- rst_regs <= '0';\r
- rst_rem_ctr <= '0';\r
- ce_rem_ctr <= '0';\r
- calc_pad <= '0';\r
- read_data <= '0';\r
- data_phase <= '0';\r
- pc_sos <= '0';\r
- pc_eod <= '0';\r
- pad_data <= '0';\r
- else\r
- loadCurrentState <= loadNextState;\r
- rst_regs <= rst_regs_comb;\r
- rst_rem_ctr <= rst_rem_ctr_comb;\r
- ce_rem_ctr <= ce_rem_ctr_comb;\r
- calc_pad <= calc_pad_comb;\r
- read_data <= read_data_comb;\r
- data_phase <= data_phase_comb;\r
- pc_sos <= pc_sos_comb;\r
- pc_eod <= pc_eod_comb;\r
- pad_data <= pad_data_comb;\r
- end if;\r
- end if;\r
-end process loadMachineProc;\r
-\r
-loadMachine : process( loadCurrentState, sf_empty, remove_done, load_done, padding_needed, PC_READY_IN )\r
-begin\r
- loadNextState <= LIDLE;\r
- rst_regs_comb <= '0';\r
- rst_rem_ctr_comb <= '0';\r
- ce_rem_ctr_comb <= '0';\r
- calc_pad_comb <= '0';\r
- read_data_comb <= '0';\r
- data_phase_comb <= '0';\r
- pc_sos_comb <= '0';\r
- pc_eod_comb <= '0';\r
- pad_data_comb <= '0';\r
- case loadCurrentState is\r
- when LIDLE =>\r
- state2 <= x"0";\r
- if( (sf_empty = '0') and (PC_READY_IN = '1') ) then\r
- loadNextState <= INIT;\r
- rst_regs_comb <= '1';\r
- rst_rem_ctr_comb <= '1';\r
- else\r
- loadNextState <= LIDLE;\r
- end if;\r
- when INIT =>\r
- state2 <= x"1";\r
- loadNextState <= REMOVE;\r
- ce_rem_ctr_comb <= '1';\r
- read_data_comb <= '1';\r
- when REMOVE =>\r
- state2 <= x"2";\r
- if( remove_done = '1' ) then\r
- loadNextState <= CALCA;\r
- calc_pad_comb <= '1';\r
- else\r
- loadNextState <= REMOVE;\r
- ce_rem_ctr_comb <= '1';\r
- read_data_comb <= '1';\r
- end if;\r
- when CALCA =>\r
- state2 <= x"3";\r
- loadNextState <= CALCB;\r
- when CALCB =>\r
- -- we need a branch in case of length "0"!!!!\r
- state2 <= x"4";\r
- loadNextState <= LOAD;\r
- read_data_comb <= '1';\r
- data_phase_comb <= '1';\r
- pc_sos_comb <= '1';\r
- when LOAD =>\r
- state2 <= x"5";\r
- if ( (load_done = '1') and (padding_needed = '0') ) then\r
- loadNextState <= CLOSE;\r
- elsif( (load_done = '1') and (padding_needed = '1') ) then\r
- loadNextState <= PAD0;\r
- data_phase_comb <= '1';\r
- else\r
- loadNextState <= LOAD;\r
- read_data_comb <= '1';\r
- data_phase_comb <= '1';\r
- end if;\r
- when PAD0 =>\r
- state2 <= x"5";\r
- loadNextState <= PAD1;\r
- data_phase_comb <= '1';\r
- pad_data_comb <= '1';\r
- when PAD1 =>\r
- state2 <= x"6";\r
- loadNextState <= PAD2;\r
- data_phase_comb <= '1';\r
- pad_data_comb <= '1';\r
- when PAD2 =>\r
- state2 <= x"7";\r
- loadNextState <= PAD3;\r
- data_phase_comb <= '1';\r
- pad_data_comb <= '1';\r
- when PAD3 =>\r
- state2 <= x"8";\r
- loadNextState <= CLOSE;\r
- pad_data_comb <= '1';\r
- when CLOSE =>\r
- state2 <= x"9";\r
- loadNextState <= WAIT_PC;\r
- pc_eod_comb <= '1';\r
- when WAIT_PC =>\r
- state2 <= x"a";\r
- if( PC_READY_IN = '1' ) then\r
- loadNextState <= LIDLE;\r
- rst_rem_ctr_comb <= '1';\r
- rst_regs_comb <= '1';\r
- else\r
- loadNextState <= WAIT_PC;\r
- end if;\r
- when others =>\r
- state2 <= x"f";\r
- loadNextState <= LIDLE;\r
- end case;\r
-end process loadMachine;\r
-\r
--- Counter for stripping the unneeded parts of the data stream, and saving the important parts\r
-THE_REMOVE_CTR: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then\r
- rem_ctr <= (others => '0');\r
- elsif( ce_rem_ctr = '1' ) then\r
- rem_ctr <= rem_ctr + 1;\r
- end if;\r
- end if;\r
-end process THE_REMOVE_CTR;\r
-\r
-remove_done_comb <= '1' when ( rem_ctr = x"6" ) else '0';\r
-\r
-THE_REM_DONE_SYNC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then\r
- remove_done <= '0';\r
- else\r
- remove_done <= remove_done_comb;\r
- end if;\r
- end if;\r
-end process THE_REM_DONE_SYNC;\r
-\r
--- extract the trigger number from splitfifo data\r
-THE_TRG_NR_PROC: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if ( (RESET = '1') or (rst_regs = '1') ) then\r
- pc_trig_nr <= (others => '0');\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"3") ) then\r
- pc_trig_nr(7 downto 0) <= pc_data;\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"4") ) then\r
- pc_trig_nr(15 downto 8) <= pc_data;\r
- end if;\r
- end if;\r
-end process THE_TRG_NR_PROC;\r
-\r
--- check for padding\r
-THE_PADDING_NEEDED_PROC: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if ( (RESET = '1') or (rst_regs = '1') ) then\r
- padding_needed <= '0';\r
- elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then\r
- padding_needed <= '1';\r
- elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then\r
- padding_needed <= '0';\r
- end if;\r
- end if;\r
-end process THE_PADDING_NEEDED_PROC;\r
-\r
--- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,\r
--- and in case of padding needed increase it accordingly\r
-THE_SUB_SIZE_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_regs = '1') ) then\r
- pc_sub_size <= (others => '0');\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then\r
- pc_sub_size(9 downto 2) <= pc_data;\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then\r
- pc_sub_size(17 downto 10) <= pc_data;\r
- elsif( (calc_pad = '1') and (padding_needed = '1') ) then\r
- pc_sub_size <= pc_sub_size + 4;\r
- end if;\r
- end if;\r
-end process THE_SUB_SIZE_PROC;\r
-\r
--- number of bytes to read from split fifo\r
-THE_READ_SIZE_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then\r
- read_size <= (others => '0');\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then\r
- read_size(9 downto 2) <= pc_data;\r
- elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then\r
- read_size(17 downto 10) <= pc_data;\r
- elsif( ((calc_pad = '1') and (load_done = '0')) ) then\r
- read_size <= read_size - 2;\r
- elsif( ((read_data = '1') and (data_phase = '1')) ) then\r
- read_size <= read_size - 1;\r
- end if;\r
- end if;\r
-end process THE_READ_SIZE_PROC;\r
-\r
-load_done_comb <= '1' when (read_size = 0) else '0';\r
-\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------------------\r
-\r
--- Debug signals\r
-debug(31) <= remove_done;\r
-debug(30) <= load_done;\r
-debug(29) <= ce_rem_ctr;\r
-debug(28) <= rst_rem_ctr;\r
-debug(27) <= rst_regs;\r
-debug(26) <= data_phase;\r
-debug(25) <= read_data;\r
-debug(24) <= pad_data;\r
-debug(23 downto 18) <= (others => '0');\r
-debug(17 downto 0) <= read_size;\r
-\r
--- Outputs\r
-FEE_READ_OUT <= fee_read;\r
-CTS_ERROR_PATTERN_OUT <= cts_error_pattern;\r
-CTS_DATA_OUT <= cts_data;\r
-CTS_DATAREADY_OUT <= cts_dataready;\r
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;\r
-CTS_LENGTH_OUT <= cts_length;\r
-\r
-PC_SOS_OUT <= pc_sos;\r
-PC_EOD_OUT <= pc_eod_q;\r
-PC_DATA_OUT <= pc_data_q;\r
-PC_WR_EN_OUT <= pc_wr_en_qq;\r
-PC_TRIG_NR_OUT <= x"0000" & pc_trig_nr;\r
-PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size;\r
-PC_PADDING_OUT <= padding_needed;\r
-\r
-BSM_SAVE_OUT <= state;\r
-BSM_LOAD_OUT <= state2;\r
-DBG_CTS_CTR_OUT <= saved_ctr(2 downto 0);\r
-DBG_REM_CTR_OUT <= rem_ctr;\r
-DBG_SF_DATA_OUT <= sf_data;\r
-DBG_SF_WCNT_OUT <= sf_wcnt;\r
-DBG_SF_RCNT_OUT <= sf_rcnt;\r
-DBG_SF_RD_EN_OUT <= sf_rd_en;\r
-DBG_SF_WR_EN_OUT <= sf_wr_en;\r
-DBG_SF_EMPTY_OUT <= sf_empty;\r
-DBG_SF_FULL_OUT <= sf_full;\r
-DBG_SF_AFULL_OUT <= sf_afull;\r
-\r
-DEBUG_OUT <= debug;\r
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;\r
-use ieee.std_logic_1164.all;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-use IEEE.std_logic_arith.all;\r
-\r
-library work;\r
-\r
-entity ip_configurator is\r
-port( \r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- -- configuration interface\r
- START_CONFIG_IN : in std_logic; -- start configuration run\r
- BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank \r
- CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used\r
- MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for\r
- MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory\r
- MEM_CLK_OUT : out std_logic; -- clock for BlockRAM\r
- -- information for IP cores\r
- DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address\r
- DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address\r
- DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port\r
- SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address\r
- SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address\r
- SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port\r
- MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size)\r
- -- Debug\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
-);\r
-end entity;\r
-\r
-architecture ip_configurator of ip_configurator is\r
-\r
--- -- Placer Directives\r
--- attribute HGROUP : string;\r
--- -- for whole architecture\r
--- attribute HGROUP of ip_configurator : architecture is "GBE_conf_group";\r
-\r
-type STATES is (IDLE, LOAD_REG, DELAY0, DELAY1, DELAY2, LOAD_DONE);\r
-signal CURRENT_STATE, NEXT_STATE : STATES;\r
-signal bsm : std_logic_vector(3 downto 0);\r
-signal ce_ctr_comb : std_logic;\r
-signal ce_ctr : std_logic;\r
-signal rst_ctr_comb : std_logic;\r
-signal rst_ctr : std_logic;\r
-signal cfg_done_comb : std_logic;\r
-signal cfg_done : std_logic;\r
-\r
-signal ctr_done_comb : std_logic;\r
-signal ctr_done : std_logic;\r
-\r
-signal wr_select_comb : std_logic_vector(15 downto 0);\r
-signal wr_select : std_logic_vector(15 downto 0);\r
-signal wr_select_q : std_logic_vector(15 downto 0);\r
-\r
-signal addr_ctr : std_logic_vector(3 downto 0);\r
-signal dest_mac : std_logic_vector(47 downto 0);\r
-signal dest_ip : std_logic_vector(31 downto 0);\r
-signal dest_udp : std_logic_vector(15 downto 0);\r
-signal src_mac : std_logic_vector(47 downto 0);\r
-signal src_ip : std_logic_vector(31 downto 0);\r
-signal src_udp : std_logic_vector(15 downto 0);\r
-signal mtu : std_logic_vector(15 downto 0);\r
-\r
-signal debug : std_logic_vector(31 downto 0);\r
-\r
-begin\r
-\r
-\r
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO\r
-STATE_MACHINE_PROC: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if RESET = '1' then\r
- CURRENT_STATE <= IDLE;\r
- ce_ctr <= '0';\r
- rst_ctr <= '0';\r
- cfg_done <= '0';\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- ce_ctr <= ce_ctr_comb;\r
- rst_ctr <= rst_ctr_comb;\r
- cfg_done <= cfg_done_comb;\r
- end if;\r
- end if;\r
-end process STATE_MACHINE_PROC;\r
-\r
-STATE_MACHINE_TRANS: process( CURRENT_STATE, START_CONFIG_IN, ctr_done )\r
-begin\r
- NEXT_STATE <= IDLE;\r
- ce_ctr_comb <= '0';\r
- rst_ctr_comb <= '0';\r
- cfg_done_comb <= '0';\r
- case CURRENT_STATE is\r
- when IDLE =>\r
- bsm <= x"0";\r
- if( START_CONFIG_IN = '1' ) then\r
- NEXT_STATE <= LOAD_REG;\r
- ce_ctr_comb <= '1';\r
- else\r
- NEXT_STATE <= IDLE;\r
- end if;\r
- when LOAD_REG =>\r
- bsm <= x"1";\r
- if( ctr_done = '1' ) then\r
- NEXT_STATE <= DELAY0;\r
- rst_ctr_comb <= '1';\r
- else\r
- NEXT_STATE <= LOAD_REG;\r
- ce_ctr_comb <= '1';\r
- end if;\r
- when DELAY0 =>\r
- bsm <= x"2";\r
- NEXT_STATE <= DELAY1;\r
- when DELAY1 =>\r
- bsm <= x"3";\r
- NEXT_STATE <= DELAY2;\r
- when DELAY2 =>\r
- bsm <= x"4";\r
- NEXT_STATE <= LOAD_DONE;\r
- cfg_done_comb <= '1';\r
- when LOAD_DONE =>\r
- bsm <= x"2";\r
- if( START_CONFIG_IN = '0' ) then\r
- NEXT_STATE <= IDLE;\r
- else\r
- NEXT_STATE <= LOAD_DONE;\r
- cfg_done_comb <= '1';\r
- end if;\r
- when others =>\r
- bsm <= x"f";\r
- NEXT_STATE <= IDLE;\r
- end case;\r
-end process STATE_MACHINE_TRANS;\r
-\r
--- address counter\r
-THE_ADDR_CTR_PROC: process( CLK )\r
-begin\r
- if ( rising_edge(CLK) ) then\r
- if ( (RESET = '1') or (rst_ctr = '1') ) then\r
- addr_ctr <= (others => '0');\r
- elsif( ce_ctr = '1' ) then\r
- addr_ctr <= addr_ctr + 1;\r
- end if; \r
- end if;\r
-end process THE_ADDR_CTR_PROC;\r
-\r
-ctr_done_comb <= '1' when (addr_ctr = x"e") else '0';\r
-\r
-THE_SYNC_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- ctr_done <= ctr_done_comb;\r
- wr_select_q <= wr_select;\r
- wr_select <= wr_select_comb;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
--- generate combinatorial write select signals, register and delay the (output registers in EBR!)\r
-wr_select_comb(0) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"0") ) else '0'; -- dest MAC low\r
-wr_select_comb(1) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"1") ) else '0'; -- dest MAC high\r
-wr_select_comb(2) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"2") ) else '0'; -- dest IP \r
-wr_select_comb(3) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"3") ) else '0'; -- dest port\r
-wr_select_comb(4) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"4") ) else '0'; -- src MAC low\r
-wr_select_comb(5) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"5") ) else '0'; -- src MAC high\r
-wr_select_comb(6) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"6") ) else '0'; -- src IP\r
-wr_select_comb(7) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"7") ) else '0'; -- src port\r
-wr_select_comb(8) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"8") ) else '0'; -- MTU\r
-wr_select_comb(9) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"9") ) else '0';\r
-wr_select_comb(10) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"a") ) else '0';\r
-wr_select_comb(11) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"b") ) else '0';\r
-wr_select_comb(12) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"c") ) else '0';\r
-wr_select_comb(13) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"d") ) else '0';\r
-wr_select_comb(14) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"e") ) else '0';\r
-wr_select_comb(15) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"f") ) else '0';\r
-\r
--- destination MAC low register\r
-THE_D_MAC_LOW_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- dest_mac(31 downto 0) <= (others => '0');\r
- elsif( wr_select_q(0) = '1') then\r
- dest_mac(31 downto 0) <= mem_data_in;\r
- end if;\r
- end if;\r
-end process THE_D_MAC_LOW_PROC;\r
-\r
--- destination MAC high register\r
-THE_D_MAC_HIGH_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- dest_mac(47 downto 32) <= (others => '0');\r
- elsif( wr_select_q(1) = '1') then\r
- dest_mac(47 downto 32) <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_D_MAC_HIGH_PROC;\r
-\r
--- destination IP register\r
-THE_D_IP_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- dest_ip <= (others => '0');\r
- elsif( wr_select_q(2) = '1') then\r
- dest_ip <= mem_data_in;\r
- end if;\r
- end if;\r
-end process THE_D_IP_PROC;\r
-\r
--- destination PORT register\r
-THE_D_PORT_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- dest_udp <= (others => '0');\r
- elsif( wr_select_q(3) = '1') then\r
- dest_udp <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_D_PORT_PROC;\r
-\r
--- source MAC low register\r
-THE_S_MAC_LOW_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- src_mac(31 downto 0) <= (others => '0');\r
- elsif( wr_select_q(4) = '1') then\r
- src_mac(31 downto 0) <= mem_data_in;\r
- end if;\r
- end if;\r
-end process THE_S_MAC_LOW_PROC;\r
-\r
--- source MAC high register\r
-THE_S_MAC_HIGH_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- src_mac(47 downto 32) <= (others => '0');\r
- elsif( wr_select_q(5) = '1') then\r
- src_mac(47 downto 32) <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_S_MAC_HIGH_PROC;\r
-\r
--- source IP register\r
-THE_S_IP_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- src_ip <= (others => '0');\r
- elsif( wr_select_q(6) = '1') then\r
- src_ip <= mem_data_in;\r
- end if;\r
- end if;\r
-end process THE_S_IP_PROC;\r
-\r
--- source PORT register\r
-THE_S_PORT_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- src_udp <= (others => '0');\r
- elsif( wr_select_q(7) = '1') then\r
- src_udp <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_S_PORT_PROC;\r
-\r
--- MTU size register\r
-THE_MTU_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- mtu <= (others => '0');\r
- elsif( wr_select_q(8) = '1') then\r
- mtu <= mem_data_in(15 downto 0);\r
- end if;\r
- end if;\r
-end process THE_MTU_PROC;\r
-\r
-\r
--- Debug signals\r
-debug(31 downto 12) <= (others => '0');\r
-debug(11 downto 8) <= addr_ctr;\r
-debug(7) <= '0';\r
-debug(6) <= ctr_done;\r
-debug(5) <= ce_ctr;\r
-debug(4) <= rst_ctr;\r
-debug(3 downto 0) <= bsm;\r
--- Outputs\r
-MEM_ADDR_OUT(7 downto 4) <= BANK_SELECT_IN;\r
-MEM_ADDR_OUT(3 downto 0) <= addr_ctr;\r
-MEM_CLK_OUT <= CLK;\r
-CONFIG_DONE_OUT <= cfg_done;\r
-\r
--- destination MAC address - swap for user convinience\r
-DEST_MAC_OUT(47 downto 40) <= dest_mac(7 downto 0);\r
-DEST_MAC_OUT(39 downto 32) <= dest_mac(15 downto 8);\r
-DEST_MAC_OUT(31 downto 24) <= dest_mac(23 downto 16);\r
-DEST_MAC_OUT(23 downto 16) <= dest_mac(31 downto 24);\r
-DEST_MAC_OUT(15 downto 8) <= dest_mac(39 downto 32);\r
-DEST_MAC_OUT(7 downto 0) <= dest_mac(47 downto 40);\r
-\r
--- destination IP address - swap for user convinience\r
-DEST_IP_OUT(31 downto 24) <= dest_ip(7 downto 0);\r
-DEST_IP_OUT(23 downto 16) <= dest_ip(15 downto 8);\r
-DEST_IP_OUT(15 downto 8) <= dest_ip(23 downto 16);\r
-DEST_IP_OUT(7 downto 0) <= dest_ip(31 downto 24);\r
-\r
--- destination port address - swap for user convinience\r
-DEST_UDP_OUT(15 downto 8) <= dest_udp(7 downto 0);\r
-DEST_UDP_OUT(7 downto 0) <= dest_udp(15 downto 8);\r
-\r
--- source MAC address - swap for user convinience\r
-SRC_MAC_OUT(47 downto 40) <= src_mac(7 downto 0);\r
-SRC_MAC_OUT(39 downto 32) <= src_mac(15 downto 8);\r
-SRC_MAC_OUT(31 downto 24) <= src_mac(23 downto 16);\r
-SRC_MAC_OUT(23 downto 16) <= src_mac(31 downto 24);\r
-SRC_MAC_OUT(15 downto 8) <= src_mac(39 downto 32);\r
-SRC_MAC_OUT(7 downto 0) <= src_mac(47 downto 40);\r
-\r
--- source IP address - swap for user convinience\r
-SRC_IP_OUT(31 downto 24) <= src_ip(7 downto 0);\r
-SRC_IP_OUT(23 downto 16) <= src_ip(15 downto 8);\r
-SRC_IP_OUT(15 downto 8) <= src_ip(23 downto 16);\r
-SRC_IP_OUT(7 downto 0) <= src_ip(31 downto 24);\r
-\r
--- source port address - swap for user convinience\r
-SRC_UDP_OUT(15 downto 8) <= src_udp(7 downto 0);\r
-SRC_UDP_OUT(7 downto 0) <= src_udp(15 downto 8);\r
-\r
--- DO NOT SWAP!\r
-MTU_OUT <= mtu;\r
-\r
-DEBUG_OUT <= debug;\r
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
-*.jhd
-*.naf
-*.srp
-*.sym
-*.log
-*tmpl.vhd
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 5.2
---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 16 -depth 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -e
-
--- Wed Jul 21 14:35:10 2010
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity debug_fifo_2kx16 is
- port (
- Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(15 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end debug_fifo_2kx16;
-
-architecture Structure of debug_fifo_2kx16 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5: std_logic;
- signal wcount_11: std_logic;
- signal co4: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5_1: std_logic;
- signal rcount_11: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_10: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_10: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
- attribute initval of LUT4_31 : label is "0x6996";
- attribute initval of LUT4_30 : label is "0x6996";
- attribute initval of LUT4_29 : label is "0x6996";
- attribute initval of LUT4_28 : label is "0x6996";
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "debug_fifo_2kx16.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL";
- attribute GSR of pdp_ram_0_0_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "debug_fifo_2kx16.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute CSDECODE_B of pdp_ram_0_1_0 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_1_0 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_1_0 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_1_0 : label is "NORMAL";
- attribute GSR of pdp_ram_0_1_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_1_0 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_1_0 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_1_0 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_0_1_0 : label is "9";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t24: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t23: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t22: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t21: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t9: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t8: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t7: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t6: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t5: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t4: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t3: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t2: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t1: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t0: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- LUT4_31: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5),
- DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(9),
- DOB1=>Q(10), DOB2=>Q(11), DOB3=>Q(12), DOB4=>Q(13),
- DOB5=>Q(14), DOB6=>Q(15), DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_121: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_120: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_119: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_118: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_117: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_116: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_115: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_114: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_113: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_112: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_111: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_110: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_109: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_108: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_107: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_106: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_105: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_104: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_103: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_102: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_101: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_85: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_71: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_61: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_60: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_59: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_58: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_57: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_56: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_55: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_54: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_53: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_52: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_51: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_50: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10,
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10,
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of debug_fifo_2kx16 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_1024x16x8
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/05/2011
-Time=18:27:25
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=1024
-Width=18
-RDepth=2048
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 18 -depth 1024 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
-
--- Mon Dec 5 18:27:25 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_1024x16x8 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_1024x16x8;
-
-architecture Structure of fifo_1024x16x8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal rcount_w0: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal co5: std_logic;
- signal wcount_10: std_logic;
- signal co4: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5_1: std_logic;
- signal rcount_11: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r8: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r9: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_10: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w9: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_1024x16x8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t23: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t22: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t21: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t20: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t19: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t18: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t17: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t16: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t15: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t14: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t13: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t12: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t11: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t10: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t9: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t8: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t7: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t6: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t5: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t4: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t3: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t2: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t1: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t0: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>w_gcount_r210,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_gcount_r26,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r4);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>w_gcount_r22, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3),
- DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8),
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- FF_116: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_115: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_114: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_113: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_112: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_111: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_110: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_109: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_108: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_107: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_106: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_105: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_104: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_103: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_102: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_101: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_100: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_99: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_98: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_97: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_96: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_95: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_94: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_93: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_92: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_91: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_90: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_89: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_88: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_87: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_86: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_85: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_84: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_83: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_82: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_81: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_80: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_79: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_78: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_77: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_76: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_75: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_74: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_73: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_72: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_66: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_65: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_64: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_63: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_62: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_60: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_59: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_58: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_57: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_56: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_55: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_54: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_53: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_52: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_51: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_50: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_49: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_48: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5,
- NC0=>iwcount_10, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r8, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r9,
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>r_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
- B1=>rcount_w10, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_1024x16x8 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Mon Dec 5 18:27:25 2011
-
--- parameterized module component declaration
-component fifo_1024x16x8
- port (Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_1024x16x8
- port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
--- Module Version: 5.4
---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 8 -depth 16384 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Mon Dec 6 19:08:10 2010
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity fifo_16kx8 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_16kx8;
-
-architecture Structure of fifo_16kx8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal co7: std_logic;
- signal wcount_14: std_logic;
- signal co6: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal co7_1: std_logic;
- signal rcount_14: std_logic;
- signal co6_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal wcount_r12: std_logic;
- signal wcount_r13: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal rcount_w12: std_logic;
- signal rcount_w13: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
- attribute initval of LUT4_41 : label is "0x6996";
- attribute initval of LUT4_40 : label is "0x6996";
- attribute initval of LUT4_39 : label is "0x6996";
- attribute initval of LUT4_38 : label is "0x6996";
- attribute initval of LUT4_37 : label is "0x6996";
- attribute initval of LUT4_36 : label is "0x6996";
- attribute initval of LUT4_35 : label is "0x6996";
- attribute initval of LUT4_34 : label is "0x6996";
- attribute initval of LUT4_33 : label is "0x6996";
- attribute initval of LUT4_32 : label is "0x6996";
- attribute initval of LUT4_31 : label is "0x6996";
- attribute initval of LUT4_30 : label is "0x6996";
- attribute initval of LUT4_29 : label is "0x6996";
- attribute initval of LUT4_28 : label is "0x6996";
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
- attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL";
- attribute GSR of pdp_ram_0_0_7 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
- attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL";
- attribute GSR of pdp_ram_0_1_6 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is "";
- attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL";
- attribute GSR of pdp_ram_0_2_5 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is "";
- attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL";
- attribute GSR of pdp_ram_0_3_4 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is "";
- attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL";
- attribute GSR of pdp_ram_0_4_3 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is "";
- attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL";
- attribute GSR of pdp_ram_0_5_2 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is "";
- attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL";
- attribute GSR of pdp_ram_0_6_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "1";
- attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_16kx8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is "";
- attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL";
- attribute GSR of pdp_ram_0_7_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "1";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t30: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t29: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t28: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t27: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t26: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t25: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t24: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t23: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t22: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t21: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t20: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t19: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t18: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t17: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t16: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t15: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t14: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t13: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t12: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t11: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t10: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t9: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t8: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t7: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t6: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t5: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t4: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t3: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t2: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t1: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t0: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- LUT4_41: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>w_gcount_r214,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_40: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>w_gcount_r210,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_39: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_gcount_r26,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_38: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_37: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>scuba_vlo, DO0=>wcount_r12);
-
- LUT4_36: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_35: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9);
-
- LUT4_34: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r8);
-
- LUT4_33: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_32: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r6);
-
- LUT4_31: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>wcount_r5);
-
- LUT4_30: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_29: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_28: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r22, DO0=>wcount_r2);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r1);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r0);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>r_gcount_w214,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>r_gcount_w210,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_gcount_w26,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w13);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>scuba_vlo, DO0=>rcount_w12);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w8);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w25, AD0=>r_gcount_w26, DO0=>rcount_w5);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w22, DO0=>rcount_w2);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_7: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(0), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_1_6: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(1), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_2_5: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(2), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_3_4: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(3), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_4_3: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(4), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_5_2: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(5), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_6_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(6), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_7_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 1)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(7), DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- FF_151: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_150: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_149: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_148: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_147: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_146: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_145: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_144: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_143: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_142: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_141: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_140: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_139: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_138: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_137: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_136: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_135: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_134: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_133: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_132: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_131: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_130: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_129: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_128: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_127: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_126: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_125: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_124: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_123: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_122: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_121: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_120: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_119: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_118: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_117: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_116: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_115: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_114: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_113: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_112: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_111: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_110: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_109: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_108: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_107: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_106: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_105: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_104: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_103: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_102: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_101: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_85: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_71: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_61: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_60: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_59: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_58: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_57: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_56: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_55: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_54: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_53: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_52: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_51: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_50: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7,
- NC0=>iwcount_14, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_1,
- NC0=>ircount_14, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>w_g2b_xor_cluster_0, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12,
- B1=>wcount_r13, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co6_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>r_g2b_xor_cluster_0, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12,
- B1=>rcount_w13, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co6_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of fifo_16kx8 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-5F900C\r
-SpeedGrade=-5\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=FIFO_DC\r
-CoreRevision=5.2\r
-ModuleName=fifo_2048x8\r
-SourceFormat=VHDL\r
-ParameterFileVersion=1.0\r
-Date=12/26/2009\r
-Time=00:12:59\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-FIFOImp=EBR Based\r
-Depth=2048\r
-Width=8\r
-RDepth=2048\r
-RWidth=8\r
-regout=0\r
-CtrlByRdEn=0\r
-EmpFlg=0\r
-PeMode=Static - Dual Threshold\r
-PeAssert=10\r
-PeDeassert=12\r
-FullFlg=0\r
-PfMode=Static - Dual Threshold\r
-PfAssert=508\r
-PfDeassert=506\r
-RDataCount=0\r
-WDataCount=0\r
-EnECC=0\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)\r
--- Module Version: 5.2\r
---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e \r
-\r
--- Sat Dec 26 00:12:59 2009\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
--- synopsys translate_off\r
-library ecp2m;\r
-use ecp2m.components.all;\r
--- synopsys translate_on\r
-\r
-entity fifo_2048x8 is\r
- port (\r
- Data: in std_logic_vector(7 downto 0); \r
- WrClock: in std_logic; \r
- RdClock: in std_logic; \r
- WrEn: in std_logic; \r
- RdEn: in std_logic; \r
- Reset: in std_logic; \r
- RPReset: in std_logic; \r
- Q: out std_logic_vector(7 downto 0); \r
- Empty: out std_logic; \r
- Full: out std_logic);\r
-end fifo_2048x8;\r
-\r
-architecture Structure of fifo_2048x8 is\r
-\r
- -- internal signal declarations\r
- signal invout_1: std_logic;\r
- signal invout_0: std_logic;\r
- signal w_g2b_xor_cluster_2_1: std_logic;\r
- signal w_g2b_xor_cluster_2: std_logic;\r
- signal w_g2b_xor_cluster_1: std_logic;\r
- signal r_g2b_xor_cluster_2_1: std_logic;\r
- signal r_g2b_xor_cluster_2: std_logic;\r
- signal r_g2b_xor_cluster_1: std_logic;\r
- signal w_gdata_0: std_logic;\r
- signal w_gdata_1: std_logic;\r
- signal w_gdata_2: std_logic;\r
- signal w_gdata_3: std_logic;\r
- signal w_gdata_4: std_logic;\r
- signal w_gdata_5: std_logic;\r
- signal w_gdata_6: std_logic;\r
- signal w_gdata_7: std_logic;\r
- signal w_gdata_8: std_logic;\r
- signal w_gdata_9: std_logic;\r
- signal w_gdata_10: std_logic;\r
- signal wptr_0: std_logic;\r
- signal wptr_1: std_logic;\r
- signal wptr_2: std_logic;\r
- signal wptr_3: std_logic;\r
- signal wptr_4: std_logic;\r
- signal wptr_5: std_logic;\r
- signal wptr_6: std_logic;\r
- signal wptr_7: std_logic;\r
- signal wptr_8: std_logic;\r
- signal wptr_9: std_logic;\r
- signal wptr_10: std_logic;\r
- signal wptr_11: std_logic;\r
- signal r_gdata_0: std_logic;\r
- signal r_gdata_1: std_logic;\r
- signal r_gdata_2: std_logic;\r
- signal r_gdata_3: std_logic;\r
- signal r_gdata_4: std_logic;\r
- signal r_gdata_5: std_logic;\r
- signal r_gdata_6: std_logic;\r
- signal r_gdata_7: std_logic;\r
- signal r_gdata_8: std_logic;\r
- signal r_gdata_9: std_logic;\r
- signal r_gdata_10: std_logic;\r
- signal rptr_0: std_logic;\r
- signal rptr_1: std_logic;\r
- signal rptr_2: std_logic;\r
- signal rptr_3: std_logic;\r
- signal rptr_4: std_logic;\r
- signal rptr_5: std_logic;\r
- signal rptr_6: std_logic;\r
- signal rptr_7: std_logic;\r
- signal rptr_8: std_logic;\r
- signal rptr_9: std_logic;\r
- signal rptr_10: std_logic;\r
- signal rptr_11: std_logic;\r
- signal w_gcount_0: std_logic;\r
- signal w_gcount_1: std_logic;\r
- signal w_gcount_2: std_logic;\r
- signal w_gcount_3: std_logic;\r
- signal w_gcount_4: std_logic;\r
- signal w_gcount_5: std_logic;\r
- signal w_gcount_6: std_logic;\r
- signal w_gcount_7: std_logic;\r
- signal w_gcount_8: std_logic;\r
- signal w_gcount_9: std_logic;\r
- signal w_gcount_10: std_logic;\r
- signal w_gcount_11: std_logic;\r
- signal r_gcount_0: std_logic;\r
- signal r_gcount_1: std_logic;\r
- signal r_gcount_2: std_logic;\r
- signal r_gcount_3: std_logic;\r
- signal r_gcount_4: std_logic;\r
- signal r_gcount_5: std_logic;\r
- signal r_gcount_6: std_logic;\r
- signal r_gcount_7: std_logic;\r
- signal r_gcount_8: std_logic;\r
- signal r_gcount_9: std_logic;\r
- signal r_gcount_10: std_logic;\r
- signal r_gcount_11: std_logic;\r
- signal w_gcount_r20: std_logic;\r
- signal w_gcount_r0: std_logic;\r
- signal w_gcount_r21: std_logic;\r
- signal w_gcount_r1: std_logic;\r
- signal w_gcount_r22: std_logic;\r
- signal w_gcount_r2: std_logic;\r
- signal w_gcount_r23: std_logic;\r
- signal w_gcount_r3: std_logic;\r
- signal w_gcount_r24: std_logic;\r
- signal w_gcount_r4: std_logic;\r
- signal w_gcount_r25: std_logic;\r
- signal w_gcount_r5: std_logic;\r
- signal w_gcount_r26: std_logic;\r
- signal w_gcount_r6: std_logic;\r
- signal w_gcount_r27: std_logic;\r
- signal w_gcount_r7: std_logic;\r
- signal w_gcount_r28: std_logic;\r
- signal w_gcount_r8: std_logic;\r
- signal w_gcount_r29: std_logic;\r
- signal w_gcount_r9: std_logic;\r
- signal w_gcount_r210: std_logic;\r
- signal w_gcount_r10: std_logic;\r
- signal w_gcount_r211: std_logic;\r
- signal w_gcount_r11: std_logic;\r
- signal r_gcount_w20: std_logic;\r
- signal r_gcount_w0: std_logic;\r
- signal r_gcount_w21: std_logic;\r
- signal r_gcount_w1: std_logic;\r
- signal r_gcount_w22: std_logic;\r
- signal r_gcount_w2: std_logic;\r
- signal r_gcount_w23: std_logic;\r
- signal r_gcount_w3: std_logic;\r
- signal r_gcount_w24: std_logic;\r
- signal r_gcount_w4: std_logic;\r
- signal r_gcount_w25: std_logic;\r
- signal r_gcount_w5: std_logic;\r
- signal r_gcount_w26: std_logic;\r
- signal r_gcount_w6: std_logic;\r
- signal r_gcount_w27: std_logic;\r
- signal r_gcount_w7: std_logic;\r
- signal r_gcount_w28: std_logic;\r
- signal r_gcount_w8: std_logic;\r
- signal r_gcount_w29: std_logic;\r
- signal r_gcount_w9: std_logic;\r
- signal r_gcount_w210: std_logic;\r
- signal r_gcount_w10: std_logic;\r
- signal r_gcount_w211: std_logic;\r
- signal r_gcount_w11: std_logic;\r
- signal empty_i: std_logic;\r
- signal rRst: std_logic;\r
- signal full_i: std_logic;\r
- signal iwcount_0: std_logic;\r
- signal iwcount_1: std_logic;\r
- signal w_gctr_ci: std_logic;\r
- signal iwcount_2: std_logic;\r
- signal iwcount_3: std_logic;\r
- signal co0: std_logic;\r
- signal iwcount_4: std_logic;\r
- signal iwcount_5: std_logic;\r
- signal co1: std_logic;\r
- signal iwcount_6: std_logic;\r
- signal iwcount_7: std_logic;\r
- signal co2: std_logic;\r
- signal iwcount_8: std_logic;\r
- signal iwcount_9: std_logic;\r
- signal co3: std_logic;\r
- signal iwcount_10: std_logic;\r
- signal iwcount_11: std_logic;\r
- signal co5: std_logic;\r
- signal wcount_11: std_logic;\r
- signal co4: std_logic;\r
- signal scuba_vhi: std_logic;\r
- signal ircount_0: std_logic;\r
- signal ircount_1: std_logic;\r
- signal r_gctr_ci: std_logic;\r
- signal ircount_2: std_logic;\r
- signal ircount_3: std_logic;\r
- signal co0_1: std_logic;\r
- signal ircount_4: std_logic;\r
- signal ircount_5: std_logic;\r
- signal co1_1: std_logic;\r
- signal ircount_6: std_logic;\r
- signal ircount_7: std_logic;\r
- signal co2_1: std_logic;\r
- signal ircount_8: std_logic;\r
- signal ircount_9: std_logic;\r
- signal co3_1: std_logic;\r
- signal ircount_10: std_logic;\r
- signal ircount_11: std_logic;\r
- signal co5_1: std_logic;\r
- signal rcount_11: std_logic;\r
- signal co4_1: std_logic;\r
- signal rden_i: std_logic;\r
- signal cmp_ci: std_logic;\r
- signal wcount_r0: std_logic;\r
- signal wcount_r1: std_logic;\r
- signal rcount_0: std_logic;\r
- signal rcount_1: std_logic;\r
- signal co0_2: std_logic;\r
- signal wcount_r2: std_logic;\r
- signal wcount_r3: std_logic;\r
- signal rcount_2: std_logic;\r
- signal rcount_3: std_logic;\r
- signal co1_2: std_logic;\r
- signal wcount_r4: std_logic;\r
- signal wcount_r5: std_logic;\r
- signal rcount_4: std_logic;\r
- signal rcount_5: std_logic;\r
- signal co2_2: std_logic;\r
- signal wcount_r6: std_logic;\r
- signal wcount_r7: std_logic;\r
- signal rcount_6: std_logic;\r
- signal rcount_7: std_logic;\r
- signal co3_2: std_logic;\r
- signal w_g2b_xor_cluster_0: std_logic;\r
- signal wcount_r9: std_logic;\r
- signal rcount_8: std_logic;\r
- signal rcount_9: std_logic;\r
- signal co4_2: std_logic;\r
- signal wcount_r10: std_logic;\r
- signal empty_cmp_clr: std_logic;\r
- signal rcount_10: std_logic;\r
- signal empty_cmp_set: std_logic;\r
- signal empty_d: std_logic;\r
- signal empty_d_c: std_logic;\r
- signal wren_i: std_logic;\r
- signal cmp_ci_1: std_logic;\r
- signal rcount_w0: std_logic;\r
- signal rcount_w1: std_logic;\r
- signal wcount_0: std_logic;\r
- signal wcount_1: std_logic;\r
- signal co0_3: std_logic;\r
- signal rcount_w2: std_logic;\r
- signal rcount_w3: std_logic;\r
- signal wcount_2: std_logic;\r
- signal wcount_3: std_logic;\r
- signal co1_3: std_logic;\r
- signal rcount_w4: std_logic;\r
- signal rcount_w5: std_logic;\r
- signal wcount_4: std_logic;\r
- signal wcount_5: std_logic;\r
- signal co2_3: std_logic;\r
- signal rcount_w6: std_logic;\r
- signal rcount_w7: std_logic;\r
- signal wcount_6: std_logic;\r
- signal wcount_7: std_logic;\r
- signal co3_3: std_logic;\r
- signal r_g2b_xor_cluster_0: std_logic;\r
- signal rcount_w9: std_logic;\r
- signal wcount_8: std_logic;\r
- signal wcount_9: std_logic;\r
- signal co4_3: std_logic;\r
- signal rcount_w10: std_logic;\r
- signal full_cmp_clr: std_logic;\r
- signal wcount_10: std_logic;\r
- signal full_cmp_set: std_logic;\r
- signal full_d: std_logic;\r
- signal full_d_c: std_logic;\r
- signal scuba_vlo: std_logic;\r
-\r
- -- local component declarations\r
- component AGEB2\r
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic; \r
- B1: in std_logic; CI: in std_logic; GE: out std_logic);\r
- end component;\r
- component AND2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component CU2\r
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; \r
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);\r
- end component;\r
- component FADD2B\r
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic; \r
- B1: in std_logic; CI: in std_logic; COUT: out std_logic; \r
- S0: out std_logic; S1: out std_logic);\r
- end component;\r
- component FD1P3BX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; SP: in std_logic; CK: in std_logic; \r
- PD: in std_logic; Q: out std_logic);\r
- end component;\r
- component FD1P3DX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; SP: in std_logic; CK: in std_logic; \r
- CD: in std_logic; Q: out std_logic);\r
- end component;\r
- component FD1S3BX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; CK: in std_logic; PD: in std_logic; \r
- Q: out std_logic);\r
- end component;\r
- component FD1S3DX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; CK: in std_logic; CD: in std_logic; \r
- Q: out std_logic);\r
- end component;\r
- component INV\r
- port (A: in std_logic; Z: out std_logic);\r
- end component;\r
- component OR2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component ROM16X1\r
- -- synopsys translate_off\r
- generic (initval : in String);\r
- -- synopsys translate_on\r
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; \r
- AD0: in std_logic; DO0: out std_logic);\r
- end component;\r
- component VHI\r
- port (Z: out std_logic);\r
- end component;\r
- component VLO\r
- port (Z: out std_logic);\r
- end component;\r
- component XOR2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component DP16KB\r
- -- synopsys translate_off\r
- generic (GSR : in String; WRITEMODE_B : in String; \r
- CSDECODE_B : in std_logic_vector(2 downto 0); \r
- CSDECODE_A : in std_logic_vector(2 downto 0); \r
- WRITEMODE_A : in String; RESETMODE : in String; \r
- REGMODE_B : in String; REGMODE_A : in String; \r
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);\r
- -- synopsys translate_on\r
- port (DIA0: in std_logic; DIA1: in std_logic; \r
- DIA2: in std_logic; DIA3: in std_logic; \r
- DIA4: in std_logic; DIA5: in std_logic; \r
- DIA6: in std_logic; DIA7: in std_logic; \r
- DIA8: in std_logic; DIA9: in std_logic; \r
- DIA10: in std_logic; DIA11: in std_logic; \r
- DIA12: in std_logic; DIA13: in std_logic; \r
- DIA14: in std_logic; DIA15: in std_logic; \r
- DIA16: in std_logic; DIA17: in std_logic; \r
- ADA0: in std_logic; ADA1: in std_logic; \r
- ADA2: in std_logic; ADA3: in std_logic; \r
- ADA4: in std_logic; ADA5: in std_logic; \r
- ADA6: in std_logic; ADA7: in std_logic; \r
- ADA8: in std_logic; ADA9: in std_logic; \r
- ADA10: in std_logic; ADA11: in std_logic; \r
- ADA12: in std_logic; ADA13: in std_logic; \r
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; \r
- CSA0: in std_logic; CSA1: in std_logic; \r
- CSA2: in std_logic; RSTA: in std_logic; \r
- DIB0: in std_logic; DIB1: in std_logic; \r
- DIB2: in std_logic; DIB3: in std_logic; \r
- DIB4: in std_logic; DIB5: in std_logic; \r
- DIB6: in std_logic; DIB7: in std_logic; \r
- DIB8: in std_logic; DIB9: in std_logic; \r
- DIB10: in std_logic; DIB11: in std_logic; \r
- DIB12: in std_logic; DIB13: in std_logic; \r
- DIB14: in std_logic; DIB15: in std_logic; \r
- DIB16: in std_logic; DIB17: in std_logic; \r
- ADB0: in std_logic; ADB1: in std_logic; \r
- ADB2: in std_logic; ADB3: in std_logic; \r
- ADB4: in std_logic; ADB5: in std_logic; \r
- ADB6: in std_logic; ADB7: in std_logic; \r
- ADB8: in std_logic; ADB9: in std_logic; \r
- ADB10: in std_logic; ADB11: in std_logic; \r
- ADB12: in std_logic; ADB13: in std_logic; \r
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; \r
- CSB0: in std_logic; CSB1: in std_logic; \r
- CSB2: in std_logic; RSTB: in std_logic; \r
- DOA0: out std_logic; DOA1: out std_logic; \r
- DOA2: out std_logic; DOA3: out std_logic; \r
- DOA4: out std_logic; DOA5: out std_logic; \r
- DOA6: out std_logic; DOA7: out std_logic; \r
- DOA8: out std_logic; DOA9: out std_logic; \r
- DOA10: out std_logic; DOA11: out std_logic; \r
- DOA12: out std_logic; DOA13: out std_logic; \r
- DOA14: out std_logic; DOA15: out std_logic; \r
- DOA16: out std_logic; DOA17: out std_logic; \r
- DOB0: out std_logic; DOB1: out std_logic; \r
- DOB2: out std_logic; DOB3: out std_logic; \r
- DOB4: out std_logic; DOB5: out std_logic; \r
- DOB6: out std_logic; DOB7: out std_logic; \r
- DOB8: out std_logic; DOB9: out std_logic; \r
- DOB10: out std_logic; DOB11: out std_logic; \r
- DOB12: out std_logic; DOB13: out std_logic; \r
- DOB14: out std_logic; DOB15: out std_logic; \r
- DOB16: out std_logic; DOB17: out std_logic);\r
- end component;\r
- attribute initval : string; \r
- attribute MEM_LPC_FILE : string; \r
- attribute MEM_INIT_FILE : string; \r
- attribute CSDECODE_B : string; \r
- attribute CSDECODE_A : string; \r
- attribute WRITEMODE_B : string; \r
- attribute WRITEMODE_A : string; \r
- attribute RESETMODE : string; \r
- attribute REGMODE_B : string; \r
- attribute REGMODE_A : string; \r
- attribute DATA_WIDTH_B : string; \r
- attribute DATA_WIDTH_A : string; \r
- attribute GSR : string; \r
- attribute initval of LUT4_31 : label is "0x6996";\r
- attribute initval of LUT4_30 : label is "0x6996";\r
- attribute initval of LUT4_29 : label is "0x6996";\r
- attribute initval of LUT4_28 : label is "0x6996";\r
- attribute initval of LUT4_27 : label is "0x6996";\r
- attribute initval of LUT4_26 : label is "0x6996";\r
- attribute initval of LUT4_25 : label is "0x6996";\r
- attribute initval of LUT4_24 : label is "0x6996";\r
- attribute initval of LUT4_23 : label is "0x6996";\r
- attribute initval of LUT4_22 : label is "0x6996";\r
- attribute initval of LUT4_21 : label is "0x6996";\r
- attribute initval of LUT4_20 : label is "0x6996";\r
- attribute initval of LUT4_19 : label is "0x6996";\r
- attribute initval of LUT4_18 : label is "0x6996";\r
- attribute initval of LUT4_17 : label is "0x6996";\r
- attribute initval of LUT4_16 : label is "0x6996";\r
- attribute initval of LUT4_15 : label is "0x6996";\r
- attribute initval of LUT4_14 : label is "0x6996";\r
- attribute initval of LUT4_13 : label is "0x6996";\r
- attribute initval of LUT4_12 : label is "0x6996";\r
- attribute initval of LUT4_11 : label is "0x6996";\r
- attribute initval of LUT4_10 : label is "0x6996";\r
- attribute initval of LUT4_9 : label is "0x6996";\r
- attribute initval of LUT4_8 : label is "0x6996";\r
- attribute initval of LUT4_7 : label is "0x6996";\r
- attribute initval of LUT4_6 : label is "0x6996";\r
- attribute initval of LUT4_5 : label is "0x6996";\r
- attribute initval of LUT4_4 : label is "0x6996";\r
- attribute initval of LUT4_3 : label is "0x0410";\r
- attribute initval of LUT4_2 : label is "0x1004";\r
- attribute initval of LUT4_1 : label is "0x0140";\r
- attribute initval of LUT4_0 : label is "0x4001";\r
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "9";\r
- attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "9";\r
- attribute GSR of FF_121 : label is "ENABLED";\r
- attribute GSR of FF_120 : label is "ENABLED";\r
- attribute GSR of FF_119 : label is "ENABLED";\r
- attribute GSR of FF_118 : label is "ENABLED";\r
- attribute GSR of FF_117 : label is "ENABLED";\r
- attribute GSR of FF_116 : label is "ENABLED";\r
- attribute GSR of FF_115 : label is "ENABLED";\r
- attribute GSR of FF_114 : label is "ENABLED";\r
- attribute GSR of FF_113 : label is "ENABLED";\r
- attribute GSR of FF_112 : label is "ENABLED";\r
- attribute GSR of FF_111 : label is "ENABLED";\r
- attribute GSR of FF_110 : label is "ENABLED";\r
- attribute GSR of FF_109 : label is "ENABLED";\r
- attribute GSR of FF_108 : label is "ENABLED";\r
- attribute GSR of FF_107 : label is "ENABLED";\r
- attribute GSR of FF_106 : label is "ENABLED";\r
- attribute GSR of FF_105 : label is "ENABLED";\r
- attribute GSR of FF_104 : label is "ENABLED";\r
- attribute GSR of FF_103 : label is "ENABLED";\r
- attribute GSR of FF_102 : label is "ENABLED";\r
- attribute GSR of FF_101 : label is "ENABLED";\r
- attribute GSR of FF_100 : label is "ENABLED";\r
- attribute GSR of FF_99 : label is "ENABLED";\r
- attribute GSR of FF_98 : label is "ENABLED";\r
- attribute GSR of FF_97 : label is "ENABLED";\r
- attribute GSR of FF_96 : label is "ENABLED";\r
- attribute GSR of FF_95 : label is "ENABLED";\r
- attribute GSR of FF_94 : label is "ENABLED";\r
- attribute GSR of FF_93 : label is "ENABLED";\r
- attribute GSR of FF_92 : label is "ENABLED";\r
- attribute GSR of FF_91 : label is "ENABLED";\r
- attribute GSR of FF_90 : label is "ENABLED";\r
- attribute GSR of FF_89 : label is "ENABLED";\r
- attribute GSR of FF_88 : label is "ENABLED";\r
- attribute GSR of FF_87 : label is "ENABLED";\r
- attribute GSR of FF_86 : label is "ENABLED";\r
- attribute GSR of FF_85 : label is "ENABLED";\r
- attribute GSR of FF_84 : label is "ENABLED";\r
- attribute GSR of FF_83 : label is "ENABLED";\r
- attribute GSR of FF_82 : label is "ENABLED";\r
- attribute GSR of FF_81 : label is "ENABLED";\r
- attribute GSR of FF_80 : label is "ENABLED";\r
- attribute GSR of FF_79 : label is "ENABLED";\r
- attribute GSR of FF_78 : label is "ENABLED";\r
- attribute GSR of FF_77 : label is "ENABLED";\r
- attribute GSR of FF_76 : label is "ENABLED";\r
- attribute GSR of FF_75 : label is "ENABLED";\r
- attribute GSR of FF_74 : label is "ENABLED";\r
- attribute GSR of FF_73 : label is "ENABLED";\r
- attribute GSR of FF_72 : label is "ENABLED";\r
- attribute GSR of FF_71 : label is "ENABLED";\r
- attribute GSR of FF_70 : label is "ENABLED";\r
- attribute GSR of FF_69 : label is "ENABLED";\r
- attribute GSR of FF_68 : label is "ENABLED";\r
- attribute GSR of FF_67 : label is "ENABLED";\r
- attribute GSR of FF_66 : label is "ENABLED";\r
- attribute GSR of FF_65 : label is "ENABLED";\r
- attribute GSR of FF_64 : label is "ENABLED";\r
- attribute GSR of FF_63 : label is "ENABLED";\r
- attribute GSR of FF_62 : label is "ENABLED";\r
- attribute GSR of FF_61 : label is "ENABLED";\r
- attribute GSR of FF_60 : label is "ENABLED";\r
- attribute GSR of FF_59 : label is "ENABLED";\r
- attribute GSR of FF_58 : label is "ENABLED";\r
- attribute GSR of FF_57 : label is "ENABLED";\r
- attribute GSR of FF_56 : label is "ENABLED";\r
- attribute GSR of FF_55 : label is "ENABLED";\r
- attribute GSR of FF_54 : label is "ENABLED";\r
- attribute GSR of FF_53 : label is "ENABLED";\r
- attribute GSR of FF_52 : label is "ENABLED";\r
- attribute GSR of FF_51 : label is "ENABLED";\r
- attribute GSR of FF_50 : label is "ENABLED";\r
- attribute GSR of FF_49 : label is "ENABLED";\r
- attribute GSR of FF_48 : label is "ENABLED";\r
- attribute GSR of FF_47 : label is "ENABLED";\r
- attribute GSR of FF_46 : label is "ENABLED";\r
- attribute GSR of FF_45 : label is "ENABLED";\r
- attribute GSR of FF_44 : label is "ENABLED";\r
- attribute GSR of FF_43 : label is "ENABLED";\r
- attribute GSR of FF_42 : label is "ENABLED";\r
- attribute GSR of FF_41 : label is "ENABLED";\r
- attribute GSR of FF_40 : label is "ENABLED";\r
- attribute GSR of FF_39 : label is "ENABLED";\r
- attribute GSR of FF_38 : label is "ENABLED";\r
- attribute GSR of FF_37 : label is "ENABLED";\r
- attribute GSR of FF_36 : label is "ENABLED";\r
- attribute GSR of FF_35 : label is "ENABLED";\r
- attribute GSR of FF_34 : label is "ENABLED";\r
- attribute GSR of FF_33 : label is "ENABLED";\r
- attribute GSR of FF_32 : label is "ENABLED";\r
- attribute GSR of FF_31 : label is "ENABLED";\r
- attribute GSR of FF_30 : label is "ENABLED";\r
- attribute GSR of FF_29 : label is "ENABLED";\r
- attribute GSR of FF_28 : label is "ENABLED";\r
- attribute GSR of FF_27 : label is "ENABLED";\r
- attribute GSR of FF_26 : label is "ENABLED";\r
- attribute GSR of FF_25 : label is "ENABLED";\r
- attribute GSR of FF_24 : label is "ENABLED";\r
- attribute GSR of FF_23 : label is "ENABLED";\r
- attribute GSR of FF_22 : label is "ENABLED";\r
- attribute GSR of FF_21 : label is "ENABLED";\r
- attribute GSR of FF_20 : label is "ENABLED";\r
- attribute GSR of FF_19 : label is "ENABLED";\r
- attribute GSR of FF_18 : label is "ENABLED";\r
- attribute GSR of FF_17 : label is "ENABLED";\r
- attribute GSR of FF_16 : label is "ENABLED";\r
- attribute GSR of FF_15 : label is "ENABLED";\r
- attribute GSR of FF_14 : label is "ENABLED";\r
- attribute GSR of FF_13 : label is "ENABLED";\r
- attribute GSR of FF_12 : label is "ENABLED";\r
- attribute GSR of FF_11 : label is "ENABLED";\r
- attribute GSR of FF_10 : label is "ENABLED";\r
- attribute GSR of FF_9 : label is "ENABLED";\r
- attribute GSR of FF_8 : label is "ENABLED";\r
- attribute GSR of FF_7 : label is "ENABLED";\r
- attribute GSR of FF_6 : label is "ENABLED";\r
- attribute GSR of FF_5 : label is "ENABLED";\r
- attribute GSR of FF_4 : label is "ENABLED";\r
- attribute GSR of FF_3 : label is "ENABLED";\r
- attribute GSR of FF_2 : label is "ENABLED";\r
- attribute GSR of FF_1 : label is "ENABLED";\r
- attribute GSR of FF_0 : label is "ENABLED";\r
- attribute syn_keep : boolean;\r
-\r
-begin\r
- -- component instantiation statements\r
- AND2_t24: AND2\r
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);\r
-\r
- INV_1: INV\r
- port map (A=>full_i, Z=>invout_1);\r
-\r
- AND2_t23: AND2\r
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);\r
-\r
- INV_0: INV\r
- port map (A=>empty_i, Z=>invout_0);\r
-\r
- OR2_t22: OR2\r
- port map (A=>Reset, B=>RPReset, Z=>rRst);\r
-\r
- XOR2_t21: XOR2\r
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);\r
-\r
- XOR2_t20: XOR2\r
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);\r
-\r
- XOR2_t19: XOR2\r
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);\r
-\r
- XOR2_t18: XOR2\r
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);\r
-\r
- XOR2_t17: XOR2\r
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);\r
-\r
- XOR2_t16: XOR2\r
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);\r
-\r
- XOR2_t15: XOR2\r
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);\r
-\r
- XOR2_t14: XOR2\r
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);\r
-\r
- XOR2_t13: XOR2\r
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);\r
-\r
- XOR2_t12: XOR2\r
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);\r
-\r
- XOR2_t11: XOR2\r
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);\r
-\r
- XOR2_t10: XOR2\r
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);\r
-\r
- XOR2_t9: XOR2\r
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);\r
-\r
- XOR2_t8: XOR2\r
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);\r
-\r
- XOR2_t7: XOR2\r
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);\r
-\r
- XOR2_t6: XOR2\r
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);\r
-\r
- XOR2_t5: XOR2\r
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);\r
-\r
- XOR2_t4: XOR2\r
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);\r
-\r
- XOR2_t3: XOR2\r
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);\r
-\r
- XOR2_t2: XOR2\r
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);\r
-\r
- XOR2_t1: XOR2\r
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);\r
-\r
- XOR2_t0: XOR2\r
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);\r
-\r
- LUT4_31: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, \r
- AD1=>w_gcount_r210, AD0=>w_gcount_r211, \r
- DO0=>w_g2b_xor_cluster_0);\r
-\r
- LUT4_30: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, \r
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, \r
- DO0=>w_g2b_xor_cluster_1);\r
-\r
- LUT4_29: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, \r
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, \r
- DO0=>w_g2b_xor_cluster_2);\r
-\r
- LUT4_28: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>wcount_r10);\r
-\r
- LUT4_27: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, \r
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);\r
-\r
- LUT4_26: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, \r
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);\r
-\r
- LUT4_25: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, \r
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);\r
-\r
- LUT4_24: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, \r
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);\r
-\r
- LUT4_23: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);\r
-\r
- LUT4_22: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);\r
-\r
- LUT4_21: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);\r
-\r
- LUT4_20: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, \r
- AD1=>w_gcount_r23, AD0=>scuba_vlo, \r
- DO0=>w_g2b_xor_cluster_2_1);\r
-\r
- LUT4_19: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);\r
-\r
- LUT4_18: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);\r
-\r
- LUT4_17: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, \r
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, \r
- DO0=>r_g2b_xor_cluster_0);\r
-\r
- LUT4_16: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, \r
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, \r
- DO0=>r_g2b_xor_cluster_1);\r
-\r
- LUT4_15: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, \r
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, \r
- DO0=>r_g2b_xor_cluster_2);\r
-\r
- LUT4_14: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>rcount_w10);\r
-\r
- LUT4_13: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, \r
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);\r
-\r
- LUT4_12: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, \r
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);\r
-\r
- LUT4_11: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, \r
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);\r
-\r
- LUT4_10: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, \r
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);\r
-\r
- LUT4_9: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);\r
-\r
- LUT4_8: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);\r
-\r
- LUT4_7: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);\r
-\r
- LUT4_6: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, \r
- AD1=>r_gcount_w23, AD0=>scuba_vlo, \r
- DO0=>r_g2b_xor_cluster_2_1);\r
-\r
- LUT4_5: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);\r
-\r
- LUT4_4: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);\r
-\r
- LUT4_3: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x0410")\r
- -- synopsys translate_on\r
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, \r
- AD0=>scuba_vlo, DO0=>empty_cmp_set);\r
-\r
- LUT4_2: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x1004")\r
- -- synopsys translate_on\r
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, \r
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);\r
-\r
- LUT4_1: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x0140")\r
- -- synopsys translate_on\r
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, \r
- AD0=>scuba_vlo, DO0=>full_cmp_set);\r
-\r
- LUT4_0: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x4001")\r
- -- synopsys translate_on\r
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, \r
- AD0=>scuba_vlo, DO0=>full_cmp_clr);\r
-\r
- pdp_ram_0_0_0: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, \r
- DATA_WIDTH_A=> 9)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), \r
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), \r
- DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, \r
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, \r
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, \r
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, \r
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, \r
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, \r
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, \r
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, \r
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, \r
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, \r
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, \r
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, \r
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, \r
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, \r
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, \r
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, \r
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, \r
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, \r
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, \r
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, \r
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, \r
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, \r
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, \r
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, \r
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), \r
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), \r
- DOB6=>Q(6), DOB7=>Q(7), DOB8=>open, DOB9=>open, DOB10=>open, \r
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, \r
- DOB15=>open, DOB16=>open, DOB17=>open);\r
-\r
- FF_121: FD1P3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, \r
- Q=>wcount_0);\r
-\r
- FF_120: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_1);\r
-\r
- FF_119: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_2);\r
-\r
- FF_118: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_3);\r
-\r
- FF_117: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_4);\r
-\r
- FF_116: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_5);\r
-\r
- FF_115: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_6);\r
-\r
- FF_114: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_7);\r
-\r
- FF_113: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_8);\r
-\r
- FF_112: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_9);\r
-\r
- FF_111: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_10);\r
-\r
- FF_110: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_11);\r
-\r
- FF_109: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_0);\r
-\r
- FF_108: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_1);\r
-\r
- FF_107: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_2);\r
-\r
- FF_106: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_3);\r
-\r
- FF_105: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_4);\r
-\r
- FF_104: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_5);\r
-\r
- FF_103: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_6);\r
-\r
- FF_102: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_7);\r
-\r
- FF_101: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_8);\r
-\r
- FF_100: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_9);\r
-\r
- FF_99: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_10);\r
-\r
- FF_98: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_11);\r
-\r
- FF_97: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_0);\r
-\r
- FF_96: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_1);\r
-\r
- FF_95: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_2);\r
-\r
- FF_94: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_3);\r
-\r
- FF_93: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_4);\r
-\r
- FF_92: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_5);\r
-\r
- FF_91: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_6);\r
-\r
- FF_90: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_7);\r
-\r
- FF_89: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_8);\r
-\r
- FF_88: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_9);\r
-\r
- FF_87: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_10);\r
-\r
- FF_86: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_11);\r
-\r
- FF_85: FD1P3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, \r
- Q=>rcount_0);\r
-\r
- FF_84: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_1);\r
-\r
- FF_83: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_2);\r
-\r
- FF_82: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_3);\r
-\r
- FF_81: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_4);\r
-\r
- FF_80: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_5);\r
-\r
- FF_79: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_6);\r
-\r
- FF_78: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_7);\r
-\r
- FF_77: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_8);\r
-\r
- FF_76: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_9);\r
-\r
- FF_75: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_10);\r
-\r
- FF_74: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_11);\r
-\r
- FF_73: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_0);\r
-\r
- FF_72: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_1);\r
-\r
- FF_71: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_2);\r
-\r
- FF_70: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_3);\r
-\r
- FF_69: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_4);\r
-\r
- FF_68: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_5);\r
-\r
- FF_67: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_6);\r
-\r
- FF_66: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_7);\r
-\r
- FF_65: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_8);\r
-\r
- FF_64: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_9);\r
-\r
- FF_63: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_10);\r
-\r
- FF_62: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_11);\r
-\r
- FF_61: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_0);\r
-\r
- FF_60: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_1);\r
-\r
- FF_59: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_2);\r
-\r
- FF_58: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_3);\r
-\r
- FF_57: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_4);\r
-\r
- FF_56: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_5);\r
-\r
- FF_55: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_6);\r
-\r
- FF_54: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_7);\r
-\r
- FF_53: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_8);\r
-\r
- FF_52: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_9);\r
-\r
- FF_51: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_10);\r
-\r
- FF_50: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_11);\r
-\r
- FF_49: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);\r
-\r
- FF_48: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);\r
-\r
- FF_47: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);\r
-\r
- FF_46: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);\r
-\r
- FF_45: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);\r
-\r
- FF_44: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);\r
-\r
- FF_43: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);\r
-\r
- FF_42: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);\r
-\r
- FF_41: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);\r
-\r
- FF_40: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);\r
-\r
- FF_39: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r10);\r
-\r
- FF_38: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r11);\r
-\r
- FF_37: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);\r
-\r
- FF_36: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);\r
-\r
- FF_35: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);\r
-\r
- FF_34: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);\r
-\r
- FF_33: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);\r
-\r
- FF_32: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);\r
-\r
- FF_31: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);\r
-\r
- FF_30: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);\r
-\r
- FF_29: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);\r
-\r
- FF_28: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);\r
-\r
- FF_27: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);\r
-\r
- FF_26: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);\r
-\r
- FF_25: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r20);\r
-\r
- FF_24: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r21);\r
-\r
- FF_23: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r22);\r
-\r
- FF_22: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r23);\r
-\r
- FF_21: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r24);\r
-\r
- FF_20: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r25);\r
-\r
- FF_19: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r26);\r
-\r
- FF_18: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r27);\r
-\r
- FF_17: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r28);\r
-\r
- FF_16: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r29);\r
-\r
- FF_15: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r210);\r
-\r
- FF_14: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r211);\r
-\r
- FF_13: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);\r
-\r
- FF_12: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);\r
-\r
- FF_11: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);\r
-\r
- FF_10: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);\r
-\r
- FF_9: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);\r
-\r
- FF_8: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);\r
-\r
- FF_7: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);\r
-\r
- FF_6: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);\r
-\r
- FF_5: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);\r
-\r
- FF_4: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);\r
-\r
- FF_3: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w210);\r
-\r
- FF_2: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w211);\r
-\r
- FF_1: FD1S3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);\r
-\r
- FF_0: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);\r
-\r
- w_gctr_cia: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, \r
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, \r
- S1=>open);\r
-\r
- w_gctr_0: CU2\r
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, \r
- NC0=>iwcount_0, NC1=>iwcount_1);\r
-\r
- w_gctr_1: CU2\r
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, \r
- NC0=>iwcount_2, NC1=>iwcount_3);\r
-\r
- w_gctr_2: CU2\r
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, \r
- NC0=>iwcount_4, NC1=>iwcount_5);\r
-\r
- w_gctr_3: CU2\r
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, \r
- NC0=>iwcount_6, NC1=>iwcount_7);\r
-\r
- w_gctr_4: CU2\r
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, \r
- NC0=>iwcount_8, NC1=>iwcount_9);\r
-\r
- w_gctr_5: CU2\r
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, \r
- NC0=>iwcount_10, NC1=>iwcount_11);\r
-\r
- scuba_vhi_inst: VHI\r
- port map (Z=>scuba_vhi);\r
-\r
- r_gctr_cia: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, \r
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, \r
- S1=>open);\r
-\r
- r_gctr_0: CU2\r
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, \r
- NC0=>ircount_0, NC1=>ircount_1);\r
-\r
- r_gctr_1: CU2\r
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, \r
- NC0=>ircount_2, NC1=>ircount_3);\r
-\r
- r_gctr_2: CU2\r
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, \r
- NC0=>ircount_4, NC1=>ircount_5);\r
-\r
- r_gctr_3: CU2\r
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, \r
- NC0=>ircount_6, NC1=>ircount_7);\r
-\r
- r_gctr_4: CU2\r
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, \r
- NC0=>ircount_8, NC1=>ircount_9);\r
-\r
- r_gctr_5: CU2\r
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, \r
- NC0=>ircount_10, NC1=>ircount_11);\r
-\r
- empty_cmp_ci_a: FADD2B\r
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, \r
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);\r
-\r
- empty_cmp_0: AGEB2\r
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, \r
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);\r
-\r
- empty_cmp_1: AGEB2\r
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, \r
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);\r
-\r
- empty_cmp_2: AGEB2\r
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, \r
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);\r
-\r
- empty_cmp_3: AGEB2\r
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, \r
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);\r
-\r
- empty_cmp_4: AGEB2\r
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, \r
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);\r
-\r
- empty_cmp_5: AGEB2\r
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, \r
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);\r
-\r
- a0: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, \r
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, \r
- S1=>open);\r
-\r
- full_cmp_ci_a: FADD2B\r
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, \r
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);\r
-\r
- full_cmp_0: AGEB2\r
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, \r
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);\r
-\r
- full_cmp_1: AGEB2\r
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, \r
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);\r
-\r
- full_cmp_2: AGEB2\r
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, \r
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);\r
-\r
- full_cmp_3: AGEB2\r
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, \r
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);\r
-\r
- full_cmp_4: AGEB2\r
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, \r
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);\r
-\r
- full_cmp_5: AGEB2\r
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, \r
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);\r
-\r
- scuba_vlo_inst: VLO\r
- port map (Z=>scuba_vlo);\r
-\r
- a1: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, \r
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, \r
- S1=>open);\r
-\r
- Empty <= empty_i;\r
- Full <= full_i;\r
-end Structure;\r
-\r
--- synopsys translate_off\r
-library ecp2m;\r
-configuration Structure_CON of fifo_2048x8 is\r
- for Structure\r
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;\r
- for all:AND2 use entity ecp2m.AND2(V); end for;\r
- for all:CU2 use entity ecp2m.CU2(V); end for;\r
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;\r
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;\r
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;\r
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;\r
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;\r
- for all:INV use entity ecp2m.INV(V); end for;\r
- for all:OR2 use entity ecp2m.OR2(V); end for;\r
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;\r
- for all:VHI use entity ecp2m.VHI(V); end for;\r
- for all:VLO use entity ecp2m.VLO(V); end for;\r
- for all:XOR2 use entity ecp2m.XOR2(V); end for;\r
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;\r
- end for;\r
-end Structure_CON;\r
-\r
--- synopsys translate_on\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)\r
--- Module Version: 5.2\r
--- Sat Dec 26 00:12:59 2009\r
-\r
--- parameterized module component declaration\r
-component fifo_2048x8\r
- port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; \r
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; \r
- Reset: in std_logic; RPReset: in std_logic; \r
- Q: out std_logic_vector(7 downto 0); Empty: out std_logic; \r
- Full: out std_logic);\r
-end component;\r
-\r
--- parameterized module component instance\r
-__ : fifo_2048x8\r
- port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, \r
- RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, \r
- Full=>__);\r
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_2048x8x16
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/05/2011
-Time=18:26:53
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=2048
-Width=9
-RDepth=1024
-RWidth=18
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 9 -depth 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -e
-
--- Mon Dec 5 18:26:53 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_2048x8x16 is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_2048x8x16;
-
-architecture Structure of fifo_2048x8x16 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal wcount_r0: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5: std_logic;
- signal wcount_11: std_logic;
- signal co4: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal co5_1: std_logic;
- signal rcount_10: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r7: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w9: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_10: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8x16.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t23: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t22: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t21: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t20: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t19: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t18: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t17: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t16: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t15: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t14: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t13: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t12: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t11: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t10: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t9: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t8: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t7: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t6: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t5: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t4: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t3: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t2: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t1: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t0: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>r_gcount_w210,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_gcount_w26,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
- ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3,
- ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, ADB11=>rptr_7,
- ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5),
- DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10),
- DOB11=>Q(11), DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14),
- DOB15=>Q(15), DOB16=>Q(16), DOB17=>Q(17));
-
- FF_116: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_115: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_114: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_113: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_112: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_111: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_110: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_109: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_108: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_107: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_106: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_105: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_104: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_103: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_102: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_101: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_100: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_99: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_98: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_97: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_96: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_95: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_94: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_93: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_92: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_91: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_90: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_89: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_88: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_87: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_86: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_85: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_84: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_83: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_82: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_81: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_80: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_79: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_78: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_77: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_76: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_75: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_74: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_73: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_72: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_71: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_70: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_66: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_65: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_64: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_63: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_62: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_59: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_58: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_57: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_56: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_55: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_54: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_53: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_52: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_51: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_50: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_49: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_48: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1,
- NC0=>ircount_10, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r1,
- B1=>wcount_r2, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r7,
- B1=>w_g2b_xor_cluster_0, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
- B1=>rcount_w0, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w1,
- B1=>rcount_w2, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w8, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w9,
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_2048x8x16 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Mon Dec 5 18:26:53 2011
-
--- parameterized module component declaration
-component fifo_2048x8x16
- port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_2048x8x16
- port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(17 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-5F900C\r
-SpeedGrade=-5\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=FIFO_DC\r
-CoreRevision=5.3\r
-ModuleName=fifo_32kx16x8_mb\r
-SourceFormat=Schematic/VHDL\r
-ParameterFileVersion=1.0\r
-Date=02/05/2010\r
-Time=16:48:12\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-FIFOImp=EBR Based\r
-Depth=32768\r
-Width=16\r
-RDepth=65536\r
-RWidth=8\r
-regout=0\r
-CtrlByRdEn=0\r
-EmpFlg=1\r
-PeMode=Dynamic - Single Threshold\r
-PeAssert=16\r
-PeDeassert=12\r
-FullFlg=1\r
-PfMode=Dynamic - Single Threshold\r
-PfAssert=32752\r
-PfDeassert=506\r
-RDataCount=1\r
-WDataCount=1\r
-EnECC=0\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
--- Module Version: 5.3
---X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e
-
--- Fri Feb 05 16:48:13 2010
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity fifo_32kx16x8_mb is
- port (
- Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(7 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end fifo_32kx16x8_mb;
-
-architecture Structure of fifo_32kx16x8_mb is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal rcount_w0: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal rcnt_reg_15_inv: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal wptr_15: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_16: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal rcnt_reg_16: std_logic;
- signal empty_i: std_logic;
- signal full_i: std_logic;
- signal rRst: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co7: std_logic;
- signal wcount_15: std_logic;
- signal co6: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8: std_logic;
- signal rcount_16: std_logic;
- signal co7_1: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal wcnt_sub_0: std_logic;
- signal wcnt_sub_1: std_logic;
- signal wcnt_sub_2: std_logic;
- signal co0_2: std_logic;
- signal wcnt_sub_3: std_logic;
- signal wcnt_sub_4: std_logic;
- signal co1_2: std_logic;
- signal wcnt_sub_5: std_logic;
- signal wcnt_sub_6: std_logic;
- signal co2_2: std_logic;
- signal wcnt_sub_7: std_logic;
- signal wcnt_sub_8: std_logic;
- signal co3_2: std_logic;
- signal wcnt_sub_9: std_logic;
- signal wcnt_sub_10: std_logic;
- signal co4_2: std_logic;
- signal wcnt_sub_11: std_logic;
- signal wcnt_sub_12: std_logic;
- signal co5_2: std_logic;
- signal wcnt_sub_13: std_logic;
- signal wcnt_sub_14: std_logic;
- signal co6_2: std_logic;
- signal wcnt_sub_15: std_logic;
- signal co7_2: std_logic;
- signal wcnt_sub_msb: std_logic;
- signal rcnt_sub_0: std_logic;
- signal rcnt_sub_1: std_logic;
- signal rcnt_sub_2: std_logic;
- signal co0_3: std_logic;
- signal rcnt_sub_3: std_logic;
- signal rcnt_sub_4: std_logic;
- signal co1_3: std_logic;
- signal rcnt_sub_5: std_logic;
- signal rcnt_sub_6: std_logic;
- signal co2_3: std_logic;
- signal rcnt_sub_7: std_logic;
- signal rcnt_sub_8: std_logic;
- signal co3_3: std_logic;
- signal rcnt_sub_9: std_logic;
- signal rcnt_sub_10: std_logic;
- signal co4_3: std_logic;
- signal rcnt_sub_11: std_logic;
- signal rcnt_sub_12: std_logic;
- signal co5_3: std_logic;
- signal rcnt_sub_13: std_logic;
- signal rcnt_sub_14: std_logic;
- signal co6_3: std_logic;
- signal rcnt_sub_15: std_logic;
- signal rcnt_sub_16: std_logic;
- signal co7_3: std_logic;
- signal rcnt_sub_msb: std_logic;
- signal co8_1d: std_logic;
- signal co8_1: std_logic;
- signal wfill_sub_0: std_logic;
- signal wptr_0: std_logic;
- signal wfill_sub_1: std_logic;
- signal wfill_sub_2: std_logic;
- signal co0_4: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wfill_sub_3: std_logic;
- signal wfill_sub_4: std_logic;
- signal co1_4: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wfill_sub_5: std_logic;
- signal wfill_sub_6: std_logic;
- signal co2_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wfill_sub_7: std_logic;
- signal wfill_sub_8: std_logic;
- signal co3_4: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wfill_sub_9: std_logic;
- signal wfill_sub_10: std_logic;
- signal co4_4: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wfill_sub_11: std_logic;
- signal wfill_sub_12: std_logic;
- signal co5_4: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wfill_sub_13: std_logic;
- signal wfill_sub_14: std_logic;
- signal co6_4: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wfill_sub_15: std_logic;
- signal co7_4: std_logic;
- signal wfill_sub_msb: std_logic;
- signal rfill_sub_0: std_logic;
- signal rptr_0: std_logic;
- signal scuba_vhi: std_logic;
- signal rfill_sub_1: std_logic;
- signal rfill_sub_2: std_logic;
- signal co0_5: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rfill_sub_3: std_logic;
- signal rfill_sub_4: std_logic;
- signal co1_5: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rfill_sub_5: std_logic;
- signal rfill_sub_6: std_logic;
- signal co2_5: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rfill_sub_7: std_logic;
- signal rfill_sub_8: std_logic;
- signal co3_5: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rfill_sub_9: std_logic;
- signal rfill_sub_10: std_logic;
- signal co4_5: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rfill_sub_11: std_logic;
- signal rfill_sub_12: std_logic;
- signal co5_5: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rfill_sub_13: std_logic;
- signal rfill_sub_14: std_logic;
- signal co6_5: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rfill_sub_15: std_logic;
- signal rfill_sub_16: std_logic;
- signal co7_5: std_logic;
- signal rptr_15: std_logic;
- signal rfill_sub_msb: std_logic;
- signal co8_2d: std_logic;
- signal co8_2: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_6: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_6: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_6: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_6: std_logic;
- signal wcount_r7: std_logic;
- signal wcount_r8: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_6: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_6: std_logic;
- signal wcount_r11: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_6: std_logic;
- signal wcount_r13: std_logic;
- signal wcount_r14: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_6: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_7: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_7: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_7: std_logic;
- signal rcount_w7: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_7: std_logic;
- signal rcount_w9: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_7: std_logic;
- signal rcount_w11: std_logic;
- signal rcount_w12: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w14: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_7: std_logic;
- signal rcount_w15: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_14: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal rcnt_reg_0: std_logic;
- signal rcnt_reg_1: std_logic;
- signal co0_8: std_logic;
- signal rcnt_reg_2: std_logic;
- signal rcnt_reg_3: std_logic;
- signal co1_8: std_logic;
- signal rcnt_reg_4: std_logic;
- signal rcnt_reg_5: std_logic;
- signal co2_8: std_logic;
- signal rcnt_reg_6: std_logic;
- signal rcnt_reg_7: std_logic;
- signal co3_8: std_logic;
- signal rcnt_reg_8: std_logic;
- signal rcnt_reg_9: std_logic;
- signal co4_8: std_logic;
- signal rcnt_reg_10: std_logic;
- signal rcnt_reg_11: std_logic;
- signal co5_8: std_logic;
- signal rcnt_reg_12: std_logic;
- signal rcnt_reg_13: std_logic;
- signal co6_8: std_logic;
- signal rcnt_reg_14: std_logic;
- signal rcnt_reg_15: std_logic;
- signal co7_7: std_logic;
- signal ae_clrsig: std_logic;
- signal ae_setsig: std_logic;
- signal ae_d: std_logic;
- signal ae_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_3: std_logic;
- signal wcnt_reg_0: std_logic;
- signal wcnt_reg_1: std_logic;
- signal co0_9: std_logic;
- signal wcnt_reg_2: std_logic;
- signal wcnt_reg_3: std_logic;
- signal co1_9: std_logic;
- signal wcnt_reg_4: std_logic;
- signal wcnt_reg_5: std_logic;
- signal co2_9: std_logic;
- signal wcnt_reg_6: std_logic;
- signal wcnt_reg_7: std_logic;
- signal co3_9: std_logic;
- signal wcnt_reg_8: std_logic;
- signal wcnt_reg_9: std_logic;
- signal co4_9: std_logic;
- signal wcnt_reg_10: std_logic;
- signal wcnt_reg_11: std_logic;
- signal co5_9: std_logic;
- signal wcnt_reg_12: std_logic;
- signal wcnt_reg_13: std_logic;
- signal co6_9: std_logic;
- signal wcnt_reg_14: std_logic;
- signal wcnt_reg_15: std_logic;
- signal af_d: std_logic;
- signal af_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX41
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
- Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
- attribute initval of LUT4_52 : label is "0x6996";
- attribute initval of LUT4_51 : label is "0x6996";
- attribute initval of LUT4_50 : label is "0x6996";
- attribute initval of LUT4_49 : label is "0x6996";
- attribute initval of LUT4_48 : label is "0x6996";
- attribute initval of LUT4_47 : label is "0x6996";
- attribute initval of LUT4_46 : label is "0x6996";
- attribute initval of LUT4_45 : label is "0x6996";
- attribute initval of LUT4_44 : label is "0x6996";
- attribute initval of LUT4_43 : label is "0x6996";
- attribute initval of LUT4_42 : label is "0x6996";
- attribute initval of LUT4_41 : label is "0x6996";
- attribute initval of LUT4_40 : label is "0x6996";
- attribute initval of LUT4_39 : label is "0x6996";
- attribute initval of LUT4_38 : label is "0x6996";
- attribute initval of LUT4_37 : label is "0x6996";
- attribute initval of LUT4_36 : label is "0x6996";
- attribute initval of LUT4_35 : label is "0x6996";
- attribute initval of LUT4_34 : label is "0x6996";
- attribute initval of LUT4_33 : label is "0x6996";
- attribute initval of LUT4_32 : label is "0x6996";
- attribute initval of LUT4_31 : label is "0x6996";
- attribute initval of LUT4_30 : label is "0x6996";
- attribute initval of LUT4_29 : label is "0x6996";
- attribute initval of LUT4_28 : label is "0x6996";
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL";
- attribute GSR of pdp_ram_0_0_31 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is "";
- attribute CSDECODE_B of pdp_ram_0_1_30 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_1_30 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_1_30 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_1_30 : label is "NORMAL";
- attribute GSR of pdp_ram_0_1_30 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_1_30 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_1_30 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_1_30 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_1_30 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_1_30 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is "";
- attribute CSDECODE_B of pdp_ram_0_2_29 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_2_29 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_2_29 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_2_29 : label is "NORMAL";
- attribute GSR of pdp_ram_0_2_29 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_2_29 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_2_29 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_2_29 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_2_29 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_2_29 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is "";
- attribute CSDECODE_B of pdp_ram_0_3_28 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_3_28 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_3_28 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_3_28 : label is "NORMAL";
- attribute GSR of pdp_ram_0_3_28 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_3_28 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_3_28 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_3_28 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_3_28 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_3_28 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is "";
- attribute CSDECODE_B of pdp_ram_0_4_27 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_4_27 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_4_27 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_4_27 : label is "NORMAL";
- attribute GSR of pdp_ram_0_4_27 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_4_27 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_4_27 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_4_27 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_4_27 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_4_27 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is "";
- attribute CSDECODE_B of pdp_ram_0_5_26 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_5_26 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_5_26 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_5_26 : label is "NORMAL";
- attribute GSR of pdp_ram_0_5_26 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_5_26 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_5_26 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_5_26 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_5_26 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_5_26 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is "";
- attribute CSDECODE_B of pdp_ram_0_6_25 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_6_25 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_6_25 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_6_25 : label is "NORMAL";
- attribute GSR of pdp_ram_0_6_25 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_6_25 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_6_25 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_6_25 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_6_25 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_6_25 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is "";
- attribute CSDECODE_B of pdp_ram_0_7_24 : label is "0b000";
- attribute CSDECODE_A of pdp_ram_0_7_24 : label is "0b000";
- attribute WRITEMODE_B of pdp_ram_0_7_24 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_7_24 : label is "NORMAL";
- attribute GSR of pdp_ram_0_7_24 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_7_24 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_7_24 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_7_24 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_7_24 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_0_7_24 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is "";
- attribute CSDECODE_B of pdp_ram_1_0_23 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_0_23 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_0_23 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_0_23 : label is "NORMAL";
- attribute GSR of pdp_ram_1_0_23 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_0_23 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_0_23 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_0_23 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_0_23 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_1_0_23 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is "";
- attribute CSDECODE_B of pdp_ram_1_1_22 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_1_22 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_1_22 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_1_22 : label is "NORMAL";
- attribute GSR of pdp_ram_1_1_22 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_1_22 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_1_22 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_1_22 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_1_22 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_1_1_22 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is "";
- attribute CSDECODE_B of pdp_ram_1_2_21 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_2_21 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_2_21 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_2_21 : label is "NORMAL";
- attribute GSR of pdp_ram_1_2_21 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_2_21 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_2_21 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_2_21 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_2_21 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_1_2_21 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is "";
- attribute CSDECODE_B of pdp_ram_1_3_20 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_3_20 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_3_20 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_3_20 : label is "NORMAL";
- attribute GSR of pdp_ram_1_3_20 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_3_20 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_3_20 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_3_20 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_3_20 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_1_3_20 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is "";
- attribute CSDECODE_B of pdp_ram_1_4_19 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_4_19 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_4_19 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_4_19 : label is "NORMAL";
- attribute GSR of pdp_ram_1_4_19 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_4_19 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_4_19 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_4_19 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_4_19 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_1_4_19 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is "";
- attribute CSDECODE_B of pdp_ram_1_5_18 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_5_18 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_5_18 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_5_18 : label is "NORMAL";
- attribute GSR of pdp_ram_1_5_18 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_5_18 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_5_18 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_5_18 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_5_18 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_1_5_18 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is "";
- attribute CSDECODE_B of pdp_ram_1_6_17 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_6_17 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_6_17 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_6_17 : label is "NORMAL";
- attribute GSR of pdp_ram_1_6_17 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_6_17 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_6_17 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_6_17 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_6_17 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_1_6_17 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is "";
- attribute CSDECODE_B of pdp_ram_1_7_16 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_7_16 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_7_16 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_7_16 : label is "NORMAL";
- attribute GSR of pdp_ram_1_7_16 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_7_16 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_7_16 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_7_16 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_7_16 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_1_7_16 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is "";
- attribute CSDECODE_B of pdp_ram_2_0_15 : label is "0b010";
- attribute CSDECODE_A of pdp_ram_2_0_15 : label is "0b010";
- attribute WRITEMODE_B of pdp_ram_2_0_15 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_0_15 : label is "NORMAL";
- attribute GSR of pdp_ram_2_0_15 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_0_15 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_0_15 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_0_15 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_0_15 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_2_0_15 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is "";
- attribute CSDECODE_B of pdp_ram_2_1_14 : label is "0b010";
- attribute CSDECODE_A of pdp_ram_2_1_14 : label is "0b010";
- attribute WRITEMODE_B of pdp_ram_2_1_14 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_1_14 : label is "NORMAL";
- attribute GSR of pdp_ram_2_1_14 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_1_14 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_1_14 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_1_14 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_1_14 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_2_1_14 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is "";
- attribute CSDECODE_B of pdp_ram_2_2_13 : label is "0b010";
- attribute CSDECODE_A of pdp_ram_2_2_13 : label is "0b010";
- attribute WRITEMODE_B of pdp_ram_2_2_13 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_2_13 : label is "NORMAL";
- attribute GSR of pdp_ram_2_2_13 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_2_13 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_2_13 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_2_13 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_2_13 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_2_2_13 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is "";
- attribute CSDECODE_B of pdp_ram_2_3_12 : label is "0b010";
- attribute CSDECODE_A of pdp_ram_2_3_12 : label is "0b010";
- attribute WRITEMODE_B of pdp_ram_2_3_12 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_3_12 : label is "NORMAL";
- attribute GSR of pdp_ram_2_3_12 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_3_12 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_3_12 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_3_12 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_3_12 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_2_3_12 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is "";
- attribute CSDECODE_B of pdp_ram_2_4_11 : label is "0b010";
- attribute CSDECODE_A of pdp_ram_2_4_11 : label is "0b010";
- attribute WRITEMODE_B of pdp_ram_2_4_11 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_4_11 : label is "NORMAL";
- attribute GSR of pdp_ram_2_4_11 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_4_11 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_4_11 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_4_11 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_4_11 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_2_4_11 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is "";
- attribute CSDECODE_B of pdp_ram_2_5_10 : label is "0b010";
- attribute CSDECODE_A of pdp_ram_2_5_10 : label is "0b010";
- attribute WRITEMODE_B of pdp_ram_2_5_10 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_5_10 : label is "NORMAL";
- attribute GSR of pdp_ram_2_5_10 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_5_10 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_5_10 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_5_10 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_5_10 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_2_5_10 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is "";
- attribute CSDECODE_B of pdp_ram_2_6_9 : label is "0b010";
- attribute CSDECODE_A of pdp_ram_2_6_9 : label is "0b010";
- attribute WRITEMODE_B of pdp_ram_2_6_9 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_6_9 : label is "NORMAL";
- attribute GSR of pdp_ram_2_6_9 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_6_9 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_6_9 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_6_9 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_6_9 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_2_6_9 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is "";
- attribute CSDECODE_B of pdp_ram_2_7_8 : label is "0b010";
- attribute CSDECODE_A of pdp_ram_2_7_8 : label is "0b010";
- attribute WRITEMODE_B of pdp_ram_2_7_8 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_7_8 : label is "NORMAL";
- attribute GSR of pdp_ram_2_7_8 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_7_8 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_7_8 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_7_8 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_7_8 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_2_7_8 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is "";
- attribute CSDECODE_B of pdp_ram_3_0_7 : label is "0b011";
- attribute CSDECODE_A of pdp_ram_3_0_7 : label is "0b011";
- attribute WRITEMODE_B of pdp_ram_3_0_7 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_0_7 : label is "NORMAL";
- attribute GSR of pdp_ram_3_0_7 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_0_7 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_0_7 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_0_7 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_0_7 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_3_0_7 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is "";
- attribute CSDECODE_B of pdp_ram_3_1_6 : label is "0b011";
- attribute CSDECODE_A of pdp_ram_3_1_6 : label is "0b011";
- attribute WRITEMODE_B of pdp_ram_3_1_6 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_1_6 : label is "NORMAL";
- attribute GSR of pdp_ram_3_1_6 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_1_6 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_1_6 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_1_6 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_1_6 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_3_1_6 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is "";
- attribute CSDECODE_B of pdp_ram_3_2_5 : label is "0b011";
- attribute CSDECODE_A of pdp_ram_3_2_5 : label is "0b011";
- attribute WRITEMODE_B of pdp_ram_3_2_5 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_2_5 : label is "NORMAL";
- attribute GSR of pdp_ram_3_2_5 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_2_5 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_2_5 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_2_5 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_2_5 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_3_2_5 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is "";
- attribute CSDECODE_B of pdp_ram_3_3_4 : label is "0b011";
- attribute CSDECODE_A of pdp_ram_3_3_4 : label is "0b011";
- attribute WRITEMODE_B of pdp_ram_3_3_4 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_3_4 : label is "NORMAL";
- attribute GSR of pdp_ram_3_3_4 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_3_4 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_3_4 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_3_4 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_3_4 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_3_3_4 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is "";
- attribute CSDECODE_B of pdp_ram_3_4_3 : label is "0b011";
- attribute CSDECODE_A of pdp_ram_3_4_3 : label is "0b011";
- attribute WRITEMODE_B of pdp_ram_3_4_3 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_4_3 : label is "NORMAL";
- attribute GSR of pdp_ram_3_4_3 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_4_3 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_4_3 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_4_3 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_4_3 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_3_4_3 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is "";
- attribute CSDECODE_B of pdp_ram_3_5_2 : label is "0b011";
- attribute CSDECODE_A of pdp_ram_3_5_2 : label is "0b011";
- attribute WRITEMODE_B of pdp_ram_3_5_2 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_5_2 : label is "NORMAL";
- attribute GSR of pdp_ram_3_5_2 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_5_2 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_5_2 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_5_2 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_5_2 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_3_5_2 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is "";
- attribute CSDECODE_B of pdp_ram_3_6_1 : label is "0b011";
- attribute CSDECODE_A of pdp_ram_3_6_1 : label is "0b011";
- attribute WRITEMODE_B of pdp_ram_3_6_1 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_6_1 : label is "NORMAL";
- attribute GSR of pdp_ram_3_6_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_6_1 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_6_1 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_6_1 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_6_1 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_3_6_1 : label is "2";
- attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_32kx16x8_mb.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is "";
- attribute CSDECODE_B of pdp_ram_3_7_0 : label is "0b011";
- attribute CSDECODE_A of pdp_ram_3_7_0 : label is "0b011";
- attribute WRITEMODE_B of pdp_ram_3_7_0 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_7_0 : label is "NORMAL";
- attribute GSR of pdp_ram_3_7_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_7_0 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_7_0 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_7_0 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_7_0 : label is "1";
- attribute DATA_WIDTH_A of pdp_ram_3_7_0 : label is "2";
- attribute GSR of FF_236 : label is "ENABLED";
- attribute GSR of FF_235 : label is "ENABLED";
- attribute GSR of FF_234 : label is "ENABLED";
- attribute GSR of FF_233 : label is "ENABLED";
- attribute GSR of FF_232 : label is "ENABLED";
- attribute GSR of FF_231 : label is "ENABLED";
- attribute GSR of FF_230 : label is "ENABLED";
- attribute GSR of FF_229 : label is "ENABLED";
- attribute GSR of FF_228 : label is "ENABLED";
- attribute GSR of FF_227 : label is "ENABLED";
- attribute GSR of FF_226 : label is "ENABLED";
- attribute GSR of FF_225 : label is "ENABLED";
- attribute GSR of FF_224 : label is "ENABLED";
- attribute GSR of FF_223 : label is "ENABLED";
- attribute GSR of FF_222 : label is "ENABLED";
- attribute GSR of FF_221 : label is "ENABLED";
- attribute GSR of FF_220 : label is "ENABLED";
- attribute GSR of FF_219 : label is "ENABLED";
- attribute GSR of FF_218 : label is "ENABLED";
- attribute GSR of FF_217 : label is "ENABLED";
- attribute GSR of FF_216 : label is "ENABLED";
- attribute GSR of FF_215 : label is "ENABLED";
- attribute GSR of FF_214 : label is "ENABLED";
- attribute GSR of FF_213 : label is "ENABLED";
- attribute GSR of FF_212 : label is "ENABLED";
- attribute GSR of FF_211 : label is "ENABLED";
- attribute GSR of FF_210 : label is "ENABLED";
- attribute GSR of FF_209 : label is "ENABLED";
- attribute GSR of FF_208 : label is "ENABLED";
- attribute GSR of FF_207 : label is "ENABLED";
- attribute GSR of FF_206 : label is "ENABLED";
- attribute GSR of FF_205 : label is "ENABLED";
- attribute GSR of FF_204 : label is "ENABLED";
- attribute GSR of FF_203 : label is "ENABLED";
- attribute GSR of FF_202 : label is "ENABLED";
- attribute GSR of FF_201 : label is "ENABLED";
- attribute GSR of FF_200 : label is "ENABLED";
- attribute GSR of FF_199 : label is "ENABLED";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t39: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_2: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t38: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_1: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t37: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t36: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t35: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t34: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t33: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t32: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t31: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t30: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t29: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t28: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t27: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t26: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t25: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t24: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t23: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t22: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t21: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t9: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t8: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t7: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t6: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- LUT4_52: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_51: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_50: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_49: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_48: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_47: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_46: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_45: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_44: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9);
-
- LUT4_43: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_42: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_41: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6);
-
- LUT4_40: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_39: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_38: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_37: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3);
-
- LUT4_36: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_35: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r2);
-
- LUT4_34: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_33: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r1);
-
- LUT4_32: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r0);
-
- LUT4_31: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- XOR2_t5: XOR2
- port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb);
-
- XOR2_t4: XOR2
- port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb);
-
- XOR2_t3: XOR2
- port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb);
-
- XOR2_t2: XOR2
- port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- INV_0: INV
- port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv);
-
- AND2_t1: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig);
-
- AND2_t0: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig);
-
- pdp_ram_0_0_31: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_0, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_1_30: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_1, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_2_29: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_2, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_3_28: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_3, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_4_27: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_4, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_5_26: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_5, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_6_25: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_6, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_0_7_24: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_7, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_1_0_23: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_0, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_1_1_22: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_1, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_1_2_21: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_2, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_1_3_20: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_3, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_1_4_19: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_4, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_1_5_18: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_5, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_1_6_17: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_6, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_1_7_16: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_7, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_2_0_15: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_0, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_2_1_14: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_1, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_2_2_13: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_2, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_2_3_12: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_3, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_2_4_11: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_4, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_2_5_10: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_5, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_2_6_9: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_6, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_2_7_8: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_7, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_3_0_7: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_0, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_3_1_6: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_1, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_3_2_5: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_2, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_3_3_4: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_3, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_3_4_3: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_4, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_3_5_2: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_5, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_3_6_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_6, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- pdp_ram_3_7_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
- DATA_WIDTH_A=> 2)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
- ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
- ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
- ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
- WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0,
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4,
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8,
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12,
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo,
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_7, DOB1=>open, DOB2=>open, DOB3=>open,
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- FF_236: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_235: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_234: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_233: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_232: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_231: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_230: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_229: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_228: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_227: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_226: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_225: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_224: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_223: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_222: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_221: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_220: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_219: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_218: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_217: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_216: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_215: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_214: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_213: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_212: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_211: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_210: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_209: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_208: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_207: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_206: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_205: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_204: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_203: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_202: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_201: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_200: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_199: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_198: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_197: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_196: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_195: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_194: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_193: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_192: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_191: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_190: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_189: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_188: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_187: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_186: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_185: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_184: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_183: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_182: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_181: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_180: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_179: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_178: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_177: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_176: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_175: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_174: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_173: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_172: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_171: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_170: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_169: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_168: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_167: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_166: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_165: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_164: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_163: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_162: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_161: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_160: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_159: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_158: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_157: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_156: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_155: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_154: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_153: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_152: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_151: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_150: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_149: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_148: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_147: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_146: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_145: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_144: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_143: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_142: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_141: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_140: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_139: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_138: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_137: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_136: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_135: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_134: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_133: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_132: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_131: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_130: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_129: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_128: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_127: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_126: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_125: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_124: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_123: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_122: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_121: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_120: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_119: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_118: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_117: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_116: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_115: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_114: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_113: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_112: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_111: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_110: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_109: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_108: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_107: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_106: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_105: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_104: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_103: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_102: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_101: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_100: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_99: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_98: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_97: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_96: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_95: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_94: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_93: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_92: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_91: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_90: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_89: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_88: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_87: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_86: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_85: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_84: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_83: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_82: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_81: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_80: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_79: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_78: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_77: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_76: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_75: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_74: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_73: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_72: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_71: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_70: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_69: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0);
-
- FF_68: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1);
-
- FF_67: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2);
-
- FF_66: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3);
-
- FF_65: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4);
-
- FF_64: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5);
-
- FF_63: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6);
-
- FF_62: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7);
-
- FF_61: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8);
-
- FF_60: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9);
-
- FF_59: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10);
-
- FF_58: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11);
-
- FF_57: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12);
-
- FF_56: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13);
-
- FF_55: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14);
-
- FF_54: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15);
-
- FF_53: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0);
-
- FF_52: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1);
-
- FF_51: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2);
-
- FF_50: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12));
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13));
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14));
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15));
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10));
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11));
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12));
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13));
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14));
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15));
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16));
-
- FF_3: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>ircount_16, NC1=>open);
-
- mux_7: MUX41
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0));
-
- mux_6: MUX41
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1));
-
- mux_5: MUX41
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2));
-
- mux_4: MUX41
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3));
-
- mux_3: MUX41
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4));
-
- mux_2: MUX41
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5));
-
- mux_1: MUX41
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6));
-
- mux_0: MUX41
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7));
-
- wcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
- S1=>wcnt_sub_0);
-
- wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2,
- B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1,
- S1=>wcnt_sub_2);
-
- wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4,
- B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3,
- S1=>wcnt_sub_4);
-
- wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6,
- B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5,
- S1=>wcnt_sub_6);
-
- wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8,
- B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7,
- S1=>wcnt_sub_8);
-
- wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9,
- S1=>wcnt_sub_10);
-
- wcnt_6: FSUB2B
- port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2,
- S0=>wcnt_sub_11, S1=>wcnt_sub_12);
-
- wcnt_7: FSUB2B
- port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13,
- S1=>wcnt_sub_14);
-
- wcnt_8: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15,
- S1=>open);
-
- rcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open,
- S1=>rcnt_sub_0);
-
- rcnt_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1,
- B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1,
- S1=>rcnt_sub_2);
-
- rcnt_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3,
- B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3,
- S1=>rcnt_sub_4);
-
- rcnt_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5,
- B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5,
- S1=>rcnt_sub_6);
-
- rcnt_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7,
- B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7,
- S1=>rcnt_sub_8);
-
- rcnt_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9,
- B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9,
- S1=>rcnt_sub_10);
-
- rcnt_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11,
- B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11,
- S1=>rcnt_sub_12);
-
- rcnt_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13,
- B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13,
- S1=>rcnt_sub_14);
-
- rcnt_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15,
- B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15,
- S1=>rcnt_sub_16);
-
- rcntd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open);
-
- wfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open,
- S1=>wfill_sub_0);
-
- wfill_1: FSUB2B
- port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3,
- BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2);
-
- wfill_2: FSUB2B
- port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5,
- BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4);
-
- wfill_3: FSUB2B
- port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7,
- BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6);
-
- wfill_4: FSUB2B
- port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9,
- BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8);
-
- wfill_5: FSUB2B
- port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9,
- S1=>wfill_sub_10);
-
- wfill_6: FSUB2B
- port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4,
- S0=>wfill_sub_11, S1=>wfill_sub_12);
-
- wfill_7: FSUB2B
- port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13,
- S1=>wfill_sub_14);
-
- wfill_8: FSUB2B
- port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- rfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
- S1=>rfill_sub_0);
-
- rfill_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2,
- BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2);
-
- rfill_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4,
- BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4);
-
- rfill_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6,
- BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6);
-
- rfill_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8,
- BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8);
-
- rfill_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10,
- BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10);
-
- rfill_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11,
- B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11,
- S1=>rfill_sub_12);
-
- rfill_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13,
- B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13,
- S1=>rfill_sub_14);
-
- rfill_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15,
- B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15,
- S1=>rfill_sub_16);
-
- rfilld: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_6, GE=>co1_6);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_6, GE=>co2_6);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_6, GE=>co3_6);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
- B1=>wcount_r8, CI=>co3_6, GE=>co4_6);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co4_6, GE=>co5_6);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11,
- B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13,
- B1=>wcount_r14, CI=>co6_6, GE=>co7_6);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_7, GE=>co1_7);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_7, GE=>co2_7);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>rcount_w8, CI=>co2_7, GE=>co3_7);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
- B1=>rcount_w10, CI=>co3_7, GE=>co4_7);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11,
- B1=>rcount_w12, CI=>co4_7, GE=>co5_7);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w14, CI=>co5_7, GE=>co6_7);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15,
- B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- ae_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- ae_cmp_0: AGEB2
- port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
- B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8);
-
- ae_cmp_1: AGEB2
- port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
- B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8);
-
- ae_cmp_2: AGEB2
- port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
- B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8);
-
- ae_cmp_3: AGEB2
- port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
- B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8);
-
- ae_cmp_4: AGEB2
- port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9),
- B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8);
-
- ae_cmp_5: AGEB2
- port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11),
- B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8);
-
- ae_cmp_6: AGEB2
- port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13),
- B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8);
-
- ae_cmp_7: AGEB2
- port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15),
- B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7);
-
- ae_cmp_8: AGEB2
- port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig,
- B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
-
- af_d_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
-
- af_d_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
- B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9);
-
- af_d_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
- B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9);
-
- af_d_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
- B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9);
-
- af_d_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
- B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9);
-
- af_d_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
- B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9);
-
- af_d_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
- B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9);
-
- af_d_cmp_6: AGEB2
- port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
- B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9);
-
- af_d_cmp_7: AGEB2
- port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14),
- B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of fifo_32kx16x8_mb is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:MUX41 use entity ecp2m.MUX41(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_32kx16x8_mb2" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 01 18 18:38:14.597" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="fifo_32kx16x8_mb2.lpc" type="lpc" modified="2018 01 18 18:38:11.000"/>
- <File name="fifo_32kx16x8_mb2.vhd" type="top_level_vhdl" modified="2018 01 18 18:38:11.000"/>
- <File name="fifo_32kx16x8_mb2_tmpl.vhd" type="template_vhdl" modified="2018 01 18 18:38:11.000"/>
- <File name="tb_fifo_32kx16x8_mb2_tmpl.vhd" type="testbench_vhdl" modified="2018 01 18 18:38:11.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp2m
-PartType=LFE2M100E
-PartName=LFE2M100E-5F1152C
-SpeedGrade=5
-Package=FPBGA1152
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.8
-ModuleName=fifo_32kx16x8_mb2
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=01/18/2018
-Time=18:38:11
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=32768
-Width=18
-RDepth=65536
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=1
-PeMode=Dynamic - Single Threshold
-PeAssert=16
-PeDeassert=12
-FullFlg=1
-PfMode=Dynamic - Single Threshold
-PfAssert=32752
-PfDeassert=506
-RDataCount=1
-WDataCount=1
-EnECC=0
-
-[Command]
-cmd_line= -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill
+++ /dev/null
-SCUBA, Version Diamond (64-bit) 3.9.1.119
-Thu Jan 18 18:38:11 2018
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill
- Circuit name : fifo_32kx16x8_mb2
- Module type : ebfifo
- Module Version : 5.8
- Ports :
- Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]
- Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull
- I/O buffer : not inserted
- EDIF output : fifo_32kx16x8_mb2.edn
- VHDL output : fifo_32kx16x8_mb2.vhd
- VHDL template : fifo_32kx16x8_mb2_tmpl.vhd
- VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_32kx16x8_mb2.srp
- Element Usage :
- AGEB2 : 34
- AND2 : 4
- CU2 : 17
- FADD2B : 16
- FSUB2B : 36
- FD1P3BX : 2
- FD1P3DX : 102
- FD1S3BX : 2
- FD1S3DX : 134
- INV : 13
- MUX321 : 9
- OR2 : 1
- ROM16X1 : 181
- XOR2 : 35
- DP16KB : 32
- Estimated Resource Usage:
- LUT : 499
- EBR : 32
- Reg : 240
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119
--- Module Version: 5.8
---/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill
-
--- Thu Jan 18 18:38:11 2018
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity fifo_32kx16x8_mb2 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(8 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end fifo_32kx16x8_mb2;
-
-architecture Structure of fifo_32kx16x8_mb2 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal func_and_inet: std_logic;
- signal func_and_inet_1: std_logic;
- signal func_and_inet_2: std_logic;
- signal func_and_inet_3: std_logic;
- signal func_and_inet_4: std_logic;
- signal func_and_inet_5: std_logic;
- signal func_and_inet_6: std_logic;
- signal func_and_inet_7: std_logic;
- signal func_and_inet_8: std_logic;
- signal func_and_inet_9: std_logic;
- signal func_and_inet_10: std_logic;
- signal func_and_inet_11: std_logic;
- signal func_and_inet_12: std_logic;
- signal func_and_inet_13: std_logic;
- signal func_and_inet_14: std_logic;
- signal func_and_inet_15: std_logic;
- signal func_and_inet_16: std_logic;
- signal func_and_inet_17: std_logic;
- signal func_and_inet_18: std_logic;
- signal func_and_inet_19: std_logic;
- signal func_and_inet_20: std_logic;
- signal func_and_inet_21: std_logic;
- signal func_and_inet_22: std_logic;
- signal func_and_inet_23: std_logic;
- signal func_and_inet_24: std_logic;
- signal func_and_inet_25: std_logic;
- signal func_and_inet_26: std_logic;
- signal func_and_inet_27: std_logic;
- signal func_and_inet_28: std_logic;
- signal func_and_inet_29: std_logic;
- signal wptr_14_inv: std_logic;
- signal func_and_inet_30: std_logic;
- signal rptr_15_inv: std_logic;
- signal func_and_inet_31: std_logic;
- signal func_and_inet_32: std_logic;
- signal func_and_inet_33: std_logic;
- signal func_and_inet_34: std_logic;
- signal func_and_inet_35: std_logic;
- signal func_and_inet_36: std_logic;
- signal func_and_inet_37: std_logic;
- signal func_and_inet_38: std_logic;
- signal func_and_inet_39: std_logic;
- signal func_and_inet_40: std_logic;
- signal func_and_inet_41: std_logic;
- signal func_and_inet_42: std_logic;
- signal func_and_inet_43: std_logic;
- signal func_and_inet_44: std_logic;
- signal func_and_inet_45: std_logic;
- signal wptr_13_inv: std_logic;
- signal func_and_inet_46: std_logic;
- signal rptr_14_inv: std_logic;
- signal func_and_inet_47: std_logic;
- signal func_and_inet_48: std_logic;
- signal func_and_inet_49: std_logic;
- signal func_and_inet_50: std_logic;
- signal func_and_inet_51: std_logic;
- signal func_and_inet_52: std_logic;
- signal func_and_inet_53: std_logic;
- signal wptr_12_inv: std_logic;
- signal func_and_inet_54: std_logic;
- signal rptr_13_inv: std_logic;
- signal func_and_inet_55: std_logic;
- signal func_and_inet_56: std_logic;
- signal func_and_inet_57: std_logic;
- signal wptr_11_inv: std_logic;
- signal func_and_inet_58: std_logic;
- signal rptr_12_inv: std_logic;
- signal func_and_inet_59: std_logic;
- signal wptr_10_inv: std_logic;
- signal func_and_inet_60: std_logic;
- signal rptr_11_inv: std_logic;
- signal func_and_inet_61: std_logic;
- signal func_and_inet_62: std_logic;
- signal func_and_inet_63: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal rcount_w0: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal rcnt_reg_15_inv: std_logic;
- signal dec1_r10: std_logic;
- signal dec0_p00: std_logic;
- signal dec3_r11: std_logic;
- signal dec2_p01: std_logic;
- signal dec5_r12: std_logic;
- signal dec4_p02: std_logic;
- signal dec7_r13: std_logic;
- signal dec6_p03: std_logic;
- signal dec9_r14: std_logic;
- signal dec8_p04: std_logic;
- signal dec11_r15: std_logic;
- signal dec10_p05: std_logic;
- signal dec13_r16: std_logic;
- signal dec12_p06: std_logic;
- signal dec15_r17: std_logic;
- signal dec14_p07: std_logic;
- signal dec17_r18: std_logic;
- signal dec16_p08: std_logic;
- signal dec19_r19: std_logic;
- signal dec18_p09: std_logic;
- signal dec21_r110: std_logic;
- signal dec20_p010: std_logic;
- signal dec23_r111: std_logic;
- signal dec22_p011: std_logic;
- signal dec25_r112: std_logic;
- signal dec24_p012: std_logic;
- signal dec27_r113: std_logic;
- signal dec26_p013: std_logic;
- signal dec29_r114: std_logic;
- signal dec28_p014: std_logic;
- signal dec31_r115: std_logic;
- signal dec30_p015: std_logic;
- signal dec33_r116: std_logic;
- signal dec32_p016: std_logic;
- signal dec35_r117: std_logic;
- signal dec34_p017: std_logic;
- signal dec37_r118: std_logic;
- signal dec36_p018: std_logic;
- signal dec39_r119: std_logic;
- signal dec38_p019: std_logic;
- signal dec41_r120: std_logic;
- signal dec40_p020: std_logic;
- signal dec43_r121: std_logic;
- signal dec42_p021: std_logic;
- signal dec45_r122: std_logic;
- signal dec44_p022: std_logic;
- signal dec47_r123: std_logic;
- signal dec46_p023: std_logic;
- signal dec49_r124: std_logic;
- signal dec48_p024: std_logic;
- signal dec51_r125: std_logic;
- signal dec50_p025: std_logic;
- signal dec53_r126: std_logic;
- signal dec52_p026: std_logic;
- signal dec55_r127: std_logic;
- signal dec54_p027: std_logic;
- signal dec57_r128: std_logic;
- signal dec56_p028: std_logic;
- signal dec59_r129: std_logic;
- signal dec58_p029: std_logic;
- signal dec61_r130: std_logic;
- signal dec60_p030: std_logic;
- signal dec63_r131: std_logic;
- signal dec62_p031: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal wptr_15: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_16: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal rcnt_reg_16: std_logic;
- signal empty_i: std_logic;
- signal full_i: std_logic;
- signal rRst: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co7: std_logic;
- signal co6: std_logic;
- signal wcount_15: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8: std_logic;
- signal co7_1: std_logic;
- signal rcount_16: std_logic;
- signal mdout1_31_0: std_logic;
- signal mdout1_30_0: std_logic;
- signal mdout1_29_0: std_logic;
- signal mdout1_28_0: std_logic;
- signal mdout1_27_0: std_logic;
- signal mdout1_26_0: std_logic;
- signal mdout1_25_0: std_logic;
- signal mdout1_24_0: std_logic;
- signal mdout1_23_0: std_logic;
- signal mdout1_22_0: std_logic;
- signal mdout1_21_0: std_logic;
- signal mdout1_20_0: std_logic;
- signal mdout1_19_0: std_logic;
- signal mdout1_18_0: std_logic;
- signal mdout1_17_0: std_logic;
- signal mdout1_16_0: std_logic;
- signal mdout1_15_0: std_logic;
- signal mdout1_14_0: std_logic;
- signal mdout1_13_0: std_logic;
- signal mdout1_12_0: std_logic;
- signal mdout1_11_0: std_logic;
- signal mdout1_10_0: std_logic;
- signal mdout1_9_0: std_logic;
- signal mdout1_8_0: std_logic;
- signal mdout1_7_0: std_logic;
- signal mdout1_6_0: std_logic;
- signal mdout1_5_0: std_logic;
- signal mdout1_4_0: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_31_1: std_logic;
- signal mdout1_30_1: std_logic;
- signal mdout1_29_1: std_logic;
- signal mdout1_28_1: std_logic;
- signal mdout1_27_1: std_logic;
- signal mdout1_26_1: std_logic;
- signal mdout1_25_1: std_logic;
- signal mdout1_24_1: std_logic;
- signal mdout1_23_1: std_logic;
- signal mdout1_22_1: std_logic;
- signal mdout1_21_1: std_logic;
- signal mdout1_20_1: std_logic;
- signal mdout1_19_1: std_logic;
- signal mdout1_18_1: std_logic;
- signal mdout1_17_1: std_logic;
- signal mdout1_16_1: std_logic;
- signal mdout1_15_1: std_logic;
- signal mdout1_14_1: std_logic;
- signal mdout1_13_1: std_logic;
- signal mdout1_12_1: std_logic;
- signal mdout1_11_1: std_logic;
- signal mdout1_10_1: std_logic;
- signal mdout1_9_1: std_logic;
- signal mdout1_8_1: std_logic;
- signal mdout1_7_1: std_logic;
- signal mdout1_6_1: std_logic;
- signal mdout1_5_1: std_logic;
- signal mdout1_4_1: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_31_2: std_logic;
- signal mdout1_30_2: std_logic;
- signal mdout1_29_2: std_logic;
- signal mdout1_28_2: std_logic;
- signal mdout1_27_2: std_logic;
- signal mdout1_26_2: std_logic;
- signal mdout1_25_2: std_logic;
- signal mdout1_24_2: std_logic;
- signal mdout1_23_2: std_logic;
- signal mdout1_22_2: std_logic;
- signal mdout1_21_2: std_logic;
- signal mdout1_20_2: std_logic;
- signal mdout1_19_2: std_logic;
- signal mdout1_18_2: std_logic;
- signal mdout1_17_2: std_logic;
- signal mdout1_16_2: std_logic;
- signal mdout1_15_2: std_logic;
- signal mdout1_14_2: std_logic;
- signal mdout1_13_2: std_logic;
- signal mdout1_12_2: std_logic;
- signal mdout1_11_2: std_logic;
- signal mdout1_10_2: std_logic;
- signal mdout1_9_2: std_logic;
- signal mdout1_8_2: std_logic;
- signal mdout1_7_2: std_logic;
- signal mdout1_6_2: std_logic;
- signal mdout1_5_2: std_logic;
- signal mdout1_4_2: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_31_3: std_logic;
- signal mdout1_30_3: std_logic;
- signal mdout1_29_3: std_logic;
- signal mdout1_28_3: std_logic;
- signal mdout1_27_3: std_logic;
- signal mdout1_26_3: std_logic;
- signal mdout1_25_3: std_logic;
- signal mdout1_24_3: std_logic;
- signal mdout1_23_3: std_logic;
- signal mdout1_22_3: std_logic;
- signal mdout1_21_3: std_logic;
- signal mdout1_20_3: std_logic;
- signal mdout1_19_3: std_logic;
- signal mdout1_18_3: std_logic;
- signal mdout1_17_3: std_logic;
- signal mdout1_16_3: std_logic;
- signal mdout1_15_3: std_logic;
- signal mdout1_14_3: std_logic;
- signal mdout1_13_3: std_logic;
- signal mdout1_12_3: std_logic;
- signal mdout1_11_3: std_logic;
- signal mdout1_10_3: std_logic;
- signal mdout1_9_3: std_logic;
- signal mdout1_8_3: std_logic;
- signal mdout1_7_3: std_logic;
- signal mdout1_6_3: std_logic;
- signal mdout1_5_3: std_logic;
- signal mdout1_4_3: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_31_4: std_logic;
- signal mdout1_30_4: std_logic;
- signal mdout1_29_4: std_logic;
- signal mdout1_28_4: std_logic;
- signal mdout1_27_4: std_logic;
- signal mdout1_26_4: std_logic;
- signal mdout1_25_4: std_logic;
- signal mdout1_24_4: std_logic;
- signal mdout1_23_4: std_logic;
- signal mdout1_22_4: std_logic;
- signal mdout1_21_4: std_logic;
- signal mdout1_20_4: std_logic;
- signal mdout1_19_4: std_logic;
- signal mdout1_18_4: std_logic;
- signal mdout1_17_4: std_logic;
- signal mdout1_16_4: std_logic;
- signal mdout1_15_4: std_logic;
- signal mdout1_14_4: std_logic;
- signal mdout1_13_4: std_logic;
- signal mdout1_12_4: std_logic;
- signal mdout1_11_4: std_logic;
- signal mdout1_10_4: std_logic;
- signal mdout1_9_4: std_logic;
- signal mdout1_8_4: std_logic;
- signal mdout1_7_4: std_logic;
- signal mdout1_6_4: std_logic;
- signal mdout1_5_4: std_logic;
- signal mdout1_4_4: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_31_5: std_logic;
- signal mdout1_30_5: std_logic;
- signal mdout1_29_5: std_logic;
- signal mdout1_28_5: std_logic;
- signal mdout1_27_5: std_logic;
- signal mdout1_26_5: std_logic;
- signal mdout1_25_5: std_logic;
- signal mdout1_24_5: std_logic;
- signal mdout1_23_5: std_logic;
- signal mdout1_22_5: std_logic;
- signal mdout1_21_5: std_logic;
- signal mdout1_20_5: std_logic;
- signal mdout1_19_5: std_logic;
- signal mdout1_18_5: std_logic;
- signal mdout1_17_5: std_logic;
- signal mdout1_16_5: std_logic;
- signal mdout1_15_5: std_logic;
- signal mdout1_14_5: std_logic;
- signal mdout1_13_5: std_logic;
- signal mdout1_12_5: std_logic;
- signal mdout1_11_5: std_logic;
- signal mdout1_10_5: std_logic;
- signal mdout1_9_5: std_logic;
- signal mdout1_8_5: std_logic;
- signal mdout1_7_5: std_logic;
- signal mdout1_6_5: std_logic;
- signal mdout1_5_5: std_logic;
- signal mdout1_4_5: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_31_6: std_logic;
- signal mdout1_30_6: std_logic;
- signal mdout1_29_6: std_logic;
- signal mdout1_28_6: std_logic;
- signal mdout1_27_6: std_logic;
- signal mdout1_26_6: std_logic;
- signal mdout1_25_6: std_logic;
- signal mdout1_24_6: std_logic;
- signal mdout1_23_6: std_logic;
- signal mdout1_22_6: std_logic;
- signal mdout1_21_6: std_logic;
- signal mdout1_20_6: std_logic;
- signal mdout1_19_6: std_logic;
- signal mdout1_18_6: std_logic;
- signal mdout1_17_6: std_logic;
- signal mdout1_16_6: std_logic;
- signal mdout1_15_6: std_logic;
- signal mdout1_14_6: std_logic;
- signal mdout1_13_6: std_logic;
- signal mdout1_12_6: std_logic;
- signal mdout1_11_6: std_logic;
- signal mdout1_10_6: std_logic;
- signal mdout1_9_6: std_logic;
- signal mdout1_8_6: std_logic;
- signal mdout1_7_6: std_logic;
- signal mdout1_6_6: std_logic;
- signal mdout1_5_6: std_logic;
- signal mdout1_4_6: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_31_7: std_logic;
- signal mdout1_30_7: std_logic;
- signal mdout1_29_7: std_logic;
- signal mdout1_28_7: std_logic;
- signal mdout1_27_7: std_logic;
- signal mdout1_26_7: std_logic;
- signal mdout1_25_7: std_logic;
- signal mdout1_24_7: std_logic;
- signal mdout1_23_7: std_logic;
- signal mdout1_22_7: std_logic;
- signal mdout1_21_7: std_logic;
- signal mdout1_20_7: std_logic;
- signal mdout1_19_7: std_logic;
- signal mdout1_18_7: std_logic;
- signal mdout1_17_7: std_logic;
- signal mdout1_16_7: std_logic;
- signal mdout1_15_7: std_logic;
- signal mdout1_14_7: std_logic;
- signal mdout1_13_7: std_logic;
- signal mdout1_12_7: std_logic;
- signal mdout1_11_7: std_logic;
- signal mdout1_10_7: std_logic;
- signal mdout1_9_7: std_logic;
- signal mdout1_8_7: std_logic;
- signal mdout1_7_7: std_logic;
- signal mdout1_6_7: std_logic;
- signal mdout1_5_7: std_logic;
- signal mdout1_4_7: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal rptr_13_ff: std_logic;
- signal rptr_12_ff: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_31_8: std_logic;
- signal mdout1_30_8: std_logic;
- signal mdout1_29_8: std_logic;
- signal mdout1_28_8: std_logic;
- signal mdout1_27_8: std_logic;
- signal mdout1_26_8: std_logic;
- signal mdout1_25_8: std_logic;
- signal mdout1_24_8: std_logic;
- signal mdout1_23_8: std_logic;
- signal mdout1_22_8: std_logic;
- signal mdout1_21_8: std_logic;
- signal mdout1_20_8: std_logic;
- signal mdout1_19_8: std_logic;
- signal mdout1_18_8: std_logic;
- signal mdout1_17_8: std_logic;
- signal mdout1_16_8: std_logic;
- signal mdout1_15_8: std_logic;
- signal mdout1_14_8: std_logic;
- signal mdout1_13_8: std_logic;
- signal mdout1_12_8: std_logic;
- signal mdout1_11_8: std_logic;
- signal mdout1_10_8: std_logic;
- signal mdout1_9_8: std_logic;
- signal mdout1_8_8: std_logic;
- signal mdout1_7_8: std_logic;
- signal mdout1_6_8: std_logic;
- signal mdout1_5_8: std_logic;
- signal mdout1_4_8: std_logic;
- signal mdout1_3_8: std_logic;
- signal mdout1_2_8: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal wcnt_sub_0: std_logic;
- signal precin: std_logic;
- signal wcnt_sub_1: std_logic;
- signal wcnt_sub_2: std_logic;
- signal co0_2: std_logic;
- signal wcnt_sub_3: std_logic;
- signal wcnt_sub_4: std_logic;
- signal co1_2: std_logic;
- signal wcnt_sub_5: std_logic;
- signal wcnt_sub_6: std_logic;
- signal co2_2: std_logic;
- signal wcnt_sub_7: std_logic;
- signal wcnt_sub_8: std_logic;
- signal co3_2: std_logic;
- signal wcnt_sub_9: std_logic;
- signal wcnt_sub_10: std_logic;
- signal co4_2: std_logic;
- signal wcnt_sub_11: std_logic;
- signal wcnt_sub_12: std_logic;
- signal co5_2: std_logic;
- signal wcnt_sub_13: std_logic;
- signal wcnt_sub_14: std_logic;
- signal co6_2: std_logic;
- signal wcnt_sub_15: std_logic;
- signal co7_2: std_logic;
- signal wcnt_sub_msb: std_logic;
- signal rcnt_sub_0: std_logic;
- signal precin_1: std_logic;
- signal rcnt_sub_1: std_logic;
- signal rcnt_sub_2: std_logic;
- signal co0_3: std_logic;
- signal rcnt_sub_3: std_logic;
- signal rcnt_sub_4: std_logic;
- signal co1_3: std_logic;
- signal rcnt_sub_5: std_logic;
- signal rcnt_sub_6: std_logic;
- signal co2_3: std_logic;
- signal rcnt_sub_7: std_logic;
- signal rcnt_sub_8: std_logic;
- signal co3_3: std_logic;
- signal rcnt_sub_9: std_logic;
- signal rcnt_sub_10: std_logic;
- signal co4_3: std_logic;
- signal rcnt_sub_11: std_logic;
- signal rcnt_sub_12: std_logic;
- signal co5_3: std_logic;
- signal rcnt_sub_13: std_logic;
- signal rcnt_sub_14: std_logic;
- signal co6_3: std_logic;
- signal rcnt_sub_15: std_logic;
- signal rcnt_sub_16: std_logic;
- signal co7_3: std_logic;
- signal rcnt_sub_msb: std_logic;
- signal co8_1d: std_logic;
- signal co8_1: std_logic;
- signal wfill_sub_0: std_logic;
- signal precin_2: std_logic;
- signal wptr_0: std_logic;
- signal wfill_sub_1: std_logic;
- signal wfill_sub_2: std_logic;
- signal co0_4: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wfill_sub_3: std_logic;
- signal wfill_sub_4: std_logic;
- signal co1_4: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wfill_sub_5: std_logic;
- signal wfill_sub_6: std_logic;
- signal co2_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wfill_sub_7: std_logic;
- signal wfill_sub_8: std_logic;
- signal co3_4: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wfill_sub_9: std_logic;
- signal wfill_sub_10: std_logic;
- signal co4_4: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wfill_sub_11: std_logic;
- signal wfill_sub_12: std_logic;
- signal co5_4: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wfill_sub_13: std_logic;
- signal wfill_sub_14: std_logic;
- signal co6_4: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wfill_sub_15: std_logic;
- signal co7_4: std_logic;
- signal wfill_sub_msb: std_logic;
- signal rfill_sub_0: std_logic;
- signal precin_3: std_logic;
- signal rptr_0: std_logic;
- signal scuba_vhi: std_logic;
- signal rfill_sub_1: std_logic;
- signal rfill_sub_2: std_logic;
- signal co0_5: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rfill_sub_3: std_logic;
- signal rfill_sub_4: std_logic;
- signal co1_5: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rfill_sub_5: std_logic;
- signal rfill_sub_6: std_logic;
- signal co2_5: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rfill_sub_7: std_logic;
- signal rfill_sub_8: std_logic;
- signal co3_5: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rfill_sub_9: std_logic;
- signal rfill_sub_10: std_logic;
- signal co4_5: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rfill_sub_11: std_logic;
- signal rfill_sub_12: std_logic;
- signal co5_5: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rfill_sub_13: std_logic;
- signal rfill_sub_14: std_logic;
- signal co6_5: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rfill_sub_15: std_logic;
- signal rfill_sub_16: std_logic;
- signal co7_5: std_logic;
- signal rptr_15: std_logic;
- signal rfill_sub_msb: std_logic;
- signal co8_2d: std_logic;
- signal co8_2: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_6: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_6: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_6: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_6: std_logic;
- signal wcount_r7: std_logic;
- signal wcount_r8: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_6: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_6: std_logic;
- signal wcount_r11: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_6: std_logic;
- signal wcount_r13: std_logic;
- signal wcount_r14: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_6: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_7: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_7: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_7: std_logic;
- signal rcount_w7: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_7: std_logic;
- signal rcount_w9: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_7: std_logic;
- signal rcount_w11: std_logic;
- signal rcount_w12: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w14: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_7: std_logic;
- signal rcount_w15: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_14: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal rcnt_reg_0: std_logic;
- signal rcnt_reg_1: std_logic;
- signal co0_8: std_logic;
- signal rcnt_reg_2: std_logic;
- signal rcnt_reg_3: std_logic;
- signal co1_8: std_logic;
- signal rcnt_reg_4: std_logic;
- signal rcnt_reg_5: std_logic;
- signal co2_8: std_logic;
- signal rcnt_reg_6: std_logic;
- signal rcnt_reg_7: std_logic;
- signal co3_8: std_logic;
- signal rcnt_reg_8: std_logic;
- signal rcnt_reg_9: std_logic;
- signal co4_8: std_logic;
- signal rcnt_reg_10: std_logic;
- signal rcnt_reg_11: std_logic;
- signal co5_8: std_logic;
- signal rcnt_reg_12: std_logic;
- signal rcnt_reg_13: std_logic;
- signal co6_8: std_logic;
- signal rcnt_reg_14: std_logic;
- signal rcnt_reg_15: std_logic;
- signal co7_7: std_logic;
- signal ae_clrsig: std_logic;
- signal ae_setsig: std_logic;
- signal ae_d: std_logic;
- signal ae_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_3: std_logic;
- signal wcnt_reg_0: std_logic;
- signal wcnt_reg_1: std_logic;
- signal co0_9: std_logic;
- signal wcnt_reg_2: std_logic;
- signal wcnt_reg_3: std_logic;
- signal co1_9: std_logic;
- signal wcnt_reg_4: std_logic;
- signal wcnt_reg_5: std_logic;
- signal co2_9: std_logic;
- signal wcnt_reg_6: std_logic;
- signal wcnt_reg_7: std_logic;
- signal co3_9: std_logic;
- signal wcnt_reg_8: std_logic;
- signal wcnt_reg_9: std_logic;
- signal co4_9: std_logic;
- signal wcnt_reg_10: std_logic;
- signal wcnt_reg_11: std_logic;
- signal co5_9: std_logic;
- signal wcnt_reg_12: std_logic;
- signal wcnt_reg_13: std_logic;
- signal co6_9: std_logic;
- signal wcnt_reg_14: std_logic;
- signal wcnt_reg_15: std_logic;
- signal af_d: std_logic;
- signal af_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX321
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; D8: in std_logic;
- D9: in std_logic; D10: in std_logic; D11: in std_logic;
- D12: in std_logic; D13: in std_logic; D14: in std_logic;
- D15: in std_logic; D16: in std_logic; D17: in std_logic;
- D18: in std_logic; D19: in std_logic; D20: in std_logic;
- D21: in std_logic; D22: in std_logic; D23: in std_logic;
- D24: in std_logic; D25: in std_logic; D26: in std_logic;
- D27: in std_logic; D28: in std_logic; D29: in std_logic;
- D30: in std_logic; D31: in std_logic; SD1: in std_logic;
- SD2: in std_logic; SD3: in std_logic; SD4: in std_logic;
- SD5: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
- attribute initval of LUT4_180 : label is "0x8000";
- attribute initval of LUT4_179 : label is "0x8000";
- attribute initval of LUT4_178 : label is "0x8000";
- attribute initval of LUT4_177 : label is "0x8000";
- attribute initval of LUT4_176 : label is "0x8000";
- attribute initval of LUT4_175 : label is "0x8000";
- attribute initval of LUT4_174 : label is "0x8000";
- attribute initval of LUT4_173 : label is "0x8000";
- attribute initval of LUT4_172 : label is "0x8000";
- attribute initval of LUT4_171 : label is "0x8000";
- attribute initval of LUT4_170 : label is "0x8000";
- attribute initval of LUT4_169 : label is "0x8000";
- attribute initval of LUT4_168 : label is "0x8000";
- attribute initval of LUT4_167 : label is "0x8000";
- attribute initval of LUT4_166 : label is "0x8000";
- attribute initval of LUT4_165 : label is "0x8000";
- attribute initval of LUT4_164 : label is "0x8000";
- attribute initval of LUT4_163 : label is "0x8000";
- attribute initval of LUT4_162 : label is "0x8000";
- attribute initval of LUT4_161 : label is "0x8000";
- attribute initval of LUT4_160 : label is "0x8000";
- attribute initval of LUT4_159 : label is "0x8000";
- attribute initval of LUT4_158 : label is "0x8000";
- attribute initval of LUT4_157 : label is "0x8000";
- attribute initval of LUT4_156 : label is "0x8000";
- attribute initval of LUT4_155 : label is "0x8000";
- attribute initval of LUT4_154 : label is "0x8000";
- attribute initval of LUT4_153 : label is "0x8000";
- attribute initval of LUT4_152 : label is "0x8000";
- attribute initval of LUT4_151 : label is "0x8000";
- attribute initval of LUT4_150 : label is "0x8000";
- attribute initval of LUT4_149 : label is "0x8000";
- attribute initval of LUT4_148 : label is "0x8000";
- attribute initval of LUT4_147 : label is "0x8000";
- attribute initval of LUT4_146 : label is "0x8000";
- attribute initval of LUT4_145 : label is "0x8000";
- attribute initval of LUT4_144 : label is "0x8000";
- attribute initval of LUT4_143 : label is "0x8000";
- attribute initval of LUT4_142 : label is "0x8000";
- attribute initval of LUT4_141 : label is "0x8000";
- attribute initval of LUT4_140 : label is "0x8000";
- attribute initval of LUT4_139 : label is "0x8000";
- attribute initval of LUT4_138 : label is "0x8000";
- attribute initval of LUT4_137 : label is "0x8000";
- attribute initval of LUT4_136 : label is "0x8000";
- attribute initval of LUT4_135 : label is "0x8000";
- attribute initval of LUT4_134 : label is "0x8000";
- attribute initval of LUT4_133 : label is "0x8000";
- attribute initval of LUT4_132 : label is "0x8000";
- attribute initval of LUT4_131 : label is "0x8000";
- attribute initval of LUT4_130 : label is "0x8000";
- attribute initval of LUT4_129 : label is "0x8000";
- attribute initval of LUT4_128 : label is "0x8000";
- attribute initval of LUT4_127 : label is "0x8000";
- attribute initval of LUT4_126 : label is "0x8000";
- attribute initval of LUT4_125 : label is "0x8000";
- attribute initval of LUT4_124 : label is "0x8000";
- attribute initval of LUT4_123 : label is "0x8000";
- attribute initval of LUT4_122 : label is "0x8000";
- attribute initval of LUT4_121 : label is "0x8000";
- attribute initval of LUT4_120 : label is "0x8000";
- attribute initval of LUT4_119 : label is "0x8000";
- attribute initval of LUT4_118 : label is "0x8000";
- attribute initval of LUT4_117 : label is "0x8000";
- attribute initval of LUT4_116 : label is "0x8000";
- attribute initval of LUT4_115 : label is "0x8000";
- attribute initval of LUT4_114 : label is "0x8000";
- attribute initval of LUT4_113 : label is "0x8000";
- attribute initval of LUT4_112 : label is "0x8000";
- attribute initval of LUT4_111 : label is "0x8000";
- attribute initval of LUT4_110 : label is "0x8000";
- attribute initval of LUT4_109 : label is "0x8000";
- attribute initval of LUT4_108 : label is "0x8000";
- attribute initval of LUT4_107 : label is "0x8000";
- attribute initval of LUT4_106 : label is "0x8000";
- attribute initval of LUT4_105 : label is "0x8000";
- attribute initval of LUT4_104 : label is "0x8000";
- attribute initval of LUT4_103 : label is "0x8000";
- attribute initval of LUT4_102 : label is "0x8000";
- attribute initval of LUT4_101 : label is "0x8000";
- attribute initval of LUT4_100 : label is "0x8000";
- attribute initval of LUT4_99 : label is "0x8000";
- attribute initval of LUT4_98 : label is "0x8000";
- attribute initval of LUT4_97 : label is "0x8000";
- attribute initval of LUT4_96 : label is "0x8000";
- attribute initval of LUT4_95 : label is "0x8000";
- attribute initval of LUT4_94 : label is "0x8000";
- attribute initval of LUT4_93 : label is "0x8000";
- attribute initval of LUT4_92 : label is "0x8000";
- attribute initval of LUT4_91 : label is "0x8000";
- attribute initval of LUT4_90 : label is "0x8000";
- attribute initval of LUT4_89 : label is "0x8000";
- attribute initval of LUT4_88 : label is "0x8000";
- attribute initval of LUT4_87 : label is "0x8000";
- attribute initval of LUT4_86 : label is "0x8000";
- attribute initval of LUT4_85 : label is "0x8000";
- attribute initval of LUT4_84 : label is "0x8000";
- attribute initval of LUT4_83 : label is "0x8000";
- attribute initval of LUT4_82 : label is "0x8000";
- attribute initval of LUT4_81 : label is "0x8000";
- attribute initval of LUT4_80 : label is "0x8000";
- attribute initval of LUT4_79 : label is "0x8000";
- attribute initval of LUT4_78 : label is "0x8000";
- attribute initval of LUT4_77 : label is "0x8000";
- attribute initval of LUT4_76 : label is "0x8000";
- attribute initval of LUT4_75 : label is "0x8000";
- attribute initval of LUT4_74 : label is "0x8000";
- attribute initval of LUT4_73 : label is "0x8000";
- attribute initval of LUT4_72 : label is "0x8000";
- attribute initval of LUT4_71 : label is "0x8000";
- attribute initval of LUT4_70 : label is "0x8000";
- attribute initval of LUT4_69 : label is "0x8000";
- attribute initval of LUT4_68 : label is "0x8000";
- attribute initval of LUT4_67 : label is "0x8000";
- attribute initval of LUT4_66 : label is "0x8000";
- attribute initval of LUT4_65 : label is "0x8000";
- attribute initval of LUT4_64 : label is "0x8000";
- attribute initval of LUT4_63 : label is "0x8000";
- attribute initval of LUT4_62 : label is "0x8000";
- attribute initval of LUT4_61 : label is "0x8000";
- attribute initval of LUT4_60 : label is "0x8000";
- attribute initval of LUT4_59 : label is "0x8000";
- attribute initval of LUT4_58 : label is "0x8000";
- attribute initval of LUT4_57 : label is "0x8000";
- attribute initval of LUT4_56 : label is "0x8000";
- attribute initval of LUT4_55 : label is "0x8000";
- attribute initval of LUT4_54 : label is "0x8000";
- attribute initval of LUT4_53 : label is "0x8000";
- attribute initval of LUT4_52 : label is "0x6996";
- attribute initval of LUT4_51 : label is "0x6996";
- attribute initval of LUT4_50 : label is "0x6996";
- attribute initval of LUT4_49 : label is "0x6996";
- attribute initval of LUT4_48 : label is "0x6996";
- attribute initval of LUT4_47 : label is "0x6996";
- attribute initval of LUT4_46 : label is "0x6996";
- attribute initval of LUT4_45 : label is "0x6996";
- attribute initval of LUT4_44 : label is "0x6996";
- attribute initval of LUT4_43 : label is "0x6996";
- attribute initval of LUT4_42 : label is "0x6996";
- attribute initval of LUT4_41 : label is "0x6996";
- attribute initval of LUT4_40 : label is "0x6996";
- attribute initval of LUT4_39 : label is "0x6996";
- attribute initval of LUT4_38 : label is "0x6996";
- attribute initval of LUT4_37 : label is "0x6996";
- attribute initval of LUT4_36 : label is "0x6996";
- attribute initval of LUT4_35 : label is "0x6996";
- attribute initval of LUT4_34 : label is "0x6996";
- attribute initval of LUT4_33 : label is "0x6996";
- attribute initval of LUT4_32 : label is "0x6996";
- attribute initval of LUT4_31 : label is "0x6996";
- attribute initval of LUT4_30 : label is "0x6996";
- attribute initval of LUT4_29 : label is "0x6996";
- attribute initval of LUT4_28 : label is "0x6996";
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL";
- attribute GSR of pdp_ram_0_0_31 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is "";
- attribute CSDECODE_B of pdp_ram_1_0_30 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_0_30 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_0_30 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_0_30 : label is "NORMAL";
- attribute GSR of pdp_ram_1_0_30 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_0_30 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_0_30 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_0_30 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_0_30 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_1_0_30 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is "";
- attribute CSDECODE_B of pdp_ram_2_0_29 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_2_0_29 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_2_0_29 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_0_29 : label is "NORMAL";
- attribute GSR of pdp_ram_2_0_29 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_0_29 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_0_29 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_0_29 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_0_29 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_2_0_29 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is "";
- attribute CSDECODE_B of pdp_ram_3_0_28 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_3_0_28 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_3_0_28 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_0_28 : label is "NORMAL";
- attribute GSR of pdp_ram_3_0_28 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_0_28 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_0_28 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_0_28 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_0_28 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_3_0_28 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is "";
- attribute CSDECODE_B of pdp_ram_4_0_27 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_4_0_27 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_4_0_27 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_4_0_27 : label is "NORMAL";
- attribute GSR of pdp_ram_4_0_27 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_4_0_27 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_4_0_27 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_4_0_27 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_4_0_27 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_4_0_27 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is "";
- attribute CSDECODE_B of pdp_ram_5_0_26 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_5_0_26 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_5_0_26 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_5_0_26 : label is "NORMAL";
- attribute GSR of pdp_ram_5_0_26 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_5_0_26 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_5_0_26 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_5_0_26 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_5_0_26 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_5_0_26 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is "";
- attribute CSDECODE_B of pdp_ram_6_0_25 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_6_0_25 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_6_0_25 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_6_0_25 : label is "NORMAL";
- attribute GSR of pdp_ram_6_0_25 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_6_0_25 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_6_0_25 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_6_0_25 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_6_0_25 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_6_0_25 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is "";
- attribute CSDECODE_B of pdp_ram_7_0_24 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_7_0_24 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_7_0_24 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_7_0_24 : label is "NORMAL";
- attribute GSR of pdp_ram_7_0_24 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_7_0_24 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_7_0_24 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_7_0_24 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_7_0_24 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_7_0_24 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is "";
- attribute CSDECODE_B of pdp_ram_8_0_23 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_8_0_23 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_8_0_23 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_8_0_23 : label is "NORMAL";
- attribute GSR of pdp_ram_8_0_23 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_8_0_23 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_8_0_23 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_8_0_23 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_8_0_23 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_8_0_23 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is "";
- attribute CSDECODE_B of pdp_ram_9_0_22 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_9_0_22 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_9_0_22 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_9_0_22 : label is "NORMAL";
- attribute GSR of pdp_ram_9_0_22 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_9_0_22 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_9_0_22 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_9_0_22 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_9_0_22 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_9_0_22 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is "";
- attribute CSDECODE_B of pdp_ram_10_0_21 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_10_0_21 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_10_0_21 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_10_0_21 : label is "NORMAL";
- attribute GSR of pdp_ram_10_0_21 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_10_0_21 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_10_0_21 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_10_0_21 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_10_0_21 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_10_0_21 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is "";
- attribute CSDECODE_B of pdp_ram_11_0_20 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_11_0_20 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_11_0_20 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_11_0_20 : label is "NORMAL";
- attribute GSR of pdp_ram_11_0_20 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_11_0_20 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_11_0_20 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_11_0_20 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_11_0_20 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_11_0_20 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is "";
- attribute CSDECODE_B of pdp_ram_12_0_19 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_12_0_19 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_12_0_19 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_12_0_19 : label is "NORMAL";
- attribute GSR of pdp_ram_12_0_19 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_12_0_19 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_12_0_19 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_12_0_19 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_12_0_19 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_12_0_19 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is "";
- attribute CSDECODE_B of pdp_ram_13_0_18 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_13_0_18 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_13_0_18 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_13_0_18 : label is "NORMAL";
- attribute GSR of pdp_ram_13_0_18 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_13_0_18 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_13_0_18 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_13_0_18 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_13_0_18 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_13_0_18 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is "";
- attribute CSDECODE_B of pdp_ram_14_0_17 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_14_0_17 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_14_0_17 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_14_0_17 : label is "NORMAL";
- attribute GSR of pdp_ram_14_0_17 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_14_0_17 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_14_0_17 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_14_0_17 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_14_0_17 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_14_0_17 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is "";
- attribute CSDECODE_B of pdp_ram_15_0_16 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_15_0_16 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_15_0_16 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_15_0_16 : label is "NORMAL";
- attribute GSR of pdp_ram_15_0_16 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_15_0_16 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_15_0_16 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_15_0_16 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_15_0_16 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_15_0_16 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is "";
- attribute CSDECODE_B of pdp_ram_16_0_15 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_16_0_15 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_16_0_15 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_16_0_15 : label is "NORMAL";
- attribute GSR of pdp_ram_16_0_15 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_16_0_15 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_16_0_15 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_16_0_15 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_16_0_15 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_16_0_15 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is "";
- attribute CSDECODE_B of pdp_ram_17_0_14 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_17_0_14 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_17_0_14 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_17_0_14 : label is "NORMAL";
- attribute GSR of pdp_ram_17_0_14 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_17_0_14 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_17_0_14 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_17_0_14 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_17_0_14 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_17_0_14 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is "";
- attribute CSDECODE_B of pdp_ram_18_0_13 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_18_0_13 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_18_0_13 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_18_0_13 : label is "NORMAL";
- attribute GSR of pdp_ram_18_0_13 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_18_0_13 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_18_0_13 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_18_0_13 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_18_0_13 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_18_0_13 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is "";
- attribute CSDECODE_B of pdp_ram_19_0_12 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_19_0_12 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_19_0_12 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_19_0_12 : label is "NORMAL";
- attribute GSR of pdp_ram_19_0_12 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_19_0_12 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_19_0_12 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_19_0_12 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_19_0_12 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_19_0_12 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is "";
- attribute CSDECODE_B of pdp_ram_20_0_11 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_20_0_11 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_20_0_11 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_20_0_11 : label is "NORMAL";
- attribute GSR of pdp_ram_20_0_11 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_20_0_11 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_20_0_11 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_20_0_11 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_20_0_11 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_20_0_11 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is "";
- attribute CSDECODE_B of pdp_ram_21_0_10 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_21_0_10 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_21_0_10 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_21_0_10 : label is "NORMAL";
- attribute GSR of pdp_ram_21_0_10 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_21_0_10 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_21_0_10 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_21_0_10 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_21_0_10 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_21_0_10 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is "";
- attribute CSDECODE_B of pdp_ram_22_0_9 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_22_0_9 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_22_0_9 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_22_0_9 : label is "NORMAL";
- attribute GSR of pdp_ram_22_0_9 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_22_0_9 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_22_0_9 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_22_0_9 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_22_0_9 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_22_0_9 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is "";
- attribute CSDECODE_B of pdp_ram_23_0_8 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_23_0_8 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_23_0_8 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_23_0_8 : label is "NORMAL";
- attribute GSR of pdp_ram_23_0_8 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_23_0_8 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_23_0_8 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_23_0_8 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_23_0_8 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_23_0_8 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is "";
- attribute CSDECODE_B of pdp_ram_24_0_7 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_24_0_7 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_24_0_7 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_24_0_7 : label is "NORMAL";
- attribute GSR of pdp_ram_24_0_7 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_24_0_7 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_24_0_7 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_24_0_7 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_24_0_7 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_24_0_7 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is "";
- attribute CSDECODE_B of pdp_ram_25_0_6 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_25_0_6 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_25_0_6 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_25_0_6 : label is "NORMAL";
- attribute GSR of pdp_ram_25_0_6 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_25_0_6 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_25_0_6 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_25_0_6 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_25_0_6 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_25_0_6 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is "";
- attribute CSDECODE_B of pdp_ram_26_0_5 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_26_0_5 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_26_0_5 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_26_0_5 : label is "NORMAL";
- attribute GSR of pdp_ram_26_0_5 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_26_0_5 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_26_0_5 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_26_0_5 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_26_0_5 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_26_0_5 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is "";
- attribute CSDECODE_B of pdp_ram_27_0_4 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_27_0_4 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_27_0_4 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_27_0_4 : label is "NORMAL";
- attribute GSR of pdp_ram_27_0_4 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_27_0_4 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_27_0_4 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_27_0_4 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_27_0_4 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_27_0_4 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is "";
- attribute CSDECODE_B of pdp_ram_28_0_3 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_28_0_3 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_28_0_3 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_28_0_3 : label is "NORMAL";
- attribute GSR of pdp_ram_28_0_3 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_28_0_3 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_28_0_3 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_28_0_3 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_28_0_3 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_28_0_3 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is "";
- attribute CSDECODE_B of pdp_ram_29_0_2 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_29_0_2 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_29_0_2 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_29_0_2 : label is "NORMAL";
- attribute GSR of pdp_ram_29_0_2 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_29_0_2 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_29_0_2 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_29_0_2 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_29_0_2 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_29_0_2 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is "";
- attribute CSDECODE_B of pdp_ram_30_0_1 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_30_0_1 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_30_0_1 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_30_0_1 : label is "NORMAL";
- attribute GSR of pdp_ram_30_0_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_30_0_1 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_30_0_1 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_30_0_1 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_30_0_1 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_30_0_1 : label is "18";
- attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_32kx16x8_mb2.lpc";
- attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is "";
- attribute CSDECODE_B of pdp_ram_31_0_0 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_31_0_0 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_31_0_0 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_31_0_0 : label is "NORMAL";
- attribute GSR of pdp_ram_31_0_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_31_0_0 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_31_0_0 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_31_0_0 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_31_0_0 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_31_0_0 : label is "18";
- attribute GSR of FF_239 : label is "ENABLED";
- attribute GSR of FF_238 : label is "ENABLED";
- attribute GSR of FF_237 : label is "ENABLED";
- attribute GSR of FF_236 : label is "ENABLED";
- attribute GSR of FF_235 : label is "ENABLED";
- attribute GSR of FF_234 : label is "ENABLED";
- attribute GSR of FF_233 : label is "ENABLED";
- attribute GSR of FF_232 : label is "ENABLED";
- attribute GSR of FF_231 : label is "ENABLED";
- attribute GSR of FF_230 : label is "ENABLED";
- attribute GSR of FF_229 : label is "ENABLED";
- attribute GSR of FF_228 : label is "ENABLED";
- attribute GSR of FF_227 : label is "ENABLED";
- attribute GSR of FF_226 : label is "ENABLED";
- attribute GSR of FF_225 : label is "ENABLED";
- attribute GSR of FF_224 : label is "ENABLED";
- attribute GSR of FF_223 : label is "ENABLED";
- attribute GSR of FF_222 : label is "ENABLED";
- attribute GSR of FF_221 : label is "ENABLED";
- attribute GSR of FF_220 : label is "ENABLED";
- attribute GSR of FF_219 : label is "ENABLED";
- attribute GSR of FF_218 : label is "ENABLED";
- attribute GSR of FF_217 : label is "ENABLED";
- attribute GSR of FF_216 : label is "ENABLED";
- attribute GSR of FF_215 : label is "ENABLED";
- attribute GSR of FF_214 : label is "ENABLED";
- attribute GSR of FF_213 : label is "ENABLED";
- attribute GSR of FF_212 : label is "ENABLED";
- attribute GSR of FF_211 : label is "ENABLED";
- attribute GSR of FF_210 : label is "ENABLED";
- attribute GSR of FF_209 : label is "ENABLED";
- attribute GSR of FF_208 : label is "ENABLED";
- attribute GSR of FF_207 : label is "ENABLED";
- attribute GSR of FF_206 : label is "ENABLED";
- attribute GSR of FF_205 : label is "ENABLED";
- attribute GSR of FF_204 : label is "ENABLED";
- attribute GSR of FF_203 : label is "ENABLED";
- attribute GSR of FF_202 : label is "ENABLED";
- attribute GSR of FF_201 : label is "ENABLED";
- attribute GSR of FF_200 : label is "ENABLED";
- attribute GSR of FF_199 : label is "ENABLED";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t39: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_12: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t38: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_11: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t37: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t36: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t35: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t34: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t33: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t32: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t31: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t30: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t29: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t28: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t27: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t26: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t25: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t24: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t23: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t22: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t21: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t20: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t19: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t18: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t17: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t16: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t15: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t14: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t13: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t12: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t11: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t10: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t9: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t8: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t7: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t6: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- INV_10: INV
- port map (A=>wptr_10, Z=>wptr_10_inv);
-
- INV_9: INV
- port map (A=>wptr_11, Z=>wptr_11_inv);
-
- INV_8: INV
- port map (A=>wptr_12, Z=>wptr_12_inv);
-
- INV_7: INV
- port map (A=>wptr_13, Z=>wptr_13_inv);
-
- INV_6: INV
- port map (A=>wptr_14, Z=>wptr_14_inv);
-
- LUT4_180: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet);
-
- LUT4_179: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_p00);
-
- INV_5: INV
- port map (A=>rptr_11, Z=>rptr_11_inv);
-
- INV_4: INV
- port map (A=>rptr_12, Z=>rptr_12_inv);
-
- INV_3: INV
- port map (A=>rptr_13, Z=>rptr_13_inv);
-
- INV_2: INV
- port map (A=>rptr_14, Z=>rptr_14_inv);
-
- INV_1: INV
- port map (A=>rptr_15, Z=>rptr_15_inv);
-
- LUT4_178: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_1);
-
- LUT4_177: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec1_r10);
-
- LUT4_176: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_2);
-
- LUT4_175: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec2_p01);
-
- LUT4_174: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_3);
-
- LUT4_173: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec3_r11);
-
- LUT4_172: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_4);
-
- LUT4_171: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec4_p02);
-
- LUT4_170: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_5);
-
- LUT4_169: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec5_r12);
-
- LUT4_168: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_6);
-
- LUT4_167: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec6_p03);
-
- LUT4_166: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_7);
-
- LUT4_165: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec7_r13);
-
- LUT4_164: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_8);
-
- LUT4_163: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec8_p04);
-
- LUT4_162: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_9);
-
- LUT4_161: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec9_r14);
-
- LUT4_160: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_10);
-
- LUT4_159: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05);
-
- LUT4_158: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_11);
-
- LUT4_157: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15);
-
- LUT4_156: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_12);
-
- LUT4_155: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06);
-
- LUT4_154: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_13);
-
- LUT4_153: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16);
-
- LUT4_152: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_14);
-
- LUT4_151: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07);
-
- LUT4_150: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_15);
-
- LUT4_149: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17);
-
- LUT4_148: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_16);
-
- LUT4_147: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08);
-
- LUT4_146: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_17);
-
- LUT4_145: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18);
-
- LUT4_144: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_18);
-
- LUT4_143: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09);
-
- LUT4_142: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_19);
-
- LUT4_141: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19);
-
- LUT4_140: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_20);
-
- LUT4_139: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010);
-
- LUT4_138: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_21);
-
- LUT4_137: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110);
-
- LUT4_136: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_22);
-
- LUT4_135: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011);
-
- LUT4_134: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_23);
-
- LUT4_133: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111);
-
- LUT4_132: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_24);
-
- LUT4_131: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012);
-
- LUT4_130: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_25);
-
- LUT4_129: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112);
-
- LUT4_128: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_26);
-
- LUT4_127: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013);
-
- LUT4_126: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_27);
-
- LUT4_125: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113);
-
- LUT4_124: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_28);
-
- LUT4_123: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014);
-
- LUT4_122: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_29);
-
- LUT4_121: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114);
-
- LUT4_120: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
- DO0=>func_and_inet_30);
-
- LUT4_119: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015);
-
- LUT4_118: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_31);
-
- LUT4_117: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115);
-
- LUT4_116: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_32);
-
- LUT4_115: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec32_p016);
-
- LUT4_114: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_33);
-
- LUT4_113: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec33_r116);
-
- LUT4_112: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_34);
-
- LUT4_111: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec34_p017);
-
- LUT4_110: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_35);
-
- LUT4_109: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec35_r117);
-
- LUT4_108: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_36);
-
- LUT4_107: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec36_p018);
-
- LUT4_106: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_37);
-
- LUT4_105: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec37_r118);
-
- LUT4_104: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13_inv, DO0=>func_and_inet_38);
-
- LUT4_103: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec38_p019);
-
- LUT4_102: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_39);
-
- LUT4_101: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec39_r119);
-
- LUT4_100: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_40);
-
- LUT4_99: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec40_p020);
-
- LUT4_98: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_41);
-
- LUT4_97: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec41_r120);
-
- LUT4_96: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_42);
-
- LUT4_95: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec42_p021);
-
- LUT4_94: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_43);
-
- LUT4_93: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec43_r121);
-
- LUT4_92: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_44);
-
- LUT4_91: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec44_p022);
-
- LUT4_90: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_45);
-
- LUT4_89: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec45_r122);
-
- LUT4_88: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13_inv, DO0=>func_and_inet_46);
-
- LUT4_87: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec46_p023);
-
- LUT4_86: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_47);
-
- LUT4_85: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec47_r123);
-
- LUT4_84: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_48);
-
- LUT4_83: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec48_p024);
-
- LUT4_82: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_49);
-
- LUT4_81: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec49_r124);
-
- LUT4_80: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_50);
-
- LUT4_79: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec50_p025);
-
- LUT4_78: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_51);
-
- LUT4_77: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec51_r125);
-
- LUT4_76: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_52);
-
- LUT4_75: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec52_p026);
-
- LUT4_74: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_53);
-
- LUT4_73: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec53_r126);
-
- LUT4_72: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
- AD0=>wptr_13, DO0=>func_and_inet_54);
-
- LUT4_71: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec54_p027);
-
- LUT4_70: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_55);
-
- LUT4_69: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec55_r127);
-
- LUT4_68: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_56);
-
- LUT4_67: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec56_p028);
-
- LUT4_66: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_57);
-
- LUT4_65: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec57_r128);
-
- LUT4_64: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_58);
-
- LUT4_63: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec58_p029);
-
- LUT4_62: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_59);
-
- LUT4_61: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec59_r129);
-
- LUT4_60: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
- AD0=>wptr_13, DO0=>func_and_inet_60);
-
- LUT4_59: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec60_p030);
-
- LUT4_58: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_61);
-
- LUT4_57: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec61_r130);
-
- LUT4_56: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
- DO0=>func_and_inet_62);
-
- LUT4_55: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec62_p031);
-
- LUT4_54: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_63);
-
- LUT4_53: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec63_r131);
-
- LUT4_52: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_51: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_50: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_49: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_48: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_47: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13);
-
- LUT4_46: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_45: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
-
- LUT4_44: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9);
-
- LUT4_43: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_42: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_41: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6);
-
- LUT4_40: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_39: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_38: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_37: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3);
-
- LUT4_36: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_35: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r2);
-
- LUT4_34: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_33: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r1);
-
- LUT4_32: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r0);
-
- LUT4_31: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- XOR2_t5: XOR2
- port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb);
-
- XOR2_t4: XOR2
- port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb);
-
- XOR2_t3: XOR2
- port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb);
-
- XOR2_t2: XOR2
- port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- INV_0: INV
- port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv);
-
- AND2_t1: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig);
-
- AND2_t0: AND2
- port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig);
-
- pdp_ram_0_0_31: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec0_p00,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec1_r10,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0,
- DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3,
- DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6,
- DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_30: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec2_p01,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec3_r11,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0,
- DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3,
- DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6,
- DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_29: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec4_p02,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec5_r12,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0,
- DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3,
- DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6,
- DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_28: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec6_p03,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec7_r13,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0,
- DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3,
- DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6,
- DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_4_0_27: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec8_p04,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec9_r14,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0,
- DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3,
- DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6,
- DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_5_0_26: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec10_p05,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec11_r15,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0,
- DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3,
- DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6,
- DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_6_0_25: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec12_p06,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec13_r16,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0,
- DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3,
- DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6,
- DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_7_0_24: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec14_p07,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec15_r17,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0,
- DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3,
- DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6,
- DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_8_0_23: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec16_p08,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec17_r18,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0,
- DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3,
- DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6,
- DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_9_0_22: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec18_p09,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec19_r19,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0,
- DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3,
- DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6,
- DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_10_0_21: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec20_p010,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec21_r110,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0,
- DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3,
- DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6,
- DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_11_0_20: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec22_p011,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec23_r111,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0,
- DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3,
- DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6,
- DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_12_0_19: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec24_p012,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec25_r112,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0,
- DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3,
- DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6,
- DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_13_0_18: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec26_p013,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec27_r113,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0,
- DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3,
- DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6,
- DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_14_0_17: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec28_p014,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec29_r114,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0,
- DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3,
- DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6,
- DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_15_0_16: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec30_p015,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec31_r115,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0,
- DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3,
- DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6,
- DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_16_0_15: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec32_p016,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec33_r116,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0,
- DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3,
- DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6,
- DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_17_0_14: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec34_p017,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec35_r117,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0,
- DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3,
- DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6,
- DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_18_0_13: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec36_p018,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec37_r118,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0,
- DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3,
- DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6,
- DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_19_0_12: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec38_p019,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec39_r119,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0,
- DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3,
- DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6,
- DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_20_0_11: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec40_p020,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec41_r120,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0,
- DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3,
- DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6,
- DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_21_0_10: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec42_p021,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec43_r121,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0,
- DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3,
- DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6,
- DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_22_0_9: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec44_p022,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec45_r122,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0,
- DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3,
- DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6,
- DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_23_0_8: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec46_p023,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec47_r123,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0,
- DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3,
- DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6,
- DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_24_0_7: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec48_p024,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec49_r124,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0,
- DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3,
- DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6,
- DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_25_0_6: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec50_p025,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec51_r125,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0,
- DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3,
- DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6,
- DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_26_0_5: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec52_p026,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec53_r126,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0,
- DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3,
- DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6,
- DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_27_0_4: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec54_p027,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec55_r127,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0,
- DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3,
- DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6,
- DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_28_0_3: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec56_p028,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec57_r128,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0,
- DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3,
- DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6,
- DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_29_0_2: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec58_p029,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec59_r129,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0,
- DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3,
- DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6,
- DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_30_0_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec60_p030,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec61_r130,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0,
- DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3,
- DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6,
- DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_31_0_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec62_p031,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec63_r131,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0,
- DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3,
- DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6,
- DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_239: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_238: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_237: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_236: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_235: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_234: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_233: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_232: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_231: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_230: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_229: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_228: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_227: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_226: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_225: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_224: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_223: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_222: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_221: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_220: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_219: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_218: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_217: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_216: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_215: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_214: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_213: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_212: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_211: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_210: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_209: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_208: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_207: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_206: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_205: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_204: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_203: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_202: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_201: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_200: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_199: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_198: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_197: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_196: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_195: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_194: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_193: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_192: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_191: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_190: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_189: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_188: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_187: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_186: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_185: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_184: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_183: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_182: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_181: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_180: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_179: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_178: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_177: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_176: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_175: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_174: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_173: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_172: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_171: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_170: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_169: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_168: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_167: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_166: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_165: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_164: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_163: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_162: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_161: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_160: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_159: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_158: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_157: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_156: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_155: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_154: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_153: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_152: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_151: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_150: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_149: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_148: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_147: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_146: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_145: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_144: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_143: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_142: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_141: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_140: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_139: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_12_ff);
-
- FF_138: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_13_ff);
-
- FF_137: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_136: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_135: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_134: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_133: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_132: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_131: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_130: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_129: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_128: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_127: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_126: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_125: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_124: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_123: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_122: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_121: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_120: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_119: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_118: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_117: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_116: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_115: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_114: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_113: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_112: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_111: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_110: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_109: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_108: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_107: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_106: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_105: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_104: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_103: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_102: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_101: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_100: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_99: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_98: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_97: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_96: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_95: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_94: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_93: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_92: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_91: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_90: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_89: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_88: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_87: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_86: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_85: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_84: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_83: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_82: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_81: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_80: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_79: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_78: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_77: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_76: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_75: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_74: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_73: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_72: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_71: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_70: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_69: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0);
-
- FF_68: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1);
-
- FF_67: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2);
-
- FF_66: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3);
-
- FF_65: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4);
-
- FF_64: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5);
-
- FF_63: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6);
-
- FF_62: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7);
-
- FF_61: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8);
-
- FF_60: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9);
-
- FF_59: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10);
-
- FF_58: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11);
-
- FF_57: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12);
-
- FF_56: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13);
-
- FF_55: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14);
-
- FF_54: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15);
-
- FF_53: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0);
-
- FF_52: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1);
-
- FF_51: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2);
-
- FF_50: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12));
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13));
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14));
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15));
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10));
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11));
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12));
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13));
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14));
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15));
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16));
-
- FF_3: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>ircount_16, NC1=>open);
-
- mux_8: MUX321
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
- D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
- D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
- D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0,
- D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0,
- D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0,
- D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0,
- D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0,
- D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(0));
-
- mux_7: MUX321
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
- D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
- D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
- D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1,
- D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1,
- D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1,
- D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1,
- D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1,
- D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(1));
-
- mux_6: MUX321
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
- D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
- D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
- D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2,
- D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2,
- D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2,
- D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2,
- D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2,
- D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(2));
-
- mux_5: MUX321
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
- D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
- D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
- D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3,
- D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3,
- D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3,
- D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3,
- D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3,
- D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(3));
-
- mux_4: MUX321
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
- D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
- D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
- D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4,
- D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4,
- D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4,
- D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4,
- D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4,
- D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(4));
-
- mux_3: MUX321
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
- D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
- D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
- D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5,
- D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5,
- D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5,
- D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5,
- D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5,
- D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(5));
-
- mux_2: MUX321
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
- D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
- D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
- D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6,
- D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6,
- D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6,
- D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6,
- D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6,
- D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(6));
-
- mux_1: MUX321
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
- D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
- D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
- D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7,
- D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7,
- D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7,
- D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7,
- D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7,
- D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(7));
-
- mux_0: MUX321
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
- D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
- D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
- D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8,
- D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8,
- D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8,
- D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8,
- D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8,
- D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(8));
-
- precin_inst860: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open,
- S1=>open);
-
- wcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>precin, BOUT=>co0_2, S0=>open,
- S1=>wcnt_sub_0);
-
- wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2,
- B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1,
- S1=>wcnt_sub_2);
-
- wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4,
- B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3,
- S1=>wcnt_sub_4);
-
- wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6,
- B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5,
- S1=>wcnt_sub_6);
-
- wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8,
- B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7,
- S1=>wcnt_sub_8);
-
- wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9,
- S1=>wcnt_sub_10);
-
- wcnt_6: FSUB2B
- port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2,
- S0=>wcnt_sub_11, S1=>wcnt_sub_12);
-
- wcnt_7: FSUB2B
- port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13,
- S1=>wcnt_sub_14);
-
- wcnt_8: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15,
- S1=>open);
-
- precin_inst903: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin_1, S0=>open,
- S1=>open);
-
- rcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rcount_0, BI=>precin_1, BOUT=>co0_3, S0=>open,
- S1=>rcnt_sub_0);
-
- rcnt_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1,
- B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1,
- S1=>rcnt_sub_2);
-
- rcnt_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3,
- B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3,
- S1=>rcnt_sub_4);
-
- rcnt_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5,
- B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5,
- S1=>rcnt_sub_6);
-
- rcnt_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7,
- B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7,
- S1=>rcnt_sub_8);
-
- rcnt_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9,
- B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9,
- S1=>rcnt_sub_10);
-
- rcnt_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11,
- B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11,
- S1=>rcnt_sub_12);
-
- rcnt_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13,
- B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13,
- S1=>rcnt_sub_14);
-
- rcnt_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15,
- B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15,
- S1=>rcnt_sub_16);
-
- rcntd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open);
-
- precin_inst948: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin_2, S0=>open,
- S1=>open);
-
- wfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo,
- B1=>rcount_w1, BI=>precin_2, BOUT=>co0_4, S0=>open,
- S1=>wfill_sub_0);
-
- wfill_1: FSUB2B
- port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3,
- BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2);
-
- wfill_2: FSUB2B
- port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5,
- BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4);
-
- wfill_3: FSUB2B
- port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7,
- BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6);
-
- wfill_4: FSUB2B
- port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9,
- BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8);
-
- wfill_5: FSUB2B
- port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10,
- B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9,
- S1=>wfill_sub_10);
-
- wfill_6: FSUB2B
- port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4,
- S0=>wfill_sub_11, S1=>wfill_sub_12);
-
- wfill_7: FSUB2B
- port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14,
- B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13,
- S1=>wfill_sub_14);
-
- wfill_8: FSUB2B
- port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15,
- S1=>open);
-
- precin_inst975: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin_3, S0=>open,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- rfill_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>rptr_0, BI=>precin_3, BOUT=>co0_5, S0=>open,
- S1=>rfill_sub_0);
-
- rfill_1: FSUB2B
- port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2,
- BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2);
-
- rfill_2: FSUB2B
- port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4,
- BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4);
-
- rfill_3: FSUB2B
- port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6,
- BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6);
-
- rfill_4: FSUB2B
- port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8,
- BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8);
-
- rfill_5: FSUB2B
- port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10,
- BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10);
-
- rfill_6: FSUB2B
- port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11,
- B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11,
- S1=>rfill_sub_12);
-
- rfill_7: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13,
- B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13,
- S1=>rfill_sub_14);
-
- rfill_8: FSUB2B
- port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15,
- B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15,
- S1=>rfill_sub_16);
-
- rfilld: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_6, GE=>co1_6);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_6, GE=>co2_6);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_6, GE=>co3_6);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
- B1=>wcount_r8, CI=>co3_6, GE=>co4_6);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co4_6, GE=>co5_6);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11,
- B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13,
- B1=>wcount_r14, CI=>co6_6, GE=>co7_6);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_7, GE=>co1_7);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_7, GE=>co2_7);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>rcount_w8, CI=>co2_7, GE=>co3_7);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
- B1=>rcount_w10, CI=>co3_7, GE=>co4_7);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11,
- B1=>rcount_w12, CI=>co4_7, GE=>co5_7);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w14, CI=>co5_7, GE=>co6_7);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15,
- B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- ae_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- ae_cmp_0: AGEB2
- port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
- B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8);
-
- ae_cmp_1: AGEB2
- port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
- B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8);
-
- ae_cmp_2: AGEB2
- port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
- B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8);
-
- ae_cmp_3: AGEB2
- port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
- B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8);
-
- ae_cmp_4: AGEB2
- port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9),
- B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8);
-
- ae_cmp_5: AGEB2
- port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11),
- B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8);
-
- ae_cmp_6: AGEB2
- port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13),
- B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8);
-
- ae_cmp_7: AGEB2
- port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15),
- B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7);
-
- ae_cmp_8: AGEB2
- port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig,
- B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
-
- af_d_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
-
- af_d_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
- B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9);
-
- af_d_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
- B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9);
-
- af_d_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
- B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9);
-
- af_d_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
- B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9);
-
- af_d_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
- B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9);
-
- af_d_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
- B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9);
-
- af_d_cmp_6: AGEB2
- port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
- B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9);
-
- af_d_cmp_7: AGEB2
- port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14),
- B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of fifo_32kx16x8_mb2 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:MUX321 use entity ecp2m.MUX321(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond (64-bit) 3.9.1.119
-Thu Jan 18 18:38:11 2018
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill
- Circuit name : fifo_32kx16x8_mb2
- Module type : ebfifo
- Module Version : 5.8
- Ports :
- Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0]
- Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull
- I/O buffer : not inserted
- EDIF output : fifo_32kx16x8_mb2.edn
- VHDL output : fifo_32kx16x8_mb2.vhd
- VHDL template : fifo_32kx16x8_mb2_tmpl.vhd
- VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_32kx16x8_mb2.srp
- Estimated Resource Usage:
- LUT : 499
- EBR : 32
- Reg : 240
-
-END SCUBA Module Synthesis
-
-File: fifo_32kx16x8_mb2.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.9.1.119
--- Module Version: 5.8
--- Thu Jan 18 18:38:11 2018
-
--- parameterized module component declaration
-component fifo_32kx16x8_mb2
- port (Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(8 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_32kx16x8_mb2
- port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__,
- AmFullThresh(14 downto 0)=>__, Q(8 downto 0)=>__, WCNT(15 downto 0)=>__,
- RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__,
- AlmostFull=>__);
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41)
--- Module Version: 5.3
--- Fri Feb 05 16:48:13 2010
-
--- parameterized module component declaration
-component fifo_32kx16x8_mb
- port (Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(15 downto 0);
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(7 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_32kx16x8_mb
- port map (Data(15 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__,
- AmFullThresh(14 downto 0)=>__, Q(7 downto 0)=>__, WCNT(15 downto 0)=>__,
- RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__,
- AlmostFull=>__);
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-5F900C\r
-SpeedGrade=-5\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=FIFO_DC\r
-CoreRevision=5.3\r
-ModuleName=fifo_4096x32\r
-SourceFormat=Schematic/VHDL\r
-ParameterFileVersion=1.0\r
-Date=12/18/2009\r
-Time=03:02:30\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-FIFOImp=EBR Based\r
-Depth=4096\r
-Width=32\r
-RDepth=4096\r
-RWidth=32\r
-regout=0\r
-CtrlByRdEn=0\r
-EmpFlg=0\r
-PeMode=Static - Dual Threshold\r
-PeAssert=10\r
-PeDeassert=12\r
-FullFlg=0\r
-PfMode=Static - Dual Threshold\r
-PfAssert=508\r
-PfDeassert=506\r
-RDataCount=0\r
-WDataCount=0\r
-EnECC=0\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)\r
--- Module Version: 5.3\r
---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e \r
-\r
--- Fri Dec 18 03:02:30 2009\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
--- synopsys translate_off\r
-library ecp2m;\r
-use ecp2m.components.all;\r
--- synopsys translate_on\r
-\r
-entity fifo_4096x32 is\r
- port (\r
- Data: in std_logic_vector(31 downto 0); \r
- WrClock: in std_logic; \r
- RdClock: in std_logic; \r
- WrEn: in std_logic; \r
- RdEn: in std_logic; \r
- Reset: in std_logic; \r
- RPReset: in std_logic; \r
- Q: out std_logic_vector(31 downto 0); \r
- Empty: out std_logic; \r
- Full: out std_logic);\r
-end fifo_4096x32;\r
-\r
-architecture Structure of fifo_4096x32 is\r
-\r
- -- internal signal declarations\r
- signal invout_1: std_logic;\r
- signal invout_0: std_logic;\r
- signal w_g2b_xor_cluster_2_1: std_logic;\r
- signal w_g2b_xor_cluster_2: std_logic;\r
- signal w_g2b_xor_cluster_1: std_logic;\r
- signal r_g2b_xor_cluster_2_1: std_logic;\r
- signal r_g2b_xor_cluster_2: std_logic;\r
- signal r_g2b_xor_cluster_1: std_logic;\r
- signal w_gdata_0: std_logic;\r
- signal w_gdata_1: std_logic;\r
- signal w_gdata_2: std_logic;\r
- signal w_gdata_3: std_logic;\r
- signal w_gdata_4: std_logic;\r
- signal w_gdata_5: std_logic;\r
- signal w_gdata_6: std_logic;\r
- signal w_gdata_7: std_logic;\r
- signal w_gdata_8: std_logic;\r
- signal w_gdata_9: std_logic;\r
- signal w_gdata_10: std_logic;\r
- signal w_gdata_11: std_logic;\r
- signal wptr_0: std_logic;\r
- signal wptr_1: std_logic;\r
- signal wptr_2: std_logic;\r
- signal wptr_3: std_logic;\r
- signal wptr_4: std_logic;\r
- signal wptr_5: std_logic;\r
- signal wptr_6: std_logic;\r
- signal wptr_7: std_logic;\r
- signal wptr_8: std_logic;\r
- signal wptr_9: std_logic;\r
- signal wptr_10: std_logic;\r
- signal wptr_11: std_logic;\r
- signal wptr_12: std_logic;\r
- signal r_gdata_0: std_logic;\r
- signal r_gdata_1: std_logic;\r
- signal r_gdata_2: std_logic;\r
- signal r_gdata_3: std_logic;\r
- signal r_gdata_4: std_logic;\r
- signal r_gdata_5: std_logic;\r
- signal r_gdata_6: std_logic;\r
- signal r_gdata_7: std_logic;\r
- signal r_gdata_8: std_logic;\r
- signal r_gdata_9: std_logic;\r
- signal r_gdata_10: std_logic;\r
- signal r_gdata_11: std_logic;\r
- signal rptr_0: std_logic;\r
- signal rptr_1: std_logic;\r
- signal rptr_2: std_logic;\r
- signal rptr_3: std_logic;\r
- signal rptr_4: std_logic;\r
- signal rptr_5: std_logic;\r
- signal rptr_6: std_logic;\r
- signal rptr_7: std_logic;\r
- signal rptr_8: std_logic;\r
- signal rptr_9: std_logic;\r
- signal rptr_10: std_logic;\r
- signal rptr_11: std_logic;\r
- signal rptr_12: std_logic;\r
- signal w_gcount_0: std_logic;\r
- signal w_gcount_1: std_logic;\r
- signal w_gcount_2: std_logic;\r
- signal w_gcount_3: std_logic;\r
- signal w_gcount_4: std_logic;\r
- signal w_gcount_5: std_logic;\r
- signal w_gcount_6: std_logic;\r
- signal w_gcount_7: std_logic;\r
- signal w_gcount_8: std_logic;\r
- signal w_gcount_9: std_logic;\r
- signal w_gcount_10: std_logic;\r
- signal w_gcount_11: std_logic;\r
- signal w_gcount_12: std_logic;\r
- signal r_gcount_0: std_logic;\r
- signal r_gcount_1: std_logic;\r
- signal r_gcount_2: std_logic;\r
- signal r_gcount_3: std_logic;\r
- signal r_gcount_4: std_logic;\r
- signal r_gcount_5: std_logic;\r
- signal r_gcount_6: std_logic;\r
- signal r_gcount_7: std_logic;\r
- signal r_gcount_8: std_logic;\r
- signal r_gcount_9: std_logic;\r
- signal r_gcount_10: std_logic;\r
- signal r_gcount_11: std_logic;\r
- signal r_gcount_12: std_logic;\r
- signal w_gcount_r20: std_logic;\r
- signal w_gcount_r0: std_logic;\r
- signal w_gcount_r21: std_logic;\r
- signal w_gcount_r1: std_logic;\r
- signal w_gcount_r22: std_logic;\r
- signal w_gcount_r2: std_logic;\r
- signal w_gcount_r23: std_logic;\r
- signal w_gcount_r3: std_logic;\r
- signal w_gcount_r24: std_logic;\r
- signal w_gcount_r4: std_logic;\r
- signal w_gcount_r25: std_logic;\r
- signal w_gcount_r5: std_logic;\r
- signal w_gcount_r26: std_logic;\r
- signal w_gcount_r6: std_logic;\r
- signal w_gcount_r27: std_logic;\r
- signal w_gcount_r7: std_logic;\r
- signal w_gcount_r28: std_logic;\r
- signal w_gcount_r8: std_logic;\r
- signal w_gcount_r29: std_logic;\r
- signal w_gcount_r9: std_logic;\r
- signal w_gcount_r210: std_logic;\r
- signal w_gcount_r10: std_logic;\r
- signal w_gcount_r211: std_logic;\r
- signal w_gcount_r11: std_logic;\r
- signal w_gcount_r212: std_logic;\r
- signal w_gcount_r12: std_logic;\r
- signal r_gcount_w20: std_logic;\r
- signal r_gcount_w0: std_logic;\r
- signal r_gcount_w21: std_logic;\r
- signal r_gcount_w1: std_logic;\r
- signal r_gcount_w22: std_logic;\r
- signal r_gcount_w2: std_logic;\r
- signal r_gcount_w23: std_logic;\r
- signal r_gcount_w3: std_logic;\r
- signal r_gcount_w24: std_logic;\r
- signal r_gcount_w4: std_logic;\r
- signal r_gcount_w25: std_logic;\r
- signal r_gcount_w5: std_logic;\r
- signal r_gcount_w26: std_logic;\r
- signal r_gcount_w6: std_logic;\r
- signal r_gcount_w27: std_logic;\r
- signal r_gcount_w7: std_logic;\r
- signal r_gcount_w28: std_logic;\r
- signal r_gcount_w8: std_logic;\r
- signal r_gcount_w29: std_logic;\r
- signal r_gcount_w9: std_logic;\r
- signal r_gcount_w210: std_logic;\r
- signal r_gcount_w10: std_logic;\r
- signal r_gcount_w211: std_logic;\r
- signal r_gcount_w11: std_logic;\r
- signal r_gcount_w212: std_logic;\r
- signal r_gcount_w12: std_logic;\r
- signal empty_i: std_logic;\r
- signal rRst: std_logic;\r
- signal full_i: std_logic;\r
- signal iwcount_0: std_logic;\r
- signal iwcount_1: std_logic;\r
- signal w_gctr_ci: std_logic;\r
- signal iwcount_2: std_logic;\r
- signal iwcount_3: std_logic;\r
- signal co0: std_logic;\r
- signal iwcount_4: std_logic;\r
- signal iwcount_5: std_logic;\r
- signal co1: std_logic;\r
- signal iwcount_6: std_logic;\r
- signal iwcount_7: std_logic;\r
- signal co2: std_logic;\r
- signal iwcount_8: std_logic;\r
- signal iwcount_9: std_logic;\r
- signal co3: std_logic;\r
- signal iwcount_10: std_logic;\r
- signal iwcount_11: std_logic;\r
- signal co4: std_logic;\r
- signal iwcount_12: std_logic;\r
- signal co6: std_logic;\r
- signal wcount_12: std_logic;\r
- signal co5: std_logic;\r
- signal scuba_vhi: std_logic;\r
- signal ircount_0: std_logic;\r
- signal ircount_1: std_logic;\r
- signal r_gctr_ci: std_logic;\r
- signal ircount_2: std_logic;\r
- signal ircount_3: std_logic;\r
- signal co0_1: std_logic;\r
- signal ircount_4: std_logic;\r
- signal ircount_5: std_logic;\r
- signal co1_1: std_logic;\r
- signal ircount_6: std_logic;\r
- signal ircount_7: std_logic;\r
- signal co2_1: std_logic;\r
- signal ircount_8: std_logic;\r
- signal ircount_9: std_logic;\r
- signal co3_1: std_logic;\r
- signal ircount_10: std_logic;\r
- signal ircount_11: std_logic;\r
- signal co4_1: std_logic;\r
- signal ircount_12: std_logic;\r
- signal co6_1: std_logic;\r
- signal rcount_12: std_logic;\r
- signal co5_1: std_logic;\r
- signal rden_i: std_logic;\r
- signal cmp_ci: std_logic;\r
- signal wcount_r0: std_logic;\r
- signal wcount_r1: std_logic;\r
- signal rcount_0: std_logic;\r
- signal rcount_1: std_logic;\r
- signal co0_2: std_logic;\r
- signal wcount_r2: std_logic;\r
- signal wcount_r3: std_logic;\r
- signal rcount_2: std_logic;\r
- signal rcount_3: std_logic;\r
- signal co1_2: std_logic;\r
- signal wcount_r4: std_logic;\r
- signal wcount_r5: std_logic;\r
- signal rcount_4: std_logic;\r
- signal rcount_5: std_logic;\r
- signal co2_2: std_logic;\r
- signal wcount_r6: std_logic;\r
- signal wcount_r7: std_logic;\r
- signal rcount_6: std_logic;\r
- signal rcount_7: std_logic;\r
- signal co3_2: std_logic;\r
- signal wcount_r8: std_logic;\r
- signal w_g2b_xor_cluster_0: std_logic;\r
- signal rcount_8: std_logic;\r
- signal rcount_9: std_logic;\r
- signal co4_2: std_logic;\r
- signal wcount_r10: std_logic;\r
- signal wcount_r11: std_logic;\r
- signal rcount_10: std_logic;\r
- signal rcount_11: std_logic;\r
- signal co5_2: std_logic;\r
- signal empty_cmp_clr: std_logic;\r
- signal empty_cmp_set: std_logic;\r
- signal empty_d: std_logic;\r
- signal empty_d_c: std_logic;\r
- signal wren_i: std_logic;\r
- signal cmp_ci_1: std_logic;\r
- signal rcount_w0: std_logic;\r
- signal rcount_w1: std_logic;\r
- signal wcount_0: std_logic;\r
- signal wcount_1: std_logic;\r
- signal co0_3: std_logic;\r
- signal rcount_w2: std_logic;\r
- signal rcount_w3: std_logic;\r
- signal wcount_2: std_logic;\r
- signal wcount_3: std_logic;\r
- signal co1_3: std_logic;\r
- signal rcount_w4: std_logic;\r
- signal rcount_w5: std_logic;\r
- signal wcount_4: std_logic;\r
- signal wcount_5: std_logic;\r
- signal co2_3: std_logic;\r
- signal rcount_w6: std_logic;\r
- signal rcount_w7: std_logic;\r
- signal wcount_6: std_logic;\r
- signal wcount_7: std_logic;\r
- signal co3_3: std_logic;\r
- signal rcount_w8: std_logic;\r
- signal r_g2b_xor_cluster_0: std_logic;\r
- signal wcount_8: std_logic;\r
- signal wcount_9: std_logic;\r
- signal co4_3: std_logic;\r
- signal rcount_w10: std_logic;\r
- signal rcount_w11: std_logic;\r
- signal wcount_10: std_logic;\r
- signal wcount_11: std_logic;\r
- signal co5_3: std_logic;\r
- signal full_cmp_clr: std_logic;\r
- signal full_cmp_set: std_logic;\r
- signal full_d: std_logic;\r
- signal full_d_c: std_logic;\r
- signal scuba_vlo: std_logic;\r
-\r
- -- local component declarations\r
- component AGEB2\r
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic; \r
- B1: in std_logic; CI: in std_logic; GE: out std_logic);\r
- end component;\r
- component AND2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component CU2\r
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; \r
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);\r
- end component;\r
- component FADD2B\r
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic; \r
- B1: in std_logic; CI: in std_logic; COUT: out std_logic; \r
- S0: out std_logic; S1: out std_logic);\r
- end component;\r
- component FD1P3BX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; SP: in std_logic; CK: in std_logic; \r
- PD: in std_logic; Q: out std_logic);\r
- end component;\r
- component FD1P3DX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; SP: in std_logic; CK: in std_logic; \r
- CD: in std_logic; Q: out std_logic);\r
- end component;\r
- component FD1S3BX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; CK: in std_logic; PD: in std_logic; \r
- Q: out std_logic);\r
- end component;\r
- component FD1S3DX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; CK: in std_logic; CD: in std_logic; \r
- Q: out std_logic);\r
- end component;\r
- component INV\r
- port (A: in std_logic; Z: out std_logic);\r
- end component;\r
- component OR2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component ROM16X1\r
- -- synopsys translate_off\r
- generic (initval : in String);\r
- -- synopsys translate_on\r
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; \r
- AD0: in std_logic; DO0: out std_logic);\r
- end component;\r
- component VHI\r
- port (Z: out std_logic);\r
- end component;\r
- component VLO\r
- port (Z: out std_logic);\r
- end component;\r
- component XOR2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component DP16KB\r
- -- synopsys translate_off\r
- generic (GSR : in String; WRITEMODE_B : in String; \r
- CSDECODE_B : in std_logic_vector(2 downto 0); \r
- CSDECODE_A : in std_logic_vector(2 downto 0); \r
- WRITEMODE_A : in String; RESETMODE : in String; \r
- REGMODE_B : in String; REGMODE_A : in String; \r
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);\r
- -- synopsys translate_on\r
- port (DIA0: in std_logic; DIA1: in std_logic; \r
- DIA2: in std_logic; DIA3: in std_logic; \r
- DIA4: in std_logic; DIA5: in std_logic; \r
- DIA6: in std_logic; DIA7: in std_logic; \r
- DIA8: in std_logic; DIA9: in std_logic; \r
- DIA10: in std_logic; DIA11: in std_logic; \r
- DIA12: in std_logic; DIA13: in std_logic; \r
- DIA14: in std_logic; DIA15: in std_logic; \r
- DIA16: in std_logic; DIA17: in std_logic; \r
- ADA0: in std_logic; ADA1: in std_logic; \r
- ADA2: in std_logic; ADA3: in std_logic; \r
- ADA4: in std_logic; ADA5: in std_logic; \r
- ADA6: in std_logic; ADA7: in std_logic; \r
- ADA8: in std_logic; ADA9: in std_logic; \r
- ADA10: in std_logic; ADA11: in std_logic; \r
- ADA12: in std_logic; ADA13: in std_logic; \r
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; \r
- CSA0: in std_logic; CSA1: in std_logic; \r
- CSA2: in std_logic; RSTA: in std_logic; \r
- DIB0: in std_logic; DIB1: in std_logic; \r
- DIB2: in std_logic; DIB3: in std_logic; \r
- DIB4: in std_logic; DIB5: in std_logic; \r
- DIB6: in std_logic; DIB7: in std_logic; \r
- DIB8: in std_logic; DIB9: in std_logic; \r
- DIB10: in std_logic; DIB11: in std_logic; \r
- DIB12: in std_logic; DIB13: in std_logic; \r
- DIB14: in std_logic; DIB15: in std_logic; \r
- DIB16: in std_logic; DIB17: in std_logic; \r
- ADB0: in std_logic; ADB1: in std_logic; \r
- ADB2: in std_logic; ADB3: in std_logic; \r
- ADB4: in std_logic; ADB5: in std_logic; \r
- ADB6: in std_logic; ADB7: in std_logic; \r
- ADB8: in std_logic; ADB9: in std_logic; \r
- ADB10: in std_logic; ADB11: in std_logic; \r
- ADB12: in std_logic; ADB13: in std_logic; \r
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; \r
- CSB0: in std_logic; CSB1: in std_logic; \r
- CSB2: in std_logic; RSTB: in std_logic; \r
- DOA0: out std_logic; DOA1: out std_logic; \r
- DOA2: out std_logic; DOA3: out std_logic; \r
- DOA4: out std_logic; DOA5: out std_logic; \r
- DOA6: out std_logic; DOA7: out std_logic; \r
- DOA8: out std_logic; DOA9: out std_logic; \r
- DOA10: out std_logic; DOA11: out std_logic; \r
- DOA12: out std_logic; DOA13: out std_logic; \r
- DOA14: out std_logic; DOA15: out std_logic; \r
- DOA16: out std_logic; DOA17: out std_logic; \r
- DOB0: out std_logic; DOB1: out std_logic; \r
- DOB2: out std_logic; DOB3: out std_logic; \r
- DOB4: out std_logic; DOB5: out std_logic; \r
- DOB6: out std_logic; DOB7: out std_logic; \r
- DOB8: out std_logic; DOB9: out std_logic; \r
- DOB10: out std_logic; DOB11: out std_logic; \r
- DOB12: out std_logic; DOB13: out std_logic; \r
- DOB14: out std_logic; DOB15: out std_logic; \r
- DOB16: out std_logic; DOB17: out std_logic);\r
- end component;\r
- attribute initval : string; \r
- attribute MEM_LPC_FILE : string; \r
- attribute MEM_INIT_FILE : string; \r
- attribute CSDECODE_B : string; \r
- attribute CSDECODE_A : string; \r
- attribute WRITEMODE_B : string; \r
- attribute WRITEMODE_A : string; \r
- attribute RESETMODE : string; \r
- attribute REGMODE_B : string; \r
- attribute REGMODE_A : string; \r
- attribute DATA_WIDTH_B : string; \r
- attribute DATA_WIDTH_A : string; \r
- attribute GSR : string; \r
- attribute initval of LUT4_33 : label is "0x6996";\r
- attribute initval of LUT4_32 : label is "0x6996";\r
- attribute initval of LUT4_31 : label is "0x6996";\r
- attribute initval of LUT4_30 : label is "0x6996";\r
- attribute initval of LUT4_29 : label is "0x6996";\r
- attribute initval of LUT4_28 : label is "0x6996";\r
- attribute initval of LUT4_27 : label is "0x6996";\r
- attribute initval of LUT4_26 : label is "0x6996";\r
- attribute initval of LUT4_25 : label is "0x6996";\r
- attribute initval of LUT4_24 : label is "0x6996";\r
- attribute initval of LUT4_23 : label is "0x6996";\r
- attribute initval of LUT4_22 : label is "0x6996";\r
- attribute initval of LUT4_21 : label is "0x6996";\r
- attribute initval of LUT4_20 : label is "0x6996";\r
- attribute initval of LUT4_19 : label is "0x6996";\r
- attribute initval of LUT4_18 : label is "0x6996";\r
- attribute initval of LUT4_17 : label is "0x6996";\r
- attribute initval of LUT4_16 : label is "0x6996";\r
- attribute initval of LUT4_15 : label is "0x6996";\r
- attribute initval of LUT4_14 : label is "0x6996";\r
- attribute initval of LUT4_13 : label is "0x6996";\r
- attribute initval of LUT4_12 : label is "0x6996";\r
- attribute initval of LUT4_11 : label is "0x6996";\r
- attribute initval of LUT4_10 : label is "0x6996";\r
- attribute initval of LUT4_9 : label is "0x6996";\r
- attribute initval of LUT4_8 : label is "0x6996";\r
- attribute initval of LUT4_7 : label is "0x6996";\r
- attribute initval of LUT4_6 : label is "0x6996";\r
- attribute initval of LUT4_5 : label is "0x6996";\r
- attribute initval of LUT4_4 : label is "0x6996";\r
- attribute initval of LUT4_3 : label is "0x0410";\r
- attribute initval of LUT4_2 : label is "0x1004";\r
- attribute initval of LUT4_1 : label is "0x0140";\r
- attribute initval of LUT4_0 : label is "0x4001";\r
- attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_0_7 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "4";\r
- attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "4";\r
- attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_1_6 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "4";\r
- attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "4";\r
- attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_2_5 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "4";\r
- attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "4";\r
- attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_3_4 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "4";\r
- attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "4";\r
- attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_4_3 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "4";\r
- attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "4";\r
- attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_5_2 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "4";\r
- attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "4";\r
- attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_6_1 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "4";\r
- attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "4";\r
- attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_7_0 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "4";\r
- attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "4";\r
- attribute GSR of FF_131 : label is "ENABLED";\r
- attribute GSR of FF_130 : label is "ENABLED";\r
- attribute GSR of FF_129 : label is "ENABLED";\r
- attribute GSR of FF_128 : label is "ENABLED";\r
- attribute GSR of FF_127 : label is "ENABLED";\r
- attribute GSR of FF_126 : label is "ENABLED";\r
- attribute GSR of FF_125 : label is "ENABLED";\r
- attribute GSR of FF_124 : label is "ENABLED";\r
- attribute GSR of FF_123 : label is "ENABLED";\r
- attribute GSR of FF_122 : label is "ENABLED";\r
- attribute GSR of FF_121 : label is "ENABLED";\r
- attribute GSR of FF_120 : label is "ENABLED";\r
- attribute GSR of FF_119 : label is "ENABLED";\r
- attribute GSR of FF_118 : label is "ENABLED";\r
- attribute GSR of FF_117 : label is "ENABLED";\r
- attribute GSR of FF_116 : label is "ENABLED";\r
- attribute GSR of FF_115 : label is "ENABLED";\r
- attribute GSR of FF_114 : label is "ENABLED";\r
- attribute GSR of FF_113 : label is "ENABLED";\r
- attribute GSR of FF_112 : label is "ENABLED";\r
- attribute GSR of FF_111 : label is "ENABLED";\r
- attribute GSR of FF_110 : label is "ENABLED";\r
- attribute GSR of FF_109 : label is "ENABLED";\r
- attribute GSR of FF_108 : label is "ENABLED";\r
- attribute GSR of FF_107 : label is "ENABLED";\r
- attribute GSR of FF_106 : label is "ENABLED";\r
- attribute GSR of FF_105 : label is "ENABLED";\r
- attribute GSR of FF_104 : label is "ENABLED";\r
- attribute GSR of FF_103 : label is "ENABLED";\r
- attribute GSR of FF_102 : label is "ENABLED";\r
- attribute GSR of FF_101 : label is "ENABLED";\r
- attribute GSR of FF_100 : label is "ENABLED";\r
- attribute GSR of FF_99 : label is "ENABLED";\r
- attribute GSR of FF_98 : label is "ENABLED";\r
- attribute GSR of FF_97 : label is "ENABLED";\r
- attribute GSR of FF_96 : label is "ENABLED";\r
- attribute GSR of FF_95 : label is "ENABLED";\r
- attribute GSR of FF_94 : label is "ENABLED";\r
- attribute GSR of FF_93 : label is "ENABLED";\r
- attribute GSR of FF_92 : label is "ENABLED";\r
- attribute GSR of FF_91 : label is "ENABLED";\r
- attribute GSR of FF_90 : label is "ENABLED";\r
- attribute GSR of FF_89 : label is "ENABLED";\r
- attribute GSR of FF_88 : label is "ENABLED";\r
- attribute GSR of FF_87 : label is "ENABLED";\r
- attribute GSR of FF_86 : label is "ENABLED";\r
- attribute GSR of FF_85 : label is "ENABLED";\r
- attribute GSR of FF_84 : label is "ENABLED";\r
- attribute GSR of FF_83 : label is "ENABLED";\r
- attribute GSR of FF_82 : label is "ENABLED";\r
- attribute GSR of FF_81 : label is "ENABLED";\r
- attribute GSR of FF_80 : label is "ENABLED";\r
- attribute GSR of FF_79 : label is "ENABLED";\r
- attribute GSR of FF_78 : label is "ENABLED";\r
- attribute GSR of FF_77 : label is "ENABLED";\r
- attribute GSR of FF_76 : label is "ENABLED";\r
- attribute GSR of FF_75 : label is "ENABLED";\r
- attribute GSR of FF_74 : label is "ENABLED";\r
- attribute GSR of FF_73 : label is "ENABLED";\r
- attribute GSR of FF_72 : label is "ENABLED";\r
- attribute GSR of FF_71 : label is "ENABLED";\r
- attribute GSR of FF_70 : label is "ENABLED";\r
- attribute GSR of FF_69 : label is "ENABLED";\r
- attribute GSR of FF_68 : label is "ENABLED";\r
- attribute GSR of FF_67 : label is "ENABLED";\r
- attribute GSR of FF_66 : label is "ENABLED";\r
- attribute GSR of FF_65 : label is "ENABLED";\r
- attribute GSR of FF_64 : label is "ENABLED";\r
- attribute GSR of FF_63 : label is "ENABLED";\r
- attribute GSR of FF_62 : label is "ENABLED";\r
- attribute GSR of FF_61 : label is "ENABLED";\r
- attribute GSR of FF_60 : label is "ENABLED";\r
- attribute GSR of FF_59 : label is "ENABLED";\r
- attribute GSR of FF_58 : label is "ENABLED";\r
- attribute GSR of FF_57 : label is "ENABLED";\r
- attribute GSR of FF_56 : label is "ENABLED";\r
- attribute GSR of FF_55 : label is "ENABLED";\r
- attribute GSR of FF_54 : label is "ENABLED";\r
- attribute GSR of FF_53 : label is "ENABLED";\r
- attribute GSR of FF_52 : label is "ENABLED";\r
- attribute GSR of FF_51 : label is "ENABLED";\r
- attribute GSR of FF_50 : label is "ENABLED";\r
- attribute GSR of FF_49 : label is "ENABLED";\r
- attribute GSR of FF_48 : label is "ENABLED";\r
- attribute GSR of FF_47 : label is "ENABLED";\r
- attribute GSR of FF_46 : label is "ENABLED";\r
- attribute GSR of FF_45 : label is "ENABLED";\r
- attribute GSR of FF_44 : label is "ENABLED";\r
- attribute GSR of FF_43 : label is "ENABLED";\r
- attribute GSR of FF_42 : label is "ENABLED";\r
- attribute GSR of FF_41 : label is "ENABLED";\r
- attribute GSR of FF_40 : label is "ENABLED";\r
- attribute GSR of FF_39 : label is "ENABLED";\r
- attribute GSR of FF_38 : label is "ENABLED";\r
- attribute GSR of FF_37 : label is "ENABLED";\r
- attribute GSR of FF_36 : label is "ENABLED";\r
- attribute GSR of FF_35 : label is "ENABLED";\r
- attribute GSR of FF_34 : label is "ENABLED";\r
- attribute GSR of FF_33 : label is "ENABLED";\r
- attribute GSR of FF_32 : label is "ENABLED";\r
- attribute GSR of FF_31 : label is "ENABLED";\r
- attribute GSR of FF_30 : label is "ENABLED";\r
- attribute GSR of FF_29 : label is "ENABLED";\r
- attribute GSR of FF_28 : label is "ENABLED";\r
- attribute GSR of FF_27 : label is "ENABLED";\r
- attribute GSR of FF_26 : label is "ENABLED";\r
- attribute GSR of FF_25 : label is "ENABLED";\r
- attribute GSR of FF_24 : label is "ENABLED";\r
- attribute GSR of FF_23 : label is "ENABLED";\r
- attribute GSR of FF_22 : label is "ENABLED";\r
- attribute GSR of FF_21 : label is "ENABLED";\r
- attribute GSR of FF_20 : label is "ENABLED";\r
- attribute GSR of FF_19 : label is "ENABLED";\r
- attribute GSR of FF_18 : label is "ENABLED";\r
- attribute GSR of FF_17 : label is "ENABLED";\r
- attribute GSR of FF_16 : label is "ENABLED";\r
- attribute GSR of FF_15 : label is "ENABLED";\r
- attribute GSR of FF_14 : label is "ENABLED";\r
- attribute GSR of FF_13 : label is "ENABLED";\r
- attribute GSR of FF_12 : label is "ENABLED";\r
- attribute GSR of FF_11 : label is "ENABLED";\r
- attribute GSR of FF_10 : label is "ENABLED";\r
- attribute GSR of FF_9 : label is "ENABLED";\r
- attribute GSR of FF_8 : label is "ENABLED";\r
- attribute GSR of FF_7 : label is "ENABLED";\r
- attribute GSR of FF_6 : label is "ENABLED";\r
- attribute GSR of FF_5 : label is "ENABLED";\r
- attribute GSR of FF_4 : label is "ENABLED";\r
- attribute GSR of FF_3 : label is "ENABLED";\r
- attribute GSR of FF_2 : label is "ENABLED";\r
- attribute GSR of FF_1 : label is "ENABLED";\r
- attribute GSR of FF_0 : label is "ENABLED";\r
- attribute syn_keep : boolean;\r
-\r
-begin\r
- -- component instantiation statements\r
- AND2_t26: AND2\r
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);\r
-\r
- INV_1: INV\r
- port map (A=>full_i, Z=>invout_1);\r
-\r
- AND2_t25: AND2\r
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);\r
-\r
- INV_0: INV\r
- port map (A=>empty_i, Z=>invout_0);\r
-\r
- OR2_t24: OR2\r
- port map (A=>Reset, B=>RPReset, Z=>rRst);\r
-\r
- XOR2_t23: XOR2\r
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);\r
-\r
- XOR2_t22: XOR2\r
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);\r
-\r
- XOR2_t21: XOR2\r
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);\r
-\r
- XOR2_t20: XOR2\r
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);\r
-\r
- XOR2_t19: XOR2\r
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);\r
-\r
- XOR2_t18: XOR2\r
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);\r
-\r
- XOR2_t17: XOR2\r
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);\r
-\r
- XOR2_t16: XOR2\r
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);\r
-\r
- XOR2_t15: XOR2\r
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);\r
-\r
- XOR2_t14: XOR2\r
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);\r
-\r
- XOR2_t13: XOR2\r
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);\r
-\r
- XOR2_t12: XOR2\r
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);\r
-\r
- XOR2_t11: XOR2\r
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);\r
-\r
- XOR2_t10: XOR2\r
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);\r
-\r
- XOR2_t9: XOR2\r
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);\r
-\r
- XOR2_t8: XOR2\r
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);\r
-\r
- XOR2_t7: XOR2\r
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);\r
-\r
- XOR2_t6: XOR2\r
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);\r
-\r
- XOR2_t5: XOR2\r
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);\r
-\r
- XOR2_t4: XOR2\r
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);\r
-\r
- XOR2_t3: XOR2\r
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);\r
-\r
- XOR2_t2: XOR2\r
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);\r
-\r
- XOR2_t1: XOR2\r
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);\r
-\r
- XOR2_t0: XOR2\r
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);\r
-\r
- LUT4_33: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, \r
- AD1=>w_gcount_r211, AD0=>w_gcount_r212, \r
- DO0=>w_g2b_xor_cluster_0);\r
-\r
- LUT4_32: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, \r
- AD1=>w_gcount_r27, AD0=>w_gcount_r28, \r
- DO0=>w_g2b_xor_cluster_1);\r
-\r
- LUT4_31: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, \r
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, \r
- DO0=>w_g2b_xor_cluster_2);\r
-\r
- LUT4_30: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>wcount_r11);\r
-\r
- LUT4_29: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, \r
- AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);\r
-\r
- LUT4_28: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, \r
- AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);\r
-\r
- LUT4_27: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, \r
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);\r
-\r
- LUT4_26: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, \r
- AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);\r
-\r
- LUT4_25: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);\r
-\r
- LUT4_24: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);\r
-\r
- LUT4_23: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);\r
-\r
- LUT4_22: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, \r
- AD1=>w_gcount_r24, AD0=>scuba_vlo, \r
- DO0=>w_g2b_xor_cluster_2_1);\r
-\r
- LUT4_21: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);\r
-\r
- LUT4_20: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);\r
-\r
- LUT4_19: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);\r
-\r
- LUT4_18: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, \r
- AD1=>r_gcount_w211, AD0=>r_gcount_w212, \r
- DO0=>r_g2b_xor_cluster_0);\r
-\r
- LUT4_17: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, \r
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, \r
- DO0=>r_g2b_xor_cluster_1);\r
-\r
- LUT4_16: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, \r
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, \r
- DO0=>r_g2b_xor_cluster_2);\r
-\r
- LUT4_15: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>rcount_w11);\r
-\r
- LUT4_14: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, \r
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);\r
-\r
- LUT4_13: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, \r
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);\r
-\r
- LUT4_12: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, \r
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);\r
-\r
- LUT4_11: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, \r
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);\r
-\r
- LUT4_10: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);\r
-\r
- LUT4_9: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);\r
-\r
- LUT4_8: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);\r
-\r
- LUT4_7: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, \r
- AD1=>r_gcount_w24, AD0=>scuba_vlo, \r
- DO0=>r_g2b_xor_cluster_2_1);\r
-\r
- LUT4_6: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);\r
-\r
- LUT4_5: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);\r
-\r
- LUT4_4: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);\r
-\r
- LUT4_3: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x0410")\r
- -- synopsys translate_on\r
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, \r
- AD0=>scuba_vlo, DO0=>empty_cmp_set);\r
-\r
- LUT4_2: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x1004")\r
- -- synopsys translate_on\r
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, \r
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);\r
-\r
- LUT4_1: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x0140")\r
- -- synopsys translate_on\r
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, \r
- AD0=>scuba_vlo, DO0=>full_cmp_set);\r
-\r
- LUT4_0: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x4001")\r
- -- synopsys translate_on\r
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, \r
- AD0=>scuba_vlo, DO0=>full_cmp_clr);\r
-\r
- pdp_ram_0_0_7: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, \r
- DATA_WIDTH_A=> 4)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), \r
- DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, \r
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, \r
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, \r
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, \r
- ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, \r
- ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, \r
- ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, \r
- ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, \r
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, \r
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, \r
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, \r
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, \r
- DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_0_1_6: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, \r
- DATA_WIDTH_A=> 4)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), \r
- DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, \r
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, \r
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, \r
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, \r
- ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, \r
- ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, \r
- ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, \r
- ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, \r
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, \r
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, \r
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, \r
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, \r
- DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_0_2_5: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, \r
- DATA_WIDTH_A=> 4)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10), \r
- DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, \r
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, \r
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, \r
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, \r
- ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, \r
- ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, \r
- ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, \r
- ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, \r
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, \r
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, \r
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, \r
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, \r
- DOA17=>open, DOB0=>Q(8), DOB1=>Q(9), DOB2=>Q(10), \r
- DOB3=>Q(11), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, \r
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, \r
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, \r
- DOB16=>open, DOB17=>open);\r
-\r
- pdp_ram_0_3_4: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, \r
- DATA_WIDTH_A=> 4)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14), \r
- DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, \r
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, \r
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, \r
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, \r
- ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, \r
- ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, \r
- ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, \r
- ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, \r
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, \r
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, \r
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, \r
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, \r
- DOA17=>open, DOB0=>Q(12), DOB1=>Q(13), DOB2=>Q(14), \r
- DOB3=>Q(15), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, \r
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, \r
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, \r
- DOB16=>open, DOB17=>open);\r
-\r
- pdp_ram_0_4_3: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, \r
- DATA_WIDTH_A=> 4)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18), \r
- DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, \r
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, \r
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, \r
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, \r
- ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, \r
- ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, \r
- ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, \r
- ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, \r
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, \r
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, \r
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, \r
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, \r
- DOA17=>open, DOB0=>Q(16), DOB1=>Q(17), DOB2=>Q(18), \r
- DOB3=>Q(19), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, \r
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, \r
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, \r
- DOB16=>open, DOB17=>open);\r
-\r
- pdp_ram_0_5_2: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, \r
- DATA_WIDTH_A=> 4)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22), \r
- DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, \r
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, \r
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, \r
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, \r
- ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, \r
- ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, \r
- ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, \r
- ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, \r
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, \r
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, \r
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, \r
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, \r
- DOA17=>open, DOB0=>Q(20), DOB1=>Q(21), DOB2=>Q(22), \r
- DOB3=>Q(23), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, \r
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, \r
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, \r
- DOB16=>open, DOB17=>open);\r
-\r
- pdp_ram_0_6_1: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, \r
- DATA_WIDTH_A=> 4)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26), \r
- DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, \r
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, \r
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, \r
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, \r
- ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, \r
- ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, \r
- ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, \r
- ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, \r
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, \r
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, \r
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, \r
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, \r
- DOA17=>open, DOB0=>Q(24), DOB1=>Q(25), DOB2=>Q(26), \r
- DOB3=>Q(27), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, \r
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, \r
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, \r
- DOB16=>open, DOB17=>open);\r
-\r
- pdp_ram_0_7_0: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, \r
- DATA_WIDTH_A=> 4)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30), \r
- DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, \r
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, \r
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, \r
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, \r
- ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, \r
- ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, \r
- ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, \r
- ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, \r
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, \r
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, \r
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, \r
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, \r
- DOA17=>open, DOB0=>Q(28), DOB1=>Q(29), DOB2=>Q(30), \r
- DOB3=>Q(31), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, \r
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, \r
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, \r
- DOB16=>open, DOB17=>open);\r
-\r
- FF_131: FD1P3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, \r
- Q=>wcount_0);\r
-\r
- FF_130: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_1);\r
-\r
- FF_129: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_2);\r
-\r
- FF_128: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_3);\r
-\r
- FF_127: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_4);\r
-\r
- FF_126: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_5);\r
-\r
- FF_125: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_6);\r
-\r
- FF_124: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_7);\r
-\r
- FF_123: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_8);\r
-\r
- FF_122: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_9);\r
-\r
- FF_121: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_10);\r
-\r
- FF_120: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_11);\r
-\r
- FF_119: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_12);\r
-\r
- FF_118: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_0);\r
-\r
- FF_117: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_1);\r
-\r
- FF_116: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_2);\r
-\r
- FF_115: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_3);\r
-\r
- FF_114: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_4);\r
-\r
- FF_113: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_5);\r
-\r
- FF_112: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_6);\r
-\r
- FF_111: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_7);\r
-\r
- FF_110: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_8);\r
-\r
- FF_109: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_9);\r
-\r
- FF_108: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_10);\r
-\r
- FF_107: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_11);\r
-\r
- FF_106: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_12);\r
-\r
- FF_105: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_0);\r
-\r
- FF_104: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_1);\r
-\r
- FF_103: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_2);\r
-\r
- FF_102: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_3);\r
-\r
- FF_101: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_4);\r
-\r
- FF_100: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_5);\r
-\r
- FF_99: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_6);\r
-\r
- FF_98: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_7);\r
-\r
- FF_97: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_8);\r
-\r
- FF_96: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_9);\r
-\r
- FF_95: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_10);\r
-\r
- FF_94: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_11);\r
-\r
- FF_93: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_12);\r
-\r
- FF_92: FD1P3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, \r
- Q=>rcount_0);\r
-\r
- FF_91: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_1);\r
-\r
- FF_90: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_2);\r
-\r
- FF_89: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_3);\r
-\r
- FF_88: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_4);\r
-\r
- FF_87: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_5);\r
-\r
- FF_86: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_6);\r
-\r
- FF_85: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_7);\r
-\r
- FF_84: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_8);\r
-\r
- FF_83: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_9);\r
-\r
- FF_82: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_10);\r
-\r
- FF_81: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_11);\r
-\r
- FF_80: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_12);\r
-\r
- FF_79: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_0);\r
-\r
- FF_78: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_1);\r
-\r
- FF_77: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_2);\r
-\r
- FF_76: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_3);\r
-\r
- FF_75: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_4);\r
-\r
- FF_74: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_5);\r
-\r
- FF_73: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_6);\r
-\r
- FF_72: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_7);\r
-\r
- FF_71: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_8);\r
-\r
- FF_70: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_9);\r
-\r
- FF_69: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_10);\r
-\r
- FF_68: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_11);\r
-\r
- FF_67: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_12);\r
-\r
- FF_66: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_0);\r
-\r
- FF_65: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_1);\r
-\r
- FF_64: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_2);\r
-\r
- FF_63: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_3);\r
-\r
- FF_62: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_4);\r
-\r
- FF_61: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_5);\r
-\r
- FF_60: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_6);\r
-\r
- FF_59: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_7);\r
-\r
- FF_58: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_8);\r
-\r
- FF_57: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_9);\r
-\r
- FF_56: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_10);\r
-\r
- FF_55: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_11);\r
-\r
- FF_54: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_12);\r
-\r
- FF_53: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);\r
-\r
- FF_52: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);\r
-\r
- FF_51: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);\r
-\r
- FF_50: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);\r
-\r
- FF_49: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);\r
-\r
- FF_48: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);\r
-\r
- FF_47: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);\r
-\r
- FF_46: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);\r
-\r
- FF_45: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);\r
-\r
- FF_44: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);\r
-\r
- FF_43: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r10);\r
-\r
- FF_42: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r11);\r
-\r
- FF_41: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r12);\r
-\r
- FF_40: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);\r
-\r
- FF_39: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);\r
-\r
- FF_38: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);\r
-\r
- FF_37: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);\r
-\r
- FF_36: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);\r
-\r
- FF_35: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);\r
-\r
- FF_34: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);\r
-\r
- FF_33: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);\r
-\r
- FF_32: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);\r
-\r
- FF_31: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);\r
-\r
- FF_30: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);\r
-\r
- FF_29: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);\r
-\r
- FF_28: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);\r
-\r
- FF_27: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r20);\r
-\r
- FF_26: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r21);\r
-\r
- FF_25: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r22);\r
-\r
- FF_24: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r23);\r
-\r
- FF_23: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r24);\r
-\r
- FF_22: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r25);\r
-\r
- FF_21: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r26);\r
-\r
- FF_20: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r27);\r
-\r
- FF_19: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r28);\r
-\r
- FF_18: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r29);\r
-\r
- FF_17: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r210);\r
-\r
- FF_16: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r211);\r
-\r
- FF_15: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r212);\r
-\r
- FF_14: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);\r
-\r
- FF_13: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);\r
-\r
- FF_12: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);\r
-\r
- FF_11: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);\r
-\r
- FF_10: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);\r
-\r
- FF_9: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);\r
-\r
- FF_8: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);\r
-\r
- FF_7: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);\r
-\r
- FF_6: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);\r
-\r
- FF_5: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);\r
-\r
- FF_4: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w210);\r
-\r
- FF_3: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w211);\r
-\r
- FF_2: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w212);\r
-\r
- FF_1: FD1S3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);\r
-\r
- FF_0: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);\r
-\r
- w_gctr_cia: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, \r
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, \r
- S1=>open);\r
-\r
- w_gctr_0: CU2\r
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, \r
- NC0=>iwcount_0, NC1=>iwcount_1);\r
-\r
- w_gctr_1: CU2\r
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, \r
- NC0=>iwcount_2, NC1=>iwcount_3);\r
-\r
- w_gctr_2: CU2\r
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, \r
- NC0=>iwcount_4, NC1=>iwcount_5);\r
-\r
- w_gctr_3: CU2\r
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, \r
- NC0=>iwcount_6, NC1=>iwcount_7);\r
-\r
- w_gctr_4: CU2\r
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, \r
- NC0=>iwcount_8, NC1=>iwcount_9);\r
-\r
- w_gctr_5: CU2\r
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, \r
- NC0=>iwcount_10, NC1=>iwcount_11);\r
-\r
- w_gctr_6: CU2\r
- port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, \r
- NC0=>iwcount_12, NC1=>open);\r
-\r
- scuba_vhi_inst: VHI\r
- port map (Z=>scuba_vhi);\r
-\r
- r_gctr_cia: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, \r
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, \r
- S1=>open);\r
-\r
- r_gctr_0: CU2\r
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, \r
- NC0=>ircount_0, NC1=>ircount_1);\r
-\r
- r_gctr_1: CU2\r
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, \r
- NC0=>ircount_2, NC1=>ircount_3);\r
-\r
- r_gctr_2: CU2\r
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, \r
- NC0=>ircount_4, NC1=>ircount_5);\r
-\r
- r_gctr_3: CU2\r
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, \r
- NC0=>ircount_6, NC1=>ircount_7);\r
-\r
- r_gctr_4: CU2\r
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, \r
- NC0=>ircount_8, NC1=>ircount_9);\r
-\r
- r_gctr_5: CU2\r
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, \r
- NC0=>ircount_10, NC1=>ircount_11);\r
-\r
- r_gctr_6: CU2\r
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, \r
- NC0=>ircount_12, NC1=>open);\r
-\r
- empty_cmp_ci_a: FADD2B\r
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, \r
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);\r
-\r
- empty_cmp_0: AGEB2\r
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, \r
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);\r
-\r
- empty_cmp_1: AGEB2\r
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, \r
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);\r
-\r
- empty_cmp_2: AGEB2\r
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, \r
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);\r
-\r
- empty_cmp_3: AGEB2\r
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, \r
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);\r
-\r
- empty_cmp_4: AGEB2\r
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, \r
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);\r
-\r
- empty_cmp_5: AGEB2\r
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, \r
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);\r
-\r
- empty_cmp_6: AGEB2\r
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, \r
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);\r
-\r
- a0: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, \r
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, \r
- S1=>open);\r
-\r
- full_cmp_ci_a: FADD2B\r
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, \r
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);\r
-\r
- full_cmp_0: AGEB2\r
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, \r
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);\r
-\r
- full_cmp_1: AGEB2\r
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, \r
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);\r
-\r
- full_cmp_2: AGEB2\r
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, \r
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);\r
-\r
- full_cmp_3: AGEB2\r
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, \r
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);\r
-\r
- full_cmp_4: AGEB2\r
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, \r
- B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);\r
-\r
- full_cmp_5: AGEB2\r
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, \r
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);\r
-\r
- full_cmp_6: AGEB2\r
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, \r
- B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c);\r
-\r
- scuba_vlo_inst: VLO\r
- port map (Z=>scuba_vlo);\r
-\r
- a1: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, \r
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, \r
- S1=>open);\r
-\r
- Empty <= empty_i;\r
- Full <= full_i;\r
-end Structure;\r
-\r
--- synopsys translate_off\r
-library ecp2m;\r
-configuration Structure_CON of fifo_4096x32 is\r
- for Structure\r
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;\r
- for all:AND2 use entity ecp2m.AND2(V); end for;\r
- for all:CU2 use entity ecp2m.CU2(V); end for;\r
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;\r
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;\r
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;\r
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;\r
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;\r
- for all:INV use entity ecp2m.INV(V); end for;\r
- for all:OR2 use entity ecp2m.OR2(V); end for;\r
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;\r
- for all:VHI use entity ecp2m.VHI(V); end for;\r
- for all:VLO use entity ecp2m.VLO(V); end for;\r
- for all:XOR2 use entity ecp2m.XOR2(V); end for;\r
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;\r
- end for;\r
-end Structure_CON;\r
-\r
--- synopsys translate_on\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41)\r
--- Module Version: 5.3\r
--- Fri Dec 18 03:02:30 2009\r
-\r
--- parameterized module component declaration\r
-component fifo_4096x32\r
- port (Data: in std_logic_vector(31 downto 0); \r
- WrClock: in std_logic; RdClock: in std_logic; \r
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; \r
- RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); \r
- Empty: out std_logic; Full: out std_logic);\r
-end component;\r
-\r
--- parameterized module component instance\r
-__ : fifo_4096x32\r
- port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, \r
- RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, \r
- Full=>__);\r
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-5F900C\r
-SpeedGrade=-5\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=FIFO_DC\r
-CoreRevision=5.2\r
-ModuleName=fifo_4096x9\r
-SourceFormat=Schematic/VHDL\r
-ParameterFileVersion=1.0\r
-Date=01/05/2010\r
-Time=23:44:15\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-FIFOImp=EBR Based\r
-Depth=4096\r
-Width=9\r
-RDepth=4096\r
-RWidth=9\r
-regout=0\r
-CtrlByRdEn=0\r
-EmpFlg=0\r
-PeMode=Static - Dual Threshold\r
-PeAssert=10\r
-PeDeassert=12\r
-FullFlg=0\r
-PfMode=Static - Dual Threshold\r
-PfAssert=508\r
-PfDeassert=506\r
-RDataCount=0\r
-WDataCount=0\r
-EnECC=0\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)\r
--- Module Version: 5.2\r
---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e \r
-\r
--- Tue Jan 5 23:44:15 2010\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
--- synopsys translate_off\r
-library ecp2m;\r
-use ecp2m.components.all;\r
--- synopsys translate_on\r
-\r
-entity fifo_4096x9 is\r
- port (\r
- Data: in std_logic_vector(8 downto 0); \r
- WrClock: in std_logic; \r
- RdClock: in std_logic; \r
- WrEn: in std_logic; \r
- RdEn: in std_logic; \r
- Reset: in std_logic; \r
- RPReset: in std_logic; \r
- Q: out std_logic_vector(8 downto 0); \r
- Empty: out std_logic; \r
- Full: out std_logic);\r
-end fifo_4096x9;\r
-\r
-architecture Structure of fifo_4096x9 is\r
-\r
- -- internal signal declarations\r
- signal invout_1: std_logic;\r
- signal invout_0: std_logic;\r
- signal w_g2b_xor_cluster_2_1: std_logic;\r
- signal w_g2b_xor_cluster_2: std_logic;\r
- signal w_g2b_xor_cluster_1: std_logic;\r
- signal r_g2b_xor_cluster_2_1: std_logic;\r
- signal r_g2b_xor_cluster_2: std_logic;\r
- signal r_g2b_xor_cluster_1: std_logic;\r
- signal w_gdata_0: std_logic;\r
- signal w_gdata_1: std_logic;\r
- signal w_gdata_2: std_logic;\r
- signal w_gdata_3: std_logic;\r
- signal w_gdata_4: std_logic;\r
- signal w_gdata_5: std_logic;\r
- signal w_gdata_6: std_logic;\r
- signal w_gdata_7: std_logic;\r
- signal w_gdata_8: std_logic;\r
- signal w_gdata_9: std_logic;\r
- signal w_gdata_10: std_logic;\r
- signal w_gdata_11: std_logic;\r
- signal wptr_0: std_logic;\r
- signal wptr_1: std_logic;\r
- signal wptr_2: std_logic;\r
- signal wptr_3: std_logic;\r
- signal wptr_4: std_logic;\r
- signal wptr_5: std_logic;\r
- signal wptr_6: std_logic;\r
- signal wptr_7: std_logic;\r
- signal wptr_8: std_logic;\r
- signal wptr_9: std_logic;\r
- signal wptr_10: std_logic;\r
- signal wptr_11: std_logic;\r
- signal wptr_12: std_logic;\r
- signal r_gdata_0: std_logic;\r
- signal r_gdata_1: std_logic;\r
- signal r_gdata_2: std_logic;\r
- signal r_gdata_3: std_logic;\r
- signal r_gdata_4: std_logic;\r
- signal r_gdata_5: std_logic;\r
- signal r_gdata_6: std_logic;\r
- signal r_gdata_7: std_logic;\r
- signal r_gdata_8: std_logic;\r
- signal r_gdata_9: std_logic;\r
- signal r_gdata_10: std_logic;\r
- signal r_gdata_11: std_logic;\r
- signal rptr_0: std_logic;\r
- signal rptr_1: std_logic;\r
- signal rptr_2: std_logic;\r
- signal rptr_3: std_logic;\r
- signal rptr_4: std_logic;\r
- signal rptr_5: std_logic;\r
- signal rptr_6: std_logic;\r
- signal rptr_7: std_logic;\r
- signal rptr_8: std_logic;\r
- signal rptr_9: std_logic;\r
- signal rptr_10: std_logic;\r
- signal rptr_12: std_logic;\r
- signal rptr_11: std_logic;\r
- signal w_gcount_0: std_logic;\r
- signal w_gcount_1: std_logic;\r
- signal w_gcount_2: std_logic;\r
- signal w_gcount_3: std_logic;\r
- signal w_gcount_4: std_logic;\r
- signal w_gcount_5: std_logic;\r
- signal w_gcount_6: std_logic;\r
- signal w_gcount_7: std_logic;\r
- signal w_gcount_8: std_logic;\r
- signal w_gcount_9: std_logic;\r
- signal w_gcount_10: std_logic;\r
- signal w_gcount_11: std_logic;\r
- signal w_gcount_12: std_logic;\r
- signal r_gcount_0: std_logic;\r
- signal r_gcount_1: std_logic;\r
- signal r_gcount_2: std_logic;\r
- signal r_gcount_3: std_logic;\r
- signal r_gcount_4: std_logic;\r
- signal r_gcount_5: std_logic;\r
- signal r_gcount_6: std_logic;\r
- signal r_gcount_7: std_logic;\r
- signal r_gcount_8: std_logic;\r
- signal r_gcount_9: std_logic;\r
- signal r_gcount_10: std_logic;\r
- signal r_gcount_11: std_logic;\r
- signal r_gcount_12: std_logic;\r
- signal w_gcount_r20: std_logic;\r
- signal w_gcount_r0: std_logic;\r
- signal w_gcount_r21: std_logic;\r
- signal w_gcount_r1: std_logic;\r
- signal w_gcount_r22: std_logic;\r
- signal w_gcount_r2: std_logic;\r
- signal w_gcount_r23: std_logic;\r
- signal w_gcount_r3: std_logic;\r
- signal w_gcount_r24: std_logic;\r
- signal w_gcount_r4: std_logic;\r
- signal w_gcount_r25: std_logic;\r
- signal w_gcount_r5: std_logic;\r
- signal w_gcount_r26: std_logic;\r
- signal w_gcount_r6: std_logic;\r
- signal w_gcount_r27: std_logic;\r
- signal w_gcount_r7: std_logic;\r
- signal w_gcount_r28: std_logic;\r
- signal w_gcount_r8: std_logic;\r
- signal w_gcount_r29: std_logic;\r
- signal w_gcount_r9: std_logic;\r
- signal w_gcount_r210: std_logic;\r
- signal w_gcount_r10: std_logic;\r
- signal w_gcount_r211: std_logic;\r
- signal w_gcount_r11: std_logic;\r
- signal w_gcount_r212: std_logic;\r
- signal w_gcount_r12: std_logic;\r
- signal r_gcount_w20: std_logic;\r
- signal r_gcount_w0: std_logic;\r
- signal r_gcount_w21: std_logic;\r
- signal r_gcount_w1: std_logic;\r
- signal r_gcount_w22: std_logic;\r
- signal r_gcount_w2: std_logic;\r
- signal r_gcount_w23: std_logic;\r
- signal r_gcount_w3: std_logic;\r
- signal r_gcount_w24: std_logic;\r
- signal r_gcount_w4: std_logic;\r
- signal r_gcount_w25: std_logic;\r
- signal r_gcount_w5: std_logic;\r
- signal r_gcount_w26: std_logic;\r
- signal r_gcount_w6: std_logic;\r
- signal r_gcount_w27: std_logic;\r
- signal r_gcount_w7: std_logic;\r
- signal r_gcount_w28: std_logic;\r
- signal r_gcount_w8: std_logic;\r
- signal r_gcount_w29: std_logic;\r
- signal r_gcount_w9: std_logic;\r
- signal r_gcount_w210: std_logic;\r
- signal r_gcount_w10: std_logic;\r
- signal r_gcount_w211: std_logic;\r
- signal r_gcount_w11: std_logic;\r
- signal r_gcount_w212: std_logic;\r
- signal r_gcount_w12: std_logic;\r
- signal empty_i: std_logic;\r
- signal rRst: std_logic;\r
- signal full_i: std_logic;\r
- signal iwcount_0: std_logic;\r
- signal iwcount_1: std_logic;\r
- signal w_gctr_ci: std_logic;\r
- signal iwcount_2: std_logic;\r
- signal iwcount_3: std_logic;\r
- signal co0: std_logic;\r
- signal iwcount_4: std_logic;\r
- signal iwcount_5: std_logic;\r
- signal co1: std_logic;\r
- signal iwcount_6: std_logic;\r
- signal iwcount_7: std_logic;\r
- signal co2: std_logic;\r
- signal iwcount_8: std_logic;\r
- signal iwcount_9: std_logic;\r
- signal co3: std_logic;\r
- signal iwcount_10: std_logic;\r
- signal iwcount_11: std_logic;\r
- signal co4: std_logic;\r
- signal iwcount_12: std_logic;\r
- signal co6: std_logic;\r
- signal wcount_12: std_logic;\r
- signal co5: std_logic;\r
- signal scuba_vhi: std_logic;\r
- signal ircount_0: std_logic;\r
- signal ircount_1: std_logic;\r
- signal r_gctr_ci: std_logic;\r
- signal ircount_2: std_logic;\r
- signal ircount_3: std_logic;\r
- signal co0_1: std_logic;\r
- signal ircount_4: std_logic;\r
- signal ircount_5: std_logic;\r
- signal co1_1: std_logic;\r
- signal ircount_6: std_logic;\r
- signal ircount_7: std_logic;\r
- signal co2_1: std_logic;\r
- signal ircount_8: std_logic;\r
- signal ircount_9: std_logic;\r
- signal co3_1: std_logic;\r
- signal ircount_10: std_logic;\r
- signal ircount_11: std_logic;\r
- signal co4_1: std_logic;\r
- signal ircount_12: std_logic;\r
- signal co6_1: std_logic;\r
- signal rcount_12: std_logic;\r
- signal co5_1: std_logic;\r
- signal mdout1_1_0: std_logic;\r
- signal mdout1_0_0: std_logic;\r
- signal mdout1_1_1: std_logic;\r
- signal mdout1_0_1: std_logic;\r
- signal mdout1_1_2: std_logic;\r
- signal mdout1_0_2: std_logic;\r
- signal mdout1_1_3: std_logic;\r
- signal mdout1_0_3: std_logic;\r
- signal mdout1_1_4: std_logic;\r
- signal mdout1_0_4: std_logic;\r
- signal mdout1_1_5: std_logic;\r
- signal mdout1_0_5: std_logic;\r
- signal mdout1_1_6: std_logic;\r
- signal mdout1_0_6: std_logic;\r
- signal mdout1_1_7: std_logic;\r
- signal mdout1_0_7: std_logic;\r
- signal rptr_11_ff: std_logic;\r
- signal mdout1_1_8: std_logic;\r
- signal mdout1_0_8: std_logic;\r
- signal rden_i: std_logic;\r
- signal cmp_ci: std_logic;\r
- signal wcount_r0: std_logic;\r
- signal wcount_r1: std_logic;\r
- signal rcount_0: std_logic;\r
- signal rcount_1: std_logic;\r
- signal co0_2: std_logic;\r
- signal wcount_r2: std_logic;\r
- signal wcount_r3: std_logic;\r
- signal rcount_2: std_logic;\r
- signal rcount_3: std_logic;\r
- signal co1_2: std_logic;\r
- signal wcount_r4: std_logic;\r
- signal wcount_r5: std_logic;\r
- signal rcount_4: std_logic;\r
- signal rcount_5: std_logic;\r
- signal co2_2: std_logic;\r
- signal wcount_r6: std_logic;\r
- signal wcount_r7: std_logic;\r
- signal rcount_6: std_logic;\r
- signal rcount_7: std_logic;\r
- signal co3_2: std_logic;\r
- signal wcount_r8: std_logic;\r
- signal w_g2b_xor_cluster_0: std_logic;\r
- signal rcount_8: std_logic;\r
- signal rcount_9: std_logic;\r
- signal co4_2: std_logic;\r
- signal wcount_r10: std_logic;\r
- signal wcount_r11: std_logic;\r
- signal rcount_10: std_logic;\r
- signal rcount_11: std_logic;\r
- signal co5_2: std_logic;\r
- signal empty_cmp_clr: std_logic;\r
- signal empty_cmp_set: std_logic;\r
- signal empty_d: std_logic;\r
- signal empty_d_c: std_logic;\r
- signal wren_i: std_logic;\r
- signal cmp_ci_1: std_logic;\r
- signal rcount_w0: std_logic;\r
- signal rcount_w1: std_logic;\r
- signal wcount_0: std_logic;\r
- signal wcount_1: std_logic;\r
- signal co0_3: std_logic;\r
- signal rcount_w2: std_logic;\r
- signal rcount_w3: std_logic;\r
- signal wcount_2: std_logic;\r
- signal wcount_3: std_logic;\r
- signal co1_3: std_logic;\r
- signal rcount_w4: std_logic;\r
- signal rcount_w5: std_logic;\r
- signal wcount_4: std_logic;\r
- signal wcount_5: std_logic;\r
- signal co2_3: std_logic;\r
- signal rcount_w6: std_logic;\r
- signal rcount_w7: std_logic;\r
- signal wcount_6: std_logic;\r
- signal wcount_7: std_logic;\r
- signal co3_3: std_logic;\r
- signal rcount_w8: std_logic;\r
- signal r_g2b_xor_cluster_0: std_logic;\r
- signal wcount_8: std_logic;\r
- signal wcount_9: std_logic;\r
- signal co4_3: std_logic;\r
- signal rcount_w10: std_logic;\r
- signal rcount_w11: std_logic;\r
- signal wcount_10: std_logic;\r
- signal wcount_11: std_logic;\r
- signal co5_3: std_logic;\r
- signal full_cmp_clr: std_logic;\r
- signal full_cmp_set: std_logic;\r
- signal full_d: std_logic;\r
- signal full_d_c: std_logic;\r
- signal scuba_vlo: std_logic;\r
-\r
- -- local component declarations\r
- component AGEB2\r
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic; \r
- B1: in std_logic; CI: in std_logic; GE: out std_logic);\r
- end component;\r
- component AND2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component CU2\r
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; \r
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);\r
- end component;\r
- component FADD2B\r
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic; \r
- B1: in std_logic; CI: in std_logic; COUT: out std_logic; \r
- S0: out std_logic; S1: out std_logic);\r
- end component;\r
- component FD1P3BX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; SP: in std_logic; CK: in std_logic; \r
- PD: in std_logic; Q: out std_logic);\r
- end component;\r
- component FD1P3DX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; SP: in std_logic; CK: in std_logic; \r
- CD: in std_logic; Q: out std_logic);\r
- end component;\r
- component FD1S3BX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; CK: in std_logic; PD: in std_logic; \r
- Q: out std_logic);\r
- end component;\r
- component FD1S3DX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; CK: in std_logic; CD: in std_logic; \r
- Q: out std_logic);\r
- end component;\r
- component INV\r
- port (A: in std_logic; Z: out std_logic);\r
- end component;\r
- component MUX21\r
- port (D0: in std_logic; D1: in std_logic; SD: in std_logic; \r
- Z: out std_logic);\r
- end component;\r
- component OR2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component ROM16X1\r
- -- synopsys translate_off\r
- generic (initval : in String);\r
- -- synopsys translate_on\r
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; \r
- AD0: in std_logic; DO0: out std_logic);\r
- end component;\r
- component VHI\r
- port (Z: out std_logic);\r
- end component;\r
- component VLO\r
- port (Z: out std_logic);\r
- end component;\r
- component XOR2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component DP16KB\r
- -- synopsys translate_off\r
- generic (GSR : in String; WRITEMODE_B : in String; \r
- CSDECODE_B : in std_logic_vector(2 downto 0); \r
- CSDECODE_A : in std_logic_vector(2 downto 0); \r
- WRITEMODE_A : in String; RESETMODE : in String; \r
- REGMODE_B : in String; REGMODE_A : in String; \r
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);\r
- -- synopsys translate_on\r
- port (DIA0: in std_logic; DIA1: in std_logic; \r
- DIA2: in std_logic; DIA3: in std_logic; \r
- DIA4: in std_logic; DIA5: in std_logic; \r
- DIA6: in std_logic; DIA7: in std_logic; \r
- DIA8: in std_logic; DIA9: in std_logic; \r
- DIA10: in std_logic; DIA11: in std_logic; \r
- DIA12: in std_logic; DIA13: in std_logic; \r
- DIA14: in std_logic; DIA15: in std_logic; \r
- DIA16: in std_logic; DIA17: in std_logic; \r
- ADA0: in std_logic; ADA1: in std_logic; \r
- ADA2: in std_logic; ADA3: in std_logic; \r
- ADA4: in std_logic; ADA5: in std_logic; \r
- ADA6: in std_logic; ADA7: in std_logic; \r
- ADA8: in std_logic; ADA9: in std_logic; \r
- ADA10: in std_logic; ADA11: in std_logic; \r
- ADA12: in std_logic; ADA13: in std_logic; \r
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; \r
- CSA0: in std_logic; CSA1: in std_logic; \r
- CSA2: in std_logic; RSTA: in std_logic; \r
- DIB0: in std_logic; DIB1: in std_logic; \r
- DIB2: in std_logic; DIB3: in std_logic; \r
- DIB4: in std_logic; DIB5: in std_logic; \r
- DIB6: in std_logic; DIB7: in std_logic; \r
- DIB8: in std_logic; DIB9: in std_logic; \r
- DIB10: in std_logic; DIB11: in std_logic; \r
- DIB12: in std_logic; DIB13: in std_logic; \r
- DIB14: in std_logic; DIB15: in std_logic; \r
- DIB16: in std_logic; DIB17: in std_logic; \r
- ADB0: in std_logic; ADB1: in std_logic; \r
- ADB2: in std_logic; ADB3: in std_logic; \r
- ADB4: in std_logic; ADB5: in std_logic; \r
- ADB6: in std_logic; ADB7: in std_logic; \r
- ADB8: in std_logic; ADB9: in std_logic; \r
- ADB10: in std_logic; ADB11: in std_logic; \r
- ADB12: in std_logic; ADB13: in std_logic; \r
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; \r
- CSB0: in std_logic; CSB1: in std_logic; \r
- CSB2: in std_logic; RSTB: in std_logic; \r
- DOA0: out std_logic; DOA1: out std_logic; \r
- DOA2: out std_logic; DOA3: out std_logic; \r
- DOA4: out std_logic; DOA5: out std_logic; \r
- DOA6: out std_logic; DOA7: out std_logic; \r
- DOA8: out std_logic; DOA9: out std_logic; \r
- DOA10: out std_logic; DOA11: out std_logic; \r
- DOA12: out std_logic; DOA13: out std_logic; \r
- DOA14: out std_logic; DOA15: out std_logic; \r
- DOA16: out std_logic; DOA17: out std_logic; \r
- DOB0: out std_logic; DOB1: out std_logic; \r
- DOB2: out std_logic; DOB3: out std_logic; \r
- DOB4: out std_logic; DOB5: out std_logic; \r
- DOB6: out std_logic; DOB7: out std_logic; \r
- DOB8: out std_logic; DOB9: out std_logic; \r
- DOB10: out std_logic; DOB11: out std_logic; \r
- DOB12: out std_logic; DOB13: out std_logic; \r
- DOB14: out std_logic; DOB15: out std_logic; \r
- DOB16: out std_logic; DOB17: out std_logic);\r
- end component;\r
- attribute initval : string; \r
- attribute MEM_LPC_FILE : string; \r
- attribute MEM_INIT_FILE : string; \r
- attribute CSDECODE_B : string; \r
- attribute CSDECODE_A : string; \r
- attribute WRITEMODE_B : string; \r
- attribute WRITEMODE_A : string; \r
- attribute RESETMODE : string; \r
- attribute REGMODE_B : string; \r
- attribute REGMODE_A : string; \r
- attribute DATA_WIDTH_B : string; \r
- attribute DATA_WIDTH_A : string; \r
- attribute GSR : string; \r
- attribute initval of LUT4_33 : label is "0x6996";\r
- attribute initval of LUT4_32 : label is "0x6996";\r
- attribute initval of LUT4_31 : label is "0x6996";\r
- attribute initval of LUT4_30 : label is "0x6996";\r
- attribute initval of LUT4_29 : label is "0x6996";\r
- attribute initval of LUT4_28 : label is "0x6996";\r
- attribute initval of LUT4_27 : label is "0x6996";\r
- attribute initval of LUT4_26 : label is "0x6996";\r
- attribute initval of LUT4_25 : label is "0x6996";\r
- attribute initval of LUT4_24 : label is "0x6996";\r
- attribute initval of LUT4_23 : label is "0x6996";\r
- attribute initval of LUT4_22 : label is "0x6996";\r
- attribute initval of LUT4_21 : label is "0x6996";\r
- attribute initval of LUT4_20 : label is "0x6996";\r
- attribute initval of LUT4_19 : label is "0x6996";\r
- attribute initval of LUT4_18 : label is "0x6996";\r
- attribute initval of LUT4_17 : label is "0x6996";\r
- attribute initval of LUT4_16 : label is "0x6996";\r
- attribute initval of LUT4_15 : label is "0x6996";\r
- attribute initval of LUT4_14 : label is "0x6996";\r
- attribute initval of LUT4_13 : label is "0x6996";\r
- attribute initval of LUT4_12 : label is "0x6996";\r
- attribute initval of LUT4_11 : label is "0x6996";\r
- attribute initval of LUT4_10 : label is "0x6996";\r
- attribute initval of LUT4_9 : label is "0x6996";\r
- attribute initval of LUT4_8 : label is "0x6996";\r
- attribute initval of LUT4_7 : label is "0x6996";\r
- attribute initval of LUT4_6 : label is "0x6996";\r
- attribute initval of LUT4_5 : label is "0x6996";\r
- attribute initval of LUT4_4 : label is "0x6996";\r
- attribute initval of LUT4_3 : label is "0x0410";\r
- attribute initval of LUT4_2 : label is "0x1004";\r
- attribute initval of LUT4_1 : label is "0x0140";\r
- attribute initval of LUT4_0 : label is "0x4001";\r
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_0_1 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9";\r
- attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9";\r
- attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is "";\r
- attribute CSDECODE_B of pdp_ram_1_0_0 : label is "0b001";\r
- attribute CSDECODE_A of pdp_ram_1_0_0 : label is "0b001";\r
- attribute WRITEMODE_B of pdp_ram_1_0_0 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_1_0_0 : label is "NORMAL";\r
- attribute GSR of pdp_ram_1_0_0 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_1_0_0 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_1_0_0 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_1_0_0 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_1_0_0 : label is "9";\r
- attribute DATA_WIDTH_A of pdp_ram_1_0_0 : label is "9";\r
- attribute GSR of FF_132 : label is "ENABLED";\r
- attribute GSR of FF_131 : label is "ENABLED";\r
- attribute GSR of FF_130 : label is "ENABLED";\r
- attribute GSR of FF_129 : label is "ENABLED";\r
- attribute GSR of FF_128 : label is "ENABLED";\r
- attribute GSR of FF_127 : label is "ENABLED";\r
- attribute GSR of FF_126 : label is "ENABLED";\r
- attribute GSR of FF_125 : label is "ENABLED";\r
- attribute GSR of FF_124 : label is "ENABLED";\r
- attribute GSR of FF_123 : label is "ENABLED";\r
- attribute GSR of FF_122 : label is "ENABLED";\r
- attribute GSR of FF_121 : label is "ENABLED";\r
- attribute GSR of FF_120 : label is "ENABLED";\r
- attribute GSR of FF_119 : label is "ENABLED";\r
- attribute GSR of FF_118 : label is "ENABLED";\r
- attribute GSR of FF_117 : label is "ENABLED";\r
- attribute GSR of FF_116 : label is "ENABLED";\r
- attribute GSR of FF_115 : label is "ENABLED";\r
- attribute GSR of FF_114 : label is "ENABLED";\r
- attribute GSR of FF_113 : label is "ENABLED";\r
- attribute GSR of FF_112 : label is "ENABLED";\r
- attribute GSR of FF_111 : label is "ENABLED";\r
- attribute GSR of FF_110 : label is "ENABLED";\r
- attribute GSR of FF_109 : label is "ENABLED";\r
- attribute GSR of FF_108 : label is "ENABLED";\r
- attribute GSR of FF_107 : label is "ENABLED";\r
- attribute GSR of FF_106 : label is "ENABLED";\r
- attribute GSR of FF_105 : label is "ENABLED";\r
- attribute GSR of FF_104 : label is "ENABLED";\r
- attribute GSR of FF_103 : label is "ENABLED";\r
- attribute GSR of FF_102 : label is "ENABLED";\r
- attribute GSR of FF_101 : label is "ENABLED";\r
- attribute GSR of FF_100 : label is "ENABLED";\r
- attribute GSR of FF_99 : label is "ENABLED";\r
- attribute GSR of FF_98 : label is "ENABLED";\r
- attribute GSR of FF_97 : label is "ENABLED";\r
- attribute GSR of FF_96 : label is "ENABLED";\r
- attribute GSR of FF_95 : label is "ENABLED";\r
- attribute GSR of FF_94 : label is "ENABLED";\r
- attribute GSR of FF_93 : label is "ENABLED";\r
- attribute GSR of FF_92 : label is "ENABLED";\r
- attribute GSR of FF_91 : label is "ENABLED";\r
- attribute GSR of FF_90 : label is "ENABLED";\r
- attribute GSR of FF_89 : label is "ENABLED";\r
- attribute GSR of FF_88 : label is "ENABLED";\r
- attribute GSR of FF_87 : label is "ENABLED";\r
- attribute GSR of FF_86 : label is "ENABLED";\r
- attribute GSR of FF_85 : label is "ENABLED";\r
- attribute GSR of FF_84 : label is "ENABLED";\r
- attribute GSR of FF_83 : label is "ENABLED";\r
- attribute GSR of FF_82 : label is "ENABLED";\r
- attribute GSR of FF_81 : label is "ENABLED";\r
- attribute GSR of FF_80 : label is "ENABLED";\r
- attribute GSR of FF_79 : label is "ENABLED";\r
- attribute GSR of FF_78 : label is "ENABLED";\r
- attribute GSR of FF_77 : label is "ENABLED";\r
- attribute GSR of FF_76 : label is "ENABLED";\r
- attribute GSR of FF_75 : label is "ENABLED";\r
- attribute GSR of FF_74 : label is "ENABLED";\r
- attribute GSR of FF_73 : label is "ENABLED";\r
- attribute GSR of FF_72 : label is "ENABLED";\r
- attribute GSR of FF_71 : label is "ENABLED";\r
- attribute GSR of FF_70 : label is "ENABLED";\r
- attribute GSR of FF_69 : label is "ENABLED";\r
- attribute GSR of FF_68 : label is "ENABLED";\r
- attribute GSR of FF_67 : label is "ENABLED";\r
- attribute GSR of FF_66 : label is "ENABLED";\r
- attribute GSR of FF_65 : label is "ENABLED";\r
- attribute GSR of FF_64 : label is "ENABLED";\r
- attribute GSR of FF_63 : label is "ENABLED";\r
- attribute GSR of FF_62 : label is "ENABLED";\r
- attribute GSR of FF_61 : label is "ENABLED";\r
- attribute GSR of FF_60 : label is "ENABLED";\r
- attribute GSR of FF_59 : label is "ENABLED";\r
- attribute GSR of FF_58 : label is "ENABLED";\r
- attribute GSR of FF_57 : label is "ENABLED";\r
- attribute GSR of FF_56 : label is "ENABLED";\r
- attribute GSR of FF_55 : label is "ENABLED";\r
- attribute GSR of FF_54 : label is "ENABLED";\r
- attribute GSR of FF_53 : label is "ENABLED";\r
- attribute GSR of FF_52 : label is "ENABLED";\r
- attribute GSR of FF_51 : label is "ENABLED";\r
- attribute GSR of FF_50 : label is "ENABLED";\r
- attribute GSR of FF_49 : label is "ENABLED";\r
- attribute GSR of FF_48 : label is "ENABLED";\r
- attribute GSR of FF_47 : label is "ENABLED";\r
- attribute GSR of FF_46 : label is "ENABLED";\r
- attribute GSR of FF_45 : label is "ENABLED";\r
- attribute GSR of FF_44 : label is "ENABLED";\r
- attribute GSR of FF_43 : label is "ENABLED";\r
- attribute GSR of FF_42 : label is "ENABLED";\r
- attribute GSR of FF_41 : label is "ENABLED";\r
- attribute GSR of FF_40 : label is "ENABLED";\r
- attribute GSR of FF_39 : label is "ENABLED";\r
- attribute GSR of FF_38 : label is "ENABLED";\r
- attribute GSR of FF_37 : label is "ENABLED";\r
- attribute GSR of FF_36 : label is "ENABLED";\r
- attribute GSR of FF_35 : label is "ENABLED";\r
- attribute GSR of FF_34 : label is "ENABLED";\r
- attribute GSR of FF_33 : label is "ENABLED";\r
- attribute GSR of FF_32 : label is "ENABLED";\r
- attribute GSR of FF_31 : label is "ENABLED";\r
- attribute GSR of FF_30 : label is "ENABLED";\r
- attribute GSR of FF_29 : label is "ENABLED";\r
- attribute GSR of FF_28 : label is "ENABLED";\r
- attribute GSR of FF_27 : label is "ENABLED";\r
- attribute GSR of FF_26 : label is "ENABLED";\r
- attribute GSR of FF_25 : label is "ENABLED";\r
- attribute GSR of FF_24 : label is "ENABLED";\r
- attribute GSR of FF_23 : label is "ENABLED";\r
- attribute GSR of FF_22 : label is "ENABLED";\r
- attribute GSR of FF_21 : label is "ENABLED";\r
- attribute GSR of FF_20 : label is "ENABLED";\r
- attribute GSR of FF_19 : label is "ENABLED";\r
- attribute GSR of FF_18 : label is "ENABLED";\r
- attribute GSR of FF_17 : label is "ENABLED";\r
- attribute GSR of FF_16 : label is "ENABLED";\r
- attribute GSR of FF_15 : label is "ENABLED";\r
- attribute GSR of FF_14 : label is "ENABLED";\r
- attribute GSR of FF_13 : label is "ENABLED";\r
- attribute GSR of FF_12 : label is "ENABLED";\r
- attribute GSR of FF_11 : label is "ENABLED";\r
- attribute GSR of FF_10 : label is "ENABLED";\r
- attribute GSR of FF_9 : label is "ENABLED";\r
- attribute GSR of FF_8 : label is "ENABLED";\r
- attribute GSR of FF_7 : label is "ENABLED";\r
- attribute GSR of FF_6 : label is "ENABLED";\r
- attribute GSR of FF_5 : label is "ENABLED";\r
- attribute GSR of FF_4 : label is "ENABLED";\r
- attribute GSR of FF_3 : label is "ENABLED";\r
- attribute GSR of FF_2 : label is "ENABLED";\r
- attribute GSR of FF_1 : label is "ENABLED";\r
- attribute GSR of FF_0 : label is "ENABLED";\r
- attribute syn_keep : boolean;\r
-\r
-begin\r
- -- component instantiation statements\r
- AND2_t26: AND2\r
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);\r
-\r
- INV_1: INV\r
- port map (A=>full_i, Z=>invout_1);\r
-\r
- AND2_t25: AND2\r
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);\r
-\r
- INV_0: INV\r
- port map (A=>empty_i, Z=>invout_0);\r
-\r
- OR2_t24: OR2\r
- port map (A=>Reset, B=>RPReset, Z=>rRst);\r
-\r
- XOR2_t23: XOR2\r
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);\r
-\r
- XOR2_t22: XOR2\r
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);\r
-\r
- XOR2_t21: XOR2\r
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);\r
-\r
- XOR2_t20: XOR2\r
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);\r
-\r
- XOR2_t19: XOR2\r
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);\r
-\r
- XOR2_t18: XOR2\r
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);\r
-\r
- XOR2_t17: XOR2\r
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);\r
-\r
- XOR2_t16: XOR2\r
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);\r
-\r
- XOR2_t15: XOR2\r
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);\r
-\r
- XOR2_t14: XOR2\r
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);\r
-\r
- XOR2_t13: XOR2\r
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);\r
-\r
- XOR2_t12: XOR2\r
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);\r
-\r
- XOR2_t11: XOR2\r
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);\r
-\r
- XOR2_t10: XOR2\r
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);\r
-\r
- XOR2_t9: XOR2\r
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);\r
-\r
- XOR2_t8: XOR2\r
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);\r
-\r
- XOR2_t7: XOR2\r
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);\r
-\r
- XOR2_t6: XOR2\r
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);\r
-\r
- XOR2_t5: XOR2\r
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);\r
-\r
- XOR2_t4: XOR2\r
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);\r
-\r
- XOR2_t3: XOR2\r
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);\r
-\r
- XOR2_t2: XOR2\r
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);\r
-\r
- XOR2_t1: XOR2\r
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);\r
-\r
- XOR2_t0: XOR2\r
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);\r
-\r
- LUT4_33: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, \r
- AD1=>w_gcount_r211, AD0=>w_gcount_r212, \r
- DO0=>w_g2b_xor_cluster_0);\r
-\r
- LUT4_32: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, \r
- AD1=>w_gcount_r27, AD0=>w_gcount_r28, \r
- DO0=>w_g2b_xor_cluster_1);\r
-\r
- LUT4_31: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, \r
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, \r
- DO0=>w_g2b_xor_cluster_2);\r
-\r
- LUT4_30: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>wcount_r11);\r
-\r
- LUT4_29: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, \r
- AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);\r
-\r
- LUT4_28: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, \r
- AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);\r
-\r
- LUT4_27: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, \r
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);\r
-\r
- LUT4_26: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, \r
- AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);\r
-\r
- LUT4_25: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);\r
-\r
- LUT4_24: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);\r
-\r
- LUT4_23: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);\r
-\r
- LUT4_22: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, \r
- AD1=>w_gcount_r24, AD0=>scuba_vlo, \r
- DO0=>w_g2b_xor_cluster_2_1);\r
-\r
- LUT4_21: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);\r
-\r
- LUT4_20: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);\r
-\r
- LUT4_19: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);\r
-\r
- LUT4_18: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, \r
- AD1=>r_gcount_w211, AD0=>r_gcount_w212, \r
- DO0=>r_g2b_xor_cluster_0);\r
-\r
- LUT4_17: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, \r
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, \r
- DO0=>r_g2b_xor_cluster_1);\r
-\r
- LUT4_16: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, \r
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, \r
- DO0=>r_g2b_xor_cluster_2);\r
-\r
- LUT4_15: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>rcount_w11);\r
-\r
- LUT4_14: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, \r
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);\r
-\r
- LUT4_13: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, \r
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);\r
-\r
- LUT4_12: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, \r
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);\r
-\r
- LUT4_11: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, \r
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);\r
-\r
- LUT4_10: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);\r
-\r
- LUT4_9: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);\r
-\r
- LUT4_8: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);\r
-\r
- LUT4_7: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, \r
- AD1=>r_gcount_w24, AD0=>scuba_vlo, \r
- DO0=>r_g2b_xor_cluster_2_1);\r
-\r
- LUT4_6: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);\r
-\r
- LUT4_5: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);\r
-\r
- LUT4_4: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);\r
-\r
- LUT4_3: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x0410")\r
- -- synopsys translate_on\r
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, \r
- AD0=>scuba_vlo, DO0=>empty_cmp_set);\r
-\r
- LUT4_2: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x1004")\r
- -- synopsys translate_on\r
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, \r
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);\r
-\r
- LUT4_1: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x0140")\r
- -- synopsys translate_on\r
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, \r
- AD0=>scuba_vlo, DO0=>full_cmp_set);\r
-\r
- LUT4_0: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x4001")\r
- -- synopsys translate_on\r
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, \r
- AD0=>scuba_vlo, DO0=>full_cmp_clr);\r
-\r
- pdp_ram_0_0_1: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, \r
- DATA_WIDTH_A=> 9)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), \r
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), \r
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, \r
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, \r
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, \r
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, \r
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, \r
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, \r
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, \r
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, \r
- CSA0=>wptr_11, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, \r
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, \r
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, \r
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, \r
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, \r
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, \r
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, \r
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, \r
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, \r
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, \r
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, \r
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>rptr_11, \r
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, \r
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, \r
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, \r
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, \r
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, \r
- DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, \r
- DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, \r
- DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, \r
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, \r
- DOB15=>open, DOB16=>open, DOB17=>open);\r
-\r
- pdp_ram_1_0_0: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, \r
- DATA_WIDTH_A=> 9)\r
- -- synopsys translate_on\r
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), \r
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), \r
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, \r
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, \r
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, \r
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, \r
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, \r
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, \r
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, \r
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, \r
- CSA0=>wptr_11, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, \r
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, \r
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, \r
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, \r
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, \r
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, \r
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, \r
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, \r
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, \r
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, \r
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, \r
- CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>rptr_11, \r
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, \r
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, \r
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, \r
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, \r
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, \r
- DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, \r
- DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, \r
- DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, \r
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, \r
- DOB15=>open, DOB16=>open, DOB17=>open);\r
-\r
- FF_132: FD1P3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, \r
- Q=>wcount_0);\r
-\r
- FF_131: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_1);\r
-\r
- FF_130: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_2);\r
-\r
- FF_129: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_3);\r
-\r
- FF_128: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_4);\r
-\r
- FF_127: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_5);\r
-\r
- FF_126: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_6);\r
-\r
- FF_125: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_7);\r
-\r
- FF_124: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_8);\r
-\r
- FF_123: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_9);\r
-\r
- FF_122: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_10);\r
-\r
- FF_121: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_11);\r
-\r
- FF_120: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_12);\r
-\r
- FF_119: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_0);\r
-\r
- FF_118: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_1);\r
-\r
- FF_117: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_2);\r
-\r
- FF_116: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_3);\r
-\r
- FF_115: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_4);\r
-\r
- FF_114: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_5);\r
-\r
- FF_113: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_6);\r
-\r
- FF_112: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_7);\r
-\r
- FF_111: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_8);\r
-\r
- FF_110: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_9);\r
-\r
- FF_109: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_10);\r
-\r
- FF_108: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_11);\r
-\r
- FF_107: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_12);\r
-\r
- FF_106: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_0);\r
-\r
- FF_105: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_1);\r
-\r
- FF_104: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_2);\r
-\r
- FF_103: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_3);\r
-\r
- FF_102: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_4);\r
-\r
- FF_101: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_5);\r
-\r
- FF_100: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_6);\r
-\r
- FF_99: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_7);\r
-\r
- FF_98: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_8);\r
-\r
- FF_97: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_9);\r
-\r
- FF_96: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_10);\r
-\r
- FF_95: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_11);\r
-\r
- FF_94: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_12);\r
-\r
- FF_93: FD1P3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, \r
- Q=>rcount_0);\r
-\r
- FF_92: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_1);\r
-\r
- FF_91: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_2);\r
-\r
- FF_90: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_3);\r
-\r
- FF_89: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_4);\r
-\r
- FF_88: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_5);\r
-\r
- FF_87: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_6);\r
-\r
- FF_86: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_7);\r
-\r
- FF_85: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_8);\r
-\r
- FF_84: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_9);\r
-\r
- FF_83: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_10);\r
-\r
- FF_82: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_11);\r
-\r
- FF_81: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_12);\r
-\r
- FF_80: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_0);\r
-\r
- FF_79: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_1);\r
-\r
- FF_78: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_2);\r
-\r
- FF_77: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_3);\r
-\r
- FF_76: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_4);\r
-\r
- FF_75: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_5);\r
-\r
- FF_74: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_6);\r
-\r
- FF_73: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_7);\r
-\r
- FF_72: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_8);\r
-\r
- FF_71: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_9);\r
-\r
- FF_70: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_10);\r
-\r
- FF_69: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_11);\r
-\r
- FF_68: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_12);\r
-\r
- FF_67: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_0);\r
-\r
- FF_66: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_1);\r
-\r
- FF_65: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_2);\r
-\r
- FF_64: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_3);\r
-\r
- FF_63: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_4);\r
-\r
- FF_62: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_5);\r
-\r
- FF_61: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_6);\r
-\r
- FF_60: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_7);\r
-\r
- FF_59: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_8);\r
-\r
- FF_58: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_9);\r
-\r
- FF_57: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_10);\r
-\r
- FF_56: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_11);\r
-\r
- FF_55: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_12);\r
-\r
- FF_54: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, \r
- Q=>rptr_11_ff);\r
-\r
- FF_53: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);\r
-\r
- FF_52: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);\r
-\r
- FF_51: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);\r
-\r
- FF_50: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);\r
-\r
- FF_49: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);\r
-\r
- FF_48: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);\r
-\r
- FF_47: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);\r
-\r
- FF_46: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);\r
-\r
- FF_45: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);\r
-\r
- FF_44: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);\r
-\r
- FF_43: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r10);\r
-\r
- FF_42: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r11);\r
-\r
- FF_41: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r12);\r
-\r
- FF_40: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);\r
-\r
- FF_39: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);\r
-\r
- FF_38: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);\r
-\r
- FF_37: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);\r
-\r
- FF_36: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);\r
-\r
- FF_35: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);\r
-\r
- FF_34: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);\r
-\r
- FF_33: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);\r
-\r
- FF_32: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);\r
-\r
- FF_31: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);\r
-\r
- FF_30: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);\r
-\r
- FF_29: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);\r
-\r
- FF_28: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);\r
-\r
- FF_27: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r20);\r
-\r
- FF_26: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r21);\r
-\r
- FF_25: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r22);\r
-\r
- FF_24: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r23);\r
-\r
- FF_23: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r24);\r
-\r
- FF_22: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r25);\r
-\r
- FF_21: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r26);\r
-\r
- FF_20: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r27);\r
-\r
- FF_19: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r28);\r
-\r
- FF_18: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r29);\r
-\r
- FF_17: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r210);\r
-\r
- FF_16: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r211);\r
-\r
- FF_15: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r212);\r
-\r
- FF_14: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);\r
-\r
- FF_13: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);\r
-\r
- FF_12: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);\r
-\r
- FF_11: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);\r
-\r
- FF_10: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);\r
-\r
- FF_9: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);\r
-\r
- FF_8: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);\r
-\r
- FF_7: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);\r
-\r
- FF_6: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);\r
-\r
- FF_5: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);\r
-\r
- FF_4: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w210);\r
-\r
- FF_3: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w211);\r
-\r
- FF_2: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w212);\r
-\r
- FF_1: FD1S3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);\r
-\r
- FF_0: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);\r
-\r
- w_gctr_cia: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, \r
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, \r
- S1=>open);\r
-\r
- w_gctr_0: CU2\r
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, \r
- NC0=>iwcount_0, NC1=>iwcount_1);\r
-\r
- w_gctr_1: CU2\r
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, \r
- NC0=>iwcount_2, NC1=>iwcount_3);\r
-\r
- w_gctr_2: CU2\r
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, \r
- NC0=>iwcount_4, NC1=>iwcount_5);\r
-\r
- w_gctr_3: CU2\r
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, \r
- NC0=>iwcount_6, NC1=>iwcount_7);\r
-\r
- w_gctr_4: CU2\r
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, \r
- NC0=>iwcount_8, NC1=>iwcount_9);\r
-\r
- w_gctr_5: CU2\r
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, \r
- NC0=>iwcount_10, NC1=>iwcount_11);\r
-\r
- w_gctr_6: CU2\r
- port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, \r
- NC0=>iwcount_12, NC1=>open);\r
-\r
- scuba_vhi_inst: VHI\r
- port map (Z=>scuba_vhi);\r
-\r
- r_gctr_cia: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, \r
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, \r
- S1=>open);\r
-\r
- r_gctr_0: CU2\r
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, \r
- NC0=>ircount_0, NC1=>ircount_1);\r
-\r
- r_gctr_1: CU2\r
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, \r
- NC0=>ircount_2, NC1=>ircount_3);\r
-\r
- r_gctr_2: CU2\r
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, \r
- NC0=>ircount_4, NC1=>ircount_5);\r
-\r
- r_gctr_3: CU2\r
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, \r
- NC0=>ircount_6, NC1=>ircount_7);\r
-\r
- r_gctr_4: CU2\r
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, \r
- NC0=>ircount_8, NC1=>ircount_9);\r
-\r
- r_gctr_5: CU2\r
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, \r
- NC0=>ircount_10, NC1=>ircount_11);\r
-\r
- r_gctr_6: CU2\r
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, \r
- NC0=>ircount_12, NC1=>open);\r
-\r
- mux_8: MUX21\r
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, \r
- Z=>Q(0));\r
-\r
- mux_7: MUX21\r
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, \r
- Z=>Q(1));\r
-\r
- mux_6: MUX21\r
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, \r
- Z=>Q(2));\r
-\r
- mux_5: MUX21\r
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, \r
- Z=>Q(3));\r
-\r
- mux_4: MUX21\r
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, \r
- Z=>Q(4));\r
-\r
- mux_3: MUX21\r
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, \r
- Z=>Q(5));\r
-\r
- mux_2: MUX21\r
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, \r
- Z=>Q(6));\r
-\r
- mux_1: MUX21\r
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, \r
- Z=>Q(7));\r
-\r
- mux_0: MUX21\r
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, \r
- Z=>Q(8));\r
-\r
- empty_cmp_ci_a: FADD2B\r
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, \r
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);\r
-\r
- empty_cmp_0: AGEB2\r
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, \r
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);\r
-\r
- empty_cmp_1: AGEB2\r
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, \r
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);\r
-\r
- empty_cmp_2: AGEB2\r
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, \r
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);\r
-\r
- empty_cmp_3: AGEB2\r
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, \r
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);\r
-\r
- empty_cmp_4: AGEB2\r
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, \r
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);\r
-\r
- empty_cmp_5: AGEB2\r
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, \r
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);\r
-\r
- empty_cmp_6: AGEB2\r
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, \r
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);\r
-\r
- a0: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, \r
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, \r
- S1=>open);\r
-\r
- full_cmp_ci_a: FADD2B\r
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, \r
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);\r
-\r
- full_cmp_0: AGEB2\r
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, \r
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);\r
-\r
- full_cmp_1: AGEB2\r
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, \r
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);\r
-\r
- full_cmp_2: AGEB2\r
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, \r
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);\r
-\r
- full_cmp_3: AGEB2\r
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, \r
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);\r
-\r
- full_cmp_4: AGEB2\r
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, \r
- B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);\r
-\r
- full_cmp_5: AGEB2\r
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, \r
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);\r
-\r
- full_cmp_6: AGEB2\r
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, \r
- B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c);\r
-\r
- scuba_vlo_inst: VLO\r
- port map (Z=>scuba_vlo);\r
-\r
- a1: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, \r
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, \r
- S1=>open);\r
-\r
- Empty <= empty_i;\r
- Full <= full_i;\r
-end Structure;\r
-\r
--- synopsys translate_off\r
-library ecp2m;\r
-configuration Structure_CON of fifo_4096x9 is\r
- for Structure\r
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;\r
- for all:AND2 use entity ecp2m.AND2(V); end for;\r
- for all:CU2 use entity ecp2m.CU2(V); end for;\r
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;\r
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;\r
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;\r
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;\r
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;\r
- for all:INV use entity ecp2m.INV(V); end for;\r
- for all:MUX21 use entity ecp2m.MUX21(V); end for;\r
- for all:OR2 use entity ecp2m.OR2(V); end for;\r
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;\r
- for all:VHI use entity ecp2m.VHI(V); end for;\r
- for all:VLO use entity ecp2m.VLO(V); end for;\r
- for all:XOR2 use entity ecp2m.XOR2(V); end for;\r
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;\r
- end for;\r
-end Structure_CON;\r
-\r
--- synopsys translate_on\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)\r
--- Module Version: 5.2\r
--- Tue Jan 5 23:44:15 2010\r
-\r
--- parameterized module component declaration\r
-component fifo_4096x9\r
- port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; \r
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; \r
- Reset: in std_logic; RPReset: in std_logic; \r
- Q: out std_logic_vector(8 downto 0); Empty: out std_logic; \r
- Full: out std_logic);\r
-end component;\r
-\r
--- parameterized module component instance\r
-__ : fifo_4096x9\r
- port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, \r
- RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, \r
- Full=>__);\r
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_512x32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:13:43
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=512
-Width=32
-RDepth=512
-RWidth=32
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:13:43 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_512x32 is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x32;
-
-architecture Structure of fifo_512x32 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
- ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7,
- ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open,
- DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4),
- DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9),
- DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13),
- DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
-
- FF_101: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_512x32 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:13:43 2011
-
--- parameterized module component declaration
-component fifo_512x32
- port (Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_512x32
- port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_512x64
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:23:40
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=512
-Width=72
-RDepth=512
-RWidth=72
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:23:40 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_512x64 is
- port (
- Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x64;
-
-architecture Structure of fifo_512x64 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x64.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x64.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
- ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
- DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
- pdp_ram_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
- DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
- DI14=>Data(50), DI15=>Data(51), DI16=>Data(52),
- DI17=>Data(53), DI18=>Data(54), DI19=>Data(55),
- DI20=>Data(56), DI21=>Data(57), DI22=>Data(58),
- DI23=>Data(59), DI24=>Data(60), DI25=>Data(61),
- DI26=>Data(62), DI27=>Data(63), DI28=>Data(64),
- DI29=>Data(65), DI30=>Data(66), DI31=>Data(67),
- DI32=>Data(68), DI33=>Data(69), DI34=>Data(70),
- DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
- ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
- ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi,
- BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock,
- CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
- ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
- ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
- ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5,
- ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55),
- DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60),
- DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65),
- DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69),
- DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37),
- DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
- DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45),
- DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49),
- DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53));
-
- FF_101: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_512x64 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:23:40 2011
-
--- parameterized module component declaration
-component fifo_512x64
- port (Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_512x64
- port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_512x72
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/22/2011
-Time=11:14:03
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=512
-Width=72
-RDepth=512
-RWidth=72
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e
-
--- Thu Sep 22 11:14:04 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_512x72 is
- port (
- Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x72;
-
-architecture Structure of fifo_512x72 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x72.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x72.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
- ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
- DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
- pdp_ram_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
- DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
- DI14=>Data(50), DI15=>Data(51), DI16=>Data(52),
- DI17=>Data(53), DI18=>Data(54), DI19=>Data(55),
- DI20=>Data(56), DI21=>Data(57), DI22=>Data(58),
- DI23=>Data(59), DI24=>Data(60), DI25=>Data(61),
- DI26=>Data(62), DI27=>Data(63), DI28=>Data(64),
- DI29=>Data(65), DI30=>Data(66), DI31=>Data(67),
- DI32=>Data(68), DI33=>Data(69), DI34=>Data(70),
- DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
- ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
- ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi,
- BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock,
- CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
- ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
- ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
- ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5,
- ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55),
- DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60),
- DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65),
- DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69),
- DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37),
- DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
- DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45),
- DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49),
- DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53));
-
- FF_101: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_512x72 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
--- Thu Sep 22 11:14:04 2011
-
--- parameterized module component declaration
-component fifo_512x72
- port (Data: in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(71 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_512x72
- port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-5F900C\r
-SpeedGrade=-5\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=FIFO_DC\r
-CoreRevision=5.2\r
-ModuleName=fifo_64kx8\r
-SourceFormat=Schematic/VHDL\r
-ParameterFileVersion=1.0\r
-Date=12/26/2009\r
-Time=00:12:05\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-FIFOImp=EBR Based\r
-Depth=65536\r
-Width=8\r
-RDepth=65536\r
-RWidth=8\r
-regout=0\r
-CtrlByRdEn=0\r
-EmpFlg=0\r
-PeMode=Static - Dual Threshold\r
-PeAssert=10\r
-PeDeassert=12\r
-FullFlg=0\r
-PfMode=Static - Dual Threshold\r
-PfAssert=508\r
-PfDeassert=506\r
-RDataCount=0\r
-WDataCount=0\r
-EnECC=0\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)\r
--- Module Version: 5.2\r
---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 65536 -width 8 -depth 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e \r
-\r
--- Sat Dec 26 00:12:05 2009\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
--- synopsys translate_off\r
-library ecp2m;\r
-use ecp2m.components.all;\r
--- synopsys translate_on\r
-\r
-entity fifo_64kx8 is\r
- port (\r
- Data: in std_logic_vector(7 downto 0); \r
- WrClock: in std_logic; \r
- RdClock: in std_logic; \r
- WrEn: in std_logic; \r
- RdEn: in std_logic; \r
- Reset: in std_logic; \r
- RPReset: in std_logic; \r
- Q: out std_logic_vector(7 downto 0); \r
- Empty: out std_logic; \r
- Full: out std_logic);\r
-end fifo_64kx8;\r
-\r
-architecture Structure of fifo_64kx8 is\r
-\r
- -- internal signal declarations\r
- signal invout_1: std_logic;\r
- signal invout_0: std_logic;\r
- signal w_g2b_xor_cluster_2_1: std_logic;\r
- signal w_g2b_xor_cluster_3_1: std_logic;\r
- signal w_g2b_xor_cluster_3_2: std_logic;\r
- signal w_g2b_xor_cluster_3: std_logic;\r
- signal w_g2b_xor_cluster_2: std_logic;\r
- signal w_g2b_xor_cluster_1: std_logic;\r
- signal func_xor_inet_3: std_logic;\r
- signal func_xor_inet_2: std_logic;\r
- signal func_xor_inet_1: std_logic;\r
- signal func_xor_inet: std_logic;\r
- signal func_xor_inet_4: std_logic;\r
- signal func_xor_inet_5: std_logic;\r
- signal r_g2b_xor_cluster_2_1: std_logic;\r
- signal r_g2b_xor_cluster_3_1: std_logic;\r
- signal r_g2b_xor_cluster_3_2: std_logic;\r
- signal r_g2b_xor_cluster_3: std_logic;\r
- signal r_g2b_xor_cluster_2: std_logic;\r
- signal r_g2b_xor_cluster_1: std_logic;\r
- signal func_xor_inet_9: std_logic;\r
- signal func_xor_inet_8: std_logic;\r
- signal func_xor_inet_7: std_logic;\r
- signal func_xor_inet_6: std_logic;\r
- signal func_xor_inet_10: std_logic;\r
- signal func_xor_inet_11: std_logic;\r
- signal w_gdata_0: std_logic;\r
- signal w_gdata_1: std_logic;\r
- signal w_gdata_2: std_logic;\r
- signal w_gdata_3: std_logic;\r
- signal w_gdata_4: std_logic;\r
- signal w_gdata_5: std_logic;\r
- signal w_gdata_6: std_logic;\r
- signal w_gdata_7: std_logic;\r
- signal w_gdata_8: std_logic;\r
- signal w_gdata_9: std_logic;\r
- signal w_gdata_10: std_logic;\r
- signal w_gdata_11: std_logic;\r
- signal w_gdata_12: std_logic;\r
- signal w_gdata_13: std_logic;\r
- signal w_gdata_14: std_logic;\r
- signal w_gdata_15: std_logic;\r
- signal wptr_0: std_logic;\r
- signal wptr_1: std_logic;\r
- signal wptr_2: std_logic;\r
- signal wptr_3: std_logic;\r
- signal wptr_4: std_logic;\r
- signal wptr_5: std_logic;\r
- signal wptr_6: std_logic;\r
- signal wptr_7: std_logic;\r
- signal wptr_8: std_logic;\r
- signal wptr_9: std_logic;\r
- signal wptr_10: std_logic;\r
- signal wptr_11: std_logic;\r
- signal wptr_12: std_logic;\r
- signal wptr_13: std_logic;\r
- signal wptr_14: std_logic;\r
- signal wptr_15: std_logic;\r
- signal wptr_16: std_logic;\r
- signal r_gdata_0: std_logic;\r
- signal r_gdata_1: std_logic;\r
- signal r_gdata_2: std_logic;\r
- signal r_gdata_3: std_logic;\r
- signal r_gdata_4: std_logic;\r
- signal r_gdata_5: std_logic;\r
- signal r_gdata_6: std_logic;\r
- signal r_gdata_7: std_logic;\r
- signal r_gdata_8: std_logic;\r
- signal r_gdata_9: std_logic;\r
- signal r_gdata_10: std_logic;\r
- signal r_gdata_11: std_logic;\r
- signal r_gdata_12: std_logic;\r
- signal r_gdata_13: std_logic;\r
- signal r_gdata_14: std_logic;\r
- signal r_gdata_15: std_logic;\r
- signal rptr_0: std_logic;\r
- signal rptr_1: std_logic;\r
- signal rptr_2: std_logic;\r
- signal rptr_3: std_logic;\r
- signal rptr_4: std_logic;\r
- signal rptr_5: std_logic;\r
- signal rptr_6: std_logic;\r
- signal rptr_7: std_logic;\r
- signal rptr_8: std_logic;\r
- signal rptr_9: std_logic;\r
- signal rptr_10: std_logic;\r
- signal rptr_11: std_logic;\r
- signal rptr_12: std_logic;\r
- signal rptr_13: std_logic;\r
- signal rptr_16: std_logic;\r
- signal rptr_14: std_logic;\r
- signal rptr_15: std_logic;\r
- signal w_gcount_0: std_logic;\r
- signal w_gcount_1: std_logic;\r
- signal w_gcount_2: std_logic;\r
- signal w_gcount_3: std_logic;\r
- signal w_gcount_4: std_logic;\r
- signal w_gcount_5: std_logic;\r
- signal w_gcount_6: std_logic;\r
- signal w_gcount_7: std_logic;\r
- signal w_gcount_8: std_logic;\r
- signal w_gcount_9: std_logic;\r
- signal w_gcount_10: std_logic;\r
- signal w_gcount_11: std_logic;\r
- signal w_gcount_12: std_logic;\r
- signal w_gcount_13: std_logic;\r
- signal w_gcount_14: std_logic;\r
- signal w_gcount_15: std_logic;\r
- signal w_gcount_16: std_logic;\r
- signal r_gcount_0: std_logic;\r
- signal r_gcount_1: std_logic;\r
- signal r_gcount_2: std_logic;\r
- signal r_gcount_3: std_logic;\r
- signal r_gcount_4: std_logic;\r
- signal r_gcount_5: std_logic;\r
- signal r_gcount_6: std_logic;\r
- signal r_gcount_7: std_logic;\r
- signal r_gcount_8: std_logic;\r
- signal r_gcount_9: std_logic;\r
- signal r_gcount_10: std_logic;\r
- signal r_gcount_11: std_logic;\r
- signal r_gcount_12: std_logic;\r
- signal r_gcount_13: std_logic;\r
- signal r_gcount_14: std_logic;\r
- signal r_gcount_15: std_logic;\r
- signal r_gcount_16: std_logic;\r
- signal w_gcount_r20: std_logic;\r
- signal w_gcount_r0: std_logic;\r
- signal w_gcount_r21: std_logic;\r
- signal w_gcount_r1: std_logic;\r
- signal w_gcount_r22: std_logic;\r
- signal w_gcount_r2: std_logic;\r
- signal w_gcount_r23: std_logic;\r
- signal w_gcount_r3: std_logic;\r
- signal w_gcount_r24: std_logic;\r
- signal w_gcount_r4: std_logic;\r
- signal w_gcount_r25: std_logic;\r
- signal w_gcount_r5: std_logic;\r
- signal w_gcount_r26: std_logic;\r
- signal w_gcount_r6: std_logic;\r
- signal w_gcount_r27: std_logic;\r
- signal w_gcount_r7: std_logic;\r
- signal w_gcount_r28: std_logic;\r
- signal w_gcount_r8: std_logic;\r
- signal w_gcount_r29: std_logic;\r
- signal w_gcount_r9: std_logic;\r
- signal w_gcount_r210: std_logic;\r
- signal w_gcount_r10: std_logic;\r
- signal w_gcount_r211: std_logic;\r
- signal w_gcount_r11: std_logic;\r
- signal w_gcount_r212: std_logic;\r
- signal w_gcount_r12: std_logic;\r
- signal w_gcount_r213: std_logic;\r
- signal w_gcount_r13: std_logic;\r
- signal w_gcount_r214: std_logic;\r
- signal w_gcount_r14: std_logic;\r
- signal w_gcount_r215: std_logic;\r
- signal w_gcount_r15: std_logic;\r
- signal w_gcount_r216: std_logic;\r
- signal w_gcount_r16: std_logic;\r
- signal r_gcount_w20: std_logic;\r
- signal r_gcount_w0: std_logic;\r
- signal r_gcount_w21: std_logic;\r
- signal r_gcount_w1: std_logic;\r
- signal r_gcount_w22: std_logic;\r
- signal r_gcount_w2: std_logic;\r
- signal r_gcount_w23: std_logic;\r
- signal r_gcount_w3: std_logic;\r
- signal r_gcount_w24: std_logic;\r
- signal r_gcount_w4: std_logic;\r
- signal r_gcount_w25: std_logic;\r
- signal r_gcount_w5: std_logic;\r
- signal r_gcount_w26: std_logic;\r
- signal r_gcount_w6: std_logic;\r
- signal r_gcount_w27: std_logic;\r
- signal r_gcount_w7: std_logic;\r
- signal r_gcount_w28: std_logic;\r
- signal r_gcount_w8: std_logic;\r
- signal r_gcount_w29: std_logic;\r
- signal r_gcount_w9: std_logic;\r
- signal r_gcount_w210: std_logic;\r
- signal r_gcount_w10: std_logic;\r
- signal r_gcount_w211: std_logic;\r
- signal r_gcount_w11: std_logic;\r
- signal r_gcount_w212: std_logic;\r
- signal r_gcount_w12: std_logic;\r
- signal r_gcount_w213: std_logic;\r
- signal r_gcount_w13: std_logic;\r
- signal r_gcount_w214: std_logic;\r
- signal r_gcount_w14: std_logic;\r
- signal r_gcount_w215: std_logic;\r
- signal r_gcount_w15: std_logic;\r
- signal r_gcount_w216: std_logic;\r
- signal r_gcount_w16: std_logic;\r
- signal empty_i: std_logic;\r
- signal rRst: std_logic;\r
- signal full_i: std_logic;\r
- signal iwcount_0: std_logic;\r
- signal iwcount_1: std_logic;\r
- signal w_gctr_ci: std_logic;\r
- signal iwcount_2: std_logic;\r
- signal iwcount_3: std_logic;\r
- signal co0: std_logic;\r
- signal iwcount_4: std_logic;\r
- signal iwcount_5: std_logic;\r
- signal co1: std_logic;\r
- signal iwcount_6: std_logic;\r
- signal iwcount_7: std_logic;\r
- signal co2: std_logic;\r
- signal iwcount_8: std_logic;\r
- signal iwcount_9: std_logic;\r
- signal co3: std_logic;\r
- signal iwcount_10: std_logic;\r
- signal iwcount_11: std_logic;\r
- signal co4: std_logic;\r
- signal iwcount_12: std_logic;\r
- signal iwcount_13: std_logic;\r
- signal co5: std_logic;\r
- signal iwcount_14: std_logic;\r
- signal iwcount_15: std_logic;\r
- signal co6: std_logic;\r
- signal iwcount_16: std_logic;\r
- signal co8: std_logic;\r
- signal wcount_16: std_logic;\r
- signal co7: std_logic;\r
- signal scuba_vhi: std_logic;\r
- signal ircount_0: std_logic;\r
- signal ircount_1: std_logic;\r
- signal r_gctr_ci: std_logic;\r
- signal ircount_2: std_logic;\r
- signal ircount_3: std_logic;\r
- signal co0_1: std_logic;\r
- signal ircount_4: std_logic;\r
- signal ircount_5: std_logic;\r
- signal co1_1: std_logic;\r
- signal ircount_6: std_logic;\r
- signal ircount_7: std_logic;\r
- signal co2_1: std_logic;\r
- signal ircount_8: std_logic;\r
- signal ircount_9: std_logic;\r
- signal co3_1: std_logic;\r
- signal ircount_10: std_logic;\r
- signal ircount_11: std_logic;\r
- signal co4_1: std_logic;\r
- signal ircount_12: std_logic;\r
- signal ircount_13: std_logic;\r
- signal co5_1: std_logic;\r
- signal ircount_14: std_logic;\r
- signal ircount_15: std_logic;\r
- signal co6_1: std_logic;\r
- signal ircount_16: std_logic;\r
- signal co8_1: std_logic;\r
- signal rcount_16: std_logic;\r
- signal co7_1: std_logic;\r
- signal mdout1_3_0: std_logic;\r
- signal mdout1_2_0: std_logic;\r
- signal mdout1_1_0: std_logic;\r
- signal mdout1_0_0: std_logic;\r
- signal mdout1_3_1: std_logic;\r
- signal mdout1_2_1: std_logic;\r
- signal mdout1_1_1: std_logic;\r
- signal mdout1_0_1: std_logic;\r
- signal mdout1_3_2: std_logic;\r
- signal mdout1_2_2: std_logic;\r
- signal mdout1_1_2: std_logic;\r
- signal mdout1_0_2: std_logic;\r
- signal mdout1_3_3: std_logic;\r
- signal mdout1_2_3: std_logic;\r
- signal mdout1_1_3: std_logic;\r
- signal mdout1_0_3: std_logic;\r
- signal mdout1_3_4: std_logic;\r
- signal mdout1_2_4: std_logic;\r
- signal mdout1_1_4: std_logic;\r
- signal mdout1_0_4: std_logic;\r
- signal mdout1_3_5: std_logic;\r
- signal mdout1_2_5: std_logic;\r
- signal mdout1_1_5: std_logic;\r
- signal mdout1_0_5: std_logic;\r
- signal mdout1_3_6: std_logic;\r
- signal mdout1_2_6: std_logic;\r
- signal mdout1_1_6: std_logic;\r
- signal mdout1_0_6: std_logic;\r
- signal rptr_15_ff: std_logic;\r
- signal rptr_14_ff: std_logic;\r
- signal mdout1_3_7: std_logic;\r
- signal mdout1_2_7: std_logic;\r
- signal mdout1_1_7: std_logic;\r
- signal mdout1_0_7: std_logic;\r
- signal rden_i: std_logic;\r
- signal cmp_ci: std_logic;\r
- signal wcount_r0: std_logic;\r
- signal wcount_r1: std_logic;\r
- signal rcount_0: std_logic;\r
- signal rcount_1: std_logic;\r
- signal co0_2: std_logic;\r
- signal wcount_r2: std_logic;\r
- signal wcount_r3: std_logic;\r
- signal rcount_2: std_logic;\r
- signal rcount_3: std_logic;\r
- signal co1_2: std_logic;\r
- signal wcount_r4: std_logic;\r
- signal wcount_r5: std_logic;\r
- signal rcount_4: std_logic;\r
- signal rcount_5: std_logic;\r
- signal co2_2: std_logic;\r
- signal wcount_r6: std_logic;\r
- signal wcount_r7: std_logic;\r
- signal rcount_6: std_logic;\r
- signal rcount_7: std_logic;\r
- signal co3_2: std_logic;\r
- signal wcount_r8: std_logic;\r
- signal wcount_r9: std_logic;\r
- signal rcount_8: std_logic;\r
- signal rcount_9: std_logic;\r
- signal co4_2: std_logic;\r
- signal wcount_r10: std_logic;\r
- signal wcount_r11: std_logic;\r
- signal rcount_10: std_logic;\r
- signal rcount_11: std_logic;\r
- signal co5_2: std_logic;\r
- signal wcount_r12: std_logic;\r
- signal w_g2b_xor_cluster_0: std_logic;\r
- signal rcount_12: std_logic;\r
- signal rcount_13: std_logic;\r
- signal co6_2: std_logic;\r
- signal wcount_r14: std_logic;\r
- signal wcount_r15: std_logic;\r
- signal rcount_14: std_logic;\r
- signal rcount_15: std_logic;\r
- signal co7_2: std_logic;\r
- signal empty_cmp_clr: std_logic;\r
- signal empty_cmp_set: std_logic;\r
- signal empty_d: std_logic;\r
- signal empty_d_c: std_logic;\r
- signal wren_i: std_logic;\r
- signal cmp_ci_1: std_logic;\r
- signal rcount_w0: std_logic;\r
- signal rcount_w1: std_logic;\r
- signal wcount_0: std_logic;\r
- signal wcount_1: std_logic;\r
- signal co0_3: std_logic;\r
- signal rcount_w2: std_logic;\r
- signal rcount_w3: std_logic;\r
- signal wcount_2: std_logic;\r
- signal wcount_3: std_logic;\r
- signal co1_3: std_logic;\r
- signal rcount_w4: std_logic;\r
- signal rcount_w5: std_logic;\r
- signal wcount_4: std_logic;\r
- signal wcount_5: std_logic;\r
- signal co2_3: std_logic;\r
- signal rcount_w6: std_logic;\r
- signal rcount_w7: std_logic;\r
- signal wcount_6: std_logic;\r
- signal wcount_7: std_logic;\r
- signal co3_3: std_logic;\r
- signal rcount_w8: std_logic;\r
- signal rcount_w9: std_logic;\r
- signal wcount_8: std_logic;\r
- signal wcount_9: std_logic;\r
- signal co4_3: std_logic;\r
- signal rcount_w10: std_logic;\r
- signal rcount_w11: std_logic;\r
- signal wcount_10: std_logic;\r
- signal wcount_11: std_logic;\r
- signal co5_3: std_logic;\r
- signal rcount_w12: std_logic;\r
- signal r_g2b_xor_cluster_0: std_logic;\r
- signal wcount_12: std_logic;\r
- signal wcount_13: std_logic;\r
- signal co6_3: std_logic;\r
- signal rcount_w14: std_logic;\r
- signal rcount_w15: std_logic;\r
- signal wcount_14: std_logic;\r
- signal wcount_15: std_logic;\r
- signal co7_3: std_logic;\r
- signal full_cmp_clr: std_logic;\r
- signal full_cmp_set: std_logic;\r
- signal full_d: std_logic;\r
- signal full_d_c: std_logic;\r
- signal scuba_vlo: std_logic;\r
-\r
- -- local component declarations\r
- component AGEB2\r
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic; \r
- B1: in std_logic; CI: in std_logic; GE: out std_logic);\r
- end component;\r
- component AND2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component CU2\r
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; \r
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);\r
- end component;\r
- component FADD2B\r
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic; \r
- B1: in std_logic; CI: in std_logic; COUT: out std_logic; \r
- S0: out std_logic; S1: out std_logic);\r
- end component;\r
- component FD1P3BX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; SP: in std_logic; CK: in std_logic; \r
- PD: in std_logic; Q: out std_logic);\r
- end component;\r
- component FD1P3DX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; SP: in std_logic; CK: in std_logic; \r
- CD: in std_logic; Q: out std_logic);\r
- end component;\r
- component FD1S3BX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; CK: in std_logic; PD: in std_logic; \r
- Q: out std_logic);\r
- end component;\r
- component FD1S3DX\r
- -- synopsys translate_off\r
- generic (GSR : in String);\r
- -- synopsys translate_on\r
- port (D: in std_logic; CK: in std_logic; CD: in std_logic; \r
- Q: out std_logic);\r
- end component;\r
- component INV\r
- port (A: in std_logic; Z: out std_logic);\r
- end component;\r
- component MUX41\r
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic; \r
- D3: in std_logic; SD1: in std_logic; SD2: in std_logic; \r
- Z: out std_logic);\r
- end component;\r
- component OR2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component ROM16X1\r
- -- synopsys translate_off\r
- generic (initval : in String);\r
- -- synopsys translate_on\r
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; \r
- AD0: in std_logic; DO0: out std_logic);\r
- end component;\r
- component VHI\r
- port (Z: out std_logic);\r
- end component;\r
- component VLO\r
- port (Z: out std_logic);\r
- end component;\r
- component XOR2\r
- port (A: in std_logic; B: in std_logic; Z: out std_logic);\r
- end component;\r
- component DP16KB\r
- -- synopsys translate_off\r
- generic (GSR : in String; WRITEMODE_B : in String; \r
- CSDECODE_B : in std_logic_vector(2 downto 0); \r
- CSDECODE_A : in std_logic_vector(2 downto 0); \r
- WRITEMODE_A : in String; RESETMODE : in String; \r
- REGMODE_B : in String; REGMODE_A : in String; \r
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);\r
- -- synopsys translate_on\r
- port (DIA0: in std_logic; DIA1: in std_logic; \r
- DIA2: in std_logic; DIA3: in std_logic; \r
- DIA4: in std_logic; DIA5: in std_logic; \r
- DIA6: in std_logic; DIA7: in std_logic; \r
- DIA8: in std_logic; DIA9: in std_logic; \r
- DIA10: in std_logic; DIA11: in std_logic; \r
- DIA12: in std_logic; DIA13: in std_logic; \r
- DIA14: in std_logic; DIA15: in std_logic; \r
- DIA16: in std_logic; DIA17: in std_logic; \r
- ADA0: in std_logic; ADA1: in std_logic; \r
- ADA2: in std_logic; ADA3: in std_logic; \r
- ADA4: in std_logic; ADA5: in std_logic; \r
- ADA6: in std_logic; ADA7: in std_logic; \r
- ADA8: in std_logic; ADA9: in std_logic; \r
- ADA10: in std_logic; ADA11: in std_logic; \r
- ADA12: in std_logic; ADA13: in std_logic; \r
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; \r
- CSA0: in std_logic; CSA1: in std_logic; \r
- CSA2: in std_logic; RSTA: in std_logic; \r
- DIB0: in std_logic; DIB1: in std_logic; \r
- DIB2: in std_logic; DIB3: in std_logic; \r
- DIB4: in std_logic; DIB5: in std_logic; \r
- DIB6: in std_logic; DIB7: in std_logic; \r
- DIB8: in std_logic; DIB9: in std_logic; \r
- DIB10: in std_logic; DIB11: in std_logic; \r
- DIB12: in std_logic; DIB13: in std_logic; \r
- DIB14: in std_logic; DIB15: in std_logic; \r
- DIB16: in std_logic; DIB17: in std_logic; \r
- ADB0: in std_logic; ADB1: in std_logic; \r
- ADB2: in std_logic; ADB3: in std_logic; \r
- ADB4: in std_logic; ADB5: in std_logic; \r
- ADB6: in std_logic; ADB7: in std_logic; \r
- ADB8: in std_logic; ADB9: in std_logic; \r
- ADB10: in std_logic; ADB11: in std_logic; \r
- ADB12: in std_logic; ADB13: in std_logic; \r
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; \r
- CSB0: in std_logic; CSB1: in std_logic; \r
- CSB2: in std_logic; RSTB: in std_logic; \r
- DOA0: out std_logic; DOA1: out std_logic; \r
- DOA2: out std_logic; DOA3: out std_logic; \r
- DOA4: out std_logic; DOA5: out std_logic; \r
- DOA6: out std_logic; DOA7: out std_logic; \r
- DOA8: out std_logic; DOA9: out std_logic; \r
- DOA10: out std_logic; DOA11: out std_logic; \r
- DOA12: out std_logic; DOA13: out std_logic; \r
- DOA14: out std_logic; DOA15: out std_logic; \r
- DOA16: out std_logic; DOA17: out std_logic; \r
- DOB0: out std_logic; DOB1: out std_logic; \r
- DOB2: out std_logic; DOB3: out std_logic; \r
- DOB4: out std_logic; DOB5: out std_logic; \r
- DOB6: out std_logic; DOB7: out std_logic; \r
- DOB8: out std_logic; DOB9: out std_logic; \r
- DOB10: out std_logic; DOB11: out std_logic; \r
- DOB12: out std_logic; DOB13: out std_logic; \r
- DOB14: out std_logic; DOB15: out std_logic; \r
- DOB16: out std_logic; DOB17: out std_logic);\r
- end component;\r
- attribute initval : string; \r
- attribute MEM_LPC_FILE : string; \r
- attribute MEM_INIT_FILE : string; \r
- attribute CSDECODE_B : string; \r
- attribute CSDECODE_A : string; \r
- attribute WRITEMODE_B : string; \r
- attribute WRITEMODE_A : string; \r
- attribute RESETMODE : string; \r
- attribute REGMODE_B : string; \r
- attribute REGMODE_A : string; \r
- attribute DATA_WIDTH_B : string; \r
- attribute DATA_WIDTH_A : string; \r
- attribute GSR : string; \r
- attribute initval of LUT4_59 : label is "0x6996";\r
- attribute initval of LUT4_58 : label is "0x6996";\r
- attribute initval of LUT4_57 : label is "0x6996";\r
- attribute initval of LUT4_56 : label is "0x6996";\r
- attribute initval of LUT4_55 : label is "0x6996";\r
- attribute initval of LUT4_54 : label is "0x6996";\r
- attribute initval of LUT4_53 : label is "0x6996";\r
- attribute initval of LUT4_52 : label is "0x6996";\r
- attribute initval of LUT4_51 : label is "0x6996";\r
- attribute initval of LUT4_50 : label is "0x6996";\r
- attribute initval of LUT4_49 : label is "0x6996";\r
- attribute initval of LUT4_48 : label is "0x6996";\r
- attribute initval of LUT4_47 : label is "0x6996";\r
- attribute initval of LUT4_46 : label is "0x6996";\r
- attribute initval of LUT4_45 : label is "0x6996";\r
- attribute initval of LUT4_44 : label is "0x6996";\r
- attribute initval of LUT4_43 : label is "0x6996";\r
- attribute initval of LUT4_42 : label is "0x6996";\r
- attribute initval of LUT4_41 : label is "0x6996";\r
- attribute initval of LUT4_40 : label is "0x6996";\r
- attribute initval of LUT4_39 : label is "0x6996";\r
- attribute initval of LUT4_38 : label is "0x6996";\r
- attribute initval of LUT4_37 : label is "0x6996";\r
- attribute initval of LUT4_36 : label is "0x6996";\r
- attribute initval of LUT4_35 : label is "0x6996";\r
- attribute initval of LUT4_34 : label is "0x6996";\r
- attribute initval of LUT4_33 : label is "0x6996";\r
- attribute initval of LUT4_32 : label is "0x6996";\r
- attribute initval of LUT4_31 : label is "0x6996";\r
- attribute initval of LUT4_30 : label is "0x6996";\r
- attribute initval of LUT4_29 : label is "0x6996";\r
- attribute initval of LUT4_28 : label is "0x6996";\r
- attribute initval of LUT4_27 : label is "0x6996";\r
- attribute initval of LUT4_26 : label is "0x6996";\r
- attribute initval of LUT4_25 : label is "0x6996";\r
- attribute initval of LUT4_24 : label is "0x6996";\r
- attribute initval of LUT4_23 : label is "0x6996";\r
- attribute initval of LUT4_22 : label is "0x6996";\r
- attribute initval of LUT4_21 : label is "0x6996";\r
- attribute initval of LUT4_20 : label is "0x6996";\r
- attribute initval of LUT4_19 : label is "0x6996";\r
- attribute initval of LUT4_18 : label is "0x6996";\r
- attribute initval of LUT4_17 : label is "0x6996";\r
- attribute initval of LUT4_16 : label is "0x6996";\r
- attribute initval of LUT4_15 : label is "0x6996";\r
- attribute initval of LUT4_14 : label is "0x6996";\r
- attribute initval of LUT4_13 : label is "0x6996";\r
- attribute initval of LUT4_12 : label is "0x6996";\r
- attribute initval of LUT4_11 : label is "0x6996";\r
- attribute initval of LUT4_10 : label is "0x6996";\r
- attribute initval of LUT4_9 : label is "0x6996";\r
- attribute initval of LUT4_8 : label is "0x6996";\r
- attribute initval of LUT4_7 : label is "0x6996";\r
- attribute initval of LUT4_6 : label is "0x6996";\r
- attribute initval of LUT4_5 : label is "0x6996";\r
- attribute initval of LUT4_4 : label is "0x6996";\r
- attribute initval of LUT4_3 : label is "0x0410";\r
- attribute initval of LUT4_2 : label is "0x1004";\r
- attribute initval of LUT4_1 : label is "0x0140";\r
- attribute initval of LUT4_0 : label is "0x4001";\r
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_0_31 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_1_30 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_1_30 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_1_30 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_1_30 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_1_30 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_1_30 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_1_30 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_1_30 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_1_30 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_0_1_30 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_2_29 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_2_29 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_2_29 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_2_29 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_2_29 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_2_29 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_2_29 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_2_29 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_2_29 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_0_2_29 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_3_28 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_3_28 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_3_28 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_3_28 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_3_28 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_3_28 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_3_28 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_3_28 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_3_28 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_0_3_28 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_4_27 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_4_27 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_4_27 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_4_27 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_4_27 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_4_27 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_4_27 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_4_27 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_4_27 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_0_4_27 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_5_26 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_5_26 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_5_26 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_5_26 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_5_26 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_5_26 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_5_26 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_5_26 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_5_26 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_0_5_26 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_6_25 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_6_25 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_6_25 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_6_25 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_6_25 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_6_25 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_6_25 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_6_25 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_6_25 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_0_6_25 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is "";\r
- attribute CSDECODE_B of pdp_ram_0_7_24 : label is "0b000";\r
- attribute CSDECODE_A of pdp_ram_0_7_24 : label is "0b000";\r
- attribute WRITEMODE_B of pdp_ram_0_7_24 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_0_7_24 : label is "NORMAL";\r
- attribute GSR of pdp_ram_0_7_24 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_0_7_24 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_0_7_24 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_0_7_24 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_0_7_24 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_0_7_24 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is "";\r
- attribute CSDECODE_B of pdp_ram_1_0_23 : label is "0b001";\r
- attribute CSDECODE_A of pdp_ram_1_0_23 : label is "0b001";\r
- attribute WRITEMODE_B of pdp_ram_1_0_23 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_1_0_23 : label is "NORMAL";\r
- attribute GSR of pdp_ram_1_0_23 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_1_0_23 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_1_0_23 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_1_0_23 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_1_0_23 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_1_0_23 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is "";\r
- attribute CSDECODE_B of pdp_ram_1_1_22 : label is "0b001";\r
- attribute CSDECODE_A of pdp_ram_1_1_22 : label is "0b001";\r
- attribute WRITEMODE_B of pdp_ram_1_1_22 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_1_1_22 : label is "NORMAL";\r
- attribute GSR of pdp_ram_1_1_22 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_1_1_22 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_1_1_22 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_1_1_22 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_1_1_22 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_1_1_22 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is "";\r
- attribute CSDECODE_B of pdp_ram_1_2_21 : label is "0b001";\r
- attribute CSDECODE_A of pdp_ram_1_2_21 : label is "0b001";\r
- attribute WRITEMODE_B of pdp_ram_1_2_21 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_1_2_21 : label is "NORMAL";\r
- attribute GSR of pdp_ram_1_2_21 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_1_2_21 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_1_2_21 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_1_2_21 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_1_2_21 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_1_2_21 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is "";\r
- attribute CSDECODE_B of pdp_ram_1_3_20 : label is "0b001";\r
- attribute CSDECODE_A of pdp_ram_1_3_20 : label is "0b001";\r
- attribute WRITEMODE_B of pdp_ram_1_3_20 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_1_3_20 : label is "NORMAL";\r
- attribute GSR of pdp_ram_1_3_20 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_1_3_20 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_1_3_20 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_1_3_20 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_1_3_20 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_1_3_20 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is "";\r
- attribute CSDECODE_B of pdp_ram_1_4_19 : label is "0b001";\r
- attribute CSDECODE_A of pdp_ram_1_4_19 : label is "0b001";\r
- attribute WRITEMODE_B of pdp_ram_1_4_19 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_1_4_19 : label is "NORMAL";\r
- attribute GSR of pdp_ram_1_4_19 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_1_4_19 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_1_4_19 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_1_4_19 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_1_4_19 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_1_4_19 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is "";\r
- attribute CSDECODE_B of pdp_ram_1_5_18 : label is "0b001";\r
- attribute CSDECODE_A of pdp_ram_1_5_18 : label is "0b001";\r
- attribute WRITEMODE_B of pdp_ram_1_5_18 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_1_5_18 : label is "NORMAL";\r
- attribute GSR of pdp_ram_1_5_18 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_1_5_18 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_1_5_18 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_1_5_18 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_1_5_18 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_1_5_18 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is "";\r
- attribute CSDECODE_B of pdp_ram_1_6_17 : label is "0b001";\r
- attribute CSDECODE_A of pdp_ram_1_6_17 : label is "0b001";\r
- attribute WRITEMODE_B of pdp_ram_1_6_17 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_1_6_17 : label is "NORMAL";\r
- attribute GSR of pdp_ram_1_6_17 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_1_6_17 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_1_6_17 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_1_6_17 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_1_6_17 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_1_6_17 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is "";\r
- attribute CSDECODE_B of pdp_ram_1_7_16 : label is "0b001";\r
- attribute CSDECODE_A of pdp_ram_1_7_16 : label is "0b001";\r
- attribute WRITEMODE_B of pdp_ram_1_7_16 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_1_7_16 : label is "NORMAL";\r
- attribute GSR of pdp_ram_1_7_16 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_1_7_16 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_1_7_16 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_1_7_16 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_1_7_16 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_1_7_16 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is "";\r
- attribute CSDECODE_B of pdp_ram_2_0_15 : label is "0b010";\r
- attribute CSDECODE_A of pdp_ram_2_0_15 : label is "0b010";\r
- attribute WRITEMODE_B of pdp_ram_2_0_15 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_2_0_15 : label is "NORMAL";\r
- attribute GSR of pdp_ram_2_0_15 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_2_0_15 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_2_0_15 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_2_0_15 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_2_0_15 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_2_0_15 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is "";\r
- attribute CSDECODE_B of pdp_ram_2_1_14 : label is "0b010";\r
- attribute CSDECODE_A of pdp_ram_2_1_14 : label is "0b010";\r
- attribute WRITEMODE_B of pdp_ram_2_1_14 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_2_1_14 : label is "NORMAL";\r
- attribute GSR of pdp_ram_2_1_14 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_2_1_14 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_2_1_14 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_2_1_14 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_2_1_14 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_2_1_14 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is "";\r
- attribute CSDECODE_B of pdp_ram_2_2_13 : label is "0b010";\r
- attribute CSDECODE_A of pdp_ram_2_2_13 : label is "0b010";\r
- attribute WRITEMODE_B of pdp_ram_2_2_13 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_2_2_13 : label is "NORMAL";\r
- attribute GSR of pdp_ram_2_2_13 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_2_2_13 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_2_2_13 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_2_2_13 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_2_2_13 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_2_2_13 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is "";\r
- attribute CSDECODE_B of pdp_ram_2_3_12 : label is "0b010";\r
- attribute CSDECODE_A of pdp_ram_2_3_12 : label is "0b010";\r
- attribute WRITEMODE_B of pdp_ram_2_3_12 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_2_3_12 : label is "NORMAL";\r
- attribute GSR of pdp_ram_2_3_12 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_2_3_12 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_2_3_12 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_2_3_12 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_2_3_12 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_2_3_12 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is "";\r
- attribute CSDECODE_B of pdp_ram_2_4_11 : label is "0b010";\r
- attribute CSDECODE_A of pdp_ram_2_4_11 : label is "0b010";\r
- attribute WRITEMODE_B of pdp_ram_2_4_11 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_2_4_11 : label is "NORMAL";\r
- attribute GSR of pdp_ram_2_4_11 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_2_4_11 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_2_4_11 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_2_4_11 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_2_4_11 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_2_4_11 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is "";\r
- attribute CSDECODE_B of pdp_ram_2_5_10 : label is "0b010";\r
- attribute CSDECODE_A of pdp_ram_2_5_10 : label is "0b010";\r
- attribute WRITEMODE_B of pdp_ram_2_5_10 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_2_5_10 : label is "NORMAL";\r
- attribute GSR of pdp_ram_2_5_10 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_2_5_10 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_2_5_10 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_2_5_10 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_2_5_10 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_2_5_10 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is "";\r
- attribute CSDECODE_B of pdp_ram_2_6_9 : label is "0b010";\r
- attribute CSDECODE_A of pdp_ram_2_6_9 : label is "0b010";\r
- attribute WRITEMODE_B of pdp_ram_2_6_9 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_2_6_9 : label is "NORMAL";\r
- attribute GSR of pdp_ram_2_6_9 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_2_6_9 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_2_6_9 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_2_6_9 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_2_6_9 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_2_6_9 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is "";\r
- attribute CSDECODE_B of pdp_ram_2_7_8 : label is "0b010";\r
- attribute CSDECODE_A of pdp_ram_2_7_8 : label is "0b010";\r
- attribute WRITEMODE_B of pdp_ram_2_7_8 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_2_7_8 : label is "NORMAL";\r
- attribute GSR of pdp_ram_2_7_8 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_2_7_8 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_2_7_8 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_2_7_8 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_2_7_8 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_2_7_8 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is "";\r
- attribute CSDECODE_B of pdp_ram_3_0_7 : label is "0b011";\r
- attribute CSDECODE_A of pdp_ram_3_0_7 : label is "0b011";\r
- attribute WRITEMODE_B of pdp_ram_3_0_7 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_3_0_7 : label is "NORMAL";\r
- attribute GSR of pdp_ram_3_0_7 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_3_0_7 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_3_0_7 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_3_0_7 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_3_0_7 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_3_0_7 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is "";\r
- attribute CSDECODE_B of pdp_ram_3_1_6 : label is "0b011";\r
- attribute CSDECODE_A of pdp_ram_3_1_6 : label is "0b011";\r
- attribute WRITEMODE_B of pdp_ram_3_1_6 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_3_1_6 : label is "NORMAL";\r
- attribute GSR of pdp_ram_3_1_6 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_3_1_6 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_3_1_6 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_3_1_6 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_3_1_6 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_3_1_6 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is "";\r
- attribute CSDECODE_B of pdp_ram_3_2_5 : label is "0b011";\r
- attribute CSDECODE_A of pdp_ram_3_2_5 : label is "0b011";\r
- attribute WRITEMODE_B of pdp_ram_3_2_5 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_3_2_5 : label is "NORMAL";\r
- attribute GSR of pdp_ram_3_2_5 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_3_2_5 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_3_2_5 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_3_2_5 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_3_2_5 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_3_2_5 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is "";\r
- attribute CSDECODE_B of pdp_ram_3_3_4 : label is "0b011";\r
- attribute CSDECODE_A of pdp_ram_3_3_4 : label is "0b011";\r
- attribute WRITEMODE_B of pdp_ram_3_3_4 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_3_3_4 : label is "NORMAL";\r
- attribute GSR of pdp_ram_3_3_4 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_3_3_4 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_3_3_4 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_3_3_4 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_3_3_4 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_3_3_4 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is "";\r
- attribute CSDECODE_B of pdp_ram_3_4_3 : label is "0b011";\r
- attribute CSDECODE_A of pdp_ram_3_4_3 : label is "0b011";\r
- attribute WRITEMODE_B of pdp_ram_3_4_3 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_3_4_3 : label is "NORMAL";\r
- attribute GSR of pdp_ram_3_4_3 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_3_4_3 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_3_4_3 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_3_4_3 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_3_4_3 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_3_4_3 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is "";\r
- attribute CSDECODE_B of pdp_ram_3_5_2 : label is "0b011";\r
- attribute CSDECODE_A of pdp_ram_3_5_2 : label is "0b011";\r
- attribute WRITEMODE_B of pdp_ram_3_5_2 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_3_5_2 : label is "NORMAL";\r
- attribute GSR of pdp_ram_3_5_2 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_3_5_2 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_3_5_2 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_3_5_2 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_3_5_2 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_3_5_2 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is "";\r
- attribute CSDECODE_B of pdp_ram_3_6_1 : label is "0b011";\r
- attribute CSDECODE_A of pdp_ram_3_6_1 : label is "0b011";\r
- attribute WRITEMODE_B of pdp_ram_3_6_1 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_3_6_1 : label is "NORMAL";\r
- attribute GSR of pdp_ram_3_6_1 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_3_6_1 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_3_6_1 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_3_6_1 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_3_6_1 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_3_6_1 : label is "1";\r
- attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_64kx8.lpc";\r
- attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is "";\r
- attribute CSDECODE_B of pdp_ram_3_7_0 : label is "0b011";\r
- attribute CSDECODE_A of pdp_ram_3_7_0 : label is "0b011";\r
- attribute WRITEMODE_B of pdp_ram_3_7_0 : label is "NORMAL";\r
- attribute WRITEMODE_A of pdp_ram_3_7_0 : label is "NORMAL";\r
- attribute GSR of pdp_ram_3_7_0 : label is "DISABLED";\r
- attribute RESETMODE of pdp_ram_3_7_0 : label is "ASYNC";\r
- attribute REGMODE_B of pdp_ram_3_7_0 : label is "NOREG";\r
- attribute REGMODE_A of pdp_ram_3_7_0 : label is "NOREG";\r
- attribute DATA_WIDTH_B of pdp_ram_3_7_0 : label is "1";\r
- attribute DATA_WIDTH_A of pdp_ram_3_7_0 : label is "1";\r
- attribute GSR of FF_173 : label is "ENABLED";\r
- attribute GSR of FF_172 : label is "ENABLED";\r
- attribute GSR of FF_171 : label is "ENABLED";\r
- attribute GSR of FF_170 : label is "ENABLED";\r
- attribute GSR of FF_169 : label is "ENABLED";\r
- attribute GSR of FF_168 : label is "ENABLED";\r
- attribute GSR of FF_167 : label is "ENABLED";\r
- attribute GSR of FF_166 : label is "ENABLED";\r
- attribute GSR of FF_165 : label is "ENABLED";\r
- attribute GSR of FF_164 : label is "ENABLED";\r
- attribute GSR of FF_163 : label is "ENABLED";\r
- attribute GSR of FF_162 : label is "ENABLED";\r
- attribute GSR of FF_161 : label is "ENABLED";\r
- attribute GSR of FF_160 : label is "ENABLED";\r
- attribute GSR of FF_159 : label is "ENABLED";\r
- attribute GSR of FF_158 : label is "ENABLED";\r
- attribute GSR of FF_157 : label is "ENABLED";\r
- attribute GSR of FF_156 : label is "ENABLED";\r
- attribute GSR of FF_155 : label is "ENABLED";\r
- attribute GSR of FF_154 : label is "ENABLED";\r
- attribute GSR of FF_153 : label is "ENABLED";\r
- attribute GSR of FF_152 : label is "ENABLED";\r
- attribute GSR of FF_151 : label is "ENABLED";\r
- attribute GSR of FF_150 : label is "ENABLED";\r
- attribute GSR of FF_149 : label is "ENABLED";\r
- attribute GSR of FF_148 : label is "ENABLED";\r
- attribute GSR of FF_147 : label is "ENABLED";\r
- attribute GSR of FF_146 : label is "ENABLED";\r
- attribute GSR of FF_145 : label is "ENABLED";\r
- attribute GSR of FF_144 : label is "ENABLED";\r
- attribute GSR of FF_143 : label is "ENABLED";\r
- attribute GSR of FF_142 : label is "ENABLED";\r
- attribute GSR of FF_141 : label is "ENABLED";\r
- attribute GSR of FF_140 : label is "ENABLED";\r
- attribute GSR of FF_139 : label is "ENABLED";\r
- attribute GSR of FF_138 : label is "ENABLED";\r
- attribute GSR of FF_137 : label is "ENABLED";\r
- attribute GSR of FF_136 : label is "ENABLED";\r
- attribute GSR of FF_135 : label is "ENABLED";\r
- attribute GSR of FF_134 : label is "ENABLED";\r
- attribute GSR of FF_133 : label is "ENABLED";\r
- attribute GSR of FF_132 : label is "ENABLED";\r
- attribute GSR of FF_131 : label is "ENABLED";\r
- attribute GSR of FF_130 : label is "ENABLED";\r
- attribute GSR of FF_129 : label is "ENABLED";\r
- attribute GSR of FF_128 : label is "ENABLED";\r
- attribute GSR of FF_127 : label is "ENABLED";\r
- attribute GSR of FF_126 : label is "ENABLED";\r
- attribute GSR of FF_125 : label is "ENABLED";\r
- attribute GSR of FF_124 : label is "ENABLED";\r
- attribute GSR of FF_123 : label is "ENABLED";\r
- attribute GSR of FF_122 : label is "ENABLED";\r
- attribute GSR of FF_121 : label is "ENABLED";\r
- attribute GSR of FF_120 : label is "ENABLED";\r
- attribute GSR of FF_119 : label is "ENABLED";\r
- attribute GSR of FF_118 : label is "ENABLED";\r
- attribute GSR of FF_117 : label is "ENABLED";\r
- attribute GSR of FF_116 : label is "ENABLED";\r
- attribute GSR of FF_115 : label is "ENABLED";\r
- attribute GSR of FF_114 : label is "ENABLED";\r
- attribute GSR of FF_113 : label is "ENABLED";\r
- attribute GSR of FF_112 : label is "ENABLED";\r
- attribute GSR of FF_111 : label is "ENABLED";\r
- attribute GSR of FF_110 : label is "ENABLED";\r
- attribute GSR of FF_109 : label is "ENABLED";\r
- attribute GSR of FF_108 : label is "ENABLED";\r
- attribute GSR of FF_107 : label is "ENABLED";\r
- attribute GSR of FF_106 : label is "ENABLED";\r
- attribute GSR of FF_105 : label is "ENABLED";\r
- attribute GSR of FF_104 : label is "ENABLED";\r
- attribute GSR of FF_103 : label is "ENABLED";\r
- attribute GSR of FF_102 : label is "ENABLED";\r
- attribute GSR of FF_101 : label is "ENABLED";\r
- attribute GSR of FF_100 : label is "ENABLED";\r
- attribute GSR of FF_99 : label is "ENABLED";\r
- attribute GSR of FF_98 : label is "ENABLED";\r
- attribute GSR of FF_97 : label is "ENABLED";\r
- attribute GSR of FF_96 : label is "ENABLED";\r
- attribute GSR of FF_95 : label is "ENABLED";\r
- attribute GSR of FF_94 : label is "ENABLED";\r
- attribute GSR of FF_93 : label is "ENABLED";\r
- attribute GSR of FF_92 : label is "ENABLED";\r
- attribute GSR of FF_91 : label is "ENABLED";\r
- attribute GSR of FF_90 : label is "ENABLED";\r
- attribute GSR of FF_89 : label is "ENABLED";\r
- attribute GSR of FF_88 : label is "ENABLED";\r
- attribute GSR of FF_87 : label is "ENABLED";\r
- attribute GSR of FF_86 : label is "ENABLED";\r
- attribute GSR of FF_85 : label is "ENABLED";\r
- attribute GSR of FF_84 : label is "ENABLED";\r
- attribute GSR of FF_83 : label is "ENABLED";\r
- attribute GSR of FF_82 : label is "ENABLED";\r
- attribute GSR of FF_81 : label is "ENABLED";\r
- attribute GSR of FF_80 : label is "ENABLED";\r
- attribute GSR of FF_79 : label is "ENABLED";\r
- attribute GSR of FF_78 : label is "ENABLED";\r
- attribute GSR of FF_77 : label is "ENABLED";\r
- attribute GSR of FF_76 : label is "ENABLED";\r
- attribute GSR of FF_75 : label is "ENABLED";\r
- attribute GSR of FF_74 : label is "ENABLED";\r
- attribute GSR of FF_73 : label is "ENABLED";\r
- attribute GSR of FF_72 : label is "ENABLED";\r
- attribute GSR of FF_71 : label is "ENABLED";\r
- attribute GSR of FF_70 : label is "ENABLED";\r
- attribute GSR of FF_69 : label is "ENABLED";\r
- attribute GSR of FF_68 : label is "ENABLED";\r
- attribute GSR of FF_67 : label is "ENABLED";\r
- attribute GSR of FF_66 : label is "ENABLED";\r
- attribute GSR of FF_65 : label is "ENABLED";\r
- attribute GSR of FF_64 : label is "ENABLED";\r
- attribute GSR of FF_63 : label is "ENABLED";\r
- attribute GSR of FF_62 : label is "ENABLED";\r
- attribute GSR of FF_61 : label is "ENABLED";\r
- attribute GSR of FF_60 : label is "ENABLED";\r
- attribute GSR of FF_59 : label is "ENABLED";\r
- attribute GSR of FF_58 : label is "ENABLED";\r
- attribute GSR of FF_57 : label is "ENABLED";\r
- attribute GSR of FF_56 : label is "ENABLED";\r
- attribute GSR of FF_55 : label is "ENABLED";\r
- attribute GSR of FF_54 : label is "ENABLED";\r
- attribute GSR of FF_53 : label is "ENABLED";\r
- attribute GSR of FF_52 : label is "ENABLED";\r
- attribute GSR of FF_51 : label is "ENABLED";\r
- attribute GSR of FF_50 : label is "ENABLED";\r
- attribute GSR of FF_49 : label is "ENABLED";\r
- attribute GSR of FF_48 : label is "ENABLED";\r
- attribute GSR of FF_47 : label is "ENABLED";\r
- attribute GSR of FF_46 : label is "ENABLED";\r
- attribute GSR of FF_45 : label is "ENABLED";\r
- attribute GSR of FF_44 : label is "ENABLED";\r
- attribute GSR of FF_43 : label is "ENABLED";\r
- attribute GSR of FF_42 : label is "ENABLED";\r
- attribute GSR of FF_41 : label is "ENABLED";\r
- attribute GSR of FF_40 : label is "ENABLED";\r
- attribute GSR of FF_39 : label is "ENABLED";\r
- attribute GSR of FF_38 : label is "ENABLED";\r
- attribute GSR of FF_37 : label is "ENABLED";\r
- attribute GSR of FF_36 : label is "ENABLED";\r
- attribute GSR of FF_35 : label is "ENABLED";\r
- attribute GSR of FF_34 : label is "ENABLED";\r
- attribute GSR of FF_33 : label is "ENABLED";\r
- attribute GSR of FF_32 : label is "ENABLED";\r
- attribute GSR of FF_31 : label is "ENABLED";\r
- attribute GSR of FF_30 : label is "ENABLED";\r
- attribute GSR of FF_29 : label is "ENABLED";\r
- attribute GSR of FF_28 : label is "ENABLED";\r
- attribute GSR of FF_27 : label is "ENABLED";\r
- attribute GSR of FF_26 : label is "ENABLED";\r
- attribute GSR of FF_25 : label is "ENABLED";\r
- attribute GSR of FF_24 : label is "ENABLED";\r
- attribute GSR of FF_23 : label is "ENABLED";\r
- attribute GSR of FF_22 : label is "ENABLED";\r
- attribute GSR of FF_21 : label is "ENABLED";\r
- attribute GSR of FF_20 : label is "ENABLED";\r
- attribute GSR of FF_19 : label is "ENABLED";\r
- attribute GSR of FF_18 : label is "ENABLED";\r
- attribute GSR of FF_17 : label is "ENABLED";\r
- attribute GSR of FF_16 : label is "ENABLED";\r
- attribute GSR of FF_15 : label is "ENABLED";\r
- attribute GSR of FF_14 : label is "ENABLED";\r
- attribute GSR of FF_13 : label is "ENABLED";\r
- attribute GSR of FF_12 : label is "ENABLED";\r
- attribute GSR of FF_11 : label is "ENABLED";\r
- attribute GSR of FF_10 : label is "ENABLED";\r
- attribute GSR of FF_9 : label is "ENABLED";\r
- attribute GSR of FF_8 : label is "ENABLED";\r
- attribute GSR of FF_7 : label is "ENABLED";\r
- attribute GSR of FF_6 : label is "ENABLED";\r
- attribute GSR of FF_5 : label is "ENABLED";\r
- attribute GSR of FF_4 : label is "ENABLED";\r
- attribute GSR of FF_3 : label is "ENABLED";\r
- attribute GSR of FF_2 : label is "ENABLED";\r
- attribute GSR of FF_1 : label is "ENABLED";\r
- attribute GSR of FF_0 : label is "ENABLED";\r
- attribute syn_keep : boolean;\r
-\r
-begin\r
- -- component instantiation statements\r
- AND2_t34: AND2\r
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);\r
-\r
- INV_1: INV\r
- port map (A=>full_i, Z=>invout_1);\r
-\r
- AND2_t33: AND2\r
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);\r
-\r
- INV_0: INV\r
- port map (A=>empty_i, Z=>invout_0);\r
-\r
- OR2_t32: OR2\r
- port map (A=>Reset, B=>RPReset, Z=>rRst);\r
-\r
- XOR2_t31: XOR2\r
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);\r
-\r
- XOR2_t30: XOR2\r
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);\r
-\r
- XOR2_t29: XOR2\r
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);\r
-\r
- XOR2_t28: XOR2\r
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);\r
-\r
- XOR2_t27: XOR2\r
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);\r
-\r
- XOR2_t26: XOR2\r
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);\r
-\r
- XOR2_t25: XOR2\r
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);\r
-\r
- XOR2_t24: XOR2\r
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);\r
-\r
- XOR2_t23: XOR2\r
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);\r
-\r
- XOR2_t22: XOR2\r
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);\r
-\r
- XOR2_t21: XOR2\r
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);\r
-\r
- XOR2_t20: XOR2\r
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);\r
-\r
- XOR2_t19: XOR2\r
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);\r
-\r
- XOR2_t18: XOR2\r
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);\r
-\r
- XOR2_t17: XOR2\r
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);\r
-\r
- XOR2_t16: XOR2\r
- port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15);\r
-\r
- XOR2_t15: XOR2\r
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);\r
-\r
- XOR2_t14: XOR2\r
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);\r
-\r
- XOR2_t13: XOR2\r
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);\r
-\r
- XOR2_t12: XOR2\r
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);\r
-\r
- XOR2_t11: XOR2\r
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);\r
-\r
- XOR2_t10: XOR2\r
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);\r
-\r
- XOR2_t9: XOR2\r
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);\r
-\r
- XOR2_t8: XOR2\r
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);\r
-\r
- XOR2_t7: XOR2\r
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);\r
-\r
- XOR2_t6: XOR2\r
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);\r
-\r
- XOR2_t5: XOR2\r
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);\r
-\r
- XOR2_t4: XOR2\r
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);\r
-\r
- XOR2_t3: XOR2\r
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);\r
-\r
- XOR2_t2: XOR2\r
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);\r
-\r
- XOR2_t1: XOR2\r
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);\r
-\r
- XOR2_t0: XOR2\r
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);\r
-\r
- LUT4_59: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, \r
- AD1=>w_gcount_r215, AD0=>w_gcount_r216, \r
- DO0=>w_g2b_xor_cluster_0);\r
-\r
- LUT4_58: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, \r
- AD1=>w_gcount_r211, AD0=>w_gcount_r212, \r
- DO0=>w_g2b_xor_cluster_1);\r
-\r
- LUT4_57: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, \r
- AD1=>w_gcount_r27, AD0=>w_gcount_r28, \r
- DO0=>w_g2b_xor_cluster_2);\r
-\r
- LUT4_56: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, \r
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, \r
- DO0=>w_g2b_xor_cluster_3);\r
-\r
- LUT4_55: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>wcount_r15);\r
-\r
- LUT4_54: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, \r
- AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14);\r
-\r
- LUT4_53: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, \r
- AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12);\r
-\r
- LUT4_52: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, \r
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);\r
-\r
- LUT4_51: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, \r
- AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, \r
- DO0=>wcount_r10);\r
-\r
- LUT4_50: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9);\r
-\r
- LUT4_49: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8);\r
-\r
- LUT4_48: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7);\r
-\r
- LUT4_47: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, \r
- AD1=>w_gcount_r28, AD0=>scuba_vlo, \r
- DO0=>w_g2b_xor_cluster_2_1);\r
-\r
- LUT4_46: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6);\r
-\r
- LUT4_45: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5);\r
-\r
- LUT4_44: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4);\r
-\r
- LUT4_43: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);\r
-\r
- LUT4_42: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, \r
- DO0=>wcount_r3);\r
-\r
- LUT4_41: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, \r
- AD1=>w_gcount_r24, AD0=>scuba_vlo, \r
- DO0=>w_g2b_xor_cluster_3_2);\r
-\r
- LUT4_40: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, \r
- DO0=>wcount_r2);\r
-\r
- LUT4_39: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, \r
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, \r
- DO0=>wcount_r1);\r
-\r
- LUT4_38: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, \r
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet);\r
-\r
- LUT4_37: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, \r
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1);\r
-\r
- LUT4_36: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, \r
- AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2);\r
-\r
- LUT4_35: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, \r
- AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3);\r
-\r
- LUT4_34: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);\r
-\r
- LUT4_33: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, \r
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, \r
- DO0=>func_xor_inet_5);\r
-\r
- LUT4_32: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0);\r
-\r
- LUT4_31: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, \r
- AD1=>r_gcount_w215, AD0=>r_gcount_w216, \r
- DO0=>r_g2b_xor_cluster_0);\r
-\r
- LUT4_30: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, \r
- AD1=>r_gcount_w211, AD0=>r_gcount_w212, \r
- DO0=>r_g2b_xor_cluster_1);\r
-\r
- LUT4_29: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, \r
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, \r
- DO0=>r_g2b_xor_cluster_2);\r
-\r
- LUT4_28: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, \r
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, \r
- DO0=>r_g2b_xor_cluster_3);\r
-\r
- LUT4_27: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>rcount_w15);\r
-\r
- LUT4_26: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, \r
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);\r
-\r
- LUT4_25: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, \r
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);\r
-\r
- LUT4_24: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, \r
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);\r
-\r
- LUT4_23: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, \r
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, \r
- DO0=>rcount_w10);\r
-\r
- LUT4_22: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);\r
-\r
- LUT4_21: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);\r
-\r
- LUT4_20: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);\r
-\r
- LUT4_19: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, \r
- AD1=>r_gcount_w28, AD0=>scuba_vlo, \r
- DO0=>r_g2b_xor_cluster_2_1);\r
-\r
- LUT4_18: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);\r
-\r
- LUT4_17: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);\r
-\r
- LUT4_16: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);\r
-\r
- LUT4_15: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);\r
-\r
- LUT4_14: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, \r
- DO0=>rcount_w3);\r
-\r
- LUT4_13: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, \r
- AD1=>r_gcount_w24, AD0=>scuba_vlo, \r
- DO0=>r_g2b_xor_cluster_3_2);\r
-\r
- LUT4_12: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, \r
- DO0=>rcount_w2);\r
-\r
- LUT4_11: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, \r
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, \r
- DO0=>rcount_w1);\r
-\r
- LUT4_10: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, \r
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6);\r
-\r
- LUT4_9: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, \r
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7);\r
-\r
- LUT4_8: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, \r
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8);\r
-\r
- LUT4_7: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, \r
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9);\r
-\r
- LUT4_6: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, \r
- AD0=>scuba_vlo, DO0=>func_xor_inet_10);\r
-\r
- LUT4_5: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, \r
- AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, \r
- DO0=>func_xor_inet_11);\r
-\r
- LUT4_4: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x6996")\r
- -- synopsys translate_on\r
- port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, \r
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);\r
-\r
- LUT4_3: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x0410")\r
- -- synopsys translate_on\r
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, \r
- AD0=>scuba_vlo, DO0=>empty_cmp_set);\r
-\r
- LUT4_2: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x1004")\r
- -- synopsys translate_on\r
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, \r
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);\r
-\r
- LUT4_1: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x0140")\r
- -- synopsys translate_on\r
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, \r
- AD0=>scuba_vlo, DO0=>full_cmp_set);\r
-\r
- LUT4_0: ROM16X1\r
- -- synopsys translate_off\r
- generic map (initval=> "0x4001")\r
- -- synopsys translate_on\r
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, \r
- AD0=>scuba_vlo, DO0=>full_cmp_clr);\r
-\r
- pdp_ram_0_0_31: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_0_0, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_0_1_30: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_0_1, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_0_2_29: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_0_2, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_0_3_28: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_0_3, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_0_4_27: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_0_4, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_0_5_26: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_0_5, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_0_6_25: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_0_6, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_0_7_24: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_0_7, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_1_0_23: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_1_0, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_1_1_22: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_1_1, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_1_2_21: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_1_2, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_1_3_20: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_1_3, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_1_4_19: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_1_4, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_1_5_18: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_1_5, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_1_6_17: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_1_6, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_1_7_16: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_1_7, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_2_0_15: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_2_0, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_2_1_14: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_2_1, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_2_2_13: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_2_2, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_2_3_12: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_2_3, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_2_4_11: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_2_4, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_2_5_10: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_2_5, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_2_6_9: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_2_6, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_2_7_8: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_2_7, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_3_0_7: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_3_0, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_3_1_6: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_3_1, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_3_2_5: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_3_2, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_3_3_4: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_3_3, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_3_4_3: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_3_4, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_3_5_2: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_3_5, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_3_6_1: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_3_6, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- pdp_ram_3_7_0: DP16KB\r
- -- synopsys translate_off\r
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, \r
- DATA_WIDTH_A=> 1)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, \r
- ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, \r
- ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, \r
- ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, \r
- WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, \r
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, \r
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, \r
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, \r
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, \r
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, \r
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, \r
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, \r
- ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, \r
- ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, \r
- ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, \r
- ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, \r
- CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, \r
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, \r
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>mdout1_3_7, DOB1=>open, DOB2=>open, DOB3=>open, \r
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, \r
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, \r
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, \r
- DOB17=>open);\r
-\r
- FF_173: FD1P3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, \r
- Q=>wcount_0);\r
-\r
- FF_172: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_1);\r
-\r
- FF_171: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_2);\r
-\r
- FF_170: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_3);\r
-\r
- FF_169: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_4);\r
-\r
- FF_168: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_5);\r
-\r
- FF_167: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_6);\r
-\r
- FF_166: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_7);\r
-\r
- FF_165: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_8);\r
-\r
- FF_164: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_9);\r
-\r
- FF_163: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_10);\r
-\r
- FF_162: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_11);\r
-\r
- FF_161: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_12);\r
-\r
- FF_160: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_13);\r
-\r
- FF_159: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_14);\r
-\r
- FF_158: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_15);\r
-\r
- FF_157: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wcount_16);\r
-\r
- FF_156: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_0);\r
-\r
- FF_155: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_1);\r
-\r
- FF_154: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_2);\r
-\r
- FF_153: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_3);\r
-\r
- FF_152: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_4);\r
-\r
- FF_151: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_5);\r
-\r
- FF_150: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_6);\r
-\r
- FF_149: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_7);\r
-\r
- FF_148: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_8);\r
-\r
- FF_147: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_9);\r
-\r
- FF_146: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_10);\r
-\r
- FF_145: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_11);\r
-\r
- FF_144: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_12);\r
-\r
- FF_143: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_13);\r
-\r
- FF_142: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_14);\r
-\r
- FF_141: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_15);\r
-\r
- FF_140: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>w_gcount_16);\r
-\r
- FF_139: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_0);\r
-\r
- FF_138: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_1);\r
-\r
- FF_137: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_2);\r
-\r
- FF_136: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_3);\r
-\r
- FF_135: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_4);\r
-\r
- FF_134: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_5);\r
-\r
- FF_133: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_6);\r
-\r
- FF_132: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_7);\r
-\r
- FF_131: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_8);\r
-\r
- FF_130: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_9);\r
-\r
- FF_129: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_10);\r
-\r
- FF_128: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_11);\r
-\r
- FF_127: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_12);\r
-\r
- FF_126: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_13);\r
-\r
- FF_125: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_14);\r
-\r
- FF_124: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_15);\r
-\r
- FF_123: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, \r
- Q=>wptr_16);\r
-\r
- FF_122: FD1P3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, \r
- Q=>rcount_0);\r
-\r
- FF_121: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_1);\r
-\r
- FF_120: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_2);\r
-\r
- FF_119: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_3);\r
-\r
- FF_118: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_4);\r
-\r
- FF_117: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_5);\r
-\r
- FF_116: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_6);\r
-\r
- FF_115: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_7);\r
-\r
- FF_114: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_8);\r
-\r
- FF_113: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_9);\r
-\r
- FF_112: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_10);\r
-\r
- FF_111: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_11);\r
-\r
- FF_110: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_12);\r
-\r
- FF_109: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_13);\r
-\r
- FF_108: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_14);\r
-\r
- FF_107: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_15);\r
-\r
- FF_106: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rcount_16);\r
-\r
- FF_105: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_0);\r
-\r
- FF_104: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_1);\r
-\r
- FF_103: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_2);\r
-\r
- FF_102: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_3);\r
-\r
- FF_101: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_4);\r
-\r
- FF_100: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_5);\r
-\r
- FF_99: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_6);\r
-\r
- FF_98: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_7);\r
-\r
- FF_97: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_8);\r
-\r
- FF_96: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_9);\r
-\r
- FF_95: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_10);\r
-\r
- FF_94: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_11);\r
-\r
- FF_93: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_12);\r
-\r
- FF_92: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_13);\r
-\r
- FF_91: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_14);\r
-\r
- FF_90: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_15);\r
-\r
- FF_89: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>r_gcount_16);\r
-\r
- FF_88: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_0);\r
-\r
- FF_87: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_1);\r
-\r
- FF_86: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_2);\r
-\r
- FF_85: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_3);\r
-\r
- FF_84: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_4);\r
-\r
- FF_83: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_5);\r
-\r
- FF_82: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_6);\r
-\r
- FF_81: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_7);\r
-\r
- FF_80: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_8);\r
-\r
- FF_79: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_9);\r
-\r
- FF_78: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_10);\r
-\r
- FF_77: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_11);\r
-\r
- FF_76: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_12);\r
-\r
- FF_75: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_13);\r
-\r
- FF_74: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_14);\r
-\r
- FF_73: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_15);\r
-\r
- FF_72: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, \r
- Q=>rptr_16);\r
-\r
- FF_71: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, \r
- Q=>rptr_14_ff);\r
-\r
- FF_70: FD1P3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, \r
- Q=>rptr_15_ff);\r
-\r
- FF_69: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);\r
-\r
- FF_68: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);\r
-\r
- FF_67: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);\r
-\r
- FF_66: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);\r
-\r
- FF_65: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);\r
-\r
- FF_64: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);\r
-\r
- FF_63: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);\r
-\r
- FF_62: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);\r
-\r
- FF_61: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);\r
-\r
- FF_60: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);\r
-\r
- FF_59: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r10);\r
-\r
- FF_58: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r11);\r
-\r
- FF_57: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r12);\r
-\r
- FF_56: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r13);\r
-\r
- FF_55: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r14);\r
-\r
- FF_54: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r15);\r
-\r
- FF_53: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r16);\r
-\r
- FF_52: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);\r
-\r
- FF_51: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);\r
-\r
- FF_50: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);\r
-\r
- FF_49: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);\r
-\r
- FF_48: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);\r
-\r
- FF_47: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);\r
-\r
- FF_46: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);\r
-\r
- FF_45: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);\r
-\r
- FF_44: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);\r
-\r
- FF_43: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);\r
-\r
- FF_42: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);\r
-\r
- FF_41: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);\r
-\r
- FF_40: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);\r
-\r
- FF_39: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);\r
-\r
- FF_38: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);\r
-\r
- FF_37: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);\r
-\r
- FF_36: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);\r
-\r
- FF_35: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r20);\r
-\r
- FF_34: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r21);\r
-\r
- FF_33: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r22);\r
-\r
- FF_32: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r23);\r
-\r
- FF_31: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r24);\r
-\r
- FF_30: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r25);\r
-\r
- FF_29: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r26);\r
-\r
- FF_28: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r27);\r
-\r
- FF_27: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r28);\r
-\r
- FF_26: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r29);\r
-\r
- FF_25: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r210);\r
-\r
- FF_24: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r211);\r
-\r
- FF_23: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r212);\r
-\r
- FF_22: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r213);\r
-\r
- FF_21: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r214);\r
-\r
- FF_20: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r215);\r
-\r
- FF_19: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, \r
- Q=>w_gcount_r216);\r
-\r
- FF_18: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);\r
-\r
- FF_17: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);\r
-\r
- FF_16: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);\r
-\r
- FF_15: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);\r
-\r
- FF_14: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);\r
-\r
- FF_13: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);\r
-\r
- FF_12: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);\r
-\r
- FF_11: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);\r
-\r
- FF_10: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);\r
-\r
- FF_9: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);\r
-\r
- FF_8: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w210);\r
-\r
- FF_7: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w211);\r
-\r
- FF_6: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w212);\r
-\r
- FF_5: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w213);\r
-\r
- FF_4: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w214);\r
-\r
- FF_3: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w215);\r
-\r
- FF_2: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, \r
- Q=>r_gcount_w216);\r
-\r
- FF_1: FD1S3BX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);\r
-\r
- FF_0: FD1S3DX\r
- -- synopsys translate_off\r
- generic map (GSR=> "ENABLED")\r
- -- synopsys translate_on\r
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);\r
-\r
- w_gctr_cia: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, \r
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, \r
- S1=>open);\r
-\r
- w_gctr_0: CU2\r
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, \r
- NC0=>iwcount_0, NC1=>iwcount_1);\r
-\r
- w_gctr_1: CU2\r
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, \r
- NC0=>iwcount_2, NC1=>iwcount_3);\r
-\r
- w_gctr_2: CU2\r
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, \r
- NC0=>iwcount_4, NC1=>iwcount_5);\r
-\r
- w_gctr_3: CU2\r
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, \r
- NC0=>iwcount_6, NC1=>iwcount_7);\r
-\r
- w_gctr_4: CU2\r
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, \r
- NC0=>iwcount_8, NC1=>iwcount_9);\r
-\r
- w_gctr_5: CU2\r
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, \r
- NC0=>iwcount_10, NC1=>iwcount_11);\r
-\r
- w_gctr_6: CU2\r
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, \r
- NC0=>iwcount_12, NC1=>iwcount_13);\r
-\r
- w_gctr_7: CU2\r
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, \r
- NC0=>iwcount_14, NC1=>iwcount_15);\r
-\r
- w_gctr_8: CU2\r
- port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, \r
- NC0=>iwcount_16, NC1=>open);\r
-\r
- scuba_vhi_inst: VHI\r
- port map (Z=>scuba_vhi);\r
-\r
- r_gctr_cia: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, \r
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, \r
- S1=>open);\r
-\r
- r_gctr_0: CU2\r
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, \r
- NC0=>ircount_0, NC1=>ircount_1);\r
-\r
- r_gctr_1: CU2\r
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, \r
- NC0=>ircount_2, NC1=>ircount_3);\r
-\r
- r_gctr_2: CU2\r
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, \r
- NC0=>ircount_4, NC1=>ircount_5);\r
-\r
- r_gctr_3: CU2\r
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, \r
- NC0=>ircount_6, NC1=>ircount_7);\r
-\r
- r_gctr_4: CU2\r
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, \r
- NC0=>ircount_8, NC1=>ircount_9);\r
-\r
- r_gctr_5: CU2\r
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, \r
- NC0=>ircount_10, NC1=>ircount_11);\r
-\r
- r_gctr_6: CU2\r
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, \r
- NC0=>ircount_12, NC1=>ircount_13);\r
-\r
- r_gctr_7: CU2\r
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, \r
- NC0=>ircount_14, NC1=>ircount_15);\r
-\r
- r_gctr_8: CU2\r
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, \r
- NC0=>ircount_16, NC1=>open);\r
-\r
- mux_7: MUX41\r
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, \r
- D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0));\r
-\r
- mux_6: MUX41\r
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, \r
- D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1));\r
-\r
- mux_5: MUX41\r
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, \r
- D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2));\r
-\r
- mux_4: MUX41\r
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, \r
- D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3));\r
-\r
- mux_3: MUX41\r
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, \r
- D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4));\r
-\r
- mux_2: MUX41\r
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, \r
- D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5));\r
-\r
- mux_1: MUX41\r
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, \r
- D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6));\r
-\r
- mux_0: MUX41\r
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, \r
- D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7));\r
-\r
- empty_cmp_ci_a: FADD2B\r
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, \r
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);\r
-\r
- empty_cmp_0: AGEB2\r
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, \r
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);\r
-\r
- empty_cmp_1: AGEB2\r
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, \r
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);\r
-\r
- empty_cmp_2: AGEB2\r
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, \r
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);\r
-\r
- empty_cmp_3: AGEB2\r
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, \r
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);\r
-\r
- empty_cmp_4: AGEB2\r
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, \r
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);\r
-\r
- empty_cmp_5: AGEB2\r
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, \r
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);\r
-\r
- empty_cmp_6: AGEB2\r
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, \r
- B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2);\r
-\r
- empty_cmp_7: AGEB2\r
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, \r
- B1=>wcount_r15, CI=>co6_2, GE=>co7_2);\r
-\r
- empty_cmp_8: AGEB2\r
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, \r
- B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c);\r
-\r
- a0: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, \r
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, \r
- S1=>open);\r
-\r
- full_cmp_ci_a: FADD2B\r
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, \r
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);\r
-\r
- full_cmp_0: AGEB2\r
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, \r
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);\r
-\r
- full_cmp_1: AGEB2\r
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, \r
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);\r
-\r
- full_cmp_2: AGEB2\r
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, \r
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);\r
-\r
- full_cmp_3: AGEB2\r
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, \r
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);\r
-\r
- full_cmp_4: AGEB2\r
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, \r
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);\r
-\r
- full_cmp_5: AGEB2\r
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, \r
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);\r
-\r
- full_cmp_6: AGEB2\r
- port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, \r
- B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3);\r
-\r
- full_cmp_7: AGEB2\r
- port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, \r
- B1=>rcount_w15, CI=>co6_3, GE=>co7_3);\r
-\r
- full_cmp_8: AGEB2\r
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, \r
- B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c);\r
-\r
- scuba_vlo_inst: VLO\r
- port map (Z=>scuba_vlo);\r
-\r
- a1: FADD2B\r
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, \r
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, \r
- S1=>open);\r
-\r
- Empty <= empty_i;\r
- Full <= full_i;\r
-end Structure;\r
-\r
--- synopsys translate_off\r
-library ecp2m;\r
-configuration Structure_CON of fifo_64kx8 is\r
- for Structure\r
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;\r
- for all:AND2 use entity ecp2m.AND2(V); end for;\r
- for all:CU2 use entity ecp2m.CU2(V); end for;\r
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;\r
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;\r
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;\r
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;\r
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;\r
- for all:INV use entity ecp2m.INV(V); end for;\r
- for all:MUX41 use entity ecp2m.MUX41(V); end for;\r
- for all:OR2 use entity ecp2m.OR2(V); end for;\r
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;\r
- for all:VHI use entity ecp2m.VHI(V); end for;\r
- for all:VLO use entity ecp2m.VLO(V); end for;\r
- for all:XOR2 use entity ecp2m.XOR2(V); end for;\r
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;\r
- end for;\r
-end Structure_CON;\r
-\r
--- synopsys translate_on\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)\r
--- Module Version: 5.2\r
--- Sat Dec 26 00:12:05 2009\r
-\r
--- parameterized module component declaration\r
-component fifo_64kx8\r
- port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; \r
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; \r
- Reset: in std_logic; RPReset: in std_logic; \r
- Q: out std_logic_vector(7 downto 0); Empty: out std_logic; \r
- Full: out std_logic);\r
-end component;\r
-\r
--- parameterized module component instance\r
-__ : fifo_64kx8\r
- port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, \r
- RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, \r
- Full=>__);\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_64kx9" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 01 18 18:38:47.674" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="fifo_64kx9.lpc" type="lpc" modified="2018 01 18 18:38:41.000"/>
- <File name="fifo_64kx9.vhd" type="top_level_vhdl" modified="2018 01 18 18:38:41.000"/>
- <File name="fifo_64kx9_tmpl.vhd" type="template_vhdl" modified="2018 01 18 18:38:41.000"/>
- <File name="tb_fifo_64kx9_tmpl.vhd" type="testbench_vhdl" modified="2018 01 18 18:38:41.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp2m
-PartType=LFE2M100E
-PartName=LFE2M100E-5F1152C
-SpeedGrade=5
-Package=FPBGA1152
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.8
-ModuleName=fifo_64kx9
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=01/18/2018
-Time=18:38:41
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=65536
-Width=9
-RDepth=65536
-RWidth=9
-regout=0
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
-
-[Command]
-cmd_line= -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1
+++ /dev/null
-SCUBA, Version Diamond (64-bit) 3.9.1.119
-Thu Jan 18 18:38:41 2018
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1
- Circuit name : fifo_64kx9
- Module type : ebfifo
- Module Version : 5.8
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : fifo_64kx9.edn
- VHDL output : fifo_64kx9.vhd
- VHDL template : fifo_64kx9_tmpl.vhd
- VHDL testbench : tb_fifo_64kx9_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_64kx9.srp
- Element Usage :
- AGEB2 : 18
- AND2 : 2
- CU2 : 18
- FADD2B : 6
- FD1P3BX : 2
- FD1P3DX : 105
- FD1S3BX : 1
- FD1S3DX : 69
- INV : 12
- MUX321 : 9
- OR2 : 1
- ROM16X1 : 188
- XOR2 : 32
- DP16KB : 32
- Estimated Resource Usage:
- LUT : 379
- EBR : 32
- Reg : 177
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119
--- Module Version: 5.8
---/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1
-
--- Thu Jan 18 18:38:41 2018
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity fifo_64kx9 is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_64kx9;
-
-architecture Structure of fifo_64kx9 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal func_and_inet: std_logic;
- signal func_and_inet_1: std_logic;
- signal func_and_inet_2: std_logic;
- signal func_and_inet_3: std_logic;
- signal func_and_inet_4: std_logic;
- signal func_and_inet_5: std_logic;
- signal func_and_inet_6: std_logic;
- signal func_and_inet_7: std_logic;
- signal func_and_inet_8: std_logic;
- signal func_and_inet_9: std_logic;
- signal func_and_inet_10: std_logic;
- signal func_and_inet_11: std_logic;
- signal func_and_inet_12: std_logic;
- signal func_and_inet_13: std_logic;
- signal func_and_inet_14: std_logic;
- signal func_and_inet_15: std_logic;
- signal func_and_inet_16: std_logic;
- signal func_and_inet_17: std_logic;
- signal func_and_inet_18: std_logic;
- signal func_and_inet_19: std_logic;
- signal func_and_inet_20: std_logic;
- signal func_and_inet_21: std_logic;
- signal func_and_inet_22: std_logic;
- signal func_and_inet_23: std_logic;
- signal func_and_inet_24: std_logic;
- signal func_and_inet_25: std_logic;
- signal func_and_inet_26: std_logic;
- signal func_and_inet_27: std_logic;
- signal func_and_inet_28: std_logic;
- signal func_and_inet_29: std_logic;
- signal wptr_15_inv: std_logic;
- signal func_and_inet_30: std_logic;
- signal rptr_15_inv: std_logic;
- signal func_and_inet_31: std_logic;
- signal func_and_inet_32: std_logic;
- signal func_and_inet_33: std_logic;
- signal func_and_inet_34: std_logic;
- signal func_and_inet_35: std_logic;
- signal func_and_inet_36: std_logic;
- signal func_and_inet_37: std_logic;
- signal func_and_inet_38: std_logic;
- signal func_and_inet_39: std_logic;
- signal func_and_inet_40: std_logic;
- signal func_and_inet_41: std_logic;
- signal func_and_inet_42: std_logic;
- signal func_and_inet_43: std_logic;
- signal func_and_inet_44: std_logic;
- signal func_and_inet_45: std_logic;
- signal wptr_14_inv: std_logic;
- signal func_and_inet_46: std_logic;
- signal rptr_14_inv: std_logic;
- signal func_and_inet_47: std_logic;
- signal func_and_inet_48: std_logic;
- signal func_and_inet_49: std_logic;
- signal func_and_inet_50: std_logic;
- signal func_and_inet_51: std_logic;
- signal func_and_inet_52: std_logic;
- signal func_and_inet_53: std_logic;
- signal wptr_13_inv: std_logic;
- signal func_and_inet_54: std_logic;
- signal rptr_13_inv: std_logic;
- signal func_and_inet_55: std_logic;
- signal func_and_inet_56: std_logic;
- signal func_and_inet_57: std_logic;
- signal wptr_12_inv: std_logic;
- signal func_and_inet_58: std_logic;
- signal rptr_12_inv: std_logic;
- signal func_and_inet_59: std_logic;
- signal wptr_11_inv: std_logic;
- signal func_and_inet_60: std_logic;
- signal rptr_11_inv: std_logic;
- signal func_and_inet_61: std_logic;
- signal func_and_inet_62: std_logic;
- signal func_and_inet_63: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_3_1: std_logic;
- signal w_g2b_xor_cluster_3_2: std_logic;
- signal w_g2b_xor_cluster_3: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_3: std_logic;
- signal func_xor_inet_2: std_logic;
- signal func_xor_inet_1: std_logic;
- signal func_xor_inet: std_logic;
- signal func_xor_inet_4: std_logic;
- signal func_xor_inet_5: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_3_1: std_logic;
- signal r_g2b_xor_cluster_3_2: std_logic;
- signal r_g2b_xor_cluster_3: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal func_xor_inet_9: std_logic;
- signal func_xor_inet_8: std_logic;
- signal func_xor_inet_7: std_logic;
- signal func_xor_inet_6: std_logic;
- signal func_xor_inet_10: std_logic;
- signal func_xor_inet_11: std_logic;
- signal dec1_r10: std_logic;
- signal dec0_p00: std_logic;
- signal dec3_r11: std_logic;
- signal dec2_p01: std_logic;
- signal dec5_r12: std_logic;
- signal dec4_p02: std_logic;
- signal dec7_r13: std_logic;
- signal dec6_p03: std_logic;
- signal dec9_r14: std_logic;
- signal dec8_p04: std_logic;
- signal dec11_r15: std_logic;
- signal dec10_p05: std_logic;
- signal dec13_r16: std_logic;
- signal dec12_p06: std_logic;
- signal dec15_r17: std_logic;
- signal dec14_p07: std_logic;
- signal dec17_r18: std_logic;
- signal dec16_p08: std_logic;
- signal dec19_r19: std_logic;
- signal dec18_p09: std_logic;
- signal dec21_r110: std_logic;
- signal dec20_p010: std_logic;
- signal dec23_r111: std_logic;
- signal dec22_p011: std_logic;
- signal dec25_r112: std_logic;
- signal dec24_p012: std_logic;
- signal dec27_r113: std_logic;
- signal dec26_p013: std_logic;
- signal dec29_r114: std_logic;
- signal dec28_p014: std_logic;
- signal dec31_r115: std_logic;
- signal dec30_p015: std_logic;
- signal dec33_r116: std_logic;
- signal dec32_p016: std_logic;
- signal dec35_r117: std_logic;
- signal dec34_p017: std_logic;
- signal dec37_r118: std_logic;
- signal dec36_p018: std_logic;
- signal dec39_r119: std_logic;
- signal dec38_p019: std_logic;
- signal dec41_r120: std_logic;
- signal dec40_p020: std_logic;
- signal dec43_r121: std_logic;
- signal dec42_p021: std_logic;
- signal dec45_r122: std_logic;
- signal dec44_p022: std_logic;
- signal dec47_r123: std_logic;
- signal dec46_p023: std_logic;
- signal dec49_r124: std_logic;
- signal dec48_p024: std_logic;
- signal dec51_r125: std_logic;
- signal dec50_p025: std_logic;
- signal dec53_r126: std_logic;
- signal dec52_p026: std_logic;
- signal dec55_r127: std_logic;
- signal dec54_p027: std_logic;
- signal dec57_r128: std_logic;
- signal dec56_p028: std_logic;
- signal dec59_r129: std_logic;
- signal dec58_p029: std_logic;
- signal dec61_r130: std_logic;
- signal dec60_p030: std_logic;
- signal dec63_r131: std_logic;
- signal dec62_p031: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal w_gdata_12: std_logic;
- signal w_gdata_13: std_logic;
- signal w_gdata_14: std_logic;
- signal w_gdata_15: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal wptr_13: std_logic;
- signal wptr_14: std_logic;
- signal wptr_15: std_logic;
- signal wptr_16: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal r_gdata_12: std_logic;
- signal r_gdata_13: std_logic;
- signal r_gdata_14: std_logic;
- signal r_gdata_15: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_16: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal rptr_13: std_logic;
- signal rptr_14: std_logic;
- signal rptr_15: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal w_gcount_13: std_logic;
- signal w_gcount_14: std_logic;
- signal w_gcount_15: std_logic;
- signal w_gcount_16: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal r_gcount_13: std_logic;
- signal r_gcount_14: std_logic;
- signal r_gcount_15: std_logic;
- signal r_gcount_16: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal w_gcount_r213: std_logic;
- signal w_gcount_r13: std_logic;
- signal w_gcount_r214: std_logic;
- signal w_gcount_r14: std_logic;
- signal w_gcount_r215: std_logic;
- signal w_gcount_r15: std_logic;
- signal w_gcount_r216: std_logic;
- signal w_gcount_r16: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal r_gcount_w213: std_logic;
- signal r_gcount_w13: std_logic;
- signal r_gcount_w214: std_logic;
- signal r_gcount_w14: std_logic;
- signal r_gcount_w215: std_logic;
- signal r_gcount_w15: std_logic;
- signal r_gcount_w216: std_logic;
- signal r_gcount_w16: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal iwcount_13: std_logic;
- signal co5: std_logic;
- signal iwcount_14: std_logic;
- signal iwcount_15: std_logic;
- signal co6: std_logic;
- signal iwcount_16: std_logic;
- signal co8: std_logic;
- signal co7: std_logic;
- signal wcount_16: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal ircount_13: std_logic;
- signal co5_1: std_logic;
- signal ircount_14: std_logic;
- signal ircount_15: std_logic;
- signal co6_1: std_logic;
- signal ircount_16: std_logic;
- signal co8_1: std_logic;
- signal co7_1: std_logic;
- signal rcount_16: std_logic;
- signal mdout1_31_0: std_logic;
- signal mdout1_30_0: std_logic;
- signal mdout1_29_0: std_logic;
- signal mdout1_28_0: std_logic;
- signal mdout1_27_0: std_logic;
- signal mdout1_26_0: std_logic;
- signal mdout1_25_0: std_logic;
- signal mdout1_24_0: std_logic;
- signal mdout1_23_0: std_logic;
- signal mdout1_22_0: std_logic;
- signal mdout1_21_0: std_logic;
- signal mdout1_20_0: std_logic;
- signal mdout1_19_0: std_logic;
- signal mdout1_18_0: std_logic;
- signal mdout1_17_0: std_logic;
- signal mdout1_16_0: std_logic;
- signal mdout1_15_0: std_logic;
- signal mdout1_14_0: std_logic;
- signal mdout1_13_0: std_logic;
- signal mdout1_12_0: std_logic;
- signal mdout1_11_0: std_logic;
- signal mdout1_10_0: std_logic;
- signal mdout1_9_0: std_logic;
- signal mdout1_8_0: std_logic;
- signal mdout1_7_0: std_logic;
- signal mdout1_6_0: std_logic;
- signal mdout1_5_0: std_logic;
- signal mdout1_4_0: std_logic;
- signal mdout1_3_0: std_logic;
- signal mdout1_2_0: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_31_1: std_logic;
- signal mdout1_30_1: std_logic;
- signal mdout1_29_1: std_logic;
- signal mdout1_28_1: std_logic;
- signal mdout1_27_1: std_logic;
- signal mdout1_26_1: std_logic;
- signal mdout1_25_1: std_logic;
- signal mdout1_24_1: std_logic;
- signal mdout1_23_1: std_logic;
- signal mdout1_22_1: std_logic;
- signal mdout1_21_1: std_logic;
- signal mdout1_20_1: std_logic;
- signal mdout1_19_1: std_logic;
- signal mdout1_18_1: std_logic;
- signal mdout1_17_1: std_logic;
- signal mdout1_16_1: std_logic;
- signal mdout1_15_1: std_logic;
- signal mdout1_14_1: std_logic;
- signal mdout1_13_1: std_logic;
- signal mdout1_12_1: std_logic;
- signal mdout1_11_1: std_logic;
- signal mdout1_10_1: std_logic;
- signal mdout1_9_1: std_logic;
- signal mdout1_8_1: std_logic;
- signal mdout1_7_1: std_logic;
- signal mdout1_6_1: std_logic;
- signal mdout1_5_1: std_logic;
- signal mdout1_4_1: std_logic;
- signal mdout1_3_1: std_logic;
- signal mdout1_2_1: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_31_2: std_logic;
- signal mdout1_30_2: std_logic;
- signal mdout1_29_2: std_logic;
- signal mdout1_28_2: std_logic;
- signal mdout1_27_2: std_logic;
- signal mdout1_26_2: std_logic;
- signal mdout1_25_2: std_logic;
- signal mdout1_24_2: std_logic;
- signal mdout1_23_2: std_logic;
- signal mdout1_22_2: std_logic;
- signal mdout1_21_2: std_logic;
- signal mdout1_20_2: std_logic;
- signal mdout1_19_2: std_logic;
- signal mdout1_18_2: std_logic;
- signal mdout1_17_2: std_logic;
- signal mdout1_16_2: std_logic;
- signal mdout1_15_2: std_logic;
- signal mdout1_14_2: std_logic;
- signal mdout1_13_2: std_logic;
- signal mdout1_12_2: std_logic;
- signal mdout1_11_2: std_logic;
- signal mdout1_10_2: std_logic;
- signal mdout1_9_2: std_logic;
- signal mdout1_8_2: std_logic;
- signal mdout1_7_2: std_logic;
- signal mdout1_6_2: std_logic;
- signal mdout1_5_2: std_logic;
- signal mdout1_4_2: std_logic;
- signal mdout1_3_2: std_logic;
- signal mdout1_2_2: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_31_3: std_logic;
- signal mdout1_30_3: std_logic;
- signal mdout1_29_3: std_logic;
- signal mdout1_28_3: std_logic;
- signal mdout1_27_3: std_logic;
- signal mdout1_26_3: std_logic;
- signal mdout1_25_3: std_logic;
- signal mdout1_24_3: std_logic;
- signal mdout1_23_3: std_logic;
- signal mdout1_22_3: std_logic;
- signal mdout1_21_3: std_logic;
- signal mdout1_20_3: std_logic;
- signal mdout1_19_3: std_logic;
- signal mdout1_18_3: std_logic;
- signal mdout1_17_3: std_logic;
- signal mdout1_16_3: std_logic;
- signal mdout1_15_3: std_logic;
- signal mdout1_14_3: std_logic;
- signal mdout1_13_3: std_logic;
- signal mdout1_12_3: std_logic;
- signal mdout1_11_3: std_logic;
- signal mdout1_10_3: std_logic;
- signal mdout1_9_3: std_logic;
- signal mdout1_8_3: std_logic;
- signal mdout1_7_3: std_logic;
- signal mdout1_6_3: std_logic;
- signal mdout1_5_3: std_logic;
- signal mdout1_4_3: std_logic;
- signal mdout1_3_3: std_logic;
- signal mdout1_2_3: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_31_4: std_logic;
- signal mdout1_30_4: std_logic;
- signal mdout1_29_4: std_logic;
- signal mdout1_28_4: std_logic;
- signal mdout1_27_4: std_logic;
- signal mdout1_26_4: std_logic;
- signal mdout1_25_4: std_logic;
- signal mdout1_24_4: std_logic;
- signal mdout1_23_4: std_logic;
- signal mdout1_22_4: std_logic;
- signal mdout1_21_4: std_logic;
- signal mdout1_20_4: std_logic;
- signal mdout1_19_4: std_logic;
- signal mdout1_18_4: std_logic;
- signal mdout1_17_4: std_logic;
- signal mdout1_16_4: std_logic;
- signal mdout1_15_4: std_logic;
- signal mdout1_14_4: std_logic;
- signal mdout1_13_4: std_logic;
- signal mdout1_12_4: std_logic;
- signal mdout1_11_4: std_logic;
- signal mdout1_10_4: std_logic;
- signal mdout1_9_4: std_logic;
- signal mdout1_8_4: std_logic;
- signal mdout1_7_4: std_logic;
- signal mdout1_6_4: std_logic;
- signal mdout1_5_4: std_logic;
- signal mdout1_4_4: std_logic;
- signal mdout1_3_4: std_logic;
- signal mdout1_2_4: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_31_5: std_logic;
- signal mdout1_30_5: std_logic;
- signal mdout1_29_5: std_logic;
- signal mdout1_28_5: std_logic;
- signal mdout1_27_5: std_logic;
- signal mdout1_26_5: std_logic;
- signal mdout1_25_5: std_logic;
- signal mdout1_24_5: std_logic;
- signal mdout1_23_5: std_logic;
- signal mdout1_22_5: std_logic;
- signal mdout1_21_5: std_logic;
- signal mdout1_20_5: std_logic;
- signal mdout1_19_5: std_logic;
- signal mdout1_18_5: std_logic;
- signal mdout1_17_5: std_logic;
- signal mdout1_16_5: std_logic;
- signal mdout1_15_5: std_logic;
- signal mdout1_14_5: std_logic;
- signal mdout1_13_5: std_logic;
- signal mdout1_12_5: std_logic;
- signal mdout1_11_5: std_logic;
- signal mdout1_10_5: std_logic;
- signal mdout1_9_5: std_logic;
- signal mdout1_8_5: std_logic;
- signal mdout1_7_5: std_logic;
- signal mdout1_6_5: std_logic;
- signal mdout1_5_5: std_logic;
- signal mdout1_4_5: std_logic;
- signal mdout1_3_5: std_logic;
- signal mdout1_2_5: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_31_6: std_logic;
- signal mdout1_30_6: std_logic;
- signal mdout1_29_6: std_logic;
- signal mdout1_28_6: std_logic;
- signal mdout1_27_6: std_logic;
- signal mdout1_26_6: std_logic;
- signal mdout1_25_6: std_logic;
- signal mdout1_24_6: std_logic;
- signal mdout1_23_6: std_logic;
- signal mdout1_22_6: std_logic;
- signal mdout1_21_6: std_logic;
- signal mdout1_20_6: std_logic;
- signal mdout1_19_6: std_logic;
- signal mdout1_18_6: std_logic;
- signal mdout1_17_6: std_logic;
- signal mdout1_16_6: std_logic;
- signal mdout1_15_6: std_logic;
- signal mdout1_14_6: std_logic;
- signal mdout1_13_6: std_logic;
- signal mdout1_12_6: std_logic;
- signal mdout1_11_6: std_logic;
- signal mdout1_10_6: std_logic;
- signal mdout1_9_6: std_logic;
- signal mdout1_8_6: std_logic;
- signal mdout1_7_6: std_logic;
- signal mdout1_6_6: std_logic;
- signal mdout1_5_6: std_logic;
- signal mdout1_4_6: std_logic;
- signal mdout1_3_6: std_logic;
- signal mdout1_2_6: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_31_7: std_logic;
- signal mdout1_30_7: std_logic;
- signal mdout1_29_7: std_logic;
- signal mdout1_28_7: std_logic;
- signal mdout1_27_7: std_logic;
- signal mdout1_26_7: std_logic;
- signal mdout1_25_7: std_logic;
- signal mdout1_24_7: std_logic;
- signal mdout1_23_7: std_logic;
- signal mdout1_22_7: std_logic;
- signal mdout1_21_7: std_logic;
- signal mdout1_20_7: std_logic;
- signal mdout1_19_7: std_logic;
- signal mdout1_18_7: std_logic;
- signal mdout1_17_7: std_logic;
- signal mdout1_16_7: std_logic;
- signal mdout1_15_7: std_logic;
- signal mdout1_14_7: std_logic;
- signal mdout1_13_7: std_logic;
- signal mdout1_12_7: std_logic;
- signal mdout1_11_7: std_logic;
- signal mdout1_10_7: std_logic;
- signal mdout1_9_7: std_logic;
- signal mdout1_8_7: std_logic;
- signal mdout1_7_7: std_logic;
- signal mdout1_6_7: std_logic;
- signal mdout1_5_7: std_logic;
- signal mdout1_4_7: std_logic;
- signal mdout1_3_7: std_logic;
- signal mdout1_2_7: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_15_ff: std_logic;
- signal rptr_14_ff: std_logic;
- signal rptr_13_ff: std_logic;
- signal rptr_12_ff: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_31_8: std_logic;
- signal mdout1_30_8: std_logic;
- signal mdout1_29_8: std_logic;
- signal mdout1_28_8: std_logic;
- signal mdout1_27_8: std_logic;
- signal mdout1_26_8: std_logic;
- signal mdout1_25_8: std_logic;
- signal mdout1_24_8: std_logic;
- signal mdout1_23_8: std_logic;
- signal mdout1_22_8: std_logic;
- signal mdout1_21_8: std_logic;
- signal mdout1_20_8: std_logic;
- signal mdout1_19_8: std_logic;
- signal mdout1_18_8: std_logic;
- signal mdout1_17_8: std_logic;
- signal mdout1_16_8: std_logic;
- signal mdout1_15_8: std_logic;
- signal mdout1_14_8: std_logic;
- signal mdout1_13_8: std_logic;
- signal mdout1_12_8: std_logic;
- signal mdout1_11_8: std_logic;
- signal mdout1_10_8: std_logic;
- signal mdout1_9_8: std_logic;
- signal mdout1_8_8: std_logic;
- signal mdout1_7_8: std_logic;
- signal mdout1_6_8: std_logic;
- signal mdout1_5_8: std_logic;
- signal mdout1_4_8: std_logic;
- signal mdout1_3_8: std_logic;
- signal mdout1_2_8: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal wcount_r9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal wcount_r12: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_12: std_logic;
- signal rcount_13: std_logic;
- signal co6_2: std_logic;
- signal wcount_r14: std_logic;
- signal wcount_r15: std_logic;
- signal rcount_14: std_logic;
- signal rcount_15: std_logic;
- signal co7_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal rcount_w12: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_12: std_logic;
- signal wcount_13: std_logic;
- signal co6_3: std_logic;
- signal rcount_w14: std_logic;
- signal rcount_w15: std_logic;
- signal wcount_14: std_logic;
- signal wcount_15: std_logic;
- signal co7_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX321
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; D8: in std_logic;
- D9: in std_logic; D10: in std_logic; D11: in std_logic;
- D12: in std_logic; D13: in std_logic; D14: in std_logic;
- D15: in std_logic; D16: in std_logic; D17: in std_logic;
- D18: in std_logic; D19: in std_logic; D20: in std_logic;
- D21: in std_logic; D22: in std_logic; D23: in std_logic;
- D24: in std_logic; D25: in std_logic; D26: in std_logic;
- D27: in std_logic; D28: in std_logic; D29: in std_logic;
- D30: in std_logic; D31: in std_logic; SD1: in std_logic;
- SD2: in std_logic; SD3: in std_logic; SD4: in std_logic;
- SD5: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
- attribute initval of LUT4_187 : label is "0x8000";
- attribute initval of LUT4_186 : label is "0x8000";
- attribute initval of LUT4_185 : label is "0x8000";
- attribute initval of LUT4_184 : label is "0x8000";
- attribute initval of LUT4_183 : label is "0x8000";
- attribute initval of LUT4_182 : label is "0x8000";
- attribute initval of LUT4_181 : label is "0x8000";
- attribute initval of LUT4_180 : label is "0x8000";
- attribute initval of LUT4_179 : label is "0x8000";
- attribute initval of LUT4_178 : label is "0x8000";
- attribute initval of LUT4_177 : label is "0x8000";
- attribute initval of LUT4_176 : label is "0x8000";
- attribute initval of LUT4_175 : label is "0x8000";
- attribute initval of LUT4_174 : label is "0x8000";
- attribute initval of LUT4_173 : label is "0x8000";
- attribute initval of LUT4_172 : label is "0x8000";
- attribute initval of LUT4_171 : label is "0x8000";
- attribute initval of LUT4_170 : label is "0x8000";
- attribute initval of LUT4_169 : label is "0x8000";
- attribute initval of LUT4_168 : label is "0x8000";
- attribute initval of LUT4_167 : label is "0x8000";
- attribute initval of LUT4_166 : label is "0x8000";
- attribute initval of LUT4_165 : label is "0x8000";
- attribute initval of LUT4_164 : label is "0x8000";
- attribute initval of LUT4_163 : label is "0x8000";
- attribute initval of LUT4_162 : label is "0x8000";
- attribute initval of LUT4_161 : label is "0x8000";
- attribute initval of LUT4_160 : label is "0x8000";
- attribute initval of LUT4_159 : label is "0x8000";
- attribute initval of LUT4_158 : label is "0x8000";
- attribute initval of LUT4_157 : label is "0x8000";
- attribute initval of LUT4_156 : label is "0x8000";
- attribute initval of LUT4_155 : label is "0x8000";
- attribute initval of LUT4_154 : label is "0x8000";
- attribute initval of LUT4_153 : label is "0x8000";
- attribute initval of LUT4_152 : label is "0x8000";
- attribute initval of LUT4_151 : label is "0x8000";
- attribute initval of LUT4_150 : label is "0x8000";
- attribute initval of LUT4_149 : label is "0x8000";
- attribute initval of LUT4_148 : label is "0x8000";
- attribute initval of LUT4_147 : label is "0x8000";
- attribute initval of LUT4_146 : label is "0x8000";
- attribute initval of LUT4_145 : label is "0x8000";
- attribute initval of LUT4_144 : label is "0x8000";
- attribute initval of LUT4_143 : label is "0x8000";
- attribute initval of LUT4_142 : label is "0x8000";
- attribute initval of LUT4_141 : label is "0x8000";
- attribute initval of LUT4_140 : label is "0x8000";
- attribute initval of LUT4_139 : label is "0x8000";
- attribute initval of LUT4_138 : label is "0x8000";
- attribute initval of LUT4_137 : label is "0x8000";
- attribute initval of LUT4_136 : label is "0x8000";
- attribute initval of LUT4_135 : label is "0x8000";
- attribute initval of LUT4_134 : label is "0x8000";
- attribute initval of LUT4_133 : label is "0x8000";
- attribute initval of LUT4_132 : label is "0x8000";
- attribute initval of LUT4_131 : label is "0x8000";
- attribute initval of LUT4_130 : label is "0x8000";
- attribute initval of LUT4_129 : label is "0x8000";
- attribute initval of LUT4_128 : label is "0x8000";
- attribute initval of LUT4_127 : label is "0x8000";
- attribute initval of LUT4_126 : label is "0x8000";
- attribute initval of LUT4_125 : label is "0x8000";
- attribute initval of LUT4_124 : label is "0x8000";
- attribute initval of LUT4_123 : label is "0x8000";
- attribute initval of LUT4_122 : label is "0x8000";
- attribute initval of LUT4_121 : label is "0x8000";
- attribute initval of LUT4_120 : label is "0x8000";
- attribute initval of LUT4_119 : label is "0x8000";
- attribute initval of LUT4_118 : label is "0x8000";
- attribute initval of LUT4_117 : label is "0x8000";
- attribute initval of LUT4_116 : label is "0x8000";
- attribute initval of LUT4_115 : label is "0x8000";
- attribute initval of LUT4_114 : label is "0x8000";
- attribute initval of LUT4_113 : label is "0x8000";
- attribute initval of LUT4_112 : label is "0x8000";
- attribute initval of LUT4_111 : label is "0x8000";
- attribute initval of LUT4_110 : label is "0x8000";
- attribute initval of LUT4_109 : label is "0x8000";
- attribute initval of LUT4_108 : label is "0x8000";
- attribute initval of LUT4_107 : label is "0x8000";
- attribute initval of LUT4_106 : label is "0x8000";
- attribute initval of LUT4_105 : label is "0x8000";
- attribute initval of LUT4_104 : label is "0x8000";
- attribute initval of LUT4_103 : label is "0x8000";
- attribute initval of LUT4_102 : label is "0x8000";
- attribute initval of LUT4_101 : label is "0x8000";
- attribute initval of LUT4_100 : label is "0x8000";
- attribute initval of LUT4_99 : label is "0x8000";
- attribute initval of LUT4_98 : label is "0x8000";
- attribute initval of LUT4_97 : label is "0x8000";
- attribute initval of LUT4_96 : label is "0x8000";
- attribute initval of LUT4_95 : label is "0x8000";
- attribute initval of LUT4_94 : label is "0x8000";
- attribute initval of LUT4_93 : label is "0x8000";
- attribute initval of LUT4_92 : label is "0x8000";
- attribute initval of LUT4_91 : label is "0x8000";
- attribute initval of LUT4_90 : label is "0x8000";
- attribute initval of LUT4_89 : label is "0x8000";
- attribute initval of LUT4_88 : label is "0x8000";
- attribute initval of LUT4_87 : label is "0x8000";
- attribute initval of LUT4_86 : label is "0x8000";
- attribute initval of LUT4_85 : label is "0x8000";
- attribute initval of LUT4_84 : label is "0x8000";
- attribute initval of LUT4_83 : label is "0x8000";
- attribute initval of LUT4_82 : label is "0x8000";
- attribute initval of LUT4_81 : label is "0x8000";
- attribute initval of LUT4_80 : label is "0x8000";
- attribute initval of LUT4_79 : label is "0x8000";
- attribute initval of LUT4_78 : label is "0x8000";
- attribute initval of LUT4_77 : label is "0x8000";
- attribute initval of LUT4_76 : label is "0x8000";
- attribute initval of LUT4_75 : label is "0x8000";
- attribute initval of LUT4_74 : label is "0x8000";
- attribute initval of LUT4_73 : label is "0x8000";
- attribute initval of LUT4_72 : label is "0x8000";
- attribute initval of LUT4_71 : label is "0x8000";
- attribute initval of LUT4_70 : label is "0x8000";
- attribute initval of LUT4_69 : label is "0x8000";
- attribute initval of LUT4_68 : label is "0x8000";
- attribute initval of LUT4_67 : label is "0x8000";
- attribute initval of LUT4_66 : label is "0x8000";
- attribute initval of LUT4_65 : label is "0x8000";
- attribute initval of LUT4_64 : label is "0x8000";
- attribute initval of LUT4_63 : label is "0x8000";
- attribute initval of LUT4_62 : label is "0x8000";
- attribute initval of LUT4_61 : label is "0x8000";
- attribute initval of LUT4_60 : label is "0x8000";
- attribute initval of LUT4_59 : label is "0x6996";
- attribute initval of LUT4_58 : label is "0x6996";
- attribute initval of LUT4_57 : label is "0x6996";
- attribute initval of LUT4_56 : label is "0x6996";
- attribute initval of LUT4_55 : label is "0x6996";
- attribute initval of LUT4_54 : label is "0x6996";
- attribute initval of LUT4_53 : label is "0x6996";
- attribute initval of LUT4_52 : label is "0x6996";
- attribute initval of LUT4_51 : label is "0x6996";
- attribute initval of LUT4_50 : label is "0x6996";
- attribute initval of LUT4_49 : label is "0x6996";
- attribute initval of LUT4_48 : label is "0x6996";
- attribute initval of LUT4_47 : label is "0x6996";
- attribute initval of LUT4_46 : label is "0x6996";
- attribute initval of LUT4_45 : label is "0x6996";
- attribute initval of LUT4_44 : label is "0x6996";
- attribute initval of LUT4_43 : label is "0x6996";
- attribute initval of LUT4_42 : label is "0x6996";
- attribute initval of LUT4_41 : label is "0x6996";
- attribute initval of LUT4_40 : label is "0x6996";
- attribute initval of LUT4_39 : label is "0x6996";
- attribute initval of LUT4_38 : label is "0x6996";
- attribute initval of LUT4_37 : label is "0x6996";
- attribute initval of LUT4_36 : label is "0x6996";
- attribute initval of LUT4_35 : label is "0x6996";
- attribute initval of LUT4_34 : label is "0x6996";
- attribute initval of LUT4_33 : label is "0x6996";
- attribute initval of LUT4_32 : label is "0x6996";
- attribute initval of LUT4_31 : label is "0x6996";
- attribute initval of LUT4_30 : label is "0x6996";
- attribute initval of LUT4_29 : label is "0x6996";
- attribute initval of LUT4_28 : label is "0x6996";
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x6996";
- attribute initval of LUT4_6 : label is "0x6996";
- attribute initval of LUT4_5 : label is "0x6996";
- attribute initval of LUT4_4 : label is "0x6996";
- attribute initval of LUT4_3 : label is "0x0410";
- attribute initval of LUT4_2 : label is "0x1004";
- attribute initval of LUT4_1 : label is "0x0140";
- attribute initval of LUT4_0 : label is "0x4001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
- attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL";
- attribute GSR of pdp_ram_0_0_31 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is "";
- attribute CSDECODE_B of pdp_ram_1_0_30 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_1_0_30 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_1_0_30 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_1_0_30 : label is "NORMAL";
- attribute GSR of pdp_ram_1_0_30 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_1_0_30 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_1_0_30 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_1_0_30 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_1_0_30 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_1_0_30 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is "";
- attribute CSDECODE_B of pdp_ram_2_0_29 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_2_0_29 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_2_0_29 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_2_0_29 : label is "NORMAL";
- attribute GSR of pdp_ram_2_0_29 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_2_0_29 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_2_0_29 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_2_0_29 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_2_0_29 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_2_0_29 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is "";
- attribute CSDECODE_B of pdp_ram_3_0_28 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_3_0_28 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_3_0_28 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_3_0_28 : label is "NORMAL";
- attribute GSR of pdp_ram_3_0_28 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_3_0_28 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_3_0_28 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_3_0_28 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_3_0_28 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_3_0_28 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is "";
- attribute CSDECODE_B of pdp_ram_4_0_27 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_4_0_27 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_4_0_27 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_4_0_27 : label is "NORMAL";
- attribute GSR of pdp_ram_4_0_27 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_4_0_27 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_4_0_27 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_4_0_27 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_4_0_27 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_4_0_27 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is "";
- attribute CSDECODE_B of pdp_ram_5_0_26 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_5_0_26 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_5_0_26 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_5_0_26 : label is "NORMAL";
- attribute GSR of pdp_ram_5_0_26 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_5_0_26 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_5_0_26 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_5_0_26 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_5_0_26 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_5_0_26 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is "";
- attribute CSDECODE_B of pdp_ram_6_0_25 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_6_0_25 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_6_0_25 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_6_0_25 : label is "NORMAL";
- attribute GSR of pdp_ram_6_0_25 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_6_0_25 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_6_0_25 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_6_0_25 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_6_0_25 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_6_0_25 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is "";
- attribute CSDECODE_B of pdp_ram_7_0_24 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_7_0_24 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_7_0_24 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_7_0_24 : label is "NORMAL";
- attribute GSR of pdp_ram_7_0_24 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_7_0_24 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_7_0_24 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_7_0_24 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_7_0_24 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_7_0_24 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is "";
- attribute CSDECODE_B of pdp_ram_8_0_23 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_8_0_23 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_8_0_23 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_8_0_23 : label is "NORMAL";
- attribute GSR of pdp_ram_8_0_23 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_8_0_23 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_8_0_23 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_8_0_23 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_8_0_23 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_8_0_23 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is "";
- attribute CSDECODE_B of pdp_ram_9_0_22 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_9_0_22 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_9_0_22 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_9_0_22 : label is "NORMAL";
- attribute GSR of pdp_ram_9_0_22 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_9_0_22 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_9_0_22 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_9_0_22 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_9_0_22 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_9_0_22 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is "";
- attribute CSDECODE_B of pdp_ram_10_0_21 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_10_0_21 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_10_0_21 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_10_0_21 : label is "NORMAL";
- attribute GSR of pdp_ram_10_0_21 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_10_0_21 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_10_0_21 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_10_0_21 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_10_0_21 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_10_0_21 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is "";
- attribute CSDECODE_B of pdp_ram_11_0_20 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_11_0_20 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_11_0_20 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_11_0_20 : label is "NORMAL";
- attribute GSR of pdp_ram_11_0_20 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_11_0_20 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_11_0_20 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_11_0_20 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_11_0_20 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_11_0_20 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is "";
- attribute CSDECODE_B of pdp_ram_12_0_19 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_12_0_19 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_12_0_19 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_12_0_19 : label is "NORMAL";
- attribute GSR of pdp_ram_12_0_19 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_12_0_19 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_12_0_19 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_12_0_19 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_12_0_19 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_12_0_19 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is "";
- attribute CSDECODE_B of pdp_ram_13_0_18 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_13_0_18 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_13_0_18 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_13_0_18 : label is "NORMAL";
- attribute GSR of pdp_ram_13_0_18 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_13_0_18 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_13_0_18 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_13_0_18 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_13_0_18 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_13_0_18 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is "";
- attribute CSDECODE_B of pdp_ram_14_0_17 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_14_0_17 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_14_0_17 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_14_0_17 : label is "NORMAL";
- attribute GSR of pdp_ram_14_0_17 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_14_0_17 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_14_0_17 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_14_0_17 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_14_0_17 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_14_0_17 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is "";
- attribute CSDECODE_B of pdp_ram_15_0_16 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_15_0_16 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_15_0_16 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_15_0_16 : label is "NORMAL";
- attribute GSR of pdp_ram_15_0_16 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_15_0_16 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_15_0_16 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_15_0_16 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_15_0_16 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_15_0_16 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is "";
- attribute CSDECODE_B of pdp_ram_16_0_15 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_16_0_15 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_16_0_15 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_16_0_15 : label is "NORMAL";
- attribute GSR of pdp_ram_16_0_15 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_16_0_15 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_16_0_15 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_16_0_15 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_16_0_15 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_16_0_15 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is "";
- attribute CSDECODE_B of pdp_ram_17_0_14 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_17_0_14 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_17_0_14 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_17_0_14 : label is "NORMAL";
- attribute GSR of pdp_ram_17_0_14 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_17_0_14 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_17_0_14 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_17_0_14 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_17_0_14 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_17_0_14 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is "";
- attribute CSDECODE_B of pdp_ram_18_0_13 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_18_0_13 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_18_0_13 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_18_0_13 : label is "NORMAL";
- attribute GSR of pdp_ram_18_0_13 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_18_0_13 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_18_0_13 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_18_0_13 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_18_0_13 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_18_0_13 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is "";
- attribute CSDECODE_B of pdp_ram_19_0_12 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_19_0_12 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_19_0_12 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_19_0_12 : label is "NORMAL";
- attribute GSR of pdp_ram_19_0_12 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_19_0_12 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_19_0_12 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_19_0_12 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_19_0_12 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_19_0_12 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is "";
- attribute CSDECODE_B of pdp_ram_20_0_11 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_20_0_11 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_20_0_11 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_20_0_11 : label is "NORMAL";
- attribute GSR of pdp_ram_20_0_11 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_20_0_11 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_20_0_11 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_20_0_11 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_20_0_11 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_20_0_11 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is "";
- attribute CSDECODE_B of pdp_ram_21_0_10 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_21_0_10 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_21_0_10 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_21_0_10 : label is "NORMAL";
- attribute GSR of pdp_ram_21_0_10 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_21_0_10 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_21_0_10 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_21_0_10 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_21_0_10 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_21_0_10 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is "";
- attribute CSDECODE_B of pdp_ram_22_0_9 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_22_0_9 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_22_0_9 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_22_0_9 : label is "NORMAL";
- attribute GSR of pdp_ram_22_0_9 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_22_0_9 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_22_0_9 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_22_0_9 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_22_0_9 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_22_0_9 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is "";
- attribute CSDECODE_B of pdp_ram_23_0_8 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_23_0_8 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_23_0_8 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_23_0_8 : label is "NORMAL";
- attribute GSR of pdp_ram_23_0_8 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_23_0_8 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_23_0_8 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_23_0_8 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_23_0_8 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_23_0_8 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is "";
- attribute CSDECODE_B of pdp_ram_24_0_7 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_24_0_7 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_24_0_7 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_24_0_7 : label is "NORMAL";
- attribute GSR of pdp_ram_24_0_7 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_24_0_7 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_24_0_7 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_24_0_7 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_24_0_7 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_24_0_7 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is "";
- attribute CSDECODE_B of pdp_ram_25_0_6 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_25_0_6 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_25_0_6 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_25_0_6 : label is "NORMAL";
- attribute GSR of pdp_ram_25_0_6 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_25_0_6 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_25_0_6 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_25_0_6 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_25_0_6 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_25_0_6 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is "";
- attribute CSDECODE_B of pdp_ram_26_0_5 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_26_0_5 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_26_0_5 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_26_0_5 : label is "NORMAL";
- attribute GSR of pdp_ram_26_0_5 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_26_0_5 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_26_0_5 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_26_0_5 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_26_0_5 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_26_0_5 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is "";
- attribute CSDECODE_B of pdp_ram_27_0_4 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_27_0_4 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_27_0_4 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_27_0_4 : label is "NORMAL";
- attribute GSR of pdp_ram_27_0_4 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_27_0_4 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_27_0_4 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_27_0_4 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_27_0_4 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_27_0_4 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is "";
- attribute CSDECODE_B of pdp_ram_28_0_3 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_28_0_3 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_28_0_3 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_28_0_3 : label is "NORMAL";
- attribute GSR of pdp_ram_28_0_3 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_28_0_3 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_28_0_3 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_28_0_3 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_28_0_3 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_28_0_3 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is "";
- attribute CSDECODE_B of pdp_ram_29_0_2 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_29_0_2 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_29_0_2 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_29_0_2 : label is "NORMAL";
- attribute GSR of pdp_ram_29_0_2 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_29_0_2 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_29_0_2 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_29_0_2 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_29_0_2 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_29_0_2 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is "";
- attribute CSDECODE_B of pdp_ram_30_0_1 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_30_0_1 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_30_0_1 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_30_0_1 : label is "NORMAL";
- attribute GSR of pdp_ram_30_0_1 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_30_0_1 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_30_0_1 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_30_0_1 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_30_0_1 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_30_0_1 : label is "9";
- attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is "";
- attribute CSDECODE_B of pdp_ram_31_0_0 : label is "0b001";
- attribute CSDECODE_A of pdp_ram_31_0_0 : label is "0b001";
- attribute WRITEMODE_B of pdp_ram_31_0_0 : label is "NORMAL";
- attribute WRITEMODE_A of pdp_ram_31_0_0 : label is "NORMAL";
- attribute GSR of pdp_ram_31_0_0 : label is "DISABLED";
- attribute RESETMODE of pdp_ram_31_0_0 : label is "ASYNC";
- attribute REGMODE_B of pdp_ram_31_0_0 : label is "NOREG";
- attribute REGMODE_A of pdp_ram_31_0_0 : label is "NOREG";
- attribute DATA_WIDTH_B of pdp_ram_31_0_0 : label is "9";
- attribute DATA_WIDTH_A of pdp_ram_31_0_0 : label is "9";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t34: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_11: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t33: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_10: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t32: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t31: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t30: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t29: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t28: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t27: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t26: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t25: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t24: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t23: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t22: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t21: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t20: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t19: XOR2
- port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
-
- XOR2_t18: XOR2
- port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
-
- XOR2_t17: XOR2
- port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
-
- XOR2_t16: XOR2
- port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15);
-
- XOR2_t15: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t14: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t13: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t12: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t11: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t10: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t9: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t8: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t7: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t6: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t5: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t4: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- XOR2_t3: XOR2
- port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
-
- XOR2_t2: XOR2
- port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
-
- XOR2_t1: XOR2
- port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
-
- XOR2_t0: XOR2
- port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
-
- INV_9: INV
- port map (A=>wptr_11, Z=>wptr_11_inv);
-
- INV_8: INV
- port map (A=>wptr_12, Z=>wptr_12_inv);
-
- INV_7: INV
- port map (A=>wptr_13, Z=>wptr_13_inv);
-
- INV_6: INV
- port map (A=>wptr_14, Z=>wptr_14_inv);
-
- INV_5: INV
- port map (A=>wptr_15, Z=>wptr_15_inv);
-
- LUT4_187: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet);
-
- LUT4_186: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_p00);
-
- INV_4: INV
- port map (A=>rptr_11, Z=>rptr_11_inv);
-
- INV_3: INV
- port map (A=>rptr_12, Z=>rptr_12_inv);
-
- INV_2: INV
- port map (A=>rptr_13, Z=>rptr_13_inv);
-
- INV_1: INV
- port map (A=>rptr_14, Z=>rptr_14_inv);
-
- INV_0: INV
- port map (A=>rptr_15, Z=>rptr_15_inv);
-
- LUT4_185: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_1);
-
- LUT4_184: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec1_r10);
-
- LUT4_183: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_2);
-
- LUT4_182: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec2_p01);
-
- LUT4_181: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_3);
-
- LUT4_180: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec3_r11);
-
- LUT4_179: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_4);
-
- LUT4_178: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec4_p02);
-
- LUT4_177: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_5);
-
- LUT4_176: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec5_r12);
-
- LUT4_175: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_6);
-
- LUT4_174: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec6_p03);
-
- LUT4_173: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_7);
-
- LUT4_172: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec7_r13);
-
- LUT4_171: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_8);
-
- LUT4_170: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec8_p04);
-
- LUT4_169: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_9);
-
- LUT4_168: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec9_r14);
-
- LUT4_167: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_10);
-
- LUT4_166: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05);
-
- LUT4_165: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_11);
-
- LUT4_164: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15);
-
- LUT4_163: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_12);
-
- LUT4_162: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06);
-
- LUT4_161: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_13);
-
- LUT4_160: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16);
-
- LUT4_159: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_14);
-
- LUT4_158: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07);
-
- LUT4_157: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_15);
-
- LUT4_156: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17);
-
- LUT4_155: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_16);
-
- LUT4_154: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08);
-
- LUT4_153: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_17);
-
- LUT4_152: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18);
-
- LUT4_151: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_18);
-
- LUT4_150: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09);
-
- LUT4_149: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_19);
-
- LUT4_148: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19);
-
- LUT4_147: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_20);
-
- LUT4_146: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010);
-
- LUT4_145: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_21);
-
- LUT4_144: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110);
-
- LUT4_143: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_22);
-
- LUT4_142: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011);
-
- LUT4_141: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_23);
-
- LUT4_140: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111);
-
- LUT4_139: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_24);
-
- LUT4_138: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012);
-
- LUT4_137: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_25);
-
- LUT4_136: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112);
-
- LUT4_135: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_26);
-
- LUT4_134: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013);
-
- LUT4_133: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_27);
-
- LUT4_132: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113);
-
- LUT4_131: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_28);
-
- LUT4_130: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014);
-
- LUT4_129: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_29);
-
- LUT4_128: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114);
-
- LUT4_127: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
- DO0=>func_and_inet_30);
-
- LUT4_126: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015);
-
- LUT4_125: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_31);
-
- LUT4_124: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv,
- AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115);
-
- LUT4_123: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_32);
-
- LUT4_122: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec32_p016);
-
- LUT4_121: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_33);
-
- LUT4_120: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec33_r116);
-
- LUT4_119: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_34);
-
- LUT4_118: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec34_p017);
-
- LUT4_117: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_35);
-
- LUT4_116: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec35_r117);
-
- LUT4_115: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_36);
-
- LUT4_114: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec36_p018);
-
- LUT4_113: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_37);
-
- LUT4_112: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec37_r118);
-
- LUT4_111: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14_inv, DO0=>func_and_inet_38);
-
- LUT4_110: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec38_p019);
-
- LUT4_109: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14_inv, DO0=>func_and_inet_39);
-
- LUT4_108: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec39_r119);
-
- LUT4_107: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_40);
-
- LUT4_106: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec40_p020);
-
- LUT4_105: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_41);
-
- LUT4_104: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec41_r120);
-
- LUT4_103: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_42);
-
- LUT4_102: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec42_p021);
-
- LUT4_101: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_43);
-
- LUT4_100: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec43_r121);
-
- LUT4_99: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_44);
-
- LUT4_98: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec44_p022);
-
- LUT4_97: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_45);
-
- LUT4_96: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec45_r122);
-
- LUT4_95: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14_inv, DO0=>func_and_inet_46);
-
- LUT4_94: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec46_p023);
-
- LUT4_93: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14_inv, DO0=>func_and_inet_47);
-
- LUT4_92: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec47_r123);
-
- LUT4_91: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_48);
-
- LUT4_90: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec48_p024);
-
- LUT4_89: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_49);
-
- LUT4_88: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec49_r124);
-
- LUT4_87: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_50);
-
- LUT4_86: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec50_p025);
-
- LUT4_85: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_51);
-
- LUT4_84: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec51_r125);
-
- LUT4_83: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_52);
-
- LUT4_82: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec52_p026);
-
- LUT4_81: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_53);
-
- LUT4_80: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec53_r126);
-
- LUT4_79: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
- AD0=>wptr_14, DO0=>func_and_inet_54);
-
- LUT4_78: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec54_p027);
-
- LUT4_77: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
- AD0=>rptr_14, DO0=>func_and_inet_55);
-
- LUT4_76: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec55_r127);
-
- LUT4_75: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_56);
-
- LUT4_74: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec56_p028);
-
- LUT4_73: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_57);
-
- LUT4_72: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec57_r128);
-
- LUT4_71: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_58);
-
- LUT4_70: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec58_p029);
-
- LUT4_69: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_59);
-
- LUT4_68: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec59_r129);
-
- LUT4_67: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
- AD0=>wptr_14, DO0=>func_and_inet_60);
-
- LUT4_66: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec60_p030);
-
- LUT4_65: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
- AD0=>rptr_14, DO0=>func_and_inet_61);
-
- LUT4_64: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec61_r130);
-
- LUT4_63: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
- DO0=>func_and_inet_62);
-
- LUT4_62: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec62_p031);
-
- LUT4_61: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
- DO0=>func_and_inet_63);
-
- LUT4_60: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec63_r131);
-
- LUT4_59: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
- AD1=>w_gcount_r215, AD0=>w_gcount_r216,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_58: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_57: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_56: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_3);
-
- LUT4_55: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r15);
-
- LUT4_54: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215,
- AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14);
-
- LUT4_53: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12);
-
- LUT4_52: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
- AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
-
- LUT4_51: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0,
- DO0=>wcount_r10);
-
- LUT4_50: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_49: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_48: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7);
-
- LUT4_47: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_46: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6);
-
- LUT4_45: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_44: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4);
-
- LUT4_43: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
-
- LUT4_42: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
- DO0=>wcount_r3);
-
- LUT4_41: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_3_2);
-
- LUT4_40: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
- DO0=>wcount_r2);
-
- LUT4_39: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
- DO0=>wcount_r1);
-
- LUT4_38: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet);
-
- LUT4_37: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1);
-
- LUT4_36: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2);
-
- LUT4_35: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
- AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3);
-
- LUT4_34: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_4);
-
- LUT4_33: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
- AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
- DO0=>func_xor_inet_5);
-
- LUT4_32: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_31: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
- AD1=>r_gcount_w215, AD0=>r_gcount_w216,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_30: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_29: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_28: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_3);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w15);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
- AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
- AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
- DO0=>rcount_w10);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
- DO0=>rcount_w3);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_3_2);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
- DO0=>rcount_w2);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
- DO0=>rcount_w1);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
- AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>func_xor_inet_10);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7,
- AD1=>func_xor_inet_8, AD0=>func_xor_inet_9,
- DO0=>func_xor_inet_11);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_31: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec1_r10,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0,
- DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3,
- DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6,
- DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_30: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec3_r11,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0,
- DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3,
- DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6,
- DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_2_0_29: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec5_r12,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0,
- DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3,
- DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6,
- DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_3_0_28: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec7_r13,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0,
- DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3,
- DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6,
- DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_4_0_27: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec9_r14,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0,
- DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3,
- DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6,
- DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_5_0_26: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec11_r15,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0,
- DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3,
- DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6,
- DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_6_0_25: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec13_r16,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0,
- DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3,
- DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6,
- DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_7_0_24: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec15_r17,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0,
- DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3,
- DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6,
- DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_8_0_23: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec17_r18,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0,
- DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3,
- DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6,
- DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_9_0_22: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec19_r19,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0,
- DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3,
- DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6,
- DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_10_0_21: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec21_r110,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0,
- DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3,
- DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6,
- DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_11_0_20: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec23_r111,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0,
- DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3,
- DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6,
- DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_12_0_19: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec25_r112,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0,
- DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3,
- DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6,
- DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_13_0_18: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec27_r113,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0,
- DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3,
- DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6,
- DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_14_0_17: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec29_r114,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0,
- DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3,
- DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6,
- DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_15_0_16: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec31_r115,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0,
- DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3,
- DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6,
- DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_16_0_15: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec33_r116,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0,
- DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3,
- DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6,
- DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_17_0_14: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec35_r117,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0,
- DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3,
- DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6,
- DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_18_0_13: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec37_r118,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0,
- DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3,
- DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6,
- DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_19_0_12: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec39_r119,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0,
- DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3,
- DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6,
- DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_20_0_11: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec41_r120,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0,
- DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3,
- DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6,
- DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_21_0_10: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec43_r121,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0,
- DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3,
- DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6,
- DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_22_0_9: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec45_r122,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0,
- DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3,
- DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6,
- DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_23_0_8: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec47_r123,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0,
- DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3,
- DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6,
- DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_24_0_7: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec49_r124,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0,
- DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3,
- DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6,
- DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_25_0_6: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec51_r125,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0,
- DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3,
- DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6,
- DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_26_0_5: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec53_r126,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0,
- DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3,
- DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6,
- DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_27_0_4: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec55_r127,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0,
- DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3,
- DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6,
- DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_28_0_3: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec57_r128,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0,
- DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3,
- DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6,
- DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_29_0_2: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec59_r129,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0,
- DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3,
- DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6,
- DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_30_0_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec61_r130,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0,
- DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3,
- DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6,
- DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_31_0_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- -- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
- CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec63_r131,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0,
- DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3,
- DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6,
- DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_176: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_175: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_174: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_173: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_172: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_171: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_170: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_169: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_168: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_167: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_166: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_165: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_164: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_163: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_13);
-
- FF_162: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_14);
-
- FF_161: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_15);
-
- FF_160: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_16);
-
- FF_159: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_158: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_157: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_156: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_155: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_154: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_153: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_152: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_151: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_150: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_149: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_148: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_147: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_146: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_13);
-
- FF_145: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_14);
-
- FF_144: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_15);
-
- FF_143: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_16);
-
- FF_142: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_141: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_140: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_139: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_138: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_137: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_136: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_135: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_134: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_133: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_132: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_131: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_130: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_129: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_13);
-
- FF_128: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_14);
-
- FF_127: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_15);
-
- FF_126: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_16);
-
- FF_125: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_124: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_123: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_122: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_121: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_120: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_119: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_118: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_117: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_116: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_115: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_114: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_113: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_112: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_13);
-
- FF_111: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_14);
-
- FF_110: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_15);
-
- FF_109: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_16);
-
- FF_108: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_107: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_106: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_105: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_104: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_103: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_102: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_101: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_13);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_14);
-
- FF_93: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_15);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_16);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_85: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_13);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_14);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_15);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_16);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_12_ff);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_13_ff);
-
- FF_71: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_14_ff);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_15_ff);
-
- FF_69: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_68: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_67: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_66: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_65: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_64: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_63: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_62: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_61: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_60: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_59: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_58: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_57: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_56: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r13);
-
- FF_55: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r14);
-
- FF_54: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r15);
-
- FF_53: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r16);
-
- FF_52: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_51: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_50: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r213);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r214);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r215);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r216);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_6: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_5: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w213);
-
- FF_4: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w214);
-
- FF_3: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w215);
-
- FF_2: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w216);
-
- FF_1: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
- NC0=>iwcount_12, NC1=>iwcount_13);
-
- w_gctr_7: CU2
- port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
- NC0=>iwcount_14, NC1=>iwcount_15);
-
- w_gctr_8: CU2
- port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8,
- NC0=>iwcount_16, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
- NC0=>ircount_12, NC1=>ircount_13);
-
- r_gctr_7: CU2
- port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
- NC0=>ircount_14, NC1=>ircount_15);
-
- r_gctr_8: CU2
- port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1,
- NC0=>ircount_16, NC1=>open);
-
- mux_8: MUX321
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
- D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
- D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
- D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0,
- D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0,
- D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0,
- D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0,
- D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0,
- D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(0));
-
- mux_7: MUX321
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
- D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
- D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
- D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1,
- D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1,
- D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1,
- D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1,
- D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1,
- D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(1));
-
- mux_6: MUX321
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
- D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
- D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
- D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2,
- D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2,
- D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2,
- D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2,
- D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2,
- D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(2));
-
- mux_5: MUX321
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
- D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
- D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
- D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3,
- D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3,
- D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3,
- D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3,
- D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3,
- D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(3));
-
- mux_4: MUX321
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
- D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
- D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
- D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4,
- D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4,
- D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4,
- D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4,
- D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4,
- D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(4));
-
- mux_3: MUX321
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
- D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
- D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
- D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5,
- D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5,
- D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5,
- D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5,
- D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5,
- D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(5));
-
- mux_2: MUX321
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
- D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
- D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
- D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6,
- D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6,
- D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6,
- D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6,
- D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6,
- D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(6));
-
- mux_1: MUX321
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
- D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
- D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
- D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7,
- D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7,
- D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7,
- D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7,
- D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7,
- D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(7));
-
- mux_0: MUX321
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
- D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
- D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
- D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8,
- D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8,
- D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8,
- D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8,
- D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8,
- D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff,
- SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
- SD5=>rptr_15_ff, Z=>Q(8));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12,
- B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2);
-
- empty_cmp_7: AGEB2
- port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14,
- B1=>wcount_r15, CI=>co6_2, GE=>co7_2);
-
- empty_cmp_8: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12,
- B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3);
-
- full_cmp_7: AGEB2
- port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14,
- B1=>rcount_w15, CI=>co6_3, GE=>co7_3);
-
- full_cmp_8: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of fifo_64kx9 is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:MUX321 use entity ecp2m.MUX321(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: module
-
-Starting process:
-
-SCUBA, Version Diamond (64-bit) 3.9.1.119
-Thu Jan 18 18:38:41 2018
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1
- Circuit name : fifo_64kx9
- Module type : ebfifo
- Module Version : 5.8
- Ports :
- Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[8:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : fifo_64kx9.edn
- VHDL output : fifo_64kx9.vhd
- VHDL template : fifo_64kx9_tmpl.vhd
- VHDL testbench : tb_fifo_64kx9_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : fifo_64kx9.srp
- Estimated Resource Usage:
- LUT : 379
- EBR : 32
- Reg : 177
-
-END SCUBA Module Synthesis
-
-File: fifo_64kx9.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.9.1.119
--- Module Version: 5.8
--- Thu Jan 18 18:38:41 2018
-
--- parameterized module component declaration
-component fifo_64kx9
- port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic;
- RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
- Reset: in std_logic; RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_64kx9
- port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-[Device]
-Family=latticeecp2m
-PartType=LFE2M100E
-PartName=LFE2M100E-5F900C
-SpeedGrade=-5
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP_TRUE
-CoreRevision=7.1
-ModuleName=ip_mem
-SourceFormat=Schematic/VHDL
-ParameterFileVersion=1.0
-Date=03/29/2010
-Time=21:52:48
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-AAddress=256
-BAddress=256
-AData=32
-BData=32
-enByte=0
-ByteSize=9
-AadPipeline=0
-BadPipeline=0
-AinPipeline=0
-BinPipeline=0
-AoutPipeline=0
-BoutPipeline=1
-AMOR=0
-BMOR=0
-AInData=Registered
-BInData=Registered
-AAdControl=Registered
-BAdControl=Registered
-MemFile=/home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem
-MemFormat=orca
-Reset=Sync
-GSR=Enabled
-WriteA=Normal
-WriteB=Normal
-Pad=0
-EnECC=0
-Optimization=Speed
-Pipeline=0
+++ /dev/null
-#Format=Address-Hex\r
-#Depth=256\r
-#DataWidth=32\r
-#AddrRadix=3\r
-#DataRadix=3\r
-\r
-00: 214397e9\r
-01: 0000001b\r
-02: c0a80002\r
-03: 0000c350\r
-04: 023bdc00\r
-05: 00000013\r
-06: c0a80005\r
-07: 0000c350\r
-08: 00000578\r
-09: 00000000\r
-0a: 00000000\r
-0b: 00000000\r
-0c: 00000000\r
-0d: 00000000\r
-0e: 00000000\r
-0f: 00000000\r
-\r
-10: 214397e9\r
-11: 0000001b\r
-12: c0a80002\r
-13: 0000c351\r
-14: 023bdc01\r
-15: 00000013\r
-16: c0a80006\r
-17: 0000c350\r
-18: 00000578\r
-19: 00000000\r
-1a: 00000000\r
-1b: 00000000\r
-1c: 00000000\r
-1d: 00000000\r
-1e: 00000000\r
-1f: 00000000\r
-\r
-20: 214397e9\r
-21: 0000001b\r
-22: c0a80002\r
-23: 0000c352\r
-24: 023bdc02\r
-25: 00000013\r
-26: c0a80007\r
-27: 0000c350\r
-28: 00000578\r
-29: 00000000\r
-2a: 00000000\r
-2b: 00000000\r
-2c: 00000000\r
-2d: 00000000\r
-2e: 00000000\r
-2f: 00000000\r
-\r
-30: 214397e9\r
-31: 0000001b\r
-32: c0a80002\r
-33: 0000c353\r
-34: 023bdc03\r
-35: 00000013\r
-36: c0a80008\r
-37: 0000c350\r
-38: 00000578\r
-39: 00000000\r
-3a: 00000000\r
-3b: 00000000\r
-3c: 00000000\r
-3d: 00000000\r
-3e: 00000000\r
-3f: 00000000\r
-\r
-40: 00000000\r
-41: 00000000\r
-42: 00000000\r
-43: 00000000\r
-44: 00000000\r
-45: 00000000\r
-46: 00000000\r
-47: 00000000\r
-48: 00000578\r
-49: 00000000\r
-4a: 00000000\r
-4b: 00000000\r
-4c: 00000000\r
-4d: 00000000\r
-4e: 00000000\r
-4f: 00000000\r
-\r
-50: 00000000\r
-51: 00000000\r
-52: 00000000\r
-53: 00000000\r
-54: 00000000\r
-55: 00000000\r
-56: 00000000\r
-57: 00000000\r
-58: 00000578\r
-59: 00000000\r
-5a: 00000000\r
-5b: 00000000\r
-5c: 00000000\r
-5d: 00000000\r
-5e: 00000000\r
-5f: 00000000\r
-\r
-60: 00000000\r
-61: 00000000\r
-62: 00000000\r
-63: 00000000\r
-64: 00000000\r
-65: 00000000\r
-66: 00000000\r
-67: 00000000\r
-68: 00000578\r
-69: 00000000\r
-6a: 00000000\r
-6b: 00000000\r
-6c: 00000000\r
-6d: 00000000\r
-6e: 00000000\r
-6f: 00000000\r
-\r
-70: 00000000\r
-71: 00000000\r
-72: 00000000\r
-73: 00000000\r
-74: 00000000\r
-75: 00000000\r
-76: 00000000\r
-77: 00000000\r
-78: 00000578\r
-79: 00000000\r
-7a: 00000000\r
-7b: 00000000\r
-7c: 00000000\r
-7d: 00000000\r
-7e: 00000000\r
-7f: 00000000\r
-\r
-80: 00000000\r
-81: 00000000\r
-82: 00000000\r
-83: 00000000\r
-84: 00000000\r
-85: 00000000\r
-86: 00000000\r
-87: 00000000\r
-88: 00000578\r
-89: 00000000\r
-8a: 00000000\r
-8b: 00000000\r
-8c: 00000000\r
-8d: 00000000\r
-8e: 00000000\r
-8f: 00000000\r
-\r
-90: 00000000\r
-91: 00000000\r
-92: 00000000\r
-93: 00000000\r
-94: 00000000\r
-95: 00000000\r
-96: 00000000\r
-97: 00000000\r
-98: 00000578\r
-99: 00000000\r
-9a: 00000000\r
-9b: 00000000\r
-9c: 00000000\r
-9d: 00000000\r
-9e: 00000000\r
-9f: 00000000\r
-\r
-a0: 00000000\r
-a1: 00000000\r
-a2: 00000000\r
-a3: 00000000\r
-a4: 00000000\r
-a5: 00000000\r
-a6: 00000000\r
-a7: 00000000\r
-a8: 00000578\r
-a9: 00000000\r
-aa: 00000000\r
-ab: 00000000\r
-ac: 00000000\r
-ad: 00000000\r
-ae: 00000000\r
-af: 00000000\r
-\r
-b0: 00000000\r
-b1: 00000000\r
-b2: 00000000\r
-b3: 00000000\r
-b4: 00000000\r
-b5: 00000000\r
-b6: 00000000\r
-b7: 00000000\r
-b8: 00000578\r
-b9: 00000000\r
-ba: 00000000\r
-bb: 00000000\r
-bc: 00000000\r
-bd: 00000000\r
-be: 00000000\r
-bf: 00000000\r
-\r
-c0: 00000000\r
-c1: 00000000\r
-c2: 00000000\r
-c3: 00000000\r
-c4: 00000000\r
-c5: 00000000\r
-c6: 00000000\r
-c7: 00000000\r
-c8: 00000578\r
-c9: 00000000\r
-ca: 00000000\r
-cb: 00000000\r
-cc: 00000000\r
-cd: 00000000\r
-ce: 00000000\r
-cf: 00000000\r
-\r
-d0: 00000000\r
-d1: 00000000\r
-d2: 00000000\r
-d3: 00000000\r
-d4: 00000000\r
-d5: 00000000\r
-d6: 00000000\r
-d7: 00000000\r
-d8: 00000578\r
-d9: 00000000\r
-da: 00000000\r
-db: 00000000\r
-dc: 00000000\r
-dd: 00000000\r
-de: 00000000\r
-df: 00000000\r
-\r
-e0: 00000000\r
-e1: 00000000\r
-e2: 00000000\r
-e3: 00000000\r
-e4: 00000000\r
-e5: 00000000\r
-e6: 00000000\r
-e7: 00000000\r
-e8: 00000578\r
-e9: 00000000\r
-ea: 00000000\r
-eb: 00000000\r
-ec: 00000000\r
-ed: 00000000\r
-ee: 00000000\r
-ef: 00000000\r
-\r
-f0: 00000000\r
-f1: 00000000\r
-f2: 00000000\r
-f3: 00000000\r
-f4: 00000000\r
-f5: 00000000\r
-f6: 00000000\r
-f7: 00000000\r
-f8: 00000578\r
-f9: 00000000\r
-fa: 00000000\r
-fb: 00000000\r
-fc: 00000000\r
-fd: 00000000\r
-fe: 00000000\r
-ff: 00000000\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 7.1
---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem -memformat orca -cascade -1 -e
-
--- Mon Mar 29 21:52:49 2010
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity ip_mem is
- port (
- DataInA: in std_logic_vector(31 downto 0);
- DataInB: in std_logic_vector(31 downto 0);
- AddressA: in std_logic_vector(7 downto 0);
- AddressB: in std_logic_vector(7 downto 0);
- ClockA: in std_logic;
- ClockB: in std_logic;
- ClockEnA: in std_logic;
- ClockEnB: in std_logic;
- WrA: in std_logic;
- WrB: in std_logic;
- ResetA: in std_logic;
- ResetB: in std_logic;
- QA: out std_logic_vector(31 downto 0);
- QB: out std_logic_vector(31 downto 0));
-end ip_mem;
-
-architecture Structure of ip_mem is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute INITVAL_3F : string;
- attribute INITVAL_3E : string;
- attribute INITVAL_3D : string;
- attribute INITVAL_3C : string;
- attribute INITVAL_3B : string;
- attribute INITVAL_3A : string;
- attribute INITVAL_39 : string;
- attribute INITVAL_38 : string;
- attribute INITVAL_37 : string;
- attribute INITVAL_36 : string;
- attribute INITVAL_35 : string;
- attribute INITVAL_34 : string;
- attribute INITVAL_33 : string;
- attribute INITVAL_32 : string;
- attribute INITVAL_31 : string;
- attribute INITVAL_30 : string;
- attribute INITVAL_2F : string;
- attribute INITVAL_2E : string;
- attribute INITVAL_2D : string;
- attribute INITVAL_2C : string;
- attribute INITVAL_2B : string;
- attribute INITVAL_2A : string;
- attribute INITVAL_29 : string;
- attribute INITVAL_28 : string;
- attribute INITVAL_27 : string;
- attribute INITVAL_26 : string;
- attribute INITVAL_25 : string;
- attribute INITVAL_24 : string;
- attribute INITVAL_23 : string;
- attribute INITVAL_22 : string;
- attribute INITVAL_21 : string;
- attribute INITVAL_20 : string;
- attribute INITVAL_1F : string;
- attribute INITVAL_1E : string;
- attribute INITVAL_1D : string;
- attribute INITVAL_1C : string;
- attribute INITVAL_1B : string;
- attribute INITVAL_1A : string;
- attribute INITVAL_19 : string;
- attribute INITVAL_18 : string;
- attribute INITVAL_17 : string;
- attribute INITVAL_16 : string;
- attribute INITVAL_15 : string;
- attribute INITVAL_14 : string;
- attribute INITVAL_13 : string;
- attribute INITVAL_12 : string;
- attribute INITVAL_11 : string;
- attribute INITVAL_10 : string;
- attribute INITVAL_0F : string;
- attribute INITVAL_0E : string;
- attribute INITVAL_0D : string;
- attribute INITVAL_0C : string;
- attribute INITVAL_0B : string;
- attribute INITVAL_0A : string;
- attribute INITVAL_09 : string;
- attribute INITVAL_08 : string;
- attribute INITVAL_07 : string;
- attribute INITVAL_06 : string;
- attribute INITVAL_05 : string;
- attribute INITVAL_04 : string;
- attribute INITVAL_03 : string;
- attribute INITVAL_02 : string;
- attribute INITVAL_01 : string;
- attribute INITVAL_00 : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute GSR : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc";
- attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem";
- attribute INITVAL_3F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_39 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_38 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_37 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_36 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_35 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_34 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_33 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_32 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_31 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_30 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_29 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_28 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_27 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_26 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_25 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_24 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_23 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_22 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_21 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_20 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_19 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_18 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_17 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_16 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_15 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_14 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_13 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_12 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_11 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_10 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_0E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_0D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_0C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_0B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_0A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_09 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_08 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_07 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_06 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_05 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_04 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000";
- attribute INITVAL_03 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9";
- attribute INITVAL_02 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9";
- attribute INITVAL_01 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9";
- attribute INITVAL_00 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9";
- attribute CSDECODE_B of ip_mem_0_0_1 : label is "0b000";
- attribute CSDECODE_A of ip_mem_0_0_1 : label is "0b000";
- attribute WRITEMODE_B of ip_mem_0_0_1 : label is "NORMAL";
- attribute WRITEMODE_A of ip_mem_0_0_1 : label is "NORMAL";
- attribute GSR of ip_mem_0_0_1 : label is "DISABLED";
- attribute RESETMODE of ip_mem_0_0_1 : label is "SYNC";
- attribute REGMODE_B of ip_mem_0_0_1 : label is "OUTREG";
- attribute REGMODE_A of ip_mem_0_0_1 : label is "NOREG";
- attribute DATA_WIDTH_B of ip_mem_0_0_1 : label is "18";
- attribute DATA_WIDTH_A of ip_mem_0_0_1 : label is "18";
- attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc";
- attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem";
- attribute INITVAL_3F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_39 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_38 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_37 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_36 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_35 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_34 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_33 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_32 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_31 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_30 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_29 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_28 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_27 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_26 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_25 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_24 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_23 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_22 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_21 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_20 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_19 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_18 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_17 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_16 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_15 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_14 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_13 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_12 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_11 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_10 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_09 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_08 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_07 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_06 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_05 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_04 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_03 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850";
- attribute INITVAL_02 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850";
- attribute INITVAL_01 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850";
- attribute INITVAL_00 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850";
- attribute CSDECODE_B of ip_mem_0_1_0 : label is "0b000";
- attribute CSDECODE_A of ip_mem_0_1_0 : label is "0b000";
- attribute WRITEMODE_B of ip_mem_0_1_0 : label is "NORMAL";
- attribute WRITEMODE_A of ip_mem_0_1_0 : label is "NORMAL";
- attribute GSR of ip_mem_0_1_0 : label is "DISABLED";
- attribute RESETMODE of ip_mem_0_1_0 : label is "SYNC";
- attribute REGMODE_B of ip_mem_0_1_0 : label is "OUTREG";
- attribute REGMODE_A of ip_mem_0_1_0 : label is "NOREG";
- attribute DATA_WIDTH_B of ip_mem_0_1_0 : label is "18";
- attribute DATA_WIDTH_A of ip_mem_0_1_0 : label is "18";
-
-begin
- -- component instantiation statements
- ip_mem_0_0_1: DP16KB
- -- synopsys translate_off
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000",
- INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9",
- INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9",
- INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9",
- INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9",
- CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
- DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
- DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
- DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
- DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
- DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
- ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
- ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
- ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
- ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA,
- CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0),
- DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3),
- DIB4=>DataInB(4), DIB5=>DataInB(5), DIB6=>DataInB(6),
- DIB7=>DataInB(7), DIB8=>DataInB(8), DIB9=>DataInB(9),
- DIB10=>DataInB(10), DIB11=>DataInB(11), DIB12=>DataInB(12),
- DIB13=>DataInB(13), DIB14=>DataInB(14), DIB15=>DataInB(15),
- DIB16=>DataInB(16), DIB17=>DataInB(17), ADB0=>scuba_vhi,
- ADB1=>scuba_vhi, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
- ADB4=>AddressB(0), ADB5=>AddressB(1), ADB6=>AddressB(2),
- ADB7=>AddressB(3), ADB8=>AddressB(4), ADB9=>AddressB(5),
- ADB10=>AddressB(6), ADB11=>AddressB(7), ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2),
- DOA3=>QA(3), DOA4=>QA(4), DOA5=>QA(5), DOA6=>QA(6),
- DOA7=>QA(7), DOA8=>QA(8), DOA9=>QA(9), DOA10=>QA(10),
- DOA11=>QA(11), DOA12=>QA(12), DOA13=>QA(13), DOA14=>QA(14),
- DOA15=>QA(15), DOA16=>QA(16), DOA17=>QA(17), DOB0=>QB(0),
- DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>QB(4),
- DOB5=>QB(5), DOB6=>QB(6), DOB7=>QB(7), DOB8=>QB(8),
- DOB9=>QB(9), DOB10=>QB(10), DOB11=>QB(11), DOB12=>QB(12),
- DOB13=>QB(13), DOB14=>QB(14), DOB15=>QB(15), DOB16=>QB(16),
- DOB17=>QB(17));
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ip_mem_0_1_0: DP16KB
- -- synopsys translate_off
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850",
- CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>DataInA(18), DIA1=>DataInA(19),
- DIA2=>DataInA(20), DIA3=>DataInA(21), DIA4=>DataInA(22),
- DIA5=>DataInA(23), DIA6=>DataInA(24), DIA7=>DataInA(25),
- DIA8=>DataInA(26), DIA9=>DataInA(27), DIA10=>DataInA(28),
- DIA11=>DataInA(29), DIA12=>DataInA(30), DIA13=>DataInA(31),
- DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo,
- DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>AddressA(0),
- ADA5=>AddressA(1), ADA6=>AddressA(2), ADA7=>AddressA(3),
- ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6),
- ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo,
- CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA,
- DIB0=>DataInB(18), DIB1=>DataInB(19), DIB2=>DataInB(20),
- DIB3=>DataInB(21), DIB4=>DataInB(22), DIB5=>DataInB(23),
- DIB6=>DataInB(24), DIB7=>DataInB(25), DIB8=>DataInB(26),
- DIB9=>DataInB(27), DIB10=>DataInB(28), DIB11=>DataInB(29),
- DIB12=>DataInB(30), DIB13=>DataInB(31), DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo,
- ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1),
- ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4),
- ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7),
- ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB,
- CLKB=>ClockB, WEB=>WrB, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19),
- DOA2=>QA(20), DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23),
- DOA6=>QA(24), DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27),
- DOA10=>QA(28), DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31),
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>QB(18), DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21),
- DOB4=>QB(22), DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25),
- DOB8=>QB(26), DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29),
- DOB12=>QB(30), DOB13=>QB(31), DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of ip_mem is
- for Structure
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 7.1
--- Mon Mar 29 21:52:49 2010
-
--- parameterized module component declaration
-component ip_mem
- port (DataInA: in std_logic_vector(31 downto 0);
- DataInB: in std_logic_vector(31 downto 0);
- AddressA: in std_logic_vector(7 downto 0);
- AddressB: in std_logic_vector(7 downto 0);
- ClockA: in std_logic; ClockB: in std_logic;
- ClockEnA: in std_logic; ClockEnB: in std_logic;
- WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic;
- ResetB: in std_logic; QA: out std_logic_vector(31 downto 0);
- QB: out std_logic_vector(31 downto 0));
-end component;
-
--- parameterized module component instance
-__ : ip_mem
- port map (DataInA(31 downto 0)=>__, DataInB(31 downto 0)=>__,
- AddressA(7 downto 0)=>__, AddressB(7 downto 0)=>__, ClockA=>__,
- ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__,
- ResetB=>__, QA(31 downto 0)=>__, QB(31 downto 0)=>__);
+++ /dev/null
-#Format=Bin\r
-#Depth=54\r
-#Width=8\r
-#AddrRadix=3\r
-#DataRadix=3\r
-#Data\r
-00001111\r
-00001111\r
-10011001\r
-00000001\r
-11101110\r
-00000101\r
-00000000\r
-00000000\r
-00001100\r
-00000000\r
-00110100\r
-00010010\r
-01111000\r
-01010110\r
-10111100\r
-10011010\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-00000000\r
-10000000\r
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-6F900C\r
-SpeedGrade=-6\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=ROM\r
-CoreRevision=5.0\r
-ModuleName=mac_init_mem\r
-SourceFormat=VHDL\r
-ParameterFileVersion=1.0\r
-Date=08/20/2009\r
-Time=16:00:49\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-Address=54\r
-Data=8\r
-adPipeline=0\r
-inPipeline=0\r
-outPipeline=1\r
-MOR=0\r
-InData=Registered\r
-AdControl=Registered\r
-MemFile=/home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem\r
-MemFormat=bin\r
-Reset=Sync\r
-Pad=0\r
-GSR=Enabled\r
-EnECC=0\r
-Optimization=Speed\r
-Pipeline=0\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)\r
--- Module Version: 5.0\r
---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -resetmode SYNC -memfile /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -memformat bin -cascade -1 -e \r
-\r
--- Thu Aug 20 16:00:49 2009\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
--- synopsys translate_off\r
-library ecp2m;\r
-use ecp2m.components.all;\r
--- synopsys translate_on\r
-\r
-entity mac_init_mem is\r
- port (\r
- Address: in std_logic_vector(5 downto 0); \r
- OutClock: in std_logic; \r
- OutClockEn: in std_logic; \r
- Reset: in std_logic; \r
- Q: out std_logic_vector(7 downto 0));\r
-end mac_init_mem;\r
-\r
-architecture Structure of mac_init_mem is\r
-\r
- -- internal signal declarations\r
- signal scuba_vhi: std_logic;\r
- signal scuba_vlo: std_logic;\r
-\r
- -- local component declarations\r
- component VHI\r
- port (Z: out std_logic);\r
- end component;\r
- component VLO\r
- port (Z: out std_logic);\r
- end component;\r
- component DP16KB\r
- -- synopsys translate_off\r
- generic (INITVAL_3F : in String; INITVAL_3E : in String; \r
- INITVAL_3D : in String; INITVAL_3C : in String; \r
- INITVAL_3B : in String; INITVAL_3A : in String; \r
- INITVAL_39 : in String; INITVAL_38 : in String; \r
- INITVAL_37 : in String; INITVAL_36 : in String; \r
- INITVAL_35 : in String; INITVAL_34 : in String; \r
- INITVAL_33 : in String; INITVAL_32 : in String; \r
- INITVAL_31 : in String; INITVAL_30 : in String; \r
- INITVAL_2F : in String; INITVAL_2E : in String; \r
- INITVAL_2D : in String; INITVAL_2C : in String; \r
- INITVAL_2B : in String; INITVAL_2A : in String; \r
- INITVAL_29 : in String; INITVAL_28 : in String; \r
- INITVAL_27 : in String; INITVAL_26 : in String; \r
- INITVAL_25 : in String; INITVAL_24 : in String; \r
- INITVAL_23 : in String; INITVAL_22 : in String; \r
- INITVAL_21 : in String; INITVAL_20 : in String; \r
- INITVAL_1F : in String; INITVAL_1E : in String; \r
- INITVAL_1D : in String; INITVAL_1C : in String; \r
- INITVAL_1B : in String; INITVAL_1A : in String; \r
- INITVAL_19 : in String; INITVAL_18 : in String; \r
- INITVAL_17 : in String; INITVAL_16 : in String; \r
- INITVAL_15 : in String; INITVAL_14 : in String; \r
- INITVAL_13 : in String; INITVAL_12 : in String; \r
- INITVAL_11 : in String; INITVAL_10 : in String; \r
- INITVAL_0F : in String; INITVAL_0E : in String; \r
- INITVAL_0D : in String; INITVAL_0C : in String; \r
- INITVAL_0B : in String; INITVAL_0A : in String; \r
- INITVAL_09 : in String; INITVAL_08 : in String; \r
- INITVAL_07 : in String; INITVAL_06 : in String; \r
- INITVAL_05 : in String; INITVAL_04 : in String; \r
- INITVAL_03 : in String; INITVAL_02 : in String; \r
- INITVAL_01 : in String; INITVAL_00 : in String; \r
- GSR : in String; WRITEMODE_B : in String; \r
- CSDECODE_B : in std_logic_vector(2 downto 0); \r
- CSDECODE_A : in std_logic_vector(2 downto 0); \r
- WRITEMODE_A : in String; RESETMODE : in String; \r
- REGMODE_B : in String; REGMODE_A : in String; \r
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);\r
- -- synopsys translate_on\r
- port (DIA0: in std_logic; DIA1: in std_logic; \r
- DIA2: in std_logic; DIA3: in std_logic; \r
- DIA4: in std_logic; DIA5: in std_logic; \r
- DIA6: in std_logic; DIA7: in std_logic; \r
- DIA8: in std_logic; DIA9: in std_logic; \r
- DIA10: in std_logic; DIA11: in std_logic; \r
- DIA12: in std_logic; DIA13: in std_logic; \r
- DIA14: in std_logic; DIA15: in std_logic; \r
- DIA16: in std_logic; DIA17: in std_logic; \r
- ADA0: in std_logic; ADA1: in std_logic; \r
- ADA2: in std_logic; ADA3: in std_logic; \r
- ADA4: in std_logic; ADA5: in std_logic; \r
- ADA6: in std_logic; ADA7: in std_logic; \r
- ADA8: in std_logic; ADA9: in std_logic; \r
- ADA10: in std_logic; ADA11: in std_logic; \r
- ADA12: in std_logic; ADA13: in std_logic; \r
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; \r
- CSA0: in std_logic; CSA1: in std_logic; \r
- CSA2: in std_logic; RSTA: in std_logic; \r
- DIB0: in std_logic; DIB1: in std_logic; \r
- DIB2: in std_logic; DIB3: in std_logic; \r
- DIB4: in std_logic; DIB5: in std_logic; \r
- DIB6: in std_logic; DIB7: in std_logic; \r
- DIB8: in std_logic; DIB9: in std_logic; \r
- DIB10: in std_logic; DIB11: in std_logic; \r
- DIB12: in std_logic; DIB13: in std_logic; \r
- DIB14: in std_logic; DIB15: in std_logic; \r
- DIB16: in std_logic; DIB17: in std_logic; \r
- ADB0: in std_logic; ADB1: in std_logic; \r
- ADB2: in std_logic; ADB3: in std_logic; \r
- ADB4: in std_logic; ADB5: in std_logic; \r
- ADB6: in std_logic; ADB7: in std_logic; \r
- ADB8: in std_logic; ADB9: in std_logic; \r
- ADB10: in std_logic; ADB11: in std_logic; \r
- ADB12: in std_logic; ADB13: in std_logic; \r
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; \r
- CSB0: in std_logic; CSB1: in std_logic; \r
- CSB2: in std_logic; RSTB: in std_logic; \r
- DOA0: out std_logic; DOA1: out std_logic; \r
- DOA2: out std_logic; DOA3: out std_logic; \r
- DOA4: out std_logic; DOA5: out std_logic; \r
- DOA6: out std_logic; DOA7: out std_logic; \r
- DOA8: out std_logic; DOA9: out std_logic; \r
- DOA10: out std_logic; DOA11: out std_logic; \r
- DOA12: out std_logic; DOA13: out std_logic; \r
- DOA14: out std_logic; DOA15: out std_logic; \r
- DOA16: out std_logic; DOA17: out std_logic; \r
- DOB0: out std_logic; DOB1: out std_logic; \r
- DOB2: out std_logic; DOB3: out std_logic; \r
- DOB4: out std_logic; DOB5: out std_logic; \r
- DOB6: out std_logic; DOB7: out std_logic; \r
- DOB8: out std_logic; DOB9: out std_logic; \r
- DOB10: out std_logic; DOB11: out std_logic; \r
- DOB12: out std_logic; DOB13: out std_logic; \r
- DOB14: out std_logic; DOB15: out std_logic; \r
- DOB16: out std_logic; DOB17: out std_logic);\r
- end component;\r
- attribute MEM_LPC_FILE : string; \r
- attribute MEM_INIT_FILE : string; \r
- attribute INITVAL_3F : string; \r
- attribute INITVAL_3E : string; \r
- attribute INITVAL_3D : string; \r
- attribute INITVAL_3C : string; \r
- attribute INITVAL_3B : string; \r
- attribute INITVAL_3A : string; \r
- attribute INITVAL_39 : string; \r
- attribute INITVAL_38 : string; \r
- attribute INITVAL_37 : string; \r
- attribute INITVAL_36 : string; \r
- attribute INITVAL_35 : string; \r
- attribute INITVAL_34 : string; \r
- attribute INITVAL_33 : string; \r
- attribute INITVAL_32 : string; \r
- attribute INITVAL_31 : string; \r
- attribute INITVAL_30 : string; \r
- attribute INITVAL_2F : string; \r
- attribute INITVAL_2E : string; \r
- attribute INITVAL_2D : string; \r
- attribute INITVAL_2C : string; \r
- attribute INITVAL_2B : string; \r
- attribute INITVAL_2A : string; \r
- attribute INITVAL_29 : string; \r
- attribute INITVAL_28 : string; \r
- attribute INITVAL_27 : string; \r
- attribute INITVAL_26 : string; \r
- attribute INITVAL_25 : string; \r
- attribute INITVAL_24 : string; \r
- attribute INITVAL_23 : string; \r
- attribute INITVAL_22 : string; \r
- attribute INITVAL_21 : string; \r
- attribute INITVAL_20 : string; \r
- attribute INITVAL_1F : string; \r
- attribute INITVAL_1E : string; \r
- attribute INITVAL_1D : string; \r
- attribute INITVAL_1C : string; \r
- attribute INITVAL_1B : string; \r
- attribute INITVAL_1A : string; \r
- attribute INITVAL_19 : string; \r
- attribute INITVAL_18 : string; \r
- attribute INITVAL_17 : string; \r
- attribute INITVAL_16 : string; \r
- attribute INITVAL_15 : string; \r
- attribute INITVAL_14 : string; \r
- attribute INITVAL_13 : string; \r
- attribute INITVAL_12 : string; \r
- attribute INITVAL_11 : string; \r
- attribute INITVAL_10 : string; \r
- attribute INITVAL_0F : string; \r
- attribute INITVAL_0E : string; \r
- attribute INITVAL_0D : string; \r
- attribute INITVAL_0C : string; \r
- attribute INITVAL_0B : string; \r
- attribute INITVAL_0A : string; \r
- attribute INITVAL_09 : string; \r
- attribute INITVAL_08 : string; \r
- attribute INITVAL_07 : string; \r
- attribute INITVAL_06 : string; \r
- attribute INITVAL_05 : string; \r
- attribute INITVAL_04 : string; \r
- attribute INITVAL_03 : string; \r
- attribute INITVAL_02 : string; \r
- attribute INITVAL_01 : string; \r
- attribute INITVAL_00 : string; \r
- attribute CSDECODE_B : string; \r
- attribute CSDECODE_A : string; \r
- attribute WRITEMODE_B : string; \r
- attribute WRITEMODE_A : string; \r
- attribute GSR : string; \r
- attribute RESETMODE : string; \r
- attribute REGMODE_B : string; \r
- attribute REGMODE_A : string; \r
- attribute DATA_WIDTH_B : string; \r
- attribute DATA_WIDTH_A : string; \r
- attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc";\r
- attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem";\r
- attribute INITVAL_3F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_3E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_3D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_3C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_3B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_3A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_39 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_38 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_37 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_36 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_35 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_34 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_33 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_32 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_31 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_30 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_2F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_2E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_2D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_2C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_2B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_2A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_29 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_28 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_27 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_26 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_25 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_24 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_23 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_22 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_21 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_20 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_1F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_1E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_1D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_1C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_1B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_1A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_19 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_18 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_17 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_16 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_15 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_14 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_13 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_12 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_11 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_10 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_0F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_0E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_0D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_0C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_0B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_0A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_09 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_08 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_07 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_06 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_05 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_04 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_03 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_02 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_01 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000";\r
- attribute INITVAL_00 of mac_init_mem_0_0_0 : label is "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F";\r
- attribute CSDECODE_B of mac_init_mem_0_0_0 : label is "0b111";\r
- attribute CSDECODE_A of mac_init_mem_0_0_0 : label is "0b000";\r
- attribute WRITEMODE_B of mac_init_mem_0_0_0 : label is "NORMAL";\r
- attribute WRITEMODE_A of mac_init_mem_0_0_0 : label is "NORMAL";\r
- attribute GSR of mac_init_mem_0_0_0 : label is "DISABLED";\r
- attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC";\r
- attribute REGMODE_B of mac_init_mem_0_0_0 : label is "NOREG";\r
- attribute REGMODE_A of mac_init_mem_0_0_0 : label is "OUTREG";\r
- attribute DATA_WIDTH_B of mac_init_mem_0_0_0 : label is "9";\r
- attribute DATA_WIDTH_A of mac_init_mem_0_0_0 : label is "9";\r
-\r
-begin\r
- -- component instantiation statements\r
- scuba_vhi_inst: VHI\r
- port map (Z=>scuba_vhi);\r
-\r
- scuba_vlo_inst: VLO\r
- port map (Z=>scuba_vlo);\r
-\r
- mac_init_mem_0_0_0: DP16KB\r
- -- synopsys translate_off\r
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", \r
- INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000", \r
- INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F", \r
- CSDECODE_B=> "111", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", \r
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", \r
- REGMODE_B=> "NOREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, \r
- DATA_WIDTH_A=> 9)\r
- -- synopsys translate_on\r
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, \r
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, \r
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, \r
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, \r
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, \r
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, \r
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, \r
- ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2), \r
- ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5), \r
- ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo, \r
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn, \r
- CLKA=>OutClock, WEA=>scuba_vlo, CSA0=>scuba_vlo, \r
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, \r
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, \r
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, \r
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, \r
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, \r
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, \r
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, \r
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, \r
- ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>scuba_vlo, \r
- ADB6=>scuba_vlo, ADB7=>scuba_vlo, ADB8=>scuba_vlo, \r
- ADB9=>scuba_vlo, ADB10=>scuba_vlo, ADB11=>scuba_vlo, \r
- ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>scuba_vhi, \r
- CLKB=>scuba_vlo, WEB=>scuba_vlo, CSB0=>scuba_vlo, \r
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>scuba_vlo, \r
- DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), \r
- DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7), DOA8=>open, DOA9=>open, \r
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, \r
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, \r
- DOB0=>open, DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, \r
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, \r
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, \r
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);\r
-\r
-end Structure;\r
-\r
--- synopsys translate_off\r
-library ecp2m;\r
-configuration Structure_CON of mac_init_mem is\r
- for Structure\r
- for all:VHI use entity ecp2m.VHI(V); end for;\r
- for all:VLO use entity ecp2m.VLO(V); end for;\r
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;\r
- end for;\r
-end Structure_CON;\r
-\r
--- synopsys translate_on\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)\r
--- Module Version: 5.0\r
--- Thu Aug 20 16:00:49 2009\r
-\r
--- parameterized module component declaration\r
-component mac_init_mem\r
- port (Address: in std_logic_vector(5 downto 0); \r
- OutClock: in std_logic; OutClockEn: in std_logic; \r
- Reset: in std_logic; Q: out std_logic_vector(7 downto 0));\r
-end component;\r
-\r
--- parameterized module component instance\r
-__ : mac_init_mem\r
- port map (Address(5 downto 0)=>__, OutClock=>__, OutClockEn=>__, \r
- Reset=>__, Q(7 downto 0)=>__);\r
+++ /dev/null
-*.jhd
-*.naf
-*.srp
-*.sym
-*.log
-*.pp
-*.tft
-*.readme
-*tmpl.vhd
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-6F900C\r
-SpeedGrade=-6\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=PCS\r
-CoreRevision=7.0\r
-ModuleName=serdes_gbe_0_extclock_8b\r
-SourceFormat=Schematic/VHDL\r
-ParameterFileVersion=1.0\r
-Date=08/20/2009\r
-Time=11:50:53\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-Protocol=Quad\r
-mode=Gigabit Ethernet\r
-Channel0=SINGLE\r
-Channel1=DISABLE\r
-Channel2=DISABLE\r
-Channel3=DISABLE\r
-Rate0=None\r
-Rate1=None\r
-Rate2=None\r
-Rate3=None\r
-TxRefClk=REFCLK\r
-RxRefClk=REFCLK\r
-ClkRate=1.25\r
-ClkMult=10X\r
-CalClkRate=125.0\r
-DataWidth=8\r
-FPGAClkRate=125.0\r
-TxRefClkCM=REFCLK\r
-RxRefClk0CM=REFCLK\r
-RxRefClk1CM=REFCLK\r
-RxRefClk2CM=REFCLK\r
-RxRefClk3CM=REFCLK\r
-ClkRateH=0.625\r
-ClkMultH=10XH\r
-CalClkRateH=125.0\r
-DataWidthH=8\r
-FPGAClkRateH=62.5\r
-VCh0=0\r
-VCh1=0\r
-VCh2=0\r
-VCh3=0\r
-PreCh0=DISABLE\r
-PreCh1=DISABLE\r
-PreCh2=DISABLE\r
-PreCh3=DISABLE\r
-TxCh0=50\r
-TxCh1=50\r
-TxCh2=50\r
-TxCh3=50\r
-EqCh0=DISABLE\r
-EqCh1=DISABLE\r
-EqCh2=DISABLE\r
-EqCh3=DISABLE\r
-RxTermCh0=50\r
-RxTermCh1=50\r
-RxTermCh2=50\r
-RxTermCh3=50\r
-RxCoupCh0=AC\r
-RxCoupCh1=AC\r
-RxCoupCh2=AC\r
-RxCoupCh3=AC\r
-Loss=0\r
-CDRLoss=0\r
-TxTerm=50\r
-TxCoup=AC\r
-TxPllLoss=0\r
-TxInvCh0=NORMAL\r
-TxInvCh1=NORMAL\r
-TxInvCh2=NORMAL\r
-TxInvCh3=NORMAL\r
-RxInvCh0=NORMAL\r
-RxInvCh1=NORMAL\r
-RxInvCh2=NORMAL\r
-RxInvCh3=NORMAL\r
-RxModeCh0=NORMAL\r
-RxModeCh1=NORMAL\r
-RxModeCh2=NORMAL\r
-RxModeCh3=NORMAL\r
-Plus=1100000101\r
-Minus=0011111010\r
-Mask=1111111111\r
-Align=AUTO\r
-CTCCh0=NORMAL\r
-CTCCh1=NORMAL\r
-CTCCh2=NORMAL\r
-CTCCh3=NORMAL\r
-CC_MATCH1=0000000000\r
-CC_MATCH2=0000000000\r
-CC_MATCH3=0110111100\r
-CC_MATCH4=0001010000\r
-MinIPG=3\r
-High=9\r
-Low=7\r
-CC_MATCH_MODE=MATCH_3_4\r
-RxDataCh0=FALSE\r
-RxDataCh1=FALSE\r
-RxDataCh2=FALSE\r
-RxDataCh3=FALSE\r
-AlignerCh0=FALSE\r
-AlignerCh1=FALSE\r
-AlignerCh2=FALSE\r
-AlignerCh3=FALSE\r
-DetectCh0=FALSE\r
-DetectCh1=FALSE\r
-DetectCh2=FALSE\r
-DetectCh3=FALSE\r
-ELSMCh0=FALSE\r
-ELSMCh1=FALSE\r
-ELSMCh2=FALSE\r
-ELSMCh3=FALSE\r
-_teidleCh0=FALSE\r
-_teidleCh1=FALSE\r
-_teidleCh2=FALSE\r
-_teidleCh3=FALSE\r
-Ports0=FALSE\r
-rdoPorts0=Serial Loopback\r
-Ports1=FALSE\r
-Ports2=TRUE\r
-Ports3=FALSE\r
-Ports3_1=FALSE\r
-Ports4=FALSE\r
+++ /dev/null
-\r
-# This file is used by the simulation model as well as the ispLEVER bitstream\r
-# generation process to automatically initialize the PCSC quad to the mode\r
-# selected in the IPexpress. This file is expected to be modified by the\r
-# end user to adjust the PCSC quad to the final design requirements.\r
-\r
-DEVICE_NAME "LFE2M100E"\r
-PROTOCOL "GIGE" \r
-CH0_MODE "SINGLE" \r
-CH1_MODE "DISABLE" \r
-CH2_MODE "DISABLE" \r
-CH3_MODE "DISABLE" \r
-PLL_SRC "REFCLK" \r
-DATARANGE "MED" \r
-CH0_CDR_SRC "REFCLK" \r
-CH0_DATA_WIDTH "8" \r
-CH0_REFCK_MULT "10X" \r
-#REFCLK_RATE 125.0\r
-#FPGAINTCLK_RATE 125.0\r
-CH0_TDRV_AMP "0" \r
-CH0_TX_PRE "DISABLE" \r
-CH0_RTERM_TX "50" \r
-CH0_RX_EQ "DISABLE" \r
-CH0_RTERM_RX "50" \r
-CH0_RX_DCC "AC" \r
-LOS_THRESHOLD "0" \r
-PLL_TERM "50" \r
-PLL_DCC "AC" \r
-PLL_LOL_SET "0" \r
-CH0_TX_SB "NORMAL" \r
-CH0_RX_SB "NORMAL" \r
-CH0_8B10B "NORMAL" \r
-COMMA_A "1100000101" \r
-COMMA_B "0011111010" \r
-COMMA_M "1111111111" \r
-CH0_COMMA_ALIGN "AUTO" \r
-CH0_CTC_BYP "BYPASS" \r
-CC_MATCH1 "0000000000" \r
-CC_MATCH2 "0000000000" \r
-CC_MATCH3 "0110111100" \r
-CC_MATCH4 "0001010000" \r
-CC_MATCH_MODE "MATCH_3_4" \r
-CC_MIN_IPG "3" \r
-CCHMARK "9" \r
-CCLMARK "7" \r
-OS_REFCK2CORE "1"\r
-OS_PLLQCLKPORTS "0"\r
-OS_INT_ALL "0"\r
-\r
+++ /dev/null
-\r
-\r
---synopsys translate_off\r
-\r
-library pcsc_work;\r
-use pcsc_work.all;\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity PCSC is\r
-GENERIC(\r
- CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"\r
- );\r
-port (\r
- HDINN0 : in std_logic;\r
- HDINN1 : in std_logic;\r
- HDINN2 : in std_logic;\r
- HDINN3 : in std_logic;\r
- HDINP0 : in std_logic;\r
- HDINP1 : in std_logic;\r
- HDINP2 : in std_logic;\r
- HDINP3 : in std_logic;\r
- REFCLKN : in std_logic;\r
- REFCLKP : in std_logic;\r
- CIN0 : in std_logic;\r
- CIN1 : in std_logic;\r
- CIN2 : in std_logic;\r
- CIN3 : in std_logic;\r
- CIN4 : in std_logic;\r
- CIN5 : in std_logic;\r
- CIN6 : in std_logic;\r
- CIN7 : in std_logic;\r
- CIN8 : in std_logic;\r
- CIN9 : in std_logic;\r
- CIN10 : in std_logic;\r
- CIN11 : in std_logic;\r
- CYAWSTN : in std_logic;\r
- FF_EBRD_CLK_0 : in std_logic;\r
- FF_EBRD_CLK_1 : in std_logic;\r
- FF_EBRD_CLK_2 : in std_logic;\r
- FF_EBRD_CLK_3 : in std_logic;\r
- FF_RXI_CLK_0 : in std_logic;\r
- FF_RXI_CLK_1 : in std_logic;\r
- FF_RXI_CLK_2 : in std_logic;\r
- FF_RXI_CLK_3 : in std_logic;\r
- FF_TX_D_0_0 : in std_logic;\r
- FF_TX_D_0_1 : in std_logic;\r
- FF_TX_D_0_2 : in std_logic;\r
- FF_TX_D_0_3 : in std_logic;\r
- FF_TX_D_0_4 : in std_logic;\r
- FF_TX_D_0_5 : in std_logic;\r
- FF_TX_D_0_6 : in std_logic;\r
- FF_TX_D_0_7 : in std_logic;\r
- FF_TX_D_0_8 : in std_logic;\r
- FF_TX_D_0_9 : in std_logic;\r
- FF_TX_D_0_10 : in std_logic;\r
- FF_TX_D_0_11 : in std_logic;\r
- FF_TX_D_0_12 : in std_logic;\r
- FF_TX_D_0_13 : in std_logic;\r
- FF_TX_D_0_14 : in std_logic;\r
- FF_TX_D_0_15 : in std_logic;\r
- FF_TX_D_0_16 : in std_logic;\r
- FF_TX_D_0_17 : in std_logic;\r
- FF_TX_D_0_18 : in std_logic;\r
- FF_TX_D_0_19 : in std_logic;\r
- FF_TX_D_0_20 : in std_logic;\r
- FF_TX_D_0_21 : in std_logic;\r
- FF_TX_D_0_22 : in std_logic;\r
- FF_TX_D_0_23 : in std_logic;\r
- FF_TX_D_1_0 : in std_logic;\r
- FF_TX_D_1_1 : in std_logic;\r
- FF_TX_D_1_2 : in std_logic;\r
- FF_TX_D_1_3 : in std_logic;\r
- FF_TX_D_1_4 : in std_logic;\r
- FF_TX_D_1_5 : in std_logic;\r
- FF_TX_D_1_6 : in std_logic;\r
- FF_TX_D_1_7 : in std_logic;\r
- FF_TX_D_1_8 : in std_logic;\r
- FF_TX_D_1_9 : in std_logic;\r
- FF_TX_D_1_10 : in std_logic;\r
- FF_TX_D_1_11 : in std_logic;\r
- FF_TX_D_1_12 : in std_logic;\r
- FF_TX_D_1_13 : in std_logic;\r
- FF_TX_D_1_14 : in std_logic;\r
- FF_TX_D_1_15 : in std_logic;\r
- FF_TX_D_1_16 : in std_logic;\r
- FF_TX_D_1_17 : in std_logic;\r
- FF_TX_D_1_18 : in std_logic;\r
- FF_TX_D_1_19 : in std_logic;\r
- FF_TX_D_1_20 : in std_logic;\r
- FF_TX_D_1_21 : in std_logic;\r
- FF_TX_D_1_22 : in std_logic;\r
- FF_TX_D_1_23 : in std_logic;\r
- FF_TX_D_2_0 : in std_logic;\r
- FF_TX_D_2_1 : in std_logic;\r
- FF_TX_D_2_2 : in std_logic;\r
- FF_TX_D_2_3 : in std_logic;\r
- FF_TX_D_2_4 : in std_logic;\r
- FF_TX_D_2_5 : in std_logic;\r
- FF_TX_D_2_6 : in std_logic;\r
- FF_TX_D_2_7 : in std_logic;\r
- FF_TX_D_2_8 : in std_logic;\r
- FF_TX_D_2_9 : in std_logic;\r
- FF_TX_D_2_10 : in std_logic;\r
- FF_TX_D_2_11 : in std_logic;\r
- FF_TX_D_2_12 : in std_logic;\r
- FF_TX_D_2_13 : in std_logic;\r
- FF_TX_D_2_14 : in std_logic;\r
- FF_TX_D_2_15 : in std_logic;\r
- FF_TX_D_2_16 : in std_logic;\r
- FF_TX_D_2_17 : in std_logic;\r
- FF_TX_D_2_18 : in std_logic;\r
- FF_TX_D_2_19 : in std_logic;\r
- FF_TX_D_2_20 : in std_logic;\r
- FF_TX_D_2_21 : in std_logic;\r
- FF_TX_D_2_22 : in std_logic;\r
- FF_TX_D_2_23 : in std_logic;\r
- FF_TX_D_3_0 : in std_logic;\r
- FF_TX_D_3_1 : in std_logic;\r
- FF_TX_D_3_2 : in std_logic;\r
- FF_TX_D_3_3 : in std_logic;\r
- FF_TX_D_3_4 : in std_logic;\r
- FF_TX_D_3_5 : in std_logic;\r
- FF_TX_D_3_6 : in std_logic;\r
- FF_TX_D_3_7 : in std_logic;\r
- FF_TX_D_3_8 : in std_logic;\r
- FF_TX_D_3_9 : in std_logic;\r
- FF_TX_D_3_10 : in std_logic;\r
- FF_TX_D_3_11 : in std_logic;\r
- FF_TX_D_3_12 : in std_logic;\r
- FF_TX_D_3_13 : in std_logic;\r
- FF_TX_D_3_14 : in std_logic;\r
- FF_TX_D_3_15 : in std_logic;\r
- FF_TX_D_3_16 : in std_logic;\r
- FF_TX_D_3_17 : in std_logic;\r
- FF_TX_D_3_18 : in std_logic;\r
- FF_TX_D_3_19 : in std_logic;\r
- FF_TX_D_3_20 : in std_logic;\r
- FF_TX_D_3_21 : in std_logic;\r
- FF_TX_D_3_22 : in std_logic;\r
- FF_TX_D_3_23 : in std_logic;\r
- FF_TXI_CLK_0 : in std_logic;\r
- FF_TXI_CLK_1 : in std_logic;\r
- FF_TXI_CLK_2 : in std_logic;\r
- FF_TXI_CLK_3 : in std_logic;\r
- FFC_CK_CORE_RX : in std_logic;\r
- FFC_CK_CORE_TX : in std_logic;\r
- FFC_EI_EN_0 : in std_logic;\r
- FFC_EI_EN_1 : in std_logic;\r
- FFC_EI_EN_2 : in std_logic;\r
- FFC_EI_EN_3 : in std_logic;\r
- FFC_ENABLE_CGALIGN_0 : in std_logic;\r
- FFC_ENABLE_CGALIGN_1 : in std_logic;\r
- FFC_ENABLE_CGALIGN_2 : in std_logic;\r
- FFC_ENABLE_CGALIGN_3 : in std_logic;\r
- FFC_FB_LOOPBACK_0 : in std_logic;\r
- FFC_FB_LOOPBACK_1 : in std_logic;\r
- FFC_FB_LOOPBACK_2 : in std_logic;\r
- FFC_FB_LOOPBACK_3 : in std_logic;\r
- FFC_LANE_RX_RST_0 : in std_logic;\r
- FFC_LANE_RX_RST_1 : in std_logic;\r
- FFC_LANE_RX_RST_2 : in std_logic;\r
- FFC_LANE_RX_RST_3 : in std_logic;\r
- FFC_LANE_TX_RST_0 : in std_logic;\r
- FFC_LANE_TX_RST_1 : in std_logic;\r
- FFC_LANE_TX_RST_2 : in std_logic;\r
- FFC_LANE_TX_RST_3 : in std_logic;\r
- FFC_MACRO_RST : in std_logic;\r
- FFC_PCI_DET_EN_0 : in std_logic;\r
- FFC_PCI_DET_EN_1 : in std_logic;\r
- FFC_PCI_DET_EN_2 : in std_logic;\r
- FFC_PCI_DET_EN_3 : in std_logic;\r
- FFC_PCIE_CT_0 : in std_logic;\r
- FFC_PCIE_CT_1 : in std_logic;\r
- FFC_PCIE_CT_2 : in std_logic;\r
- FFC_PCIE_CT_3 : in std_logic;\r
- FFC_PFIFO_CLR_0 : in std_logic;\r
- FFC_PFIFO_CLR_1 : in std_logic;\r
- FFC_PFIFO_CLR_2 : in std_logic;\r
- FFC_PFIFO_CLR_3 : in std_logic;\r
- FFC_QUAD_RST : in std_logic;\r
- FFC_RRST_0 : in std_logic;\r
- FFC_RRST_1 : in std_logic;\r
- FFC_RRST_2 : in std_logic;\r
- FFC_RRST_3 : in std_logic;\r
- FFC_RXPWDNB_0 : in std_logic;\r
- FFC_RXPWDNB_1 : in std_logic;\r
- FFC_RXPWDNB_2 : in std_logic;\r
- FFC_RXPWDNB_3 : in std_logic;\r
- FFC_SB_INV_RX_0 : in std_logic;\r
- FFC_SB_INV_RX_1 : in std_logic;\r
- FFC_SB_INV_RX_2 : in std_logic;\r
- FFC_SB_INV_RX_3 : in std_logic;\r
- FFC_SB_PFIFO_LP_0 : in std_logic;\r
- FFC_SB_PFIFO_LP_1 : in std_logic;\r
- FFC_SB_PFIFO_LP_2 : in std_logic;\r
- FFC_SB_PFIFO_LP_3 : in std_logic;\r
- FFC_SIGNAL_DETECT_0 : in std_logic;\r
- FFC_SIGNAL_DETECT_1 : in std_logic;\r
- FFC_SIGNAL_DETECT_2 : in std_logic;\r
- FFC_SIGNAL_DETECT_3 : in std_logic;\r
- FFC_TRST : in std_logic;\r
- FFC_TXPWDNB_0 : in std_logic;\r
- FFC_TXPWDNB_1 : in std_logic;\r
- FFC_TXPWDNB_2 : in std_logic;\r
- FFC_TXPWDNB_3 : in std_logic;\r
- SCIADDR0 : in std_logic;\r
- SCIADDR1 : in std_logic;\r
- SCIADDR2 : in std_logic;\r
- SCIADDR3 : in std_logic;\r
- SCIADDR4 : in std_logic;\r
- SCIADDR5 : in std_logic;\r
- SCIENAUX : in std_logic;\r
- SCIENCH0 : in std_logic;\r
- SCIENCH1 : in std_logic;\r
- SCIENCH2 : in std_logic;\r
- SCIENCH3 : in std_logic;\r
- SCIRD : in std_logic;\r
- SCISELAUX : in std_logic;\r
- SCISELCH0 : in std_logic;\r
- SCISELCH1 : in std_logic;\r
- SCISELCH2 : in std_logic;\r
- SCISELCH3 : in std_logic;\r
- SCIWDATA0 : in std_logic;\r
- SCIWDATA1 : in std_logic;\r
- SCIWDATA2 : in std_logic;\r
- SCIWDATA3 : in std_logic;\r
- SCIWDATA4 : in std_logic;\r
- SCIWDATA5 : in std_logic;\r
- SCIWDATA6 : in std_logic;\r
- SCIWDATA7 : in std_logic;\r
- SCIWSTN : in std_logic;\r
- HDOUTN0 : out std_logic;\r
- HDOUTN1 : out std_logic;\r
- HDOUTN2 : out std_logic;\r
- HDOUTN3 : out std_logic;\r
- HDOUTP0 : out std_logic;\r
- HDOUTP1 : out std_logic;\r
- HDOUTP2 : out std_logic;\r
- HDOUTP3 : out std_logic;\r
- COUT0 : out std_logic;\r
- COUT1 : out std_logic;\r
- COUT2 : out std_logic;\r
- COUT3 : out std_logic;\r
- COUT4 : out std_logic;\r
- COUT5 : out std_logic;\r
- COUT6 : out std_logic;\r
- COUT7 : out std_logic;\r
- COUT8 : out std_logic;\r
- COUT9 : out std_logic;\r
- COUT10 : out std_logic;\r
- COUT11 : out std_logic;\r
- COUT12 : out std_logic;\r
- COUT13 : out std_logic;\r
- COUT14 : out std_logic;\r
- COUT15 : out std_logic;\r
- COUT16 : out std_logic;\r
- COUT17 : out std_logic;\r
- COUT18 : out std_logic;\r
- COUT19 : out std_logic;\r
- FF_RX_D_0_0 : out std_logic;\r
- FF_RX_D_0_1 : out std_logic;\r
- FF_RX_D_0_2 : out std_logic;\r
- FF_RX_D_0_3 : out std_logic;\r
- FF_RX_D_0_4 : out std_logic;\r
- FF_RX_D_0_5 : out std_logic;\r
- FF_RX_D_0_6 : out std_logic;\r
- FF_RX_D_0_7 : out std_logic;\r
- FF_RX_D_0_8 : out std_logic;\r
- FF_RX_D_0_9 : out std_logic;\r
- FF_RX_D_0_10 : out std_logic;\r
- FF_RX_D_0_11 : out std_logic;\r
- FF_RX_D_0_12 : out std_logic;\r
- FF_RX_D_0_13 : out std_logic;\r
- FF_RX_D_0_14 : out std_logic;\r
- FF_RX_D_0_15 : out std_logic;\r
- FF_RX_D_0_16 : out std_logic;\r
- FF_RX_D_0_17 : out std_logic;\r
- FF_RX_D_0_18 : out std_logic;\r
- FF_RX_D_0_19 : out std_logic;\r
- FF_RX_D_0_20 : out std_logic;\r
- FF_RX_D_0_21 : out std_logic;\r
- FF_RX_D_0_22 : out std_logic;\r
- FF_RX_D_0_23 : out std_logic;\r
- FF_RX_D_1_0 : out std_logic;\r
- FF_RX_D_1_1 : out std_logic;\r
- FF_RX_D_1_2 : out std_logic;\r
- FF_RX_D_1_3 : out std_logic;\r
- FF_RX_D_1_4 : out std_logic;\r
- FF_RX_D_1_5 : out std_logic;\r
- FF_RX_D_1_6 : out std_logic;\r
- FF_RX_D_1_7 : out std_logic;\r
- FF_RX_D_1_8 : out std_logic;\r
- FF_RX_D_1_9 : out std_logic;\r
- FF_RX_D_1_10 : out std_logic;\r
- FF_RX_D_1_11 : out std_logic;\r
- FF_RX_D_1_12 : out std_logic;\r
- FF_RX_D_1_13 : out std_logic;\r
- FF_RX_D_1_14 : out std_logic;\r
- FF_RX_D_1_15 : out std_logic;\r
- FF_RX_D_1_16 : out std_logic;\r
- FF_RX_D_1_17 : out std_logic;\r
- FF_RX_D_1_18 : out std_logic;\r
- FF_RX_D_1_19 : out std_logic;\r
- FF_RX_D_1_20 : out std_logic;\r
- FF_RX_D_1_21 : out std_logic;\r
- FF_RX_D_1_22 : out std_logic;\r
- FF_RX_D_1_23 : out std_logic;\r
- FF_RX_D_2_0 : out std_logic;\r
- FF_RX_D_2_1 : out std_logic;\r
- FF_RX_D_2_2 : out std_logic;\r
- FF_RX_D_2_3 : out std_logic;\r
- FF_RX_D_2_4 : out std_logic;\r
- FF_RX_D_2_5 : out std_logic;\r
- FF_RX_D_2_6 : out std_logic;\r
- FF_RX_D_2_7 : out std_logic;\r
- FF_RX_D_2_8 : out std_logic;\r
- FF_RX_D_2_9 : out std_logic;\r
- FF_RX_D_2_10 : out std_logic;\r
- FF_RX_D_2_11 : out std_logic;\r
- FF_RX_D_2_12 : out std_logic;\r
- FF_RX_D_2_13 : out std_logic;\r
- FF_RX_D_2_14 : out std_logic;\r
- FF_RX_D_2_15 : out std_logic;\r
- FF_RX_D_2_16 : out std_logic;\r
- FF_RX_D_2_17 : out std_logic;\r
- FF_RX_D_2_18 : out std_logic;\r
- FF_RX_D_2_19 : out std_logic;\r
- FF_RX_D_2_20 : out std_logic;\r
- FF_RX_D_2_21 : out std_logic;\r
- FF_RX_D_2_22 : out std_logic;\r
- FF_RX_D_2_23 : out std_logic;\r
- FF_RX_D_3_0 : out std_logic;\r
- FF_RX_D_3_1 : out std_logic;\r
- FF_RX_D_3_2 : out std_logic;\r
- FF_RX_D_3_3 : out std_logic;\r
- FF_RX_D_3_4 : out std_logic;\r
- FF_RX_D_3_5 : out std_logic;\r
- FF_RX_D_3_6 : out std_logic;\r
- FF_RX_D_3_7 : out std_logic;\r
- FF_RX_D_3_8 : out std_logic;\r
- FF_RX_D_3_9 : out std_logic;\r
- FF_RX_D_3_10 : out std_logic;\r
- FF_RX_D_3_11 : out std_logic;\r
- FF_RX_D_3_12 : out std_logic;\r
- FF_RX_D_3_13 : out std_logic;\r
- FF_RX_D_3_14 : out std_logic;\r
- FF_RX_D_3_15 : out std_logic;\r
- FF_RX_D_3_16 : out std_logic;\r
- FF_RX_D_3_17 : out std_logic;\r
- FF_RX_D_3_18 : out std_logic;\r
- FF_RX_D_3_19 : out std_logic;\r
- FF_RX_D_3_20 : out std_logic;\r
- FF_RX_D_3_21 : out std_logic;\r
- FF_RX_D_3_22 : out std_logic;\r
- FF_RX_D_3_23 : out std_logic;\r
- FF_RX_F_CLK_0 : out std_logic;\r
- FF_RX_F_CLK_1 : out std_logic;\r
- FF_RX_F_CLK_2 : out std_logic;\r
- FF_RX_F_CLK_3 : out std_logic;\r
- FF_RX_H_CLK_0 : out std_logic;\r
- FF_RX_H_CLK_1 : out std_logic;\r
- FF_RX_H_CLK_2 : out std_logic;\r
- FF_RX_H_CLK_3 : out std_logic;\r
- FF_RX_Q_CLK_0 : out std_logic;\r
- FF_RX_Q_CLK_1 : out std_logic;\r
- FF_RX_Q_CLK_2 : out std_logic;\r
- FF_RX_Q_CLK_3 : out std_logic;\r
- FF_TX_F_CLK : out std_logic;\r
- FF_TX_H_CLK : out std_logic;\r
- FF_TX_Q_CLK : out std_logic;\r
- FFS_CC_OVERRUN_0 : out std_logic;\r
- FFS_CC_OVERRUN_1 : out std_logic;\r
- FFS_CC_OVERRUN_2 : out std_logic;\r
- FFS_CC_OVERRUN_3 : out std_logic;\r
- FFS_CC_UNDERRUN_0 : out std_logic;\r
- FFS_CC_UNDERRUN_1 : out std_logic;\r
- FFS_CC_UNDERRUN_2 : out std_logic;\r
- FFS_CC_UNDERRUN_3 : out std_logic;\r
- FFS_LS_SYNC_STATUS_0 : out std_logic;\r
- FFS_LS_SYNC_STATUS_1 : out std_logic;\r
- FFS_LS_SYNC_STATUS_2 : out std_logic;\r
- FFS_LS_SYNC_STATUS_3 : out std_logic;\r
- FFS_PCIE_CON_0 : out std_logic;\r
- FFS_PCIE_CON_1 : out std_logic;\r
- FFS_PCIE_CON_2 : out std_logic;\r
- FFS_PCIE_CON_3 : out std_logic;\r
- FFS_PCIE_DONE_0 : out std_logic;\r
- FFS_PCIE_DONE_1 : out std_logic;\r
- FFS_PCIE_DONE_2 : out std_logic;\r
- FFS_PCIE_DONE_3 : out std_logic;\r
- FFS_RLOS_LO_0 : out std_logic;\r
- FFS_RLOS_LO_1 : out std_logic;\r
- FFS_RLOS_LO_2 : out std_logic;\r
- FFS_RLOS_LO_3 : out std_logic;\r
- OOB_OUT_0 : out std_logic;\r
- OOB_OUT_1 : out std_logic;\r
- OOB_OUT_2 : out std_logic;\r
- OOB_OUT_3 : out std_logic;\r
- REFCK2CORE : out std_logic;\r
- SCIINT : out std_logic;\r
- SCIRDATA0 : out std_logic;\r
- SCIRDATA1 : out std_logic;\r
- SCIRDATA2 : out std_logic;\r
- SCIRDATA3 : out std_logic;\r
- SCIRDATA4 : out std_logic;\r
- SCIRDATA5 : out std_logic;\r
- SCIRDATA6 : out std_logic;\r
- SCIRDATA7 : out std_logic;\r
- FFS_PLOL : out std_logic;\r
- FFS_RLOL_0 : out std_logic;\r
- FFS_RLOL_1 : out std_logic;\r
- FFS_RLOL_2 : out std_logic;\r
- FFS_RLOL_3 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_3 : out std_logic\r
-);\r
-\r
-end PCSC;\r
-\r
-architecture PCSC_arch of PCSC is\r
-\r
-component PCSC_sim\r
-GENERIC(\r
- CONFIG_FILE : String\r
- );\r
-port (\r
- HDINN0 : in std_logic;\r
- HDINN1 : in std_logic;\r
- HDINN2 : in std_logic;\r
- HDINN3 : in std_logic;\r
- HDINP0 : in std_logic;\r
- HDINP1 : in std_logic;\r
- HDINP2 : in std_logic;\r
- HDINP3 : in std_logic;\r
- REFCLKN : in std_logic;\r
- REFCLKP : in std_logic;\r
- CIN0 : in std_logic;\r
- CIN1 : in std_logic;\r
- CIN2 : in std_logic;\r
- CIN3 : in std_logic;\r
- CIN4 : in std_logic;\r
- CIN5 : in std_logic;\r
- CIN6 : in std_logic;\r
- CIN7 : in std_logic;\r
- CIN8 : in std_logic;\r
- CIN9 : in std_logic;\r
- CIN10 : in std_logic;\r
- CIN11 : in std_logic;\r
- CYAWSTN : in std_logic;\r
- FF_EBRD_CLK_0 : in std_logic;\r
- FF_EBRD_CLK_1 : in std_logic;\r
- FF_EBRD_CLK_2 : in std_logic;\r
- FF_EBRD_CLK_3 : in std_logic;\r
- FF_RXI_CLK_0 : in std_logic;\r
- FF_RXI_CLK_1 : in std_logic;\r
- FF_RXI_CLK_2 : in std_logic;\r
- FF_RXI_CLK_3 : in std_logic;\r
- FF_TX_D_0_0 : in std_logic;\r
- FF_TX_D_0_1 : in std_logic;\r
- FF_TX_D_0_2 : in std_logic;\r
- FF_TX_D_0_3 : in std_logic;\r
- FF_TX_D_0_4 : in std_logic;\r
- FF_TX_D_0_5 : in std_logic;\r
- FF_TX_D_0_6 : in std_logic;\r
- FF_TX_D_0_7 : in std_logic;\r
- FF_TX_D_0_8 : in std_logic;\r
- FF_TX_D_0_9 : in std_logic;\r
- FF_TX_D_0_10 : in std_logic;\r
- FF_TX_D_0_11 : in std_logic;\r
- FF_TX_D_0_12 : in std_logic;\r
- FF_TX_D_0_13 : in std_logic;\r
- FF_TX_D_0_14 : in std_logic;\r
- FF_TX_D_0_15 : in std_logic;\r
- FF_TX_D_0_16 : in std_logic;\r
- FF_TX_D_0_17 : in std_logic;\r
- FF_TX_D_0_18 : in std_logic;\r
- FF_TX_D_0_19 : in std_logic;\r
- FF_TX_D_0_20 : in std_logic;\r
- FF_TX_D_0_21 : in std_logic;\r
- FF_TX_D_0_22 : in std_logic;\r
- FF_TX_D_0_23 : in std_logic;\r
- FF_TX_D_1_0 : in std_logic;\r
- FF_TX_D_1_1 : in std_logic;\r
- FF_TX_D_1_2 : in std_logic;\r
- FF_TX_D_1_3 : in std_logic;\r
- FF_TX_D_1_4 : in std_logic;\r
- FF_TX_D_1_5 : in std_logic;\r
- FF_TX_D_1_6 : in std_logic;\r
- FF_TX_D_1_7 : in std_logic;\r
- FF_TX_D_1_8 : in std_logic;\r
- FF_TX_D_1_9 : in std_logic;\r
- FF_TX_D_1_10 : in std_logic;\r
- FF_TX_D_1_11 : in std_logic;\r
- FF_TX_D_1_12 : in std_logic;\r
- FF_TX_D_1_13 : in std_logic;\r
- FF_TX_D_1_14 : in std_logic;\r
- FF_TX_D_1_15 : in std_logic;\r
- FF_TX_D_1_16 : in std_logic;\r
- FF_TX_D_1_17 : in std_logic;\r
- FF_TX_D_1_18 : in std_logic;\r
- FF_TX_D_1_19 : in std_logic;\r
- FF_TX_D_1_20 : in std_logic;\r
- FF_TX_D_1_21 : in std_logic;\r
- FF_TX_D_1_22 : in std_logic;\r
- FF_TX_D_1_23 : in std_logic;\r
- FF_TX_D_2_0 : in std_logic;\r
- FF_TX_D_2_1 : in std_logic;\r
- FF_TX_D_2_2 : in std_logic;\r
- FF_TX_D_2_3 : in std_logic;\r
- FF_TX_D_2_4 : in std_logic;\r
- FF_TX_D_2_5 : in std_logic;\r
- FF_TX_D_2_6 : in std_logic;\r
- FF_TX_D_2_7 : in std_logic;\r
- FF_TX_D_2_8 : in std_logic;\r
- FF_TX_D_2_9 : in std_logic;\r
- FF_TX_D_2_10 : in std_logic;\r
- FF_TX_D_2_11 : in std_logic;\r
- FF_TX_D_2_12 : in std_logic;\r
- FF_TX_D_2_13 : in std_logic;\r
- FF_TX_D_2_14 : in std_logic;\r
- FF_TX_D_2_15 : in std_logic;\r
- FF_TX_D_2_16 : in std_logic;\r
- FF_TX_D_2_17 : in std_logic;\r
- FF_TX_D_2_18 : in std_logic;\r
- FF_TX_D_2_19 : in std_logic;\r
- FF_TX_D_2_20 : in std_logic;\r
- FF_TX_D_2_21 : in std_logic;\r
- FF_TX_D_2_22 : in std_logic;\r
- FF_TX_D_2_23 : in std_logic;\r
- FF_TX_D_3_0 : in std_logic;\r
- FF_TX_D_3_1 : in std_logic;\r
- FF_TX_D_3_2 : in std_logic;\r
- FF_TX_D_3_3 : in std_logic;\r
- FF_TX_D_3_4 : in std_logic;\r
- FF_TX_D_3_5 : in std_logic;\r
- FF_TX_D_3_6 : in std_logic;\r
- FF_TX_D_3_7 : in std_logic;\r
- FF_TX_D_3_8 : in std_logic;\r
- FF_TX_D_3_9 : in std_logic;\r
- FF_TX_D_3_10 : in std_logic;\r
- FF_TX_D_3_11 : in std_logic;\r
- FF_TX_D_3_12 : in std_logic;\r
- FF_TX_D_3_13 : in std_logic;\r
- FF_TX_D_3_14 : in std_logic;\r
- FF_TX_D_3_15 : in std_logic;\r
- FF_TX_D_3_16 : in std_logic;\r
- FF_TX_D_3_17 : in std_logic;\r
- FF_TX_D_3_18 : in std_logic;\r
- FF_TX_D_3_19 : in std_logic;\r
- FF_TX_D_3_20 : in std_logic;\r
- FF_TX_D_3_21 : in std_logic;\r
- FF_TX_D_3_22 : in std_logic;\r
- FF_TX_D_3_23 : in std_logic;\r
- FF_TXI_CLK_0 : in std_logic;\r
- FF_TXI_CLK_1 : in std_logic;\r
- FF_TXI_CLK_2 : in std_logic;\r
- FF_TXI_CLK_3 : in std_logic;\r
- FFC_CK_CORE_RX : in std_logic;\r
- FFC_CK_CORE_TX : in std_logic;\r
- FFC_EI_EN_0 : in std_logic;\r
- FFC_EI_EN_1 : in std_logic;\r
- FFC_EI_EN_2 : in std_logic;\r
- FFC_EI_EN_3 : in std_logic;\r
- FFC_ENABLE_CGALIGN_0 : in std_logic;\r
- FFC_ENABLE_CGALIGN_1 : in std_logic;\r
- FFC_ENABLE_CGALIGN_2 : in std_logic;\r
- FFC_ENABLE_CGALIGN_3 : in std_logic;\r
- FFC_FB_LOOPBACK_0 : in std_logic;\r
- FFC_FB_LOOPBACK_1 : in std_logic;\r
- FFC_FB_LOOPBACK_2 : in std_logic;\r
- FFC_FB_LOOPBACK_3 : in std_logic;\r
- FFC_LANE_RX_RST_0 : in std_logic;\r
- FFC_LANE_RX_RST_1 : in std_logic;\r
- FFC_LANE_RX_RST_2 : in std_logic;\r
- FFC_LANE_RX_RST_3 : in std_logic;\r
- FFC_LANE_TX_RST_0 : in std_logic;\r
- FFC_LANE_TX_RST_1 : in std_logic;\r
- FFC_LANE_TX_RST_2 : in std_logic;\r
- FFC_LANE_TX_RST_3 : in std_logic;\r
- FFC_MACRO_RST : in std_logic;\r
- FFC_PCI_DET_EN_0 : in std_logic;\r
- FFC_PCI_DET_EN_1 : in std_logic;\r
- FFC_PCI_DET_EN_2 : in std_logic;\r
- FFC_PCI_DET_EN_3 : in std_logic;\r
- FFC_PCIE_CT_0 : in std_logic;\r
- FFC_PCIE_CT_1 : in std_logic;\r
- FFC_PCIE_CT_2 : in std_logic;\r
- FFC_PCIE_CT_3 : in std_logic;\r
- FFC_PFIFO_CLR_0 : in std_logic;\r
- FFC_PFIFO_CLR_1 : in std_logic;\r
- FFC_PFIFO_CLR_2 : in std_logic;\r
- FFC_PFIFO_CLR_3 : in std_logic;\r
- FFC_QUAD_RST : in std_logic;\r
- FFC_RRST_0 : in std_logic;\r
- FFC_RRST_1 : in std_logic;\r
- FFC_RRST_2 : in std_logic;\r
- FFC_RRST_3 : in std_logic;\r
- FFC_RXPWDNB_0 : in std_logic;\r
- FFC_RXPWDNB_1 : in std_logic;\r
- FFC_RXPWDNB_2 : in std_logic;\r
- FFC_RXPWDNB_3 : in std_logic;\r
- FFC_SB_INV_RX_0 : in std_logic;\r
- FFC_SB_INV_RX_1 : in std_logic;\r
- FFC_SB_INV_RX_2 : in std_logic;\r
- FFC_SB_INV_RX_3 : in std_logic;\r
- FFC_SB_PFIFO_LP_0 : in std_logic;\r
- FFC_SB_PFIFO_LP_1 : in std_logic;\r
- FFC_SB_PFIFO_LP_2 : in std_logic;\r
- FFC_SB_PFIFO_LP_3 : in std_logic;\r
- FFC_SIGNAL_DETECT_0 : in std_logic;\r
- FFC_SIGNAL_DETECT_1 : in std_logic;\r
- FFC_SIGNAL_DETECT_2 : in std_logic;\r
- FFC_SIGNAL_DETECT_3 : in std_logic;\r
- FFC_TRST : in std_logic;\r
- FFC_TXPWDNB_0 : in std_logic;\r
- FFC_TXPWDNB_1 : in std_logic;\r
- FFC_TXPWDNB_2 : in std_logic;\r
- FFC_TXPWDNB_3 : in std_logic;\r
- SCIADDR0 : in std_logic;\r
- SCIADDR1 : in std_logic;\r
- SCIADDR2 : in std_logic;\r
- SCIADDR3 : in std_logic;\r
- SCIADDR4 : in std_logic;\r
- SCIADDR5 : in std_logic;\r
- SCIENAUX : in std_logic;\r
- SCIENCH0 : in std_logic;\r
- SCIENCH1 : in std_logic;\r
- SCIENCH2 : in std_logic;\r
- SCIENCH3 : in std_logic;\r
- SCIRD : in std_logic;\r
- SCISELAUX : in std_logic;\r
- SCISELCH0 : in std_logic;\r
- SCISELCH1 : in std_logic;\r
- SCISELCH2 : in std_logic;\r
- SCISELCH3 : in std_logic;\r
- SCIWDATA0 : in std_logic;\r
- SCIWDATA1 : in std_logic;\r
- SCIWDATA2 : in std_logic;\r
- SCIWDATA3 : in std_logic;\r
- SCIWDATA4 : in std_logic;\r
- SCIWDATA5 : in std_logic;\r
- SCIWDATA6 : in std_logic;\r
- SCIWDATA7 : in std_logic;\r
- SCIWSTN : in std_logic;\r
- HDOUTN0 : out std_logic;\r
- HDOUTN1 : out std_logic;\r
- HDOUTN2 : out std_logic;\r
- HDOUTN3 : out std_logic;\r
- HDOUTP0 : out std_logic;\r
- HDOUTP1 : out std_logic;\r
- HDOUTP2 : out std_logic;\r
- HDOUTP3 : out std_logic;\r
- COUT0 : out std_logic;\r
- COUT1 : out std_logic;\r
- COUT2 : out std_logic;\r
- COUT3 : out std_logic;\r
- COUT4 : out std_logic;\r
- COUT5 : out std_logic;\r
- COUT6 : out std_logic;\r
- COUT7 : out std_logic;\r
- COUT8 : out std_logic;\r
- COUT9 : out std_logic;\r
- COUT10 : out std_logic;\r
- COUT11 : out std_logic;\r
- COUT12 : out std_logic;\r
- COUT13 : out std_logic;\r
- COUT14 : out std_logic;\r
- COUT15 : out std_logic;\r
- COUT16 : out std_logic;\r
- COUT17 : out std_logic;\r
- COUT18 : out std_logic;\r
- COUT19 : out std_logic;\r
- FF_RX_D_0_0 : out std_logic;\r
- FF_RX_D_0_1 : out std_logic;\r
- FF_RX_D_0_2 : out std_logic;\r
- FF_RX_D_0_3 : out std_logic;\r
- FF_RX_D_0_4 : out std_logic;\r
- FF_RX_D_0_5 : out std_logic;\r
- FF_RX_D_0_6 : out std_logic;\r
- FF_RX_D_0_7 : out std_logic;\r
- FF_RX_D_0_8 : out std_logic;\r
- FF_RX_D_0_9 : out std_logic;\r
- FF_RX_D_0_10 : out std_logic;\r
- FF_RX_D_0_11 : out std_logic;\r
- FF_RX_D_0_12 : out std_logic;\r
- FF_RX_D_0_13 : out std_logic;\r
- FF_RX_D_0_14 : out std_logic;\r
- FF_RX_D_0_15 : out std_logic;\r
- FF_RX_D_0_16 : out std_logic;\r
- FF_RX_D_0_17 : out std_logic;\r
- FF_RX_D_0_18 : out std_logic;\r
- FF_RX_D_0_19 : out std_logic;\r
- FF_RX_D_0_20 : out std_logic;\r
- FF_RX_D_0_21 : out std_logic;\r
- FF_RX_D_0_22 : out std_logic;\r
- FF_RX_D_0_23 : out std_logic;\r
- FF_RX_D_1_0 : out std_logic;\r
- FF_RX_D_1_1 : out std_logic;\r
- FF_RX_D_1_2 : out std_logic;\r
- FF_RX_D_1_3 : out std_logic;\r
- FF_RX_D_1_4 : out std_logic;\r
- FF_RX_D_1_5 : out std_logic;\r
- FF_RX_D_1_6 : out std_logic;\r
- FF_RX_D_1_7 : out std_logic;\r
- FF_RX_D_1_8 : out std_logic;\r
- FF_RX_D_1_9 : out std_logic;\r
- FF_RX_D_1_10 : out std_logic;\r
- FF_RX_D_1_11 : out std_logic;\r
- FF_RX_D_1_12 : out std_logic;\r
- FF_RX_D_1_13 : out std_logic;\r
- FF_RX_D_1_14 : out std_logic;\r
- FF_RX_D_1_15 : out std_logic;\r
- FF_RX_D_1_16 : out std_logic;\r
- FF_RX_D_1_17 : out std_logic;\r
- FF_RX_D_1_18 : out std_logic;\r
- FF_RX_D_1_19 : out std_logic;\r
- FF_RX_D_1_20 : out std_logic;\r
- FF_RX_D_1_21 : out std_logic;\r
- FF_RX_D_1_22 : out std_logic;\r
- FF_RX_D_1_23 : out std_logic;\r
- FF_RX_D_2_0 : out std_logic;\r
- FF_RX_D_2_1 : out std_logic;\r
- FF_RX_D_2_2 : out std_logic;\r
- FF_RX_D_2_3 : out std_logic;\r
- FF_RX_D_2_4 : out std_logic;\r
- FF_RX_D_2_5 : out std_logic;\r
- FF_RX_D_2_6 : out std_logic;\r
- FF_RX_D_2_7 : out std_logic;\r
- FF_RX_D_2_8 : out std_logic;\r
- FF_RX_D_2_9 : out std_logic;\r
- FF_RX_D_2_10 : out std_logic;\r
- FF_RX_D_2_11 : out std_logic;\r
- FF_RX_D_2_12 : out std_logic;\r
- FF_RX_D_2_13 : out std_logic;\r
- FF_RX_D_2_14 : out std_logic;\r
- FF_RX_D_2_15 : out std_logic;\r
- FF_RX_D_2_16 : out std_logic;\r
- FF_RX_D_2_17 : out std_logic;\r
- FF_RX_D_2_18 : out std_logic;\r
- FF_RX_D_2_19 : out std_logic;\r
- FF_RX_D_2_20 : out std_logic;\r
- FF_RX_D_2_21 : out std_logic;\r
- FF_RX_D_2_22 : out std_logic;\r
- FF_RX_D_2_23 : out std_logic;\r
- FF_RX_D_3_0 : out std_logic;\r
- FF_RX_D_3_1 : out std_logic;\r
- FF_RX_D_3_2 : out std_logic;\r
- FF_RX_D_3_3 : out std_logic;\r
- FF_RX_D_3_4 : out std_logic;\r
- FF_RX_D_3_5 : out std_logic;\r
- FF_RX_D_3_6 : out std_logic;\r
- FF_RX_D_3_7 : out std_logic;\r
- FF_RX_D_3_8 : out std_logic;\r
- FF_RX_D_3_9 : out std_logic;\r
- FF_RX_D_3_10 : out std_logic;\r
- FF_RX_D_3_11 : out std_logic;\r
- FF_RX_D_3_12 : out std_logic;\r
- FF_RX_D_3_13 : out std_logic;\r
- FF_RX_D_3_14 : out std_logic;\r
- FF_RX_D_3_15 : out std_logic;\r
- FF_RX_D_3_16 : out std_logic;\r
- FF_RX_D_3_17 : out std_logic;\r
- FF_RX_D_3_18 : out std_logic;\r
- FF_RX_D_3_19 : out std_logic;\r
- FF_RX_D_3_20 : out std_logic;\r
- FF_RX_D_3_21 : out std_logic;\r
- FF_RX_D_3_22 : out std_logic;\r
- FF_RX_D_3_23 : out std_logic;\r
- FF_RX_F_CLK_0 : out std_logic;\r
- FF_RX_F_CLK_1 : out std_logic;\r
- FF_RX_F_CLK_2 : out std_logic;\r
- FF_RX_F_CLK_3 : out std_logic;\r
- FF_RX_H_CLK_0 : out std_logic;\r
- FF_RX_H_CLK_1 : out std_logic;\r
- FF_RX_H_CLK_2 : out std_logic;\r
- FF_RX_H_CLK_3 : out std_logic;\r
- FF_RX_Q_CLK_0 : out std_logic;\r
- FF_RX_Q_CLK_1 : out std_logic;\r
- FF_RX_Q_CLK_2 : out std_logic;\r
- FF_RX_Q_CLK_3 : out std_logic;\r
- FF_TX_F_CLK : out std_logic;\r
- FF_TX_H_CLK : out std_logic;\r
- FF_TX_Q_CLK : out std_logic;\r
- FFS_CC_OVERRUN_0 : out std_logic;\r
- FFS_CC_OVERRUN_1 : out std_logic;\r
- FFS_CC_OVERRUN_2 : out std_logic;\r
- FFS_CC_OVERRUN_3 : out std_logic;\r
- FFS_CC_UNDERRUN_0 : out std_logic;\r
- FFS_CC_UNDERRUN_1 : out std_logic;\r
- FFS_CC_UNDERRUN_2 : out std_logic;\r
- FFS_CC_UNDERRUN_3 : out std_logic;\r
- FFS_LS_SYNC_STATUS_0 : out std_logic;\r
- FFS_LS_SYNC_STATUS_1 : out std_logic;\r
- FFS_LS_SYNC_STATUS_2 : out std_logic;\r
- FFS_LS_SYNC_STATUS_3 : out std_logic;\r
- FFS_PCIE_CON_0 : out std_logic;\r
- FFS_PCIE_CON_1 : out std_logic;\r
- FFS_PCIE_CON_2 : out std_logic;\r
- FFS_PCIE_CON_3 : out std_logic;\r
- FFS_PCIE_DONE_0 : out std_logic;\r
- FFS_PCIE_DONE_1 : out std_logic;\r
- FFS_PCIE_DONE_2 : out std_logic;\r
- FFS_PCIE_DONE_3 : out std_logic;\r
- FFS_RLOS_LO_0 : out std_logic;\r
- FFS_RLOS_LO_1 : out std_logic;\r
- FFS_RLOS_LO_2 : out std_logic;\r
- FFS_RLOS_LO_3 : out std_logic;\r
- OOB_OUT_0 : out std_logic;\r
- OOB_OUT_1 : out std_logic;\r
- OOB_OUT_2 : out std_logic;\r
- OOB_OUT_3 : out std_logic;\r
- REFCK2CORE : out std_logic;\r
- SCIINT : out std_logic;\r
- SCIRDATA0 : out std_logic;\r
- SCIRDATA1 : out std_logic;\r
- SCIRDATA2 : out std_logic;\r
- SCIRDATA3 : out std_logic;\r
- SCIRDATA4 : out std_logic;\r
- SCIRDATA5 : out std_logic;\r
- SCIRDATA6 : out std_logic;\r
- SCIRDATA7 : out std_logic;\r
- FFS_PLOL : out std_logic;\r
- FFS_RLOL_0 : out std_logic;\r
- FFS_RLOL_1 : out std_logic;\r
- FFS_RLOL_2 : out std_logic;\r
- FFS_RLOL_3 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_3 : out std_logic\r
-);\r
-end component;\r
-\r
-begin\r
-\r
-PCSC_sim_inst : PCSC_sim\r
-generic map (\r
- CONFIG_FILE => CONFIG_FILE)\r
-port map (\r
- HDINN0 => HDINN0,\r
- HDINN1 => HDINN1,\r
- HDINN2 => HDINN2,\r
- HDINN3 => HDINN3,\r
- HDINP0 => HDINP0,\r
- HDINP1 => HDINP1,\r
- HDINP2 => HDINP2,\r
- HDINP3 => HDINP3,\r
- REFCLKN => REFCLKN,\r
- REFCLKP => REFCLKP,\r
- CIN11 => CIN11,\r
- CIN10 => CIN10,\r
- CIN9 => CIN9,\r
- CIN8 => CIN8,\r
- CIN7 => CIN7,\r
- CIN6 => CIN6,\r
- CIN5 => CIN5,\r
- CIN4 => CIN4,\r
- CIN3 => CIN3,\r
- CIN2 => CIN2,\r
- CIN1 => CIN1,\r
- CIN0 => CIN0,\r
- CYAWSTN => CYAWSTN,\r
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,\r
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,\r
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,\r
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,\r
- FF_RXI_CLK_3 => FF_RXI_CLK_3,\r
- FF_RXI_CLK_2 => FF_RXI_CLK_2,\r
- FF_RXI_CLK_1 => FF_RXI_CLK_1,\r
- FF_RXI_CLK_0 => FF_RXI_CLK_0,\r
-\r
- FF_TX_D_0_0 => FF_TX_D_0_0,\r
- FF_TX_D_0_1 => FF_TX_D_0_1,\r
- FF_TX_D_0_2 => FF_TX_D_0_2,\r
- FF_TX_D_0_3 => FF_TX_D_0_3,\r
- FF_TX_D_0_4 => FF_TX_D_0_4,\r
- FF_TX_D_0_5 => FF_TX_D_0_5,\r
- FF_TX_D_0_6 => FF_TX_D_0_6,\r
- FF_TX_D_0_7 => FF_TX_D_0_7,\r
- FF_TX_D_0_8 => FF_TX_D_0_8,\r
- FF_TX_D_0_9 => FF_TX_D_0_9,\r
- FF_TX_D_0_10 => FF_TX_D_0_10,\r
- FF_TX_D_0_11 => FF_TX_D_0_11,\r
- FF_TX_D_0_12 => FF_TX_D_0_12,\r
- FF_TX_D_0_13 => FF_TX_D_0_13,\r
- FF_TX_D_0_14 => FF_TX_D_0_14,\r
- FF_TX_D_0_15 => FF_TX_D_0_15,\r
- FF_TX_D_0_16 => FF_TX_D_0_16,\r
- FF_TX_D_0_17 => FF_TX_D_0_17,\r
- FF_TX_D_0_18 => FF_TX_D_0_18,\r
- FF_TX_D_0_19 => FF_TX_D_0_19,\r
- FF_TX_D_0_20 => FF_TX_D_0_20,\r
- FF_TX_D_0_21 => FF_TX_D_0_21,\r
- FF_TX_D_0_22 => FF_TX_D_0_22,\r
- FF_TX_D_0_23 => FF_TX_D_0_23,\r
- FF_TX_D_1_0 => FF_TX_D_1_0,\r
- FF_TX_D_1_1 => FF_TX_D_1_1,\r
- FF_TX_D_1_2 => FF_TX_D_1_2,\r
- FF_TX_D_1_3 => FF_TX_D_1_3,\r
- FF_TX_D_1_4 => FF_TX_D_1_4,\r
- FF_TX_D_1_5 => FF_TX_D_1_5,\r
- FF_TX_D_1_6 => FF_TX_D_1_6,\r
- FF_TX_D_1_7 => FF_TX_D_1_7,\r
- FF_TX_D_1_8 => FF_TX_D_1_8,\r
- FF_TX_D_1_9 => FF_TX_D_1_9,\r
- FF_TX_D_1_10 => FF_TX_D_1_10,\r
- FF_TX_D_1_11 => FF_TX_D_1_11,\r
- FF_TX_D_1_12 => FF_TX_D_1_12,\r
- FF_TX_D_1_13 => FF_TX_D_1_13,\r
- FF_TX_D_1_14 => FF_TX_D_1_14,\r
- FF_TX_D_1_15 => FF_TX_D_1_15,\r
- FF_TX_D_1_16 => FF_TX_D_1_16,\r
- FF_TX_D_1_17 => FF_TX_D_1_17,\r
- FF_TX_D_1_18 => FF_TX_D_1_18,\r
- FF_TX_D_1_19 => FF_TX_D_1_19,\r
- FF_TX_D_1_20 => FF_TX_D_1_20,\r
- FF_TX_D_1_21 => FF_TX_D_1_21,\r
- FF_TX_D_1_22 => FF_TX_D_1_22,\r
- FF_TX_D_1_23 => FF_TX_D_1_23,\r
- FF_TX_D_2_0 => FF_TX_D_2_0,\r
- FF_TX_D_2_1 => FF_TX_D_2_1,\r
- FF_TX_D_2_2 => FF_TX_D_2_2,\r
- FF_TX_D_2_3 => FF_TX_D_2_3,\r
- FF_TX_D_2_4 => FF_TX_D_2_4,\r
- FF_TX_D_2_5 => FF_TX_D_2_5,\r
- FF_TX_D_2_6 => FF_TX_D_2_6,\r
- FF_TX_D_2_7 => FF_TX_D_2_7,\r
- FF_TX_D_2_8 => FF_TX_D_2_8,\r
- FF_TX_D_2_9 => FF_TX_D_2_9,\r
- FF_TX_D_2_10 => FF_TX_D_2_10,\r
- FF_TX_D_2_11 => FF_TX_D_2_11,\r
- FF_TX_D_2_12 => FF_TX_D_2_12,\r
- FF_TX_D_2_13 => FF_TX_D_2_13,\r
- FF_TX_D_2_14 => FF_TX_D_2_14,\r
- FF_TX_D_2_15 => FF_TX_D_2_15,\r
- FF_TX_D_2_16 => FF_TX_D_2_16,\r
- FF_TX_D_2_17 => FF_TX_D_2_17,\r
- FF_TX_D_2_18 => FF_TX_D_2_18,\r
- FF_TX_D_2_19 => FF_TX_D_2_19,\r
- FF_TX_D_2_20 => FF_TX_D_2_20,\r
- FF_TX_D_2_21 => FF_TX_D_2_21,\r
- FF_TX_D_2_22 => FF_TX_D_2_22,\r
- FF_TX_D_2_23 => FF_TX_D_2_23,\r
- FF_TX_D_3_0 => FF_TX_D_3_0,\r
- FF_TX_D_3_1 => FF_TX_D_3_1,\r
- FF_TX_D_3_2 => FF_TX_D_3_2,\r
- FF_TX_D_3_3 => FF_TX_D_3_3,\r
- FF_TX_D_3_4 => FF_TX_D_3_4,\r
- FF_TX_D_3_5 => FF_TX_D_3_5,\r
- FF_TX_D_3_6 => FF_TX_D_3_6,\r
- FF_TX_D_3_7 => FF_TX_D_3_7,\r
- FF_TX_D_3_8 => FF_TX_D_3_8,\r
- FF_TX_D_3_9 => FF_TX_D_3_9,\r
- FF_TX_D_3_10 => FF_TX_D_3_10,\r
- FF_TX_D_3_11 => FF_TX_D_3_11,\r
- FF_TX_D_3_12 => FF_TX_D_3_12,\r
- FF_TX_D_3_13 => FF_TX_D_3_13,\r
- FF_TX_D_3_14 => FF_TX_D_3_14,\r
- FF_TX_D_3_15 => FF_TX_D_3_15,\r
- FF_TX_D_3_16 => FF_TX_D_3_16,\r
- FF_TX_D_3_17 => FF_TX_D_3_17,\r
- FF_TX_D_3_18 => FF_TX_D_3_18,\r
- FF_TX_D_3_19 => FF_TX_D_3_19,\r
- FF_TX_D_3_20 => FF_TX_D_3_20,\r
- FF_TX_D_3_21 => FF_TX_D_3_21,\r
- FF_TX_D_3_22 => FF_TX_D_3_22,\r
- FF_TX_D_3_23 => FF_TX_D_3_23,\r
- FF_TXI_CLK_0 => FF_TXI_CLK_0,\r
- FF_TXI_CLK_1 => FF_TXI_CLK_1,\r
- FF_TXI_CLK_2 => FF_TXI_CLK_2,\r
- FF_TXI_CLK_3 => FF_TXI_CLK_3,\r
- FFC_CK_CORE_RX => FFC_CK_CORE_RX,\r
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,\r
- FFC_EI_EN_0 => FFC_EI_EN_0,\r
- FFC_EI_EN_1 => FFC_EI_EN_1,\r
- FFC_EI_EN_2 => FFC_EI_EN_2,\r
- FFC_EI_EN_3 => FFC_EI_EN_3,\r
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,\r
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,\r
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,\r
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,\r
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,\r
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,\r
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,\r
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,\r
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,\r
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,\r
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,\r
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,\r
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,\r
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,\r
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,\r
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,\r
- FFC_MACRO_RST => FFC_MACRO_RST,\r
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,\r
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,\r
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,\r
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,\r
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,\r
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,\r
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,\r
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,\r
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,\r
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,\r
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,\r
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,\r
- FFC_QUAD_RST => FFC_QUAD_RST,\r
- FFC_RRST_0 => FFC_RRST_0,\r
- FFC_RRST_1 => FFC_RRST_1,\r
- FFC_RRST_2 => FFC_RRST_2,\r
- FFC_RRST_3 => FFC_RRST_3,\r
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,\r
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,\r
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,\r
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,\r
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,\r
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,\r
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,\r
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,\r
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,\r
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,\r
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,\r
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,\r
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,\r
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,\r
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,\r
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,\r
- FFC_TRST => FFC_TRST,\r
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,\r
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,\r
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,\r
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,\r
- SCIADDR0 => SCIADDR0,\r
- SCIADDR1 => SCIADDR1,\r
- SCIADDR2 => SCIADDR2,\r
- SCIADDR3 => SCIADDR3,\r
- SCIADDR4 => SCIADDR4,\r
- SCIADDR5 => SCIADDR5,\r
- SCIENAUX => SCIENAUX,\r
- SCIENCH0 => SCIENCH0,\r
- SCIENCH1 => SCIENCH1,\r
- SCIENCH2 => SCIENCH2,\r
- SCIENCH3 => SCIENCH3,\r
- SCIRD => SCIRD,\r
- SCISELAUX => SCISELAUX,\r
- SCISELCH0 => SCISELCH0,\r
- SCISELCH1 => SCISELCH1,\r
- SCISELCH2 => SCISELCH2,\r
- SCISELCH3 => SCISELCH3,\r
- SCIWDATA0 => SCIWDATA0,\r
- SCIWDATA1 => SCIWDATA1,\r
- SCIWDATA2 => SCIWDATA2,\r
- SCIWDATA3 => SCIWDATA3,\r
- SCIWDATA4 => SCIWDATA4,\r
- SCIWDATA5 => SCIWDATA5,\r
- SCIWDATA6 => SCIWDATA6,\r
- SCIWDATA7 => SCIWDATA7,\r
- SCIWSTN => SCIWSTN,\r
- HDOUTN0 => HDOUTN0,\r
- HDOUTN1 => HDOUTN1,\r
- HDOUTN2 => HDOUTN2,\r
- HDOUTN3 => HDOUTN3,\r
- HDOUTP0 => HDOUTP0,\r
- HDOUTP1 => HDOUTP1,\r
- HDOUTP2 => HDOUTP2,\r
- HDOUTP3 => HDOUTP3,\r
- COUT19 => COUT19,\r
- COUT18 => COUT18,\r
- COUT17 => COUT17,\r
- COUT16 => COUT16,\r
- COUT15 => COUT15,\r
- COUT14 => COUT14,\r
- COUT13 => COUT13,\r
- COUT12 => COUT12,\r
- COUT11 => COUT11,\r
- COUT10 => COUT10,\r
- COUT9 => COUT9,\r
- COUT8 => COUT8,\r
- COUT7 => COUT7,\r
- COUT6 => COUT6,\r
- COUT5 => COUT5,\r
- COUT4 => COUT4,\r
- COUT3 => COUT3,\r
- COUT2 => COUT2,\r
- COUT1 => COUT1,\r
- COUT0 => COUT0,\r
- FF_RX_D_0_0 => FF_RX_D_0_0,\r
- FF_RX_D_0_1 => FF_RX_D_0_1,\r
- FF_RX_D_0_2 => FF_RX_D_0_2,\r
- FF_RX_D_0_3 => FF_RX_D_0_3,\r
- FF_RX_D_0_4 => FF_RX_D_0_4,\r
- FF_RX_D_0_5 => FF_RX_D_0_5,\r
- FF_RX_D_0_6 => FF_RX_D_0_6,\r
- FF_RX_D_0_7 => FF_RX_D_0_7,\r
- FF_RX_D_0_8 => FF_RX_D_0_8,\r
- FF_RX_D_0_9 => FF_RX_D_0_9,\r
- FF_RX_D_0_10 => FF_RX_D_0_10,\r
- FF_RX_D_0_11 => FF_RX_D_0_11,\r
- FF_RX_D_0_12 => FF_RX_D_0_12,\r
- FF_RX_D_0_13 => FF_RX_D_0_13,\r
- FF_RX_D_0_14 => FF_RX_D_0_14,\r
- FF_RX_D_0_15 => FF_RX_D_0_15,\r
- FF_RX_D_0_16 => FF_RX_D_0_16,\r
- FF_RX_D_0_17 => FF_RX_D_0_17,\r
- FF_RX_D_0_18 => FF_RX_D_0_18,\r
- FF_RX_D_0_19 => FF_RX_D_0_19,\r
- FF_RX_D_0_20 => FF_RX_D_0_20,\r
- FF_RX_D_0_21 => FF_RX_D_0_21,\r
- FF_RX_D_0_22 => FF_RX_D_0_22,\r
- FF_RX_D_0_23 => FF_RX_D_0_23,\r
- FF_RX_D_1_0 => FF_RX_D_1_0,\r
- FF_RX_D_1_1 => FF_RX_D_1_1,\r
- FF_RX_D_1_2 => FF_RX_D_1_2,\r
- FF_RX_D_1_3 => FF_RX_D_1_3,\r
- FF_RX_D_1_4 => FF_RX_D_1_4,\r
- FF_RX_D_1_5 => FF_RX_D_1_5,\r
- FF_RX_D_1_6 => FF_RX_D_1_6,\r
- FF_RX_D_1_7 => FF_RX_D_1_7,\r
- FF_RX_D_1_8 => FF_RX_D_1_8,\r
- FF_RX_D_1_9 => FF_RX_D_1_9,\r
- FF_RX_D_1_10 => FF_RX_D_1_10,\r
- FF_RX_D_1_11 => FF_RX_D_1_11,\r
- FF_RX_D_1_12 => FF_RX_D_1_12,\r
- FF_RX_D_1_13 => FF_RX_D_1_13,\r
- FF_RX_D_1_14 => FF_RX_D_1_14,\r
- FF_RX_D_1_15 => FF_RX_D_1_15,\r
- FF_RX_D_1_16 => FF_RX_D_1_16,\r
- FF_RX_D_1_17 => FF_RX_D_1_17,\r
- FF_RX_D_1_18 => FF_RX_D_1_18,\r
- FF_RX_D_1_19 => FF_RX_D_1_19,\r
- FF_RX_D_1_20 => FF_RX_D_1_20,\r
- FF_RX_D_1_21 => FF_RX_D_1_21,\r
- FF_RX_D_1_22 => FF_RX_D_1_22,\r
- FF_RX_D_1_23 => FF_RX_D_1_23,\r
- FF_RX_D_2_0 => FF_RX_D_2_0,\r
- FF_RX_D_2_1 => FF_RX_D_2_1,\r
- FF_RX_D_2_2 => FF_RX_D_2_2,\r
- FF_RX_D_2_3 => FF_RX_D_2_3,\r
- FF_RX_D_2_4 => FF_RX_D_2_4,\r
- FF_RX_D_2_5 => FF_RX_D_2_5,\r
- FF_RX_D_2_6 => FF_RX_D_2_6,\r
- FF_RX_D_2_7 => FF_RX_D_2_7,\r
- FF_RX_D_2_8 => FF_RX_D_2_8,\r
- FF_RX_D_2_9 => FF_RX_D_2_9,\r
- FF_RX_D_2_10 => FF_RX_D_2_10,\r
- FF_RX_D_2_11 => FF_RX_D_2_11,\r
- FF_RX_D_2_12 => FF_RX_D_2_12,\r
- FF_RX_D_2_13 => FF_RX_D_2_13,\r
- FF_RX_D_2_14 => FF_RX_D_2_14,\r
- FF_RX_D_2_15 => FF_RX_D_2_15,\r
- FF_RX_D_2_16 => FF_RX_D_2_16,\r
- FF_RX_D_2_17 => FF_RX_D_2_17,\r
- FF_RX_D_2_18 => FF_RX_D_2_18,\r
- FF_RX_D_2_19 => FF_RX_D_2_19,\r
- FF_RX_D_2_20 => FF_RX_D_2_20,\r
- FF_RX_D_2_21 => FF_RX_D_2_21,\r
- FF_RX_D_2_22 => FF_RX_D_2_22,\r
- FF_RX_D_2_23 => FF_RX_D_2_23,\r
- FF_RX_D_3_0 => FF_RX_D_3_0,\r
- FF_RX_D_3_1 => FF_RX_D_3_1,\r
- FF_RX_D_3_2 => FF_RX_D_3_2,\r
- FF_RX_D_3_3 => FF_RX_D_3_3,\r
- FF_RX_D_3_4 => FF_RX_D_3_4,\r
- FF_RX_D_3_5 => FF_RX_D_3_5,\r
- FF_RX_D_3_6 => FF_RX_D_3_6,\r
- FF_RX_D_3_7 => FF_RX_D_3_7,\r
- FF_RX_D_3_8 => FF_RX_D_3_8,\r
- FF_RX_D_3_9 => FF_RX_D_3_9,\r
- FF_RX_D_3_10 => FF_RX_D_3_10,\r
- FF_RX_D_3_11 => FF_RX_D_3_11,\r
- FF_RX_D_3_12 => FF_RX_D_3_12,\r
- FF_RX_D_3_13 => FF_RX_D_3_13,\r
- FF_RX_D_3_14 => FF_RX_D_3_14,\r
- FF_RX_D_3_15 => FF_RX_D_3_15,\r
- FF_RX_D_3_16 => FF_RX_D_3_16,\r
- FF_RX_D_3_17 => FF_RX_D_3_17,\r
- FF_RX_D_3_18 => FF_RX_D_3_18,\r
- FF_RX_D_3_19 => FF_RX_D_3_19,\r
- FF_RX_D_3_20 => FF_RX_D_3_20,\r
- FF_RX_D_3_21 => FF_RX_D_3_21,\r
- FF_RX_D_3_22 => FF_RX_D_3_22,\r
- FF_RX_D_3_23 => FF_RX_D_3_23,\r
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,\r
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,\r
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,\r
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,\r
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,\r
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,\r
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,\r
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,\r
- FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,\r
- FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,\r
- FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,\r
- FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,\r
- FF_TX_F_CLK => FF_TX_F_CLK,\r
- FF_TX_H_CLK => FF_TX_H_CLK,\r
- FF_TX_Q_CLK => FF_TX_Q_CLK,\r
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,\r
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,\r
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,\r
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,\r
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,\r
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,\r
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,\r
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,\r
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,\r
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,\r
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,\r
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,\r
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,\r
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,\r
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,\r
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,\r
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,\r
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,\r
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,\r
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,\r
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,\r
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,\r
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,\r
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,\r
- FFS_PLOL => FFS_PLOL,\r
- FFS_RLOL_0 => FFS_RLOL_0,\r
- FFS_RLOL_1 => FFS_RLOL_1,\r
- FFS_RLOL_2 => FFS_RLOL_2,\r
- FFS_RLOL_3 => FFS_RLOL_3,\r
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,\r
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,\r
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,\r
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,\r
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,\r
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,\r
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,\r
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,\r
- OOB_OUT_0 => OOB_OUT_0,\r
- OOB_OUT_1 => OOB_OUT_1,\r
- OOB_OUT_2 => OOB_OUT_2,\r
- OOB_OUT_3 => OOB_OUT_3,\r
- REFCK2CORE => REFCK2CORE,\r
- SCIINT => SCIINT,\r
- SCIRDATA0 => SCIRDATA0,\r
- SCIRDATA1 => SCIRDATA1,\r
- SCIRDATA2 => SCIRDATA2,\r
- SCIRDATA3 => SCIRDATA3,\r
- SCIRDATA4 => SCIRDATA4,\r
- SCIRDATA5 => SCIRDATA5,\r
- SCIRDATA6 => SCIRDATA6,\r
- SCIRDATA7 => SCIRDATA7\r
- );\r
-\r
-end PCSC_arch;\r
-\r
---synopsys translate_on\r
-\r
---synopsys translate_off\r
-library ECP2;\r
-use ECP2.components.all;\r
---synopsys translate_on\r
-\r
-library IEEE, STD;\r
-use IEEE.std_logic_1164.all;\r
-use STD.TEXTIO.all;\r
-\r
-entity serdes_gbe_0_extclock_8b is\r
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt");\r
- port (\r
- refclkp, refclkn : in std_logic;\r
- hdinp0, hdinn0 : in std_logic;\r
- hdoutp0, hdoutn0 : out std_logic;\r
- ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;\r
- ff_txdata_ch0 : in std_logic_vector (7 downto 0);\r
- ff_rxdata_ch0 : out std_logic_vector (7 downto 0);\r
- ff_tx_k_cntrl_ch0 : in std_logic;\r
- ff_rx_k_cntrl_ch0 : out std_logic;\r
- ff_rxfullclk_ch0 : out std_logic;\r
- ff_xmit_ch0 : in std_logic;\r
- ff_correct_disp_ch0 : in std_logic;\r
- ff_disp_err_ch0, ff_cv_ch0 : out std_logic;\r
- ff_rx_even_ch0 : out std_logic;\r
- ffc_rrst_ch0 : in std_logic;\r
- ffc_lane_tx_rst_ch0 : in std_logic;\r
- ffc_lane_rx_rst_ch0 : in std_logic;\r
- ffc_txpwdnb_ch0 : in std_logic;\r
- ffc_rxpwdnb_ch0 : in std_logic;\r
- ffs_rlos_lo_ch0 : out std_logic;\r
- ffs_ls_sync_status_ch0 : out std_logic;\r
- ffs_rlol_ch0 : out std_logic;\r
- oob_out_ch0 : out std_logic;\r
- ffc_macro_rst : in std_logic;\r
- ffc_quad_rst : in std_logic;\r
- ffc_trst : in std_logic;\r
- ff_txfullclk : out std_logic;\r
- ff_txhalfclk : out std_logic;\r
- refck2core : out std_logic;\r
- ffs_plol : out std_logic);\r
-\r
-end serdes_gbe_0_extclock_8b;\r
-\r
-architecture serdes_gbe_0_extclock_8b_arch of serdes_gbe_0_extclock_8b is\r
-\r
-component VLO\r
-port (\r
- Z : out std_logic);\r
-end component;\r
-\r
-component VHI\r
-port (\r
- Z : out std_logic);\r
-end component;\r
-component PCSC\r
---synopsys translate_off\r
-GENERIC(\r
- CONFIG_FILE : String\r
- );\r
---synopsys translate_on\r
-port (\r
- HDINN0 : in std_logic;\r
- HDINN1 : in std_logic;\r
- HDINN2 : in std_logic;\r
- HDINN3 : in std_logic;\r
- HDINP0 : in std_logic;\r
- HDINP1 : in std_logic;\r
- HDINP2 : in std_logic;\r
- HDINP3 : in std_logic;\r
- REFCLKN : in std_logic;\r
- REFCLKP : in std_logic;\r
- CIN0 : in std_logic;\r
- CIN1 : in std_logic;\r
- CIN2 : in std_logic;\r
- CIN3 : in std_logic;\r
- CIN4 : in std_logic;\r
- CIN5 : in std_logic;\r
- CIN6 : in std_logic;\r
- CIN7 : in std_logic;\r
- CIN8 : in std_logic;\r
- CIN9 : in std_logic;\r
- CIN10 : in std_logic;\r
- CIN11 : in std_logic;\r
- CYAWSTN : in std_logic;\r
- FF_EBRD_CLK_0 : in std_logic;\r
- FF_EBRD_CLK_1 : in std_logic;\r
- FF_EBRD_CLK_2 : in std_logic;\r
- FF_EBRD_CLK_3 : in std_logic;\r
- FF_RXI_CLK_0 : in std_logic;\r
- FF_RXI_CLK_1 : in std_logic;\r
- FF_RXI_CLK_2 : in std_logic;\r
- FF_RXI_CLK_3 : in std_logic;\r
- FF_TX_D_0_0 : in std_logic;\r
- FF_TX_D_0_1 : in std_logic;\r
- FF_TX_D_0_2 : in std_logic;\r
- FF_TX_D_0_3 : in std_logic;\r
- FF_TX_D_0_4 : in std_logic;\r
- FF_TX_D_0_5 : in std_logic;\r
- FF_TX_D_0_6 : in std_logic;\r
- FF_TX_D_0_7 : in std_logic;\r
- FF_TX_D_0_8 : in std_logic;\r
- FF_TX_D_0_9 : in std_logic;\r
- FF_TX_D_0_10 : in std_logic;\r
- FF_TX_D_0_11 : in std_logic;\r
- FF_TX_D_0_12 : in std_logic;\r
- FF_TX_D_0_13 : in std_logic;\r
- FF_TX_D_0_14 : in std_logic;\r
- FF_TX_D_0_15 : in std_logic;\r
- FF_TX_D_0_16 : in std_logic;\r
- FF_TX_D_0_17 : in std_logic;\r
- FF_TX_D_0_18 : in std_logic;\r
- FF_TX_D_0_19 : in std_logic;\r
- FF_TX_D_0_20 : in std_logic;\r
- FF_TX_D_0_21 : in std_logic;\r
- FF_TX_D_0_22 : in std_logic;\r
- FF_TX_D_0_23 : in std_logic;\r
- FF_TX_D_1_0 : in std_logic;\r
- FF_TX_D_1_1 : in std_logic;\r
- FF_TX_D_1_2 : in std_logic;\r
- FF_TX_D_1_3 : in std_logic;\r
- FF_TX_D_1_4 : in std_logic;\r
- FF_TX_D_1_5 : in std_logic;\r
- FF_TX_D_1_6 : in std_logic;\r
- FF_TX_D_1_7 : in std_logic;\r
- FF_TX_D_1_8 : in std_logic;\r
- FF_TX_D_1_9 : in std_logic;\r
- FF_TX_D_1_10 : in std_logic;\r
- FF_TX_D_1_11 : in std_logic;\r
- FF_TX_D_1_12 : in std_logic;\r
- FF_TX_D_1_13 : in std_logic;\r
- FF_TX_D_1_14 : in std_logic;\r
- FF_TX_D_1_15 : in std_logic;\r
- FF_TX_D_1_16 : in std_logic;\r
- FF_TX_D_1_17 : in std_logic;\r
- FF_TX_D_1_18 : in std_logic;\r
- FF_TX_D_1_19 : in std_logic;\r
- FF_TX_D_1_20 : in std_logic;\r
- FF_TX_D_1_21 : in std_logic;\r
- FF_TX_D_1_22 : in std_logic;\r
- FF_TX_D_1_23 : in std_logic;\r
- FF_TX_D_2_0 : in std_logic;\r
- FF_TX_D_2_1 : in std_logic;\r
- FF_TX_D_2_2 : in std_logic;\r
- FF_TX_D_2_3 : in std_logic;\r
- FF_TX_D_2_4 : in std_logic;\r
- FF_TX_D_2_5 : in std_logic;\r
- FF_TX_D_2_6 : in std_logic;\r
- FF_TX_D_2_7 : in std_logic;\r
- FF_TX_D_2_8 : in std_logic;\r
- FF_TX_D_2_9 : in std_logic;\r
- FF_TX_D_2_10 : in std_logic;\r
- FF_TX_D_2_11 : in std_logic;\r
- FF_TX_D_2_12 : in std_logic;\r
- FF_TX_D_2_13 : in std_logic;\r
- FF_TX_D_2_14 : in std_logic;\r
- FF_TX_D_2_15 : in std_logic;\r
- FF_TX_D_2_16 : in std_logic;\r
- FF_TX_D_2_17 : in std_logic;\r
- FF_TX_D_2_18 : in std_logic;\r
- FF_TX_D_2_19 : in std_logic;\r
- FF_TX_D_2_20 : in std_logic;\r
- FF_TX_D_2_21 : in std_logic;\r
- FF_TX_D_2_22 : in std_logic;\r
- FF_TX_D_2_23 : in std_logic;\r
- FF_TX_D_3_0 : in std_logic;\r
- FF_TX_D_3_1 : in std_logic;\r
- FF_TX_D_3_2 : in std_logic;\r
- FF_TX_D_3_3 : in std_logic;\r
- FF_TX_D_3_4 : in std_logic;\r
- FF_TX_D_3_5 : in std_logic;\r
- FF_TX_D_3_6 : in std_logic;\r
- FF_TX_D_3_7 : in std_logic;\r
- FF_TX_D_3_8 : in std_logic;\r
- FF_TX_D_3_9 : in std_logic;\r
- FF_TX_D_3_10 : in std_logic;\r
- FF_TX_D_3_11 : in std_logic;\r
- FF_TX_D_3_12 : in std_logic;\r
- FF_TX_D_3_13 : in std_logic;\r
- FF_TX_D_3_14 : in std_logic;\r
- FF_TX_D_3_15 : in std_logic;\r
- FF_TX_D_3_16 : in std_logic;\r
- FF_TX_D_3_17 : in std_logic;\r
- FF_TX_D_3_18 : in std_logic;\r
- FF_TX_D_3_19 : in std_logic;\r
- FF_TX_D_3_20 : in std_logic;\r
- FF_TX_D_3_21 : in std_logic;\r
- FF_TX_D_3_22 : in std_logic;\r
- FF_TX_D_3_23 : in std_logic;\r
- FF_TXI_CLK_0 : in std_logic;\r
- FF_TXI_CLK_1 : in std_logic;\r
- FF_TXI_CLK_2 : in std_logic;\r
- FF_TXI_CLK_3 : in std_logic;\r
- FFC_CK_CORE_RX : in std_logic;\r
- FFC_CK_CORE_TX : in std_logic;\r
- FFC_EI_EN_0 : in std_logic;\r
- FFC_EI_EN_1 : in std_logic;\r
- FFC_EI_EN_2 : in std_logic;\r
- FFC_EI_EN_3 : in std_logic;\r
- FFC_ENABLE_CGALIGN_0 : in std_logic;\r
- FFC_ENABLE_CGALIGN_1 : in std_logic;\r
- FFC_ENABLE_CGALIGN_2 : in std_logic;\r
- FFC_ENABLE_CGALIGN_3 : in std_logic;\r
- FFC_FB_LOOPBACK_0 : in std_logic;\r
- FFC_FB_LOOPBACK_1 : in std_logic;\r
- FFC_FB_LOOPBACK_2 : in std_logic;\r
- FFC_FB_LOOPBACK_3 : in std_logic;\r
- FFC_LANE_RX_RST_0 : in std_logic;\r
- FFC_LANE_RX_RST_1 : in std_logic;\r
- FFC_LANE_RX_RST_2 : in std_logic;\r
- FFC_LANE_RX_RST_3 : in std_logic;\r
- FFC_LANE_TX_RST_0 : in std_logic;\r
- FFC_LANE_TX_RST_1 : in std_logic;\r
- FFC_LANE_TX_RST_2 : in std_logic;\r
- FFC_LANE_TX_RST_3 : in std_logic;\r
- FFC_MACRO_RST : in std_logic;\r
- FFC_PCI_DET_EN_0 : in std_logic;\r
- FFC_PCI_DET_EN_1 : in std_logic;\r
- FFC_PCI_DET_EN_2 : in std_logic;\r
- FFC_PCI_DET_EN_3 : in std_logic;\r
- FFC_PCIE_CT_0 : in std_logic;\r
- FFC_PCIE_CT_1 : in std_logic;\r
- FFC_PCIE_CT_2 : in std_logic;\r
- FFC_PCIE_CT_3 : in std_logic;\r
- FFC_PFIFO_CLR_0 : in std_logic;\r
- FFC_PFIFO_CLR_1 : in std_logic;\r
- FFC_PFIFO_CLR_2 : in std_logic;\r
- FFC_PFIFO_CLR_3 : in std_logic;\r
- FFC_QUAD_RST : in std_logic;\r
- FFC_RRST_0 : in std_logic;\r
- FFC_RRST_1 : in std_logic;\r
- FFC_RRST_2 : in std_logic;\r
- FFC_RRST_3 : in std_logic;\r
- FFC_RXPWDNB_0 : in std_logic;\r
- FFC_RXPWDNB_1 : in std_logic;\r
- FFC_RXPWDNB_2 : in std_logic;\r
- FFC_RXPWDNB_3 : in std_logic;\r
- FFC_SB_INV_RX_0 : in std_logic;\r
- FFC_SB_INV_RX_1 : in std_logic;\r
- FFC_SB_INV_RX_2 : in std_logic;\r
- FFC_SB_INV_RX_3 : in std_logic;\r
- FFC_SB_PFIFO_LP_0 : in std_logic;\r
- FFC_SB_PFIFO_LP_1 : in std_logic;\r
- FFC_SB_PFIFO_LP_2 : in std_logic;\r
- FFC_SB_PFIFO_LP_3 : in std_logic;\r
- FFC_SIGNAL_DETECT_0 : in std_logic;\r
- FFC_SIGNAL_DETECT_1 : in std_logic;\r
- FFC_SIGNAL_DETECT_2 : in std_logic;\r
- FFC_SIGNAL_DETECT_3 : in std_logic;\r
- FFC_TRST : in std_logic;\r
- FFC_TXPWDNB_0 : in std_logic;\r
- FFC_TXPWDNB_1 : in std_logic;\r
- FFC_TXPWDNB_2 : in std_logic;\r
- FFC_TXPWDNB_3 : in std_logic;\r
- SCIADDR0 : in std_logic;\r
- SCIADDR1 : in std_logic;\r
- SCIADDR2 : in std_logic;\r
- SCIADDR3 : in std_logic;\r
- SCIADDR4 : in std_logic;\r
- SCIADDR5 : in std_logic;\r
- SCIENAUX : in std_logic;\r
- SCIENCH0 : in std_logic;\r
- SCIENCH1 : in std_logic;\r
- SCIENCH2 : in std_logic;\r
- SCIENCH3 : in std_logic;\r
- SCIRD : in std_logic;\r
- SCISELAUX : in std_logic;\r
- SCISELCH0 : in std_logic;\r
- SCISELCH1 : in std_logic;\r
- SCISELCH2 : in std_logic;\r
- SCISELCH3 : in std_logic;\r
- SCIWDATA0 : in std_logic;\r
- SCIWDATA1 : in std_logic;\r
- SCIWDATA2 : in std_logic;\r
- SCIWDATA3 : in std_logic;\r
- SCIWDATA4 : in std_logic;\r
- SCIWDATA5 : in std_logic;\r
- SCIWDATA6 : in std_logic;\r
- SCIWDATA7 : in std_logic;\r
- SCIWSTN : in std_logic;\r
- HDOUTN0 : out std_logic;\r
- HDOUTN1 : out std_logic;\r
- HDOUTN2 : out std_logic;\r
- HDOUTN3 : out std_logic;\r
- HDOUTP0 : out std_logic;\r
- HDOUTP1 : out std_logic;\r
- HDOUTP2 : out std_logic;\r
- HDOUTP3 : out std_logic;\r
- COUT0 : out std_logic;\r
- COUT1 : out std_logic;\r
- COUT2 : out std_logic;\r
- COUT3 : out std_logic;\r
- COUT4 : out std_logic;\r
- COUT5 : out std_logic;\r
- COUT6 : out std_logic;\r
- COUT7 : out std_logic;\r
- COUT8 : out std_logic;\r
- COUT9 : out std_logic;\r
- COUT10 : out std_logic;\r
- COUT11 : out std_logic;\r
- COUT12 : out std_logic;\r
- COUT13 : out std_logic;\r
- COUT14 : out std_logic;\r
- COUT15 : out std_logic;\r
- COUT16 : out std_logic;\r
- COUT17 : out std_logic;\r
- COUT18 : out std_logic;\r
- COUT19 : out std_logic;\r
- FF_RX_D_0_0 : out std_logic;\r
- FF_RX_D_0_1 : out std_logic;\r
- FF_RX_D_0_2 : out std_logic;\r
- FF_RX_D_0_3 : out std_logic;\r
- FF_RX_D_0_4 : out std_logic;\r
- FF_RX_D_0_5 : out std_logic;\r
- FF_RX_D_0_6 : out std_logic;\r
- FF_RX_D_0_7 : out std_logic;\r
- FF_RX_D_0_8 : out std_logic;\r
- FF_RX_D_0_9 : out std_logic;\r
- FF_RX_D_0_10 : out std_logic;\r
- FF_RX_D_0_11 : out std_logic;\r
- FF_RX_D_0_12 : out std_logic;\r
- FF_RX_D_0_13 : out std_logic;\r
- FF_RX_D_0_14 : out std_logic;\r
- FF_RX_D_0_15 : out std_logic;\r
- FF_RX_D_0_16 : out std_logic;\r
- FF_RX_D_0_17 : out std_logic;\r
- FF_RX_D_0_18 : out std_logic;\r
- FF_RX_D_0_19 : out std_logic;\r
- FF_RX_D_0_20 : out std_logic;\r
- FF_RX_D_0_21 : out std_logic;\r
- FF_RX_D_0_22 : out std_logic;\r
- FF_RX_D_0_23 : out std_logic;\r
- FF_RX_D_1_0 : out std_logic;\r
- FF_RX_D_1_1 : out std_logic;\r
- FF_RX_D_1_2 : out std_logic;\r
- FF_RX_D_1_3 : out std_logic;\r
- FF_RX_D_1_4 : out std_logic;\r
- FF_RX_D_1_5 : out std_logic;\r
- FF_RX_D_1_6 : out std_logic;\r
- FF_RX_D_1_7 : out std_logic;\r
- FF_RX_D_1_8 : out std_logic;\r
- FF_RX_D_1_9 : out std_logic;\r
- FF_RX_D_1_10 : out std_logic;\r
- FF_RX_D_1_11 : out std_logic;\r
- FF_RX_D_1_12 : out std_logic;\r
- FF_RX_D_1_13 : out std_logic;\r
- FF_RX_D_1_14 : out std_logic;\r
- FF_RX_D_1_15 : out std_logic;\r
- FF_RX_D_1_16 : out std_logic;\r
- FF_RX_D_1_17 : out std_logic;\r
- FF_RX_D_1_18 : out std_logic;\r
- FF_RX_D_1_19 : out std_logic;\r
- FF_RX_D_1_20 : out std_logic;\r
- FF_RX_D_1_21 : out std_logic;\r
- FF_RX_D_1_22 : out std_logic;\r
- FF_RX_D_1_23 : out std_logic;\r
- FF_RX_D_2_0 : out std_logic;\r
- FF_RX_D_2_1 : out std_logic;\r
- FF_RX_D_2_2 : out std_logic;\r
- FF_RX_D_2_3 : out std_logic;\r
- FF_RX_D_2_4 : out std_logic;\r
- FF_RX_D_2_5 : out std_logic;\r
- FF_RX_D_2_6 : out std_logic;\r
- FF_RX_D_2_7 : out std_logic;\r
- FF_RX_D_2_8 : out std_logic;\r
- FF_RX_D_2_9 : out std_logic;\r
- FF_RX_D_2_10 : out std_logic;\r
- FF_RX_D_2_11 : out std_logic;\r
- FF_RX_D_2_12 : out std_logic;\r
- FF_RX_D_2_13 : out std_logic;\r
- FF_RX_D_2_14 : out std_logic;\r
- FF_RX_D_2_15 : out std_logic;\r
- FF_RX_D_2_16 : out std_logic;\r
- FF_RX_D_2_17 : out std_logic;\r
- FF_RX_D_2_18 : out std_logic;\r
- FF_RX_D_2_19 : out std_logic;\r
- FF_RX_D_2_20 : out std_logic;\r
- FF_RX_D_2_21 : out std_logic;\r
- FF_RX_D_2_22 : out std_logic;\r
- FF_RX_D_2_23 : out std_logic;\r
- FF_RX_D_3_0 : out std_logic;\r
- FF_RX_D_3_1 : out std_logic;\r
- FF_RX_D_3_2 : out std_logic;\r
- FF_RX_D_3_3 : out std_logic;\r
- FF_RX_D_3_4 : out std_logic;\r
- FF_RX_D_3_5 : out std_logic;\r
- FF_RX_D_3_6 : out std_logic;\r
- FF_RX_D_3_7 : out std_logic;\r
- FF_RX_D_3_8 : out std_logic;\r
- FF_RX_D_3_9 : out std_logic;\r
- FF_RX_D_3_10 : out std_logic;\r
- FF_RX_D_3_11 : out std_logic;\r
- FF_RX_D_3_12 : out std_logic;\r
- FF_RX_D_3_13 : out std_logic;\r
- FF_RX_D_3_14 : out std_logic;\r
- FF_RX_D_3_15 : out std_logic;\r
- FF_RX_D_3_16 : out std_logic;\r
- FF_RX_D_3_17 : out std_logic;\r
- FF_RX_D_3_18 : out std_logic;\r
- FF_RX_D_3_19 : out std_logic;\r
- FF_RX_D_3_20 : out std_logic;\r
- FF_RX_D_3_21 : out std_logic;\r
- FF_RX_D_3_22 : out std_logic;\r
- FF_RX_D_3_23 : out std_logic;\r
- FF_RX_F_CLK_0 : out std_logic;\r
- FF_RX_F_CLK_1 : out std_logic;\r
- FF_RX_F_CLK_2 : out std_logic;\r
- FF_RX_F_CLK_3 : out std_logic;\r
- FF_RX_H_CLK_0 : out std_logic;\r
- FF_RX_H_CLK_1 : out std_logic;\r
- FF_RX_H_CLK_2 : out std_logic;\r
- FF_RX_H_CLK_3 : out std_logic;\r
- FF_RX_Q_CLK_0 : out std_logic;\r
- FF_RX_Q_CLK_1 : out std_logic;\r
- FF_RX_Q_CLK_2 : out std_logic;\r
- FF_RX_Q_CLK_3 : out std_logic;\r
- FF_TX_F_CLK : out std_logic;\r
- FF_TX_H_CLK : out std_logic;\r
- FF_TX_Q_CLK : out std_logic;\r
- FFS_CC_OVERRUN_0 : out std_logic;\r
- FFS_CC_OVERRUN_1 : out std_logic;\r
- FFS_CC_OVERRUN_2 : out std_logic;\r
- FFS_CC_OVERRUN_3 : out std_logic;\r
- FFS_CC_UNDERRUN_0 : out std_logic;\r
- FFS_CC_UNDERRUN_1 : out std_logic;\r
- FFS_CC_UNDERRUN_2 : out std_logic;\r
- FFS_CC_UNDERRUN_3 : out std_logic;\r
- FFS_LS_SYNC_STATUS_0 : out std_logic;\r
- FFS_LS_SYNC_STATUS_1 : out std_logic;\r
- FFS_LS_SYNC_STATUS_2 : out std_logic;\r
- FFS_LS_SYNC_STATUS_3 : out std_logic;\r
- FFS_PCIE_CON_0 : out std_logic;\r
- FFS_PCIE_CON_1 : out std_logic;\r
- FFS_PCIE_CON_2 : out std_logic;\r
- FFS_PCIE_CON_3 : out std_logic;\r
- FFS_PCIE_DONE_0 : out std_logic;\r
- FFS_PCIE_DONE_1 : out std_logic;\r
- FFS_PCIE_DONE_2 : out std_logic;\r
- FFS_PCIE_DONE_3 : out std_logic;\r
- FFS_RLOS_LO_0 : out std_logic;\r
- FFS_RLOS_LO_1 : out std_logic;\r
- FFS_RLOS_LO_2 : out std_logic;\r
- FFS_RLOS_LO_3 : out std_logic;\r
- OOB_OUT_0 : out std_logic;\r
- OOB_OUT_1 : out std_logic;\r
- OOB_OUT_2 : out std_logic;\r
- OOB_OUT_3 : out std_logic;\r
- REFCK2CORE : out std_logic;\r
- SCIINT : out std_logic;\r
- SCIRDATA0 : out std_logic;\r
- SCIRDATA1 : out std_logic;\r
- SCIRDATA2 : out std_logic;\r
- SCIRDATA3 : out std_logic;\r
- SCIRDATA4 : out std_logic;\r
- SCIRDATA5 : out std_logic;\r
- SCIRDATA6 : out std_logic;\r
- SCIRDATA7 : out std_logic;\r
- FFS_PLOL : out std_logic;\r
- FFS_RLOL_0 : out std_logic;\r
- FFS_RLOL_1 : out std_logic;\r
- FFS_RLOL_2 : out std_logic;\r
- FFS_RLOL_3 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
- FFS_TXFBFIFO_ERROR_3 : out std_logic\r
-);\r
-end component;\r
- attribute IS_ASB: string;\r
- attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";\r
- attribute CONFIG_FILE: string;\r
- attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;\r
- attribute black_box_pad_pin: string;\r
- attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";\r
-\r
-signal fpsc_vlo : std_logic := '0';\r
-signal cin : std_logic_vector (11 downto 0) := "000000000000";\r
-signal cout : std_logic_vector (19 downto 0);\r
-\r
-begin\r
-\r
-vlo_inst : VLO port map(Z => fpsc_vlo);\r
-\r
--- pcs_quad instance\r
-PCSC_INST : PCSC\r
---synopsys translate_off\r
- generic map (CONFIG_FILE => USER_CONFIG_FILE)\r
---synopsys translate_on\r
-port map (\r
- FFC_CK_CORE_TX => fpsc_vlo,\r
- FFC_CK_CORE_RX => fpsc_vlo,\r
- REFCLKP => refclkp,\r
- REFCLKN => refclkn,\r
- HDINP0 => hdinp0,\r
- HDINN0 => hdinn0,\r
- HDOUTP0 => hdoutp0,\r
- HDOUTN0 => hdoutn0,\r
- SCISELCH0 => fpsc_vlo,\r
- SCIENCH0 => fpsc_vlo,\r
- FF_RXI_CLK_0 => ff_rxiclk_ch0,\r
- FF_TXI_CLK_0 => ff_txiclk_ch0,\r
- FF_EBRD_CLK_0 => ff_ebrd_clk_0,\r
- FF_RX_F_CLK_0 => ff_rxfullclk_ch0,\r
- FF_RX_H_CLK_0 => open,\r
- FF_RX_Q_CLK_0 => open,\r
- FF_TX_D_0_0 => ff_txdata_ch0(0),\r
- FF_TX_D_0_1 => ff_txdata_ch0(1),\r
- FF_TX_D_0_2 => ff_txdata_ch0(2),\r
- FF_TX_D_0_3 => ff_txdata_ch0(3),\r
- FF_TX_D_0_4 => ff_txdata_ch0(4),\r
- FF_TX_D_0_5 => ff_txdata_ch0(5),\r
- FF_TX_D_0_6 => ff_txdata_ch0(6),\r
- FF_TX_D_0_7 => ff_txdata_ch0(7),\r
- FF_TX_D_0_8 => ff_tx_k_cntrl_ch0,\r
- FF_TX_D_0_9 => fpsc_vlo,\r
- FF_TX_D_0_10 => ff_xmit_ch0,\r
- FF_TX_D_0_11 => ff_correct_disp_ch0,\r
- FF_TX_D_0_12 => fpsc_vlo,\r
- FF_TX_D_0_13 => fpsc_vlo,\r
- FF_TX_D_0_14 => fpsc_vlo,\r
- FF_TX_D_0_15 => fpsc_vlo,\r
- FF_TX_D_0_16 => fpsc_vlo,\r
- FF_TX_D_0_17 => fpsc_vlo,\r
- FF_TX_D_0_18 => fpsc_vlo,\r
- FF_TX_D_0_19 => fpsc_vlo,\r
- FF_TX_D_0_20 => fpsc_vlo,\r
- FF_TX_D_0_21 => fpsc_vlo,\r
- FF_TX_D_0_22 => fpsc_vlo,\r
- FF_TX_D_0_23 => fpsc_vlo,\r
- FF_RX_D_0_0 => ff_rxdata_ch0(0),\r
- FF_RX_D_0_1 => ff_rxdata_ch0(1),\r
- FF_RX_D_0_2 => ff_rxdata_ch0(2),\r
- FF_RX_D_0_3 => ff_rxdata_ch0(3),\r
- FF_RX_D_0_4 => ff_rxdata_ch0(4),\r
- FF_RX_D_0_5 => ff_rxdata_ch0(5),\r
- FF_RX_D_0_6 => ff_rxdata_ch0(6),\r
- FF_RX_D_0_7 => ff_rxdata_ch0(7),\r
- FF_RX_D_0_8 => ff_rx_k_cntrl_ch0,\r
- FF_RX_D_0_9 => ff_disp_err_ch0,\r
- FF_RX_D_0_10 => ff_cv_ch0,\r
- FF_RX_D_0_11 => ff_rx_even_ch0,\r
- FF_RX_D_0_12 => open,\r
- FF_RX_D_0_13 => open,\r
- FF_RX_D_0_14 => open,\r
- FF_RX_D_0_15 => open,\r
- FF_RX_D_0_16 => open,\r
- FF_RX_D_0_17 => open,\r
- FF_RX_D_0_18 => open,\r
- FF_RX_D_0_19 => open,\r
- FF_RX_D_0_20 => open,\r
- FF_RX_D_0_21 => open,\r
- FF_RX_D_0_22 => open,\r
- FF_RX_D_0_23 => open,\r
- FFC_RRST_0 => ffc_rrst_ch0,\r
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,\r
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,\r
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,\r
- FFC_PFIFO_CLR_0 => fpsc_vlo,\r
- FFC_FB_LOOPBACK_0 => fpsc_vlo,\r
- FFC_SB_INV_RX_0 => fpsc_vlo,\r
- FFC_PCIE_CT_0 => fpsc_vlo,\r
- FFC_PCI_DET_EN_0 => fpsc_vlo,\r
- FFS_PCIE_DONE_0 => open,\r
- FFS_PCIE_CON_0 => open,\r
- FFC_EI_EN_0 => fpsc_vlo,\r
- FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0,\r
- FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0,\r
- FFC_TXPWDNB_0 => ffc_txpwdnb_ch0,\r
- FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0,\r
- FFS_RLOS_LO_0 => ffs_rlos_lo_ch0,\r
- FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0,\r
- FFS_CC_UNDERRUN_0 => open,\r
- FFS_CC_OVERRUN_0 => open,\r
- FFS_RXFBFIFO_ERROR_0 => open,\r
- FFS_TXFBFIFO_ERROR_0 => open,\r
- FFS_RLOL_0 => ffs_rlol_ch0,\r
- OOB_OUT_0 => oob_out_ch0,\r
- HDINP1 => fpsc_vlo,\r
- HDINN1 => fpsc_vlo,\r
- HDOUTP1 => open,\r
- HDOUTN1 => open,\r
- SCISELCH1 => fpsc_vlo,\r
- SCIENCH1 => fpsc_vlo,\r
- FF_RXI_CLK_1 => fpsc_vlo,\r
- FF_TXI_CLK_1 => fpsc_vlo,\r
- FF_EBRD_CLK_1 => fpsc_vlo,\r
- FF_RX_F_CLK_1 => open,\r
- FF_RX_H_CLK_1 => open,\r
- FF_RX_Q_CLK_1 => open,\r
- FF_TX_D_1_0 => fpsc_vlo,\r
- FF_TX_D_1_1 => fpsc_vlo,\r
- FF_TX_D_1_2 => fpsc_vlo,\r
- FF_TX_D_1_3 => fpsc_vlo,\r
- FF_TX_D_1_4 => fpsc_vlo,\r
- FF_TX_D_1_5 => fpsc_vlo,\r
- FF_TX_D_1_6 => fpsc_vlo,\r
- FF_TX_D_1_7 => fpsc_vlo,\r
- FF_TX_D_1_8 => fpsc_vlo,\r
- FF_TX_D_1_9 => fpsc_vlo,\r
- FF_TX_D_1_10 => fpsc_vlo,\r
- FF_TX_D_1_11 => fpsc_vlo,\r
- FF_TX_D_1_12 => fpsc_vlo,\r
- FF_TX_D_1_13 => fpsc_vlo,\r
- FF_TX_D_1_14 => fpsc_vlo,\r
- FF_TX_D_1_15 => fpsc_vlo,\r
- FF_TX_D_1_16 => fpsc_vlo,\r
- FF_TX_D_1_17 => fpsc_vlo,\r
- FF_TX_D_1_18 => fpsc_vlo,\r
- FF_TX_D_1_19 => fpsc_vlo,\r
- FF_TX_D_1_20 => fpsc_vlo,\r
- FF_TX_D_1_21 => fpsc_vlo,\r
- FF_TX_D_1_22 => fpsc_vlo,\r
- FF_TX_D_1_23 => fpsc_vlo,\r
- FF_RX_D_1_0 => open,\r
- FF_RX_D_1_1 => open,\r
- FF_RX_D_1_2 => open,\r
- FF_RX_D_1_3 => open,\r
- FF_RX_D_1_4 => open,\r
- FF_RX_D_1_5 => open,\r
- FF_RX_D_1_6 => open,\r
- FF_RX_D_1_7 => open,\r
- FF_RX_D_1_8 => open,\r
- FF_RX_D_1_9 => open,\r
- FF_RX_D_1_10 => open,\r
- FF_RX_D_1_11 => open,\r
- FF_RX_D_1_12 => open,\r
- FF_RX_D_1_13 => open,\r
- FF_RX_D_1_14 => open,\r
- FF_RX_D_1_15 => open,\r
- FF_RX_D_1_16 => open,\r
- FF_RX_D_1_17 => open,\r
- FF_RX_D_1_18 => open,\r
- FF_RX_D_1_19 => open,\r
- FF_RX_D_1_20 => open,\r
- FF_RX_D_1_21 => open,\r
- FF_RX_D_1_22 => open,\r
- FF_RX_D_1_23 => open,\r
- FFC_RRST_1 => fpsc_vlo,\r
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,\r
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,\r
- FFC_SB_INV_RX_1 => fpsc_vlo,\r
- FFC_PFIFO_CLR_1 => fpsc_vlo,\r
- FFC_PCIE_CT_1 => fpsc_vlo,\r
- FFC_PCI_DET_EN_1 => fpsc_vlo,\r
- FFC_FB_LOOPBACK_1 => fpsc_vlo,\r
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,\r
- FFC_EI_EN_1 => fpsc_vlo,\r
- FFC_LANE_TX_RST_1 => fpsc_vlo,\r
- FFC_LANE_RX_RST_1 => fpsc_vlo,\r
- FFC_TXPWDNB_1 => fpsc_vlo,\r
- FFC_RXPWDNB_1 => fpsc_vlo,\r
- FFS_RLOS_LO_1 => open,\r
- FFS_PCIE_DONE_1 => open,\r
- FFS_PCIE_CON_1 => open,\r
- FFS_LS_SYNC_STATUS_1 => open,\r
- FFS_CC_UNDERRUN_1 => open,\r
- FFS_CC_OVERRUN_1 => open,\r
- FFS_RLOL_1 => open,\r
- FFS_RXFBFIFO_ERROR_1 => open,\r
- FFS_TXFBFIFO_ERROR_1 => open,\r
- OOB_OUT_1 => open,\r
- HDINP2 => fpsc_vlo,\r
- HDINN2 => fpsc_vlo,\r
- HDOUTP2 => open,\r
- HDOUTN2 => open,\r
- SCISELCH2 => fpsc_vlo,\r
- SCIENCH2 => fpsc_vlo,\r
- FF_RXI_CLK_2 => fpsc_vlo,\r
- FF_TXI_CLK_2 => fpsc_vlo,\r
- FF_EBRD_CLK_2 => fpsc_vlo,\r
- FF_RX_F_CLK_2 => open,\r
- FF_RX_H_CLK_2 => open,\r
- FF_RX_Q_CLK_2 => open,\r
- FF_TX_D_2_0 => fpsc_vlo,\r
- FF_TX_D_2_1 => fpsc_vlo,\r
- FF_TX_D_2_2 => fpsc_vlo,\r
- FF_TX_D_2_3 => fpsc_vlo,\r
- FF_TX_D_2_4 => fpsc_vlo,\r
- FF_TX_D_2_5 => fpsc_vlo,\r
- FF_TX_D_2_6 => fpsc_vlo,\r
- FF_TX_D_2_7 => fpsc_vlo,\r
- FF_TX_D_2_8 => fpsc_vlo,\r
- FF_TX_D_2_9 => fpsc_vlo,\r
- FF_TX_D_2_10 => fpsc_vlo,\r
- FF_TX_D_2_11 => fpsc_vlo,\r
- FF_TX_D_2_12 => fpsc_vlo,\r
- FF_TX_D_2_13 => fpsc_vlo,\r
- FF_TX_D_2_14 => fpsc_vlo,\r
- FF_TX_D_2_15 => fpsc_vlo,\r
- FF_TX_D_2_16 => fpsc_vlo,\r
- FF_TX_D_2_17 => fpsc_vlo,\r
- FF_TX_D_2_18 => fpsc_vlo,\r
- FF_TX_D_2_19 => fpsc_vlo,\r
- FF_TX_D_2_20 => fpsc_vlo,\r
- FF_TX_D_2_21 => fpsc_vlo,\r
- FF_TX_D_2_22 => fpsc_vlo,\r
- FF_TX_D_2_23 => fpsc_vlo,\r
- FF_RX_D_2_0 => open,\r
- FF_RX_D_2_1 => open,\r
- FF_RX_D_2_2 => open,\r
- FF_RX_D_2_3 => open,\r
- FF_RX_D_2_4 => open,\r
- FF_RX_D_2_5 => open,\r
- FF_RX_D_2_6 => open,\r
- FF_RX_D_2_7 => open,\r
- FF_RX_D_2_8 => open,\r
- FF_RX_D_2_9 => open,\r
- FF_RX_D_2_10 => open,\r
- FF_RX_D_2_11 => open,\r
- FF_RX_D_2_12 => open,\r
- FF_RX_D_2_13 => open,\r
- FF_RX_D_2_14 => open,\r
- FF_RX_D_2_15 => open,\r
- FF_RX_D_2_16 => open,\r
- FF_RX_D_2_17 => open,\r
- FF_RX_D_2_18 => open,\r
- FF_RX_D_2_19 => open,\r
- FF_RX_D_2_20 => open,\r
- FF_RX_D_2_21 => open,\r
- FF_RX_D_2_22 => open,\r
- FF_RX_D_2_23 => open,\r
- FFC_RRST_2 => fpsc_vlo,\r
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,\r
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,\r
- FFC_SB_INV_RX_2 => fpsc_vlo,\r
- FFC_PFIFO_CLR_2 => fpsc_vlo,\r
- FFC_PCIE_CT_2 => fpsc_vlo,\r
- FFC_PCI_DET_EN_2 => fpsc_vlo,\r
- FFC_FB_LOOPBACK_2 => fpsc_vlo,\r
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,\r
- FFC_EI_EN_2 => fpsc_vlo,\r
- FFC_LANE_TX_RST_2 => fpsc_vlo,\r
- FFC_LANE_RX_RST_2 => fpsc_vlo,\r
- FFC_TXPWDNB_2 => fpsc_vlo,\r
- FFC_RXPWDNB_2 => fpsc_vlo,\r
- FFS_RLOS_LO_2 => open,\r
- FFS_PCIE_DONE_2 => open,\r
- FFS_PCIE_CON_2 => open,\r
- FFS_LS_SYNC_STATUS_2 => open,\r
- FFS_CC_UNDERRUN_2 => open,\r
- FFS_CC_OVERRUN_2 => open,\r
- FFS_RLOL_2 => open,\r
- FFS_RXFBFIFO_ERROR_2 => open,\r
- FFS_TXFBFIFO_ERROR_2 => open,\r
- OOB_OUT_2 => open,\r
- HDINP3 => fpsc_vlo,\r
- HDINN3 => fpsc_vlo,\r
- HDOUTP3 => open,\r
- HDOUTN3 => open,\r
- SCISELCH3 => fpsc_vlo,\r
- SCIENCH3 => fpsc_vlo,\r
- FF_RXI_CLK_3 => fpsc_vlo,\r
- FF_TXI_CLK_3 => fpsc_vlo,\r
- FF_EBRD_CLK_3 => fpsc_vlo,\r
- FF_RX_F_CLK_3 => open,\r
- FF_RX_H_CLK_3 => open,\r
- FF_RX_Q_CLK_3 => open,\r
- FF_TX_D_3_0 => fpsc_vlo,\r
- FF_TX_D_3_1 => fpsc_vlo,\r
- FF_TX_D_3_2 => fpsc_vlo,\r
- FF_TX_D_3_3 => fpsc_vlo,\r
- FF_TX_D_3_4 => fpsc_vlo,\r
- FF_TX_D_3_5 => fpsc_vlo,\r
- FF_TX_D_3_6 => fpsc_vlo,\r
- FF_TX_D_3_7 => fpsc_vlo,\r
- FF_TX_D_3_8 => fpsc_vlo,\r
- FF_TX_D_3_9 => fpsc_vlo,\r
- FF_TX_D_3_10 => fpsc_vlo,\r
- FF_TX_D_3_11 => fpsc_vlo,\r
- FF_TX_D_3_12 => fpsc_vlo,\r
- FF_TX_D_3_13 => fpsc_vlo,\r
- FF_TX_D_3_14 => fpsc_vlo,\r
- FF_TX_D_3_15 => fpsc_vlo,\r
- FF_TX_D_3_16 => fpsc_vlo,\r
- FF_TX_D_3_17 => fpsc_vlo,\r
- FF_TX_D_3_18 => fpsc_vlo,\r
- FF_TX_D_3_19 => fpsc_vlo,\r
- FF_TX_D_3_20 => fpsc_vlo,\r
- FF_TX_D_3_21 => fpsc_vlo,\r
- FF_TX_D_3_22 => fpsc_vlo,\r
- FF_TX_D_3_23 => fpsc_vlo,\r
- FF_RX_D_3_0 => open,\r
- FF_RX_D_3_1 => open,\r
- FF_RX_D_3_2 => open,\r
- FF_RX_D_3_3 => open,\r
- FF_RX_D_3_4 => open,\r
- FF_RX_D_3_5 => open,\r
- FF_RX_D_3_6 => open,\r
- FF_RX_D_3_7 => open,\r
- FF_RX_D_3_8 => open,\r
- FF_RX_D_3_9 => open,\r
- FF_RX_D_3_10 => open,\r
- FF_RX_D_3_11 => open,\r
- FF_RX_D_3_12 => open,\r
- FF_RX_D_3_13 => open,\r
- FF_RX_D_3_14 => open,\r
- FF_RX_D_3_15 => open,\r
- FF_RX_D_3_16 => open,\r
- FF_RX_D_3_17 => open,\r
- FF_RX_D_3_18 => open,\r
- FF_RX_D_3_19 => open,\r
- FF_RX_D_3_20 => open,\r
- FF_RX_D_3_21 => open,\r
- FF_RX_D_3_22 => open,\r
- FF_RX_D_3_23 => open,\r
- FFC_RRST_3 => fpsc_vlo,\r
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,\r
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,\r
- FFC_SB_INV_RX_3 => fpsc_vlo,\r
- FFC_PFIFO_CLR_3 => fpsc_vlo,\r
- FFC_PCIE_CT_3 => fpsc_vlo,\r
- FFC_PCI_DET_EN_3 => fpsc_vlo,\r
- FFC_FB_LOOPBACK_3 => fpsc_vlo,\r
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,\r
- FFC_EI_EN_3 => fpsc_vlo,\r
- FFC_LANE_TX_RST_3 => fpsc_vlo,\r
- FFC_LANE_RX_RST_3 => fpsc_vlo,\r
- FFC_TXPWDNB_3 => fpsc_vlo,\r
- FFC_RXPWDNB_3 => fpsc_vlo,\r
- FFS_RLOS_LO_3 => open,\r
- FFS_PCIE_DONE_3 => open,\r
- FFS_PCIE_CON_3 => open,\r
- FFS_LS_SYNC_STATUS_3 => open,\r
- FFS_CC_UNDERRUN_3 => open,\r
- FFS_CC_OVERRUN_3 => open,\r
- FFS_RLOL_3 => open,\r
- FFS_RXFBFIFO_ERROR_3 => open,\r
- FFS_TXFBFIFO_ERROR_3 => open,\r
- OOB_OUT_3 => open,\r
- SCIWDATA0 => fpsc_vlo,\r
- SCIWDATA1 => fpsc_vlo,\r
- SCIWDATA2 => fpsc_vlo,\r
- SCIWDATA3 => fpsc_vlo,\r
- SCIWDATA4 => fpsc_vlo,\r
- SCIWDATA5 => fpsc_vlo,\r
- SCIWDATA6 => fpsc_vlo,\r
- SCIWDATA7 => fpsc_vlo,\r
- SCIADDR0 => fpsc_vlo,\r
- SCIADDR1 => fpsc_vlo,\r
- SCIADDR2 => fpsc_vlo,\r
- SCIADDR3 => fpsc_vlo,\r
- SCIADDR4 => fpsc_vlo,\r
- SCIADDR5 => fpsc_vlo,\r
- SCIRDATA0 => open,\r
- SCIRDATA1 => open,\r
- SCIRDATA2 => open,\r
- SCIRDATA3 => open,\r
- SCIRDATA4 => open,\r
- SCIRDATA5 => open,\r
- SCIRDATA6 => open,\r
- SCIRDATA7 => open,\r
- SCIENAUX => fpsc_vlo,\r
- SCISELAUX => fpsc_vlo,\r
- SCIRD => fpsc_vlo,\r
- SCIWSTN => fpsc_vlo,\r
- CYAWSTN => fpsc_vlo,\r
- SCIINT => open,\r
- FFC_MACRO_RST => ffc_macro_rst,\r
- FFC_QUAD_RST => ffc_quad_rst,\r
- FFC_TRST => ffc_trst,\r
- FF_TX_F_CLK => ff_txfullclk,\r
- FF_TX_H_CLK => ff_txhalfclk,\r
- FF_TX_Q_CLK => open,\r
- REFCK2CORE => refck2core,\r
- CIN0 => cin(0),\r
- CIN1 => cin(1),\r
- CIN2 => cin(2),\r
- CIN3 => cin(3),\r
- CIN4 => cin(4),\r
- CIN5 => cin(5),\r
- CIN6 => cin(6),\r
- CIN7 => cin(7),\r
- CIN8 => cin(8),\r
- CIN9 => cin(9),\r
- CIN10 => cin(10),\r
- CIN11 => cin(11),\r
- COUT0 => cout(0),\r
- COUT1 => cout(1),\r
- COUT2 => cout(2),\r
- COUT3 => cout(3),\r
- COUT4 => cout(4),\r
- COUT5 => cout(5),\r
- COUT6 => cout(6),\r
- COUT7 => cout(7),\r
- COUT8 => cout(8),\r
- COUT9 => cout(9),\r
- COUT10 => cout(10),\r
- COUT11 => cout(11),\r
- COUT12 => cout(12),\r
- COUT13 => cout(13),\r
- COUT14 => cout(14),\r
- COUT15 => cout(15),\r
- COUT16 => cout(16),\r
- COUT17 => cout(17),\r
- COUT18 => cout(18),\r
- COUT19 => cout(19),\r
- FFS_PLOL => ffs_plol);\r
-\r
---synopsys translate_off\r
-file_read : PROCESS\r
-VARIABLE open_status : file_open_status;\r
-FILE config : text;\r
-BEGIN\r
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);\r
- IF (open_status = name_error) THEN\r
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"\r
- severity ERROR;\r
- END IF;\r
- wait;\r
-END PROCESS;\r
---synopsys translate_on\r
-\r
-end serdes_gbe_0_extclock_8b_arch ;\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_ch4" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 04 04 20:33:50.582" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_ch4.lpc" type="lpc" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.pp" type="pp" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.sym" type="sym" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.tft" type="tft" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.txt" type="pcs_module" modified="2012 04 04 20:33:49.000"/>
- <File name="serdes_ch4.vhd" type="top_level_vhdl" modified="2012 04 04 20:33:49.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-MODULE serdes_ch4 DEFIN serdes_ch4.vhd
- SUBMODULE PCSD
- INSTANCE PCSD_INST
- SUBMODULE VHI
- INSTANCE vhi_inst
- SUBMODULE VLO
- INSTANCE vlo_inst
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_ch4
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/04/2012
-Time=20:33:49
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=RXTX
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=GIGE
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=1.25
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=125.0
-_tx_protocol0=DISABLED
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=GIGE
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=125.0
-_tx_ficlk_rate1=125.0
-_tx_ficlk_rate2=125.0
-_tx_ficlk_rate3=125.0
-_pll_rxsrc0=EXTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2.5
-_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=1.25
-_rx_protocol0=DISABLED
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=GIGE
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=250.0
-_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=125.0
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
-_rx_ficlk_rate0=250.0
-_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=125.0
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=AC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=AC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P5
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111111
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=2
-_k00=00
-_k01=00
-_k02=00
-_k03=01
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=00
-_byten00=00000000
-_byten01=00000000
-_byten02=00000000
-_byten03=10111100
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=01010000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=10111100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=01010000
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=DISABLED
-_sci_int_port=DISABLED
-_refck2core=DISABLED
-Regen=auto
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_ch4.pp=pp
-serdes_ch4.tft=tft
-serdes_ch4.txt=pcs_module
-serdes_ch4.sym=sym
+++ /dev/null
-hdinp_ch3 i
-hdinn_ch3 i
-hdoutp_ch3 o
-hdoutn_ch3 o
-rxiclk_ch3 i
-txiclk_ch3 i
-rx_full_clk_ch3 o
-rx_half_clk_ch3 o
-tx_full_clk_ch3 o
-tx_half_clk_ch3 o
-fpga_rxrefclk_ch3 i
-txdata_ch3[7] i
-txdata_ch3[6] i
-txdata_ch3[5] i
-txdata_ch3[4] i
-txdata_ch3[3] i
-txdata_ch3[2] i
-txdata_ch3[1] i
-txdata_ch3[0] i
-tx_k_ch3 i
-xmit_ch3 i
-tx_disp_correct_ch3 i
-rxdata_ch3[7] o
-rxdata_ch3[6] o
-rxdata_ch3[5] o
-rxdata_ch3[4] o
-rxdata_ch3[3] o
-rxdata_ch3[2] o
-rxdata_ch3[1] o
-rxdata_ch3[0] o
-rx_k_ch3 o
-rx_disp_err_ch3 o
-rx_cv_err_ch3 o
-rx_serdes_rst_ch3_c i
-sb_felb_ch3_c i
-sb_felb_rst_ch3_c i
-tx_pcs_rst_ch3_c i
-tx_pwrup_ch3_c i
-rx_pcs_rst_ch3_c i
-rx_pwrup_ch3_c i
-rx_los_low_ch3_s o
-lsm_status_ch3_s o
-rx_cdr_lol_ch3_s o
-fpga_txrefclk i
-tx_serdes_rst_c i
-tx_pll_lol_qd_s o
-rst_qd_c i
-serdes_rst_qd_c i
+++ /dev/null
-#define _device_name "LFE3-150EA"
-#define _ch0_pll_rxsrc "REFCLK_EXT"
-#define _ch0_mode "DISABLED"
-#define _ch0_protocol "G8B10B"
-#define _ch0_ldr "DISABLED"
-#define _ch0_tx_data_rate "FULL"
-#define _ch0_tx_data_width "8"
-#define _ch0_tx_fifo "ENABLED"
-#define _ch0_tx_ficlk_rate 125.0
-#define _ch0_rx_datarange "MEDHIGH"
-#define _ch0_rx_data_rate "FULL"
-#define _ch0_rxrefclk_rate "250.0"
-#define _ch0_rx_data_width "8"
-#define _ch0_rx_fifo "ENABLED"
-#define _ch0_rx_ficlk_rate 250.0
-#define _ch0_tdrv "0"
-#define _ch0_tx_pre "DISABLED"
-#define _ch0_rterm_tx "50"
-#define _ch0_rx_eq "DISABLED"
-#define _ch0_rterm_rx "50"
-#define _ch0_rx_dcc "AC"
-#define _los_threshold_lo0 "2"
-#define _ch0_tx_sb "DISABLED"
-#define _ch0_tx_8b10b "ENABLED"
-#define _ch0_rx_sb "DISABLED"
-#define _ch0_ird "DISABLED"
-#define _ch0_rx_8b10b "ENABLED"
-#define _ch0_rxwa "ENABLED"
-#define _ch0_ilsm "ENABLED"
-#define _ch0_scomma "K28P157"
-#define _ch0_comma_a "1100000101"
-#define _ch0_comma_b "0011111010"
-#define _ch0_comma_m "1111111100"
-#define _ch0_ctc "DISABLED"
-#define _ch0_cc_match_mode "1"
-#define _ch0_byten "0000000000"
-#define _ch0_byten1 "0000000000"
-#define _ch0_byten2 "0100011100"
-#define _ch0_byten3 "0100011100"
-#define _ch0_cc_min_ipg "3"
-#define _ch0_lbtype "DISABLED"
-#define _ch0_teidle "DISABLED"
-#define _ch0_rx_lol_port "INTERNAL"
-
-#define _ch1_pll_rxsrc "REFCLK_EXT"
-#define _ch1_mode "DISABLED"
-#define _ch1_protocol "G8B10B"
-#define _ch1_ldr "DISABLED"
-#define _ch1_tx_data_rate "FULL"
-#define _ch1_tx_data_width "8"
-#define _ch1_tx_fifo "ENABLED"
-#define _ch1_tx_ficlk_rate 125.0
-#define _ch1_rx_datarange "MEDHIGH"
-#define _ch1_rx_data_rate "FULL"
-#define _ch1_rxrefclk_rate "250.0"
-#define _ch1_rx_data_width "8"
-#define _ch1_rx_fifo "ENABLED"
-#define _ch1_rx_ficlk_rate 250.0
-#define _ch1_tdrv "0"
-#define _ch1_tx_pre "DISABLED"
-#define _ch1_rterm_tx "50"
-#define _ch1_rx_eq "DISABLED"
-#define _ch1_rterm_rx "50"
-#define _ch1_rx_dcc "AC"
-#define _los_threshold_lo1 "2"
-#define _ch1_tx_sb "DISABLED"
-#define _ch1_tx_8b10b "ENABLED"
-#define _ch1_rx_sb "DISABLED"
-#define _ch1_ird "DISABLED"
-#define _ch1_rx_8b10b "ENABLED"
-#define _ch1_rxwa "ENABLED"
-#define _ch1_ilsm "ENABLED"
-#define _ch1_scomma "K28P157"
-#define _ch1_comma_a "1100000101"
-#define _ch1_comma_b "0011111010"
-#define _ch1_comma_m "1111111100"
-#define _ch1_ctc "DISABLED"
-#define _ch1_cc_match_mode "1"
-#define _ch1_byten "0000000000"
-#define _ch1_byten1 "0000000000"
-#define _ch1_byten2 "0100011100"
-#define _ch1_byten3 "0100011100"
-#define _ch1_cc_min_ipg "3"
-#define _ch1_lbtype "DISABLED"
-#define _ch1_teidle "DISABLED"
-#define _ch1_rx_lol_port "INTERNAL"
-
-#define _ch2_pll_rxsrc "REFCLK_EXT"
-#define _ch2_mode "DISABLED"
-#define _ch2_protocol "G8B10B"
-#define _ch2_ldr "DISABLED"
-#define _ch2_tx_data_rate "FULL"
-#define _ch2_tx_data_width "8"
-#define _ch2_tx_fifo "ENABLED"
-#define _ch2_tx_ficlk_rate 125.0
-#define _ch2_rx_datarange "MEDHIGH"
-#define _ch2_rx_data_rate "FULL"
-#define _ch2_rxrefclk_rate "250.0"
-#define _ch2_rx_data_width "8"
-#define _ch2_rx_fifo "ENABLED"
-#define _ch2_rx_ficlk_rate 250.0
-#define _ch2_tdrv "0"
-#define _ch2_tx_pre "DISABLED"
-#define _ch2_rterm_tx "50"
-#define _ch2_rx_eq "DISABLED"
-#define _ch2_rterm_rx "50"
-#define _ch2_rx_dcc "AC"
-#define _los_threshold_lo2 "2"
-#define _ch2_tx_sb "DISABLED"
-#define _ch2_tx_8b10b "ENABLED"
-#define _ch2_rx_sb "DISABLED"
-#define _ch2_ird "DISABLED"
-#define _ch2_rx_8b10b "ENABLED"
-#define _ch2_rxwa "ENABLED"
-#define _ch2_ilsm "ENABLED"
-#define _ch2_scomma "K28P157"
-#define _ch2_comma_a "1100000101"
-#define _ch2_comma_b "0011111010"
-#define _ch2_comma_m "1111111100"
-#define _ch2_ctc "DISABLED"
-#define _ch2_cc_match_mode "1"
-#define _ch2_byten "0000000000"
-#define _ch2_byten1 "0000000000"
-#define _ch2_byten2 "0100011100"
-#define _ch2_byten3 "0100011100"
-#define _ch2_cc_min_ipg "3"
-#define _ch2_lbtype "DISABLED"
-#define _ch2_teidle "DISABLED"
-#define _ch2_rx_lol_port "INTERNAL"
-
-#define _ch3_pll_rxsrc "REFCLK_CORE"
-#define _ch3_mode "RXTX"
-#define _ch3_protocol "GIGE"
-#define _ch3_ldr "DISABLED"
-#define _ch3_tx_data_rate "FULL"
-#define _ch3_tx_data_width "8"
-#define _ch3_tx_fifo "ENABLED"
-#define _ch3_tx_ficlk_rate 125.0
-#define _ch3_rx_datarange "MED"
-#define _ch3_rx_data_rate "FULL"
-#define _ch3_rxrefclk_rate "125.0"
-#define _ch3_rx_data_width "8"
-#define _ch3_rx_fifo "ENABLED"
-#define _ch3_rx_ficlk_rate 125.0
-#define _ch3_tdrv "0"
-#define _ch3_tx_pre "DISABLED"
-#define _ch3_rterm_tx "50"
-#define _ch3_rx_eq "DISABLED"
-#define _ch3_rterm_rx "50"
-#define _ch3_rx_dcc "AC"
-#define _los_threshold_lo3 "2"
-#define _ch3_tx_sb "DISABLED"
-#define _ch3_tx_8b10b "ENABLED"
-#define _ch3_rx_sb "DISABLED"
-#define _ch3_ird "DISABLED"
-#define _ch3_rx_8b10b "ENABLED"
-#define _ch3_rxwa "ENABLED"
-#define _ch3_ilsm "ENABLED"
-#define _ch3_scomma "K28P5"
-#define _ch3_comma_a "1100000101"
-#define _ch3_comma_b "0011111010"
-#define _ch3_comma_m "1111111111"
-#define _ch3_ctc "DISABLED"
-#define _ch3_cc_match_mode "2"
-#define _ch3_byten "0110111100"
-#define _ch3_byten1 "0001010000"
-#define _ch3_byten2 "0110111100"
-#define _ch3_byten3 "0001010000"
-#define _ch3_cc_min_ipg "3"
-#define _ch3_lbtype "DISABLED"
-#define _ch3_teidle "DISABLED"
-#define _ch3_rx_lol_port "INTERNAL"
-
-#define _datarange "MED"
-#define _pll_txsrc "REFCLK_CORE"
-#define _refclk_mult "10X"
-#define _refclk_rate 125.0
-#define _pll_term "50"
-#define _pll_dcc "AC"
-#define _pll_lol_set "0"
-#define _cchmark "9"
-#define _cclmark "7"
-#define _rst_gen "DISABLED"
-#define _sci_ports "DISABLED"
-#define _sci_int_port "DISABLED"
-#define _refck2core "DISABLED"
-#define _circuit_name serdes_ch4
-#define _lang vhdl
-
-#include <pcs/PCSD.vhd>
-#include <pcs/pcsd_cfg.txt>
+++ /dev/null
-
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: Lattice Semiconductor Corporation
- MODULE: serdes_ch4
- DESIGN: serdes_ch4
- FILENAME: serdes_ch4.readme
- PROJECT: Unknown
- VERSION: 2.0
- This file is auto generated by the ispLEVER
-
-
-NOTE: This readme file has been provided to instantiate the interface
-netlist. Since this template contains synthesis attributes for precision that
-are crucial to the design flow, we recommend that you use this
-template in your FPGA design.
-entity chip is
-port (
-
--- Add your FPGA design top level I/Os here
-
-
--- ASIC side pins for PCSD. These pins must exist for the
--- PCS core.
- refclkp : in std_logic;
- refclkn : in std_logic;
- hdinp_ch0 : in std_logic;
- hdinn_ch0 : in std_logic;
- hdinp_ch1 : in std_logic;
- hdinn_ch1 : in std_logic;
- hdinp_ch2 : in std_logic;
- hdinn_ch2 : in std_logic;
- hdinp_ch3 : in std_logic;
- hdinn_ch3 : in std_logic;
-
- hdoutp_ch0 : out std_logic;
- hdoutn_ch0 : out std_logic;
- hdoutp_ch1 : out std_logic;
- hdoutn_ch1 : out std_logic;
- hdoutp_ch2 : out std_logic;
- hdoutn_ch2 : out std_logic;
- hdoutp_ch3 : out std_logic;
- hdoutn_ch3 : out std_logic;
-
-
-);
-end chip;
-
-architecture chip_arch of chip is
-
--- This defines all the high-speed ports. You may have to remove
--- some of them depending on your design.
-attribute nopad : string;
-attribute nopad of
- refclkp, refclkn,
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
-
- COMPONENT serdes_ch4
- PORT(
- hdinp_ch3 : IN std_logic;
- hdinn_ch3 : IN std_logic;
- rxiclk_ch3 : IN std_logic;
- txiclk_ch3 : IN std_logic;
- fpga_rxrefclk_ch3 : IN std_logic;
- txdata_ch3 : IN std_logic_vector(7 downto 0);
- tx_k_ch3 : IN std_logic;
- xmit_ch3 : IN std_logic;
- tx_disp_correct_ch3 : IN std_logic;
- rx_serdes_rst_ch3_c : IN std_logic;
- sb_felb_ch3_c : IN std_logic;
- sb_felb_rst_ch3_c : IN std_logic;
- tx_pcs_rst_ch3_c : IN std_logic;
- tx_pwrup_ch3_c : IN std_logic;
- rx_pcs_rst_ch3_c : IN std_logic;
- rx_pwrup_ch3_c : IN std_logic;
- fpga_txrefclk : IN std_logic;
- tx_serdes_rst_c : IN std_logic;
- rst_qd_c : IN std_logic;
- serdes_rst_qd_c : IN std_logic;
- hdoutp_ch3 : OUT std_logic;
- hdoutn_ch3 : OUT std_logic;
- rx_full_clk_ch3 : OUT std_logic;
- rx_half_clk_ch3 : OUT std_logic;
- tx_full_clk_ch3 : OUT std_logic;
- tx_half_clk_ch3 : OUT std_logic;
- rxdata_ch3 : OUT std_logic_vector(7 downto 0);
- rx_k_ch3 : OUT std_logic;
- rx_disp_err_ch3 : OUT std_logic;
- rx_cv_err_ch3 : OUT std_logic;
- rx_los_low_ch3_s : OUT std_logic;
- lsm_status_ch3_s : OUT std_logic;
- rx_cdr_lol_ch3_s : OUT std_logic;
- tx_pll_lol_qd_s : OUT std_logic
- );
- END COMPONENT;
-
-
-
- uut: serdes_ch4 PORT MAP(
- hdinp_ch3 => hdinp_ch3,
- hdinn_ch3 => hdinn_ch3,
- hdoutp_ch3 => hdoutp_ch3,
- hdoutn_ch3 => hdoutn_ch3,
- rxiclk_ch3 => rxiclk_ch3,
- txiclk_ch3 => txiclk_ch3,
- rx_full_clk_ch3 => rx_full_clk_ch3,
- rx_half_clk_ch3 => rx_half_clk_ch3,
- tx_full_clk_ch3 => tx_full_clk_ch3,
- tx_half_clk_ch3 => tx_half_clk_ch3,
- fpga_rxrefclk_ch3 => fpga_rxrefclk_ch3,
- txdata_ch3 => txdata_ch3,
- tx_k_ch3 => tx_k_ch3,
- xmit_ch3 => xmit_ch3,
- tx_disp_correct_ch3 => tx_disp_correct_ch3,
- rxdata_ch3 => rxdata_ch3,
- rx_k_ch3 => rx_k_ch3,
- rx_disp_err_ch3 => rx_disp_err_ch3,
- rx_cv_err_ch3 => rx_cv_err_ch3,
- rx_serdes_rst_ch3_c => rx_serdes_rst_ch3_c,
- sb_felb_ch3_c => sb_felb_ch3_c,
- sb_felb_rst_ch3_c => sb_felb_rst_ch3_c,
- tx_pcs_rst_ch3_c => tx_pcs_rst_ch3_c,
- tx_pwrup_ch3_c => tx_pwrup_ch3_c,
- rx_pcs_rst_ch3_c => rx_pcs_rst_ch3_c,
- rx_pwrup_ch3_c => rx_pwrup_ch3_c,
- rx_los_low_ch3_s => rx_los_low_ch3_s,
- lsm_status_ch3_s => lsm_status_ch3_s,
- rx_cdr_lol_ch3_s => rx_cdr_lol_ch3_s,
- fpga_txrefclk => fpga_txrefclk,
- tx_serdes_rst_c => tx_serdes_rst_c,
- tx_pll_lol_qd_s => tx_pll_lol_qd_s,
- rst_qd_c => rst_qd_c,
- serdes_rst_qd_c => serdes_rst_qd_c
- );
-
-
-
-
+++ /dev/null
-serdes_ch4.vhd
+++ /dev/null
-@set suppresnewline=on@
-
-@comment --------------------------------------------------------------------- @
-@comment Template-drive TFI generator @
-@comment Template for TFI generation. @
-@comment --------------------------------------------------------------------- @
-
-@set suppresnewline=off@
- TOOL: orcapp
- DATE: 19-MAR-2008 13:11:52
- TITLE: %title%
- MODULE: %module%
- DESIGN: %module%
- FILENAME: %filename%
- PROJECT: %project%
- VERSION: %ver%
- This file is auto generated by the ispLEVER
-@set suppresnewline=on@
-
-@cr@
-@cr@
-
-@set sigdelim=@
-
-NOTE: This readme file has been provided to instantiate the interface@cr@
-netlist. Since this template contains synthesis attributes for precision that@cr@
-are crucial to the design flow, we recommend that you use this@cr@
-template in your FPGA design.@cr@
-entity chip is@cr@
-port (@cr@
-@cr@
--- Add your FPGA design top level I/Os here@cr@
-@cr@
-@cr@
--- ASIC side pins for PCSD. These pins must exist for the@cr@
--- PCS core.@cr@
- refclkp : in std_logic;@cr@
- refclkn : in std_logic;@cr@
- hdinp_ch0 : in std_logic;@cr@
- hdinn_ch0 : in std_logic;@cr@
- hdinp_ch1 : in std_logic;@cr@
- hdinn_ch1 : in std_logic;@cr@
- hdinp_ch2 : in std_logic;@cr@
- hdinn_ch2 : in std_logic;@cr@
- hdinp_ch3 : in std_logic;@cr@
- hdinn_ch3 : in std_logic;@cr@
-@cr@
- hdoutp_ch0 : out std_logic;@cr@
- hdoutn_ch0 : out std_logic;@cr@
- hdoutp_ch1 : out std_logic;@cr@
- hdoutn_ch1 : out std_logic;@cr@
- hdoutp_ch2 : out std_logic;@cr@
- hdoutn_ch2 : out std_logic;@cr@
- hdoutp_ch3 : out std_logic;@cr@
- hdoutn_ch3 : out std_logic;@cr@
-@cr@
-@cr@
-);@cr@
-end chip;@cr@
-@cr@
-architecture chip_arch of chip is@cr@
-@cr@
--- This defines all the high-speed ports. You may have to remove@cr@
--- some of them depending on your design.@cr@
-attribute nopad : string;@cr@
-attribute nopad of@cr@
- refclkp, refclkn,@cr@
- hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
- hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
- hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
- hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
-
-@cr@
-@tab@COMPONENT %module%
-@set sigdelim=@
-@cr@@tab@PORT(
-@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
-@ifhas oport=*@ @comment if the design has any output ports... @
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
- @set sigdelim=;@
- @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
-@endif@
-@ifnhas oport=*@ @comment we need an "else in this language! @
- @set sigdelim=;@
- @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
-@endif@
-@cr@@tab@@tab@);@cr@
-@tab@END COMPONENT;@cr@@cr@
-@comment Now do a signal declaration for each port @
-
-@cr@@cr@
-@comment do the component instantiation @
-@set sigdelim=,@
-@tab@uut: %module% PORT MAP(
-@iterate@%port%
-@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
-@cr@@tab@);@cr@@cr@
-@set suppresnewline=off@
-
-
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH3_PROTOCOL "GIGE"
-CH0_MODE "DISABLED"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "RXTX"
-CH3_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MED"
-CH3_RX_DATARATE_RANGE "MED"
-REFCK_MULT "10X"
-#REFCLK_RATE 125.0
-CH3_RX_DATA_RATE "FULL"
-CH3_TX_DATA_RATE "FULL"
-CH3_TX_DATA_WIDTH "8"
-CH3_RX_DATA_WIDTH "8"
-CH3_TX_FIFO "ENABLED"
-CH3_RX_FIFO "ENABLED"
-CH3_TDRV "0"
-#CH3_TX_FICLK_RATE 125.0
-#CH3_RXREFCLK_RATE "125.0"
-#CH3_RX_FICLK_RATE 125.0
-CH3_TX_PRE "DISABLED"
-CH3_RTERM_TX "50"
-CH3_RX_EQ "DISABLED"
-CH3_RTERM_RX "50"
-CH3_RX_DCC "AC"
-CH3_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH3_TX_SB "DISABLED"
-CH3_RX_SB "DISABLED"
-CH3_TX_8B10B "ENABLED"
-CH3_RX_8B10B "ENABLED"
-CH3_COMMA_A "1100000101"
-CH3_COMMA_B "0011111010"
-CH3_COMMA_M "1111111111"
-CH3_RXWA "ENABLED"
-CH3_ILSM "ENABLED"
-CH3_CTC "DISABLED"
-CH3_CC_MATCH3 "0110111100"
-CH3_CC_MATCH4 "0001010000"
-CH3_CC_MATCH_MODE "2"
-CH3_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH3_SSLB "DISABLED"
-CH3_SPLBPORTS "DISABLED"
-CH3_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "DISABLED"
-
-
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "serdes_ch4.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_EXT";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_CORE";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_ch4 is
- GENERIC (USER_CONFIG_FILE : String := "serdes_ch4.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
--- CH2 --
--- CH3 --
- hdinp_ch3, hdinn_ch3 : in std_logic;
- hdoutp_ch3, hdoutn_ch3 : out std_logic;
- rxiclk_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- txdata_ch3 : in std_logic_vector (7 downto 0);
- tx_k_ch3 : in std_logic;
- xmit_ch3 : in std_logic;
- tx_disp_correct_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- rx_serdes_rst_ch3_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
- tx_pcs_rst_ch3_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pcs_rst_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
----- Miscillaneous ports
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- rst_qd_c : in std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end serdes_ch4;
-
-
-architecture serdes_ch4_arch of serdes_ch4 is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH3_CDR_SRC: string;
- attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch3_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- rx_los_low_ch3_s <= rx_los_low_ch3_sig;
- rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH3_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => open,
- HDOUTN0 => open,
- HDINP0 => fpsc_vlo,
- HDINN0 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => fpsc_vlo,
- FF_TXI_CLK_0 => fpsc_vlo,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => open,
- FF_RX_H_CLK_0 => open,
- FF_TX_F_CLK_0 => open,
- FF_TX_H_CLK_0 => open,
- FFC_CK_CORE_RX_0 => fpsc_vlo,
- FF_TX_D_0_0 => fpsc_vlo,
- FF_TX_D_0_1 => fpsc_vlo,
- FF_TX_D_0_2 => fpsc_vlo,
- FF_TX_D_0_3 => fpsc_vlo,
- FF_TX_D_0_4 => fpsc_vlo,
- FF_TX_D_0_5 => fpsc_vlo,
- FF_TX_D_0_6 => fpsc_vlo,
- FF_TX_D_0_7 => fpsc_vlo,
- FF_TX_D_0_8 => fpsc_vlo,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => fpsc_vlo,
- FF_TX_D_0_11 => fpsc_vlo,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => open,
- FF_RX_D_0_1 => open,
- FF_RX_D_0_2 => open,
- FF_RX_D_0_3 => open,
- FF_RX_D_0_4 => open,
- FF_RX_D_0_5 => open,
- FF_RX_D_0_6 => open,
- FF_RX_D_0_7 => open,
- FF_RX_D_0_8 => open,
- FF_RX_D_0_9 => open,
- FF_RX_D_0_10 => open,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => fpsc_vlo,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => fpsc_vlo,
- FFC_TXPWDNB_0 => fpsc_vlo,
- FFC_LANE_RX_RST_0 => fpsc_vlo,
- FFC_RXPWDNB_0 => fpsc_vlo,
- FFS_RLOS_LO_0 => open,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => open,
- HDOUTN1 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_TX_F_CLK_1 => open,
- FF_TX_H_CLK_1 => open,
- FFC_CK_CORE_RX_1 => fpsc_vlo,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => fpsc_vlo,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => hdoutp_ch3,
- HDOUTN3 => hdoutn_ch3,
- HDINP3 => hdinp_ch3,
- HDINN3 => hdinn_ch3,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => rxiclk_ch3,
- FF_TXI_CLK_3 => txiclk_ch3,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => rx_full_clk_ch3,
- FF_RX_H_CLK_3 => rx_half_clk_ch3,
- FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
- FF_TX_H_CLK_3 => tx_half_clk_ch3,
- FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
- FF_TX_D_3_0 => txdata_ch3(0),
- FF_TX_D_3_1 => txdata_ch3(1),
- FF_TX_D_3_2 => txdata_ch3(2),
- FF_TX_D_3_3 => txdata_ch3(3),
- FF_TX_D_3_4 => txdata_ch3(4),
- FF_TX_D_3_5 => txdata_ch3(5),
- FF_TX_D_3_6 => txdata_ch3(6),
- FF_TX_D_3_7 => txdata_ch3(7),
- FF_TX_D_3_8 => tx_k_ch3,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => xmit_ch3,
- FF_TX_D_3_11 => tx_disp_correct_ch3,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => rxdata_ch3(0),
- FF_RX_D_3_1 => rxdata_ch3(1),
- FF_RX_D_3_2 => rxdata_ch3(2),
- FF_RX_D_3_3 => rxdata_ch3(3),
- FF_RX_D_3_4 => rxdata_ch3(4),
- FF_RX_D_3_5 => rxdata_ch3(5),
- FF_RX_D_3_6 => rxdata_ch3(6),
- FF_RX_D_3_7 => rxdata_ch3(7),
- FF_RX_D_3_8 => rx_k_ch3,
- FF_RX_D_3_9 => rx_disp_err_ch3,
- FF_RX_D_3_10 => rx_cv_err_ch3,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => rx_serdes_rst_ch3_c,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
- FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
- FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
- FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
- FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
- FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
- SCIWDATA7 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA0 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIRDATA7 => open,
- SCIRDATA6 => open,
- SCIRDATA5 => open,
- SCIRDATA4 => open,
- SCIRDATA3 => open,
- SCIRDATA2 => open,
- SCIRDATA1 => open,
- SCIRDATA0 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
-
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end serdes_ch4_arch ;
+++ /dev/null
-Starting process: Module
-
-Starting process:
-
- Module Name: serdes_ch4
- Core Name: PCS
- LPC file : serdes_ch4.lpc
- Parameter File : serdes_ch4.pp
- Command line: /opt/lattice/diamond/1.4/ispfpga/bin/lin/orcapp -Fmaco serdes_ch4.pp
- Return Value:
-
-
-
- Module PCS has been generated in /home/greg/projects/trb3/trb3_gbe/. successfully!
-
-/opt/lattice/diamond/1.4/bin/lin/hdl2jhd -tfi -mod serdes_ch4 -ext readme -out serdes_ch4 -tpl serdes_ch4.tft serdes_ch4.vhd
-
-Done successfully!
-File: serdes_ch4.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
-[Device]
-Family=latticeecp2m
-PartType=LFE2M100E
-PartName=LFE2M100E-6F900C
-SpeedGrade=-6
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=7.0
-ModuleName=serdes_gbe_0_intclock_8b
-SourceFormat=Schematic/VHDL
-ParameterFileVersion=1.0
-Date=04/28/2010
-Time=20:09:02
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-Protocol=Quad
-mode=Gigabit Ethernet
-Channel0=SINGLE
-Channel1=DISABLE
-Channel2=DISABLE
-Channel3=DISABLE
-Rate0=None
-Rate1=None
-Rate2=None
-Rate3=None
-TxRefClk=CORE_TXREFCLK
-RxRefClk=CORE_RXREFCLK
-ClkRate=1.25
-ClkMult=10X
-CalClkRate=125.0
-DataWidth=8
-FPGAClkRate=125.0
-TxRefClkCM=REFCLK
-RxRefClk0CM=REFCLK
-RxRefClk1CM=REFCLK
-RxRefClk2CM=REFCLK
-RxRefClk3CM=REFCLK
-ClkRateH=0.625
-ClkMultH=10XH
-CalClkRateH=125.0
-DataWidthH=8
-FPGAClkRateH=62.5
-VCh0=0
-VCh1=0
-VCh2=0
-VCh3=0
-PreCh0=DISABLE
-PreCh1=DISABLE
-PreCh2=DISABLE
-PreCh3=DISABLE
-TxCh0=50
-TxCh1=50
-TxCh2=50
-TxCh3=50
-EqCh0=DISABLE
-EqCh1=DISABLE
-EqCh2=DISABLE
-EqCh3=DISABLE
-RxTermCh0=50
-RxTermCh1=50
-RxTermCh2=50
-RxTermCh3=50
-RxCoupCh0=AC
-RxCoupCh1=AC
-RxCoupCh2=AC
-RxCoupCh3=AC
-Loss=0
-CDRLoss=0
-TxTerm=50
-TxCoup=AC
-TxPllLoss=0
-TxInvCh0=NORMAL
-TxInvCh1=NORMAL
-TxInvCh2=NORMAL
-TxInvCh3=NORMAL
-RxInvCh0=NORMAL
-RxInvCh1=NORMAL
-RxInvCh2=NORMAL
-RxInvCh3=NORMAL
-RxModeCh0=NORMAL
-RxModeCh1=NORMAL
-RxModeCh2=NORMAL
-RxModeCh3=NORMAL
-Plus=1100000101
-Minus=0011111010
-Mask=1111111111
-Align=AUTO
-CTCCh0=NORMAL
-CTCCh1=NORMAL
-CTCCh2=NORMAL
-CTCCh3=NORMAL
-CC_MATCH1=0000000000
-CC_MATCH2=0000000000
-CC_MATCH3=0110111100
-CC_MATCH4=0001010000
-MinIPG=3
-High=9
-Low=7
-CC_MATCH_MODE=MATCH_3_4
-RxDataCh0=FALSE
-RxDataCh1=FALSE
-RxDataCh2=FALSE
-RxDataCh3=FALSE
-AlignerCh0=FALSE
-AlignerCh1=FALSE
-AlignerCh2=FALSE
-AlignerCh3=FALSE
-DetectCh0=FALSE
-DetectCh1=FALSE
-DetectCh2=FALSE
-DetectCh3=FALSE
-ELSMCh0=FALSE
-ELSMCh1=FALSE
-ELSMCh2=FALSE
-ELSMCh3=FALSE
-_teidleCh0=FALSE
-_teidleCh1=FALSE
-_teidleCh2=FALSE
-_teidleCh3=FALSE
-Ports0=FALSE
-rdoPorts0=Serial Loopback
-Ports1=FALSE
-Ports2=TRUE
-Ports3=FALSE
-Ports3_1=FALSE
-Ports4=FALSE
+++ /dev/null
-
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSC quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSC quad to the final design requirements.
-
-DEVICE_NAME "LFE2M100E"
-PROTOCOL "GIGE"
-CH0_MODE "SINGLE"
-CH1_MODE "DISABLE"
-CH2_MODE "DISABLE"
-CH3_MODE "DISABLE"
-PLL_SRC "CORE_TXREFCLK"
-DATARANGE "MED"
-CH0_CDR_SRC "CORE_RXREFCLK"
-CH0_DATA_WIDTH "8"
-CH0_REFCK_MULT "10X"
-#REFCLK_RATE 125.0
-#FPGAINTCLK_RATE 125.0
-CH0_TDRV_AMP "0"
-CH0_TX_PRE "DISABLE"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLE"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "AC"
-LOS_THRESHOLD "0"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "NORMAL"
-CH0_RX_SB "NORMAL"
-CH0_8B10B "NORMAL"
-COMMA_A "1100000101"
-COMMA_B "0011111010"
-COMMA_M "1111111111"
-CH0_COMMA_ALIGN "AUTO"
-CH0_CTC_BYP "BYPASS"
-CC_MATCH1 "0000000000"
-CC_MATCH2 "0000000000"
-CC_MATCH3 "0110111100"
-CC_MATCH4 "0001010000"
-CC_MATCH_MODE "MATCH_3_4"
-CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-OS_REFCK2CORE "1"
-OS_PLLQCLKPORTS "0"
-OS_INT_ALL "0"
-
+++ /dev/null
-
-
---synopsys translate_off
-
-library pcsc_work;
-use pcsc_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSC is
-GENERIC(
- CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-
-end PCSC;
-
-architecture PCSC_arch of PCSC is
-
-component PCSC_sim
-GENERIC(
- CONFIG_FILE : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-end component;
-
-begin
-
-PCSC_sim_inst : PCSC_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE)
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
-
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX => FFC_CK_CORE_RX,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,
- FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,
- FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,
- FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,
- FF_TX_F_CLK => FF_TX_F_CLK,
- FF_TX_H_CLK => FF_TX_H_CLK,
- FF_TX_Q_CLK => FF_TX_Q_CLK,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- OOB_OUT_0 => OOB_OUT_0,
- OOB_OUT_1 => OOB_OUT_1,
- OOB_OUT_2 => OOB_OUT_2,
- OOB_OUT_3 => OOB_OUT_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7
- );
-
-end PCSC_arch;
-
---synopsys translate_on
-
---synopsys translate_off
-library ECP2;
-use ECP2.components.all;
---synopsys translate_on
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_gbe_0_intclock_8b is
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt");
- port (
- core_txrefclk : in std_logic;
- core_rxrefclk : in std_logic;
- hdinp0, hdinn0 : in std_logic;
- hdoutp0, hdoutn0 : out std_logic;
- ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;
- ff_txdata_ch0 : in std_logic_vector (7 downto 0);
- ff_rxdata_ch0 : out std_logic_vector (7 downto 0);
- ff_tx_k_cntrl_ch0 : in std_logic;
- ff_rx_k_cntrl_ch0 : out std_logic;
- ff_rxfullclk_ch0 : out std_logic;
- ff_xmit_ch0 : in std_logic;
- ff_correct_disp_ch0 : in std_logic;
- ff_disp_err_ch0, ff_cv_ch0 : out std_logic;
- ff_rx_even_ch0 : out std_logic;
- ffc_rrst_ch0 : in std_logic;
- ffc_lane_tx_rst_ch0 : in std_logic;
- ffc_lane_rx_rst_ch0 : in std_logic;
- ffc_txpwdnb_ch0 : in std_logic;
- ffc_rxpwdnb_ch0 : in std_logic;
- ffs_rlos_lo_ch0 : out std_logic;
- ffs_ls_sync_status_ch0 : out std_logic;
- ffs_rlol_ch0 : out std_logic;
- oob_out_ch0 : out std_logic;
- ffc_macro_rst : in std_logic;
- ffc_quad_rst : in std_logic;
- ffc_trst : in std_logic;
- ff_txfullclk : out std_logic;
- ff_txhalfclk : out std_logic;
- refck2core : out std_logic;
- ffs_plol : out std_logic);
-
-end serdes_gbe_0_intclock_8b;
-
-architecture serdes_gbe_0_intclock_8b_arch of serdes_gbe_0_intclock_8b is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-component PCSC
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-end component;
- attribute IS_ASB: string;
- attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal fpsc_vlo : std_logic := '0';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-
--- pcs_quad instance
-PCSC_INST : PCSC
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE)
---synopsys translate_on
-port map (
- FFC_CK_CORE_TX => core_txrefclk,
- FFC_CK_CORE_RX => core_rxrefclk,
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
- HDINP0 => hdinp0,
- HDINN0 => hdinn0,
- HDOUTP0 => hdoutp0,
- HDOUTN0 => hdoutn0,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => ff_rxiclk_ch0,
- FF_TXI_CLK_0 => ff_txiclk_ch0,
- FF_EBRD_CLK_0 => ff_ebrd_clk_0,
- FF_RX_F_CLK_0 => ff_rxfullclk_ch0,
- FF_RX_H_CLK_0 => open,
- FF_RX_Q_CLK_0 => open,
- FF_TX_D_0_0 => ff_txdata_ch0(0),
- FF_TX_D_0_1 => ff_txdata_ch0(1),
- FF_TX_D_0_2 => ff_txdata_ch0(2),
- FF_TX_D_0_3 => ff_txdata_ch0(3),
- FF_TX_D_0_4 => ff_txdata_ch0(4),
- FF_TX_D_0_5 => ff_txdata_ch0(5),
- FF_TX_D_0_6 => ff_txdata_ch0(6),
- FF_TX_D_0_7 => ff_txdata_ch0(7),
- FF_TX_D_0_8 => ff_tx_k_cntrl_ch0,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => ff_xmit_ch0,
- FF_TX_D_0_11 => ff_correct_disp_ch0,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => ff_rxdata_ch0(0),
- FF_RX_D_0_1 => ff_rxdata_ch0(1),
- FF_RX_D_0_2 => ff_rxdata_ch0(2),
- FF_RX_D_0_3 => ff_rxdata_ch0(3),
- FF_RX_D_0_4 => ff_rxdata_ch0(4),
- FF_RX_D_0_5 => ff_rxdata_ch0(5),
- FF_RX_D_0_6 => ff_rxdata_ch0(6),
- FF_RX_D_0_7 => ff_rxdata_ch0(7),
- FF_RX_D_0_8 => ff_rx_k_cntrl_ch0,
- FF_RX_D_0_9 => ff_disp_err_ch0,
- FF_RX_D_0_10 => ff_cv_ch0,
- FF_RX_D_0_11 => ff_rx_even_ch0,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
- FFC_RRST_0 => ffc_rrst_ch0,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFS_PCIE_DONE_0 => open,
- FFS_PCIE_CON_0 => open,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0,
- FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0,
- FFC_TXPWDNB_0 => ffc_txpwdnb_ch0,
- FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0,
- FFS_RLOS_LO_0 => ffs_rlos_lo_ch0,
- FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0,
- FFS_CC_UNDERRUN_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- FFS_RLOL_0 => ffs_rlol_ch0,
- OOB_OUT_0 => oob_out_ch0,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- HDOUTP1 => open,
- HDOUTN1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_RX_Q_CLK_1 => open,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- OOB_OUT_1 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- HDOUTP2 => open,
- HDOUTN2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_RX_Q_CLK_2 => open,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- OOB_OUT_2 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- HDOUTP3 => open,
- HDOUTN3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_RX_Q_CLK_3 => open,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- OOB_OUT_3 => open,
- SCIWDATA0 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA7 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIRDATA0 => open,
- SCIRDATA1 => open,
- SCIRDATA2 => open,
- SCIRDATA3 => open,
- SCIRDATA4 => open,
- SCIRDATA5 => open,
- SCIRDATA6 => open,
- SCIRDATA7 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_MACRO_RST => ffc_macro_rst,
- FFC_QUAD_RST => ffc_quad_rst,
- FFC_TRST => ffc_trst,
- FF_TX_F_CLK => ff_txfullclk,
- FF_TX_H_CLK => ff_txhalfclk,
- FF_TX_Q_CLK => open,
- REFCK2CORE => refck2core,
- CIN0 => cin(0),
- CIN1 => cin(1),
- CIN2 => cin(2),
- CIN3 => cin(3),
- CIN4 => cin(4),
- CIN5 => cin(5),
- CIN6 => cin(6),
- CIN7 => cin(7),
- CIN8 => cin(8),
- CIN9 => cin(9),
- CIN10 => cin(10),
- CIN11 => cin(11),
- COUT0 => cout(0),
- COUT1 => cout(1),
- COUT2 => cout(2),
- COUT3 => cout(3),
- COUT4 => cout(4),
- COUT5 => cout(5),
- COUT6 => cout(6),
- COUT7 => cout(7),
- COUT8 => cout(8),
- COUT9 => cout(9),
- COUT10 => cout(10),
- COUT11 => cout(11),
- COUT12 => cout(12),
- COUT13 => cout(13),
- COUT14 => cout(14),
- COUT15 => cout(15),
- COUT16 => cout(16),
- COUT17 => cout(17),
- COUT18 => cout(18),
- COUT19 => cout(19),
- FFS_PLOL => ffs_plol);
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-
-end serdes_gbe_0_intclock_8b_arch ;
+++ /dev/null
-[Device]
-Family=latticeecp2m
-PartType=LFE2M50E
-PartName=LFE2M50E-5F900C
-SpeedGrade=-5
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_gbe_0_intclock_8b
-SourceFormat=Schematic/VHDL
-ParameterFileVersion=1.0
-Date=07/31/2010
-Time=18:08:44
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-Protocol=Quad
-mode=Gigabit Ethernet
-Channel0=SINGLE
-Channel1=DISABLE
-Channel2=DISABLE
-Channel3=DISABLE
-Rate0=None
-Rate1=None
-Rate2=None
-Rate3=None
-TxRefClk=CORE_TXREFCLK
-RxRefClk=CORE_RXREFCLK
-ClkRate=1.25
-ClkMult=10X
-CalClkRate=125.0
-DataWidth=8
-FPGAClkRate=125.0
-TxRefClkCM=REFCLK
-RxRefClk0CM=REFCLK
-RxRefClk1CM=REFCLK
-RxRefClk2CM=REFCLK
-RxRefClk3CM=REFCLK
-ClkRateH=0.625
-ClkMultH=10XH
-CalClkRateH=125.0
-DataWidthH=8
-FPGAClkRateH=62.5
-VCh0=0
-VCh1=0
-VCh2=0
-VCh3=0
-PreCh0=DISABLE
-PreCh1=DISABLE
-PreCh2=DISABLE
-PreCh3=DISABLE
-TxCh0=50
-TxCh1=50
-TxCh2=50
-TxCh3=50
-EqCh0=DISABLE
-EqCh1=DISABLE
-EqCh2=DISABLE
-EqCh3=DISABLE
-RxTermCh0=50
-RxTermCh1=50
-RxTermCh2=50
-RxTermCh3=50
-RxCoupCh0=AC
-RxCoupCh1=AC
-RxCoupCh2=AC
-RxCoupCh3=AC
-Loss=0
-CDRLoss=0
-TxTerm=50
-TxCoup=AC
-TxPllLoss=0
-TxInvCh0=NORMAL
-TxInvCh1=NORMAL
-TxInvCh2=NORMAL
-TxInvCh3=NORMAL
-RxInvCh0=NORMAL
-RxInvCh1=NORMAL
-RxInvCh2=NORMAL
-RxInvCh3=NORMAL
-RxModeCh0=NORMAL
-RxModeCh1=NORMAL
-RxModeCh2=NORMAL
-RxModeCh3=NORMAL
-Plus=1100000101
-Minus=0011111010
-Mask=1111111111
-Align=AUTO
-CTCCh0=NORMAL
-CTCCh1=NORMAL
-CTCCh2=NORMAL
-CTCCh3=NORMAL
-CC_MATCH1=0000000000
-CC_MATCH2=0000000000
-CC_MATCH3=0110111100
-CC_MATCH4=0001010000
-MinIPG=3
-High=9
-Low=7
-CC_MATCH_MODE=MATCH_3_4
-RxDataCh0=FALSE
-RxDataCh1=FALSE
-RxDataCh2=FALSE
-RxDataCh3=FALSE
-AlignerCh0=FALSE
-AlignerCh1=FALSE
-AlignerCh2=FALSE
-AlignerCh3=FALSE
-DetectCh0=FALSE
-DetectCh1=FALSE
-DetectCh2=FALSE
-DetectCh3=FALSE
-ELSMCh0=FALSE
-ELSMCh1=FALSE
-ELSMCh2=FALSE
-ELSMCh3=FALSE
-_teidleCh0=FALSE
-_teidleCh1=FALSE
-_teidleCh2=FALSE
-_teidleCh3=FALSE
-Ports0=FALSE
-rdoPorts0=Serial Loopback
-Ports1=FALSE
-Ports2=FALSE
-Ports3=FALSE
-Ports3_1=FALSE
-Ports4=FALSE
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
+++ /dev/null
-
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSC quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSC quad to the final design requirements.
-
-DEVICE_NAME "LFE2M50E"
-PROTOCOL "GIGE"
-CH0_MODE "SINGLE"
-CH1_MODE "DISABLE"
-CH2_MODE "DISABLE"
-CH3_MODE "DISABLE"
-PLL_SRC "CORE_TXREFCLK"
-DATARANGE "MED"
-CH0_CDR_SRC "CORE_RXREFCLK"
-CH0_DATA_WIDTH "8"
-CH0_REFCK_MULT "10X"
-#REFCLK_RATE 125.0
-#FPGAINTCLK_RATE 125.0
-CH0_TDRV_AMP "0"
-CH0_TX_PRE "DISABLE"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLE"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "AC"
-LOS_THRESHOLD "0"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "NORMAL"
-CH0_RX_SB "NORMAL"
-CH0_8B10B "NORMAL"
-COMMA_A "1100000101"
-COMMA_B "0011111010"
-COMMA_M "1111111111"
-CH0_COMMA_ALIGN "AUTO"
-CH0_CTC_BYP "BYPASS"
-CC_MATCH1 "0000000000"
-CC_MATCH2 "0000000000"
-CC_MATCH3 "0110111100"
-CC_MATCH4 "0001010000"
-CC_MATCH_MODE "MATCH_3_4"
-CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-OS_REFCK2CORE "0"
-OS_PLLQCLKPORTS "0"
-OS_INT_ALL "0"
-
+++ /dev/null
-
-
---synopsys translate_off
-
-library pcsc_work;
-use pcsc_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSC is
-GENERIC(
- CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-
-end PCSC;
-
-architecture PCSC_arch of PCSC is
-
-component PCSC_sim
-GENERIC(
- CONFIG_FILE : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-end component;
-
-begin
-
-PCSC_sim_inst : PCSC_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE)
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
-
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX => FFC_CK_CORE_RX,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,
- FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,
- FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,
- FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,
- FF_TX_F_CLK => FF_TX_F_CLK,
- FF_TX_H_CLK => FF_TX_H_CLK,
- FF_TX_Q_CLK => FF_TX_Q_CLK,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- OOB_OUT_0 => OOB_OUT_0,
- OOB_OUT_1 => OOB_OUT_1,
- OOB_OUT_2 => OOB_OUT_2,
- OOB_OUT_3 => OOB_OUT_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7
- );
-
-end PCSC_arch;
-
---synopsys translate_on
-
---synopsys translate_off
-library ECP2;
-use ECP2.components.all;
---synopsys translate_on
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_gbe_0_intclock_8b is
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt");
- port (
- core_txrefclk : in std_logic;
- core_rxrefclk : in std_logic;
- hdinp0, hdinn0 : in std_logic;
- hdoutp0, hdoutn0 : out std_logic;
- ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;
- ff_txdata_ch0 : in std_logic_vector (7 downto 0);
- ff_rxdata_ch0 : out std_logic_vector (7 downto 0);
- ff_tx_k_cntrl_ch0 : in std_logic;
- ff_rx_k_cntrl_ch0 : out std_logic;
- ff_rxfullclk_ch0 : out std_logic;
- ff_xmit_ch0 : in std_logic;
- ff_correct_disp_ch0 : in std_logic;
- ff_disp_err_ch0, ff_cv_ch0 : out std_logic;
- ff_rx_even_ch0 : out std_logic;
- ffc_rrst_ch0 : in std_logic;
- ffc_lane_tx_rst_ch0 : in std_logic;
- ffc_lane_rx_rst_ch0 : in std_logic;
- ffc_txpwdnb_ch0 : in std_logic;
- ffc_rxpwdnb_ch0 : in std_logic;
- ffs_rlos_lo_ch0 : out std_logic;
- ffs_ls_sync_status_ch0 : out std_logic;
- ffs_rlol_ch0 : out std_logic;
- oob_out_ch0 : out std_logic;
- ffc_macro_rst : in std_logic;
- ffc_quad_rst : in std_logic;
- ffc_trst : in std_logic;
- ff_txfullclk : out std_logic;
- ff_txhalfclk : out std_logic;
- ffs_plol : out std_logic);
-
-end serdes_gbe_0_intclock_8b;
-
-architecture serdes_gbe_0_intclock_8b_arch of serdes_gbe_0_intclock_8b is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-component PCSC
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-end component;
- attribute IS_ASB: string;
- attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSC_INST : label is "62.5";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSC_INST : label is "62.5";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSC_INST : label is "62.5";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSC_INST : label is "62.5";
- attribute FREQUENCY_PIN_FF_TX_F_CLK: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK of PCSC_INST : label is "125.0";
- attribute FREQUENCY_PIN_FF_TX_H_CLK: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK of PCSC_INST : label is "62.5";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal fpsc_vlo : std_logic := '0';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-
--- pcs_quad instance
-PCSC_INST : PCSC
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE)
---synopsys translate_on
-port map (
- FFC_CK_CORE_TX => core_txrefclk,
- FFC_CK_CORE_RX => core_rxrefclk,
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
- HDINP0 => hdinp0,
- HDINN0 => hdinn0,
- HDOUTP0 => hdoutp0,
- HDOUTN0 => hdoutn0,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => ff_rxiclk_ch0,
- FF_TXI_CLK_0 => ff_txiclk_ch0,
- FF_EBRD_CLK_0 => ff_ebrd_clk_0,
- FF_RX_F_CLK_0 => ff_rxfullclk_ch0,
- FF_RX_H_CLK_0 => open,
- FF_RX_Q_CLK_0 => open,
- FF_TX_D_0_0 => ff_txdata_ch0(0),
- FF_TX_D_0_1 => ff_txdata_ch0(1),
- FF_TX_D_0_2 => ff_txdata_ch0(2),
- FF_TX_D_0_3 => ff_txdata_ch0(3),
- FF_TX_D_0_4 => ff_txdata_ch0(4),
- FF_TX_D_0_5 => ff_txdata_ch0(5),
- FF_TX_D_0_6 => ff_txdata_ch0(6),
- FF_TX_D_0_7 => ff_txdata_ch0(7),
- FF_TX_D_0_8 => ff_tx_k_cntrl_ch0,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => ff_xmit_ch0,
- FF_TX_D_0_11 => ff_correct_disp_ch0,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => ff_rxdata_ch0(0),
- FF_RX_D_0_1 => ff_rxdata_ch0(1),
- FF_RX_D_0_2 => ff_rxdata_ch0(2),
- FF_RX_D_0_3 => ff_rxdata_ch0(3),
- FF_RX_D_0_4 => ff_rxdata_ch0(4),
- FF_RX_D_0_5 => ff_rxdata_ch0(5),
- FF_RX_D_0_6 => ff_rxdata_ch0(6),
- FF_RX_D_0_7 => ff_rxdata_ch0(7),
- FF_RX_D_0_8 => ff_rx_k_cntrl_ch0,
- FF_RX_D_0_9 => ff_disp_err_ch0,
- FF_RX_D_0_10 => ff_cv_ch0,
- FF_RX_D_0_11 => ff_rx_even_ch0,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
- FFC_RRST_0 => ffc_rrst_ch0,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFS_PCIE_DONE_0 => open,
- FFS_PCIE_CON_0 => open,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0,
- FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0,
- FFC_TXPWDNB_0 => ffc_txpwdnb_ch0,
- FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0,
- FFS_RLOS_LO_0 => ffs_rlos_lo_ch0,
- FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0,
- FFS_CC_UNDERRUN_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- FFS_RLOL_0 => ffs_rlol_ch0,
- OOB_OUT_0 => oob_out_ch0,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- HDOUTP1 => open,
- HDOUTN1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_RX_Q_CLK_1 => open,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- OOB_OUT_1 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- HDOUTP2 => open,
- HDOUTN2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_RX_Q_CLK_2 => open,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- OOB_OUT_2 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- HDOUTP3 => open,
- HDOUTN3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_RX_Q_CLK_3 => open,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- OOB_OUT_3 => open,
- SCIWDATA0 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA7 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIRDATA0 => open,
- SCIRDATA1 => open,
- SCIRDATA2 => open,
- SCIRDATA3 => open,
- SCIRDATA4 => open,
- SCIRDATA5 => open,
- SCIRDATA6 => open,
- SCIRDATA7 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_MACRO_RST => ffc_macro_rst,
- FFC_QUAD_RST => ffc_quad_rst,
- FFC_TRST => ffc_trst,
- FF_TX_F_CLK => ff_txfullclk,
- FF_TX_H_CLK => ff_txhalfclk,
- FF_TX_Q_CLK => open,
- REFCK2CORE => open,
- CIN0 => cin(0),
- CIN1 => cin(1),
- CIN2 => cin(2),
- CIN3 => cin(3),
- CIN4 => cin(4),
- CIN5 => cin(5),
- CIN6 => cin(6),
- CIN7 => cin(7),
- CIN8 => cin(8),
- CIN9 => cin(9),
- CIN10 => cin(10),
- CIN11 => cin(11),
- COUT0 => cout(0),
- COUT1 => cout(1),
- COUT2 => cout(2),
- COUT3 => cout(3),
- COUT4 => cout(4),
- COUT5 => cout(5),
- COUT6 => cout(6),
- COUT7 => cout(7),
- COUT8 => cout(8),
- COUT9 => cout(9),
- COUT10 => cout(10),
- COUT11 => cout(11),
- COUT12 => cout(12),
- COUT13 => cout(13),
- COUT14 => cout(14),
- COUT15 => cout(15),
- COUT16 => cout(16),
- COUT17 => cout(17),
- COUT18 => cout(18),
- COUT19 => cout(19),
- FFS_PLOL => ffs_plol);
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-
-end serdes_gbe_0_intclock_8b_arch ;
+++ /dev/null
-*.jhd
-*.naf
-*.srp
-*.sym
-*.log
-*.v
-*.htm
-*.tcl
-*tmpl.vhd
-sgmii_pcs_eval
-
+++ /dev/null
-[Device]
-Family=ep5m00
-PartType=LFE2M100E
-PartName=LFE2M100E-5F900C
-SpeedGrade=-5
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=IPCFG
-CoreStatus=Demo
-CoreName=SGMII/Gb Ethernet PCS
-CoreRevision=3.2
-ModuleName=sgmii_gbe_pcs32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=06/17/2011
-Time=11:34:20
-
-[Parameters]
-RX_CTC=2
-RX_CTC_LOW=16
-RX_CTC_HIGH=32
-EasyConnect=1
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
-SpeedGrade=8
-Package=FPBGA1156
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP
-CoreRevision=6.1
-ModuleName=statts_mem
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/05/2011
-Time=22:40:38
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-RAddress=1020
-RData=8
-WAddress=255
-WData=32
-enByte=0
-ByteSize=9
-adPipeline=0
-inPipeline=0
-outPipeline=0
-MOR=0
-InData=Registered
-AdControl=Registered
-MemFile=
-MemFormat=bin
-Reset=Sync
-GSR=Enabled
-Pad=0
-EnECC=0
-Optimization=Speed
-EnSleep=ENABLED
-Pipeline=0
-
-[FilesGenerated]
-=mem
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 6.1
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 8 -data_width 32 -num_rows 255 -cascade -1 -e
-
--- Mon Dec 5 22:40:38 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity statts_mem is
- port (
- WrAddress: in std_logic_vector(7 downto 0);
- RdAddress: in std_logic_vector(9 downto 0);
- Data: in std_logic_vector(31 downto 0);
- WE: in std_logic;
- RdClock: in std_logic;
- RdClockEn: in std_logic;
- Reset: in std_logic;
- WrClock: in std_logic;
- WrClockEn: in std_logic;
- Q: out std_logic_vector(7 downto 0));
-end statts_mem;
-
-architecture Structure of statts_mem is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of statts_mem_0_0_0 : label is "statts_mem.lpc";
- attribute MEM_INIT_FILE of statts_mem_0_0_0 : label is "";
- attribute RESETMODE of statts_mem_0_0_0 : label is "SYNC";
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- statts_mem_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>scuba_vlo, DI9=>Data(8), DI10=>Data(9), DI11=>Data(10),
- DI12=>Data(11), DI13=>Data(12), DI14=>Data(13),
- DI15=>Data(14), DI16=>Data(15), DI17=>scuba_vlo,
- DI18=>Data(16), DI19=>Data(17), DI20=>Data(18),
- DI21=>Data(19), DI22=>Data(20), DI23=>Data(21),
- DI24=>Data(22), DI25=>Data(23), DI26=>scuba_vlo,
- DI27=>Data(24), DI28=>Data(25), DI29=>Data(26),
- DI30=>Data(27), DI31=>Data(28), DI32=>Data(29),
- DI33=>Data(30), DI34=>Data(31), DI35=>scuba_vlo,
- ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
- ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
- ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>scuba_vlo,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>RdAddress(0),
- ADR4=>RdAddress(1), ADR5=>RdAddress(2), ADR6=>RdAddress(3),
- ADR7=>RdAddress(4), ADR8=>RdAddress(5), ADR9=>RdAddress(6),
- ADR10=>RdAddress(7), ADR11=>RdAddress(8),
- ADR12=>RdAddress(9), ADR13=>scuba_vlo, CER=>RdClockEn,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2),
- DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7),
- DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
- DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
- DO18=>open, DO19=>open, DO20=>open, DO21=>open, DO22=>open,
- DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open,
- DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open,
- DO33=>open, DO34=>open, DO35=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of statts_mem is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 6.1
--- Mon Dec 5 22:40:38 2011
-
--- parameterized module component declaration
-component statts_mem
- port (WrAddress: in std_logic_vector(7 downto 0);
- RdAddress: in std_logic_vector(9 downto 0);
- Data: in std_logic_vector(31 downto 0); WE: in std_logic;
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; WrClock: in std_logic;
- WrClockEn: in std_logic; Q: out std_logic_vector(7 downto 0));
-end component;
-
--- parameterized module component instance
-__ : statts_mem
- port map (WrAddress(7 downto 0)=>__, RdAddress(9 downto 0)=>__, Data(31 downto 0)=>__,
- WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__,
- WrClockEn=>__, Q(7 downto 0)=>__);
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_1024x16x8
- port (Data : in std_logic_vector(17 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(17 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(8 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_1024x16x8
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 1027 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 1027 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 1027 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_2048x8
- port (Data : in std_logic_vector(7 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(7 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_2048x8
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 2051 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_2048x8x16
- port (Data : in std_logic_vector(8 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(17 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(8 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(17 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_2048x8x16
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 2051 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 2051 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.9.1.119
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-use IEEE.math_real.all;
-
-use IEEE.numeric_std.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_32kx16x8_mb2
- port (Data : in std_logic_vector(17 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(8 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(17 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0');
- signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0');
- signal Q : std_logic_vector(8 downto 0);
- signal WCNT : std_logic_vector(15 downto 0);
- signal RCNT : std_logic_vector(16 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
- signal AlmostEmpty: std_logic;
- signal AlmostFull: std_logic;
-begin
- u1 : fifo_32kx16x8_mb2
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh,
- Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full,
- AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 32771 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_32kx16x8_mb
- port (Data : in std_logic_vector(15 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(7 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic;
- AlmostFull: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(15 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0');
- signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0');
- signal Q : std_logic_vector(7 downto 0);
- signal WCNT : std_logic_vector(15 downto 0);
- signal RCNT : std_logic_vector(16 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
- signal AlmostEmpty: std_logic;
- signal AlmostFull: std_logic;
-begin
- u1 : fifo_32kx16x8_mb
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh,
- Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full,
- AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 32771 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 32771 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41)\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.std_logic_unsigned.all;\r
-\r
-entity tb is\r
-end entity tb;\r
-\r
-\r
-architecture test of tb is \r
-\r
- component fifo_32kx16x8\r
- port (Data : in std_logic_vector(15 downto 0); \r
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; \r
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; \r
- Q : out std_logic_vector(7 downto 0); \r
- WCNT : out std_logic_vector(15 downto 0); \r
- RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; \r
- Full: out std_logic\r
- );\r
- end component;\r
-\r
- signal Data : std_logic_vector(15 downto 0) := (others => '0');\r
- signal WrClock: std_logic := '0';\r
- signal RdClock: std_logic := '0';\r
- signal WrEn: std_logic := '0';\r
- signal RdEn: std_logic := '0';\r
- signal Reset: std_logic := '0';\r
- signal RPReset: std_logic := '0';\r
- signal Q : std_logic_vector(7 downto 0);\r
- signal WCNT : std_logic_vector(15 downto 0);\r
- signal RCNT : std_logic_vector(16 downto 0);\r
- signal Empty: std_logic;\r
- signal Full: std_logic;\r
-begin\r
- u1 : fifo_32kx16x8\r
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock, \r
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, \r
- Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full\r
- );\r
-\r
- process\r
-\r
- begin\r
- Data <= (others => '0') ;\r
- wait for 100 ns;\r
- wait until Reset = '0';\r
- for i in 0 to 32771 loop\r
- wait until WrClock'event and WrClock = '1';\r
- Data <= Data + '1' after 1 ns;\r
- end loop;\r
- wait;\r
- end process;\r
-\r
- WrClock <= not WrClock after 5.00 ns;\r
-\r
- RdClock <= not RdClock after 5.00 ns;\r
-\r
- process\r
-\r
- begin\r
- WrEn <= '0' ;\r
- wait for 100 ns;\r
- wait until Reset = '0';\r
- for i in 0 to 32771 loop\r
- wait until WrClock'event and WrClock = '1';\r
- WrEn <= '1' after 1 ns;\r
- end loop;\r
- WrEn <= '0' ;\r
- wait;\r
- end process;\r
-\r
- process\r
-\r
- begin\r
- RdEn <= '0' ;\r
- wait until Reset = '0';\r
- wait until WrEn = '1';\r
- wait until WrEn = '0';\r
- for i in 0 to 32771 loop\r
- wait until RdClock'event and RdClock = '1';\r
- RdEn <= '1' after 1 ns;\r
- end loop;\r
- RdEn <= '0' ;\r
- wait;\r
- end process;\r
-\r
- process\r
-\r
- begin\r
- Reset <= '1' ;\r
- wait for 100 ns;\r
- Reset <= '0' ;\r
- wait;\r
- end process;\r
-\r
- process\r
-\r
- begin\r
- RPReset <= '1' ;\r
- wait for 100 ns;\r
- RPReset <= '0' ;\r
- wait;\r
- end process;\r
-\r
-end architecture test;\r
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_4096x32
- port (Data : in std_logic_vector(31 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(31 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(31 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(31 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_4096x32
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 4099 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_4096x9
- port (Data : in std_logic_vector(8 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(8 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(8 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_4096x9
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 4099 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 4099 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_512x32
- port (Data : in std_logic_vector(31 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(31 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(31 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(31 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_512x32
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 515 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_512x64
- port (Data : in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(71 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(71 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(71 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_512x64
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 515 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_512x72
- port (Data : in std_logic_vector(71 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(71 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(71 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(71 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_512x72
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 515 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 515 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_64kx8
- port (Data : in std_logic_vector(7 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(7 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(7 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_64kx8
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 65539 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.9.1.119
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-use IEEE.math_real.all;
-
-use IEEE.numeric_std.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component fifo_64kx9
- port (Data : in std_logic_vector(8 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(8 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(8 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(8 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : fifo_64kx9
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 65539 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 65539 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component ip_mem
- port (DataInA : in std_logic_vector(31 downto 0);
- DataInB : in std_logic_vector(31 downto 0);
- AddressA : in std_logic_vector(7 downto 0);
- AddressB : in std_logic_vector(7 downto 0); ClockA: in std_logic;
- ClockB: in std_logic; ClockEnA: in std_logic;
- ClockEnB: in std_logic; WrA: in std_logic; WrB: in std_logic;
- ResetA: in std_logic; ResetB: in std_logic;
- QA : out std_logic_vector(31 downto 0);
- QB : out std_logic_vector(31 downto 0)
- );
- end component;
-
- signal DataInA : std_logic_vector(31 downto 0) := (others => '0');
- signal DataInB : std_logic_vector(31 downto 0) := (others => '0');
- signal AddressA : std_logic_vector(7 downto 0) := (others => '0');
- signal AddressB : std_logic_vector(7 downto 0) := (others => '0');
- signal ClockA: std_logic := '0';
- signal ClockB: std_logic := '0';
- signal ClockEnA: std_logic := '0';
- signal ClockEnB: std_logic := '0';
- signal WrA: std_logic := '0';
- signal WrB: std_logic := '0';
- signal ResetA: std_logic := '0';
- signal ResetB: std_logic := '0';
- signal QA : std_logic_vector(31 downto 0);
- signal QB : std_logic_vector(31 downto 0);
-begin
- u1 : ip_mem
- port map (DataInA => DataInA, DataInB => DataInB, AddressA => AddressA,
- AddressB => AddressB, ClockA => ClockA, ClockB => ClockB,
- ClockEnA => ClockEnA, ClockEnB => ClockEnB, WrA => WrA, WrB => WrB,
- ResetA => ResetA, ResetB => ResetB, QA => QA, QB => QB
- );
-
- process
-
- begin
- DataInA <= (others => '0') ;
- wait for 100 ns;
- wait until ResetA = '0';
- for i in 0 to 259 loop
- wait until ClockA'event and ClockA = '1';
- DataInA <= DataInA + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- DataInB <= (others => '0') ;
- wait for 100 ns;
- wait until ResetB = '0';
- wait until WrB = '1';
- for i in 0 to 259 loop
- wait until ClockB'event and ClockB = '1';
- DataInB <= DataInB + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- AddressA <= (others => '0') ;
- wait for 100 ns;
- wait until ResetA = '0';
- for i in 0 to 518 loop
- wait until ClockA'event and ClockA = '1';
- AddressA <= AddressA + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- AddressB <= (others => '0') ;
- wait for 100 ns;
- wait until ResetB = '0';
- wait until WrB = '1';
- for i in 0 to 518 loop
- wait until ClockB'event and ClockB = '1';
- AddressB <= AddressB + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- ClockA <= not ClockA after 5.00 ns;
-
- ClockB <= not ClockB after 5.00 ns;
-
- process
-
- begin
- ClockEnA <= '0' ;
- wait for 100 ns;
- wait until ResetA = '0';
- ClockEnA <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- ClockEnB <= '0' ;
- wait for 100 ns;
- wait until ResetB = '0';
- ClockEnB <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- WrA <= '0' ;
- wait until ResetA = '0';
- for i in 0 to 259 loop
- wait until ClockA'event and ClockA = '1';
- WrA <= '1' after 1 ns;
- end loop;
- WrA <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- WrB <= '0' ;
- wait until ResetB = '0';
- wait until WrA = '1';
- wait until WrA = '0';
- for i in 0 to 259 loop
- wait until ClockA'event and ClockA = '1';
- end loop;
- for i in 0 to 259 loop
- wait until ClockB'event and ClockB = '1';
- WrB <= '1' after 1 ns;
- end loop;
- WrB <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- ResetA <= '1' ;
- wait for 100 ns;
- ResetA <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- ResetB <= '1' ;
- wait for 100 ns;
- ResetB <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component mac_init_mem
- port (Address : in std_logic_vector(5 downto 0);
- OutClock: in std_logic; OutClockEn: in std_logic;
- Reset: in std_logic; Q : out std_logic_vector(7 downto 0)
- );
- end component;
-
- signal Address : std_logic_vector(5 downto 0) := (others => '0');
- signal OutClock: std_logic := '0';
- signal OutClockEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
-begin
- u1 : mac_init_mem
- port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn,
- Reset => Reset, Q => Q
- );
-
- process
-
- begin
- Address <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 57 loop
- wait until OutClock'event and OutClock = '1';
- Address <= Address + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- OutClock <= not OutClock after 5.00 ns;
-
- process
-
- begin
- OutClockEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- OutClockEn <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component statts_mem
- port (WrAddress : in std_logic_vector(7 downto 0);
- RdAddress : in std_logic_vector(9 downto 0);
- Data : in std_logic_vector(31 downto 0); WE: in std_logic;
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; WrClock: in std_logic;
- WrClockEn: in std_logic; Q : out std_logic_vector(7 downto 0)
- );
- end component;
-
- signal WrAddress : std_logic_vector(7 downto 0) := (others => '0');
- signal RdAddress : std_logic_vector(9 downto 0) := (others => '0');
- signal Data : std_logic_vector(31 downto 0) := (others => '0');
- signal WE: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal RdClockEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal WrClock: std_logic := '0';
- signal WrClockEn: std_logic := '0';
- signal Q : std_logic_vector(7 downto 0);
-begin
- u1 : statts_mem
- port map (WrAddress => WrAddress, RdAddress => RdAddress, Data => Data,
- WE => WE, RdClock => RdClock, RdClockEn => RdClockEn, Reset => Reset,
- WrClock => WrClock, WrClockEn => WrClockEn, Q => Q
- );
-
- process
-
- begin
- WrAddress <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 516 loop
- wait until WrClock'event and WrClock = '1';
- WrAddress <= WrAddress + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- RdAddress <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 516 loop
- wait until RdClock'event and RdClock = '1';
- RdAddress <= RdAddress + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 258 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- WE <= '0' ;
- wait until Reset = '0';
- for i in 0 to 258 loop
- wait until WrClock'event and WrClock = '1';
- WE <= '1' after 1 ns;
- end loop;
- WE <= '0' ;
- wait;
- end process;
-
- RdClock <= not RdClock after 20.00 ns;
-
- process
-
- begin
- RdClockEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- RdClockEn <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- process
-
- begin
- WrClockEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- WrClockEn <= '1' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
-*.jhd
-*.naf
-*.srp
-*.sym
-*.log
-*.tcl
-*.v
-*tmpl.vhd
-ts_mac_eval
+++ /dev/null
-[Device]
-Family=ep5m00
-PartType=LFE2M100E
-PartName=LFE2M100E-6F900C
-SpeedGrade=-6
-Package=FPBGA900
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=IPCFG
-CoreStatus=Demo
-CoreName=Tri-Speed Ethernet MAC
-CoreRevision=3.4
-ModuleName=tsmac3
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=06/17/2011
-Time=11:30:22
-
-[Parameters]
-MIIM=No
-MODE=SGMII easy connect
-SYNP_TOOL=1
-PREC_TOOL=0
-MODS_TOOL=1
-ALDC_TOOL=0
-MULT_WB=NO
-LOOPBACK=NO
-STAT_REGS=NO
-
-[Files]
-Synthesis=
-Simulation=
-Logical=
-Physical=
-Misc=
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-use IEEE.std_logic_arith.all;\r
-\r
-library work;\r
---use work.trb_net_std.all;\r
---use work.trb_net_components.all;\r
---use work.trb_net16_hub_func.all;\r
-\r
-entity mb_mac_sim is\r
-port (\r
- --------------------------------------------------------------------------\r
- --------------- clock, reset, clock enable -------------------------------\r
- HCLK : in std_logic;\r
- TX_MAC_CLK : in std_logic;\r
- RX_MAC_CLK : in std_logic;\r
- RESET_N : in std_logic;\r
- TXMAC_CLK_EN : in std_logic;\r
- RXMAC_CLK_EN : in std_logic;\r
- --------------------------------------------------------------------------\r
- --------------- SGMII receive interface ----------------------------------\r
- RXD : in std_logic_vector(7 downto 0);\r
- RX_DV : in std_logic;\r
- RX_ER : in std_logic;\r
- COL : in std_logic;\r
- CRS : in std_logic;\r
- --------------------------------------------------------------------------\r
- --------------- SGMII transmit interface ---------------------------------\r
- TXD : out std_logic_vector(7 downto 0);\r
- TX_EN : out std_logic;\r
- TX_ER : out std_logic;\r
- --------------------------------------------------------------------------\r
- --------------- CPU configuration interface ------------------------------\r
- HADDR : in std_logic_vector(7 downto 0);\r
- HDATAIN : in std_logic_vector(7 downto 0);\r
- HCS_N : in std_logic;\r
- HWRITE_N : in std_logic;\r
- HREAD_N : in std_logic;\r
- HDATAOUT : out std_logic_vector(7 downto 0);\r
- HDATAOUT_EN_N : out std_logic;\r
- HREADY_N : out std_logic;\r
- CPU_IF_GBIT_EN : out std_logic;\r
- --------------------------------------------------------------------------\r
- --------------- Transmit FIFO interface ----------------------------------\r
- TX_FIFODATA : in std_logic_vector(7 downto 0);\r
- TX_FIFOAVAIL : in std_logic;\r
- TX_FIFOEOF : in std_logic;\r
- TX_FIFOEMPTY : in std_logic;\r
- TX_MACREAD : out std_logic;\r
- TX_DONE : out std_logic;\r
- TX_SNDPAUSTIM : in std_logic_vector(15 downto 0);\r
- TX_SNDPAUSREQ : in std_logic;\r
- TX_FIFOCTRL : in std_logic;\r
- TX_DISCFRM : out std_logic;\r
- TX_STATEN : out std_logic;\r
- TX_STATVEC : out std_logic_vector(30 downto 0);\r
- --------------------------------------------------------------------------\r
- --------------- Receive FIFO interface -----------------------------------\r
- RX_DBOUT : out std_logic_vector(7 downto 0);\r
- RX_FIFO_FULL : in std_logic;\r
- IGNORE_PKT : in std_logic; \r
- RX_FIFO_ERROR : out std_logic;\r
- RX_STAT_VECTOR : out std_logic_vector(31 downto 0);\r
- RX_STAT_EN : out std_logic;\r
- RX_WRITE : out std_logic;\r
- RX_EOF : out std_logic;\r
- RX_ERROR : out std_logic\r
-);\r
-end mb_mac_sim;\r
-\r
-architecture mb_mac_sim of mb_mac_sim is\r
-\r
-\r
--- CPU interface stuff\r
-type HC_STATES is (HC_SLEEP, HC_READ, HC_WRITE, HC_RACK, HC_WACK);\r
-signal HC_CURRENT_STATE, HC_NEXT_STATE: HC_STATES;\r
-\r
-signal hready_n_comb : std_logic;\r
-signal hready_n_buf : std_logic;\r
-signal hdataout_en_n_comb : std_logic;\r
-signal hdataout_en_n_buf : std_logic;\r
-\r
--- TX stuff\r
-type TX_STATES is (TX_SLEEP, TX_READ, TX_DELAY, TX_TRANS, TX_CHECK);\r
-signal TX_CURRENT_STATE, TX_NEXT_STATE: TX_STATES;\r
-\r
-signal tx_bsm : std_logic_vector(3 downto 0);\r
-signal tx_macread_comb : std_logic;\r
-signal tx_done_comb : std_logic;\r
-signal tx_done_buf : std_logic;\r
-\r
-signal preread_ctr : std_logic_vector(3 downto 0); -- preread counter for TX\r
-signal preread_ce_comb : std_logic;\r
-signal preread_rst_comb : std_logic;\r
-signal preread_done_comb : std_logic;\r
-signal read_on_comb : std_logic;\r
-\r
-\r
-begin\r
-\r
-------------------------------------------------------------------------------\r
--- state machine for configuration interface\r
-------------------------------------------------------------------------------\r
--- BUG: no register simulated here!\r
-\r
--- state registers\r
-HC_STATE_MEM: process( HCLK ) \r
-begin\r
- if ( RESET_N = '0' ) then\r
- HC_CURRENT_STATE <= HC_SLEEP;\r
- hready_n_buf <= '1';\r
- hdataout_en_n_buf <= '1';\r
- elsif( rising_edge(HCLK) ) then\r
- HC_CURRENT_STATE <= HC_NEXT_STATE;\r
- hready_n_buf <= hready_n_comb;\r
- hdataout_en_n_buf <= hdataout_en_n_comb;\r
- end if;\r
-end process HC_STATE_MEM;\r
-\r
--- state transitions\r
-HC_STATE_TRANSFORM: process( HC_CURRENT_STATE, HCS_N, HREAD_N, HWRITE_N )\r
-begin\r
- HC_NEXT_STATE <= HC_SLEEP; -- avoid latches\r
- hready_n_comb <= '1';\r
- hdataout_en_n_comb <= '1';\r
- case HC_CURRENT_STATE is\r
- when HC_SLEEP => if ( (HCS_N = '0') and (HREAD_N = '0') ) then\r
- HC_NEXT_STATE <= HC_READ;\r
- elsif( (HCS_N = '0') and (HWRITE_N = '0') ) then\r
- HC_NEXT_STATE <= HC_WRITE;\r
- else\r
- HC_NEXT_STATE <= HC_SLEEP;\r
- end if;\r
- when HC_READ => HC_NEXT_STATE <= HC_RACK;\r
- hdataout_en_n_comb <= '0';\r
- hready_n_comb <= '0';\r
- when HC_RACK => HC_NEXT_STATE <= HC_SLEEP;\r
- when HC_WRITE => HC_NEXT_STATE <= HC_WACK;\r
- hready_n_comb <= '0';\r
- when HC_WACK => HC_NEXT_STATE <= HC_SLEEP;\r
- when others => HC_NEXT_STATE <= HC_SLEEP;\r
- end case;\r
-end process HC_STATE_TRANSFORM; \r
-\r
-HREADY_N <= hready_n_buf;\r
-HDATAOUT_EN_N <= hdataout_en_n_buf;\r
-\r
-------------------------------------------------------------------------------\r
--- state machine for "transmission"\r
-------------------------------------------------------------------------------\r
-\r
--- preread counter\r
-THE_PREREAD_CTR: process( TX_MAC_CLK )\r
-begin\r
- if ( RESET_N = '0' ) then\r
- preread_ctr <= (others => '0');\r
- elsif( rising_edge(TX_MAC_CLK) ) then\r
- if ( preread_rst_comb = '1' ) then\r
- preread_ctr <= (others => '0');\r
- elsif( preread_ce_comb = '1' ) then\r
- preread_ctr <= preread_ctr + 1; \r
- end if;\r
- end if; \r
-end process THE_PREREAD_CTR;\r
-preread_done_comb <= '1' when (preread_ctr = x"6") \r
- else '0';\r
-\r
--- state registers\r
-TX_STATE_MEM: process( TX_MAC_CLK, RESET_N ) \r
-begin\r
- if ( RESET_N = '0' ) then\r
- TX_CURRENT_STATE <= TX_SLEEP;\r
- tx_done_buf <= '0';\r
- elsif( rising_edge(TX_MAC_CLK) ) then\r
- TX_CURRENT_STATE <= TX_NEXT_STATE;\r
- tx_done_buf <= tx_done_comb;\r
- end if;\r
-end process TX_STATE_MEM;\r
-\r
-tx_macread_comb <= preread_ce_comb or read_on_comb;\r
-\r
--- state transitions\r
-TX_STATE_TRANSFORM: process( TX_CURRENT_STATE, TX_FIFOEMPTY, TX_FIFOAVAIL, TX_FIFOEOF, preread_done_comb )\r
-begin\r
- TX_NEXT_STATE <= TX_SLEEP; -- avoid latches\r
- preread_ce_comb <= '0';\r
- preread_rst_comb <= '0';\r
- read_on_comb <= '0';\r
- tx_done_comb <= '0';\r
- case TX_CURRENT_STATE is\r
- when TX_SLEEP => tx_bsm <= x"0";\r
- if( TX_FIFOEMPTY = '0' ) then\r
- TX_NEXT_STATE <= TX_READ;\r
- preread_ce_comb <= '1';\r
- else\r
- TX_NEXT_STATE <= TX_SLEEP;\r
- end if;\r
- when TX_READ => tx_bsm <= x"1";\r
- if ( TX_FIFOEMPTY = '1' ) then\r
- TX_NEXT_STATE <= TX_DELAY;\r
- preread_rst_comb <= '1';\r
- elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '0') ) then\r
- TX_NEXT_STATE <= TX_DELAY;\r
- preread_rst_comb <= '1';\r
- elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '1') ) then\r
- TX_NEXT_STATE <= TX_TRANS;\r
- preread_rst_comb <= '1';\r
- read_on_comb <= '1';\r
- else\r
- TX_NEXT_STATE <= TX_READ;\r
- preread_ce_comb <= '1';\r
- end if;\r
- when TX_DELAY => tx_bsm <= x"2";\r
- if( TX_FIFOAVAIL = '1' ) then\r
- TX_NEXT_STATE <= TX_TRANS;\r
- read_on_comb <= '1';\r
- else\r
- TX_NEXT_STATE <= TX_DELAY;\r
- end if;\r
- when TX_TRANS => tx_bsm <= x"3";\r
- if( TX_FIFOEOF = '1' ) then\r
- TX_NEXT_STATE <= TX_CHECK;\r
- tx_done_comb <= '1'; -- don't know if this is realistic\r
- else\r
- TX_NEXT_STATE <= TX_TRANS;\r
- read_on_comb <= '1';\r
- end if;\r
- when TX_CHECK => tx_bsm <= x"4";\r
- if( (TX_FIFOEMPTY = '0') and (TX_FIFOAVAIL = '1') ) then\r
- TX_NEXT_STATE <= TX_READ;\r
- preread_ce_comb <= '1';\r
- else\r
- TX_NEXT_STATE <= TX_SLEEP;\r
- end if;\r
- when others => tx_bsm <= x"f";\r
- TX_NEXT_STATE <= TX_SLEEP;\r
- end case;\r
-end process TX_STATE_TRANSFORM;\r
-\r
-\r
-\r
-\r
-------------------------------------------------------------------------------\r
--- Fake signals\r
-------------------------------------------------------------------------------\r
-RX_DBOUT <= preread_ctr & tx_bsm; -- x"00";\r
-RX_FIFO_ERROR <= '0';\r
-RX_STAT_VECTOR <= x"0000_0000";\r
-RX_STAT_EN <= '0';\r
-RX_WRITE <= '0';\r
-RX_EOF <= '0';\r
-RX_ERROR <= '0';\r
-\r
-TX_DISCFRM <= '0';\r
-TX_EN <= '0';\r
-TX_ER <= '0';\r
-TX_STATVEC <= (others => '0');\r
-TX_STATEN <= '0';\r
-TXD <= x"00";\r
-\r
-CPU_IF_GBIT_EN <= '0';\r
-\r
-TX_DONE <= tx_done_buf;\r
-TX_MACREAD <= tx_macread_comb;\r
-\r
-HDATAOUT <= x"00";\r
-\r
-\r
-end mb_mac_sim;\r
-\r
-\r
---port map(\r
--- --------------------------------------------------------------------------\r
--- --------------- clock, reset, clock enable -------------------------------\r
--- hclk => CLK, -- (in) host clock (100MHz)\r
--- txmac_clk => TX_MAC_CLK, -- (in) GbE clock (125MHz)\r
--- rxmac_clk => '0', -- (in) not used (no receiving on GbE)\r
--- reset_n => GSR_N, -- (in) global set/reset\r
--- txmac_clk_en => TSM_TX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation\r
--- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation\r
--- --------------------------------------------------------------------------\r
--- --------------- SGMII receive interface ----------------------------------\r
--- rxd => x"00", -- (in) receive data from SGMII core\r
--- rx_dv => '0', -- (in) data valid from SGMII core\r
--- rx_er => '0', -- (in) receive data error \r
--- col => TSM_COL_IN, -- (in) collision from SGMII core\r
--- crs => TSM_CRS_IN, -- (in) carrier sense from SGMII core\r
--- --------------------------------------------------------------------------\r
--- --------------- SGMII transmit interface ---------------------------------\r
--- txd => CH_TXD_OUT, -- (out) transmit data to SGMII core\r
--- tx_en => CH_TX_EN_OUT, -- (out) transmit enable\r
--- tx_er => CH_TX_ER_OUT, -- (out) transmit error\r
--- --------------------------------------------------------------------------\r
--- --------------- CPU configuration interface ------------------------------\r
--- haddr => haddr, -- (in) host address bus for configuration\r
--- hdatain => hdataout, -- (in) host data bus for write accesses\r
--- hcs_n => hcs, -- (in) host chip select signal\r
--- hwrite_n => hwrite, -- (in) host write strobe signal\r
--- hread_n => hread, -- (in) host read strobe signal\r
--- hdataout => hdatain, -- (out) host data bus for read accesses\r
--- hdataout_en_n => hdataout_en, -- (out) read data valid signal\r
--- hready_n => hready, -- (out) data acknowledge signal \r
--- cpu_if_gbit_en => open, -- (out) status bit \r
--- --------------------------------------------------------------------------\r
--- --------------- Transmit FIFO interface ----------------------------------\r
--- tx_fifodata => ft_data(7 downto 0), -- (in) transmit FIFO data bus\r
--- tx_fifoavail => mac_fifoavail, -- (in) transmit FIFO data available\r
--- tx_fifoeof => mac_fifoeof, -- (in) transmit FIFO end of frame \r
--- tx_fifoempty => mac_fifoempty, -- (in) transmit FIFO empty\r
--- tx_macread => mac_tx_rd_en, -- (out) transmit FIFO read\r
--- tx_done => mac_tx_done, -- (out) transmit done (without errors)\r
--- tx_sndpaustim => x"0000", -- (in) PAUSE frame timer\r
--- tx_sndpausreq => '0', -- (in) PAUSE frame request\r
--- tx_fifoctrl => '0', -- (in) FIFO control frame ('0' = data, '1' = control)\r
--- tx_discfrm => open, -- (out) discard frame\r
--- tx_staten => open, -- (out) transmit statistics vector enable \r
--- tx_statvec => open, -- (out) transmit statistics vector\r
--- --------------------------------------------------------------------------\r
--- --------------- Receive FIFO interface -----------------------------------\r
--- rx_dbout => open, -- (out) receive FIFO data output\r
--- rx_fifo_full => '0', -- (in) receive FIFO full\r
--- ignore_pkt => '0', -- (in) ignore next packet\r
--- rx_fifo_error => open, -- (out) receive FIFO error\r
--- rx_stat_vector => open, -- (out) receive statistics vector\r
--- rx_stat_en => open, -- (out) receive statistics vector enable\r
--- rx_write => open, -- (out) receive FIFO write\r
--- rx_eof => open, -- (out) end of frame\r
--- rx_error => open -- (out) receive packet error\r
---);\r
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-
-entity slv_mac_memory is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- BUSY_IN : in std_logic;
- -- Slave bus
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- I/O to the backend
- MEM_CLK_IN : in std_logic;
- MEM_ADDR_IN : in std_logic_vector(7 downto 0);
- MEM_DATA_OUT : out std_logic_vector(31 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
-);
-end entity;
-
-architecture Behavioral of slv_mac_memory is
-
-component ip_mem is
-port(
- DataInA : in std_logic_vector(31 downto 0);
- DataInB : in std_logic_vector(31 downto 0);
- AddressA : in std_logic_vector(7 downto 0);
- AddressB : in std_logic_vector(7 downto 0);
- ClockA : in std_logic;
- ClockB : in std_logic;
- ClockEnA : in std_logic;
- ClockEnB : in std_logic;
- WrA : in std_logic;
- WrB : in std_logic;
- ResetA : in std_logic;
- ResetB : in std_logic;
- QA : out std_logic_vector(31 downto 0);
- QB : out std_logic_vector(31 downto 0)
-);
-end component ip_mem;
-
--- Signals
-type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
-signal CURRENT_STATE, NEXT_STATE: STATES;
-
--- slave bus signals
-signal slv_busy_x : std_logic;
-signal slv_busy : std_logic;
-signal slv_ack_x : std_logic;
-signal slv_ack : std_logic;
-signal store_wr_x : std_logic;
-signal store_wr : std_logic;
-signal store_rd_x : std_logic;
-signal store_rd : std_logic;
-
-signal reg_busy : std_logic;
-
-begin
-
--- Fake
-reg_busy <= busy_in;
-stat <= (others => '0');
-
----------------------------------------------------------
--- Statemachine --
----------------------------------------------------------
--- State memory process
-STATE_MEM: process( clk )
-begin
- if( rising_edge(clk) ) then
- if( reset = '1' ) then
- CURRENT_STATE <= SLEEP;
- slv_busy <= '0';
- slv_ack <= '0';
- store_wr <= '0';
- store_rd <= '0';
- else
- CURRENT_STATE <= NEXT_STATE;
- slv_busy <= slv_busy_x;
- slv_ack <= slv_ack_x;
- store_wr <= store_wr_x;
- store_rd <= store_rd_x;
- end if;
- end if;
-end process STATE_MEM;
-
--- Transition matrix
-TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy )
-begin
- NEXT_STATE <= SLEEP;
- slv_busy_x <= '0';
- slv_ack_x <= '0';
- store_wr_x <= '0';
- store_rd_x <= '0';
- case CURRENT_STATE is
- when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then
- NEXT_STATE <= RD_RDY;
- store_rd_x <= '1';
- elsif( (reg_busy = '0') and (slv_write_in = '1') ) then
- NEXT_STATE <= WR_RDY;
- store_wr_x <= '1';
- elsif( (reg_busy = '1') and (slv_read_in = '1') ) then
- NEXT_STATE <= RD_BSY;
- elsif( (reg_busy = '1') and (slv_write_in = '1') ) then
- NEXT_STATE <= WR_BSY;
- else
- NEXT_STATE <= SLEEP;
- end if;
- when RD_RDY => NEXT_STATE <= RD_ACK;
- when WR_RDY => NEXT_STATE <= WR_ACK;
- when RD_ACK => if( slv_read_in = '0' ) then
- NEXT_STATE <= DONE;
- slv_ack_x <= '1';
- else
- NEXT_STATE <= RD_ACK;
- slv_ack_x <= '1';
- end if;
- when WR_ACK => if( slv_write_in = '0' ) then
- NEXT_STATE <= DONE;
- slv_ack_x <= '1';
- else
- NEXT_STATE <= WR_ACK;
- slv_ack_x <= '1';
- end if;
- when RD_BSY => if( slv_read_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= RD_BSY;
- slv_busy_x <= '1';
- end if;
- when WR_BSY => if( slv_write_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= WR_BSY;
- slv_busy_x <= '1';
- end if;
- when DONE => NEXT_STATE <= SLEEP;
-
- when others => NEXT_STATE <= SLEEP;
- end case;
-end process TRANSFORM;
-
----------------------------------------------------------
--- data handling --
----------------------------------------------------------
-
-THE_MAC_MEM: ip_mem
-port map(
- DataInA => slv_data_in,
- AddressA => slv_addr_in,
- ClockA => clk,
- ClockEnA => '1',
- QA => slv_data_out,
- WrA => store_wr,
- ResetA => reset,
- DataInB => x"0000_0000",
- AddressB => mem_addr_in,
- ClockB => mem_clk_in,
- ClockEnB => '1',
- WrB => '0', -- never write
- ResetB => reset,
- QB => mem_data_out
-);
-
--- output signals
-slv_ack_out <= slv_ack;
-slv_busy_out <= slv_busy;
-
-end Behavioral;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
---use work.adcmv3_components.all;
-
-
-entity slv_register is
-generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" );
-port( CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- BUSY_IN : in std_logic;
- -- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- I/O to the backend
- REG_DATA_IN : in std_logic_vector(31 downto 0);
- REG_DATA_OUT : out std_logic_vector(31 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
- );
-end entity;
-
-architecture Behavioral of slv_register is
-
--- Signals
-
- type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
- signal CURRENT_STATE, NEXT_STATE: STATES;
-
- -- slave bus signals
- signal slv_busy_x : std_logic;
- signal slv_busy : std_logic;
- signal slv_ack_x : std_logic;
- signal slv_ack : std_logic;
- signal store_wr_x : std_logic;
- signal store_wr : std_logic;
- signal store_rd_x : std_logic;
- signal store_rd : std_logic;
-
- signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input
- signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data
- signal reg_busy : std_logic;
-
-begin
-
--- Fake
-reg_busy <= busy_in;
-stat <= (others => '0');
-
----------------------------------------------------------
--- Statemachine --
----------------------------------------------------------
--- State memory process
-STATE_MEM: process( clk_in )
-begin
- if( rising_edge(clk_in) ) then
- if( reset_in = '1' ) then
- CURRENT_STATE <= SLEEP;
- slv_busy <= '0';
- slv_ack <= '0';
- store_wr <= '0';
- store_rd <= '0';
- else
- CURRENT_STATE <= NEXT_STATE;
- slv_busy <= slv_busy_x;
- slv_ack <= slv_ack_x;
- store_wr <= store_wr_x;
- store_rd <= store_rd_x;
- end if;
- end if;
-end process STATE_MEM;
-
--- Transition matrix
-TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy )
-begin
- NEXT_STATE <= SLEEP;
- slv_busy_x <= '0';
- slv_ack_x <= '0';
- store_wr_x <= '0';
- store_rd_x <= '0';
- case CURRENT_STATE is
- when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then
- NEXT_STATE <= RD_RDY;
- store_rd_x <= '1';
- elsif( (reg_busy = '0') and (slv_write_in = '1') ) then
- NEXT_STATE <= WR_RDY;
- store_wr_x <= '1';
- elsif( (reg_busy = '1') and (slv_read_in = '1') ) then
- NEXT_STATE <= RD_BSY;
- slv_busy_x <= '1'; -- added 23022009
- elsif( (reg_busy = '1') and (slv_write_in = '1') ) then
- NEXT_STATE <= WR_BSY;
- slv_busy_x <= '1'; -- added 23022009
- else
- NEXT_STATE <= SLEEP;
- end if;
- when RD_RDY => NEXT_STATE <= RD_ACK;
- slv_ack_x <= '1';
- when WR_RDY => NEXT_STATE <= WR_ACK;
- slv_ack_x <= '1';
- when RD_ACK => if( slv_read_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= RD_ACK;
- slv_ack_x <= '1';
- end if;
- when WR_ACK => if( slv_write_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= WR_ACK;
- slv_ack_x <= '1';
- end if;
- when RD_BSY => if( slv_read_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= RD_BSY;
- slv_busy_x <= '1';
- end if;
- when WR_BSY => if( slv_write_in = '0' ) then
- NEXT_STATE <= DONE;
- else
- NEXT_STATE <= WR_BSY;
- slv_busy_x <= '1';
- end if;
- when DONE => NEXT_STATE <= SLEEP;
-
- when others => NEXT_STATE <= SLEEP;
- end case;
-end process TRANSFORM;
-
----------------------------------------------------------
--- data handling --
----------------------------------------------------------
-
--- register write
-THE_WRITE_REG_PROC: process( clk_in )
-begin
- if( rising_edge(clk_in) ) then
- if ( reset_in = '1' ) then
- reg_slv_data_in <= RESET_VALUE;
- elsif( store_wr = '1' ) then
- reg_slv_data_in <= slv_data_in;
- end if;
- end if;
-end process THE_WRITE_REG_PROC;
-
--- register read
-THE_READ_REG_PROC: process( clk_in )
-begin
- if( rising_edge(clk_in) ) then
- if ( reset_in = '1' ) then
- reg_slv_data_out <= (others => '0');
- elsif( store_rd = '1' ) then
- reg_slv_data_out <= reg_data_in;
- end if;
- end if;
-end process THE_READ_REG_PROC;
-
--- output signals
-slv_ack_out <= slv_ack;
-slv_busy_out <= slv_busy;
-slv_data_out <= reg_slv_data_out;
-
----------------------------------------------------------
--- signals to backend --
----------------------------------------------------------
-
-reg_data_out <= reg_slv_data_in;
-
-end Behavioral;
+++ /dev/null
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT feeder\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
- CTS_CODE_IN : IN std_logic_vector(7 downto 0);\r
- CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
- CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);\r
- CTS_START_READOUT_IN : IN std_logic;\r
- CTS_READ_IN : IN std_logic;\r
- FEE_DATA_IN : IN std_logic_vector(15 downto 0);\r
- FEE_DATAREADY_IN : IN std_logic;\r
- FEE_BUSY_IN : IN std_logic;\r
- FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);\r
- PC_READY_IN : IN std_logic; \r
- CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- CTS_DATAREADY_OUT : OUT std_logic;\r
- CTS_READOUT_FINISHED_OUT : OUT std_logic;\r
- CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
- CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
- FEE_READ_OUT : OUT std_logic;\r
- PC_WR_EN_OUT : OUT std_logic;\r
- PC_DATA_OUT : OUT std_logic_vector(7 downto 0);\r
- PC_SOS_OUT : OUT std_logic;\r
- PC_EOD_OUT : OUT std_logic;\r
- PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_PADDING_OUT : OUT std_logic;\r
- BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0);\r
- BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0);\r
- DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0);\r
- DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RD_EN_OUT : OUT std_logic;\r
- DBG_SF_WR_EN_OUT : OUT std_logic;\r
- DBG_SF_EMPTY_OUT : OUT std_logic;\r
- DBG_SF_FULL_OUT : OUT std_logic;\r
- DBG_SF_AFULL_OUT : OUT std_logic;\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);\r
- SIGNAL CTS_START_READOUT_IN : std_logic;\r
- SIGNAL CTS_READ_IN : std_logic;\r
- SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL CTS_DATAREADY_OUT : std_logic;\r
- SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;\r
- SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);\r
- SIGNAL FEE_DATAREADY_IN : std_logic;\r
- SIGNAL FEE_READ_OUT : std_logic;\r
- SIGNAL FEE_BUSY_IN : std_logic;\r
- SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);\r
- SIGNAL PC_WR_EN_OUT : std_logic;\r
- SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL PC_READY_IN : std_logic;\r
- SIGNAL PC_SOS_OUT : std_logic;\r
- SIGNAL PC_EOD_OUT : std_logic;\r
- SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_PADDING_OUT : std_logic;\r
- SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0);\r
- SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0);\r
- SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RD_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_WR_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_EMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_FULL_OUT : std_logic;\r
- SIGNAL DBG_SF_AFULL_OUT : std_logic;\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: feeder PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- CTS_NUMBER_IN => CTS_NUMBER_IN,\r
- CTS_CODE_IN => CTS_CODE_IN,\r
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,\r
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,\r
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,\r
- CTS_READ_IN => CTS_READ_IN,\r
- CTS_DATA_OUT => CTS_DATA_OUT,\r
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,\r
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,\r
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,\r
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,\r
- FEE_DATA_IN => FEE_DATA_IN,\r
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,\r
- FEE_READ_OUT => FEE_READ_OUT,\r
- FEE_BUSY_IN => FEE_BUSY_IN,\r
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,\r
- PC_WR_EN_OUT => PC_WR_EN_OUT,\r
- PC_DATA_OUT => PC_DATA_OUT,\r
- PC_READY_IN => PC_READY_IN,\r
- PC_SOS_OUT => PC_SOS_OUT,\r
- PC_EOD_OUT => PC_EOD_OUT,\r
- PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT,\r
- PC_TRIG_NR_OUT => PC_TRIG_NR_OUT,\r
- PC_PADDING_OUT => PC_PADDING_OUT,\r
- BSM_SAVE_OUT => BSM_SAVE_OUT,\r
- BSM_LOAD_OUT => BSM_LOAD_OUT,\r
- DBG_REM_CTR_OUT => DBG_REM_CTR_OUT,\r
- DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT,\r
- DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT,\r
- DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT,\r
- DBG_SF_DATA_OUT => DBG_SF_DATA_OUT,\r
- DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT,\r
- DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT,\r
- DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT,\r
- DBG_SF_FULL_OUT => DBG_SF_FULL_OUT,\r
- DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
-\r
-CLOCK_GEN: process\r
-begin\r
- clk <= '1'; wait for 5.0 ns;\r
- clk <= '0'; wait for 5.0 ns;\r
-end process CLOCK_GEN;\r
-\r
--- Testbench\r
-TESTBENCH_PROC: process\r
-variable test_data_len : integer range 0 to 65535 := 49;\r
-variable test_loop_len : integer range 0 to 65535 := 0;\r
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";\r
-variable test_evt_len : unsigned(15 downto 0) := x"0000";\r
-variable test_data : unsigned(15 downto 0) := x"ffff";\r
-\r
-variable trigger_counter : unsigned(15 downto 0) := x"4710";\r
-variable trigger_loop : integer range 0 to 65535 := 15;\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- cts_number_in <= x"0000";\r
- cts_code_in <= x"00";\r
- cts_information_in <= x"00";\r
- cts_readout_type_in <= x"0";\r
- cts_start_readout_in <= '0';\r
- cts_read_in <= '0';\r
- fee_data_in <= x"0000";\r
- fee_dataready_in <= '0';\r
- fee_status_bits_in <= x"0000_0000";\r
- fee_busy_in <= '0';\r
- pc_ready_in <= '0';\r
-\r
- wait for 22 ns;\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- wait for 200 ns;\r
-\r
-\r
--------------------------------------------------------------------------------\r
--- Loop the transmissions\r
--------------------------------------------------------------------------------\r
- trigger_counter := x"4710";\r
- trigger_loop := 9;\r
- test_data_len := 14;\r
-\r
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop\r
- -- IPU transmission starts\r
- wait until rising_edge(clk);\r
- cts_number_in <= std_logic_vector( trigger_counter );\r
- cts_code_in <= x"aa";\r
- cts_information_in <= x"de";\r
- cts_readout_type_in <= x"1";\r
- cts_start_readout_in <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- fee_busy_in <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- -- ONE DATA TRANSMISSION\r
- -- calculate the needed variables\r
--- test_data_len := 4096;\r
- test_loop_len := 2*(test_data_len - 1) + 1;\r
- test_hdr_len := to_unsigned( test_data_len + 1, 16 );\r
- test_evt_len := to_unsigned( test_data_len, 16 );\r
-\r
- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)\r
- fee_dataready_in <= '1';\r
- fee_data_in <= x"10aa";\r
- wait until rising_edge(clk);\r
- fee_data_in <= std_logic_vector( trigger_counter );\r
- wait until rising_edge(clk);\r
- fee_data_in <= std_logic_vector( test_hdr_len );\r
- wait until rising_edge(clk);\r
- fee_data_in <= x"ff21";\r
- wait until rising_edge(clk);\r
- fee_data_in <= std_logic_vector( test_evt_len );\r
- wait until rising_edge(clk);\r
- fee_data_in <= x"ff22"; \r
-\r
- test_data := x"ffff";\r
- MY_DATA_LOOP: for J in 0 to test_loop_len loop\r
- test_data := test_data + 1;\r
- wait until rising_edge(clk);\r
- fee_data_in <= std_logic_vector(test_data); \r
- end loop MY_DATA_LOOP;\r
- \r
- fee_busy_in <= '0'; -- correct?\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '0';\r
- fee_data_in <= x"0000"; \r
-\r
- trigger_loop := trigger_loop + 1;\r
- trigger_counter := trigger_counter + 1;\r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_read_in <= '1';\r
- wait until rising_edge(clk);\r
- cts_read_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_start_readout_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk); \r
- end loop MY_TRIGGER_LOOP;\r
--------------------------------------------------------------------------------\r
--------------------------------------------------------------------------------\r
--------------------------------------------------------------------------------\r
-\r
-\r
- wait for 300 ns;\r
-\r
- -- Start packet_constructor\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_ready_in <= '1';\r
- wait until rising_edge(clk);\r
-\r
- wait;\r
-\r
- wait until rising_edge(clk);\r
- wait until pc_eod_out = '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_ready_in <= '0';\r
-\r
- -- Stay a while... stay forever!!!\r
- wait; \r
- \r
-end process TESTBENCH_PROC;\r
-\r
-\r
-END;\r
+++ /dev/null
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.math_real.all;
-USE ieee.numeric_std.ALL;
-
-ENTITY testbench IS
-END testbench;
-
-ARCHITECTURE behavior OF testbench IS
- component trb_net16_gbe_buf is
- generic(
- DO_SIMULATION : integer range 0 to 1 := 1;
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
- );
- port(
- CLK : in std_logic;
- TEST_CLK : in std_logic; -- only for simulation!
- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
-RESET : IN std_logic;
- GSR_N : IN std_logic;
- STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0);
- ------------------------
- IP_CFG_START_IN : IN std_logic;
- IP_CFG_BANK_SEL_IN : IN std_logic_vector(3 downto 0);
- IP_CFG_MEM_DATA_IN : IN std_logic_vector(31 downto 0);
- MR_RESET_IN : IN std_logic;
- MR_MODE_IN : IN std_logic;
- MR_RESTART_IN : IN std_logic;
- IP_CFG_MEM_CLK_OUT : OUT std_logic;
- IP_CFG_DONE_OUT : OUT std_logic;
- IP_CFG_MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0);
- -- gk 29.03.10
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- gk 26.04.10
- -- registers setup interface
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
- -- gk 23.04.10
- LED_PACKET_SENT_OUT : out std_logic;
- LED_AN_DONE_N_OUT : out std_logic;
- ------------------------
- CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);
- CTS_CODE_IN : IN std_logic_vector(7 downto 0);
- CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);
- CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);
- CTS_START_READOUT_IN : IN std_logic;
- CTS_READ_IN : IN std_logic;
- FEE_DATA_IN : IN std_logic_vector(15 downto 0);
- FEE_DATAREADY_IN : IN std_logic;
- FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);
- FEE_BUSY_IN : IN std_logic;
- SFP_RXD_P_IN : IN std_logic;
- SFP_RXD_N_IN : IN std_logic;
- SFP_REFCLK_P_IN : IN std_logic;
- SFP_REFCLK_N_IN : IN std_logic;
- SFP_PRSNT_N_IN : IN std_logic;
- SFP_LOS_IN : IN std_logic;
- STAGE_STAT_REGS_OUT : OUT std_logic_vector(31 downto 0);
- CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);
- CTS_DATAREADY_OUT : OUT std_logic;
- CTS_READOUT_FINISHED_OUT : OUT std_logic;
- CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);
- CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);
- FEE_READ_OUT : OUT std_logic;
- SFP_TXD_P_OUT : OUT std_logic;
- SFP_TXD_N_OUT : OUT std_logic;
- SFP_TXDIS_OUT : OUT std_logic;
-
- ANALYZER_DEBUG_OUT : OUT std_logic_vector(63 downto 0)
- );
- END COMPONENT;
-
- SIGNAL CLK : std_logic;
- SIGNAL TEST_CLK : std_logic;
- SIGNAL RESET : std_logic;
- SIGNAL GSR_N : std_logic;
- SIGNAL STAGE_STAT_REGS_OUT : std_logic_vector(31 downto 0);
- SIGNAL STAGE_CTRL_REGS_IN : std_logic_vector(31 downto 0);
- SIGNAL IP_CFG_START_IN : std_logic;
- SIGNAL IP_CFG_BANK_SEL_IN : std_logic_vector(3 downto 0);
- SIGNAL IP_CFG_MEM_DATA_IN : std_logic_vector(31 downto 0);
- SIGNAL MR_RESET_IN : std_logic;
- SIGNAL MR_MODE_IN : std_logic;
- SIGNAL MR_RESTART_IN : std_logic;
- SIGNAL IP_CFG_MEM_CLK_OUT : std_logic;
- SIGNAL IP_CFG_DONE_OUT : std_logic;
- SIGNAL IP_CFG_MEM_ADDR_OUT : std_logic_vector(7 downto 0);
- SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);
- SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);
- SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);
- SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);
- SIGNAL CTS_START_READOUT_IN : std_logic;
- SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);
- SIGNAL CTS_DATAREADY_OUT : std_logic;
- SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;
- SIGNAL CTS_READ_IN : std_logic;
- SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);
- SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);
- SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);
- SIGNAL FEE_DATAREADY_IN : std_logic;
- SIGNAL FEE_READ_OUT : std_logic;
- SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);
- SIGNAL FEE_BUSY_IN : std_logic;
- SIGNAL SFP_RXD_P_IN : std_logic;
- SIGNAL SFP_RXD_N_IN : std_logic;
- SIGNAL SFP_TXD_P_OUT : std_logic;
- SIGNAL SFP_TXD_N_OUT : std_logic;
- SIGNAL SFP_REFCLK_P_IN : std_logic;
- SIGNAL SFP_REFCLK_N_IN : std_logic;
- SIGNAL SFP_PRSNT_N_IN : std_logic;
- SIGNAL SFP_LOS_IN : std_logic;
- SIGNAL SFP_TXDIS_OUT : std_logic;
- SIGNAL IG_CTS_CTR_TST : std_logic_vector(2 downto 0);
- SIGNAL IG_REM_CTR_TST : std_logic_vector(3 downto 0);
- SIGNAL IG_BSM_LOAD_TST : std_logic_vector(3 downto 0);
- SIGNAL IG_BSM_SAVE_TST : std_logic_vector(3 downto 0);
- SIGNAL IG_DATA_TST : std_logic_vector(15 downto 0);
- SIGNAL IG_WCNT_TST : std_logic_vector(15 downto 0);
- SIGNAL IG_RCNT_TST : std_logic_vector(16 downto 0);
- SIGNAL IG_RD_EN_TST : std_logic;
- SIGNAL IG_WR_EN_TST : std_logic;
- SIGNAL IG_EMPTY_TST : std_logic;
- SIGNAL IG_AEMPTY_TST : std_logic;
- SIGNAL IG_FULL_TST : std_logic;
- SIGNAL IG_AFULL_TST : std_logic;
- SIGNAL PC_WR_EN_TST : std_logic;
- SIGNAL PC_DATA_TST : std_logic_vector(7 downto 0);
- SIGNAL PC_READY_TST : std_logic;
- SIGNAL PC_START_OF_SUB_TST : std_logic;
- SIGNAL PC_END_OF_DATA_TST : std_logic;
- SIGNAL PC_SUB_SIZE_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_TRIG_NR_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_PADDING_TST : std_logic;
- SIGNAL PC_DECODING_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_EVENT_ID_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_QUEUE_DEC_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_BSM_CONSTR_TST : std_logic_vector(3 downto 0);
- SIGNAL PC_BSM_LOAD_TST : std_logic_vector(3 downto 0);
- SIGNAL PC_BSM_SAVE_TST : std_logic_vector(3 downto 0);
- SIGNAL PC_SHF_EMPTY_TST : std_logic;
- SIGNAL PC_SHF_FULL_TST : std_logic;
- SIGNAL PC_SHF_WR_EN_TST : std_logic;
- SIGNAL PC_SHF_RD_EN_TST : std_logic;
- SIGNAL PC_SHF_Q_TST : std_logic_vector(7 downto 0);
- SIGNAL PC_DF_EMPTY_TST : std_logic;
- SIGNAL PC_DF_FULL_TST : std_logic;
- SIGNAL PC_DF_WR_EN_TST : std_logic;
- SIGNAL PC_DF_RD_EN_TST : std_logic;
- SIGNAL PC_DF_Q_TST : std_logic_vector(7 downto 0);
- SIGNAL PC_ALL_CTR_TST : std_logic_vector(4 downto 0);
- SIGNAL PC_SUB_CTR_TST : std_logic_vector(4 downto 0);
- SIGNAL PC_BYTES_LOADED_TST : std_logic_vector(15 downto 0);
- SIGNAL PC_SIZE_LEFT_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_SUB_SIZE_TO_SAVE_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_SUB_SIZE_LOADED_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_SUB_BYTES_LOADED_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_QUEUE_SIZE_TST : std_logic_vector(31 downto 0);
- SIGNAL PC_ACT_QUEUE_SIZE_TST : std_logic_vector(31 downto 0);
- SIGNAL FC_WR_EN_TST : std_logic;
- SIGNAL FC_DATA_TST : std_logic_vector(7 downto 0);
- SIGNAL FC_H_READY_TST : std_logic;
- SIGNAL FC_READY_TST : std_logic;
- SIGNAL FC_IP_SIZE_TST : std_logic_vector(15 downto 0);
- SIGNAL FC_UDP_SIZE_TST : std_logic_vector(15 downto 0);
- SIGNAL FC_IDENT_TST : std_logic_vector(15 downto 0);
- SIGNAL FC_FLAGS_OFFSET_TST : std_logic_vector(15 downto 0);
- SIGNAL FC_SOD_TST : std_logic;
- SIGNAL FC_EOD_TST : std_logic;
- SIGNAL FC_BSM_CONSTR_TST : std_logic_vector(7 downto 0);
- SIGNAL FC_BSM_TRANS_TST : std_logic_vector(3 downto 0);
- SIGNAL FT_DATA_TST : std_logic_vector(8 downto 0);
- SIGNAL FT_TX_EMPTY_TST : std_logic;
- SIGNAL FT_START_OF_PACKET_TST : std_logic;
- SIGNAL FT_BSM_INIT_TST : std_logic_vector(3 downto 0);
- SIGNAL FT_BSM_MAC_TST : std_logic_vector(3 downto 0);
- SIGNAL FT_BSM_TRANS_TST : std_logic_vector(3 downto 0);
- SIGNAL MAC_HADDR_TST : std_logic_vector(7 downto 0);
- SIGNAL MAC_HDATA_TST : std_logic_vector(7 downto 0);
- SIGNAL MAC_HCS_TST : std_logic;
- SIGNAL MAC_HWRITE_TST : std_logic;
- SIGNAL MAC_HREAD_TST : std_logic;
- SIGNAL MAC_HREADY_TST : std_logic;
- SIGNAL MAC_HDATA_EN_TST : std_logic;
- SIGNAL MAC_FIFOAVAIL_TST : std_logic;
- SIGNAL MAC_FIFOEOF_TST : std_logic;
- SIGNAL MAC_FIFOEMPTY_TST : std_logic;
- SIGNAL MAC_TX_READ_TST : std_logic;
- SIGNAL MAC_TX_DONE_TST : std_logic;
- SIGNAL PCS_AN_LP_ABILITY_TST : std_logic_vector(15 downto 0);
- SIGNAL PCS_AN_COMPLETE_TST : std_logic;
- SIGNAL PCS_AN_PAGE_RX_TST : std_logic;
- SIGNAL ANALYZER_DEBUG_OUT : std_logic_vector(63 downto 0);
- --gk 29.03.10
- signal SLV_ADDR_IN : std_logic_vector(7 downto 0);
- signal SLV_READ_IN : std_logic;
- signal SLV_WRITE_IN : std_logic;
- signal SLV_BUSY_OUT : std_logic;
- signal SLV_ACK_OUT : std_logic;
- signal SLV_DATA_IN : std_logic_vector(31 downto 0);
- signal SLV_DATA_OUT : std_logic_vector(31 downto 0);
-
-BEGIN
-
--- Please check and add your generic clause manually
- uut: trb_net16_gbe_buf
- GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 )
- PORT MAP(
- CLK => CLK,
- CLK_125_IN => '0',
- TEST_CLK => TEST_CLK,
- RESET => RESET,
- GSR_N => GSR_N,
- STAGE_STAT_REGS_OUT => STAGE_STAT_REGS_OUT,
- STAGE_CTRL_REGS_IN => STAGE_CTRL_REGS_IN,
- IP_CFG_START_IN => IP_CFG_START_IN,
- IP_CFG_BANK_SEL_IN => IP_CFG_BANK_SEL_IN,
- IP_CFG_MEM_DATA_IN => IP_CFG_MEM_DATA_IN,
- MR_RESET_IN => MR_RESET_IN,
- MR_MODE_IN => MR_MODE_IN,
- MR_RESTART_IN => MR_RESTART_IN,
- IP_CFG_MEM_CLK_OUT => IP_CFG_MEM_CLK_OUT,
- IP_CFG_DONE_OUT => IP_CFG_DONE_OUT,
- IP_CFG_MEM_ADDR_OUT => IP_CFG_MEM_ADDR_OUT,
- -- gk 29.03.10
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
- -- gk 22.04.10
- -- registers setup interface
- BUS_ADDR_IN => x"00",
- BUS_DATA_IN => x"0000_0000",
- BUS_DATA_OUT => open,
- BUS_WRITE_EN_IN => '0',
- BUS_READ_EN_IN => '0',
- BUS_ACK_OUT => open,
- -- gk 23.04.10
- LED_PACKET_SENT_OUT => open,
- LED_AN_DONE_N_OUT => open,
- --------------------------
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- SFP_RXD_P_IN => SFP_RXD_P_IN,
- SFP_RXD_N_IN => SFP_RXD_N_IN,
- SFP_TXD_P_OUT => SFP_TXD_P_OUT,
- SFP_TXD_N_OUT => SFP_TXD_N_OUT,
- SFP_REFCLK_P_IN => SFP_REFCLK_P_IN,
- SFP_REFCLK_N_IN => SFP_REFCLK_N_IN,
- SFP_PRSNT_N_IN => SFP_PRSNT_N_IN,
- SFP_LOS_IN => SFP_LOS_IN,
- SFP_TXDIS_OUT => SFP_TXDIS_OUT,
- ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT
- );
-
-
-
--- 100 MHz system clock
-CLOCK_GEN_PROC: process
-begin
- clk <= '1'; wait for 5.0 ns;
- clk <= '0'; wait for 5.0 ns;
-end process CLOCK_GEN_PROC;
-
--- 125 MHz MAC clock
-CLOCK2_GEN_PROC: process
-begin
- test_clk <= '1'; wait for 4.0 ns;
- test_clk <= '0'; wait for 3.0 ns;
-end process CLOCK2_GEN_PROC;
-
--- Testbench
-TESTBENCH_PROC: process
--- test data from TRBnet
-variable test_data_len : integer range 0 to 65535 := 1;
-variable test_loop_len : integer range 0 to 65535 := 0;
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";
-variable test_evt_len : unsigned(15 downto 0) := x"0000";
-variable test_data : unsigned(15 downto 0) := x"ffff";
-
-variable trigger_counter : unsigned(15 downto 0) := x"4710";
-variable trigger_loop : integer range 0 to 65535 := 15;
-
--- 1400 bytes MTU => 350 as limit for fragmentation
-variable max_event_size : real := 512.0;
-
-variable seed1 : positive; -- seed for random generator
-variable seed2 : positive; -- seed for random generator
-variable rand : real; -- random value (0.0 ... 1.0)
-variable int_rand : integer; -- random value, scaled to your needs
-variable cts_random_number : std_logic_vector(7 downto 0);
-
-variable stim : std_logic_vector(15 downto 0);
-
-
--- RND test
---UNIFORM(seed1, seed2, rand);
---int_rand := INTEGER(TRUNC(rand*65536.0));
---stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
-
-begin
- -- Setup signals
- reset <= '0';
- gsr_n <= '1';
-
- stage_ctrl_regs_in <= x"0000_0000";
-
- --ip_cfg_start_in <= '0';
- --ip_cfg_bank_sel_in <= x"0";
- --ip_cfg_mem_data_in <= x"0000_0000";
- mr_reset_in <= '0';
- mr_mode_in <= '0';
- mr_restart_in <= '0';
- SLV_ADDR_IN <= x"00";
- SLV_READ_IN <= '0';
- SLV_WRITE_IN <= '0';
- SLV_DATA_IN <= x"0000_0000";
-
- sfp_los_in <= '0'; -- signal from SFP is present
- sfp_prsnt_n_in <= '0'; -- SFP itself is present
- sfp_refclk_n_in <= '0';
- sfp_refclk_p_in <= '1';
-
- cts_number_in <= x"0000";
- cts_code_in <= x"00";
- cts_information_in <= x"00";
- cts_readout_type_in <= x"0";
- cts_start_readout_in <= '0';
- cts_read_in <= '0';
-
- fee_data_in <= x"0000";
- fee_dataready_in <= '0';
- fee_status_bits_in <= x"1234_5678";
- fee_busy_in <= '0';
-
- wait for 22 ns;
-
- -- Reset the whole stuff
- wait until rising_edge(clk);
- reset <= '1';
- gsr_n <= '0';
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- reset <= '0';
- gsr_n <= '1';
- wait until rising_edge(clk);
- --wait for 100 ns;
-
- -- Tests may start here
- wait until ft_bsm_init_tst = x"7";
-
- --ip_cfg_start_in <= '1';
-
- wait for 500 ns;
-
-
--------------------------------------------------------------------------------
--- Loop the transmissions
--------------------------------------------------------------------------------
- trigger_counter := x"4710";
- trigger_loop := 10;
-
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop
- -- generate a real random byte for CTS
- UNIFORM(seed1, seed2, rand);
- int_rand := INTEGER(TRUNC(rand*256.0));
- cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));
-
- -- IPU transmission starts
- wait until rising_edge(clk);
- cts_number_in <= std_logic_vector( trigger_counter );
- cts_code_in <= cts_random_number;
- cts_information_in <= x"d2"; -- cts_information_in <= x"de"; -- gk 29.03.10
- cts_readout_type_in <= x"1";
- cts_start_readout_in <= '1';
- wait until rising_edge(clk);
- wait for 400 ns;
-
- wait until rising_edge(clk);
- fee_busy_in <= '1';
- wait for 300 ns;
- wait until rising_edge(clk);
-
- -- ONE DATA TRANSMISSION
- -- dice a length
- UNIFORM(seed1, seed2, rand);
- test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;
-
- test_data_len := 9685;
- --test_data_len := 400;
-
- -- calculate the needed variables
- test_loop_len := 2*(test_data_len - 1) + 1;
- test_hdr_len := to_unsigned( test_data_len + 1, 16 );
- test_evt_len := to_unsigned( test_data_len, 16 );
-
- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)
- fee_dataready_in <= '1';
- fee_data_in <= x"10" & cts_random_number;
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word
- fee_dataready_in <= '0';
- wait until rising_edge(clk); -- BLA
- wait until rising_edge(clk); -- BLA
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- fee_dataready_in <= '1';
- fee_data_in <= std_logic_vector( trigger_counter );
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word
- fee_dataready_in <= '0';
- wait until rising_edge(clk); -- BLA
- wait until rising_edge(clk); -- BLA
- wait until rising_edge(clk); -- BLA
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- fee_dataready_in <= '1';
- fee_data_in <= std_logic_vector( test_hdr_len );
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word
- fee_data_in <= x"ff21";
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word
- fee_dataready_in <= '0';
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- fee_dataready_in <= '1';
- fee_data_in <= std_logic_vector( test_evt_len );
- wait until rising_edge(clk) and (fee_read_out = '1');
- fee_data_in <= x"ff22";
- wait until rising_edge(clk) and (fee_read_out = '1');
- fee_dataready_in <= '0';
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
-
- test_data := x"ffff";
- MY_DATA_LOOP: for J in 0 to test_loop_len loop
- test_data := test_data + 1;
- wait until rising_edge(clk);
- fee_data_in <= std_logic_vector(test_data);
- if( (test_data MOD 5) = 0 ) then
- fee_dataready_in <= '0';
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- fee_dataready_in <= '1';
- else
- fee_dataready_in <= '1';
- end if;
- --fee_dataready_in <= '1';
- end loop MY_DATA_LOOP;
- -- there must be padding words to get multiple of four LWs
-
- wait until rising_edge(clk);
- fee_dataready_in <= '0';
- fee_data_in <= x"0000";
-
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- fee_busy_in <= '0';
-
-
- trigger_loop := trigger_loop + 1;
- trigger_counter := trigger_counter + 1;
-
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- cts_read_in <= '1';
- wait until rising_edge(clk);
- cts_read_in <= '0';
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- cts_start_readout_in <= '0';
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
- wait until rising_edge(clk);
-
- --wait for 8 us;
-
- end loop MY_TRIGGER_LOOP;
-
--- wait for 8 us;
--------------------------------------------------------------------------------
--- end of loop
--------------------------------------------------------------------------------
- -- Stay a while... stay forever!!!
- wait;
-
-end process TESTBENCH_PROC;
-
-END;
-
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT ip_configurator\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- START_CONFIG_IN : IN std_logic;\r
- BANK_SELECT_IN : IN std_logic_vector(3 downto 0);\r
- MEM_DATA_IN : IN std_logic_vector(31 downto 0); \r
- CONFIG_DONE_OUT : OUT std_logic;\r
- MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0);\r
- MEM_CLK_OUT : OUT std_logic;\r
- DEST_MAC_OUT : OUT std_logic_vector(47 downto 0);\r
- DEST_IP_OUT : OUT std_logic_vector(31 downto 0);\r
- DEST_UDP_OUT : OUT std_logic_vector(15 downto 0);\r
- SRC_MAC_OUT : OUT std_logic_vector(47 downto 0);\r
- SRC_IP_OUT : OUT std_logic_vector(31 downto 0);\r
- SRC_UDP_OUT : OUT std_logic_vector(15 downto 0);\r
- MTU_OUT : OUT std_logic_vector(15 downto 0);\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL START_CONFIG_IN : std_logic;\r
- SIGNAL BANK_SELECT_IN : std_logic_vector(3 downto 0);\r
- SIGNAL CONFIG_DONE_OUT : std_logic;\r
- SIGNAL MEM_ADDR_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL MEM_DATA_IN : std_logic_vector(31 downto 0);\r
- SIGNAL MEM_CLK_OUT : std_logic;\r
- SIGNAL DEST_MAC_OUT : std_logic_vector(47 downto 0);\r
- SIGNAL DEST_IP_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL DEST_UDP_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL SRC_MAC_OUT : std_logic_vector(47 downto 0);\r
- SIGNAL SRC_IP_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL SRC_UDP_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL MTU_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: ip_configurator PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- START_CONFIG_IN => START_CONFIG_IN,\r
- BANK_SELECT_IN => BANK_SELECT_IN,\r
- CONFIG_DONE_OUT => CONFIG_DONE_OUT,\r
- MEM_ADDR_OUT => MEM_ADDR_OUT,\r
- MEM_DATA_IN => MEM_DATA_IN,\r
- MEM_CLK_OUT => MEM_CLK_OUT,\r
- DEST_MAC_OUT => DEST_MAC_OUT,\r
- DEST_IP_OUT => DEST_IP_OUT,\r
- DEST_UDP_OUT => DEST_UDP_OUT,\r
- SRC_MAC_OUT => SRC_MAC_OUT,\r
- SRC_IP_OUT => SRC_IP_OUT,\r
- SRC_UDP_OUT => SRC_UDP_OUT,\r
- MTU_OUT => MTU_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
-\r
-\r
-CLK_GEN_PROC: process\r
-begin\r
- clk <= '0'; wait for 5.0 ns;\r
- clk <= '1'; wait for 5.0 ns;\r
-end process CLK_GEN_PROC;\r
-\r
-THE_TESTBENCH: process\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- start_config_in <= '0';\r
- bank_select_in <= x"0";\r
- mem_data_in <= x"0000_0000";\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait for 100 ns;\r
- wait until rising_edge(clk);\r
- \r
- -- Tests may start now\r
- wait until rising_edge(clk);\r
- start_config_in <= '1';\r
- wait until mem_addr_out(3 downto 0) = x"1";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"4902d745"; -- dest MAC low\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"00006cf0"; -- dest MAC high\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"c0a80002"; -- dest IP\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"0000c350"; -- dest port\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"eeeeeeee"; -- src MAC low\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"0000eeee"; -- src MAC high\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"c0a80005"; -- src IP\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"0000c350"; -- src port\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"00000578"; -- MTU\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"99999999";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"aaaaaaaa";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"bbbbbbbb";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"cccccccc";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"dddddddd";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"eeeeeeee";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"ffffffff";\r
- wait until rising_edge(clk);\r
- mem_data_in <= x"00000000";\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- start_config_in <= '0';\r
- \r
- -- Stay a while... stay forever!!! Muahahaha!!!!!\r
- wait;\r
-end process THE_TESTBENCH;\r
-\r
-\r
-END;\r
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.math_real.all;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT trb_net16_ipu2gbe\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- START_CONFIG_OUT : OUT std_logic;\r
- BANK_SELECT_OUT : OUT std_logic_vector(3 downto 0);\r
- CONFIG_DONE_IN : IN std_logic;\r
- DATA_GBE_ENABLE_IN : IN std_logic;\r
- DATA_IPU_ENABLE_IN : IN std_logic;\r
- MULTI_EVT_ENABLE_IN : IN std_logic;\r
- CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
- CTS_CODE_IN : IN std_logic_vector(7 downto 0);\r
- CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
- CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);\r
- CTS_START_READOUT_IN : IN std_logic;\r
- CTS_READ_IN : IN std_logic;\r
- FEE_DATA_IN : IN std_logic_vector(15 downto 0);\r
- FEE_DATAREADY_IN : IN std_logic;\r
- FEE_BUSY_IN : IN std_logic;\r
- FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);\r
- PC_READY_IN : IN std_logic; \r
- CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- CTS_DATAREADY_OUT : OUT std_logic;\r
- CTS_READOUT_FINISHED_OUT : OUT std_logic;\r
- CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
- CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
- FEE_READ_OUT : OUT std_logic;\r
- PC_WR_EN_OUT : OUT std_logic;\r
- PC_DATA_OUT : OUT std_logic_vector(7 downto 0);\r
- PC_SOS_OUT : OUT std_logic;\r
- PC_EOD_OUT : OUT std_logic;\r
- PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0);\r
- PC_PADDING_OUT : OUT std_logic;\r
- BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0);\r
- BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0);\r
- DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0);\r
- DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0);\r
- DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
- DBG_SF_RD_EN_OUT : OUT std_logic;\r
- DBG_SF_WR_EN_OUT : OUT std_logic;\r
- DBG_SF_EMPTY_OUT : OUT std_logic;\r
- DBG_SF_AEMPTY_OUT : OUT std_logic;\r
- DBG_SF_FULL_OUT : OUT std_logic;\r
- DBG_SF_AFULL_OUT : OUT std_logic;\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL START_CONFIG_OUT : std_logic;\r
- SIGNAL BANK_SELECT_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL CONFIG_DONE_IN : std_logic;\r
- SIGNAL DATA_GBE_ENABLE_IN : std_logic;\r
- SIGNAL DATA_IPU_ENABLE_IN : std_logic;\r
- SIGNAL MULTI_EVT_ENABLE_IN : std_logic;\r
- SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);\r
- SIGNAL CTS_START_READOUT_IN : std_logic;\r
- SIGNAL CTS_READ_IN : std_logic;\r
- SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL CTS_DATAREADY_OUT : std_logic;\r
- SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;\r
- SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);\r
- SIGNAL FEE_DATAREADY_IN : std_logic;\r
- SIGNAL FEE_READ_OUT : std_logic;\r
- SIGNAL FEE_BUSY_IN : std_logic;\r
- SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);\r
- SIGNAL PC_WR_EN_OUT : std_logic;\r
- SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL PC_READY_IN : std_logic;\r
- SIGNAL PC_SOS_OUT : std_logic;\r
- SIGNAL PC_EOD_OUT : std_logic;\r
- SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL PC_PADDING_OUT : std_logic;\r
- SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0);\r
- SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0);\r
- SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SF_RD_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_WR_EN_OUT : std_logic;\r
- SIGNAL DBG_SF_EMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_AEMPTY_OUT : std_logic;\r
- SIGNAL DBG_SF_FULL_OUT : std_logic;\r
- SIGNAL DBG_SF_AFULL_OUT : std_logic;\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: trb_net16_ipu2gbe PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- START_CONFIG_OUT => START_CONFIG_OUT,\r
- BANK_SELECT_OUT => BANK_SELECT_OUT,\r
- CONFIG_DONE_IN => CONFIG_DONE_IN,\r
- DATA_GBE_ENABLE_IN => DATA_GBE_ENABLE_IN,\r
- DATA_IPU_ENABLE_IN => DATA_IPU_ENABLE_IN,\r
- MULTI_EVT_ENABLE_IN => MULTI_EVT_ENABLE_IN,\r
- CTS_NUMBER_IN => CTS_NUMBER_IN,\r
- CTS_CODE_IN => CTS_CODE_IN,\r
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,\r
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,\r
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,\r
- CTS_READ_IN => CTS_READ_IN,\r
- CTS_DATA_OUT => CTS_DATA_OUT,\r
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,\r
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,\r
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,\r
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,\r
- FEE_DATA_IN => FEE_DATA_IN,\r
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,\r
- FEE_READ_OUT => FEE_READ_OUT,\r
- FEE_BUSY_IN => FEE_BUSY_IN,\r
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,\r
- PC_WR_EN_OUT => PC_WR_EN_OUT,\r
- PC_DATA_OUT => PC_DATA_OUT,\r
- PC_READY_IN => PC_READY_IN,\r
- PC_SOS_OUT => PC_SOS_OUT,\r
- PC_EOD_OUT => PC_EOD_OUT,\r
- PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT,\r
- PC_TRIG_NR_OUT => PC_TRIG_NR_OUT,\r
- PC_PADDING_OUT => PC_PADDING_OUT,\r
- BSM_SAVE_OUT => BSM_SAVE_OUT,\r
- BSM_LOAD_OUT => BSM_LOAD_OUT,\r
- DBG_REM_CTR_OUT => DBG_REM_CTR_OUT,\r
- DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT,\r
- DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT,\r
- DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT,\r
- DBG_SF_DATA_OUT => DBG_SF_DATA_OUT,\r
- DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT,\r
- DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT,\r
- DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT,\r
- DBG_SF_AEMPTY_OUT => DBG_SF_AEMPTY_OUT,\r
- DBG_SF_FULL_OUT => DBG_SF_FULL_OUT,\r
- DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
-\r
-CLOCK_GEN: process\r
-begin\r
- clk <= '1'; wait for 5.0 ns;\r
- clk <= '0'; wait for 5.0 ns;\r
-end process CLOCK_GEN;\r
-\r
-PC_READY_PROC: process\r
-begin\r
- pc_ready_in <= '0';\r
- wait for 500 ns;\r
- pc_ready_in <= '1';\r
- wait for 500 ns;\r
- pc_ready_in <= '0';\r
- wait for 99 us;\r
-end process PC_READY_PROC;\r
-\r
--- Testbench\r
-TESTBENCH_PROC: process\r
--- test data from TRBnet\r
-variable test_data_len : integer range 0 to 65535 := 1;\r
-variable test_loop_len : integer range 0 to 65535 := 0;\r
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";\r
-variable test_evt_len : unsigned(15 downto 0) := x"0000";\r
-variable test_data : unsigned(15 downto 0) := x"ffff";\r
-\r
-variable trigger_counter : unsigned(15 downto 0) := x"4710";\r
-variable trigger_loop : integer range 0 to 65535 := 15;\r
-\r
--- 1400 bytes MTU => 350 as limit for fragmentation\r
---variable max_event_size : real := 512.0;\r
-variable max_event_size : real := 17.0;\r
-\r
-variable seed1 : positive; -- seed for random generator\r
-variable seed2 : positive; -- seed for random generator\r
-variable rand : real; -- random value (0.0 ... 1.0)\r
-variable int_rand : integer; -- random value, scaled to your needs\r
-variable cts_random_number : std_logic_vector(7 downto 0);\r
-\r
-variable stim : std_logic_vector(15 downto 0);\r
-\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- cts_number_in <= x"0000";\r
- cts_code_in <= x"00";\r
- cts_information_in <= x"00";\r
- cts_readout_type_in <= x"0";\r
- cts_start_readout_in <= '0';\r
- cts_read_in <= '0';\r
- fee_data_in <= x"0000";\r
- fee_dataready_in <= '0';\r
- fee_status_bits_in <= x"0000_0000";\r
- fee_busy_in <= '0';\r
--- pc_ready_in <= '0';\r
-\r
- config_done_in <= '1';\r
- data_gbe_enable_in <= '1';\r
- data_ipu_enable_in <= '0';\r
- multi_evt_enable_in <= '0';\r
-\r
- wait for 22 ns;\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- wait for 200 ns;\r
-\r
----------------------------\r
-\r
--------------------------------------------------------------------------------\r
--- Loop the transmissions\r
--------------------------------------------------------------------------------\r
- trigger_counter := x"4710";\r
- trigger_loop := 2;\r
-\r
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop\r
- -- generate a real random byte for CTS\r
- UNIFORM(seed1, seed2, rand);\r
- int_rand := INTEGER(TRUNC(rand*256.0));\r
- cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));\r
- \r
- -- IPU transmission starts\r
- wait until rising_edge(clk);\r
- cts_number_in <= std_logic_vector( trigger_counter );\r
- cts_code_in <= cts_random_number;\r
- cts_information_in <= x"de";\r
- cts_readout_type_in <= x"1";\r
- cts_start_readout_in <= '1';\r
- wait until rising_edge(clk);\r
- wait for 400 ns;\r
-\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '1';\r
- wait for 300 ns;\r
- wait until rising_edge(clk);\r
-\r
- -- ONE DATA TRANSMISSION\r
- -- dice a length\r
- UNIFORM(seed1, seed2, rand);\r
- test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;\r
- \r
--- test_data_len := 9685;\r
- \r
- -- calculate the needed variables\r
- test_loop_len := 2*(test_data_len - 1) + 1;\r
- test_hdr_len := to_unsigned( test_data_len + 1, 16 );\r
- test_evt_len := to_unsigned( test_data_len, 16 );\r
-\r
- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)\r
- fee_dataready_in <= '1';\r
- fee_data_in <= x"10" & cts_random_number;\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( trigger_counter );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_hdr_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word\r
- fee_data_in <= x"ff21";\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_evt_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_data_in <= x"ff22"; \r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- test_data := x"ffff";\r
- MY_DATA_LOOP: for J in 0 to test_loop_len loop\r
- test_data := test_data + 1;\r
- wait until rising_edge(clk) and (fee_read_out = '1'); --\r
- fee_data_in <= std_logic_vector(test_data); \r
- if( (test_data MOD 5) = 0 ) then\r
- fee_dataready_in <= '0';\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- else\r
- fee_dataready_in <= '1';\r
- end if;\r
- end loop MY_DATA_LOOP;\r
- -- there must be padding words to get multiple of four LWs\r
- \r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '0';\r
- fee_data_in <= x"0000"; \r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '0';\r
-\r
-\r
- trigger_loop := trigger_loop + 1;\r
- trigger_counter := trigger_counter + 1;\r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_read_in <= '1';\r
- wait until rising_edge(clk);\r
- cts_read_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_start_readout_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk); \r
- \r
- --wait for 8 us;\r
-\r
- end loop MY_TRIGGER_LOOP;\r
-\r
-\r
-\r
----------------------------\r
----------------------------\r
- wait for 300 ns;\r
-\r
- wait;\r
-\r
- -- Start packet_constructor\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
--- pc_ready_in <= '1';\r
- wait until rising_edge(clk);\r
-\r
- wait until rising_edge(clk);\r
- wait until pc_eod_out = '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
--- pc_ready_in <= '0';\r
-\r
- -- Stay a while... stay forever!!!\r
- wait; \r
- \r
-end process TESTBENCH_PROC;\r
-\r
-\r
-END;\r
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT trb_net16_lsm_sfp_gbe\r
- PORT(\r
- SYSCLK : IN std_logic;\r
- RESET : IN std_logic;\r
- CLEAR : IN std_logic;\r
- SFP_MISSING_IN : IN std_logic;\r
- SFP_LOS_IN : IN std_logic;\r
- SD_LINK_OK_IN : IN std_logic;\r
- SD_LOS_IN : IN std_logic;\r
- SD_TXCLK_BAD_IN : IN std_logic;\r
- SD_RXCLK_BAD_IN : IN std_logic; \r
- FULL_RESET_OUT : OUT std_logic;\r
- LANE_RESET_OUT : OUT std_logic;\r
- USER_RESET_OUT : OUT std_logic;\r
- TIMING_CTR_OUT : OUT std_logic_vector(18 downto 0);\r
- BSM_OUT : OUT std_logic_vector(3 downto 0);\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL SYSCLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL CLEAR : std_logic;\r
- SIGNAL SFP_MISSING_IN : std_logic;\r
- SIGNAL SFP_LOS_IN : std_logic;\r
- SIGNAL SD_LINK_OK_IN : std_logic;\r
- SIGNAL SD_LOS_IN : std_logic;\r
- SIGNAL SD_TXCLK_BAD_IN : std_logic;\r
- SIGNAL SD_RXCLK_BAD_IN : std_logic;\r
- SIGNAL FULL_RESET_OUT : std_logic;\r
- SIGNAL LANE_RESET_OUT : std_logic;\r
- SIGNAL USER_RESET_OUT : std_logic;\r
- SIGNAL TIMING_CTR_OUT : std_logic_vector(18 downto 0);\r
- SIGNAL BSM_OUT : std_logic_vector(3 downto 0);\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: trb_net16_lsm_sfp_gbe PORT MAP(\r
- SYSCLK => SYSCLK,\r
- RESET => RESET,\r
- CLEAR => CLEAR,\r
- SFP_MISSING_IN => SFP_MISSING_IN,\r
- SFP_LOS_IN => SFP_LOS_IN,\r
- SD_LINK_OK_IN => SD_LINK_OK_IN,\r
- SD_LOS_IN => SD_LOS_IN,\r
- SD_TXCLK_BAD_IN => SD_TXCLK_BAD_IN,\r
- SD_RXCLK_BAD_IN => SD_RXCLK_BAD_IN,\r
- FULL_RESET_OUT => FULL_RESET_OUT,\r
- LANE_RESET_OUT => LANE_RESET_OUT,\r
- USER_RESET_OUT => USER_RESET_OUT,\r
- TIMING_CTR_OUT => TIMING_CTR_OUT,\r
- BSM_OUT => BSM_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
- \r
-\r
-CLOCK_GEN: process\r
-begin\r
- sysclk <= '1'; wait for 4.0 ns;\r
- sysclk <= '0'; wait for 4.0 ns;\r
-end process CLOCK_GEN;\r
-\r
-THE_TESTBENCH: process\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- clear <= '0';\r
- sfp_missing_in <= '0';\r
- sfp_los_in <= '0';\r
- sd_link_ok_in <= '0';\r
- sd_los_in <= '0';\r
- sd_txclk_bad_in <= '1';\r
- sd_rxclk_bad_in <= '1';\r
- wait for 100 ns;\r
- \r
- -- Reset\r
- clear <= '1';\r
- wait for 100 ns;\r
- clear <= '0';\r
- wait for 10 ns;\r
- \r
- -- Tests may start now\r
- wait until falling_edge(full_reset_out);\r
- wait for 123 ns;\r
- sd_txclk_bad_in <= '0';\r
- wait for 433 ns;\r
- sd_rxclk_bad_in <= '0';\r
-\r
- wait for 1.1 us;\r
- sd_rxclk_bad_in <= '1';\r
- wait for 33 ns;\r
- sd_rxclk_bad_in <= '0';\r
-\r
- \r
- wait until rising_edge(sysclk); \r
- \r
- -- Stay a while.... stay forever!!! Muahahaha!!!!\r
- wait;\r
-\r
-end process THE_TESTBENCH;\r
- \r
-END;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee; \r
-USE ieee.std_logic_1164.ALL; \r
-USE ieee.numeric_std.ALL; \r
- \r
-ENTITY testbench IS \r
-END testbench; \r
- \r
-ARCHITECTURE behavior OF testbench IS \r
- \r
- COMPONENT trb_net16_gbe_packet_constr \r
- PORT( \r
- RESET : IN std_logic; \r
- CLK : IN std_logic; \r
- PC_WR_EN_IN : IN std_logic; \r
- PC_DATA_IN : IN std_logic_vector(7 downto 0); \r
- PC_START_OF_SUB_IN : IN std_logic; \r
- PC_END_OF_DATA_IN : IN std_logic; \r
- PC_SUB_SIZE_IN : IN std_logic_vector(31 downto 0); \r
- PC_DECODING_IN : IN std_logic_vector(31 downto 0); \r
- PC_EVENT_ID_IN : IN std_logic_vector(31 downto 0); \r
- PC_TRIG_NR_IN : IN std_logic_vector(31 downto 0); \r
- PC_QUEUE_DEC_IN : IN std_logic_vector(31 downto 0); \r
- PC_MAX_FRAME_SIZE_IN : IN std_logic_vector(15 downto 0);\r
- FC_H_READY_IN : IN std_logic; \r
- FC_READY_IN : IN std_logic; \r
- PC_READY_OUT : OUT std_logic; \r
- FC_WR_EN_OUT : OUT std_logic; \r
- FC_DATA_OUT : OUT std_logic_vector(7 downto 0); \r
- FC_IP_SIZE_OUT : OUT std_logic_vector(15 downto 0); \r
- FC_UDP_SIZE_OUT : OUT std_logic_vector(15 downto 0); \r
- FC_IDENT_OUT : OUT std_logic_vector(15 downto 0); \r
- FC_FLAGS_OFFSET_OUT : OUT std_logic_vector(15 downto 0);\r
- FC_SOD_OUT : OUT std_logic; \r
- FC_EOD_OUT : OUT std_logic; \r
- BSM_CONSTR_OUT : OUT std_logic_vector(3 downto 0); \r
- BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); \r
- BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); \r
- DBG_SHF_EMPTY : OUT std_logic;\r
- DBG_SHF_FULL : OUT std_logic;\r
- DBG_SHF_WR_EN : OUT std_logic;\r
- DBG_SHF_RD_EN : OUT std_logic;\r
- DBG_DF_EMPTY : OUT std_logic;\r
- DBG_DF_FULL : OUT std_logic;\r
- DBG_DF_WR_EN : OUT std_logic;\r
- DBG_DF_RD_EN : OUT std_logic;\r
- DBG_ALL_CTR : OUT std_logic_vector(4 downto 0);\r
- DBG_SUB_CTR : OUT std_logic_vector(4 downto 0);\r
- DBG_MY_CTR : OUT std_logic_vector(1 downto 0);\r
- DBG_BYTES_LOADED : OUT std_logic_vector(15 downto 0);\r
- DBG_SIZE_LEFT : OUT std_logic_vector(31 downto 0);\r
- DBG_SUB_SIZE_TO_SAVE : OUT std_logic_vector(31 downto 0);\r
- DBG_SUB_SIZE_LOADED : OUT std_logic_vector(31 downto 0);\r
- DBG_SUB_BYTES_LOADED : OUT std_logic_vector(31 downto 0);\r
- DBG_QUEUE_SIZE : OUT std_logic_vector(31 downto 0);\r
- DBG_ACT_QUEUE_SIZE : OUT std_logic_vector(31 downto 0);\r
- DEBUG_OUT : OUT std_logic_vector(31 downto 0) \r
- ); \r
- END COMPONENT; \r
-\r
- SIGNAL RESET : std_logic; \r
- SIGNAL CLK : std_logic; \r
- SIGNAL PC_WR_EN_IN : std_logic; \r
- SIGNAL PC_DATA_IN : std_logic_vector(7 downto 0); \r
- SIGNAL PC_READY_OUT : std_logic; \r
- SIGNAL PC_START_OF_SUB_IN : std_logic; \r
- SIGNAL PC_END_OF_DATA_IN : std_logic; \r
- SIGNAL PC_SUB_SIZE_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_DECODING_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_EVENT_ID_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_TRIG_NR_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_QUEUE_DEC_IN : std_logic_vector(31 downto 0); \r
- SIGNAL PC_MAX_FRAME_SIZE_IN : std_logic_vector(15 downto 0);\r
- SIGNAL FC_WR_EN_OUT : std_logic; \r
- SIGNAL FC_DATA_OUT : std_logic_vector(7 downto 0); \r
- SIGNAL FC_H_READY_IN : std_logic; \r
- SIGNAL FC_READY_IN : std_logic; \r
- SIGNAL FC_IP_SIZE_OUT : std_logic_vector(15 downto 0); \r
- SIGNAL FC_UDP_SIZE_OUT : std_logic_vector(15 downto 0); \r
- SIGNAL FC_IDENT_OUT : std_logic_vector(15 downto 0); \r
- SIGNAL FC_FLAGS_OFFSET_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL FC_SOD_OUT : std_logic; \r
- SIGNAL FC_EOD_OUT : std_logic; \r
- SIGNAL BSM_CONSTR_OUT : std_logic_vector(3 downto 0); \r
- SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); \r
- SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); \r
- SIGNAL DBG_SHF_EMPTY : std_logic;\r
- SIGNAL DBG_SHF_FULL : std_logic;\r
- SIGNAL DBG_SHF_WR_EN : std_logic;\r
- SIGNAL DBG_SHF_RD_EN : std_logic;\r
- SIGNAL DBG_DF_EMPTY : std_logic;\r
- SIGNAL DBG_DF_FULL : std_logic;\r
- SIGNAL DBG_DF_WR_EN : std_logic;\r
- SIGNAL DBG_DF_RD_EN : std_logic;\r
- SIGNAL DBG_ALL_CTR : std_logic_vector(4 downto 0);\r
- SIGNAL DBG_SUB_CTR : std_logic_vector(4 downto 0);\r
- SIGNAL DBG_MY_CTR : std_logic_vector(1 downto 0);\r
- SIGNAL DBG_BYTES_LOADED : std_logic_vector(15 downto 0);\r
- SIGNAL DBG_SIZE_LEFT : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_SUB_SIZE_TO_SAVE : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_SUB_SIZE_LOADED : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_SUB_BYTES_LOADED : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_QUEUE_SIZE : std_logic_vector(31 downto 0);\r
- SIGNAL DBG_ACT_QUEUE_SIZE : std_logic_vector(31 downto 0);\r
- SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); \r
- \r
-BEGIN \r
- \r
--- Please check and add your generic clause manually \r
- uut: trb_net16_gbe_packet_constr PORT MAP( \r
- RESET => RESET, \r
- CLK => CLK, \r
- PC_WR_EN_IN => PC_WR_EN_IN, \r
- PC_DATA_IN => PC_DATA_IN, \r
- PC_READY_OUT => PC_READY_OUT, \r
- PC_START_OF_SUB_IN => PC_START_OF_SUB_IN, \r
- PC_END_OF_DATA_IN => PC_END_OF_DATA_IN, \r
- PC_SUB_SIZE_IN => PC_SUB_SIZE_IN, \r
- PC_DECODING_IN => PC_DECODING_IN, \r
- PC_EVENT_ID_IN => PC_EVENT_ID_IN, \r
- PC_TRIG_NR_IN => PC_TRIG_NR_IN, \r
- PC_QUEUE_DEC_IN => PC_QUEUE_DEC_IN,\r
- PC_MAX_FRAME_SIZE_IN => PC_MAX_FRAME_SIZE_IN, \r
- FC_WR_EN_OUT => FC_WR_EN_OUT, \r
- FC_DATA_OUT => FC_DATA_OUT, \r
- FC_H_READY_IN => FC_H_READY_IN, \r
- FC_READY_IN => FC_READY_IN, \r
- FC_IP_SIZE_OUT => FC_IP_SIZE_OUT, \r
- FC_UDP_SIZE_OUT => FC_UDP_SIZE_OUT, \r
- FC_IDENT_OUT => FC_IDENT_OUT, \r
- FC_FLAGS_OFFSET_OUT => FC_FLAGS_OFFSET_OUT, \r
- FC_SOD_OUT => FC_SOD_OUT, \r
- FC_EOD_OUT => FC_EOD_OUT, \r
- BSM_CONSTR_OUT => BSM_CONSTR_OUT, \r
- BSM_LOAD_OUT => BSM_LOAD_OUT, \r
- BSM_SAVE_OUT => BSM_SAVE_OUT, \r
- DBG_SHF_EMPTY => DBG_SHF_EMPTY,\r
- DBG_SHF_FULL => DBG_SHF_FULL,\r
- DBG_SHF_WR_EN => DBG_SHF_WR_EN,\r
- DBG_SHF_RD_EN => DBG_SHF_RD_EN,\r
- DBG_DF_EMPTY => DBG_DF_EMPTY,\r
- DBG_DF_FULL => DBG_DF_FULL,\r
- DBG_DF_WR_EN => DBG_DF_WR_EN,\r
- DBG_DF_RD_EN => DBG_DF_RD_EN,\r
- DBG_ALL_CTR => DBG_ALL_CTR,\r
- DBG_SUB_CTR => DBG_SUB_CTR,\r
- DBG_MY_CTR => DBG_MY_CTR,\r
- DBG_BYTES_LOADED => DBG_BYTES_LOADED, \r
- DBG_SIZE_LEFT => DBG_SIZE_LEFT, \r
- DBG_SUB_SIZE_TO_SAVE => DBG_SUB_SIZE_TO_SAVE,\r
- DBG_SUB_SIZE_LOADED => DBG_SUB_SIZE_LOADED,\r
- DBG_SUB_BYTES_LOADED => DBG_SUB_BYTES_LOADED,\r
- DBG_QUEUE_SIZE => DBG_QUEUE_SIZE,\r
- DBG_ACT_QUEUE_SIZE => DBG_ACT_QUEUE_SIZE,\r
- DEBUG_OUT => DEBUG_OUT\r
- ); \r
- \r
-CLK_GEN: process\r
-begin\r
- clk <= '1'; wait for 5.0 ns;\r
- clk <= '0'; wait for 5.0 ns;\r
-end process CLK_GEN;\r
-\r
-THE_TESTBENCH: process\r
-variable test_data_len : integer range 0 to 65535 := 1;\r
-variable test_loop_len : integer range 0 to 65535 := 0;\r
-variable test_evt_len : unsigned(15 downto 0) := x"0000";\r
-variable test_evt_len_vec : std_logic_vector(15 downto 0);\r
-variable test_sub_len : unsigned(15 downto 0) := x"0000";\r
-variable test_sub_len_vec : std_logic_vector(15 downto 0);\r
-variable test_data : unsigned(15 downto 0) := x"ffff";\r
-variable test_data_vec : std_logic_vector(15 downto 0);\r
-\r
-variable trigger_counter : unsigned(15 downto 0) := x"4710";\r
-variable trigger_loop : integer range 0 to 65535 := 15;\r
-begin\r
- -- Set up signals\r
- reset <= '0';\r
- pc_wr_en_in <= '0';\r
- pc_data_in <= x"00";\r
- pc_start_of_sub_in <= '0';\r
- pc_end_of_data_in <= '0';\r
- pc_sub_size_in <= x"0000_0000";\r
- pc_trig_nr_in <= x"0000_0000";\r
- pc_decoding_in <= x"0002_0001"; -- static\r
- pc_event_id_in <= x"0000_00ca"; -- static\r
- pc_queue_dec_in <= x"0003_0062"; -- static\r
- pc_max_frame_size_in <= x"0578"; -- static\r
- fc_h_ready_in <= '0';\r
- fc_ready_in <= '0';\r
- wait until rising_edge(clk);\r
-\r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- wait for 200 ns;\r
- wait until rising_edge(clk);\r
- \r
- -- Tests may start now\r
-\r
--------------------------------------------------------------------------------\r
--- Loop the transmissions\r
--------------------------------------------------------------------------------\r
- trigger_counter := x"4710";\r
- trigger_loop := 0;\r
-\r
- test_data_len := 14;\r
-\r
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop\r
-\r
- -- calculate the needed variables\r
- test_loop_len := 2*(test_data_len - 1) + 1;\r
- test_evt_len := to_unsigned( test_data_len, 16 );\r
- test_evt_len_vec := std_logic_vector(test_evt_len);\r
- test_sub_len := test_evt_len + 1;\r
- test_sub_len_vec := std_logic_vector(test_sub_len);\r
-\r
- -- start of subevent marker\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_trig_nr_in <= x"0000" & std_logic_vector(trigger_counter);\r
- pc_sub_size_in <= b"0000_0000_0000_00" & test_sub_len_vec & b"00";\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_start_of_sub_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_start_of_sub_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_data_in <= test_evt_len_vec(15 downto 8);\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_data_in <= test_evt_len_vec(7 downto 0);\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_wr_en_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- pc_data_in <= x"ff"; -- source address high byte\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_data_in <= x"22"; -- source address low byte\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_wr_en_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- \r
- test_data := x"ffff";\r
- MY_DATA_LOOP: for J in 0 to test_loop_len loop\r
- test_data := test_data + 1;\r
- test_data_vec := std_logic_vector(test_data);\r
- wait until rising_edge(clk);\r
- pc_data_in <= test_data_vec(15 downto 8);\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_data_in <= test_data_vec(7 downto 0);\r
- pc_wr_en_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_wr_en_in <= '0';\r
--- wait until rising_edge(clk);\r
--- wait until rising_edge(clk); \r
- end loop MY_DATA_LOOP;\r
-\r
- -- end of subevent marker\r
--- wait until rising_edge(clk);\r
- pc_end_of_data_in <= '1';\r
- wait until rising_edge(clk);\r
- pc_end_of_data_in <= '0';\r
- pc_sub_size_in <= x"0000_0000";\r
- pc_trig_nr_in <= x"0000_0000";\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- trigger_loop := trigger_loop + 1;\r
- trigger_counter := trigger_counter + 1;\r
-\r
- wait for 500 ns;\r
- wait until rising_edge(clk);\r
- end loop MY_TRIGGER_LOOP;\r
-\r
--- wait for 8 us;\r
--------------------------------------------------------------------------------\r
--- end of loop\r
--------------------------------------------------------------------------------\r
-\r
- wait until rising_edge(clk);\r
- fc_ready_in <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fc_h_ready_in <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- \r
- -- Stay a while... stay forever!!!Muahahah!!!\r
- wait;\r
-\r
-end process THE_TESTBENCH; \r
- \r
-END;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT slv_mac_memory\r
- PORT(\r
- CLK : IN std_logic;\r
- RESET : IN std_logic;\r
- BUSY_IN : IN std_logic;\r
- SLV_ADDR_IN : IN std_logic_vector(7 downto 0);\r
- SLV_READ_IN : IN std_logic;\r
- SLV_WRITE_IN : IN std_logic;\r
- SLV_DATA_IN : IN std_logic_vector(31 downto 0);\r
- MEM_CLK_IN : IN std_logic;\r
- MEM_ADDR_IN : IN std_logic_vector(7 downto 0); \r
- SLV_BUSY_OUT : OUT std_logic;\r
- SLV_ACK_OUT : OUT std_logic;\r
- SLV_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- MEM_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- STAT : OUT std_logic_vector(31 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL BUSY_IN : std_logic;\r
- SIGNAL SLV_ADDR_IN : std_logic_vector(7 downto 0);\r
- SIGNAL SLV_READ_IN : std_logic;\r
- SIGNAL SLV_WRITE_IN : std_logic;\r
- SIGNAL SLV_BUSY_OUT : std_logic;\r
- SIGNAL SLV_ACK_OUT : std_logic;\r
- SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0);\r
- SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL MEM_CLK_IN : std_logic;\r
- SIGNAL MEM_ADDR_IN : std_logic_vector(7 downto 0);\r
- SIGNAL MEM_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL STAT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: slv_mac_memory PORT MAP(\r
- CLK => CLK,\r
- RESET => RESET,\r
- BUSY_IN => BUSY_IN,\r
- SLV_ADDR_IN => SLV_ADDR_IN,\r
- SLV_READ_IN => SLV_READ_IN,\r
- SLV_WRITE_IN => SLV_WRITE_IN,\r
- SLV_BUSY_OUT => SLV_BUSY_OUT,\r
- SLV_ACK_OUT => SLV_ACK_OUT,\r
- SLV_DATA_IN => SLV_DATA_IN,\r
- SLV_DATA_OUT => SLV_DATA_OUT,\r
- MEM_CLK_IN => MEM_CLK_IN,\r
- MEM_ADDR_IN => MEM_ADDR_IN,\r
- MEM_DATA_OUT => MEM_DATA_OUT,\r
- STAT => STAT\r
- );\r
-\r
-CLK_GEN_PROC: process\r
-begin\r
- clk <= '0'; mem_clk_in <= '0'; wait for 5.0 ns;\r
- clk <= '1'; mem_clk_in <= '1'; wait for 5.0 ns;\r
-end process CLK_GEN_PROC;\r
-\r
-THE_TESTBENCH: process\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- busy_in <= '0';\r
- slv_addr_in <= x"00";\r
- slv_read_in <= '0';\r
- slv_write_in <= '0';\r
- slv_data_in <= x"dead_beef";\r
- mem_addr_in <= x"f0";\r
- wait until rising_edge(clk);\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- wait until rising_edge(clk);\r
- \r
- -- Tests may start now\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"00";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"01";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"02";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"03";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"04";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"05";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"06";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"07";\r
- wait until rising_edge(clk);\r
- mem_addr_in <= x"08";\r
- \r
- -- Stay a while... stay forever!!! Muahahaha!!!!!\r
- wait;\r
-end process THE_TESTBENCH;\r
-\r
-END;\r
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb_net_gbe_components.all;
---use work.version.all;
-
-entity trb_net16_gbe_buf is
-generic(
- DO_SIMULATION : integer range 0 to 1 := 1;
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
-);
-port(
- CLK : in std_logic;
- TEST_CLK : in std_logic; -- only for simulation!
- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
- RESET : in std_logic;
- GSR_N : in std_logic;
- -- Debug
- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);
- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);
- -- configuration interface
- IP_CFG_START_IN : in std_logic;
- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);
- IP_CFG_DONE_OUT : out std_logic;
- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);
- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);
- IP_CFG_MEM_CLK_OUT : out std_logic;
- MR_RESET_IN : in std_logic;
- MR_MODE_IN : in std_logic;
- MR_RESTART_IN : in std_logic;
- -- gk 29.03.10
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- gk 22.04.10
- -- registers setup interface
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
- -- gk 23.04.10
- LED_PACKET_SENT_OUT : out std_logic;
- LED_AN_DONE_N_OUT : out std_logic;
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- --SFP Connection
- SFP_RXD_P_IN : in std_logic;
- SFP_RXD_N_IN : in std_logic;
- SFP_TXD_P_OUT : out std_logic;
- SFP_TXD_N_OUT : out std_logic;
- SFP_REFCLK_P_IN : in std_logic;
- SFP_REFCLK_N_IN : in std_logic;
- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SFP_TXDIS_OUT : out std_logic; -- SFP disable
- -- debug ports
- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end entity trb_net16_gbe_buf;
-
-architecture trb_net16_gbe_buf of trb_net16_gbe_buf is
-
--- Placer Directives
-attribute HGROUP : string;
--- for whole architecture
-attribute HGROUP of trb_net16_gbe_buf : architecture is "GBE_BUF_group";
-
-
-component tsmac3
-port(
- --------------- clock and reset port declarations ------------------
- hclk : in std_logic;
- txmac_clk : in std_logic;
- rxmac_clk : in std_logic;
- reset_n : in std_logic;
- txmac_clk_en : in std_logic;
- rxmac_clk_en : in std_logic;
- ------------------- Input signals to the GMII ----------------
- rxd : in std_logic_vector(7 downto 0);
- rx_dv : in std_logic;
- rx_er : in std_logic;
- col : in std_logic;
- crs : in std_logic;
- -------------------- Input signals to the CPU I/F -------------------
- haddr : in std_logic_vector(7 downto 0);
- hdatain : in std_logic_vector(7 downto 0);
- hcs_n : in std_logic;
- hwrite_n : in std_logic;
- hread_n : in std_logic;
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata : in std_logic_vector(7 downto 0);
- tx_fifoavail : in std_logic;
- tx_fifoeof : in std_logic;
- tx_fifoempty : in std_logic;
- tx_sndpaustim : in std_logic_vector(15 downto 0);
- tx_sndpausreq : in std_logic;
- tx_fifoctrl : in std_logic;
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
- rx_fifo_full : in std_logic;
- ignore_pkt : in std_logic;
- -------------------- Output signals from the GMII -----------------------
- txd : out std_logic_vector(7 downto 0);
- tx_en : out std_logic;
- tx_er : out std_logic;
- -------------------- Output signals from the CPU I/F -------------------
- hdataout : out std_logic_vector(7 downto 0);
- hdataout_en_n : out std_logic;
- hready_n : out std_logic;
- cpu_if_gbit_en : out std_logic;
- ---------------- Output signals from the Tx MAC FIFO I/F ---------------
- tx_macread : out std_logic;
- tx_discfrm : out std_logic;
- tx_staten : out std_logic;
- tx_done : out std_logic;
- tx_statvec : out std_logic_vector(30 downto 0);
- ---------------- Output signals from the Rx MAC FIFO I/F ---------------
- rx_fifo_error : out std_logic;
- rx_stat_vector : out std_logic_vector(31 downto 0);
- rx_dbout : out std_logic_vector(7 downto 0);
- rx_write : out std_logic;
- rx_stat_en : out std_logic;
- rx_eof : out std_logic;
- rx_error : out std_logic
-);
-end component;
-
-component mb_mac_sim is
-port (
- --------------------------------------------------------------------------
- --------------- clock, reset, clock enable -------------------------------
- HCLK : in std_logic;
- TX_MAC_CLK : in std_logic;
- RX_MAC_CLK : in std_logic;
- RESET_N : in std_logic;
- TXMAC_CLK_EN : in std_logic;
- RXMAC_CLK_EN : in std_logic;
- --------------------------------------------------------------------------
- --------------- SGMII receive interface ----------------------------------
- RXD : in std_logic_vector(7 downto 0);
- RX_DV : in std_logic;
- RX_ER : in std_logic;
- COL : in std_logic;
- CRS : in std_logic;
- --------------------------------------------------------------------------
- --------------- SGMII transmit interface ---------------------------------
- TXD : out std_logic_vector(7 downto 0);
- TX_EN : out std_logic;
- TX_ER : out std_logic;
- --------------------------------------------------------------------------
- --------------- CPU configuration interface ------------------------------
- HADDR : in std_logic_vector(7 downto 0);
- HDATAIN : in std_logic_vector(7 downto 0);
- HCS_N : in std_logic;
- HWRITE_N : in std_logic;
- HREAD_N : in std_logic;
- HDATAOUT : out std_logic_vector(7 downto 0);
- HDATAOUT_EN_N : out std_logic;
- HREADY_N : out std_logic;
- CPU_IF_GBIT_EN : out std_logic;
- --------------------------------------------------------------------------
- --------------- Transmit FIFO interface ----------------------------------
- TX_FIFODATA : in std_logic_vector(7 downto 0);
- TX_FIFOAVAIL : in std_logic;
- TX_FIFOEOF : in std_logic;
- TX_FIFOEMPTY : in std_logic;
- TX_MACREAD : out std_logic;
- TX_DONE : out std_logic;
- TX_SNDPAUSTIM : in std_logic_vector(15 downto 0);
- TX_SNDPAUSREQ : in std_logic;
- TX_FIFOCTRL : in std_logic;
- TX_DISCFRM : out std_logic;
- TX_STATEN : out std_logic;
- TX_STATVEC : out std_logic_vector(30 downto 0);
- --------------------------------------------------------------------------
- --------------- Receive FIFO interface -----------------------------------
- RX_DBOUT : out std_logic_vector(7 downto 0);
- RX_FIFO_FULL : in std_logic;
- IGNORE_PKT : in std_logic;
- RX_FIFO_ERROR : out std_logic;
- RX_STAT_VECTOR : out std_logic_vector(31 downto 0);
- RX_STAT_EN : out std_logic;
- RX_WRITE : out std_logic;
- RX_EOF : out std_logic;
- RX_ERROR : out std_logic
-);
-end component;
-
-component slv_mac_memory is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- BUSY_IN : in std_logic;
- -- Slave bus
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- I/O to the backend
- MEM_CLK_IN : in std_logic;
- MEM_ADDR_IN : in std_logic_vector(7 downto 0);
- MEM_DATA_OUT : out std_logic_vector(31 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
-);
-end component;
-
-component fifo_4096x9 is
-port(
- Data : in std_logic_vector(8 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-signal ig_bsm_save : std_logic_vector(3 downto 0);
-signal ig_bsm_load : std_logic_vector(3 downto 0);
-signal ig_cts_ctr : std_logic_vector(2 downto 0);
-signal ig_rem_ctr : std_logic_vector(3 downto 0);
-signal ig_debug : std_logic_vector(31 downto 0);
-signal ig_data : std_logic_vector(15 downto 0);
-signal ig_wcnt : std_logic_vector(15 downto 0);
-signal ig_rcnt : std_logic_vector(16 downto 0);
-signal ig_rd_en : std_logic;
-signal ig_wr_en : std_logic;
-signal ig_empty : std_logic;
-signal ig_aempty : std_logic;
-signal ig_full : std_logic;
-signal ig_afull : std_logic;
-
-signal pc_wr_en : std_logic;
-signal pc_data : std_logic_vector(7 downto 0);
-signal pc_eod : std_logic;
-signal pc_sos : std_logic;
-signal pc_ready : std_logic;
-signal pc_padding : std_logic;
-signal pc_decoding : std_logic_vector(31 downto 0);
-signal pc_event_id : std_logic_vector(31 downto 0);
-signal pc_queue_dec : std_logic_vector(31 downto 0);
-signal pc_max_frame_size : std_logic_vector(15 downto 0);
-signal pc_bsm_constr : std_logic_vector(3 downto 0);
-signal pc_bsm_load : std_logic_vector(3 downto 0);
-signal pc_bsm_save : std_logic_vector(3 downto 0);
-signal pc_shf_empty : std_logic;
-signal pc_shf_full : std_logic;
-signal pc_shf_wr_en : std_logic;
-signal pc_shf_rd_en : std_logic;
-signal pc_shf_q : std_logic_vector(7 downto 0);
-signal pc_df_empty : std_logic;
-signal pc_df_full : std_logic;
-signal pc_df_wr_en : std_logic;
-signal pc_df_rd_en : std_logic;
-signal pc_df_q : std_logic_vector(7 downto 0);
-signal pc_all_ctr : std_logic_vector(4 downto 0);
-signal pc_sub_ctr : std_logic_vector(4 downto 0);
-signal pc_bytes_loaded : std_logic_vector(15 downto 0);
-signal pc_size_left : std_logic_vector(31 downto 0);
-signal pc_sub_size_to_save : std_logic_vector(31 downto 0);
-signal pc_sub_size_loaded : std_logic_vector(31 downto 0);
-signal pc_sub_bytes_loaded : std_logic_vector(31 downto 0);
-signal pc_queue_size : std_logic_vector(31 downto 0);
-signal pc_act_queue_size : std_logic_vector(31 downto 0);
-
-signal fee_read : std_logic;
-signal cts_readout_finished : std_logic;
-signal cts_dataready : std_logic;
-signal cts_length : std_logic_vector(15 downto 0);
-signal cts_data : std_logic_vector(31 downto 0); -- DHDR of rest packet
-signal cts_error_pattern : std_logic_vector(31 downto 0);
-
-signal pc_sub_size : std_logic_vector(31 downto 0);
-signal pc_trig_nr : std_logic_vector(31 downto 0);
-
-signal fc_wr_en : std_logic;
-signal fc_data : std_logic_vector(7 downto 0);
-signal fc_ip_size : std_logic_vector(15 downto 0);
-signal fc_udp_size : std_logic_vector(15 downto 0);
-signal fc_ident : std_logic_vector(15 downto 0);
-signal fc_flags_offset : std_logic_vector(15 downto 0);
-signal fc_sod : std_logic;
-signal fc_eod : std_logic;
-signal fc_h_ready : std_logic;
-signal fc_ready : std_logic;
-signal fc_dest_mac : std_logic_vector(47 downto 0);
-signal fc_dest_ip : std_logic_vector(31 downto 0);
-signal fc_dest_udp : std_logic_vector(15 downto 0);
-signal fc_src_mac : std_logic_vector(47 downto 0);
-signal fc_src_ip : std_logic_vector(31 downto 0);
-signal fc_src_udp : std_logic_vector(15 downto 0);
-signal fc_type : std_logic_vector(15 downto 0);
-signal fc_ihl_version : std_logic_vector(7 downto 0);
-signal fc_tos : std_logic_vector(7 downto 0);
-signal fc_ttl : std_logic_vector(7 downto 0);
-signal fc_protocol : std_logic_vector(7 downto 0);
-signal fc_bsm_constr : std_logic_vector(7 downto 0);
-signal fc_bsm_trans : std_logic_vector(3 downto 0);
-
-signal ft_data : std_logic_vector(8 downto 0);-- gk 04.05.10
-signal ft_tx_empty : std_logic;
-signal ft_start_of_packet : std_logic;
-signal ft_bsm_init : std_logic_vector(3 downto 0);
-signal ft_bsm_mac : std_logic_vector(3 downto 0);
-signal ft_bsm_trans : std_logic_vector(3 downto 0);
-
-signal mac_haddr : std_logic_vector(7 downto 0);
-signal mac_hdataout : std_logic_vector(7 downto 0);
-signal mac_hcs : std_logic;
-signal mac_hwrite : std_logic;
-signal mac_hread : std_logic;
-signal mac_fifoavail : std_logic;
-signal mac_fifoempty : std_logic;
-signal mac_fifoeof : std_logic;
-signal mac_hready : std_logic;
-signal mac_hdata_en : std_logic;
-signal mac_tx_done : std_logic;
-signal mac_tx_read : std_logic;
-
-signal serdes_clk_125 : std_logic;
-signal mac_tx_clk_en : std_logic;
-signal mac_rx_clk_en : std_logic;
-signal mac_col : std_logic;
-signal mac_crs : std_logic;
-signal pcs_txd : std_logic_vector(7 downto 0);
-signal pcs_tx_en : std_logic;
-signal pcs_tx_er : std_logic;
-signal pcs_an_lp_ability : std_logic_vector(15 downto 0);
-signal pcs_an_complete : std_logic;
-signal pcs_an_page_rx : std_logic;
-
-signal pcs_stat_debug : std_logic_vector(63 downto 0);
-
-signal stage_stat_regs : std_logic_vector(31 downto 0);
-signal stage_ctrl_regs : std_logic_vector(31 downto 0);
-
-signal analyzer_debug : std_logic_vector(63 downto 0);
-
-signal ip_cfg_start : std_logic;
-signal ip_cfg_bank : std_logic_vector(3 downto 0);
-signal ip_cfg_done : std_logic;
-
-signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);
-signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
-signal ip_cfg_mem_clk : std_logic;
-
--- gk 22.04.10
-signal max_packet : std_logic_vector(31 downto 0);
-signal min_packet : std_logic_vector(31 downto 0);
-signal use_gbe : std_logic;
-signal use_trbnet : std_logic;
-signal use_multievents : std_logic;
--- gk 26.04.10
-signal readout_ctr : std_logic_vector(23 downto 0);
-signal readout_ctr_valid : std_logic;
-signal gbe_trig_nr : std_logic_vector(31 downto 0);
--- gk 28.04.10
-signal pc_delay : std_logic_vector(31 downto 0);
--- gk 04.05.10
-signal ft_eod : std_logic;
--- gk 01.06.10
-signal dbg_ipu2gbe1 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe2 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe3 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe4 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe5 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe6 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe7 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe8 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe9 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe10 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe11 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe12 : std_logic_vector(31 downto 0);
-signal dbg_pc1 : std_logic_vector(31 downto 0);
-signal dbg_pc2 : std_logic_vector(31 downto 0);
-signal dbg_fc1 : std_logic_vector(31 downto 0);
-signal dbg_fc2 : std_logic_vector(31 downto 0);
-signal dbg_ft1 : std_logic_vector(31 downto 0);
-signal dbg_ft2 : std_logic_vector(31 downto 0);
--- gk 08.06.10
-signal mac_tx_staten : std_logic;
-signal mac_tx_statevec : std_logic_vector(30 downto 0);
-signal mac_tx_discfrm : std_logic;
-
-signal dbg_rd_en : std_logic;
-signal dbg_q : std_logic_vector(15 downto 0);
-
--- gk 21.07.10
-signal allow_large : std_logic;
-
--- gk 28.07.10
-signal bytes_sent_ctr : std_logic_vector(31 downto 0);
-signal monitor_sent : std_logic_vector(31 downto 0);
-signal monitor_dropped : std_logic_vector(31 downto 0);
-signal monitor_sm : std_logic_vector(31 downto 0);
-signal monitor_lr : std_logic_vector(31 downto 0);
-signal monitor_hr : std_logic_vector(31 downto 0);
-signal monitor_fifos : std_logic_vector(31 downto 0);
-signal monitor_fifos_q : std_logic_vector(31 downto 0);
-signal monitor_discfrm : std_logic_vector(31 downto 0);
-
--- gk 02.08.10
-signal discfrm_ctr : std_logic_vector(31 downto 0);
-
--- gk 28.09.10
-signal dbg_reset_fifo : std_logic;
-signal db_fifo_rst : std_logic;
-
--- gk 30.09.10
-signal fc_rd_en : std_logic;
-signal link_ok : std_logic;
-signal link_ok_timeout_ctr : std_logic_vector(15 downto 0);
-
-type linkStates is (ACTIVE, INACTIVE, TIMEOUT, FINALIZE);
-signal link_current_state, link_next_state : linkStates;
-
-signal link_down_ctr : std_logic_vector(15 downto 0);
-signal link_down_ctr_lock : std_logic;
-
-signal link_state : std_logic_vector(3 downto 0);
-
-signal monitor_empty : std_logic_vector(31 downto 0);
-
--- gk 07.10.10
-signal pc_eos : std_logic;
-
--- gk 09.12.10
-signal frame_delay : std_logic_vector(31 downto 0);
-
-begin
-
-stage_ctrl_regs <= STAGE_CTRL_REGS_IN;
-
--- gk 23.04.10
-LED_PACKET_SENT_OUT <= pc_ready;
-LED_AN_DONE_N_OUT <= not link_ok; --not pcs_an_complete;
-
--- gk 22.04.10 moved to gbe_setup entity
--- PacketConstructor fixed magic values
---pc_decoding <= x"00020001"; -- !!!! swap it!!!! -- gk 22.04.10
---pc_event_id <= x"000000ca"; -- !!!! swap it!!!! -- gk 22.04.10
---pc_queue_dec <= x"00030062"; -- !!!! swap it!!!! -- gk 22.04.10
-
--- FrameConstructor fixed magic values
-fc_type <= x"0008";
-fc_ihl_version <= x"45";
-fc_tos <= x"10";
-fc_ttl <= x"ff";
-fc_protocol <= x"11";
-
--- gk 22.04.10 new entity to set values via slow control
-SETUP : gbe_setup
-port map(
- CLK => CLK,
- RESET => RESET,
-
- -- gk 26.04.10
- -- interface to regio bus
- BUS_ADDR_IN => BUS_ADDR_IN,
- BUS_DATA_IN => BUS_DATA_IN,
- BUS_DATA_OUT => BUS_DATA_OUT,
- BUS_WRITE_EN_IN => BUS_WRITE_EN_IN,
- BUS_READ_EN_IN => BUS_READ_EN_IN,
- BUS_ACK_OUT => BUS_ACK_OUT,
-
- GBE_TRIG_NR_IN => pc_trig_nr, -- gk 26.04.10
-
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT => pc_event_id,
- GBE_SUBEVENT_DEC_OUT => pc_decoding,
- GBE_QUEUE_DEC_OUT => pc_queue_dec,
- GBE_MAX_PACKET_OUT => max_packet,
- GBE_MIN_PACKET_OUT => min_packet, -- gk 20.07.10
- GBE_MAX_FRAME_OUT => pc_max_frame_size,
- GBE_USE_GBE_OUT => use_gbe,
- GBE_USE_TRBNET_OUT => use_trbnet,
- GBE_USE_MULTIEVENTS_OUT => use_multievents,
- GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10
- GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10
- GBE_DELAY_OUT => pc_delay,
- GBE_ALLOW_LARGE_OUT => allow_large, -- gk 21.07.10
- GBE_FRAME_DELAY_OUT => frame_delay, -- gk 09.12.10
- -- gk 28.07.10
- MONITOR_BYTES_IN => bytes_sent_ctr,
- MONITOR_SENT_IN => monitor_sent,
- MONITOR_DROPPED_IN => monitor_dropped,
- MONITOR_SM_IN => monitor_sm,
- MONITOR_LR_IN => monitor_lr,
- MONITOR_HDR_IN => monitor_hr,
- MONITOR_FIFOS_IN => monitor_fifos_q,
- MONITOR_DISCFRM_IN => monitor_discfrm,
- MONITOR_EMPTY_IN => monitor_empty,
- MONITOR_LINK_DWN_IN(15 downto 0) => link_down_ctr, -- gk 30.09.10
- MONITOR_LINK_DWN_IN(19 downto 16) => link_state,
- MONITOR_LINK_DWN_IN(23 downto 20) => ft_bsm_trans,
- MONITOR_LINK_DWN_IN(27 downto 24) => fc_bsm_trans,
- MONITOR_LINK_DWN_IN(31 downto 28) => (others => '0'),
- -- gk 01.06.10
- DBG_IPU2GBE1_IN => dbg_ipu2gbe1,
- DBG_IPU2GBE2_IN => dbg_ipu2gbe2,
- DBG_IPU2GBE3_IN => dbg_ipu2gbe3,
- DBG_IPU2GBE4_IN => dbg_ipu2gbe4,
- DBG_IPU2GBE5_IN => dbg_ipu2gbe5,
- DBG_IPU2GBE6_IN => dbg_ipu2gbe6,
- DBG_IPU2GBE7_IN => dbg_ipu2gbe7,
- DBG_IPU2GBE8_IN => dbg_ipu2gbe8,
- DBG_IPU2GBE9_IN => dbg_ipu2gbe9,
- DBG_IPU2GBE10_IN => dbg_ipu2gbe10,
- DBG_IPU2GBE11_IN => dbg_ipu2gbe11,
- DBG_IPU2GBE12_IN => dbg_ipu2gbe12,
- DBG_PC1_IN => dbg_pc1,
- DBG_PC2_IN => dbg_pc2,
- DBG_FC1_IN => dbg_fc1,
- DBG_FC2_IN => dbg_fc2,
- DBG_FT1_IN => dbg_ft1,
- DBG_FT2_IN => dbg_ft2,
- DBG_FIFO_RD_EN_OUT => dbg_rd_en,
- DBG_FIFO_Q_IN => dbg_q
- --DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10
-);
-
--- IP configurator: allows IP config to change for each event builder
-THE_IP_CONFIGURATOR: ip_configurator
-port map(
- CLK => CLK,
- RESET => RESET,
- -- configuration interface
- START_CONFIG_IN => ip_cfg_start, --IP_CFG_START_IN, -- new -- gk 7.03.10
- BANK_SELECT_IN => ip_cfg_bank, --IP_CFG_BANK_SEL_IN, -- new -- gk 27.03.10
- CONFIG_DONE_OUT => ip_cfg_done, --IP_CFG_DONE_OUT, -- new -- gk 27.03.10
- MEM_ADDR_OUT => ip_cfg_mem_addr, --IP_CFG_MEM_ADDR_OUT, -- new -- gk 27.03.10
- MEM_DATA_IN => ip_cfg_mem_data, --IP_CFG_MEM_DATA_IN, -- new -- gk 27.03.10
- MEM_CLK_OUT => ip_cfg_mem_clk, --IP_CFG_MEM_CLK_OUT, -- new -- gk 27.03.10
- -- information for IP cores
- DEST_MAC_OUT => fc_dest_mac,
- DEST_IP_OUT => fc_dest_ip,
- DEST_UDP_OUT => fc_dest_udp,
- SRC_MAC_OUT => fc_src_mac,
- SRC_IP_OUT => fc_src_ip,
- SRC_UDP_OUT => fc_src_udp,
- MTU_OUT => open, --pc_max_frame_size, -- gk 22.04.10
- -- Debug
- DEBUG_OUT => open
-);
-
--- gk 27.03.01
-MB_IP_CONFIG: slv_mac_memory
-port map(
- CLK => CLK, -- clk_100,
- RESET => RESET, --reset_i,
- BUSY_IN => '0',
- -- Slave bus
- SLV_ADDR_IN => SLV_ADDR_IN, --x"00", --mb_ip_mem_addr(7 downto 0),
- SLV_READ_IN => SLV_READ_IN, --'0', --mb_ip_mem_read,
- SLV_WRITE_IN => SLV_WRITE_IN, --mb_ip_mem_write,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT, --mb_ip_mem_ack,
- SLV_DATA_IN => SLV_DATA_IN, --mb_ip_mem_data_wr,
- SLV_DATA_OUT => SLV_DATA_OUT, --mb_ip_mem_data_rd,
- -- I/O to the backend
- MEM_CLK_IN => ip_cfg_mem_clk,
- MEM_ADDR_IN => ip_cfg_mem_addr,
- MEM_DATA_OUT => ip_cfg_mem_data,
- -- Status lines
- STAT => open
-);
-
--- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS
-THE_IPU_INTERFACE: trb_net16_ipu2gbe
-port map(
- CLK => CLK,
- RESET => RESET,
- --Event information coming from CTS
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_OUT => cts_data,
- CTS_DATAREADY_OUT => cts_dataready,
- CTS_READOUT_FINISHED_OUT => cts_readout_finished,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => cts_length,
- CTS_ERROR_PATTERN_OUT => cts_error_pattern,
- -- Data from Frontends
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => fee_read,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- slow control interface
- START_CONFIG_OUT => ip_cfg_start, --open, --: out std_logic; -- reconfigure MACs/IPs/ports/packet size -- gk 27.03.10
- BANK_SELECT_OUT => ip_cfg_bank, --open, --: out std_logic_vector(3 downto 0); -- configuration page address -- gk 27.03.10
- CONFIG_DONE_IN => ip_cfg_done, --'1', --: in std_logic; -- configuration finished -- gk 27.03.10
- DATA_GBE_ENABLE_IN => use_gbe, --'1', --: in std_logic; -- IPU data is forwarded to GbE -- gk 22.04.10
- DATA_IPU_ENABLE_IN => use_trbnet, --'0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet -- gk 22.04.10
- MULT_EVT_ENABLE_IN => use_multievents,
- MAX_MESSAGE_SIZE_IN => max_packet, --x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl -- gk 22.04.10
- MIN_MESSAGE_SIZE_IN => min_packet, -- gk 20.07.10
- READOUT_CTR_IN => readout_ctr, -- gk 26.04.10
- READOUT_CTR_VALID_IN => readout_ctr_valid, -- gk 26.04.10
- ALLOW_LARGE_IN => allow_large, -- gk 21.07.10
- -- PacketConstructor interface
- PC_WR_EN_OUT => pc_wr_en,
- PC_DATA_OUT => pc_data,
- PC_READY_IN => pc_ready,
- PC_SOS_OUT => pc_sos,
- PC_EOS_OUT => pc_eos, -- gk 07.10.10
- PC_EOD_OUT => pc_eod,
- PC_SUB_SIZE_OUT => pc_sub_size,
- PC_TRIG_NR_OUT => pc_trig_nr,
- PC_PADDING_OUT => pc_padding,
- MONITOR_OUT(31 downto 0) => monitor_sent,
- MONITOR_OUT(63 downto 32) => monitor_dropped,
- MONITOR_OUT(95 downto 64) => monitor_hr,
- MONITOR_OUT(127 downto 96) => monitor_sm,
- MONITOR_OUT(159 downto 128) => monitor_lr,
- MONITOR_OUT(191 downto 160) => monitor_fifos,
- MONITOR_OUT(223 downto 192) => monitor_empty,
- DEBUG_OUT(31 downto 0) => dbg_ipu2gbe1,
- DEBUG_OUT(63 downto 32) => dbg_ipu2gbe2,
- DEBUG_OUT(95 downto 64) => dbg_ipu2gbe3,
- DEBUG_OUT(127 downto 96) => dbg_ipu2gbe4,
- DEBUG_OUT(159 downto 128) => dbg_ipu2gbe5,
- DEBUG_OUT(191 downto 160) => dbg_ipu2gbe6,
- DEBUG_OUT(223 downto 192) => dbg_ipu2gbe7,
- DEBUG_OUT(255 downto 224) => dbg_ipu2gbe8,
- DEBUG_OUT(287 downto 256) => dbg_ipu2gbe9,
- DEBUG_OUT(319 downto 288) => dbg_ipu2gbe10,
- DEBUG_OUT(351 downto 320) => dbg_ipu2gbe11,
- DEBUG_OUT(383 downto 352) => dbg_ipu2gbe12
-);
-
--- Second stage: Packet constructor
-PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr
-port map(
- -- ports for user logic
- RESET => RESET,
- CLK => CLK,
- PC_WR_EN_IN => pc_wr_en,
- PC_DATA_IN => pc_data,
- PC_READY_OUT => pc_ready,
- PC_START_OF_SUB_IN => pc_sos,
- PC_END_OF_SUB_IN => pc_eos, -- gk 07.10.10
- PC_END_OF_DATA_IN => pc_eod,
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN => pc_sub_size,
- PC_PADDING_IN => pc_padding, -- gk 29.03.10
- PC_DECODING_IN => pc_decoding,
- PC_EVENT_ID_IN => pc_event_id,
- PC_TRIG_NR_IN => pc_trig_nr,
- PC_QUEUE_DEC_IN => pc_queue_dec,
- PC_MAX_FRAME_SIZE_IN => pc_max_frame_size,
- PC_DELAY_IN => pc_delay, -- gk 28.04.10
- MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10
- -- NEW PORTS
- FC_WR_EN_OUT => fc_wr_en,
- FC_DATA_OUT => fc_data,
- FC_H_READY_IN => fc_h_ready,
- FC_READY_IN => fc_ready,
- FC_IP_SIZE_OUT => fc_ip_size,
- FC_UDP_SIZE_OUT => fc_udp_size,
- FC_IDENT_OUT => fc_ident,
- FC_FLAGS_OFFSET_OUT => fc_flags_offset,
- FC_SOD_OUT => fc_sod,
- FC_EOD_OUT => fc_eod,
- DEBUG_OUT(31 downto 0) => dbg_pc1,
- DEBUG_OUT(63 downto 32) => dbg_pc2
-);
-
--- gk 04.08.10
-MON_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0);
- if (dbg_pc1(28) = '1') then
- monitor_fifos_q(5 downto 4) <= b"11";
- else
- monitor_fifos_q(5 downto 4) <= b"00";
- end if;
- if (dbg_pc1(30) = '1') then
- monitor_fifos_q(7 downto 6) <= b"11";
- else
- monitor_fifos_q(7 downto 6) <= b"00";
- end if;
- if (dbg_fc1(28) = '1') then
- monitor_fifos_q(11 downto 8) <= b"1111";
- else
- monitor_fifos_q(11 downto 8) <= b"0000";
- end if;
- if (pcs_an_complete = '0') then
- monitor_fifos_q(15 downto 12) <= b"1111";
- else
- monitor_fifos_q(15 downto 12) <= b"0000";
- end if;
- end if;
-end process MON_PROC;
-
--- Third stage: Frame Constructor
-FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
-port map(
- -- ports for user logic
- RESET => RESET,
- CLK => CLK,
- LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
- --
- WR_EN_IN => fc_wr_en,
- DATA_IN => fc_data,
- START_OF_DATA_IN => fc_sod,
- END_OF_DATA_IN => fc_eod,
- IP_F_SIZE_IN => fc_ip_size,
- UDP_P_SIZE_IN => fc_udp_size,
- HEADERS_READY_OUT => fc_h_ready,
- READY_OUT => fc_ready,
- DEST_MAC_ADDRESS_IN => fc_dest_mac,
- DEST_IP_ADDRESS_IN => fc_dest_ip,
- DEST_UDP_PORT_IN => fc_dest_udp,
- SRC_MAC_ADDRESS_IN => fc_src_mac,
- SRC_IP_ADDRESS_IN => fc_src_ip,
- SRC_UDP_PORT_IN => fc_src_udp,
- FRAME_TYPE_IN => fc_type,
- IHL_VERSION_IN => fc_ihl_version,
- TOS_IN => fc_tos,
- IDENTIFICATION_IN => fc_ident,
- FLAGS_OFFSET_IN => fc_flags_offset,
- TTL_IN => fc_ttl,
- PROTOCOL_IN => fc_protocol,
- FRAME_DELAY_IN => frame_delay, -- gk 09.12.10
- -- ports for packetTransmitter
- RD_CLK => serdes_clk_125,
- FT_DATA_OUT => ft_data,
- --FT_EOD_OUT => ft_eod, -- gk 04.05.10
- FT_TX_EMPTY_OUT => ft_tx_empty,
- FT_TX_RD_EN_IN => fc_rd_en, --mac_tx_read, -- gk 30.09.10
- FT_START_OF_PACKET_OUT => ft_start_of_packet,
- FT_TX_DONE_IN => mac_tx_done,
- FT_TX_DISCFRM_IN => mac_tx_discfrm,
- -- debug ports
- BSM_CONSTR_OUT => fc_bsm_constr,
- BSM_TRANS_OUT => fc_bsm_trans,
- DEBUG_OUT(31 downto 0) => dbg_fc1,
- DEBUG_OUT(63 downto 32) => dbg_fc2
-);
-
---***********************
--- LINK STATE CONTROL
---***********************
-
--- gk 30.09.10
-fc_rd_en <= '1' when ((link_ok = '1') and (mac_tx_read = '1'))
- or (link_ok = '0')
- else '0';
-
--- gk 30.09.10
-LINK_STATE_MACHINE_PROC : process(serdes_clk_125)
-begin
- if rising_edge(serdes_clk_125) then
- if (RESET = '1') or (dbg_reset_fifo = '1') then
- link_current_state <= INACTIVE;
- else
- link_current_state <= link_next_state;
- end if;
- end if;
-end process;
-
--- gk 30.09.10
-LINK_STATE_MACHINE : process(serdes_clk_125)
-begin
- case link_current_state is
-
- when ACTIVE =>
- link_state <= x"1";
- if (pcs_an_complete = '0') then
- link_next_state <= INACTIVE;
- else
- link_next_state <= link_current_state;
- end if;
-
- when INACTIVE =>
- link_state <= x"2";
- if (pcs_an_complete = '1') then
- link_next_state <= TIMEOUT;
- else
- link_next_state <= link_current_state;
- end if;
-
- when TIMEOUT =>
- link_state <= x"3";
- if (pcs_an_complete = '0') then
- link_next_state <= INACTIVE;
- else
- if (link_ok_timeout_ctr = x"ffff") then
- link_next_state <= FINALIZE;
- else
- link_next_state <= link_current_state;
- end if;
- end if;
-
- when FINALIZE =>
- link_state <= x"4";
- if (pcs_an_complete = '0') then
- link_next_state <= INACTIVE;
- else
- if (pc_ready = '1') then
- link_next_state <= ACTIVE;
- else
- link_next_state <= link_current_state;
- end if;
- end if;
-
- end case;
-end process LINK_STATE_MACHINE;
-
--- gk 30.09.10
-LINK_OK_CTR_PROC : process(serdes_clk_125)
-begin
- if rising_edge(serdes_clk_125) then
- if (RESET = '1') or (link_current_state /= TIMEOUT) then
- link_ok_timeout_ctr <= (others => '0');
- elsif (link_current_state = TIMEOUT) then
- link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1";
- end if;
- end if;
-end process LINK_OK_CTR_PROC;
-
--- gk 30.09.10
-LINK_OK_PROC : process(serdes_clk_125)
-begin
- if rising_edge(serdes_clk_125) then
- if (RESET = '1') then
- link_ok <= '0';
- elsif (link_current_state = ACTIVE) then
- link_ok <= '1';
- else
- link_ok <= '0';
- end if;
- end if;
-end process LINK_OK_PROC;
-
--- gk 30.09.10
-LINK_DOWN_CTR_PROC : process(serdes_clk_125)
-begin
- if rising_edge(serdes_clk_125) then
- if (RESET = '1') then
- link_down_ctr <= (others => '0');
- link_down_ctr_lock <= '0';
- elsif (pcs_an_complete = '1') then
- link_down_ctr_lock <= '0';
- elsif ((pcs_an_complete = '0') and (link_down_ctr_lock = '0')) then
- link_down_ctr <= link_down_ctr + x"1";
- link_down_ctr_lock <= '1';
- end if;
- end if;
-end process LINK_DOWN_CTR_PROC;
-
-
-
-
-FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
-port map(
- CLK => CLK,
- RESET => RESET,
- LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
- TX_MAC_CLK => serdes_clk_125,
- TX_EMPTY_IN => ft_tx_empty,
- START_OF_PACKET_IN => ft_start_of_packet,
- DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10
- -- MAC interface
- HADDR_OUT => mac_haddr,
- HDATA_OUT => mac_hdataout,
- HCS_OUT => mac_hcs,
- HWRITE_OUT => mac_hwrite,
- HREAD_OUT => mac_hread,
- HREADY_IN => mac_hready,
- HDATA_EN_IN => mac_hdata_en,
- TX_FIFOAVAIL_OUT => mac_fifoavail,
- TX_FIFOEOF_OUT => mac_fifoeof,
- TX_FIFOEMPTY_OUT => mac_fifoempty,
- TX_DONE_IN => mac_tx_done,
- TX_DISCFRM_IN => mac_tx_discfrm,
- -- Debug
- BSM_INIT_OUT => ft_bsm_init,
- BSM_MAC_OUT => ft_bsm_mac,
- BSM_TRANS_OUT => ft_bsm_trans,
- DBG_RD_DONE_OUT => open,
- DBG_INIT_DONE_OUT => open,
- DBG_ENABLED_OUT => open,
- DEBUG_OUT => open
- --DEBUG_OUT(31 downto 0) => open,
- --DEBUG_OUT(63 downto 32) => open
-);
-
--- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in
-imp_gen: if (DO_SIMULATION = 0) generate
- --------------------------------------------------------------------------------------------
- --------------------------------------------------------------------------------------------
- -- Implementation
- --------------------------------------------------------------------------------------------
- --------------------------------------------------------------------------------------------
-
- -- MAC part
- MAC: tsmac3
- port map(
- ----------------- clock and reset port declarations ------------------
- hclk => CLK,
- txmac_clk => serdes_clk_125,
- rxmac_clk => serdes_clk_125,
- reset_n => GSR_N,
- txmac_clk_en => mac_tx_clk_en,
- rxmac_clk_en => mac_rx_clk_en,
- ------------------- Input signals to the GMII ---------------- NOT USED
- rxd => x"00",
- rx_dv => '0',
- rx_er => '0',
- col => mac_col,
- crs => mac_crs,
- -------------------- Input signals to the CPU I/F -------------------
- haddr => mac_haddr,
- hdatain => mac_hdataout,
- hcs_n => mac_hcs,
- hwrite_n => mac_hwrite,
- hread_n => mac_hread,
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata => ft_data(7 downto 0),
- tx_fifoavail => mac_fifoavail,
- tx_fifoeof => mac_fifoeof,
- tx_fifoempty => mac_fifoempty,
- tx_sndpaustim => x"0000",
- tx_sndpausreq => '0',
- tx_fifoctrl => '0', -- always data frame
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
- rx_fifo_full => '0',
- ignore_pkt => '0',
- ---------------- Output signals from the GMII -----------------------
- txd => pcs_txd,
- tx_en => pcs_tx_en,
- tx_er => pcs_tx_er,
- ----------------- Output signals from the CPU I/F -------------------
- hdataout => open,
- hdataout_en_n => mac_hdata_en,
- hready_n => mac_hready,
- cpu_if_gbit_en => open,
- ------------- Output signals from the Tx MAC FIFO I/F ---------------
- tx_macread => mac_tx_read,
- tx_discfrm => mac_tx_discfrm,
- tx_staten => mac_tx_staten, -- gk 08.06.10
- tx_statvec => mac_tx_statevec, -- gk 08.06.10
- tx_done => mac_tx_done,
- ------------- Output signals from the Rx MAC FIFO I/F ---------------
- rx_fifo_error => open,
- rx_stat_vector => open,
- rx_dbout => open,
- rx_write => open,
- rx_stat_en => open,
- rx_eof => open,
- rx_error => open
- );
-
- -- gk 08.06.10
- dbg_statevec_proc : process(serdes_clk_125)
- begin
- if rising_edge(serdes_clk_125) then
- if (RESET = '1') then
- dbg_ft1 <= (others => '0');
- elsif (mac_tx_staten = '1') then
- dbg_ft1(30 downto 0) <= mac_tx_statevec;
- dbg_ft1(31) <= mac_tx_discfrm;
- end if;
- end if;
- end process dbg_statevec_proc;
-
- dbg_ft2 <= stage_stat_regs;
-
- serdes_intclk_gen: if (USE_125MHZ_EXTCLK = 0) generate
- -- PHY part
- PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b
- generic map(
- USE_125MHZ_EXTCLK => 0
- )
- port map(
- RESET => RESET,
- GSR_N => GSR_N,
- CLK_125_OUT => serdes_clk_125,
- CLK_125_IN => CLK_125_IN,
- FT_TX_CLK_EN_OUT => mac_tx_clk_en,
- FT_RX_CLK_EN_OUT => mac_rx_clk_en,
- --connection to frame transmitter (tsmac)
- FT_COL_OUT => mac_col,
- FT_CRS_OUT => mac_crs,
- FT_TXD_IN => pcs_txd,
- FT_TX_EN_IN => pcs_tx_en,
- FT_TX_ER_IN => pcs_tx_er,
- --SFP Connection
- SD_RXD_P_IN => SFP_RXD_P_IN,
- SD_RXD_N_IN => SFP_RXD_N_IN,
- SD_TXD_P_OUT => SFP_TXD_P_OUT,
- SD_TXD_N_OUT => SFP_TXD_N_OUT,
- SD_REFCLK_P_IN => SFP_REFCLK_P_IN,
- SD_REFCLK_N_IN => SFP_REFCLK_N_IN,
- SD_PRSNT_N_IN => SFP_PRSNT_N_IN,
- SD_LOS_IN => SFP_LOS_IN,
- SD_TXDIS_OUT => SFP_TXDIS_OUT,
- -- Autonegotiation stuff
- MR_ADV_ABILITY_IN => x"0020", -- full duplex only
- MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability,
- MR_AN_PAGE_RX_OUT => pcs_an_page_rx,
- MR_AN_COMPLETE_OUT => pcs_an_complete,
- MR_RESET_IN => MR_RESET_IN,
- MR_MODE_IN => MR_MODE_IN,
- MR_AN_ENABLE_IN => '1', -- do autonegotiation
- MR_RESTART_AN_IN => MR_RESTART_IN,
- -- Status and control port
- STAT_OP => open,
- CTRL_OP => x"0000",
- STAT_DEBUG => pcs_stat_debug, --open,
- CTRL_DEBUG => x"0000_0000_0000_0000"
- );
- end generate serdes_intclk_gen;
-
- serdes_extclk_gen: if (USE_125MHZ_EXTCLK = 1) generate
- -- PHY part
- PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b
- generic map(
- USE_125MHZ_EXTCLK => 1
- )
- port map(
- RESET => RESET,
- GSR_N => GSR_N,
- CLK_125_OUT => serdes_clk_125,
- CLK_125_IN => '0', -- not used
- FT_TX_CLK_EN_OUT => mac_tx_clk_en,
- FT_RX_CLK_EN_OUT => mac_rx_clk_en,
- --connection to frame transmitter (tsmac)
- FT_COL_OUT => mac_col,
- FT_CRS_OUT => mac_crs,
- FT_TXD_IN => pcs_txd,
- FT_TX_EN_IN => pcs_tx_en,
- FT_TX_ER_IN => pcs_tx_er,
- --SFP Connection
- SD_RXD_P_IN => SFP_RXD_P_IN,
- SD_RXD_N_IN => SFP_RXD_N_IN,
- SD_TXD_P_OUT => SFP_TXD_P_OUT,
- SD_TXD_N_OUT => SFP_TXD_N_OUT,
- SD_REFCLK_P_IN => SFP_REFCLK_P_IN,
- SD_REFCLK_N_IN => SFP_REFCLK_N_IN,
- SD_PRSNT_N_IN => SFP_PRSNT_N_IN,
- SD_LOS_IN => SFP_LOS_IN,
- SD_TXDIS_OUT => SFP_TXDIS_OUT,
- -- Autonegotiation stuff
- MR_ADV_ABILITY_IN => x"0020", -- full duplex only
- MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability,
- MR_AN_PAGE_RX_OUT => pcs_an_page_rx,
- MR_AN_COMPLETE_OUT => pcs_an_complete,
- MR_RESET_IN => MR_RESET_IN,
- MR_MODE_IN => MR_MODE_IN,
- MR_AN_ENABLE_IN => '1', -- do autonegotiation
- MR_RESTART_AN_IN => MR_RESTART_IN,
- -- Status and control port
- STAT_OP => open,
- CTRL_OP => x"0000",
- STAT_DEBUG => pcs_stat_debug, --open,
- CTRL_DEBUG => x"0000_0000_0000_0000"
- );
- end generate serdes_extclk_gen;
-
- stage_stat_regs(31 downto 28) <= x"e";
- stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link s-tatus
- stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm
- stage_stat_regs(19) <= '0';
- stage_stat_regs(18) <= link_ok; -- gk 30.09.10
- stage_stat_regs(17) <= pcs_an_complete;
- stage_stat_regs(16) <= pcs_an_page_rx;
- stage_stat_regs(15 downto 0) <= pcs_an_lp_ability;
-
-end generate imp_gen;
-
--- in case of simulation we include a fake MAC and no PHY/SerDes.
-sim_gen: if (DO_SIMULATION = 1) generate
- --------------------------------------------------------------------------------------------
- --------------------------------------------------------------------------------------------
- -- Simulation
- --------------------------------------------------------------------------------------------
- --------------------------------------------------------------------------------------------
- MAC: mb_mac_sim
- port map( --------------------------------------------------------------------------
- --------------- clock, reset, clock enable -------------------------------
- HCLK => CLK,
- TX_MAC_CLK => serdes_clk_125,
- RX_MAC_CLK => serdes_clk_125,
- RESET_N => GSR_N,
- TXMAC_CLK_EN => mac_tx_clk_en,
- RXMAC_CLK_EN => mac_rx_clk_en,
- --------------------------------------------------------------------------
- --------------- SGMII receive interface ----------------------------------
- RXD => x"00",
- RX_DV => '0',
- RX_ER => '0',
- COL => mac_col,
- CRS => mac_crs,
- --------------------------------------------------------------------------
- --------------- SGMII transmit interface ---------------------------------
- TXD => pcs_txd,
- TX_EN => pcs_tx_en,
- TX_ER => pcs_tx_er,
- --------------------------------------------------------------------------
- --------------- CPU configuration interface ------------------------------
- HADDR => mac_haddr,
- HDATAIN => mac_hdataout,
- HCS_N => mac_hcs,
- HWRITE_N => mac_hwrite,
- HREAD_N => mac_hread,
- HDATAOUT => open,
- HDATAOUT_EN_N => mac_hdata_en,
- HREADY_N => mac_hready,
- CPU_IF_GBIT_EN => open,
- --------------------------------------------------------------------------
- --------------- Transmit FIFO interface ----------------------------------
- TX_FIFODATA => ft_data(7 downto 0),
- TX_FIFOAVAIL => mac_fifoavail,
- TX_FIFOEOF => mac_fifoeof,
- TX_FIFOEMPTY => mac_fifoempty,
- TX_MACREAD => mac_tx_read,
- TX_DONE => mac_tx_done,
- TX_SNDPAUSTIM => x"0000",
- TX_SNDPAUSREQ => '0',
- TX_FIFOCTRL => '0',
- TX_DISCFRM => open,
- TX_STATEN => open,
- TX_STATVEC => open,
- --------------------------------------------------------------------------
- --------------- Receive FIFO interface -----------------------------------
- RX_DBOUT => open,
- RX_FIFO_FULL => '0',
- IGNORE_PKT => '0',
- RX_FIFO_ERROR => open,
- RX_STAT_VECTOR => open,
- RX_STAT_EN => open,
- RX_WRITE => open,
- RX_EOF => open,
- RX_ERROR => open
- );
-
- -- add external test clock for the MAC part
- serdes_clk_125 <= TEST_CLK;
-
- -- fake signals
- pcs_an_lp_ability <= x"4060";
- pcs_an_page_rx <= '0';
- pcs_an_complete <= '1';
- mac_tx_clk_en <= '1';
- mac_rx_clk_en <= '1';
-
- stage_stat_regs(31 downto 0) <= (others => '0');
-
- pcs_stat_debug(63 downto 0) <= (others => '0');
-
- SFP_TXD_P_OUT <= '1';
- SFP_TXD_N_OUT <= '0';
- SFP_TXDIS_OUT <= '0';
-
-end generate sim_gen;
-
--- gk 28.07.10
-BYTES_SENT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- bytes_sent_ctr <= (others => '0');
- elsif (fc_wr_en = '1') then
- bytes_sent_ctr <= bytes_sent_ctr + x"1";
- end if;
- end if;
-end process BYTES_SENT_CTR_PROC;
-
--- gk 02.08.10
-DISCFRM_PROC : process(serdes_clk_125)
-begin
- if rising_edge(serdes_clk_125) then
- if (RESET = '1') then
- discfrm_ctr <= (others => '0');
- elsif (mac_tx_discfrm = '1') then
- discfrm_ctr <= discfrm_ctr + x"1";
- end if;
- end if;
-end process DISCFRM_PROC;
-
-discfrm_sync : signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 32
- )
- port map(
- RESET => RESET,
- D_IN => discfrm_ctr,
- CLK0 => serdes_clk_125,
- CLK1 => CLK,
- D_OUT => monitor_discfrm
- );
-
--- gk 29.09.10
--- debug fifo saves each sent frame, but drops it after receiving information that everything went fine
--- otherwise, the frame will be kept to readout via slow control
-db_fifo_rst <= '1' when ((RESET = '1') or ((mac_tx_done = '1') and (discfrm_ctr = x"00000000"))) else '0';
-
--- debug_fifo : fifo_4096x9
--- port map(
--- Data(7 downto 0) => pcs_txd,
--- Data(8) => '0',
--- WrClock => serdes_clk_125,
--- RdClock => CLK,
--- WrEn => pcs_tx_en,
--- RdEn => dbg_rd_en,
--- Reset => db_fifo_rst,
--- RPReset => db_fifo_rst,
--- Q => dbg_q(8 downto 0),
--- Empty => open,
--- Full => open
--- );
-
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-
---***************
--- LOGIC ANALYZER SIGNALS
---***************
-analyzer_debug <= pcs_stat_debug;
-
--- Outputs
-FEE_READ_OUT <= fee_read;
-
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
-CTS_DATAREADY_OUT <= cts_dataready;
-CTS_DATA_OUT <= cts_data;
-CTS_LENGTH_OUT <= cts_length;
-CTS_ERROR_PATTERN_OUT <= cts_error_pattern;
-
-STAGE_STAT_REGS_OUT <= stage_stat_regs;
-
-ANALYZER_DEBUG_OUT <= analyzer_debug;
-
-end architecture;
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.trb_net16_hub_func.all;\r
-\r
-entity trb_net16_gbe_frame_constr is\r
-port( \r
- -- ports for user logic\r
- RESET : in std_logic;\r
- CLK : in std_logic;\r
- LINK_OK_IN : in std_logic; -- gk 03.08.10\r
- --\r
- WR_EN_IN : in std_logic;\r
- DATA_IN : in std_logic_vector(7 downto 0);\r
- START_OF_DATA_IN : in std_logic;\r
- END_OF_DATA_IN : in std_logic;\r
- IP_F_SIZE_IN : in std_logic_vector(15 downto 0);\r
- UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation\r
- HEADERS_READY_OUT : out std_logic;\r
- READY_OUT : out std_logic;\r
- DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
- DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
- DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
- SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
- SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
- SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0);\r
- IHL_VERSION_IN : in std_logic_vector(7 downto 0);\r
- TOS_IN : in std_logic_vector(7 downto 0);\r
- IDENTIFICATION_IN : in std_logic_vector(15 downto 0);\r
- FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);\r
- TTL_IN : in std_logic_vector(7 downto 0);\r
- PROTOCOL_IN : in std_logic_vector(7 downto 0);\r
- FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10\r
- -- ports for packetTransmitter\r
- RD_CLK : in std_logic; -- 125MHz clock!!!\r
- FT_DATA_OUT : out std_logic_vector(8 downto 0);\r
- FT_TX_EMPTY_OUT : out std_logic;\r
- FT_TX_RD_EN_IN : in std_logic;\r
- FT_START_OF_PACKET_OUT : out std_logic;\r
- FT_TX_DONE_IN : in std_logic;\r
- FT_TX_DISCFRM_IN : in std_logic;\r
- -- debug ports\r
- BSM_CONSTR_OUT : out std_logic_vector(7 downto 0);\r
- BSM_TRANS_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
-);\r
-end trb_net16_gbe_frame_constr;\r
-\r
-architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is\r
-\r
--- -- Placer Directives\r
--- attribute HGROUP : string;\r
--- -- for whole architecture\r
--- attribute HGROUP of trb_net16_gbe_frame_constr : architecture is "GBE_frame_group";\r
-\r
-component fifo_4096x9 is\r
-port( \r
- Data : in std_logic_vector(8 downto 0);\r
- WrClock : in std_logic;\r
- RdClock : in std_logic;\r
- WrEn : in std_logic;\r
- RdEn : in std_logic;\r
- Reset : in std_logic;\r
- RPReset : in std_logic;\r
- Q : out std_logic_vector(8 downto 0);\r
- Empty : out std_logic;\r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
-attribute sys_encoding : string;\r
-\r
-type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION,\r
- TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS,\r
- SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH,\r
- UDP_CS, SAVE_DATA, CLEANUP, DELAY);\r
-signal constructCurrentState, constructNextState : constructStates;\r
-signal bsm_constr : std_logic_vector(7 downto 0);\r
-attribute sys_encoding of constructCurrentState: signal is "safe,gray";\r
-\r
-type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP);\r
-signal transmitCurrentState, transmitNextState : transmitStates;\r
-signal bsm_trans : std_logic_vector(3 downto 0);\r
-\r
-signal headers_int_counter : integer range 0 to 6;\r
-signal fpf_data : std_logic_vector(7 downto 0);\r
-signal fpf_empty : std_logic;\r
-signal fpf_full : std_logic;\r
-signal fpf_wr_en : std_logic;\r
-signal fpf_rd_en : std_logic;\r
-signal fpf_q : std_logic_vector(8 downto 0);\r
-signal ip_size : std_logic_vector(15 downto 0);\r
-signal ip_checksum : std_logic_vector(31 downto 0);\r
-signal udp_size : std_logic_vector(15 downto 0);\r
-signal udp_checksum : std_logic_vector(15 downto 0);\r
-signal ft_sop : std_logic;\r
-signal put_udp_headers : std_logic;\r
-signal ready_frames_ctr : std_logic_vector(15 downto 0);\r
-signal sent_frames_ctr : std_logic_vector(15 downto 0);\r
-signal debug : std_logic_vector(63 downto 0);\r
-signal ready : std_logic;\r
-signal headers_ready : std_logic;\r
-\r
-signal cur_max : integer range 0 to 10;\r
-\r
-signal ready_frames_ctr_q : std_logic_vector(15 downto 0);\r
-signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10\r
-\r
-signal fpf_reset : std_logic; -- gk 01.01.01\r
-\r
--- gk 09.12.10\r
-signal delay_ctr : std_logic_vector(31 downto 0);\r
-signal frame_delay_reg : std_logic_vector(31 downto 0);\r
-\r
-begin\r
-\r
--- Fakes\r
-udp_checksum <= x"0000"; -- no checksum test needed\r
---debug <= (others => '0');\r
-\r
-ready <= '1' when (constructCurrentState = IDLE)\r
- else '0';\r
-headers_ready <= '1' when (constructCurrentState = SAVE_DATA)\r
- else '0';\r
-\r
-sizeProc: process( put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN )\r
-begin\r
- if( put_udp_headers = '1' ) then\r
- ip_size <= IP_F_SIZE_IN + x"14" + x"8";\r
- udp_size <= UDP_P_SIZE_IN + x"8";\r
- else\r
- ip_size <= IP_F_SIZE_IN + x"14";\r
- udp_size <= UDP_P_SIZE_IN;\r
- end if;\r
-end process sizeProc;\r
-\r
-ipCsProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (constructCurrentState = IDLE) then\r
- ip_checksum <= x"00000000";\r
- else\r
- case constructCurrentState is\r
- when DEST_MAC_ADDR =>\r
- case headers_int_counter is\r
- when 0 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(7 downto 0);\r
- when 1 =>\r
- ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(15 downto 8);\r
- when 2 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(23 downto 16);\r
- when 3 =>\r
- ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(31 downto 24);\r
- when 4 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(7 downto 0);\r
- when 5 =>\r
- ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(15 downto 8);\r
- when others => null;\r
- end case;\r
- when SRC_MAC_ADDR =>\r
- case headers_int_counter is\r
- when 0 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(23 downto 16);\r
- when 1 =>\r
- ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(31 downto 24);\r
- when 2 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IHL_VERSION_IN;\r
- when 3 =>\r
- ip_checksum <= ip_checksum + TOS_IN;\r
- when 4 =>\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + ip_size(15 downto 8);\r
- when 5 =>\r
- ip_checksum <= ip_checksum + ip_size(7 downto 0);\r
- when others => null;\r
- end case;\r
- when VERSION =>\r
- if headers_int_counter = 0 then\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IDENTIFICATION_IN(7 downto 0);\r
- end if;\r
- when TOS_S =>\r
- if headers_int_counter = 0 then\r
- ip_checksum <= ip_checksum + IDENTIFICATION_IN(15 downto 8);\r
- end if;\r
- when IP_LENGTH =>\r
- if headers_int_counter = 0 then\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + FLAGS_OFFSET_IN(15 downto 8);\r
- elsif headers_int_counter = 1 then\r
- ip_checksum <= ip_checksum + FLAGS_OFFSET_IN(7 downto 0);\r
- end if;\r
- when IDENT =>\r
- if headers_int_counter = 0 then\r
- ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + TTL_IN;\r
- elsif headers_int_counter = 1 then\r
- ip_checksum <= ip_checksum + PROTOCOL_IN;\r
- end if;\r
- -- gk 29.03.10 corrected the bug with bad checksums when sum larger than 16b\r
- when FLAGS =>\r
- if headers_int_counter = 0 then\r
- ip_cs_temp_right <= ip_checksum(31 downto 16);\r
- elsif headers_int_counter = 1 then\r
- ip_checksum(31 downto 16) <= (others => '0');\r
- end if;\r
- when TTL_S =>\r
- if headers_int_counter = 0 then\r
- ip_checksum <= ip_checksum + ip_cs_temp_right;\r
- end if;\r
- when PROTO =>\r
- if headers_int_counter = 0 then\r
- ip_checksum(15 downto 0) <= ip_checksum(15 downto 0) + ip_checksum(31 downto 16);\r
- end if;\r
- when others => null;\r
- end case;\r
- end if;\r
- end if;\r
-end process ipCsProc;\r
-\r
-\r
-constructMachineProc: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if( RESET = '1' ) then\r
- constructCurrentState <= IDLE;\r
- else\r
- constructCurrentState <= constructNextState;\r
- end if;\r
- end if;\r
-end process constructMachineProc;\r
-\r
---find next state of construct machine\r
-constructMachine: process( constructCurrentState, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, delay_ctr, FRAME_DELAY_IN )\r
-begin\r
- constructNextState <= constructCurrentState;\r
- if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0\r
- case constructCurrentState is\r
- when IDLE =>\r
- if( START_OF_DATA_IN = '1' ) then\r
- constructNextState <= DEST_MAC_ADDR;\r
- end if;\r
- when DEST_MAC_ADDR =>\r
- constructNextState <= SRC_MAC_ADDR;\r
- when SRC_MAC_ADDR =>\r
- constructNextState <= FRAME_TYPE_S;\r
- when FRAME_TYPE_S =>\r
- constructNextState <= VERSION;\r
- when VERSION =>\r
- constructNextState <= TOS_S;\r
- when TOS_S =>\r
- constructNextState <= IP_LENGTH;\r
- when IP_LENGTH =>\r
- constructNextState <= IDENT;\r
- when IDENT =>\r
- constructNextState <= FLAGS;\r
- when FLAGS =>\r
- constructNextState <= TTL_S;\r
- when TTL_S =>\r
- constructNextState <= PROTO;\r
- when PROTO =>\r
- constructNextState <= HEADER_CS;\r
- when HEADER_CS =>\r
- constructNextState <= SRC_IP_ADDR;\r
- when SRC_IP_ADDR =>\r
- constructNextState <= DEST_IP_ADDR;\r
- when DEST_IP_ADDR =>\r
- if (put_udp_headers = '1') then\r
- constructNextState <= SRC_PORT;\r
- else\r
- constructNextState <= SAVE_DATA;\r
- end if;\r
- when SRC_PORT =>\r
- constructNextState <= DEST_PORT;\r
- when DEST_PORT =>\r
- constructNextState <= UDP_LENGTH;\r
- when UDP_LENGTH =>\r
- constructNextState <= UDP_CS;\r
- when UDP_CS =>\r
- constructNextState <= SAVE_DATA;\r
- when SAVE_DATA =>\r
- if (END_OF_DATA_IN = '1') then\r
- constructNextState <= CLEANUP;\r
- end if;\r
- when CLEANUP =>\r
- constructNextState <= DELAY; -- gk 10.12.10 IDLE;\r
-\r
- -- gk 09.12.10\r
- when DELAY =>\r
- if (delay_ctr = FRAME_DELAY_IN) then\r
- constructNextState <= IDLE;\r
- else\r
- constructNextState <= DELAY;\r
- end if;\r
-\r
- when others =>\r
- constructNextState <= IDLE;\r
- end case;\r
- end if;\r
-end process constructMachine;\r
-\r
--- gk 09.12.10\r
-delayCtrProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (constructCurrentState = IDLE) or (constructCurrentState = CLEANUP) then\r
- delay_ctr <= (others => '0');\r
- elsif (constructCurrentState = DELAY) then\r
- delay_ctr <= delay_ctr + x"1";\r
- end if;\r
-\r
- frame_delay_reg <= FRAME_DELAY_IN;\r
- end if;\r
-end process delayCtrProc;\r
-\r
-\r
-bsmConstrProc : process(constructCurrentState)\r
-begin\r
---find maximum time in each state & set state bits\r
- case constructCurrentState is\r
- when IDLE => cur_max <= 0; bsm_constr <= x"01";\r
- when DEST_MAC_ADDR => cur_max <= 5; bsm_constr <= x"02";\r
- when SRC_MAC_ADDR => cur_max <= 5; bsm_constr <= x"03";\r
- when FRAME_TYPE_S => cur_max <= 1; bsm_constr <= x"04";\r
- when VERSION => cur_max <= 0; bsm_constr <= x"05";\r
- when TOS_S => cur_max <= 0; bsm_constr <= x"06";\r
- when IP_LENGTH => cur_max <= 1; bsm_constr <= x"07";\r
- when IDENT => cur_max <= 1; bsm_constr <= x"08";\r
- when FLAGS => cur_max <= 1; bsm_constr <= x"09";\r
- when TTL_S => cur_max <= 0; bsm_constr <= x"0a";\r
- when PROTO => cur_max <= 0; bsm_constr <= x"0b";\r
- when HEADER_CS => cur_max <= 1; bsm_constr <= x"0c";\r
- when SRC_IP_ADDR => cur_max <= 3; bsm_constr <= x"0d";\r
- when DEST_IP_ADDR => cur_max <= 3; bsm_constr <= x"0e";\r
- when SRC_PORT => cur_max <= 1; bsm_constr <= x"0f";\r
- when DEST_PORT => cur_max <= 1; bsm_constr <= x"10";\r
- when UDP_LENGTH => cur_max <= 1; bsm_constr <= x"11";\r
- when UDP_CS => cur_max <= 1; bsm_constr <= x"12";\r
- when SAVE_DATA => cur_max <= 0; bsm_constr <= x"13";\r
- when CLEANUP => cur_max <= 0; bsm_constr <= x"14";\r
- when DELAY => cur_max <= 0; bsm_constr <= x"15";\r
- when others => cur_max <= 0; bsm_constr <= x"1f";\r
- end case;\r
-end process;\r
-\r
-\r
-headersIntProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (constructCurrentState = IDLE) then\r
- headers_int_counter <= 0;\r
- else\r
- if (headers_int_counter = cur_max) then\r
- headers_int_counter <= 0;\r
- else\r
- headers_int_counter <= headers_int_counter + 1;\r
- end if;\r
- end if;\r
- end if;\r
-end process headersIntProc;\r
-\r
-\r
-\r
-putUdpHeadersProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (FLAGS_OFFSET_IN(12 downto 0) = "0000000000000") then\r
- put_udp_headers <= '1';\r
- else\r
- put_udp_headers <= '0';\r
- end if;\r
- end if;\r
-end process putUdpHeadersProc;\r
-\r
-\r
-fpfWrEnProc : process(constructCurrentState, WR_EN_IN, RESET, LINK_OK_IN)\r
-begin\r
- if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10\r
- fpf_wr_en <= '0';\r
- elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) and (constructCurrentState /= DELAY) then\r
- fpf_wr_en <= '1';\r
- elsif (constructCurrentState = SAVE_DATA) and (WR_EN_IN = '1') then\r
- fpf_wr_en <= '1';\r
- else\r
- fpf_wr_en <= '0';\r
- end if;\r
-end process fpfWrEnProc;\r
-\r
-fpfDataProc : process(constructCurrentState, DEST_MAC_ADDRESS_IN, SRC_MAC_ADDRESS_IN, FRAME_TYPE_IN, IHL_VERSION_IN,\r
- TOS_IN, ip_size, IDENTIFICATION_IN, FLAGS_OFFSET_IN, TTL_IN, PROTOCOL_IN,\r
- ip_checksum, SRC_IP_ADDRESS_IN, DEST_IP_ADDRESS_IN,\r
- SRC_UDP_PORT_IN, DEST_UDP_PORT_IN, udp_size, udp_checksum, headers_int_counter, DATA_IN)\r
-begin\r
- case constructCurrentState is\r
- when IDLE => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when DEST_MAC_ADDR => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when SRC_MAC_ADDR => fpf_data <= SRC_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when FRAME_TYPE_S => fpf_data <= FRAME_TYPE_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when VERSION => fpf_data <= IHL_VERSION_IN;\r
- when TOS_S => fpf_data <= TOS_IN;\r
- when IP_LENGTH => fpf_data <= ip_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when IDENT => fpf_data <= IDENTIFICATION_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when FLAGS => fpf_data <= FLAGS_OFFSET_IN(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when TTL_S => fpf_data <= TTL_IN;\r
- when PROTO => fpf_data <= PROTOCOL_IN;\r
- when HEADER_CS => fpf_data <= x"ff" - ip_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when SRC_IP_ADDR => fpf_data <= SRC_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when DEST_IP_ADDR => fpf_data <= DEST_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when SRC_PORT => fpf_data <= SRC_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when DEST_PORT => fpf_data <= DEST_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8);\r
- when UDP_LENGTH => fpf_data <= udp_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when UDP_CS => fpf_data <= udp_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
- when SAVE_DATA => fpf_data <= DATA_IN;\r
- when CLEANUP => fpf_data <= x"ab";\r
- when DELAY => fpf_data <= x"ac";\r
- when others => fpf_data <= x"00";\r
- end case;\r
-end process fpfDataProc;\r
-\r
-\r
-readyFramesCtrProc: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10\r
- ready_frames_ctr <= (others => '0');\r
- elsif (constructCurrentState = CLEANUP) then\r
- ready_frames_ctr <= ready_frames_ctr + 1;\r
- end if;\r
- end if;\r
-end process readyFramesCtrProc;\r
-\r
-fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10\r
-\r
-FINAL_PACKET_FIFO: fifo_4096x9\r
-port map( \r
- Data(7 downto 0) => fpf_data,\r
- Data(8) => END_OF_DATA_IN,\r
- WrClock => CLK,\r
- RdClock => RD_CLK,\r
- WrEn => fpf_wr_en,\r
- RdEn => FT_TX_RD_EN_IN,\r
- Reset => fpf_reset,\r
- RPReset => fpf_reset,\r
- Q => fpf_q,\r
- Empty => fpf_empty,\r
- Full => fpf_full\r
-);\r
-\r
-transferToRdClock : signal_sync\r
- generic map(\r
- DEPTH => 2,\r
- WIDTH => 16\r
- )\r
- port map(\r
- RESET => RESET,\r
- D_IN => ready_frames_ctr,\r
- CLK0 => RD_CLK, --CLK,\r
- CLK1 => RD_CLK,\r
- D_OUT => ready_frames_ctr_q\r
- );\r
-\r
-transmitMachineProc: process( RD_CLK )\r
-begin\r
- if( rising_edge(RD_CLK) ) then\r
- if( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10\r
- transmitCurrentState <= T_IDLE;\r
- else\r
- transmitCurrentState <= transmitNextState;\r
- end if;\r
- end if;\r
-end process transmitMachineProc;\r
-\r
-transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, ready_frames_ctr_q, FT_TX_DISCFRM_IN )\r
-begin\r
- case transmitCurrentState is\r
- when T_IDLE =>\r
- bsm_trans <= x"0";\r
- if( (sent_frames_ctr /= ready_frames_ctr_q) ) then\r
- transmitNextState <= T_LOAD;\r
- else\r
- transmitNextState <= T_IDLE;\r
- end if;\r
- when T_LOAD =>\r
- bsm_trans <= x"1";\r
- if( fpf_q(8) = '1' ) then\r
- transmitNextState <= T_TRANSMIT;\r
- else\r
- transmitNextState <= T_LOAD;\r
- end if;\r
- when T_TRANSMIT =>\r
- bsm_trans <= x"2";\r
- -- gk 03.08.10\r
- if ((LINK_OK_IN = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then\r
- transmitNextState <= T_CLEANUP;\r
- elsif (LINK_OK_IN = '0') then\r
- transmitNextState <= T_PAUSE;\r
- else\r
- transmitNextState <= T_TRANSMIT;\r
- end if;\r
- when T_PAUSE =>\r
- transmitNextState <= T_CLEANUP;\r
- when T_CLEANUP =>\r
- bsm_trans <= x"3";\r
- transmitNextState <= T_IDLE;\r
- when others =>\r
- bsm_trans <= x"f";\r
- transmitNextState <= T_IDLE;\r
- end case;\r
-end process transmitMachine;\r
-\r
-\r
-\r
-sopProc: process( RD_CLK )\r
-begin\r
- if rising_edge(RD_CLK) then\r
- if ( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10\r
- ft_sop <= '0';\r
- elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then\r
- ft_sop <= '1';\r
- else\r
- ft_sop <= '0';\r
- end if;\r
- end if;\r
-end process sopProc;\r
-\r
-sentFramesCtrProc: process( RD_CLK )\r
-begin\r
- if rising_edge(RD_CLK) then\r
- if ( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10\r
- sent_frames_ctr <= (others => '0');\r
- -- gk 03.08.10\r
- elsif( FT_TX_DONE_IN = '1' ) or (FT_TX_DISCFRM_IN = '1') then\r
- sent_frames_ctr <= sent_frames_ctr + 1;\r
- end if;\r
- end if;\r
-end process sentFramesCtrProc;\r
-\r
-debug(7 downto 0) <= bsm_constr;\r
-debug(11 downto 8) <= bsm_trans;\r
-debug(27 downto 12) <= sent_frames_ctr;\r
-debug(28) <= fpf_full;\r
-debug(29) <= fpf_empty;\r
-debug(30) <= ready;\r
-debug(31) <= headers_ready;\r
-debug(47 downto 32) <= ready_frames_ctr_q;\r
-debug(48) <= '0';\r
-\r
-\r
--- Output\r
-FT_DATA_OUT <= fpf_q;\r
-FT_TX_EMPTY_OUT <= fpf_empty;\r
-FT_START_OF_PACKET_OUT <= ft_sop;\r
-READY_OUT <= ready;\r
-HEADERS_READY_OUT <= headers_ready;\r
-\r
-BSM_CONSTR_OUT <= bsm_constr;\r
-BSM_TRANS_OUT <= bsm_trans;\r
-DEBUG_OUT <= debug;\r
-\r
-end trb_net16_gbe_frame_constr;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.trb_net16_hub_func.all;\r
-\r
-entity trb_net16_gbe_frame_trans is\r
-port (\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- LINK_OK_IN : in std_logic; -- gk 03.08.10\r
- TX_MAC_CLK : in std_logic;\r
- TX_EMPTY_IN : in std_logic;\r
- START_OF_PACKET_IN : in std_logic;\r
- DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC\r
- -- NEW PORTS\r
- HADDR_OUT : out std_logic_vector(7 downto 0);\r
- HDATA_OUT : out std_logic_vector(7 downto 0);\r
- HCS_OUT : out std_logic;\r
- HWRITE_OUT : out std_logic;\r
- HREAD_OUT : out std_logic;\r
- HREADY_IN : in std_logic;\r
- HDATA_EN_IN : in std_logic;\r
- TX_FIFOAVAIL_OUT : out std_logic;\r
- TX_FIFOEOF_OUT : out std_logic;\r
- TX_FIFOEMPTY_OUT : out std_logic;\r
- TX_DONE_IN : in std_logic;\r
- TX_DISCFRM_IN : in std_logic;\r
- -- Debug\r
- BSM_INIT_OUT : out std_logic_vector(3 downto 0);\r
- BSM_MAC_OUT : out std_logic_vector(3 downto 0);\r
- BSM_TRANS_OUT : out std_logic_vector(3 downto 0);\r
- DBG_RD_DONE_OUT : out std_logic;\r
- DBG_INIT_DONE_OUT : out std_logic;\r
- DBG_ENABLED_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
-);\r
-end trb_net16_gbe_frame_trans;\r
-\r
--- FifoRd ?!?\r
-\r
-architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is\r
-\r
--- -- Placer Directives\r
--- attribute HGROUP : string;\r
--- -- for whole architecture\r
--- attribute HGROUP of trb_net16_gbe_frame_trans : architecture is "GBE_frame_group";\r
-\r
-component mac_init_mem is\r
-port (\r
- Address : in std_logic_vector(5 downto 0); \r
- OutClock : in std_logic; \r
- OutClockEn : in std_logic; \r
- Reset : in std_logic; \r
- Q : out std_logic_vector(7 downto 0)\r
-);\r
-end component;\r
-\r
-attribute syn_encoding : string;\r
-\r
-type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED);\r
-signal macInitState, macInitNextState : macInitStates;\r
-attribute syn_encoding of macInitState: signal is "safe,gray";\r
-signal bsm_init : std_logic_vector(3 downto 0);\r
- \r
-type macStates is (M_RESETING, M_IDLE, M_INIT);\r
-signal macCurrentState, macNextState : macStates;\r
-signal bsm_mac : std_logic_vector(3 downto 0);\r
- \r
-type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO);\r
-signal transmitCurrentState, transmitNextState : transmitStates;\r
-attribute syn_encoding of transmitCurrentState: signal is "safe,gray";\r
-signal bsm_trans : std_logic_vector(3 downto 0);\r
-\r
-signal tx_fifoavail_i : std_logic;\r
-signal tx_fifoeof_i : std_logic;\r
-\r
--- host interface signals\r
-signal hcs_n_i : std_logic;\r
-signal hwrite_n_i : std_logic;\r
-signal hread_n_i : std_logic;\r
-\r
--- MAC INITIALIZATION signals\r
-signal macInitMemAddr : std_logic_vector(5 downto 0);\r
-signal macInitMemQ : std_logic_vector(7 downto 0);\r
-signal macInitMemEn : std_logic;\r
-signal reading_done : std_logic;\r
-signal init_done : std_logic;\r
-signal enabled : std_logic;\r
-signal addrSig : std_logic_vector(5 downto 0);\r
-signal addr2 : std_logic_vector(5 downto 0);\r
-signal resetAddr : std_logic;\r
-\r
-signal FifoEmpty : std_logic;\r
-signal debug : std_logic_vector(63 downto 0);\r
-\r
-begin\r
-\r
--- Fakes\r
-debug <= (others => '0');\r
-\r
-\r
-TransmitStateMachineProc : process (TX_MAC_CLK)\r
-begin\r
- if rising_edge(TX_MAC_CLK) then\r
- if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10\r
- transmitCurrentState <= T_IDLE;\r
- else\r
- transmitCurrentState <= transmitNextState;\r
- end if;\r
- end if;\r
-end process TransmitStatemachineProc;\r
-\r
-TransmitStateMachine : process (transmitCurrentState, macCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN)\r
-begin\r
- case transmitCurrentState is\r
- when T_IDLE =>\r
- bsm_trans <= x"0";\r
- if ((START_OF_PACKET_IN = '1') and (macCurrentState = M_IDLE)) then\r
- transmitNextState <= T_TRANSMIT;\r
- else\r
- transmitNextState <= T_IDLE;\r
- end if;\r
- when T_TRANSMIT =>\r
- bsm_trans <= x"1";\r
- if (DATA_ENDFLAG_IN = '1') then\r
- transmitNextState <= T_WAITFORFIFO;\r
- else\r
- transmitNextState <= T_TRANSMIT;\r
- end if;\r
- when T_WAITFORFIFO =>\r
- bsm_trans <= x"2";\r
- if (TX_DONE_IN = '1') then --or (TX_DISCFRM_IN = '1') then\r
- transmitNextState <= T_IDLE;\r
- else\r
- transmitNextState <= T_WAITFORFIFO;\r
- end if;\r
- when others =>\r
- bsm_trans <= x"f";\r
- transmitNextState <= T_IDLE;\r
- end case;\r
-end process TransmitStateMachine;\r
- \r
-FifoAvailProc : process (TX_MAC_CLK)\r
-begin\r
- if rising_edge(TX_MAC_CLK) then\r
- if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10\r
- tx_fifoavail_i <= '0';\r
- elsif (transmitCurrentState = T_TRANSMIT) then\r
- tx_fifoavail_i <= '1';\r
- else\r
- tx_fifoavail_i <= '0';\r
- end if;\r
- end if;\r
-end process FifoAvailProc;\r
-\r
-FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, RESET)\r
-begin\r
- if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10\r
- FifoEmpty <= '1';\r
- elsif (transmitCurrentState = T_WAITFORFIFO) then\r
- FifoEmpty <= '1';\r
- elsif (transmitCurrentState = T_TRANSMIT) then\r
- FifoEmpty <= TX_EMPTY_IN;\r
- elsif (((transmitCurrentState = T_IDLE) or (transmitCurrentState = T_WAITFORFIFO)) and (START_OF_PACKET_IN = '1')) then\r
- FifoEmpty <= '0';\r
- else\r
- FifoEmpty <= '1';\r
- end if;\r
-end process FifoEmptyProc;\r
-\r
-tx_fifoeof_i <= '1' when ((DATA_ENDFLAG_IN = '1') and (transmitCurrentState = T_TRANSMIT)) \r
- else '0';\r
-\r
--- main MAC state machine\r
-MacStateMachineProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if RESET = '1' then\r
- macCurrentState <= M_RESETING;\r
- else\r
- macCurrentState <= macNextState;\r
- end if;\r
- end if;\r
-end process MacStateMachineProc;\r
- \r
-MacStatesMachine: process(macCurrentState, reading_done)\r
-begin\r
- case macCurrentState is\r
- when M_RESETING =>\r
- bsm_mac <= x"0";\r
- macNextState <= M_INIT;\r
- when M_IDLE =>\r
- bsm_mac <= x"1";\r
- macNextState <= M_IDLE;\r
- when M_INIT =>\r
- bsm_mac <= x"2";\r
- if (reading_done = '1') then\r
- macNextState <= M_IDLE;\r
- else\r
- macNextState <= M_INIT;\r
- end if;\r
- when others =>\r
- bsm_mac <= x"f";\r
- macNextState <= M_RESETING;\r
- end case;\r
-end process MacStatesMachine; \r
-\r
-\r
----------------------------------------------------------------------------------\r
----------------------------------------------------------------------------------\r
--- MAC initialization statemachine, memory and address counters\r
----------------------------------------------------------------------------------\r
----------------------------------------------------------------------------------\r
- \r
--- state machine used to initialize MAC registers with data saved in macInitDataInv2.mem via macInitMem\r
-MacInitStateMachineProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if RESET = '1' then\r
- macInitState <= I_IDLE;\r
- else\r
- macInitState <= macInitNextState;\r
- end if;\r
- end if;\r
-end process MacInitStateMachineProc;\r
- \r
-MacInitStateMachine : process (macInitState, macCurrentState, init_done, HREADY_IN, reading_done, HDATA_EN_IN, enabled)\r
-begin \r
- case macInitState is\r
- when I_IDLE => \r
- bsm_init <= x"0";\r
- if (macCurrentState = M_INIT) then\r
- macInitNextState <= I_WRITE;\r
- else\r
- macInitNextState <= I_IDLE;\r
- end if;\r
- when I_INCRADDRESS => \r
- bsm_init <= x"1";\r
- if ((init_done = '0') and (enabled = '0') and (reading_done = '0')) then -- write to regs 2 and up\r
- macInitNextState <= I_PAUSE;\r
- elsif ((init_done = '1') and (enabled = '0') and (reading_done = '0')) then -- write to regs 0 and 1\r
- macInitNextState <= I_PAUSE3;\r
- elsif ((init_done = '1') and (enabled = '1') and (reading_done = '0')) then -- read all regs to fifo\r
- macInitNextState <= I_PAUSE2;\r
- else\r
- macInitNextState <= I_ENDED;\r
- end if;\r
- when I_PAUSE =>\r
- bsm_init <= x"2";\r
- if (HREADY_IN = '1') then\r
- macInitNextState <= I_WRITE; \r
- else\r
- macInitNextState <= I_PAUSE;\r
- end if;\r
- when I_WRITE =>\r
- bsm_init <= x"3";\r
- if (HREADY_IN = '0') then\r
- macInitNextState <= I_INCRADDRESS;\r
- else\r
- macInitNextState <= I_WRITE;\r
- end if; \r
- when I_PAUSE2 =>\r
- bsm_init <= x"4";\r
- if (HREADY_IN = '1') then\r
- macInitNextState <= I_READ;\r
- else\r
- macInitNextState <= I_PAUSE2;\r
- end if;\r
- when I_READ =>\r
- bsm_init <= x"5";\r
- if (HDATA_EN_IN = '0') then\r
- macInitNextState <= I_INCRADDRESS;\r
- else\r
- macInitNextState <= I_READ;\r
- end if;\r
- when I_PAUSE3 =>\r
- bsm_init <= x"6";\r
- if (HREADY_IN = '1') then\r
- macInitNextState <= I_WRITE;\r
- else\r
- macInitNextState <= I_PAUSE3;\r
- end if;\r
- when I_ENDED =>\r
- bsm_init <= x"7";\r
- macInitNextState <= I_ENDED;\r
- when others =>\r
- bsm_init <= x"f";\r
- macInitNextState <= I_IDLE;\r
- end case;\r
-end process MacInitStateMachine;\r
- \r
-addrSig <= addr2 when ((reading_done = '0') and (init_done = '1') and (enabled = '1')) \r
- else macInitMemAddr;\r
-\r
--- initialization ROM\r
-MacInitMemory : mac_init_mem\r
-port map (\r
- Address => macInitMemAddr,\r
- OutClock => CLK,\r
- OutClockEn => macInitMemEn,\r
- Reset => RESET,\r
- Q => macInitMemQ \r
-);\r
- \r
--- MAC ready signal (?)\r
-enabledProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- enabled <= '0';\r
- elsif ((reading_done = '0') and (init_done = '1') and (macInitMemAddr = "000010")) then -- write only to the first register (mode)\r
- enabled <= '1';\r
- elsif (macInitState = I_IDLE) then\r
- enabled <= '0';\r
- end if;\r
- end if;\r
-end process enabledProc;\r
- \r
-add2 : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- addr2 <= "111111";\r
- elsif ((macInitState = I_INCRADDRESS) and (init_done = '1') and (enabled = '1')) then\r
- addr2 <= addr2 + "1";\r
- elsif (macInitState = I_IDLE) then\r
- addr2 <= "111111";\r
- end if;\r
- end if;\r
-end process add2;\r
- \r
-readingDoneProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- reading_done <= '0';\r
- elsif (macInitState = I_IDLE) then\r
- reading_done <= '0';\r
- elsif (addr2 = "110101") then -- read all registers\r
- reading_done <= '1';\r
- end if;\r
- end if;\r
-end process readingDoneProc;\r
-\r
-initDoneProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- init_done <= '0';\r
- elsif (macInitState = I_IDLE) then\r
- init_done <= '0';\r
- elsif (macInitMemAddr = "110101") then -- write to all registers\r
- init_done <= '1';\r
- end if;\r
- end if;\r
-end process initDoneProc;\r
- \r
--- HWRITE signal (registered)\r
-hwriteProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- hwrite_n_i <= '1';\r
- elsif ((macInitState = I_WRITE) and (HREADY_IN = '1')) then\r
- hwrite_n_i <= '0';\r
- else\r
- hwrite_n_i <= '1';\r
- end if;\r
- end if;\r
-end process hwriteProc;\r
- \r
--- HREAD signal (registered)\r
-hreadProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- hread_n_i <= '1';\r
- elsif ((macInitState = I_READ) and (HREADY_IN = '1')) then\r
- hread_n_i <= '0';\r
- else\r
- hread_n_i <= '1';\r
- end if;\r
- end if; \r
-end process hreadProc;\r
- \r
--- HCS signal (registered)\r
-hcsProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- hcs_n_i <= '1';\r
- elsif ((macInitState = I_WRITE) and (HREADY_IN = '1')) then\r
- hcs_n_i <= '0';\r
- elsif ((macInitState = I_READ) and (HREADY_IN = '1')) then\r
- hcs_n_i <= '0';\r
- else\r
- hcs_n_i <= '1';\r
- end if;\r
- end if;\r
-end process hcsProc;\r
- \r
--- address lines for the initialization memory\r
-macInitMemAddrProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- macInitMemAddr <= "000010";\r
- elsif (resetAddr = '1') then\r
- macInitMemAddr <= "000000";\r
- else\r
- if (macInitState = I_INCRADDRESS) then\r
- macInitMemAddr <= macInitMemAddr + "1";\r
- elsif (macInitState = I_IDLE) then\r
- macInitMemAddr <= "000010";\r
- end if;\r
- end if;\r
- end if;\r
-end process macInitMemAddrProc;\r
-\r
--- address counter reset signal (registered)\r
-resetAddrProc : process (CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- resetAddr <= '0';\r
- elsif (macInitState = I_IDLE) then\r
- resetAddr <= '0';\r
- elsif (macInitMemAddr = "110101") then\r
- resetAddr <= '1';\r
- elsif (macInitState = I_PAUSE3) then\r
- resetAddr <= '0';\r
- end if;\r
- end if;\r
-end process resetAddrProc;\r
- \r
-macInitMemEn <= '1' when (macCurrentState = M_INIT) \r
- else '0';\r
-\r
-\r
-\r
--- Outputs\r
-HADDR_OUT <= b"00" & addrSig;\r
-HDATA_OUT <= macInitMemQ;\r
-HCS_OUT <= hcs_n_i;\r
-HWRITE_OUT <= hwrite_n_i;\r
-HREAD_OUT <= hread_n_i;\r
-TX_FIFOAVAIL_OUT <= tx_fifoavail_i;\r
-TX_FIFOEOF_OUT <= tx_fifoeof_i;\r
-TX_FIFOEMPTY_OUT <= FifoEmpty;\r
-\r
-BSM_INIT_OUT <= bsm_init;\r
-BSM_MAC_OUT <= bsm_mac;\r
-BSM_TRANS_OUT <= bsm_trans;\r
-DBG_RD_DONE_OUT <= reading_done;\r
-DBG_INIT_DONE_OUT <= init_done;\r
-DBG_ENABLED_OUT <= enabled;\r
-DEBUG_OUT <= debug;\r
-\r
-end trb_net16_gbe_frame_trans;\r
-\r
-\r
---MAC : tsmac3\r
---port map(\r
--- --------------------------------------------------------------------------\r
--- --------------- clock, reset, clock enable -------------------------------\r
--- hclk => CLK, -- (in) host clock (100MHz)\r
--- txmac_clk => TX_MAC_CLK, -- (in) GbE clock (125MHz)\r
--- rxmac_clk => '0', -- (in) not used (no receiving on GbE)\r
--- reset_n => GSR_N, -- (in) global set/reset\r
--- txmac_clk_en => TSM_TX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation\r
--- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation\r
--- --------------------------------------------------------------------------\r
--- --------------- SGMII receive interface ----------------------------------\r
--- rxd => x"00", -- (in) receive data from SGMII core\r
--- rx_dv => '0', -- (in) data valid from SGMII core\r
--- rx_er => '0', -- (in) receive data error \r
--- col => TSM_COL_IN, -- (in) collision from SGMII core\r
--- crs => TSM_CRS_IN, -- (in) carrier sense from SGMII core\r
--- --------------------------------------------------------------------------\r
--- --------------- SGMII transmit interface ---------------------------------\r
--- txd => CH_TXD_OUT, -- (out) transmit data to SGMII core\r
--- tx_en => CH_TX_EN_OUT, -- (out) transmit enable\r
--- tx_er => CH_TX_ER_OUT, -- (out) transmit error\r
--- --------------------------------------------------------------------------\r
--- --------------- CPU configuration interface ------------------------------\r
--- haddr => haddr, -- (in) host address bus for configuration\r
--- hdatain => hdataout, -- (in) host data bus for write accesses\r
--- hcs_n => hcs, -- (in) host chip select signal\r
--- hwrite_n => hwrite, -- (in) host write strobe signal\r
--- hread_n => hread, -- (in) host read strobe signal\r
--- hdataout => hdatain, -- (out) host data bus for read accesses\r
--- hdataout_en_n => hdataout_en, -- (out) read data valid signal\r
--- hready_n => hready, -- (out) data acknowledge signal \r
--- cpu_if_gbit_en => open, -- (out) status bit \r
--- --------------------------------------------------------------------------\r
--- --------------- Transmit FIFO interface ----------------------------------\r
--- tx_fifodata => ft_data(7 downto 0), -- (in) transmit FIFO data bus\r
--- tx_fifoavail => mac_fifoavail, -- (in) transmit FIFO data available\r
--- tx_fifoeof => mac_fifoeof, -- (in) transmit FIFO end of frame \r
--- tx_fifoempty => mac_fifoempty, -- (in) transmit FIFO empty\r
--- tx_macread => mac_tx_rd_en, -- (out) transmit FIFO read\r
--- tx_done => mac_tx_done, -- (out) transmit done (without errors)\r
--- tx_sndpaustim => x"0000", -- (in) PAUSE frame timer\r
--- tx_sndpausreq => '0', -- (in) PAUSE frame request\r
--- tx_fifoctrl => '0', -- (in) FIFO control frame ('0' = data, '1' = control)\r
--- tx_discfrm => open, -- (out) discard frame\r
--- tx_staten => open, -- (out) transmit statistics vector enable \r
--- tx_statvec => open, -- (out) transmit statistics vector\r
--- --------------------------------------------------------------------------\r
--- --------------- Receive FIFO interface -----------------------------------\r
--- rx_dbout => open, -- (out) receive FIFO data output\r
--- rx_fifo_full => '0', -- (in) receive FIFO full\r
--- ignore_pkt => '0', -- (in) ignore next packet\r
--- rx_fifo_error => open, -- (out) receive FIFO error\r
--- rx_stat_vector => open, -- (out) receive statistics vector\r
--- rx_stat_en => open, -- (out) receive statistics vector enable\r
--- rx_write => open, -- (out) receive FIFO write\r
--- rx_eof => open, -- (out) end of frame\r
--- rx_error => open -- (out) receive packet error\r
---);\r
-\r
-\r
-\r
-\r
-\r
-\r
---MAC : tsmac3\r
---port map(\r
------------------ clock and reset port declarations ------------------\r
--- hclk => LVDS_CLK_200P,\r
--- txmac_clk => TX_MAC_CLK,\r
--- rxmac_clk => '0',\r
--- reset_n => GSR_N, -- done\r
--- txmac_clk_en => TSM_TX_CLK_EN_IN, -- done\r
--- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- done\r
---------------------- Input signals to the GMII ---------------- NOT USED\r
--- rxd => x"00",\r
--- rx_dv => '0',\r
--- rx_er => '0',\r
--- col => TSM_COL_IN, -- done\r
--- crs => TSM_CRS_IN, -- done\r
--- -------------------- Input signals to the CPU I/F -------------------\r
--- haddr(5 downto 0) => addrSig, -- done\r
--- haddr(7 downto 6) => "00",\r
--- hdatain => macInitMemQ, -- done\r
--- hcs_n => hcs_n_i, -- done\r
--- hwrite_n => hwrite_n_i, -- done\r
--- hread_n => hread_n_i, -- done\r
------------------- Input signals to the Tx MAC FIFO I/F ---------------\r
--- tx_fifodata => DATA_IN(7 downto 0), -- done\r
--- tx_fifoavail => tx_fifoavail_i, -- done\r
--- tx_fifoeof => tx_fifoeof_i, -- done\r
--- tx_fifoempty => FifoEmpty, -- done\r
--- tx_sndpaustim => x"0000",\r
--- tx_sndpausreq => '0',\r
--- tx_fifoctrl => '0', -- always data frame\r
------------------- Input signals to the Rx MAC FIFO I/F --------------- \r
--- rx_fifo_full => '0',\r
--- ignore_pkt => '0',\r
----------------------- Output signals from the GMII -----------------------\r
--- txd => CH_TXD_OUT, -- done\r
--- tx_en => CH_TX_EN_OUT, -- done\r
--- tx_er => CH_TX_ER_OUT, -- done\r
----------------------- Output signals from the CPU I/F -------------------\r
--- hdataout => hdataout_i, -- done\r
--- hdataout_en_n => hdataout_en_n_i, -- done\r
--- hready_n => hready_n_i, -- done\r
--- cpu_if_gbit_en => gbe_enabled, -- done\r
------------------- Output signals from the Tx MAC FIFO I/F --------------- \r
--- tx_macread => FifoRd, -- done\r
--- tx_discfrm => tx_discfrm_i, -- not used\r
--- tx_staten => tx_staten_i, -- done\r
--- tx_statvec => tx_statvec_i, -- done\r
--- tx_done => tx_done_i, -- done\r
------------------- Output signals from the Rx MAC FIFO I/F --------------- \r
--- rx_fifo_error => open,\r
--- rx_stat_vector => open,\r
--- rx_dbout => open,\r
--- rx_write => open,\r
--- rx_stat_en => open,\r
--- rx_eof => rx_eof_i, -- done\r
--- rx_error => rx_error_i -- done\r
---);\r
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-use IEEE.std_logic_arith.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.trb_net16_hub_func.all;\r
-\r
-entity trb_net16_gbe_packet_constr is\r
-port(\r
- RESET : in std_logic;\r
- CLK : in std_logic;\r
- -- ports for user logic\r
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic\r
- PC_DATA_IN : in std_logic_vector(7 downto 0);\r
- PC_READY_OUT : out std_logic;\r
- PC_START_OF_SUB_IN : in std_logic;\r
- PC_END_OF_DATA_IN : in std_logic;\r
- -- queue and subevent layer headers\r
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap\r
- PC_PADDING_IN : in std_logic; -- gk 29.03.10\r
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap\r
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap\r
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!\r
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap\r
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP\r
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10\r
- MULT_EVT_ENABLE_IN : in std_logic; -- gk 08.11.10\r
- PC_END_OF_SUB_IN : in std_logic; -- gk 08.10.11\r
- -- FrameConstructor ports\r
- FC_WR_EN_OUT : out std_logic;\r
- FC_DATA_OUT : out std_logic_vector(7 downto 0);\r
- FC_H_READY_IN : in std_logic;\r
- FC_READY_IN : in std_logic;\r
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);\r
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);\r
- FC_IDENT_OUT : out std_logic_vector(15 downto 0);\r
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);\r
- FC_SOD_OUT : out std_logic;\r
- FC_EOD_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
-);\r
-end trb_net16_gbe_packet_constr;\r
-\r
-architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is\r
-\r
--- -- Placer Directives\r
--- attribute HGROUP : string;\r
--- -- for whole architecture\r
--- attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_packet_constr_group";\r
-\r
-component fifo_64kx9\r
-port (\r
- Data : in std_logic_vector(8 downto 0); \r
- WrClock : in std_logic; \r
- RdClock : in std_logic; \r
- WrEn : in std_logic; \r
- RdEn : in std_logic; \r
- Reset : in std_logic; \r
- RPReset : in std_logic; \r
- Q : out std_logic_vector(8 downto 0); \r
- Empty : out std_logic; \r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
--- FIFO for SubEventHeader information\r
--- gk 06.12.10 component fifo_2048x8 is\r
---component fifo_16kx8 is\r
-component fifo_2048x8 is\r
-port (\r
- Data : in std_logic_vector(7 downto 0); \r
- WrClock : in std_logic; \r
- RdClock : in std_logic; \r
- WrEn : in std_logic; \r
- RdEn : in std_logic; \r
- Reset : in std_logic; \r
- RPReset : in std_logic; \r
- Q : out std_logic_vector(7 downto 0); \r
- Empty : out std_logic; \r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
-signal df_wr_en : std_logic;\r
-signal df_rd_en : std_logic;\r
-signal df_q : std_logic_vector(7 downto 0);\r
-signal df_q_reg : std_logic_vector(7 downto 0);\r
-signal df_empty : std_logic;\r
-signal df_full : std_logic;\r
-\r
-signal fc_data : std_logic_vector(7 downto 0);\r
-signal fc_wr_en : std_logic;\r
-signal fc_sod : std_logic;\r
-signal fc_eod : std_logic;\r
-signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter!\r
-signal fc_flags_offset : std_logic_vector(15 downto 0);\r
-\r
-signal shf_data : std_logic_vector(7 downto 0);\r
-signal shf_wr_en : std_logic;\r
-signal shf_rd_en : std_logic;\r
-signal shf_q : std_logic_vector(7 downto 0);\r
-signal shf_empty : std_logic;\r
-signal shf_full : std_logic;\r
-\r
-type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD);\r
-signal constructCurrentState, constructNextState : constructStates;\r
-signal constr_state : std_logic_vector(3 downto 0);\r
-signal all_int_ctr : integer range 0 to 31;\r
-signal all_ctr : std_logic_vector(4 downto 0);\r
-\r
-type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM);\r
-signal saveSubCurrentState, saveSubNextState : saveSubStates;\r
-signal save_state : std_logic_vector(3 downto 0);\r
-signal sub_int_ctr : integer range 0 to 31;\r
-signal sub_ctr : std_logic_vector(4 downto 0);\r
-signal my_int_ctr : integer range 0 to 3;\r
-signal my_ctr : std_logic_vector(1 downto 0);\r
-\r
-type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY);\r
-signal loadCurrentState, loadNextState: loadStates;\r
-signal load_state : std_logic_vector(3 downto 0);\r
-\r
-signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination\r
-signal queue_size_temp : std_logic_vector(31 downto 0);\r
-signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid\r
-signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame\r
-signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf\r
-signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted\r
-signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent \r
-signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet\r
-signal size_left : std_logic_vector(31 downto 0);\r
-signal fc_ip_size : std_logic_vector(15 downto 0);\r
-signal fc_udp_size : std_logic_vector(15 downto 0);\r
-signal max_frame_size : std_logic_vector(15 downto 0);\r
-signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term\r
-signal debug : std_logic_vector(63 downto 0);\r
-signal pc_ready : std_logic;\r
-\r
-signal pc_sub_size : std_logic_vector(31 downto 0);\r
-signal pc_trig_nr : std_logic_vector(31 downto 0);\r
-signal rst_after_sub_comb : std_logic; -- gk 08.04.10\r
-signal rst_after_sub : std_logic; -- gk 08.04.10\r
-signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10\r
-signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10\r
-signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10\r
-\r
--- gk 26.07.10\r
-signal load_eod : std_logic;\r
-signal load_eod_q : std_logic;\r
-\r
--- gk 08.11.11\r
-signal df_eod : std_logic;\r
-\r
--- gk 04.12.10\r
-signal first_sub_in_multi : std_logic;\r
-signal from_divide_state : std_logic;\r
-signal disable_prep : std_logic;\r
-\r
-begin\r
-\r
--- Fakes\r
---debug <= (others => '0');\r
-\r
-my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order\r
-load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10\r
-\r
-all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging\r
-sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging\r
-my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging\r
-\r
-max_frame_size <= PC_MAX_FRAME_SIZE_IN;\r
-\r
--- Ready signal for PacketConstructor\r
-pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0';\r
-\r
--- store event information on Start_of_Subevent\r
-THE_EVT_INFO_STORE_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if (RESET = '1') then -- gk 31.05.10\r
- pc_sub_size <= (others => '0');\r
- pc_trig_nr <= (others => '0');\r
- elsif( PC_START_OF_SUB_IN = '1' ) then\r
- pc_sub_size <= PC_SUB_SIZE_IN;\r
- pc_trig_nr <= PC_TRIG_NR_IN;\r
- end if;\r
- end if;\r
-end process;\r
-\r
--- Data FIFO for incoming packet data from IPU buffer\r
--- gk 26.07.10\r
-DATA_FIFO : fifo_64kx9\r
-port map(\r
- Data(7 downto 0) => PC_DATA_IN,\r
- Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 08.11.10\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => df_wr_en,\r
- RdEn => df_rd_en,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q(7 downto 0) => df_q,\r
- Q(8) => load_eod,\r
- Empty => df_empty,\r
- Full => df_full\r
-);\r
-\r
--- gk 08.11.10\r
-df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1'))\r
- or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1'))\r
- else '0';\r
-\r
-LOAD_EOD_PROC : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- load_eod_q <= '0';\r
- else\r
- load_eod_q <= load_eod;\r
- end if;\r
- end if;\r
-end process LOAD_EOD_PROC;\r
-\r
--- Write enable for the data FIFO\r
--- !!!combinatorial signal!!!\r
--- could be avoided as IPU2GBE does only send data in case of PC_READY.\r
-df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) \r
- else '0';\r
-\r
--- Output register for data FIFO\r
-dfQProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- df_q_reg <= df_q;\r
- end if;\r
-end process dfQProc;\r
-\r
--- Construction state machine\r
-constructMachineProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- constructCurrentState <= CIDLE;\r
- else\r
- constructCurrentState <= constructNextState;\r
- end if;\r
- end if;\r
-end process constructMachineProc;\r
-\r
-constructMachine : process(constructCurrentState, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr)\r
-begin\r
- case constructCurrentState is\r
- when CIDLE =>\r
- constr_state <= x"0";\r
- --if( PC_WR_EN_IN = '1' ) then\r
- -- gk 04.12.10\r
- if (PC_START_OF_SUB_IN = '1') then\r
- constructNextState <= SAVE_DATA;\r
- else\r
- constructNextState <= CIDLE;\r
- end if;\r
- when SAVE_DATA =>\r
- constr_state <= x"1";\r
- if( PC_END_OF_DATA_IN = '1' ) then\r
- constructNextState <= WAIT_FOR_LOAD;\r
- else\r
- constructNextState <= SAVE_DATA;\r
- end if;\r
- when WAIT_FOR_LOAD =>\r
- constr_state <= x"2";\r
- if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted\r
- constructNextState <= CIDLE;\r
- else\r
- constructNextState <= WAIT_FOR_LOAD;\r
- end if;\r
- when others =>\r
- constr_state <= x"f";\r
- constructNextState <= CIDLE;\r
- end case;\r
-end process constructMachine;\r
-\r
---***********************\r
--- SIZE COUNTERS FOR SAVING SIDE\r
---***********************\r
-\r
--- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size\r
--- that's why they are removed if pc_padding flag is asserted\r
-sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0')\r
- else (x"c" + pc_sub_size); -- subevent headers + data\r
-\r
--- BUG HERE BUG HERE BUG HERE BUG HERE\r
--- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents\r
-queueSizeProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
- queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination\r
- elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then\r
- queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers\r
- end if;\r
- end if;\r
-end process queueSizeProc;\r
-\r
---***********************\r
--- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION\r
---***********************\r
-\r
-loadMachineProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- loadCurrentState <= LIDLE;\r
- else\r
- loadCurrentState <= loadNextState;\r
- end if;\r
- end if;\r
-end process loadMachineProc;\r
-\r
-loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty,\r
- sub_bytes_loaded, sub_size_loaded, size_left, FC_H_READY_IN, max_frame_size, \r
- bytes_loaded, divide_position, PC_DELAY_IN, delay_ctr, load_eod_q)\r
-begin\r
- case loadCurrentState is\r
- when LIDLE =>\r
- load_state <= x"0";\r
- if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then\r
- loadNextState <= WAIT_FOR_FC;\r
- else\r
- loadNextState <= LIDLE;\r
- end if;\r
- when WAIT_FOR_FC =>\r
- load_state <= x"1";\r
- if (FC_H_READY_IN = '1') then\r
- loadNextState <= PUT_Q_LEN;\r
- else\r
- loadNextState <= WAIT_FOR_FC;\r
- end if;\r
- when PUT_Q_LEN =>\r
- load_state <= x"2";\r
- if (all_int_ctr = 3) then\r
- loadNextState <= PUT_Q_DEC;\r
- else\r
- loadNextState <= PUT_Q_LEN;\r
- end if;\r
- when PUT_Q_DEC =>\r
- load_state <= x"3";\r
- if (all_int_ctr = 3) then\r
- loadNextState <= LOAD_SUB;\r
- else\r
- loadNextState <= PUT_Q_DEC;\r
- end if;\r
- when LOAD_SUB =>\r
- load_state <= x"4";\r
- if (bytes_loaded = max_frame_size - 1) then\r
- loadNextState <= DIVIDE;\r
- elsif (all_int_ctr = 15) then\r
- loadNextState <= PREP_DATA;\r
- else\r
- loadNextState <= LOAD_SUB;\r
- end if;\r
- when PREP_DATA =>\r
- load_state <= x"5";\r
- loadNextState <= LOAD_DATA;\r
--- when LOAD_DATA =>\r
--- load_state <= x"6";\r
--- if (bytes_loaded = max_frame_size - 1) then\r
--- loadNextState <= DIVIDE;\r
--- -- gk 26.07.10\r
--- -- close packet after one event loaded\r
--- elsif (load_eod_q = '1') then\r
--- loadNextState <= LOAD_TERM;\r
--- -- elsif (sub_bytes_loaded = sub_size_loaded) then -- if all subevent bytes are loaded\r
--- -- if (size_left = x"00000021") then -- and there is no more data, only termination left\r
--- -- -- gk 21.07.10\r
--- -- if (PC_SKIP_TERM_IN = '0') then\r
--- -- loadNextState <= LOAD_TERM; -- add termination and close packet\r
--- -- else\r
--- -- loadNextState <= CLEANUP;\r
--- -- end if;\r
--- -- else -- there is more data in fifo\r
--- -- loadNextState <= LOAD_SUB; -- add another subevent\r
--- -- end if;\r
--- else\r
--- loadNextState <= LOAD_DATA;\r
--- end if;\r
- -- gk 04.12.10\r
- when LOAD_DATA =>\r
- load_state <= x"6";\r
- if (bytes_loaded = max_frame_size - 1) then\r
- loadNextState <= DIVIDE;\r
- -- gk 07.10.10\r
- elsif (load_eod_q = '1') then\r
- if (MULT_EVT_ENABLE_IN = '1') then\r
- if (size_left < x"0000_0030") then\r
- loadNextState <= LOAD_TERM;\r
- else\r
- loadNextState <= LOAD_SUB;\r
- end if;\r
- else\r
- loadNextState <= LOAD_TERM;\r
- end if;\r
- else\r
- loadNextState <= LOAD_DATA;\r
- end if;\r
- when DIVIDE =>\r
- load_state <= x"7";\r
- if (FC_H_READY_IN = '1') then\r
- if (divide_position = "00") then\r
- loadNextState <= PREP_DATA;\r
- elsif (divide_position = "01") then\r
- loadNextState <= LOAD_SUB;\r
- else\r
- loadNextState <= LOAD_TERM;\r
- end if;\r
- else\r
- loadNextState <= DIVIDE;\r
- end if;\r
- when LOAD_TERM =>\r
- load_state <= x"8";\r
- if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then\r
- loadNextState <= DIVIDE;\r
- elsif (all_int_ctr = 31) then\r
- loadNextState <= CLEANUP;\r
- else\r
- loadNextState <= LOAD_TERM;\r
- end if;\r
- -- gk 28.04.10\r
- when CLEANUP =>\r
- load_state <= x"9";\r
- if (PC_DELAY_IN = x"0000_0000") then\r
- loadNextState <= LIDLE;\r
- else\r
- loadNextState <= DELAY;\r
- end if;\r
- -- gk 28.04.10\r
- when DELAY =>\r
- load_state <= x"a";\r
- if (delay_ctr = x"0000_0000") then\r
- loadNextState <= LIDLE;\r
- else\r
- loadNextState <= DELAY;\r
- end if;\r
- when others =>\r
- load_state <= x"f";\r
- loadNextState <= LIDLE;\r
- end case;\r
-end process loadMachine;\r
-\r
--- gk 04.12.10\r
-firstSubInMultiProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LOAD_TERM) then\r
- first_sub_in_multi <= '1';\r
- elsif (loadCurrentState = LOAD_DATA) then\r
- first_sub_in_multi <= '0';\r
- end if;\r
- end if;\r
-end process;\r
-\r
--- gk 04.12.10\r
-fromDivideStateProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- from_divide_state <= '0';\r
- elsif (loadCurrentState = DIVIDE) then\r
- from_divide_state <= '1';\r
- elsif (loadCurrentState = PREP_DATA) then\r
- from_divide_state <= '0';\r
- end if;\r
- end if;\r
-end process fromDivideStateProc;\r
-\r
-dividePositionProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- divide_position <= "00";\r
- elsif (bytes_loaded = max_frame_size - 1) then\r
- if (loadCurrentState = LIDLE) then\r
- divide_position <= "00";\r
- disable_prep <= '0'; -- gk 05.12.10\r
- elsif (loadCurrentState = LOAD_DATA) then\r
- -- gk 05.12.10\r
- -- gk 26.07.10\r
- if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term\r
- divide_position <= "11";\r
- disable_prep <= '0'; -- gk 05.12.10\r
- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then\r
- if (size_left > x"0000_0028") then\r
- divide_position <= "01";\r
- disable_prep <= '0'; -- gk 05.12.10\r
- else\r
- divide_position <= "11";\r
- disable_prep <= '0'; -- gk 05.12.10\r
- end if;\r
- else\r
- divide_position <= "00"; -- still data loaded divide on data\r
- disable_prep <= '1'; -- gk 05.12.10\r
- end if;\r
- elsif (loadCurrentState = LOAD_SUB) then\r
- if (all_int_ctr = 15) then\r
- divide_position <= "00";\r
- disable_prep <= '1'; -- gk 05.12.10\r
- else\r
- divide_position <= "01";\r
- disable_prep <= '0'; -- gk 05.12.10\r
- end if;\r
- elsif (loadCurrentState = LOAD_TERM) then\r
- divide_position <= "11";\r
- disable_prep <= '0'; -- gk 05.12.10\r
- end if;\r
- elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep\r
- disable_prep <= '0';\r
- end if;\r
- end if;\r
-end process dividePositionProc;\r
-\r
-allIntCtrProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then -- gk 31.05.10\r
- all_int_ctr <= 0;\r
- else\r
- case loadCurrentState is\r
- \r
- when LIDLE => all_int_ctr <= 0;\r
- \r
- when WAIT_FOR_FC => all_int_ctr <= 0;\r
- \r
- when PUT_Q_LEN =>\r
- if (all_int_ctr = 3) then\r
- all_int_ctr <= 0;\r
- else\r
- all_int_ctr <= all_int_ctr + 1;\r
- end if;\r
- \r
- when PUT_Q_DEC =>\r
- if (all_int_ctr = 3) then\r
- all_int_ctr <= 0;\r
- else\r
- all_int_ctr <= all_int_ctr + 1;\r
- end if;\r
- \r
- when LOAD_SUB =>\r
- if (all_int_ctr = 15) then\r
- all_int_ctr <= 0;\r
- else\r
- all_int_ctr <= all_int_ctr + 1;\r
- end if;\r
- \r
- when LOAD_DATA => all_int_ctr <= 0;\r
- \r
- when LOAD_TERM =>\r
- if (all_int_ctr = 31) then\r
- all_int_ctr <= 0;\r
- else\r
- all_int_ctr <= all_int_ctr + 1;\r
- end if;\r
- \r
- when DIVIDE => null; --all_int_ctr <= all_int_ctr;\r
- \r
- when CLEANUP => all_int_ctr <= 0;\r
- \r
- when PREP_DATA => all_int_ctr <= 0;\r
- \r
- when DELAY => all_int_ctr <= 0;\r
- end case;\r
- end if;\r
- end if;\r
-end process allIntCtrProc;\r
-\r
-dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, \r
- sub_size_loaded, all_int_ctr, RESET, load_eod, load_eod_q)\r
-begin\r
- if (RESET = '1') then -- gk 31.05.10\r
- df_rd_en <= '0';\r
- elsif (loadCurrentState = LOAD_DATA) then\r
--- if (bytes_loaded >= max_frame_size - x"1") then\r
--- df_rd_en <= '0';\r
--- elsif (sub_bytes_loaded >= sub_size_loaded) then\r
--- df_rd_en <= '0';\r
- if (bytes_loaded = max_frame_size - x"1") then\r
- df_rd_en <= '0';\r
- -- gk 26.07.10\r
- --elsif (load_eod = '1') or (load_eod_q = '1') then\r
- elsif (load_eod_q = '1') then\r
- df_rd_en <= '0';\r
--- elsif (sub_bytes_loaded = sub_size_loaded) then\r
--- df_rd_en <= '0';\r
- else\r
- df_rd_en <= '1';\r
- end if;\r
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then\r
- df_rd_en <= '1';\r
- elsif (loadCurrentState = PREP_DATA) then\r
- df_rd_en <= '1';\r
- else\r
- df_rd_en <= '0';\r
- end if;\r
-end process dfRdEnProc;\r
-\r
-shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET)\r
-begin\r
- if (RESET = '1') then -- gk 31.05.10\r
- shf_rd_en <= '0';\r
- elsif (loadCurrentState = LOAD_SUB) then\r
- shf_rd_en <= '1';\r
- elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then\r
- shf_rd_en <= '1';\r
- elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then\r
- shf_rd_en <= '1';\r
- else\r
- shf_rd_en <= '0';\r
- end if;\r
-end process shfRdEnProc;\r
-\r
-\r
-fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep)\r
-begin\r
- if (RESET = '1') then -- gk 31.05.10\r
- fc_wr_en <= '0';\r
- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then\r
- fc_wr_en <= '1';\r
- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then\r
- fc_wr_en <= '1';\r
- -- gk 04.12.10\r
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then\r
- fc_wr_en <= '1';\r
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then\r
- fc_wr_en <= '1';\r
- else\r
- fc_wr_en <= '0';\r
- end if;\r
-end process fcWrEnProc;\r
-\r
--- was all_int_ctr\r
-fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr)\r
-begin\r
- case loadCurrentState is\r
- when LIDLE => fc_data <= x"af";\r
- when WAIT_FOR_FC => fc_data <= x"bf";\r
- -- gk 08.04.10 my_int_ctr changed to load_int_ctr\r
- when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8);\r
- when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8);\r
- when LOAD_SUB => fc_data <= shf_q;\r
- when PREP_DATA => fc_data <= df_q_reg;\r
- when LOAD_DATA => fc_data <= df_q_reg;\r
- when LOAD_TERM => fc_data <= shf_q;\r
- when DIVIDE => fc_data <= x"cf";\r
- when CLEANUP => fc_data <= x"df";\r
- when others => fc_data <= x"00";\r
- end case;\r
-end process fcDataProc;\r
-\r
--- delay counters\r
--- gk 28.04.10\r
-DELAY_CTR_PROC : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if ((RESET = '1') or (loadCurrentState = LIDLE)) then\r
- delay_ctr <= PC_DELAY_IN;\r
- elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then\r
- delay_ctr <= delay_ctr - x"1";\r
- end if;\r
- end if;\r
-end process DELAY_CTR_PROC;\r
-\r
--- gk 28.04.10\r
-TICKS_CTR_PROC : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then\r
- ticks_ctr <= x"00";\r
- elsif (loadCurrentState = DELAY) then\r
- ticks_ctr <= ticks_ctr + x"1";\r
- end if;\r
- end if;\r
-end process TICKS_CTR_PROC;\r
-\r
-\r
---***********************\r
--- SIZE COUNTERS FOR LOADING SIDE\r
---***********************\r
-\r
-queue_size_temp <= queue_size - x"20"; -- size of data without termination\r
-\r
--- gk 08.04.10\r
-rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or\r
- ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) \r
- else '0';\r
-\r
--- gk 08.04.10\r
-RST_AFTER_SUB_PROC : process(CLK)\r
-begin\r
- if(rising_edge(CLK)) then\r
- if(RESET = '1') then\r
- rst_after_sub <= '0';\r
- else\r
- rst_after_sub <= rst_after_sub_comb;\r
- end if;\r
- end if;\r
-end process RST_AFTER_SUB_PROC;\r
-\r
--- counts all bytes loaded to divide data into frames\r
-bytesLoadedProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then\r
- bytes_loaded <= x"0000";\r
- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then\r
- bytes_loaded <= bytes_loaded + x"1";\r
- -- gk 05.12.10\r
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then\r
--- bytes_loaded <= bytes_loaded + x"1";\r
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then\r
- bytes_loaded <= bytes_loaded + x"1";\r
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then\r
- bytes_loaded <= bytes_loaded + x"1";\r
- end if;\r
- end if;\r
-end process bytesLoadedProc;\r
-\r
--- size of subevent loaded from memory\r
-subSizeLoadedProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10\r
- sub_size_loaded <= x"00000000";\r
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then\r
- -- was all_int_ctr\r
- -- gk 08.04.10 my_int_ctr changed to load_int_ctr\r
- sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q;\r
- -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo\r
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then\r
- sub_size_loaded <= sub_size_loaded + x"4";\r
- end if;\r
- end if;\r
-end process subSizeLoadedProc;\r
-\r
--- counts only raw data bytes being loaded\r
-subBytesLoadedProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10\r
- sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count\r
- elsif (loadCurrentState = LOAD_DATA) then\r
- sub_bytes_loaded <= sub_bytes_loaded + x"1";\r
- end if;\r
- end if;\r
-end process subBytesLoadedProc;\r
-\r
--- counts the size of the large udp packet\r
-actualPacketProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
- actual_packet_size <= x"0008";\r
- elsif (fc_wr_en = '1') then\r
- actual_packet_size <= actual_packet_size + x"1";\r
- end if;\r
- end if;\r
-end process actualPacketProc;\r
-\r
-actualQueueSizeProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
- actual_queue_size <= (others => '0');\r
- elsif (loadCurrentState = LIDLE) then\r
- actual_queue_size <= queue_size;\r
- end if;\r
- end if;\r
-end process actualQueueSizeProc;\r
-\r
--- amount of bytes left to send in current packet\r
-sizeLeftProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
- size_left <= (others => '0');\r
- elsif (loadCurrentState = LIDLE) then\r
- size_left <= queue_size;\r
- elsif (fc_wr_en = '1') then\r
- size_left <= size_left - 1;\r
- end if;\r
- end if;\r
-end process sizeLeftProc;\r
-\r
--- HOT FIX: don't rely on CTS information, count the packets on your own.\r
--- In this case, we increment the fragmented packet ID with EOD from ipu2gbe.\r
-THE_FC_IDENT_COUNTER_PROC: process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- fc_ident <= (others => '0');\r
- elsif (PC_END_OF_DATA_IN = '1') then\r
- fc_ident <= fc_ident + 1;\r
- end if;\r
- end if;\r
-end process THE_FC_IDENT_COUNTER_PROC;\r
-\r
-fc_flags_offset(15 downto 14) <= "00";\r
-\r
-moreFragmentsProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
- fc_flags_offset(13) <= '0';\r
- elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then\r
- if ((actual_queue_size - actual_packet_size) < max_frame_size) then\r
- fc_flags_offset(13) <= '0'; -- no more fragments\r
- else\r
- fc_flags_offset(13) <= '1'; -- more fragments\r
- end if;\r
- end if;\r
- end if;\r
-end process moreFragmentsProc;\r
-\r
-eodProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- fc_eod <= '0';\r
- elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then\r
- fc_eod <= '1';\r
- elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then\r
- fc_eod <= '1';\r
- elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then\r
- fc_eod <= '1';\r
- else\r
- fc_eod <= '0';\r
- end if;\r
- end if;\r
-end process eodProc;\r
-\r
-sodProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- fc_sod <= '0';\r
- elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then\r
- fc_sod <= '1';\r
- elsif (loadCurrentState = DIVIDE) and (FC_READY_IN = '1') then\r
- fc_sod <= '1';\r
- else\r
- fc_sod <= '0';\r
- end if;\r
- end if;\r
-end process sodProc;\r
-\r
-offsetProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
- fc_flags_offset(12 downto 0) <= (others => '0');\r
- elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) then\r
- fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3);\r
- end if;\r
- end if;\r
-end process offsetProc;\r
-\r
-fcIPSizeProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET= '1') then\r
- fc_ip_size <= (others => '0');\r
- elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then\r
- if (size_left >= max_frame_size) then\r
- fc_ip_size <= max_frame_size;\r
- else\r
- fc_ip_size <= size_left(15 downto 0);\r
- end if;\r
- end if;\r
- end if;\r
-end process fcIPSizeProc;\r
-\r
-fcUDPSizeProc : process(CLK)\r
- begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- fc_udp_size <= (others => '0');\r
- elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then\r
- fc_udp_size <= queue_size(15 downto 0);\r
- end if;\r
- end if;\r
-end process fcUDPSizeProc;\r
-\r
-\r
---***********************\r
--- SUBEVENT HEADERS WRITE AND READ\r
---***********************\r
-\r
---SUBEVENT_HEADERS_FIFO : fifo_16kx8 -- gk 06.12.10 fifo_2048x8\r
-SUBEVENT_HEADERS_FIFO : fifo_2048x8\r
-port map(\r
- Data => shf_data,\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => shf_wr_en,\r
- RdEn => shf_rd_en,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q => shf_q,\r
- Empty => shf_empty,\r
- Full => shf_full\r
-);\r
-\r
--- write enable for SHF \r
-shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA))\r
- else '0';\r
-\r
--- data multiplexing for SHF (convert 32bit LWs to 8bit)\r
--- CHANGED. \r
--- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC.\r
-shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, \r
- pc_trig_nr, my_int_ctr, fc_data)\r
-begin\r
- case saveSubCurrentState is\r
- when SIDLE => shf_data <= x"ac";\r
- when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
- when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
- when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
- when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
- when SAVE_TERM => shf_data <= fc_data;\r
- when others => shf_data <= x"00";\r
- end case;\r
-end process shfDataProc;\r
-\r
-saveSubMachineProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') then\r
- saveSubCurrentState <= SIDLE;\r
- else\r
- saveSubCurrentState <= saveSubNextState;\r
- end if;\r
- end if;\r
-end process saveSubMachineProc;\r
-\r
-saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, FC_H_READY_IN)\r
-begin\r
- case saveSubCurrentState is\r
- when SIDLE =>\r
- save_state <= x"0";\r
- if (PC_START_OF_SUB_IN = '1') then\r
- saveSubNextState <= SAVE_SIZE;\r
- -- this branch is dangerous!\r
- elsif (loadCurrentState = WAIT_FOR_FC) and (FC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len\r
- saveSubNextState <= SAVE_TERM;\r
- else\r
- saveSubNextState <= SIDLE;\r
- end if;\r
- when SAVE_SIZE =>\r
- save_state <= x"1";\r
- if (sub_int_ctr = 3) then\r
- saveSubNextState <= SAVE_DECODING;\r
- else\r
- saveSubNextState <= SAVE_SIZE;\r
- end if;\r
- when SAVE_DECODING =>\r
- save_state <= x"2";\r
- if (sub_int_ctr = 3) then\r
- saveSubNextState <= SAVE_ID;\r
- else\r
- saveSubNextState <= SAVE_DECODING;\r
- end if;\r
- when SAVE_ID =>\r
- save_state <= x"3";\r
- if (sub_int_ctr = 3) then\r
- saveSubNextState <= SAVE_TRIG_NR;\r
- else\r
- saveSubNextState <= SAVE_ID;\r
- end if;\r
- when SAVE_TRIG_NR =>\r
- save_state <= x"4";\r
- if (sub_int_ctr = 3) then\r
- saveSubNextState <= SIDLE;\r
- else\r
- saveSubNextState <= SAVE_TRIG_NR;\r
- end if;\r
- when SAVE_TERM =>\r
- save_state <= x"5";\r
- if (sub_int_ctr = 31) then\r
- saveSubNextState <= SIDLE;\r
- else\r
- saveSubNextState <= SAVE_TERM;\r
- end if;\r
- when others =>\r
- save_state <= x"f";\r
- saveSubNextState <= SIDLE;\r
- end case;\r
-end process;\r
-\r
--- This counter is used for breaking down 32bit information words into 8bit bytes for \r
--- storing them in the SHF.\r
--- It is also used for the termination 32byte sequence.\r
-subIntProc: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1') or (saveSubCurrentState = SIDLE) then\r
- sub_int_ctr <= 0;\r
- elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then\r
- sub_int_ctr <= 0;\r
- elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then\r
- sub_int_ctr <= 0;\r
- elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then\r
- sub_int_ctr <= sub_int_ctr + 1;\r
- end if;\r
- end if;\r
-end process subIntProc;\r
-\r
-debug(3 downto 0) <= constr_state;\r
-debug(7 downto 4) <= save_state;\r
-debug(11 downto 8) <= load_state;\r
-debug(27 downto 12) <= queue_size(15 downto 0);\r
-debug(28) <= df_full;\r
-debug(29) <= df_empty;\r
-debug(30) <= shf_full;\r
-debug(31) <= shf_empty;\r
-\r
-debug(47 downto 32) <= size_left(15 downto 0);\r
-debug(52 downto 48) <= all_ctr;\r
-debug(53) <= pc_ready;\r
-\r
--- outputs\r
-PC_READY_OUT <= pc_ready;\r
-FC_WR_EN_OUT <= fc_wr_en;\r
-FC_DATA_OUT <= fc_data;\r
-FC_IP_SIZE_OUT <= fc_ip_size;\r
-FC_UDP_SIZE_OUT <= fc_udp_size;\r
-FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0);\r
-FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8);\r
-FC_FLAGS_OFFSET_OUT <= fc_flags_offset;\r
-FC_SOD_OUT <= fc_sod;\r
-FC_EOD_OUT <= fc_eod;\r
-\r
-DEBUG_OUT <= debug;\r
-\r
-end trb_net16_gbe_packet_constr;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
---use work.version.all;
-
-
-entity gbe_setup is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
-
- -- interface to regio bus
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
-
- -- gk 26.04.10
- -- input from gbe_buf (only to return the whole trigger number via regio)
- GBE_TRIG_NR_IN : in std_logic_vector(31 downto 0);
-
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0);
- GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_MAX_PACKET_OUT : out std_logic_vector(31 downto 0);
- GBE_MIN_PACKET_OUT : out std_logic_vector(31 downto 0);
- GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0);
- GBE_USE_GBE_OUT : out std_logic;
- GBE_USE_TRBNET_OUT : out std_logic;
- GBE_USE_MULTIEVENTS_OUT : out std_logic;
- GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10
- GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10
- GBE_DELAY_OUT : out std_logic_vector(31 downto 0);
- GBE_ALLOW_LARGE_OUT : out std_logic;
- GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10
- -- gk 28.07.10
- MONITOR_BYTES_IN : in std_logic_vector(31 downto 0);
- MONITOR_SENT_IN : in std_logic_vector(31 downto 0);
- MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0);
- MONITOR_SM_IN : in std_logic_vector(31 downto 0);
- MONITOR_LR_IN : in std_logic_vector(31 downto 0);
- MONITOR_HDR_IN : in std_logic_vector(31 downto 0);
- MONITOR_FIFOS_IN : in std_logic_vector(31 downto 0);
- MONITOR_DISCFRM_IN : in std_logic_vector(31 downto 0);
- MONITOR_LINK_DWN_IN : in std_logic_vector(31 downto 0); -- gk 30.09.10
- MONITOR_EMPTY_IN : in std_logic_vector(31 downto 0); -- gk 01.10.10
- -- gk 01.06.10
- DBG_IPU2GBE1_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE2_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE3_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE4_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE5_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE6_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE7_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE8_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE9_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE10_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE11_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE12_IN : in std_logic_vector(31 downto 0);
- DBG_PC1_IN : in std_logic_vector(31 downto 0);
- DBG_PC2_IN : in std_logic_vector(31 downto 0);
- DBG_FC1_IN : in std_logic_vector(31 downto 0);
- DBG_FC2_IN : in std_logic_vector(31 downto 0);
- DBG_FT1_IN : in std_logic_vector(31 downto 0);
- DBG_FT2_IN : in std_logic_vector(31 downto 0);
- DBG_FIFO_RD_EN_OUT : out std_logic;
- DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0)
- --DBG_RESET_FIFO_OUT : out std_logic -- gk 28.09.10
-);
-end entity;
-
-architecture gbe_setup of gbe_setup is
-
--- -- Placer Directives
--- attribute HGROUP : string;
--- -- for whole architecture
--- attribute HGROUP of gbe_setup : architecture is "GBE_conf_group";
-
-signal reset_values : std_logic;
-
-signal subevent_id : std_logic_vector(31 downto 0);
-signal subevent_dec : std_logic_vector(31 downto 0);
-signal queue_dec : std_logic_vector(31 downto 0);
-signal max_packet : std_logic_vector(31 downto 0);
-signal min_packet : std_logic_vector(31 downto 0); -- gk 07.20.10
-signal max_frame : std_logic_vector(15 downto 0);
-signal use_gbe : std_logic;
-signal use_trbnet : std_logic;
-signal use_multievents : std_logic;
-signal readout_ctr : std_logic_vector(23 downto 0); -- gk 26.04.10
-signal readout_ctr_valid : std_logic; -- gk 26.04.10
-signal ack : std_logic; -- gk 26.04.10
-signal ack_q : std_logic; -- gk 26.04.10
-signal data_out : std_logic_vector(31 downto 0); -- gk 26.04.10
-signal delay : std_logic_vector(31 downto 0); -- gk 28.04.10
-signal allow_large : std_logic; -- gk 21.07.10
-signal reset_fifo : std_logic; -- gk 28.09.10
-signal frame_delay : std_logic_vector(31 downto 0); -- gk 09.12.10
-
-begin
-
-OUT_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- GBE_SUBEVENT_ID_OUT <= subevent_id;
- GBE_SUBEVENT_DEC_OUT <= subevent_dec;
- GBE_QUEUE_DEC_OUT <= queue_dec;
- GBE_MAX_PACKET_OUT <= max_packet;
- GBE_MIN_PACKET_OUT <= min_packet;
- GBE_MAX_FRAME_OUT <= max_frame;
- GBE_USE_GBE_OUT <= use_gbe;
- GBE_USE_TRBNET_OUT <= use_trbnet;
- GBE_USE_MULTIEVENTS_OUT <= use_multievents;
- GBE_READOUT_CTR_OUT <= readout_ctr; -- gk 26.04.10
- GBE_READOUT_CTR_VALID_OUT <= readout_ctr_valid; -- gk 26.04.10
- BUS_ACK_OUT <= ack_q; -- gk 26.04.10
- ack_q <= ack; -- gk 26.04.10
- BUS_DATA_OUT <= data_out; -- gk 26.04.10
- GBE_DELAY_OUT <= delay; -- gk 28.04.10
- GBE_ALLOW_LARGE_OUT <= allow_large; -- gk 21.07.10
- --DBG_RESET_FIFO_OUT <= reset_fifo; -- gk 28.09.10
- GBE_FRAME_DELAY_OUT <= frame_delay; -- gk 09.12.10
- end if;
-end process OUT_PROC;
-
--- gk 26.04.10
-ACK_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- ack <= '0';
- elsif ((BUS_WRITE_EN_IN = '1') or (BUS_READ_EN_IN = '1')) then
- ack <= '1';
- else
- ack <= '0';
- end if;
- end if;
-end process ACK_PROC;
-
-WRITE_PROC : process(CLK)
-begin
- DBG_FIFO_RD_EN_OUT <= '0';
-
- if rising_edge(CLK) then
- if ( (RESET = '1') or (reset_values = '1') ) then
- subevent_id <= x"0000_00cf";
- subevent_dec <= x"0002_0001";
- queue_dec <= x"0003_0062";
- max_packet <= x"0000_ea60"; --x"0000_fde8"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester
- min_packet <= x"0000_0007"; -- gk 20.07.10
- max_frame <= x"0578";
- use_gbe <= '0'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured
- use_trbnet <= '0';
- use_multievents <= '0';
- reset_values <= '0';
- readout_ctr <= x"00_0000"; -- gk 26.04.10 -- gk 07.06.10 corrected bug found by Sergey
- readout_ctr_valid <= '0'; -- gk 26.04.10
- delay <= x"0000_0000"; -- gk 28.04.10
- DBG_FIFO_RD_EN_OUT <= '0';
- allow_large <= '0'; -- gk 21.07.10
- reset_fifo <= '0'; -- gk 28.09.10
- frame_delay <= x"0000_0000"; -- gk 09.12.10
-
- elsif (BUS_WRITE_EN_IN = '1') then
- case BUS_ADDR_IN is
-
- when x"00" =>
- subevent_id <= BUS_DATA_IN;
-
- when x"01" =>
- subevent_dec <= BUS_DATA_IN;
-
- when x"02" =>
- queue_dec <= BUS_DATA_IN;
-
- when x"03" =>
- max_packet <= BUS_DATA_IN;
-
- when x"04" =>
- max_frame <= BUS_DATA_IN(15 downto 0);
-
- when x"05" =>
- if (BUS_DATA_IN = x"0000_0000") then
- use_gbe <= '0';
- else
- use_gbe <= '1';
- end if;
-
- when x"06" =>
- if (BUS_DATA_IN = x"0000_0000") then
- use_trbnet <= '0';
- else
- use_trbnet <= '1';
- end if;
-
- when x"07" =>
- if (BUS_DATA_IN = x"0000_0000") then
- use_multievents <= '0';
- else
- use_multievents <= '1';
- end if;
-
- -- gk 26.04.10
- when x"08" =>
- readout_ctr <= BUS_DATA_IN(23 downto 0);
- readout_ctr_valid <= '1';
-
- -- gk 28.04.10
- when x"09" =>
- delay <= BUS_DATA_IN;
-
- when x"0a" =>
- DBG_FIFO_RD_EN_OUT <= '1';
-
- -- gk 20.07.10
- when x"0b" =>
- min_packet <= BUS_DATA_IN;
-
- -- gk 21.07.10
- when x"0c" =>
- if (BUS_DATA_IN = x"0000_0000") then
- allow_large <= '0';
- else
- allow_large <= '1';
- end if;
-
- -- gk 09.12.10
- when x"0d" =>
- frame_delay <= BUS_DATA_IN;
-
- -- gk 28.09.10
- when x"fe" =>
- if (BUS_DATA_IN = x"ffff_ffff") then
- reset_fifo <= '1';
- else
- reset_fifo <= '0';
- end if;
-
- when x"ff" =>
- if (BUS_DATA_IN = x"ffff_ffff") then
- reset_values <= '1';
- else
- reset_values <= '0';
- end if;
-
- when others =>
- subevent_id <= subevent_id;
- subevent_dec <= subevent_dec;
- queue_dec <= queue_dec;
- max_packet <= max_packet;
- min_packet <= min_packet;
- max_frame <= max_frame;
- use_gbe <= use_gbe;
- use_trbnet <= use_trbnet;
- use_multievents <= use_multievents;
- reset_values <= reset_values;
- readout_ctr <= readout_ctr; -- gk 26.04.10
- readout_ctr_valid <= readout_ctr_valid; -- gk 26.04.10
- delay <= delay; -- gk 28.04.10
- DBG_FIFO_RD_EN_OUT <= '0';
- allow_large <= allow_large;
- reset_fifo <= reset_fifo; -- gk 28.09.10
- frame_delay <= frame_delay;
- end case;
- else
- reset_values <= '0';
- readout_ctr_valid <= '0'; -- gk 26.04.10
- --reset_fifo <= '0'; -- gk 28.09.10
- end if;
- end if;
-end process WRITE_PROC;
-
--- gk 26.04.10
-READ_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- data_out <= (others => '0');
- elsif (BUS_READ_EN_IN = '1') then
- case BUS_ADDR_IN is
-
- when x"00" =>
- data_out <= subevent_id;
-
- when x"01" =>
- data_out <= subevent_dec;
-
- when x"02" =>
- data_out <= queue_dec;
-
- when x"03" =>
- data_out <= max_packet;
-
- when x"04" =>
- data_out(15 downto 0) <= max_frame;
- data_out(31 downto 16) <= (others => '0');
-
- when x"05" =>
- if (use_gbe = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- when x"06" =>
- if (use_trbnet = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- when x"07" =>
- if (use_multievents = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- when x"08" =>
- data_out <= GBE_TRIG_NR_IN;
-
- when x"09" =>
- data_out <= delay;
-
- when x"0b" =>
- data_out <= min_packet;
-
- -- gk 21.07.10
- when x"0c" =>
- if (allow_large = '0') then
- data_out <= x"0000_0000";
- else
- data_out <= x"0000_0001";
- end if;
-
- -- gk 09.12.10
- when x"0d" =>
- data_out <= frame_delay;
-
- -- gk 01.06.10
- when x"e0" =>
- data_out <= DBG_IPU2GBE1_IN;
-
- when x"e1" =>
- data_out <= DBG_IPU2GBE2_IN;
-
- when x"e2" =>
- data_out <= DBG_PC1_IN;
-
- when x"e3" =>
- data_out <= DBG_PC2_IN;
-
- when x"e4" =>
- data_out <= DBG_FC1_IN;
-
- when x"e5" =>
- data_out <= DBG_FC2_IN;
-
- when x"e6" =>
- data_out <= DBG_FT1_IN;
-
- when x"e7" =>
- data_out <= DBG_FT2_IN;
-
- when x"e8" =>
- data_out(15 downto 0) <= DBG_FIFO_Q_IN;
- data_out(31 downto 16) <= (others => '0');
-
- when x"e9" =>
- data_out <= DBG_IPU2GBE3_IN;
-
- when x"ea" =>
- data_out <= DBG_IPU2GBE4_IN;
-
- when x"eb" =>
- data_out <= DBG_IPU2GBE5_IN;
-
- when x"ec" =>
- data_out <= DBG_IPU2GBE6_IN;
-
- when x"ed" =>
- data_out <= DBG_IPU2GBE7_IN;
-
- when x"ee" =>
- data_out <= DBG_IPU2GBE8_IN;
-
- when x"ef" =>
- data_out <= DBG_IPU2GBE9_IN;
-
- when x"f0" =>
- data_out <= DBG_IPU2GBE10_IN;
-
- when x"f1" =>
- data_out <= DBG_IPU2GBE11_IN;
-
- when x"f2" =>
- data_out <= DBG_IPU2GBE12_IN;
-
- when x"f3" =>
- data_out <= MONITOR_BYTES_IN;
-
- when x"f4" =>
- data_out <= MONITOR_SENT_IN;
-
- when x"f5" =>
- data_out <= MONITOR_DROPPED_IN;
-
- when x"f6" =>
- data_out <= MONITOR_SM_IN;
-
- when x"f7" =>
- data_out <= MONITOR_LR_IN;
-
- when x"f8" =>
- data_out <= MONITOR_HDR_IN;
-
- when x"f9" =>
- data_out <= MONITOR_FIFOS_IN;
-
- when x"fa" =>
- data_out <= MONITOR_DISCFRM_IN;
-
- when x"fb" =>
- data_out <= MONITOR_LINK_DWN_IN;
-
- when x"fc" =>
- data_out <= MONITOR_EMPTY_IN;
-
- when others =>
- data_out <= (others => '0');
- end case;
- end if;
- end if;
-end process READ_PROC;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-
-entity trb_net16_ipu2gbe is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
- MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- -- PacketConstructor interface
- ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic; -- gk 08.11.10
- PC_EOD_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_PADDING_OUT : out std_logic;
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
-);
-end entity;
-
-architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is
-
--- -- Placer Directives
--- attribute HGROUP : string;
--- -- for whole architecture
--- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe_group";
-
-component fifo_32kx16x8_mb2
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(8 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0);
- Empty : out std_logic;
- AlmostEmpty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
-);
-end component;
-
-type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE);
-signal saveCurrentState, saveNextState : saveStates;
-signal state : std_logic_vector(3 downto 0);
-signal data_req_comb : std_logic;
-signal data_req : std_logic; -- request data signal, will be used for fee_read generation
-signal rst_saved_ctr_comb : std_logic;
-signal rst_saved_ctr : std_logic;
-
-signal fee_read_comb : std_logic;
-signal fee_read : std_logic; -- fee_read signal
-signal saved_ctr : std_logic_vector(16 downto 0);
-signal ce_saved_ctr : std_logic;
-
--- header data
-signal cts_rnd : std_logic_vector(15 downto 0);
-signal cts_rnd_saved : std_logic;
-signal cts_trg : std_logic_vector(15 downto 0);
-signal cts_trg_saved : std_logic;
-signal cts_len : std_logic_vector(16 downto 0);
-signal cts_len_saved : std_logic;
-
--- CTS interface
-signal cts_error_pattern : std_logic_vector(31 downto 0);
-signal cts_length : std_logic_vector(15 downto 0);
-signal cts_readout_finished : std_logic;
-signal cts_dataready : std_logic;
-signal cts_data : std_logic_vector(31 downto 0);
-
--- Split FIFO signals
-signal sf_data : std_logic_vector(15 downto 0);
-signal sf_wr_en_comb : std_logic;
-signal sf_wr_en : std_logic; -- write signal for FIFO
-signal sf_rd_en_comb : std_logic;
-signal sf_rd_en : std_logic; -- read signal for FIFO
-signal sf_wcnt : std_logic_vector(15 downto 0);
-signal sf_rcnt : std_logic_vector(16 downto 0);
-signal sf_empty : std_logic;
-signal sf_aempty : std_logic;
-signal sf_full : std_logic;
-signal sf_afull : std_logic;
-
--------------------------------------------------------------------
-type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2);
-signal loadCurrentState, loadNextState : loadStates;
-signal state2 : std_logic_vector(3 downto 0);
-
-signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data
-signal rst_rem_ctr_comb : std_logic;
-signal rst_rem_ctr : std_logic; -- reset the remove counter
-signal rst_regs_comb : std_logic;
-signal rst_regs : std_logic; -- reset storage registers
-signal rem_phase_comb : std_logic;
-signal rem_phase : std_logic; -- header remove phase
-signal data_phase_comb : std_logic;
-signal data_phase : std_logic; -- data transport phase from split fifo to PC
-signal pad_phase_comb : std_logic;
-signal pad_phase : std_logic; -- padding phase
-signal calc_pad_comb : std_logic;
-signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE
-signal pad_data_comb : std_logic;
-signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value
-
-signal pc_sos_comb : std_logic;
-signal pc_sos : std_logic; -- start of data signal
-signal pc_eod_comb : std_logic;
-signal pc_eod : std_logic; -- end of data signal
-
-signal ce_rem_ctr_comb : std_logic;
-signal ce_rem_ctr : std_logic; -- count enable for remove counter
-signal remove_done_comb : std_logic;
-signal remove_done : std_logic; -- end of header stripping process
-signal read_done_comb : std_logic;
-signal read_done : std_logic; -- end of data phase (read phase from SF)
-
-signal pc_data : std_logic_vector(7 downto 0);
-signal pc_data_q : std_logic_vector(7 downto 0);
-signal pc_trig_nr : std_logic_vector(15 downto 0);
-signal pc_sub_size : std_logic_vector(17 downto 0);
-signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo
-signal padding_needed : std_logic;
-signal pc_wr_en_comb : std_logic;
-signal pc_wr_en_q : std_logic;
-signal pc_wr_en_qq : std_logic;
-signal pc_wr_en_qqq : std_logic;
-signal pc_eod_q : std_logic;
-
-signal debug : std_logic_vector(383 downto 0);
-
--- gk
-signal bank_select : std_logic_vector(3 downto 0);
-signal save_addr_comb : std_logic;
-signal save_addr : std_logic;
-signal addr_saved_comb : std_logic;
-signal addr_saved : std_logic;
-signal start_config : std_logic;
-signal config_done : std_logic;
-signal add_sub_state : std_logic;
-signal add_sub_state_comb : std_logic;
-signal add_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub : std_logic;
-signal load_sub_comb : std_logic;
-signal load_sub_done : std_logic;
-signal load_sub_done_comb : std_logic;
-signal load_sub_ctr : std_logic_vector(3 downto 0);
-signal load_sub_ctr_comb : std_logic;
-signal actual_message_size : std_logic_vector(31 downto 0);
-signal more_subevents : std_logic;
-signal trig_random : std_logic_vector(7 downto 0);
-signal readout_ctr : std_logic_vector(23 downto 0);
-signal readout_ctr_lock : std_logic;
-signal pc_trig_nr_q : std_logic_vector(31 downto 0);
-
--- gk 20.07.10
-signal inc_data_ctr : std_logic_vector(31 downto 0);
-signal dropped_sm_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_lr_events_ctr : std_logic_vector(31 downto 0);
-signal dropped_ctr : std_logic_vector(31 downto 0);
--- gk 22.07.10
-signal headers_invalid : std_logic;
-signal headers_invalid_ctr : std_logic_vector(31 downto 0);
-signal cts_len_q : std_logic_vector(15 downto 0);
-signal cts_trg_q : std_logic_vector(15 downto 0);
-signal cts_rnd_q : std_logic_vector(15 downto 0);
-signal first_run_trg : std_logic_vector(15 downto 0);
-signal first_run_addr : std_logic_vector(15 downto 0);
-signal first_run_lock : std_logic;
-signal cts_addr : std_logic_vector(15 downto 0);
-signal cts_addr_q : std_logic_vector(15 downto 0);
-signal cts_addr_saved : std_logic;
-
--- gk 24.07.10
-signal save_eod : std_logic;
-signal save_eod_comb : std_logic;
-
-signal load_eod : std_logic;
-signal endpoint_addr : std_logic_vector(15 downto 0);
-signal endp_addr_lock : std_logic;
-
-signal saved_events_ctr : std_logic_vector(15 downto 0);
-signal loaded_events_ctr : std_logic_vector(15 downto 0);
-signal constr_events_ctr : std_logic_vector(31 downto 0);
-signal event_waiting : std_logic;
-
-signal drop_sub : std_logic;
-signal drop_sub_comb : std_logic;
-signal drop_event : std_logic;
-signal drop_event_comb : std_logic;
-signal drop_small : std_logic;
-signal drop_large : std_logic;
-signal drop_headers : std_logic;
-signal drop_small_comb : std_logic;
-signal drop_large_comb : std_logic;
-signal drop_headers_comb : std_logic;
-signal inc_trg_ctr : std_logic;
-signal inc_trg_ctr_comb : std_logic;
-
-signal invalid_hsize_ctr : std_logic_vector(15 downto 0);
-signal invalid_hsize_lock : std_logic;
-
-signal load_eod_q : std_logic;
-signal read_size_q : std_logic_vector(17 downto 0);
-
--- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked
-signal sf_real_wr_en : std_logic;
-
--- gk 01.10.10
-signal found_empty_evt : std_logic;
-signal found_empty_evt_comb : std_logic;
-signal found_empty_evt_ctr : std_logic_vector(31 downto 0);
-
--- gk 06.10.10
-signal message_size : std_logic_vector(31 downto 0);
-
--- gk 07.12.10
-signal prev_bank_select : std_logic_vector(3 downto 0);
-signal first_event : std_logic;
-
--- gk 29.07.11
-signal trg_type : std_logic_vector(3 downto 0);
-signal prev_trg_type : std_logic_vector(3 downto 0);
-
-begin
-
-BANK_SELECT_OUT <= bank_select; -- gk 27.03.10
-START_CONFIG_OUT <= start_config; -- gk 27.03.10
-config_done <= CONFIG_DONE_IN; -- gk 29.03.10
-
--- CTS interface signals
-cts_error_pattern <= (others => '0'); -- FAKE
-
-cts_length <= x"0000"; -- length of data payload is always 0
-cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'
-
-cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';
-
-cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE)
- else '0';
-
--- Byte swapping... done here. TAKE CARE!
--- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes
--- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port.
--- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped
--- for GbE inside the packet constructor.
---
--- Long live the Endianess!
-
--- Sync all critical pathes
-THE_SYNC_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below
- sf_wr_en <= sf_wr_en_comb;
- ce_rem_ctr <= ce_rem_ctr_comb;
- sf_rd_en <= sf_rd_en_comb;
- fee_read <= fee_read_comb;
- read_done <= read_done_comb;
- pc_eod_q <= pc_eod;
- pc_wr_en_qqq <= pc_wr_en_qq;
- pc_wr_en_qq <= pc_wr_en_q;
- pc_wr_en_q <= pc_wr_en_comb;
- end if;
-end process THE_SYNC_PROC;
-
--- gk 27.03.10 data selector for sf to write the evt builder address on top of data
-SF_DATA_PROC : process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if (RESET = '1') then -- gk 31.05.10
- sf_data <= (others => '0');
- elsif( save_addr = '1' ) then
- -- gk 29.07.11 added to this data word the trigger type in order to close multi events
- sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address
- sf_data(11 downto 4) <= x"bc";
- sf_data(15 downto 12) <= CTS_READOUT_TYPE_IN;
- -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then
- sf_data <= x"0001"; -- gk 11.06.10
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then
- sf_data <= x"5555"; -- gk 11.06.10
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then
- sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
- elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then
- sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
- else
- sf_data <= FEE_DATA_IN;
- end if;
- end if;
-end process SF_DATA_PROC;
-
--- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY
-fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
- else '0';
-
--- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY
-sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
- (save_addr = '1') or
- (add_sub_state = '1') -- gk 29.03.10 save the subsubevent
- else '0';
-
--- gk 06.08.10
-sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0';
-
--- gk 27.03.10 do not count evt builder address as saved ipu bytes
---ce_saved_ctr <= sf_wr_en;
-ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en;
-
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO
-saveMachineProc: process( CLK )
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saveCurrentState <= SIDLE;
- data_req <= '0';
- rst_saved_ctr <= '0';
- save_addr <= '0'; -- gk 27.03.10
- addr_saved <= '0'; -- gk 27.03.10
- add_sub_state <= '0'; -- gk 29.03.10
- save_eod <= '0'; -- gk 25.07.10
- else
- saveCurrentState <= saveNextState;
- data_req <= data_req_comb;
- rst_saved_ctr <= rst_saved_ctr_comb;
- save_addr <= save_addr_comb; -- gk 27.03.10
- addr_saved <= addr_saved_comb; -- gk 27.03.10
- add_sub_state <= add_sub_state_comb; -- gk 29.03.10
- save_eod <= save_eod_comb; -- gk 25.07.10
- end if;
- end if;
-end process saveMachineProc;
-
-saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN)
-begin
- saveNextState <= SIDLE;
- data_req_comb <= '0';
- rst_saved_ctr_comb <= '0';
- save_addr_comb <= '0'; -- gk 27.03.10
- addr_saved_comb <= '0'; -- gk 27.03.10
- add_sub_state_comb <= '0'; -- gk 29.03.10
- save_eod_comb <= '0'; -- gk 25.07.10
- case saveCurrentState is
- when SIDLE =>
- state <= x"0";
- if (CTS_START_READOUT_IN = '1') then
- saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10
- data_req_comb <= '1';
- rst_saved_ctr_comb <= '1';
- else
- saveNextState <= SIDLE;
- end if;
- -- gk 27.03.10
- when SAVE_EVT_ADDR =>
- state <= x"5";
- saveNextState <= WAIT_FOR_DATA;
- data_req_comb <= '1';
- save_addr_comb <= '1';
- when WAIT_FOR_DATA =>
- state <= x"1";
- if (FEE_BUSY_IN = '1') then
- saveNextState <= SAVE_DATA;
- data_req_comb <= '1';
- else
- saveNextState <= WAIT_FOR_DATA;
- data_req_comb <= '1';
- end if;
- addr_saved_comb <= '1'; -- gk 27.03.10
- when SAVE_DATA =>
- state <= x"2";
- if (FEE_BUSY_IN = '0') then
- saveNextState <= TERMINATE;
- else
- saveNextState <= SAVE_DATA;
- data_req_comb <= '1';
- end if;
- when TERMINATE =>
- state <= x"3";
- if (CTS_READ_IN = '1') then
- saveNextState <= SCLOSE;
- else
- saveNextState <= TERMINATE;
- end if;
- when SCLOSE =>
- state <= x"4";
- if (CTS_START_READOUT_IN = '0') then
- saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10
- else
- saveNextState <= SCLOSE;
- end if;
- -- gk 29.03.10 new states during which the subsub bytes are saved
- when ADD_SUBSUB1 =>
- state <= x"6";
- saveNextState <= ADD_SUBSUB2;
- add_sub_state_comb <= '1';
- when ADD_SUBSUB2 =>
- state<= x"7";
- saveNextState <= ADD_SUBSUB3;
- add_sub_state_comb <= '1';
- save_eod_comb <= '1';
- when ADD_SUBSUB3 =>
- state<= x"8";
- saveNextState <= ADD_SUBSUB4;
- add_sub_state_comb <= '1';
- when ADD_SUBSUB4 =>
- state<= x"9";
- saveNextState <= SIDLE;
- add_sub_state_comb <= '1';
- when others =>
- state <= x"f";
- saveNextState <= SIDLE;
- end case;
-end process saveMachine;
-
--- gk 29.03.10
-ADD_SUB_CTR_PROC : process( CLK )
-begin
- if( rising_edge( CLK ) ) then
- if( (RESET = '1') or (rst_saved_ctr = '1') ) then
- add_sub_ctr <= (others => '0');
- elsif( add_sub_state = '1' ) then
- add_sub_ctr <= add_sub_ctr + 1;
- end if;
- end if;
-end process ADD_SUB_CTR_PROC;
-
---********
--- SAVE INCOMING EVENT HEADERS
---********
-
--- Counter for header word storage
-THE_CTS_SAVED_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- saved_ctr <= (others => '0');
- elsif( ce_saved_ctr = '1' ) then
- saved_ctr <= saved_ctr + 1;
- end if;
- end if;
-end process THE_CTS_SAVED_CTR;
-
--- save triggerRnd from incoming data for cts response
-CTS_RND_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_rnd <= (others => '0');
- cts_rnd_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then
- cts_rnd <= sf_data;
- cts_rnd_saved <= '1';
- end if;
- end if;
-end process CTS_RND_PROC;
-
--- save triggerNr from incoming data for cts response
-CTS_TRG_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_trg <= (others => '0');
- cts_trg_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then
- cts_trg <= sf_data;
- cts_trg_saved <= '1';
- end if;
- end if;
-end process CTS_TRG_PROC;
-
--- save size from incoming data for cts response (future) and to get rid of padding
-CTS_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_len <= (others => '0');
- cts_len_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then
- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words
- cts_len(0) <= '0';
- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then
- cts_len <= cts_len + x"4";
- cts_len_saved <= '1';
- end if;
- end if;
-end process CTS_SIZE_PROC;
-
--- gk 22.07.10
-CTS_ADDR_PROC : process(CLK)
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then
- cts_addr <= (others => '0');
- cts_addr_saved <= '0';
- elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then
- cts_addr <= sf_data;
- cts_addr_saved <= '1';
- end if;
- end if;
-end process CTS_ADDR_PROC;
-
---******
--- SAVE FIRST EVENT HEADER VALUES
---******
-
--- gk 22.07.10
-FIRST_RUN_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- first_run_trg <= (others => '0');
- first_run_addr <= (others => '0');
- first_run_lock <= '0';
- elsif (first_run_lock = '0') and (cts_addr_saved = '1') then
- first_run_trg <= cts_trg;
- first_run_addr <= cts_addr;
- first_run_lock <= '1';
- -- important: value saved by saveMachine but incremented by loadMachine
- elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then
- first_run_trg <= first_run_trg + x"1";
- end if;
- end if;
-end process FIRST_RUN_PROC;
-
--- gk 25.07.10
-SAVED_EVT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saved_events_ctr <= (others => '0');
- elsif (save_eod = '1') then
- saved_events_ctr <= saved_events_ctr + x"1";
- end if;
- end if;
-end process SAVED_EVT_CTR_PROC;
-
-
--- gk 20.07.10
-INC_DATA_CTR_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (rst_saved_ctr = '1') then
- inc_data_ctr <= (others => '0');
- elsif (sf_wr_en = '1') and (data_req = '1') then
- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1";
- end if;
- end if;
-end process INC_DATA_CTR_proc;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Split FIFO
-THE_SPLIT_FIFO: fifo_32kx16x8_mb2
-port map(
- -- Byte swapping for correct byte order on readout side of FIFO
- Data(7 downto 0) => sf_data(15 downto 8),
- Data(8) => '0',
- Data(16 downto 9) => sf_data(7 downto 0),
- Data(17) => save_eod,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en,
- RdEn => sf_rd_en,
- Reset => RESET,
- RPReset => RESET,
- AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead
- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751
- Q(7 downto 0) => pc_data,
- Q(8) => load_eod,
- WCNT => sf_wcnt,
- RCNT => sf_rcnt,
- Empty => sf_empty,
- AlmostEmpty => sf_aempty,
- Full => sf_full,
- AlmostFull => sf_afull
-);
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- gk 25.07.10
-EVENT_WAITING_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- event_waiting <= '0';
- elsif (loaded_events_ctr /= saved_events_ctr) then
- event_waiting <= '1';
- else
- event_waiting <= '0';
- end if;
- end if;
-end process EVENT_WAITING_PROC;
-
--- write signal for PC data
-pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or
- (pad_phase = '1') or
- ((load_sub = '1') and (sf_rd_en = '1')) or
- ((drop_sub = '1') and (sf_rd_en = '1')) or
- ((drop_event = '1') and (sf_rd_en = '1'))
- else '0';
-
-sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or
- --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or
- ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10
- ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10
- ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or
- ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') )
- else '0';
-
-ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') )
- else '0';
-
--- FIFO data delay process (also forces padding bytes to known value)
-THE_DATA_DELAY_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( pad_data = '1' ) then
- pc_data_q <= x"aa"; -- padding for 64bit
- -- gk 21.07.10
- -- set the error flag if a broken packet is sent
- elsif (drop_sub = '1') and (load_sub_ctr = x"3") then
- pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0);
- else
- pc_data_q <= pc_data;
- end if;
- end if;
-end process THE_DATA_DELAY_PROC;
-
--- Statemachine for reading the data payload from the SPLIT_FIFO and feeding
--- it into the packet constructor
-loadMachineProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- loadCurrentState <= LIDLE;
- rst_rem_ctr <= '0';
- rem_phase <= '0';
- calc_pad <= '0';
- data_phase <= '0';
- pad_phase <= '0';
- pc_sos <= '0';
- pc_eod <= '0';
- rst_regs <= '0';
- pad_data <= '0';
- load_sub <= '0'; -- gk 30.03.10
- drop_sub <= '0'; -- gk 25.07.10
- drop_event <= '0'; -- gk 25.07.10
- drop_small <= '0'; -- gk 25.07.10
- drop_large <= '0'; -- gk 25.07.10
- drop_headers <= '0'; -- gk 25.07.10
- inc_trg_ctr <= '0'; -- gk 26.07.10
- found_empty_evt <= '0'; -- gk 01.10.10
- else
- loadCurrentState <= loadNextState;
- rst_rem_ctr <= rst_rem_ctr_comb;
- rem_phase <= rem_phase_comb;
- calc_pad <= calc_pad_comb;
- data_phase <= data_phase_comb;
- pad_phase <= pad_phase_comb;
- pc_sos <= pc_sos_comb;
- pc_eod <= pc_eod_comb;
- rst_regs <= rst_regs_comb;
- pad_data <= pad_data_comb;
- load_sub <= load_sub_comb; -- gk 30.03.1
- drop_sub <= drop_sub_comb; -- gk 25.07.10
- drop_event <= drop_event_comb; -- gk 25.07.10
- drop_small <= drop_small_comb; -- gk 25.07.10
- drop_large <= drop_large_comb; -- gk 25.07.10
- drop_headers <= drop_headers_comb; -- gk 25.07.10
- inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10
- found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10
- end if;
- end if;
-end process loadMachineProc;
-
-loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, first_run_addr, load_eod, event_waiting, bank_select, prev_bank_select)
-begin
- loadNextState <= LIDLE;
- rst_rem_ctr_comb <= '0';
- rem_phase_comb <= '0';
- calc_pad_comb <= '0';
- data_phase_comb <= '0';
- pad_phase_comb <= '0';
- pc_sos_comb <= '0';
- pc_eod_comb <= '0';
- rst_regs_comb <= '0';
- pad_data_comb <= '0';
- load_sub_comb <= '0'; -- gk 30.03.10
- drop_sub_comb <= '0'; -- gk 25.07.10
- drop_event_comb <= '0'; -- gk 25.07.10
- drop_small_comb <= '0'; -- gk 25.07.10
- drop_large_comb <= '0'; -- gk 25.07.10
- drop_headers_comb <= '0'; -- gk 25.07.10
- inc_trg_ctr_comb <= '0'; -- gk 26.07.10
- found_empty_evt_comb <= '0'; -- gk 01.10.10
- case loadCurrentState is
- when LIDLE =>
- state2 <= x"0";
- -- gk 23.07.10
- --if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10
- -- gk 04.12.10
- if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then
- loadNextState <= INIT;
- rst_rem_ctr_comb <= '1';
- rst_regs_comb <= '1';
- else
- loadNextState <= LIDLE;
- end if;
- when INIT =>
- state2 <= x"1";
- loadNextState <= REMOVE;
- rem_phase_comb <= '1';
--- when REMOVE =>
--- state2 <= x"2";
--- if( remove_done = '1' ) then
--- loadNextState <= WAIT_TO_REMOVE;
--- inc_trg_ctr_comb <= '1';
--- else
--- loadNextState <= REMOVE;
--- rem_phase_comb <= '1';
--- end if;
- -- gk 03.12.10
- when REMOVE =>
- state2 <= x"2";
- if( remove_done = '1' ) then
- -- gk 06.10.10
- if (MULT_EVT_ENABLE_IN = '1') then
- if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then
- -- gk 07.12.10
- if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet
- loadNextState <= WAIT_PC;
- -- gk 29.07.11
- elsif (first_event = '0') and (prev_trg_type /= trg_type) then -- check if the trigger type has changed, if so close the current packet
- loadNextState <= WAIT_PC;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
- else
- loadNextState <= WAIT_PC;
- end if;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
- inc_trg_ctr_comb <= '1';
- else
- loadNextState <= REMOVE;
- rem_phase_comb <= '1';
- end if;
-
- when WAIT_TO_REMOVE =>
- if (rem_ctr = x"a") then
- loadNextState <= DECIDE;
- else
- loadNextState <= WAIT_TO_REMOVE;
- end if;
- when DECIDE =>
- if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_large_comb <= '1';
- elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10
- loadNextState <= CALCA;
- found_empty_evt_comb <= '1';
- elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_small_comb <= '1';
- elsif (pc_trig_nr + x"1" /= first_run_trg) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_headers_comb <= '1';
- elsif (endpoint_addr /= first_run_addr) then
- loadNextState <= PAUSE_BEFORE_DROP1;
- drop_headers_comb <= '1';
- else
- loadNextState <= CALCA;
- end if;
- calc_pad_comb <= '1';
- when CALCA =>
- state2 <= x"3";
- loadNextState <= CALCB;
- pc_sos_comb <= '1';
- when CALCB =>
- -- we need a branch in case of length "0"!!!!
- state2 <= x"4";
- loadNextState <= LOAD;
- data_phase_comb <= '1';
- when LOAD =>
- state2 <= x"5";
- -- gk 31.03.10 after loading subevent data read the subsubevent from sf
- if (load_eod = '1') then
- loadNextState <= LOAD_SUBSUB;
- else
- loadNextState <= LOAD;
- data_phase_comb <= '1';
- end if;
- -- gk 31.03.10
- when LOAD_SUBSUB =>
- state2 <= x"d";
- if( load_sub_done = '1' ) then
- if( padding_needed = '0' ) then
- loadNextState <= CALCC;
- else
- loadNextState <= PAD0;
- pad_phase_comb <= '1';
- end if;
- else
- loadNextState <= LOAD_SUBSUB;
- load_sub_comb <= '1';
- end if;
- when PAD0 =>
- state2 <= x"6";
- loadNextState <= PAD1;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD1 =>
- state2 <= x"7";
- loadNextState <= PAD2;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD2 =>
- state2 <= x"8";
- loadNextState <= PAD3;
- pad_phase_comb <= '1';
- pad_data_comb <= '1';
- when PAD3 =>
- state2 <= x"9";
- loadNextState <= CALCC;
- pad_data_comb <= '1';
--- when CALCC =>
--- state2 <= x"a";
--- loadNextState <= CLOSE;
--- pc_eod_comb <= '1';
- -- gk 04.12.10
- when CALCC =>
- state2 <= x"a";
- if (MULT_EVT_ENABLE_IN = '1') then
- loadNextState <= LIDLE;
- else
- loadNextState <= CLOSE;
- end if;
- pc_eod_comb <= '1';
- when CLOSE =>
- state2 <= x"b";
- loadNextState <= WAIT_PC;
- rst_regs_comb <= '1';
--- when WAIT_PC =>
--- state2 <= x"c";
--- if( PC_READY_IN = '1' ) then
--- loadNextState <= LIDLE;
--- else
--- loadNextState <= WAIT_PC;
--- end if;
- -- gk 03.12.10
- when WAIT_PC =>
- state2 <= x"c";
- if( PC_READY_IN = '1' ) then
- -- gk 06.10.10
- if (MULT_EVT_ENABLE_IN = '1') then
- loadNextState <= WAIT_TO_REMOVE;
- else
- loadNextState <= LIDLE;
- end if;
- else
- loadNextState <= WAIT_PC;
- end if;
- when PAUSE_BEFORE_DROP1 =>
- loadNextState <= PAUSE_BEFORE_DROP2;
- pc_sos_comb <= '1';
- when PAUSE_BEFORE_DROP2 =>
- loadNextState <= DROP;
- drop_event_comb <= '1';
- -- gk 23.07.10
- when DROP =>
- state2 <= x"e";
- -- when data is dropped the eod marker stands as its end
- if (load_eod = '1') then
- loadNextState <= DROP_SUBSUB;
- else
- loadNextState <= DROP;
- drop_event_comb <= '1';
- end if;
- -- gk 25.07.10
- when DROP_SUBSUB =>
- if (load_sub_done = '1') then
- if( padding_needed = '0' ) then
- loadNextState <= CALCC;
- else
- loadNextState <= PAD0;
- pad_phase_comb <= '1';
- end if;
- else
- loadNextState <= DROP_SUBSUB;
- drop_sub_comb <= '1';
- end if;
- when others =>
- state2 <= x"f";
- loadNextState <= LIDLE;
- end case;
-end process loadMachine;
-
--- gk 07.10.10
-PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0';
-
--- gk 25.07.10
-INVALID_STATS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- dropped_lr_events_ctr <= (others => '0');
- dropped_sm_events_ctr <= (others => '0');
- headers_invalid_ctr <= (others => '0');
- dropped_ctr <= (others => '0');
- invalid_hsize_ctr <= (others => '0');
- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10
- elsif (rst_regs = '1') then
- invalid_hsize_lock <= '0';
- elsif (drop_small = '1') then
- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1";
- dropped_ctr <= dropped_ctr + x"1";
- elsif (drop_large = '1') then
- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1";
- dropped_ctr <= dropped_ctr + x"1";
- elsif (drop_headers = '1') then
- headers_invalid_ctr <= headers_invalid_ctr + x"1";
- dropped_ctr <= dropped_ctr + x"1";
- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ??
- invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
- invalid_hsize_lock <= '1';
- -- gk 01.10.10
- elsif (found_empty_evt = '1') then
- found_empty_evt_ctr <= found_empty_evt_ctr + x"1";
- end if;
- end if;
-end process INVALID_STATS_PROC;
-
--- gk 05.08.10
-INVALID_H_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- load_eod_q <= load_eod;
- read_size_q <= read_size;
- end if;
-end process INVALID_H_PROC;
-
--- gk 26.04.10
-READOUT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then
- readout_ctr <= READOUT_CTR_IN;
- readout_ctr_lock <= '0';
- elsif (pc_sos = '1') then
- readout_ctr <= readout_ctr + x"1";
- end if;
- end if;
-end process READOUT_CTR_PROC;
-
---******
--- SELECTION OF EVENT BUILDER
---******
-
--- gk 29.07.11 added trigger type
--- gk 27.03.10
-bank_select_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- -- gk 29.03.10
- if ((RESET = '1') or (rst_regs = '1')) then
- bank_select <= "0000";
- trg_type <= "0000";
- -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
- elsif ((sf_rd_en = '1') and (rem_ctr = x"2")) then
- bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
- elsif ((sf_rd_en = '1') and (rem_ctr = x"1")) then
- trg_type <= pc_data(7 downto 4);
- end if;
- end if;
-end process bank_select_proc;
-
--- gk 07.12.10
-first_event_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = WAIT_PC) then
- first_event <= '1';
- elsif (remove_done = '1') then
- first_event <= '0';
- end if;
- end if;
-end process first_event_proc;
-
--- gk 29.07.11 added trigger type
--- gk 07.12.10
-prev_bank_proc : process(CLK)
-begin
- if (RESET = '1') or (loadCurrentState = WAIT_PC) then
- prev_bank_select <= "0000";
- prev_trg_type <= "0000";
- elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then
- prev_bank_select <= bank_select;
- prev_trg_type <= trg_type;
- end if;
-end process prev_bank_proc;
-
--- gk 29.03.10
-start_config_proc : process( CLK )
-begin
- if rising_edge( CLK ) then
- if ((RESET = '1') or (config_done = '1') or (rst_regs = '1')) then
- start_config <= '0';
- elsif ((sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1')) then -- gk 01.06.10
- start_config <= '1';
- end if;
- end if;
-end process start_config_proc;
-
-
---******
--- LOAD SUBSUBEVENT
---******
-
--- gk 30.03.10
-load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') )
- else '0';
-
--- gk 30.03.10
-LOAD_SUB_CTR_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
- load_sub_ctr <= (others => '0');
- elsif( (load_sub_ctr_comb = '1') ) then
- load_sub_ctr <= load_sub_ctr + 1;
- end if;
- end if;
-end process LOAD_SUB_CTR_PROC;
-
--- gk 30.03.10
--- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or
--- ((load_sub_ctr = x"4") and (drop_sub = '1'))
--- else '0';
-load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0';
-
--- gk 30.03.10
-LOAD_SUB_DONE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10
- load_sub_done <= '0';
- else
- load_sub_done <= load_sub_done_comb;
- end if;
- end if;
-end process LOAD_SUB_DONE_PROC;
-
---******
--- EXTRACT EVENT HEADERS FROM SPLITFIFO
---******
-
--- Counter for stripping the unneeded parts of the data stream, and saving the important parts
-THE_REMOVE_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
- rem_ctr <= (others => '0');
- elsif( (ce_rem_ctr = '1') ) then
- rem_ctr <= rem_ctr + 1;
- end if;
- end if;
-end process THE_REMOVE_CTR;
-
-remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address
-
-THE_REM_DONE_SYNC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then
- remove_done <= '0';
- else
- remove_done <= remove_done_comb;
- end if;
- end if;
-end process THE_REM_DONE_SYNC;
-
--- gk 26.04.10
-TRIG_RANDOM_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (rst_regs = '1')) then
- trig_random <= (others => '0');
- elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then
- trig_random <= pc_data;
- end if;
- end if;
-end process TRIG_RANDOM_PROC;
-
--- extract the trigger number from splitfifo data
-THE_TRG_NR_PROC: process( CLK )
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- pc_trig_nr <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10
- pc_trig_nr(7 downto 0) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10
- pc_trig_nr(15 downto 8) <= pc_data;
- end if;
- end if;
-end process THE_TRG_NR_PROC;
-
--- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,
--- and in case of padding needed increase it accordingly
-THE_SUB_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- pc_sub_size <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
- pc_sub_size(9 downto 2) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
- pc_sub_size(17 downto 10) <= pc_data;
- -- gk 20.07.10
- -- gk 30.03.10 bug fixed in the way that is written below
- -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save
- elsif( (calc_pad = '1') and (padding_needed = '1') ) then
- pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!!
- elsif( (calc_pad = '1') and (padding_needed = '0') ) then
- pc_sub_size <= pc_sub_size + x"8";
- end if;
- end if;
-end process THE_SUB_SIZE_PROC;
-
--- gk 06.10.10
-MESSAGE_SIZE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- message_size <= x"0000_0028";
- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
- message_size <= x"0000_0028";
- elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then
- message_size <= x"0000_0028";
- elsif (pc_sos = '1') then
- message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers
- end if;
- end if;
-end process MESSAGE_SIZE_PROC;
-
--- gk 25.07.10
-ENDP_ADDRESS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (rst_regs = '1') then
- endpoint_addr <= (others => '0');
- endp_addr_lock <= '0';
- elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then
- endpoint_addr(7 downto 0) <= pc_data;
- endp_addr_lock <= '1';
- elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then
- endpoint_addr(15 downto 8) <= pc_data;
- endp_addr_lock <= '0';
- end if;
- end if;
-end process ENDP_ADDRESS_PROC;
-
-
-
--- check for padding
-THE_PADDING_NEEDED_PROC: process( CLK )
-begin
- if rising_edge(CLK) then
- if ( (RESET = '1') or (rst_regs = '1') ) then
- padding_needed <= '0';
- elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then
- padding_needed <= '1';
- elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then
- padding_needed <= '0';
- end if;
- end if;
-end process THE_PADDING_NEEDED_PROC;
-
--- number of bytes to read from split fifo
-THE_READ_SIZE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then
- read_size <= (others => '0');
- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10
- read_size(9 downto 2) <= pc_data;
- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10
- read_size(17 downto 10) <= pc_data;
- elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then
- read_size <= read_size - 1;
- -- gk 25.07.10
- elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then
- read_size <= read_size - 1;
- end if;
- end if;
-end process THE_READ_SIZE_PROC;
-
-read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2"
-
---******
--- EVENTS COUNTERS
---******
-
--- gk 25.07.10
-LOADED_EVT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- loaded_events_ctr <= (others => '0');
- elsif (remove_done = '1') then
- loaded_events_ctr <= loaded_events_ctr + x"1";
- end if;
- end if;
-end process LOADED_EVT_CTR_PROC;
-
--- gk 25.07.10
-CONSTR_EVENTS_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- constr_events_ctr <= (others => '0');
- elsif (pc_eod = '1') then
- constr_events_ctr <= constr_events_ctr + x"1";
- end if;
- end if;
-end process CONSTR_EVENTS_CTR_PROC;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Debug signals
-debug(0) <= sf_full;
-debug(1) <= sf_empty;
-debug(2) <= sf_afull;
-debug(3) <= sf_aempty;
-
-debug(7 downto 4) <= state2;
-
-debug(11 downto 8) <= state;
-
-dbg_bs_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- debug(15 downto 12) <= (others => '0');
- elsif ((sf_rd_en = '1') and (rem_ctr = x"3")) then
- debug(15 downto 12) <= bank_select;
- end if;
- end if;
-end process dbg_bs_proc;
-
-debug(16) <= config_done;
-debug(17) <= '0'; --remove_done;
-debug(18) <= read_done;
-debug(19) <= padding_needed;
-
-debug(20) <= load_sub_done;
-
-dbg_cts_inf_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- debug(39 downto 32) <= (others => '0');
- elsif ( save_addr = '1' ) then
- debug(39 downto 32) <= CTS_INFORMATION_IN;
- end if;
- end if;
-end process dbg_cts_inf_proc;
-
-debug(47 downto 40) <= (others => '0');
-
-
-debug(63 downto 48) <= actual_message_size(15 downto 0);
-
-dbg_pc_sub_size_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- debug(81 downto 64) <= (others => '0');
- elsif (loadCurrentState = DECIDE) then
- debug(81 downto 64) <= pc_sub_size;
- end if;
- end if;
-end process dbg_pc_sub_size_proc;
-
-dbg_empty_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (rst_regs = '1') then
- debug(84 downto 82) <= (others => '0');
- elsif (read_size = 2) then
- debug(82) <= sf_empty;
- elsif (read_size = 1) then
- debug(83) <= sf_empty;
- elsif (read_size = 0) then
- debug(84) <= sf_empty;
- end if;
- end if;
-end process dbg_empty_proc;
-
-debug(95 downto 85) <= (others => '0');
-
-dbg_inc_ctr_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- debug(127 downto 96) <= (others => '1');
- elsif (saveCurrentState = SCLOSE) then
- debug(127 downto 96) <= inc_data_ctr;
- end if;
- end if;
-end process dbg_inc_ctr_proc;
-
-debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0);
-debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0);
-
-debug(175 downto 160) <= headers_invalid_ctr(15 downto 0);
-debug(191 downto 176) <= (others => '0');
-
-dbg_cts_q_proc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- cts_len_q <= (others => '0');
- cts_rnd_q <= (others => '0');
- cts_trg_q <= (others => '0');
- cts_addr_q <= (others => '0');
- elsif (cts_len_saved = '1') then
- cts_len_q <= cts_len(16 downto 1);
- cts_addr_q <= cts_addr;
- cts_rnd_q <= cts_rnd;
- cts_trg_q <= cts_trg;
- end if;
- end if;
-end process dbg_cts_q_proc;
-
-debug(207 downto 192) <= cts_trg_q;
-debug(223 downto 208) <= cts_rnd_q;
-debug(239 downto 224) <= cts_addr_q;
-debug(255 downto 240) <= cts_len_q;
-debug(271 downto 256) <= first_run_trg;
-debug(287 downto 272) <= first_run_addr;
-
-debug(303 downto 288) <= saved_events_ctr;
-debug(319 downto 304) <= loaded_events_ctr;
-
-debug(335 downto 320) <= constr_events_ctr(15 downto 0);
-debug(351 downto 336) <= dropped_ctr(15 downto 0);
-
-debug(367 downto 352) <= invalid_hsize_ctr;
-debug(383 downto 368) <= (others => '0');
-
-MONITOR_OUT(31 downto 0) <= constr_events_ctr;
-MONITOR_OUT(63 downto 32) <= dropped_ctr;
-MONITOR_OUT(95 downto 64) <= headers_invalid_ctr;
-MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr;
-MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
-MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000";
-MONITOR_OUT(191 downto 164) <= (others => '0');
-MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10
-
--- Outputs
-FEE_READ_OUT <= fee_read;
-CTS_ERROR_PATTERN_OUT <= cts_error_pattern;
-CTS_DATA_OUT <= cts_data;
-CTS_DATAREADY_OUT <= cts_dataready;
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
-CTS_LENGTH_OUT <= cts_length;
-
-PC_SOS_OUT <= pc_sos;
---PC_EOD_OUT <= pc_eod; -- gk 26.07.10 --pc_eod_q;
-PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1'))
- or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1'))
- -- gk 07.12.10
- or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1'))
- else '0'; -- gk 07.10.10
-PC_DATA_OUT <= pc_data_q;
-PC_WR_EN_OUT <= pc_wr_en_qq;
-
-PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random;
-
-PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size;
-PC_PADDING_OUT <= padding_needed;
-
-DEBUG_OUT <= debug;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
--- LinkStateMachine for SFPs (GigE)\r
-\r
--- Still missing: link reset features, fifo full error handling, signals on stat_op\r
--- Take care: all input signals must be synchronous to SYSCLK,\r
--- all output signals are synchronous to SYSCLK.\r
--- Clock Domain Crossing is in your responsibility!\r
-\r
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.std_logic_ARITH.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-library work;\r
---use work.trb_net_std.all;\r
-\r
-entity trb_net16_lsm_sfp_gbe is\r
-port( SYSCLK : in std_logic; -- fabric clock (100MHz)\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available\r
- -- status signals\r
- SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place)\r
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)\r
- SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)\r
- SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)\r
- SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)\r
- -- control signals\r
- FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset\r
- LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset\r
- USER_RESET_OUT : out std_logic; -- FPGA reset for user logic\r
- -- debug signals\r
- TIMING_CTR_OUT : out std_logic_vector(18 downto 0);\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-end entity;\r
-\r
-architecture lsm_sfp_gbe of trb_net16_lsm_sfp_gbe is\r
-\r
--- state machine signals\r
-type STATES is ( QRST, SLEEP, DELAY, USERRST, LINK );\r
-signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
-signal state_bits : std_logic_vector(3 downto 0);\r
-signal next_ce_tctr : std_logic;\r
-signal ce_tctr : std_logic;\r
-signal next_rst_tctr : std_logic;\r
-signal rst_tctr : std_logic;\r
-signal next_quad_rst : std_logic;\r
-signal quad_rst : std_logic;\r
-signal next_lane_rst : std_logic;\r
-signal lane_rst : std_logic;\r
-signal next_user_rst : std_logic;\r
-signal user_rst : std_logic;\r
-signal sfp_missing_q : std_logic;\r
-signal sfp_missing_qq : std_logic;\r
-signal sfp_los_q : std_logic;\r
-signal sfp_los_qq : std_logic;\r
-signal sd_rxclk_bad_q : std_logic;\r
-signal sd_rxclk_bad_qq : std_logic;\r
-signal sd_rxclk_bad_qqq : std_logic;\r
-signal sd_txclk_bad_q : std_logic;\r
-signal sd_txclk_bad_qq : std_logic;\r
-signal sd_txclk_bad_qqq : std_logic;\r
-signal sd_rxclk_warn_comb : std_logic;\r
-signal sd_rxclk_warn : std_logic; -- rising edge on rlol detected\r
-signal sd_txclk_warn_comb : std_logic;\r
-signal sd_txclk_warn : std_logic; -- rising edge on plol detected\r
-signal timing_ctr : std_logic_vector(18 downto 0);\r
-signal debug : std_logic_vector(31 downto 0);\r
-\r
-begin\r
-\r
--- Debug signals\r
-debug(31 downto 4) <= (others => '0');\r
-debug(3) <= sd_txclk_warn;\r
-debug(2) <= sd_rxclk_warn;\r
-debug(1) <= rst_tctr;\r
-debug(0) <= ce_tctr;\r
-\r
--- synchronize external signals from SFP\r
-THE_SYNC_PROC: process( sysclk )\r
-begin\r
- if( rising_edge(sysclk) ) then\r
- -- SFP input signals\r
- sfp_missing_qq <= sfp_missing_q;\r
- sfp_missing_q <= sfp_missing_in;\r
- sfp_los_qq <= sfp_los_q;\r
- sfp_los_q <= sfp_los_in;\r
- -- SerDes input signals\r
- sd_rxclk_bad_qqq <= sd_rxclk_bad_qq;\r
- sd_rxclk_bad_qq <= sd_rxclk_bad_q;\r
- sd_rxclk_bad_q <= sd_rxclk_bad_in;\r
- sd_txclk_bad_qqq <= sd_txclk_bad_q;\r
- sd_txclk_bad_qq <= sd_txclk_bad_q;\r
- sd_txclk_bad_q <= sd_txclk_bad_in;\r
- -- edge detectors\r
- sd_rxclk_warn <= sd_rxclk_warn_comb;\r
- sd_txclk_warn <= sd_txclk_warn_comb;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
--- combinatorial part of edge detectors (rlol, see remark on page 8-63 in HB1003.pdf)\r
-sd_rxclk_warn_comb <= '1' when ( (sd_rxclk_bad_qqq = '0') and (sd_rxclk_bad_qq = '1') ) else '0';\r
-sd_txclk_warn_comb <= '1' when ( (sd_txclk_bad_qqq = '0') and (sd_txclk_bad_qq = '1') ) else '0';\r
-\r
---------------------------------------------------------------------------\r
--- Main control state machine, startup control for SFP\r
---------------------------------------------------------------------------\r
-\r
--- Timing counter for reset sequencing\r
-THE_TIMING_COUNTER_PROC: process( sysclk, clear )\r
-begin\r
- if( clear = '1' ) then\r
- timing_ctr <= (others => '0');\r
- elsif( rising_edge(sysclk) ) then\r
- if ( (rst_tctr = '1') or (sd_rxclk_warn = '1') or (sd_txclk_warn = '1') ) then\r
- timing_ctr <= (others => '0');\r
- elsif( ce_tctr = '1' ) then\r
- timing_ctr <= timing_ctr + 1;\r
- end if;\r
- end if;\r
-end process THE_TIMING_COUNTER_PROC;\r
-\r
--- State machine\r
--- state registers\r
-STATE_MEM: process( sysclk, clear )\r
-begin\r
- if( clear = '1' ) then\r
- CURRENT_STATE <= QRST;\r
- ce_tctr <= '0';\r
- rst_tctr <= '0';\r
- quad_rst <= '1';\r
- lane_rst <= '1';\r
- user_rst <= '1';\r
- elsif( rising_edge(sysclk) ) then\r
- CURRENT_STATE <= NEXT_STATE;\r
- ce_tctr <= next_ce_tctr;\r
- rst_tctr <= next_rst_tctr;\r
- quad_rst <= next_quad_rst;\r
- lane_rst <= next_lane_rst;\r
- user_rst <= next_user_rst;\r
- end if;\r
-end process STATE_MEM;\r
-\r
--- state transitions\r
-PROC_STATE_TRANSFORM: process( CURRENT_STATE, sfp_missing_qq, sfp_los_qq, sd_txclk_bad_qqq, sd_rxclk_bad_qqq,\r
- timing_ctr(8), timing_ctr(18), timing_ctr(17),\r
- reset )\r
-begin\r
- NEXT_STATE <= QRST; -- avoid latches\r
- next_ce_tctr <= '0';\r
- next_rst_tctr <= '0';\r
- next_quad_rst <= '0';\r
- next_lane_rst <= '0';\r
- next_user_rst <= '0';\r
- case CURRENT_STATE is\r
- when QRST => -- initial state, we stay there unless CLEAR is deasserted.\r
- state_bits <= x"0";\r
- if( (timing_ctr(8) = '1') ) then\r
- NEXT_STATE <= SLEEP; -- release QUAD_RST, wait for lock of RxClock and TxClock\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- next_rst_tctr <= '1';\r
- else\r
- NEXT_STATE <= QRST; -- count delay\r
- next_ce_tctr <= '1';\r
- next_quad_rst <= '1';\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
- when SLEEP => -- we check for SFP presence and signal\r
- state_bits <= x"1";\r
- if( (sfp_missing_qq = '0') and (sfp_los_qq = '0') ) then\r
- NEXT_STATE <= DELAY; -- do a correctly timed QUAD reset (about 150ns)\r
- next_ce_tctr <= '1';\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- else\r
- NEXT_STATE <= SLEEP; -- wait for SFP present signal\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
- when DELAY => -- we wait approx. 4ms and check for PLL lock in the SerDes\r
- state_bits <= x"2";\r
- if( (timing_ctr(18) = '1') and (timing_ctr(17) = '1') and (sd_rxclk_bad_qqq = '0') and (sd_txclk_bad_qqq = '0') ) then\r
- NEXT_STATE <= USERRST; -- we release lane reset\r
- next_ce_tctr <= '1';\r
- next_user_rst <= '1';\r
- else\r
- NEXT_STATE <= DELAY;\r
- next_ce_tctr <= '1';\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
- when USERRST => -- short delay for user reset\r
- state_bits <= x"3";\r
- if( (timing_ctr(18) = '0') and (timing_ctr(17) = '0') ) then\r
- NEXT_STATE <= LINK;\r
- next_rst_tctr <= '1';\r
- else\r
- NEXT_STATE <= USERRST;\r
- next_ce_tctr <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
- when LINK => -- operational\r
- state_bits <= x"4";\r
- NEXT_STATE <= LINK;\r
- when others => \r
- NEXT_STATE <= QRST;\r
- end case;\r
- \r
- -- emergency jumps in case of SFP problems\r
- if( ((sfp_missing_qq = '1') or (sfp_los_qq = '1') or (RESET = '1')) and CURRENT_STATE /= QRST ) then\r
- NEXT_STATE <= SLEEP; -- wait for SFP present signal\r
- next_rst_tctr <= '1';\r
- next_lane_rst <= '1';\r
- next_user_rst <= '1';\r
- end if;\r
-end process;\r
-\r
---------------------------------------------------------------------------\r
--- Output signals\r
---------------------------------------------------------------------------\r
-full_reset_out <= quad_rst;\r
-lane_reset_out <= lane_rst;\r
-user_reset_out <= user_rst;\r
-\r
---------------------------------------------------------------------------\r
--- Debug output\r
---------------------------------------------------------------------------\r
-timing_ctr_out <= timing_ctr;\r
-bsm_out <= state_bits;\r
-debug_out <= debug;\r
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.std_logic_ARITH.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-\r
-entity trb_net16_med_ecp_sfp_gbe_8b is\r
--- gk 28.04.10\r
-generic (\r
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
-);\r
-port(\r
- RESET : in std_logic;\r
- GSR_N : in std_logic;\r
- CLK_125_OUT : out std_logic;\r
- CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk\r
- --SGMII connection to frame transmitter (tsmac)\r
- FT_TX_CLK_EN_OUT : out std_logic;\r
- FT_RX_CLK_EN_OUT : out std_logic;\r
- FT_COL_OUT : out std_logic;\r
- FT_CRS_OUT : out std_logic;\r
- FT_TXD_IN : in std_logic_vector(7 downto 0);\r
- FT_TX_EN_IN : in std_logic;\r
- FT_TX_ER_IN : in std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic; -- SFP disable\r
- -- Autonegotiation stuff \r
- MR_RESET_IN : in std_logic;\r
- MR_MODE_IN : in std_logic;\r
- MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); -- should be x"0020\r
- MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); -- advert page from link partner\r
- MR_AN_PAGE_RX_OUT : out std_logic;\r
- MR_AN_COMPLETE_OUT : out std_logic; \r
- MR_AN_ENABLE_IN : in std_logic;\r
- MR_RESTART_AN_IN : in std_logic;\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
-);\r
-end entity;\r
-\r
-architecture trb_net16_med_ecp_sfp_gbe_8b of trb_net16_med_ecp_sfp_gbe_8b is\r
-\r
--- Placer Directives\r
-attribute HGROUP : string;\r
--- for whole architecture\r
-attribute HGROUP of trb_net16_med_ecp_sfp_gbe_8b : architecture is "media_interface_group";\r
-attribute syn_sharing : string;\r
-attribute syn_sharing of trb_net16_med_ecp_sfp_gbe_8b : architecture is "off";\r
-\r
-component serdes_gbe_0_extclock_8b is\r
-GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt");\r
-port( refclkp : in std_logic;\r
- refclkn : in std_logic;\r
- hdinp0 : in std_logic;\r
- hdinn0 : in std_logic;\r
- hdoutp0 : out std_logic;\r
- hdoutn0 : out std_logic;\r
- ff_rxiclk_ch0 : in std_logic;\r
- ff_txiclk_ch0 : in std_logic;\r
- ff_ebrd_clk_0 : in std_logic;\r
- ff_txdata_ch0 : in std_logic_vector (7 downto 0);\r
- ff_rxdata_ch0 : out std_logic_vector (7 downto 0);\r
- ff_tx_k_cntrl_ch0 : in std_logic;\r
- ff_rx_k_cntrl_ch0 : out std_logic;\r
- ff_rxfullclk_ch0 : out std_logic;\r
- ff_xmit_ch0 : in std_logic;\r
- ff_correct_disp_ch0 : in std_logic;\r
- ff_disp_err_ch0 : out std_logic;\r
- ff_cv_ch0 : out std_logic;\r
- ff_rx_even_ch0 : out std_logic;\r
- ffc_rrst_ch0 : in std_logic;\r
- ffc_lane_tx_rst_ch0 : in std_logic;\r
- ffc_lane_rx_rst_ch0 : in std_logic;\r
- ffc_txpwdnb_ch0 : in std_logic;\r
- ffc_rxpwdnb_ch0 : in std_logic;\r
- ffs_rlos_lo_ch0 : out std_logic;\r
- ffs_ls_sync_status_ch0 : out std_logic;\r
- ffs_rlol_ch0 : out std_logic;\r
- oob_out_ch0 : out std_logic;\r
- ffc_macro_rst : in std_logic;\r
- ffc_quad_rst : in std_logic;\r
- ffc_trst : in std_logic;\r
- ff_txfullclk : out std_logic;\r
- ff_txhalfclk : out std_logic;\r
- refck2core : out std_logic;\r
- ffs_plol : out std_logic\r
- );\r
-end component;\r
-\r
-component serdes_gbe_0_intclock_8b is\r
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt");\r
- port (\r
- core_txrefclk : in std_logic;\r
- core_rxrefclk : in std_logic;\r
- hdinp0, hdinn0 : in std_logic;\r
- hdoutp0, hdoutn0 : out std_logic;\r
- ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;\r
- ff_txdata_ch0 : in std_logic_vector (7 downto 0);\r
- ff_rxdata_ch0 : out std_logic_vector (7 downto 0);\r
- ff_tx_k_cntrl_ch0 : in std_logic;\r
- ff_rx_k_cntrl_ch0 : out std_logic;\r
- ff_rxfullclk_ch0 : out std_logic;\r
- ff_xmit_ch0 : in std_logic;\r
- ff_correct_disp_ch0 : in std_logic;\r
- ff_disp_err_ch0, ff_cv_ch0 : out std_logic;\r
- ff_rx_even_ch0 : out std_logic;\r
- ffc_rrst_ch0 : in std_logic;\r
- ffc_lane_tx_rst_ch0 : in std_logic;\r
- ffc_lane_rx_rst_ch0 : in std_logic;\r
- ffc_txpwdnb_ch0 : in std_logic;\r
- ffc_rxpwdnb_ch0 : in std_logic;\r
- ffs_rlos_lo_ch0 : out std_logic;\r
- ffs_ls_sync_status_ch0 : out std_logic;\r
- ffs_rlol_ch0 : out std_logic;\r
- oob_out_ch0 : out std_logic;\r
- ffc_macro_rst : in std_logic;\r
- ffc_quad_rst : in std_logic;\r
- ffc_trst : in std_logic;\r
- ff_txfullclk : out std_logic;\r
- ff_txhalfclk : out std_logic;\r
- ffs_plol : out std_logic);\r
-\r
-end component;\r
-\r
-component sgmii_gbe_pcs32\r
-port( rst_n : in std_logic;\r
- signal_detect : in std_logic;\r
- gbe_mode : in std_logic;\r
- sgmii_mode : in std_logic;\r
- operational_rate : in std_logic_vector(1 downto 0);\r
- debug_link_timer_short : in std_logic;\r
- rx_compensation_err : out std_logic;\r
- tx_clk_125 : in std_logic; \r
- tx_clock_enable_source : out std_logic;\r
- tx_clock_enable_sink : in std_logic; \r
- tx_d : in std_logic_vector(7 downto 0); \r
- tx_en : in std_logic; \r
- tx_er : in std_logic; \r
- rx_clk_125 : in std_logic; \r
- rx_clock_enable_source : out std_logic;\r
- rx_clock_enable_sink : in std_logic; \r
- rx_d : out std_logic_vector(7 downto 0); \r
- rx_dv : out std_logic; \r
- rx_er : out std_logic; \r
- col : out std_logic; \r
- crs : out std_logic; \r
- tx_data : out std_logic_vector(7 downto 0); \r
- tx_kcntl : out std_logic; \r
- tx_disparity_cntl : out std_logic; \r
- serdes_recovered_clk : in std_logic; \r
- rx_data : in std_logic_vector(7 downto 0); \r
- rx_even : in std_logic; \r
- rx_kcntl : in std_logic; \r
- rx_disp_err : in std_logic; \r
- rx_cv_err : in std_logic; \r
- rx_err_decode_mode : in std_logic; \r
- mr_an_complete : out std_logic; \r
- mr_page_rx : out std_logic; \r
- mr_lp_adv_ability : out std_logic_vector(15 downto 0); \r
- mr_main_reset : in std_logic; \r
- mr_an_enable : in std_logic; \r
- mr_restart_an : in std_logic; \r
- mr_adv_ability : in std_logic_vector(15 downto 0) \r
- );\r
-end component;\r
-\r
-component trb_net16_lsm_sfp_gbe is\r
-port( SYSCLK : in std_logic; -- fabric clock (100MHz)\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available\r
- -- status signals\r
- SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place)\r
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)\r
- SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)\r
- SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)\r
- SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)\r
- -- control signals\r
- FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset\r
- LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset\r
- USER_RESET_OUT : out std_logic; -- FPGA reset for user logic\r
- -- debug signals\r
- TIMING_CTR_OUT : out std_logic_vector(18 downto 0);\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-signal refclkcore : std_logic;\r
-\r
-signal sd_link_ok : std_logic;\r
-signal sd_link_error : std_logic_vector(2 downto 0);\r
-\r
-signal sd_tx_data : std_logic_vector(7 downto 0);\r
-signal sd_tx_kcntl : std_logic;\r
-signal sd_tx_correct_disp : std_logic;\r
-signal sd_tx_clk : std_logic;\r
-\r
-signal sd_rx_data : std_logic_vector(7 downto 0);\r
-signal sd_rx_even : std_logic;\r
-signal sd_rx_kcntl : std_logic;\r
-signal sd_rx_disp_error : std_logic;\r
-signal sd_rx_cv_error : std_logic;\r
-signal sd_rx_clk : std_logic;\r
-\r
-signal pcs_mr_an_complete : std_logic;\r
-signal pcs_mr_ability : std_logic_vector(15 downto 0);\r
-signal pcs_mr_page_rx : std_logic;\r
-signal pcs_mr_reset : std_logic;\r
-\r
-signal pcs_tx_clk_en : std_logic;\r
-signal pcs_rx_clk_en : std_logic;\r
-signal pcs_rx_comp_err : std_logic;\r
-\r
-signal pcs_rx_d : std_logic_vector(7 downto 0);\r
-signal pcs_rx_dv : std_logic;\r
-signal pcs_rx_er : std_logic;\r
-\r
-signal sd_rx_debug : std_logic_vector(15 downto 0);\r
-signal sd_tx_debug : std_logic_vector(15 downto 0);\r
-\r
-signal buf_stat_debug : std_logic_vector(63 downto 0);\r
-\r
-signal quad_rst : std_logic;\r
-signal lane_rst : std_logic;\r
-signal user_rst : std_logic;\r
-\r
-signal reset_bsm : std_logic_vector(3 downto 0);\r
-signal reset_debug : std_logic_vector(31 downto 0);\r
-\r
-begin\r
-\r
--- Reset state machine for SerDes\r
-THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe\r
-port map(\r
- SYSCLK => refclkcore,\r
- RESET => '0', -- really?\r
- CLEAR => RESET, -- from 100MHz PLL, includes async part\r
- -- status signals\r
- SFP_MISSING_IN => SD_PRSNT_N_IN,\r
- SFP_LOS_IN => SD_LOS_IN,\r
- SD_LINK_OK_IN => '1', -- not used\r
- SD_LOS_IN => '0', -- not used\r
- SD_TXCLK_BAD_IN => sd_link_error(2), -- plol\r
- SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol\r
- -- control signals\r
- FULL_RESET_OUT => quad_rst,\r
- LANE_RESET_OUT => lane_rst,\r
- USER_RESET_OUT => user_rst,\r
- -- debug signals\r
- TIMING_CTR_OUT => open,\r
- BSM_OUT => reset_bsm,\r
- DEBUG_OUT => reset_debug\r
-);\r
-\r
--- gk 28.04.10\r
--- SerDes for GbE\r
-clk_int : if (USE_125MHZ_EXTCLK = 0) generate\r
-\r
- refclkcore <= CLK_125_IN;\r
-\r
- SERDES_GBE : serdes_gbe_0_intclock_8b\r
- port map(\r
- core_txrefclk => CLK_125_IN,\r
- core_rxrefclk => CLK_125_IN,\r
- hdinp0 => SD_RXD_P_IN,\r
- hdinn0 => SD_RXD_N_IN,\r
- hdoutp0 => SD_TXD_P_OUT,\r
- hdoutn0 => SD_TXD_N_OUT,\r
- ff_rxiclk_ch0 => sd_rx_clk,\r
- ff_txiclk_ch0 => sd_tx_clk,\r
- ff_ebrd_clk_0 => sd_rx_clk,\r
- ff_txdata_ch0 => sd_tx_data,\r
- ff_rxdata_ch0 => sd_rx_data,\r
- ff_tx_k_cntrl_ch0 => sd_tx_kcntl,\r
- ff_rx_k_cntrl_ch0 => sd_rx_kcntl,\r
- ff_rxfullclk_ch0 => sd_rx_clk,\r
- ff_xmit_ch0 => '0',\r
- ff_correct_disp_ch0 => sd_tx_correct_disp,\r
- ff_disp_err_ch0 => sd_rx_disp_error,\r
- ff_cv_ch0 => sd_rx_cv_error,\r
- ff_rx_even_ch0 => sd_rx_even,\r
- ffc_rrst_ch0 => '0',\r
- ffc_lane_tx_rst_ch0 => lane_rst,\r
- ffc_lane_rx_rst_ch0 => lane_rst,\r
- ffc_txpwdnb_ch0 => '1',\r
- ffc_rxpwdnb_ch0 => '1',\r
- ffs_rlos_lo_ch0 => sd_link_error(0),\r
- ffs_ls_sync_status_ch0 => sd_link_ok,\r
- ffs_rlol_ch0 => sd_link_error(1),\r
- oob_out_ch0 => open,\r
- ffc_macro_rst => '0',\r
- ffc_quad_rst => quad_rst,\r
- ffc_trst => '0',\r
- ff_txfullclk => sd_tx_clk,\r
- ff_txhalfclk => open,\r
- ffs_plol => sd_link_error(2)\r
- );\r
-end generate clk_int;\r
-\r
-clk_ext : if (USE_125MHZ_EXTCLK = 1) generate\r
- SERDES_GBE : serdes_gbe_0_extclock_8b \r
- port map( -- SerDes connection to outside world\r
- refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input\r
- refclkn => SD_REFCLK_N_IN,\r
- hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input\r
- hdinn0 => SD_RXD_N_IN,\r
- hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output\r
- hdoutn0 => SD_TXD_N_OUT,\r
- refck2core => refclkcore, -- reference clock from input\r
- -- RX part\r
- ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output\r
- ff_rxiclk_ch0 => sd_rx_clk,\r
- ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice\r
- ff_rxdata_ch0 => sd_rx_data, -- RX data output\r
- ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output\r
- ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output)\r
- ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error\r
- ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error\r
- -- TX part\r
- ff_txfullclk => sd_tx_clk, -- TX full clock output\r
- ff_txiclk_ch0 => sd_tx_clk, \r
- ff_txhalfclk => open,\r
- ff_txdata_ch0 => sd_tx_data, -- TX data input\r
- ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input\r
- ff_xmit_ch0 => '0', -- for autonegotiation (input)\r
- ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input)\r
- -- Resets and power down\r
- ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high)\r
- ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel\r
- ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel\r
- ffc_rrst_ch0 => '0', -- '0' for normal operation\r
- ffc_macro_rst => '0', -- '0' for normal operation\r
- ffc_trst => '0', -- '0' for normal operation\r
- ffc_txpwdnb_ch0 => '1', -- must be '1'\r
- ffc_rxpwdnb_ch0 => '1', -- must be '1'\r
- -- Status outputs\r
- ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas?\r
- ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel\r
- ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL\r
- ffs_plol => sd_link_error(2), -- loss of lock in TX PLL\r
- oob_out_ch0 => open -- not needed\r
- );\r
-end generate clk_ext;\r
-\r
-SD_RX_DATA_PROC: process( sd_rx_clk )\r
-begin\r
- if( rising_edge(sd_rx_clk) ) then\r
- sd_rx_debug(15 downto 12) <= (others => '0');\r
- sd_rx_debug(11) <= sd_rx_disp_error;\r
- sd_rx_debug(10) <= sd_rx_even;\r
- sd_rx_debug(9) <= sd_rx_cv_error;\r
- sd_rx_debug(8) <= sd_rx_kcntl;\r
- sd_rx_debug(7 downto 0) <= sd_rx_data;\r
- end if;\r
-end process SD_RX_DATA_PROC;\r
-\r
-SD_TX_DATA_PROC: process( sd_tx_clk )\r
-begin\r
- if( rising_edge(sd_tx_clk) ) then\r
- sd_tx_debug(15 downto 10) <= (others => '0');\r
- sd_tx_debug(9) <= sd_tx_correct_disp;\r
- sd_tx_debug(8) <= sd_tx_kcntl;\r
- sd_tx_debug(7 downto 0) <= sd_tx_data;\r
- end if;\r
-end process SD_TX_DATA_PROC;\r
-\r
-buf_stat_debug(63 downto 40) <= (others => '0');\r
-buf_stat_debug(39 downto 36) <= reset_debug(3 downto 0);\r
-buf_stat_debug(35 downto 32) <= reset_bsm;\r
--- logic analyzer signals\r
-buf_stat_debug(31) <= pcs_mr_page_rx;\r
-buf_stat_debug(30) <= pcs_mr_reset; --pcs_mr_an_complete;\r
-buf_stat_debug(28 downto 26) <= reset_bsm(2 downto 0);\r
-buf_stat_debug(25 downto 23) <= sd_link_error(2 downto 0);\r
-buf_stat_debug(22) <= sd_link_ok;\r
-buf_stat_debug(21 downto 12) <= sd_tx_debug(9 downto 0);\r
-buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0);\r
-\r
-\r
-SGMII_GBE_PCS : sgmii_gbe_pcs32\r
-port map(\r
- rst_n => GSR_N,\r
- signal_detect => sd_link_ok,\r
- gbe_mode => '1',\r
- sgmii_mode => MR_MODE_IN,\r
- operational_rate => "10",\r
- debug_link_timer_short => '0',\r
- rx_compensation_err => pcs_rx_comp_err,\r
- -- MAC interface\r
- tx_clk_125 => refclkcore, -- original clock from SerDes\r
- tx_clock_enable_source => pcs_tx_clk_en,\r
- tx_clock_enable_sink => pcs_tx_clk_en,\r
- tx_d => FT_TXD_IN, -- TX data from MAC\r
- tx_en => FT_TX_EN_IN, -- TX data enable from MAC\r
- tx_er => FT_TX_ER_IN, -- TX error from MAC\r
- rx_clk_125 => refclkcore, -- original clock from SerDes\r
- rx_clock_enable_source => pcs_rx_clk_en,\r
- rx_clock_enable_sink => pcs_rx_clk_en,\r
- rx_d => pcs_rx_d, -- RX data to MAC\r
- rx_dv => pcs_rx_dv, -- RX data enable to MAC\r
- rx_er => pcs_rx_er, -- RX error to MAC\r
- col => FT_COL_OUT,\r
- crs => FT_CRS_OUT,\r
- -- SerDes interface\r
- tx_data => sd_tx_data, -- TX data to SerDes\r
- tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes\r
- tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes)\r
- serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream\r
- rx_data => sd_rx_data, -- RX data from SerDes\r
- rx_kcntl => sd_rx_kcntl, -- RX komma control from SerDes\r
- rx_err_decode_mode => '0', -- receive error control mode fixed to normal\r
- rx_even => '0', -- unused (receive error control mode = normal, tie to GND)\r
- rx_disp_err => sd_rx_disp_error, -- RX disparity error from SerDes\r
- rx_cv_err => sd_rx_cv_error, -- RX code violation error from SerDes\r
- -- Autonegotiation stuff\r
- mr_an_complete => pcs_mr_an_complete,\r
- mr_page_rx => pcs_mr_page_rx,\r
- mr_lp_adv_ability => pcs_mr_ability,\r
- mr_main_reset => pcs_mr_reset,\r
- mr_an_enable => MR_AN_ENABLE_IN,\r
- mr_restart_an => MR_RESTART_AN_IN,\r
- mr_adv_ability => MR_ADV_ABILITY_IN\r
-);\r
-\r
-pcs_mr_reset <= MR_RESET_IN or RESET or user_rst;\r
-\r
-FT_TX_CLK_EN_OUT <= pcs_tx_clk_en; -- to MAC\r
-FT_RX_CLK_EN_OUT <= pcs_rx_clk_en; -- to MAC\r
-\r
-MR_AN_LP_ABILITY_OUT <= pcs_mr_ability;\r
-MR_AN_COMPLETE_OUT <= pcs_mr_an_complete;\r
-MR_AN_PAGE_RX_OUT <= pcs_mr_page_rx;\r
-\r
--- Clock games\r
-CLK_125_OUT <= refclkcore;\r
-\r
--- Fakes\r
-STAT_OP <= (others => '0');\r
-SD_TXDIS_OUT <= '0'; -- enable \r
-STAT_DEBUG <= buf_stat_debug;\r
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-library work;
-use work.trb_net_std.all;
-
-package trb_net_gbe_components is
-
--- gk 01.07.10
-component trb_net16_ipu2gbe is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
- MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- -- PacketConstructor interface
- ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic; -- gk 07.10.10
- PC_EOD_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_PADDING_OUT : out std_logic;
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
-);
-end component;
-
-component trb_net16_gbe_packet_constr is
-port(
- RESET : in std_logic;
- CLK : in std_logic;
- MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10
- -- ports for user logic
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
- PC_DATA_IN : in std_logic_vector(7 downto 0);
- PC_READY_OUT : out std_logic;
- PC_START_OF_SUB_IN : in std_logic;
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10
- PC_END_OF_DATA_IN : in std_logic;
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
- PC_PADDING_IN : in std_logic; -- gk 29.03.10
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10
- -- FrameConstructor ports
- FC_WR_EN_OUT : out std_logic;
- FC_DATA_OUT : out std_logic_vector(7 downto 0);
- FC_H_READY_IN : in std_logic;
- FC_READY_IN : in std_logic;
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_IDENT_OUT : out std_logic_vector(15 downto 0);
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- FC_SOD_OUT : out std_logic;
- FC_EOD_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_frame_constr is
-port(
- -- ports for user logic
- RESET : in std_logic;
- CLK : in std_logic;
- LINK_OK_IN : in std_logic; -- gk 03.08.10
- --
- WR_EN_IN : in std_logic;
- DATA_IN : in std_logic_vector(7 downto 0);
- START_OF_DATA_IN : in std_logic;
- END_OF_DATA_IN : in std_logic;
- IP_F_SIZE_IN : in std_logic_vector(15 downto 0);
- UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation
- HEADERS_READY_OUT : out std_logic;
- READY_OUT : out std_logic;
- DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
- IHL_VERSION_IN : in std_logic_vector(7 downto 0);
- TOS_IN : in std_logic_vector(7 downto 0);
- IDENTIFICATION_IN : in std_logic_vector(15 downto 0);
- FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
- TTL_IN : in std_logic_vector(7 downto 0);
- PROTOCOL_IN : in std_logic_vector(7 downto 0);
- FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10
- -- ports for packetTransmitter
- RD_CLK : in std_logic; -- 125MHz clock!!!
- FT_DATA_OUT : out std_logic_vector(8 downto 0);
- FT_TX_EMPTY_OUT : out std_logic;
- FT_TX_RD_EN_IN : in std_logic;
- FT_START_OF_PACKET_OUT : out std_logic;
- FT_TX_DONE_IN : in std_logic;
- FT_TX_DISCFRM_IN : in std_logic;
- -- debug ports
- BSM_CONSTR_OUT : out std_logic_vector(7 downto 0);
- BSM_TRANS_OUT : out std_logic_vector(3 downto 0);
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_frame_trans is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
- LINK_OK_IN : in std_logic; -- gk 03.08.10
- TX_MAC_CLK : in std_logic;
- TX_EMPTY_IN : in std_logic;
- START_OF_PACKET_IN : in std_logic;
- DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC
- -- NEW PORTS
- HADDR_OUT : out std_logic_vector(7 downto 0);
- HDATA_OUT : out std_logic_vector(7 downto 0);
- HCS_OUT : out std_logic;
- HWRITE_OUT : out std_logic;
- HREAD_OUT : out std_logic;
- HREADY_IN : in std_logic;
- HDATA_EN_IN : in std_logic;
- TX_FIFOAVAIL_OUT : out std_logic;
- TX_FIFOEOF_OUT : out std_logic;
- TX_FIFOEMPTY_OUT : out std_logic;
- TX_DONE_IN : in std_logic;
- TX_DISCFRM_IN : in std_logic;
- -- Debug
- BSM_INIT_OUT : out std_logic_vector(3 downto 0);
- BSM_MAC_OUT : out std_logic_vector(3 downto 0);
- BSM_TRANS_OUT : out std_logic_vector(3 downto 0);
- DBG_RD_DONE_OUT : out std_logic;
- DBG_INIT_DONE_OUT : out std_logic;
- DBG_ENABLED_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_med_ecp_sfp_gbe_8b is
--- gk 28.04.10
-generic (
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
-);
-port(
- RESET : in std_logic;
- GSR_N : in std_logic;
- CLK_125_OUT : out std_logic;
- CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk
- --SGMII connection to frame transmitter (tsmac)
- FT_TX_CLK_EN_OUT : out std_logic;
- FT_RX_CLK_EN_OUT : out std_logic;
- FT_COL_OUT : out std_logic;
- FT_CRS_OUT : out std_logic;
- FT_TXD_IN : in std_logic_vector(7 downto 0);
- FT_TX_EN_IN : in std_logic;
- FT_TX_ER_IN : in std_logic;
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic;
- SD_REFCLK_N_IN : in std_logic;
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic; -- SFP disable
- -- Autonegotiation stuff
- MR_RESET_IN : in std_logic;
- MR_MODE_IN : in std_logic;
- MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0);
- MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0);
- MR_AN_PAGE_RX_OUT : out std_logic;
- MR_AN_COMPLETE_OUT : out std_logic;
- MR_AN_ENABLE_IN : in std_logic;
- MR_RESTART_AN_IN : in std_logic;
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
-);
-end component;
-
-component gbe_setup is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
-
- -- interface to regio bus
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
-
- GBE_TRIG_NR_IN : in std_logic_vector(31 downto 0);
-
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0);
- GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0);
- GBE_MAX_PACKET_OUT : out std_logic_vector(31 downto 0);
- GBE_MIN_PACKET_OUT : out std_logic_vector(31 downto 0);
- GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0);
- GBE_USE_GBE_OUT : out std_logic;
- GBE_USE_TRBNET_OUT : out std_logic;
- GBE_USE_MULTIEVENTS_OUT : out std_logic;
- GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10
- GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10
- GBE_DELAY_OUT : out std_logic_vector(31 downto 0);
- GBE_ALLOW_LARGE_OUT : out std_logic;
- GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10
- -- gk 28.07.10
- MONITOR_BYTES_IN : in std_logic_vector(31 downto 0);
- MONITOR_SENT_IN : in std_logic_vector(31 downto 0);
- MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0);
- MONITOR_SM_IN : in std_logic_vector(31 downto 0);
- MONITOR_LR_IN : in std_logic_vector(31 downto 0);
- MONITOR_HDR_IN : in std_logic_vector(31 downto 0);
- MONITOR_FIFOS_IN : in std_logic_vector(31 downto 0);
- MONITOR_DISCFRM_IN : in std_logic_vector(31 downto 0);
- MONITOR_LINK_DWN_IN : in std_logic_vector(31 downto 0); -- gk 30.09.10
- MONITOR_EMPTY_IN : in std_logic_vector(31 downto 0); -- gk 01.10.10
- -- gk 01.06.10
- DBG_IPU2GBE1_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE2_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE3_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE4_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE5_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE6_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE7_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE8_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE9_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE10_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE11_IN : in std_logic_vector(31 downto 0);
- DBG_IPU2GBE12_IN : in std_logic_vector(31 downto 0);
- DBG_PC1_IN : in std_logic_vector(31 downto 0);
- DBG_PC2_IN : in std_logic_vector(31 downto 0);
- DBG_FC1_IN : in std_logic_vector(31 downto 0);
- DBG_FC2_IN : in std_logic_vector(31 downto 0);
- DBG_FT1_IN : in std_logic_vector(31 downto 0);
- DBG_FT2_IN : in std_logic_vector(31 downto 0);
- DBG_FIFO_RD_EN_OUT : out std_logic;
- DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0)
- --DBG_FIFO_RESET_OUT : out std_logic
-);
-end component;
-
-
-component ip_configurator is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- configuration interface
- START_CONFIG_IN : in std_logic; -- start configuration run
- BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank
- CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used
- MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for
- MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory
- MEM_CLK_OUT : out std_logic; -- clock for BlockRAM
- -- information for IP cores
- DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address
- DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address
- DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port
- SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address
- SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address
- SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port
- MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size)
- -- Debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end component;
-
-end package;
\ No newline at end of file
MAC_CONF_MACHINE_PROC : process(CLK)
begin
- if RESET = '1' then
- mac_conf_current_state <= IDLE;
- elsif rising_edge(CLK) then
- mac_conf_current_state <= mac_conf_next_state;
+ if( rising_edge(CLK) ) then
+ if( RESET = '1' ) then
+ mac_conf_current_state <= IDLE;
+ else
+ mac_conf_current_state <= mac_conf_next_state;
+ end if;
end if;
end process MAC_CONF_MACHINE_PROC;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-
-entity forwarder is
- port(
- CLK : in std_logic;\r
- CLEAR : in std_logic;\r
- RESET : in std_logic;
- --
- FRAME_AVAIL_IN : in std_logic;
- FIFO_FULL_IN : in std_logic;
- FRAME_REQ_OUT : out std_logic;
- FRAME_ACK_IN : in std_logic;\r
- --\r
- DEBUG : out std_logic_vector(15 downto 0)
- );
-end entity forwarder;
-
-architecture forwarder_arch of forwarder is
-
--- Components
-
--- state machine signals
- type state_t is (IDLE,REQ,ACK);
- signal STATE, NEXT_STATE : state_t;\r
-
--- Signals
- signal rb_full : std_logic;\r
- signal req_x : std_logic;
- signal req_q : std_logic;
-\r
-begin
-\r
- -----------------------------------------------------------
- -- statemachine: clocked process
- -----------------------------------------------------------
- THE_FSM: process( CLK, CLEAR )
- begin
- if ( CLEAR = '1' ) then
- STATE <= IDLE;
- req_q <= '0';
- elsif( rising_edge(CLK) ) then
- STATE <= NEXT_STATE;
- req_q <= req_x;
- end if;
- end process THE_FSM;\r
-\r
- THE_STATE_TRANSITIONS: process( STATE, FIFO_FULL_IN, FRAME_AVAIL_IN, FRAME_ACK_IN )
- begin
- req_x <= '0';
- \r
- case STATE is
-\r
- when IDLE =>\r
- if( (FIFO_FULL_IN = '0') and (FRAME_AVAIL_IN = '1') ) then\r
- NEXT_STATE <= REQ;
- req_x <= '1';\r
- else\r
- NEXT_STATE <= IDLE;\r
- end if;\r
- \r
- when REQ =>\r
- if( FRAME_ACK_IN = '1' ) then\r
- NEXT_STATE <= ACK;\r
- else\r
- NEXT_STATE <= REQ;\r
- end if;\r
- \r
- when ACK =>
- NEXT_STATE <= IDLE;\r
-\r
- when others =>\r
- NEXT_STATE <= IDLE;\r
- end case;\r
- end process THE_STATE_TRANSITIONS;\r
-\r
- FRAME_REQ_OUT <= req_q;\r
-
-end architecture;
+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-\r
-entity gather_ports is\r
- port(\r
- CLK : in std_logic;\r
- CLEAR : in std_logic;\r
- RESET : in std_logic;\r
- --\r
- FRAME_AVAIL_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
- FRAME_REQ_OUT : out std_logic_vector(15 downto 0);\r
- FRAME_ACK_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
- PORT_SELECT_OUT : out std_logic_vector(15 downto 0);\r
- CYCLE_DONE_OUT : out std_logic;\r
- --\r
- DEBUG : out std_logic_vector(15 downto 0)\r
- );\r
-end entity gather_ports;\r
-\r
-architecture gather_ports_arch of gather_ports is\r
-\r
--- Components\r
-\r
--- state machine signals\r
- type state_t is (IDLE, STORE, DO_PORTS, DELAY, CLEANUP);\r
- signal STATE, NEXT_STATE : state_t;\r
-\r
--- Signals\r
- signal gather_needed_x : std_logic;\r
- signal store_ports_x : std_logic;\r
- signal all_ports_done_x : std_logic;\r
- signal stored_ports : std_logic_vector(15 downto 0);
- signal next_port_x : std_logic_vector(15 downto 0);\r
- signal select_ports : std_logic_vector(15 downto 0);\r
- signal req_ports : std_logic_vector(15 downto 0);\r
-\r
-begin\r
-\r
- -- we need to start a gather cycle if any src port has frames available\r
- gather_needed_x <= '1' when FRAME_AVAIL_IN /= x"0000" else '0';\r
-\r
- -- store the src port status\r
- GEN_REGS: for I in 0 to 15 generate\r
- THE_SRC_STORE_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- stored_ports(I) <= '0';\r
- elsif( rising_edge(CLK) ) then\r
- if( store_ports_x = '1' ) then\r
- stored_ports(I) <= FRAME_AVAIL_IN(I);\r
- elsif( FRAME_ACK_IN(I) = '1' ) then\r
- stored_ports(I) <= '0';\r
- end if;\r
- end if;\r
- end process THE_SRC_STORE_PROC;\r
- end generate;\r
-\r
- all_ports_done_x <= '1' when stored_ports = x"0000" else '0';\r
-\r
- -- select the port data\r
- THE_SELECT_PORT_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- select_ports <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- select_ports <= next_port_x;\r
- end if;\r
- end process THE_SELECT_PORT_PROC;\r
-\r
- PORT_SELECT_OUT <= select_ports;\r
-\r
- -- port frame request, one clock cycle pulse\r
- req_ports <= not select_ports and next_port_x when rising_edge(CLK);\r
-\r
- FRAME_REQ_OUT <= req_ports;\r
-\r
- CYCLE_DONE_OUT <= '1' when STATE = CLEANUP else '0';\r
-\r
- -- priority decoced "next port to serve" signals\r
- THE_NEXT_PORT_PROC: process( stored_ports )\r
- begin\r
- if ( stored_ports(0) = '1' ) then\r
- next_port_x <= x"0001";\r
- elsif( stored_ports(1) = '1' ) then
- next_port_x <= x"0002";
- elsif( stored_ports(2) = '1' ) then
- next_port_x <= x"0004";
- elsif( stored_ports(3) = '1' ) then
- next_port_x <= x"0008";
- elsif( stored_ports(4) = '1' ) then
- next_port_x <= x"0010";
- elsif( stored_ports(5) = '1' ) then
- next_port_x <= x"0020";
- elsif( stored_ports(6) = '1' ) then
- next_port_x <= x"0040";
- elsif( stored_ports(7) = '1' ) then
- next_port_x <= x"0080";
- elsif( stored_ports(8) = '1' ) then
- next_port_x <= x"0100";
- elsif( stored_ports(9) = '1' ) then
- next_port_x <= x"0200";
- elsif( stored_ports(10) = '1' ) then
- next_port_x <= x"0400";
- elsif( stored_ports(11) = '1' ) then
- next_port_x <= x"0800";
- elsif( stored_ports(12) = '1' ) then
- next_port_x <= x"1000";
- elsif( stored_ports(13) = '1' ) then
- next_port_x <= x"2000";
- elsif( stored_ports(14) = '1' ) then
- next_port_x <= x"4000";
- elsif( stored_ports(15) = '1' ) then
- next_port_x <= x"8000";\r
- else\r
- next_port_x <= x"0000";
- end if;
- end process THE_NEXT_PORT_PROC;\r
-\r
- -----------------------------------------------------------\r
- -- statemachine: clocked process\r
- -----------------------------------------------------------\r
- THE_FSM: process( CLK, CLEAR )\r
- begin\r
- if ( CLEAR = '1' ) then\r
- STATE <= IDLE;\r
- elsif( rising_edge(CLK) ) then\r
- STATE <= NEXT_STATE;\r
- end if;\r
- end process THE_FSM;\r
-\r
- THE_STATE_TRANSITIONS: process( STATE, gather_needed_x, all_ports_done_x )\r
- begin\r
- store_ports_x <= '0';\r
-\r
- case STATE is\r
-\r
- when IDLE =>\r
- if( gather_needed_x = '1' ) then\r
- NEXT_STATE <= STORE;\r
- store_ports_x <= '1';\r
- else\r
- NEXT_STATE <= IDLE;\r
- end if;\r
-\r
- when STORE =>\r
- NEXT_STATE <= DO_PORTS;\r
-\r
- when DO_PORTS =>\r
- if( all_ports_done_x = '1' ) then\r
- NEXT_STATE <= DELAY;\r
- else\r
- NEXT_STATE <= DO_PORTS;\r
- end if;\r
-\r
- when DELAY =>\r
- NEXT_STATE <= CLEANUP;\r
-\r
- when CLEANUP =>\r
- if( gather_needed_x = '1' ) then\r
- NEXT_STATE <= STORE;\r
- store_ports_x <= '1';\r
- else\r
- NEXT_STATE <= IDLE;\r
- end if;\r
-\r
- when others =>\r
- NEXT_STATE <= IDLE;\r
- end case;\r
- end process THE_STATE_TRANSITIONS;\r
-\r
-\r
-\r
-end architecture;\r
+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-\r
-entity gbe_lsm is\r
- port(\r
- CLK : in std_logic;\r
- CLEAR : in std_logic;\r
- RESET : in std_logic;\r
- -- \r
- MAC_AN_COMPLETE_IN : in std_logic; -- PCS Autonegotiation completed\r
- MAC_READY_CONF_IN : in std_logic; -- MAC configuration completed\r
- MAC_RECONF_OUT : out std_logic; -- start MAC configuration\r
- --\r
- LINK_ACTIVE_OUT : out std_logic;\r
- --\r
- DEBUG : out std_logic_vector(15 downto 0)\r
- );\r
-end entity gbe_lsm;\r
-\r
-architecture gbe_lsm_arch of gbe_lsm is\r
-\r
--- Components\r
-\r
--- state machine signals\r
- type state_t is (INACTIVE,WAIT_PCS,ENABLE_MAC,DELAY,ACTIVATED);\r
- signal STATE, NEXT_STATE : state_t;\r
-\r
--- Signals\r
- signal dly_ctr : unsigned(15 downto 0);\r
- signal ce_dly_ctr : std_logic;\r
- signal rst_dly_ctr : std_logic;\r
- signal dly_ctr_done : std_logic;\r
- signal reconf_mac : std_logic;\r
-\r
-begin\r
-\r
- MAC_RECONF_OUT <= reconf_mac;\r
-\r
- LINK_ACTIVE_OUT <= '1' when (STATE = ACTIVATED) else '0';\r
- \r
- THE_DLY_CTR: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- dly_ctr <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- if ( rst_dly_ctr = '1' ) then\r
- dly_ctr <= (others => '0');\r
- elsif( ce_dly_ctr = '1' ) then\r
- dly_ctr <= dly_ctr + 1;\r
- end if;\r
- end if;\r
- end process THE_DLY_CTR;\r
- \r
- dly_ctr_done <= '1' when dly_ctr = x"ffff" else '0';\r
-\r
- -----------------------------------------------------------\r
- -- statemachine: clocked process\r
- -----------------------------------------------------------\r
- THE_FSM: process( CLK, CLEAR )\r
- begin\r
- if ( CLEAR = '1' ) then\r
- STATE <= INACTIVE;\r
- elsif( rising_edge(CLK) ) then\r
- STATE <= NEXT_STATE;\r
- end if;\r
- end process THE_FSM;\r
-\r
- THE_STATE_TRANSITIONS: process( STATE, MAC_AN_COMPLETE_IN, MAC_READY_CONF_IN, dly_ctr_done )\r
- begin\r
- reconf_mac <= '0';\r
- ce_dly_ctr <= '0';\r
- rst_dly_ctr <= '0';\r
- \r
- case STATE is\r
-\r
- when INACTIVE =>\r
- rst_dly_ctr <= '1';\r
- if( MAC_AN_COMPLETE_IN = '1' ) then\r
- NEXT_STATE <= WAIT_PCS;\r
- else\r
- NEXT_STATE <= INACTIVE;\r
- end if;\r
-\r
- when WAIT_PCS =>\r
- ce_dly_ctr <= '1';\r
- if( MAC_AN_COMPLETE_IN = '0' ) then\r
- NEXT_STATE <= INACTIVE;\r
- else\r
- if( dly_ctr_done = '1' ) then \r
- NEXT_STATE <= ENABLE_MAC;\r
- reconf_mac <= '1';\r
- else\r
- NEXT_STATE <= WAIT_PCS;\r
- end if;\r
- end if;\r
-\r
- when ENABLE_MAC =>\r
- rst_dly_ctr <= '1';\r
- if( MAC_AN_COMPLETE_IN = '0' ) then\r
- NEXT_STATE <= INACTIVE;\r
- else\r
- if( MAC_READY_CONF_IN = '1' ) then\r
- NEXT_STATE <= DELAY;\r
- else \r
- NEXT_STATE <= ENABLE_MAC;\r
- end if;\r
- end if;\r
-\r
- when DELAY =>\r
- ce_dly_ctr <= '1';\r
- if( MAC_AN_COMPLETE_IN = '0' ) then\r
- NEXT_STATE <= INACTIVE;\r
- else\r
- if( dly_ctr_done = '1' ) then\r
- NEXT_STATE <= ACTIVATED;\r
- else \r
- NEXT_STATE <= DELAY;\r
- end if;\r
- end if;\r
- \r
- when ACTIVATED =>\r
- rst_dly_ctr <= '1';\r
- if( MAC_AN_COMPLETE_IN = '0' ) then\r
- NEXT_STATE <= INACTIVE;\r
- else\r
- NEXT_STATE <= ACTIVATED;\r
- end if;\r
-\r
- when others =>\r
- NEXT_STATE <= INACTIVE;\r
- end case;\r
- end process THE_STATE_TRANSITIONS;\r
-\r
-end architecture;\r
);
port(
RESET : in std_logic;
- GSR_N : in std_logic;
- CLK_SYS : in std_logic;
+ RESET_N : in std_logic;
+ CLEAR : in std_logic;
+ CLEAR_N : in std_logic;
CLK_125 : in std_logic;
- CLK_125_RX : out std_logic_vector(3 downto 0);
-- FIFO interface RX
FIFO_DATA_OUT : out std_logic_vector(4 * 9 - 1 downto 0);
FIFO_FULL_IN : in std_logic_vector(3 downto 0);
);
end entity gbe_med_fifo;
-architecture RTL of gbe_med_fifo is
+architecture gbe_med_fifo_arch of gbe_med_fifo is
component sgmii_gbe_pcs42
port(
signal rx_pcs_rst_q : std_logic_vector(3 downto 0);
signal rx_serdes_rst : std_logic_vector(3 downto 0);
signal rx_serdes_rst_q : std_logic_vector(3 downto 0);
- signal init_quad : std_logic;
signal tx_plol_lol : std_logic;
signal debug : std_logic_vector(63 downto 0);
signal led_timer_done : std_logic;
signal led_activity_x : std_logic_vector(3 downto 0);
signal led_activity : std_logic_vector(4 * 2 - 1 downto 0);
-
-begin
- init_quad <= not GSR_N;
+ attribute HGROUP : string;
+-- attribute BBOX : string;
+ attribute HGROUP of gbe_med_fifo_arch : architecture is "gbe_med_fifo_group";
+-- attribute BBOX of ddmtd_arch : architecture is "2,2";
+
+begin
gbe_serdes: entity serdes_gbe_4ch_ds
port map(
fpga_txrefclk => CLK_125,
tx_serdes_rst_c => '0',
tx_pll_lol_qd_s => tx_plol_lol,
- rst_qd_c => init_quad,
+ rst_qd_c => CLEAR, -- ONLY ONCE
serdes_rst_qd_c => '0',
tx_sync_qd_c => '0'
);
-- CAVEAT: reset signals MUST BE sync'ed to recovered RX clock!
THE_MAIN_RX_RST: main_rx_reset_RS
port map(
- CLEAR => init_quad,
+ CLEAR => CLEAR,
CLK_REF => CLK_125,
CDR_LOL_IN => rx_cdr_lol(i),
CV_IN => sd_rx_cv_error(i),
D_OUT(0) => rx_pcs_rst_q(i),
D_OUT(1) => rx_serdes_rst_q(i)
);
-
- CLK_125_RX(i) <= sd_rx_clk(i);
-- SGMII core
SGMII_GBE_PCS : sgmii_gbe_pcs42
port map(
- rst_n => GSR_N,
+ rst_n => RESET_N,
signal_detect => link_rx_ready(i),
gbe_mode => '1',
sgmii_mode => '0',
operational_rate((i + 1) * 2 - 1 downto i * 2) <= b"10";
- mr_main_reset(i) <= init_quad;
+ mr_main_reset(i) <= RESET;
mr_restart_an(i) <= pulse(i);
mr_an_enable(i) <= link_rx_ready(i);
mr_adv_ability((i + 1) * 16 - 1 downto i * 16) <= x"0020";
hclk => CLK_125, -- BUG: can be CLK_125
txmac_clk => CLK_125,
rxmac_clk => CLK_125,
- reset_n => GSR_N,
+ reset_n => RESET_N,
------------------- Input signals to the GMII ----------------
rxd => pcs_rxd((i + 1) * 8 - 1 downto i * 8),
rx_dv => pcs_rx_en(i),
-- CAN BE OPTIMIZED
TSMAC_CONTROLLER : trb_net16_gbe_mac_control
port map(
- CLK => CLK_125, -- BUG: can be CLK_125
+ CLK => CLK_125,
RESET => RESET,
-- signals to/from main controller
MC_TSMAC_READY_OUT => mac_ready_conf(i),
-- initializes MAC after AN is complete
THE_FW_GBE_LSM: entity gbe_lsm
port map(
- CLK => CLK_125, -- BUG: can be CLK_125
- CLEAR => init_quad,
+ CLK => CLK_125,
RESET => RESET,
--
MAC_AN_COMPLETE_IN => an_complete(i),
THE_FW_RB: entity rx_rb
port map(
CLK => CLK_125,
- CLEAR => init_quad,
RESET => RESET,
-- MAC interface (RX)
MAC_RX_DATA_IN => mac_rx_data((i + 1) * 8 - 1 downto i * 8),
THE_FW_FIFO: entity tx_fifo
port map(
CLK => CLK_125,
- CLEAR => init_quad,
RESET => RESET,
-- MAC interface
MAC_TX_DATA_OUT => mac_tx_data((i + 1) * 8 - 1 downto i * 8),
led_timer_done_x <= '1' when (std_logic_vector(led_timer) = x"fffff") else '0';
-end architecture RTL;
+end architecture gbe_med_fifo_arch;
port(
RESET : in std_logic;
GSR_N : in std_logic;
- CLK_SYS : in std_logic;
CLK_125 : in std_logic;
- CLK_125_RX : out std_logic_vector(3 downto 0);
-- MAC status and config
MAC_READY_CONF_OUT : out std_logic_vector(3 downto 0);
MAC_RECONF_IN : in std_logic_vector(3 downto 0) := (others => '0');
D_OUT(0) => rx_pcs_rst_q(i),
D_OUT(1) => rx_serdes_rst_q(i)
);
-
- CLK_125_RX(i) <= sd_rx_clk(i);
-- SGMII core
SGMII_GBE_PCS : sgmii_gbe_pcs42
MAC: tsmac41
port map(
----------------- clock and reset port declarations ------------------
- hclk => CLK_SYS,
+ hclk => CLK_125,
txmac_clk => CLK_125,
rxmac_clk => CLK_125,
reset_n => GSR_N,
TSMAC_CONTROLLER : trb_net16_gbe_mac_control
port map(
- CLK => CLK_SYS,
+ CLK => CLK_125,
RESET => RESET,
-- signals to/from main controller
MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(i),
+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-\r
-entity rx_rb is\r
- port(\r
- CLK : in std_logic;\r
- CLEAR : in std_logic;\r
- RESET : in std_logic;\r
- -- MAC interface (RX)\r
- MAC_RX_DATA_IN : in std_logic_vector(7 downto 0); -- RX data from TSMAC\r
- MAC_RX_WR_IN : in std_logic; -- RX data write from TSMAC\r
- MAC_RX_EOF_IN : in std_logic; -- RX EndOfFrame from TSMAC\r
- MAC_RX_ERROR_IN : in std_logic; -- RX Error from TSMAC\r
- MAC_RX_FIFOFULL_OUT : out std_logic;\r
- -- FIFO interface (TX)\r
- FIFO_FULL_IN : in std_logic; -- TX fifo full, delay read from ring buffer\r
- FIFO_WR_OUT : out std_logic; -- TX fifo write\r
- FIFO_Q_OUT : out std_logic_vector(8 downto 0); -- TX data\r
- FRAME_REQ_IN : in std_logic; -- one pulse starts readout of frame stored in ring buffer\r
- FRAME_ACK_OUT : out std_logic; -- one pulse for "end of frame"\r
- FRAME_AVAIL_OUT : out std_logic; -- number of frames stored in ring buffer\r
- FRAME_START_OUT : out std_logic; -- StartOfFrame signal\r
- --\r
- DEBUG : out std_logic_vector(15 downto 0)\r
- );\r
-end entity rx_rb;\r
-\r
-architecture rx_rb_arch of rx_rb is\r
-\r
--- Components\r
- component rb_4k_9\r
- port(\r
- WRADDRESS : in std_logic_vector(11 downto 0); \r
- RDADDRESS : in std_logic_vector(11 downto 0); \r
- DATA : in std_logic_vector(8 downto 0); \r
- WE : in std_logic; \r
- RDCLOCK : in std_logic; \r
- RDCLOCKEN : in std_logic; \r
- RESET : in std_logic; \r
- WRCLOCK : in std_logic; \r
- WRCLOCKEN : in std_logic; \r
- Q : out std_logic_vector(8 downto 0)\r
- );\r
- end component rb_4k_9;\r
-\r
--- state machine signals\r
- type state_t is (RX_DENY,RX_READY,RX_FRAME,FRAME_OK,FRAME_BAD,FORWARD,SKIP);\r
- signal STATE, NEXT_STATE : state_t;\r
-\r
--- Signals\r
- signal rd_ptr : unsigned(11 downto 0);\r
- signal wr_ptr : unsigned(11 downto 0);\r
- signal last_wr_ptr : std_logic_vector(11 downto 0);\r
- signal rb_used : unsigned(11 downto 0);\r
- signal rb_full : std_logic;\r
- signal rb_empty : std_logic;\r
- signal ce_wr_ptr : std_logic;\r
- signal ld_wr_ptr : std_logic;\r
- signal ce_rd_ptr : std_logic;\r
- signal wr_ram : std_logic;\r
- signal rd_ram : std_logic;\r
- signal ram_q : std_logic_vector(8 downto 0);\r
- signal frame_active : std_logic;\r
- signal frame_requested : std_logic;\r
- signal fifo_wr_int : std_logic;\r
- signal empty_read_ack : std_logic;\r
- signal normal_read_ack : std_logic;\r
- signal sof_int : std_logic;\r
- signal frames_avail : unsigned(7 downto 0);\r
-\r
-\r
-begin\r
-\r
- -- FrameActive: we must not change to "receive" in the middle of a frame\r
- -- when "buffer full" condition is deasserted\r
- THE_FRAME_ACTIVE_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- frame_active <= '0';\r
- elsif( rising_edge(CLK) ) then\r
- if( (MAC_RX_WR_IN = '1') and (frame_active = '0') ) then\r
- frame_active <= '1';\r
- elsif( (MAC_RX_EOF_IN = '1') and (frame_active = '1') ) then\r
- frame_active <= '0';\r
- end if;\r
- end if;\r
- end process THE_FRAME_ACTIVE_PROC;\r
-\r
- -- Write pointer for ring buffer\r
- THE_WR_PTR_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- wr_ptr <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- if ( ld_wr_ptr = '1' ) then\r
- wr_ptr <= unsigned(last_wr_ptr);\r
- elsif( ce_wr_ptr = '1' ) then\r
- wr_ptr <= wr_ptr + 1;\r
- end if;\r
- end if;\r
- end process THE_WR_PTR_PROC;\r
-\r
- -- Read pointer for ring buffer\r
- THE_RD_PTR_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- rd_ptr <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- if( ce_rd_ptr = '1' ) then\r
- rd_ptr <= rd_ptr + 1;\r
- end if;\r
- end if;\r
- end process THE_RD_PTR_PROC;\r
-\r
- -- ring buffer fill level\r
- rb_used <= wr_ptr - rd_ptr;\r
- \r
- -- ring buffer full \r
- -- TAKE CARE: the last byte of a frame is taken into account\r
- -- by "one less" for the full condition\r
- rb_full <= '1' when (rb_used(11 downto 1) = b"1111_1111_111") else '0';\r
-\r
- rb_empty <= '1' when (rb_used(11 downto 0) = b"0000_0000_0000") else '0';\r
-\r
- MAC_RX_FIFOFULL_OUT <= rb_full;\r
- \r
- -- last write pointer: used to drop a broken frame, in case\r
- THE_LAST_WR_PTR_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- last_wr_ptr <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- if( (STATE = RX_READY) and (MAC_RX_WR_IN = '1') ) then\r
- last_wr_ptr <= std_logic_vector(wr_ptr);\r
- end if;\r
- end if;\r
- end process THE_LAST_WR_PTR_PROC;\r
-\r
- -- DPRAM as ring buffer\r
- THE_DP_RAM: rb_4k_9\r
- port map(\r
- WRADDRESS => std_logic_vector(wr_ptr),\r
- RDADDRESS => std_logic_vector(rd_ptr),\r
- DATA(8) => MAC_RX_EOF_IN,\r
- DATA(7 downto 0) => MAC_RX_DATA_IN,\r
- WE => wr_ram,\r
- RDCLOCK => CLK,\r
- RDCLOCKEN => '1',\r
- RESET => CLEAR,\r
- WRCLOCK => CLK,\r
- WRCLOCKEN => '1',\r
- Q => ram_q\r
- );\r
-\r
- -- write signal\r
- wr_ram <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) or\r
- ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) \r
- else '0';\r
- ce_wr_ptr <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) or\r
- ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) \r
- else '0';\r
-\r
- -- FrameReq signal, one pulse only\r
- THE_FRAME_REQ_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- frame_requested <= '0';\r
- elsif( rising_edge(CLK) ) then\r
- if( (FRAME_REQ_IN = '1') and (frame_requested = '0') ) then\r
- frame_requested <= '1';\r
- elsif( ((ram_q(8) = '1') and (frame_requested = '1')) or (empty_read_ack = '1') ) then\r
- frame_requested <= '0';\r
- end if;\r
- end if;\r
- end process THE_FRAME_REQ_PROC;\r
-\r
- -- EmptyReadAck signal, used to handle a request to RX_RB with no frame to send\r
- empty_read_ack <= FRAME_REQ_IN and rb_empty when rising_edge(CLK);\r
- \r
- -- NormalReadAck signal\r
- normal_read_ack <= ram_q(8) and fifo_wr_int;\r
- \r
- -- read signal\r
- rd_ram <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty = '0')) else '0';\r
- ce_rd_ptr <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty = '0')) else '0';\r
- \r
- sof_int <= FRAME_REQ_IN and not frame_requested when rising_edge(CLK);\r
- \r
- FRAME_ACK_OUT <= normal_read_ack or empty_read_ack;\r
- \r
- FRAME_START_OUT <= sof_int;\r
- \r
- FIFO_Q_OUT <= ram_q;\r
- \r
- fifo_wr_int <= rd_ram when rising_edge(CLK);\r
- \r
- FIFO_WR_OUT <= fifo_wr_int;\r
- \r
- -- FramesAvailable counter\r
- THE_FRAMES_AVAIL_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- frames_avail <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- if ( (STATE = FRAME_OK) and (normal_read_ack = '0') ) then\r
- -- one frame written successfully\r
- frames_avail <= frames_avail + 1;\r
- elsif( (STATE /= FRAME_OK) and (normal_read_ack = '1') ) then\r
- -- one frame read successfully\r
- frames_avail <= frames_avail - 1;\r
- end if;\r
- end if;\r
- end process THE_FRAMES_AVAIL_PROC;\r
- \r
- FRAME_AVAIL_OUT <= '1' when (frames_avail /= x"00") else '0';\r
-\r
- -----------------------------------------------------------\r
- -- statemachine: clocked process\r
- -----------------------------------------------------------\r
- THE_FSM: process( CLK, CLEAR )\r
- begin\r
- if ( CLEAR = '1' ) then\r
- STATE <= RX_DENY;\r
- elsif( rising_edge(CLK) ) then\r
- STATE <= NEXT_STATE;\r
- end if;\r
- end process THE_FSM;\r
-\r
- THE_STATE_TRANSITIONS: process( STATE, MAC_RX_WR_IN, MAC_RX_EOF_IN, MAC_RX_ERROR_IN, frame_active, rb_full )\r
- begin\r
- ld_wr_ptr <= '0';\r
- \r
- case STATE is\r
-\r
- when RX_DENY =>\r
- if( (frame_active = '0') and (rb_full = '0') ) then\r
- NEXT_STATE <= RX_READY;\r
- else\r
- NEXT_STATE <= RX_DENY;\r
- end if;\r
- \r
- when RX_READY =>\r
- if( MAC_RX_WR_IN = '1' ) then\r
- NEXT_STATE <= RX_FRAME;\r
- else\r
- NEXT_STATE <= RX_READY;\r
- end if;\r
- \r
- when RX_FRAME =>\r
- if ( (MAC_RX_EOF_IN = '1') and (MAC_RX_ERROR_IN = '0') and (rb_full = '0') ) then\r
- NEXT_STATE <= FRAME_OK;\r
- elsif( (MAC_RX_EOF_IN = '1') and ((MAC_RX_ERROR_IN = '1') or (rb_full = '1')) ) then\r
- NEXT_STATE <= FRAME_BAD;\r
- ld_wr_ptr <= '1';\r
- else\r
- NEXT_STATE <= RX_FRAME;\r
- end if;\r
- \r
- when FRAME_OK =>\r
- NEXT_STATE <= FORWARD;\r
- \r
- when FORWARD =>\r
- if( rb_full = '0' ) then\r
- NEXT_STATE <= RX_READY;\r
- else\r
- NEXT_STATE <= RX_DENY;\r
- end if;\r
-\r
- when FRAME_BAD =>\r
- NEXT_STATE <= SKIP;\r
- \r
- when SKIP =>\r
- if( rb_full = '0' ) then\r
- NEXT_STATE <= RX_READY;\r
- else\r
- NEXT_STATE <= RX_DENY;\r
- end if;\r
-\r
- when others =>\r
- NEXT_STATE <= RX_DENY;\r
- end case;\r
- end process THE_STATE_TRANSITIONS;\r
-\r
-\r
-\r
-end architecture;\r
+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-\r
-entity scatter_ports is\r
- port(\r
- CLK : in std_logic;\r
- CLEAR : in std_logic;\r
- RESET : in std_logic;\r
- --\r
- FIFO_FULL_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
- FIFO_FULL_OUT : out std_logic;\r
- FRAME_AVAIL_IN : in std_logic := '0';\r
- FRAME_REQ_OUT : out std_logic;\r
- FRAME_ACK_IN : in std_logic := '0';\r
- CYCLE_DONE_OUT : out std_logic;\r
- --\r
- DEBUG : out std_logic_vector(15 downto 0)\r
- );\r
-end entity scatter_ports;\r
-\r
-architecture scatter_ports_arch of scatter_ports is\r
-\r
--- Components\r
-\r
--- state machine signals\r
- type state_t is (IDLE, DO_PORT, DELAY, CLEANUP);\r
- signal STATE, NEXT_STATE : state_t;\r
-\r
--- Signals\r
- signal req_int : std_logic;\r
- signal req_x : std_logic;\r
-\r
-begin\r
-\r
- CYCLE_DONE_OUT <= '1' when STATE = CLEANUP else '0';\r
-\r
- FRAME_REQ_OUT <= req_int;\r
-\r
- FIFO_FULL_OUT <= '0' when FIFO_FULL_IN = x"0000" else '1';\r
- \r
- -----------------------------------------------------------\r
- -- statemachine: clocked process\r
- -----------------------------------------------------------\r
- THE_FSM: process( CLK, CLEAR )\r
- begin\r
- if ( CLEAR = '1' ) then\r
- STATE <= IDLE;\r
- req_int <= '0';\r
- elsif( rising_edge(CLK) ) then\r
- STATE <= NEXT_STATE;\r
- req_int <= req_x;\r
- end if;\r
- end process THE_FSM;\r
-\r
- THE_STATE_TRANSITIONS: process( STATE, FRAME_AVAIL_IN, FRAME_ACK_IN )\r
- begin\r
- req_x <= '0';\r
-\r
- case STATE is\r
-\r
- when IDLE =>\r
- if( FRAME_AVAIL_IN = '1' ) then\r
- NEXT_STATE <= DO_PORT;\r
- req_x <= '1';\r
- else\r
- NEXT_STATE <= IDLE;\r
- end if;\r
-\r
- when DO_PORT =>\r
- if( FRAME_ACK_IN = '1' ) then\r
- NEXT_STATE <= DELAY;\r
- else\r
- NEXT_STATE <= DO_PORT;\r
- end if;\r
-\r
- when DELAY =>\r
- NEXT_STATE <= CLEANUP;\r
-\r
- when CLEANUP =>\r
- if( FRAME_AVAIL_IN = '1' ) then\r
- NEXT_STATE <= DO_PORT;\r
- req_x <= '1';\r
- else\r
- NEXT_STATE <= IDLE;\r
- end if;\r
-\r
- when others =>\r
- NEXT_STATE <= IDLE;\r
- end case;\r
- end process THE_STATE_TRANSITIONS;\r
-\r
-\r
-\r
-end architecture;\r
+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-\r
-entity tx_fifo is\r
- port(\r
- CLK : in std_logic;\r
- CLEAR : in std_logic;\r
- RESET : in std_logic;\r
- -- MAC interface\r
- MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0);\r
- MAC_TX_READ_IN : in std_logic;\r
- MAC_FIFOEOF_OUT : out std_logic; -- end of frame marker\r
- MAC_FIFOEMPTY_OUT : out std_logic; -- must never happen during TX\r
- MAC_FIFOAVAIL_OUT : out std_logic; -- starts TX process in MAC\r
- MAC_TX_DONE_IN : in std_logic; -- frame sent\r
- -- FIFO interface\r
- FIFO_FULL_OUT : out std_logic;\r
- FIFO_WR_IN : in std_logic;\r
- FIFO_D_IN : in std_logic_vector(8 downto 0);\r
- -- Link stuff\r
- FRAME_START_IN : in std_logic;\r
- LINK_ACTIVE_IN : in std_logic;\r
- --\r
- DEBUG : out std_logic_vector(15 downto 0)\r
- );\r
-end entity tx_fifo;\r
-\r
-architecture tx_fifo_arch of tx_fifo is\r
-\r
--- Components\r
- component fifo_4k_9\r
- port(\r
- DATA : in std_logic_vector(8 downto 0); \r
- CLOCK : in std_logic;\r
- WREN : in std_logic; \r
- RDEN : in std_logic;\r
- RESET : in std_logic;\r
- Q : out std_logic_vector(8 downto 0);\r
- EMPTY : out std_logic; \r
- FULL : out std_logic;\r
- ALMOSTFULL : out std_logic\r
- );\r
- end component fifo_4k_9;\r
-\r
--- component fifo_4k_9\r
--- port(\r
--- DATA : in std_logic_vector(8 downto 0); \r
--- WRCLOCK : in std_logic;\r
--- RDCLOCK : in std_logic;\r
--- WREN : in std_logic; \r
--- RDEN : in std_logic;\r
--- RESET : in std_logic;\r
--- RPRESET : in std_logic; \r
--- Q : out std_logic_vector(8 downto 0);\r
--- EMPTY : out std_logic; \r
--- FULL : out std_logic;\r
--- ALMOSTEMPTY : out std_logic; \r
--- ALMOSTFULL : out std_logic\r
--- );\r
--- end component fifo_4k_9;\r
- \r
--- state machine signals\r
-\r
--- Signals\r
- signal frames_avail : unsigned(7 downto 0);\r
- signal frame_written : std_logic;\r
- signal frame_read : std_logic;\r
- signal mac_fifoeof : std_logic;\r
- signal mac_tx_read : std_logic;\r
- signal frame_active : std_logic;\r
- signal fifo_wr : std_logic;\r
-\r
-begin\r
-\r
- -- FrameActice signal - used to inhibt acceptance of runt frames\r
- THE_FRAME_ACTIVE_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- frame_active <= '0';\r
- elsif( rising_edge(CLK) ) then\r
- if ( FRAME_START_IN = '1' ) then\r
- frame_active <= LINK_ACTIVE_IN;\r
- elsif( frame_written = '1' ) then\r
- frame_active <= '0';\r
- end if;\r
- end if;\r
- end process THE_FRAME_ACTIVE_PROC;\r
-\r
- fifo_wr <= FIFO_WR_IN and frame_active;\r
-\r
- -- TX FIFO storing full outgoing frames\r
- THE_TX_FIFO: fifo_4k_9\r
- port map(\r
- DATA => FIFO_D_IN,\r
- CLOCK => CLK,\r
- WREN => fifo_wr, --FIFO_WR_IN,\r
- RDEN => MAC_TX_READ_IN,\r
- RESET => CLEAR,\r
- Q(8) => mac_fifoeof,\r
- Q(7 downto 0) => MAC_TX_DATA_OUT,\r
- EMPTY => MAC_FIFOEMPTY_OUT, \r
- FULL => open,\r
- ALMOSTFULL => FIFO_FULL_OUT\r
- );\r
-\r
--- -- TX FIFO storing full outgoing frames\r
--- THE_TX_FIFO: fifo_4k_9\r
--- port map(\r
--- DATA => FIFO_D_IN,\r
--- WRCLOCK => CLK,\r
--- RDCLOCK => CLK,\r
--- WREN => fifo_wr, --FIFO_WR_IN,\r
--- RDEN => MAC_TX_READ_IN,\r
--- RESET => CLEAR,\r
--- RPRESET => CLEAR, \r
--- Q(8) => mac_fifoeof,\r
--- Q(7 downto 0) => MAC_TX_DATA_OUT,\r
--- EMPTY => MAC_FIFOEMPTY_OUT, \r
--- FULL => open,\r
--- ALMOSTEMPTY => open, \r
--- ALMOSTFULL => FIFO_FULL_OUT\r
--- );\r
- \r
- MAC_FIFOEOF_OUT <= mac_fifoeof;\r
-\r
- mac_tx_read <= MAC_TX_READ_IN when rising_edge(CLK);\r
-\r
- -- one frame written to FIFO\r
- frame_written <= '1' when (FIFO_D_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0';\r
-\r
- -- one frame read from FIFO\r
- frame_read <= '1' when (mac_fifoeof = '1') and (mac_tx_read = '1') else '0';\r
-\r
- -- FramesAvailable counter\r
- THE_FRAMES_AVAIL_PROC: process( CLK, CLEAR )\r
- begin\r
- if( CLEAR = '1' ) then\r
- frames_avail <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- if ( (frame_written = '1') and (frame_read = '0') ) then\r
- -- one frame written successfully\r
- frames_avail <= frames_avail + 1;\r
- elsif( (frame_written = '0') and (frame_read = '1') ) then\r
- -- one frame read successfully\r
- frames_avail <= frames_avail - 1;\r
- end if;\r
- end if;\r
- end process THE_FRAMES_AVAIL_PROC;\r
-\r
- MAC_FIFOAVAIL_OUT <= '1' when (frames_avail /= x"00") else '0';\r
-\r
-end architecture;\r
+++ /dev/null
--------------------------------------------------------------------------------
--- Title : Detector Trigger Unit
--- Project : HADES Second Level Trigger
--------------------------------------------------------------------------------
--- File : L12TrugBusInterface.vhd
--- Author : Markus Petri, Daniel Schaefer
--- Created : 2002/03/27
--- Last modified : 2007/01/12 T. Perez
--------------------------------------------------------------------------------
--- Description : Generic Interace for the Trigger Bus
---
--------------------------------------------------------------------------------
--- Modification history :
--- 2002/03/27 : created
--- 2002/05/31 : corrected TrigBus sequence, implemented BSY;
--- 2007/01/12 : change in libraries to adapt to trbnet: numeric -> arith
--- CLK_10 removed. Now DTU code is much faster than TRIGGERBUS.
--- 2007/02/23 : DVAL is not being produced. ???
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-
-entity L12TrigBusInterface is
- port (
--- from Trigger bus
- TSTR : in std_logic; -- trigger strobe
- DSTR : in std_logic; -- data strobe
- DIN : in std_logic_vector(3 downto 0);
--- to Trigger bus
- BSY : out std_logic;
- ERR : out std_logic;
--- general
- RES : in std_logic;
- CLK : in std_logic; -- should be 40 MHz!!
--- CLK_10 : in std_logic; -- should be 10 MHz
--- to state engine (and others)
- DVAL : out std_logic; -- high for 2 clk cycles when TRIGTAG
- -- and TRIGCODE have been received
- TRIGTAG : out std_logic_vector(7 downto 0);
- TRIGCODE : out std_logic_vector(3 downto 0);
--- from state engine
- TRIGTAG_MISMATCH : in std_logic; -- this is high whenever the received
- -- TRIGTAG is not equal to the DTU's
- -- internal counter and is not starting
- -- with a 0 at begin
- BUSY : in std_logic -- this should be controlled by the
- -- state engine and is passed directly
- -- to the trigger bus (where it is wired-
- -- or with all the other busy's from
- -- the DTU's, CTU)
- );
-end L12TrigBusInterface;
-
-architecture ARCH_L12TrigInterface of L12TrigBusInterface is
--------------------------------------------------------------------------------
- type ShiftReg is array (0 to 2) of
- std_logic_vector(3 downto 0);
--------------------------------------------------------------------------------
- signal NIBCNT : integer range 0 to 3; -- # of current nibble
- signal TRIGBUFF : ShiftReg;
- signal TSTR_REG, TSTR_REG_REG : std_logic;
- signal DSTR_REG, DSTR_REG_REG : std_logic;
--- signal DVAL_REG, DVAL_REG_LONG, DVAL_sync : std_logic;
- signal DVAL_REG, DVAL_REG_REG : std_logic;
- signal DIN_REG : std_logic_vector(3 downto 0);
--- signal counter_for_DVAL : integer range 0 to 3;
-
- signal TRIGCODE_i : std_logic_vector(3 downto 0);
- signal BUSY_FAST, BUSY_i : std_logic;
--------------------------------------------------------------------------------
-
-begin
-
- -- first we register all our inputs
-
- reg_DIN : process (CLK, RES)
- begin -- process reg_DIN
- if RES = '1' then -- asynchronous reset (active high)
- DIN_REG <= (others => '0');
- elsif CLK'event and CLK = '1' then -- rising clock edge
- DIN_REG <= (DIN);
- end if;
- end process reg_DIN;
-
- reg_TSTR : process (CLK, RES)
- begin -- process reg_NEW_TAG
- if RES = '1' then -- asynchronous reset (active high)
- TSTR_REG <= '0';
- elsif CLK'event and CLK = '1' then -- rising clock edge
- TSTR_REG <= TSTR;
- end if;
- end process reg_TSTR;
-
- reg_reg_TSTR : process (CLK, RES)
- begin -- process reg_NEW_TAG
- if RES = '1' then -- asynchronous reset (active high)
- TSTR_REG_REG <= '0';
- elsif CLK'event and CLK = '1' then -- rising clock edge
- TSTR_REG_REG <= TSTR_REG;
- end if;
- end process reg_reg_TSTR;
-
- reg_DSTR : process (CLK, RES)
- begin -- process reg_NEW_TAG
- if RES = '1' then -- asynchronous reset (active high)
- DSTR_REG <= '0';
- elsif CLK'event and CLK = '1' then -- rising clock edge
- DSTR_REG <= DSTR;
- end if;
- end process reg_DSTR;
-
- reg_reg_DSTR : process (CLK, RES)
- begin -- process reg_NEW_TAG
- if RES = '1' then -- asynchronous reset (active high)
- DSTR_REG_REG <= '0';
- elsif CLK'event and CLK = '1' then -- rising clock edge
- DSTR_REG_REG <= DSTR_REG;
- end if;
- end process reg_reg_DSTR;
-
- CodeBuffering : process (CLK, RES)
- begin -- process CodeBuffering
- if RES = '1' then
- TRIGCODE_i <= (others => '0');
- elsif (CLK'event and CLK = '1') then
- if (TSTR_REG = '0') and (TSTR_REG_REG = '1') then
- -- falling edge of TSTR
- TRIGCODE_i <= DIN_REG;
- -- den registerten Wert
- end if;
- end if;
- end process CodeBuffering;
-
- TagBuffering : process (CLK, RES)
- begin -- process TagBuffering
- if RES = '1' then -- asynchronous reset (active high)
- NIBCNT <= 0;
- DVAL_REG <= '0';
- elsif CLK'event and CLK = '1' then -- rising clock edge
- DVAL_REG <= '0';
- if NIBCNT >= 3 then
- NIBCNT <= 0;
- DVAL_REG <= '1';
- elsif (DSTR_REG = '0') and (DSTR_REG_REG = '1') then
- NIBCNT <= NIBCNT + 1;
- end if;
- end if;
- end process TagBuffering;
-
- Shift_Reg : process (CLK, RES)
- begin -- process TagBuffering
- if RES = '1' then -- asynchronous reset (active high)
- TRIGBUFF(0) <= (others => '0');
- TRIGBUFF(1) <= (others => '0');
- TRIGBUFF(2) <= (others => '0');
- elsif CLK'event and CLK = '1' then -- rising clock edge
- if (DSTR_REG = '0') and (DSTR_REG_REG = '1') then -- falling edge of DSTR
- TRIGBUFF(2) <= TRIGBUFF(1);
- TRIGBUFF(1) <= TRIGBUFF(0);
- TRIGBUFF(0) <= DIN_REG; -- shift register
- end if;
- end if;
- end process Shift_Reg;
-
- -- purpose: register DVAL
- -- type : sequential
- -- inputs : CLK, RES, DVAL
- -- outputs: DVAL_sync
- DVAL_OUT : process (CLK, RES, DVAL_REG)
- begin -- process DVAL_reg
- if RES = '1' then -- asynchronous reset (active low)
- DVAL_REG_REG <= '0';
- DVAL <= '0';
- elsif CLK'event and CLK = '1' then -- rising clock edge
- DVAL_REG_REG <= DVAL_REG;
- DVAL <= DVAL_REG or DVAL_REG_REG;
- end if;
- end process DVAL_OUT;
-
-
- SynchBSY : process(RES, CLK)
- begin
- if (RES = '1') then
- BSY <= '0';
- elsif (CLK'event and CLK = '1') then
- BSY <= BUSY_i;
- end if;
- end process SynchBSY;
--------------------------------------------------------------------------------
--- Combinatorial Signals
--------------------------------------------------------------------------------
- TRIGTAG <= TRIGBUFF(1) & TRIGBUFF(2);
- TRIGCODE <= TRIGCODE_i;
- ERR <= TRIGTAG_MISMATCH;
--- DSTR_INV <= NOT(DSTR);
- -- purpose: Set a fast busy on TSTR
- -- type : sequential
- -- inputs : CLK, RES, BUSY
- -- outputs: BUSY_FASt
- FastBusy : process (CLK, RES, BUSY)
- begin -- process FastBusy
- if RES = '1' or BUSY = '1'then -- asynchronous reset (active high)
- BUSY_FAST <= '0';
- elsif CLK'event and CLK = '1' then -- rising clock edge
- if TSTR_REG = '1' then
- BUSY_FAST <= '1';
- end if;
- end if;
- end process FastBusy;
- BUSY_i <= BUSY or BUSY_FAST;
-end ARCH_L12TrigInterface;
+++ /dev/null
-library IEEE;\r
-use IEEE.STD_LOGIC_1164.ALL;\r
-use IEEE.STD_LOGIC_ARITH.ALL;\r
-use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
-\r
-entity bus_handler is\r
-port( CLK_IN : in std_logic;\r
- CLEAR_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus \r
- DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
- DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
- DAT_READ_ENABLE_IN : in std_logic; -- read pulse\r
- DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
- DAT_TIMEOUT_IN : in std_logic; -- access timed out\r
- DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
- DAT_WRITE_ACK_OUT : out std_logic; -- data accepted\r
- DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
- DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
- SLV_SELECT_OUT : out std_logic_vector(47 downto 0); -- select signal for slave entities\r
- SLV_READ_OUT : out std_logic; -- read signal for slave entities\r
- SLV_WRITE_OUT : out std_logic; -- write signal for slave entities\r
- SLV_BUSY_IN : in std_logic; -- wired OR busy from slave entities\r
- SLV_ACK_IN : in std_logic; -- slave has accepted access\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0); -- read data from slaves\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0); -- write data to slaves\r
- STAT : out std_logic_vector(31 downto 0)\r
- );\r
-end entity;\r
-\r
-architecture Behavioral of bus_handler is\r
-\r
--- Signals\r
- type STATES is (SLEEP,RACC,WACC,RFAIL,WFAIL,ROK,WOK,STATW,STATS,STATD,NOONE,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
- \r
- signal bsm : std_logic_vector(3 downto 0);\r
-\r
- signal rst_strb_x : std_logic;\r
- signal rst_strb : std_logic;\r
- signal buf_dat_write_ack_x : std_logic;\r
- signal buf_dat_write_ack : std_logic;\r
- signal buf_dat_dataready_x : std_logic;\r
- signal buf_dat_dataready : std_logic;\r
- signal buf_dat_no_more_data_x : std_logic;\r
- signal buf_dat_no_more_data : std_logic;\r
- signal buf_dat_unknown_addr_x : std_logic;\r
- signal buf_dat_unknown_addr : std_logic;\r
-\r
- signal buf_slv_select_x : std_logic_vector(47 downto 0);\r
- signal buf_slv_select : std_logic_vector(47 downto 0);\r
- signal buf_slv_read : std_logic;\r
- signal buf_slv_write : std_logic;\r
- signal no_slave_reg_x : std_logic;\r
- signal no_slave_mem_x : std_logic;\r
- signal no_slave : std_logic;\r
- signal slave_busy : std_logic;\r
- signal slave_ack : std_logic;\r
-\r
-begin\r
-\r
--- Memory map:\r
--- 80xx => single registers\r
--- axxx => pedestal memory APV[15:0]\r
--- bxxx => threshold memory APV[15:0]\r
-\r
-------------------------------------------------------------------------------\r
--- This part is crucial, as ACK and BSY are tristate signals!\r
-------------------------------------------------------------------------------\r
--- Slave address decoder - registers (single address decoding)\r
-THE_ADDRESS_DEC_REG_PROC: process( dat_addr_in )\r
-begin\r
- case dat_addr_in is\r
- when x"8083" => buf_slv_select_x(15 downto 0) <= x"8000"; no_slave_reg_x <= '0'; -- trigger 3\r
- when x"8082" => buf_slv_select_x(15 downto 0) <= x"4000"; no_slave_reg_x <= '0'; -- trigger 2\r
- when x"8081" => buf_slv_select_x(15 downto 0) <= x"2000"; no_slave_reg_x <= '0'; -- trigger 1\r
- when x"8080" => buf_slv_select_x(15 downto 0) <= x"1000"; no_slave_reg_x <= '0'; -- trigger 0\r
- when x"8040" => buf_slv_select_x(15 downto 0) <= x"0800"; no_slave_reg_x <= '0'; -- I2C master\r
- when x"8021" => buf_slv_select_x(15 downto 0) <= x"0400"; no_slave_reg_x <= '0'; -- EDS_DONE\r
- when x"8020" => buf_slv_select_x(15 downto 0) <= x"0200"; no_slave_reg_x <= '0'; -- BUF_DONE\r
- when x"8001" => buf_slv_select_x(15 downto 0) <= x"0100"; no_slave_reg_x <= '0'; -- test register bad\r
- when x"8000" => buf_slv_select_x(15 downto 0) <= x"0080"; no_slave_reg_x <= '0'; -- test register good\r
- when x"8002" => buf_slv_select_x(15 downto 0) <= x"0040"; no_slave_reg_x <= '0'; -- real test register \r
- when others => buf_slv_select_x(15 downto 0) <= x"0000"; no_slave_reg_x <= '1';\r
- end case;\r
-end process THE_ADDRESS_DEC_REG_PROC;\r
-\r
--- Slave address decoder - memory (256 longwords decoding)\r
-THE_ADDRESS_DEC_MEM_PROC: process( dat_addr_in(15 downto 8) )\r
-begin\r
- case dat_addr_in(15 downto 8) is\r
- when x"a0" => buf_slv_select_x(47 downto 16) <= x"8000_0000"; no_slave_mem_x <= '0'; -- pedestal 0\r
- when x"a1" => buf_slv_select_x(47 downto 16) <= x"4000_0000"; no_slave_mem_x <= '0'; -- pedestal 1\r
- when x"a2" => buf_slv_select_x(47 downto 16) <= x"2000_0000"; no_slave_mem_x <= '0'; -- pedestal 2 \r
- when x"a3" => buf_slv_select_x(47 downto 16) <= x"1000_0000"; no_slave_mem_x <= '0'; -- pedestal 3 \r
- when x"a4" => buf_slv_select_x(47 downto 16) <= x"0800_0000"; no_slave_mem_x <= '0'; -- pedestal 4 \r
- when x"a5" => buf_slv_select_x(47 downto 16) <= x"0400_0000"; no_slave_mem_x <= '0'; -- pedestal 5 \r
- when x"a6" => buf_slv_select_x(47 downto 16) <= x"0200_0000"; no_slave_mem_x <= '0'; -- pedestal 6 \r
- when x"a7" => buf_slv_select_x(47 downto 16) <= x"0100_0000"; no_slave_mem_x <= '0'; -- pedestal 7 \r
- when x"a8" => buf_slv_select_x(47 downto 16) <= x"0080_0000"; no_slave_mem_x <= '0'; -- pedestal 8 \r
- when x"a9" => buf_slv_select_x(47 downto 16) <= x"0040_0000"; no_slave_mem_x <= '0'; -- pedestal 9 \r
- when x"aa" => buf_slv_select_x(47 downto 16) <= x"0020_0000"; no_slave_mem_x <= '0'; -- pedestal 10 \r
- when x"ab" => buf_slv_select_x(47 downto 16) <= x"0010_0000"; no_slave_mem_x <= '0'; -- pedestal 11 \r
- when x"ac" => buf_slv_select_x(47 downto 16) <= x"0008_0000"; no_slave_mem_x <= '0'; -- pedestal 12 \r
- when x"ad" => buf_slv_select_x(47 downto 16) <= x"0004_0000"; no_slave_mem_x <= '0'; -- pedestal 13 \r
- when x"ae" => buf_slv_select_x(47 downto 16) <= x"0002_0000"; no_slave_mem_x <= '0'; -- pedestal 14 \r
- when x"af" => buf_slv_select_x(47 downto 16) <= x"0001_0000"; no_slave_mem_x <= '0'; -- pedestal 15 \r
- when x"b0" => buf_slv_select_x(47 downto 16) <= x"0000_8000"; no_slave_mem_x <= '0'; -- threshold 0\r
- when x"b1" => buf_slv_select_x(47 downto 16) <= x"0000_4000"; no_slave_mem_x <= '0'; -- threshold 1 \r
- when x"b2" => buf_slv_select_x(47 downto 16) <= x"0000_2000"; no_slave_mem_x <= '0'; -- threshold 2 \r
- when x"b3" => buf_slv_select_x(47 downto 16) <= x"0000_1000"; no_slave_mem_x <= '0'; -- threshold 3 \r
- when x"b4" => buf_slv_select_x(47 downto 16) <= x"0000_0800"; no_slave_mem_x <= '0'; -- threshold 4 \r
- when x"b5" => buf_slv_select_x(47 downto 16) <= x"0000_0400"; no_slave_mem_x <= '0'; -- threshold 5 \r
- when x"b6" => buf_slv_select_x(47 downto 16) <= x"0000_0200"; no_slave_mem_x <= '0'; -- threshold 6 \r
- when x"b7" => buf_slv_select_x(47 downto 16) <= x"0000_0100"; no_slave_mem_x <= '0'; -- threshold 7 \r
- when x"b8" => buf_slv_select_x(47 downto 16) <= x"0000_0080"; no_slave_mem_x <= '0'; -- threshold 8 \r
- when x"b9" => buf_slv_select_x(47 downto 16) <= x"0000_0040"; no_slave_mem_x <= '0'; -- threshold 9 \r
- when x"ba" => buf_slv_select_x(47 downto 16) <= x"0000_0020"; no_slave_mem_x <= '0'; -- threshold 10 \r
- when x"bb" => buf_slv_select_x(47 downto 16) <= x"0000_0010"; no_slave_mem_x <= '0'; -- threshold 11 \r
- when x"bc" => buf_slv_select_x(47 downto 16) <= x"0000_0008"; no_slave_mem_x <= '0'; -- threshold 12 \r
- when x"bd" => buf_slv_select_x(47 downto 16) <= x"0000_0004"; no_slave_mem_x <= '0'; -- threshold 13 \r
- when x"be" => buf_slv_select_x(47 downto 16) <= x"0000_0002"; no_slave_mem_x <= '0'; -- threshold 14\r
- when x"bf" => buf_slv_select_x(47 downto 16) <= x"0000_0001"; no_slave_mem_x <= '0'; -- threshold 15\r
- when others => buf_slv_select_x(47 downto 16) <= x"0000_0000"; no_slave_mem_x <= '1';\r
- end case;\r
-end process THE_ADDRESS_DEC_MEM_PROC;\r
-\r
-\r
--- synchronize signals\r
-THE_SYNC_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- buf_slv_select <= buf_slv_select_x;\r
- no_slave <= no_slave_reg_x and no_slave_mem_x;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
-\r
--- Slave response lines\r
-slave_ack <= slv_ack_in when ( no_slave = '0' ) else '0';\r
-slave_busy <= slv_busy_in when ( no_slave = '0' ) else '0';\r
-dat_data_out <= slv_data_in when ( no_slave = '0' ) else (others => '0');\r
-\r
--- Data tunneling to slave entities\r
-slv_data_out <= dat_data_in;\r
-\r
--- Read / write strobe\r
-THE_READ_WRITE_STROBE_PROC: process( clk_in, clear_in )\r
-begin\r
- if( clear_in = '1' ) then\r
- buf_slv_read <= '0';\r
- buf_slv_write <= '0';\r
- elsif( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- buf_slv_read <= '0';\r
- buf_slv_write <= '0';\r
- elsif( (dat_read_enable_in = '1') and (dat_write_enable_in = '0') ) then\r
- buf_slv_read <= '1';\r
- buf_slv_write <= '0';\r
- elsif( (dat_read_enable_in = '0') and (dat_write_enable_in = '1') ) then\r
- buf_slv_read <= '0';\r
- buf_slv_write <= '1';\r
- elsif( rst_strb = '1' ) then\r
- buf_slv_read <= '0';\r
- buf_slv_write <= '0';\r
- end if;\r
- end if;\r
-end process THE_READ_WRITE_STROBE_PROC;\r
-\r
-\r
-\r
--- The main state machine\r
--- State memory process\r
-STATE_MEM: process( clk_in, clear_in )\r
-begin\r
- if( clear_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- rst_strb <= '0';\r
- buf_dat_dataready <= '0';\r
- buf_dat_no_more_data <= '0';\r
- buf_dat_write_ack <= '0';\r
- buf_dat_unknown_addr <= '0';\r
- elsif( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- rst_strb <= '0';\r
- buf_dat_dataready <= '0';\r
- buf_dat_no_more_data <= '0';\r
- buf_dat_write_ack <= '0';\r
- buf_dat_unknown_addr <= '0';\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- rst_strb <= rst_strb_x;\r
- buf_dat_dataready <= buf_dat_dataready_x;\r
- buf_dat_no_more_data <= buf_dat_no_more_data_x;\r
- buf_dat_write_ack <= buf_dat_write_ack_x;\r
- buf_dat_unknown_addr <= buf_dat_unknown_addr_x;\r
- end if;\r
- end if;\r
-end process STATE_MEM;\r
-\r
--- Transition matrix\r
-TRANSFORM: process(CURRENT_STATE, no_slave, buf_slv_read, buf_slv_write, slave_ack, slave_busy, dat_timeout_in )\r
-begin\r
- NEXT_STATE <= SLEEP;\r
- rst_strb_x <= '0';\r
- buf_dat_dataready_x <= '0';\r
- buf_dat_no_more_data_x <= '0';\r
- buf_dat_write_ack_x <= '0';\r
- buf_dat_unknown_addr_x <= '0';\r
- case CURRENT_STATE is\r
- when SLEEP => if ( (no_slave = '1') and ((buf_slv_read = '1') or (buf_slv_write = '1')) ) then\r
- NEXT_STATE <= NOONE;\r
- buf_dat_unknown_addr_x <= '1';\r
- elsif( (buf_slv_read = '1') and (buf_slv_write = '0') ) then\r
- NEXT_STATE <= RACC;\r
- elsif( (buf_slv_read = '0') and (buf_slv_write = '1') ) then\r
- NEXT_STATE <= WACC;\r
- else\r
- NEXT_STATE <= SLEEP;\r
- end if;\r
- when RACC => if ( dat_timeout_in = '1' ) then\r
- NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- elsif( slave_busy = '1' ) then\r
- NEXT_STATE <= RFAIL;\r
- buf_dat_no_more_data_x <= '1';\r
- elsif( slave_ack = '1' ) then\r
- NEXT_STATE <= ROK;\r
- buf_dat_dataready_x <= '1';\r
- else\r
- NEXT_STATE <= RACC;\r
- end if;\r
- when RFAIL => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when ROK => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when WACC => if ( dat_timeout_in = '1' ) then\r
- NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- elsif( slave_busy = '1' ) then\r
- NEXT_STATE <= WFAIL;\r
- buf_dat_no_more_data_x <= '1';\r
- elsif( slave_ack = '1' ) then\r
- NEXT_STATE <= WOK;\r
- buf_dat_write_ack_x <= '1';\r
- else\r
- NEXT_STATE <= WACC;\r
- end if;\r
- when WFAIL => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when WOK => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when NOONE => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when DONE => NEXT_STATE <= SLEEP; -- ?????\r
- -- Just in case...\r
- when others => NEXT_STATE <= SLEEP; \r
- end case;\r
-end process TRANSFORM;\r
-\r
--- Output decoding\r
-DECODE: process(CURRENT_STATE)\r
-begin\r
- case CURRENT_STATE is\r
- when SLEEP => bsm <= x"0";\r
- when RACC => bsm <= x"1";\r
- when ROK => bsm <= x"2";\r
- when RFAIL => bsm <= x"3";\r
- when WACC => bsm <= x"4";\r
- when WOK => bsm <= x"5";\r
- when NOONE => bsm <= x"6";\r
- when DONE => bsm <= x"7";\r
- when others => bsm <= x"f";\r
- end case; \r
-end process DECODE;\r
-\r
--- Outputs\r
-dat_dataready_out <= buf_dat_dataready;\r
-dat_no_more_data_out <= buf_dat_no_more_data;\r
-dat_unknown_addr_out <= buf_dat_unknown_addr;\r
-dat_write_ack_out <= buf_dat_write_ack;\r
-\r
-slv_select_out <= buf_slv_select;\r
-slv_read_out <= buf_slv_read;\r
-slv_write_out <= buf_slv_write;\r
-\r
-stat(31 downto 9) <= (others => '0');\r
-stat(8) <= rst_strb;\r
-stat(7 downto 4) <= (others => '0');\r
-stat(3 downto 0) <= bsm;\r
-\r
-end Behavioral;\r
+++ /dev/null
-library IEEE;\r
-use IEEE.STD_LOGIC_1164.ALL;\r
-use IEEE.STD_LOGIC_ARITH.ALL;\r
-use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
-\r
-entity bus_handler_oepb is\r
- generic(\r
- AMOUNT_OF_SLAVES : integer := 17\r
- );\r
- port(\r
- CLK_IN : in std_logic;\r
- CLEAR_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus\r
- DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
- DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
- DAT_READ_ENABLE_IN : in std_logic; -- read pulse\r
- DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
- DAT_TIMEOUT_IN : in std_logic; -- access timed out\r
- DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
- DAT_WRITE_ACK_OUT : out std_logic; -- data accepted\r
- DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
- DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
- SLV_SELECT_OUT : out std_logic_vector(AMOUNT_OF_SLAVES-1 downto 0); -- select signal for slave entities\r
- SLV_READ_OUT : out std_logic; -- read signal for slave entities\r
- SLV_WRITE_OUT : out std_logic; -- write signal for slave entities\r
- SLV_BUSY_IN : in std_logic; -- wired OR busy from slave entities\r
- SLV_ACK_IN : in std_logic; -- slave has accepted access\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0); -- read data from slaves\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0); -- write data to slaves\r
- STAT : out std_logic_vector(31 downto 0)\r
- );\r
-end entity;\r
-\r
-architecture Behavioral of bus_handler_oepb is\r
-\r
--- Signals\r
- type STATES is (SLEEP,RACC,WACC,RFAIL,WFAIL,ROK,WOK,STATW,STATS,STATD,NOONE,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- signal bsm : std_logic_vector(3 downto 0);\r
-\r
- signal rst_strb_x : std_logic;\r
- signal rst_strb : std_logic;\r
- signal buf_dat_write_ack_x : std_logic;\r
- signal buf_dat_write_ack : std_logic;\r
- signal buf_dat_dataready_x : std_logic;\r
- signal buf_dat_dataready : std_logic;\r
- signal buf_dat_no_more_data_x : std_logic;\r
- signal buf_dat_no_more_data : std_logic;\r
- signal buf_dat_unknown_addr_x : std_logic;\r
- signal buf_dat_unknown_addr : std_logic;\r
-\r
- signal buf_slv_select_x : std_logic_vector(AMOUNT_OF_SLAVES-1 downto 0);\r
- signal buf_slv_select : std_logic_vector(AMOUNT_OF_SLAVES-1 downto 0);\r
- signal buf_slv_read : std_logic;\r
- signal buf_slv_write : std_logic;\r
- signal no_slave_reg_x : std_logic;\r
- signal no_slave_mem_x : std_logic;\r
- signal no_slave : std_logic;\r
- signal slave_busy : std_logic;\r
- signal slave_ack : std_logic;\r
-\r
-begin\r
-\r
--- Memory map:\r
--- full range: 8000 - FFFF\r
--- 8000 - 80FF ADC (17)\r
--- 9000 - 9FFF SPI\r
--- A000 - A7FF Threshold Bytes (16)\r
--- F000 - F00F Test readout addresses (15-0)\r
-\r
-\r
--- 80xx => single registers\r
--- axxx => pedestal memory APV[15:0]\r
--- bxxx => threshold memory APV[15:0]\r
-\r
-------------------------------------------------------------------------------\r
--- This part is crucial, as ACK and BSY are tristate signals!\r
-------------------------------------------------------------------------------\r
-\r
-THE_ADDRESS_DEC_REG_PROC: process( dat_addr_in )\r
- begin\r
- buf_slv_select_x <= (others => '0');\r
- no_slave_reg_x <= '0';\r
- if dat_addr_in(15 downto 4) = x"F00" then\r
- buf_slv_select_x(to_integer(unsigned(dat_addr_in(3 downto 0)))) <= '1';\r
- elsif dat_addr_in(15 downto 11) = x"A" & '0' then\r
- buf_slv_select_x(16) <= '1';\r
- elsif dat_addr_in(15 downto 8) = x"80" then\r
- buf_slv_select_x(17) <= '1';\r
- else\r
- no_slave_reg_x <= '1';\r
- end if;\r
- end process;\r
-\r
-\r
-\r
-\r
--- synchronize signals\r
-THE_SYNC_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- buf_slv_select <= buf_slv_select_x;\r
- no_slave <= no_slave_reg_x and no_slave_mem_x;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
-\r
--- Slave response lines\r
-slave_ack <= slv_ack_in when ( no_slave = '0' ) else '0';\r
-slave_busy <= slv_busy_in when ( no_slave = '0' ) else '0';\r
-dat_data_out <= slv_data_in when ( no_slave = '0' ) else (others => '0');\r
-\r
--- Data tunneling to slave entities\r
-slv_data_out <= dat_data_in;\r
-\r
--- Read / write strobe\r
-THE_READ_WRITE_STROBE_PROC: process( clk_in, clear_in )\r
-begin\r
- if( clear_in = '1' ) then\r
- buf_slv_read <= '0';\r
- buf_slv_write <= '0';\r
- elsif( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- buf_slv_read <= '0';\r
- buf_slv_write <= '0';\r
- elsif( (dat_read_enable_in = '1') and (dat_write_enable_in = '0') ) then\r
- buf_slv_read <= '1';\r
- buf_slv_write <= '0';\r
- elsif( (dat_read_enable_in = '0') and (dat_write_enable_in = '1') ) then\r
- buf_slv_read <= '0';\r
- buf_slv_write <= '1';\r
- elsif( rst_strb = '1' ) then\r
- buf_slv_read <= '0';\r
- buf_slv_write <= '0';\r
- end if;\r
- end if;\r
-end process THE_READ_WRITE_STROBE_PROC;\r
-\r
-\r
-\r
--- The main state machine\r
--- State memory process\r
-STATE_MEM: process( clk_in, clear_in )\r
-begin\r
- if( clear_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- rst_strb <= '0';\r
- buf_dat_dataready <= '0';\r
- buf_dat_no_more_data <= '0';\r
- buf_dat_write_ack <= '0';\r
- buf_dat_unknown_addr <= '0';\r
- elsif( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- rst_strb <= '0';\r
- buf_dat_dataready <= '0';\r
- buf_dat_no_more_data <= '0';\r
- buf_dat_write_ack <= '0';\r
- buf_dat_unknown_addr <= '0';\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- rst_strb <= rst_strb_x;\r
- buf_dat_dataready <= buf_dat_dataready_x;\r
- buf_dat_no_more_data <= buf_dat_no_more_data_x;\r
- buf_dat_write_ack <= buf_dat_write_ack_x;\r
- buf_dat_unknown_addr <= buf_dat_unknown_addr_x;\r
- end if;\r
- end if;\r
-end process STATE_MEM;\r
-\r
--- Transition matrix\r
-TRANSFORM: process(CURRENT_STATE, no_slave, buf_slv_read, buf_slv_write, slave_ack, slave_busy, dat_timeout_in )\r
-begin\r
- NEXT_STATE <= SLEEP;\r
- rst_strb_x <= '0';\r
- buf_dat_dataready_x <= '0';\r
- buf_dat_no_more_data_x <= '0';\r
- buf_dat_write_ack_x <= '0';\r
- buf_dat_unknown_addr_x <= '0';\r
- case CURRENT_STATE is\r
- when SLEEP => if ( (no_slave = '1') and ((buf_slv_read = '1') or (buf_slv_write = '1')) ) then\r
- NEXT_STATE <= NOONE;\r
- buf_dat_unknown_addr_x <= '1';\r
- elsif( (buf_slv_read = '1') and (buf_slv_write = '0') ) then\r
- NEXT_STATE <= RACC;\r
- elsif( (buf_slv_read = '0') and (buf_slv_write = '1') ) then\r
- NEXT_STATE <= WACC;\r
- else\r
- NEXT_STATE <= SLEEP;\r
- end if;\r
- when RACC => if ( dat_timeout_in = '1' ) then\r
- NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- elsif( slave_busy = '1' ) then\r
- NEXT_STATE <= RFAIL;\r
- buf_dat_no_more_data_x <= '1';\r
- elsif( slave_ack = '1' ) then\r
- NEXT_STATE <= ROK;\r
- buf_dat_dataready_x <= '1';\r
- else\r
- NEXT_STATE <= RACC;\r
- end if;\r
- when RFAIL => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when ROK => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when WACC => if ( dat_timeout_in = '1' ) then\r
- NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- elsif( slave_busy = '1' ) then\r
- NEXT_STATE <= WFAIL;\r
- buf_dat_no_more_data_x <= '1';\r
- elsif( slave_ack = '1' ) then\r
- NEXT_STATE <= WOK;\r
- buf_dat_write_ack_x <= '1';\r
- else\r
- NEXT_STATE <= WACC;\r
- end if;\r
- when WFAIL => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when WOK => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when NOONE => NEXT_STATE <= DONE;\r
- rst_strb_x <= '1';\r
- when DONE => NEXT_STATE <= SLEEP; -- ?????\r
- -- Just in case...\r
- when others => NEXT_STATE <= SLEEP;\r
- end case;\r
-end process TRANSFORM;\r
-\r
--- Output decoding\r
-DECODE: process(CURRENT_STATE)\r
-begin\r
- case CURRENT_STATE is\r
- when SLEEP => bsm <= x"0";\r
- when RACC => bsm <= x"1";\r
- when ROK => bsm <= x"2";\r
- when RFAIL => bsm <= x"3";\r
- when WACC => bsm <= x"4";\r
- when WOK => bsm <= x"5";\r
- when NOONE => bsm <= x"6";\r
- when DONE => bsm <= x"7";\r
- when others => bsm <= x"f";\r
- end case;\r
-end process DECODE;\r
-\r
--- Outputs\r
-dat_dataready_out <= buf_dat_dataready;\r
-dat_no_more_data_out <= buf_dat_no_more_data;\r
-dat_unknown_addr_out <= buf_dat_unknown_addr;\r
-dat_write_ack_out <= buf_dat_write_ack;\r
-\r
-slv_select_out <= buf_slv_select;\r
-slv_read_out <= buf_slv_read;\r
-slv_write_out <= buf_slv_write;\r
-\r
-stat(31 downto 9) <= (others => '0');\r
-stat(8) <= rst_strb;\r
-stat(7 downto 4) <= (others => '0');\r
-stat(3 downto 0) <= bsm;\r
-\r
-end Behavioral;\r
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.all;
-
-
-entity etrax_interface is
- generic(
- STATUS_REGISTERS : integer := 4;
- CONTROL_REGISTERS : integer := 4
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- --Connection to Etrax
- ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);
- ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0);
- ETRAX_BUS_BUSY : out std_logic;
- --Connection to internal FPGA logic (all addresses above 0x100)
- INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
- INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
- INTERNAL_READ_OUT : out std_logic;
- INTERNAL_WRITE_OUT : out std_logic;
- INTERNAL_DATAREADY_IN : in std_logic;
- INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl)
- FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0);
- FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
- --Reset FPGA via Etrax
- EXTERNAL_RESET : out std_logic;
- STAT : out std_logic_vector(15 downto 0)
- );
-end etrax_interface;
-architecture etrax_interface of etrax_interface is
-
- component signal_sync is
- generic(
- WIDTH : integer := 2;
- DEPTH : integer := 1
- );
- port(
- RESET : in std_logic;
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- D_IN : in std_logic_vector(WIDTH-1 downto 0);
- D_OUT : out std_logic_vector(WIDTH-1 downto 0)
- );
- end component;
-
- type ETRAX_RW_STATE_MACHINE is (IDLE, SAVE_DATA_1 ,SAVE_DATA_2 , SEND_DATA_1, SEND_DATA_2, WAIT_FOR_DATA, SEND_EXTERNAL_TRIGGER ); --SEND_VALID
- signal ETRAX_RW_STATE_currentstate,ETRAX_RW_STATE_nextstate : ETRAX_RW_STATE_MACHINE;
-
- signal etrax_trigger_pulse : std_logic;
- signal saved_address : std_logic_vector (15 downto 0);
- signal saved_data : std_logic_vector(31 downto 0);
- signal saved_data_fpga : std_logic_vector(31 downto 0);
-
- signal read_cycle : std_logic;
- signal write_cycle : std_logic;
-
- signal etrax_is_ready_to_read_i : std_logic;
- signal internal_reset_i : std_logic;
- signal communication_state : std_logic_vector(3 downto 0);
- signal buf_FPGA_REGISTER_OUT : std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
- signal last_BUSC : std_logic_vector(17 downto 16);
- signal reg_BUSC : std_logic_vector(17 downto 0);
-
- signal delayed_internal_reset_i : std_logic;
-
-begin
-
- STAT(3 downto 0) <= communication_state;
- STAT(4) <= read_cycle;
- STAT(5) <= write_cycle;
- STAT(6) <= reg_BUSC(16);
- STAT(7) <= etrax_trigger_pulse;
- STAT(8) <= reg_BUSC(17);
-
- MAKE_RESET: process (CLK)
- begin
- if rising_edge(CLK) then
- if (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') or RESET = '1' then
- internal_reset_i <= '1';
- else
- internal_reset_i <= '0';
- end if;
- end if;
- end process MAKE_RESET;
-
- BUSC_SYNC : signal_sync
- generic map(
- WIDTH => 18,
- DEPTH => 1
- )
- port map(
- RESET => RESET,
- CLK0 => CLK,
- CLK1 => CLK,
- D_IN => ETRAX_DATA_BUS_C,
- D_OUT => reg_BUSC
- );
-
- THE_RESET_DELAY : signal_sync
- generic map(
- WIDTH => 1,
- DEPTH => 4
- )
- port map(
- RESET => '0',
- CLK0 => CLK,
- CLK1 => CLK,
- D_IN(0) => internal_reset_i,
- D_OUT(0) => delayed_internal_reset_i
- );
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- last_BUSC <= reg_BUSC(17 downto 16);
- end if;
- end process;
-
- etrax_trigger_pulse <= (last_BUSC(16) xor reg_BUSC(16)) and not delayed_internal_reset_i;
-
- EXTERNAL_RESET <= internal_reset_i or delayed_internal_reset_i;
- ETRAX_BUS_BUSY <= '0' when ETRAX_RW_STATE_currentstate = IDLE else '1';
-
- read_cycle <= saved_address(15);
- write_cycle <= not saved_address(15);
-
- ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK)
- begin
- if rising_edge(CLK) then
- if delayed_internal_reset_i = '1' then
- ETRAX_RW_STATE_currentstate <= IDLE;
- else
- ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate;
- end if;
- end if;
- end process;
-
- ETRAX_FPGA_COMUNICATION: process (ETRAX_RW_STATE_currentstate,etrax_trigger_pulse, --saved_rw_mode(15)
- read_cycle, write_cycle, INTERNAL_DATAREADY_IN, saved_address)
- begin
- communication_state <= x"1";
- ETRAX_RW_STATE_nextstate <= ETRAX_RW_STATE_currentstate;
- case ETRAX_RW_STATE_currentstate is
- when IDLE =>
- communication_state <= x"1";
- if etrax_trigger_pulse = '1' then
- ETRAX_RW_STATE_nextstate <= SAVE_DATA_1;
- end if;
-
- when SAVE_DATA_1 =>
- communication_state <= x"2";
- if read_cycle = '1' then
- ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
- elsif etrax_trigger_pulse = '1' then
- ETRAX_RW_STATE_nextstate <= SAVE_DATA_2;
- end if;
-
- when SAVE_DATA_2 =>
- communication_state <= x"3";
- if etrax_trigger_pulse = '1' then
- ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
- end if;
-
- when SEND_EXTERNAL_TRIGGER =>
- communication_state <= x"4";
- if read_cycle = '1' and (INTERNAL_DATAREADY_IN = '1' or saved_address(14 downto 5) = 0) then
- ETRAX_RW_STATE_nextstate <= SEND_DATA_1;
- elsif write_cycle = '1' then
- ETRAX_RW_STATE_nextstate <= IDLE;
- else
- ETRAX_RW_STATE_nextstate <= WAIT_FOR_DATA;
- end if;
-
- when WAIT_FOR_DATA =>
- communication_state <= x"5";
- if INTERNAL_DATAREADY_IN = '1' then
- ETRAX_RW_STATE_nextstate <= SEND_DATA_1;
- end if;
-
- when SEND_DATA_1 =>
- communication_state <= x"6";
- if etrax_trigger_pulse = '1' then
- ETRAX_RW_STATE_nextstate <= SEND_DATA_2;
- end if;
-
- when SEND_DATA_2 =>
- communication_state <= x"7";
- if etrax_trigger_pulse = '1' then
- ETRAX_RW_STATE_nextstate <= IDLE;
- end if;
- end case;
- end process ETRAX_FPGA_COMUNICATION;
-
- REGISTER_ETRAX_BUS: process (CLK)
- begin
- if rising_edge(CLK) then
- if delayed_internal_reset_i = '1' then
- saved_address <= (others => '0');
- saved_data <= (others => '0');
- elsif ETRAX_RW_STATE_currentstate = IDLE and etrax_trigger_pulse = '1' then
- saved_address(15 downto 0) <= reg_BUSC(15 downto 0);
- elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_1 and etrax_trigger_pulse = '1' then
- saved_data(31 downto 16) <= reg_BUSC(15 downto 0);
- elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_2 and etrax_trigger_pulse = '1' then
- saved_data(15 downto 0) <= reg_BUSC(15 downto 0);
- end if;
- end if;
- end process REGISTER_ETRAX_BUS;
-
-
- INTERNAL_ADDRESS_OUT <= '0' & saved_address(14 downto 0);
- INTERNAL_DATA_OUT <= saved_data;
-
- INTERNAL_WRITE_OUT <= '1' when write_cycle = '1' and saved_address(14 downto 5) /= 0
- and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER
- else '0';
- INTERNAL_READ_OUT <= '1' when read_cycle = '1' and saved_address(14 downto 5) /= 0
- and ETRAX_RW_STATE_currentstate = SAVE_DATA_1
- else '0';
-
- FPGA_REGISTER_OUT <= buf_FPGA_REGISTER_OUT;
-
- ETRAX_DATA_BUS_CHOOSE : process (CLK)
- begin
- if rising_edge(CLK) then
- if delayed_internal_reset_i = '1' then
- ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000";
- elsif ETRAX_RW_STATE_currentstate = SEND_DATA_1 then
- ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(31 downto 16);
- ETRAX_DATA_BUS_B(16) <= '1';
- elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 then
- ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(15 downto 0);
- ETRAX_DATA_BUS_B(16) <= '1';
- else
- ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000";
- end if;
- end if;
- end process ETRAX_DATA_BUS_CHOOSE;
-
- ETRAX_DATA_BUS_B(17) <= '1';
-
- DATA_SOURCE_SELECT : process (CLK)
- variable stat_num : integer range 0 to STATUS_REGISTERS-1;
- variable ctrl_num : integer range 0 to CONTROL_REGISTERS-1;
- begin
- if rising_edge(CLK) then
- stat_num := conv_integer(saved_address(3 downto 0));
- ctrl_num := conv_integer(saved_address(3 downto 0));
- if read_cycle = '1' then
- if saved_address(14 downto 5) = 0 then
- if saved_address(4) = '0' then --status regs
- saved_data_fpga <= FPGA_REGISTER_IN((stat_num)*32+31 downto stat_num*32);
- elsif saved_address(4) = '1' then
- saved_data_fpga <= buf_FPGA_REGISTER_OUT((ctrl_num)*32+31 downto (ctrl_num)*32);
- else
- saved_data_fpga <= (others => '0');
- end if;
- elsif INTERNAL_DATAREADY_IN = '1' then
- saved_data_fpga <= INTERNAL_DATA_IN;
- end if;
- elsif write_cycle = '1' and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER then
- if saved_address(4) = '1' and saved_address(14 downto 5) = 0 then
- buf_FPGA_REGISTER_OUT((ctrl_num+1)*32-1 downto (ctrl_num)*32) <= saved_data;
- end if;
- end if;
-
- end if;
- end process DATA_SOURCE_SELECT;
-end architecture;
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity rom_16x8 is
- generic(
- INIT0 : std_logic_vector(15 downto 0) := x"12A0";
- INIT1 : std_logic_vector(15 downto 0) := x"23b1";
- INIT2 : std_logic_vector(15 downto 0) := x"34c2";
- INIT3 : std_logic_vector(15 downto 0) := x"49d3";
- INIT4 : std_logic_vector(15 downto 0) := x"56e5";
- INIT5 : std_logic_vector(15 downto 0) := x"67d5";
- INIT6 : std_logic_vector(15 downto 0) := x"7818";
- INIT7 : std_logic_vector(15 downto 0) := x"8927"
- );
- port(
- CLK : in std_logic;
- a : in std_logic_vector(2 downto 0);
- dout : out std_logic_vector(15 downto 0)
- );
-end entity;
-
-architecture rom_16x8_arch of rom_16x8 is
- type ram_t is array(0 to 7) of std_logic_vector(15 downto 0);
- SIGNAL rom : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7);
-begin
- rom(0) <= INIT0;
- rom(1) <= INIT1;
- rom(2) <= INIT2;
- rom(3) <= INIT3;
- rom(4) <= INIT4;
- rom(5) <= INIT5;
- rom(6) <= INIT6;
- rom(7) <= INIT7;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- dout <= rom(conv_integer(a));
- end if;
- end process;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-
---
--- Verific VHDL Description of module DCUA
---
-
--- DCUA is a black-box. Cannot print a valid VHDL entity description for it
-
---
--- Verific VHDL Description of module serdes_sync_0rsl_core
---
-
--- serdes_sync_0rsl_core is a black-box. Cannot print a valid VHDL entity description for it
-
---
--- Verific VHDL Description of module serdes_sync_0sll_core
---
-
--- serdes_sync_0sll_core is a black-box. Cannot print a valid VHDL entity description for it
-
---
--- Verific VHDL Description of module serdes_sync_0
---
-
-library ieee ;
-use ieee.std_logic_1164.all ;
-
-library ecp5um ;
-use ecp5um.components.all ;
-
-entity serdes_sync_0 is
- port (hdoutp: out std_logic;
- hdoutn: out std_logic;
- hdinp: in std_logic;
- hdinn: in std_logic;
- rxrefclk: in std_logic;
- rx_pclk: out std_logic;
- tx_pclk: out std_logic;
- txdata: in std_logic_vector(7 downto 0);
- tx_k: in std_logic_vector(0 downto 0);
- tx_force_disp: in std_logic_vector(0 downto 0);
- tx_disp_sel: in std_logic_vector(0 downto 0);
- rxdata: out std_logic_vector(7 downto 0);
- rx_k: out std_logic_vector(0 downto 0);
- rx_disp_err: out std_logic_vector(0 downto 0);
- rx_cv_err: out std_logic_vector(0 downto 0);
- tx_idle_c: in std_logic;
- signal_detect_c: in std_logic;
- rx_los_low_s: out std_logic;
- lsm_status_s: out std_logic;
- rx_cdr_lol_s: out std_logic;
- sli_rst: in std_logic;
- tx_pwrup_c: in std_logic;
- rx_pwrup_c: in std_logic;
- sci_wrdata: in std_logic_vector(7 downto 0);
- sci_addr: in std_logic_vector(5 downto 0);
- sci_rddata: out std_logic_vector(7 downto 0);
- sci_en_dual: in std_logic;
- sci_sel_dual: in std_logic;
- sci_en: in std_logic;
- sci_sel: in std_logic;
- sci_rd: in std_logic;
- sci_wrn: in std_logic;
- sci_int: out std_logic;
- cyawstn: in std_logic;
- serdes_pdb: in std_logic;
- pll_refclki: in std_logic;
- rsl_disable: in std_logic;
- rsl_rst: in std_logic;
- serdes_rst_dual_c: in std_logic;
- rst_dual_c: in std_logic;
- tx_serdes_rst_c: in std_logic;
- tx_pcs_rst_c: in std_logic;
- pll_lol: out std_logic;
- rsl_tx_rdy: out std_logic;
- rx_serdes_rst_c: in std_logic;
- rx_pcs_rst_c: in std_logic;
- rsl_rx_rdy: out std_logic
- );
-
-end entity serdes_sync_0;
-
-architecture v1 of serdes_sync_0 is
- component serdes_sync_0rsl_core is
- generic (pnum_channels: integer := 1;
- pprotocol: string := "G8B10B";
- pserdes_mode: string := "RX AND TX";
- pport_tx_rdy: string := "ENABLED";
- pwait_tx_rdy: integer := 3000;
- pport_rx_rdy: string := "ENABLED";
- pwait_rx_rdy: integer := 3000);
- port (rui_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132)
- rui_serdes_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133)
- rui_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134)
- rui_rsl_disable: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135)
- rui_tx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137)
- rui_tx_serdes_rst_c: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138)
- rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139)
- rdi_pll_lol: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140)
- rui_rx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142)
- rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143)
- rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144)
- rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145)
- rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146)
- rdo_serdes_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149)
- rdo_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150)
- ruo_tx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152)
- rdo_tx_serdes_rst_c: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153)
- rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154)
- ruo_rx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156)
- rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157)
- rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158)
- );
-
- end component serdes_sync_0rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88)
- component serdes_sync_0sll_core is
- generic (PPROTOCOL: string := "G8B10B";
- PLOL_SETTING: integer := 1;
- PDYN_RATE_CTRL: string := "DISABLED";
- PPCIE_MAX_RATE: string := "2.5";
- PDIFF_VAL_LOCK: integer := 19;
- PDIFF_VAL_UNLOCK: integer := 131;
- PPCLK_TC: integer := 65536;
- PDIFF_DIV11_VAL_LOCK: integer := 0;
- PDIFF_DIV11_VAL_UNLOCK: integer := 0;
- PPCLK_DIV11_TC: integer := 0);
- port (sli_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125)
- sli_refclk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126)
- sli_pclk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127)
- sli_div2_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128)
- sli_div11_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129)
- sli_gear_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130)
- sli_cpri_mode: in std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131)
- sli_pcie_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132)
- slo_plol: out std_logic -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135)
- );
-
- end component serdes_sync_0sll_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107)
- signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9,
- n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17,
- n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,
- rsl_serdes_rst_dual_c,rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23,
- n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,
- n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51,
- n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,
- n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,
- n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,
- n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n115,n114,
- n113,pll_lol_c,n125,n124,n116,n117,n118,n119,n120,n121,n122,
- n123,\_Z\,n127,n126,gnd,pwr : std_logic;
- attribute LOC : string;
- attribute LOC of DCU0_inst : label is "DCU0";
- attribute CHAN : string;
- attribute CHAN of DCU0_inst : label is "CH0";
-begin
- rx_pclk <= rx_pclk_c;
- tx_pclk <= tx_pclk_c;
- rx_los_low_s <= rx_los_low_s_c;
- rx_cdr_lol_s <= rx_cdr_lol_s_c;
- pll_lol <= pll_lol_c;
- DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
- D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
- D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
- D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
- D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
- CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",
- CH0_GE_AN_ENABLE=>"0b0",CH0_PRBS_LOCK=>"0b0",CH0_PRBS_ENABLE=>"0b0",
- CH0_ENABLE_CG_ALIGN=>"0b1",CH0_TX_GEAR_MODE=>"0b0",CH0_RX_GEAR_MODE=>"0b0",
- CH0_PCS_DET_TIME_SEL=>"0b00",CH0_PCIE_EI_EN=>"0b0",CH0_TX_GEAR_BYPASS=>"0b0",
- CH0_ENC_BYPASS=>"0b0",CH0_SB_BYPASS=>"0b0",CH0_RX_SB_BYPASS=>"0b0",
- CH0_WA_BYPASS=>"0b0",CH0_DEC_BYPASS=>"0b0",CH0_CTC_BYPASS=>"0b1",
- CH0_RX_GEAR_BYPASS=>"0b0",CH0_LSM_DISABLE=>"0b0",CH0_MATCH_2_ENABLE=>"0b0",
- CH0_MATCH_4_ENABLE=>"0b1",CH0_MIN_IPG_CNT=>"0b11",CH0_CC_MATCH_1=>"0x1BC",
- CH0_CC_MATCH_2=>"0x11C",CH0_CC_MATCH_3=>"0x11C",CH0_CC_MATCH_4=>"0x11C",
- CH0_UDF_COMMA_MASK=>"0x0ff",CH0_UDF_COMMA_A=>"0x083",CH0_UDF_COMMA_B=>"0x07C",
- CH0_RX_DCO_CK_DIV=>"0b000",CH0_RCV_DCC_EN=>"0b0",CH0_TPWDNB=>"0b1",
- CH0_RATE_MODE_TX=>"0b0",CH0_RTERM_TX=>"0d19",CH0_TX_CM_SEL=>"0b00",
- CH0_TDRV_PRE_EN=>"0b0",CH0_TDRV_SLICE0_SEL=>"0b00",CH0_TDRV_SLICE1_SEL=>"0b00",
- CH0_TDRV_SLICE2_SEL=>"0b01",CH0_TDRV_SLICE3_SEL=>"0b01",CH0_TDRV_SLICE4_SEL=>"0b01",
- CH0_TDRV_SLICE5_SEL=>"0b00",CH0_TDRV_SLICE0_CUR=>"0b000",CH0_TDRV_SLICE1_CUR=>"0b000",
- CH0_TDRV_SLICE2_CUR=>"0b11",CH0_TDRV_SLICE3_CUR=>"0b11",CH0_TDRV_SLICE4_CUR=>"0b01",
- CH0_TDRV_SLICE5_CUR=>"0b00",CH0_TDRV_DAT_SEL=>"0b00",CH0_TX_DIV11_SEL=>"0b0",
- CH0_RPWDNB=>"0b1",CH0_RATE_MODE_RX=>"0b0",CH0_RX_DIV11_SEL=>"0b0",
- CH0_SEL_SD_RX_CLK=>"0b1",CH0_FF_RX_H_CLK_EN=>"0b0",CH0_FF_RX_F_CLK_DIS=>"0b0",
- CH0_FF_TX_H_CLK_EN=>"0b0",CH0_FF_TX_F_CLK_DIS=>"0b0",CH0_TDRV_POST_EN=>"0b0",
- CH0_TX_POST_SIGN=>"0b0",CH0_TX_PRE_SIGN=>"0b0",CH0_REQ_LVL_SET=>"0b00",
- CH0_REQ_EN=>"0b1",CH0_RTERM_RX=>"0d22",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b1",
- CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000",
- CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b100",CH0_RX_LOS_CEQ=>"0b11",
- CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0",
- CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH0_CDR_MAX_RATE=>"2",
- CH0_TXAMPLITUDE=>"0d800",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED",
- CH0_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b10",D_SETICONST_AUX=>"0b01",
- D_SETIRPOLY_CH=>"0b10",D_SETICONST_CH=>"0b10",D_REQ_ISET=>"0b001",
- D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH0_CDR_CNT4SEL=>"0b00",
- CH0_CDR_CNT8SEL=>"0b00",CH0_DCOATDCFG=>"0b00",CH0_DCOATDDLY=>"0b00",
- CH0_DCOBYPSATD=>"0b1",CH0_DCOCALDIV=>"0b000",CH0_DCOCTLGI=>"0b011",
- CH0_DCODISBDAVOID=>"0b0",CH0_DCOFLTDAC=>"0b00",CH0_DCOFTNRG=>"0b001",
- CH0_DCOIOSTUNE=>"0b010",CH0_DCOITUNE=>"0b00",CH0_DCOITUNE4LSB=>"0b010",
- CH0_DCOIUPDNX2=>"0b1",CH0_DCONUOFLSB=>"0b100",CH0_DCOSCALEI=>"0b01",
- CH0_DCOSTARTVAL=>"0b010",CH0_DCOSTEP=>"0b11",CH0_BAND_THRESHOLD=>"0d0",
- CH0_AUTO_FACQ_EN=>"0b1",CH0_AUTO_CALIB_EN=>"0b1",CH0_CALIB_CK_MODE=>"0b0",
- CH0_REG_BAND_OFFSET=>"0d0",CH0_REG_BAND_SEL=>"0d0",CH0_REG_IDAC_SEL=>"0d0",
- CH0_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00",
- D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
- D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
- D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d10",
- D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01",
- D_RG_EN=>"0b0",D_RG_SET=>"0b00")
- port map (CH0_HDINP=>hdinp,CH1_HDINP=>n106,CH0_HDINN=>hdinn,CH1_HDINN=>n106,
- D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47,
- CH0_RX_REFCLK=>rxrefclk,CH1_RX_REFCLK=>n106,CH0_FF_RXI_CLK=>rx_pclk_c,
- CH1_FF_RXI_CLK=>n105,CH0_FF_TXI_CLK=>tx_pclk_c,CH1_FF_TXI_CLK=>n105,CH0_FF_EBRD_CLK=>n48,
- CH1_FF_EBRD_CLK=>n105,CH0_FF_TX_D_0=>txdata(0),CH1_FF_TX_D_0=>n106,CH0_FF_TX_D_1=>txdata(1),
- CH1_FF_TX_D_1=>n106,CH0_FF_TX_D_2=>txdata(2),CH1_FF_TX_D_2=>n106,CH0_FF_TX_D_3=>txdata(3),
- CH1_FF_TX_D_3=>n106,CH0_FF_TX_D_4=>txdata(4),CH1_FF_TX_D_4=>n106,CH0_FF_TX_D_5=>txdata(5),
- CH1_FF_TX_D_5=>n106,CH0_FF_TX_D_6=>txdata(6),CH1_FF_TX_D_6=>n106,CH0_FF_TX_D_7=>txdata(7),
- CH1_FF_TX_D_7=>n106,CH0_FF_TX_D_8=>tx_k(0),CH1_FF_TX_D_8=>n106,CH0_FF_TX_D_9=>tx_force_disp(0),
- CH1_FF_TX_D_9=>n106,CH0_FF_TX_D_10=>tx_disp_sel(0),CH1_FF_TX_D_10=>n106,
- CH0_FF_TX_D_11=>n47,CH1_FF_TX_D_11=>n106,CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106,
- CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106,CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106,
- CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106,CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106,
- CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106,CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106,
- CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106,CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106,
- CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106,CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106,
- CH0_FF_TX_D_23=>n47,CH1_FF_TX_D_23=>n106,CH0_FFC_EI_EN=>tx_idle_c,CH1_FFC_EI_EN=>n106,
- CH0_FFC_PCIE_DET_EN=>n47,CH1_FFC_PCIE_DET_EN=>n106,CH0_FFC_PCIE_CT=>n47,
- CH1_FFC_PCIE_CT=>n106,CH0_FFC_SB_INV_RX=>n106,CH1_FFC_SB_INV_RX=>n106,
- CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106,CH0_FFC_SIGNAL_DETECT=>signal_detect_c,
- CH1_FFC_SIGNAL_DETECT=>n106,CH0_FFC_FB_LOOPBACK=>n47,CH1_FFC_FB_LOOPBACK=>n106,
- CH0_FFC_SB_PFIFO_LP=>n47,CH1_FFC_SB_PFIFO_LP=>n106,CH0_FFC_PFIFO_CLR=>n47,
- CH1_FFC_PFIFO_CLR=>n106,CH0_FFC_RATE_MODE_RX=>n106,CH1_FFC_RATE_MODE_RX=>n106,
- CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106,CH0_FFC_DIV11_MODE_RX=>n47,
- CH1_FFC_DIV11_MODE_RX=>n106,CH0_FFC_DIV11_MODE_TX=>n47,CH1_FFC_DIV11_MODE_TX=>n106,
- CH0_FFC_RX_GEAR_MODE=>n47,CH1_FFC_RX_GEAR_MODE=>n106,CH0_FFC_TX_GEAR_MODE=>n47,
- CH1_FFC_TX_GEAR_MODE=>n106,CH0_FFC_LDR_CORE2TX_EN=>n106,CH1_FFC_LDR_CORE2TX_EN=>n106,
- CH0_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH1_FFC_LANE_TX_RST=>n106,CH0_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,
- CH1_FFC_LANE_RX_RST=>n106,CH0_FFC_RRST=>rsl_rx_serdes_rst_c,CH1_FFC_RRST=>n106,
- CH0_FFC_TXPWDNB=>tx_pwrup_c,CH1_FFC_TXPWDNB=>n106,CH0_FFC_RXPWDNB=>rx_pwrup_c,
- CH1_FFC_RXPWDNB=>n106,CH0_LDR_CORE2TX=>n106,CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0),
- D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3),
- D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6),
- D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1),
- D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4),
- D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual,
- CH0_SCIEN=>sci_en,CH1_SCIEN=>n106,CH0_SCISEL=>sci_sel,CH1_SCISEL=>n106,
- D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106,
- D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,
- D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n47,
- CH1_FFC_CDR_EN_BITSLIP=>n106,D_SCAN_ENABLE=>n47,D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,
- D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47,D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,
- D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47,D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,
- D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47,D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,
- D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47,D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,
- CH0_HDOUTP=>hdoutp,CH1_HDOUTP=>n50,CH0_HDOUTN=>hdoutn,CH1_HDOUTN=>n51,
- D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,
- CH0_FF_RX_F_CLK=>n5,CH1_FF_RX_F_CLK=>n52,CH0_FF_RX_H_CLK=>n6,CH1_FF_RX_H_CLK=>n53,
- CH0_FF_TX_F_CLK=>n7,CH1_FF_TX_F_CLK=>n54,CH0_FF_TX_H_CLK=>n8,CH1_FF_TX_H_CLK=>n55,
- CH0_FF_RX_PCLK=>rx_pclk_c,CH1_FF_RX_PCLK=>n56,CH0_FF_TX_PCLK=>tx_pclk_c,
- CH1_FF_TX_PCLK=>n57,CH0_FF_RX_D_0=>rxdata(0),CH1_FF_RX_D_0=>n58,CH0_FF_RX_D_1=>rxdata(1),
- CH1_FF_RX_D_1=>n59,CH0_FF_RX_D_2=>rxdata(2),CH1_FF_RX_D_2=>n60,CH0_FF_RX_D_3=>rxdata(3),
- CH1_FF_RX_D_3=>n61,CH0_FF_RX_D_4=>rxdata(4),CH1_FF_RX_D_4=>n62,CH0_FF_RX_D_5=>rxdata(5),
- CH1_FF_RX_D_5=>n63,CH0_FF_RX_D_6=>rxdata(6),CH1_FF_RX_D_6=>n64,CH0_FF_RX_D_7=>rxdata(7),
- CH1_FF_RX_D_7=>n65,CH0_FF_RX_D_8=>rx_k(0),CH1_FF_RX_D_8=>n66,CH0_FF_RX_D_9=>rx_disp_err(0),
- CH1_FF_RX_D_9=>n67,CH0_FF_RX_D_10=>rx_cv_err(0),CH1_FF_RX_D_10=>n68,CH0_FF_RX_D_11=>n9,
- CH1_FF_RX_D_11=>n69,CH0_FF_RX_D_12=>n70,CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,
- CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74,CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,
- CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78,CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,
- CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82,CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,
- CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86,CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,
- CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90,CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n10,
- CH1_FF_RX_D_23=>n92,CH0_FFS_PCIE_DONE=>n11,CH1_FFS_PCIE_DONE=>n93,CH0_FFS_PCIE_CON=>n12,
- CH1_FFS_PCIE_CON=>n94,CH0_FFS_RLOS=>rx_los_low_s_c,CH1_FFS_RLOS=>n95,
- CH0_FFS_LS_SYNC_STATUS=>lsm_status_s,CH1_FFS_LS_SYNC_STATUS=>n96,CH0_FFS_CC_UNDERRUN=>n13,
- CH1_FFS_CC_UNDERRUN=>n97,CH0_FFS_CC_OVERRUN=>n14,CH1_FFS_CC_OVERRUN=>n98,
- CH0_FFS_RXFBFIFO_ERROR=>n15,CH1_FFS_RXFBFIFO_ERROR=>n99,CH0_FFS_TXFBFIFO_ERROR=>n16,
- CH1_FFS_TXFBFIFO_ERROR=>n100,CH0_FFS_RLOL=>rx_cdr_lol_s_c,CH1_FFS_RLOL=>n101,
- CH0_FFS_SKP_ADDED=>n17,CH1_FFS_SKP_ADDED=>n102,CH0_FFS_SKP_DELETED=>n18,
- CH1_FFS_SKP_DELETED=>n103,CH0_LDR_RX2CORE=>n104,CH1_LDR_RX2CORE=>n115,
- D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2),
- D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5),
- D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int,
- D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21,D_SCAN_OUT_3=>n22,
- D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25,D_SCAN_OUT_7=>n26,
- D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30,D_COUT4=>n31,D_COUT5=>n32,
- D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36,D_COUT10=>n37,D_COUT11=>n38,
- D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41,D_COUT15=>n42,D_COUT16=>n43,
- D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49);
- n48 <= '1' ;
- n47 <= '0' ;
- n1 <= 'Z' ;
- n2 <= 'Z' ;
- n3 <= 'Z' ;
- n4 <= 'Z' ;
- n5 <= 'Z' ;
- n6 <= 'Z' ;
- n7 <= 'Z' ;
- n8 <= 'Z' ;
- n9 <= 'Z' ;
- n10 <= 'Z' ;
- n11 <= 'Z' ;
- n12 <= 'Z' ;
- n13 <= 'Z' ;
- n14 <= 'Z' ;
- n15 <= 'Z' ;
- n16 <= 'Z' ;
- n17 <= 'Z' ;
- n18 <= 'Z' ;
- n19 <= 'Z' ;
- n20 <= 'Z' ;
- n21 <= 'Z' ;
- n22 <= 'Z' ;
- n23 <= 'Z' ;
- n24 <= 'Z' ;
- n25 <= 'Z' ;
- n26 <= 'Z' ;
- n27 <= 'Z' ;
- n28 <= 'Z' ;
- n29 <= 'Z' ;
- n30 <= 'Z' ;
- n31 <= 'Z' ;
- n32 <= 'Z' ;
- n33 <= 'Z' ;
- n34 <= 'Z' ;
- n35 <= 'Z' ;
- n36 <= 'Z' ;
- n37 <= 'Z' ;
- n38 <= 'Z' ;
- n39 <= 'Z' ;
- n40 <= 'Z' ;
- n41 <= 'Z' ;
- n42 <= 'Z' ;
- n43 <= 'Z' ;
- n44 <= 'Z' ;
- n45 <= 'Z' ;
- n46 <= 'Z' ;
- n49 <= 'Z' ;
- n106 <= '0' ;
- n105 <= '1' ;
- n50 <= 'Z' ;
- n51 <= 'Z' ;
- n52 <= 'Z' ;
- n53 <= 'Z' ;
- n54 <= 'Z' ;
- n55 <= 'Z' ;
- n56 <= 'Z' ;
- n57 <= 'Z' ;
- n58 <= 'Z' ;
- n59 <= 'Z' ;
- n60 <= 'Z' ;
- n61 <= 'Z' ;
- n62 <= 'Z' ;
- n63 <= 'Z' ;
- n64 <= 'Z' ;
- n65 <= 'Z' ;
- n66 <= 'Z' ;
- n67 <= 'Z' ;
- n68 <= 'Z' ;
- n69 <= 'Z' ;
- n70 <= 'Z' ;
- n71 <= 'Z' ;
- n72 <= 'Z' ;
- n73 <= 'Z' ;
- n74 <= 'Z' ;
- n75 <= 'Z' ;
- n76 <= 'Z' ;
- n77 <= 'Z' ;
- n78 <= 'Z' ;
- n79 <= 'Z' ;
- n80 <= 'Z' ;
- n81 <= 'Z' ;
- n82 <= 'Z' ;
- n83 <= 'Z' ;
- n84 <= 'Z' ;
- n85 <= 'Z' ;
- n86 <= 'Z' ;
- n87 <= 'Z' ;
- n88 <= 'Z' ;
- n89 <= 'Z' ;
- n90 <= 'Z' ;
- n91 <= 'Z' ;
- n92 <= 'Z' ;
- n93 <= 'Z' ;
- n94 <= 'Z' ;
- n95 <= 'Z' ;
- n96 <= 'Z' ;
- n97 <= 'Z' ;
- n98 <= 'Z' ;
- n99 <= 'Z' ;
- n100 <= 'Z' ;
- n101 <= 'Z' ;
- n102 <= 'Z' ;
- n103 <= 'Z' ;
- n104 <= 'Z' ;
- n115 <= 'Z' ;
- rsl_inst: component serdes_sync_0rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c,
- rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki,
- rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n125,
- rui_tx_pcs_rst_c(2)=>n125,rui_tx_pcs_rst_c(1)=>n125,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c,
- rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n125,
- rui_rx_serdes_rst_c(2)=>n125,rui_rx_serdes_rst_c(1)=>n125,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c,
- rui_rx_pcs_rst_c(3)=>n125,rui_rx_pcs_rst_c(2)=>n125,rui_rx_pcs_rst_c(1)=>n125,
- rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n125,rdi_rx_los_low_s(2)=>n125,
- rdi_rx_los_low_s(1)=>n125,rdi_rx_los_low_s(0)=>rx_los_low_s_c,
- rdi_rx_cdr_lol_s(3)=>n125,rdi_rx_cdr_lol_s(2)=>n125,rdi_rx_cdr_lol_s(1)=>n125,
- rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,
- rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c,
- rdo_tx_pcs_rst_c(3)=>n116,rdo_tx_pcs_rst_c(2)=>n117,rdo_tx_pcs_rst_c(1)=>n118,
- rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n119,
- rdo_rx_serdes_rst_c(2)=>n120,rdo_rx_serdes_rst_c(1)=>n121,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c,
- rdo_rx_pcs_rst_c(3)=>n122,rdo_rx_pcs_rst_c(2)=>n123,rdo_rx_pcs_rst_c(1)=>\_Z\,
- rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c);
- n114 <= '1' ;
- n113 <= '0' ;
- n125 <= '0' ;
- n124 <= '1' ;
- n116 <= 'Z' ;
- n117 <= 'Z' ;
- n118 <= 'Z' ;
- n119 <= 'Z' ;
- n120 <= 'Z' ;
- n121 <= 'Z' ;
- n122 <= 'Z' ;
- n123 <= 'Z' ;
- \_Z\ <= 'Z' ;
- sll_inst: component serdes_sync_0sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki,
- sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd,
- sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd,
- sli_pcie_mode=>gnd,slo_plol=>pll_lol_c);
- n127 <= '1' ;
- n126 <= '0' ;
- gnd <= '0' ;
- pwr <= '1' ;
-
-end architecture v1;
-
+++ /dev/null
-
-
-// ===========================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// ---------------------------------------------------------------------------
-// Copyright (c) 2016 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code
-// pursuant to the terms of the Lattice Reference Design License Agreement.
-//
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// ---------------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// ---------------------------------------------------------------------------
-//
-// =============================================================================
-// FILE DETAILS
-// Project : RSL- Reset Sequence Logic
-// File : rsl_core.v
-// Title : Top-level file for RSL
-// Dependencies : 1.
-// : 2.
-// Description :
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.0
-// Author(s) : BM
-// Mod. Date : October 28, 2013
-// Changes Made : Initial Creation
-// -----------------------------------------------------------------------------
-// Version : 1.1
-// Author(s) : BM
-// Mod. Date : November 06, 2013
-// Changes Made : Tx/Rx separation, ready port code exclusion
-// -----------------------------------------------------------------------------
-// Version : 1.2
-// Author(s) : BM
-// Mod. Date : June 13, 2014
-// Changes Made : Updated Rx PCS reset method
-// -----------------------------------------------------------------------------
-// -----------------------------------------------------------------------------
-// Version : 1.3
-// Author(s) : UA
-// Mod. Date : Dec 19, 2014
-// Changes Made : Added new parameter fro PCIE
-// -----------------------------------------------------------------------------
-// Version : 1.31
-// Author(s) : BM/UM
-// Mod. Date : Feb 23, 2016
-// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy
-// and the rx_rdy wait counter are reset to zero on
-// LOL or LOS. Reverted back the counter value change for PCIE.
-// -----------------------------------------------------------------------------
-// Version : 1.4
-// Author(s) : EB
-// Mod. Date: : March 21, 2017
-// Changes Made :
-// -----------------------------------------------------------------------------
-// Version : 1.5
-// Author(s) : ES
-// Mod. Date: : May 8, 2017
-// Changes Made : Implemented common RSL behaviour as proposed by BM.
-// =============================================================================
-
-`timescale 1ns/10ps
-
-module serdes_sync_0rsl_core (
- // ------------ Inputs
- // Common
- rui_rst, // Active high reset for the RSL module
- rui_serdes_rst_dual_c, // SERDES macro reset user command
- rui_rst_dual_c, // PCS dual reset user command
- rui_rsl_disable, // Active high signal that disables all reset outputs of RSL
- // Tx
- rui_tx_ref_clk, // Tx reference clock
- rui_tx_serdes_rst_c, // Tx SERDES reset user command
- rui_tx_pcs_rst_c, // Tx lane reset user command
- rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES
- // Rx
- rui_rx_ref_clk, // Rx reference clock
- rui_rx_serdes_rst_c, // SERDES Receive channel reset user command
- rui_rx_pcs_rst_c, // Rx lane reset user command
- rdi_rx_los_low_s, // Receive loss of signal status input from SERDES
- rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES
-
- // ------------ Outputs
- // Common
- rdo_serdes_rst_dual_c, // SERDES macro reset command output
- rdo_rst_dual_c, // PCS dual reset command output
- // Tx
- ruo_tx_rdy, // Tx lane ready status output
- rdo_tx_serdes_rst_c, // SERDES Tx reset command output
- rdo_tx_pcs_rst_c, // PCS Tx lane reset command output
- // Rx
- ruo_rx_rdy, // Rx lane ready status output
- rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output
- rdo_rx_pcs_rst_c // PCS Rx lane reset command output
- );
-
-// ------------ Module parameters
-`ifdef NUM_CHANNELS
- parameter pnum_channels = `NUM_CHANNELS; // 1,2,4
-`else
- parameter pnum_channels = 1;
-`endif
-
-`ifdef PCIE
- parameter pprotocol = "PCIE";
-`else
- parameter pprotocol = "";
-`endif
-
-`ifdef RX_ONLY
- parameter pserdes_mode = "RX ONLY";
-`else
- `ifdef TX_ONLY
- parameter pserdes_mode = "TX ONLY";
- `else
- parameter pserdes_mode = "RX AND TX";
- `endif
-`endif
-
-`ifdef PORT_TX_RDY
- parameter pport_tx_rdy = "ENABLED";
-`else
- parameter pport_tx_rdy = "DISABLED";
-`endif
-
-`ifdef WAIT_TX_RDY
- parameter pwait_tx_rdy = `WAIT_TX_RDY;
-`else
- parameter pwait_tx_rdy = 3000;
-`endif
-
-`ifdef PORT_RX_RDY
- parameter pport_rx_rdy = "ENABLED";
-`else
- parameter pport_rx_rdy = "DISABLED";
-`endif
-
-`ifdef WAIT_RX_RDY
- parameter pwait_rx_rdy = `WAIT_RX_RDY;
-`else
- parameter pwait_rx_rdy = 3000;
-`endif
-
-// ------------ Local parameters
- localparam wa_num_cycles = 1024;
- localparam dac_num_cycles = 3;
- localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3
- localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz
- localparam lwait_b4_trst_s = 781; // for simulation
- localparam lplol_cnt_width = 20; // width for lwait_b4_trst
- localparam lwait_after_plol0 = 4;
- localparam lwait_b4_rrst = 180224; // total calibration time
- localparam lrrst_wait_width = 20;
- localparam lwait_after_rrst = 800000; // For CPRI- unused
- localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team
- localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst
- localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles
- localparam lwait_after_lols_s = 150; // wait cycles provided by design team
- localparam llols_cnt_width = 18; // lols count width
- localparam lrdb_max = 15; // maximum debounce count
- localparam ltxr_wait_width = 12; // width of tx ready wait counter
- localparam lrxr_wait_width = 12; // width of tx ready wait counter
-
-// ------------ input ports
- input rui_rst;
- input rui_serdes_rst_dual_c;
- input rui_rst_dual_c;
- input rui_rsl_disable;
-
- input rui_tx_ref_clk;
- input rui_tx_serdes_rst_c;
- input [3:0] rui_tx_pcs_rst_c;
- input rdi_pll_lol;
-
- input rui_rx_ref_clk;
- input [3:0] rui_rx_serdes_rst_c;
- input [3:0] rui_rx_pcs_rst_c;
- input [3:0] rdi_rx_los_low_s;
- input [3:0] rdi_rx_cdr_lol_s;
-
-// ------------ output ports
- output rdo_serdes_rst_dual_c;
- output rdo_rst_dual_c;
-
- output ruo_tx_rdy;
- output rdo_tx_serdes_rst_c;
- output [3:0] rdo_tx_pcs_rst_c;
-
- output ruo_rx_rdy;
- output [3:0] rdo_rx_serdes_rst_c;
- output [3:0] rdo_rx_pcs_rst_c;
-
-// ------------ Internal registers and wires
- // inputs
- wire rui_rst;
- wire rui_serdes_rst_dual_c;
- wire rui_rst_dual_c;
- wire rui_rsl_disable;
- wire rui_tx_ref_clk;
- wire rui_tx_serdes_rst_c;
- wire [3:0] rui_tx_pcs_rst_c;
- wire rdi_pll_lol;
- wire rui_rx_ref_clk;
- wire [3:0] rui_rx_serdes_rst_c;
- wire [3:0] rui_rx_pcs_rst_c;
- wire [3:0] rdi_rx_los_low_s;
- wire [3:0] rdi_rx_cdr_lol_s;
-
- // outputs
- wire rdo_serdes_rst_dual_c;
- wire rdo_rst_dual_c;
- wire ruo_tx_rdy;
- wire rdo_tx_serdes_rst_c;
- wire [3:0] rdo_tx_pcs_rst_c;
- wire ruo_rx_rdy;
- wire [3:0] rdo_rx_serdes_rst_c;
- wire [3:0] rdo_rx_pcs_rst_c;
-
- // internal signals
- // common
- wire rsl_enable;
- wire [lplol_cnt_width-1:0] wait_b4_trst;
- wire [lrlol_cnt_width-1:0] wait_b4_rrst;
- wire [llols_cnt_width-1:0] wait_after_lols;
- reg pll_lol_p1;
- reg pll_lol_p2;
- reg pll_lol_p3;
- // ------------ Tx
- // rdo_tx_serdes_rst_c
- reg [lplol_cnt_width-1:0] plol_cnt;
- wire plol_cnt_tc;
-
- reg [2:0] txs_cnt;
- reg txs_rst;
- wire txs_cnt_tc;
- // rdo_tx_pcs_rst_c
- wire plol_fedge;
- wire plol_redge;
- reg waita_plol0;
- reg [2:0] plol0_cnt;
- wire plol0_cnt_tc;
- reg [2:0] txp_cnt;
- reg txp_rst;
- wire txp_cnt_tc;
- // ruo_tx_rdy
- wire dual_or_serd_rst;
- wire tx_any_pcs_rst;
- wire tx_any_rst;
- reg txsr_appd /* synthesis syn_keep=1 */;
- reg txdpr_appd;
- reg [pnum_channels-1:0] txpr_appd;
- reg txr_wt_en;
- reg [ltxr_wait_width-1:0] txr_wt_cnt;
- wire txr_wt_tc;
- reg ruo_tx_rdyr;
-
- // ------------ Rx
- wire comb_rlos;
- wire comb_rlol;
- //wire rlols;
- wire rx_all_well;
-
- //reg rlols_p1;
- //reg rlols_p2;
- //reg rlols_p3;
-
- reg rlol_p1;
- reg rlol_p2;
- reg rlol_p3;
- reg rlos_p1;
- reg rlos_p2;
- reg rlos_p3;
-
- //reg [3:0] rdb_cnt;
- //wire rdb_cnt_max;
- //wire rdb_cnt_zero;
- //reg rlols_db;
- //reg rlols_db_p1;
-
- reg [3:0] rlol_db_cnt;
- wire rlol_db_cnt_max;
- wire rlol_db_cnt_zero;
- reg rlol_db;
- reg rlol_db_p1;
-
- reg [3:0] rlos_db_cnt;
- wire rlos_db_cnt_max;
- wire rlos_db_cnt_zero;
- reg rlos_db;
- reg rlos_db_p1;
-
- // rdo_rx_serdes_rst_c
- reg [lrlol_cnt_width-1:0] rlol1_cnt;
- wire rlol1_cnt_tc;
- reg [2:0] rxs_cnt;
- reg rxs_rst;
- wire rxs_cnt_tc;
- reg [lrrst_wait_width-1:0] rrst_cnt;
- wire rrst_cnt_tc;
- reg rrst_wait;
- // rdo_rx_pcs_rst_c
- //wire rlols_fedge;
- //wire rlols_redge;
- wire rlol_fedge;
- wire rlol_redge;
- wire rlos_fedge;
- wire rlos_redge;
-
- reg wait_calib;
- reg waita_rlols0;
- reg [llols_cnt_width-1:0] rlols0_cnt;
- wire rlols0_cnt_tc;
- reg [2:0] rxp_cnt;
- reg rxp_rst;
- wire rxp_cnt_tc;
-
- wire rx_any_serd_rst;
- reg [llols_cnt_width-1:0] rlolsz_cnt;
- wire rlolsz_cnt_tc;
- reg [2:0] rxp_cnt2;
- reg rxp_rst2;
- wire rxp_cnt2_tc;
- reg [15:0] data_loop_b_cnt;
- reg data_loop_b;
- wire data_loop_b_tc;
-
- // ruo_rx_rdy
- reg [pnum_channels-1:0] rxsr_appd;
- reg [pnum_channels-1:0] rxpr_appd;
- reg rxsdr_appd /* synthesis syn_keep=1 */;
- reg rxdpr_appd;
- wire rxsdr_or_sr_appd;
- wire dual_or_rserd_rst;
- wire rx_any_pcs_rst;
- wire rx_any_rst;
- reg rxr_wt_en;
- reg [lrxr_wait_width-1:0] rxr_wt_cnt;
- wire rxr_wt_tc;
- reg ruo_rx_rdyr;
-
-// ==================================================================
-// Start of code
-// ==================================================================
- assign rsl_enable = ~rui_rsl_disable;
-
-// ------------ rdo_serdes_rst_dual_c
- assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c;
-
-// ------------ rdo_rst_dual_c
- assign rdo_rst_dual_c = rui_rst_dual_c;
-
-// ------------ Setting counter values for RSL_SIM_MODE
- `ifdef RSL_SIM_MODE
- assign wait_b4_trst = lwait_b4_trst_s;
- assign wait_b4_rrst = lwait_b4_rrst_s;
- assign wait_after_lols = lwait_after_lols_s;
- `else
- assign wait_b4_trst = lwait_b4_trst;
- assign wait_b4_rrst = lwait_b4_rrst;
- assign wait_after_lols = lwait_after_lols;
- `endif
-
-// ==================================================================
-// Tx
-// ==================================================================
- generate
- if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin
-
-// ------------ Synchronizing pll_lol to the tx clock
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) begin
- pll_lol_p1 <= 1'd0;
- pll_lol_p2 <= 1'd0;
- pll_lol_p3 <= 1'd0;
- end
- else begin
- pll_lol_p1 <= rdi_pll_lol;
- pll_lol_p2 <= pll_lol_p1;
- pll_lol_p3 <= pll_lol_p2;
- end
- end
-
-// ------------ rdo_tx_serdes_rst_c
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- plol_cnt <= 'd0;
- else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1))
- plol_cnt <= 'd0;
- else
- plol_cnt <= plol_cnt+1;
- end
- assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0;
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) begin
- txs_cnt <= 'd0; // tx serdes reset pulse count
- txs_rst <= 1'b0; // tx serdes reset
- end
- else if(plol_cnt_tc==1)
- txs_rst <= 1'b1;
- else if(txs_cnt_tc==1) begin
- txs_cnt <= 'd0;
- txs_rst <= 1'b0;
- end
- else if(txs_rst==1)
- txs_cnt <= txs_cnt+1;
- end
- assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0;
-
- assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c;
-
-// ------------ rdo_tx_pcs_rst_c
- assign plol_fedge = ~pll_lol_p2 & pll_lol_p3;
- assign plol_redge = pll_lol_p2 & ~pll_lol_p3;
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- waita_plol0 <= 1'd0;
- else if(plol_fedge==1'b1)
- waita_plol0 <= 1'b1;
- else if((plol0_cnt_tc==1)||(plol_redge==1))
- waita_plol0 <= 1'd0;
- end
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- plol0_cnt <= 'd0;
- else if((pll_lol_p2==1)||(plol0_cnt_tc==1))
- plol0_cnt <= 'd0;
- else if(waita_plol0==1'b1)
- plol0_cnt <= plol0_cnt+1;
- end
- assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0;
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) begin
- txp_cnt <= 'd0; // tx serdes reset pulse count
- txp_rst <= 1'b0; // tx serdes reset
- end
- else if(plol0_cnt_tc==1)
- txp_rst <= 1'b1;
- else if(txp_cnt_tc==1) begin
- txp_cnt <= 'd0;
- txp_rst <= 1'b0;
- end
- else if(txp_rst==1)
- txp_cnt <= txp_cnt+1;
- end
- assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0;
-
- genvar i;
- for(i=0;i<pnum_channels;i=i+1) begin : ifor
- assign rdo_tx_pcs_rst_c[i] = (rsl_enable&txp_rst)| rui_tx_pcs_rst_c[i];
- end
- if(pnum_channels==1)
- assign rdo_tx_pcs_rst_c[3:1] = 3'b000;
- else if(pnum_channels==2)
- assign rdo_tx_pcs_rst_c[3:2] = 2'b00;
-
- // ------------ ruo_tx_rdy
- if(pport_tx_rdy=="ENABLED") begin
- assign dual_or_serd_rst = rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c;
- assign tx_any_pcs_rst = rdo_rst_dual_c|(|rdo_tx_pcs_rst_c[pnum_channels-1:0]);
- assign tx_any_rst = dual_or_serd_rst | tx_any_pcs_rst;
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txsr_appd <= 1'b1; // tx serdes reset applied
- else if(dual_or_serd_rst==1)
- txsr_appd <= 1'b1;
- end
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txdpr_appd <= 1'b0; // tx dual (pcs) reset applied
- else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
- txdpr_appd <= 1'b0;
- else if(rdo_rst_dual_c==1)
- txdpr_appd <= 1'b1;
- end
-
- genvar m;
- for(m=0;m<pnum_channels;m=m+1) begin :mfor
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txpr_appd[m] <= 1'b0; // tx pcs reset applied
- else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
- txpr_appd[m] <= 1'b0;
- else if(txsr_appd&(rdo_tx_pcs_rst_c[m]|txdpr_appd))
- txpr_appd[m] <= 1'b1;
- end
- end
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txr_wt_en <= 0; // tx ready wait counter enable
- else if((txr_wt_tc==1)||(dual_or_serd_rst==1))
- txr_wt_en <= 0;
- else if((~ruo_tx_rdyr)&(~pll_lol_p2)&(&txpr_appd))
- txr_wt_en <= 1;
- end
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- txr_wt_cnt <= 'd0; // tx ready wait count
- else if((txr_wt_tc==1)||(tx_any_rst==1))
- txr_wt_cnt <= 'd0;
- else if(txr_wt_en==1)
- txr_wt_cnt <= txr_wt_cnt+1;
- end
- assign txr_wt_tc = (txr_wt_cnt==pwait_tx_rdy)?1'b1:1'b0;
-
- always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- ruo_tx_rdyr <= 1'b0; // tx serdes reset applied
- else if((tx_any_rst==1)||(pll_lol_p2==1))
- ruo_tx_rdyr <= 1'b0;
- else if(txr_wt_tc==1)
- ruo_tx_rdyr <= 1'b1;
- end
- assign ruo_tx_rdy = ruo_tx_rdyr;
- end // if pport_tx_rdy
- else
- assign ruo_tx_rdy = 1'b0;
- end // generate if(Rx and Tx) or (Tx only)
- else begin // generate else (Rx only)
- assign rdo_tx_serdes_rst_c = 1'b0;
- assign rdo_tx_pcs_rst_c = 4'd0;
- assign ruo_tx_rdy = 1'b0;
- end
- endgenerate
-
-// ==================================================================
-// Rx
-// ==================================================================
- generate
- if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY")) begin
- assign comb_rlos = |rdi_rx_los_low_s[pnum_channels-1:0];
- assign comb_rlol = |rdi_rx_cdr_lol_s[pnum_channels-1:0];
- //assign rlols = comb_rlos|comb_rlol;
-
- // ------------ Synchronizing rlols to the rx ref clock
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) begin
- //rlols_p1 <= 1'd0;
- //rlols_p2 <= 1'd0;
- //rlols_p3 <= 1'd0;
- //rlols_db_p1 <= 1'd1;
-
- rlol_p1 <= 1'd0;
- rlol_p2 <= 1'd0;
- rlol_p3 <= 1'd0;
- rlol_db_p1 <= 1'd1;
-
- rlos_p1 <= 1'd0;
- rlos_p2 <= 1'd0;
- rlos_p3 <= 1'd0;
- rlos_db_p1 <= 1'd1;
- end
- else begin
- //rlols_p1 <= rlols;
- //rlols_p2 <= rlols_p1;
- //rlols_p3 <= rlols_p2;
- //rlols_db_p1 <= rlols_db;
-
- rlol_p1 <= comb_rlol;
- rlol_p2 <= rlol_p1;
- rlol_p3 <= rlol_p2;
- rlol_db_p1 <= rlol_db;
-
- rlos_p1 <= comb_rlos;
- rlos_p2 <= rlos_p1;
- rlos_p3 <= rlos_p2;
- rlos_db_p1 <= rlos_db;
- end
- end
- assign rx_all_well = ~rlol_db && ~rlos_db;
-
-//******************************************************************************
-// [ES:05.03.17] Unused registers for clean-up
-//------------------------------------------------------------------------------
-// ------------ Debouncing rlols
-// always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
-// if(rui_rst==1'b1) rdb_cnt <= lrdb_max;
-// else if(rlols_p2==1) begin
-// if(!rdb_cnt_max) rdb_cnt <= rdb_cnt+1;
-// end
-// else if(!rdb_cnt_zero) rdb_cnt <= rdb_cnt-1;
-// end
-// assign rdb_cnt_max = (rdb_cnt==lrdb_max);
-// assign rdb_cnt_zero = (rdb_cnt==0);
-// always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
-// if(rui_rst==1'b1) rlols_db <= 1;
-// else if(rdb_cnt_max) rlols_db <= 1;
-// else if(rdb_cnt_zero) rlols_db <= 0;
-// end
-//******************************************************************************
-
-// ------------ Debouncing rlol
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) rlol_db_cnt <= lrdb_max;
- else if(rlol_p2==1) begin
- if(!rlol_db_cnt_max) rlol_db_cnt <= rlol_db_cnt+1;
- end
- else if(!rlol_db_cnt_zero) rlol_db_cnt <= rlol_db_cnt-1;
- end
- assign rlol_db_cnt_max = (rlol_db_cnt==lrdb_max);
- assign rlol_db_cnt_zero = (rlol_db_cnt==0);
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) rlol_db <= 1;
- else if(rlol_db_cnt_max) rlol_db <= 1;
- else if(rlol_db_cnt_zero) rlol_db <= 0;
- end
-
-// ------------ Debouncing rlos
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) rlos_db_cnt <= lrdb_max;
- else if(rlos_p2==1) begin
- if(!rlos_db_cnt_max) rlos_db_cnt <= rlos_db_cnt+1;
- end
- else if(!rlos_db_cnt_zero) rlos_db_cnt <= rlos_db_cnt-1;
- end
- assign rlos_db_cnt_max = (rlos_db_cnt==lrdb_max);
- assign rlos_db_cnt_zero = (rlos_db_cnt==0);
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1) rlos_db <= 1;
- else if(rlos_db_cnt_max) rlos_db <= 1;
- else if(rlos_db_cnt_zero) rlos_db <= 0;
- end
-
-// ------------ Calib time trigger
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- wait_calib <= 1'd1;
- end
- else begin
- if (rlol1_cnt_tc) begin
- if (rlol_db)
- wait_calib <= 1'd1;
- else
- wait_calib <= 1'd0;
- end
- else if (rlos_redge)
- wait_calib <= 1'd0;
- else if (rlos_fedge) begin
- wait_calib <= 1'd1;
- end
- end
- end
-
- //***************************************************************************
- // Total calibration time counter
- // - this covers the band calibration time (256 cycles * 64) and
- // DAC calibration time (16384 cycles * 10 bits)
- //---------------------------------------------------------------------------
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- rlol1_cnt <= 'd0; // Counting when Rx LOL is 1 and Rx LOS is 0
- end
- else begin
- if(rxs_rst || rlol1_cnt_tc || rlos_redge)
- rlol1_cnt <= 'd0;
- else if (wait_calib)
- rlol1_cnt <= rlol1_cnt+1;
- end
- end
- assign rlol1_cnt_tc = (rlol1_cnt==wait_b4_rrst);
-
-// ------------ rdo_rx_serdes_rst_c
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- rxs_cnt <= 'd0; // rx serdes reset pulse count
- rxs_rst <= 1'b0; // rx serdes reset
- end
- else begin
- if (rlos_db)
- rxs_rst <= 1'b0;
- else if (rlol1_cnt_tc && rlol_db)
- rxs_rst <= 1'b1;
- else if (rxs_cnt_tc==1) begin
- rxs_rst <= 1'b0;
- end
-
- if (rxs_cnt_tc)
- rxs_cnt <= 'd0;
- else
- if (rxs_rst==1)
- rxs_cnt <= rxs_cnt+1;
- end
- end
- assign rxs_cnt_tc = (rxs_cnt==lreset_pwidth)?1'b1:1'b0;
-
- //***************************************************************************
- // [ES:05.03.17] Unused logic from CPRI rrst_wait
- //---------------------------------------------------------------------------
- // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- // if(rui_rst==1'b1)
- // rrst_cnt <= 'd0;
- // else if(rlol1_cnt_tc)
- // rrst_cnt <= 'd0;
- // else if(rrst_wait)
- // rrst_cnt <= rrst_cnt+1;
- // end
- // assign rrst_cnt_tc = (rrst_cnt==lwait_after_rrst) ? 1'b1 : 1'b0;
- // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- // if(rui_rst==1'b1)
- // rrst_wait <= 0;
- // else if(pprotocol != "CPRI")
- // rrst_wait <= 0;
- // else if(rlol1_cnt_tc)
- // rrst_wait <= 1;
- // else if(rrst_cnt_tc==1)
- // rrst_wait <= 0;
- // end
- //***************************************************************************
-
- genvar j;
- for(j=0;j<pnum_channels;j=j+1) begin :jfor
- assign rdo_rx_serdes_rst_c[j] = (rsl_enable&rxs_rst)| rui_rx_serdes_rst_c[j];
- end
- if(pnum_channels==1)
- assign rdo_rx_serdes_rst_c[3:1] = 3'b000;
- else if(pnum_channels==2)
- assign rdo_rx_serdes_rst_c[3:2] = 2'b00;
-
-// ------------ rdo_rx_pcs_rst_c
- //assign rlols_fedge = ~rlols_db & rlols_db_p1;
- //assign rlols_redge = rlols_db & ~rlols_db_p1;
-
- assign rlol_fedge = ~rlol_db & rlol_db_p1;
- assign rlol_redge = rlol_db & ~rlol_db_p1;
- assign rlos_fedge = ~rlos_db & rlos_db_p1;
- assign rlos_redge = rlos_db & ~rlos_db_p1;
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- waita_rlols0 <= 1'd0;
- end
- else begin
- if ((rlos_fedge && ~rlol_db) || (rlol_fedge && ~rlos_db))
- waita_rlols0 <= 1'b1;
- else if (rlos_redge || rlol_redge)
- waita_rlols0 <= 1'd0;
- else if (rlols0_cnt_tc==1)
- waita_rlols0 <= 1'd0;
- end
- end
-
- //***************************************************************************
- // Post RLOL check before pcs_rst deassertion
- // - allowance of 2-4 DAC calibration cycles + 1024 cycles for WA module
- // (word alignment).
- //---------------------------------------------------------------------------
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- rlols0_cnt <= 'd0;
- end
- else begin
- if (rlol_redge || rlos_redge || rlols0_cnt_tc)
- rlols0_cnt <= 'd0;
- else if (waita_rlols0==1)
- rlols0_cnt <= rlols0_cnt+1;
- end
- end
- assign rlols0_cnt_tc = (rlols0_cnt == wait_after_lols);
- assign rx_any_serd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c);
-
- //***************************************************************************
- // [ES:05.03.17] Unused registers for clean-up
- //---------------------------------------------------------------------------
- // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- // if(rui_rst==1'b1)
- // rlolsz_cnt <= 'd0; // Counting when both Rx LOL is 0 and Rx LOS is 0
- // else if((rlol_db|rx_any_serd_rst)||(rlolsz_cnt_tc==1))
- // rlolsz_cnt <= 'd0;
- // else if((rlolsz_cnt_tc==0)&&(rlol_db==0))
- // rlolsz_cnt <= rlolsz_cnt+1;
- // end
- // assign rlolsz_cnt_tc = (rlolsz_cnt==wait_after_lols);
- //***************************************************************************
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if (rui_rst==1'b1) begin
- rxp_cnt2 <= 'd0; // pcs serdes reset pulse count
- rxp_rst2 <= 1'b1; // rx pcs reset
- end
- else begin
- if (rx_any_serd_rst || rlos_redge) begin
- rxp_rst2 <= 1'b1;
- end
- else if (rlols0_cnt_tc) begin
- rxp_rst2 <= 1'b0;
- end
- //***********************************************************************
- // [ES:05.03.17] No need for pulse width
- //-----------------------------------------------------------------------
- // else if(rxp_cnt2_tc==1) begin
- // rxp_cnt2 <= 'd0;
- // rxp_rst2 <= 1'b0;
- // end
- //***********************************************************************
- // [ES:05.03.17] No need for pulse width
- //-----------------------------------------------------------------------
- // else if (rxp_rst2==1)
- // rxp_cnt2 <= rxp_cnt2+1;
- //***********************************************************************
- end // else: !if(rui_rst==1'b1)
- end // always @ (posedge rui_rx_ref_clk or posedge rui_rst)
- //assign rxp_cnt2_tc = (rxp_cnt2==lreset_pwidth)?1'b1:1'b0;
-
- //***************************************************************************
- // [ES:05.03.17] No need for pulse width
- //---------------------------------------------------------------------------
- //else begin
- // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- // if(rui_rst==1'b1)
- // rxp_rst2 <= 1'b1; // rx pcs reset
- // else if(rx_any_serd_rst)
- // rxp_rst2 <= 1'b1;
- // else if(rlolsz_cnt_tc==1)
- // rxp_rst2 <= 1'b0;
- // end
- //end
- //***************************************************************************
-
- genvar k;
- for(k=0;k<pnum_channels;k=k+1) begin: kfor
- assign rdo_rx_pcs_rst_c[k] = (rsl_enable&rxp_rst2)| rui_rx_pcs_rst_c[k];
- end
- if(pnum_channels==1)
- assign rdo_rx_pcs_rst_c[3:1] = 3'b000;
- else if(pnum_channels==2)
- assign rdo_rx_pcs_rst_c[3:2] = 2'b00;
-
-// ------------ ruo_rx_rdy
- if(pport_rx_rdy=="ENABLED") begin
- assign dual_or_rserd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c[pnum_channels-1:0]);
- assign rx_any_pcs_rst = rdo_rst_dual_c|(|rdo_rx_pcs_rst_c[pnum_channels-1:0]);
- assign rx_any_rst = dual_or_rserd_rst | rx_any_pcs_rst;
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxsdr_appd <= 1'b1; // Serdes dual reset (macro reset) applied
- else if(rdo_serdes_rst_dual_c==1)
- rxsdr_appd <= 1'b1;
- end
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxdpr_appd <= 1'b0; // Rx dual PCS reset (dual reset) applied
- else if(~rx_all_well|dual_or_rserd_rst)
- rxdpr_appd <= 1'b0;
- else if(rdo_rst_dual_c==1)
- rxdpr_appd <= 1'b1;
- end
-
- genvar l;
- for(l=0;l<pnum_channels;l=l+1) begin : lfor
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxsr_appd[l] <= 1'b0; // rx serdes reset applied
- else if(rdo_rx_serdes_rst_c[l]==1)
- rxsr_appd[l] <= 1'b1;
- end
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxpr_appd[l] <= 1'b0; // rx pcs reset applied
- else if(rdi_rx_los_low_s[l]|rdi_rx_cdr_lol_s[l]|rdo_serdes_rst_dual_c|rdo_rx_serdes_rst_c[l])
- rxpr_appd[l] <= 1'b0;
- else if(rxsdr_or_sr_appd&(~rx_all_well)&rdo_rx_pcs_rst_c[l])
- rxpr_appd[l] <= 1'b1;
- end
- end
-
- assign rxsdr_or_sr_appd = rxsdr_appd|(&rxsr_appd);
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxr_wt_en <= 0; // rx ready wait counter enable
- //else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1))
- else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1)||(rx_all_well==0)) // BM, 2/4/16
- rxr_wt_en <= 0;
- else if(~ruo_rx_rdyr&rx_all_well&((&rxpr_appd)|rxdpr_appd))
- rxr_wt_en <= 1;
- end
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- rxr_wt_cnt <= 'd0; // rx ready wait count
- //else if((rxr_wt_tc==1)||(rx_any_rst==1))
- else if((rxr_wt_tc==1)||(rx_any_rst==1)||(rx_all_well==0)) // BM, 2/4/16
- rxr_wt_cnt <= 'd0;
- else if(rxr_wt_en==1)
- rxr_wt_cnt <= rxr_wt_cnt+1;
- end
- assign rxr_wt_tc = (rxr_wt_cnt==pwait_rx_rdy)?1'b1:1'b0;
-
- always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
- if(rui_rst==1'b1)
- ruo_rx_rdyr <= 1'b0; // rx serdes reset applied
- else if((rx_any_rst==1)||(rx_all_well==0))
- ruo_rx_rdyr <= 1'b0;
- else if(rxr_wt_tc==1)
- ruo_rx_rdyr <= 1'b1;
- end
- assign ruo_rx_rdy = ruo_rx_rdyr;
- end // if pport_rx_rdy
- else
- assign ruo_rx_rdy = 1'b0;
- end // if ((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
-
- else begin // generate else (Tx only)
- assign rdo_rx_serdes_rst_c = 4'd0;
- assign rdo_rx_pcs_rst_c = 4'd0;
- assign ruo_rx_rdy = 1'b0;
- end // else: !if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
-
- endgenerate
-
-endmodule
-
-
-// ===========================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// ---------------------------------------------------------------------------
-// Copyright (c) 2015 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code
-// pursuant to the terms of the Lattice Reference Design License Agreement.
-//
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// ---------------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// ---------------------------------------------------------------------------
-//
-// =============================================================================
-// FILE DETAILS
-// Project : SLL - Soft Loss Of Lock(LOL) Logic
-// File : sll_core.v
-// Title : Top-level file for SLL
-// Dependencies : 1.
-// : 2.
-// Description :
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.0
-// Author(s) : AV
-// Mod. Date : March 2, 2015
-// Changes Made : Initial Creation
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.1
-// Author(s) : AV
-// Mod. Date : June 8, 2015
-// Changes Made : Following updates were made
-// : 1. Changed all the PLOL status logic and FSM to run
-// : on sli_refclk.
-// : 2. Added the HB logic for presence of tx_pclk
-// : 3. Changed the lparam assignment scheme for
-// : simulation purposes.
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.2
-// Author(s) : AV
-// Mod. Date : June 24, 2015
-// Changes Made : Updated the gearing logic for SDI dynamic rate change
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.3
-// Author(s) : AV
-// Mod. Date : July 14, 2015
-// Changes Made : Added the logic for dynamic rate change in CPRI
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.4
-// Author(s) : AV
-// Mod. Date : August 21, 2015
-// Changes Made : Added the logic for dynamic rate change of 5G CPRI &
-// PCIe.
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.5
-// Author(s) : ES/EB
-// Mod. Date : March 21, 2017
-// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff
-// : to sli_refclk.
-// : 2. Updated terminal count logic for PCIe 5G
-// : 3. Modified checking of pcount_diff in SLL state
-// : machine to cover actual count
-// : (from 16-bits to 22-bits)
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.6
-// Author(s) : ES
-// Mod. Date : April 19, 2017
-// Changes Made : 1. Added registered lock and unlock signal from
-// pdiff_sync to totally decouple pcount_diff from
-// SLL state machine.
-// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI
-// is operating @ 4.9125Gbps data rate.
-// =============================================================================
-`timescale 1ns/10ps
-
-module serdes_sync_0sll_core (
- //Reset and Clock inputs
- sli_rst, //Active high asynchronous reset input
- sli_refclk, //Refclk input to the Tx PLL
- sli_pclk, //Tx pclk output from the PCS
-
- //Control inputs
- sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate
- sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11
- sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20
- sli_cpri_mode, //Mode of operation specific to CPRI protocol
- sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G)
-
- //LOL Output
- slo_plol //Tx PLL Loss of Lock output to the user logic
- );
-
-// Inputs
-input sli_rst;
-input sli_refclk;
-input sli_pclk;
-input sli_div2_rate;
-input sli_div11_rate;
-input sli_gear_mode;
-input [2:0] sli_cpri_mode;
-input sli_pcie_mode;
-
-// Outputs
-output slo_plol;
-
-
-// Parameters
-parameter PPROTOCOL = "PCIE"; //Protocol selected by the User
-parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3
-parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control
-parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate
-parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock
-parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock
-parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk
-parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11
-parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11
-parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk
-
-
-// Local Parameters
-localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state
-localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state
-localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state
-localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state
-`ifdef RSL_SIM_MODE
-localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk
-`else
-localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk
-`endif
-localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse
-localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal
-
-// Local Parameters related to the CPRI dynamic modes
-// Terminal count values for the four CPRI modes
-localparam LPCLK_TC_0 = 32768;
-localparam LPCLK_TC_1 = 65536;
-localparam LPCLK_TC_2 = 131072;
-localparam LPCLK_TC_3 = 163840;
-localparam LPCLK_TC_4 = 65536;
-
-// Lock values count values for the four CPRI modes and four PLOL settings (4x5)
-// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4
-localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19;
-localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19;
-localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98;
-localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262;
-
-// Unlock values count values for the four CPRI modes and four PLOL settings (4x5)
-// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4
-localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39;
-localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131;
-localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144;
-localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393;
-
-// Input and Output reg and wire declarations
-wire sli_rst;
-wire sli_refclk;
-wire sli_pclk;
-wire sli_div2_rate;
-wire sli_div11_rate;
-wire sli_gear_mode;
-wire [2:0] sli_cpri_mode;
-wire sli_pcie_mode;
-wire slo_plol;
-
-//-------------- Internal signals reg and wire declarations --------------------
-
-//Signals running on sli_refclk
-reg [15:0] rcount; //16-bit Counter
-reg rtc_pul; //Terminal count pulse
-reg rtc_pul_p1; //Terminal count pulse pipeline
-reg rtc_ctrl; //Terminal count pulse control
-
-reg [7:0] rhb_wait_cnt; //Heartbeat wait counter
-
-//Heatbeat synchronization and pipeline registers
-wire rhb_sync;
-reg rhb_sync_p2;
-reg rhb_sync_p1;
-
-//Pipeling registers for dynamic control mode
-wire rgear;
-wire rdiv2;
-wire rdiv11;
-reg rgear_p1;
-reg rdiv2_p1;
-reg rdiv11_p1;
-
-reg rstat_pclk; //Pclk presence/absence status
-
-reg [21:0] rcount_tc; //Tx_pclk terminal count register
-reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock
-reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock
-
-wire rpcie_mode; //PCIe mode signal synchronized to refclk
-reg rpcie_mode_p1; //PCIe mode pipeline register
-
-wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk
-reg rcpri_mod_ch_p1; //CPRI mode change pipeline register
-reg rcpri_mod_ch_p2; //CPRI mode change pipeline register
-reg rcpri_mod_ch_st; //CPRI mode change status
-
-reg [1:0] sll_state; //Current-state register for LOL FSM
-
-reg pll_lock; //PLL Lock signal
-
-//Signals running on sli_pclk
-//Synchronization and pipeline registers
-wire ppul_sync;
-reg ppul_sync_p1;
-reg ppul_sync_p2;
-reg ppul_sync_p3;
-
-wire pdiff_sync;
-reg pdiff_sync_p1;
-
-reg [21:0] pcount; //22-bit counter
-reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value
-
-//Heartbeat counter and heartbeat signal running on pclk
-reg [2:0] phb_cnt;
-reg phb;
-
-//CPRI dynamic mode releated signals
-reg [2:0] pcpri_mode;
-reg pcpri_mod_ch;
-
-//Assignment scheme changed mainly for simulation purpose
-wire [15:0] LRCLK_TC_w;
-assign LRCLK_TC_w = LRCLK_TC;
-
-reg unlock;
-reg lock;
-
-//Heartbeat synchronization
-sync # (.PDATA_RST_VAL(0)) phb_sync_inst (
- .clk (sli_refclk),
- .rst (sli_rst),
- .data_in (phb),
- .data_out(rhb_sync)
- );
-
-
-//Terminal count pulse synchronization
-sync # (.PDATA_RST_VAL(0)) rtc_sync_inst (
- .clk (sli_pclk),
- .rst (sli_rst),
- .data_in (rtc_pul),
- .data_out(ppul_sync)
- );
-
-//Differential value logic update synchronization
-sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst (
- .clk (sli_refclk),
- .rst (sli_rst),
- .data_in (ppul_sync),
- .data_out(pdiff_sync)
- );
-
-//Gear mode synchronization
-sync # (.PDATA_RST_VAL(0)) gear_sync_inst (
- .clk (sli_refclk),
- .rst (sli_rst),
- .data_in (sli_gear_mode),
- .data_out(rgear)
- );
-
-//Div2 synchronization
-sync # (.PDATA_RST_VAL(0)) div2_sync_inst (
- .clk (sli_refclk),
- .rst (sli_rst),
- .data_in (sli_div2_rate),
- .data_out(rdiv2)
- );
-
-//Div11 synchronization
-sync # (.PDATA_RST_VAL(0)) div11_sync_inst (
- .clk (sli_refclk),
- .rst (sli_rst),
- .data_in (sli_div11_rate),
- .data_out(rdiv11)
- );
-
-//CPRI mode change synchronization
-sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst (
- .clk (sli_refclk),
- .rst (sli_rst),
- .data_in (pcpri_mod_ch),
- .data_out(rcpri_mod_ch_sync)
- );
-
-//PCIe mode change synchronization
-sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst (
- .clk (sli_refclk),
- .rst (sli_rst),
- .data_in (sli_pcie_mode),
- .data_out(rpcie_mode)
- );
-
-// =============================================================================
-// Synchronized Lock/Unlock signals
-// =============================================================================
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- unlock <= 1'b0;
- lock <= 1'b0;
- pdiff_sync_p1 <= 1'b0;
- end
- else begin
- pdiff_sync_p1 <= pdiff_sync;
- if (unlock) begin
- unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock;
- end
- else begin
- unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0;
- end
- if (lock) begin
- lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock;
- end
- else begin
- lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0;
- end
- end
-end
-
-// =============================================================================
-// Refclk Counter, pulse generation logic and Heartbeat monitor logic
-// =============================================================================
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- rcount <= 16'd0;
- rtc_pul <= 1'b0;
- rtc_ctrl <= 1'b0;
- rtc_pul_p1 <= 1'b0;
- end
- else begin
- //Counter logic
- if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
- if (rtc_ctrl == 1'b1) begin
- rcount <= LRCLK_TC_PUL_WIDTH;
- end
- end
- else begin
- if (rcount != LRCLK_TC_w) begin
- rcount <= rcount + 1;
- end
- else begin
- rcount <= 16'd0;
- end
- end
-
- //Pulse control logic
- if (rcount == LRCLK_TC_w - 1) begin
- rtc_ctrl <= 1'b1;
- end
-
- //Pulse Generation logic
- if (rtc_ctrl == 1'b1) begin
- if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin
- rtc_pul <= 1'b1;
- end
- else begin
- rtc_pul <= 1'b0;
- end
- end
-
- rtc_pul_p1 <= rtc_pul;
- end
-end
-
-
-// =============================================================================
-// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic
-// =============================================================================
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- rhb_sync_p1 <= 1'b0;
- rhb_sync_p2 <= 1'b0;
- rhb_wait_cnt <= 8'd0;
- rstat_pclk <= 1'b0;
- rgear_p1 <= 1'b0;
- rdiv2_p1 <= 1'b0;
- rdiv11_p1 <= 1'b0;
- rcpri_mod_ch_p1 <= 1'b0;
- rcpri_mod_ch_p2 <= 1'b0;
- rcpri_mod_ch_st <= 1'b0;
- rpcie_mode_p1 <= 1'b0;
-
- end
- else begin
- //Pipeline stages for the Heartbeat
- rhb_sync_p1 <= rhb_sync;
- rhb_sync_p2 <= rhb_sync_p1;
-
- //Pipeline stages of the Dynamic rate control signals
- rgear_p1 <= rgear;
- rdiv2_p1 <= rdiv2;
- rdiv11_p1 <= rdiv11;
-
- //Pipeline stage for PCIe mode
- rpcie_mode_p1 <= rpcie_mode;
-
- //Pipeline stage for CPRI mode change
- rcpri_mod_ch_p1 <= rcpri_mod_ch_sync;
- rcpri_mod_ch_p2 <= rcpri_mod_ch_p1;
-
- //CPRI mode change status logic
- if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin
- rcpri_mod_ch_st <= 1'b1;
- end
-
- //Heartbeat wait counter and monitor logic
- if (rtc_ctrl == 1'b1) begin
- if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin
- rhb_wait_cnt <= 8'd0;
- rstat_pclk <= 1'b1;
- end
- else if (rhb_wait_cnt == LHB_WAIT_CNT) begin
- rhb_wait_cnt <= 8'd0;
- rstat_pclk <= 1'b0;
- end
- else begin
- rhb_wait_cnt <= rhb_wait_cnt + 1;
- end
- end
- end
-end
-
-
-// =============================================================================
-// Pipleline registers for the TC pulse and CPRI mode change logic
-// =============================================================================
-always @(posedge sli_pclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- ppul_sync_p1 <= 1'b0;
- ppul_sync_p2 <= 1'b0;
- ppul_sync_p3 <= 1'b0;
- pcpri_mode <= 3'b0;
- pcpri_mod_ch <= 1'b0;
- end
- else begin
- ppul_sync_p1 <= ppul_sync;
- ppul_sync_p2 <= ppul_sync_p1;
- ppul_sync_p3 <= ppul_sync_p2;
-
- //CPRI mode change logic
- pcpri_mode <= sli_cpri_mode;
-
- if (pcpri_mode != sli_cpri_mode) begin
- pcpri_mod_ch <= ~pcpri_mod_ch;
- end
- end
-end
-
-
-// =============================================================================
-// Terminal count logic
-// =============================================================================
-
-//For SDI protocol with Dynamic rate control enabled
-generate
-if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- rcount_tc <= 22'd0;
- rdiff_comp_lock <= 16'd0;
- rdiff_comp_unlock <= 16'd0;
- end
- else begin
- //Terminal count logic
- //Div by 11 is enabled
- if (rdiv11 == 1'b1) begin
- //Gear mode is 16/20
- if (rgear == 1'b1) begin
- rcount_tc <= PPCLK_DIV11_TC;
- rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK;
- rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK;
- end
- else begin
- rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0};
- rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0};
- rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0};
- end
- end
- //Div by 2 is enabled
- else if (rdiv2 == 1'b1) begin
- //Gear mode is 16/20
- if (rgear == 1'b1) begin
- rcount_tc <= {1'b0,PPCLK_TC[21:1]};
- rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]};
- rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
- end
- else begin
- rcount_tc <= PPCLK_TC;
- rdiff_comp_lock <= PDIFF_VAL_LOCK;
- rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
- end
- end
- //Both div by 11 and div by 2 are disabled
- else begin
- //Gear mode is 16/20
- if (rgear == 1'b1) begin
- rcount_tc <= PPCLK_TC;
- rdiff_comp_lock <= PDIFF_VAL_LOCK;
- rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
- end
- else begin
- rcount_tc <= {PPCLK_TC[20:0],1'b0};
- rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0};
- rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0};
- end
- end
- end
-end
-end
-endgenerate
-
-//For G8B10B protocol with Dynamic rate control enabled
-generate
-if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- rcount_tc <= 22'd0;
- rdiff_comp_lock <= 16'd0;
- rdiff_comp_unlock <= 16'd0;
- end
- else begin
- //Terminal count logic
- //Div by 2 is enabled
- if (rdiv2 == 1'b1) begin
- rcount_tc <= {1'b0,PPCLK_TC[21:1]};
- rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]};
- rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
- end
- else begin
- rcount_tc <= PPCLK_TC;
- rdiff_comp_lock <= PDIFF_VAL_LOCK;
- rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
- end
- end
-end
-end
-endgenerate
-
-
-//For CPRI protocol with Dynamic rate control is disabled
-generate
-if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- rcount_tc <= 22'd0;
- rdiff_comp_lock <= 16'd0;
- rdiff_comp_unlock <= 16'd0;
- end
- else begin
- //Terminal count logic for CPRI protocol
- //Only if there is a change in the rate mode from the default
- if (rcpri_mod_ch_st == 1'b1) begin
- if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin
- case(sli_cpri_mode)
- 3'd0 : begin //For 0.6Gbps
- rcount_tc <= LPCLK_TC_0;
- case(PLOL_SETTING)
- 'd0 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_00;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
- end
-
- 'd1 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_01;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_01;
- end
-
- 'd2 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_02;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_02;
- end
-
- 'd3 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_03;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_03;
- end
-
- default : begin
- rdiff_comp_lock <= LPDIFF_LOCK_00;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
- end
- endcase
- end
-
- 3'd1 : begin //For 1.2Gbps
- rcount_tc <= LPCLK_TC_1;
- case(PLOL_SETTING)
- 'd0 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_10;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
- end
-
- 'd1 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_11;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_11;
- end
-
- 'd2 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_12;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_12;
- end
-
- 'd3 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_13;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_13;
- end
-
- default : begin
- rdiff_comp_lock <= LPDIFF_LOCK_10;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
- end
- endcase
- end
-
- 3'd2 : begin //For 2.4Gbps
- rcount_tc <= LPCLK_TC_2;
- case(PLOL_SETTING)
- 'd0 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_20;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
- end
-
- 'd1 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_21;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_21;
- end
-
- 'd2 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_22;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_22;
- end
-
- 'd3 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_23;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_23;
- end
-
- default : begin
- rdiff_comp_lock <= LPDIFF_LOCK_20;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
- end
- endcase
- end
-
- 3'd3 : begin //For 3.07Gbps
- rcount_tc <= LPCLK_TC_3;
- case(PLOL_SETTING)
- 'd0 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_30;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_30;
- end
-
- 'd1 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_31;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_31;
- end
-
- 'd2 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_32;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_32;
- end
-
- 'd3 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_33;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_33;
- end
- endcase
- end
-
- 3'd4 : begin //For 4.9125bps
- rcount_tc <= LPCLK_TC_4;
- case(PLOL_SETTING)
- 'd0 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_40;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
- end
-
- 'd1 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_41;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_41;
- end
-
- 'd2 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_42;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_42;
- end
-
- 'd3 : begin
- rdiff_comp_lock <= LPDIFF_LOCK_43;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_43;
- end
-
- default : begin
- rdiff_comp_lock <= LPDIFF_LOCK_40;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
- end
- endcase
- end
-
- default : begin
- rcount_tc <= LPCLK_TC_0;
- rdiff_comp_lock <= LPDIFF_LOCK_00;
- rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
- end
- endcase
- end
- end
- else begin
- //If there is no change in the CPRI rate mode from default
- rcount_tc <= PPCLK_TC;
- rdiff_comp_lock <= PDIFF_VAL_LOCK;
- rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
- end
- end
-end
-end
-endgenerate
-
-//For PCIe protocol with Dynamic rate control disabled
-generate
-if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- rcount_tc <= 22'd0;
- rdiff_comp_lock <= 16'd0;
- rdiff_comp_unlock <= 16'd0;
- end
- else begin
- //Terminal count logic
- if (PPCIE_MAX_RATE == "2.5") begin
- //2.5G mode is enabled
- rcount_tc <= PPCLK_TC;
- rdiff_comp_lock <= PDIFF_VAL_LOCK;
- rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
- end
- else begin
- //5G mode is enabled
- if (rpcie_mode == 1'b1) begin
- rcount_tc <= PPCLK_TC;
- rdiff_comp_lock <= PDIFF_VAL_LOCK;
- rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
- end
- else begin
- //2.5G mode is enabled
- rcount_tc <= {1'b0,PPCLK_TC[21:1]};
- rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]};
- rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
- end
- end
- end
-end
-end
-endgenerate
-
-//For all protocols other than CPRI & PCIe
-generate
-if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- rcount_tc <= 22'd0;
- rdiff_comp_lock <= 16'd0;
- rdiff_comp_unlock <= 16'd0;
- end
- else begin
- //Terminal count logic for all protocols other than CPRI & PCIe
- rcount_tc <= PPCLK_TC;
- rdiff_comp_lock <= PDIFF_VAL_LOCK;
- rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
- end
-end
-end
-endgenerate
-
-
-// =============================================================================
-// Tx_pclk counter, Heartbeat and Differential value logic
-// =============================================================================
-always @(posedge sli_pclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- pcount <= 22'd0;
- pcount_diff <= 22'd65535;
- phb_cnt <= 3'd0;
- phb <= 1'b0;
- end
- else begin
- //Counter logic
- if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
- pcount <= 22'd0;
- end
- else begin
- pcount <= pcount + 1;
- end
-
- //Heartbeat logic
- phb_cnt <= phb_cnt + 1;
-
- if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin
- phb <= 1'b1;
- end
- else begin
- phb <= 1'b0;
- end
-
- //Differential value logic
- if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
- pcount_diff <= rcount_tc + ~(pcount) + 1;
- end
- else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin
- if (pcount_diff[21] == 1'b1) begin
- pcount_diff <= ~(pcount_diff) + 1;
- end
- end
- end
-end
-
-
-// =============================================================================
-// State transition logic for SLL FSM
-// =============================================================================
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- sll_state <= LPLL_LOSS_ST;
- end
- else begin
- //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI
- if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) ||
- (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
- sll_state <= LPLL_LOSS_ST;
- end
- else begin
- case(sll_state)
- LPLL_LOSS_ST : begin
- if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
- if (unlock) begin
- sll_state <= LPLL_LOSS_ST;
- end
- else if (lock) begin
- if (PLOL_SETTING == 2'd0) begin
- sll_state <= LPLL_PRELOCK_ST;
- end
- else begin
- sll_state <= LPLL_LOCK_ST;
- end
- end
- end
- end
-
- LPLL_LOCK_ST : begin
- if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
- if (lock) begin
- sll_state <= LPLL_LOCK_ST;
- end
- else begin
- if (PLOL_SETTING == 2'd0) begin
- sll_state <= LPLL_LOSS_ST;
- end
- else begin
- sll_state <= LPLL_PRELOSS_ST;
- end
- end
- end
- end
-
- LPLL_PRELOCK_ST : begin
- if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
- if (lock) begin
- sll_state <= LPLL_LOCK_ST;
- end
- else begin
- sll_state <= LPLL_PRELOSS_ST;
- end
- end
- end
-
- LPLL_PRELOSS_ST : begin
- if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
- if (unlock) begin
- sll_state <= LPLL_PRELOSS_ST;
- end
- else if (lock) begin
- sll_state <= LPLL_LOCK_ST;
- end
- end
- end
-
- default: begin
- sll_state <= LPLL_LOSS_ST;
- end
- endcase
- end
- end
-end
-
-
-// =============================================================================
-// Logic for Tx PLL Lock
-// =============================================================================
-always @(posedge sli_refclk or posedge sli_rst) begin
- if (sli_rst == 1'b1) begin
- pll_lock <= 1'b0;
- end
- else begin
- case(sll_state)
- LPLL_LOSS_ST : begin
- pll_lock <= 1'b0;
- end
-
- LPLL_LOCK_ST : begin
- pll_lock <= 1'b1;
- end
-
- LPLL_PRELOSS_ST : begin
- pll_lock <= 1'b0;
- end
-
- default: begin
- pll_lock <= 1'b0;
- end
- endcase
- end
-end
-
-assign slo_plol = ~(pll_lock);
-
-endmodule
-
-
-// ===========================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// ---------------------------------------------------------------------------
-// Copyright (c) 2015 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code
-// pursuant to the terms of the Lattice Reference Design License Agreement.
-//
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// ---------------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// ---------------------------------------------------------------------------
-//
-// =============================================================================
-// FILE DETAILS
-// Project : Synchronizer Logic
-// File : sync.v
-// Title : Synchronizer module
-// Description :
-// =============================================================================
-// REVISION HISTORY
-// Version : 1.0
-// Author(s) : AV
-// Mod. Date : July 7, 2015
-// Changes Made : Initial Creation
-// -----------------------------------------------------------------------------
-// Version : 1.1
-// Author(s) : EB
-// Mod. Date : March 21, 2017
-// Changes Made :
-// =============================================================================
-
-`ifndef PCS_SYNC_MODULE
-`define PCS_SYNC_MODULE
-module sync (
- clk,
- rst,
- data_in,
- data_out
- );
-
-input clk; //Clock in which the async data needs to be synchronized to
-input rst; //Active high reset
-input data_in; //Asynchronous data
-output data_out; //Synchronized data
-
-parameter PDATA_RST_VAL = 0; //Reset value for the registers
-
-reg data_p1;
-reg data_p2;
-
-// =============================================================================
-// Synchronization logic
-// =============================================================================
-always @(posedge clk or posedge rst) begin
- if (rst == 1'b1) begin
- data_p1 <= PDATA_RST_VAL;
- data_p2 <= PDATA_RST_VAL;
- end
- else begin
- data_p1 <= data_in;
- data_p2 <= data_p1;
- end
-end
-
-assign data_out = data_p2;
-
-endmodule
-`endif
-
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58)
--- Module Version: 4.4
---/opt/lattice/isplever7.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 18 -depth 512 -no_enable -pe 10 -pf 508 -e
-
--- Thu Mar 19 16:21:17 2009
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity ecp2m_link_fifo is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end ecp2m_link_fifo;
-
-architecture Structure of ecp2m_link_fifo is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal full_i: std_logic;
- signal rRst: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal cmp_ci: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal iae_setcount_0: std_logic;
- signal iae_setcount_1: std_logic;
- signal ae_set_ctr_ci: std_logic;
- signal iae_setcount_2: std_logic;
- signal iae_setcount_3: std_logic;
- signal co0_4: std_logic;
- signal iae_setcount_4: std_logic;
- signal iae_setcount_5: std_logic;
- signal co1_4: std_logic;
- signal iae_setcount_6: std_logic;
- signal iae_setcount_7: std_logic;
- signal co2_4: std_logic;
- signal iae_setcount_8: std_logic;
- signal iae_setcount_9: std_logic;
- signal co4_2: std_logic;
- signal ae_setcount_9: std_logic;
- signal co3_4: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal ae_setcount_0: std_logic;
- signal ae_setcount_1: std_logic;
- signal co0_5: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal ae_setcount_2: std_logic;
- signal ae_setcount_3: std_logic;
- signal co1_5: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal ae_setcount_4: std_logic;
- signal ae_setcount_5: std_logic;
- signal co2_5: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal ae_setcount_6: std_logic;
- signal ae_setcount_7: std_logic;
- signal co3_5: std_logic;
- signal wcount_r8: std_logic;
- signal ae_set_cmp_clr: std_logic;
- signal ae_setcount_8: std_logic;
- signal ae_set_cmp_set: std_logic;
- signal ae_set_d: std_logic;
- signal ae_set_d_c: std_logic;
- signal scuba_vhi: std_logic;
- signal iaf_setcount_0: std_logic;
- signal iaf_setcount_1: std_logic;
- signal af_set_ctr_ci: std_logic;
- signal iaf_setcount_2: std_logic;
- signal iaf_setcount_3: std_logic;
- signal co0_6: std_logic;
- signal iaf_setcount_4: std_logic;
- signal iaf_setcount_5: std_logic;
- signal co1_6: std_logic;
- signal iaf_setcount_6: std_logic;
- signal iaf_setcount_7: std_logic;
- signal co2_6: std_logic;
- signal iaf_setcount_8: std_logic;
- signal iaf_setcount_9: std_logic;
- signal co4_3: std_logic;
- signal af_setcount_9: std_logic;
- signal co3_6: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_3: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal af_setcount_0: std_logic;
- signal af_setcount_1: std_logic;
- signal co0_7: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal af_setcount_2: std_logic;
- signal af_setcount_3: std_logic;
- signal co1_7: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal af_setcount_4: std_logic;
- signal af_setcount_5: std_logic;
- signal co2_7: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal af_setcount_6: std_logic;
- signal af_setcount_7: std_logic;
- signal co3_7: std_logic;
- signal rcount_w8: std_logic;
- signal af_set_cmp_clr: std_logic;
- signal af_setcount_8: std_logic;
- signal af_set_cmp_set: std_logic;
- signal af_set: std_logic;
- signal af_set_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KB
- -- synopsys translate_off
- generic (CSDECODE_R : in std_logic_vector(2 downto 0);
- CSDECODE_W : in std_logic_vector(2 downto 0);
- GSR : in String; RESETMODE : in String;
- REGMODE : in String; DATA_WIDTH_R : in Integer;
- DATA_WIDTH_W : in Integer);
- -- synopsys translate_on
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_R : string;
- attribute CSDECODE_W : string;
- attribute RESETMODE : string;
- attribute REGMODE : string;
- attribute DATA_WIDTH_R : string;
- attribute DATA_WIDTH_W : string;
- attribute GSR : string;
- attribute initval of LUT4_27 : label is "0x6996";
- attribute initval of LUT4_26 : label is "0x6996";
- attribute initval of LUT4_25 : label is "0x6996";
- attribute initval of LUT4_24 : label is "0x6996";
- attribute initval of LUT4_23 : label is "0x6996";
- attribute initval of LUT4_22 : label is "0x6996";
- attribute initval of LUT4_21 : label is "0x6996";
- attribute initval of LUT4_20 : label is "0x6996";
- attribute initval of LUT4_19 : label is "0x6996";
- attribute initval of LUT4_18 : label is "0x6996";
- attribute initval of LUT4_17 : label is "0x6996";
- attribute initval of LUT4_16 : label is "0x6996";
- attribute initval of LUT4_15 : label is "0x6996";
- attribute initval of LUT4_14 : label is "0x6996";
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x0410";
- attribute initval of LUT4_6 : label is "0x1004";
- attribute initval of LUT4_5 : label is "0x0140";
- attribute initval of LUT4_4 : label is "0x4001";
- attribute initval of LUT4_3 : label is "0x13c8";
- attribute initval of LUT4_2 : label is "0x2004";
- attribute initval of LUT4_1 : label is "0x4c32";
- attribute initval of LUT4_0 : label is "0x8001";
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "ecp2m_link_fifo.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000";
- attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
- attribute GSR of pdp_ram_0_0_0 : label is "ENABLED";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
- attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG";
- attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
- attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_27: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_26: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_25: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_24: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_23: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_22: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_21: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_20: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_19: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_18: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_14: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x13c8")
- -- synopsys translate_on
- port map (AD3=>ae_setcount_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>rptr_9, DO0=>ae_set_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x2004")
- -- synopsys translate_on
- port map (AD3=>ae_setcount_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>rptr_9, DO0=>ae_set_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4c32")
- -- synopsys translate_on
- port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>wptr_9, DO0=>af_set_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8001")
- -- synopsys translate_on
- port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>wptr_9, DO0=>af_set_cmp_clr);
-
- pdp_ram_0_0_0: PDPW16KB
- -- synopsys translate_off
- generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "ENABLED",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
- DATA_WIDTH_W=> 36)
- -- synopsys translate_on
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
- DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
- DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
- DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
- DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
- ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7,
- ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
- DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
- DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
- DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0),
- DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
- DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
- DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
- DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
-
- FF_123: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_122: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_121: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_120: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_119: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_118: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_117: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_116: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_115: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_114: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_113: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_112: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_111: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_110: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_109: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_108: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_107: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_106: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_105: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_104: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_103: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_102: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_101: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_100: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_99: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_98: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_97: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_96: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_95: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_94: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_93: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_92: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_91: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_90: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_89: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_88: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_87: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_86: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_85: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_84: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_83: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_82: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_81: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_80: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_79: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_78: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_77: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_76: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_75: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_74: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_73: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_72: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_71: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_70: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_69: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_63: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_62: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_61: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_60: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_59: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_58: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_57: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_56: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_55: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_54: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_53: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_52: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_51: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_50: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_49: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_48: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_47: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_46: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_45: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_44: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_43: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_42: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_41: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_40: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_39: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_38: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_37: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_36: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_35: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_34: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_33: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_32: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_31: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_30: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_29: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_28: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_23: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- FF_21: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>ae_setcount_0);
-
- FF_20: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_1, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>ae_setcount_1);
-
- FF_19: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_2);
-
- FF_18: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_3, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>ae_setcount_3);
-
- FF_17: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_4);
-
- FF_16: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_5);
-
- FF_15: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_6);
-
- FF_14: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_7);
-
- FF_13: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_8);
-
- FF_12: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_9);
-
- FF_11: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ae_set_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
-
- FF_10: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_0);
-
- FF_9: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_1);
-
- FF_8: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_2);
-
- FF_7: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_3);
-
- FF_6: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_4);
-
- FF_5: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_5);
-
- FF_4: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_6);
-
- FF_3: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_7);
-
- FF_2: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_8);
-
- FF_1: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_9);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- ae_set_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>ae_set_ctr_ci, S0=>open,
- S1=>open);
-
- ae_set_ctr_0: CU2
- port map (CI=>ae_set_ctr_ci, PC0=>ae_setcount_0,
- PC1=>ae_setcount_1, CO=>co0_4, NC0=>iae_setcount_0,
- NC1=>iae_setcount_1);
-
- ae_set_ctr_1: CU2
- port map (CI=>co0_4, PC0=>ae_setcount_2, PC1=>ae_setcount_3,
- CO=>co1_4, NC0=>iae_setcount_2, NC1=>iae_setcount_3);
-
- ae_set_ctr_2: CU2
- port map (CI=>co1_4, PC0=>ae_setcount_4, PC1=>ae_setcount_5,
- CO=>co2_4, NC0=>iae_setcount_4, NC1=>iae_setcount_5);
-
- ae_set_ctr_3: CU2
- port map (CI=>co2_4, PC0=>ae_setcount_6, PC1=>ae_setcount_7,
- CO=>co3_4, NC0=>iae_setcount_6, NC1=>iae_setcount_7);
-
- ae_set_ctr_4: CU2
- port map (CI=>co3_4, PC0=>ae_setcount_8, PC1=>ae_setcount_9,
- CO=>co4_2, NC0=>iae_setcount_8, NC1=>iae_setcount_9);
-
- ae_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- ae_set_cmp_0: AGEB2
- port map (A0=>ae_setcount_0, A1=>ae_setcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci_2, GE=>co0_5);
-
- ae_set_cmp_1: AGEB2
- port map (A0=>ae_setcount_2, A1=>ae_setcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_5, GE=>co1_5);
-
- ae_set_cmp_2: AGEB2
- port map (A0=>ae_setcount_4, A1=>ae_setcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_5, GE=>co2_5);
-
- ae_set_cmp_3: AGEB2
- port map (A0=>ae_setcount_6, A1=>ae_setcount_7,
- B0=>w_g2b_xor_cluster_0, B1=>wcount_r7, CI=>co2_5, GE=>co3_5);
-
- ae_set_cmp_4: AGEB2
- port map (A0=>ae_setcount_8, A1=>ae_set_cmp_set, B0=>wcount_r8,
- B1=>ae_set_cmp_clr, CI=>co3_5, GE=>ae_set_d_c);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- af_set_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open,
- S1=>open);
-
- af_set_ctr_0: CU2
- port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0,
- PC1=>af_setcount_1, CO=>co0_6, NC0=>iaf_setcount_0,
- NC1=>iaf_setcount_1);
-
- af_set_ctr_1: CU2
- port map (CI=>co0_6, PC0=>af_setcount_2, PC1=>af_setcount_3,
- CO=>co1_6, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3);
-
- af_set_ctr_2: CU2
- port map (CI=>co1_6, PC0=>af_setcount_4, PC1=>af_setcount_5,
- CO=>co2_6, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5);
-
- af_set_ctr_3: CU2
- port map (CI=>co2_6, PC0=>af_setcount_6, PC1=>af_setcount_7,
- CO=>co3_6, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7);
-
- af_set_ctr_4: CU2
- port map (CI=>co3_6, PC0=>af_setcount_8, PC1=>af_setcount_9,
- CO=>co4_3, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9);
-
- af_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
-
- af_set_cmp_0: AGEB2
- port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_7);
-
- af_set_cmp_1: AGEB2
- port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_7, GE=>co1_7);
-
- af_set_cmp_2: AGEB2
- port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_7, GE=>co2_7);
-
- af_set_cmp_3: AGEB2
- port map (A0=>af_setcount_6, A1=>af_setcount_7,
- B0=>r_g2b_xor_cluster_0, B1=>rcount_w7, CI=>co2_7, GE=>co3_7);
-
- af_set_cmp_4: AGEB2
- port map (A0=>af_setcount_8, A1=>af_set_cmp_set, B0=>rcount_w8,
- B1=>af_set_cmp_clr, CI=>co3_7, GE=>af_set_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of ecp2m_link_fifo is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:AND2 use entity ecp2m.AND2(V); end for;
- for all:CU2 use entity ecp2m.CU2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:OR2 use entity ecp2m.OR2(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:XOR2 use entity ecp2m.XOR2(V); end for;
- for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
-
-entity etrax_interfacev2 is
- generic (
- RW_SYSTEM : integer range 1 to 2:=1
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DATA_BUS : in std_logic_vector(31 downto 0);
- ETRAX_DATA_BUS_B : inout std_logic_vector(16 downto 0);
- ETRAX_DATA_BUS_B_17 : in std_logic;--_vector(16 downto 0);
- ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
- ETRAX_DATA_BUS_E : inout std_logic_vector(9 downto 8);
- DATA_VALID : in std_logic;
- ETRAX_BUS_BUSY : in std_logic;
- ETRAX_IS_READY_TO_READ : out std_logic;
- TDC_TCK : out std_logic;
- TDC_TDI : out std_logic;
- TDC_TMS : out std_logic;
- TDC_TRST : out std_logic;
- TDC_TDO : in std_logic;
- TDC_RESET : out std_logic;
- EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
- EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
- EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
- EXTERNAL_ACK : out std_logic;
- EXTERNAL_VALID : in std_logic;
- EXTERNAL_MODE : out std_logic_vector(15 downto 0);
- FPGA_REGISTER_00 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0E : out std_logic_vector(31 downto 0);
- LVL2_VALID : in std_logic
- -- DEBUG_REGISTER_OO : out std_logic_vector(31 downto 0)
- );
-end etrax_interfacev2;
-
-architecture etrax_interfacev2 of etrax_interfacev2 is
-
- component edge_to_pulse
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
- end component;
-
- signal etrax_trigger_pulse : std_logic;
- signal rw_operation_finished_pulse : std_logic;
- signal saved_rw_mode : std_logic_vector(15 downto 0);
- signal saved_address : std_logic_vector (31 downto 0);
- signal saved_data : std_logic_vector(31 downto 0);
- signal saved_data_fpga : std_logic_vector(31 downto 0);
-
- signal fpga_register_00_i : std_logic_vector(31 downto 0);
- signal fpga_register_01_i : std_logic_vector(31 downto 0);
- signal fpga_register_02_i : std_logic_vector(31 downto 0);
- signal fpga_register_03_i : std_logic_vector(31 downto 0);
- signal fpga_register_04_i : std_logic_vector(31 downto 0);
- signal fpga_register_05_i : std_logic_vector(31 downto 0);
- signal fpga_register_06_i : std_logic_vector(31 downto 0);
- signal fpga_register_07_i : std_logic_vector(31 downto 0);
- signal fpga_register_08_i : std_logic_vector(31 downto 0);
- signal fpga_register_09_i : std_logic_vector(31 downto 0);
- signal fpga_register_0A_i : std_logic_vector(31 downto 0);
- signal fpga_register_0B_i : std_logic_vector(31 downto 0);
- signal fpga_register_0C_i : std_logic_vector(31 downto 0);
- signal fpga_register_0D_i : std_logic_vector(31 downto 0);
- signal fpga_register_0E_i : std_logic_vector(31 downto 0);
- signal saved_external_data : std_logic_vector(31 downto 0);
- signal etrax_is_ready_to_read_i : std_logic;
- signal lvl2_not_valid_pulse : std_logic;
- signal counter_for_pulses : std_logic_vector(2 downto 0);
- signal internal_reset_i : std_logic := '0';
-
- signal data_from_etrax : std_logic_vector(80 downto 0);
- signal etrax_std_data_counter : std_logic_vector(7 downto 0):=x"00";
- signal enable_transmition : std_logic :='1';
- signal etrax_strobe : std_logic;
- signal data_to_etrax : std_logic_vector(31 downto 0);
- signal reset_counter : std_logic_vector(15 downto 0) := x"0000";
- signal external_reset_counter : std_logic_vector(31 downto 0);
- signal en_trigg_to_etrax : std_logic;
- signal busy_dma_counter : std_logic_vector(3 downto 0);
- signal busy_dma : std_logic;
- signal etrax_busy_end_pulse : std_logic;
- signal not_etrax_busy : std_logic;
- signal data_valid_synch : std_logic;
- signal send_data : std_logic;
- signal data_bus_reg : std_logic_vector(31 downto 0);
- constant INTERFACE_FOR_TRANSFER : integer := 2; --1 DMA, 2 no DMA
- signal readout_lvl2_fifo_to_long :std_logic;
- signal readout_lvl2_fifo_to_long_synch :std_logic;
- signal readout_lvl2_fifo :std_logic;
- signal etrax_busy_start : std_logic;
- signal data_valid_start_pulse : std_logic;
- signal data_valid_end_pulse : std_logic;
- signal data_valid_not : std_logic;
- signal etrax_busy_end : std_logic;
- signal write_to_dma : std_logic;
- signal write_to_dma_synch : std_logic;
- signal word16_counter : std_logic_vector(7 downto 0);
- signal write_to_dma_synch_synch : std_logic;
-begin
-
-
--------------------------------------------------------------------------------
--- transmition for reading, writing fpga registers, dsp, sdram , addon . . .
--------------------------------------------------------------------------------
-
- TRB_SYSTEM : if RW_SYSTEM = 1 generate
- ETRAX_DATA_BUS_C(17) <= 'Z';
- STROBE_PULSER : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => ETRAX_DATA_BUS_C(17),
- pulse => etrax_strobe);
-
- SAVE_ETRAX_DATA : process (CLK, RESET)
- variable etrax_data_counter : integer := 0;
- begin
- if rising_edge(CLK)then
- if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') then
- etrax_data_counter := 0;
- data_from_etrax <= (others => '0');
- ETRAX_DATA_BUS_C(16) <= 'Z';
- enable_transmition <= '1';
- etrax_std_data_counter <= x"00";
- elsif etrax_strobe = '1' and etrax_std_data_counter < 81 then -- and etrax_data_counter < 81 and etrax_data_counter > 0 then
- data_from_etrax(etrax_data_counter) <= ETRAX_DATA_BUS_C(16);
- etrax_data_counter := etrax_data_counter + 1;
- ETRAX_DATA_BUS_C(16) <= 'Z';
- enable_transmition <= '0';
- etrax_std_data_counter <= etrax_std_data_counter + 1;
- elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then
- data_from_etrax <= data_from_etrax;
- ETRAX_DATA_BUS_C(16) <= data_to_etrax(0);
- etrax_data_counter := etrax_data_counter + 1;
- etrax_std_data_counter <= etrax_std_data_counter + 1;
- enable_transmition <= '0';
- elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then
- data_from_etrax <= data_from_etrax;
- ETRAX_DATA_BUS_C(16) <= data_to_etrax((etrax_data_counter-81) mod 32);
- etrax_data_counter := etrax_data_counter + 1;
- etrax_std_data_counter <= etrax_std_data_counter + 1;
- enable_transmition <= '0';
- end if;
- end if;
- end process SAVE_ETRAX_DATA;
- end generate TRB_SYSTEM;
- -- we should add one state to wait for the data from external device (valid
- -- pulse- > one long puls on the data bus !)
- ADDON_SYSTEM : if RW_SYSTEM = 2 generate
- ETRAX_DATA_BUS_E(8) <= 'Z';
- STROBE_PULSER : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => ETRAX_DATA_BUS_E(9),--
- pulse => etrax_strobe);
-
- SAVE_ETRAX_DATA : process (CLK, RESET)
- variable etrax_data_counter : integer := 0;
- begin
- if rising_edge(CLK)then
- if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') then
- etrax_data_counter := 0;
- data_from_etrax <= (others => '0');
- ETRAX_DATA_BUS_E(8) <= 'Z';
- enable_transmition <= '1';
- etrax_std_data_counter <= x"00";
- elsif etrax_strobe = '1' and etrax_std_data_counter < 81 then -- and etrax_data_counter < 81 and etrax_data_counter > 0 then
- data_from_etrax(etrax_data_counter) <= ETRAX_DATA_BUS_E(8);
- etrax_data_counter := etrax_data_counter + 1;
- ETRAX_DATA_BUS_E(8) <= 'Z';
- enable_transmition <= '0';
- etrax_std_data_counter <= etrax_std_data_counter + 1;
- elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then
- data_from_etrax <= data_from_etrax;
- ETRAX_DATA_BUS_E(8) <= data_to_etrax(0);
- etrax_data_counter := etrax_data_counter + 1;
- etrax_std_data_counter <= etrax_std_data_counter + 1;
- enable_transmition <= '0';
- elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then
- data_from_etrax <= data_from_etrax;
- ETRAX_DATA_BUS_E(8) <= data_to_etrax( (etrax_data_counter-81) mod 32);
- etrax_data_counter := etrax_data_counter + 1;
- etrax_std_data_counter <= etrax_std_data_counter + 1;
- enable_transmition <= '0';
- end if;
- end if;
- end process SAVE_ETRAX_DATA;
- end generate ADDON_SYSTEM;
-
- data_to_etrax <= saved_data_fpga when saved_rw_mode(7 downto 0) = x"00" else saved_external_data;
- RW_FINISHED_PULSER : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => EXTERNAL_VALID,
- pulse => rw_operation_finished_pulse);
- --for reading only 1us for responce for any external device !!! - ask RADEK
- --abut timing
- REGISTER_ETRAX_BUS: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if rw_operation_finished_pulse = '1' then
- saved_external_data <= EXTERNAL_DATA_IN;
- else
- saved_external_data <= saved_external_data;
- end if;
- end if;
- end process REGISTER_ETRAX_BUS;
- EXTERNAL_ADDRESS <= saved_address;
- EXTERNAL_MODE <= saved_rw_mode(15 downto 0);
- EXTERNAL_DATA_OUT <= saved_data;
- EXTERNAL_ACK <= '1' when etrax_std_data_counter = 80 else '0';
-
- CLOCK_SAVED_DATA: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- saved_rw_mode <= (others => '0');
- saved_address <= (others => '0');
- saved_data <= (others => '0');
- else
- saved_rw_mode <= data_from_etrax(15 downto 0);
- saved_address <= data_from_etrax(47 downto 16);
- saved_data <= data_from_etrax(79 downto 48);
- end if;
- end if;
- end process CLOCK_SAVED_DATA;
-
- REGISTERS: process (CLK)
- begin
- if rising_edge(CLK) then
--- if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
- fpga_register_01_i <= FPGA_REGISTER_01;
- fpga_register_02_i <= FPGA_REGISTER_02;
- fpga_register_03_i <= FPGA_REGISTER_03;
- fpga_register_04_i <= FPGA_REGISTER_04;
- fpga_register_05_i <= FPGA_REGISTER_05;
- FPGA_REGISTER_06 <= fpga_register_06_i; --this used for TDCjtag enable(0)
- FPGA_REGISTER_07 <= fpga_register_07_i;
- fpga_register_08_i <= FPGA_REGISTER_08;
- fpga_register_09_i <= FPGA_REGISTER_09;
- fpga_register_0A_i <= FPGA_REGISTER_0A;
- fpga_register_0B_i <= FPGA_REGISTER_0B;
- fpga_register_0c_i <= FPGA_REGISTER_0C;
- fpga_register_0d_i <= FPGA_REGISTER_0D;
- FPGA_REGISTER_0E <= fpga_register_0e_i;
- end if;
- end process REGISTERS;
-
- DATA_SOURCE_SELECT : process (CLK,RESET,saved_rw_mode,saved_address)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then--(ETRAX_DATA_BUS_C(16) = '1' and ETRAX_DATA_BUS_C(17) = '1') then
- fpga_register_06_i <= x"00000000";
- fpga_register_07_i <= x"00000000";
- fpga_register_0e_i <= x"00000000";
- else
- case saved_rw_mode(7 downto 0) is
- when "00000000" =>
- if saved_rw_mode(15) = '1' then
- case saved_address(31 downto 0) is
- when x"00000000" => saved_data_fpga <= fpga_register_00_i;
- when x"00000001" => saved_data_fpga <= fpga_register_01_i;
- when x"00000002" => saved_data_fpga <= fpga_register_02_i;
- when x"00000003" => saved_data_fpga <= fpga_register_03_i;
- when x"00000004" => saved_data_fpga <= fpga_register_04_i;
- when x"00000005" => saved_data_fpga <= fpga_register_05_i;
- when x"00000006" => saved_data_fpga <= fpga_register_06_i;
- when x"00000007" => saved_data_fpga <= fpga_register_07_i;
- when x"00000008" => saved_data_fpga <= fpga_register_08_i;
- when x"00000009" => saved_data_fpga <= fpga_register_09_i;
- when x"0000000A" => saved_data_fpga <= fpga_register_0A_i;
- when x"0000000B" => saved_data_fpga <= fpga_register_0B_i;
- when x"0000000C" => saved_data_fpga <= fpga_register_0C_i;
- when x"0000000D" => saved_data_fpga <= fpga_register_0D_i;
- when x"0000000E" => saved_data_fpga <= fpga_register_0E_i;
- when others => saved_data_fpga <= x"deadface";
- end case;
- elsif saved_rw_mode(15) = '0' and etrax_std_data_counter = 80 then
- case saved_address(31 downto 0) is
- when x"00000006" => fpga_register_06_i <= saved_data;
- when x"00000007" => fpga_register_07_i <= saved_data;
- when x"0000000e" => fpga_register_0e_i <= saved_data;
- when others => null;
- end case;
- end if;
- when "00000001" => --DSP write read
- saved_data_fpga <= saved_external_data;
- when x"02" => --sdram
- saved_data_fpga <= saved_external_data;
- when x"03" => --ADDON board write read
- saved_data_fpga <= saved_external_data;
- when others =>
- saved_data_fpga <= x"deadface";
- end case;
- end if;
- end if;
- end process DATA_SOURCE_SELECT;
-
--------------------------------------------------------------------------------
--- data transmitio fpga -> etrax
--------------------------------------------------------------------------------
---DMA
- DMA_INTERFACE: if INTERFACE_FOR_TRANSFER=1 generate
-
- REG_DATA_TO_ETRAXa:process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- data_bus_reg <= (others => '0');
- write_to_dma_synch <= '0';
- write_to_dma_synch_synch <= '0';
- else
- data_bus_reg <= DATA_BUS;
- write_to_dma_synch <= readout_lvl2_fifo;--write_to_dma;
- write_to_dma_synch_synch <= write_to_dma_synch;
- end if;
- end if;
- end process REG_DATA_TO_ETRAXa;
- ETRAX_DATA_BUS_B(7 downto 0) <= data_bus_reg(31 downto 24);
--- ETRAX_DATA_BUS_B(6 downto 0) <= data_bus_reg(30 downto 24); --!!!test
- ETRAX_DATA_BUS_B(15 downto 8) <= data_bus_reg(23 downto 16);
- ETRAX_DATA_BUS_C(15 downto 8) <= data_bus_reg(15 downto 8);
- ETRAX_DATA_BUS_C(7 downto 4) <= data_bus_reg(7 downto 4);
-
-
--- ETRAX_DATA_BUS_B(7) <= ETRAX_DATA_BUS_B_17; --for test
-
- TDC_TMS <= ETRAX_DATA_BUS_C(1) when fpga_register_06_i(0) = '1' else '1';
- TDC_TCK <= ETRAX_DATA_BUS_C(2) when fpga_register_06_i(0) = '1' else '1';
- TDC_TDI <= ETRAX_DATA_BUS_C(3) when fpga_register_06_i(0) = '1' else '1';
- ETRAX_DATA_BUS_C(0) <= TDC_TDO when fpga_register_06_i(0) = '1' else data_bus_reg(0);
- ETRAX_DATA_BUS_C(1) <= 'Z' when fpga_register_06_i(0) = '1' else data_bus_reg(1);
- ETRAX_DATA_BUS_C(2) <= 'Z' when fpga_register_06_i(0) = '1' else data_bus_reg(2);
- ETRAX_DATA_BUS_C(3) <= 'Z' when fpga_register_06_i(0) = '1' else data_bus_reg(3);
-
- START_READOUT : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => DATA_VALID,
- pulse => data_valid_start_pulse);
- data_valid_not <= not DATA_VALID;
-
- END_READOUT : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => data_valid_not,
- pulse => data_valid_end_pulse);
-
- ETRAX_BUSY_START_PULSER : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => ETRAX_DATA_BUS_B_17,
- pulse => etrax_busy_start);
-
- not_etrax_busy <= not ETRAX_DATA_BUS_B_17;
-
- ETRAX_BUSY_END_PULSER : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => not_etrax_busy,
- pulse => etrax_busy_end);
-
- COUNTER_FOR_READOUT: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- word16_counter <= x"FF";
- elsif (data_valid_start_pulse = '1') or (etrax_busy_end = '1' and DATA_VALID = '1') then
- word16_counter <= x"00";
- elsif word16_counter < x"1e" then
- word16_counter <= word16_counter + 1;
- else
- word16_counter <= word16_counter;
- end if;
- end if;
- end process COUNTER_FOR_READOUT;
-
- READOUT_LVL2_FIFO_PROC: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' or data_valid_end_pulse = '1' or word16_counter = x"1e" then
- readout_lvl2_fifo <= '0';
- elsif word16_counter < x"1e" then
- readout_lvl2_fifo <= word16_counter(0);
- end if;
- end if;
- end process READOUT_LVL2_FIFO_PROC;
-
- WRITE_TO_ETRAX_DMA: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' or word16_counter = x"1e" then
- write_to_dma <= '0';
- elsif word16_counter = x"00" then
- write_to_dma <= '1';
- end if;
- end if;
- end process WRITE_TO_ETRAX_DMA;
-
- etrax_is_ready_to_read_i <= (data_valid_start_pulse or readout_lvl2_fifo) and DATA_VALID;
- ETRAX_IS_READY_TO_READ <= readout_lvl2_fifo;
- ETRAX_DATA_BUS_B(16) <= write_to_dma_synch_synch;--(not CLK) and (write_to_dma_synch_synch);
-
- end generate DMA_INTERFACE;
-
-
--- NO DMA
- WITHOUT_DMA_ETRAX_INTERFACE: if INTERFACE_FOR_TRANSFER = 2 generate
-
- ETRAX_READY_PULSE : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => ETRAX_DATA_BUS_B_17,
- pulse => etrax_is_ready_to_read_i);
-
- MAKE_PULSES: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- counter_for_pulses <= "000";
- else
- counter_for_pulses <= counter_for_pulses + 1;
- end if;
- end if;
- end process make_pulses;
-
- LVL2_NOT_VALID_READY_PULSE : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => counter_for_pulses(2),
- pulse => lvl2_not_valid_pulse);
-
- ETRAX_IS_READY_TO_READ <= DATA_VALID and ((etrax_is_ready_to_read_i and (not LVL2_VALID)) or (lvl2_not_valid_pulse and LVL2_VALID));
-
- TDC_TMS <= ETRAX_DATA_BUS_C(1) when fpga_register_06_i(0) = '1' else '1';
- TDC_TCK <= ETRAX_DATA_BUS_C(2) when fpga_register_06_i(0) = '1' else '1';
- TDC_TDI <= ETRAX_DATA_BUS_C(3) when fpga_register_06_i(0) = '1' else '1';
- ETRAX_DATA_BUS_C(0) <= TDC_TDO when fpga_register_06_i(0) = '1' else DATA_BUS(16);
- ETRAX_DATA_BUS_C(1) <= 'Z' when fpga_register_06_i(0) = '1' else DATA_BUS(17);
- ETRAX_DATA_BUS_C(2) <= 'Z' when fpga_register_06_i(0) = '1' else DATA_BUS(18);
- ETRAX_DATA_BUS_C(3) <= 'Z' when fpga_register_06_i(0) = '1' else DATA_BUS(19);
- ETRAX_DATA_BUS_C(15 downto 4) <= DATA_BUS(31 downto 20);
- ETRAX_DATA_BUS_B(15 downto 0) <= DATA_BUS(15 downto 0);
- ETRAX_DATA_BUS_B(16) <= DATA_VALID and (not LVL2_VALID);
-
-
- REG_DATA_TO_ETRAX: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- data_bus_reg <= (others => '0');
- else
- data_bus_reg <= DATA_BUS;
- end if;
- end if;
- end process REG_DATA_TO_ETRAX;
-end generate WITHOUT_DMA_ETRAX_INTERFACE;
-
-end etrax_interfacev2;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_arith.all;
-use IEEE.STD_LOGIC_unsigned.all;
-
-
-entity f_divider is
-
- generic(
- cnt : integer := 4000 -- Der Teiler teilt durch "cnt" , wenn Test = 0 ist. --
- );
-
- port (
- clk : in std_logic;
- ena_cnt : in std_logic;
- f_div : out std_logic
- );
-
-end f_divider;
-
-
-
-architecture arch_f_divider of f_divider is
-
- function How_many_Bits (int : integer) return integer is
- variable i, tmp : integer;
- begin
- tmp := int;
- i := 0;
- while tmp > 0 loop
- tmp := tmp / 2;
- i := i + 1;
- end loop;
- return i;
- end How_many_bits;
-
-
- --+
- --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können? |
- --+
- constant c_counter_width : integer := How_many_Bits(cnt - 2);
-
- --+ ---------------------------------------------------------------------------------------------+
- --| Des Zähler "s_counter" muss ein Bit breiter definiert werden, als zur Abarbeitung des "cnt" |
- --| nötig wäre. Dieses Bit wird beim Zählerunterlauf '1'. Der Zählerablauf wird dadurch ohne |
- --| Komparator erkannt, er steht als getaktetes physikalisches Signal zur Verfügung. |
- --+ ---------------------------------------------------------------------------------------------+
- signal s_counter : std_logic_vector(c_counter_width downto 0) := conv_std_logic_vector(0, c_counter_width+1);
-
- --+ ---------------------------------------------------------------------------------------------+
- --| Teiler muss mit einen um -2 geringeren Wert geladen werden. Da das Neuladen erst durch dem |
- --| Unterlauf Zählers erfolgt. D.h. die Null und minus Eins werden mitgezählt. |
- --+ ---------------------------------------------------------------------------------------------+
- constant c_ld_value : integer := cnt - 2;
-
-begin
- p_f_divider : process (clk)
- begin
- if clk'event and clk = '1' then
- if s_counter(s_counter'high) = '1' then -- Bei underflow wird neu geladen --
- s_counter <= conv_std_logic_vector(c_ld_value, s_counter'length);
- elsif ena_cnt = '1' then
- if s_counter(s_counter'high) = '0' then -- Kein underflow erreicht weiter --
- s_counter <= s_counter - 1; -- subtrahieren. --
- end if;
- end if;
- end if;
- end process p_f_divider;
-
- f_div <= s_counter(s_counter'high);
-
-end arch_f_divider;
-
-
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-
---library synplify;
---use synplify.attributes.all;
-
-
-entity edge_to_pulse is
-
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
-
-end edge_to_pulse;
-
-architecture arch_edge_to_pulse of edge_to_pulse is
- signal signal_sync : std_logic;
- signal old_sync : std_logic;
- type state is (idle, high, wait_for_low); -- state
- signal current_state, next_state : state;
-
-begin -- arch_edge_to_pulse
-
- fsm : process (clock)
- begin -- process fsm
- if rising_edge(clock) then -- rising clock edge
- if en_clk = '1' then
- current_state <= next_state;
- signal_sync <= signal_in;
- end if;
- end if;
- end process fsm;
-
-
- fsm_comb : process (current_state, signal_sync)
- begin -- process fsm_comb
- case current_state is
- when idle =>
- pulse <= '0';
- if signal_sync = '1' then
- next_state <= high;
- else
- next_state <= idle;
- end if;
- when high =>
- pulse <= '1';
- next_state <= wait_for_low;
--- when wait_for_low_1 =>
--- pulse <= '1';
--- next_state <= wait_for_low;
- when wait_for_low =>
- pulse <= '0';
- if signal_sync = '0' then
- next_state <= idle;
- else
- next_state <= wait_for_low;
- end if;
- when others =>
- pulse <= '0';
- next_state <= idle;
- end case;
- end process fsm_comb;
-
-
-end arch_edge_to_pulse;
-
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package support is
-
- component f_divider
- generic (
- cnt : integer);
- port (
- clk : in std_logic;
- ena_cnt : in std_logic;
- f_div : out std_logic);
- end component;
-
- component edge_to_pulse
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
- end component;
-
-
-end support;
-
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
-library ieee;
-library work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.all;
-use work.trb_net_std.all;
-use work.trb_net16_hub_func.all;
-
-entity flexi_PCS_channel_synch is
-
- port (
- SYSTEM_CLK : in std_logic;
- TX_CLK : in std_logic;
- RX_CLK : in std_logic;
- RESET : in std_logic;
- RXD : in std_logic_vector(15 downto 0);
- RXD_SYNCH : out std_logic_vector(15 downto 0);
- RX_K : in std_logic_vector(1 downto 0);
- RX_RST : out std_logic;
- CV : in std_logic_vector(1 downto 0);
- TXD : in std_logic_vector(15 downto 0);
- TXD_SYNCH : out std_logic_vector(15 downto 0);
- TX_K : out std_logic_vector(1 downto 0);
- DATA_VALID_IN : in std_logic;
- DATA_VALID_OUT : out std_logic;
- FLEXI_PCS_STATUS : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_ERROR_OUT : out std_logic_vector(2 downto 0);
- MED_READ_IN : in std_logic
- );
-
-end flexi_PCS_channel_synch;
-architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is
- component flexi_PCS_fifo_EBR
- port (
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(17 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostEmpty : out std_logic;
- AlmostFull : out std_logic);
- end component;
-
- component ecp2m_link_fifo
- port (
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(17 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostEmpty : out std_logic;
- AlmostFull : out std_logic);
- end component;
-
- component simpleupcounter_32bit
- port (
- QOUT : out std_logic_vector(31 downto 0);
- UP : in std_logic;
- CLK : in std_logic;
- CLR : in std_logic);
- end component;
- component simpleupcounter_16bit
- port (
- QOUT : out std_logic_vector(15 downto 0);
- UP : in std_logic;
- CLK : in std_logic;
- CLR : in std_logic);
- end component;
- component simpleupcounter_8bit
- port (
- QOUT : out std_logic_vector(15 downto 0);
- UP : in std_logic;
- CLK : in std_logic;
- CLR : in std_logic);
- end component;
- component edge_to_pulse
- port (
- CLOCK : in std_logic;
- EN_CLK : in std_logic;
- SIGNAL_IN : in std_logic;
- PULSE : out std_logic);
- end component;
- type SYNCH_MACHINE is (IDLE, SYNCH_START, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, NORMAL_OPERATION_1, NORMAL_OPERATION_2);
- signal SYNCH_CURRENT, SYNCH_NEXT : SYNCH_MACHINE;
- signal fsm_debug_register : std_logic_vector(2 downto 0);
- signal resync_counter_up :std_logic;
- signal resync_counter_clr :std_logic;
- signal resync_counter : std_logic_vector(31 downto 0);
- signal cv_i : std_logic_vector(1 downto 0);
- signal cv_or : std_logic;
- signal cv_counter : std_logic_vector(15 downto 0);
- signal rx_rst_i : std_logic;
- signal rxd_synch_i : std_logic_vector(15 downto 0);
- signal rxd_synch_synch_i : std_logic_vector(15 downto 0);
- signal rx_k_synch_i : std_logic_vector(1 downto 0);
- signal rx_k_synch_synch_i : std_logic_vector(1 downto 0);
- signal fifo_data_in : std_logic_vector(17 downto 0);
- signal fifo_data_out : std_logic_vector(17 downto 0);
- signal fifo_wr_en : std_logic;
- signal fifo_rd_en : std_logic;
- signal fifo_rst : std_logic;
- signal fifo_full : std_logic;
- signal fifo_almost_full : std_logic;
- signal fifo_empty : std_logic;
- signal fifo_almost_empty : std_logic;
- signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal start_counter_1 : std_logic_vector(31 downto 0);
- signal start_counter_2 : std_logic_vector(31 downto 0);
- signal fifo_rd_pulse : std_logic;
- signal fifo_rd_cnt : std_logic_vector(15 downto 0);
- signal fifo_wr_cnt : std_logic_vector(15 downto 0);
- signal not_fifo_empty : std_logic;
- signal fifo_rd_en_dv : std_logic;
- -----------------------------------------------------------------------------
- -- fifo to optical link
- -----------------------------------------------------------------------------
- signal data_valid_out_i : std_logic;
- signal fifo_opt_not_empty : std_logic;
- signal fifo_opt_empty : std_logic;
- signal fifo_opt_empty_synch : std_logic;
- signal data_opt_in : std_logic_vector(17 downto 0);
- signal txd_fifo_out : std_logic_vector(17 downto 0);
- signal fifo_opt_full : std_logic;
- signal fifo_opt_almost_empty : std_logic;
- signal fifo_opt_almost_full : std_logic;
- signal not_clk : std_logic;
- signal txd_synch_i : std_logic_vector(15 downto 0);
- signal tx_k_i : std_logic;
- signal fifo_opt_empty_synch_synch : std_logic;
- signal fifo_rd_en_hub : std_logic;
- constant SYSTEM : Integer := 2;
-begin
- SEND_ERROR: process (SYSTEM_CLK, RESET,SYNCH_CURRENT)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- MED_ERROR_OUT <= ERROR_NC;
- elsif SYNCH_CURRENT = NORMAL_OPERATION_1 or SYNCH_CURRENT = NORMAL_OPERATION_2 then
- MED_ERROR_OUT <= ERROR_OK;
- elsif SYNCH_CURRENT = WAIT_1 or SYNCH_CURRENT = WAIT_2 then
- MED_ERROR_OUT <= ERROR_WAIT;
- else
- MED_ERROR_OUT <= ERROR_NC;
- end if;
- end if;
- end process SEND_ERROR;
- PACKET_NUM: process (SYSTEM_CLK, RESET,fifo_rd_en)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- packet_number <= "011";
- elsif fifo_rd_en = '1' then
- if packet_number = c_max_word_number then
- packet_number <= "000";
- else
- packet_number <= packet_number + 1;
- end if;
- end if;
- end if;
- end process PACKET_NUM;
- MED_PACKET_NUM_OUT <= packet_number;
- LINK_STATUS : process (SYSTEM_CLK,RESET)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- RX_RST <= '0';
- FLEXI_PCS_STATUS(15 downto 0) <= (others => '0');
- else
- RX_RST <= rx_rst_i;
- FLEXI_PCS_STATUS(2 downto 0) <= fsm_debug_register;
- FLEXI_PCS_STATUS(7 downto 3) <= fifo_empty & fifo_full & fifo_opt_empty & fifo_opt_full & DATA_VALID_IN;--fifo_almost_full &
- --'0';
- FLEXI_PCS_STATUS(15 downto 8) <= fifo_wr_cnt(3 downto 0) & fifo_rd_cnt(3 downto 0);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0);
--- FLEXI_PCS_STATUS(11 downto 8) <= fifo_wr_cnt(4 downto 1);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0);
- end if;
- end if;
- end process LINK_STATUS;
- -----------------------------------------------------------------------------
- -- data from hub to link
- -----------------------------------------------------------------------------
- data_opt_in <= "00" & TXD;
- SYSTEM_SCM_MEMa: if SYSTEM=1 generate
- CHANNEL_FIFO_TO_OPT: flexi_PCS_fifo_EBR
- port map (
- Data => data_opt_in,
- WrClock => SYSTEM_CLK,
- RdClock => TX_CLK,
- WrEn => DATA_VALID_IN,
- RdEn => fifo_opt_not_empty,
- Reset => fifo_rst,
- RPReset => fifo_rst,
- Q => txd_fifo_out,
- Empty => fifo_opt_empty,
- Full => fifo_opt_full,
- AlmostEmpty => fifo_opt_almost_empty,
- AlmostFull => fifo_opt_almost_full
- );
- end generate SYSTEM_SCM_MEMa;
-
- SYSTEM_ECP2_MEMa: if SYSTEM=2 generate
- CHANNEL_FIFO_TO_OPT: ecp2m_link_fifo
- port map (
- Data => data_opt_in,
- WrClock => SYSTEM_CLK,
- RdClock => TX_CLK,
- WrEn => DATA_VALID_IN,
- RdEn => fifo_opt_not_empty,
- Reset => fifo_rst,
- RPReset => fifo_rst,
- Q => txd_fifo_out,
- Empty => fifo_opt_empty,
- Full => fifo_opt_full,
- AlmostEmpty => fifo_opt_almost_empty,
- AlmostFull => fifo_opt_almost_full
- );
- end generate SYSTEM_ECP2_MEMa;
-
-
- DATA_SEND_TO_LINK: process (TX_CLK, RESET, DATA_VALID_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch)
- begin
- if rising_edge(TX_CLK) then --falling ???
- if RESET = '1' then
- tx_k_i <= '0';
- txd_synch_i <= (others => '0');
- fifo_opt_empty_synch <= fifo_opt_empty;
- fifo_opt_empty_synch_synch <= fifo_opt_empty_synch;
- fifo_opt_not_empty <= not fifo_opt_empty;
- elsif fifo_opt_empty_synch = '0' and fifo_opt_empty_synch_synch ='0' then
- tx_k_i <= '0';
- txd_synch_i <= txd_fifo_out(15 downto 0);
- fifo_opt_empty_synch <= fifo_opt_empty;
- fifo_opt_empty_synch_synch <= fifo_opt_empty_synch;
- fifo_opt_not_empty <= not fifo_opt_empty;
- else
- tx_k_i <= '1';
- txd_synch_i <= x"c5bc";
- fifo_opt_empty_synch <= fifo_opt_empty;
- fifo_opt_empty_synch_synch <= fifo_opt_empty_synch;
- fifo_opt_not_empty <= not fifo_opt_empty;
- end if;
- end if;
- end process DATA_SEND_TO_LINK;
- SYNCH_DATA: process (TX_CLK)
- begin
- if rising_edge(TX_CLK) then
- TXD_SYNCH <= txd_synch_i;
- TX_K(0) <= tx_k_i;
- TX_K(1) <= '0';
- end if;
- end process SYNCH_DATA;
--- TX_FORCE_DISP(1) <= '0';
- -----------------------------------------------------------------------------
- -- from link to hub
- -----------------------------------------------------------------------------
- SYSTEM_SCM_MEMb: if SYSTEM=1 generate
- CHANNEL_FIFO_TO_FPGA: flexi_PCS_fifo_EBR
- port map (
- Data => fifo_data_in,
- WrClock => RX_CLK,
- RdClock => SYSTEM_CLK,
- WrEn => fifo_wr_en,
- RdEn => fifo_rd_en,
- Reset => fifo_rst,
- RPReset => fifo_rst,
- Q => fifo_data_out,
- Empty => fifo_empty,
- Full => fifo_full,
- AlmostEmpty => fifo_almost_empty,
- AlmostFull => fifo_almost_full
- );
- end generate SYSTEM_SCM_MEMb;
-
- SYSTEM_ECP2_MEMb: if SYSTEM=2 generate
- CHANNEL_FIFO_TO_FPGA: ecp2m_link_fifo
- port map (
- Data => fifo_data_in,
- WrClock => RX_CLK,
- RdClock => SYSTEM_CLK,
- WrEn => fifo_wr_en,
- RdEn => fifo_rd_en,
- Reset => fifo_rst,
- RPReset => fifo_rst,
- Q => fifo_data_out,
- Empty => fifo_empty,
- Full => fifo_full,
- AlmostEmpty => fifo_almost_empty,
- AlmostFull => fifo_almost_full
- );
- end generate SYSTEM_ECP2_MEMb;
-
- not_fifo_empty <= not fifo_empty;
- RD_FIFO_PULSE: edge_to_pulse
- port map (
- clock => SYSTEM_CLK,
- en_clk => '1',
- signal_in => not_fifo_empty,
- pulse => fifo_rd_pulse);
- READING_THE_FIFO: process (SYSTEM_CLK, RESET, fifo_rd_pulse,MED_READ_IN,fifo_empty,data_valid_out_i)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- data_valid_out_i <= '0';
- fifo_rd_en_hub <= '0';
- elsif fifo_rd_pulse = '1' then
- data_valid_out_i <= '1';
- fifo_rd_en_hub <= MED_READ_IN;
- elsif MED_READ_IN = '1' and fifo_empty = '1' and data_valid_out_i = '1' then
- data_valid_out_i <= '0';
- fifo_rd_en_hub <= '0';
- elsif data_valid_out_i = '1' and fifo_empty = '0' then
- data_valid_out_i <= '1';
- fifo_rd_en_hub <= MED_READ_IN;
- end if;
- end if;
- end process READING_THE_FIFO;
- DATA_VALID_OUT <= data_valid_out_i;
- fifo_rd_en <= (fifo_rd_en_hub and (not fifo_empty)) or fifo_rd_pulse;
- RXD_SYNCH <= fifo_data_out(15 downto 0);
--- DATA_VALID_OUT <= fifo_data_out(16) and (not fifo_empty);
- VALID_DATA_SEND_TO_API: process (RX_CLK, RESET)
- begin
- if rising_edge(RX_CLK) then
- if RESET = '1' then
- rxd_synch_i <= (others => '0');
- rxd_synch_synch_i <= rxd_synch_i;
- rx_k_synch_i <= "00";
- rx_k_synch_synch_i <= rx_k_synch_i;
- else-- RX_K(0) = '1' then
- rxd_synch_i <= RXD;
- rxd_synch_synch_i <= rxd_synch_i;
- rx_k_synch_i <= RX_K;
- rx_k_synch_synch_i <= rx_k_synch_i;
- end if;
- end if;
- end process VALID_DATA_SEND_TO_API;
- SHIFT_OR_NOT_DATA_IN: process (RX_CLK, RESET, SYNCH_CURRENT)
- begin
- if rising_edge(RX_CLK) then
- if RESET = '1' then
- fifo_data_in <= (others => '0');
- elsif SYNCH_CURRENT = NORMAL_OPERATION_2 then
- fifo_data_in <= '0' & (not RX_K(0)) & RXD;
- elsif SYNCH_CURRENT = NORMAL_OPERATION_1 then
- fifo_data_in <= '0' & (not RX_K(1)) & rxd_synch_i(7 downto 0) & RXD(15 downto 8);
- else
- fifo_data_in <= (others => '0');
- end if;
- end if;
- end process SHIFT_OR_NOT_DATA_IN;
-
--- SYNCH_CLOCK : process (RX_CLK, RESET)
- SYNCH_CLOCK : process (SYSTEM_CLK, RESET)
- begin
- if rising_edge (SYSTEM_CLK) then
- if RESET = '1' then
- SYNCH_CURRENT <= IDLE; --no_sim--
---sim-- SYNCH_CURRENT <= NORMAL_OPERATION_2;
- cv_i <= (others => '0');
- else
- SYNCH_CURRENT <= SYNCH_NEXT;
- cv_i <= CV;
- end if;
- end if;
- end process SYNCH_CLOCK;
- SYNCH_FSM : process( SYNCH_CURRENT, rxd_synch_i, resync_counter, cv_i,RX_K, MED_READ_IN ,fifo_rd_pulse, fifo_rd_en_hub,rx_k_synch_i)
- begin
- case (SYNCH_CURRENT) is
- when IDLE =>
- fifo_rst <= '1';
- fifo_wr_en <= '0';
- fsm_debug_register(2 downto 0) <= "001";
- rx_rst_i <= '0';
- resync_counter_up <= '0';
- resync_counter_clr <= '1';
--- if rxd_synch_i = x"bc50" then
--- SYNCH_NEXT <= WAIT_1;--NORMAL_OPERATION_1;--WAIT_1;
- --els
- if rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc" then
- SYNCH_NEXT <= WAIT_2;--NORMAL_OPERATION_2; --WAIT_2;
- else
- SYNCH_NEXT <= RESYNC1;
- end if;
- when RESYNC1 =>
- fifo_rst <= '0';
- fifo_wr_en <= '0';
- fsm_debug_register(2 downto 0) <= "010";
- rx_rst_i <= '1';
- resync_counter_up <= '1';
- resync_counter_clr <= '0';
- if resync_counter(8) = '1' then
- SYNCH_NEXT <= RESYNC2;
- else
- SYNCH_NEXT <= RESYNC1;
- end if;
- when RESYNC2 =>
- fifo_rst <= '0';
- fifo_wr_en <= '0';
- fsm_debug_register(2 downto 0) <= "010";
- rx_rst_i <= '0';
- resync_counter_up <= '1';
- resync_counter_clr <= '0';
- if resync_counter(16) = '1' then --at least 400us
- SYNCH_NEXT <= RESYNC3;
- else
- SYNCH_NEXT <= RESYNC2;
- end if;
-
- when RESYNC3 =>
- fifo_rst <= '0';
- fifo_wr_en <= '0';
- fsm_debug_register(2 downto 0) <= "010";
- rx_rst_i <= '0';
- resync_counter_up <= '0';
- resync_counter_clr <= '1';
--- if rxd_synch_i = x"bc50" and rx_k_synch_i(1) = '1' then
--- SYNCH_NEXT <= WAIT_1;--NORMAL_OPERATION_1;
- --els
- if (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' then
- SYNCH_NEXT <= WAIT_2;--no_sim--
---sim-- SYNCH_NEXT <= NORMAL_OPERATION_2;
- else
- SYNCH_NEXT <= IDLE;
- end if;
- when WAIT_1 =>
- fifo_rst <= '0';
- rx_rst_i <= '0';
- fifo_wr_en <= '0';
- fsm_debug_register(2 downto 0) <= "011";
- resync_counter_up <= '1';
- resync_counter_clr <= '0';
- if resync_counter(27) = '1' and (rxd_synch_i = x"bc50" or rxd_synch_i = x"bcc5") and rx_k_synch_i(1) = '1' then
- SYNCH_NEXT <= NORMAL_OPERATION_1;
- elsif resync_counter(26) = '1' and (rxd_synch_i /= x"bc50" or rx_k_synch_i(1) = '0') then
- SYNCH_NEXT <= RESYNC1;
- else
- SYNCH_NEXT <= WAIT_1;
- end if;
- when WAIT_2 =>
- fifo_rst <= '0';
- fifo_wr_en <= '0';
- rx_rst_i <= '0';
- fsm_debug_register(2 downto 0) <= "011";
- resync_counter_up <= '1';
- resync_counter_clr <= '0';
- if resync_counter(27) = '1' and (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' then
- SYNCH_NEXT <= NORMAL_OPERATION_2;
- elsif resync_counter(26) = '1' and (rxd_synch_i(7 downto 0) /= x"bc" or rx_k_synch_i(0) = '0') then
- SYNCH_NEXT <= RESYNC1;
- else
- SYNCH_NEXT <= WAIT_2;
- end if;
- when NORMAL_OPERATION_1 =>
- fifo_rst <= '0';
- fifo_wr_en <= not rx_k_synch_i(1);
- fsm_debug_register(2 downto 0) <= "110";
- rx_rst_i <= '0';
- resync_counter_up <= '0';
- resync_counter_clr <= '0';
- if cv_i(0) = '1' or cv_i(1) = '1' then
- SYNCH_NEXT <= IDLE;
- else
- SYNCH_NEXT <= NORMAL_OPERATION_1;
- end if;
- when NORMAL_OPERATION_2 =>
- fifo_rst <='0';--no_sim--
---sim-- fifo_rst <=RESET;
- fifo_wr_en <= not rx_k_synch_i(0);
- fsm_debug_register(2 downto 0) <= "111";
- rx_rst_i <= '0';
- resync_counter_up <= '0';
- resync_counter_clr <= '0';
- if cv_i(0) = '1' or cv_i(1) = '1' then
- SYNCH_NEXT <= IDLE;
- else
- SYNCH_NEXT <= NORMAL_OPERATION_2;
- end if;
- when others =>
- fifo_rst <= '0';
- fifo_wr_en <= '0';
- resync_counter_up <= '0';
- resync_counter_clr <= '0';
- fsm_debug_register(2 downto 0) <= "000";
- rx_rst_i <= '0';
- SYNCH_NEXT <= IDLE;
- end case;
- end process SYNCH_FSM;
-
- RESYNC_COUNTER_INST : simpleupcounter_32bit
- port map (
- QOUT => resync_counter,
- UP => resync_counter_up,
- CLK => SYSTEM_CLK,
- CLR => resync_counter_clr);
- cv_or <= cv_i(0) or cv_i(1);
- CV_COUNTER_INST: simpleupcounter_16bit
- port map (
- QOUT => cv_counter,
- UP => cv_or,
- CLK => RX_CLK,
- CLR => RESET);
- WR_COUNTER_INST: simpleupcounter_16bit
- port map (
- QOUT => fifo_wr_cnt,
- UP => fifo_wr_en,
- CLK => SYSTEM_CLK,
- CLR => RESET);
- fifo_rd_en_dv <= fifo_rd_en and fifo_data_out(16) and fifo_empty;
- RD_COUNTER_INST: simpleupcounter_16bit
- port map (
- QOUT => fifo_rd_cnt,
- UP => DATA_VALID_IN,--fifo_rd_en_dv,--fifo_rd_en,
- CLK => SYSTEM_CLK,
- CLR => RESET);
-end flexi_PCS_channel_synch;
---reciving idle for 1ms and start e11o until recive e11o and idle
---write to fifo when rx_k is 1 ?
--- wait for reset
--- wait for pll locked
--- send idles
--- wait 650ms (counter(27) = 1)
--- enable rx
--- wait 650ms (counter(27) = 1)
--- enable tx
--- ready
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
--- Module Version: 4.2
---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n flexi_PCS_fifo_EBR -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -e
-
--- Tue Nov 27 10:58:36 2007
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library SCM;
-use SCM.COMPONENTS.all;
--- synopsys translate_on
-
-entity flexi_PCS_fifo_EBR is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end flexi_PCS_fifo_EBR;
-
-architecture Structure of flexi_PCS_fifo_EBR is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal Empty_int: std_logic;
- signal Full_int: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component FIFO16KA
- -- synopsys translate_off
- generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
- FULLPOINTER : in std_logic_vector(14 downto 0);
- AFPOINTER1 : in std_logic_vector(14 downto 0);
- AEPOINTER1 : in std_logic_vector(14 downto 0);
- AFPOINTER : in std_logic_vector(14 downto 0);
- AEPOINTER : in std_logic_vector(14 downto 0);
- CSDECODE_R : in std_logic_vector(1 downto 0);
- CSDECODE_W : in std_logic_vector(1 downto 0);
- RESETMODE : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- -- synopsys translate_on
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- FULLI: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; EMPTYI: in std_logic;
- CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
- RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
- RST: in std_logic; RPRST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic;
- EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
- FF: out std_logic);
- end component;
- attribute FULLPOINTER1 : string;
- attribute FULLPOINTER : string;
- attribute AFPOINTER1 : string;
- attribute AFPOINTER : string;
- attribute AEPOINTER1 : string;
- attribute AEPOINTER : string;
- attribute RESETMODE : string;
- attribute REGMODE : string;
- attribute CSDECODE_R : string;
- attribute CSDECODE_W : string;
- attribute DATA_WIDTH_R : string;
- attribute DATA_WIDTH_W : string;
- attribute FULLPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111000001";
- attribute FULLPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111100001";
- attribute AFPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101000001";
- attribute AFPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101100001";
- attribute AEPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101111111";
- attribute AEPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101011111";
- attribute RESETMODE of flexi_PCS_fifo_EBR_0_0 : label is "ASYNC";
- attribute REGMODE of flexi_PCS_fifo_EBR_0_0 : label is "NOREG";
- attribute CSDECODE_R of flexi_PCS_fifo_EBR_0_0 : label is "0b11";
- attribute CSDECODE_W of flexi_PCS_fifo_EBR_0_0 : label is "0b11";
- attribute DATA_WIDTH_R of flexi_PCS_fifo_EBR_0_0 : label is "36";
- attribute DATA_WIDTH_W of flexi_PCS_fifo_EBR_0_0 : label is "36";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- flexi_PCS_fifo_EBR_0_0: FIFO16KA
- -- synopsys translate_off
- generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001",
- AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001",
- AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
- CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- -- synopsys translate_on
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
- DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
- DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
- DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
- DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
- EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi,
- WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
- RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
- DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
- DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
- DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0),
- DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
- DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
- DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
- DO33=>Q(15), DO34=>Q(16), DO35=>Q(17), EF=>Empty_int,
- AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int);
-
- Empty <= Empty_int;
- Full <= Full_int;
-end Structure;
-
--- synopsys translate_off
-library SCM;
-configuration Structure_CON of flexi_PCS_fifo_EBR is
- for Structure
- for all:VHI use entity SCM.VHI(V); end for;
- for all:VLO use entity SCM.VLO(V); end for;
- for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
-library ieee;
-library work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.all;
-use work.trb_net_std.all;
-
-entity flexi_PCS_synch is
- generic (
- HOW_MANY_CHANNELS : positive);
- port (
- SYSTEM_CLK : in std_logic;
- CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
- RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- RESET : in std_logic;
- RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
- MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0);
- MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0)
- );
-end flexi_PCS_synch;
-architecture flexi_PCS_synch of flexi_PCS_synch is
- component flexi_PCS_channel_synch
- port (
- SYSTEM_CLK : in std_logic;
- TX_CLK : in std_logic;
- RX_CLK : in std_logic;
- RESET : in std_logic;
- RXD : in std_logic_vector(15 downto 0);
- RXD_SYNCH : out std_logic_vector(15 downto 0);
- RX_K : in std_logic_vector(1 downto 0);
- RX_RST : out std_logic;
- CV : in std_logic_vector(1 downto 0);
- TXD : in std_logic_vector(15 downto 0);
- TXD_SYNCH : out std_logic_vector(15 downto 0);
- TX_K : out std_logic_vector(1 downto 0);
- DATA_VALID_IN : in std_logic;
- DATA_VALID_OUT : out std_logic;
- FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_ERROR_OUT : out std_logic_vector(2 downto 0);
- MED_READ_IN : in std_logic
- );
- end component;
-begin
- CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate
- begin
- MED_READ_OUT <= (others => '1');
-
- SYNCH :flexi_PCS_channel_synch
- port map (
- SYSTEM_CLK => SYSTEM_CLK,
- TX_CLK => CLK(bit_index/4), --4 different channles clk
- RX_CLK => RX_CLK(bit_index),
- RESET => RESET,
- RXD => RXD((bit_index*16+15) downto bit_index*16),
- RXD_SYNCH => MED_DATA_OUT((bit_index*16+15) downto bit_index*16),
- RX_K => RX_K(bit_index*2+1 downto bit_index*2),
- RX_RST => RX_RST(bit_index),
- CV => CV((bit_index*2+1) downto bit_index*2),
- TXD => MED_DATA_IN((bit_index*16+15) downto bit_index*16),
- TXD_SYNCH => TXD_SYNCH((bit_index*16+15) downto bit_index*16),
- TX_K => TX_K(bit_index*2+1 downto bit_index*2),
- DATA_VALID_IN => MED_DATAREADY_IN(bit_index),
- DATA_VALID_OUT => MED_DATAREADY_OUT(bit_index),
- FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16),
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH),
- MED_ERROR_OUT => MED_ERROR_OUT((bit_index*3+2) downto bit_index*3),
- MED_READ_IN => MED_READ_IN(bit_index)
- );
- end generate;
-end flexi_PCS_synch;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
-library ieee;
-library work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.all;
-use work.version.all;
-use work.trb_net_std.all;
-use work.trb_net16_hub_func.all;
--- library sc;
--- use sc.components.all;
-entity hub is
- generic (
- HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 16
- );
- port (
- LVDS_CLK_200P : in std_logic;
--- LVDS_CLK_200N : in std_logic;
--- SERDES_200N : in std_logic;
--- SERDES_200P : in std_logic;
--- ADO_LV : in std_logic_vector(61 downto 0);
- --addon connector
- ADO_TTL : inout std_logic_vector(46 downto 0);
- --diode
- DBAD : out std_logic;
- DGOOD : out std_logic;
- DINT : out std_logic;
- DWAIT : out std_logic;
- LOK : out std_logic_vector(16 downto 1);
- RT : out std_logic_vector(16 downto 1);
- TX_DIS : out std_logic_vector(16 downto 1);
- IPLL : out std_logic;
- OPLL : out std_logic;
- --data to/from optical tranceivers
- SFP_INP_N : in std_logic_vector(15 downto 0);
- SFP_INP_P : in std_logic_vector(15 downto 0);
- SFP_OUT_N : out std_logic_vector(15 downto 0);
- SFP_OUT_P : out std_logic_vector(15 downto 0);
- --tempsens
- FS_PE_11 : inout std_logic;
- --etrax_interface
- FS_PE : inout std_logic_vector(9 downto 8)--sim-- ;
---sim-- OPT_DATA_IN : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
---sim-- OPT_DATA_OUT : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
---sim-- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
---sim-- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0)
- );
-end hub;
-architecture hub of hub is
- component trb_hub_interface
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- STROBE : in std_logic;
- INTERNAL_DATA_IN : in std_logic_vector(7 downto 0);
- INTERNAL_DATA_OUT : out std_logic_vector(7 downto 0);
- INTERNAL_ADDRESS : in std_logic_vector(15 downto 0);
- INTERNAL_MODE : in std_logic;
- VALID_DATA_SENT : out std_logic;
- hub_register_00 : in std_logic_vector(7 downto 0);
- hub_register_01 : in std_logic_vector(7 downto 0);
- hub_register_02 : in std_logic_vector(7 downto 0);
- hub_register_03 : in std_logic_vector(7 downto 0);
- hub_register_04 : in std_logic_vector(7 downto 0);
- hub_register_05 : in std_logic_vector(7 downto 0);
- hub_register_06 : in std_logic_vector(7 downto 0);
- hub_register_07 : in std_logic_vector(7 downto 0);
- hub_register_08 : in std_logic_vector(7 downto 0);
- hub_register_09 : in std_logic_vector(7 downto 0);
- hub_register_0a : out std_logic_vector(7 downto 0);
- hub_register_0b : out std_logic_vector(7 downto 0);
- hub_register_0c : out std_logic_vector(7 downto 0);
- hub_register_0d : out std_logic_vector(7 downto 0);
- hub_register_0e : out std_logic_vector(7 downto 0);
- hub_register_0f : out std_logic_vector(7 downto 0);
- hub_register_10 : in std_logic_vector(7 downto 0);
- hub_register_11 : in std_logic_vector(7 downto 0);
- hub_register_12 : in std_logic_vector(7 downto 0);
- hub_register_13 : in std_logic_vector(7 downto 0);
- hub_register_14 : in std_logic_vector(7 downto 0);
- hub_register_15 : in std_logic_vector(7 downto 0);
- hub_register_16 : in std_logic_vector(7 downto 0)
- );
- end component;
- component serdes_fpga_ref_clk--serdes, flexi PCS
- port(
--- refclkp : in std_logic;
--- refclkn : in std_logic;
- rxrefclk : in std_logic;
- refclk : in std_logic;
- hdinp_0 : in std_logic;
- hdinn_0 : in std_logic;
- tclk_0 : in std_logic;
- rclk_0 : in std_logic;
- tx_rst_0 : in std_logic;
- rx_rst_0 : in std_logic;
- txd_0 : in std_logic_vector(15 downto 0);
- tx_k_0 : in std_logic_vector(1 downto 0);
- tx_force_disp_0 : in std_logic_vector(1 downto 0);
- tx_disp_sel_0 : in std_logic_vector(1 downto 0);
- tx_crc_init_0 : in std_logic_vector(1 downto 0);
- word_align_en_0 : in std_logic;
- mca_align_en_0 : in std_logic;
- felb_0 : in std_logic;
- lsm_en_0 : in std_logic;
- hdinp_1 : in std_logic;
- hdinn_1 : in std_logic;
- tclk_1 : in std_logic;
- rclk_1 : in std_logic;
- tx_rst_1 : in std_logic;
- rx_rst_1 : in std_logic;
- txd_1 : in std_logic_vector(15 downto 0);
- tx_k_1 : in std_logic_vector(1 downto 0);
- tx_force_disp_1 : in std_logic_vector(1 downto 0);
- tx_disp_sel_1 : in std_logic_vector(1 downto 0);
- tx_crc_init_1 : in std_logic_vector(1 downto 0);
- word_align_en_1 : in std_logic;
- mca_align_en_1 : in std_logic;
- felb_1 : in std_logic;
- lsm_en_1 : in std_logic;
- hdinp_2 : in std_logic;
- hdinn_2 : in std_logic;
- tclk_2 : in std_logic;
- rclk_2 : in std_logic;
- tx_rst_2 : in std_logic;
- rx_rst_2 : in std_logic;
- txd_2 : in std_logic_vector(15 downto 0);
- tx_k_2 : in std_logic_vector(1 downto 0);
- tx_force_disp_2 : in std_logic_vector(1 downto 0);
- tx_disp_sel_2 : in std_logic_vector(1 downto 0);
- tx_crc_init_2 : in std_logic_vector(1 downto 0);
- word_align_en_2 : in std_logic;
- mca_align_en_2 : in std_logic;
- felb_2 : in std_logic;
- lsm_en_2 : in std_logic;
- hdinp_3 : in std_logic;
- hdinn_3 : in std_logic;
- tclk_3 : in std_logic;
- rclk_3 : in std_logic;
- tx_rst_3 : in std_logic;
- rx_rst_3 : in std_logic;
- txd_3 : in std_logic_vector(15 downto 0);
- tx_k_3 : in std_logic_vector(1 downto 0);
- tx_force_disp_3 : in std_logic_vector(1 downto 0);
- tx_disp_sel_3 : in std_logic_vector(1 downto 0);
- tx_crc_init_3 : in std_logic_vector(1 downto 0);
- word_align_en_3 : in std_logic;
- mca_align_en_3 : in std_logic;
- felb_3 : in std_logic;
- lsm_en_3 : in std_logic;
- mca_resync_01 : in std_logic;
- mca_resync_23 : in std_logic;
- quad_rst : in std_logic;
- serdes_rst : in std_logic;
- rxa_pclk : out std_logic;
- rxb_pclk : out std_logic;
- hdoutp_0 : out std_logic;
- hdoutn_0 : out std_logic;
- ref_0_sclk : out std_logic;
- rx_0_sclk : out std_logic;
- rxd_0 : out std_logic_vector(15 downto 0);
- rx_k_0 : out std_logic_vector(1 downto 0);
- rx_disp_err_detect_0 : out std_logic_vector(1 downto 0);
- rx_cv_detect_0 : out std_logic_vector(1 downto 0);
- rx_crc_eop_0 : out std_logic_vector(1 downto 0);
- lsm_status_0 : out std_logic;
- hdoutp_1 : out std_logic;
- hdoutn_1 : out std_logic;
- ref_1_sclk : out std_logic;
- rx_1_sclk : out std_logic;
- rxd_1 : out std_logic_vector(15 downto 0);
- rx_k_1 : out std_logic_vector(1 downto 0);
- rx_disp_err_detect_1 : out std_logic_vector(1 downto 0);
- rx_cv_detect_1 : out std_logic_vector(1 downto 0);
- rx_crc_eop_1 : out std_logic_vector(1 downto 0);
- lsm_status_1 : out std_logic;
- hdoutp_2 : out std_logic;
- hdoutn_2 : out std_logic;
- ref_2_sclk : out std_logic;
- rx_2_sclk : OUT std_logic;
- rxd_2 : OUT std_logic_vector(15 downto 0);
- rx_k_2 : OUT std_logic_vector(1 downto 0);
- rx_disp_err_detect_2 : OUT std_logic_vector(1 downto 0);
- rx_cv_detect_2 : OUT std_logic_vector(1 downto 0);
- rx_crc_eop_2 : OUT std_logic_vector(1 downto 0);
- lsm_status_2 : OUT std_logic;
- hdoutp_3 : OUT std_logic;
- hdoutn_3 : OUT std_logic;
- ref_3_sclk : OUT std_logic;
- rx_3_sclk : OUT std_logic;
- rxd_3 : OUT std_logic_vector(15 downto 0);
- rx_k_3 : OUT std_logic_vector(1 downto 0);
- rx_disp_err_detect_3 : out std_logic_vector(1 downto 0);
- rx_cv_detect_3 : out std_logic_vector(1 downto 0);
- rx_crc_eop_3 : out std_logic_vector(1 downto 0);
- lsm_status_3 : out std_logic;
- mca_aligned_01 : out std_logic;
- mca_inskew_01 : out std_logic;
- mca_outskew_01 : out std_logic;
- mca_aligned_23 : out std_logic;
- mca_inskew_23 : out std_logic;
- mca_outskew_23 : out std_logic;
- ref_pclk : out std_logic
- );
- end component;
- component flexi_PCS_synch
- generic (
- HOW_MANY_CHANNELS : positive);
- port (
- SYSTEM_CLK : in std_logic;
- CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
- RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- RESET : in std_logic;
- RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
- MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0);
- MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0)
- );
- end component;
- component pll_ref
- port (
- clk : in std_logic;
- clkop : out std_logic;
- clkos : out std_logic;
- lock : out std_logic);
- end component;
--- component trb_net16_hub_base
--- generic (
--- --general settings
--- MUX_SECURE_MODE : integer range 0 to 1 := c_NO;
--- --hub control
--- HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 0;--c_SLOW_CTRL_CHANNEL;
--- HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL;
--- HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4;
--- HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
--- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
--- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F00A";
--- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
--- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
--- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
--- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
--- --media interfaces
--- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := HOW_MANY_CHANNELS;
--- MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
--- -- settings for apis
--- API_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
--- API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
--- API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0);
--- API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
--- API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
--- --trigger reading interfaces
--- TRG_NUMBER : integer range 0 to c_MAX_TRG_PER_HUB := 0;
--- TRG_SECURE_MODE : integer range 0 to 1 := c_NO;
--- TRG_CHANNELS : hub_api_config_t := (0,1,0,0,0,0,0,0)
--- );
--- port (
--- CLK : in std_logic;
--- RESET : in std_logic;
--- CLK_EN : in std_logic;
--- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
--- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
--- MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
--- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
--- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
--- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
--- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
--- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
--- MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0);
--- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
--- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
--- APL_DATA_IN : in std_logic_vector (API_NUMBER*c_DATA_WIDTH downto 0);
--- APL_PACKET_NUM_IN : in std_logic_vector (API_NUMBER*c_NUM_WIDTH downto 0);
--- APL_DATAREADY_IN : in std_logic_vector (API_NUMBER downto 0);
--- APL_READ_OUT : out std_logic_vector (API_NUMBER downto 0);
--- APL_SHORT_TRANSFER_IN : in std_logic_vector (API_NUMBER downto 0);
--- APL_DTYPE_IN : in std_logic_vector (API_NUMBER*4 downto 0);
--- APL_ERROR_PATTERN_IN : in std_logic_vector (API_NUMBER*32 downto 0);
--- APL_SEND_IN : in std_logic_vector (API_NUMBER downto 0);
--- APL_TARGET_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0);
--- APL_DATA_OUT : out std_logic_vector (API_NUMBER*16 downto 0);
--- APL_PACKET_NUM_OUT : out std_logic_vector (API_NUMBER*c_NUM_WIDTH downto 0);
--- APL_TYP_OUT : out std_logic_vector (API_NUMBER*3 downto 0);
--- APL_DATAREADY_OUT : out std_logic_vector (API_NUMBER downto 0);
--- APL_READ_IN : in std_logic_vector (API_NUMBER downto 0);
--- APL_RUN_OUT : out std_logic_vector (API_NUMBER downto 0);
--- APL_MY_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0);
--- APL_SEQNR_OUT : out std_logic_vector (API_NUMBER*8 downto 0);
--- TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0);
--- TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0);
--- TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0);
--- TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0);
--- TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0);
--- TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0);
--- ONEWIRE : inout std_logic;
--- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
--- HUB_STAT_GEN : out std_logic_vector (31 downto 0);
--- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
--- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
--- ETRAX_CTRL : in std_logic_vector (15 downto 0)
--- );
--- end component;
- component simpleupcounter_16bit
- port (
- QOUT : out std_logic_vector(15 downto 0);
- UP : in std_logic;
- CLK : in std_logic;
- CLR : in std_logic);
- end component;
- component simpleupcounter_32bit
- port (
- QOUT : out std_logic_vector(31 downto 0);
- UP : in std_logic;
- CLK : in std_logic;
- CLR : in std_logic);
- end component;
- component trb_net_onewire
- generic (
- USE_TEMPERATURE_READOUT : integer range 0 to 1;
- CLK_PERIOD : integer);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- ONEWIRE : inout std_logic;
- DATA_OUT : out std_logic_vector(15 downto 0);
- ADDR_OUT : out std_logic_vector(2 downto 0);
- WRITE_OUT : out std_logic;
- TEMP_OUT : out std_logic_vector(11 downto 0);
- STAT : out std_logic_vector(31 downto 0));
- end component;
- component edge_to_pulse
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
- end component;
- component DCS
--- synthesis translate_off
- --sim
- generic (
- DCSMODE : string := "LOW_LOW");
--- synthesis translate_on
- port (
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- SEL : in std_logic;
- DCSOUT : out std_logic);
- end component;
- component etrax_interfacev2
- generic (
- RW_SYSTEM : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DATA_BUS : in std_logic_vector(31 downto 0);
- ETRAX_DATA_BUS_B : inout std_logic_vector(16 downto 0);
- ETRAX_DATA_BUS_B_17 : in std_logic;
- ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
- ETRAX_DATA_BUS_E : inout std_logic_vector(10 downto 9);
- DATA_VALID : in std_logic;
- ETRAX_BUS_BUSY : in std_logic;
- ETRAX_IS_READY_TO_READ : out std_logic;
- TDC_TCK : out std_logic;
- TDC_TDI : out std_logic;
- TDC_TMS : out std_logic;
- TDC_TRST : out std_logic;
- TDC_TDO : in std_logic;
- TDC_RESET : out std_logic;
- EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
- EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
- EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
- EXTERNAL_ACK : out std_logic;
- EXTERNAL_VALID : in std_logic;
- EXTERNAL_MODE : out std_logic_vector(15 downto 0);
- FPGA_REGISTER_00 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0E : out std_logic_vector(31 downto 0);
--- EXTERNAL_RESET : out std_logic;
- LVL2_VALID : in std_logic);
- end component;
-
- component hub_etrax_interface
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- ETRAX_DATA_BUS : inout std_logic_vector(17 downto 5);
- EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
- EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
- EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
- EXTERNAL_ACK : out std_logic;
- EXTERNAL_VALID : in std_logic;
- EXTERNAL_MODE : out std_logic_vector(7 downto 0);
- FPGA_REGISTER_00 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0E : out std_logic_vector(31 downto 0);
- EXTERNAL_RESET : out std_logic);
- end component;
-
- component simple_hub
- generic (
- HOW_MANY_CHANNELS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- DATA_IN_VALID : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- SEND_DATA : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- ENABLE_CHANNELS : in std_logic_vector(15 downto 0);
- READ_DATA : out std_logic_vector(HOW_MANY_CHANNELS -1 downto 0);
- HUB_DEBUG : out std_logic_vector(31 downto 0)
- );
- end component;
--- constant HOW_MANY_CHANNELS : integer := 16;
- -----------------------------------------------------------------------------
- -- FLEXI_PCS
- -----------------------------------------------------------------------------
- signal ref_pclk : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0);
- signal rxd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- signal rxd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- signal rx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal rx_rst_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- signal cv_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal txd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- signal txd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- signal tx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal rxb_pclk_a : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0);
- signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- signal flexi_pcs_synch_status_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal word_align_en : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- -----------------------------------------------------------------------------
- -- hub trb interface
- -----------------------------------------------------------------------------
- signal hub_register_00_i : std_logic_vector(31 downto 0);
- signal hub_register_01_i : std_logic_vector(31 downto 0);
- signal hub_register_02_i : std_logic_vector(31 downto 0);
- signal hub_register_03_i : std_logic_vector(31 downto 0);
- signal hub_register_04_i : std_logic_vector(31 downto 0);
- signal hub_register_05_i : std_logic_vector(31 downto 0);
- signal hub_register_06_i : std_logic_vector(31 downto 0);
- signal hub_register_07_i : std_logic_vector(31 downto 0);
- signal hub_register_08_i : std_logic_vector(31 downto 0);
- signal hub_register_09_i : std_logic_vector(31 downto 0);
- signal hub_register_0a_i : std_logic_vector(31 downto 0);
- signal hub_register_0b_i : std_logic_vector(31 downto 0);
- signal hub_register_0c_i : std_logic_vector(31 downto 0);
- signal hub_register_0d_i : std_logic_vector(31 downto 0);
- signal hub_register_0e_i : std_logic_vector(31 downto 0);
- signal hub_register_0f_i : std_logic_vector(31 downto 0);
- signal hub_register_10_i : std_logic_vector(31 downto 0);
- signal hub_register_11_i : std_logic_vector(31 downto 0);
- signal hub_register_12_i : std_logic_vector(31 downto 0);
- signal hub_register_13_i : std_logic_vector(31 downto 0);
- signal hub_register_14_i : std_logic_vector(31 downto 0);
- signal hub_register_15_i : std_logic_vector(31 downto 0);
- signal hub_register_16_i : std_logic_vector(31 downto 0);
- signal ADO_TTL_12 : std_logic;
- -----------------------------------------------------------------------------
- -- flexi_PCS to hub interface
- -----------------------------------------------------------------------------
- signal med_dataready_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- --test
- signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_dataready_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_read_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_read_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_data_out_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal med_data_in_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal med_packet_num_out_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- signal med_error_out_i : std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
- signal med_stat_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal med_ctrl_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal hub_stat_channel_i : std_logic_vector(2**(c_MUX_WIDTH-1)*16-1 downto 0);
- signal hub_stat_gen_i : std_logic_vector(31 downto 0);
-
- -----------------------------------------------------------------------------
- -- other
- -----------------------------------------------------------------------------
- signal hub_register_0e_and_0d : std_logic_vector(15 downto 0) := x"0006";
- signal cv_counter : std_logic_vector(31 downto 0);
- signal cv_countera : std_logic_vector(31 downto 0);
- signal serdes_ref_clk : std_logic;
- signal serdes_ref_lock : std_logic;
- signal serdes_ref_clks : std_logic;
- signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*2 -1 downto 0);
- signal mplex_ctrl_i : std_logic_vector (HOW_MANY_CHANNELS*32-1 downto 0);
- signal word_counter_for_api_00 : std_logic_vector(1 downto 0);
- signal word_counter_for_api_01 : std_logic_vector(1 downto 0);
- signal global_reset_i : std_logic;
- signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0";
- signal registered_signals : std_logic_vector(7 downto 0);
- signal hub_register_0a_i_synch : std_logic_vector(7 downto 0);
- signal hub_register_0e_and_0d_synch : std_logic_vector(15 downto 0);
- signal test_signal : std_logic_vector(1 downto 0);
- signal pulse_test : std_logic;
- signal saved_lvl1_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0');
- signal saved_lvl2_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0');
- signal all_lvl1_ready : std_logic;
- signal all_lvl2_ready : std_logic;
- signal flexi_pcs_ref_clk : std_logic;
- signal lok_i : std_logic_vector(16 downto 1);
- signal not_used_lok : std_logic_vector(15 downto 0);
- signal used_channels_locked : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal channels_locked : std_logic_vector(16 downto 1);
- signal switch_rx_clk : std_logic;
- signal lock_pattern : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal all_lvl1_ready_delay1 : std_logic;
- signal all_lvl1_ready_delay2 : std_logic;
- signal all_lvl2_ready_delay1 : std_logic;
- signal all_lvl2_ready_delay2 : std_logic;
- -- etrax interface
--- signal external_address_i : std_logic_vector(31 downto 0);
--- signal external_data_out_i : std_logic_vector(31 downto 0);
--- signal external_data_in_i : std_logic_vector(31 downto 0);
--- signal external_ack_i : std_logic;
--- signal external_valid_i : std_logic;
--- signal external_mode_i : std_logic_vector(7 downto 0);
--- signal data_valid_i : std_logic;
- signal debug_register_00_i : std_logic_vector(7 downto 0);
- signal test2 : std_logic_vector(1 downto 0);
- signal med_read_counter : std_logic_vector(3 downto 0);
- -- simulation
- signal rx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal tx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal cv_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal rx_clk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- signal ref_pclk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
- constant trb_net_enable : integer := 0;
- --etrax interface
- signal external_address_i : std_logic_vector(31 downto 0);
- signal external_data_out_i : std_logic_vector(31 downto 0);
- signal external_data_in_i : std_logic_vector(31 downto 0);
- signal external_ack_i : std_logic;
- signal external_valid_i : std_logic;
- signal external_mode_i : std_logic_vector(15 downto 0);
- signal fpga_register_00_i : std_logic_vector(31 downto 0);
- signal fpga_register_01_i : std_logic_vector(31 downto 0);
- signal fpga_register_02_i : std_logic_vector(31 downto 0);
- signal fpga_register_03_i : std_logic_vector(31 downto 0);
- signal fpga_register_04_i : std_logic_vector(31 downto 0);
- signal fpga_register_05_i : std_logic_vector(31 downto 0);
- signal fpga_register_06_i : std_logic_vector(31 downto 0):=x"00000003";
- signal fpga_register_07_i : std_logic_vector(31 downto 0);
- signal fpga_register_08_i : std_logic_vector(31 downto 0);
- signal fpga_register_09_i : std_logic_vector(31 downto 0);
- signal fpga_register_0a_i : std_logic_vector(31 downto 0);
- signal fpga_register_0b_i : std_logic_vector(31 downto 0);
- signal fpga_register_0c_i : std_logic_vector(31 downto 0);
- signal fpga_register_0d_i : std_logic_vector(31 downto 0);
- signal fpga_register_0e_i : std_logic_vector(31 downto 0);
- --simple hub
- signal hub_debug_i : std_logic_vector(31 downto 0);
- --test
- constant OPT_TEST_MODE : integer := 1;
-
-begin
- GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt)
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_cnt < x"e" then
- global_reset_cnt <= global_reset_cnt + 1;
- global_reset_i <= '1';
- elsif global_reset_cnt = x"e" then
- global_reset_i <= '0';
- global_reset_cnt <= x"e";
- else
- global_reset_i <= '0';
- global_reset_cnt <= global_reset_cnt;
- end if;
- end if;
- end process GLOBAL_RESET;
- REF_PLL: pll_ref
- port map (
- clk => LVDS_CLK_200P,
- clkop => serdes_ref_clk,
- clkos => serdes_ref_clks,
- lock => serdes_ref_lock);
- TEST: edge_to_pulse
- port map (
- clock => ref_pclk(0),
- en_clk => '1',
- signal_in => hub_register_0a_i(0),
- pulse => pulse_test);
- test_signal(1) <= pulse_test;
- test_signal(0) <= pulse_test;
- REF_CLK_SELECT: DCS
- -- synthesis translate_off
-
- generic map (--no_sim--
- DCSMODE => DCSMODE)--no_sim--
- -- synthesis translate_on
- port map (
- CLK0 => LVDS_CLK_200P,
- CLK1 => '0',
- SEL => switch_rx_clk,--hub_register_0a_i(0),--'0',--switch_rx_clk,
- DCSOUT => flexi_pcs_ref_clk);
- SWITCH_CLOCK: process (LVDS_CLK_200P, global_reset_i)
- begin -- process SWITCH_CLOCK
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' or lock_pattern /= used_channels_locked then -- asynchronous reset (active low)
- switch_rx_clk <= '0';
- lock_pattern <= (others => '1');
- elsif lock_pattern = used_channels_locked then
- switch_rx_clk <= '1';
- lock_pattern <= (others => '1');
- end if;
- end if;
- end process SWITCH_CLOCK;
--- LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
--- begin
--- used_channels_locked(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
--- end generate LOK_STATUS_DIOD_EN;
-
- --lock_pattern(15 downto HOW_MANY_CHANNELS) <= lok_i(16 downto HOW_MANY_CHANNELS +1);
- QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate
- begin
- QUAD : serdes_fpga_ref_clk
- port map (
--- refclkp => SERDES_200P,
--- refclkn => SERDES_200N,
- rxrefclk => flexi_pcs_ref_clk,--LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P,
- refclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P,
- hdinp_0 => SFP_INP_P(bit_index*4+0),
- hdinn_0 => SFP_INP_N(bit_index*4+0),
- tclk_0 => ref_pclk(bit_index),
- rclk_0 => rx_clk_i(0+bit_index*4),
- tx_rst_0 => '0',
- rx_rst_0 => rx_rst_i(0+bit_index*4),--hub_register_0a_i(0),
- txd_0 => txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--
- tx_k_0 => tx_k_i(1+bit_index*8 downto 0+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
- tx_force_disp_0 => "00",--hub_register_0a_i(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),
- tx_disp_sel_0 => "00",--hub_register_0a_i(5 downto 4), --"00",--hub_register_0a_i_synch(5 downto 4),--"00",
- tx_crc_init_0 => "00",
- word_align_en_0 => '1',--word_align_en(0+bit_index*4),--'1',
- mca_align_en_0 => '0',
- felb_0 => '0',
- lsm_en_0 => '0',
- hdinp_1 => SFP_INP_P(bit_index*4+1),
- hdinn_1 => SFP_INP_N(bit_index*4+1),
- tclk_1 => ref_pclk(bit_index),
- rclk_1 => rx_clk_i(1+bit_index*4),
- tx_rst_1 => '0',
- rx_rst_1 => rx_rst_i(1+bit_index*4),
- txd_1 => txd_synch_i(31+bit_index*64 downto 16+bit_index*64),
- tx_k_1 => tx_k_i(3+bit_index*8 downto 2+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
- tx_force_disp_1 => "00",--tx_k_i(3+bit_index*8 downto 2+bit_index*8),
- tx_disp_sel_1 => "00",
- tx_crc_init_1 => "00",
- word_align_en_1 => '1',--word_align_en(1+bit_index*4),--'1',--
- mca_align_en_1 => '0',
- felb_1 => '0',
- lsm_en_1 => '0',
- hdinp_2 => SFP_INP_P(bit_index*4+2),
- hdinn_2 => SFP_INP_N(bit_index*4+2),
- tclk_2 => ref_pclk(bit_index),
- rclk_2 => rx_clk_i(2+bit_index*4),
- tx_rst_2 => '0',
- rx_rst_2 => rx_rst_i(2+bit_index*4),
- txd_2 => txd_synch_i(47+bit_index*64 downto 32+bit_index*64),
- tx_k_2 => tx_k_i(5+bit_index*8 downto 4+bit_index*8),--"10",
- tx_force_disp_2 => "00",--
- tx_disp_sel_2 => "00",
- tx_crc_init_2 => "00",
- word_align_en_2 => '1',--word_align_en(2+bit_index*4),--'1',
- mca_align_en_2 => '0',
- felb_2 => '0',
- lsm_en_2 => '0',
- hdinp_3 => SFP_INP_P(bit_index*4+3),
- hdinn_3 => SFP_INP_N(bit_index*4+3),
- tclk_3 => ref_pclk(bit_index),
- rclk_3 => rx_clk_i(3+bit_index*4),
- tx_rst_3 => '0',
- rx_rst_3 => rx_rst_i(3+bit_index*4),
- txd_3 => txd_synch_i(63+bit_index*64 downto 48+bit_index*64),
- tx_k_3 => tx_k_i(7+bit_index*8 downto 6+bit_index*8),--"10",
- tx_force_disp_3 => "00",
- tx_disp_sel_3 => "00",
- tx_crc_init_3 => "00",
- word_align_en_3 => '1',--word_align_en(3+bit_index*4),--'1',
- mca_align_en_3 => '0',
- felb_3 => '0',
- lsm_en_3 => '0',
- mca_resync_01 => '0',
- mca_resync_23 => '0',
- quad_rst => '0',
- serdes_rst => '0',
- rxa_pclk => rx_clk_i(0+bit_index*4),
- rxb_pclk => rxb_pclk_a(bit_index),
- hdoutp_0 => SFP_OUT_P(bit_index*4+0),
- hdoutn_0 => SFP_OUT_N(bit_index*4+0),
- ref_0_sclk => open,
- rx_0_sclk => open,
- rxd_0 => rxd_i(15+bit_index*64 downto 0+bit_index*64),
- rx_k_0 => rx_k_i(1+bit_index*8 downto 0+bit_index*8),
- rx_disp_err_detect_0 => open, --rx_disp_err_detect_0_a,
- rx_cv_detect_0 => cv_i(1+bit_index*8 downto 0+bit_index*8),
- rx_crc_eop_0 => open,
- lsm_status_0 => open,
- hdoutp_1 => SFP_OUT_P(bit_index*4+1),
- hdoutn_1 => SFP_OUT_N(bit_index*4+1),
- ref_1_sclk => open,
- rx_1_sclk => rx_clk_i(1+bit_index*4),
- rxd_1 => rxd_i(31+bit_index*64 downto 16+bit_index*64),
- rx_k_1 => rx_k_i(3+bit_index*8 downto 2+bit_index*8),
- rx_disp_err_detect_1 => open, --rx_disp_err_detect_1_a,
- rx_cv_detect_1 => cv_i(3+bit_index*8 downto 2+bit_index*8),
- rx_crc_eop_1 => open,
- lsm_status_1 => open,
- hdoutp_2 => SFP_OUT_P(bit_index*4+2),
- hdoutn_2 => SFP_OUT_N(bit_index*4+2),
- ref_2_sclk => open,
- rx_2_sclk => rx_clk_i(2+bit_index*4),
- rxd_2 => rxd_i(47+bit_index*64 downto 32+bit_index*64),
- rx_k_2 => rx_k_i(5+bit_index*8 downto 4+bit_index*8),
- rx_disp_err_detect_2 => open, --rx_disp_err_detect_2_a,
- rx_cv_detect_2 => cv_i(5+bit_index*8 downto 4+bit_index*8),
- rx_crc_eop_2 => open,
- lsm_status_2 => open,
- hdoutp_3 => SFP_OUT_P(bit_index*4+3),
- hdoutn_3 => SFP_OUT_N(bit_index*4+3),
- ref_3_sclk => open,
- rx_3_sclk => rx_clk_i(3+bit_index*4),
- rxd_3 => rxd_i(63+bit_index*64 downto 48+bit_index*64),
- rx_k_3 => rx_k_i(7+bit_index*8 downto 6+bit_index*8),
- rx_disp_err_detect_3 => open, --rx_disp_err_detect_3_a,
- rx_cv_detect_3 => cv_i(7+bit_index*8 downto 6+bit_index*8),
- rx_crc_eop_3 => open,
- lsm_status_3 => open,
- mca_aligned_01 => open, --mca_aligned_01_i,
- mca_inskew_01 => open, --mca_inskew_01_i,
- mca_outskew_01 => open, --mca_outskew_01_i,
- mca_aligned_23 => open, --mca_aligned_23_i,
- mca_inskew_23 => open, --mca_inskew_23_i,
- mca_outskew_23 => open, --mca_outskew_23_i,
- ref_pclk => ref_pclk(bit_index)
- );
- end generate QUAD_GENERATE;
- -- word_align_en <= not rx_rst_i;
---sim-- SIMULATION_CONNECTION: for i in 0 to HOW_MANY_CHANNELS-1 generate
---sim-- rx_k_sim(i*2) <= not OPT_DATA_VALID_IN(i);
---sim-- rx_k_sim(i*2+1) <= '0';
---sim-- OPT_DATA_VALID_OUT(i) <= not tx_k_sim(i*2);
---sim-- rx_clk_sim <= (others => LVDS_CLK_200P);
---sim-- ref_pclk_sim <= (others => LVDS_CLK_200P);
---sim-- cv_sim <= (others => '0');
---sim-- end generate SIMULATION_CONNECTION;
- FLEXI_PCS_INT : flexi_PCS_synch
- generic map (
- HOW_MANY_CHANNELS => HOW_MANY_CHANNELS)
- port map (
- SYSTEM_CLK => LVDS_CLK_200P,
- CLK => ref_pclk,--no_sim--
---sim-- CLK => ref_pclk_sim,
- RX_CLK => rx_clk_i,--no_sim--
---sim-- RX_CLK => rx_clk_sim,
- RESET => global_reset_i,
- RXD => rxd_i,--no_sim--
---sim-- RXD => OPT_DATA_IN,
- MED_DATA_OUT => med_data_out_i,
- RX_K => rx_k_i,--no_sim--
---sim-- RX_K => rx_k_sim,
- RX_RST => rx_rst_i,
- CV => cv_i,--no_sim--
---sim-- CV => cv_sim,
- MED_DATA_IN => med_data_in_i,
- TXD_SYNCH => txd_synch_i, --no_sim--
---sim-- TXD_SYNCH => OPT_DATA_OUT,
- TX_K => tx_k_i, --no_sim--
---sim-- TX_K => tx_k_sim,
- FLEXI_PCS_SYNCH_STATUS => flexi_pcs_synch_status_i,
- MED_DATAREADY_IN => med_dataready_in_i,
- MED_DATAREADY_OUT => med_dataready_out_i,
- MED_PACKET_NUM_IN => med_packet_num_in_i,
- MED_PACKET_NUM_OUT => med_packet_num_out_i,
- MED_READ_IN => med_read_in_i,
- MED_READ_OUT => med_read_out_i,
- MED_ERROR_OUT => med_error_out_i,
- MED_STAT_OP => med_stat_op_i,
- MED_CTRL_OP => med_ctrl_op_i
- );
--- SIMPLE_HUB_GEN: if trb_net_enable = 0 and OPT_TEST_MODE = 0 generate
--- SIMPLE_HUB_INST: simple_hub
--- generic map (
--- HOW_MANY_CHANNELS => HOW_MANY_CHANNELS)
--- port map (
--- CLK => LVDS_CLK_200P,
--- RESET => global_reset_i,
--- DATA_IN => med_data_out_i,
--- DATA_OUT => med_data_in_i,
--- DATA_IN_VALID => med_dataready_out_i,
--- SEND_DATA => med_dataready_in_i,
--- ENABLE_CHANNELS => fpga_register_06_i(15 downto 0),
--- READ_DATA => med_read_in_i,
--- HUB_DEBUG => hub_debug_i
--- );
-
--- end generate SIMPLE_HUB_GEN;
-
--- ENABLE_OPT_TEST: if OPT_TEST_MODE = 1 generate
- med_read_in_i <= (others => '1');
- med_data_in_i <= med_data_out_i;
- med_dataready_in_i <= med_dataready_out_i;
--- end generate ENABLE_OPT_TEST;
--- ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0);
--- ADO_TTL(34 downto 19) <= med_dataready_out_i(0)& med_data_out_i(14 downto 0);
--- ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0);
--- ADO_TTL(15 downto 0) <= rx_k_i(1 downto 0) & rxd_i(13 downto 0);
--- med_data_in_i(15 downto 0) <= hub_register_0e_and_0d;
--- med_read_in_i <= (others => '1'); --test
-
--- ENABLE_TRB_NET: if trb_net_enable = 1 generate
--- HUB_API: trb_net16_hub_base
--- port map (
--- CLK => LVDS_CLK_200P,
--- RESET => global_reset_i,
--- CLK_EN => '1',
--- MED_DATAREADY_OUT => med_dataready_in_i,
--- MED_DATA_OUT => med_data_in_i,
--- MED_PACKET_NUM_OUT => med_packet_num_in_i,
--- MED_READ_IN => med_read_out_i,
--- MED_DATAREADY_IN => med_dataready_out_i,
--- MED_DATA_IN => med_data_out_i,
--- MED_PACKET_NUM_IN => med_packet_num_out_i,
--- MED_READ_OUT => med_read_in_i,
--- MED_ERROR_IN => med_error_out_i,
--- MED_STAT_OP => med_stat_op_i,
--- MED_CTRL_OP => med_ctrl_op_i,
--- APL_DATA_IN => (others => '0'),
--- APL_PACKET_NUM_IN => (others => '0'),
--- APL_DATAREADY_IN => (others => '0'),
--- APL_READ_OUT => open,
--- APL_SHORT_TRANSFER_IN => (others => '0'),
--- APL_DTYPE_IN => (others => '0'),
--- APL_ERROR_PATTERN_IN => (others => '0'),
--- APL_SEND_IN => (others => '0'),
--- APL_TARGET_ADDRESS_IN => (others => '0'),
--- APL_DATA_OUT => open,
--- APL_PACKET_NUM_OUT => open,
--- APL_TYP_OUT => open,
--- APL_DATAREADY_OUT => open,
--- APL_READ_IN => (others => '0'),
--- APL_RUN_OUT => open,
--- APL_MY_ADDRESS_IN => (others => '0'),
--- APL_SEQNR_OUT => open,
--- TRG_GOT_TRIGGER_OUT => open,
--- TRG_ERROR_PATTERN_OUT => open,
--- TRG_DTYPE_OUT => open,
--- TRG_SEQNR_OUT => open,
--- TRG_ERROR_PATTERN_IN => (others => '0'),
--- TRG_RELEASE_IN => (others => '0'),
--- ONEWIRE => FS_PE_11,
--- HUB_STAT_CHANNEL => hub_stat_channel_i,
--- HUB_STAT_GEN => hub_stat_gen_i,
--- MPLEX_CTRL => mplex_ctrl_i,
--- MPLEX_STAT => open,
--- ETRAX_CTRL => hub_register_0e_and_0d
--- );
--- end generate ENABLE_TRB_NET;
- ETRAX_RW_DATA_INTERFACE: etrax_interfacev2
- generic map (
- RW_SYSTEM => 2)
- port map (
- CLK => LVDS_CLK_200P,
- RESET => global_reset_i,
- DATA_BUS => (others => '0'),
- ETRAX_DATA_BUS_B => open,--(others => '0'),
- ETRAX_DATA_BUS_B_17 => '0',
- ETRAX_DATA_BUS_C => open,--(others => '0'),
- ETRAX_DATA_BUS_E => FS_PE(9 downto 8),
- DATA_VALID => '0',
- ETRAX_BUS_BUSY => '0',
- ETRAX_IS_READY_TO_READ => open,
- TDC_TCK => open,
- TDC_TDI => open,
- TDC_TMS => open,
- TDC_TRST => open,
- TDC_TDO => '0',
- TDC_RESET => open,
- EXTERNAL_ADDRESS => external_address_i,
- EXTERNAL_DATA_OUT => external_data_out_i,
- EXTERNAL_DATA_IN => x"ddbbccaa",--external_data_in_i,
- EXTERNAL_ACK => external_ack_i,
- EXTERNAL_VALID => external_ack_i,--external_valid_i,
- EXTERNAL_MODE => external_mode_i,
- FPGA_REGISTER_00 => fpga_register_00_i,
- FPGA_REGISTER_01 => fpga_register_01_i,
- FPGA_REGISTER_02 => fpga_register_02_i,
- FPGA_REGISTER_03 => fpga_register_03_i,
- FPGA_REGISTER_04 => fpga_register_04_i,
- FPGA_REGISTER_05 => fpga_register_05_i,
- FPGA_REGISTER_06 => fpga_register_06_i,
- FPGA_REGISTER_07 => fpga_register_07_i,
- FPGA_REGISTER_08 => fpga_register_08_i,
- FPGA_REGISTER_09 => fpga_register_09_i,
- FPGA_REGISTER_0A => fpga_register_0A_i,
- FPGA_REGISTER_0B => fpga_register_0B_i,
- FPGA_REGISTER_0C => fpga_register_0C_i,
- FPGA_REGISTER_0D => fpga_register_0D_i,
- FPGA_REGISTER_0E => fpga_register_0E_i,
- -- EXTERNAL_RESET => open,
- LVL2_VALID => '0');
- fpga_register_00_i <= x"0000"& lok_i;
- fpga_register_01_i <= hub_debug_i;
- fpga_register_02_i <= flexi_pcs_synch_status_i(31 downto 0);
- fpga_register_03_i <= flexi_pcs_synch_status_i(63 downto 32);
- fpga_register_04_i <= flexi_pcs_synch_status_i(95 downto 64);
-
- COUNT_LVL1_START: process (LVDS_CLK_200P, global_reset_i )
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' then
- fpga_register_05_i <= (others => '0');
- elsif med_dataready_out_i(0) = '1' and med_data_out_i(15 downto 12) = x"1" then
- fpga_register_05_i <= fpga_register_05_i + 1;
- end if;
- end if;
- end process COUNT_LVL1_START;
-
- COUNT_LVL1_SEND: process (LVDS_CLK_200P, global_reset_i )
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' then
- fpga_register_08_i <= (others => '0');
- elsif med_dataready_in_i(1) = '1' and med_data_in_i(31 downto 28) = x"1" then
- fpga_register_08_i <= fpga_register_08_i + 1;
- end if;
- end if;
- end process COUNT_LVL1_SEND;
-
- COUNT_LVL1_SEND: process (LVDS_CLK_200P, global_reset_i )
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' then
- fpga_register_09_i <= (others => '0');
- elsif med_dataready_in_i(1) = '1' then
- fpga_register_09_i <= fpga_register_08_i + 1;
- end if;
- end if;
- end process COUNT_LVL1_SEND;
-
- COUNT_LVL1_END: process (LVDS_CLK_200P, global_reset_i )
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' then
- fpga_register_07_i <= (others => '0');
- elsif med_dataready_out_i(1) = '1' and med_data_out_i(31 downto 28) = x"1" then
- fpga_register_07_i <= fpga_register_07_i + 1;
- end if;
- end if;
- end process COUNT_LVL1_END;
-
- TX_DIS_g : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
- begin
- TX_DIS(synch_fsm_state+1) <= '0';
- end generate;
-
- TX_DIS_g1 : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
- begin
- WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
- TX_DIS(16-not_connected) <= '1';
- end generate WHEN_NOT_ALL_EN;
- end generate;
-
----------------------------------------------------------------------------
--- setting LED
----------------------------------------------------------------------------
-
- --correct this for channels 11-8 - mirrored due to schematics -- also
- --adressing of sfps !!!
- LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
- begin
- lok_i(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16);
- end generate LOK_STATUS_DIOD_EN;
-
- LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate
- begin
- hub_register_00_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
- end generate LOK_STATUS_REGISTER_0;
-
- LOK_STATUS_REGISTER_1 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 - 8) generate
- begin
- hub_register_01_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16+8*16);
- end generate LOK_STATUS_REGISTER_1;
-
- LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
- begin
- WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
- lok_i(16-not_connected) <= '1';
- end generate WHEN_NOT_ALL_EN;
- end generate LOK_STATUS_DIOD_DIS;
- LOK <= lok_i;
- IPLL <= '0';
- OPLL <= '0';
- DBAD <= ADO_TTL(11);
- DGOOD <= '1';
- DINT <= '0';
- DWAIT <= global_reset_i;
-
- CV_COUNTERaaa: process (LVDS_CLK_200P, global_reset_i)
- begin
- if rising_edge(LVDS_CLK_200P) then -- rising clock edge
- if global_reset_i = '1' then -- asynchronous reset (active low)
- cv_counter <= (others => '0');
- else
- cv_counter <= cv_counter + 1;
- end if;
- end if;
- end process CV_COUNTERaaa;
- CV_COUNTERaab: process (ref_pclk(0), global_reset_i)
- begin
- if rising_edge(ref_pclk(0)) then -- rising clock edge
- if global_reset_i = '1' then -- asynchronous reset (active low)
- cv_countera <= (others => '0');
- else
- cv_countera <= cv_countera + 1;
- end if;
- end if;
- end process CV_COUNTERaab;
- RT(8) <= cv_counter(23);
- RT(9) <= med_read_in_i(0);
- RT(16 downto 10) <= flexi_pcs_synch_status_i(7 downto 1);
- RT(2) <= flexi_pcs_ref_clk;--cv_counter(0);
- RT(1) <= not switch_rx_clk;--ref_pclk(0);
-
- RT(3) <= LVDS_CLK_200P;
-
- RT(4) <= rx_k_i(0);
-
- RT(5) <= med_dataready_out_i(0);--serdes_ref_clk;
- RT(6) <= med_data_out_i(0);--serdes_ref_clks;
- RT(7) <= med_data_out_i(1);--serdes_ref_lock;
-
-end hub;
-
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-entity link_test is
-
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_OUT : out std_logic_vector(15 downto 0);
- VALID_IN : in std_logic;
- VALID_OUT : out std_logic;
- LINK_DEBUG : out std_logic_vector(31 downto 0);
- LINK_INFO : in std_logic_vector(15 downto 0)
- );
-
-end link_test;
-
-architecture link_test of link_test is
-
- component up_down_counter
- generic (
- NUMBER_OF_BITS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic;
- DOWN_IN : in std_logic);
- end component;
-
- component mdc_dc_lvl1_dpram_rand
- port (
- DataInA : in std_logic_vector(7 downto 0);
- DataInB : in std_logic_vector(7 downto 0);
- AddressA : in std_logic_vector(8 downto 0);
- AddressB : in std_logic_vector(8 downto 0);
- ClockA : in std_logic;
- ClockB : in std_logic;
- ClockEnA : in std_logic;
- ClockEnB : in std_logic;
- WrA : in std_logic;
- WrB : in std_logic;
- ResetA : in std_logic;
- ResetB : in std_logic;
- QA : out std_logic_vector(7 downto 0);
- QB : out std_logic_vector(7 downto 0));
- end component;
-
- component mdc_dc_lvl1_dpram_zero
- port (
- DataInA : in std_logic_vector(7 downto 0);
- DataInB : in std_logic_vector(7 downto 0);
- AddressA : in std_logic_vector(8 downto 0);
- AddressB : in std_logic_vector(8 downto 0);
- ClockA : in std_logic;
- ClockB : in std_logic;
- ClockEnA : in std_logic;
- ClockEnB : in std_logic;
- WrA : in std_logic;
- WrB : in std_logic;
- ResetA : in std_logic;
- ResetB : in std_logic;
- QA : out std_logic_vector(7 downto 0);
- QB : out std_logic_vector(7 downto 0));
- end component;
- type TEST_LINK_FSM is (IDLE, TEST1, TEST2, TEST3, TEST4, TRANSMITION_ERROR) ;
- signal TEST_LINK_FSM_current, TEST_LINK_FSM_next : TEST_LINK_FSM;
- signal wait_for_second_board_counter : std_logic_vector(31 downto 0);
- signal enable_sec_board_counter : std_logic;
- signal mem_diff : std_logic;
- signal mem_check_ok : std_logic;
-
- signal random_memory_address : std_logic_vector(8 downto 0);
- signal random_memory_send : std_logic;
-
- signal zero_memory_read_address : std_logic_vector(8 downto 0);
- signal zero_memory_write_address : std_logic_vector(8 downto 0);
- signal zero_memory_read : std_logic;
-
- signal zero_memory_data_out : std_logic_vector(7 downto 0);
- signal rand_memory_data_out : std_logic_vector(7 downto 0);
-
- signal counter_for_send_en : std_logic_vector(10 downto 0);
-
- signal rand_memory_data_out_synch : std_logic_vector(7 downto 0);
- signal rand_memory_data_out_synch_synch : std_logic_vector(7 downto 0);
- signal rand_memory_data_out_synch_synch_synch : std_logic_vector(7 downto 0);
-
- signal wait_for_data_counter : std_logic_vector(27 downto 0);
- signal wait_for_data_en : std_logic;
-
- signal link_debug_i : std_logic_vector(1 downto 0);
- signal wait_for_data_reset : std_logic;
-
- signal zero_memory_read_synch : std_logic;
- signal wait_for_second_board_reset : std_logic;
-
-
-begin
- TEST_CLOCK : process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- TEST_LINK_FSM_current <= IDLE;
- else
- TEST_LINK_FSM_current <= TEST_LINK_FSM_next;
- end if;
- end if;
- end process TEST_CLOCK;
- FSM_TO_TEST_LINK : process (CLK)
- begin
- case TEST_LINK_FSM_current is
- when IDLE =>
- link_debug_i <= "01";
- enable_sec_board_counter <= '0';
- mem_check_ok <= '0';
- random_memory_send <= '0';
- wait_for_data_reset <= '1';
- VALID_OUT <= '0';
- wait_for_second_board_reset <= '1';
- if LINK_INFO(0)='1' then
- TEST_LINK_FSM_next <= TEST1;
- else
- TEST_LINK_FSM_next <= IDLE;
- end if;
- when TEST1 =>
- link_debug_i <= "10";
- enable_sec_board_counter <= '1';
- mem_check_ok <= '0';
- random_memory_send <= '0';
- VALID_OUT <= '0';
- wait_for_data_reset <= '1';
- wait_for_second_board_reset <= '0';
- if wait_for_second_board_counter(27)='1' then
- TEST_LINK_FSM_next <= TEST2;
- else
- TEST_LINK_FSM_next <= TEST1;
- end if;
- when TEST2 =>
- link_debug_i <= "11";
- enable_sec_board_counter <= '0';
- mem_check_ok <= '1';
- random_memory_send <= '1';
- VALID_OUT <= counter_for_send_en(10);
- wait_for_data_reset <= '0';
- wait_for_second_board_reset <= '0';
- if (LINK_INFO(1)= '1' or LINK_INFO(2)='1' or mem_diff = '1') and wait_for_data_en = '0' then
- TEST_LINK_FSM_next <= IDLE;
- else
- TEST_LINK_FSM_next <= TEST2;
- end if;
- when TRANSMITION_ERROR =>
- link_debug_i <= "00";
- enable_sec_board_counter <= '0';
- mem_check_ok <= '0';
- random_memory_send <= '0';
- wait_for_data_reset <= '1';
- wait_for_second_board_reset <= '0';
- when others =>
- link_debug_i <= "00";
- enable_sec_board_counter <= '0';
- mem_check_ok <= '0';
- random_memory_send <= '0';
- wait_for_data_reset <= '1';
- wait_for_second_board_reset <= '0';
- TEST_LINK_FSM_next <= IDLE;
- end case;
- end process FSM_TO_TEST_LINK;
-
-
- WAIT_FOR_SECOND_BOARD: up_down_counter
- generic map (
- NUMBER_OF_BITS => 32)
- port map (
- CLK => CLK,
- RESET => wait_for_second_board_reset,
- COUNT_OUT => wait_for_second_board_counter,
- UP_IN => enable_sec_board_counter,
- DOWN_IN => '0');
- wait_for_data_en <= random_memory_send and (not wait_for_data_counter(27));
-
- WAIT_FOR_DATA: up_down_counter
- generic map (
- NUMBER_OF_BITS => 28)
- port map (
- CLK => CLK,
- RESET => wait_for_data_reset,
- COUNT_OUT => wait_for_data_counter,
- UP_IN => wait_for_data_en,
- DOWN_IN => '0');
-
-
- WRITE_ZERO_MEM_ADDRESS: up_down_counter
- generic map (
- NUMBER_OF_BITS => 9)
- port map (
- CLK => CLK,
- RESET => wait_for_second_board_reset,--RESET,
- COUNT_OUT => zero_memory_write_address,
- UP_IN => VALID_IN,
- DOWN_IN => '0');
-
- READ_ZERO_MEM_ADDRESS: up_down_counter
- generic map (
- NUMBER_OF_BITS => 9)
- port map (
- CLK => CLK,
- RESET => wait_for_second_board_reset,--RESET,
- COUNT_OUT => zero_memory_read_address,
- UP_IN => zero_memory_read,
- DOWN_IN => '0');
-
- READ_RAND_MEM_ADDRESS: up_down_counter
- generic map (
- NUMBER_OF_BITS => 9)
- port map (
- CLK => CLK,
- RESET => wait_for_second_board_reset,--RESET,
- COUNT_OUT => random_memory_address,
- UP_IN => random_memory_send,
- DOWN_IN => '0');
-
- SEND_RAND_MEM_EN: up_down_counter
- generic map (
- NUMBER_OF_BITS => 11)
- port map (
- CLK => CLK,
- RESET => wait_for_second_board_reset,--RESET,
- COUNT_OUT => counter_for_send_en,
- UP_IN => '1',
- DOWN_IN => '0');
-
- MEM_RANDOM: mdc_dc_lvl1_dpram_rand
- port map (
- DataInA => (others => '0'),
- DataInB => (others => '0'),
- AddressA => random_memory_address,
- AddressB => (others => '0'),
- ClockA => CLK,
- ClockB => CLK,
- ClockEnA => '1',
- ClockEnB => '0',
- WrA => '0',
- WrB => '0',
- ResetA => '0',
- ResetB => '0',
- QA => rand_memory_data_out,
- QB => open);
-
- MEM_ZERO: mdc_dc_lvl1_dpram_zero
- port map (
- DataInA => DATA_IN(7 downto 0),
- DataInB => (others => '0'),
- AddressA => zero_memory_write_address,
- AddressB => zero_memory_read_address,
- ClockA => CLK,
- ClockB => CLK,
- ClockEnA => '1',
- ClockEnB => '1',
- WrA => VALID_IN,
- WrB => '0',
- ResetA => '0',
- ResetB => '0',
- QA => open,
- QB => zero_memory_data_out);
- START_COMPARISON: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1'or TEST_LINK_FSM_current = IDLE then
- zero_memory_read <= '0';
- elsif rand_memory_data_out = zero_memory_data_out then
- zero_memory_read <= '1';
- else
--- zero_memory_read <= '0';
- zero_memory_read <= zero_memory_read;
- end if;
- end if;
- end process START_COMPARISON;
- MAKE_COMPARISON: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1'or wait_for_second_board_reset = '1' then
- mem_diff <= '1';
- elsif rand_memory_data_out_synch_synch = zero_memory_data_out then
- mem_diff <= '0';
- elsif zero_memory_read_synch = '1' and rand_memory_data_out_synch_synch_synch /= zero_memory_data_out then
- mem_diff <= '1';
--- mem_diff <= '0';
- end if;
- end if;
- end process MAKE_COMPARISON;
-
- SYNCH_DATA: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' or wait_for_second_board_reset = '1' then
- rand_memory_data_out_synch_synch_synch <= (others => '0');
- rand_memory_data_out_synch_synch <= (others => '0');
- rand_memory_data_out_synch <= (others => '0');
- zero_memory_read_synch <= '0';
- else
- rand_memory_data_out_synch_synch_synch<= rand_memory_data_out_synch_synch;
- rand_memory_data_out_synch_synch<= rand_memory_data_out_synch;
- rand_memory_data_out_synch <= rand_memory_data_out;
- zero_memory_read_synch <= zero_memory_read;
- end if;
- end if;
- end process SYNCH_DATA;
-
-
- LINK_DEBUG(3 downto 0) <= zero_memory_data_out(3 downto 0);
- LINK_DEBUG(7 downto 4) <= rand_memory_data_out_synch_synch_synch(3 downto 0);
- LINK_DEBUG(9 downto 8) <= link_debug_i;
- LINK_DEBUG(10) <= VALID_IN;
- LINK_DEBUG(11) <= random_memory_send;
- LINK_DEBUG(12) <= zero_memory_read;
- LINK_DEBUG(14 downto 13) <= LINK_INFO(2 downto 1);
- LINK_DEBUG(15) <= mem_diff;
- DATA_OUT <= rand_memory_data_out & rand_memory_data_out;
-
-end link_test;
+++ /dev/null
-
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSC quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSC quad to the final design requirements.
-
-DEVICE_NAME "LFE2M35E"
-PROTOCOL "G8B10B"
-CH0_MODE "DISABLE"
-CH1_MODE "DISABLE"
-CH2_MODE "SINGLE"
-CH3_MODE "DISABLE"
-PLL_SRC "CORE_TXREFCLK"
-DATARANGE "MEDHIGH"
-CH2_CDR_SRC "CORE_RXREFCLK"
-CH2_DATA_WIDTH "16"
-CH2_REFCK_MULT "20X"
-#REFCLK_RATE 100
-#FPGAINTCLK_RATE 100
-CH2_TDRV_AMP "0"
-CH2_TX_PRE "DISABLE"
-CH2_RTERM_TX "50"
-CH2_RX_EQ "DISABLE"
-CH2_RTERM_RX "50"
-CH2_RX_DCC "DC"
-LOS_THRESHOLD "0"
-PLL_TERM "50"
-PLL_DCC "DC"
-PLL_LOL_SET "0"
-CH2_TX_SB "NORMAL"
-CH2_RX_SB "NORMAL"
-CH2_8B10B "NORMAL"
-COMMA_A "1100000101"
-COMMA_B "0011111010"
-COMMA_M "1111111111"
-CH2_COMMA_ALIGN "DYNAMIC"
-CH2_CTC_BYP "BYPASS"
-CC_MATCH1 "0000000000"
-CC_MATCH2 "0000000000"
-CC_MATCH3 "0100011100"
-CC_MATCH4 "0100011100"
-CC_MATCH_MODE "MATCH_4"
-CC_MIN_IPG "0"
-CCHMARK "4"
-CCLMARK "4"
-OS_REFCK2CORE "1"
-OS_PLLQCLKPORTS "0"
-OS_INT_ALL "0"
-
+++ /dev/null
-
-
---synopsys translate_off
-
-library pcsc_work;
-use pcsc_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSC is
-GENERIC(
- CONFIG_FILE : String := "pcs_for_ecp2m.txt"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-
-end PCSC;
-
-architecture PCSC_arch of PCSC is
-
-component PCSC_sim
-GENERIC(
- CONFIG_FILE : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-end component;
-
-begin
-
-PCSC_sim_inst : PCSC_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE)
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
-
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX => FFC_CK_CORE_RX,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,
- FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,
- FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,
- FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,
- FF_TX_F_CLK => FF_TX_F_CLK,
- FF_TX_H_CLK => FF_TX_H_CLK,
- FF_TX_Q_CLK => FF_TX_Q_CLK,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- OOB_OUT_0 => OOB_OUT_0,
- OOB_OUT_1 => OOB_OUT_1,
- OOB_OUT_2 => OOB_OUT_2,
- OOB_OUT_3 => OOB_OUT_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7
- );
-
-end PCSC_arch;
-
---synopsys translate_on
-
---synopsys translate_off
-library ECP2;
-use ECP2.components.all;
---synopsys translate_on
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity pcs_for_ecp2m is
- GENERIC (USER_CONFIG_FILE : String := "pcs_for_ecp2m.txt");
- port (
- core_txrefclk : in std_logic;
- core_rxrefclk : in std_logic;
- hdinp2, hdinn2 : in std_logic;
- hdoutp2, hdoutn2 : out std_logic;
- ff_rxiclk_ch2, ff_txiclk_ch2, ff_ebrd_clk_2 : in std_logic;
- ff_txdata_ch2 : in std_logic_vector (15 downto 0);
- ff_rxdata_ch2 : out std_logic_vector (15 downto 0);
- ff_tx_k_cntrl_ch2 : in std_logic_vector (1 downto 0);
- ff_rx_k_cntrl_ch2 : out std_logic_vector (1 downto 0);
- ff_rxfullclk_ch2 : out std_logic;
- ff_rxhalfclk_ch2 : out std_logic;
- ff_force_disp_ch2 : in std_logic_vector (1 downto 0);
- ff_disp_sel_ch2 : in std_logic_vector (1 downto 0);
- ff_correct_disp_ch2 : in std_logic_vector (1 downto 0);
- ff_disp_err_ch2, ff_cv_ch2 : out std_logic_vector (1 downto 0);
- ffc_rrst_ch2 : in std_logic;
- ffc_signal_detect_ch2 : in std_logic;
- ffc_enable_cgalign_ch2 : in std_logic;
- ffc_lane_tx_rst_ch2 : in std_logic;
- ffc_lane_rx_rst_ch2 : in std_logic;
- ffc_txpwdnb_ch2 : in std_logic;
- ffc_rxpwdnb_ch2 : in std_logic;
- ffs_rlos_lo_ch2 : out std_logic;
- ffs_rlol_ch2 : out std_logic;
- oob_out_ch2 : out std_logic;
- ffc_macro_rst : in std_logic;
- ffc_quad_rst : in std_logic;
- ffc_trst : in std_logic;
- ff_txfullclk : out std_logic;
- ff_txhalfclk : out std_logic;
- refck2core : out std_logic;
- ffs_plol : out std_logic);
-
-end pcs_for_ecp2m;
-
-architecture pcs_for_ecp2m_arch of pcs_for_ecp2m is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-component PCSC
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_RX_Q_CLK_0 : out std_logic;
- FF_RX_Q_CLK_1 : out std_logic;
- FF_RX_Q_CLK_2 : out std_logic;
- FF_RX_Q_CLK_3 : out std_logic;
- FF_TX_F_CLK : out std_logic;
- FF_TX_H_CLK : out std_logic;
- FF_TX_Q_CLK : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- OOB_OUT_0 : out std_logic;
- OOB_OUT_1 : out std_logic;
- OOB_OUT_2 : out std_logic;
- OOB_OUT_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic
-);
-end component;
- attribute IS_ASB: string;
- attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal fpsc_vlo : std_logic := '0';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-
--- pcs_quad instance
-PCSC_INST : PCSC
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE)
---synopsys translate_on
-port map (
- FFC_CK_CORE_TX => core_txrefclk,
- FFC_CK_CORE_RX => core_rxrefclk,
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
- HDINP0 => fpsc_vlo,
- HDINN0 => fpsc_vlo,
- HDOUTP0 => open,
- HDOUTN0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => fpsc_vlo,
- FF_TXI_CLK_0 => fpsc_vlo,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => open,
- FF_RX_H_CLK_0 => open,
- FF_RX_Q_CLK_0 => open,
- FF_TX_D_0_0 => fpsc_vlo,
- FF_TX_D_0_1 => fpsc_vlo,
- FF_TX_D_0_2 => fpsc_vlo,
- FF_TX_D_0_3 => fpsc_vlo,
- FF_TX_D_0_4 => fpsc_vlo,
- FF_TX_D_0_5 => fpsc_vlo,
- FF_TX_D_0_6 => fpsc_vlo,
- FF_TX_D_0_7 => fpsc_vlo,
- FF_TX_D_0_8 => fpsc_vlo,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => fpsc_vlo,
- FF_TX_D_0_11 => fpsc_vlo,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => open,
- FF_RX_D_0_1 => open,
- FF_RX_D_0_2 => open,
- FF_RX_D_0_3 => open,
- FF_RX_D_0_4 => open,
- FF_RX_D_0_5 => open,
- FF_RX_D_0_6 => open,
- FF_RX_D_0_7 => open,
- FF_RX_D_0_8 => open,
- FF_RX_D_0_9 => open,
- FF_RX_D_0_10 => open,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
- FFC_RRST_0 => fpsc_vlo,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => fpsc_vlo,
- FFC_LANE_RX_RST_0 => fpsc_vlo,
- FFC_TXPWDNB_0 => fpsc_vlo,
- FFC_RXPWDNB_0 => fpsc_vlo,
- FFS_RLOS_LO_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_LS_SYNC_STATUS_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_RLOL_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- OOB_OUT_0 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- HDOUTP1 => open,
- HDOUTN1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_RX_Q_CLK_1 => open,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- OOB_OUT_1 => open,
- HDINP2 => hdinp2,
- HDINN2 => hdinn2,
- HDOUTP2 => hdoutp2,
- HDOUTN2 => hdoutn2,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => ff_rxiclk_ch2,
- FF_TXI_CLK_2 => ff_txiclk_ch2,
- FF_EBRD_CLK_2 => ff_ebrd_clk_2,
- FF_RX_F_CLK_2 => ff_rxfullclk_ch2,
- FF_RX_H_CLK_2 => ff_rxhalfclk_ch2,
- FF_RX_Q_CLK_2 => open,
- FF_TX_D_2_0 => ff_txdata_ch2(0),
- FF_TX_D_2_1 => ff_txdata_ch2(1),
- FF_TX_D_2_2 => ff_txdata_ch2(2),
- FF_TX_D_2_3 => ff_txdata_ch2(3),
- FF_TX_D_2_4 => ff_txdata_ch2(4),
- FF_TX_D_2_5 => ff_txdata_ch2(5),
- FF_TX_D_2_6 => ff_txdata_ch2(6),
- FF_TX_D_2_7 => ff_txdata_ch2(7),
- FF_TX_D_2_8 => ff_tx_k_cntrl_ch2(0),
- FF_TX_D_2_9 => ff_force_disp_ch2(0),
- FF_TX_D_2_10 => ff_disp_sel_ch2(0),
- FF_TX_D_2_11 => ff_correct_disp_ch2(0),
- FF_TX_D_2_12 => ff_txdata_ch2(8),
- FF_TX_D_2_13 => ff_txdata_ch2(9),
- FF_TX_D_2_14 => ff_txdata_ch2(10),
- FF_TX_D_2_15 => ff_txdata_ch2(11),
- FF_TX_D_2_16 => ff_txdata_ch2(12),
- FF_TX_D_2_17 => ff_txdata_ch2(13),
- FF_TX_D_2_18 => ff_txdata_ch2(14),
- FF_TX_D_2_19 => ff_txdata_ch2(15),
- FF_TX_D_2_20 => ff_tx_k_cntrl_ch2(1),
- FF_TX_D_2_21 => ff_force_disp_ch2(1),
- FF_TX_D_2_22 => ff_disp_sel_ch2(1),
- FF_TX_D_2_23 => ff_correct_disp_ch2(1),
- FF_RX_D_2_0 => ff_rxdata_ch2(0),
- FF_RX_D_2_1 => ff_rxdata_ch2(1),
- FF_RX_D_2_2 => ff_rxdata_ch2(2),
- FF_RX_D_2_3 => ff_rxdata_ch2(3),
- FF_RX_D_2_4 => ff_rxdata_ch2(4),
- FF_RX_D_2_5 => ff_rxdata_ch2(5),
- FF_RX_D_2_6 => ff_rxdata_ch2(6),
- FF_RX_D_2_7 => ff_rxdata_ch2(7),
- FF_RX_D_2_8 => ff_rx_k_cntrl_ch2(0),
- FF_RX_D_2_9 => ff_disp_err_ch2(0),
- FF_RX_D_2_10 => ff_cv_ch2(0),
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => ff_rxdata_ch2(8),
- FF_RX_D_2_13 => ff_rxdata_ch2(9),
- FF_RX_D_2_14 => ff_rxdata_ch2(10),
- FF_RX_D_2_15 => ff_rxdata_ch2(11),
- FF_RX_D_2_16 => ff_rxdata_ch2(12),
- FF_RX_D_2_17 => ff_rxdata_ch2(13),
- FF_RX_D_2_18 => ff_rxdata_ch2(14),
- FF_RX_D_2_19 => ff_rxdata_ch2(15),
- FF_RX_D_2_20 => ff_rx_k_cntrl_ch2(1),
- FF_RX_D_2_21 => ff_disp_err_ch2(1),
- FF_RX_D_2_22 => ff_cv_ch2(1),
- FF_RX_D_2_23 => open,
- FFC_RRST_2 => ffc_rrst_ch2,
- FFC_SIGNAL_DETECT_2 => ffc_signal_detect_ch2,
- FFC_ENABLE_CGALIGN_2 => ffc_enable_cgalign_ch2,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFS_PCIE_DONE_2 => open,
- FFS_PCIE_CON_2 => open,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => ffc_lane_tx_rst_ch2,
- FFC_LANE_RX_RST_2 => ffc_lane_rx_rst_ch2,
- FFC_TXPWDNB_2 => ffc_txpwdnb_ch2,
- FFC_RXPWDNB_2 => ffc_rxpwdnb_ch2,
- FFS_RLOS_LO_2 => ffs_rlos_lo_ch2,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- FFS_RLOL_2 => ffs_rlol_ch2,
- OOB_OUT_2 => oob_out_ch2,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- HDOUTP3 => open,
- HDOUTN3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_RX_Q_CLK_3 => open,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- OOB_OUT_3 => open,
- SCIWDATA0 => fpsc_vlo,
- SCIWDATA1 => fpsc_vlo,
- SCIWDATA2 => fpsc_vlo,
- SCIWDATA3 => fpsc_vlo,
- SCIWDATA4 => fpsc_vlo,
- SCIWDATA5 => fpsc_vlo,
- SCIWDATA6 => fpsc_vlo,
- SCIWDATA7 => fpsc_vlo,
- SCIADDR0 => fpsc_vlo,
- SCIADDR1 => fpsc_vlo,
- SCIADDR2 => fpsc_vlo,
- SCIADDR3 => fpsc_vlo,
- SCIADDR4 => fpsc_vlo,
- SCIADDR5 => fpsc_vlo,
- SCIRDATA0 => open,
- SCIRDATA1 => open,
- SCIRDATA2 => open,
- SCIRDATA3 => open,
- SCIRDATA4 => open,
- SCIRDATA5 => open,
- SCIRDATA6 => open,
- SCIRDATA7 => open,
- SCIENAUX => fpsc_vlo,
- SCISELAUX => fpsc_vlo,
- SCIRD => fpsc_vlo,
- SCIWSTN => fpsc_vlo,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_MACRO_RST => ffc_macro_rst,
- FFC_QUAD_RST => ffc_quad_rst,
- FFC_TRST => ffc_trst,
- FF_TX_F_CLK => ff_txfullclk,
- FF_TX_H_CLK => ff_txhalfclk,
- FF_TX_Q_CLK => open,
- REFCK2CORE => refck2core,
- CIN0 => cin(0),
- CIN1 => cin(1),
- CIN2 => cin(2),
- CIN3 => cin(3),
- CIN4 => cin(4),
- CIN5 => cin(5),
- CIN6 => cin(6),
- CIN7 => cin(7),
- CIN8 => cin(8),
- CIN9 => cin(9),
- CIN10 => cin(10),
- CIN11 => cin(11),
- COUT0 => cout(0),
- COUT1 => cout(1),
- COUT2 => cout(2),
- COUT3 => cout(3),
- COUT4 => cout(4),
- COUT5 => cout(5),
- COUT6 => cout(6),
- COUT7 => cout(7),
- COUT8 => cout(8),
- COUT9 => cout(9),
- COUT10 => cout(10),
- COUT11 => cout(11),
- COUT12 => cout(12),
- COUT13 => cout(13),
- COUT14 => cout(14),
- COUT15 => cout(15),
- COUT16 => cout(16),
- COUT17 => cout(17),
- COUT18 => cout(18),
- COUT19 => cout(19),
- FFS_PLOL => ffs_plol);
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-
-end pcs_for_ecp2m_arch ;
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-
-
-entity rich is
- port(
- CLK40M : in std_logic;
- CLK100M_P : in std_logic;
- CLK100M_N : in std_logic;
- FPGA_LED : out std_logic_vector(4 downto 0);
- SD_RXD_P : in std_logic;
- SD_RXD_N : in std_logic;
- SD_TXD_P : out std_logic;
- SD_TXD_N : out std_logic;
- SD_MD : inout std_logic_vector(2 downto 0);
- SD_TXDIS : out std_logic;
- SD_LOS : in std_logic;
- SD_TXFAULT : out std_logic;
- SD_RATE : out std_logic;
- ONEWIRE : inout std_logic;
- FPGA_EXP : out std_logic_vector(15 downto 0)
- );
-end entity;
-
-architecture rich of rich is
-
- component pcs_for_ecp2m
- port(
- core_txrefclk : in std_logic;
- core_rxrefclk : in std_logic;
- hdinp2 : in std_logic;
- hdinn2 : in std_logic;
- ff_rxiclk_ch2 : in std_logic;
- ff_txiclk_ch2 : in std_logic;
- ff_ebrd_clk_2 : in std_logic;
- ff_txdata_ch2 : in std_logic_vector(15 downto 0);
- ff_tx_k_cntrl_ch2 : in std_logic_vector(1 downto 0);
- ff_force_disp_ch2 : in std_logic_vector(1 downto 0);
- ff_disp_sel_ch2 : in std_logic_vector(1 downto 0);
- ff_correct_disp_ch2 : in std_logic_vector(1 downto 0);
- ffc_rrst_ch2 : in std_logic;
- ffc_signal_detect_ch2 : in std_logic;
- ffc_enable_cgalign_ch2 : in std_logic;
- ffc_lane_tx_rst_ch2 : in std_logic;
- ffc_lane_rx_rst_ch2 : in std_logic;
- ffc_txpwdnb_ch2 : in std_logic;
- ffc_rxpwdnb_ch2 : in std_logic;
- ffc_macro_rst : in std_logic;
- ffc_quad_rst : in std_logic;
- ffc_trst : in std_logic;
- hdoutp2 : out std_logic;
- hdoutn2 : out std_logic;
- ff_rxdata_ch2 : out std_logic_vector(15 downto 0);
- ff_rx_k_cntrl_ch2 : out std_logic_vector(1 downto 0);
- ff_rxfullclk_ch2 : out std_logic;
- ff_rxhalfclk_ch2 : out std_logic;
- ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0);
- ff_cv_ch2 : OUT std_logic_vector(1 downto 0);
- ffs_rlos_lo_ch2 : OUT std_logic;
- ffs_rlol_ch2 : OUT std_logic;
- oob_out_ch2 : OUT std_logic;
- ff_txfullclk : OUT std_logic;
- ff_txhalfclk : OUT std_logic;
- refck2core : OUT std_logic;
- ffs_plol : OUT std_logic
- );
- END COMPONENT;
-
- component flexi_PCS_channel_synch
- port (
- SYSTEM_CLK : in std_logic;
- TX_CLK : in std_logic;
- RX_CLK : in std_logic;
- RESET : in std_logic;
- RXD : in std_logic_vector(15 downto 0);
- RXD_SYNCH : out std_logic_vector(15 downto 0);
- RX_K : in std_logic_vector(1 downto 0);
- RX_RST : out std_logic;
- CV : in std_logic_vector(1 downto 0);
- TXD : in std_logic_vector(15 downto 0);
- TXD_SYNCH : out std_logic_vector(15 downto 0);
- TX_K : out std_logic_vector(1 downto 0);
- DATA_VALID_IN : in std_logic;
- DATA_VALID_OUT : out std_logic;
- FLEXI_PCS_STATUS : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_ERROR_OUT : out std_logic_vector(2 downto 0);
- MED_READ_IN : in std_logic);
- end component;
-
- component flexi_PCS_synch
- generic (
- HOW_MANY_CHANNELS : positive);
- port (
- SYSTEM_CLK : in std_logic;
- CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
- RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- RESET : in std_logic;
- RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
- MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
- MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0);
- MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0)
- );
- end component;
-
- component DCS
--- synthesis translate_off
- --sim
- generic (
- DCSMODE : string := "POS");
--- synthesis translate_on
- port (
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- SEL : in std_logic;
- DCSOUT : out std_logic);
- end component;
-
- component link_test
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_OUT : out std_logic_vector(15 downto 0);
- VALID_IN : in std_logic;
- VALID_OUT : out std_logic;
- LINK_DEBUG : out std_logic_vector(31 downto 0);
- LINK_INFO : in std_logic_vector(15 downto 0));
- end component;
-
- signal core_txrefclk_i : std_logic;
- signal core_rxrefclk_i : std_logic;
- signal hdinp2_i : std_logic;
- signal hdinn2_i : std_logic;
- signal ff_rxiclk_ch2_i : std_logic;
- signal ff_txiclk_ch2_i : std_logic;
- signal ff_ebrd_clk_2_i : std_logic;
- signal ff_txdata_ch2_i : std_logic_vector(15 downto 0);
- signal ff_tx_k_cntrl_ch2_i : std_logic_vector(1 downto 0);
- signal ff_force_disp_ch2_i : std_logic_vector(1 downto 0);
- signal ff_disp_sel_ch2_i : std_logic_vector(1 downto 0);
- signal ff_correct_disp_ch2_i : std_logic_vector(1 downto 0);
- signal ffc_rrst_ch2_i : std_logic;
- signal ffc_signal_detect_ch2_i : std_logic;
- signal ffc_enable_cgalign_ch2_i : std_logic;
- signal ffc_lane_tx_rst_ch2_i : std_logic;
- signal ffc_lane_rx_rst_ch2_i : std_logic;
- signal ffc_txpwdnb_ch2_i : std_logic;
- signal ffc_rxpwdnb_ch2_i : std_logic;
- signal ffc_macro_rst_i : std_logic;
- signal ffc_quad_rst_i : std_logic;
- signal ffc_trst_i : std_logic;
- signal hdoutp2_i : std_logic;
- signal hdoutn2_i : std_logic;
- signal ff_rxdata_ch2_i : std_logic_vector(15 downto 0);
- signal ff_rx_k_cntrl_ch2_i : std_logic_vector(1 downto 0);
- signal ff_rxfullclk_ch2_i : std_logic;
- signal ff_rxhalfclk_ch2_i : std_logic;
- signal ff_disp_err_ch2_i : std_logic_vector(1 downto 0);
- signal ff_cv_ch2_i : std_logic_vector(1 downto 0);
- signal ffs_rlos_lo_ch2_i : std_logic;
- signal ffs_rlol_ch2_i : std_logic;
- signal oob_out_ch2_i : std_logic;
- signal ff_txfullclk_i : std_logic;
- signal ff_txhalfclk_i : std_logic;
- signal refck2core_i : std_logic;
- signal ffs_plol_i : std_logic;
- -- reset
- signal global_reset_cnt : std_logic_vector(3 downto 0);
- signal global_reset_i : std_logic:='0';
- signal counter : std_logic_vector(31 downto 0);
- -- dcs_clock
- signal dcs_clk_out : std_logic;
- signal not_lock : std_logic;
- --synch
- signal data_valid_out_i : std_logic;
- signal flexi_PCS_status_i : std_logic_vector(15 downto 0);
- signal ffc_lane_rx_rst_ch2_start : std_logic;
- signal ffc_lane_rx_rst_ch2_resync : std_logic;
- --test
- signal data_out_i : std_logic_vector(15 downto 0);
- signal data_in_i : std_logic_vector(15 downto 0);
- signal data_valid_in_i : std_logic;
- signal test_link_debug : std_logic_vector(31 downto 0);
- signal test_link_info : std_logic_vector(15 downto 0);
-begin -- rich
- RESET_COUNTER_a : process (CLK40M)
- begin
- if rising_edge(CLK40M) then
- if counter < x"0ffffffe" then
- counter <= counter +1;
- else
- counter <= counter;
- end if;
- end if;
- end process RESET_COUNTER_a;
-
- ffc_quad_rst_i <= '1' when (counter > x"0000ffff" and counter < x"0001000f") else '0';
- ffc_lane_tx_rst_ch2_i <= '1' when (counter > x"00ffffff" and counter < x"0f00000f") else '0';
- ffc_lane_rx_rst_ch2_start <= '1' when (counter > x"00ffffff" and counter < x"0f00000f") else '0';
-
- REF_CLK_SELECT: DCS
- -- synthesis translate_off
-
- generic map (--no_sim--
- DCSMODE => "POS")--no_sim--
- -- synthesis translate_on
- port map (
- CLK0 => ff_rxhalfclk_ch2_i,
- CLK1 => CLK40M,
- SEL => ffs_rlol_ch2_i,--hub_register_0a_i(0),--'0',--switch_rx_clk,
- DCSOUT => dcs_clk_out);
-
- serdes : pcs_for_ecp2m port map(
- core_txrefclk => CLK40M,
- core_rxrefclk => dcs_clk_out,--CLK40M,--ff_rxhalfclk_ch2_i,
- hdinp2 => SD_RXD_P,
- hdinn2 => SD_RXD_N,
- hdoutp2 => SD_TXD_P,
- hdoutn2 => SD_TXD_N,
- ff_rxiclk_ch2 => ff_rxhalfclk_ch2_i,
- ff_txiclk_ch2 => ff_txhalfclk_i,
- ff_ebrd_clk_2 => open,--ff_ebrd_clk_2_i,
- ff_txdata_ch2 => ff_txdata_ch2_i,
- ff_rxdata_ch2 => ff_rxdata_ch2_i,
- ff_tx_k_cntrl_ch2 => ff_tx_k_cntrl_ch2_i,
- ff_rx_k_cntrl_ch2 => ff_rx_k_cntrl_ch2_i,
- ff_rxfullclk_ch2 => ff_rxfullclk_ch2_i,
- ff_rxhalfclk_ch2 => ff_rxhalfclk_ch2_i,
- ff_force_disp_ch2 => "00",--ff_force_disp_ch2_i,
- ff_disp_sel_ch2 => "00",--ff_disp_sel_ch2_i,
- ff_correct_disp_ch2 => ff_correct_disp_ch2_i,
- ff_disp_err_ch2 => ff_disp_err_ch2_i,
- ff_cv_ch2 => ff_cv_ch2_i,
- ffc_rrst_ch2 => '0',--ffc_rrst_ch2_i,
- ffc_signal_detect_ch2 => '1',--ffc_signal_detect_ch2_i,
- ffc_enable_cgalign_ch2 => '1',--ffc_enable_cgalign_ch2_i,
- ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2_i,
- ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2_i,
- ffc_txpwdnb_ch2 => '1',--ffc_txpwdnb_ch2_i,
- ffc_rxpwdnb_ch2 => '1',--ffc_rxpwdnb_ch2_i,
- ffs_rlos_lo_ch2 => ffs_rlos_lo_ch2_i,
- ffs_rlol_ch2 => ffs_rlol_ch2_i,
- oob_out_ch2 => oob_out_ch2_i,
- ffc_macro_rst => '0',--ffc_macro_rst_i,
- ffc_quad_rst => global_reset_i,--ffc_quad_rst_i,
- ffc_trst => '0',--ffc_trst_i,
- ff_txfullclk => ff_txfullclk_i,
- ff_txhalfclk => ff_txhalfclk_i,
- refck2core => refck2core_i,
- ffs_plol => ffs_plol_i
- );
- ffc_lane_rx_rst_ch2_i <= ffc_lane_rx_rst_ch2_resync or ffc_lane_rx_rst_ch2_start;
-
- SYNCH: flexi_PCS_channel_synch
- port map (
- SYSTEM_CLK => CLK40M,
- TX_CLK => ff_txhalfclk_i,
- RX_CLK => ff_rxhalfclk_ch2_i,
- RESET => global_reset_i,
- RXD => ff_rxdata_ch2_i,
- RXD_SYNCH => data_in_i,
- RX_K => ff_rx_k_cntrl_ch2_i,
- RX_RST => ffc_lane_rx_rst_ch2_resync,
- CV => ff_cv_ch2_i,
- TXD => data_out_i,
- TXD_SYNCH => ff_txdata_ch2_i,
- TX_K => ff_tx_k_cntrl_ch2_i,
- DATA_VALID_IN => data_valid_in_i,
- DATA_VALID_OUT => data_valid_out_i,
- FLEXI_PCS_STATUS => flexi_pcs_status_i,
- MED_PACKET_NUM_OUT => open,
- MED_ERROR_OUT => open,
- MED_READ_IN => '1');
-
- test_link_info(2 downto 0) <= ff_cv_ch2_i & flexi_pcs_status_i(2);
-
- LINK_TETS_INST: link_test
- port map (
- CLK => CLK40M,
- RESET => global_reset_i,
- DATA_IN => data_in_i,
- DATA_OUT => data_out_i,
- VALID_IN => data_valid_out_i,
- VALID_OUT => data_valid_in_i,
- LINK_DEBUG => test_link_debug,
- LINK_INFO => test_link_info);
-
-
-
- GLOBAL_RESET: process(CLK40M,global_reset_cnt,global_reset_i)
- begin
- if rising_edge(CLK40M) then
- if global_reset_cnt < x"e" or global_reset_cnt =x"f" then
- global_reset_cnt <= global_reset_cnt + 1;
- global_reset_i <= '1';
- elsif global_reset_cnt = x"e" then
- global_reset_i <= '0';
- global_reset_cnt <= x"e";
- else
- global_reset_i <= '0';
- global_reset_cnt <= global_reset_cnt;
- end if;
- end if;
- end process GLOBAL_RESET;
-
--- ff_tx_k_cntrl_ch2_i <= "10";
--- ff_txdata_ch2_i <= x"bcc5";
- FPGA_LED(4 downto 1) <= "1010";
- FPGA_LED(0) <= not flexi_pcs_status_i(2);
-
- FPGA_EXP <= test_link_debug(15 downto 0);
-
--- FPGA_EXP(0) <= CLK40M;
--- FPGA_EXP(1) <= ff_rxhalfclk_ch2_i;
--- FPGA_EXP(2) <= dcs_clk_out;
--- FPGA_EXP(3) <= ff_cv_ch2_i(0);
--- FPGA_EXP(4) <= ff_cv_ch2_i(1);
--- FPGA_EXP(5) <= ff_rx_k_cntrl_ch2_i(0);
--- FPGA_EXP(6) <= ff_rx_k_cntrl_ch2_i(1);
--- FPGA_EXP(7) <= ff_disp_err_ch2_i(0);
--- FPGA_EXP(8) <= ff_disp_err_ch2_i(1);
--- FPGA_EXP(9) <= ffs_rlos_lo_ch2_i;
--- FPGA_EXP(10)<= ffs_rlol_ch2_i;
--- FPGA_EXP(11)<= global_reset_i;
--- FPGA_EXP(12)<= ffs_plol_i;
--- FPGA_EXP(13) <= not flexi_pcs_status_i(2);
--- FPGA_EXP(14) <= ffc_lane_rx_rst_ch2_i;
-
-end rich;
+++ /dev/null
-
-
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCS quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCS quad to the final design requirements.
-# channel_0 is in "8b10b" mode
-# channel_1 is in "8b10b" mode
-# channel_2 is in "8b10b" mode
-# channel_3 is in "8b10b" mode
-
-ch0 13 03 # Powerup Channel
-ch0 00 00
-ch1 13 03 # Powerup Channel
-ch1 00 00
-ch2 13 03 # Powerup Channel
-ch2 00 00
-ch3 13 03 # Powerup Channel
-ch3 00 00
-quad 00 00
-quad 01 E4
-quad 28 40 # Reference clock multiplier
-quad 29 11 # FPGA sourced refclk
-quad 02 00 # ref_pclk source is ch0
-quad 04 00 # MCA enable 4 channels
-
-quad 18 10 # 8b10b Mode
-quad 14 FF # Word Alignment Mask
-quad 15 7c # +ve K
-quad 16 b6 # -ve K
-quad 17 36
-
-quad 19 8C # Enable word_align_en port, FPGA bus width is 16-bit/20-bit
-
-#quad 1e 01 #SOP EOP only 1 word 24.04.2008
-#quad 1f ff
-#quad 20 7c
-#quad 21 7c
-#quad 22 5
-#quad 23 7c
-#quad 24 7c
-#quad 25 5
-
-
-ch0 14 90 # 16% pre-emphasis
-ch0 15 10 # +6dB equalization
-ch1 14 90 # 16% pre-emphasis
-ch1 15 10 # +6dB equalization
-ch2 14 90 # 16% pre-emphasis
-ch2 15 10 # +6dB equalization
-ch3 14 90 # 16% pre-emphasis
-ch3 15 10 # +6dB equalization
-
-# These lines must appear last in the autoconfig file. These lines apply the correct
-# reset sequence to the PCS block upon bitstream configuration
-quad 41 00 # de-assert serdes_rst
-quad 40 ff # assert datapath reset for all channels
-quad 40 00 # de-assert datapath reset for all channels
-
-
-
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-entity up_down_counter is
-
- generic (
- NUMBER_OF_BITS : positive
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic;
- DOWN_IN : in std_logic
- );
-
-end up_down_counter;
-
-architecture up_down_counter of up_down_counter is
-
-signal counter: std_logic_vector (NUMBER_OF_BITS-1 downto 0);
-
-begin
-
- COUNTER_PROC : process (CLK, RESET, UP_IN, DOWN_IN)
- begin
- if rising_edge(clk) then
- if RESET = '1' then
- counter <= (others => '0');
- elsif UP_IN = '1' and DOWN_IN = '0' then
- counter <= counter + 1;
- elsif UP_IN = '0' and DOWN_IN = '1' then
- counter <= counter - 1;
- else
- counter <= counter;
- end if;
- end if;
- end process COUNTER_PROC;
-
- COUNT_OUT <= counter;
-
-end up_down_counter;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library ieee;
-library work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.all;
-
-entity Sfp_Interface is
- generic (
- I2C_SPEED : std_logic_vector(15 downto 0) := x"0200"
-------------------------------------------------------------------------------------
--- I2C_SPEED = 100 MHz / working frequency |
--- max working frequency 400 kHz |
--- Example: for 400 kHz working frequency => I2C_SPEED = FPGA freq / Working freq |
--- I2C_SPEED = 100MHz / 400kHz |
--- I2C_SPEED = 250 = x"FA" |
-------------------------------------------------------------------------------------
- );
- port(
- CLK_IN : in std_logic; -- System clock
- RST_IN : in std_logic; -- System reset
--- host side
- START_PULSE : in std_logic; -- System start pulse
- DEVICE_ADDRESS : in std_logic_vector(7 downto 0) :=x"06"; -- Device address input: x"06" for SFP_Interface
- DATA_OUT : out std_logic_vector(15 downto 0); -- Data output from optical transmitter
- READ_DONE : out std_logic; -- Reading process done
- SFP_ADDRESS : in std_logic_vector(7 downto 0); -- SFP address
----------------------------------------------------------------
--- SFP_ADDRESS values: |
---------------------------------------------------------------|
--- x"60" => Internally measured module temperature |
--- x"66" => Measured TX optical output power |
--- x"68" => Measured RX optical input power |
----------------------------------------------------------------
--- optical transceiver side
- SCL : out std_logic_vector(15 downto 0); -- I2C Serial clock I/O
- SDA : inout std_logic_vector(15 downto 0); -- I2C Serial data I/O
- DEBUG : out std_logic_vector(31 downto 0)
- );
-
-end Sfp_Interface;
--------------------------------------------------------------------------------
-
-architecture behavioral of Sfp_Interface is
--------------------------------------------------------------------------------
--- Internal Lines
--------------------------------------------------------------------------------
- signal scl_int : std_logic := '1';
- signal sda_int : std_logic := '1';
- signal sda_int_mem : std_logic := '1';
- signal byte_2_send : std_logic_vector(7 downto 0) := x"00";
- signal byte_2_send_mem : std_logic_vector(7 downto 0) := x"00";
- signal byte_2_read : std_logic_vector(15 downto 0) := x"0000";
- signal data_out_int : std_logic_vector(15 downto 0) := x"0000";
- signal data_out_int_mem : std_logic_vector(15 downto 0) := x"0000";
- signal bit_read : std_logic := '0';
- signal bit_read_mem : std_logic := '0';
- signal read_done_int : std_logic := '0';
---
- signal en_reset_cnt : std_logic := '0';
- signal stop_reset_cnt : std_logic := '0';
- signal rst_reset_cnt : std_logic := '0';
- signal reset_cnt : std_logic_vector(3 downto 0) := "0001";
- signal reset_done : std_logic := '0';
- signal reset_done_mem : std_logic := '0';
---
- signal en_bit_cnt : std_logic := '0';
- signal stop_bit_cnt : std_logic := '0';
- signal rst_bit_cnt : std_logic := '0';
- signal bit_cnt : std_logic_vector(5 downto 0) := "000000";
---
- signal stop_fre_cnt : std_logic := '0';
- signal rst_fre_cnt : std_logic := '0';
- signal fre_cnt : std_logic_vector(15 downto 0) := x"0000";
---
- signal en_shift_reg : std_logic := '0';
- signal en_FSM : std_logic := '0';
- signal sfp_address_i : std_logic_vector(7 downto 0) := x"00";
- signal device_address_i : std_logic_vector(7 downto 0) := x"06";
- signal start_pulse_i : std_logic := '0';
---
- signal debug_signal : std_logic_vector(31 downto 0) := x"00000000";
- signal select_line : integer range 0 to 15;
--------------------------------------------------------------------------------
- type STATES is (IDLE, RESET_A, RESET_B, RESET_C, RESET_D, START_A, START_B,
- START_C, START_D, STOP_A, STOP_B, STOP_C, STOP_D, SEND_BYTE_A,
- SEND_BYTE_B, SEND_BYTE_C, SEND_BYTE_D, READ_BYTE_A, READ_BYTE_B,
- READ_BYTE_C, READ_BYTE_D, SEND_ACK_A, SEND_ACK_B, SEND_ACK_C,
- SEND_ACK_D, READ_ACK_A, READ_ACK_B, READ_ACK_C, READ_ACK_D);
- signal STATE_CURRENT : STATES;
- signal STATE_NEXT : STATES;
--------------------------------------------------------------------------------
-
-
--------------------------------------------------------------------------------
-begin
- stop_reset_cnt <= rst_in or rst_reset_cnt;
- stop_bit_cnt <= rst_in or rst_bit_cnt;
- stop_fre_cnt <= rst_in or rst_fre_cnt;
- select_line <= to_integer(unsigned(DEVICE_ADDRESS(3 downto 0)));
-
- proc_counters : process begin
- wait until rising_edge(CLK_IN);
- if stop_fre_cnt = '1' then
- fre_cnt <= x"0000";
- else
- fre_cnt <= std_logic_vector(unsigned(fre_cnt)+1);
- end if;
-
- if stop_bit_cnt = '1' then
- bit_cnt <= "000000";
- elsif en_bit_cnt = '1' then
- bit_cnt <= std_logic_vector(unsigned(bit_cnt)+1);
- end if;
-
- if stop_reset_cnt = '1' then
- reset_cnt <= "0000";
- elsif en_reset_cnt = '1' then
- reset_cnt <= std_logic_vector(unsigned(reset_cnt)+1);
- end if;
-
-
- end process;
-
- Frequency_Division : process (CLK_IN, RST_IN, fre_cnt)
- begin
- if rising_edge(CLK_IN) then
- if RST_IN = '1' then
- en_FSM <= '0';
- rst_fre_cnt <= '0';
- elsif fre_cnt = I2C_SPEED then
- en_FSM <= '1';
- rst_fre_cnt <= '1';
- else
- en_FSM <= '0';
- rst_fre_cnt <= '0';
- end if;
- end if;
- end process Frequency_Division;
--------------------------------------------------------------------------------
- Address_Assingment : process (CLK_IN, RST_IN, START_PULSE)
- begin
- if rising_edge(CLK_IN) then
- if RST_IN = '1' then
- sfp_address_i <= x"00";
- device_address_i <= x"00";
- start_pulse_i <= '0';
- elsif START_PULSE = '1' then
- sfp_address_i <= SFP_ADDRESS;
- device_address_i <= DEVICE_ADDRESS;
- start_pulse_i <= START_PULSE;
- else
- start_pulse_i <= '0';
- end if;
- end if;
- end process Address_Assingment;
--------------------------------------------------------------------------------
- Syncronising : process (CLK_IN, RST_IN)
- begin
- if rising_edge(CLK_IN) then
- if RST_IN = '1' then
- STATE_CURRENT <= IDLE;
- DATA_OUT <= x"0000";
- READ_DONE <= '0';
- data_out_int_mem <= x"0000";
- byte_2_send_mem <= x"00";
- reset_done_mem <= '0';
- bit_read_mem <= '0';
- SCL <= (others => 'Z');
- SDA <= (others => 'Z');
- sda_int_mem <= '1';
- DEBUG <= x"00000000";
- else
- STATE_CURRENT <= STATE_NEXT;
- DATA_OUT <= data_out_int;
- READ_DONE <= read_done_int;
- data_out_int_mem <= data_out_int;
- byte_2_send_mem <= byte_2_send;
- reset_done_mem <= reset_done;
- sda_int_mem <= sda_int;
- bit_read_mem <= bit_read;
- SCL <= (others => scl_int);
- SDA <= (others => sda_int);
- DEBUG <= debug_signal;
- end if;
- end if;
- end process Syncronising;
--------------------------------------------------------------------------------
- Shift_Register : process (CLK_IN, RST_IN, en_shift_reg)
- begin
- if rising_edge(CLK_IN) then
- if RST_IN = '1' then
- byte_2_read <= x"0000";
- elsif en_shift_reg = '1' then
- byte_2_read <= byte_2_read(14 downto 0) & bit_read;
- end if;
- end if;
- end process Shift_Register;
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
--- The State Machine
--------------------------------------------------------------------------------
- State_Decoder : process (start_pulse_i, device_address_i, STATE_CURRENT,
- reset_cnt, reset_done, reset_done_mem, bit_cnt, SDA,
- byte_2_send_mem, byte_2_read, data_out_int_mem,
- en_FSM, sda_int_mem, sfp_address_i, bit_read_mem)
- begin
- en_reset_cnt <= '0';
- rst_reset_cnt <= '0';
- en_bit_cnt <= '0';
- rst_bit_cnt <= '0';
- en_shift_reg <= '0';
- sda_int <= 'Z';
- scl_int <= 'Z';
- byte_2_send <= byte_2_send_mem;
- data_out_int <= data_out_int_mem;
- reset_done <= reset_done_mem;
- bit_read <= bit_read_mem;
- read_done_int <= '0';
- STATE_NEXT <= STATE_CURRENT;
-
- case (STATE_CURRENT) is
---IDLE
- when IDLE =>
- if start_pulse_i = '1' and reset_done = '0' then
- STATE_NEXT <= RESET_C;
- elsif start_pulse_i = '1' and reset_done = '1' then
- STATE_NEXT <= START_A;
- else
- STATE_NEXT <= IDLE;
- end if;
- debug_signal <= x"00000001";
---RESET
- when RESET_A =>
- scl_int <= '0';
- sda_int <= '1';
- if en_FSM = '1' then
- STATE_NEXT <= RESET_B;
- end if;
- debug_signal <= x"00000002";
---
- when RESET_B =>
- scl_int <= '0';
- sda_int <= '1';
- if reset_cnt = "1000" and en_FSM = '1' then
- STATE_NEXT <= START_C;
- rst_reset_cnt <= '1';
- reset_done <= '1';
- elsif en_FSM = '1' then
- STATE_NEXT <= RESET_C;
- en_reset_cnt <= '1';
- end if;
- debug_signal <= x"00000003";
---
- when RESET_C =>
- scl_int <= '1';
- sda_int <= '1';
- if en_FSM = '1' then
- STATE_NEXT <= RESET_D;
- end if;
- debug_signal <= x"00000004";
---
- when RESET_D =>
- scl_int <= '1';
- sda_int <= '1';
- if en_FSM = '1' then
- STATE_NEXT <= RESET_A;
- end if;
- debug_signal <= x"00000005";
---START
- when START_A =>
- scl_int <= '0';
- sda_int <= '1';
- if en_FSM = '1' then
- STATE_NEXT <= START_B;
- end if;
- debug_signal <= x"00000006";
---
- when START_B =>
- scl_int <= '0';
- sda_int <= '1';
- if en_FSM = '1' then
- STATE_NEXT <= START_C;
- end if;
- debug_signal <= x"00000007";
---
- when START_C =>
- scl_int <= '1';
- sda_int <= '1';
- if en_FSM = '1' then
- STATE_NEXT <= START_D;
- end if;
- debug_signal <= x"00000008";
---
- when START_D =>
- scl_int <= '1';
- sda_int <= '0';
- if bit_cnt = "010011" and en_FSM = '1' then
- byte_2_send <= x"A3";
- STATE_NEXT <= SEND_BYTE_A;
- en_bit_cnt <= '1';
- elsif bit_cnt = "000000" and en_FSM = '1' then
- byte_2_send <= x"A2";
- STATE_NEXT <= SEND_BYTE_A;
- en_bit_cnt <= '1';
- elsif en_FSM = '0' then
- STATE_NEXT <= STATE_CURRENT;
- else
- byte_2_send <= x"00";
- STATE_NEXT <= IDLE;
- end if;
- debug_signal <= x"00000009";
---STOP
- when STOP_A =>
- scl_int <= '0';
- sda_int <= '0';
- if en_FSM = '1' then
- STATE_NEXT <= STOP_B;
- end if;
- debug_signal <= x"0000000a";
---
- when STOP_B =>
- scl_int <= '0';
- sda_int <= '0';
- if en_FSM = '1' then
- STATE_NEXT <= STOP_C;
- end if;
- debug_signal <= x"0000000b";
---
- when STOP_C =>
- scl_int <= '1';
- sda_int <= '0';
- if en_FSM = '1' then
- STATE_NEXT <= STOP_D;
- end if;
- debug_signal <= x"0000000c";
---
- when STOP_D =>
- scl_int <= '1';
- sda_int <= '1';
- rst_bit_cnt <= '1';
- if en_FSM = '1' then
- STATE_NEXT <= IDLE;
- end if;
- debug_signal <= x"0000000d";
---SEND_BYTE
- when SEND_BYTE_A =>
- scl_int <= '0';
- sda_int <= byte_2_send(7);
- if en_FSM = '1' then
- STATE_NEXT <= SEND_BYTE_B;
- end if;
- debug_signal <= x"0000000e";
---
- when SEND_BYTE_B =>
- scl_int <= '0';
- sda_int <= byte_2_send(7);
- if en_FSM = '1' then
- STATE_NEXT <= SEND_BYTE_C;
- end if;
- debug_signal <= x"0000000f";
---
- when SEND_BYTE_C =>
- scl_int <= '1';
- sda_int <= byte_2_send(7);
- if en_FSM = '1' then
- STATE_NEXT <= SEND_BYTE_D;
- end if;
- debug_signal <= x"00000010";
---
- when SEND_BYTE_D =>
- scl_int <= '1';
- sda_int <= byte_2_send(7);
- if (bit_cnt = "001000" or bit_cnt = "010001" or bit_cnt = "011011") and en_FSM = '1' then
- STATE_NEXT <= READ_ACK_A;
- byte_2_send <= byte_2_send_mem(6 downto 0) & byte_2_send_mem(7);
- en_bit_cnt <= '1';
- en_shift_reg <= '1';
- elsif en_FSM = '1' then
- STATE_NEXT <= SEND_BYTE_A;
- byte_2_send <= byte_2_send_mem(6 downto 0) & byte_2_send_mem(7);
- en_bit_cnt <= '1';
- en_shift_reg <= '1';
- else
- STATE_NEXT <= STATE_CURRENT;
- end if;
- debug_signal <= x"00000011";
---READ_BYTE
- when READ_BYTE_A =>
- scl_int <= '0';
- if en_FSM = '1' then
- STATE_NEXT <= READ_BYTE_B;
- end if;
- debug_signal <= x"00000012";
---
- when READ_BYTE_B =>
- scl_int <= '0';
- if en_FSM = '1' then
- STATE_NEXT <= READ_BYTE_C;
- end if;
- debug_signal <= x"00000013";
---
- when READ_BYTE_C =>
- scl_int <= '1';
- bit_read <= SDA(select_line);
- if en_FSM = '1' then
- STATE_NEXT <= READ_BYTE_D;
- end if;
- debug_signal <= x"00000014";
---
- when READ_BYTE_D =>
- scl_int <= '1';
- if (bit_cnt = "100100" or bit_cnt = "101100") and en_FSM = '1' then
- STATE_NEXT <= SEND_ACK_A;
- en_bit_cnt <= '1';
- en_shift_reg <= '1';
- elsif en_FSM = '1' then
- STATE_NEXT <= READ_BYTE_A;
- en_bit_cnt <= '1';
- en_shift_reg <= '1';
- else
- STATE_NEXT <= STATE_CURRENT;
- end if;
- debug_signal <= x"00000015";
---SEND_ACK
- when SEND_ACK_A =>
- scl_int <= '0';
- if bit_cnt = "101101" then
- sda_int <= '1';
- elsif bit_cnt = "100101" then
- sda_int <= '0';
- else
- sda_int <= 'X';
- end if;
- if en_FSM = '1' then
- STATE_NEXT <= SEND_ACK_B;
- end if;
- debug_signal <= x"00000016";
---
- when SEND_ACK_B =>
- scl_int <= '0';
- if bit_cnt = "101101" then
- sda_int <= '1';
- elsif bit_cnt = "100101" then
- sda_int <= '0';
- else
- sda_int <= 'X';
- end if;
- if en_FSM = '1' then
- STATE_NEXT <= SEND_ACK_C;
- end if;
- debug_signal <= x"00000017";
---
- when SEND_ACK_C =>
- scl_int <= '1';
- if bit_cnt = "101101" then
- sda_int <= '1';
- elsif bit_cnt = "100101" then
- sda_int <= '0';
- else
- sda_int <= 'X';
- end if;
- if en_FSM = '1' then
- STATE_NEXT <= SEND_ACK_D;
- end if;
- debug_signal <= x"00000018";
---
- when SEND_ACK_D =>
- scl_int <= '1';
- if bit_cnt = "101101" and en_FSM = '1' then
- sda_int <= '1';
- STATE_NEXT <= STOP_A;
- data_out_int <= byte_2_read;
- read_done_int <= '1';
- elsif bit_cnt = "100101" and en_FSM = '1' then
- sda_int <= '0';
- STATE_NEXT <= READ_BYTE_A;
- elsif en_FSM = '0' then
- sda_int <= sda_int_mem;
- STATE_NEXT <= STATE_CURRENT;
- else
- sda_int <= 'X';
- STATE_NEXT <= IDLE;
- end if;
- debug_signal <= x"00000019";
---READ_ACK
- when READ_ACK_A =>
- scl_int <= '0';
- if en_FSM = '1' then
- STATE_NEXT <= READ_ACK_B;
- end if;
- debug_signal <= x"0000001a";
---
- when READ_ACK_B =>
- scl_int <= '0';
- if en_FSM = '1' then
- STATE_NEXT <= READ_ACK_C;
- end if;
- debug_signal <= x"0000001b";
---
- when READ_ACK_C =>
- scl_int <= '1';
- bit_read <= SDA(select_line);
- if en_FSM = '1' then
- STATE_NEXT <= READ_ACK_D;
- end if;
- debug_signal <= x"0000001c";
---
- when READ_ACK_D =>
- scl_int <= '1';
- if bit_read = '0' and bit_cnt = "001001" and en_FSM = '1' then
- STATE_NEXT <= SEND_BYTE_A;
- byte_2_send <= sfp_address_i(7 downto 0);
- en_bit_cnt <= '1';
- elsif bit_read = '0' and bit_cnt = "010010" and en_FSM = '1' then
- STATE_NEXT <= START_A;
- en_bit_cnt <= '1';
- elsif bit_read = '0' and bit_cnt = "011100" and en_FSM = '1' then
- STATE_NEXT <= READ_BYTE_A;
- en_bit_cnt <= '1';
- elsif bit_read = '1' and en_FSM = '1' then
- STATE_NEXT <= STOP_A;
- en_bit_cnt <= '1';
- elsif en_FSM = '0' then
- STATE_NEXT <= STATE_CURRENT;
- else
- STATE_NEXT <= IDLE;
- end if;
- debug_signal <= x"0000001d";
---OTHERS
- when others =>
- scl_int <= '1';
- sda_int <= '1';
- byte_2_send <= x"00";
- STATE_NEXT <= IDLE;
- debug_signal <= x"0000001e";
-
- end case;
-end process State_Decoder;
--------------------------------------------------------------------------------
-
-end behavioral;
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-
-entity sram_is61 is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- RAM_CLK : out std_logic;
- RAM_DATA : inout std_logic_vector(17 downto 0);
- RAM_ADDR : out std_logic_vector(19 downto 0);
- RAM_ADVN : out std_logic;
- RAM_ADSCN : out std_logic;
- RAM_ADSPN : out std_logic;
- RAM_GWN : out std_logic;
- RAM_CEN : out std_logic;
- RAM_OEN : out std_logic;
-
- INT_DATA_IN : in std_logic_vector(17 downto 0);
- INT_ADDR_IN : in std_logic_vector(19 downto 0);
- INT_DATA_OUT : out std_logic_vector(17 downto 0);
- INT_WRITE_EN : in std_logic;
- INT_BURST_WRITE_EN : in std_logic;
- INT_READ_EN : in std_logic;
- INT_BURST_READ_EN : in std_logic;
- INT_BUSY_OUT : out std_logic;
- INT_VALID_OUT : out std_logic;
-
- STAT_DEBUG : out std_logic_vector(31 downto 0);
- );
-end entity;
-
--- write_en is always followed by two or more clock cycles busy time
--- up to four burst_write might come in subsequent clock cycles, then several cycles busy followe
--- if burst_write goes low after the first, 2nd or 3rd clock cycle, the burst cycle is finished.
--- start of a burst cycle is always with lower two address bits = 0.
--- address is read only once during burst cycle
-
--- pulse on read_en will give one data word from ram, thus one valid
--- pulse on burst_read_en will read four words from ram, thus four consecutive valids
--- user must be able to read offered data, no waitstates are possible
-
--- after falling edge of busy signal the next access can be started immediately
-
-
-
-architecture sram_is61_arch of sram_is61 is
-
-component ddr_off
- port (Clk: in std_logic; Data: in std_logic_vector(1 downto 0);
- Q: out std_logic_vector(0 downto 0));
-end component;
-
-
-
- type state_t is (IDLE, );
- signal current_state : state_t;
- signal next_state : state_t;
-
- signal next_oe : std_logic; -- output enable
- signal next_ce : std_logic; -- chip enable
- signal next_gw : std_logic; -- write enable
- signal next_adsp : std_logic; -- address register enable
- signal next_adsc : std_logic; -- address register enable
- signal next_adv : std_logic; -- address advance
-
- signal reg_oen : std_logic;
- signal reg_cen : std_logic;
- signal reg_gwn : std_logic;
- signal reg_adspn : std_logic;
- signal reg_adscn : std_logic;
- signal reg_advn : std_logic;
- signal ram_clock : std_logic;
- signal next_ram_data : std_logic_vector(17 downto 0);
- signal reg_ram_data : std_logic_vector(17 downto 0);
- signal reg_ram_data_in : std_logic_vector(17 dowtno 0);
-
- signal last_oe : std_logic;
- signal current_oe : std_logic;
-
-begin
-
-RAM_CEN <= reg_cen;
-RAM_OEN <= reg_oen;
-RAM_GWN <= reg_gwn;
-RAM_ADSPN <= reg_adspn;
-RAM_ADSCN <= reg_adscn;
-RAM_ADVN <= reg_advn;
-RAM_CLK <= ram_clock;
-
- THE_RAM_CLOCK : ddr_off
- port map (
- Clk => CLK,
- Data(1 downto 0) => "01",
- Q(0) => ram_clock
- );
-
-
- THE_DATA_OUTPUT_PROC : process(last_oe, reg_ram_data)
- begin
- if last_oe = '1' then
- RAM_DATA <= (others => 'Z');
- else
- RAM_DATA <= reg_ram_data;
- end if;
- end process;
-
-
- THE_DATA_INPUT_SYNC : process(CLK)
- begin
- if rising_edge(CLK) then
- reg_ram_data_in <= RAM_DATA;
- end if;
- end process;
-
-
- THE_OUTPUT_SYNC : process(CLK)
- begin
- if rising_edge(CLK) then
- reg_oen <= not next_oe;
- reg_cen <= not next_ce;
- reg_gwn <= not next_gw;
- reg_adspn <= not next_adsp;
- reg_adscn <= not next_adsc;
- reg_advn <= not next_adv;
- end if;
- end process;
-
-
-
- THE_FSM_SYNC : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_state <= IDLE;
- else
- current_state <= next_state;
- current_oe <= next_oe;
- last_oe <= current_oe;
- end if;
- end if;
- end process;
-
- THE_MAIN_FSM : process(current_state)
- begin
- next_state <= current_state;
- next_oe <= '0';
- next_ce <= not RESET;
- next_gw <= '0';
- next_adsp <= '0';
- next_adsc <= '0';
- next_adv <= '0';
- next_ram_data <= reg_ram_data;
-
- case current_state is
- when IDLE =>
- end case;
- end process;
-
-
-
-
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-\documentstyle[german,timing,12pt,a4wide]{article}
-\pagestyle{empty}
-\begin{document}
-
-\begin{timing}[2s]{4cm}
-\tin{1}{FIFO\_FULL\_OUT}
-\tin{2}{DATA\_IN}
-\tin{3}{WRITE\_IN}
-\tin{4}{SEND\_IN}
-\tin{5}{RUN\_OUT}
-\til{1}{
-%..xxx...xxx...xxx...xxx...
-LLLLLLLLLHHHHHHHHHLLLLLLLLL}
-\til{2}{
-ZZZVVVXVVXVVVVVVVVVVVVVVXVV}
-\tnote{2}{3.7}{D1}
-\tnote{2}{6.7}{D2}
-\tnote{2}{9.7}{D3}
-\tnote{2}{24.7}{D3}
-\til{3}{
-LLLHHHHHHHHHLLLLLLLLLHHHHHH}
-\til{4}{
-LLLLLLLLLLLLHHHHHHHHHHHHHHH}
-\til{5}{
-LLLLLLLLLLLLLLLHHHHHHHHHHHH}
-%\tnote{2}{3}{Adressen}\tnote{2}{11}{Status}
-%\tnote{2}{36}{Adressen}\tnote{2}{44}{Status}
-\sline{0.5}{0}{5}
-\sline{0.5}{3}{5}
-\sline{0.5}{6}{5}
-\sline{0.5}{9}{5}
-\sline{0.5}{12}{5}
-\sline{0.5}{15}{5}
-\sline{0.5}{18}{5}
-\sline{0.5}{21}{5}
-\sline{0.5}{24}{5}
-\sline{0.5}{27}{5}
-\end{timing}
-
-%Early pre-fill and the starting phase of the channel master. This also shows
-%the behaviour of a released transfer: During the FIFO\_FULL the master
-%releases the writing, and after the FIFO\_FULL is pulled down it takes 2 clock
-%cycles after the new data word can be written
-
-\newpage
-
-\begin{timing}[2s]{4cm}
-\tin{1}{FIFO\_FULL\_OUT}
-\tin{2}{DATA\_IN}
-\tin{3}{WRITE\_IN}
-\til{1}{
-%..xxx...xxx...xxx...xxx...
-LLLLLLLLLHHHHHHHHHLLLLLLLLLHHHLLLLLL}
-\til{2}{
-ZZZVVVXVVXVVVVVVVVVVVXVVXVVXVVVVVXVV}
-\tnote{2}{3.7}{D1}
-\tnote{2}{6.7}{D2}
-\tnote{2}{9.7}{D3}
-\tnote{2}{21.7}{D3}
-\tnote{2}{24.7}{D4}
-\tnote{2}{27.7}{D5}
-\tnote{2}{33.7}{D6}
-\til{3}{
-LLLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH}
-\sline{0.5}{0}{3}
-\sline{0.5}{3}{3}
-\sline{0.5}{6}{3}
-\sline{0.5}{9}{3}
-\sline{0.5}{12}{3}
-\sline{0.5}{15}{3}
-\sline{0.5}{18}{3}
-\sline{0.5}{21}{3}
-\sline{0.5}{24}{3}
-\sline{0.5}{27}{3}
-\sline{0.5}{30}{3}
-\sline{0.5}{33}{3}
-\sline{0.5}{36}{3}
-\end{timing}
-
-%The running channel: Continous transfer if data words are always in the
-%pipeline. Care has to be taken if no new data word can be provided, then
-%WRITE\_IN has to be pulled down after the last valid word.
-
-
-\newpage
-
-
-
-\begin{timing}[2s]{4cm}
-\tin{1}{FIFO\_FULL\_OUT}
-\tin{2}{DATA\_IN}
-\tin{3}{WRITE\_IN}
-\tin{4}{SEND\_IN}
-\tin{5}{RUN\_OUT}
-\til{1}{
-%..xxx...xxx...xxx...xxx...
-LLLLLLLLLLLLLLLLLLLLLLLLLLL}
-\til{2}{
-VVVXVVXVVXVVXVVUUUUUUUUUUUU}
-\tnote{2}{0.7}{D1}
-\tnote{2}{3.7}{D2}
-\tnote{2}{6.7}{D3}
-\tnote{2}{9.7}{D4}
-\til{3}{
-HHHHHHHHHHHHHHHFFFFFFFFFFFF}
-\til{4}{
-HHHHHHHHHHHHHHHLLLLLLLLLLLL}
-\til{5}{
-HHHHHHHHHHHHHHHHHHHHHHHHHHH}
-%\tnote{2}{3}{Adressen}\tnote{2}{11}{Status}
-%\tnote{2}{36}{Adressen}\tnote{2}{44}{Status}
-\sline{0.5}{0}{5}
-\sline{0.5}{3}{5}
-\sline{0.5}{6}{5}
-\sline{0.5}{9}{5}
-\sline{0.5}{12}{5}
-\sline{0.5}{15}{5}
-\sline{0.5}{18}{5}
-\sline{0.5}{21}{5}
-\sline{0.5}{24}{5}
-\sline{0.5}{27}{5}
-\end{timing}
-
-%The last words. SEND\_IN is released,
-%RUN\_OUT will stay high. During this stage, all writes are ignored.
-%Now it is time to wait for the answer!
-
-\newpage
-
-
-
-\begin{timing}[2s]{4cm}
-\tin{1}{DATAREADY\_OUT}
-\tin{2}{DATA\_OUT}
-\tin{3}{READ\_IN}
-\tin{4}{TYP\_OUT}
-\til{1}{
-%..xxx...xxx...xxx...xxx...
-LLLHHHHHHHHHLLLLLLHHHHHHHHH}
-\til{2}{
-UUUXVVVVVXVVUUUUUUXVVVVVXVV}
-\tnote{2}{3.7}{D1}
-\tnote{2}{9.7}{D2}
-\tnote{2}{18.7}{D3}
-\tnote{2}{24.7}{D4}
-\til{3}{
-LLLLLLHHHHHHHHHLLLLLLHHHHHH}
-\til{4}{
-UUUVVVVVVVVVUUUUUUVVVVVVVVV}
-\tnote{4}{3.7}{DAT or HDR}
-\tnote{4}{18.7}{DAT or HDR}
-%\tnote{2}{3}{Adressen}\tnote{2}{11}{Status}
-%\tnote{2}{36}{Adressen}\tnote{2}{44}{Status}
-\sline{0.5}{0}{4}
-\sline{0.5}{3}{4}
-\sline{0.5}{6}{4}
-\sline{0.5}{9}{4}
-\sline{0.5}{12}{4}
-\sline{0.5}{15}{4}
-\sline{0.5}{18}{4}
-\sline{0.5}{21}{4}
-\sline{0.5}{24}{4}
-\sline{0.5}{27}{4}
-\end{timing}
-
-%A typical read cycle after the answer arrives from the slaves.
-%Same is true like for the writing: READ\_IN may stay high to save
-%1 clock cycle. But the target must be able to read the offered word, otherwise
-%it is lost.
-
-\newpage
-
-
-
-\begin{timing}[2s]{4cm}
-\tin{1}{DATAREADY\_OUT}
-\tin{2}{DATA\_OUT}
-\tin{3}{READ\_IN}
-\tin{4}{TYP\_OUT}
-\tin{5}{RUN\_OUT}
-\til{1}{
-%..xxx...xxx...xxx...xxx...
-LLLHHHHHHLLLLLLLLL}
-\til{2}{
-UUUXVVVVVUUUUUUUUU}
-\tnote{2}{3.7}{TRM}
-\til{3}{
-LLLLLLHHHLLLLLLLLL}
-\til{4}{
-UUUVVVVVVUUUUUUUUU}
-\tnote{4}{3.7}{TRM}
-\til{5}{
-HHHHHHHHHFFFFFFLLL}
-%\tnote{2}{3}{Adressen}\tnote{2}{11}{Status}
-%\tnote{2}{36}{Adressen}\tnote{2}{44}{Status}
-\sline{0.5}{0}{5}
-\sline{0.5}{3}{5}
-\sline{0.5}{6}{5}
-\sline{0.5}{9}{5}
-\sline{0.5}{12}{5}
-\sline{0.5}{15}{5}
-\sline{0.5}{18}{5}
-
-\end{timing}
-
-%The end of the story: The TRM word. After this has been read, the
-%RUN\_OUT will be released and a new transfer may by initialized.
-
-\end{document}
-
+++ /dev/null
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% TIMING.MF
-%
-% Zeichensatz zum Darstellen von Zeitdiagrammen digitaler
-% Schaltungen.
-% Hauptdatei f\81r alle Zeichens\84tze
-%
-% Ludwig May, Dezember 1991
-% Jens Leilich, \8enderungen im Mai 1994
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-define_pixels(p_size,p3_size);
-%define_good_x_pixels(c_width);
-%define_good_y_pixels(c_height);
-define_whole_pixels(c_width,c_height,p2_size);
-if not odd c_width: c_width:=c_width-1; fi
-
-font_x_height c_height#;
-font_quad c_width#;
-
-pen pinsel;
-pinsel=(pencircle xscaled (0.8*p_size) yscaled p_size);
-
-
-beginchar("H",c_width#,c_height#,bt#); "High Level";
-
-pickup pinsel;
-draw (-c_width,c_height)--(0,c_height);
-showit;
-endchar;
-
-
-beginchar("L",c_width#,c_height#,bt#); "Low Level";
-
-pickup pinsel;
-draw (-c_width,0)--(0,0);
-showit;
-endchar;
-
-%1/12->xs#/12, damit Steigung von HL und LH wie UV (JL,8.1.94)
-beginchar(0,2*c_width#,c_height#,bt#); "High-Low";
-
-pickup pinsel;
-draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(xs#/12*c_width,0)--(c_width,0);
-showit;
-endchar;
-
-beginchar(1,2*c_width#,c_height#,bt#); "Low-High";
-
-pickup pinsel;
-draw (-c_width,0)--(-xs#/12*c_width,0)--(xs#/12*c_width,c_height)--(c_width,c_height);
-showit;
-endchar;
-
-beginchar(12,2*c_width#,c_height#,bt#); "Change Bus";
-
-pickup pinsel;
-draw (-c_width,0)--(-xs#/12*c_width,0);
-draw (-c_width,c_height)--(-xs#/12*c_width,c_height);
-draw (xs#/12*c_width,0)--(c_width,0);
-draw (xs#/12*c_width,c_height)--(c_width,c_height);
-draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height);
-draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0);
-showit;
-endchar;
-
-beginchar("V",c_width#,c_height#,bt#); "Valid Bus";
-
-pickup pinsel;
-draw (-c_width,0)--(0,0);
-draw (-c_width,c_height)--(0,c_height);
-showit;
-endchar;
-
-beginchar("Z",c_width#,c_height#,bt#); "Tristate Bus";
-
-pickup pinsel;
-draw (-c_width,c_height/2)--(0,c_height/2);
-showit;
-endchar;
-
-beginchar(2,2*c_width#,c_height#,bt#); "Tristate -> Valid Bus";
-
-pickup pinsel;
-draw (-c_width,c_height/2)--(0/12*c_width,c_height/2);
-draw (0/12*c_width,c_height/2)--(xs#/12*c_width,c_height)--(c_width,c_height);
-draw (0/12*c_width,c_height/2)--(xs#/12*c_width,0)--(c_width,0);
-showit;
-endchar;
-
-beginchar(3,2*c_width#,c_height#,bt#); "Valid -> Tristate Bus";
-
-pickup pinsel;
-draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(0/12*c_width,c_height/2);
-draw (-c_width,0)--(-xs#/12*c_width,0)--(0/12*c_width,c_height/2);
-draw (0/12*c_width,c_height/2)--(c_width,c_height/2);
-showit;
-endchar;
-
-
-beginchar("U",c_width#,c_height#,bt#); "Invalid Bus";
-
-pickup pinsel;
-draw (-c_width,0)--(0,0);
-draw (-c_width,c_height)--(0,c_height);
-
-pickup pencircle scaled p3_size;
-draw (-c_width,5/6*c_height)--(-c_width/2,c_height);
-draw (-c_width,c_height/2)--(0,5/6*c_height);
-draw (-c_width,1/6*c_height)--(0,c_height/2);
-draw (-c_width/2,0)--(0,1/6*c_height);
-showit;
-endchar;
-
-
-beginchar(4,2*c_width#,c_height#,bt#); "Tristate -> Invalid Bus";
-
-y1=s_f#*2/3*(x1+c_width)+1/2*c_height;
-x1=y1*(xs#/s_f#/12)+(6-xs#*0.5)*c_height/s_f#/12-c_width;% Startpunkt der 1. Linie
-%y1=s_f#* 12/xs#*(x1+c_width)-(6/xs#-0.5)*c_height;% Startpunkt der 1. Linie
-y2=s_f#*2/3*(x2+c_width)+1/6*c_height;
-x2=y2*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 2. Linie
-%y2=s_f#*-12/xs#*(x2+c_width)+(6/xs#+0.5)*c_height;% Startpunkt der 2. Linie
-y3=s_f#*2/3*(x3+c_width)-1/6*c_height;
-x3=y3*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 3. Linie
-%y3=s_f#*-12/xs#*(x3+c_width)+(6/xs#+0.5)*c_height;% Startpunkt der 3. Linie
-
-pickup pinsel;
-draw (-c_width,c_height/2)--(0/12*c_width,c_height/2);
-draw (0/12*c_width,c_height/2)--(xs#/12*c_width,c_height)--(c_width,c_height);
-draw (0/12*c_width,c_height/2)--(xs#/12*c_width,0)--(c_width,0);
-
-pickup pencircle scaled p3_size;
-draw z1--(1/2*c_width,c_height);
-draw z2--(c_width,5/6*c_height);
-draw z3--(c_width,c_height/2);
-draw (1/2*c_width,0)--(c_width,1/6*c_height);
-showit;
-endchar;
-
-beginchar(5,2*c_width#,c_height#,bt#); "Invalid -> Tristate Bus";
-
-y1=s_f#*2/3*(x1+c_width)+1/2*c_height ;
-x1=y1*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 1. Linie
-%y1=s_f#*-12/xs#*(x1+c_width)+(6/xs#+0.5)*c_height; % Startpunkt der 1. Linie
-y2=s_f#*2/3*(x2+c_width)+1/6*c_height ;
-x2=y2*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 2. Linie
-%y2=s_f#*-12/xs#*(x2+c_width)+(6/xs#+0.5)*c_height; % Startpunkt der 2. Linie
-y3=s_f#*2/3*(x3+c_width)-1/6*c_height ;
-x3=y3*(xs#/s_f#/12)+(6-xs#*0.5)*c_height/s_f#/12-c_width;% Startpunkt der 3. Linie
-%y3=s_f#* 12/xs#*(x3+c_width)-(6/xs#-0.5)*c_height; % Startpunkt der 3. Linie
-
-pickup pinsel;
-draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(0/12*c_width,c_height/2);
-draw (-c_width,0)--(-xs#/12*c_width,0)--(0/12*c_width,c_height/2);
-draw (0/12*c_width,c_height/2)--(c_width,c_height/2);
-
-pickup pencircle scaled p3_size;
-draw (-c_width,5/6*c_height)--(-c_width/2,c_height);
-draw (-c_width,c_height/2)--z1;
-draw (-c_width,1/6*c_height)--z2;
-draw (-c_width/2,0)--z3;
-showit;
-endchar;
-
-
-beginchar(6,2*c_width#,c_height#,bt#); "Valid -> Invalid Bus";
-
-y1=s_f#*2/3*(x1+c_width)+1/2*c_height;
-x1=y1*(xs#/s_f#/12)+(6-xs#*0.5)*c_height/s_f#/12-c_width;% Startpunkt der 1. Linie
-%y1=s_f#* 12/xs#*(x1+c_width)-(6/xs#-0.5)*c_height;% 1. Linie
-y2=s_f#*2/3*(x2+c_width)+1/6*c_height;
-x2=y2*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 2. Linie
-%y2=s_f#*-12/xs#*(x2+c_width)+(6/xs#+0.5)*c_height;% 2. Linie
-y3=s_f#*2/3*(x3+c_width)-1/6*c_height;
-x3=y3*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 3. Linie
-%y3=s_f#*-12/xs#*(x3+c_width)+(6/xs#+0.5)*c_height;% 3. Linie
-
-pickup pinsel;
-draw (-c_width,0)--(-xs#/12*c_width,0);
-draw (-c_width,c_height)--(-xs#/12*c_width,c_height);
-draw (xs#/12*c_width,0)--(c_width,0);
-draw (xs#/12*c_width,c_height)--(c_width,c_height);
-draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height);
-draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0);
-
-pickup pencircle scaled p3_size;
-draw z1--(1/2*c_width,c_height);
-draw z2--(c_width,5/6*c_height);
-draw z3--(c_width,1/2*c_height);
-draw (1/2*c_width,0)--(c_width,1/6*c_height);
-showit;
-endchar;
-
-beginchar(7,2*c_width#,c_height#,bt#); "Invalid -> Valid Bus";
-
-y1=s_f#*2/3*(x1+c_width)+1/2*c_height;
-x1=y1*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 1. Linie
-%y1=s_f#*-12/xs#*(x1+c_width)+(6/xs#+0.5)*c_height;% 1. Linie
-y2=s_f#*2/3*(x2+c_width)+1/6*c_height;
-x2=y2*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 2. Linie
-%y2=s_f#*-12/xs#*(x2+c_width)+(6/xs#+0.5)*c_height;% 2. Linie
-y3=s_f#*2/3*(x3+c_width)-1/6*c_height;
-x3=y3*(xs#/s_f#/12)+(6-xs#*0.5)*c_height/s_f#/12-c_width;% Startpunkt der 3. Linie
-%y3=s_f#* 12/xs#*(x3+c_width)-(6/xs#-0.5)*c_height;% 3. Linie
-
-pickup pinsel;
-draw (-c_width,0)--(-xs#/12*c_width,0);
-draw (-c_width,c_height)--(-xs#/12*c_width,c_height);
-draw (xs#/12*c_width,0)--(c_width,0);
-draw (xs#/12*c_width,c_height)--(c_width,c_height);
-draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height);
-draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0);
-
-pickup pencircle scaled p3_size;
-draw (-c_width,5/6*c_height)--(-1/2*c_width,c_height);
-draw (-c_width,1/2*c_height)--z1;
-draw (-c_width,1/6*c_height)--z2;
-draw (-1/2*c_width,0)--z3;
-showit;
-endchar;
-
-beginchar("F",c_width#,c_height#,bt#); "Floating Line";
-
-pickup pinsel;
-draw (-c_width,0)--(0,0);
-draw (-c_width,c_height)--(0,c_height);
-showit;
-endchar;
-
-%1/12->xs#/12, damit Steigung von FL und FH wie UV (JL,8.1.94)
-beginchar(13,2*c_width#,c_height#,bt#); "Float-Low";
-
-pickup pinsel;
-draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(xs#/12*c_width,0);
-draw (-c_width,0)--(c_width,0);
-showit;
-endchar;
-
-beginchar(14,2*c_width#,c_height#,bt#); "Float-High";
-
-pickup pinsel;
-draw (-c_width,0)--(-xs#/12*c_width,0)--(xs#/12*c_width,c_height);
-draw (-c_width,c_height)--(c_width,c_height);
-showit;
-endchar;
-
-beginchar(15,2*c_width#,c_height#,bt#); "High-Float";
-
-pickup pinsel;
-draw (-c_width,c_height)--(c_width,c_height);
-draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0)--(c_width,0);
-showit;
-endchar;
-
-beginchar(16,2*c_width#,c_height#,bt#); "Low-Float";
-
-pickup pinsel;
-draw (-c_width,0)--(c_width,0);
-draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height)--(c_width,c_height);
-showit;
-endchar;
-
-
-beginchar("-",c_width#/2,c_height#,bt#); "...";
-
-pickup pencircle scaled p3_size;
-draw (-c_width,-1/12*c_height)--(-c_width,13/12*c_height);
-draw (-c_width/2-1,-1/12*c_height)--(-c_width/2-1,13/12*c_height);
-showit;
-endchar;
-
-beginchar("T",c_width#,1/6*c_height#,bt#); "TOP";
-
-pickup pinsel;
-draw (-c_width,1/12*c_height)--(-c_width,1/6*c_height)--(0,1/6*c_height);
-showit;
-endchar;
-
-beginchar("B",c_width#,1/6*c_height#,bt#); "BOTTOM";
-
-pickup pinsel;
-draw (-c_width,1/12*c_height)--(-c_width,0)--(0,0);
-showit;
-endchar;
-
-beginchar(8,3/2*c_width#,1/6*c_height#,bt#); "TOP-";
-
-pickup pinsel;
-draw (-c_width,1/12*c_height)--(-c_width,1/6*c_height)--(0,1/6*c_height);
-pickup pencircle scaled p3_size;
-draw (0+1,0)--(0+1,2/12*c_height);
-draw (1/2*c_width-1,0)--(1/2*c_width-1,2/12*c_height);
-showit;
-endchar;
-
-beginchar(9,3/2*c_width#,1/6*c_height#,bt#); "BOTTOM-";
-
-pickup pinsel;
-draw (-c_width,1/12*c_height)--(-c_width,0)--(0,0);
-pickup pencircle scaled p3_size;
-draw (0+1,0)--(0+1,2/12*c_height);
-draw (1/2*c_width-1,0)--(1/2*c_width-1,2/12*c_height);
-showit;
-endchar;
-
-beginchar(10,3/2*c_width#,1/6*c_height#,bt#); "top-";
-
-pickup pinsel;
-draw (-c_width,1/6*c_height)--(0,1/6*c_height);
-pickup pencircle scaled p3_size;
-draw (0+1,0)--(0+1,2/12*c_height);
-draw (1/2*c_width-1,0)--(1/2*c_width-1,2/12*c_height);
-showit;
-endchar;
-
-beginchar(11,3/2*c_width#,1/6*c_height#,bt#); "bottom-";
-
-pickup pinsel;
-draw (-c_width,0)--(0,0);
-pickup pencircle scaled p3_size;
-draw (0+1,0)--(0+1,2/12*c_height);
-draw (1/2*c_width-1,0)--(1/2*c_width-1,2/12*c_height);
-showit;
-endchar;
-
-beginchar("t",c_width#,1/6*c_height#,bt#);
-
-pickup pinsel;
-draw (-c_width,1/6*c_height)--(0,1/6*c_height);
-showit;
-endchar;
-
-beginchar("b",c_width#,1/6*c_height#,bt#);
-
-pickup pinsel;
-draw (-c_width,0)--(0,0);
-showit;
-endchar;
-
-%Pfeil von 1/2 nach 7/8 der Breite vergr\94\9eert (JL,8.1.94)
-beginchar("A",c_width#,3/12*c_height#,0); "Arrow left";
-
-pickup pencircle scaled p_size;
-draw (-1/8*c_width,1/12*c_height)--(0,1/12*c_height);
-fill (-1/8*c_width,2/12*c_height)--(-c_width,1/12*c_height)--(-1/8*c_width,0)--cycle;
-showit;
-endchar;
-
-beginchar("P",c_width#,3/12*c_height#,0); "Arrow right";
-
-pickup pencircle scaled p_size;
-draw (-c_width,1/12*c_height)--(-1/8*c_width,1/12*c_height);
-fill (-7/8*c_width,2/12*c_height)--(0,1/12*c_height)--(-7/8*c_width,0)--cycle;
-showit;
-endchar;
-
-beginchar("a",c_width#,3/12*c_height#,0); "Arrow line";
-
-pickup pencircle scaled p_size;
-draw (-c_width,1/12*c_height)--(0,1/12*c_height);
-showit;
-endchar;
-
-
-%dasselbe wie "U"
-beginchar("X",c_width#,c_height#,bt#); "Unknown";
-pickup pinsel;
-draw (-c_width,0)--(0,0);
-draw (-c_width,c_height)--(0,c_height);
-
-pickup pencircle scaled p3_size;
-draw (-c_width,5/6*c_height)--(-c_width/2,c_height);
-draw (-c_width,c_height/2)--(0,5/6*c_height);
-draw (-c_width,1/6*c_height)--(0,c_height/2);
-draw (-c_width/2,0)--(0,1/6*c_height);
-showit;
-endchar;
-
-%Leerzeichen mit Punkten, damit nachtr\84glich gezeichnet werden kann
-%(JL,8.1.94)
-
-beginchar(".",c_width#,c_height#,bt#); "Leer";
-pickup pinsel;
-fill (-c_width,0)--(-c_width+p2_size,0)--
- (-c_width+p2_size,p2_size)--(-c_width,p2_size)--cycle;
-fill (-c_width,c_height)--(-c_width+p2_size,c_height)--
- (-c_width+p2_size,c_height-p2_size)--(-c_width,c_height-p2_size)--cycle;
-showit;
-endchar;
-
-beginchar("h",c_width#,c_height#,bt#); "High Level";
-pickup pinsel;
-draw (-c_width,c_height)--(0,c_height);
-fill (-c_width,0)--(-c_width+p2_size,0)--
- (-c_width+p2_size,p2_size)--(-c_width,p2_size)--cycle;
-showit;
-endchar;
-
-
-beginchar("l",c_width#,c_height#,bt#); "Low Level";
-pickup pinsel;
-draw (-c_width,0)--(0,0);
-fill (-c_width,c_height)--(-c_width+p2_size,c_height)--
- (-c_width+p2_size,c_height-p2_size)--(-c_width,c_height-p2_size)--cycle;
-showit;
-endchar;
-
-beginchar(20,2*c_width#,c_height#,bt#); "High-Low";
-pickup pinsel;
-draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(xs#/12*c_width,0)--(c_width,0);
-fill (-c_width,0)--(-c_width+p2_size,0)--
- (-c_width+p2_size,p2_size)--(-c_width,p2_size)--cycle;
-fill (0,c_height)--(p2_size,c_height)--
- (p2_size,c_height-p2_size)--(0,c_height-p2_size)--cycle;
-showit;
-endchar;
-
-beginchar(21,2*c_width#,c_height#,bt#); "Low-High";
-pickup pinsel;
-draw (-c_width,0)--(-xs#/12*c_width,0)--(xs#/12*c_width,c_height)--(c_width,c_height);
-fill (0,0)--(p2_size,0)--
- (p2_size,p2_size)--(0,p2_size)--cycle;
-fill (-c_width,c_height)--(-c_width+p2_size,c_height)--
- (-c_width+p2_size,c_height-p2_size)--(-c_width,c_height-p2_size)--cycle;
-showit;
-endchar;
-
-beginchar("f",c_width#,c_height#,bt#); "Floating Line";
-pickup pinsel;
-draw (-c_width,0)--(0,0);
-draw (-c_width,c_height)--(0,c_height);
-showit;
-endchar;
-
-beginchar(33,2*c_width#,c_height#,bt#); "Float-Low";
-pickup pinsel;
-draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(xs#/12*c_width,0);
-draw (-c_width,0)--(c_width,0);
-fill (0,c_height)--(p2_size,c_height)--
- (p2_size,c_height-p2_size)--(0,c_height-p2_size)--cycle;
-showit;
-endchar;
-
-beginchar(34,2*c_width#,c_height#,bt#); "Float-High";
-pickup pinsel;
-draw (-c_width,0)--(-xs#/12*c_width,0)--(xs#/12*c_width,c_height);
-draw (-c_width,c_height)--(c_width,c_height);
-fill (0,0)--(p2_size,0)--
- (p2_size,p2_size)--(0,p2_size)--cycle;
-showit;
-endchar;
-
-beginchar(35,2*c_width#,c_height#,bt#); "High-Float";
-pickup pinsel;
-draw (-c_width,c_height)--(c_width,c_height);
-draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0)--(c_width,0);
-fill (-c_width,0)--(-c_width+p2_size,0)--
- (-c_width+p2_size,p2_size)--(-c_width,p2_size)--cycle;
-showit;
-endchar;
-
-beginchar(36,2*c_width#,c_height#,bt#); "Low-Float";
-pickup pinsel;
-draw (-c_width,0)--(c_width,0);
-draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height)--(c_width,c_height);
-fill (-c_width,c_height)--(-c_width+p2_size,c_height)--
- (-c_width+p2_size,c_height-p2_size)--(-c_width,c_height-p2_size)--cycle;
-showit;
-endchar;
-
-
-% HX,LX,XH,XL und dasselbe mit U statt X sind eigtl. Pfusch
-% vielleicht mal Zeichen f\81r machen... (JL)
-ligtable "H":"L"=:0, "F"=:15, "V"=:15, "X"=:15;
-ligtable "L":"H"=:1, "F"=:16, "V"=:16, "X"=:16;
-ligtable "F":"L"=:13,"H"=:14;
-ligtable "h":"l"=:20,"f"=:35; % Version mit Punkten zum Zeichnen (JL, 4.2.94)
-ligtable "l":"h"=:21,"f"=:36;
-ligtable "f":"l"=:33,"h"=:34;
-ligtable "Z":"V"=:2, "U"=:4;
-ligtable "V":"Z"=:3, "U"=:6, "X"=:12, "L"=:13, "H"=:14;
-ligtable "U":"Z"=:5, "V"=:7, "X"=:7, "L"=:13, "H"=:14; % UX=:7 [UV] (JL, 8.1.94)
-ligtable "X":"V"=:12,"U"=:6, "L"=:13, "H"=:14; % XU=:6 [VU] (JL, 8.1.94)
-ligtable "T":"-"=:8;
-ligtable "B":"-"=:9;
-ligtable "t":"-"=:10;
-ligtable "b":"-"=:11;
-
-end;
-
+++ /dev/null
-% timing.sty: Ludwig May/Jens Leilich 10.12.91
-%
-% Dieses Style-File erleichtert den Umgang mit dem Timing-Font.
-%
-% Es stellt Kommandos zur Positionierung von einzelnen Elementen
-% eines Timing-Diagramms in einer picture-Umgebung zur Verfuegung.
-%
-%
-% Folgende Kommandos sind verfuegbar:
-%
-% Erweiterte picture-Umgebung
-% \begin{timing}[Zeichensatz]{Randgroesse}
-% \end{timing}
-% Zeichensatz ist 1,2,1s,2s. Die Zahl gibt die Breite an,
-% s bedeutet schr\84ge Flanken. 2 ist default.
-%
-% Zeile mit Timingdiagramm
-% \til{y-pos}{Zeichenkette}
-%
-% Label fuer Zeile
-% \tin{y-pos}{Zeichenkette}
-%
-% Bemerkung
-% \tnote{y-pos}{x-pos}{Zeichenkette}
-%
-% Pfeil nach rechts zeigend
-% \rarw{y-pos}{x-pos}{laenge}{Zeichenkette}
-%
-% Pfeil nach links zeigend
-% \larw{y-pos}{x-pos}{laenge}{Zeichenkette}
-%
-% Senkrechte Linie
-% \sline{y1-pos}{x-pos}{y2-pos}
-%
-% Zeitmarken als Argument fuer \til
-% \timingcounter{Markenabstand}{Startwert}{Endwert}{Intervall}
-% Zeitmarken als Argument fuer \til nach Unterbrechung
-% \conttimingcounter{Markenabstand}{Startwert}{Endwert}{Intervall}
-%
-%
-% Abstandsfaktor fuer einzelne Zeilen
-% \timescalefactor
-%
-% Evtl. n\94tige Anpassung fuer Ausrichtung senkrechter Linien
-% \timadjust
-%
-%
-% Dieses Style-File und der dazugehoerige Zeichensatz wurde erstellt,
-% um moeglichst einfach ein paar Timingdiagramme in meine Studienarbeit
-% integrieren zu koennen. Da es in der vorliegenden Form meine
-% Erwartungen vollstaendig erfuellt hat, haben ich aus Zeitgruenden keine
-% grosse Ueberarbeitung durchgefuehrt. Vielleicht kann das jemand uebernehmen,
-% der von der ganzen Materie mehr Ahnung hat. Ein Problem ist z.B. die
-% ungenaue horizontale Ausrichtung der senkrechten Linien (ist irgendwie
-% Druckertreiber abhaengig, evtl. MAX_DRIFT des Treibers auf 0 setzen).
-% Da aber grosses Interesse an dem Style besteht, haben ich ihn mal in
-% Umlauf gegeben. Wenn jemand Verbesserungen durchfuehrt, waeren ich an
-% einer Rueckmeldung an folgende Adresse dankbar:
-%
-% Ludwig May
-% Friedrichstrasse 23b
-% 6100 Darmstadt
-%
-% Bitte keine Fragen stellen, ich habe fuer eine weitere Unterstuetzung
-% weder Zeit noch ausreichend Gelegenheit.
-%
-% Ludwig May
-%
-% Ich habe Font und Style weiterentwickelt zu Lehrzwecken, da ich
-% Elektrotechnik an BBS unterrichte.
-% Verbesserungsvorschl\84ge und Lob ;-) k\94nnen auch an mich gerichtet
-% werden.
-% Jens Leilich, C/O BBS Technik I, Franz-Zang-Str. 3--7, 67059 Ludwigshafen
-% Jens_Leilich @ lu.maus.de
-%
-\typeout{Timing Style, Ludwig May <Dec 1991> Jens Leilich <May 1994>.}
-%
-%
-% Alle benoetigten Counter, Dimensionen und Boxen definieren
-%
-%
-\newfont{\timon}{timing1 scaled 1000}
-\newfont{\timtw}{timing2 scaled 1000}
-\newfont{\timons}{timing1s scaled 1000}
-\newfont{\timtws}{timing2s scaled 1000}
-\newfont{\timbs}{cmr5 scaled 1000}
-\newcount\counttime
-\newdimen\timetmpdim
-\newdimen\timehdrdim
-\newcount\timetmpcnt
-\newcount\timearwcnt
-\newdimen\timeskipdim
-\newdimen\timewidthdim
-\newbox\timebox
-\def\timescalefactor{2}
-\def\timadjust{0.0pt}
-%
-%
-% Neue Umgebung definieren
-%
-%
-\def\timing{\@ifnextchar [{\@@timing}{\@@timing[2]}}
-
-\def\@@timing[#1]#2%
-{
-\expandafter\def\csname tim@@1\endcsname{\let\tim\timon}
-\expandafter\def\csname tim@@2\endcsname{\let\tim\timtw}
-\expandafter\def\csname tim@@1s\endcsname{\let\tim\timons}
-\expandafter\def\csname tim@@2s\endcsname{\let\tim\timtws}
-\def\tim{%
- \typeout{Timing font `#1' not defined, assumed 2. Use 1,2,1s,2s only!}
- \timtw \let\tim\timtw}
-\csname tim@@#1\endcsname
-\tim
-\timehdrdim=#2
-\advance\timehdrdim by 1em
-%
-%
-% Lokale Befehle definieren
-%
-%
-%
-% Hilfroutine zum Zeichen von Pfeilen variabler Laenge
-%
-%
-\newcommand{\timatail}[1]{ \mbox{ \tim
- \counttime=2
- \ifnum##1>1
- \loop
- a%
- \ifnum\counttime<##1 \advance\counttime by 1
- \repeat
- \fi
-}}
-%
-%
-% Hilfroutine zum Zeichen der Zeitmarkierung
-%
-%
-\newcommand{\lb}[2]{{\tim\makebox[##1em][c]{\timbs##2}}}
-%
-%
-% \timingcounter
-%
-%
-\newcommand{\timingcounter}[4]{ \mbox{ \tim
- \counttime=##1\divide\counttime by -2
- \hskip\counttime em
- \hskip -1em
- \counttime=##2
- \loop
- \lb{##1}{\number\counttime}
- \ifnum\counttime<##3 \advance\counttime by ##4
- \repeat
-}}
-%
-%
-% \conttimingcounter
-%
-%
-\newcommand{\conttimingcounter}[4]{ \mbox{ \tim
- \hskip 0.5em
- \counttime=##2
- \loop
- \lb{##1}{\number\counttime}
- \ifnum\counttime<##3 \advance\counttime by ##4
- \repeat
-}}
-%
-%
-% \til
-%
-%
-\newcommand{\til}[2]{
-\tim
-\timetmpdim=##1ex
-\timetmpdim=\timescalefactor\timetmpdim
-%
-% Maximale y-Groesse festhalten
-%
-\ifdim\timetmpdim>\timeskipdim
- \global\timeskipdim=\timetmpdim
-\fi
-\timetmpcnt=\timetmpdim
-\timetmpdim=\timehdrdim
-\advance\timetmpdim by -\timadjust
-\timearwcnt=\timetmpdim
-\setbox\timebox=\hbox{##2}
-%
-% Maximale x-Groesse festhalten
-%
-\ifdim\wd\timebox>\timewidthdim
- \global\timewidthdim=\wd\timebox
-\fi
-\put(\timearwcnt,-\timetmpcnt){\tim\makebox(0,0)[l]{\box\timebox}}
-%\put(\timearwcnt,-\timetmpcnt){\tim\makebox(0,0)[l]{##2}}
-}
-%
-%
-% \tin
-%
-%
-\newcommand{\tin}[2]{
-\tim
-\timetmpdim=##1ex
-\timetmpdim=\timescalefactor\timetmpdim
-\timetmpcnt=\timetmpdim
-\put(0,-\timetmpcnt){\makebox(0,0)[lb]{\rm##2}}
-}
-%
-%
-% \tnote
-%
-%
-\newcommand{\tnote}[3]{
-\tim
-\timetmpdim=##1ex
-\advance\timetmpdim by -0.3pt
-\timetmpdim=\timescalefactor\timetmpdim
-\timetmpcnt=\timetmpdim
-\timetmpdim=##2em
-\advance\timetmpdim by \timehdrdim
-\advance\timetmpdim by -1em
-\timearwcnt=\timetmpdim
-\put(\timearwcnt,-\timetmpcnt){\tim\makebox(0,0)[l]{\scriptsize\sf##3}}
-}
-%
-%
-% \larw
-%
-%
-\newcommand{\larw}[4]{
-\tim
-\timetmpdim=##1ex
-\timetmpdim=\timescalefactor\timetmpdim
-\timetmpcnt=\timetmpdim
-\timetmpdim=##2em
-\advance\timetmpdim by \timehdrdim
-\timearwcnt=\timetmpdim
-\put(\timearwcnt,-\timetmpcnt)%
- {\makebox(0,0)[l]{\tiny\vbox{\tim\hbox{\hskip-1em\hbox to ##3em{\hss\timbs\strut##4\hfil}}\nointerlineskip\vskip-4pt\hbox{A\timatail{##3}}}}}
-}
-%
-%
-% \rarw
-%
-%
-\newcommand{\rarw}[4]{
-\tim
-\timetmpdim=##1ex
-\timetmpdim=\timescalefactor\timetmpdim
-\timetmpcnt=\timetmpdim
-\timetmpdim=##2em
-\advance\timetmpdim by \timehdrdim
-\timearwcnt=\timetmpdim
-\put(\timearwcnt,-\timetmpcnt)%
- {\makebox(0,0)[l]{\tiny\vbox{\tim\hbox{\hskip-1em\hbox to ##3em{\hfil\timbs\strut##4\hss}}\nointerlineskip\vskip-4pt\hbox{\timatail{##3}P}}}}
-}
-%
-%
-% \sline
-%
-%
-\newcommand{\sline}[3]{
-\tim
-\timetmpdim=##1ex
-\timetmpdim=\timescalefactor\timetmpdim
-\timetmpcnt=\timetmpdim
-\timetmpdim=##2em
-\advance\timetmpdim by \timehdrdim
-\advance\timetmpdim by -1em
-\timearwcnt=\timetmpdim
-\timetmpdim=##3ex
-\advance \timetmpdim by -##1ex
-\advance \timetmpdim by 0.09ex
-\timetmpdim=\timescalefactor\timetmpdim
-\counttime=\timetmpdim
-\put(\timearwcnt,-\timetmpcnt)%
- {\line(0,-1){\counttime}}
-}
-%
-%
-% Weitere Initialisierung
-%
-%
-\timeskipdim=0pt
-\timewidthdim=0pt
-\unitlength 1sp
-\begin{picture}(0,0)
-\linethickness{0.4pt}
-}%
-%
-%
-% Ende der Umgebung definieren
-%
-%
-\def\endtiming{
-\global\advance\timeskipdim by 15pt
-\end{picture}
-%
-% Da picture(0,0) definiert wurde, wird jetzt die wirkliche Groesse durch
-% ein \rule freigehalten.
-%
-\timeskipdim=1.0\timeskipdim
-\timewidthdim=1.0\timewidthdim
-\advance\timewidthdim by \timehdrdim
-\rule{\timewidthdim}{0pt}
-\rule[-\timeskipdim]{0pt}{\timeskipdim}
-}
+++ /dev/null
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% TIMING1.MF
-%
-% Zeichensatz zum Darstellen von Zeitdiagrammen digitaler
-% Schaltungen.
-% Datei f\81r Zeichensatz mit ca. 1mm Breite
-%
-% Ludwig May, Dezember 1991
-% Jens Leilich, \8enderungen im Mai 1994
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-mode_setup;
-
-font_size 10/300in#;
-font_identifier:="TIMING1";
-font_coding_scheme:="UNSPECIFIED";
-
-u#:=1/60in#;
-c_width#:=5/2u#;
-c_height#:=15u#;
-p_size#:=u#/2;
-p2_size#:=p_size#*2;
-p3_size#:=p_size#/3;
-s_f#:=c_height#/2/c_width#;
-xs#:=0; % muss zwischen 0 und 6 liegen
-bt#:=10;
-
-input timing
-
+++ /dev/null
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\r
-% TIMING1.MF \r
-%\r
-% Zeichensatz zum Darstellen von Zeitdiagrammen digitaler\r
-% Schaltungen.\r
-% Datei f\81r Zeichensatz mit ca. 1mm Breite\r
-%\r
-% Ludwig May, Dezember 1991\r
-% Jens Leilich, \8enderungen im Mai 1994\r
-%\r
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\r
-mode_setup;\r
-\r
-font_size 10/300in#;\r
-font_identifier:="TIMING1";\r
-font_coding_scheme:="UNSPECIFIED";\r
-\r
-u#:=1/60in#;\r
-c_width#:=5/2u#;\r
-c_height#:=15u#;\r
-p_size#:=u#/2;\r
-p2_size#:=p_size#*2;\r
-p3_size#:=p_size#/3;\r
-s_f#:=c_height#/2/c_width#;\r
-xs#:=3; % muss zwischen 0 und 6 liegen\r
-bt#:=10;\r
-\r
-input timing\r
-\r
+++ /dev/null
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\r
-% TIMING2.MF \r
-%\r
-% Zeichensatz zum Darstellen von Zeitdiagrammen digitaler\r
-% Schaltungen.\r
-% Datei f\81r Zeichensatz mit ca. 2mm Breite\r
-%\r
-% Ludwig May, Dezember 1991\r
-% Jens Leilich, \8enderungen im Mai 1994\r
-%\r
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\r
-mode_setup;\r
-\r
-font_size 10/300in#;\r
-font_identifier:="TIMING2";\r
-font_coding_scheme:="UNSPECIFIED";\r
-\r
-u#:=1/60in#;\r
-c_width#:=5u#;\r
-c_height#:=15u#;\r
-p_size#:=u#/2;\r
-p2_size#:=p_size#*2;\r
-p3_size#:=p_size#/3;\r
-s_f#:=c_height#/2/c_width#;\r
-xs#:=0; % muss zwischen 0 und 6 liegen\r
-bt#:=10;\r
-\r
-input timing\r
-\r
+++ /dev/null
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\r
-% TIMING2.MF \r
-%\r
-% Zeichensatz zum Darstellen von Zeitdiagrammen digitaler\r
-% Schaltungen.\r
-% Datei f\81r Zeichensatz mit ca. 2mm Breite\r
-%\r
-% Ludwig May, Dezember 1991\r
-% Jens Leilich, \8enderungen im Mai 1994\r
-%\r
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\r
-mode_setup;\r
-\r
-font_size 10/300in#;\r
-font_identifier:="TIMING2";\r
-font_coding_scheme:="UNSPECIFIED";\r
-\r
-u#:=1/60in#;\r
-c_width#:=5u#;\r
-c_height#:=15u#;\r
-p_size#:=u#/2;\r
-p2_size#:=p_size#*2;\r
-p3_size#:=p_size#/3;\r
-s_f#:=c_height#/2/c_width#;\r
-xs#:=3; % muss zwischen 0 und 6 liegen\r
-bt#:=10;\r
-\r
-input timing\r
-\r
+++ /dev/null
-latex $1.tex
-a=`dvitype --output-level=1 $1.dvi | sed -n '/totalpages=.*$/s/^.*ges=//p'`
-dvips $1.dvi
-
-for ((b=1; b <= a ; b++)) # Double parentheses, and "LIMIT" with no "$".
-do
- echo $b
-
- psselect -p$b-$b $1.ps > $1_$b.ps
- ps2epsi $1_$b.ps $1_$b.eps
- #convert -density 150x150 $1_$b.eps $1_$b.png
- convert -density 75x75 $1_$b.eps $1_$b.png
- rm $1_$b.ps $1_$b.eps
-done
-
+++ /dev/null
--- connection between the TRBNET and any application
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-
-entity trb_net16_api_active is
-
- generic (
- FIFO_TO_INT_DEPTH : integer := std_FIFO_DEPTH; -- direction to medium
- FIFO_TO_APL_DEPTH : integer := std_FIFO_DEPTH; -- direction to application
- SBUF_VERSION : integer := std_SBUF_VERSION;
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN : in std_logic; --
- APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN : in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
- APL_READ_IN : in std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT : out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- INT_INIT_DATAREADY_OUT : out std_logic;
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN : in std_logic;
-
- INT_INIT_DATAREADY_IN : in std_logic;
- INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT : out std_logic;
-
-
- INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT : out std_logic;
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN : in std_logic;
-
- INT_REPLY_DATAREADY_IN : in std_logic;
- INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT : out std_logic;
-
- -- Status and control port
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
-end entity;
-
-architecture trb_net16_api_active_arch of trb_net16_api_active is
-
- component trb_net16_api_base is
- generic (
- API_TYPE : integer := 1; -- type of api: 0 passive, 1 active
- FIFO_TO_INT_DEPTH : integer := FIFO_TO_INT_DEPTH;
- FIFO_TO_APL_DEPTH : integer := FIFO_TO_APL_DEPTH;
- SBUF_VERSION : integer := std_SBUF_VERSION
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN : in std_logic; --
- APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN : in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
- APL_READ_IN : in std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT : out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- INT_MASTER_DATAREADY_OUT : out std_logic;
- INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_IN : in std_logic;
-
- INT_MASTER_DATAREADY_IN : in std_logic;
- INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_OUT : out std_logic;
-
-
- INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_SLAVE_DATAREADY_OUT : out std_logic;
- INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_IN : in std_logic;
-
- INT_SLAVE_DATAREADY_IN : in std_logic;
- INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_OUT : out std_logic;
-
- -- Status and control port
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
- end component;
-
-begin
-
- BASE_API: trb_net16_api_base
- generic map (
- API_TYPE => 1,
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- SBUF_VERSION => SBUF_VERSION
- )
- port map (
- CLK => CLK,
- CLK_EN => CLK_EN,
- RESET => RESET,
-
- APL_DATA_IN => APL_DATA_IN,
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
- APL_DATA_OUT => APL_DATA_OUT,
- APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
-
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
- INT_MASTER_DATA_OUT => INT_INIT_DATA_OUT,
- INT_MASTER_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT,
- INT_MASTER_READ_IN => INT_INIT_READ_IN,
-
- INT_MASTER_DATAREADY_IN => INT_INIT_DATAREADY_IN,
- INT_MASTER_DATA_IN => INT_INIT_DATA_IN,
- INT_MASTER_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN,
- INT_MASTER_READ_OUT => INT_INIT_READ_OUT,
-
- INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN,
-
- INT_SLAVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
- INT_SLAVE_DATA_OUT => INT_REPLY_DATA_OUT,
- INT_SLAVE_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT,
- INT_SLAVE_READ_IN => INT_REPLY_READ_IN,
-
- INT_SLAVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN,
- INT_SLAVE_DATA_IN => INT_REPLY_DATA_IN,
- INT_SLAVE_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN,
- INT_SLAVE_READ_OUT => INT_REPLY_READ_OUT,
- -- Status and control port
- STAT_FIFO_TO_INT => STAT_FIFO_TO_INT,
- STAT_FIFO_TO_APL => STAT_FIFO_TO_APL
- -- not needed now, but later
- );
-
-end architecture;
+++ /dev/null
--- connection between the TRBNET and any application
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net16_api_passive is
-
- generic (
- FIFO_TO_INT_DEPTH : integer := std_FIFO_DEPTH; -- direction to medium
- FIFO_TO_APL_DEPTH : integer := std_FIFO_DEPTH; -- direction to application
- SBUF_VERSION : integer := std_SBUF_VERSION;
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN : in std_logic; --
- APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN : in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
- APL_READ_IN : in std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT : out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- INT_INIT_DATAREADY_OUT : out std_logic;
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN : in std_logic;
-
- INT_INIT_DATAREADY_IN : in std_logic;
- INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT : out std_logic;
-
-
- INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT : out std_logic;
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN : in std_logic;
-
- INT_REPLY_DATAREADY_IN : in std_logic;
- INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT : out std_logic;
-
- -- Status and control port
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
-end entity;
-
-architecture trb_net16_api_passive_arch of trb_net16_api_passive is
-
- component trb_net16_api_base is
- generic (
- API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
- FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium
- FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN : in std_logic; --
- APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN : in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
- APL_READ_IN : in std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT : out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- INT_MASTER_DATAREADY_OUT : out std_logic;
- INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_IN : in std_logic;
-
- INT_MASTER_DATAREADY_IN : in std_logic;
- INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_OUT : out std_logic;
-
-
- INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_SLAVE_DATAREADY_OUT : out std_logic;
- INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_IN : in std_logic;
-
- INT_SLAVE_DATAREADY_IN : in std_logic;
- INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_OUT : out std_logic;
-
- -- Status and control port
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
- end component;
-
-begin
-
- BASE_API: trb_net16_api_base
- generic map (
- API_TYPE => 0,
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- SBUF_VERSION => SBUF_VERSION
- )
- port map (
- CLK => CLK,
- CLK_EN => CLK_EN,
- RESET => RESET,
-
- APL_DATA_IN => APL_DATA_IN,
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
- APL_DATA_OUT => APL_DATA_OUT,
- APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
-
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
- INT_MASTER_DATA_OUT => INT_REPLY_DATA_OUT,
- INT_MASTER_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT,
- INT_MASTER_READ_IN => INT_REPLY_READ_IN,
-
- INT_MASTER_DATAREADY_IN => INT_REPLY_DATAREADY_IN,
- INT_MASTER_DATA_IN => INT_REPLY_DATA_IN,
- INT_MASTER_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN,
- INT_MASTER_READ_OUT => INT_REPLY_READ_OUT,
-
- INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN,
-
- INT_SLAVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
- INT_SLAVE_DATA_OUT => INT_INIT_DATA_OUT,
- INT_SLAVE_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT,
- INT_SLAVE_READ_IN => INT_INIT_READ_IN,
-
- INT_SLAVE_DATAREADY_IN => INT_INIT_DATAREADY_IN,
- INT_SLAVE_DATA_IN => INT_INIT_DATA_IN,
- INT_SLAVE_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN,
- INT_SLAVE_READ_OUT => INT_INIT_READ_OUT,
- -- Status and control port
- STAT_FIFO_TO_INT => STAT_FIFO_TO_INT,
- STAT_FIFO_TO_APL => STAT_FIFO_TO_APL
- -- not needed now, but later
- );
-
-end architecture;
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-
-entity trb_net16_api_streaming is
- generic(
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;
- FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;
- FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- SECURE_MODE_TO_APL : integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_INT : integer range 0 to 1 := c_YES;
- APL_WRITE_ALL_WORDS: integer range 0 to 1 := c_NO
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_INIT_DATAREADY_IN : in std_logic;
- INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT : out std_logic;
-
- INT_REPLY_DATAREADY_OUT : out std_logic;
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN : in std_logic;
-
- INT_REPLY_DATAREADY_IN : in std_logic;
- INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT : out std_logic;
-
- --apl init channel
- APL_INIT_DATA_IN : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_INIT_PACKET_NUM_IN : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_INIT_DATAREADY_IN : out std_logic;
-
- --apl reply sending
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_DATAREADY_IN : in std_logic;
- APL_READ_OUT : out std_logic;
- APL_SHORT_TRANSFER_IN : in std_logic;
- APL_DTYPE_IN : in std_logic_vector (3 downto 0);
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
- APL_SEND_IN : in std_logic;
-
- -- reply receiving
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0);
- APL_DATAREADY_OUT : out std_logic;
- APL_READ_IN : in std_logic;
-
- -- APL Control port
- APL_RUN_OUT : out std_logic;
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
- APL_LOOPBACK : in std_logic;
-
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
-end entity;
-
-
-architecture trb_net16_api_streaming_arch of trb_net16_api_streaming is
- component trb_net16_dummy_fifo is
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data
- PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data
- PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic; -- Full Flag
- EMPTY_OUT : out std_logic
- );
- end component;
-
- component trb_net16_fifo is
- generic (
- DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1) 64Bit packets
- USE_VENDOR_CORES : integer := c_YES
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data
- PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data
- PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic; -- Full Flag
- EMPTY_OUT : out std_logic
- );
- end component;
-
- component trb_net16_sbuf is
- generic (
- VERSION : integer := 0
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN : in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word
- COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
- -- Port to synchronous output.
- SYN_DATAREADY_OUT : out STD_LOGIC;
- SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word
- SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
- SYN_READ_IN : in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER : out STD_LOGIC
- );
- end component;
-
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := 0;
- SECURE_MODE : integer range 0 to 1 := 0
- --if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these must be available when hold_trm goes low
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in std_logic;
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out std_logic;
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_GOT_TRM: out std_logic;
- APL_RELEASE_TRM: in std_logic;
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0)
- -- Status and control port
- );
- end component;
-
- component trb_net_sbuf is
- generic (
- DATA_WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH;
- VERSION: integer := SBUF_VERSION);
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
- -- signals for the APL to INT fifo:
- signal fifo_to_int_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0);
- signal fifo_to_int_write : std_logic;
- signal fifo_to_int_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal fifo_to_int_packet_num_out : std_logic_vector(1 downto 0);
- signal fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal fifo_to_int_read : std_logic;
- signal fifo_to_int_full : std_logic;
- signal fifo_to_int_empty : std_logic;
-
- -- signals for the INT to APL:
- signal fifo_to_apl_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal fifo_to_apl_packet_num_in : std_logic_vector(1 downto 0);
- signal fifo_to_apl_write : std_logic;
- signal fifo_to_apl_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0);
- signal fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal fifo_to_apl_read : std_logic;
- signal fifo_to_apl_full : std_logic;
- signal fifo_to_apl_empty : std_logic;
- signal saved_fifo_to_apl_packet_type, current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0);
-
- signal saved_fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal saved_fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal last_fifo_to_apl_read : std_logic;
- signal last_fifo_to_int_read : std_logic;
-
- signal state_bits, state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0);
--- signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic;
-
- signal next_INT_REPLY_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal next_INT_REPLY_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal next_INT_REPLY_DATAREADY_OUT: std_logic;
- signal sbuf_free, sbuf_next_READ: std_logic;
- signal reg_INT_REPLY_READ_OUT: std_logic;
- signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic;
- signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal next_APL_TYP_OUT, reg_APL_TYP_OUT, buf_APL_TYP_OUT: std_logic_vector(2 downto 0);
-
- type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB);
- signal out_select: OUTPUT_SELECT;
- signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0);
- signal combined_header_F1, combined_header_F2, combined_header_F3, combined_header_F0 : std_logic_vector(15 downto 0);
- signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3, combined_trailer_F0 : std_logic_vector(15 downto 0);
- signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3, registered_trailer_F0 : std_logic_vector(15 downto 0);
- signal current_combined_header, current_registered_trailer, current_data : std_logic_vector(15 downto 0);
-
- signal update_registered_trailer: std_logic;
- signal master_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-
- type PAS_API_TO_APL_STATE_T is (sa_IDLE, sa_INACTIVE);
- signal state_to_apl, next_state_to_apl : PAS_API_TO_APL_STATE_T;
-
- type state_to_int_t is ( INACTIVE, IDLE, SEND_SHORT, SEND_HEADER, RUNNING, SEND_TRAILER, SHUTDOWN);
- signal state_to_int, next_state_to_int : state_to_int_t;
-
--- type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR);
--- signal current_state, next_state : API_STATE;
- signal throw_away : std_logic;
- signal fifo_to_apl_read_before : std_logic;
- signal fifo_to_int_read_before : std_logic;
-
- signal sbuf_to_apl_next_READ : std_logic;
- signal sbuf_to_apl_free : std_logic;
- signal sbuf_apl_type_dataready : std_logic;
-
- signal master_start, master_end, slave_start, slave_end : std_logic;
- signal master_running, slave_running : std_logic;
-
- signal buf_INT_REPLY_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal buf_INT_REPLY_DATAREADY_OUT : std_logic;
-
- signal next_fifo_was_not_empty, fifo_was_not_empty : std_logic;
-
-begin
-
- APL_INIT_DATAREADY_IN <= INT_INIT_DATAREADY_IN;
- APL_INIT_DATA_IN <= INT_INIT_DATA_IN;
- APL_INIT_PACKET_NUM_IN <= INT_INIT_PACKET_NUM_IN;
- INT_INIT_READ_OUT <= '1';
-
----------------------------------------
--- fifo to internal
----------------------------------------
-
- FIFO_TO_INT: trb_net16_fifo
- generic map (
- DEPTH => FIFO_TO_INT_DEPTH,
- USE_VENDOR_CORES => USE_VENDOR_CORES)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_int_data_in,
- PACKET_NUM_IN => fifo_to_int_packet_num_in,
- WRITE_ENABLE_IN => fifo_to_int_write,
- DATA_OUT => fifo_to_int_data_out,
- PACKET_NUM_OUT => fifo_to_int_packet_num_out,
- READ_ENABLE_IN => fifo_to_int_read,
- FULL_OUT => fifo_to_int_full,
- EMPTY_OUT => fifo_to_int_empty
- );
-
- STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0);
- STAT_FIFO_TO_INT(3) <= fifo_to_int_write;
- STAT_FIFO_TO_INT(6 downto 4) <= buf_INT_REPLY_PACKET_NUM_OUT;
- STAT_FIFO_TO_INT(7) <= buf_INT_REPLY_DATAREADY_OUT;
- STAT_FIFO_TO_INT(8) <= INT_REPLY_READ_IN;
- STAT_FIFO_TO_INT(11 downto 9) <= fifo_to_int_data_out(2 downto 0);
- STAT_FIFO_TO_INT(12) <= fifo_to_int_read;
- STAT_FIFO_TO_INT(13) <= fifo_to_int_read_before;
- STAT_FIFO_TO_INT(14) <= fifo_to_int_full;
- STAT_FIFO_TO_INT(15) <= fifo_to_int_empty;
- STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT;
- STAT_FIFO_TO_INT(17) <= sbuf_to_apl_free;
- STAT_FIFO_TO_INT(18) <= fifo_to_apl_read_before;
- STAT_FIFO_TO_INT(19) <= fifo_to_apl_read;
- STAT_FIFO_TO_INT(20) <= fifo_to_apl_empty;
- STAT_FIFO_TO_INT(21) <= fifo_to_apl_write;
- STAT_FIFO_TO_INT(24 downto 22) <= next_INT_REPLY_PACKET_NUM_OUT;
- STAT_FIFO_TO_INT(25) <= next_INT_REPLY_DATAREADY_OUT;
- STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int;
- STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl;
----------------------------------------
--- fifo to apl
----------------------------------------
-
- FIFO_TO_APL: trb_net16_fifo
- generic map (
- DEPTH => FIFO_TO_APL_DEPTH,
- USE_VENDOR_CORES => USE_VENDOR_CORES)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_apl_data_in,
- PACKET_NUM_IN => fifo_to_apl_packet_num_in,
- WRITE_ENABLE_IN => fifo_to_apl_write,
- DATA_OUT => fifo_to_apl_data_out,
- PACKET_NUM_OUT => fifo_to_apl_packet_num_out,
- READ_ENABLE_IN => fifo_to_apl_read,
- FULL_OUT => fifo_to_apl_full,
- EMPTY_OUT => fifo_to_apl_empty
- );
-
- STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0);
- STAT_FIFO_TO_APL(3) <= fifo_to_apl_write;
- STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0);
- STAT_FIFO_TO_APL(11) <= fifo_to_apl_read;
- STAT_FIFO_TO_APL(14) <= fifo_to_apl_full;
- STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty;
- STAT_FIFO_TO_APL(7 downto 4) <= (others => '0');
- --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0');
- STAT_FIFO_TO_APL(31 downto 16) <= (others => '0');
- STAT_FIFO_TO_APL(13) <= reg_INT_REPLY_READ_OUT;
- STAT_FIFO_TO_APL(12) <= INT_REPLY_DATAREADY_IN;
- STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT;
-
----------------------------------------
--- a sbuf (to_int direction)
----------------------------------------
- gen_int_sbuf : if SECURE_MODE_TO_INT = 1 generate
- SBUF: trb_net16_sbuf
- generic map (
- VERSION => SBUF_VERSION)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => next_INT_REPLY_DATAREADY_OUT,
- COMB_next_READ_OUT => sbuf_next_READ,
- COMB_READ_IN => '1',
- COMB_DATA_IN => next_INT_REPLY_DATA_OUT,
- COMB_PACKET_NUM_IN => next_INT_REPLY_PACKET_NUM_OUT,
- SYN_DATAREADY_OUT => buf_INT_REPLY_DATAREADY_OUT,
- SYN_DATA_OUT => INT_REPLY_DATA_OUT,
- SYN_PACKET_NUM_OUT => buf_INT_REPLY_PACKET_NUM_OUT,
- SYN_READ_IN => INT_REPLY_READ_IN
- );
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- sbuf_free <= '0';
- else
- sbuf_free <= sbuf_next_READ or INT_REPLY_READ_IN;
- end if;
- end if;
- end process;
- end generate;
- gen_int_nonsbuf : if SECURE_MODE_TO_INT = 0 generate
- buf_INT_REPLY_DATAREADY_OUT <= next_INT_REPLY_DATAREADY_OUT;
- INT_REPLY_DATA_OUT <= next_INT_REPLY_DATA_OUT;
- buf_INT_REPLY_PACKET_NUM_OUT <= next_INT_REPLY_PACKET_NUM_OUT;
- sbuf_free <= INT_REPLY_READ_IN;
- end generate;
-INT_REPLY_PACKET_NUM_OUT <= buf_INT_REPLY_PACKET_NUM_OUT;
-INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT;
----------------------------------------
--- a sbuf (to_apl direction)
----------------------------------------
- gen_apl_sbuf : if SECURE_MODE_TO_APL = 1 generate
- SBUF_TO_APL: trb_net16_sbuf
- generic map (
- VERSION => SBUF_VERSION)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => next_APL_DATAREADY_OUT,
- COMB_next_READ_OUT => sbuf_to_apl_next_READ,
- COMB_READ_IN => '1',
- COMB_DATA_IN => next_APL_DATA_OUT,
- COMB_PACKET_NUM_IN => next_APL_PACKET_NUM_OUT,
- SYN_DATAREADY_OUT => reg_APL_DATAREADY_OUT,
- SYN_DATA_OUT => reg_APL_DATA_OUT,
- SYN_PACKET_NUM_OUT => reg_APL_PACKET_NUM_OUT,
- SYN_READ_IN => APL_READ_IN
- );
- SBUF_TO_APL2: trb_net_sbuf
- generic map (
- VERSION => SBUF_VERSION,
- DATA_WIDTH => 3)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => next_APL_DATAREADY_OUT,
- COMB_next_READ_OUT => open,
- COMB_READ_IN => '1',
- COMB_DATA_IN => next_APL_TYP_OUT,
- SYN_DATAREADY_OUT => sbuf_apl_type_dataready,
- SYN_DATA_OUT => buf_APL_TYP_OUT,
- SYN_READ_IN => APL_READ_IN
- );
-
- reg_APL_TYP_OUT <= TYPE_ILLEGAL when sbuf_apl_type_dataready = '0' else buf_APL_TYP_OUT;
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- sbuf_to_apl_free <= '0';
- else
- sbuf_to_apl_free <= sbuf_to_apl_next_READ;
- end if;
- end if;
- end process;
- end generate;
-
- gen_apl_nonsbuf : if SECURE_MODE_TO_APL = 0 generate
- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
- reg_APL_DATA_OUT <= next_APL_DATA_OUT;
- reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT;
- reg_APL_TYP_OUT <= next_APL_TYP_OUT;
- sbuf_to_apl_free <= APL_READ_IN;
- end generate;
-
- next_APL_DATA_OUT <= fifo_to_apl_data_out;
- next_APL_PACKET_NUM_OUT <= fifo_to_apl_long_packet_num_out;
- next_APL_TYP_OUT <= current_fifo_to_apl_packet_type;
- APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT;
- APL_DATA_OUT <= reg_APL_DATA_OUT;
- APL_PACKET_NUM_OUT <= reg_APL_PACKET_NUM_OUT;
- APL_TYP_OUT <= reg_APL_TYP_OUT;
- APL_SEQNR_OUT <= sequence_counter;
-
-
-
----------------------------------------
---regenerate long packet numbers
----------------------------------------
- fifo_to_int_long_packet_num_out(2) <= fifo_to_int_packet_num_out(1);
- fifo_to_int_long_packet_num_out(0) <= fifo_to_int_packet_num_out(0);
- fifo_to_int_long_packet_num_out(1) <= not saved_fifo_to_int_long_packet_num_out(1) when last_fifo_to_int_read = '1' and not saved_fifo_to_int_long_packet_num_out(2) = '1' and saved_fifo_to_int_long_packet_num_out(0) = '1' else saved_fifo_to_int_long_packet_num_out(1);
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- saved_fifo_to_int_long_packet_num_out <= (others => '0');
- elsif last_fifo_to_int_read = '1' then
- saved_fifo_to_int_long_packet_num_out <= fifo_to_int_long_packet_num_out;
- end if;
- end if;
- end process;
-
-
- fifo_to_apl_long_packet_num_out(2) <= fifo_to_apl_packet_num_out(1);
- fifo_to_apl_long_packet_num_out(0) <= fifo_to_apl_packet_num_out(0);
- fifo_to_apl_long_packet_num_out(1) <= not saved_fifo_to_apl_long_packet_num_out(1) when last_fifo_to_apl_read = '1' and not saved_fifo_to_apl_long_packet_num_out(2) = '1' and saved_fifo_to_apl_long_packet_num_out(0) = '1' else saved_fifo_to_apl_long_packet_num_out(1);
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- saved_fifo_to_apl_long_packet_num_out <= (others => '0');
- elsif last_fifo_to_apl_read = '1' then
- saved_fifo_to_apl_long_packet_num_out <= fifo_to_apl_long_packet_num_out;
- end if;
- end if;
- end process;
-
----------------------------------------
--- save packet type
----------------------------------------
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' or fifo_to_apl_long_packet_num_out = c_F3 then
- saved_fifo_to_apl_packet_type <= TYPE_ILLEGAL;
- elsif fifo_to_apl_long_packet_num_out = c_H0 then
- saved_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0);
- end if;
- end if;
- end process;
- --create comb. real packet type
- current_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0) when (fifo_to_apl_long_packet_num_out = c_H0)
- else saved_fifo_to_apl_packet_type;
-
----------------------------------------
--- select data for int direction
----------------------------------------
-
-
- process(current_combined_header, current_registered_trailer, current_data, out_select)
- begin
- case out_select is
- when HDR => next_INT_REPLY_DATA_OUT <= current_combined_header;
- when TRM => next_INT_REPLY_DATA_OUT <= current_registered_trailer;
- when others => next_INT_REPLY_DATA_OUT <= current_data;
- end case;
- end process;
-
-
-
- process(master_counter, fifo_to_int_data_out, combined_header_F1, registered_trailer_F1,
- combined_header_F2, registered_trailer_F2, registered_trailer_F0,
- combined_header_F3, registered_trailer_F3, combined_header_F0)
- begin
- case master_counter is
- when c_F0 =>
- current_combined_header <= combined_header_F0;
- current_registered_trailer <= registered_trailer_F0;
- current_data <= fifo_to_int_data_out;
- when c_F1 =>
- current_combined_header <= combined_header_F1;
- current_registered_trailer <= registered_trailer_F1;
- current_data <= fifo_to_int_data_out;
- when c_F2 =>
- current_combined_header <= combined_header_F2;
- current_registered_trailer <= registered_trailer_F2;
- current_data <= fifo_to_int_data_out;
- when c_F3 =>
- current_combined_header <= combined_header_F3;
- current_registered_trailer <= registered_trailer_F3;
- current_data <= fifo_to_int_data_out;
- when others =>
- current_combined_header <= "0000000000000" & TYPE_HDR;
- current_registered_trailer <= "0000000000000" & TYPE_TRM;
- current_data <= "0000000000000" & TYPE_DAT;
- end case;
- end process;
-
- next_INT_REPLY_PACKET_NUM_OUT <= master_counter;
-
- MASTER_TRANSFER_COUNTER : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- master_counter <= c_H0;
- elsif next_INT_REPLY_DATAREADY_OUT = '1' then
- if master_counter = c_max_word_number then
- master_counter <= (others => '0');
- else
- master_counter <= master_counter + 1;
- end if;
- end if;
- end if;
- end process;
-
-
----------------------------------------
--- keep track of fifo read operations
----------------------------------------
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- fifo_to_apl_read_before <= '0';
- else
- last_fifo_to_apl_read <= fifo_to_apl_read;
- if fifo_to_apl_read = '1' then
- fifo_to_apl_read_before <= '1';
- elsif sbuf_to_apl_free = '1' or throw_away = '1' then
- fifo_to_apl_read_before <= '0';
- end if;
- end if;
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- fifo_to_int_read_before <= '0';
- else
- last_fifo_to_int_read <= fifo_to_int_read;
- if fifo_to_int_read = '1' then
- fifo_to_int_read_before <= '1';
- elsif next_INT_REPLY_DATAREADY_OUT = '1' and master_counter /= "00" then --implies sbuf_free
- fifo_to_int_read_before <= '0';
- end if;
- end if;
- end if;
- end process;
-
-
-
----------------------------------------
---state machine for direction to APL
----------------------------------------
- to_apl : process(fifo_to_apl_full, reg_INT_REPLY_READ_OUT, INT_REPLY_DATAREADY_IN, fifo_to_apl_empty,
- fifo_to_apl_long_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT,
- sbuf_to_apl_free, INT_REPLY_DATA_IN, INT_REPLY_PACKET_NUM_IN,
- reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away,state_to_int )
- begin
- reg_INT_REPLY_READ_OUT <= not fifo_to_apl_full;
- fifo_to_apl_write <= reg_INT_REPLY_READ_OUT and INT_REPLY_DATAREADY_IN;
- fifo_to_apl_read <= '0';
- next_APL_DATAREADY_OUT <= '0';
- next_state_to_apl <= state_to_apl;
- throw_away <= '0';
- slave_start <= '0';
- slave_end <= '0';
-
- case state_to_apl is
- when sa_IDLE =>
- slave_start <= fifo_to_apl_write;
- if APL_WRITE_ALL_WORDS = 0 then
- next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and not fifo_to_apl_long_packet_num_out(2) and sbuf_to_apl_free;
- throw_away <= fifo_to_apl_long_packet_num_out(2);
- else
- next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and sbuf_to_apl_free;
- end if;
- fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away);
- if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = c_F3 and sbuf_to_apl_free = '1' then
- next_state_to_apl <= sa_INACTIVE;
- slave_end <= '1';
- end if;
- when sa_INACTIVE =>
- if state_to_int = INACTIVE then
- next_state_to_apl <= sa_IDLE;
- end if;
- end case;
- end process;
-
----------------------------------------
---state machine for direction to INT
----------------------------------------
- to_int : process(state_to_int, APL_SHORT_TRANSFER_IN, APL_SEND_IN, slave_start,
- master_counter, sbuf_free, fifo_to_int_empty, sequence_counter, fifo_to_int_read_before,
- state_to_apl, master_start, fifo_was_not_empty)
- begin
- next_state_to_int <= state_to_int;
- update_registered_trailer <= '0';
- out_select <= DAT;
- next_INT_REPLY_DATAREADY_OUT <= '0';
- next_sequence_counter <= sequence_counter;
- fifo_to_int_read <= '0';
- master_start <= '0';
- master_end <= '0';
- next_fifo_was_not_empty <= fifo_was_not_empty or not fifo_to_int_empty;
-
- case state_to_int is
- when INACTIVE =>
- if slave_start = '1' then
- next_state_to_int <= IDLE;
- end if;
- when IDLE =>
- next_fifo_was_not_empty <= '0';
- if APL_SEND_IN = '1' then
- master_start <= '1';
- if APL_SHORT_TRANSFER_IN = '1' then
- next_state_to_int <= SEND_SHORT;
- else
- next_state_to_int <= SEND_HEADER;
- end if;
- end if;
- when SEND_SHORT =>
- if APL_SEND_IN = '0' then
- update_registered_trailer <= '1';
- next_state_to_int <= SEND_TRAILER;
- end if;
- when SEND_HEADER =>
- out_select <= HDR;
- next_INT_REPLY_DATAREADY_OUT <= sbuf_free;
- if master_counter = c_F3 and sbuf_free = '1' then
- next_state_to_int <= RUNNING;
- end if;
- when RUNNING =>
- fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2);
- next_INT_REPLY_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or master_counter(2));
- if APL_SEND_IN = '0' and fifo_was_not_empty = '1' then -- terminate the transfer
- update_registered_trailer <= '1';
- if fifo_to_int_empty = '1' and master_counter = c_F3 and sbuf_free = '1' then
- next_state_to_int <= SEND_TRAILER; -- immediate stop
- else
- next_state_to_int <= SHUTDOWN; -- send rest of data / padding
- end if;
- end if;
- when SHUTDOWN =>
- fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2);
- next_INT_REPLY_DATAREADY_OUT <= sbuf_free and
- ((fifo_to_int_read_before or master_counter(2)) or --write data from fifo
- (fifo_to_int_empty and not master_counter(2))); --fill with padding words
- if master_counter = c_F3 and fifo_to_int_empty = '1' and sbuf_free = '1' then
- next_state_to_int <= SEND_TRAILER;
- end if;
- when SEND_TRAILER =>
- out_select <= TRM;
- next_INT_REPLY_DATAREADY_OUT <= sbuf_free;
- if master_counter = "11" and sbuf_free = '1' then
- next_state_to_int <= INACTIVE;
- next_sequence_counter <= sequence_counter +1;
- master_end <= '1';
- end if;
- end case;
- end process;
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- state_to_apl <= sa_IDLE;
- state_to_int <= INACTIVE;
- sequence_counter <= (others => '0');
- fifo_was_not_empty <= '0';
- else
- state_to_apl <= next_state_to_apl;
- state_to_int <= next_state_to_int;
- sequence_counter <= next_sequence_counter;
- fifo_was_not_empty <= next_fifo_was_not_empty;
- end if;
- end if;
- end process;
-
-
-
----------------------------------------
---
----------------------------------------
-
- --save target address for passive api
- reg_hdr_f1: process(CLK)
- begin
- if rising_edge(CLK) then
- if current_fifo_to_apl_packet_type = TYPE_HDR then
- if fifo_to_apl_long_packet_num_out = c_F1 then
- combined_header_F1 <= fifo_to_apl_data_out;
- end if;
- end if;
- end if;
- end process;
- -- combine the next header
- combined_header_F0 <= APL_MY_ADDRESS_IN;
- combined_header_F2 <= (others => '0');
- combined_header_F3(15 downto 14) <= (others => '0'); -- LAY
- combined_header_F3(13 downto 12) <= (others => '0'); -- VERS
- combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR
- combined_header_F3(3 downto 0) <= APL_DTYPE_IN;
- combined_trailer_F0 <= (others => '0');
- combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16);
- combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 0);
- combined_trailer_F3(15 downto 14) <= (others => '0'); -- res.
- combined_trailer_F3(13 downto 12) <= (others => '0'); -- VERS
- combined_trailer_F3(11 downto 4) <= sequence_counter; -- SEQNR
- combined_trailer_F3(3 downto 0) <= APL_DTYPE_IN;
-
- -- connect Transmitter port
- fifo_to_int_data_in <= APL_DATA_IN;
- fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN(2) & APL_PACKET_NUM_IN(0);
- fifo_to_int_write <= (APL_DATAREADY_IN and not fifo_to_int_full);
- APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing
-
- -- connect receiver
- fifo_to_apl_data_in <= INT_REPLY_DATA_IN;
- fifo_to_apl_packet_num_in <= INT_REPLY_PACKET_NUM_IN(2) & INT_REPLY_PACKET_NUM_IN(0);
- INT_REPLY_READ_OUT <= reg_INT_REPLY_READ_OUT;
-
- RUN_OUT_gen : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- APL_RUN_OUT <= '0';
- else
- if slave_start = '1' then
- APL_RUN_OUT <= '1';
- elsif slave_running = '0' and state_to_int = INACTIVE then
- APL_RUN_OUT <= '0';
- end if;
- end if;
- end if;
- end process;
-
- RUNNING_gen : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- master_running <= '0';
- slave_running <= '0';
- else
- if master_start = '1' then
- master_running <= '1';
- elsif master_end = '1' then
- master_running <= '0';
- end if;
- if slave_start = '1' then
- slave_running <= '1';
- elsif slave_end = '1' then
- slave_running <= '0';
- end if;
- end if;
- end if;
- end process;
-
- REG3 : process(CLK)
- begin
- if rising_edge(CLK) then
- if update_registered_trailer = '1' then
- registered_trailer_F0 <= combined_trailer_F0;
- registered_trailer_F1 <= combined_trailer_F1;
- registered_trailer_F2 <= combined_trailer_F2;
- registered_trailer_F3 <= combined_trailer_F3;
- end if;
- end if;
- end process;
-
---for simulation only
-
-
- process(state_to_apl)
- begin
- case state_to_apl is
- when sa_IDLE => state_bits_to_apl <= "000";
- when sa_INACTIVE => state_bits_to_apl <= "100";
- when others => state_bits_to_apl <= "111";
- end case;
- end process;
- process(state_to_int)
- begin
- case state_to_int is
- when IDLE => state_bits_to_int <= "000";
- when SEND_HEADER => state_bits_to_int <= "001";
- when RUNNING => state_bits_to_int <= "010";
- when SHUTDOWN => state_bits_to_int <= "011";
- when SEND_SHORT => state_bits_to_int <= "100";
- when SEND_TRAILER => state_bits_to_int <= "101";
- when INACTIVE => state_bits_to_int <= "110";
- when others => state_bits_to_int <= "111";
- end case;
- end process;
-
-
-end architecture;
+++ /dev/null
-
----------------------------------------------------------------------------
--- --
--- Module : fifoctlr_cc_v2.vhd Last Update: 01/07/05 --
--- --
--- Description : FifO controller top level. --
--- Implements a 511x36 FifO w/common read/write clocks. --
--- --
--- The following VHDL code implements a 511x36 FifO in a Virtex2 --
--- device. The inputs are a Clock, a Read Enable, a Write Enable, --
--- Write Data, and a FifO_gsr signal as an initial reset. The outputs --
--- are Read Data, Full, Empty, and the FifOcount outputs, which --
--- indicate how full the FifO is. --
--- --
--- Designer : Nick Camilleri --
--- --
--- Company : Xilinx, Inc. --
--- --
--- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
--- WHATSOEVER AND XILINX SPECifICALLY DISCLAIMS ANY --
--- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --
--- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --
--- THEY ARE ONLY INTendED TO BE USED BY XILINX --
--- CUSTOMERS, AND WITHIN XILINX DEVICES. --
--- --
--- Copyright (c) 2000 Xilinx, Inc. --
--- All rights reserved --
--- --
----------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use work.trb_net_std.all;
-library unisim;
-use UNISIM.VComponents.all;
-
-entity trb_net16_bram_fifo is
- port (clock_in: IN std_logic;
- read_enable_in: IN std_logic;
- write_enable_in: IN std_logic;
- write_data_in: IN std_logic_vector(17 downto 0);
- fifo_gsr_in: IN std_logic;
- read_data_out: OUT std_logic_vector(17 downto 0);
- full_out: OUT std_logic;
- empty_out: OUT std_logic;
- fifocount_out: OUT std_logic_vector(3 downto 0));
-end trb_net16_bram_fifo;
-
-architecture trb_net16_bram_fifo_arch of trb_net16_bram_fifo is
- signal clock: std_logic;
- signal read_enable: std_logic;
- signal write_enable: std_logic;
- signal fifo_gsr: std_logic;
- signal read_data: std_logic_vector(17 downto 0) := "000000000000000000";
- signal write_data: std_logic_vector(17 downto 0);
- signal full: std_logic;
- signal empty: std_logic;
- signal read_addr: std_logic_vector(9 downto 0) := "0000000000";
- signal write_addr: std_logic_vector(9 downto 0) := "0000000000";
- signal fcounter: std_logic_vector(9 downto 0) := "0000000000";
- signal read_allow: std_logic;
- signal write_allow: std_logic;
- signal fcnt_allow: std_logic;
- signal fcntandout: std_logic_vector(3 downto 0);
- signal ra_or_fcnt0: std_logic;
- signal wa_or_fcnt0: std_logic;
- signal emptyg: std_logic;
- signal fullg: std_logic;
- signal gnd_bus: std_logic_vector(17 downto 0);
- signal gnd: std_logic;
- signal pwr: std_logic;
- signal read_after_write: std_logic;
- signal read_after_empty: std_logic;
-
-component BUFG
- port (
- I: IN std_logic;
- O: OUT std_logic);
-end component;
-
-component RAMB16_S18_S18
- port (
- ADDRA: IN std_logic_vector(9 downto 0);
- ADDRB: IN std_logic_vector(9 downto 0);
- DIA: IN std_logic_vector(15 downto 0);
- DIB: IN std_logic_vector(15 downto 0);
- DIPA: IN std_logic_vector(1 downto 0);
- DIPB: IN std_logic_vector(1 downto 0);
- WEA: IN std_logic;
- WEB: IN std_logic;
- CLKA: IN std_logic;
- CLKB: IN std_logic;
- SSRA: IN std_logic;
- SSRB: IN std_logic;
- ENA: IN std_logic;
- ENB: IN std_logic;
- DOA: OUT std_logic_vector(15 downto 0);
- DOB: OUT std_logic_vector(15 downto 0);
- DOPA: OUT std_logic_vector(1 downto 0);
- DOPB: OUT std_logic_vector(1 downto 0));
-end component;
-
-begin
- read_enable <= read_enable_in;
- write_enable <= write_enable_in;
- fifo_gsr <= fifo_gsr_in;
- write_data <= write_data_in;
- read_data_out <= read_data;
-
- full_out <= full;
- gnd_bus <= "000000000000000000";
- gnd <= '0';
- pwr <= '1';
- empty_out <= (empty or read_after_write) and read_after_empty;
- clock <= clock_in;
-
---------------------------------------------------------------------------
--- --
--- Block RAM instantiation for FifO. Module is 1024x18, of which one --
--- address location is sacrificed for the overall speed of the design. --
--- --
---------------------------------------------------------------------------
-
-bram1: RAMB16_S18_S18 port map (ADDRA => read_addr, ADDRB => write_addr,
- DIA => gnd_bus(17 downto 2), DIPA => gnd_bus(1 downto 0),
- DIB => write_data(17 downto 2), DIPB => write_data(1 downto 0),
- WEA => gnd, WEB => pwr, CLKA => clock, CLKB => clock,
- SSRA => gnd, SSRB => gnd, ENA => read_allow, ENB => write_allow,
- DOA => read_data(17 downto 2), DOPA => read_data(1 downto 0),
- DOB => open, DOPB => open );
-
----------------------------------------------------------------
--- --
--- Set allow flags, which control the clock enables for --
--- read, write, and count operations. --
--- --
----------------------------------------------------------------
-
-write_allow <= write_enable AND NOT fullg;
-read_allow <= (read_enable or read_after_write) AND NOT empty;-- ;
-fcnt_allow <= write_allow XOR read_allow; -- and not read_after_write
-
-proc33: process (clock)
-begin
- if rising_edge(clock) then
- if (fifo_gsr = '1') then
- read_after_write <= '0';
- else
- if empty = '1' and read_after_empty='1' and write_enable = '1' then
- read_after_write <= '1';
- else
- read_after_write <= '0';
- end if;
- end if;
- end if;
-end process;
-
-process(clock)
- begin
- if rising_edge(clock) then
- if fifo_gsr = '1' or (empty = '0' and emptyg = '1') then
- read_after_empty <= empty;
- elsif read_enable_in = '1' then
- read_after_empty <= '1';
- end if;
- end if;
- end process;
-
----------------------------------------------------------------
--- --
--- Empty flag is set on fifo_gsr (initial), or when on the --
--- next clock cycle, Write Enable is low, and either the --
--- FifOcount is equal to 0, or it is equal to 1 and Read --
--- Enable is high (about to go Empty). --
--- --
----------------------------------------------------------------
-
-ra_or_fcnt0 <= (read_allow OR NOT fcounter(0));
-
-emptyg <= (not or_all(fcounter(9 downto 1)) AND ra_or_fcnt0) AND NOT write_allow;
-
-proc3: process (clock, fifo_gsr)
-begin
- if rising_edge(clock) then
- if (fifo_gsr = '1') then
- empty <= '1';
- else
- empty <= emptyg;
- end if;
- end if;
-end process proc3;
-
----------------------------------------------------------------
--- --
--- Full flag is set on fifo_gsr (but it is cleared on the --
--- first valid clock edge after fifo_gsr is removed), or --
--- when on the next clock cycle, Read Enable is low, and --
--- either the FifOcount is equal to 3FF (hex), or it is --
--- equal to 3FE and the Write Enable is high (about to go --
--- Full). --
--- --
----------------------------------------------------------------
-
---wa_or_fcnt0 <= (write_allow OR fcounter(0));
-wa_or_fcnt0 <= fcounter(0);
-fullg <= (and_all(fcounter(9 downto 1)) AND wa_or_fcnt0 AND NOT read_allow);
-
-proc4: process (clock, fifo_gsr)
-begin
- if rising_edge(clock) then
- if (fifo_gsr = '1') then
- full <= '1';
- else
- full <= fullg;
- end if;
- end if;
-end process proc4;
-
-----------------------------------------------------------------
--- --
--- Generation of Read and Write address pointers. They now --
--- use binary counters, because it is simpler in simulation, --
--- and the previous LFSR implementation wasn't in the --
--- critical path. --
--- --
-----------------------------------------------------------------
-
-proc5: process (clock, fifo_gsr)
-begin
- if rising_edge(clock) then
- if (fifo_gsr = '1') then
- read_addr <= (others => '0');
- elsif (read_allow = '1') then
- read_addr <= read_addr + '1';
- end if;
- end if;
-end process proc5;
-
-proc6: process (clock, fifo_gsr)
-begin
- if rising_edge(clock) then
- if (fifo_gsr = '1') then
- write_addr <= "0000000000";
- elsif (write_allow = '1') then
- write_addr <= write_addr + '1';
- end if;
- end if;
-end process proc6;
-
-----------------------------------------------------------------
--- --
--- Generation of FifOcount outputs. Used to determine how --
--- full FifO is, based on a counter that keeps track of how --
--- many words are in the FifO. Also used to generate Full --
--- and Empty flags. Only the upper four bits of the counter --
--- are sent outside the module. --
--- --
-----------------------------------------------------------------
-
-proc7: process (clock, fifo_gsr)
-begin
- if rising_edge(clock) then
- if (fifo_gsr = '1') then
- fcounter <= "0000000000";
- elsif (fcnt_allow = '1') then
- if (read_allow = '1') then -- and read_after_write = '0'
- fcounter <= fcounter - '1';
- else
- fcounter <= fcounter + '1';
- end if;
- end if;
- end if;
-end process proc7;
-
-fifocount_out <= fcounter(9 downto 6);
-
-end architecture;
-
+++ /dev/null
--- the full endpoint for HADES: trg, data, data, regio
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-
-
-entity trb_net16_endpoint_1_trg_2_api_1_regio is
- generic (
- USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- API_TYPE : channel_config_t := (c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE);
- IBUF_DEPTH : channel_config_t := (0,6,6,6);
- FIFO_TO_INT_DEPTH : channel_config_t := (0,6,6,6);
- FIFO_TO_APL_DEPTH : channel_config_t := (0,6,6,6);
- IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
- INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
- REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- SCTR_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
- SCTR_NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
- --standard values for output registers
- SCTR_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
- --set to 0 for unused ctrl registers to save resources
- SCTR_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
- --set to 0 for each unused bit in a register
- SCTR_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
- --no data / address out?
- SCTR_USE_DATA_PORT : integer := c_NO;
- SCTR_USE_1WIRE_INTERFACE : integer := c_YES;
- SCTR_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- SCTR_INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
- SCTR_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- SCTR_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- SCTR_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
- MED_STAT_OP : in std_logic_vector (15 downto 0);
- MED_CTRL_OP : out std_logic_vector (15 downto 0);
-
- -- LVL1 trigger APL
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- LVL1_GOT_TRIGGER_OUT : out std_logic;
- LVL1_DTYPE_OUT : out std_logic_vector(3 downto 0);
- LVL1_SEQNR_OUT : out std_logic_vector(7 downto 0);
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";
- LVL1_RELEASE_IN : in std_logic := '0';
-
- -- IPU-Data Channel APL
- IPUD_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000";
- IPUD_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00";
- IPUD_APL_DATAREADY_IN : in std_logic := '0';
- IPUD_APL_READ_OUT : out std_logic;
- IPUD_APL_SHORT_TRANSFER_IN: in std_logic := '0';
- IPUD_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0";
- IPUD_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000";
- IPUD_APL_SEND_IN : in std_logic:= '0';
- IPUD_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000";
- IPUD_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- IPUD_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- IPUD_APL_TYP_OUT : out std_logic_vector (2 downto 0);
- IPUD_APL_DATAREADY_OUT : out std_logic;
- IPUD_APL_READ_IN : in std_logic:= '0';
- IPUD_APL_RUN_OUT : out std_logic;
- IPUD_APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
- -- LVL2-Data Channel APL
- LVL2_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000";
- LVL2_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00";
- LVL2_APL_DATAREADY_IN : in std_logic := '0';
- LVL2_APL_READ_OUT : out std_logic;
- LVL2_APL_SHORT_TRANSFER_IN: in std_logic := '0';
- LVL2_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0";
- LVL2_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000";
- LVL2_APL_SEND_IN : in std_logic:= '0';
- LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000";
- LVL2_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- LVL2_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- LVL2_APL_TYP_OUT : out std_logic_vector (2 downto 0);
- LVL2_APL_DATAREADY_OUT : out std_logic;
- LVL2_APL_READ_IN : in std_logic:= '0';
- LVL2_APL_RUN_OUT : out std_logic;
- LVL2_APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
- -- Slow Control Data Port
- SCTR_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
- SCTR_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- SCTR_REGISTERS_IN : in std_logic_vector(32*2**(SCTR_NUM_STAT_REGS)-1 downto 0) := (others => '0');
- SCTR_REGISTERS_OUT : out std_logic_vector(32*2**(SCTR_NUM_CTRL_REGS)-1 downto 0);
- --following ports only used when using internal data port
- SCTR_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- SCTR_READ_ENABLE_OUT : out std_logic;
- SCTR_WRITE_ENABLE_OUT : out std_logic;
- SCTR_DATA_OUT : out std_logic_vector(32-1 downto 0);
- SCTR_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- SCTR_DATAREADY_IN : in std_logic := '0';
- SCTR_NO_MORE_DATA_IN : in std_logic := '0';
- --IDRAM is used if no 1-wire interface, onewire used otherwise
- SCTR_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
- SCTR_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- SCTR_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";
- SCTR_IDRAM_WR_IN : in std_logic := '0';
- SCTR_ONEWIRE_INOUT : inout std_logic;
- --Additional r/w access to ctrl registers
- SCTR_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
- SCTR_EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
- SCTR_EXT_REG_WRITE_IN : in std_logic := '0';
- SCTR_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0) := (others => '0');
- -- Status
- MPLEX_CTRL : in std_logic_vector (31 downto 0) := (others => '0');
- STAT_CTRL_INIT_BUFFER : in std_logic_vector (4*32-1 downto 0) := (others => '0');
- STAT_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');
- STAT_GEN_1 : out std_logic_vector (31 downto 0); -- General Status
- STAT_GEN_2 : out std_logic_vector (31 downto 0); -- General Status
- CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0')
- );
-end entity;
-
-
-
-
-
-architecture trb_net16_endpoint_1_trg_2_api_1_regio_arch of trb_net16_endpoint_1_trg_2_api_1_regio is
-
- component trb_net_onewire is
- generic(
- USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
- CLK_PERIOD : integer := 10 --clk period in ns
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- --connection to 1-wire interface
- ONEWIRE : inout std_logic;
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT : out std_logic_vector(15 downto 0);
- ADDR_OUT : out std_logic_vector(2 downto 0);
- WRITE_OUT: out std_logic;
- TEMP_OUT : out std_logic_vector(11 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_regIO is
- generic (
- REGISTER_WIDTH : integer range 32 to 32 := 32;
- ADDRESS_WIDTH : integer range 8 to 16 := 16;
- NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers
- NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
- --standard values for output registers
- INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '0');
- --set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
- --set to 0 for each unused bit in a register
- USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '1');
- USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
-
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Port to API
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- API_SHORT_TRANSFER_OUT : out std_logic;
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- API_SEND_OUT : out std_logic;
- API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
- -- Receiver port
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_TYP_IN : in std_logic_vector (2 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- -- APL Control port
- API_RUN_IN : in std_logic;
- API_SEQNR_IN : in std_logic_vector (7 downto 0);
-
- --Port to write Unique ID
- IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
- IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
- IDRAM_WR_IN : in std_logic;
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
-
- --Common Register in / out
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- --Custom Register in / out
- REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
- REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
- --Internal Data Port
- DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
- DAT_READ_ENABLE_OUT : out std_logic;
- DAT_WRITE_ENABLE_OUT: out std_logic;
- DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0);
- --Data input can only be used as reaction on read or write access. write operation should return data
- --if successful
- DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
- DAT_DATAREADY_IN : in std_logic;
- DAT_NO_MORE_DATA_IN : in std_logic;
- --finish transmission, when reading from a fifo and it got empty
- --Additional write access to ctrl registers
- EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
- EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
- EXT_REG_WRITE_IN : in std_logic;
- EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_iobuf is
- generic (
- IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
-
- MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read)
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_ERROR_IN: in std_logic_vector (2 downto 0);
-
-
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_GEN: in std_logic_vector (31 downto 0);
- STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_api_base is
- generic (
- API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
- FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
- FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
- FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
- APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in std_logic; --
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL_READ_IN: in std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_MASTER_DATAREADY_OUT: out std_logic;
- INT_MASTER_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_IN: in std_logic;
-
- INT_MASTER_DATAREADY_IN: in std_logic;
- INT_MASTER_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_OUT: out std_logic;
-
-
- INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the SLAVE path)
- INT_SLAVE_DATAREADY_OUT: out std_logic;
- INT_SLAVE_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_IN: in std_logic;
-
- INT_SLAVE_DATAREADY_IN: in std_logic;
- INT_SLAVE_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
- component trb_net16_io_multiplexer is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
- end component;
-
- component trb_net16_term_buf is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic
- );
- end component;
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := 0;
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in std_logic;
-
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out std_logic;
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_GOT_TRM: out std_logic;
- APL_RELEASE_TRM: in std_logic;
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
- -- Status and control port
- );
- end component;
-signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);
-signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0);
-
-signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0);
-signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0);
-
-signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0);
-
-signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0);
-
--- for the connection to the multiplexer
-signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0);
-signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
-signal MED_IO_READ_OUT : std_logic_vector(3 downto 0);
-
-signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0);
-signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0);
-signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0);
-signal MED_IO_READ_IN : std_logic_vector(7 downto 0);
-
-signal buf_APL_DATA_IN : std_logic_vector(3*c_DATA_WIDTH-1 downto 0);
-signal buf_APL_PACKET_NUM_IN : std_logic_vector(3*c_NUM_WIDTH-1 downto 0);
-signal buf_APL_DATAREADY_IN : std_logic_vector(2 downto 0);
-signal buf_APL_READ_OUT : std_logic_vector(2 downto 0);
-signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(2 downto 0);
-signal buf_APL_DTYPE_IN : std_logic_vector(3*4-1 downto 0);
-signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(3*32-1 downto 0);
-signal buf_APL_SEND_IN : std_logic_vector(2 downto 0);
-signal buf_APL_TARGET_ADDRESS_IN : std_logic_vector(3*16-1 downto 0);
-signal buf_APL_DATA_OUT : std_logic_vector(3*c_DATA_WIDTH-1 downto 0);
-signal buf_APL_PACKET_NUM_OUT : std_logic_vector(3*c_NUM_WIDTH-1 downto 0);
-signal buf_APL_DATAREADY_OUT : std_logic_vector(2 downto 0);
-signal buf_APL_READ_IN : std_logic_vector(2 downto 0);
-signal buf_APL_TYP_OUT : std_logic_vector(3*3-1 downto 0);
-signal buf_APL_RUN_OUT : std_logic_vector(2 downto 0);
-signal buf_APL_SEQNR_OUT : std_logic_vector(3*8-1 downto 0);
-
-signal MY_ADDRESS : std_logic_vector(15 downto 0);
-
-signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0);
-signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0);
-signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
-signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0);
-signal buf_STAT_CTRL_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
-signal SCTR_REGIO_STAT : std_logic_vector(31 downto 0);
-
-signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);
-
-signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0);
-signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
-signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
-signal buf_IDRAM_WR_IN : std_logic;
-
-begin
-
- MED_CTRL_OP(15) <= MED_STAT_OP(15);
- MED_CTRL_OP(14 downto 0) <= (others => '0');
-
- --Connections for data channel
- genbuffers : for i in 0 to 3 generate
- geniobuf: if USE_CHANNEL(i) = c_YES generate
- IOBUF: trb_net16_iobuf
- generic map (
- IBUF_DEPTH => IBUF_DEPTH(i),
- IBUF_SECURE_MODE => IBUF_SECURE_MODE(i),
- SBUF_VERSION => 0,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i),
- USE_VENDOR_CORES => c_YES,
- USE_CHECKSUM => cfg_USE_CHECKSUM(i),
- INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA(i),
- REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i)
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
-
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
- MED_READ_OUT => MED_IO_READ_OUT(i),
- MED_ERROR_IN => MED_ERROR_IN,
-
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1),
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_IN => buf_to_apl_INIT_READ(i),
-
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i),
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i),
-
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i),
-
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i),
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i),
-
- -- Status and control port
- STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32),
- STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32),
- CTRL_GEN => buf_CTRL_GEN(32*(i+1)-1 downto i*32),
- STAT_CTRL_IBUF_BUFFER => buf_STAT_CTRL_INIT_BUFFER(32*(i+1)-1 downto i*32)
- );
- genactapi : if API_TYPE(i) = c_API_ACTIVE and i /= 0 generate
- DAT_ACTIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => API_TYPE(i),
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i),
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i),
- FORCE_REPLY => cfg_FORCE_REPLY(i),
- SBUF_VERSION => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- APL_DATAREADY_IN => buf_APL_DATAREADY_IN(i),
- APL_READ_OUT => buf_APL_READ_OUT(i),
- APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(i),
- APL_DTYPE_IN => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),
- APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
- APL_SEND_IN => buf_APL_SEND_IN(i),
- APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((i+1)*16-1 downto i*16),
- -- Receiver port
- APL_DATA_OUT => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- APL_TYP_OUT => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),
- APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(i),
- APL_READ_IN => buf_APL_READ_IN(i),
- -- APL Control port
- APL_RUN_OUT => buf_APL_RUN_OUT(i),
- APL_MY_ADDRESS_IN => MY_ADDRESS,
- APL_SEQNR_OUT => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
- -- Status and control port
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
- );
- end generate;
- genpasapi : if API_TYPE(i) = c_API_PASSIVE and i /= 0 generate
- constant j : integer := i-1;
- begin
- DAT_PASSIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => API_TYPE(i),
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i),
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i),
- FORCE_REPLY => cfg_FORCE_REPLY(i),
- SBUF_VERSION => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
- APL_DATAREADY_IN => buf_APL_DATAREADY_IN(j),
- APL_READ_OUT => buf_APL_READ_OUT(j),
- APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j),
- APL_DTYPE_IN => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4),
- APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32),
- APL_SEND_IN => buf_APL_SEND_IN(j),
- APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((j+1)*16-1 downto j*16),
- -- Receiver port
- APL_DATA_OUT => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
- APL_TYP_OUT => buf_APL_TYP_OUT((j+1)*3-1 downto j*3),
- APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j),
- APL_READ_IN => buf_APL_READ_IN(j),
- -- APL Control port
- APL_RUN_OUT => buf_APL_RUN_OUT(j),
- APL_MY_ADDRESS_IN => MY_ADDRESS,
- APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i),
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i),
- -- Status and control port
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
- );
- end generate;
- gentrgapi : if i = 0 generate
- apl_to_buf_INIT_DATAREADY(0) <= '0';
- apl_to_buf_INIT_DATA(15 downto 0) <= (others => '0');
- apl_to_buf_INIT_PACKET_NUM(1 downto 0) <= "00";
- buf_to_apl_REPLY_READ(0) <= '1';
- trglvl1 : trb_net16_term
- generic map(
- USE_APL_PORT => c_YES,
- SECURE_MODE => std_TERM_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_IN => apl_to_buf_REPLY_READ(i),
-
- INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_OUT => buf_to_apl_INIT_READ(i),
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => LVL1_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => LVL1_SEQNR_OUT,
- APL_GOT_TRM => LVL1_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => LVL1_RELEASE_IN,
- APL_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN
- );
- end generate;
- end generate;
- gentermbuf: if USE_CHANNEL(i) = c_NO generate
- termbuf: trb_net16_term_buf
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
- MED_READ_OUT => MED_IO_READ_OUT(i),
-
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1)
- );
- end generate;
- end generate;
-
-
- buf_APL_DATA_IN(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH) <= IPUD_APL_DATA_IN;
- buf_APL_DATA_IN(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH) <= LVL2_APL_DATA_IN;
- buf_APL_PACKET_NUM_IN(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH) <= IPUD_APL_PACKET_NUM_IN;
- buf_APL_PACKET_NUM_IN(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH) <= LVL2_APL_PACKET_NUM_IN;
- buf_APL_DATAREADY_IN(0) <= IPUD_APL_DATAREADY_IN;
- buf_APL_DATAREADY_IN(1) <= LVL2_APL_DATAREADY_IN;
- IPUD_APL_READ_OUT <= buf_APL_READ_OUT(0);
- LVL2_APL_READ_OUT <= buf_APL_READ_OUT(1);
- buf_APL_SHORT_TRANSFER_IN(0) <= IPUD_APL_SHORT_TRANSFER_IN;
- buf_APL_SHORT_TRANSFER_IN(1) <= LVL2_APL_SHORT_TRANSFER_IN;
- buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN;
- buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN;
- buf_APL_ERROR_PATTERN_IN(1*32-1 downto 0*32) <= IPUD_APL_ERROR_PATTERN_IN;
- buf_APL_ERROR_PATTERN_IN(2*32-1 downto 1*32) <= LVL2_APL_ERROR_PATTERN_IN;
- buf_APL_SEND_IN(0) <= IPUD_APL_SEND_IN;
- buf_APL_SEND_IN(1) <= LVL2_APL_SEND_IN;
- buf_APL_TARGET_ADDRESS_IN(1*16-1 downto 0*16) <= IPUD_APL_TARGET_ADDRESS_IN;
- buf_APL_TARGET_ADDRESS_IN(2*16-1 downto 1*16) <= LVL2_APL_TARGET_ADDRESS_IN;
-
- IPUD_APL_DATA_OUT <= buf_APL_DATA_OUT(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH);
- LVL2_APL_DATA_OUT <= buf_APL_DATA_OUT(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH);
- IPUD_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH);
- LVL2_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH);
- IPUD_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(0);
- LVL2_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(1);
- buf_APL_READ_IN(0) <= IPUD_APL_READ_IN;
- buf_APL_READ_IN(1) <= LVL2_APL_READ_IN;
- IPUD_APL_TYP_OUT <= buf_APL_TYP_OUT(2 downto 0);
- LVL2_APL_TYP_OUT <= buf_APL_TYP_OUT(5 downto 3);
-
- buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN;
- buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN;
- IPUD_APL_RUN_OUT <= buf_APL_RUN_OUT(0);
- LVL2_APL_RUN_OUT <= buf_APL_RUN_OUT(1);
- IPUD_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(1*8-1 downto 0*8);
- LVL2_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(2*8-1 downto 1*8);
-
- gen_regio : if USE_CHANNEL(c_SLOW_CTRL_CHANNEL) = c_YES generate
- regIO : trb_net16_regIO
- generic map(
- REGISTER_WIDTH => 32,
- ADDRESS_WIDTH => 16,
- NUM_STAT_REGS => SCTR_NUM_STAT_REGS,
- NUM_CTRL_REGS => SCTR_NUM_CTRL_REGS,
- --standard values for output registers
- INIT_CTRL_REGS => SCTR_INIT_CTRL_REGS,
- --set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS => SCTR_USED_CTRL_REGS,
- --set to 0 for each unused bit in a register
- USED_CTRL_BITMASK => SCTR_USED_CTRL_BITMASK,
- --no data / address out?
- USE_DAT_PORT => SCTR_USE_DATA_PORT,
- INIT_ADDRESS => SCTR_INIT_ADDRESS,
- INIT_UNIQUE_ID => SCTR_INIT_UNIQUE_ID,
- COMPILE_TIME => SCTR_COMPILE_TIME,
- COMPILE_VERSION => SCTR_COMPILE_VERSION,
- HARDWARE_VERSION => SCTR_HARDWARE_VERSION
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Port to API
- API_DATA_OUT => buf_APL_DATA_IN(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH),
- API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH),
- API_DATAREADY_OUT => buf_APL_DATAREADY_IN(2),
- API_READ_IN => buf_APL_READ_OUT(2),
- API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(2),
- API_DTYPE_OUT => buf_APL_DTYPE_IN(3*4-1 downto 2*4),
- API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN(3*32-1 downto 2*32),
- API_SEND_OUT => buf_APL_SEND_IN(2),
- API_TARGET_ADDRESS_OUT => buf_APL_TARGET_ADDRESS_IN(3*16-1 downto 2*16),
- API_DATA_IN => buf_APL_DATA_OUT(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH),
- API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH),
- API_TYP_IN => buf_APL_TYP_OUT(3*3-1 downto 2*3),
- API_DATAREADY_IN => buf_APL_DATAREADY_OUT(2),
- API_READ_OUT => buf_APL_READ_IN(2),
- API_RUN_IN => buf_APL_RUN_OUT(2),
- API_SEQNR_IN => buf_APL_SEQNR_OUT(3*8-1 downto 2*8),
- --Port to write Unique ID
- IDRAM_DATA_IN => buf_IDRAM_DATA_IN,
- IDRAM_DATA_OUT => buf_IDRAM_DATA_OUT,
- IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN,
- IDRAM_WR_IN => buf_IDRAM_WR_IN,
- MY_ADDRESS_OUT => MY_ADDRESS,
- --Common Register in / out
- COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN,
- COMMON_CTRL_REG_OUT => SCTR_COMMON_CTRL_REG_OUT,
- --Custom Register in / out
- REGISTERS_IN => SCTR_REGISTERS_IN,
- REGISTERS_OUT => SCTR_REGISTERS_OUT,
- --following ports only used when no internal register is accessed
- DAT_ADDR_OUT => SCTR_ADDR_OUT,
- DAT_READ_ENABLE_OUT => SCTR_READ_ENABLE_OUT,
- DAT_WRITE_ENABLE_OUT => SCTR_WRITE_ENABLE_OUT,
- DAT_DATA_OUT => SCTR_DATA_OUT,
- DAT_DATA_IN => SCTR_DATA_IN,
- DAT_DATAREADY_IN => SCTR_DATAREADY_IN,
- DAT_NO_MORE_DATA_IN => SCTR_NO_MORE_DATA_IN,
- EXT_REG_DATA_IN => SCTR_EXT_REG_DATA_IN,
- EXT_REG_DATA_OUT => SCTR_EXT_REG_DATA_OUT,
- EXT_REG_WRITE_IN => SCTR_EXT_REG_WRITE_IN,
- EXT_REG_ADDR_IN => SCTR_EXT_REG_ADDR_IN,
- STAT => SCTR_REGIO_STAT
- );
- end generate;
-
- gen_no1wire : if SCTR_USE_1WIRE_INTERFACE = 0 generate
- buf_IDRAM_DATA_IN <= SCTR_IDRAM_DATA_IN;
- buf_IDRAM_ADDR_IN <= SCTR_IDRAM_ADDR_IN;
- buf_IDRAM_WR_IN <= SCTR_IDRAM_WR_IN;
- SCTR_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;
- SCTR_ONEWIRE_INOUT <= '0';
- buf_COMMON_STAT_REG_IN <= SCTR_COMMON_STAT_REG_IN;
- end generate;
- gen_1wire : if SCTR_USE_1WIRE_INTERFACE = 1 generate
- buf_COMMON_STAT_REG_IN(19 downto 0) <= SCTR_COMMON_STAT_REG_IN(19 downto 0);
- buf_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32) <= SCTR_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32);
-
- SCTR_IDRAM_DATA_OUT <= (others => '0');
-
- onewire_interface : trb_net_onewire
- generic map(
- USE_TEMPERATURE_READOUT => c_YES,
- CLK_PERIOD => 10
- )
- port map(
- CLK => CLK,
- RESET => RESET,
- --connection to 1-wire interface
- ONEWIRE => SCTR_ONEWIRE_INOUT,
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT => buf_IDRAM_DATA_IN,
- ADDR_OUT => buf_IDRAM_ADDR_IN,
- WRITE_OUT=> buf_IDRAM_WR_IN,
- TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20),
- STAT => open
- );
- end generate;
-
-
- MPLEX: trb_net16_io_multiplexer
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
- INT_DATAREADY_OUT => MED_IO_DATAREADY_IN,
- INT_DATA_OUT => MED_IO_DATA_IN,
- INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN,
- INT_READ_IN => MED_IO_READ_OUT,
- INT_DATAREADY_IN => MED_IO_DATAREADY_OUT,
- INT_DATA_IN => MED_IO_DATA_OUT,
- INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT,
- INT_READ_OUT => MED_IO_READ_IN,
- CTRL => MPLEX_CTRL
- );
-
-
-buf_STAT_CTRL_INIT_BUFFER <= STAT_CTRL_INIT_BUFFER;
-buf_CTRL_GEN <= CTRL_GEN;
-STAT_GEN_1 <= (others => '0');
-STAT_GEN_2 <= (others => '0');
-
-end architecture;
-
+++ /dev/null
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-
-
-entity trb_net16_endpoint_2_trg is
- generic (
- --channel numbers
- LVL1_CHANNEL_NUM : integer := 0;
- LVL2_CHANNEL_NUM : integer := 1;
- --register error_pattern_in?
- LVL1_SECURE_MODE : integer := std_TERM_SECURE_MODE;
- LVL2_SECURE_MODE : integer := std_TERM_SECURE_MODE
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
- MED_STAT_OP : in std_logic_vector (15 downto 0);
- MED_CTRL_OP : out std_logic_vector (15 downto 0);
-
- -- LVL1 trigger APL
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- LVL1_GOT_TRIGGER_OUT : out std_logic;
- LVL1_DTYPE_OUT : out std_logic_vector(3 downto 0);
- LVL1_SEQNR_OUT : out std_logic_vector(7 downto 0);
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- LVL1_RELEASE_IN : in std_logic;
-
- -- LVL2 trigger APL
- LVL2_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- LVL2_GOT_TRIGGER_OUT : out std_logic;
- LVL2_DTYPE_OUT : out std_logic_vector(3 downto 0);
- LVL2_SEQNR_OUT : out std_logic_vector(7 downto 0);
- LVL2_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- LVL2_RELEASE_IN : in std_logic
- );
-end entity;
-
-
-
-
-
-architecture trb_net16_endpoint_2_trg_arch of trb_net16_endpoint_2_trg is
-
-
-
- component trb_net16_iobuf is
- generic (
- IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
-
- MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read)
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_ERROR_IN: in std_logic_vector (2 downto 0);
-
-
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_GEN: in std_logic_vector (31 downto 0);
- STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0)
- );
- end component;
-
-
-
- component trb_net16_io_multiplexer is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
- end component;
-
- component trb_net16_term_buf is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic
- );
- end component;
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := 0;
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in std_logic;
-
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out std_logic;
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_GOT_TRM: out std_logic;
- APL_RELEASE_TRM: in std_logic;
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
- -- Status and control port
- );
- end component;
- constant channels : integer := 2**(c_MUX_WIDTH-1);
-signal apl_to_buf_INIT_DATAREADY: std_logic_vector(channels-1 downto 0);
-signal apl_to_buf_INIT_DATA : std_logic_vector (channels*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (channels*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_READ : std_logic_vector(channels-1 downto 0);
-
-signal buf_to_apl_INIT_DATAREADY: std_logic_vector(channels-1 downto 0);
-signal buf_to_apl_INIT_DATA : std_logic_vector (channels*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (channels*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_READ : std_logic_vector(channels-1 downto 0);
-
-signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(channels-1 downto 0);
-signal apl_to_buf_REPLY_DATA : std_logic_vector (channels*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (channels*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_READ : std_logic_vector(channels-1 downto 0);
-
-signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(channels-1 downto 0);
-signal buf_to_apl_REPLY_DATA : std_logic_vector (channels*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (channels*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_READ : std_logic_vector(channels-1 downto 0);
-
--- for the connection to the multiplexer
-signal MED_IO_DATAREADY_IN : std_logic_vector(channels-1 downto 0);
-signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
-signal MED_IO_READ_OUT : std_logic_vector(channels-1 downto 0);
-
-signal MED_IO_DATAREADY_OUT : std_logic_vector(channels*2-1 downto 0);
-signal MED_IO_DATA_OUT : std_logic_vector (channels*2*c_DATA_WIDTH-1 downto 0);
-signal MED_IO_PACKET_NUM_OUT : std_logic_vector (channels*2*c_NUM_WIDTH-1 downto 0);
-signal MED_IO_READ_IN : std_logic_vector(channels*2-1 downto 0);
-
-signal MY_ADDRESS : std_logic_vector(15 downto 0);
-
-signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (channels*32-1 downto 0);
-signal buf_STAT_GEN : std_logic_vector(32*channels-1 downto 0);
-signal buf_STAT_INIT_BUFFER : std_logic_vector(32*channels-1 downto 0);
-signal buf_CTRL_GEN : std_logic_vector(32*channels-1 downto 0);
-signal buf_STAT_CTRL_INIT_BUFFER : std_logic_vector(32*channels-1 downto 0);
-signal SCTR_REGIO_STAT : std_logic_vector(31 downto 0);
-
-signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);
-
-
-begin
-
- MED_CTRL_OP(15) <= MED_STAT_OP(15);
- MED_CTRL_OP(14 downto 0) <= (others => '0');
-
- --Connections for data channel
- genbuffers : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
- geniobuf: if i = LVL1_CHANNEL_NUM or i = LVL2_CHANNEL_NUM generate
- IOBUF: trb_net16_iobuf
- generic map (
- IBUF_DEPTH => 0,
- IBUF_SECURE_MODE => c_YES,
- SBUF_VERSION => 0,
- USE_ACKNOWLEDGE => c_NO,
- USE_VENDOR_CORES => c_YES,
- USE_CHECKSUM => c_NO,
- INIT_CAN_SEND_DATA => c_NO,
- REPLY_CAN_SEND_DATA => c_YES
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
-
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
- MED_READ_OUT => MED_IO_READ_OUT(i),
- MED_ERROR_IN => MED_ERROR_IN,
-
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1),
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_IN => buf_to_apl_INIT_READ(i),
-
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i),
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i),
-
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i),
-
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i),
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i),
-
- -- Status and control port
- STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32),
- STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32),
- CTRL_GEN => (others => '0'),
- STAT_CTRL_IBUF_BUFFER => (others => '0')
- );
-
-
- genlvl1 : if i = LVL1_CHANNEL_NUM generate
- apl_to_buf_INIT_DATAREADY(i) <= '0';
- apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
- apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= "00";
- buf_to_apl_REPLY_READ(i) <= '1';
- trglvl1 : trb_net16_term
- generic map(
- USE_APL_PORT => c_YES,
- SECURE_MODE => LVL1_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_IN => apl_to_buf_REPLY_READ(i),
-
- INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_OUT => buf_to_apl_INIT_READ(i),
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => LVL1_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => LVL1_SEQNR_OUT,
- APL_GOT_TRM => LVL1_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => LVL1_RELEASE_IN,
- APL_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN
- );
- end generate;
- genlvl2 : if i = LVL2_CHANNEL_NUM generate
- apl_to_buf_INIT_DATAREADY(i) <= '0';
- apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
- apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= "00";
- buf_to_apl_REPLY_READ(i) <= '1';
- trglvl1 : trb_net16_term
- generic map(
- USE_APL_PORT => c_YES,
- SECURE_MODE => LVL2_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_IN => apl_to_buf_REPLY_READ(i),
-
- INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_OUT => buf_to_apl_INIT_READ(i),
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => LVL2_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => LVL2_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => LVL2_SEQNR_OUT,
- APL_GOT_TRM => LVL2_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => LVL2_RELEASE_IN,
- APL_ERROR_PATTERN_IN => LVL2_ERROR_PATTERN_IN
- );
- end generate;
- end generate;
- gentermbuf: if i /= LVL1_CHANNEL_NUM and i /= LVL2_CHANNEL_NUM generate
- termbuf: trb_net16_term_buf
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
- MED_READ_OUT => MED_IO_READ_OUT(i),
-
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1)
- );
- end generate;
- end generate;
-
-
- MPLEX: trb_net16_io_multiplexer
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
- INT_DATAREADY_OUT => MED_IO_DATAREADY_IN,
- INT_DATA_OUT => MED_IO_DATA_IN,
- INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN,
- INT_READ_IN => MED_IO_READ_OUT,
- INT_DATAREADY_IN => MED_IO_DATAREADY_OUT,
- INT_DATA_IN => MED_IO_DATA_OUT,
- INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT,
- INT_READ_OUT => MED_IO_READ_IN,
- CTRL => (others => '0')
- );
-
-
-end architecture;
-
+++ /dev/null
-
--- NOT UP TO DATE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
--- this is an trigger receiver combined with a passive api
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net16_endpoint_2_trg_1_api is
-
- generic (
- --api type for data channel
- API_TYPE : integer range 0 to 1 := 0;
- --Fifo for data channel
- DAT_INIT_DEPTH : integer range 0 to 7 := 2;
- DAT_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here
- DAT_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1;
- DAT_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1;
- --SBUF_DATA_VERSION : integer range 0 to 1 := 0;
- --Fifo for TRG channel
- TRG1_INIT_DEPTH : integer range 0 to 7 := 0;
- TRG1_REPLY_DEPTH : integer range 0 to 7 := 0;
- TRG1_SECURE_MODE : integer range 0 to 1 := 0;
- TRG2_INIT_DEPTH : integer range 0 to 7 := 0;
- TRG2_REPLY_DEPTH : integer range 0 to 7 := 0;
- TRG2_SECURE_MODE : integer range 0 to 1 := 0;
- --SBUF_TRG_VERSION : integer range 0 to 1 := 0;
- --Multiplexer
- MUX_WIDTH : integer range 1 to 5 := 3;
- MUX_SECURE_MODE : integer range 0 to 1 := 0;
- TRG1_CHANNEL : integer range 0 to 3 := 0; --range 0 to 2**(MUX_WIDTH-1)
- TRG2_CHANNEL : integer range 0 to 3 := 1; --range 0 to 2**(MUX_WIDTH-1)
- DAT_CHANNEL : integer range 0 to 3 := 3; --range 0 to 2**(MUX_WIDTH-1)
- --General
- DATA_WIDTH : integer range 16 to 16 := 16;
- NUM_WIDTH : integer range 2 to 2 := 2
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_READ_IN: in std_logic; -- Media is reading
- MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- -- APL Transceiver port
- APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in std_logic; --
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in std_logic; -- Release sending of the data
- APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL_READ_IN: in std_logic; -- Read data word
- APL_RUN_OUT: out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0);
-
- -- TRG1 Receiver port
- TRG1_GOT_TRIGGER_OUT : out std_logic;
- TRG1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- TRG1_DTYPE_OUT : out std_logic_vector(3 downto 0);
- TRG1_SEQNR_OUT : out std_logic_vector(7 downto 0);
- TRG1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- TRG1_RELEASE_IN : in std_logic;
-
- -- TRG2 Receiver port
- TRG2_GOT_TRIGGER_OUT : out std_logic;
- TRG2_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- TRG2_DTYPE_OUT : out std_logic_vector(3 downto 0);
- TRG2_SEQNR_OUT : out std_logic_vector(7 downto 0);
- TRG2_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- TRG2_RELEASE_IN : in std_logic;
-
- -- Status and control port => for debugging
- STAT_DAT_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_DAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_DAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_DAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- STAT_DAT_api_control_signals: out std_logic_vector(31 downto 0);
- CTRL_DAT_GEN: in std_logic_vector (31 downto 0);
- CTRL_DAT_LOCKED: in std_logic_vector (31 downto 0);
- STAT_DAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_DAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
- STAT_TRG1_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_TRG1_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_TRG1_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_TRG1_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- STAT_TRG1_api_control_signals: out std_logic_vector(31 downto 0);
- CTRL_TRG1_GEN: in std_logic_vector (31 downto 0);
- CTRL_TRG1_LOCKED: in std_logic_vector (31 downto 0);
- STAT_TRG1_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_TRG1_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
- STAT_TRG2_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_TRG2_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_TRG2_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_TRG2_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- STAT_TRG2_api_control_signals: out std_logic_vector(31 downto 0);
- CTRL_TRG2_GEN: in std_logic_vector (31 downto 0);
- CTRL_TRG2_LOCKED: in std_logic_vector (31 downto 0);
- STAT_TRG2_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_TRG2_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
- STAT_MPLEX: out std_logic_vector(31 downto 0);
- MPLEX_CTRL: in std_logic_vector (31 downto 0);
- DAT_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- DAT_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-end entity;
-
-architecture trb_net16_endpoint_2_trg_1_api_arch of trb_net16_endpoint_2_trg_1_api_endpoint is
-
- component trb_net16_iobuf is
-
- generic (
- INIT_DEPTH : integer := 1;
- REPLY_DEPTH : integer := 1
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_INIT_READ_IN: in std_logic; -- Media is reading
-
- MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_REPLY_READ_IN: in std_logic; -- Media is reading
-
- MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
- INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- CTRL_GEN: in std_logic_vector (31 downto 0);
- CTRL_LOCKED: in std_logic_vector (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_api_base is
- generic (API_TYPE : integer := API_TYPE; -- type of api: 0 passive, 1 active
- --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
- FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium
- FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path
- -- if set to 0, no buffer is used
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
- APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN : in std_logic; --
- APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN : in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
- APL_READ_IN : in std_logic; -- Read data word
- -- APL Control port
- APL_RUN_OUT : out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- INT_MASTER_DATAREADY_OUT : out std_logic;
- INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
- INT_MASTER_READ_IN : in std_logic;
- INT_MASTER_DATAREADY_IN : in std_logic;
- INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
- INT_MASTER_READ_OUT : out std_logic;
- INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR
- INT_SLAVE_DATAREADY_OUT : out std_logic;
- INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
- INT_SLAVE_READ_IN : in std_logic;
- INT_SLAVE_DATAREADY_IN : in std_logic;
- INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
- INT_SLAVE_READ_OUT : out std_logic;
- -- Status and control port
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := 1;
- SECURE_MODE : integer range 0 to 1 := 0
- --if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these must be available when hold_trm goes low
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- INT_READ_IN: in std_logic;
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_READ_OUT: out std_logic;
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_GOT_TRM: out std_logic;
- APL_RELEASE_TRM: in std_logic;
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
- -- Status and control port
- );
- end component;
-
- component trb_net16_io_multiplexer is
- generic (
- DATA_WIDTH : integer := 16;
- NUM_WIDTH : integer := 2;
- MUX_WIDTH : integer range 1 to 5 := 3;
- MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not?
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);
- MED_READ_IN: in std_logic;
- -- Internal direction port
- INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
- INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
- INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
- INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
- INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
- INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
- -- Status and control port
- CTRL: in std_logic_vector (31 downto 0);
- STAT: out std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_term_buf is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0);
- MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- MED_INIT_READ_IN: in std_logic;
- MED_INIT_DATAREADY_IN: in std_logic;
- MED_INIT_DATA_IN: in std_logic_vector (15 downto 0);
- MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_INIT_READ_OUT: out std_logic;
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0);
- MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
- MED_REPLY_DATAREADY_IN: in std_logic;
- MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0);
- MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_REPLY_READ_OUT: out std_logic
- );
- end component;
-signal apl_to_buf_DAT_INIT_DATAREADY: std_logic;
-signal apl_to_buf_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_DAT_INIT_READ : std_logic;
-
-signal buf_to_apl_DAT_INIT_DATAREADY: std_logic;
-signal buf_to_apl_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_DAT_INIT_READ : std_logic;
-
-signal apl_to_buf_DAT_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_DAT_REPLY_READ : std_logic;
-
-signal buf_to_apl_DAT_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_DAT_REPLY_READ : std_logic;
-
-signal apl_to_buf_TRG1_INIT_DATAREADY: std_logic;
-signal apl_to_buf_TRG1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG1_INIT_READ : std_logic;
-
-signal buf_to_apl_TRG1_INIT_DATAREADY: std_logic;
-signal buf_to_apl_TRG1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG1_INIT_READ : std_logic;
-
-signal apl_to_buf_TRG1_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_TRG1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG1_REPLY_READ : std_logic;
-
-signal buf_to_apl_TRG1_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_TRG1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG1_REPLY_READ : std_logic;
-
-signal apl_to_buf_TRG2_INIT_DATAREADY: std_logic;
-signal apl_to_buf_TRG2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG2_INIT_READ : std_logic;
-
-signal buf_to_apl_TRG2_INIT_DATAREADY: std_logic;
-signal buf_to_apl_TRG2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG2_INIT_READ : std_logic;
-
-signal apl_to_buf_TRG2_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_TRG2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG2_REPLY_READ : std_logic;
-
-signal buf_to_apl_TRG2_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_TRG2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG2_REPLY_READ : std_logic;
-
--- for the connection to the multiplexer
-signal MED_DAT_INIT_DATAREADY_OUT : std_logic;
-signal MED_DAT_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT_INIT_READ_IN : std_logic;
-
-signal MED_DAT_INIT_DATAREADY_IN : std_logic;
-signal MED_DAT_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT_INIT_READ_OUT : std_logic;
-
-signal MED_DAT_REPLY_DATAREADY_OUT : std_logic;
-signal MED_DAT_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT_REPLY_READ_IN : std_logic;
-
-signal MED_DAT_REPLY_DATAREADY_IN : std_logic;
-signal MED_DAT_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT_REPLY_READ_OUT : std_logic;
-
-signal MED_TRG1_INIT_DATAREADY_OUT : std_logic_vector(1 downto 0);
-signal MED_TRG1_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG1_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG1_INIT_READ_IN : std_logic_vector(1 downto 0);
-
-signal MED_TRG1_INIT_DATAREADY_IN : std_logic_vector(1 downto 0);
-signal MED_TRG1_INIT_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG1_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG1_INIT_READ_OUT : std_logic_vector(1 downto 0);
-
-signal MED_TRG1_REPLY_DATAREADY_OUT : std_logic_vector(1 downto 0);
-signal MED_TRG1_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG1_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG1_REPLY_READ_IN : std_logic_vector(1 downto 0);
-
-signal MED_TRG1_REPLY_DATAREADY_IN : std_logic_vector(1 downto 0);
-signal MED_TRG1_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG1_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG1_REPLY_READ_OUT : std_logic_vector(1 downto 0);
-
-signal MED_TRG2_INIT_DATAREADY_OUT : std_logic_vector(1 downto 0);
-signal MED_TRG2_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG2_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG2_INIT_READ_IN : std_logic_vector(1 downto 0);
-
-signal MED_TRG2_INIT_DATAREADY_IN : std_logic_vector(1 downto 0);
-signal MED_TRG2_INIT_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG2_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG2_INIT_READ_OUT : std_logic_vector(1 downto 0);
-
-signal MED_TRG2_REPLY_DATAREADY_OUT : std_logic_vector(1 downto 0);
-signal MED_TRG2_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG2_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG2_REPLY_READ_IN : std_logic_vector(1 downto 0);
-
-signal MED_TRG2_REPLY_DATAREADY_IN : std_logic_vector(1 downto 0);
-signal MED_TRG2_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG2_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG2_REPLY_READ_OUT : std_logic_vector(1 downto 0);
-
-signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
-signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
-signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-
-signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
-signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-
-begin
-
- --Connections for data and trigger channel
- genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate
- gendat: if i = DAT_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_DAT_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_DAT_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT_REPLY_PACKET_NUM_OUT;
- MED_DAT_INIT_READ_IN <= m_READ_IN(i*2);
- MED_DAT_REPLY_READ_IN <= m_READ_IN(i*2+1);
- MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
- MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_DAT_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
- MED_DAT_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
- MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
- MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
- m_READ_OUT(i*2) <= MED_DAT_INIT_READ_OUT;
- m_READ_OUT(i*2+1) <= MED_DAT_REPLY_READ_OUT;
- end generate;
- gentrg1: if i = TRG1_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_TRG1_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_TRG1_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG1_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG1_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG1_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG1_REPLY_PACKET_NUM_OUT;
- MED_TRG1_INIT_READ_IN <= m_READ_IN(i*2);
- MED_TRG1_REPLY_READ_IN <= m_READ_IN(i*2+1);
- MED_TRG1_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
- MED_TRG1_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_TRG1_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
- MED_TRG1_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
- MED_TRG1_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
- MED_TRG1_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
- m_READ_OUT(i*2) <= MED_TRG1_INIT_READ_OUT;
- m_READ_OUT(i*2+1) <= MED_TRG1_REPLY_READ_OUT;
- end generate;
- gentrg1: if i = TRG2_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_TRG2_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_TRG2_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG2_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG2_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG2_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG2_REPLY_PACKET_NUM_OUT;
- MED_TRG2_INIT_READ_IN <= m_READ_IN(i*2);
- MED_TRG2_REPLY_READ_IN <= m_READ_IN(i*2+1);
- MED_TRG2_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
- MED_TRG2_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_TRG2_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
- MED_TRG2_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
- MED_TRG2_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
- MED_TRG2_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
- m_READ_OUT(i*2) <= MED_TRG2_INIT_READ_OUT;
- m_READ_OUT(i*2+1) <= MED_TRG2_REPLY_READ_OUT;
- end generate;
- genelse: if i /= DAT_CHANNEL and i /= TRG1_CHANNEL and i /= TRG2_CHANNEL generate
- termbuf: trb_net16_term_buf
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
- MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
- MED_INIT_READ_IN => m_READ_IN(i*2),
- MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),
- MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
- MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
- MED_INIT_READ_OUT => m_READ_OUT(i*2),
-
- MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
- MED_REPLY_READ_IN => m_READ_IN(i*2+1),
- MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1),
- MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
- MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
- MED_REPLY_READ_OUT => m_READ_OUT(i*2+1)
- );
- end generate;
- end generate;
-
- gen_actapi: if API_TYPE = 1 generate
- DAT_ACTIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => 1,
- FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
- INT_MASTER_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_INIT_PACKET_NUM,
- INT_MASTER_READ_IN => apl_to_buf_DAT_INIT_READ,
- INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
- INT_MASTER_DATA_IN => buf_to_apl_DAT_INIT_DATA,
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_INIT_PACKET_NUM,
- INT_MASTER_READ_OUT => buf_to_apl_DAT_INIT_READ,
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
- INT_SLAVE_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_REPLY_PACKET_NUM,
- INT_SLAVE_READ_IN => apl_to_buf_DAT_REPLY_READ,
- INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
- INT_SLAVE_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_REPLY_PACKET_NUM,
- INT_SLAVE_READ_OUT => buf_to_apl_DAT_REPLY_READ,
- -- Status and control port
- STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
- );
- end generate;
-
- gen_pasapi: if API_TYPE = 0 generate
- DAT_PASSIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => 0,
- FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => (others => '0'),
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
- INT_MASTER_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_REPLY_PACKET_NUM,
- INT_MASTER_READ_IN => apl_to_buf_DAT_REPLY_READ,
- INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
- INT_MASTER_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_REPLY_PACKET_NUM,
- INT_MASTER_READ_OUT => buf_to_apl_DAT_REPLY_READ,
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
- INT_SLAVE_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_INIT_PACKET_NUM,
- INT_SLAVE_READ_IN => apl_to_buf_DAT_INIT_READ,
- INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
- INT_SLAVE_DATA_IN => buf_to_apl_DAT_INIT_DATA,
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_INIT_PACKET_NUM,
- INT_SLAVE_READ_OUT => buf_to_apl_DAT_INIT_READ,
- -- Status and control port
- STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
- );
- end generate;
-
-STAT_DAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
-STAT_DAT_api_control_signals(3) <= APL_WRITE_IN;
-STAT_DAT_api_control_signals(4) <= APL_SEND_IN;
-STAT_DAT_api_control_signals(7 downto 5) <= (others => '0');
-STAT_DAT_api_control_signals(10 downto 8) <= apl_to_buf_DAT_INIT_DATA(2 downto 0);
-STAT_DAT_api_control_signals(11) <= apl_to_buf_DAT_INIT_DATAREADY;
-STAT_DAT_api_control_signals(12) <= apl_to_buf_DAT_INIT_READ;
-STAT_DAT_api_control_signals(31 downto 13) <= (others => '0');
-
-
-
-DAT_IOBUF: trb_net16_iobuf
- generic map(
- INIT_DEPTH => DAT_INIT_DEPTH,
- REPLY_DEPTH => DAT_REPLY_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_DAT_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_DAT_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_DAT_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_DAT_INIT_READ_IN,
- MED_INIT_DATAREADY_IN => MED_DAT_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_DAT_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_DAT_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_DAT_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_DAT_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_DAT_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_DAT_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_DAT_REPLY_READ_IN,
- MED_REPLY_DATAREADY_IN => MED_DAT_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_DAT_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_DAT_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_DAT_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_DAT_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_DAT_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_DAT_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_DAT_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_DAT_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_DAT_INIT_READ,
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_DAT_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_DAT_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_DAT_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_DAT_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_DAT_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_DAT_GEN,
- STAT_LOCKED => STAT_DAT_LOCKED,
- STAT_INIT_BUFFER => STAT_DAT_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_DAT_REPLY_BUFFER,
- CTRL_GEN => CTRL_DAT_GEN,
- CTRL_LOCKED => CTRL_DAT_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_DAT_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_DAT_CTRL_REPLY_BUFFER
- );
-
- TRG1_IOBUF: trb_net16_iobuf
- generic map(
- INIT_DEPTH => TRG1_INIT_DEPTH,
- REPLY_DEPTH => TRG1_REPLY_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_TRG1_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_TRG1_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_TRG1_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_TRG1_INIT_READ_IN,
- MED_INIT_DATAREADY_IN => MED_TRG1_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_TRG1_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_TRG1_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_TRG1_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_TRG1_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_TRG1_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_TRG1_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_TRG1_REPLY_READ_IN,
- MED_REPLY_DATAREADY_IN => MED_TRG1_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_TRG1_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_TRG1_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_TRG1_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_TRG1_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_TRG1_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG1_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_TRG1_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_TRG1_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_TRG1_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG1_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_TRG1_INIT_READ,
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG1_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_TRG1_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG1_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_TRG1_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_TRG1_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_TRG1_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG1_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_TRG1_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_TRG1_GEN,
- STAT_LOCKED => STAT_TRG1_LOCKED,
- STAT_INIT_BUFFER => STAT_TRG1_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_TRG1_REPLY_BUFFER,
- CTRL_GEN => CTRL_TRG1_GEN,
- CTRL_LOCKED => CTRL_TRG1_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_TRG1_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_TRG1_CTRL_REPLY_BUFFER
- );
-
- TRG2_IOBUF: trb_net16_iobuf
- generic map(
- INIT_DEPTH => TRG2_INIT_DEPTH,
- REPLY_DEPTH => TRG2_REPLY_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_TRG2_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_TRG2_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_TRG2_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_TRG2_INIT_READ_IN,
- MED_INIT_DATAREADY_IN => MED_TRG2_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_TRG2_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_TRG2_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_TRG2_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_TRG2_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_TRG2_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_TRG2_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_TRG2_REPLY_READ_IN,
- MED_REPLY_DATAREADY_IN => MED_TRG2_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_TRG2_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_TRG2_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_TRG2_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_TRG2_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_TRG2_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG2_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_TRG2_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_TRG2_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_TRG2_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG2_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_TRG2_INIT_READ,
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG2_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_TRG2_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG2_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_TRG2_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_TRG2_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_TRG2_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG2_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_TRG2_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_TRG2_GEN,
- STAT_LOCKED => STAT_TRG2_LOCKED,
- STAT_INIT_BUFFER => STAT_TRG2_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_TRG2_REPLY_BUFFER,
- CTRL_GEN => CTRL_TRG2_GEN,
- CTRL_LOCKED => CTRL_TRG2_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_TRG2_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_TRG2_CTRL_REPLY_BUFFER
- );
-
- MPLEX: trb_net16_io_multiplexer
- generic map (
- DATA_WIDTH => DATA_WIDTH,
- NUM_WIDTH => NUM_WIDTH,
- MUX_WIDTH => MUX_WIDTH,
- MUX_SECURE_MODE => MUX_SECURE_MODE
- )
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
- INT_READ_IN =>m_READ_OUT,
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
- INT_READ_OUT =>m_READ_IN,
- CTRL => MPLEX_CTRL
- );
-
- TRG1_INIT : trb_net16_term
- generic map (
- FIFO_TERM_BUFFER_DEPTH => 0,
- SECURE_MODE => TRG1_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- INT_DATAREADY_OUT => apl_to_buf_TRG1_REPLY_DATAREADY,
- INT_DATA_OUT => apl_to_buf_TRG1_REPLY_DATA,
- INT_PACKET_NUM_OUT => apl_to_buf_TRG1_REPLY_PACKET_NUM,
- INT_READ_IN => apl_to_buf_TRG1_REPLY_READ,
- INT_DATAREADY_IN => buf_to_apl_TRG1_INIT_DATAREADY,
- INT_DATA_IN => buf_to_apl_TRG1_INIT_DATA,
- INT_PACKET_NUM_IN => buf_to_apl_TRG1_INIT_PACKET_NUM,
- INT_READ_OUT => buf_to_apl_TRG1_INIT_READ,
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => TRG1_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => TRG1_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => TRG1_SEQNR_OUT,
- APL_GOT_TRM => TRG1_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => TRG1_RELEASE_IN,
- APL_ERROR_PATTERN_IN => TRG1_ERROR_PATTERN_IN
- -- Status and control port
- );
-
- TRG2_INIT : trb_net16_term
- generic map (
- FIFO_TERM_BUFFER_DEPTH => 0,
- SECURE_MODE => TRG2_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- INT_DATAREADY_OUT => apl_to_buf_TRG2_REPLY_DATAREADY,
- INT_DATA_OUT => apl_to_buf_TRG2_REPLY_DATA,
- INT_PACKET_NUM_OUT => apl_to_buf_TRG2_REPLY_PACKET_NUM,
- INT_READ_IN => apl_to_buf_TRG2_REPLY_READ,
- INT_DATAREADY_IN => buf_to_apl_TRG2_INIT_DATAREADY,
- INT_DATA_IN => buf_to_apl_TRG2_INIT_DATA,
- INT_PACKET_NUM_IN => buf_to_apl_TRG2_INIT_PACKET_NUM,
- INT_READ_OUT => buf_to_apl_TRG2_INIT_READ,
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => TRG2_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => TRG2_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => TRG2_SEQNR_OUT,
- APL_GOT_TRM => TRG2_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => TRG2_RELEASE_IN,
- APL_ERROR_PATTERN_IN => TRG2_ERROR_PATTERN_IN
- -- Status and control port
- );
-
-apl_to_buf_TRG1_INIT_DATAREADY <= '0';
-apl_to_buf_TRG1_INIT_DATA <= (others => '0');
-apl_to_buf_TRG1_INIT_PACKET_NUM <= (others => '0');
-buf_to_apl_TRG1_REPLY_READ <= '1';
-
-apl_to_buf_TRG2_INIT_DATAREADY <= '0';
-apl_to_buf_TRG2_INIT_DATA <= (others => '0');
-apl_to_buf_TRG2_INIT_PACKET_NUM <= (others => '0');
-buf_to_apl_TRG2_REPLY_READ <= '1';
-end architecture;
+++ /dev/null
-
--- NOT UP TO DATE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
--- this is an trigger receiver combined with a passive api
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net16_endpoint_2_trg_2_api is
-
- generic (
- --api type for data channel
- API1_TYPE : integer range 0 to 1 := 0;
- API2_TYPE : integer range 0 to 1 := 0;
- --Fifo for data channel
- DAT1_INIT_DEPTH : integer range 0 to 7 := 2;
- DAT1_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here
- DAT1_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1;
- DAT1_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1;
- DAT2_INIT_DEPTH : integer range 0 to 7 := 2;
- DAT2_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here
- DAT2_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1;
- DAT2_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1;
- --SBUF_DATA_VERSION : integer range 0 to 1 := 0;
- --Fifo for TRG channel
- TRG1_INIT_DEPTH : integer range 0 to 7 := 0;
- TRG1_REPLY_DEPTH : integer range 0 to 7 := 0;
- TRG1_SECURE_MODE : integer range 0 to 1 := 0;
- TRG2_INIT_DEPTH : integer range 0 to 7 := 0;
- TRG2_REPLY_DEPTH : integer range 0 to 7 := 0;
- TRG2_SECURE_MODE : integer range 0 to 1 := 0;
- --SBUF_TRG_VERSION : integer range 0 to 1 := 0;
- --Multiplexer
- MUX_WIDTH : integer range 1 to 5 := 3;
- MUX_SECURE_MODE : integer range 0 to 1 := 0;
- TRG1_CHANNEL : integer range 0 to 3 := 0; --range 0 to 2**(MUX_WIDTH-1)
- TRG2_CHANNEL : integer range 0 to 3 := 1; --range 0 to 2**(MUX_WIDTH-1)
- DAT1_CHANNEL : integer range 0 to 3 := 2; --range 0 to 2**(MUX_WIDTH-1)
- DAT2_CHANNEL : integer range 0 to 3 := 3; --range 0 to 2**(MUX_WIDTH-1)
- --General
- DATA_WIDTH : integer range 16 to 16 := 16;
- NUM_WIDTH : integer range 2 to 2 := 2
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_READ_IN: in std_logic; -- Media is reading
- MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- -- APL1 Transceiver port
- APL1_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
- APL1_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- APL1_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
- APL1_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL1_SHORT_TRANSFER_IN: in std_logic; --
- APL1_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL1_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL1_SEND_IN: in std_logic; -- Release sending of the data
- APL1_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
- APL1_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- APL1_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL1_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL1_READ_IN: in std_logic; -- Read data word
- APL1_RUN_OUT: out std_logic; -- Data transfer is running
- APL1_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL1_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL1_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0);
-
- -- APL2 Transceiver port
- APL2_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
- APL2_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- APL2_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
- APL2_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL2_SHORT_TRANSFER_IN: in std_logic; --
- APL2_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL2_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL2_SEND_IN: in std_logic; -- Release sending of the data
- APL2_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
- APL2_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- APL2_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL2_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL2_READ_IN: in std_logic; -- Read data word
- APL2_RUN_OUT: out std_logic; -- Data transfer is running
- APL2_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL2_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL2_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0);
-
- -- TRG1 Receiver port
- TRG1_GOT_TRIGGER_OUT : out std_logic;
- TRG1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- TRG1_DTYPE_OUT : out std_logic_vector(3 downto 0);
- TRG1_SEQNR_OUT : out std_logic_vector(7 downto 0);
- TRG1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- TRG1_RELEASE_IN : in std_logic;
-
- -- TRG2 Receiver port
- TRG2_GOT_TRIGGER_OUT : out std_logic;
- TRG2_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- TRG2_DTYPE_OUT : out std_logic_vector(3 downto 0);
- TRG2_SEQNR_OUT : out std_logic_vector(7 downto 0);
- TRG2_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- TRG2_RELEASE_IN : in std_logic;
-
- -- Status and control port => for debugging
- STAT_DAT2_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_DAT2_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_DAT2_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_DAT2_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- STAT_DAT2_api_control_signals: out std_logic_vector(31 downto 0);
- CTRL_DAT2_GEN: in std_logic_vector (31 downto 0);
- CTRL_DAT2_LOCKED: in std_logic_vector (31 downto 0);
- STAT_DAT2_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_DAT2_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
- STAT_TRG2_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_TRG2_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_TRG2_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_TRG2_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- STAT_TRG2_api_control_signals: out std_logic_vector(31 downto 0);
- CTRL_TRG2_GEN: in std_logic_vector (31 downto 0);
- CTRL_TRG2_LOCKED: in std_logic_vector (31 downto 0);
- STAT_TRG2_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_TRG2_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
- STAT_MPLEX: out std_logic_vector(31 downto 0);
- MPLEX_CTRL: in std_logic_vector (31 downto 0);
- DAT1_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- DAT1_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- DAT2_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- DAT2_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-end entity;
-
-architecture trb_net16_endpoint_2_trg_2_api_arch of trb_net16_endpoint_2_trg_2_api_endpoint is
-
- component trb_net16_iobuf is
-
- generic (
- INIT_DEPTH : integer := 1;
- REPLY_DEPTH : integer := 1
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_INIT_READ_IN: in std_logic; -- Media is reading
-
- MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_REPLY_READ_IN: in std_logic; -- Media is reading
-
- MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
- INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- CTRL_GEN: in std_logic_vector (31 downto 0);
- CTRL_LOCKED: in std_logic_vector (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_api_base is
- generic (API_TYPE : integer := API_TYPE; -- type of api: 0 passive, 1 active
- --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
- FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium
- FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path
- -- if set to 0, no buffer is used
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
- APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN : in std_logic; --
- APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN : in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
- APL_READ_IN : in std_logic; -- Read data word
- -- APL Control port
- APL_RUN_OUT : out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- INT_MASTER_DATAREADY_OUT : out std_logic;
- INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
- INT_MASTER_READ_IN : in std_logic;
- INT_MASTER_DATAREADY_IN : in std_logic;
- INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
- INT_MASTER_READ_OUT : out std_logic;
- INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR
- INT_SLAVE_DATAREADY_OUT : out std_logic;
- INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
- INT_SLAVE_READ_IN : in std_logic;
- INT_SLAVE_DATAREADY_IN : in std_logic;
- INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
- INT_SLAVE_READ_OUT : out std_logic;
- -- Status and control port
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := 1;
- SECURE_MODE : integer range 0 to 1 := 0
- --if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these must be available when hold_trm goes low
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- INT_READ_IN: in std_logic;
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_READ_OUT: out std_logic;
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_GOT_TRM: out std_logic;
- APL_RELEASE_TRM: in std_logic;
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
- -- Status and control port
- );
- end component;
-
- component trb_net16_io_multiplexer is
- generic (
- DATA_WIDTH : integer := 16;
- NUM_WIDTH : integer := 2;
- MUX_WIDTH : integer range 1 to 5 := 3;
- MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not?
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);
- MED_READ_IN: in std_logic;
- -- Internal direction port
- INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
- INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
- INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
- INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
- INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
- INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
- -- Status and control port
- CTRL: in std_logic_vector (31 downto 0);
- STAT: out std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_term_buf is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0);
- MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- MED_INIT_READ_IN: in std_logic;
- MED_INIT_DATAREADY_IN: in std_logic;
- MED_INIT_DATA_IN: in std_logic_vector (15 downto 0);
- MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_INIT_READ_OUT: out std_logic;
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0);
- MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
- MED_REPLY_DATAREADY_IN: in std_logic;
- MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0);
- MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_REPLY_READ_OUT: out std_logic
- );
- end component;
-signal apl_to_buf_DAT1_INIT_DATAREADY: std_logic;
-signal apl_to_buf_DAT1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_DAT1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_DAT1_INIT_READ : std_logic;
-
-signal buf_to_apl_DAT1_INIT_DATAREADY: std_logic;
-signal buf_to_apl_DAT1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_DAT1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_DAT1_INIT_READ : std_logic;
-
-signal apl_to_buf_DAT1_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_DAT1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_DAT1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_DAT1_REPLY_READ : std_logic;
-
-signal buf_to_apl_DAT1_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_DAT1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_DAT1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_DAT1_REPLY_READ : std_logic;
-
-signal apl_to_buf_DAT2_INIT_DATAREADY: std_logic;
-signal apl_to_buf_DAT2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_DAT2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_DAT2_INIT_READ : std_logic;
-
-signal buf_to_apl_DAT2_INIT_DATAREADY: std_logic;
-signal buf_to_apl_DAT2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_DAT2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_DAT2_INIT_READ : std_logic;
-
-signal apl_to_buf_DAT2_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_DAT2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_DAT2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_DAT2_REPLY_READ : std_logic;
-
-signal buf_to_apl_DAT2_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_DAT2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_DAT2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_DAT2_REPLY_READ : std_logic;
-
-signal apl_to_buf_TRG1_INIT_DATAREADY: std_logic;
-signal apl_to_buf_TRG1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG1_INIT_READ : std_logic;
-
-signal buf_to_apl_TRG1_INIT_DATAREADY: std_logic;
-signal buf_to_apl_TRG1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG1_INIT_READ : std_logic;
-
-signal apl_to_buf_TRG1_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_TRG1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG1_REPLY_READ : std_logic;
-
-signal buf_to_apl_TRG1_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_TRG1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG1_REPLY_READ : std_logic;
-
-signal apl_to_buf_TRG2_INIT_DATAREADY: std_logic;
-signal apl_to_buf_TRG2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG2_INIT_READ : std_logic;
-
-signal buf_to_apl_TRG2_INIT_DATAREADY: std_logic;
-signal buf_to_apl_TRG2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG2_INIT_READ : std_logic;
-
-signal apl_to_buf_TRG2_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_TRG2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG2_REPLY_READ : std_logic;
-
-signal buf_to_apl_TRG2_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_TRG2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG2_REPLY_READ : std_logic;
-
--- for the connection to the multiplexer
-signal MED_DAT1_INIT_DATAREADY_OUT : std_logic;
-signal MED_DAT1_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT1_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT1_INIT_READ_IN : std_logic;
-
-signal MED_DAT1_INIT_DATAREADY_IN : std_logic;
-signal MED_DAT1_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT1_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT1_INIT_READ_OUT : std_logic;
-
-signal MED_DAT1_REPLY_DATAREADY_OUT : std_logic;
-signal MED_DAT1_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT1_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT1_REPLY_READ_IN : std_logic;
-
-signal MED_DAT1_REPLY_DATAREADY_IN : std_logic;
-signal MED_DAT1_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT1_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT1_REPLY_READ_OUT : std_logic;
-
-signal MED_DAT2_INIT_DATAREADY_OUT : std_logic;
-signal MED_DAT2_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT2_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT2_INIT_READ_IN : std_logic;
-
-signal MED_DAT2_INIT_DATAREADY_IN : std_logic;
-signal MED_DAT2_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT2_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT2_INIT_READ_OUT : std_logic;
-
-signal MED_DAT2_REPLY_DATAREADY_OUT : std_logic;
-signal MED_DAT2_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT2_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT2_REPLY_READ_IN : std_logic;
-
-signal MED_DAT2_REPLY_DATAREADY_IN : std_logic;
-signal MED_DAT2_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT2_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT2_REPLY_READ_OUT : std_logic;
-
-signal MED_TRG1_INIT_DATAREADY_OUT : std_logic_vector(1 downto 0);
-signal MED_TRG1_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG1_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG1_INIT_READ_IN : std_logic_vector(1 downto 0);
-
-signal MED_TRG1_INIT_DATAREADY_IN : std_logic_vector(1 downto 0);
-signal MED_TRG1_INIT_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG1_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG1_INIT_READ_OUT : std_logic_vector(1 downto 0);
-
-signal MED_TRG1_REPLY_DATAREADY_OUT : std_logic_vector(1 downto 0);
-signal MED_TRG1_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG1_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG1_REPLY_READ_IN : std_logic_vector(1 downto 0);
-
-signal MED_TRG1_REPLY_DATAREADY_IN : std_logic_vector(1 downto 0);
-signal MED_TRG1_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG1_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG1_REPLY_READ_OUT : std_logic_vector(1 downto 0);
-
-signal MED_TRG2_INIT_DATAREADY_OUT : std_logic_vector(1 downto 0);
-signal MED_TRG2_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG2_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG2_INIT_READ_IN : std_logic_vector(1 downto 0);
-
-signal MED_TRG2_INIT_DATAREADY_IN : std_logic_vector(1 downto 0);
-signal MED_TRG2_INIT_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG2_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG2_INIT_READ_OUT : std_logic_vector(1 downto 0);
-
-signal MED_TRG2_REPLY_DATAREADY_OUT : std_logic_vector(1 downto 0);
-signal MED_TRG2_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG2_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG2_REPLY_READ_IN : std_logic_vector(1 downto 0);
-
-signal MED_TRG2_REPLY_DATAREADY_IN : std_logic_vector(1 downto 0);
-signal MED_TRG2_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0);
-signal MED_TRG2_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0);
-signal MED_TRG2_REPLY_READ_OUT : std_logic_vector(1 downto 0);
-
-signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
-signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
-signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-
-signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
-signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-
-begin
-
- --Connections for data and trigger channel
- genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate
- gendat1: if i = DAT1_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_DAT1_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_DAT1_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT1_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT1_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT1_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT1_REPLY_PACKET_NUM_OUT;
- MED_DAT1_INIT_READ_IN <= m_READ_IN(i*2);
- MED_DAT1_REPLY_READ_IN <= m_READ_IN(i*2+1);
- MED_DAT1_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
- MED_DAT1_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_DAT1_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
- MED_DAT1_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
- MED_DAT1_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
- MED_DAT1_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
- m_READ_OUT(i*2) <= MED_DAT1_INIT_READ_OUT;
- m_READ_OUT(i*2+1) <= MED_DAT1_REPLY_READ_OUT;
- end generate;
- gendat2: if i = DAT2_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_DAT2_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_DAT2_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT2_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT2_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT2_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT2_REPLY_PACKET_NUM_OUT;
- MED_DAT2_INIT_READ_IN <= m_READ_IN(i*2);
- MED_DAT2_REPLY_READ_IN <= m_READ_IN(i*2+1);
- MED_DAT2_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
- MED_DAT2_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_DAT2_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
- MED_DAT2_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
- MED_DAT2_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
- MED_DAT2_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
- m_READ_OUT(i*2) <= MED_DAT2_INIT_READ_OUT;
- m_READ_OUT(i*2+1) <= MED_DAT2_REPLY_READ_OUT;
- end generate;
- gentrg1: if i = TRG1_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_TRG1_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_TRG1_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG1_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG1_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG1_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG1_REPLY_PACKET_NUM_OUT;
- MED_TRG1_INIT_READ_IN <= m_READ_IN(i*2);
- MED_TRG1_REPLY_READ_IN <= m_READ_IN(i*2+1);
- MED_TRG1_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
- MED_TRG1_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_TRG1_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
- MED_TRG1_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
- MED_TRG1_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
- MED_TRG1_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
- m_READ_OUT(i*2) <= MED_TRG1_INIT_READ_OUT;
- m_READ_OUT(i*2+1) <= MED_TRG1_REPLY_READ_OUT;
- end generate;
- gentrg1: if i = TRG2_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_TRG2_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_TRG2_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG2_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG2_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG2_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG2_REPLY_PACKET_NUM_OUT;
- MED_TRG2_INIT_READ_IN <= m_READ_IN(i*2);
- MED_TRG2_REPLY_READ_IN <= m_READ_IN(i*2+1);
- MED_TRG2_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
- MED_TRG2_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_TRG2_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
- MED_TRG2_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
- MED_TRG2_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
- MED_TRG2_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
- m_READ_OUT(i*2) <= MED_TRG2_INIT_READ_OUT;
- m_READ_OUT(i*2+1) <= MED_TRG2_REPLY_READ_OUT;
- end generate;
- genelse: if i /= DAT1_CHANNEL and i /= DAT2_CHANNEL and i /= TRG1_CHANNEL and i /= TRG2_CHANNEL generate
- termbuf: trb_net16_term_buf
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
- MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
- MED_INIT_READ_IN => m_READ_IN(i*2),
- MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),
- MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
- MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
- MED_INIT_READ_OUT => m_READ_OUT(i*2),
-
- MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
- MED_REPLY_READ_IN => m_READ_IN(i*2+1),
- MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1),
- MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
- MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
- MED_REPLY_READ_OUT => m_READ_OUT(i*2+1)
- );
- end generate;
- end generate;
-
- gen_actapi1: if API1_TYPE = 1 generate
- DAT_ACTIVE_API1: trb_net16_api_base
- generic map (
- API_TYPE => 1,
- FIFO_TO_INT_DEPTH => DAT1_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => DAT1_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL1_DATA_IN,
- APL_PACKET_NUM_IN => APL1_PACKET_NUM_IN,
- APL_WRITE_IN => APL1_WRITE_IN,
- APL_FIFO_FULL_OUT => APL1_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL1_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL1_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL1_ERROR_PATTERN_IN,
- APL_SEND_IN => APL1_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL1_TARGET_ADDRESS_IN,
- -- Receiver port
- APL_DATA_OUT => APL1_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL1_PACKET_NUM_OUT,
- APL_TYP_OUT => APL1_TYP_OUT,
- APL_DATAREADY_OUT => APL1_DATAREADY_OUT,
- APL_READ_IN => APL1_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL1_RUN_OUT,
- APL_MY_ADDRESS_IN => APL1_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL1_SEQNR_OUT,
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT1_INIT_DATAREADY,
- INT_MASTER_DATA_OUT => apl_to_buf_DAT1_INIT_DATA,
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT1_INIT_PACKET_NUM,
- INT_MASTER_READ_IN => apl_to_buf_DAT1_INIT_READ,
- INT_MASTER_DATAREADY_IN => buf_to_apl_DAT1_INIT_DATAREADY,
- INT_MASTER_DATA_IN => buf_to_apl_DAT1_INIT_DATA,
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT1_INIT_PACKET_NUM,
- INT_MASTER_READ_OUT => buf_to_apl_DAT1_INIT_READ,
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT1_REPLY_DATAREADY,
- INT_SLAVE_DATA_OUT => apl_to_buf_DAT1_REPLY_DATA,
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT1_REPLY_PACKET_NUM,
- INT_SLAVE_READ_IN => apl_to_buf_DAT1_REPLY_READ,
- INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT1_REPLY_DATAREADY,
- INT_SLAVE_DATA_IN => buf_to_apl_DAT1_REPLY_DATA,
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT1_REPLY_PACKET_NUM,
- INT_SLAVE_READ_OUT => buf_to_apl_DAT1_REPLY_READ,
- -- Status and control port
- STAT_FIFO_TO_INT => DAT1_api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => DAT1_api_stat_fifo_to_apl
- );
- end generate;
-
- gen_pasapi1: if API1_TYPE = 0 generate
- DAT_PASSIVE_API1: trb_net16_api_base
- generic map (
- API_TYPE => 0,
- FIFO_TO_INT_DEPTH => DAT1_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => DAT1_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL1_DATA_IN,
- APL_PACKET_NUM_IN => APL1_PACKET_NUM_IN,
- APL_WRITE_IN => APL1_WRITE_IN,
- APL_FIFO_FULL_OUT => APL1_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL1_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL1_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL1_ERROR_PATTERN_IN,
- APL_SEND_IN => APL1_SEND_IN,
- APL_TARGET_ADDRESS_IN => (others => '0'),
- -- Receiver port
- APL_DATA_OUT => APL1_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL1_PACKET_NUM_OUT,
- APL_TYP_OUT => APL1_TYP_OUT,
- APL_DATAREADY_OUT => APL1_DATAREADY_OUT,
- APL_READ_IN => APL1_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL1_RUN_OUT,
- APL_MY_ADDRESS_IN => APL1_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL1_SEQNR_OUT,
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT1_REPLY_DATAREADY,
- INT_MASTER_DATA_OUT => apl_to_buf_DAT1_REPLY_DATA,
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT1_REPLY_PACKET_NUM,
- INT_MASTER_READ_IN => apl_to_buf_DAT1_REPLY_READ,
- INT_MASTER_DATAREADY_IN => buf_to_apl_DAT1_REPLY_DATAREADY,
- INT_MASTER_DATA_IN => buf_to_apl_DAT1_REPLY_DATA,
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT1_REPLY_PACKET_NUM,
- INT_MASTER_READ_OUT => buf_to_apl_DAT1_REPLY_READ,
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT1_INIT_DATAREADY,
- INT_SLAVE_DATA_OUT => apl_to_buf_DAT1_INIT_DATA,
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT1_INIT_PACKET_NUM,
- INT_SLAVE_READ_IN => apl_to_buf_DAT1_INIT_READ,
- INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT1_INIT_DATAREADY,
- INT_SLAVE_DATA_IN => buf_to_apl_DAT1_INIT_DATA,
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT1_INIT_PACKET_NUM,
- INT_SLAVE_READ_OUT => buf_to_apl_DAT1_INIT_READ,
- -- Status and control port
- STAT_FIFO_TO_INT => DAT1_api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => DAT1_api_stat_fifo_to_apl
- );
- end generate;
-
-STAT_DAT1_api_control_signals(2 downto 0) <= APL1_DATA_IN(2 downto 0);
-STAT_DAT1_api_control_signals(3) <= APL1_WRITE_IN;
-STAT_DAT1_api_control_signals(4) <= APL1_SEND_IN;
-STAT_DAT1_api_control_signals(7 downto 5) <= (others => '0');
-STAT_DAT1_api_control_signals(10 downto 8) <= apl_to_buf_DAT1_INIT_DATA(2 downto 0);
-STAT_DAT1_api_control_signals(11) <= apl_to_buf_DAT1_INIT_DATAREADY;
-STAT_DAT1_api_control_signals(12) <= apl_to_buf_DAT1_INIT_READ;
-STAT_DAT1_api_control_signals(31 downto 13) <= (others => '0');
-
- gen_actapi2: if API2_TYPE = 1 generate
- DAT_ACTIVE_API1: trb_net16_api_base
- generic map (
- API_TYPE => 1,
- FIFO_TO_INT_DEPTH => DAT2_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => DAT2_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL2_DATA_IN,
- APL_PACKET_NUM_IN => APL2_PACKET_NUM_IN,
- APL_WRITE_IN => APL2_WRITE_IN,
- APL_FIFO_FULL_OUT => APL2_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL2_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL2_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL2_ERROR_PATTERN_IN,
- APL_SEND_IN => APL2_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL2_TARGET_ADDRESS_IN,
- -- Receiver port
- APL_DATA_OUT => APL2_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL2_PACKET_NUM_OUT,
- APL_TYP_OUT => APL2_TYP_OUT,
- APL_DATAREADY_OUT => APL2_DATAREADY_OUT,
- APL_READ_IN => APL2_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL2_RUN_OUT,
- APL_MY_ADDRESS_IN => APL2_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL2_SEQNR_OUT,
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT2_INIT_DATAREADY,
- INT_MASTER_DATA_OUT => apl_to_buf_DAT2_INIT_DATA,
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT2_INIT_PACKET_NUM,
- INT_MASTER_READ_IN => apl_to_buf_DAT2_INIT_READ,
- INT_MASTER_DATAREADY_IN => buf_to_apl_DAT2_INIT_DATAREADY,
- INT_MASTER_DATA_IN => buf_to_apl_DAT2_INIT_DATA,
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT2_INIT_PACKET_NUM,
- INT_MASTER_READ_OUT => buf_to_apl_DAT2_INIT_READ,
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT2_REPLY_DATAREADY,
- INT_SLAVE_DATA_OUT => apl_to_buf_DAT2_REPLY_DATA,
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT2_REPLY_PACKET_NUM,
- INT_SLAVE_READ_IN => apl_to_buf_DAT2_REPLY_READ,
- INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT2_REPLY_DATAREADY,
- INT_SLAVE_DATA_IN => buf_to_apl_DAT2_REPLY_DATA,
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT2_REPLY_PACKET_NUM,
- INT_SLAVE_READ_OUT => buf_to_apl_DAT2_REPLY_READ,
- -- Status and control port
- STAT_FIFO_TO_INT => DAT2_api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => DAT2_api_stat_fifo_to_apl
- );
- end generate;
-
- gen_pasapi2: if API2_TYPE = 0 generate
- DAT_PASSIVE_API1: trb_net16_api_base
- generic map (
- API_TYPE => 0,
- FIFO_TO_INT_DEPTH => DAT2_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => DAT2_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL2_DATA_IN,
- APL_PACKET_NUM_IN => APL2_PACKET_NUM_IN,
- APL_WRITE_IN => APL2_WRITE_IN,
- APL_FIFO_FULL_OUT => APL2_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL2_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL2_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL2_ERROR_PATTERN_IN,
- APL_SEND_IN => APL2_SEND_IN,
- APL_TARGET_ADDRESS_IN => (others => '0'),
- -- Receiver port
- APL_DATA_OUT => APL2_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL2_PACKET_NUM_OUT,
- APL_TYP_OUT => APL2_TYP_OUT,
- APL_DATAREADY_OUT => APL2_DATAREADY_OUT,
- APL_READ_IN => APL2_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL2_RUN_OUT,
- APL_MY_ADDRESS_IN => APL2_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL2_SEQNR_OUT,
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT2_REPLY_DATAREADY,
- INT_MASTER_DATA_OUT => apl_to_buf_DAT2_REPLY_DATA,
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT2_REPLY_PACKET_NUM,
- INT_MASTER_READ_IN => apl_to_buf_DAT2_REPLY_READ,
- INT_MASTER_DATAREADY_IN => buf_to_apl_DAT2_REPLY_DATAREADY,
- INT_MASTER_DATA_IN => buf_to_apl_DAT2_REPLY_DATA,
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT2_REPLY_PACKET_NUM,
- INT_MASTER_READ_OUT => buf_to_apl_DAT2_REPLY_READ,
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT2_INIT_DATAREADY,
- INT_SLAVE_DATA_OUT => apl_to_buf_DAT2_INIT_DATA,
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT2_INIT_PACKET_NUM,
- INT_SLAVE_READ_IN => apl_to_buf_DAT2_INIT_READ,
- INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT2_INIT_DATAREADY,
- INT_SLAVE_DATA_IN => buf_to_apl_DAT2_INIT_DATA,
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT2_INIT_PACKET_NUM,
- INT_SLAVE_READ_OUT => buf_to_apl_DAT2_INIT_READ,
- -- Status and control port
- STAT_FIFO_TO_INT => DAT2_api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => DAT2_api_stat_fifo_to_apl
- );
- end generate;
-
-STAT_DAT2_api_control_signals(2 downto 0) <= APL2_DATA_IN(2 downto 0);
-STAT_DAT2_api_control_signals(3) <= APL2_WRITE_IN;
-STAT_DAT2_api_control_signals(4) <= APL2_SEND_IN;
-STAT_DAT2_api_control_signals(7 downto 5) <= (others => '0');
-STAT_DAT2_api_control_signals(10 downto 8) <= apl_to_buf_DAT2_INIT_DATA(2 downto 0);
-STAT_DAT2_api_control_signals(11) <= apl_to_buf_DAT2_INIT_DATAREADY;
-STAT_DAT2_api_control_signals(12) <= apl_to_buf_DAT2_INIT_READ;
-STAT_DAT2_api_control_signals(31 downto 13) <= (others => '0');
-
-DAT1_IOBUF: trb_net16_iobuf
- generic map(
- INIT_DEPTH => DAT1_INIT_DEPTH,
- REPLY_DEPTH => DAT1_REPLY_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_DAT1_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_DAT1_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_DAT1_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_DAT1_INIT_READ_IN,
- MED_INIT_DATAREADY_IN => MED_DAT1_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_DAT1_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_DAT1_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_DAT1_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_DAT1_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_DAT1_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_DAT1_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_DAT1_REPLY_READ_IN,
- MED_REPLY_DATAREADY_IN => MED_DAT1_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_DAT1_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_DAT1_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_DAT1_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_DAT1_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_DAT1_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT1_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_DAT1_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_DAT1_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_DAT1_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT1_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_DAT1_INIT_READ,
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT1_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_DAT1_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT1_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_DAT1_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_DAT1_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_DAT1_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT1_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_DAT1_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_DAT1_GEN,
- STAT_LOCKED => STAT_DAT1_LOCKED,
- STAT_INIT_BUFFER => STAT_DAT1_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_DAT1_REPLY_BUFFER,
- CTRL_GEN => CTRL_DAT1_GEN,
- CTRL_LOCKED => CTRL_DAT1_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_DAT1_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_DAT1_CTRL_REPLY_BUFFER
- );
-
-DAT2_IOBUF: trb_net16_iobuf
- generic map(
- INIT_DEPTH => DAT2_INIT_DEPTH,
- REPLY_DEPTH => DAT2_REPLY_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_DAT2_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_DAT2_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_DAT2_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_DAT2_INIT_READ_IN,
- MED_INIT_DATAREADY_IN => MED_DAT2_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_DAT2_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_DAT2_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_DAT2_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_DAT2_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_DAT2_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_DAT2_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_DAT2_REPLY_READ_IN,
- MED_REPLY_DATAREADY_IN => MED_DAT2_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_DAT2_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_DAT2_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_DAT2_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_DAT2_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_DAT2_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT2_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_DAT2_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_DAT2_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_DAT2_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT2_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_DAT2_INIT_READ,
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT2_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_DAT2_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT2_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_DAT2_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_DAT2_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_DAT2_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT2_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_DAT2_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_DAT2_GEN,
- STAT_LOCKED => STAT_DAT2_LOCKED,
- STAT_INIT_BUFFER => STAT_DAT2_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_DAT2_REPLY_BUFFER,
- CTRL_GEN => CTRL_DAT2_GEN,
- CTRL_LOCKED => CTRL_DAT2_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_DAT2_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_DAT2_CTRL_REPLY_BUFFER
- );
-
- TRG1_IOBUF: trb_net16_iobuf
- generic map(
- INIT_DEPTH => TRG1_INIT_DEPTH,
- REPLY_DEPTH => TRG1_REPLY_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_TRG1_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_TRG1_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_TRG1_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_TRG1_INIT_READ_IN,
- MED_INIT_DATAREADY_IN => MED_TRG1_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_TRG1_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_TRG1_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_TRG1_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_TRG1_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_TRG1_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_TRG1_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_TRG1_REPLY_READ_IN,
- MED_REPLY_DATAREADY_IN => MED_TRG1_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_TRG1_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_TRG1_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_TRG1_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_TRG1_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_TRG1_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG1_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_TRG1_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_TRG1_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_TRG1_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG1_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_TRG1_INIT_READ,
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG1_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_TRG1_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG1_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_TRG1_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_TRG1_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_TRG1_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG1_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_TRG1_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_TRG1_GEN,
- STAT_LOCKED => STAT_TRG1_LOCKED,
- STAT_INIT_BUFFER => STAT_TRG1_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_TRG1_REPLY_BUFFER,
- CTRL_GEN => CTRL_TRG1_GEN,
- CTRL_LOCKED => CTRL_TRG1_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_TRG1_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_TRG1_CTRL_REPLY_BUFFER
- );
-
- TRG2_IOBUF: trb_net16_iobuf
- generic map(
- INIT_DEPTH => TRG2_INIT_DEPTH,
- REPLY_DEPTH => TRG2_REPLY_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_TRG2_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_TRG2_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_TRG2_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_TRG2_INIT_READ_IN,
- MED_INIT_DATAREADY_IN => MED_TRG2_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_TRG2_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_TRG2_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_TRG2_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_TRG2_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_TRG2_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_TRG2_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_TRG2_REPLY_READ_IN,
- MED_REPLY_DATAREADY_IN => MED_TRG2_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_TRG2_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_TRG2_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_TRG2_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_TRG2_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_TRG2_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG2_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_TRG2_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_TRG2_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_TRG2_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG2_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_TRG2_INIT_READ,
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG2_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_TRG2_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG2_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_TRG2_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_TRG2_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_TRG2_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG2_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_TRG2_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_TRG2_GEN,
- STAT_LOCKED => STAT_TRG2_LOCKED,
- STAT_INIT_BUFFER => STAT_TRG2_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_TRG2_REPLY_BUFFER,
- CTRL_GEN => CTRL_TRG2_GEN,
- CTRL_LOCKED => CTRL_TRG2_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_TRG2_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_TRG2_CTRL_REPLY_BUFFER
- );
-
- MPLEX: trb_net16_io_multiplexer
- generic map (
- DATA_WIDTH => DATA_WIDTH,
- NUM_WIDTH => NUM_WIDTH,
- MUX_WIDTH => MUX_WIDTH,
- MUX_SECURE_MODE => MUX_SECURE_MODE
- )
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
- INT_READ_IN =>m_READ_OUT,
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
- INT_READ_OUT =>m_READ_IN,
- CTRL => MPLEX_CTRL
- );
-
- TRG1_INIT : trb_net16_term
- generic map (
- FIFO_TERM_BUFFER_DEPTH => 0,
- SECURE_MODE => TRG1_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- INT_DATAREADY_OUT => apl_to_buf_TRG1_REPLY_DATAREADY,
- INT_DATA_OUT => apl_to_buf_TRG1_REPLY_DATA,
- INT_PACKET_NUM_OUT => apl_to_buf_TRG1_REPLY_PACKET_NUM,
- INT_READ_IN => apl_to_buf_TRG1_REPLY_READ,
- INT_DATAREADY_IN => buf_to_apl_TRG1_INIT_DATAREADY,
- INT_DATA_IN => buf_to_apl_TRG1_INIT_DATA,
- INT_PACKET_NUM_IN => buf_to_apl_TRG1_INIT_PACKET_NUM,
- INT_READ_OUT => buf_to_apl_TRG1_INIT_READ,
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => TRG1_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => TRG1_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => TRG1_SEQNR_OUT,
- APL_GOT_TRM => TRG1_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => TRG1_RELEASE_IN,
- APL_ERROR_PATTERN_IN => TRG1_ERROR_PATTERN_IN
- -- Status and control port
- );
-
- TRG2_INIT : trb_net16_term
- generic map (
- FIFO_TERM_BUFFER_DEPTH => 0,
- SECURE_MODE => TRG2_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- INT_DATAREADY_OUT => apl_to_buf_TRG2_REPLY_DATAREADY,
- INT_DATA_OUT => apl_to_buf_TRG2_REPLY_DATA,
- INT_PACKET_NUM_OUT => apl_to_buf_TRG2_REPLY_PACKET_NUM,
- INT_READ_IN => apl_to_buf_TRG2_REPLY_READ,
- INT_DATAREADY_IN => buf_to_apl_TRG2_INIT_DATAREADY,
- INT_DATA_IN => buf_to_apl_TRG2_INIT_DATA,
- INT_PACKET_NUM_IN => buf_to_apl_TRG2_INIT_PACKET_NUM,
- INT_READ_OUT => buf_to_apl_TRG2_INIT_READ,
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => TRG2_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => TRG2_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => TRG2_SEQNR_OUT,
- APL_GOT_TRM => TRG2_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => TRG2_RELEASE_IN,
- APL_ERROR_PATTERN_IN => TRG2_ERROR_PATTERN_IN
- -- Status and control port
- );
-
-apl_to_buf_TRG1_INIT_DATAREADY <= '0';
-apl_to_buf_TRG1_INIT_DATA <= (others => '0');
-apl_to_buf_TRG1_INIT_PACKET_NUM <= (others => '0');
-buf_to_apl_TRG1_REPLY_READ <= '1';
-
-apl_to_buf_TRG2_INIT_DATAREADY <= '0';
-apl_to_buf_TRG2_INIT_DATA <= (others => '0');
-apl_to_buf_TRG2_INIT_PACKET_NUM <= (others => '0');
-buf_to_apl_TRG2_REPLY_READ <= '1';
-end architecture;
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
---the first media interface is always the uplink & stream output!
-
-entity trb_net16_hub_streaming_port is
- generic(
- --hub control
- HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
- HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
- HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_YES;
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0');
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E";
- CLOCK_FREQUENCY : integer range 1 to 200 := 100;
- USE_ONEWIRE : integer range 0 to 2 := c_YES;
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
- --media interfaces
- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
- MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
- MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
- MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES);
- MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO)
- );
-
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- --Media Interface
- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
-
- --Event information coming from CTS
- CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
- CTS_CODE_OUT : out std_logic_vector (7 downto 0);
- CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
- CTS_START_READOUT_OUT : out std_logic;
-
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_IN : in std_logic_vector (31 downto 0);
- CTS_DATAREADY_IN : in std_logic;
- CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
- CTS_READ_OUT : out std_logic;
- CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
- CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
-
- -- Data from Frontends
- FEE_DATA_OUT : out std_logic_vector (15 downto 0);
- FEE_DATAREADY_OUT : out std_logic;
- FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
- FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
- FEE_BUSY_OUT : out std_logic;
-
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
-
- COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
- COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
- ONEWIRE : inout std_logic;
- ONEWIRE_MONITOR_IN : in std_logic;
- ONEWIRE_MONITOR_OUT : out std_logic;
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- TIMER_TICKS_OUT : out std_logic_vector(1 downto 0);
-
- --REGIO INTERFACE
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- REGIO_READ_ENABLE_OUT : out std_logic;
- REGIO_WRITE_ENABLE_OUT : out std_logic;
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- REGIO_DATAREADY_IN : in std_logic := '0';
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';
- REGIO_WRITE_ACK_IN : in std_logic := '0';
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
- REGIO_TIMEOUT_OUT : out std_logic;
-
-
- --status and control ports
- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
- HUB_STAT_GEN : out std_logic_vector (31 downto 0);
- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
- STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
- --Debugging registers
- STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
- CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
- );
-end entity;
-
-
-architecture trb_net16_hub_streaming_arch of trb_net16_hub_streaming_port is
-
-constant mii : integer := MII_NUMBER-1;
-
-signal hub_init_dataready_out : std_logic_vector(3 downto 0);
-signal hub_reply_dataready_out : std_logic_vector(3 downto 0);
-signal hub_init_dataready_in : std_logic_vector(3 downto 0);
-signal hub_reply_dataready_in : std_logic_vector(3 downto 0);
-
-signal hub_init_read_out : std_logic_vector(3 downto 0);
-signal hub_reply_read_out : std_logic_vector(3 downto 0);
-signal hub_init_read_in : std_logic_vector(3 downto 0);
-signal hub_reply_read_in : std_logic_vector(3 downto 0);
-
-signal hub_init_data_out : std_logic_vector(48 downto 0);
-signal hub_reply_data_out : std_logic_vector(48 downto 0);
-signal hub_init_data_in : std_logic_vector(48 downto 0);
-signal hub_reply_data_in : std_logic_vector(48 downto 0);
-
-signal hub_init_packet_num_out : std_logic_vector(9 downto 0);
-signal hub_reply_packet_num_out : std_logic_vector(9 downto 0);
-signal hub_init_packet_num_in : std_logic_vector(9 downto 0);
-signal hub_reply_packet_num_in : std_logic_vector(9 downto 0);
-
-signal cts_init_data_out : std_logic_vector(15 downto 0);
-signal cts_init_dataready_out : std_logic;
-signal cts_init_packet_num_out : std_logic_vector(2 downto 0);
-signal cts_init_read_in : std_logic;
-
-signal cts_reply_data_in : std_logic_vector(15 downto 0);
-signal cts_reply_dataready_in : std_logic;
-signal cts_reply_packet_num_in : std_logic_vector(2 downto 0);
-signal cts_reply_read_out : std_logic;
-
-signal common_ctrl : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-signal common_stat : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-signal my_address : std_logic_vector(15 downto 0);
-
-signal io_dataready_out : std_logic_vector(7 downto 0);
-signal io_data_out : std_logic_vector(127 downto 0);
-signal io_packet_num_out : std_logic_vector(23 downto 0);
-signal io_read_in : std_logic_vector(7 downto 0);
-
-signal io_dataready_in : std_logic_vector(3 downto 0);
-signal io_read_out : std_logic_vector(3 downto 0);
-signal io_data_in : std_logic_vector(4*16-1 downto 0);
-signal io_packet_num_in : std_logic_vector(4*3-1 downto 0);
-signal io_error_in : std_logic_vector(2 downto 0);
-
-signal reset_i : std_logic;
-
-signal HUB_MED_CTRL_OP : std_logic_vector(mii*16-1 downto 0);
-signal reset_i_mux_io : std_logic;
-
-signal hub_make_network_reset : std_logic;
-signal hub_got_network_reset : std_logic;
-signal timer_ticks : std_logic_vector(1 downto 0);
-signal hub_ctrl_debug : std_logic_vector(31 downto 0);
-
-begin
-
----------------------------------------------------------------------
--- Reset
----------------------------------------------------------------------
---13: reset sequence received
---14: not connected
---15: send reset sequence
-
- SYNC_RESET_MUX_IO : process(CLK)
- begin
- if rising_edge(CLK) then
- reset_i <= RESET;
- reset_i_mux_io <= MED_STAT_OP(mii*16+14) or reset_i;
- end if;
- end process;
-
-
---generate media resync
- gen_resync : for i in 0 to mii-1 generate
- MED_CTRL_OP(13+i*16 downto i*16) <= (others => '0');
- MED_CTRL_OP(14+i*16) <= HUB_MED_CTRL_OP(14+i*16);
- MED_CTRL_OP(15+i*16) <= hub_make_network_reset ;
- end generate;
- MED_CTRL_OP(13+mii*16 downto mii*16) <= (others => '0');
- MED_CTRL_OP(14+mii*16) <= '0';
- MED_CTRL_OP(15+mii*16) <= hub_make_network_reset;
-
-
- hub_make_network_reset <= MED_STAT_OP(15) or MED_STAT_OP(15+mii*16);
-
----------------------------------------------------------------------
--- Connecting I/O
----------------------------------------------------------------------
-
- COMMON_CTRL_REGS <= common_ctrl;
- COMMON_STAT_REGS <= common_stat;
- MY_ADDRESS_OUT <= my_address;
-
-
----------------------------------------------------------------------
--- The Hub
----------------------------------------------------------------------
-
-
- THE_HUB : trb_net16_hub_base
- generic map (
- --hub control
- HUB_CTRL_CHANNELNUM => HUB_CTRL_CHANNELNUM,
- HUB_CTRL_DEPTH => HUB_CTRL_DEPTH,
- HUB_USED_CHANNELS => HUB_USED_CHANNELS,
- USE_CHECKSUM => USE_CHECKSUM,
- USE_VENDOR_CORES => USE_VENDOR_CORES,
- IBUF_SECURE_MODE => IBUF_SECURE_MODE,
- INIT_ADDRESS => INIT_ADDRESS,
- INIT_UNIQUE_ID => INIT_UNIQUE_ID,
- COMPILE_TIME => COMPILE_TIME,
- INCLUDED_FEATURES => INCLUDED_FEATURES,
- HARDWARE_VERSION => HARDWARE_VERSION,
- HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- USE_ONEWIRE => USE_ONEWIRE,
- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
- MII_NUMBER => mii,
- MII_IBUF_DEPTH => MII_IBUF_DEPTH,
- MII_IS_UPLINK => MII_IS_UPLINK,
- MII_IS_DOWNLINK => MII_IS_DOWNLINK,
- MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY,
- INIT_ENDPOINT_ID => INIT_ENDPOINT_ID,
- INT_NUMBER => 3,
- INT_CHANNELS => (0=>0,1=>1,2=>3,others=>0)
- )
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- --Media interfacces
- MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0),
- MED_DATA_OUT => med_data_out(mii*16-1 downto 0),
- MED_PACKET_NUM_OUT=> med_packet_num_out(mii*3-1 downto 0),
- MED_READ_IN => med_read_in(mii-1 downto 0),
- MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0),
- MED_DATA_IN => med_data_in(mii*16-1 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0),
- MED_READ_OUT => med_read_out(mii-1 downto 0),
- MED_STAT_OP => med_stat_op(mii*16-1 downto 0),
- MED_CTRL_OP => HUB_MED_CTRL_OP(mii*16-1 downto 0),
-
- INT_INIT_DATAREADY_OUT => hub_init_dataready_out,
- INT_INIT_DATA_OUT => hub_init_data_out,
- INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_out,
- INT_INIT_READ_IN => hub_init_read_in,
- INT_INIT_DATAREADY_IN => hub_init_dataready_in,
- INT_INIT_DATA_IN => hub_init_data_in,
- INT_INIT_PACKET_NUM_IN => hub_init_packet_num_in,
- INT_INIT_READ_OUT => hub_init_read_out,
- INT_REPLY_DATAREADY_OUT => hub_reply_dataready_out,
- INT_REPLY_DATA_OUT => hub_reply_data_out,
- INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_out,
- INT_REPLY_READ_IN => hub_reply_read_in,
- INT_REPLY_DATAREADY_IN => hub_reply_dataready_in,
- INT_REPLY_DATA_IN => hub_reply_data_in,
- INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_in,
- INT_REPLY_READ_OUT => hub_reply_read_out,
- --REGIO INTERFACE
- REGIO_ADDR_OUT => REGIO_ADDR_OUT,
- REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
- REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
- REGIO_DATA_OUT => REGIO_DATA_OUT,
- REGIO_DATA_IN => REGIO_DATA_IN,
- REGIO_DATAREADY_IN => REGIO_DATAREADY_IN,
- REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,
- REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
- REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
- REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
- TIMER_TICKS_OUT => timer_ticks,
- ONEWIRE => ONEWIRE,
- ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
- ONEWIRE_MONITOR_OUT=> ONEWIRE_MONITOR_OUT,
- MY_ADDRESS_OUT => my_address,
- COMMON_CTRL_REGS => common_ctrl,
- COMMON_STAT_REGS => common_stat,
- MPLEX_CTRL => (others => '0'),
- CTRL_DEBUG => hub_ctrl_debug,
- STAT_DEBUG => STAT_DEBUG
- );
-
- hub_ctrl_debug(2 downto 0) <= not io_error_in;
- hub_ctrl_debug(31 downto 3) <= (others => '0');
- TIMER_TICKS_OUT <= timer_ticks;
----------------------------------------------------------------------
--- I/O Buffers
----------------------------------------------------------------------
-
- THE_IOBUF_0 : trb_net16_iobuf
- generic map(
- IBUF_DEPTH => 6,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(0),
- USE_CHECKSUM => cfg_USE_CHECKSUM(0),
- INIT_CAN_SEND_DATA => c_YES,
- INIT_CAN_RECEIVE_DATA => c_YES,
- REPLY_CAN_SEND_DATA => c_YES,
- REPLY_CAN_RECEIVE_DATA => c_YES
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => io_dataready_out(0),
- MED_INIT_DATA_OUT => io_data_out(15 downto 0),
- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(2 downto 0),
- MED_INIT_READ_IN => io_read_in(0),
-
- MED_REPLY_DATAREADY_OUT => io_dataready_out(1),
- MED_REPLY_DATA_OUT => io_data_out(31 downto 16),
- MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(5 downto 3),
- MED_REPLY_READ_IN => io_read_in(1),
-
- MED_DATAREADY_IN => io_dataready_in(0),
- MED_DATA_IN => io_data_in(15 downto 0),
- MED_PACKET_NUM_IN => io_packet_num_in(2 downto 0),
- MED_READ_OUT => io_read_out(0),
- MED_ERROR_IN => io_error_in,
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => hub_init_dataready_in(0),
- INT_INIT_DATA_OUT => hub_init_data_in(15 downto 0),
- INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(2 downto 0),
- INT_INIT_READ_IN => hub_init_read_out(0),
-
- INT_INIT_DATAREADY_IN => hub_init_dataready_out(0),
- INT_INIT_DATA_IN => hub_init_data_out(15 downto 0),
- INT_INIT_PACKET_NUM_IN => hub_init_packet_num_out(2 downto 0),
- INT_INIT_READ_OUT => hub_init_read_in(0),
-
- INT_REPLY_DATAREADY_OUT => hub_reply_dataready_in(0),
- INT_REPLY_DATA_OUT => hub_reply_data_in(15 downto 0),
- INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_in(2 downto 0),
- INT_REPLY_READ_IN => hub_reply_read_out(0),
-
- INT_REPLY_DATAREADY_IN => hub_reply_dataready_out(0),
- INT_REPLY_DATA_IN => hub_reply_data_out(15 downto 0),
- INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(2 downto 0),
- INT_REPLY_READ_OUT => hub_reply_read_in(0),
-
- -- Status and control port
- STAT_GEN => open,
- STAT_IBUF_BUFFER => open,
- CTRL_GEN => (others => '0'),
- STAT_INIT_OBUF_DEBUG => open,
- STAT_REPLY_OBUF_DEBUG => open,
- TIMER_TICKS_IN => timer_ticks
- );
-
-
- THE_IOBUF_1 : trb_net16_iobuf
- generic map(
- IBUF_DEPTH => 6,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(1),
- USE_CHECKSUM => cfg_USE_CHECKSUM(1),
- INIT_CAN_SEND_DATA => c_YES,
- INIT_CAN_RECEIVE_DATA => c_YES,
- REPLY_CAN_SEND_DATA => c_YES,
- REPLY_CAN_RECEIVE_DATA => c_YES
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => io_dataready_out(2),
- MED_INIT_DATA_OUT => io_data_out(47 downto 32),
- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6),
- MED_INIT_READ_IN => io_read_in(2),
-
- MED_REPLY_DATAREADY_OUT => io_dataready_out(3),
- MED_REPLY_DATA_OUT => io_data_out(63 downto 48),
- MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(11 downto 9),
- MED_REPLY_READ_IN => io_read_in(3),
-
- MED_DATAREADY_IN => io_dataready_in(1),
- MED_DATA_IN => io_data_in(31 downto 16),
- MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3),
- MED_READ_OUT => io_read_out(1),
- MED_ERROR_IN => io_error_in,
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => cts_init_dataready_out,
- INT_INIT_DATA_OUT => cts_init_data_out,
- INT_INIT_PACKET_NUM_OUT => cts_init_packet_num_out,
- INT_INIT_READ_IN => cts_init_read_in,
-
- INT_INIT_DATAREADY_IN => '0',
- INT_INIT_DATA_IN => (others => '0'),
- INT_INIT_PACKET_NUM_IN => (others => '0'),
- INT_INIT_READ_OUT => open,
-
- INT_REPLY_DATAREADY_OUT => open,
- INT_REPLY_DATA_OUT => open,
- INT_REPLY_PACKET_NUM_OUT => open,
- INT_REPLY_READ_IN => '1',
-
- INT_REPLY_DATAREADY_IN => cts_reply_dataready_in,
- INT_REPLY_DATA_IN => cts_reply_data_in,
- INT_REPLY_PACKET_NUM_IN => cts_reply_packet_num_in,
- INT_REPLY_READ_OUT => cts_reply_read_out,
-
- -- Status and control port
- STAT_GEN => open,
- STAT_IBUF_BUFFER => open,
- CTRL_GEN => (others => '0'),
- STAT_INIT_OBUF_DEBUG => open,
- STAT_REPLY_OBUF_DEBUG => open,
- TIMER_TICKS_IN => timer_ticks
- );
-
- THE_IOBUF_2 : trb_net16_term_buf
- port map (
- -- Misc
- CLK => CLK ,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => io_dataready_out(4),
- MED_INIT_DATA_OUT => io_data_out(79 downto 64),
- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(14 downto 12),
- MED_INIT_READ_IN => io_read_in(4),
- MED_REPLY_DATAREADY_OUT => io_dataready_out(5),
- MED_REPLY_DATA_OUT => io_data_out(95 downto 80),
- MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(17 downto 15),
- MED_REPLY_READ_IN => io_read_in(5),
- MED_DATAREADY_IN => io_dataready_in(2),
- MED_DATA_IN => io_data_in(47 downto 32),
- MED_PACKET_NUM_IN => io_packet_num_in(8 downto 6),
- MED_READ_OUT => io_read_out(2)
- );
-
- THE_IOBUF_3 : trb_net16_iobuf
- generic map(
- IBUF_DEPTH => 6,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(3),
- USE_CHECKSUM => cfg_USE_CHECKSUM(3),
- INIT_CAN_SEND_DATA => c_YES,
- INIT_CAN_RECEIVE_DATA => c_YES,
- REPLY_CAN_SEND_DATA => c_YES,
- REPLY_CAN_RECEIVE_DATA => c_YES
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => io_dataready_out(6),
- MED_INIT_DATA_OUT => io_data_out(111 downto 96),
- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(20 downto 18),
- MED_INIT_READ_IN => io_read_in(6),
-
- MED_REPLY_DATAREADY_OUT => io_dataready_out(7),
- MED_REPLY_DATA_OUT => io_data_out(127 downto 112),
- MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(23 downto 21),
- MED_REPLY_READ_IN => io_read_in(7),
-
- MED_DATAREADY_IN => io_dataready_in(3),
- MED_DATA_IN => io_data_in(63 downto 48),
- MED_PACKET_NUM_IN => io_packet_num_in(11 downto 9),
- MED_READ_OUT => io_read_out(3),
- MED_ERROR_IN => io_error_in,
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => hub_init_dataready_in(2),
- INT_INIT_DATA_OUT => hub_init_data_in(47 downto 32),
- INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(8 downto 6),
- INT_INIT_READ_IN => hub_init_read_out(2),
-
- INT_INIT_DATAREADY_IN => hub_init_dataready_out(2),
- INT_INIT_DATA_IN => hub_init_data_out(47 downto 32),
- INT_INIT_PACKET_NUM_IN => hub_init_packet_num_out(8 downto 6),
- INT_INIT_READ_OUT => hub_init_read_in(2),
-
- INT_REPLY_DATAREADY_OUT => hub_reply_dataready_in(2),
- INT_REPLY_DATA_OUT => hub_reply_data_in(47 downto 32),
- INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_in(8 downto 6),
- INT_REPLY_READ_IN => hub_reply_read_out(2),
-
- INT_REPLY_DATAREADY_IN => hub_reply_dataready_out(2),
- INT_REPLY_DATA_IN => hub_reply_data_out(47 downto 32),
- INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(8 downto 6),
- INT_REPLY_READ_OUT => hub_reply_read_in(2),
-
- -- Status and control port
- STAT_GEN => open,
- STAT_IBUF_BUFFER => open,
- CTRL_GEN => (others => '0'),
- STAT_INIT_OBUF_DEBUG => open,
- STAT_REPLY_OBUF_DEBUG => open,
- TIMER_TICKS_IN => timer_ticks
- );
-
----------------------------------------------------------------------
--- Multiplexer
----------------------------------------------------------------------
- MPLEX: trb_net16_io_multiplexer
- port map (
- CLK => CLK,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN(mii),
- MED_DATA_IN => MED_DATA_IN(mii*16+15 downto mii*16),
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN(mii*3+2 downto mii*3),
- MED_READ_OUT => MED_READ_OUT(mii),
- MED_DATAREADY_OUT => MED_DATAREADY_OUT(mii),
- MED_DATA_OUT => MED_DATA_OUT(mii*16+15 downto mii*16),
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(mii*3+2 downto mii*3),
- MED_READ_IN => MED_READ_IN(mii),
- INT_DATAREADY_OUT => io_dataready_in,
- INT_DATA_OUT => io_data_in,
- INT_PACKET_NUM_OUT => io_packet_num_in,
- INT_READ_IN => io_read_out,
- INT_DATAREADY_IN => io_dataready_out,
- INT_DATA_IN => io_data_out,
- INT_PACKET_NUM_IN => io_packet_num_out,
- INT_READ_OUT => io_read_in,
- CTRL => (others => '0'),
- STAT => open
- );
- io_error_in <= MED_STAT_OP(mii*16+2 downto mii*16+0);
-
----------------------------------------------------------------------
--- IPU Channel
----------------------------------------------------------------------
-
- hub_reply_data_in(31 downto 16) <= (others => '0');
- hub_reply_packet_num_in(5 downto 3) <= (others => '0');
- hub_reply_dataready_in(1) <= '0';
- hub_init_read_in(1) <= '1';
-
- THE_STREAMING : trb_net16_api_ipu_streaming
- port map(
- CLK => CLK,
- RESET => reset_i,
- CLK_EN => CLK_EN,
-
- -- Internal direction port
-
- FEE_INIT_DATA_OUT => hub_init_data_in(31 downto 16),
- FEE_INIT_DATAREADY_OUT => hub_init_dataready_in(1),
- FEE_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(5 downto 3),
- FEE_INIT_READ_IN => hub_init_read_out(1),
-
- FEE_REPLY_DATA_IN => hub_reply_data_out(31 downto 16),
- FEE_REPLY_DATAREADY_IN => hub_reply_dataready_out(1),
- FEE_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(5 downto 3),
- FEE_REPLY_READ_OUT => hub_reply_read_in(1),
-
- CTS_INIT_DATA_IN => cts_init_data_out,
- CTS_INIT_DATAREADY_IN => cts_init_dataready_out,
- CTS_INIT_PACKET_NUM_IN => cts_init_packet_num_out,
- CTS_INIT_READ_OUT => cts_init_read_in,
-
- CTS_REPLY_DATA_OUT => cts_reply_data_in,
- CTS_REPLY_DATAREADY_OUT => cts_reply_dataready_in,
- CTS_REPLY_PACKET_NUM_OUT => cts_reply_packet_num_in,
- CTS_REPLY_READ_IN => cts_reply_read_out,
-
- --Event information coming from CTS
- CTS_NUMBER_OUT => CTS_NUMBER_OUT,
- CTS_CODE_OUT => CTS_CODE_OUT,
- CTS_INFORMATION_OUT => CTS_INFORMATION_OUT,
- CTS_READOUT_TYPE_OUT => CTS_READOUT_TYPE_OUT,
- CTS_START_READOUT_OUT => CTS_START_READOUT_OUT,
-
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_IN => CTS_DATA_IN,
- CTS_DATAREADY_IN => CTS_DATAREADY_IN,
- CTS_READOUT_FINISHED_IN => CTS_READOUT_FINISHED_IN,
- CTS_READ_OUT => CTS_READ_OUT,
- CTS_LENGTH_IN => CTS_LENGTH_IN,
- CTS_STATUS_BITS_IN => CTS_STATUS_BITS_IN,
-
- -- Data from Frontends
- FEE_DATA_OUT => FEE_DATA_OUT,
- FEE_DATAREADY_OUT => FEE_DATAREADY_OUT,
- FEE_READ_IN => FEE_READ_IN,
- FEE_STATUS_BITS_OUT => FEE_STATUS_BITS_OUT,
- FEE_BUSY_OUT => FEE_BUSY_OUT,
-
- MY_ADDRESS_IN => MY_ADDRESS_IN,
- CTRL_SEQNR_RESET => common_ctrl(10)
-
- );
-
--- STAT_DEBUG(0) <= cts_reply_dataready_in;
--- STAT_DEBUG(1) <= cts_reply_read_out;
--- STAT_DEBUG(2) <= cts_init_dataready_out;
--- STAT_DEBUG(3) <= cts_reply_read_out;
--- STAT_DEBUG(4) <= io_dataready_out(2);
--- STAT_DEBUG(5) <= io_dataready_out(3);
--- STAT_DEBUG(6) <= '0';
--- STAT_DEBUG(7) <= '0';
-
-
-end architecture;
\ No newline at end of file
+++ /dev/null
--- A 16bit data interface between two devices using a common clock, 32 data lines and 4 control lines
-
-
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net16_med_16_CC is
- port(
- CLK : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
-
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
-
- DATA_OUT : out std_logic_vector(15 downto 0);
- DATA_VALID_OUT : out std_logic;
- DATA_CTRL_OUT : out std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_VALID_IN : in std_logic;
- DATA_CTRL_IN : in std_logic;
-
- STAT_OP : out std_logic_vector(15 downto 0);
- CTRL_OP : in std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(63 downto 0)
- );
- attribute syn_useioff : boolean;
- attribute syn_useioff of DATA_OUT : signal is true;
- attribute syn_useioff of DATA_VALID_OUT : signal is true;
- attribute syn_useioff of DATA_CTRL_OUT : signal is true;
- attribute syn_useioff of DATA_IN : signal is true;
- attribute syn_useioff of DATA_VALID_IN : signal is true;
- attribute syn_useioff of DATA_CTRL_IN : signal is true;
-
-end entity;
-
-architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is
-
- component signal_sync is
- generic(
- WIDTH : integer := 18;
- DEPTH : integer := 3
- );
- port(
- RESET : in std_logic;
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- D_IN : in std_logic_vector(WIDTH-1 downto 0);
- D_OUT : out std_logic_vector(WIDTH-1 downto 0)
- );
- end component;
-
- signal buf_DATA_IN : std_logic_vector(15 downto 0);
- signal buf_DATA_VALID_IN : std_logic;
- signal buf_DATA_CTRL_IN : std_logic;
-
- signal reg_DATA_IN : std_logic_vector(15 downto 0);
- signal reg_DATA_VALID_IN : std_logic;
- signal reg_DATA_CTRL_IN : std_logic;
-
- signal last_DATA_CTRL_IN : std_logic;
- signal link_running : std_logic;
-
- signal buf_DATA_VALID_OUT : std_logic;
- signal buf_DATA_CTRL_OUT : std_logic;
- signal buf_DATA_OUT : std_logic_vector(15 downto 0);
- signal PRESENT_SIG : std_logic;
- signal led_counter : unsigned(18 downto 0);
-
- signal link_led : std_logic;
- signal tx_led : std_logic;
- signal rx_led : std_logic;
- --signal resync : std_logic;
- --signal resync_counter : unsigned(4 downto 0);
-
- signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal buf_MED_READ_OUT : std_logic;
- signal buf_MED_DATAREADY_OUT : std_logic;
- signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal buf_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0);
-
- signal not_connected : std_logic;
- signal resync_received: std_logic;
- type link_state_t is (STARTUP, WAITING, WORKING, RESYNCING, RESYNC_WAIT);
- signal link_state : link_state_t;
- signal med_error : std_logic_vector(2 downto 0);
- signal pattern_counter : unsigned(11 downto 0);
- signal pattern_detected : std_logic;
- signal state_bits : std_logic_vector(2 downto 0);
- signal make_reset : std_logic;
-
-
-begin
-
------------------------
---Receiver
------------------------
-
- PROC_RX_INPUT : process(CLK)
- begin
- if rising_edge(CLK) then
- buf_DATA_IN <= DATA_IN;
- buf_DATA_VALID_IN <= DATA_VALID_IN;
- buf_DATA_CTRL_IN <= DATA_CTRL_IN;
- end if;
- end process;
-
- THE_RX_SIGNAL_SYNC: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 18
- )
- port map(
- RESET => RESET,
- D_IN(15 downto 0) => buf_DATA_IN,
- D_IN(16) => buf_DATA_VALID_IN,
- D_IN(17) => buf_DATA_CTRL_IN,
- CLK0 => CLK,
- CLK1 => CLK,
- D_OUT(15 downto 0) => reg_DATA_IN,
- D_OUT(16) => reg_DATA_VALID_IN,
- D_OUT(17) => reg_DATA_CTRL_IN
- );
-
-
- PROC_RX_COUNTER : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- rx_counter <= c_H0;
- elsif buf_MED_DATAREADY_OUT = '1' and CLK_EN = '1' then
- if rx_counter = c_max_word_number then
- rx_counter <= (others => '0');
- else
- rx_counter <= rx_counter + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- buf_MED_PACKET_NUM_OUT <= rx_counter;
- buf_MED_DATAREADY_OUT <= reg_DATA_VALID_IN and link_running;
- buf_MED_DATA_OUT <= reg_DATA_IN;
- buf_MED_READ_OUT <= link_running;
- MED_READ_OUT <= buf_MED_READ_OUT;
-
- PROC_REG_MED_OUT : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- MED_DATA_OUT <= buf_MED_DATA_OUT;
- MED_DATAREADY_OUT <= '0';
- MED_PACKET_NUM_OUT<= buf_MED_PACKET_NUM_OUT;
- else
- MED_DATA_OUT <= buf_MED_DATA_OUT;
- MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT;
- MED_PACKET_NUM_OUT<= buf_MED_PACKET_NUM_OUT;
- end if;
- end if;
- end process;
-
-
------------------------
---Link detection & Status & Control signals
------------------------
-
- STAT_OP(2 downto 0) <= med_error;
- STAT_OP(8 downto 3) <= (others => '0');
- STAT_OP(9) <= link_led;
- STAT_OP(10) <= rx_led;
- STAT_OP(11) <= tx_led;
- STAT_OP(12) <= '0';
- STAT_OP(13) <= make_reset;
- STAT_OP(14) <= not_connected;
- STAT_OP(15) <= resync_received;
-
-
- PROC_LED : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' or not_connected = '1' then
- led_counter <= (others => '0');
- rx_led <= '0';
- tx_led <= '0';
- link_led <= '0';
- else
- led_counter <= led_counter + 1;
- link_led <= link_running;
- if led_counter(18) = '1' then
- led_counter <= (others => '0');
- rx_led <= '0';
- tx_led <= '0';
- end if;
- if buf_MED_DATAREADY_OUT = '1' then
- rx_led <= '1';
- end if;
- if MED_DATAREADY_IN = '1' and buf_MED_READ_OUT = '1' then
- tx_led <= '1';
- end if;
- end if;
- end if;
- end process;
-
-
- PROC_SIGNAL_DETECT_PREPARE : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- last_DATA_CTRL_IN <= '0';
- pattern_detected <= '0';
- elsif reg_DATA_VALID_IN = '0' then
- last_DATA_CTRL_IN <= reg_DATA_CTRL_IN;
- pattern_detected <= last_DATA_CTRL_IN xor reg_DATA_CTRL_IN;
- end if;
- end if;
- end process;
-
- PROC_FSM : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- link_state <= STARTUP;
- link_running <= '0';
- resync_received <= '0';
- not_connected <= '1';
- make_reset <= '0';
- else
- case link_state is
- when STARTUP =>
- med_error <= ERROR_NC;
- link_running <= '0';
- not_connected <= '1';
- resync_received <= '0';
- if pattern_detected = '1' then
- not_connected <= '0';
- link_state <= WAITING;
- pattern_counter <= x"040";
- end if;
-
- when WAITING =>
- med_error <= ERROR_WAIT;
- if pattern_detected = '1' and reg_DATA_VALID_IN = '0' then
- pattern_counter <= pattern_counter + "1";
- elsif pattern_detected = '0' then
- pattern_counter <= pattern_counter - x"40";
- end if;
- if pattern_counter < x"040" then
- link_state <= STARTUP;
- elsif pattern_counter = x"FFF" then
- link_state <= WORKING;
- end if;
-
- when WORKING =>
- med_error <= ERROR_OK;
- link_running <= '1';
--- if CTRL_OP(15) = '1' then
--- link_state <= RESYNCING;
--- resync_counter <= (others => '0');
--- link_running <= '0';
--- end if;
--- if (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '1' and rx_counter /= c_H0)
--- or (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '0' and rx_counter = c_H0) then
--- resync_needed <= '1';
--- else
--- resync_needed <= '0';
--- end if;
- if reg_DATA_VALID_IN = '0' and reg_DATA_IN = x"FEFE" then
- resync_received <= '1';
- else
- resync_received <= '0';
- make_reset <= resync_received;
- end if;
-
- if pattern_detected = '0' then
- link_running <= '0';
- link_state <= STARTUP;
- end if;
-
--- when RESYNCING =>
--- med_error <= ERROR_WAIT;
--- resync <= '1';
--- if CTRL_OP(15) = '0' then
--- resync <= '0';
--- link_state <= RESYNC_WAIT;
--- end if;
-
- when RESYNC_WAIT =>
- med_error <= ERROR_WAIT;
- if reg_DATA_VALID_IN = '0' and reg_DATA_IN = x"AAAA" then
- link_state <= WAITING;
- pattern_counter <= x"040";
- elsif pattern_detected = '0' then
- link_state <= STARTUP;
- end if;
-
- when others =>
- link_state <= STARTUP;
- end case;
- end if;
- end if;
- end process;
-
- state_bits <= "000" when link_state = STARTUP else
- "001" when link_state = WAITING else
- "010" when link_state = RESYNCING else
- "011" when link_state = RESYNC_WAIT else
- "100" when link_state = WORKING else "111";
-
-
------------------------
---Sender
------------------------
-
-
---Generate tx signals
- PROC_SEND_DATA : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- buf_DATA_VALID_OUT <= '0';
- buf_DATA_CTRL_OUT <= '0';
- buf_DATA_OUT <= (others => '0');
- PRESENT_SIG <= '0';
- elsif CTRL_OP(15) = '1' then
- buf_DATA_VALID_OUT <= '0';
- buf_DATA_CTRL_OUT <= not buf_DATA_CTRL_OUT;
- buf_DATA_OUT <= x"FEFE";
- elsif MED_DATAREADY_IN = '1' and buf_MED_READ_OUT = '1' then
- buf_DATA_VALID_OUT <= '1';
- buf_DATA_OUT <= MED_DATA_IN;
- if MED_PACKET_NUM_IN = c_H0 then
- buf_DATA_CTRL_OUT <= '1';
- else
- buf_DATA_CTRL_OUT <= '0';
- end if;
- else
- buf_DATA_OUT <= x"AAAA";
- buf_DATA_CTRL_OUT <= PRESENT_SIG;
- buf_DATA_VALID_OUT <= '0';
- PRESENT_SIG <= not PRESENT_SIG;
- end if;
- end if;
- end process;
-
---Generate O-FF
- PROC_OUTPUT : process(CLK)
- begin
- if rising_edge(CLK) then
- DATA_VALID_OUT <= buf_DATA_VALID_OUT;
- DATA_CTRL_OUT <= buf_DATA_CTRL_OUT;
- DATA_OUT <= buf_DATA_OUT;
- end if;
- end process;
-
-
-
------------------------
---Debug
------------------------
-
-STAT_DEBUG(15 downto 0) <= reg_DATA_IN;
-STAT_DEBUG(16) <= reg_DATA_VALID_IN;
-STAT_DEBUG(17) <= reg_DATA_CTRL_IN;
-STAT_DEBUG(18) <= resync_received;
-STAT_DEBUG(22 downto 19)<= std_logic_vector(pattern_counter(3 downto 0));
-STAT_DEBUG(23) <= '0';
-STAT_DEBUG(26 downto 24)<= state_bits;
-
-STAT_DEBUG(63 downto 27) <= (others => '0');
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-entity trb_net16_med_16_IC is
- generic(
- DATA_CLK_OUT_PHASE : std_logic := '1'
- );
- port(
- CLK : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
-
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
-
- DATA_OUT : out std_logic_vector(15 downto 0);
- DATA_VALID_OUT : out std_logic;
- DATA_CTRL_OUT : out std_logic;
- DATA_CLK_OUT : out std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_VALID_IN : in std_logic;
- DATA_CTRL_IN : in std_logic;
- DATA_CLK_IN : in std_logic;
-
- STAT_OP : out std_logic_vector(15 downto 0);
- CTRL_OP : in std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(63 downto 0)
- );
-end entity;
-
-
-
-architecture trb_net16_med_16_IC_arch of trb_net16_med_16_IC is
- signal buf_DATA_IN : std_logic_vector(15 downto 0);
- signal buf_DATA_VALID_IN : std_logic;
- signal buf_DATA_CTRL_IN : std_logic;
- signal reg_DATA_IN : std_logic_vector(15 downto 0);
- signal reg_DATA_VALID_IN : std_logic;
- signal reg_DATA_CTRL_IN : std_logic;
-
- signal rx_allow_qrx : std_logic;
- signal rx_fifo_read : std_logic;
- signal rx_fifo_write : std_logic;
- signal rx_fifo_reset : std_logic;
- signal rx_fifo_full : std_logic;
- signal rx_fifo_empty : std_logic;
- signal rx_fifo_valid_read : std_logic;
- signal rx_fifo_dout : std_logic_vector(17 downto 0);
-
- signal rx_allow : std_logic;
- signal tx_allow : std_logic;
-
- signal rx_counter : unsigned(2 downto 0);
-
- signal buf_MED_DATAREADY_OUT : std_logic;
- signal buf_MED_DATA_OUT : std_logic_vector(15 downto 0);
- signal buf_MED_READ_OUT : std_logic;
-
- signal buf_DATA_VALID_OUT : std_logic;
- signal buf_DATA_CTRL_OUT : std_logic;
- signal buf_DATA_OUT : std_logic_vector(15 downto 0);
-
- signal reg0_DATA_VALID_IN : std_logic;
- signal reg0_DATA_CTRL_IN : std_logic;
- signal reg0_DATA_IN : std_logic_vector(15 downto 0);
-
- signal med_error : std_logic_vector(2 downto 0);
- signal link_led : std_logic;
- signal link_running : std_logic;
- signal tx_led : std_logic;
- signal rx_led : std_logic;
- signal make_reset : std_logic;
- signal not_connected : std_logic;
- signal resync_received : std_logic;
- signal led_counter : unsigned(18 downto 0);
-
- signal state_bits : std_logic_vector(2 downto 0);
- type link_state_t is (STARTUP, WAITING, WORKING, RESYNC_WAIT);
- signal link_state : link_state_t;
- signal pattern_detected_q : std_logic;
-
- signal pattern_counter : unsigned(11 downto 0);
- signal pattern_detected : std_logic;
- signal last_DATA_CTRL_IN : std_logic;
- signal present_sig : std_logic;
-
-
- signal rx_idle_pattern : std_logic;
- signal rx_idle_pattern_q : std_logic;
- signal rx_resync_pattern : std_logic;
- signal rx_resync_pattern_q : std_logic;
- signal pattern_valid : std_logic;
- signal pattern_valid_q : std_logic;
-
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of trb_net16_med_16_IC_arch : architecture is "media_interface_group";
-
-begin
-
--------------------------------------------
--- RX Input
--------------------------------------------
-
- THE_INPUT_FF : process(DATA_CLK_IN)
- begin
- if falling_edge(DATA_CLK_IN) then
- buf_DATA_IN <= DATA_IN;
- buf_DATA_VALID_IN <= DATA_VALID_IN;
- buf_DATA_CTRL_IN <= DATA_CTRL_IN;
- end if;
- end process;
-
-
- THE_INPUT_SYNC : process(DATA_CLK_IN)
- begin
- if falling_edge(DATA_CLK_IN) then
- reg0_DATA_IN <= buf_DATA_IN;
- reg0_DATA_VALID_IN <= buf_DATA_VALID_IN;
- reg0_DATA_CTRL_IN <= buf_DATA_CTRL_IN;
- end if;
- end process;
- THE_INPUT_SYNC_2 : process(DATA_CLK_IN)
- begin
- if rising_edge(DATA_CLK_IN) then
- reg_DATA_IN <= reg0_DATA_IN;
- reg_DATA_VALID_IN <= reg0_DATA_VALID_IN;
- reg_DATA_CTRL_IN <= reg0_DATA_CTRL_IN;
- end if;
- end process;
-
--- THE_INPUT_SYNC : signal_sync
--- generic map(
--- DEPTH => 1,
--- WIDTH => 18
--- )
--- port map(
--- RESET => RESET,
--- D_IN(15 downto 0) => buf_DATA_IN,
--- D_IN(16) => buf_DATA_VALID_IN,
--- D_IN(17) => buf_DATA_CTRL_IN,
--- CLK0 => DATA_CLK_IN,
--- CLK1 => DATA_CLK_IN,
--- D_OUT(15 downto 0) => reg_DATA_IN,
--- D_OUT(16) => reg_DATA_VALID_IN,
--- D_OUT(17) => reg_DATA_CTRL_IN
--- );
-
--------------------------------------------
--- RX Fifo
--------------------------------------------
-
- THE_RX_FIFO : trb_net_fifo_16bit_bram_dualport
- port map(
- read_clock_in => CLK,
- write_clock_in => DATA_CLK_IN,
- read_enable_in => rx_fifo_read,
- write_enable_in => rx_fifo_write,
- fifo_gsr_in => rx_fifo_reset,
- write_data_in(15 downto 0) => reg_DATA_IN,
- write_data_in(16) => reg_DATA_VALID_IN,
- write_data_in(17) => reg_DATA_CTRL_IN,
- read_data_out => rx_fifo_dout,
- full_out => rx_fifo_full,
- empty_out => rx_fifo_empty,
- fifostatus_out => open,
- valid_read_out => open,
- almost_empty_out => open,
- almost_full_out => open
- );
-
- rx_fifo_write <= reg_DATA_VALID_IN and rx_allow_qrx;
- rx_fifo_reset <= RESET or not rx_allow_qrx;
- rx_fifo_read <= rx_allow;
-
-
--------------------------------------------
--- RX Output
--------------------------------------------
-
- PROC_RX_COUNTER : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- rx_counter <= unsigned(c_H0);
- elsif buf_MED_DATAREADY_OUT = '1' and CLK_EN = '1' then
- if rx_counter = unsigned(c_max_word_number) then
- rx_counter <= (others => '0');
- else
- rx_counter <= rx_counter + 1;
- end if;
- end if;
- end if;
- end process;
-
- PROC_RX_READ : process(CLK)
- begin
- if rising_edge(CLK) then
- rx_fifo_valid_read <= rx_fifo_read and not rx_fifo_empty;
- buf_MED_DATAREADY_OUT <= rx_fifo_valid_read;
- buf_MED_DATA_OUT <= rx_fifo_dout(15 downto 0);
- end if;
- end process;
-
-
- MED_DATA_OUT <= buf_MED_DATA_OUT;
- MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT;
- MED_PACKET_NUM_OUT <= std_logic_vector(rx_counter);
-
-
--------------------------------------------
--- TX
--------------------------------------------
-
-
- buf_MED_READ_OUT <= tx_allow;
- MED_READ_OUT <= buf_MED_READ_OUT;
-
-
- PROC_SEND_DATA : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- buf_DATA_VALID_OUT <= '0';
- buf_DATA_CTRL_OUT <= '0';
- buf_DATA_OUT <= (others => '0');
- present_sig <= '0';
- elsif CTRL_OP(15) = '1' then
- buf_DATA_VALID_OUT <= '0';
- buf_DATA_CTRL_OUT <= not buf_DATA_CTRL_OUT;
- buf_DATA_OUT <= x"FEFE";
- elsif MED_DATAREADY_IN = '1' and buf_MED_READ_OUT = '1' then
- buf_DATA_VALID_OUT <= '1';
- buf_DATA_OUT <= MED_DATA_IN;
- if MED_PACKET_NUM_IN = c_H0 then
- buf_DATA_CTRL_OUT <= '1';
- else
- buf_DATA_CTRL_OUT <= '0';
- end if;
- else
- buf_DATA_OUT <= x"AAAA";
- buf_DATA_CTRL_OUT <= present_sig;
- buf_DATA_VALID_OUT <= '0';
- present_sig <= not present_sig;
- end if;
- end if;
- end process;
-
-
- THE_CLK_OUT : ddr_off
- port map(
- Clk => CLK,
- Data(0) => not DATA_CLK_OUT_PHASE,
- Data(1) => DATA_CLK_OUT_PHASE,
- Q(0) => DATA_CLK_OUT
- );
-
-
- PROC_DATA_OUTPUT : process(CLK)
- begin
- if rising_edge(CLK) then
- DATA_VALID_OUT <= buf_DATA_VALID_OUT;
- DATA_CTRL_OUT <= buf_DATA_CTRL_OUT;
- DATA_OUT <= buf_DATA_OUT;
- end if;
- end process;
-
-
--------------------------------------------
--- Link Control
--------------------------------------------
-
- PROC_SIGNAL_DETECT_PREPARE : process(DATA_CLK_IN)
- begin
- if rising_edge(DATA_CLK_IN) then
- if RESET = '1' then
- last_DATA_CTRL_IN <= '0';
- pattern_detected <= '0';
- pattern_valid <= '0';
- elsif reg_DATA_VALID_IN = '0' then
- last_DATA_CTRL_IN <= reg_DATA_CTRL_IN;
- pattern_detected <= last_DATA_CTRL_IN xor reg_DATA_CTRL_IN;
- pattern_valid <= pattern_detected and not reg_DATA_VALID_IN;
- end if;
- end if;
- end process;
-
-
- PROC_FSM : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- link_state <= STARTUP;
- link_running <= '0';
- resync_received <= '0';
- not_connected <= '1';
- make_reset <= '0';
- rx_allow <= '0';
- tx_allow <= '0';
- else
- case link_state is
- when STARTUP =>
- med_error <= ERROR_NC;
- link_running <= '0';
- not_connected <= '1';
- resync_received <= '0';
- rx_allow <= '0';
- tx_allow <= '0';
- if pattern_detected_q = '1' then
- not_connected <= '0';
- link_state <= WAITING;
- pattern_counter <= x"040";
- end if;
-
- when WAITING =>
- med_error <= ERROR_WAIT;
- if pattern_valid_q = '1' then
- pattern_counter <= pattern_counter + "1";
- elsif pattern_detected_q = '0' then
- pattern_counter <= pattern_counter - x"39";
- end if;
- if pattern_counter < x"040" then
- link_state <= STARTUP;
- elsif pattern_counter = x"DFF" then
- rx_allow <= '1';
- elsif pattern_counter = x"FFF" then
- link_state <= WORKING;
- tx_allow <= '1';
- end if;
-
- when WORKING =>
- med_error <= ERROR_OK;
- link_running <= '1';
- if rx_resync_pattern_q = '1' then
- resync_received <= '1';
- else
- resync_received <= '0';
- make_reset <= resync_received;
- end if;
-
- if pattern_detected_q = '0' then
- link_running <= '0';
- link_state <= STARTUP;
- end if;
-
- when RESYNC_WAIT =>
- med_error <= ERROR_WAIT;
- if rx_idle_pattern_q = '1' then
- link_state <= WAITING;
- pattern_counter <= x"040";
- elsif pattern_detected_q = '0' then
- link_state <= STARTUP;
- end if;
-
- when others =>
- link_state <= STARTUP;
- end case;
- end if;
- end if;
- end process;
-
- state_bits <= "000" when link_state = STARTUP else
- "001" when link_state = WAITING else
- "011" when link_state = RESYNC_WAIT else
- "100" when link_state = WORKING else "111";
-
--------------------------------------------
--- Transfer RX status to sys clock domain
--------------------------------------------
-
- rx_idle_pattern <= '1' when reg_DATA_IN = x"AAAA" and reg_DATA_VALID_IN = '0' else '0';
- rx_resync_pattern <= '1' when reg_DATA_IN = x"FEFE" and reg_DATA_VALID_IN = '0' else '0';
-
-
- THE_SYNC_TO_SYS : signal_sync
- generic map(
- DEPTH => 3,
- WIDTH => 4
- )
- port map(
- RESET => RESET,
- D_IN(0) => pattern_detected,
- D_IN(1) => rx_idle_pattern,
- D_IN(2) => rx_resync_pattern,
- D_IN(3) => pattern_valid,
- CLK0 => DATA_CLK_IN,
- CLK1 => CLK,
- D_OUT(0) => pattern_detected_q,
- D_OUT(1) => rx_idle_pattern_q,
- D_OUT(2) => rx_resync_pattern_q,
- D_OUT(3) => pattern_valid_q
- );
-
- THE_SYNC_TO_RX : signal_sync
- generic map(
- DEPTH => 3,
- WIDTH => 1
- )
- port map(
- RESET => RESET,
- D_IN(0) => rx_allow,
- CLK0 => CLK,
- CLK1 => DATA_CLK_IN,
- D_OUT(0) => rx_allow_qrx
- );
-
-
-
-
-
--------------------------------------------
--- Link Status Information
--------------------------------------------
-
- PROC_LED : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' or not_connected = '1' then
- led_counter <= (others => '0');
- rx_led <= '0';
- tx_led <= '0';
- link_led <= '0';
- else
- led_counter <= led_counter + 1;
- link_led <= link_running;
- if led_counter(18) = '1' then
- led_counter <= (others => '0');
- rx_led <= '0';
- tx_led <= '0';
- end if;
- if buf_MED_DATAREADY_OUT = '1' then
- rx_led <= '1';
- end if;
- if MED_DATAREADY_IN = '1' and buf_MED_READ_OUT = '1' then
- tx_led <= '1';
- end if;
- end if;
- end if;
- end process;
-
-
- STAT_OP(2 downto 0) <= med_error;
- STAT_OP(8 downto 3) <= (others => '0');
- STAT_OP(9) <= link_led;
- STAT_OP(10) <= rx_led;
- STAT_OP(11) <= tx_led;
- STAT_OP(12) <= '0';
- STAT_OP(13) <= make_reset;
- STAT_OP(14) <= not_connected;
- STAT_OP(15) <= resync_received;
-
-
--------------------------------------------
--- Debug
--------------------------------------------
- STAT_DEBUG(0) <= reg_DATA_VALID_IN;
- STAT_DEBUG(1) <= reg_DATA_CTRL_IN;
- STAT_DEBUG(2) <= make_reset;
- STAT_DEBUG(3) <= MED_DATAREADY_IN;
- STAT_DEBUG(4) <= last_DATA_CTRL_IN;
- STAT_DEBUG(5) <= buf_DATA_VALID_OUT;
- STAT_DEBUG(6) <= buf_MED_READ_OUT;
- STAT_DEBUG(7) <= resync_received;
- STAT_DEBUG(15 downto 8) <= reg_DATA_IN(7 downto 0);
- STAT_DEBUG(18 downto 16) <= state_bits;
- STAT_DEBUG(31 downto 19) <= buf_DATA_OUT(12 downto 0);
-
- STAT_DEBUG(63 downto 32) <= (others => '0');
-
-end architecture;
\ No newline at end of file
+++ /dev/null
---media interface with 16 data lines, single data rate and oversampling of RX input
---oversampling running at 250 MHz
-
-
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net16_med_16_SDR_OS is
- generic(
- TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT : out std_logic;
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN : in std_logic;
-
- INT_DATAREADY_IN : in std_logic;
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT : out std_logic;
-
- -- Media direction port
- TX_DATA_OUT : out std_logic_vector (15 downto 0);
- TX_CLK_OUT : out std_logic;
- TX_CTRL_OUT : out std_logic_vector (3 downto 0);
- RX_DATA_IN : in std_logic_vector (15 downto 0);
- RX_CLK_IN : in std_logic;
- RX_CTRL_IN : in std_logic_vector (3 downto 0);
-
- -- Status and control port
- STAT_OP: out std_logic_vector (15 downto 0);
- CTRL_OP: in std_logic_vector (15 downto 0);
-
- STAT: out std_logic_vector (31 downto 0);
- CTRL: in std_logic_vector (31 downto 0)
- );
-end entity;
-
-architecture trb_net16_med_16_SDR_OS_arch of trb_net16_med_16_SDR_OS is
- component trb_net_clock_generator is
- generic(
- FREQUENCY_IN : real;
- FREQUENCY_OUT : real;
- CLOCK_MULT : integer range 1 to 32;
- CLOCK_DIV : integer range 1 to 32;
- CLKIN_DIVIDE_BY_2 : boolean;
- CLKIN_PERIOD : real
- );
- port(
- RESET : in std_logic;
- CLK_IN : in std_logic;
- CLK_OUT : out std_logic;
- LOCKED : out std_logic
- );
- end component;
-
- component trb_net_fifo_16bit_bram_dualport is
- generic(
- USE_STATUS_FLAGS : integer := c_YES
- );
- port (
- read_clock_in: IN std_logic;
- write_clock_in: IN std_logic;
- read_enable_in: IN std_logic;
- write_enable_in: IN std_logic;
- fifo_gsr_in: IN std_logic;
- write_data_in: IN std_logic_vector(17 downto 0);
- read_data_out: OUT std_logic_vector(17 downto 0);
- full_out: OUT std_logic;
- empty_out: OUT std_logic;
- fifostatus_out: OUT std_logic_vector(3 downto 0);
- valid_read_out: OUT std_logic;
- almost_empty_out:OUT std_logic;
- almost_full_out :OUT std_logic
- );
- end component;
-
- component dualdatarate_flipflop is
- --1 clock, no CE, PRE for Lattice SCM
- generic(
- WIDTH : integer := 1
- );
- port(
- C0 : in std_logic;
- C1 : in std_logic;
- CE : in std_logic;
- CLR : in std_logic;
- D0 : in std_logic_vector(WIDTH-1 downto 0);
- D1 : in std_logic_vector(WIDTH-1 downto 0);
- PRE : in std_logic;
- Q : out std_logic_vector(WIDTH-1 downto 0)
- );
- end component;
-
- signal RECV_CLK, recv_clk_locked : std_logic;
- signal reg_RX_CLK, buf_RX_CLK, last_RX_CLK : std_logic;
- signal reg_RX_CTRL, buf_RX_CTRL : std_logic_vector(3 downto 0);
- signal reg_RX_DATA, buf_RX_DATA : std_logic_vector(15 downto 0);
-
- signal rx_datavalid : std_logic;
- signal rx_first_packet : std_logic;
- signal rx_reset : std_logic;
- signal rx_parity : std_logic;
- signal rx_parity_match : std_logic;
-
- signal rx_fifo_read_enable : std_logic;
- signal rx_fifo_write_enable, next_rx_fifo_write_enable: std_logic;
- signal rx_fifo_data_in, next_rx_fifo_data_in : std_logic_vector(17 downto 0);
- signal rx_fifo_data_out : std_logic_vector(17 downto 0);
- signal rx_fifo_full : std_logic;
- signal rx_fifo_empty : std_logic;
- signal rx_fifostatus_out : std_logic_vector(3 downto 0);
- signal rx_valid_read_out : std_logic;
- signal rx_almost_empty_out : std_logic;
- signal rx_almost_full_out : std_logic;
-
-
- signal buf_INT_DATAREADY_OUT : std_logic;
-
- signal rx_packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal wait_for_startup : std_logic;
- signal wait_for_startup_slow : std_logic;
- signal rx_CLK_counter : std_logic_vector(4 downto 0);
- signal rx_clock_detect : std_logic;
-
- signal med_reset : std_logic;
-
- signal tx_datavalid, tx_first_packet, tx_reset, tx_parity : std_logic;
- signal buf_INT_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal buf_INT_READ_OUT : std_logic;
- signal tx_clock_enable : std_logic;
- signal next_tx_reset : std_logic;
- signal buf_tx_reset : std_logic;
- signal buf_tx_clk : std_logic;
- signal recv_clk_real_locked : std_logic;
- signal locked_counter : std_logic_vector(19 downto 0);
-
- signal led_counter : std_logic_vector(18 downto 0);
- signal send_resync_counter : std_logic_vector(11 downto 0);
- signal send_resync : std_logic;
- signal rx_led, tx_led, link_led : std_logic;
- signal med_error : std_logic_vector(2 downto 0);
- signal trbnet_reset : std_logic;
-begin
-
-
---Transmitter (full speed only)
--------------------------
- INT_READ_OUT <= buf_INT_READ_OUT;
- buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset;
-
- TX_DATA_OUT <= buf_INT_DATA_IN;
- TX_CTRL_OUT(0) <= tx_datavalid;
- TX_CTRL_OUT(1) <= tx_first_packet;
- TX_CTRL_OUT(2) <= tx_reset;
- TX_CTRL_OUT(3) <= tx_parity;
-
- tx_clock_enable <= not RESET;
-
- next_tx_reset <= CTRL_OP(15) or (recv_clk_real_locked and wait_for_startup_slow);
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- TX_CLK_OUT <= buf_tx_clk;
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- tx_datavalid <= '0';
- tx_reset <= '1';
- buf_tx_reset <= '1';
- buf_INT_DATA_IN <= (others => '0');
- tx_first_packet <= '0';
- tx_parity <= '0';
- buf_tx_clk <= '0';
- else
- buf_INT_DATA_IN <= INT_DATA_IN;
- tx_datavalid <= INT_DATAREADY_IN and buf_INT_READ_OUT;
- if INT_PACKET_NUM_IN = c_H0 then
- tx_first_packet <= '1';
- else
- tx_first_packet <= '0';
- end if;
- tx_reset <= buf_tx_reset;
- buf_tx_reset <= next_tx_reset;
- tx_parity <= xor_all(INT_DATA_IN);
- buf_tx_clk <= not buf_tx_clk;
- end if;
- end if;
- end process;
-
-
-
---Receiver
--------------------------
- RECV_CLOCK_GEN : trb_net_clock_generator
- generic map(
- FREQUENCY_IN => 100.0,
- FREQUENCY_OUT => 200.0,
- CLOCK_MULT => 2,
- CLOCK_DIV => 1,
- CLKIN_DIVIDE_BY_2 => false,
- CLKIN_PERIOD => 10.0
- )
- port map(
- RESET => RESET,
- CLK_IN => CLK,
- CLK_OUT => RECV_CLK,
- LOCKED => recv_clk_locked
- );
-
-process(CLK)
- begin
- if rising_edge(CLK) then
- if recv_clk_locked = '0' then
- locked_counter <= (others => '0');
- recv_clk_real_locked <= '0';
- else
- if locked_counter /= x"0000F" then
- locked_counter <= locked_counter + 1;
- else
- recv_clk_real_locked <= '1';
- end if;
- end if;
- end if;
- end process;
-
- RX_INPUT_REG : process(RECV_CLK)
- begin
- if rising_edge(RECV_CLK) then
- reg_RX_CLK <= RX_CLK_IN;
- reg_RX_CTRL <= RX_CTRL_IN;
- reg_RX_DATA <= RX_DATA_IN;
- end if;
- end process;
-
- RX_REG : process(RECV_CLK, recv_clk_real_locked)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_real_locked = '0' then
- buf_RX_CTRL <= (others => '0');
- buf_RX_CLK <= '0';
- last_RX_CLK <= '0';
- buf_RX_DATA <= (others => '0');
- else
- buf_RX_CLK <= reg_RX_CLK;
- buf_RX_DATA <= reg_RX_DATA;
- buf_RX_CTRL <= reg_RX_CTRL;
- last_RX_CLK <= buf_RX_CLK;
- end if;
- end if;
- end process;
-
- rx_datavalid <= buf_RX_CTRL(0);
- rx_first_packet <= buf_RX_CTRL(1);
- rx_reset <= buf_RX_CTRL(2);
- rx_parity <= buf_RX_CTRL(3);
-
- rx_parity_match <= '1' when rx_parity = xor_all(buf_RX_DATA) else '0';
- next_rx_fifo_write_enable <= (buf_RX_CLK xor last_RX_CLK) and rx_datavalid;
- next_rx_fifo_data_in <= rx_first_packet & rx_parity_match & buf_RX_DATA;
-
- reg_fifo_in : process(RECV_CLK)
- begin
- if rising_edge(RECV_CLK) then
- rx_fifo_write_enable <= next_rx_fifo_write_enable;
- rx_fifo_data_in <= next_rx_fifo_data_in;
- end if;
- end process;
-
- RX_FIFO : trb_net_fifo_16bit_bram_dualport
- port map(
- read_clock_in => CLK,
- write_clock_in => RECV_CLK,
- read_enable_in => rx_fifo_read_enable,
- write_enable_in => rx_fifo_write_enable,
- fifo_gsr_in => med_reset,
- write_data_in => rx_fifo_data_in,
- read_data_out => rx_fifo_data_out,
- full_out => rx_fifo_full,
- empty_out => rx_fifo_empty,
- fifostatus_out => rx_fifostatus_out,
- valid_read_out => rx_valid_read_out,
- almost_empty_out => rx_almost_empty_out,
- almost_full_out => rx_almost_full_out
- );
-
- rx_fifo_read_enable <= INT_READ_IN;
-
- INT_DATA_OUT <= rx_fifo_data_out(15 downto 0);
- INT_PACKET_NUM_OUT <= rx_packet_counter;
- INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
-
- packet_counter_p : process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- rx_packet_counter <= "100";
- elsif buf_INT_DATAREADY_OUT = '1' then
- if rx_packet_counter = c_max_word_number then
- rx_packet_counter <= (others => '0');
- else
- rx_packet_counter <= rx_packet_counter + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- rx_dataready_p : process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- buf_INT_DATAREADY_OUT <= '0';
- else
- buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty;
- end if;
- end if;
- end process;
-
-
---monitor link
--------------------------
- process(CLK)
- begin
- if rising_edge(CLK) then
- wait_for_startup_slow <= wait_for_startup;
- end if;
- end process;
-
- process(RECV_CLK, recv_clk_real_locked,med_reset)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_real_locked = '0' or med_reset = '1' or rx_clock_detect = '0' then
- wait_for_startup <= '1';
- elsif rx_reset = '1' and recv_clk_locked = '1' then
- wait_for_startup <= '0';
- end if;
- end if;
- end process;
-
-
- ERROR_OUT_gen : process(CLK)
- begin
- if rising_edge(CLK) then
- if recv_clk_real_locked = '0' or rx_clock_detect = '0' then
- med_error <= ERROR_NC;
- elsif (buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(16) = '0') then --Parity error
- med_error <= ERROR_ENCOD;
- elsif (rx_packet_counter /= "100" and buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(17) = '1') then
- med_error <= ERROR_FATAL; --Counter error
- else
- med_error <= ERROR_OK;
- end if;
- end if;
- end process;
-
-
- rx_clk_detect_counter: process (RECV_CLK, recv_clk_real_locked)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_real_locked = '0' then
- rx_CLK_counter <= (others => '0');
- rx_clock_detect <= '0';
- elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then
- rx_CLK_counter <= (others => '0');
- rx_clock_detect <= '1';
- elsif rx_CLK_counter /= 31 then
- rx_CLK_counter <= rx_CLK_counter + 1;
- elsif rx_CLK_counter = 31 then
- rx_clock_detect <= '0';
- end if;
- end if;
- end process;
-
-
---STAT & CTRL Ports
--------------------------
-
---LED
- link_led <= rx_clock_detect and not wait_for_startup_slow;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if led_counter(18) = '1' then
- led_counter <= (others => '0');
- else
- led_counter <= led_counter + 1;
- end if;
- if rx_fifo_empty = '0' then
- rx_led <= '1';
- elsif led_counter(18) = '1' then
- rx_led <= '0';
- end if;
- if tx_datavalid = '1' then
- tx_led <= '1';
- elsif led_counter(18) = '1' then
- tx_led <= '0';
- end if;
- end if;
- end process;
-
-
- STAT_OP(2 downto 0) <= med_error;
- STAT_OP(8 downto 3) <= (others => '0');
- STAT_OP(9) <= link_led;
- STAT_OP(10) <= rx_led;
- STAT_OP(11) <= tx_led;
- STAT_OP(12) <= '0';
- STAT_OP(13) <= trbnet_reset;
- STAT_OP(14) <= rx_clock_detect;
- STAT_OP(15) <= '1' when rx_reset = '1' and wait_for_startup_slow = '0' else '0';
-
- STAT(12) <= rx_parity_match;
- STAT(11) <= RECV_CLK;
- STAT(10) <= recv_clk_real_locked;
- STAT(9) <= rx_reset;
- STAT(8) <= buf_RX_CLK xor last_RX_CLK;
- STAT(7) <= recv_clk_locked;
- STAT(6) <= wait_for_startup;
- STAT(5) <= rx_first_packet;
- STAT(4) <= buf_tx_clk; --not or_all(INT_PACKET_NUM_IN); --tx_first_packet;
- STAT(3) <= rx_datavalid;
- STAT(2) <= next_tx_reset;
- STAT(1) <= buf_RX_CLK;
-
- STAT(13) <= or_all(rx_fifostatus_out);
- STAT(14) <= rx_valid_read_out;
- STAT(15) <= rx_almost_empty_out;
- STAT(16) <= rx_almost_full_out;
- STAT(31 downto 17) <= (others => '0');
-
- med_reset <= RESET or send_resync;
- trbnet_reset <= rx_reset or not recv_clk_real_locked;
-
-
---detect resync
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- send_resync <= '0';
- send_resync_counter <= (others => '0');
- else
- if not (send_resync_counter = 0) then
- send_resync_counter <= send_resync_counter + 1;
- end if;
- if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then
- send_resync <= '1';
- send_resync_counter <= send_resync_counter + 1;
- end if;
- if send_resync_counter = x"00F" then
- send_resync <= '0';
- end if;
- end if;
- end if;
- end process;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
---media interface with 16 data lines, single data rate and oversampling of RX input
---oversampling running at 250 MHz
-
-
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net16_med_8_DDR_OS is
- generic(
- TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT : out std_logic;
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN : in std_logic;
-
- INT_DATAREADY_IN : in std_logic;
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT : out std_logic;
-
- -- Media direction port
- TX_DATA_OUT : out std_logic_vector (7 downto 0);
- TX_CLK_OUT : out std_logic;
- TX_CTRL_OUT : out std_logic_vector (1 downto 0);
- RX_DATA_IN : in std_logic_vector (7 downto 0);
- RX_CLK_IN : in std_logic;
- RX_CTRL_IN : in std_logic_vector (1 downto 0);
-
- -- Status and control port
- STAT_OP: out std_logic_vector (15 downto 0);
- CTRL_OP: in std_logic_vector (15 downto 0);
-
- STAT: out std_logic_vector (31 downto 0);
- CTRL: in std_logic_vector (31 downto 0)
- );
-end entity;
-
-architecture trb_net16_med_8_DDR_OS_arch of trb_net16_med_8_DDR_OS is
-
- component trb_net_clock_generator is
- generic(
- FREQUENCY_IN : real;
- FREQUENCY_OUT : real;
- CLOCK_MULT : integer range 1 to 32;
- CLOCK_DIV : integer range 1 to 32;
- CLKIN_DIVIDE_BY_2 : boolean;
- CLKIN_PERIOD : real
- );
- port(
- RESET : in std_logic;
- CLK_IN : in std_logic;
- CLK_OUT : out std_logic;
- LOCKED : out std_logic
- );
- end component;
-
- component trb_net_fifo_16bit_bram_dualport is
- generic(
- USE_STATUS_FLAGS : integer := c_YES
- );
- port (
- read_clock_in: IN std_logic;
- write_clock_in: IN std_logic;
- read_enable_in: IN std_logic;
- write_enable_in: IN std_logic;
- fifo_gsr_in: IN std_logic;
- write_data_in: IN std_logic_vector(17 downto 0);
- read_data_out: OUT std_logic_vector(17 downto 0);
- full_out: OUT std_logic;
- empty_out: OUT std_logic;
- fifostatus_out: OUT std_logic_vector(3 downto 0);
- valid_read_out: OUT std_logic;
- almost_empty_out:OUT std_logic;
- almost_full_out :OUT std_logic
- );
- end component;
-
- component signal_sync is
- generic(
- WIDTH : integer := 1; --
- DEPTH : integer := 3
- );
- port(
- RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
- CLK0 : in std_logic; --clock for first FF
- CLK1 : in std_logic; --Clock for other FF
- D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input
- D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output
- );
- end component;
-
- signal RECV_CLK, recv_clk_locked : std_logic;
- signal reg_RX_CLK, buf_RX_CLK, last_RX_CLK : std_logic;
- signal reg_RX_CTRL, buf_RX_CTRL : std_logic_vector(1 downto 0);
- signal reg_RX_DATA, buf_RX_DATA : std_logic_vector(7 downto 0);
-
- signal rx_datavalid : std_logic;
- signal rx_reset : std_logic;
-
- signal rx_fifo_read_enable : std_logic;
- signal rx_fifo_write_enable, next_rx_fifo_write_enable: std_logic;
- signal rx_fifo_data_in, next_rx_fifo_data_in : std_logic_vector(17 downto 0);
- signal rx_fifo_data_out : std_logic_vector(17 downto 0);
- signal rx_fifo_full : std_logic;
- signal rx_fifo_empty : std_logic;
- signal rx_fifostatus_out : std_logic_vector(3 downto 0);
- signal rx_valid_read_out : std_logic;
- signal rx_almost_empty_out : std_logic;
- signal rx_almost_full_out : std_logic;
- signal saved_fifo_data_out : std_logic_vector(7 downto 0);
-
- signal buf_INT_DATAREADY_OUT : std_logic;
-
- signal rx_packet_counter : std_logic_vector(3 downto 0);
- signal wait_for_startup : std_logic;
- signal wait_for_startup_slow : std_logic;
- signal rx_CLK_counter : std_logic_vector(4 downto 0);
- signal rx_clock_detect : std_logic;
-
- signal med_reset : std_logic;
-
- signal tx_datavalid, tx_first_packet, tx_reset, tx_parity : std_logic;
- signal buf_INT_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal buf_INT_READ_OUT : std_logic;
- signal tx_clock_enable : std_logic;
- signal next_tx_reset : std_logic;
- signal buf_tx_reset : std_logic;
- signal buf_tx_clk : std_logic;
- signal recv_clk_real_locked : std_logic;
- signal locked_counter : std_logic_vector(19 downto 0);
-
- signal led_counter : std_logic_vector(18 downto 0);
- signal rx_led, tx_led, link_led : std_logic;
- signal med_error : std_logic_vector(2 downto 0);
-
- signal tx_data : std_logic_vector(7 downto 0);
- signal tx_word_waiting : std_logic;
- signal tx_data_buffer : std_logic_vector(7 downto 0);
- signal next_recv_clk_locked : std_logic;
- signal recv_clk_real_locked_q : std_logic;
-begin
-
-
---Transmitter (full speed only)
--------------------------
- INT_READ_OUT <= buf_INT_READ_OUT;
-
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- TX_CLK_OUT <= buf_tx_clk;
- TX_DATA_OUT <= tx_data;
- TX_CTRL_OUT(0) <= tx_datavalid;
- TX_CTRL_OUT(1) <= buf_tx_reset;
- end if;
- end process;
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- buf_tx_reset <= '1';
- buf_tx_clk <= '0';
- else
- buf_tx_reset <= (recv_clk_real_locked_q and wait_for_startup_slow);
- buf_tx_clk <= not buf_tx_clk;
- end if;
- end if;
- end process;
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- tx_datavalid <= '0';
- buf_INT_DATA_IN <= (others => '0');
- buf_INT_READ_OUT <= '0';
- tx_data <= (others => '0');
- tx_word_waiting <= '0';
- else
- if tx_word_waiting = '1' then
- tx_data <= tx_data_buffer;
- tx_datavalid <= '1';
- buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset;
- tx_word_waiting <= '0';
- elsif INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then
- tx_data <= INT_DATA_IN(15 downto 8);
- tx_data_buffer <= INT_DATA_IN(7 downto 0);
- tx_datavalid <= '1';
- tx_word_waiting <= '1';
- buf_INT_READ_OUT <= '0';
- else
- tx_datavalid <= '0';
- buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset;
- end if;
- end if;
- end if;
- end process;
-
-
-
---Receiver
--------------------------
- RECV_CLOCK_GEN : trb_net_clock_generator
- generic map(
- FREQUENCY_IN => 100.0,
- FREQUENCY_OUT => 200.0,
- CLOCK_MULT => 2,
- CLOCK_DIV => 1,
- CLKIN_DIVIDE_BY_2 => false,
- CLKIN_PERIOD => 10.0
- )
- port map(
- RESET => RESET,
- CLK_IN => CLK,
- CLK_OUT => RECV_CLK,
- LOCKED => recv_clk_locked
- );
-
--- THE_SYNC_TO_CLK : signal_sync
--- generic map(
--- DEPTH => 2,
--- WIDTH => 1
--- )
--- port map(
--- RESET => RESET,
--- D_IN(0) => next_recv_clk_locked,
--- CLK0 => CLK,
--- CLK1 => CLK,
--- D_OUT(0) => recv_clk_locked
--- );
-
- THE_SYNC_TO_CLK_0 : signal_sync
- generic map(
- DEPTH => 3,
- WIDTH => 1
- )
- port map(
- RESET => RESET,
- D_IN(0) => recv_clk_real_locked,
- CLK0 => CLK,
- CLK1 => CLK,
- D_OUT(0) => recv_clk_real_locked_q
- );
-
-process(CLK)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_locked = '0' then
- locked_counter <= (others => '0');
- recv_clk_real_locked <= '0';
- else
- if locked_counter /= x"0000F" then
- locked_counter <= locked_counter + 1;
- else
- recv_clk_real_locked <= '1';
- end if;
- end if;
- end if;
- end process;
-
- RX_INPUT_REG : process(RECV_CLK)
- begin
- if rising_edge(RECV_CLK) then
- reg_RX_CLK <= RX_CLK_IN;
- reg_RX_CTRL <= RX_CTRL_IN;
- reg_RX_DATA <= RX_DATA_IN;
- end if;
- end process;
-
- RX_REG : process(RECV_CLK, recv_clk_real_locked)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_real_locked = '0' then
- buf_RX_CTRL <= (others => '0');
- buf_RX_CLK <= '0';
- last_RX_CLK <= '0';
- buf_RX_DATA <= (others => '0');
- else
- buf_RX_CLK <= reg_RX_CLK;
- buf_RX_DATA <= reg_RX_DATA;
- buf_RX_CTRL <= reg_RX_CTRL;
- last_RX_CLK <= buf_RX_CLK;
- end if;
- end if;
- end process;
-
- rx_datavalid <= buf_RX_CTRL(0);
- rx_reset <= buf_RX_CTRL(1);
-
- next_rx_fifo_write_enable <= (buf_RX_CLK xor last_RX_CLK) and rx_datavalid;
- next_rx_fifo_data_in <= x"00" & '0' & '0' & buf_RX_DATA;
-
- reg_fifo_in : process(RECV_CLK)
- begin
- if rising_edge(RECV_CLK) then
- rx_fifo_write_enable <= next_rx_fifo_write_enable;
- rx_fifo_data_in <= next_rx_fifo_data_in;
- end if;
- end process;
-
- RX_FIFO : trb_net_fifo_16bit_bram_dualport
- port map(
- read_clock_in => CLK,
- write_clock_in => RECV_CLK,
- read_enable_in => rx_fifo_read_enable,
- write_enable_in => rx_fifo_write_enable,
- fifo_gsr_in => med_reset,
- write_data_in => rx_fifo_data_in,
- read_data_out => rx_fifo_data_out,
- full_out => rx_fifo_full,
- empty_out => rx_fifo_empty,
- fifostatus_out => rx_fifostatus_out,
- valid_read_out => rx_valid_read_out,
- almost_empty_out => rx_almost_empty_out,
- almost_full_out => rx_almost_full_out
- );
-
- rx_fifo_read_enable <= INT_READ_IN;
-
- proc_rx_dataoutput : process(CLK)
- begin
- if rising_edge(CLK) then
- INT_DATA_OUT <= saved_fifo_data_out(7 downto 0) & rx_fifo_data_out(7 downto 0);
- INT_PACKET_NUM_OUT <= rx_packet_counter(3 downto 1);
- INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
- end if;
- end process;
-
- packet_counter_p : process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- rx_packet_counter <= "0111";
- elsif rx_fifo_read_enable = '1' and rx_fifo_empty = '0' then
- if rx_packet_counter = c_max_word_number & '1' then
- rx_packet_counter <= (others => '0');
- else
- rx_packet_counter <= rx_packet_counter + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- rx_dataready_p : process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- buf_INT_DATAREADY_OUT <= '0';
- saved_fifo_data_out <= (others => '0');
- else
- buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty and not rx_packet_counter(0);
- if rx_fifo_read_enable = '1' and rx_fifo_empty = '0' and rx_packet_counter(0) = '1' then
- saved_fifo_data_out <= rx_fifo_data_out(7 downto 0);
- end if;
- end if;
- end if;
- end process;
-
-
---monitor link
--------------------------
-
- THE_SYNCTOCLK : signal_sync
- generic map(
- DEPTH => 3,
- WIDTH => 1
- )
- port map(
- RESET => RESET,
- D_IN(0) => wait_for_startup,
- CLK0 => CLK,
- CLK1 => CLK,
- D_OUT(0) => wait_for_startup_slow
- );
-
-
- process(RECV_CLK, recv_clk_real_locked,med_reset)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_real_locked = '0' or med_reset = '1' or rx_clock_detect = '0' then
- wait_for_startup <= '1';
- elsif rx_reset = '1' and recv_clk_real_locked = '1' then --
- wait_for_startup <= '0';
- end if;
- end if;
- end process;
-
-
- ERROR_OUT_gen : process(CLK)
- begin
- if rising_edge(CLK) then
- if recv_clk_real_locked = '0' or rx_clock_detect = '0' then -- or wait_for_startup_slow = '1'
- med_error <= ERROR_NC;
- else
- med_error <= ERROR_OK;
- end if;
- end if;
- end process;
-
-
- rx_clk_detect_counter: process (RECV_CLK, recv_clk_real_locked)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_real_locked = '0' then
- rx_CLK_counter <= (others => '0');
- rx_clock_detect <= '0';
- elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then
- rx_CLK_counter <= (others => '0');
- rx_clock_detect <= '1';
- elsif rx_CLK_counter /= 31 then
- rx_CLK_counter <= rx_CLK_counter + 1;
- elsif rx_CLK_counter = 31 then
- rx_clock_detect <= '0';
- end if;
- end if;
- end process;
-
-
---STAT & CTRL Ports
--------------------------
-
---LED
- link_led <= rx_clock_detect and not wait_for_startup_slow;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if led_counter(18) = '1' then
- led_counter <= (others => '0');
- else
- led_counter <= led_counter + 1;
- end if;
- if rx_fifo_empty = '0' then
- rx_led <= '1';
- elsif led_counter(18) = '1' then
- rx_led <= '0';
- end if;
- if tx_datavalid = '1' then
- tx_led <= '1';
- elsif led_counter(18) = '1' then
- tx_led <= '0';
- end if;
- end if;
- end process;
-
-
- STAT_OP(2 downto 0) <= med_error;
- STAT_OP(8 downto 3) <= (others => '0');
- STAT_OP(9) <= link_led;
- STAT_OP(10) <= rx_led;
- STAT_OP(11) <= tx_led;
- STAT_OP(12) <= '0';
- STAT_OP(13) <= '0'; --trbnet_reset;
- STAT_OP(14) <= rx_clock_detect;
- STAT_OP(15) <= '1' when rx_reset = '1' and wait_for_startup_slow = '0' else '0';
-
-
- STAT(7 downto 0) <= buf_RX_DATA;
- STAT(9 downto 8) <= buf_RX_CTRL;
- STAT(10) <= buf_RX_CLK;
- STAT(11) <= wait_for_startup_slow;
- STAT(12) <= rx_fifo_empty;
- STAT(13) <= rx_fifo_read_enable;
- STAT(14) <= rx_fifo_write_enable;
- STAT(15) <= rx_clock_detect;
- STAT(31 downto 16) <= (others => '0');
-
- med_reset <= RESET;
--- trbnet_reset <= rx_reset or not recv_clk_real_locked;
-
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net16_med_8_SDR_OS is
- generic(
- TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT : out std_logic;
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN : in std_logic;
-
- INT_DATAREADY_IN : in std_logic;
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT : out std_logic;
-
- -- Media direction port
- TX_DATA_OUT : out std_logic_vector (7 downto 0);
- TX_CLK_OUT : out std_logic;
- TX_CTRL_OUT : out std_logic_vector (1 downto 0);
- RX_DATA_IN : in std_logic_vector (7 downto 0);
- RX_CLK_IN : in std_logic;
- RX_CTRL_IN : in std_logic_vector (1 downto 0);
-
- -- Status and control port
- STAT_OP: out std_logic_vector (15 downto 0);
- CTRL_OP: in std_logic_vector (15 downto 0);
-
- STAT: out std_logic_vector (31 downto 0);
- CTRL: in std_logic_vector (31 downto 0)
- );
-end entity;
-
-architecture trb_net16_med_8_SDR_OS_arch of trb_net16_med_8_SDR_OS is
-
- component trb_net_fifo_16bit_bram_dualport is
- generic(
- USE_STATUS_FLAGS : integer := c_YES
- );
- port (
- read_clock_in: IN std_logic;
- write_clock_in: IN std_logic;
- read_enable_in: IN std_logic;
- write_enable_in: IN std_logic;
- fifo_gsr_in: IN std_logic;
- write_data_in: IN std_logic_vector(17 downto 0);
- read_data_out: OUT std_logic_vector(17 downto 0);
- full_out: OUT std_logic;
- empty_out: OUT std_logic;
- fifostatus_out: OUT std_logic_vector(3 downto 0);
- valid_read_out: OUT std_logic;
- almost_empty_out:OUT std_logic;
- almost_full_out :OUT std_logic
- );
- end component;
-
- component signal_sync is
- generic(
- WIDTH : integer := 1; --
- DEPTH : integer := 3
- );
- port(
- RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
- CLK0 : in std_logic; --clock for first FF
- CLK1 : in std_logic; --Clock for other FF
- D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input
- D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output
- );
- end component;
-
- signal reg_RX_CLK, buf_RX_CLK, last_RX_CLK : std_logic;
- signal reg_RX_CTRL, buf_RX_CTRL : std_logic_vector(1 downto 0);
- signal reg_RX_DATA, buf_RX_DATA : std_logic_vector(7 downto 0);
-
- signal rx_datavalid : std_logic;
- signal rx_reset : std_logic;
- signal rx_fifo_read_enable : std_logic;
- signal rx_fifo_write_enable, next_rx_fifo_write_enable: std_logic;
- signal rx_fifo_data_in, next_rx_fifo_data_in : std_logic_vector(17 downto 0);
- signal rx_fifo_data_out : std_logic_vector(17 downto 0);
- signal rx_fifo_empty : std_logic;
- signal rx_packet_counter : std_logic_vector(3 downto 0);
- signal rx_CLK_counter : std_logic_vector(4 downto 0);
- signal rx_clock_detect : std_logic;
-
-
- signal saved_fifo_data_out : std_logic_vector(7 downto 0);
-
- signal med_reset : std_logic;
-
- signal tx_datavalid : std_logic;
- signal buf_INT_READ_OUT : std_logic;
- signal buf_INT_DATAREADY_OUT : std_logic;
- signal buf_tx_reset : std_logic;
- signal buf_tx_clk : std_logic;
-
- signal led_counter : std_logic_vector(18 downto 0);
- signal rx_led, tx_led, link_led : std_logic;
- signal med_error : std_logic_vector(2 downto 0);
-
- signal tx_data : std_logic_vector(7 downto 0);
- signal tx_word_waiting : std_logic;
- signal tx_data_buffer : std_logic_vector(7 downto 0);
- signal last_rx_fifo_read_enable : std_logic;
- signal last_rx_fifo_empty : std_logic;
- signal buf_tx_half_clk : std_logic;
- signal rx_active : std_logic;
- signal tx_active : std_logic;
- signal rx_fifo_reset : std_logic;
- signal active_counter : std_logic_vector(15 downto 0);
-
-begin
-
- med_reset <= RESET;
-
-
-
---Transmitter
--------------------------
- INT_READ_OUT <= buf_INT_READ_OUT;
-
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- TX_CLK_OUT <= buf_tx_half_clk;
- TX_DATA_OUT <= tx_data;
- TX_CTRL_OUT(0) <= tx_datavalid;
- TX_CTRL_OUT(1) <= buf_tx_reset;
- end if;
- end process;
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- buf_tx_reset <= '1';
- buf_tx_clk <= '0';
- buf_tx_half_clk <= '0';
- else
- buf_tx_reset <= not tx_active;
- buf_tx_clk <= not buf_tx_clk;
- if buf_tx_clk = '1' then
- buf_tx_half_clk <= not buf_tx_half_clk;
- end if;
- end if;
- end if;
- end process;
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' or tx_active = '0' then
- tx_datavalid <= '0';
- buf_INT_READ_OUT <= '0';
- tx_data <= (others => '0');
- tx_word_waiting <= '0';
- else
- buf_INT_READ_OUT <= '0';
- if buf_tx_half_clk = '0' and buf_tx_clk = '0' then
- if tx_word_waiting = '1' then
- tx_data <= tx_data_buffer;
- tx_datavalid <= '1';
- tx_word_waiting <= '0';
- elsif INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then
- tx_data <= INT_DATA_IN(15 downto 8);
- tx_data_buffer <= INT_DATA_IN(7 downto 0);
- tx_datavalid <= '1';
- tx_word_waiting <= '1';
- else
- tx_datavalid <= '0';
- end if;
- elsif buf_tx_half_clk = '1' and buf_tx_clk = '1' then
- buf_INT_READ_OUT <= not tx_word_waiting and tx_active;
- end if;
- end if;
- end if;
- end process;
-
-
-
---Receiver
--------------------------
-
- RX_INPUT_REG : process(CLK)
- begin
- if rising_edge(CLK) then
- reg_RX_CLK <= RX_CLK_IN;
- reg_RX_CTRL <= RX_CTRL_IN;
- reg_RX_DATA <= RX_DATA_IN;
- end if;
- end process;
-
- RX_REG : process(CLK)
- begin
- if rising_edge(CLK) then
- buf_RX_CLK <= reg_RX_CLK;
- buf_RX_DATA <= reg_RX_DATA;
- buf_RX_CTRL <= reg_RX_CTRL;
- last_RX_CLK <= buf_RX_CLK;
- end if;
- end process;
-
- rx_datavalid <= buf_RX_CTRL(0);
- rx_reset <= buf_RX_CTRL(1);
-
- next_rx_fifo_write_enable <= (buf_RX_CLK and not last_RX_CLK) and rx_datavalid and rx_active;
- next_rx_fifo_data_in <= x"00" & '0' & '0' & buf_RX_DATA;
-
- reg_fifo_in : process(CLK)
- begin
- if rising_edge(CLK) then
- rx_fifo_write_enable <= next_rx_fifo_write_enable;
- rx_fifo_data_in <= next_rx_fifo_data_in;
- end if;
- end process;
-
- RX_FIFO : trb_net_fifo_16bit_bram_dualport
- port map(
- read_clock_in => CLK,
- write_clock_in => CLK,
- read_enable_in => rx_fifo_read_enable,
- write_enable_in => rx_fifo_write_enable,
- fifo_gsr_in => rx_fifo_reset,
- write_data_in => rx_fifo_data_in,
- read_data_out => rx_fifo_data_out,
- full_out => open,
- empty_out => rx_fifo_empty,
- fifostatus_out => open,
- valid_read_out => open,
- almost_empty_out => open,
- almost_full_out => open
- );
-
- rx_fifo_reset <= med_reset or not rx_active;
- rx_fifo_read_enable <= INT_READ_IN;
-
- proc_rx_dataoutput : process(CLK)
- begin
- if rising_edge(CLK) then
- INT_DATA_OUT <= saved_fifo_data_out(7 downto 0) & rx_fifo_data_out(7 downto 0);
- INT_PACKET_NUM_OUT <= rx_packet_counter(3 downto 1);
- INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
-
- last_rx_fifo_read_enable <= rx_fifo_read_enable;
- last_rx_fifo_empty <= rx_fifo_empty;
- end if;
- end process;
-
- packet_counter_p : process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- rx_packet_counter <= "0111";
- elsif rx_fifo_read_enable = '1' and rx_fifo_empty = '0' then
- if rx_packet_counter = c_max_word_number & '1' then
- rx_packet_counter <= (others => '0');
- else
- rx_packet_counter <= rx_packet_counter + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- rx_dataready_p : process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- buf_INT_DATAREADY_OUT <= '0';
- saved_fifo_data_out <= (others => '0');
- else
- buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty and not rx_packet_counter(0);
- if last_rx_fifo_read_enable = '1' and last_rx_fifo_empty = '0' and rx_packet_counter(0) = '0' then
- saved_fifo_data_out <= rx_fifo_data_out(7 downto 0);
- end if;
- end if;
- end if;
- end process;
-
-
---monitor link
--------------------------
-
-
- ERROR_OUT_gen : process(CLK)
- begin
- if rising_edge(CLK) then
- if rx_clock_detect = '0' or rx_active = '0' then
- med_error <= ERROR_NC;
- else
- med_error <= ERROR_OK;
- end if;
- end if;
- end process;
-
-
- rx_clk_detect_counter: process (CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- rx_CLK_counter <= (others => '0');
- rx_clock_detect <= '0';
- elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then
- rx_CLK_counter <= (others => '0');
- rx_clock_detect <= '1';
- elsif rx_CLK_counter /= 31 then
- rx_CLK_counter <= rx_CLK_counter + 1;
- elsif rx_CLK_counter = 31 then
- rx_clock_detect <= '0';
- end if;
- end if;
- end process;
-
- proc_active : process(CLK)
- begin
- if rising_edge(CLK) then
- if rx_clock_detect = '0' then
- active_counter <= (others => '0');
- elsif active_counter < x"FFFF" then
- active_counter <= active_counter + 1;
- end if;
- if active_counter > x"8000" then
- rx_active <= '1';
- else
- rx_active <= '0';
- end if;
- if active_counter = x"FFFF" then
- tx_active <= '1';
- else
- tx_active <= '0';
- end if;
- end if;
- end process;
-
---STAT & CTRL Ports
--------------------------
-
---LED
- link_led <= rx_clock_detect and rx_active and tx_active;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if led_counter(18) = '1' then
- led_counter <= (others => '0');
- else
- led_counter <= led_counter + 1;
- end if;
- if rx_fifo_empty = '0' then
- rx_led <= '1';
- elsif led_counter(18) = '1' then
- rx_led <= '0';
- end if;
- if tx_datavalid = '1' then
- tx_led <= '1';
- elsif led_counter(18) = '1' then
- tx_led <= '0';
- end if;
- end if;
- end process;
-
-
- STAT_OP(2 downto 0) <= med_error;
- STAT_OP(8 downto 3) <= (others => '0');
- STAT_OP(9) <= link_led;
- STAT_OP(10) <= rx_led;
- STAT_OP(11) <= tx_led;
- STAT_OP(12) <= '0';
- STAT_OP(13) <= '0'; --trbnet_reset;
- STAT_OP(14) <= not rx_clock_detect;
- STAT_OP(15) <= not rx_active;
-
-
- STAT(7 downto 0) <= buf_RX_DATA;
- STAT(9 downto 8) <= buf_RX_CTRL;
- STAT(10) <= buf_RX_CLK;
- STAT(11) <= '0';
- STAT(12) <= rx_fifo_empty;
- STAT(13) <= rx_fifo_read_enable;
- STAT(14) <= rx_fifo_write_enable;
- STAT(15) <= rx_clock_detect;
- STAT(23 downto 16) <= tx_data;
- STAT(24) <= tx_datavalid;
- STAT(31 downto 25) <= (others => '0');
-
-
-
-end architecture;
\ No newline at end of file
+++ /dev/null
---media interface with 16 data lines, single data rate and oversampling of RX input
---oversampling running at 250 MHz
-
-
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net16_med_8_SDR_sync is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT : out std_logic;
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN : in std_logic;
-
- INT_DATAREADY_IN : in std_logic;
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT : out std_logic;
-
- -- Media direction port
- TX_DATA_OUT : out std_logic_vector (15 downto 0);
- TX_CTRL_OUT : out std_logic_vector (3 downto 0);
- RX_DATA_IN : in std_logic_vector (15 downto 0);
- RX_CTRL_IN : in std_logic_vector (3 downto 0);
-
- -- Status and control port
- STAT_OP: out std_logic_vector (15 downto 0);
- CTRL_OP: in std_logic_vector (15 downto 0);
-
- STAT: out std_logic_vector (31 downto 0);
- CTRL: in std_logic_vector (31 downto 0)
- );
-end entity;
-
-architecture trb_net16_med_8_SDR_sync_arch of trb_net16_med_8_SDR_sync is
-
- component trb_net_fifo_16bit_bram_dualport is
- generic(
- USE_STATUS_FLAGS : integer := c_YES
- );
- port (
- read_clock_in: IN std_logic;
- write_clock_in: IN std_logic;
- read_enable_in: IN std_logic;
- write_enable_in: IN std_logic;
- fifo_gsr_in: IN std_logic;
- write_data_in: IN std_logic_vector(17 downto 0);
- read_data_out: OUT std_logic_vector(17 downto 0);
- full_out: OUT std_logic;
- empty_out: OUT std_logic;
- fifostatus_out: OUT std_logic_vector(3 downto 0);
- valid_read_out: OUT std_logic;
- almost_empty_out:OUT std_logic;
- almost_full_out :OUT std_logic
- );
- end component;
-
- component dualdatarate_flipflop is
- --1 clock, no CE, PRE for Lattice SCM
- generic(
- WIDTH : integer := 1
- );
- port(
- C0 : in std_logic;
- C1 : in std_logic;
- CE : in std_logic;
- CLR : in std_logic;
- D0 : in std_logic_vector(WIDTH-1 downto 0);
- D1 : in std_logic_vector(WIDTH-1 downto 0);
- PRE : in std_logic;
- Q : out std_logic_vector(WIDTH-1 downto 0)
- );
- end component;
-
- signal RECV_CLK, recv_clk_locked : std_logic;
- signal reg_RX_CLK, buf_RX_CLK, last_RX_CLK : std_logic;
- signal reg_RX_CTRL, buf_RX_CTRL : std_logic_vector(3 downto 0);
- signal reg_RX_DATA, buf_RX_DATA : std_logic_vector(15 downto 0);
-
- signal rx_datavalid : std_logic;
- signal rx_first_packet : std_logic;
- signal rx_reset : std_logic;
- signal rx_parity : std_logic;
- signal rx_parity_match : std_logic;
-
- signal rx_fifo_read_enable : std_logic;
- signal rx_fifo_write_enable, next_rx_fifo_write_enable: std_logic;
- signal rx_fifo_data_in, next_rx_fifo_data_in : std_logic_vector(17 downto 0);
- signal rx_fifo_data_out : std_logic_vector(17 downto 0);
- signal rx_fifo_full : std_logic;
- signal rx_fifo_empty : std_logic;
- signal rx_fifostatus_out : std_logic_vector(3 downto 0);
- signal rx_valid_read_out : std_logic;
- signal rx_almost_empty_out : std_logic;
- signal rx_almost_full_out : std_logic;
-
-
- signal buf_INT_DATAREADY_OUT : std_logic;
-
- signal rx_packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal wait_for_startup : std_logic;
- signal wait_for_startup_slow : std_logic;
- signal rx_CLK_counter : std_logic_vector(4 downto 0);
- signal rx_clock_detect : std_logic;
-
- signal med_reset : std_logic;
-
- signal tx_datavalid, tx_first_packet, tx_reset, tx_parity : std_logic;
- signal buf_INT_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal buf_INT_READ_OUT : std_logic;
- signal tx_clock_enable : std_logic;
- signal next_tx_reset : std_logic;
- signal buf_tx_reset : std_logic;
- signal buf_tx_clk : std_logic;
- signal recv_clk_real_locked : std_logic;
- signal locked_counter : std_logic_vector(19 downto 0);
-
- signal led_counter : std_logic_vector(18 downto 0);
- signal send_resync_counter : std_logic_vector(11 downto 0);
- signal send_resync : std_logic;
- signal rx_led, tx_led, link_led : std_logic;
- signal med_error : std_logic_vector(2 downto 0);
- signal trbnet_reset : std_logic;
-begin
-
-
---Transmitter (full speed only)
--------------------------
- INT_READ_OUT <= buf_INT_READ_OUT;
- buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset;
-
- TX_DATA_OUT <= buf_INT_DATA_IN;
- TX_CTRL_OUT(0) <= tx_datavalid;
- TX_CTRL_OUT(1) <= tx_first_packet;
- TX_CTRL_OUT(2) <= tx_reset;
- TX_CTRL_OUT(3) <= tx_parity;
-
- tx_clock_enable <= not RESET;
-
- next_tx_reset <= CTRL_OP(15) or (recv_clk_real_locked and wait_for_startup_slow);
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- TX_CLK_OUT <= buf_tx_clk;
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- tx_datavalid <= '0';
- tx_reset <= '1';
- buf_tx_reset <= '1';
- buf_INT_DATA_IN <= (others => '0');
- tx_first_packet <= '0';
- tx_parity <= '0';
- buf_tx_clk <= '0';
- else
- buf_INT_DATA_IN <= INT_DATA_IN;
- tx_datavalid <= INT_DATAREADY_IN and buf_INT_READ_OUT;
- if INT_PACKET_NUM_IN = c_H0 then
- tx_first_packet <= '1';
- else
- tx_first_packet <= '0';
- end if;
- tx_reset <= buf_tx_reset;
- buf_tx_reset <= next_tx_reset;
- tx_parity <= xor_all(INT_DATA_IN);
- buf_tx_clk <= not buf_tx_clk;
- end if;
- end if;
- end process;
-
-
-
---Receiver
--------------------------
- RECV_CLOCK_GEN : trb_net_clock_generator
- generic map(
- FREQUENCY_IN => 100.0,
- FREQUENCY_OUT => 200.0,
- CLOCK_MULT => 2,
- CLOCK_DIV => 1,
- CLKIN_DIVIDE_BY_2 => false,
- CLKIN_PERIOD => 10.0
- )
- port map(
- RESET => RESET,
- CLK_IN => CLK,
- CLK_OUT => RECV_CLK,
- LOCKED => recv_clk_locked
- );
-
-process(CLK)
- begin
- if rising_edge(CLK) then
- if recv_clk_locked = '0' then
- locked_counter <= (others => '0');
- recv_clk_real_locked <= '0';
- else
- if locked_counter /= x"0000F" then
- locked_counter <= locked_counter + 1;
- else
- recv_clk_real_locked <= '1';
- end if;
- end if;
- end if;
- end process;
-
- RX_INPUT_REG : process(RECV_CLK)
- begin
- if rising_edge(RECV_CLK) then
- reg_RX_CLK <= RX_CLK_IN;
- reg_RX_CTRL <= RX_CTRL_IN;
- reg_RX_DATA <= RX_DATA_IN;
- end if;
- end process;
-
- RX_REG : process(RECV_CLK, recv_clk_real_locked)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_real_locked = '0' then
- buf_RX_CTRL <= (others => '0');
- buf_RX_CLK <= '0';
- last_RX_CLK <= '0';
- buf_RX_DATA <= (others => '0');
- else
- buf_RX_CLK <= reg_RX_CLK;
- buf_RX_DATA <= reg_RX_DATA;
- buf_RX_CTRL <= reg_RX_CTRL;
- last_RX_CLK <= buf_RX_CLK;
- end if;
- end if;
- end process;
-
- rx_datavalid <= buf_RX_CTRL(0);
- rx_first_packet <= buf_RX_CTRL(1);
- rx_reset <= buf_RX_CTRL(2);
- rx_parity <= buf_RX_CTRL(3);
-
- rx_parity_match <= '1' when rx_parity = xor_all(buf_RX_DATA) else '0';
- next_rx_fifo_write_enable <= (buf_RX_CLK xor last_RX_CLK) and rx_datavalid;
- next_rx_fifo_data_in <= rx_first_packet & rx_parity_match & buf_RX_DATA;
-
- reg_fifo_in : process(RECV_CLK)
- begin
- if rising_edge(RECV_CLK) then
- rx_fifo_write_enable <= next_rx_fifo_write_enable;
- rx_fifo_data_in <= next_rx_fifo_data_in;
- end if;
- end process;
-
- RX_FIFO : trb_net_fifo_16bit_bram_dualport
- port map(
- read_clock_in => CLK,
- write_clock_in => RECV_CLK,
- read_enable_in => rx_fifo_read_enable,
- write_enable_in => rx_fifo_write_enable,
- fifo_gsr_in => med_reset,
- write_data_in => rx_fifo_data_in,
- read_data_out => rx_fifo_data_out,
- full_out => rx_fifo_full,
- empty_out => rx_fifo_empty,
- fifostatus_out => rx_fifostatus_out,
- valid_read_out => rx_valid_read_out,
- almost_empty_out => rx_almost_empty_out,
- almost_full_out => rx_almost_full_out
- );
-
- rx_fifo_read_enable <= INT_READ_IN;
-
- INT_DATA_OUT <= rx_fifo_data_out(15 downto 0);
- INT_PACKET_NUM_OUT <= rx_packet_counter;
- INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
-
- packet_counter_p : process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- rx_packet_counter <= "100";
- elsif buf_INT_DATAREADY_OUT = '1' then
- if rx_packet_counter = c_max_word_number then
- rx_packet_counter <= (others => '0');
- else
- rx_packet_counter <= rx_packet_counter + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- rx_dataready_p : process(CLK)
- begin
- if rising_edge(CLK) then
- if med_reset = '1' then
- buf_INT_DATAREADY_OUT <= '0';
- else
- buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty;
- end if;
- end if;
- end process;
-
-
---monitor link
--------------------------
- process(CLK)
- begin
- if rising_edge(CLK) then
- wait_for_startup_slow <= wait_for_startup;
- end if;
- end process;
-
- process(RECV_CLK, recv_clk_real_locked,med_reset)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_real_locked = '0' or med_reset = '1' or rx_clock_detect = '0' then
- wait_for_startup <= '1';
- elsif rx_reset = '1' and recv_clk_locked = '1' then
- wait_for_startup <= '0';
- end if;
- end if;
- end process;
-
-
- ERROR_OUT_gen : process(CLK)
- begin
- if rising_edge(CLK) then
- if recv_clk_real_locked = '0' or rx_clock_detect = '0' then
- med_error <= ERROR_NC;
- elsif (buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(16) = '0') then --Parity error
- med_error <= ERROR_ENCOD;
- elsif (rx_packet_counter /= "100" and buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(17) = '1') then
- med_error <= ERROR_FATAL; --Counter error
- else
- med_error <= ERROR_OK;
- end if;
- end if;
- end process;
-
-
- rx_clk_detect_counter: process (RECV_CLK, recv_clk_real_locked)
- begin
- if rising_edge(RECV_CLK) then
- if recv_clk_real_locked = '0' then
- rx_CLK_counter <= (others => '0');
- rx_clock_detect <= '0';
- elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then
- rx_CLK_counter <= (others => '0');
- rx_clock_detect <= '1';
- elsif rx_CLK_counter /= 31 then
- rx_CLK_counter <= rx_CLK_counter + 1;
- elsif rx_CLK_counter = 31 then
- rx_clock_detect <= '0';
- end if;
- end if;
- end process;
-
-
---STAT & CTRL Ports
--------------------------
-
---LED
- link_led <= rx_clock_detect and not wait_for_startup_slow;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if led_counter(18) = '1' then
- led_counter <= (others => '0');
- else
- led_counter <= led_counter + 1;
- end if;
- if rx_fifo_empty = '0' then
- rx_led <= '1';
- elsif led_counter(18) = '1' then
- rx_led <= '0';
- end if;
- if tx_datavalid = '1' then
- tx_led <= '1';
- elsif led_counter(18) = '1' then
- tx_led <= '0';
- end if;
- end if;
- end process;
-
-
- STAT_OP(2 downto 0) <= med_error;
- STAT_OP(8 downto 3) <= (others => '0');
- STAT_OP(9) <= link_led;
- STAT_OP(10) <= rx_led;
- STAT_OP(11) <= tx_led;
- STAT_OP(12) <= '0';
- STAT_OP(13) <= trbnet_reset;
- STAT_OP(14) <= rx_clock_detect;
- STAT_OP(15) <= '1' when rx_reset = '1' and wait_for_startup_slow = '0' else '0';
-
- STAT(12) <= rx_parity_match;
- STAT(11) <= RECV_CLK;
- STAT(10) <= recv_clk_real_locked;
- STAT(9) <= rx_reset;
- STAT(8) <= buf_RX_CLK xor last_RX_CLK;
- STAT(7) <= recv_clk_locked;
- STAT(6) <= wait_for_startup;
- STAT(5) <= rx_first_packet;
- STAT(4) <= buf_tx_clk; --not or_all(INT_PACKET_NUM_IN); --tx_first_packet;
- STAT(3) <= rx_datavalid;
- STAT(2) <= next_tx_reset;
- STAT(1) <= buf_RX_CLK;
-
- STAT(13) <= or_all(rx_fifostatus_out);
- STAT(14) <= rx_valid_read_out;
- STAT(15) <= rx_almost_empty_out;
- STAT(16) <= rx_almost_full_out;
- STAT(31 downto 17) <= (others => '0');
-
- med_reset <= RESET or send_resync;
- trbnet_reset <= rx_reset or not recv_clk_real_locked;
-
-
---detect resync
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- send_resync <= '0';
- send_resync_counter <= (others => '0');
- else
- if not (send_resync_counter = 0) then
- send_resync_counter <= send_resync_counter + 1;
- end if;
- if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then
- send_resync <= '1';
- send_resync_counter <= send_resync_counter + 1;
- end if;
- if send_resync_counter = x"00F" then
- send_resync <= '0';
- end if;
- end if;
- end if;
- end process;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-LIBRARY unisim;
-USE UNISIM.VComponents.all;
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-
-entity trb_net16_med_tlk is
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- TLK_CLK : in std_logic;
- TLK_ENABLE : out std_logic;
- TLK_LCKREFN : out std_logic;
- TLK_LOOPEN : out std_logic;
- TLK_PRBSEN : out std_logic;
- TLK_RXD : in std_logic_vector(15 downto 0);
- TLK_RX_CLK : in std_logic;
- TLK_RX_DV : in std_logic;
- TLK_RX_ER : in std_logic;
- TLK_TXD : out std_logic_vector(15 downto 0);
- TLK_TX_EN : out std_logic;
- TLK_TX_ER : out std_logic;
- SFP_LOS : in std_logic;
- SFP_TX_DIS : out std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_READ_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- STAT : out std_logic_vector (63 downto 0);
- STAT_MONITOR : out std_logic_vector ( 100 downto 0);
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0)
- --connect STAT(0) to LED
- );
-end trb_net16_med_tlk;
-
-architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is
-
- signal fifo_din_a : std_logic_vector(17 downto 0);
- signal fifo_dout_a : std_logic_vector(17 downto 0);
- signal fifo_wr_en_a : std_logic;
- signal fifo_rd_en_a : std_logic;
- signal fifo_empty_a : std_logic;
- signal fifo_full_a : std_logic;
- signal fifo_din_m : std_logic_vector(17 downto 0);
- signal fifo_dout_m : std_logic_vector(17 downto 0);
- signal fifo_rd_en_m : std_logic;
- signal fifo_wr_en_m : std_logic;
- signal fifo_empty_m : std_logic;
- signal fifo_full_m : std_logic;
- signal fifo_valid_read_m, fifo_valid_read_a : std_logic;
- signal fifo_almost_full_m, fifo_almost_full_a : std_logic;
- signal fifo_almost_empty_m, fifo_almost_empty_a : std_logic;
-
-
- signal fifo_reset : std_logic;
- signal fifo_status_a : std_logic_vector(3 downto 0);
- signal fifo_status_m : std_logic_vector(3 downto 0);
- signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal buf_MED_READ_OUT : std_logic;
- signal buf_MED_DATAREADY_OUT : std_logic;
- signal rx_allow : std_logic;
- signal tx_allow : std_logic;
- signal internal_reset : std_logic;
-
-
- signal reg_RXD : std_logic_vector(15 downto 0);
- signal reg_RX_DV : std_logic;
- signal reg_RX_ER : std_logic;
- signal reg_TXD : std_logic_vector(15 downto 0);
- signal reg_TX_EN : std_logic;
- signal reg_TX_ER : std_logic;
-
- signal TLK_CLK_neg : std_logic;
- signal CLK_FB_Out, FB_CLK : std_logic;
-
- type tlk_state_t is (RESETTING, WAIT_FOR_RX_LOCK, WAIT_FOR_TX_ALLOW, WORKING);
- signal current_state, next_state : tlk_state_t;
- signal next_tx_allow, next_rx_allow : std_logic:='1';
- signal counter, next_counter : std_logic_vector(28 downto 0);
- signal next_internal_reset : std_logic;
- signal buf_MED_ERROR_OUT, next_MED_ERROR_OUT : std_logic_vector(2 downto 0);
- signal state_bits : std_logic_vector(2 downto 0);
- signal counter_reset : std_logic;
-
- signal reg_SFP_LOS : std_logic;
-
- signal send_reset : std_logic;
- signal make_reset : std_logic;
- signal send_reset_counter : std_logic_vector(6 downto 0);
- signal send_reset_q : std_logic;
- signal make_reset_q : std_logic;
- signal sending_reset: std_logic;
-
- signal buf_RESET_TRBNET_OUT : std_logic;
-
- signal led_counter : std_logic_vector(18 downto 0);
- signal rx_led, tx_led, link_led : std_logic;
-
- signal comb_fifo_wr_en_a : std_logic;
- signal comb_fifo_din_a : std_logic_vector(17 downto 0);
-
-begin
-
- TLK_ENABLE <= not RESET;
- TLK_LCKREFN <= '1';
- TLK_PRBSEN <= '0';
- TLK_LOOPEN <= '0';
- SFP_TX_DIS <= RESET;
-
-
-
-
----------------------------------------------
---Receiver FIFO
----------------------------------------------
-
- FIFO_OPT_TO_MED: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map(
- read_clock_in => CLK,
- write_clock_in => TLK_RX_CLK,
- read_enable_in => fifo_rd_en_a,
- write_enable_in => fifo_wr_en_a,
- fifo_gsr_in => fifo_reset,
- write_data_in => fifo_din_a,
- read_data_out => fifo_dout_a,
- full_out => fifo_full_a,
- empty_out => fifo_empty_a,
- fifostatus_out => fifo_status_a,
- valid_read_out => fifo_valid_read_a,
- almost_empty_out=> fifo_almost_empty_a,
- almost_full_out => fifo_almost_full_a
- );
-
- fifo_rd_en_a <= rx_allow;
- fifo_reset <= internal_reset;
-
-
- buf_MED_READ_OUT <= tx_allow;
- buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_dout_a(17) and rx_allow;
-
-
- PROC_PACKET_COUNTER : process(CLK)
- begin
- if rising_edge(CLK) then
- if internal_reset = '1' or buf_RESET_TRBNET_OUT = '1' then
- buf_MED_PACKET_NUM_OUT <= c_H0;
- elsif buf_MED_DATAREADY_OUT = '1' then
- if buf_MED_PACKET_NUM_OUT = c_max_word_number then
- buf_MED_PACKET_NUM_OUT <= (others => '0');
- else
- buf_MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT + 1;
- end if;
- end if;
- end if;
- end process;
-
- REG_MED_OUTPUTS : process(CLK)
- begin
- if rising_edge(CLK) then
- MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT;
- MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT;
- MED_DATA_OUT <= fifo_dout_a(15 downto 0);
- MED_READ_OUT <= buf_MED_READ_OUT;
- end if;
- end process;
-
-
-
- REG_RX_FIFO_INPUTS : process(TLK_RX_CLK)
- begin
- if rising_edge(TLK_RX_CLK) then
- fifo_wr_en_a <= (reg_RX_DV and not reg_RX_ER) and rx_allow;
- fifo_din_a <= reg_RX_ER & reg_RX_DV & reg_RXD;
- end if;
- end process;
-
- SYNC_TLK_RX_INPUT : process(TLK_RX_CLK)
- begin
- if rising_edge(TLK_RX_CLK) then
- reg_RXD <= TLK_RXD;
- reg_RX_DV <= TLK_RX_DV;
- reg_RX_ER <= TLK_RX_ER;
- end if;
- end process;
-
-
-
----------------------------------------------
---Detect Reset (Error Propagation)
----------------------------------------------
-
-
- process(TLK_RX_CLK)
- begin
- if rising_edge(TLK_RX_CLK) then
- if RESET = '1' then
- send_reset_counter <= (others => '0');
- send_reset <= '0';
- make_reset <= '0';
- else
- if reg_RX_DV = '1' and reg_RX_ER = '1' and send_reset_counter(5) = '0' then
- send_reset_counter <= send_reset_counter + 1;
- elsif reg_RX_ER = '0' then
- send_reset_counter <= (others => '0');
- end if;
- if send_reset = '1' and reg_RX_ER = '0' then --do reset
- make_reset <= '1';
- send_reset <= '0';
- elsif send_reset_counter(5) = '1' and reg_RX_ER = '1' then --send reset
- send_reset <= '1';
- make_reset <= '0';
- else
- send_reset <= '0';
- make_reset <= '0';
- end if;
- end if;
- end if;
- end process;
-
- SYNC_SEND_RESET : signal_sync
- generic map(
- WIDTH => 2,
- DEPTH => 2
- )
- port map(
- RESET => RESET,
- CLK0 => CLK,
- CLK1 => CLK,
- D_IN(0) => send_reset,
- D_IN(1) => make_reset,
- D_OUT(0) => send_reset_q,
- D_OUT(1) => make_reset_q
- );
-
- SYNC_SENDING_RESET : signal_sync
- generic map(
- WIDTH => 1,
- DEPTH => 2
- )
- port map(
- RESET => RESET,
- CLK0 => TLK_CLK_neg,
- CLK1 => TLK_CLK_neg,
- D_IN(0) => CTRL_OP(15),
- D_OUT(0) => sending_reset
- );
-
-
- SYNC_SFP_LOS : signal_sync
- generic map(
- WIDTH => 1,
- DEPTH => 2
- )
- port map(
- RESET => RESET,
- CLK0 => CLK,
- CLK1 => CLK,
- D_IN(0) => SFP_LOS,
- D_OUT(0) => reg_SFP_LOS
- );
-
----------------------------------------------
---A DCM - not really used
----------------------------------------------
-
-U_DCM_Transmitter: DCM --no_sim--
- generic map( --no_sim--
- CLKIN_PERIOD => 10.00, -- 30.30ns--no_sim--
- STARTUP_WAIT => FALSE,--no_sim--
- PHASE_SHIFT => 0,--no_sim--
- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",--no_sim--
- CLKOUT_PHASE_SHIFT => "FIXED"--no_sim--
- )--no_sim--
- port map (--no_sim--
- CLKIN => TLK_CLK,--no_sim--
- CLKFB => FB_CLK,--no_sim--
- DSSEN => '0',--no_sim--
- PSINCDEC => '0',--no_sim--
- PSEN => '0',--no_sim--
- PSCLK => '0',--no_sim--
- RST => RESET,--no_sim--
- CLK0 => CLK_FB_Out, -- for feedback--no_sim--
- CLK90=> open,--no_sim--
- LOCKED => open--no_sim--
- );--no_sim--
---
-U0_BUFG: BUFG port map (I => CLK_FB_Out, O => TLK_CLK_neg);--no_sim--
-U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);--no_sim--
---sim--TLK_CLK_neg <= not TLK_CLK;
-
-
-
----------------------------------------------
---TX FIFO
----------------------------------------------
-
- FIFO_MED_TO_OPT: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map(
- read_clock_in => TLK_CLK_neg,
- write_clock_in => CLK,
- read_enable_in => fifo_rd_en_m,
- write_enable_in => fifo_wr_en_m,
- fifo_gsr_in => fifo_reset,
- write_data_in => fifo_din_m,
- read_data_out => fifo_dout_m,
- valid_read_out => fifo_valid_read_m,
- full_out => fifo_full_m,
- empty_out => fifo_empty_m,
- fifostatus_out => fifo_status_m,
- almost_empty_out=> fifo_almost_empty_m,
- almost_full_out => fifo_almost_full_m
- );
-
-
-
- REG_TLK_TX_OUT : process(TLK_CLK_neg)
- begin
- if rising_edge(TLK_CLK_neg) then
- TLK_TX_EN <= reg_TX_EN;
- TLK_TX_ER <= reg_TX_ER;
- TLK_TXD <= reg_TXD;
- end if;
- end process;
-
- REG_TLK_TX_buffers : process(TLK_CLK_neg)
- begin
- if rising_edge(TLK_CLK_neg) then
- reg_TXD <= fifo_dout_m(15 downto 0);
- reg_TX_ER <= sending_reset;
- reg_TX_EN <= (fifo_valid_read_m and fifo_dout_m(16)) or sending_reset;
- end if;
- end process;
-
- PROC_TX_FIFO_INPUT : process(CLK)
- begin
- if rising_edge(CLK) then
- fifo_wr_en_m <= (MED_DATAREADY_IN and buf_MED_READ_OUT);
- fifo_din_m <= MED_PACKET_NUM_IN(2) & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN;
- end if;
- end process;
-
- fifo_rd_en_m <= tx_allow;
-
-
-
-
-
----------------------------------------------
---Link State Machine
----------------------------------------------
-
- medium_states : process(current_state, tx_allow, rx_allow, internal_reset, MED_READ_IN,
- reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT, counter, make_reset_q)
- begin
- next_state <= current_state;
- next_tx_allow <= tx_allow;
- next_rx_allow <= rx_allow;
- next_internal_reset <= internal_reset;
- next_counter <= counter + 1;
- counter_reset <= reg_RX_ER and not reg_RX_DV;
- next_MED_ERROR_OUT <= buf_MED_ERROR_OUT;
-
- case current_state is
- when RESETTING =>
- next_MED_ERROR_OUT <= ERROR_NC;
- next_internal_reset <= '1';
- next_rx_allow <= '0';
- next_tx_allow <= '0';
- counter_reset <= '0';
- if counter(16) = '1' then
- counter_reset <= '1';
- next_state <= WAIT_FOR_RX_LOCK;
- next_internal_reset <= '0';
- end if;
- when WAIT_FOR_RX_LOCK =>
- next_internal_reset <= '0';
- if counter(28) = '1' then
- counter_reset <= '1';
- next_rx_allow <= '1';
- next_state <= WAIT_FOR_TX_ALLOW;
- end if;
- when WAIT_FOR_TX_ALLOW =>
- next_MED_ERROR_OUT <= ERROR_WAIT;
- next_internal_reset <= '0';
- if counter(28) = '1' then
- next_tx_allow <= '1';
- next_state <= WORKING;
- end if;
- when WORKING =>
- next_MED_ERROR_OUT <= ERROR_OK;
- next_tx_allow <= '1';
- next_rx_allow <= '1';
- next_internal_reset <= '0';
- end case;
- if reg_RX_ER = '1' and reg_RX_DV = '0' and internal_reset = '0' then
- next_rx_allow <= '0';
- next_tx_allow <= '0';
- next_state <= WAIT_FOR_RX_LOCK;
- next_MED_ERROR_OUT <= ERROR_WAIT;
- end if;
- if MED_READ_IN = '0' then
- next_MED_ERROR_OUT <= ERROR_NC;
- end if;
- if make_reset_q = '1' or reg_SFP_LOS = '1' then
- next_state <= RESETTING;
- next_MED_ERROR_OUT <= ERROR_NC;
- counter_reset <= '1';
- end if;
- end process;
-
- process(current_state)
- begin
- case current_state is
- when RESETTING => state_bits <= "000";
- when WAIT_FOR_RX_LOCK => state_bits <= "001";
- when WAIT_FOR_TX_ALLOW => state_bits <= "011";
- when WORKING => state_bits <= "100";
- when others => state_bits <= "111";
- end case;
- end process;
-
-
-
- states_reg : process(CLK)
- begin
- if rising_edge(CLK) then
- tx_allow <= next_tx_allow;
- rx_allow <= next_rx_allow;
- end if;
- end process;
-
- states_reg_counter : process(CLK)
- begin
- if rising_edge(CLK) then
- if counter_reset = '1' then
- counter <= (others => '0');
- else
- counter <= next_counter;
- end if;
- end if;
- end process;
-
- states_reg_2 : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_state <= RESETTING;--no_sim--
---sim-- current_state <= WORKING;
- internal_reset <= '1';
- buf_MED_ERROR_OUT <= ERROR_NC;
- else
- current_state <= next_state;
- internal_reset <= next_internal_reset;
- buf_MED_ERROR_OUT <= next_MED_ERROR_OUT;
- end if;
- end if;
- end process;
-
-
-
-
-
----------------------------------------------
---STAT_OP & LED
----------------------------------------------
- process(CLK)
- begin
- if rising_edge(CLK) then
- if led_counter(18) = '1' then
- led_counter <= (others => '0');
- else
- led_counter <= led_counter + 1;
- end if;
- if buf_med_dataready_out = '1' then
- rx_led <= '1';
- elsif led_counter(18) = '1' then
- rx_led <= '0';
- end if;
-
- if MED_DATAREADY_IN = '1' then
- tx_led <= '1';
- elsif led_counter(18) = '1' then
- tx_led <= '0';
- end if;
-
- end if;
- end process;
-
- link_led <= (counter(24) or tx_allow) and not reg_sfp_los;
-
- stat_op(2 downto 0) <= buf_MED_ERROR_OUT;
- stat_op(8 downto 3) <= (others => '0'); -- unused
- stat_op(9) <= link_led;
- stat_op(10) <= rx_led; --rx led
- stat_op(11) <= tx_led; --tx led
- stat_op(12) <= '0'; -- unused
- stat_op(13) <= make_reset_q;
- stat_op(14) <= reg_SFP_LOS or make_reset_q; -- reset out
- stat_op(15) <= send_reset_q; -- protocol error
-
----------------------------------------------
---Debugging
----------------------------------------------
-
-
- STAT(0) <= counter(24) or tx_allow;
- STAT(1) <= rx_allow;
- STAT(2) <= tx_allow;
- STAT(3) <= fifo_wr_en_a;
- STAT(4) <= fifo_rd_en_a;
- STAT(5) <= fifo_empty_a;
- STAT(6) <= fifo_rd_en_m;
- STAT(7) <= fifo_empty_m;
- STAT(8) <= fifo_full_a;
- STAT(9) <= fifo_full_m;
- STAT(10)<= fifo_dout_m(14);
- STAT(11)<= fifo_dout_a(14);
- STAT(12)<= fifo_din_a(14);
--- STAT(11)<= last_fifo_rd_en_a;
- STAT(13) <= internal_reset;
- STAT(14) <= reg_RX_DV;
- STAT(15) <= reg_RX_ER;
- STAT(31 downto 16) <= reg_RXD;
- STAT(32) <= fifo_valid_read_m;
- STAT(33) <= fifo_valid_read_a;
- STAT(36 downto 34) <= state_bits;
- STAT(40 downto 37) <= fifo_status_a;
- STAT(44 downto 41) <= fifo_status_m;
- STAT(48 downto 45) <= fifo_dout_m(3 downto 0);
- STAT(50 downto 49) <= fifo_dout_m(17 downto 16);
- STAT(54 downto 51) <= fifo_din_a(3 downto 0);
- STAT(56 downto 55) <= fifo_din_a(17 downto 16);
- STAT(57) <= make_reset;
- STAT(58) <= send_reset;
- STAT(59) <= TLK_CLK_neg;
- STAT(60) <= fifo_wr_en_m;
- STAT(63 downto 61) <= send_reset_counter(2 downto 0);
- --STAT(63 downto 57) <= (others => '0');
-
- STAT_MONITOR(17 downto 0) <= fifo_din_a;
- STAT_MONITOR(18) <= fifo_almost_full_m;
- STAT_MONITOR(19) <= fifo_almost_full_a;
- STAT_MONITOR(20) <= fifo_almost_empty_m;
- STAT_MONITOR(21) <= fifo_almost_empty_a;
- STAT_MONITOR(37 downto 22) <= CTRL_OP;
- STAT_MONITOR(45 downto 38) <= (others => '0');
- STAT_MONITOR(46) <= reg_TX_ER;
- STAT_MONITOR(47) <= reg_TX_EN;
- STAT_MONITOR(63 downto 48) <= reg_TXD;
- STAT_MONITOR(81 downto 64) <= fifo_din_a; -- RX_ER & RX_DV & RX_DATA
- STAT_MONITOR(88 downto 82) <= send_reset_counter;
- STAT_MONITOR(100 downto 89) <= (others => '0');
-
-
-
-
-end architecture;
+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
---use work.trb_net_components.all;\r
-\r
-entity trb_net16_rx_packets is\r
-port(\r
- -- Resets\r
- RESET_IN : in std_logic;\r
- QUAD_RST_IN : in std_logic;\r
- -- data stream from SerDes\r
- CLK_IN : in std_logic; -- SerDes RX clock\r
- RX_ALLOW_IN : in std_logic;\r
- RX_DATA_IN : in std_logic_vector(7 downto 0);\r
- RX_K_IN : in std_logic;\r
- -- media interface\r
- SYSCLK_IN : in std_logic; -- 100MHz master clock\r
- MED_DATA_OUT : out std_logic_vector(15 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
- MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);\r
- -- reset handling\r
- SEND_RESET_WORDS_OUT : out std_logic;\r
- MAKE_TRBNET_RESET_OUT : out std_logic;\r
- -- Status signals\r
- PACKET_TIMEOUT_OUT : out std_logic;\r
- -- Debug signals\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
-);\r
-end entity trb_net16_rx_packets;\r
-\r
-\r
-architecture behavioral of trb_net16_rx_packets is\r
-\r
--- components\r
-component trb_net_fifo_8bit_16bit_bram_dualport is\r
-port(\r
- READ_CLOCK_IN : in std_logic;\r
- WRITE_CLOCK_IN : in std_logic;\r
- READ_ENABLE_IN : in std_logic;\r
- WRITE_ENABLE_IN : in std_logic;\r
- FIFO_GSR_IN : in std_logic;\r
- WRITE_DATA_IN : in std_logic_vector(7 downto 0);\r
- READ_DATA_OUT : out std_logic_vector(15 downto 0);\r
- FULL_OUT : out std_logic;\r
- EMPTY_OUT : out std_logic;\r
- WCNT_OUT : out std_logic_vector(9 downto 0);\r
- RCNT_OUT : out std_logic_vector(8 downto 0)\r
-);\r
-end component trb_net_fifo_8bit_16bit_bram_dualport;\r
-\r
--- State description:\r
---\r
--- IDLE: wait for any data to be written into the FIFO\r
--- RD1 : first word prefetch\r
--- RD2 : first word output reg, second word prefetch, wait state for full packet in FIFO\r
--- RDI : generates initial dataready_out, wait state for handshake of first data word\r
--- RD3 : second word output reg, third word prefetch, wait state for handshake of second data word\r
--- RD4 : third word output reg, fourth word prefetch, wait state for handshake of third data word\r
--- RD5 : fourth word output reg, fifth word prefetch, wait state for handshake of forth data word\r
--- => decision: continous data stream or stalling as FIFO runs empty!\r
--- RDO : fifth word output reg, wait state for handshake of fifth data word, can also resume transmission\r
--- if new data is available in FIFO\r
--- RDW : fifth word output reg, first word prefetch, wait state for handshake of fifth data word,\r
--- continue data stream or stall if for complete packet\r
-\r
--- state declarations\r
-type STATES is (IDLE, RD1, RD2, RDI, RD3, RD4, RD5, RDO, RDW, TOC, CLEAN);\r
-signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
--- normal signals\r
-signal bsm_x : std_logic_vector(3 downto 0);\r
-signal bsm : std_logic_vector(3 downto 0);\r
-signal update_x : std_logic;\r
-signal med_dataready_x : std_logic;\r
-signal med_dataready : std_logic;\r
-signal med_data : std_logic_vector(15 downto 0);\r
-\r
-signal buf_rx_data : std_logic_vector(7 downto 0);\r
-signal buf_rx_k : std_logic;\r
-\r
-signal fifo_wr_en : std_logic;\r
-signal fifo_rd_en_x : std_logic;\r
-signal fifo_wr_data : std_logic_vector(7 downto 0);\r
-signal fifo_rd_data : std_logic_vector(15 downto 0);\r
-signal fifo_reset : std_logic;\r
-signal fifo_rcnt_stdlv : std_logic_vector(8 downto 0);\r
-signal fifo_rcnt : unsigned(8 downto 0);\r
-signal fifo_rst_x : std_logic;\r
-signal fifo_rst : std_logic;\r
-\r
-signal rx_counter : unsigned(2 downto 0);\r
-\r
-signal is_idle_word : std_logic;\r
-signal rx_starting : std_logic;\r
-signal send_reset_words : std_logic;\r
-signal make_trbnet_reset : std_logic;\r
-signal reset_word_cnt : unsigned(4 downto 0);\r
-\r
-signal timeout_ctr : unsigned(9 downto 0);\r
-signal rst_toc_x : std_logic;\r
-signal rst_toc : std_logic;\r
-signal ce_toc_x : std_logic;\r
-signal ce_toc : std_logic;\r
-signal toc_done_x : std_logic;\r
-signal toc_done : std_logic;\r
-\r
-signal debug : std_logic_vector(15 downto 0);\r
-\r
-begin\r
-\r
-----------------------------------------------------------------------\r
--- FIFO write process\r
-----------------------------------------------------------------------\r
-THE_WRITE_RX_FIFO_PROC: process( CLK_IN )\r
-begin\r
- if( rising_edge(CLK_IN) ) then\r
- buf_rx_data <= RX_DATA_IN;\r
- buf_rx_k <= RX_K_IN;\r
- if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then\r
- fifo_wr_en <= '0';\r
- is_idle_word <= '1';\r
- rx_starting <= '1';\r
- else\r
- fifo_wr_data <= buf_rx_data;\r
- if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then\r
- fifo_wr_en <= '1';\r
- else\r
- fifo_wr_en <= '0';\r
- end if;\r
- if ( buf_rx_k = '1' ) then\r
- is_idle_word <= '1';\r
- rx_starting <= '0';\r
- elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then\r
- is_idle_word <= '0';\r
- end if;\r
- end if;\r
- end if;\r
-end process THE_WRITE_RX_FIFO_PROC;\r
-\r
-----------------------------------------------------------------------\r
--- TRBnet reset handling\r
-----------------------------------------------------------------------\r
-THE_CNT_RESET_PROC: process( CLK_IN )\r
-begin\r
- if( rising_edge(CLK_IN) ) then\r
- if( RESET_IN = '1' ) then\r
- send_reset_words <= '0';\r
- make_trbnet_reset <= '0';\r
- reset_word_cnt <= (others => '0');\r
- else\r
- send_reset_words <= '0';\r
- make_trbnet_reset <= '0';\r
- if( (buf_rx_data = x"FE") and (buf_rx_k = '1') ) then\r
- if( reset_word_cnt(4) = '0' ) then\r
- reset_word_cnt <= reset_word_cnt + 1;\r
- else\r
- send_reset_words <= '1';\r
- end if;\r
- else\r
- reset_word_cnt <= (others => '0');\r
- make_trbnet_reset <= reset_word_cnt(4);\r
- end if;\r
- end if;\r
- end if;\r
-end process;\r
-\r
-----------------------------------------------------------------------\r
--- the RX FIFO itself\r
-----------------------------------------------------------------------\r
-THE_RX_FIFO: trb_net_fifo_8bit_16bit_bram_dualport\r
-port map(\r
- READ_CLOCK_IN => SYSCLK_IN,\r
- WRITE_CLOCK_IN => CLK_IN,\r
- READ_ENABLE_IN => fifo_rd_en_x,\r
- WRITE_ENABLE_IN => fifo_wr_en,\r
- FIFO_GSR_IN => fifo_reset,\r
- WRITE_DATA_IN => fifo_wr_data,\r
- READ_DATA_OUT => fifo_rd_data,\r
- FULL_OUT => open,\r
- EMPTY_OUT => open,\r
- WCNT_OUT => open, -- not needed\r
- RCNT_OUT => fifo_rcnt_stdlv\r
-);\r
-\r
-fifo_reset <= RESET_IN or QUAD_RST_IN or not RX_ALLOW_IN or fifo_rst;\r
-\r
-fifo_rcnt <= unsigned(fifo_rcnt_stdlv);\r
-\r
-----------------------------------------------------------------------\r
--- RX packet state machine\r
-----------------------------------------------------------------------\r
--- state registers\r
-STATE_MEM: process( SYSCLK_IN )\r
-begin\r
- if( rising_edge(SYSCLK_IN) ) then\r
- if( RESET_IN = '1' ) then\r
- CURRENT_STATE <= IDLE;\r
- med_dataready <= '0';\r
- ce_toc <= '0';\r
- rst_toc <= '0';\r
- fifo_rst <= '0';\r
- bsm <= (others => '0');\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- med_dataready <= med_dataready_x;\r
- ce_toc <= ce_toc_x;\r
- rst_toc <= rst_toc_x;\r
- fifo_rst <= fifo_rst_x;\r
- bsm <= bsm_x;\r
- end if;\r
- end if;\r
-end process STATE_MEM;\r
-\r
--- state transitions\r
-STATE_TRANSFORM: process( CURRENT_STATE, fifo_rcnt, MED_READ_IN, med_dataready, toc_done )\r
-begin\r
- NEXT_STATE <= IDLE; -- avoid latches\r
- fifo_rd_en_x <= '0';\r
- med_dataready_x <= '0';\r
- update_x <= '0';\r
- ce_toc_x <= '0';\r
- rst_toc_x <= '0';\r
- fifo_rst_x <= '0';\r
- case CURRENT_STATE is\r
- when IDLE => if( fifo_rcnt > 0 ) then\r
- -- we have at least one data word in FIFO, so we prefetch it\r
- NEXT_STATE <= RD1;\r
- fifo_rd_en_x <= '1';\r
- ce_toc_x <= '1';\r
- else\r
- NEXT_STATE <= IDLE;\r
- end if;\r
- when RD1 => if ( fifo_rcnt > 1 ) then -- was 0\r
- -- second data word is available in FIFO, so we prefetch it and\r
- -- forward the first word to the output register\r
- NEXT_STATE <= RD2;\r
- fifo_rd_en_x <= '1';\r
- update_x <= '1';\r
- ce_toc_x <= '1';\r
- elsif( toc_done = '1' ) then\r
- NEXT_STATE <= TOC;\r
- rst_toc_x <= '1';\r
- fifo_rst_x <= '1';\r
- else\r
- NEXT_STATE <= RD1;\r
- ce_toc_x <= '1';\r
- end if;\r
- when RD2 => if ( fifo_rcnt > 2 ) then\r
- -- at least all three missing words in FIFO... so we go ahead and notify full packet availability\r
- NEXT_STATE <= RDI;\r
- med_dataready_x <= '1';\r
- rst_toc_x <= '1';\r
- elsif( toc_done = '1' ) then\r
- NEXT_STATE <= TOC;\r
- rst_toc_x <= '1';\r
- fifo_rst_x <= '1';\r
- else\r
- NEXT_STATE <= RD2;\r
- ce_toc_x <= '1';\r
- end if;\r
- when RDI => med_dataready_x <= '1';\r
- if( MED_READ_IN = '1' ) then\r
- -- first word of packet has been transfered, update output register and prefetch next data word\r
- NEXT_STATE <= RD3;\r
- fifo_rd_en_x <= '1';\r
- update_x <= '1';\r
- else\r
- NEXT_STATE <= RDI;\r
- end if;\r
- when RD3 => med_dataready_x <= '1';\r
- if( MED_READ_IN = '1' ) then\r
- -- second word of packet has been transfered, update output register and prefetch next data word\r
- NEXT_STATE <= RD4;\r
- fifo_rd_en_x <= '1';\r
- update_x <= '1';\r
- else\r
- NEXT_STATE <= RD3;\r
- end if;\r
- when RD4 => med_dataready_x <= '1';\r
- -- third word of packet has been transfered, update output register and prefetch next data word\r
- if( MED_READ_IN = '1' ) then\r
- NEXT_STATE <= RD5;\r
- fifo_rd_en_x <= '1';\r
- update_x <= '1';\r
- else\r
- NEXT_STATE <= RD4;\r
- end if;\r
- when RD5 => med_dataready_x <= '1';\r
- -- DANGER. This is the key state for decisions here.\r
- -- There are many ways to do it the wrong way, depending on the FIFO fill level.\r
- if ( (MED_READ_IN = '1') and (fifo_rcnt < 3) ) then -- was 2, changed due to RCNT latency\r
- -- fourth word of packet has been transfered, and FIFO has not seen any new packet word.\r
- -- so we update output register only, no prefetch\r
- NEXT_STATE <= RDO;\r
- update_x <= '1';\r
- elsif( (MED_READ_IN = '1') and (fifo_rcnt > 2) ) then -- was 1, changed due to RCNT latency\r
- -- fourth word of packet DONE, new packet data already in the FIFO\r
- -- so we can prefetch on data word already and update the output register\r
- NEXT_STATE <= RDW;\r
- fifo_rd_en_x <= '1';\r
- update_x <= '1';\r
- else\r
- NEXT_STATE <= RD5;\r
- end if;\r
- when RDO => if ( (MED_READ_IN = '1') and (fifo_rcnt = 0) ) then\r
- -- last word of packet has been transfered, and no new data words to handle.\r
- -- we keep the last transfered word in the output register and wait for new packets to arrive.\r
- NEXT_STATE <= IDLE;\r
- elsif( (MED_READ_IN = '1') and (fifo_rcnt > 0) ) then\r
- -- last word of packet has been transfered, and a new packet data available.\r
- -- so we enter the prefetch phase again.\r
- NEXT_STATE <= RD1;\r
- fifo_rd_en_x <= '1';\r
- else\r
- NEXT_STATE <= RDO;\r
- med_dataready_x <= '1';\r
- end if;\r
- when RDW => if ( (MED_READ_IN = '1') and (fifo_rcnt > 3) ) then\r
- -- last word of packet has been transfered, complete packet in FIFO, so we can go ahead.\r
- NEXT_STATE <= RDI;\r
- fifo_rd_en_x <= '1';\r
- update_x <= '1';\r
- med_dataready_x <= '1';\r
- elsif( (MED_READ_IN = '1') and (fifo_rcnt < 4 ) ) then\r
- -- last word of packet has been transfered, but new packet not complete yet.\r
- NEXT_STATE <= RD2;\r
- fifo_rd_en_x <= '1';\r
- update_x <= '1';\r
- else\r
- NEXT_STATE <= RDW;\r
- med_dataready_x <= '1';\r
- end if;\r
- when TOC => NEXT_STATE <= CLEAN;\r
- fifo_rst_x <= '1';\r
- when CLEAN => NEXT_STATE <= IDLE;\r
-\r
- when others => NEXT_STATE <= IDLE;\r
- end case;\r
-end process STATE_TRANSFORM;\r
-\r
--- just for debugging\r
-THE_DECODE_PROC: process( NEXT_STATE )\r
-begin\r
- case NEXT_STATE is\r
- when IDLE => bsm_x <= x"0";\r
- when RD1 => bsm_x <= x"1";\r
- when RD2 => bsm_x <= x"2";\r
- when RDI => bsm_x <= x"3";\r
- when RD3 => bsm_x <= x"4";\r
- when RD4 => bsm_x <= x"5";\r
- when RD5 => bsm_x <= x"6";\r
- when RDO => bsm_x <= x"7";\r
- when RDW => bsm_x <= x"8";\r
- when TOC => bsm_x <= x"9";\r
- when CLEAN => bsm_x <= x"a";\r
- when others => bsm_x <= x"f";\r
- end case;\r
-end process THE_DECODE_PROC;\r
-\r
-THE_SYNC_PROC: process( SYSCLK_IN )\r
-begin\r
- if( rising_edge(SYSCLK_IN) ) then\r
- if( update_x = '1' ) then\r
- med_data <= fifo_rd_data;\r
- end if;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
-----------------------------------------------------------------------\r
--- RX packet counter\r
-----------------------------------------------------------------------\r
-THE_RX_PACKETS_PROC: process( SYSCLK_IN )\r
-begin\r
- if( rising_edge(SYSCLK_IN) ) then\r
- if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then\r
- rx_counter <= unsigned(c_H0);\r
- else\r
- if( (med_dataready = '1') and (MED_READ_IN = '1') ) then -- modified\r
- if( rx_counter = unsigned(c_max_word_number) ) then\r
- rx_counter <= (others => '0');\r
- else\r
- rx_counter <= rx_counter + 1;\r
- end if;\r
- end if;\r
- end if;\r
- end if;\r
-end process THE_RX_PACKETS_PROC;\r
-\r
-----------------------------------------------------------------------\r
--- Timeout counter\r
-----------------------------------------------------------------------\r
-THE_TOC_PROC: process( SYSCLK_IN )\r
-begin\r
- if( rising_edge(SYSCLK_IN) ) then\r
- toc_done <= toc_done_x;\r
- if ( (RESET_IN = '1') or (rst_toc = '1') ) then\r
- timeout_ctr <= (others => '0');\r
- elsif( (ce_toc = '1') and (toc_done = '0') ) then\r
- timeout_ctr <= timeout_ctr + 1;\r
- end if;\r
- end if;\r
-end process THE_TOC_PROC;\r
-\r
-toc_done_x <= '1' when ( timeout_ctr(9 downto 2) = b"11_1111_11" ) else '0';\r
-\r
-----------------------------------------------------------------------\r
--- Debug signals\r
-----------------------------------------------------------------------\r
-debug(15 downto 13) <= (others => '0');\r
-debug(12 downto 4) <= fifo_rcnt_stdlv;\r
-debug(3) <= toc_done;\r
-debug(2) <= ce_toc;\r
-debug(1) <= rst_toc;\r
-debug(0) <= fifo_rst;\r
-\r
---debug(15 downto 8) <= fifo_rcnt_stdlv(7 downto 0);\r
---debug(7 downto 2) <= (others => '0');\r
---debug(1) <= update_x;\r
---debug(0) <= fifo_rd_en_x;\r
-\r
-----------------------------------------------------------------------\r
--- Output signals\r
-----------------------------------------------------------------------\r
-SEND_RESET_WORDS_OUT <= send_reset_words;\r
-MAKE_TRBNET_RESET_OUT <= make_trbnet_reset;\r
-PACKET_TIMEOUT_OUT <= fifo_rst;\r
-\r
-MED_DATAREADY_OUT <= med_dataready;\r
-MED_DATA_OUT <= med_data;\r
-MED_PACKET_NUM_OUT <= std_logic_vector(rx_counter);\r
-\r
-BSM_OUT <= bsm;\r
-DBG_OUT <= debug;\r
-\r
-end behavioral;
\ No newline at end of file
+++ /dev/null
-
------------------------------------
---D18 data structure
--- XXXXXXXX0+++++++ 00
--- 1+++++++2+++++++ 01
--- 3+++++++4+++++++ 10
--- 5+++++++6+++++++ 11
-------------------------------------
---X unused, / error+parity, + data
-------------------------------------
-
-
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_18_to_16_converter is
- generic ( VERSION : integer := 0); --Version of included sbufs
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- D18_DATAREADY_IN: in STD_LOGIC;
- D18_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0);
- D18_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word
- D18_READ_OUT: out STD_LOGIC;
-
- D16_DATAREADY_OUT: out STD_LOGIC;
- D16_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word
- D16_READ_IN: in STD_LOGIC;
- D16_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(1 downto 0);
-
- D18_DATAREADY_OUT: out STD_LOGIC;
- D18_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(1 downto 0);
- D18_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word
- D18_READ_IN: in STD_LOGIC;
-
- D16_DATAREADY_IN: in STD_LOGIC;
- D16_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word
- D16_READ_OUT: out STD_LOGIC;
- D16_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0)
- );
-end entity;
-
-architecture trb_net_18_to_16_converter_arch of trb_net_18_to_16_converter is
- component trb_net_sbuf
- generic (DATA_WIDTH : integer := 16;
- VERSION: integer := 0);
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- -- the COMB_next_READ_OUT should be connected via comb. logic to a register
- -- to provide COMB_READ_IN (feedback path with 1 cycle delay)
- -- The "REAL" READ_OUT can be constructed in the comb via COMB_next_READ_
- -- OUT and the READ_IN: If one of these is ='1', no problem to read in next
- -- step.
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- -- Port to synchronous output.
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
-signal dbuf18_comb_dataready_in : std_logic;
-signal dbuf18_next_read_out : std_logic;
-signal dbuf18_comb_read_in : std_logic;
-signal dbuf18_comb_data_in, buf_D16_DATA_OUT : std_logic_vector(17 downto 0);
-signal dbuf18_status : std_logic_vector(31 downto 0);
-signal buffer_dbuf18_comb_data_in : std_logic_vector(7 downto 0);
-signal next_buffer_dbuf18_comb_data_in : std_logic_vector(7 downto 0);
-signal next_buf_D18_READ_OUT, buf_D18_READ_OUT : std_logic;
-signal D18_PACKET4, last_D18_PACKET4 : std_logic;
-
-
-signal dbuf16_comb_dataready_in : std_logic;
-signal dbuf16_next_read_out : std_logic;
-signal dbuf16_comb_read_in : std_logic;
-signal dbuf16_comb_data_in, buf_D18_data_out : std_logic_vector(17 downto 0);
-signal dbuf16_status : std_logic_vector(31 downto 0);
-signal buffer_dbuf16_comb_data_in : std_logic_vector(7 downto 0);
-signal next_buffer_dbuf16_comb_data_in : std_logic_vector(7 downto 0);
-signal next_buf_D16_READ_OUT, buf_D16_READ_OUT : std_logic;
-signal D16_packet, next_D16_packet : std_logic_vector(1 downto 0);
-signal last_dbuf18_next_read_out : std_logic;
-
-
-begin
-
------------------------------------------------------------
---Direction 18 to 16
------------------------------------------------------------
-
-
-
-next_buf_D18_READ_OUT <= dbuf18_next_read_out;--and not D18_PACKET4;
-D18_READ_OUT <= buf_D18_READ_OUT;
-
- D18to16 : process(buffer_dbuf18_comb_data_in, dbuf18_comb_data_in, last_D18_PACKET4,
- buf_D18_READ_OUT, D18_DATAREADY_IN, D18_PACKET_NUM_IN, D18_DATA_IN,
- last_dbuf18_next_read_out)
- variable newdata : std_logic;
- begin
- dbuf18_comb_dataready_in <= '0';
- next_buffer_dbuf18_comb_data_in <= buffer_dbuf18_comb_data_in;
- dbuf18_comb_data_in <= dbuf18_comb_data_in;
- D18_PACKET4 <= '0';
-
-
- if buf_D18_READ_OUT = '1' and D18_DATAREADY_IN = '1' then
- newdata := '1';
- else
- newdata := '0';
- end if;
-
-
- if ((D18_PACKET_NUM_IN /= "00" and newdata = '1') or last_D18_PACKET4 = '1') then
- dbuf18_comb_dataready_in <= '1';
- end if;
-
-
- if newdata = '1' and D18_PACKET_NUM_IN /= "00" then
- dbuf18_comb_data_in(7 downto 0) <= D18_DATA_IN(15 downto 8);
- else
- dbuf18_comb_data_in(7 downto 0) <= D18_DATA_IN(15 downto 8);--(others => '0');
- end if;
-
- if newdata = '1' or last_D18_PACKET4 = '1' then
- dbuf18_comb_data_in(15 downto 8) <= buffer_dbuf18_comb_data_in(7 downto 0);
- if last_D18_PACKET4 = '0' then
- dbuf18_comb_data_in(17 downto 16) <= D18_PACKET_NUM_IN - 1;
- else
- dbuf18_comb_data_in(17 downto 16) <= "11";
- end if;
- else
- dbuf18_comb_data_in(15 downto 8) <= (others => '0');
- dbuf18_comb_data_in(17 downto 16) <= "00";
- end if;
-
-
- if (D18_PACKET_NUM_IN = "11" and newdata = '1') or (last_D18_PACKET4 = '1' and last_dbuf18_next_read_out = '0') then
- D18_PACKET4 <= '1';
- end if;
-
- if newdata = '1' then
- next_buffer_dbuf18_comb_data_in <= D18_DATA_IN(7 downto 0);
- end if;
-
-
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- buffer_dbuf18_comb_data_in <= (others => '0');
- last_D18_PACKET4 <= '0';
- buf_D18_READ_OUT <= '0';
- last_dbuf18_next_read_out <= '0';
- else
- buffer_dbuf18_comb_data_in <= next_buffer_dbuf18_comb_data_in;
- last_D18_PACKET4 <= D18_PACKET4;
- buf_D18_READ_OUT <= next_buf_D18_READ_OUT;
- last_dbuf18_next_read_out <= dbuf18_next_read_out;
- end if;
- end if;
- end process;
-
-
- DBUF18 : trb_net_sbuf --dbuf from 18Bit to 16Bit
- generic map(DATA_WIDTH => 18, VERSION => VERSION)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => dbuf18_comb_dataready_in,
- COMB_next_READ_OUT => dbuf18_next_read_out,
- COMB_READ_IN => last_dbuf18_next_read_out,
- COMB_DATA_IN => dbuf18_comb_data_in,
- -- Port to synchronous output.
- SYN_DATAREADY_OUT => D16_DATAREADY_OUT,
- SYN_DATA_OUT => buf_D16_DATA_OUT,
- SYN_READ_IN => D16_READ_IN,
- -- Status and control port
- STAT_BUFFER => dbuf18_status(0)
- );
-
-D16_DATA_OUT <= buf_D16_DATA_OUT(15 downto 0);
-D16_PACKET_NUM_OUT <= buf_D16_DATA_OUT(17 downto 16);
-
-
-
-
------------------------------------------------------------
---Direction 16 to 18
------------------------------------------------------------
-
-next_buf_D16_READ_OUT <= dbuf16_next_read_out;
-D16_READ_OUT <= buf_D16_READ_OUT;
-dbuf16_comb_data_in(15 downto 8) <= (others => '0');
- D16to18 : process(buffer_dbuf16_comb_data_in, dbuf16_comb_data_in,
- buf_D16_READ_OUT, D16_DATAREADY_IN, D16_DATA_IN, D16_PACKET_NUM_IN)
- variable newdata : std_logic;
- begin
-
- if buf_D16_READ_OUT = '1' and D16_DATAREADY_IN = '1' then
- newdata := '1';
- else
- newdata := '0';
- end if;
-
- dbuf16_comb_dataready_in <= newdata;
- --next_buffer_dbuf16_comb_data_in <= buffer_dbuf16_comb_data_in;
- --dbuf16_comb_data_in <= dbuf16_comb_data_in;
-
- dbuf16_comb_data_in(17 downto 16) <= D16_PACKET_NUM_IN;
-
- if newdata = '1' then
- dbuf16_comb_data_in(7 downto 0) <= D16_DATA_IN(15 downto 8);
- else
- dbuf16_comb_data_in(7 downto 0) <= (others => '0');
- end if;
-
- if newdata = '1' then
- if D16_PACKET_NUM_IN = "11" then
- next_buffer_dbuf16_comb_data_in <= (others => '0');
- else
- next_buffer_dbuf16_comb_data_in <= D16_DATA_IN(7 downto 0);
- end if;
- else
- next_buffer_dbuf16_comb_data_in <= buffer_dbuf16_comb_data_in;
- end if;
- end process;
-
- process(CLK, RESET)
- begin
- if RESET = '1' then
- buffer_dbuf16_comb_data_in <= (others => '0');
- --D16_packet <= "00";
- buf_D16_READ_OUT <= '0';
- elsif rising_edge(CLK) then
- buffer_dbuf16_comb_data_in <= next_buffer_dbuf16_comb_data_in;
- --D16_packet <= next_D16_packet;
- buf_D16_READ_OUT <= next_buf_D16_READ_OUT;
- else
- buffer_dbuf16_comb_data_in <= buffer_dbuf16_comb_data_in;
- --D16_packet <= D16_packet;
- buf_D16_READ_OUT <= buf_D16_READ_OUT;
- end if;
- end process;
-
-
- DBUF16 : trb_net_sbuf --dbuf from 16Bit to 18Bit
- generic map(DATA_WIDTH => 18, VERSION => VERSION)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => dbuf16_comb_dataready_in,
- COMB_next_READ_OUT => dbuf16_next_read_out,
- COMB_READ_IN => dbuf16_comb_read_in,
- COMB_DATA_IN => dbuf16_comb_data_in,
- -- Port to synchronous output.
- SYN_DATAREADY_OUT => D18_DATAREADY_OUT,
- SYN_DATA_OUT => buf_D18_data_out,
- SYN_READ_IN => D18_READ_IN,
- -- Status and control port
- STAT_BUFFER => dbuf16_status(0)
- );
-
-D18_DATA_OUT <= buf_D18_data_out(15 downto 0);
-D18_PACKET_NUM_OUT <= buf_D18_data_out(17 downto 16);
-
- dbuf16_read_in_gen : process(CLK, RESET)
- begin
- if RESET = '1' then
- dbuf16_comb_read_in <= '0';
- elsif rising_edge(CLK) then
- dbuf16_comb_read_in <= dbuf16_next_read_out;
- else
- dbuf16_comb_read_in <= dbuf16_comb_read_in;
- end if;
- end process;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
---this is a converter from 64/55 Bit to 18 Bit format.
---It's just a quick hack and should not be used in the final network
---for example, no packet number check is implemented and one cycle is wasted
-
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_55_to_18_converter is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- D55_DATA_IN : in std_logic_vector(55 downto 0);
- D55_DATAREADY_IN : in std_logic;
- D55_READ_OUT : out std_logic;
-
- D18_DATA_OUT : out std_logic_vector(15 downto 0);
- D18_PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
- D18_DATAREADY_OUT : out std_logic;
- D18_READ_IN : in std_logic;
-
- D55_DATA_OUT : out std_logic_vector(55 downto 0);
- D55_DATAREADY_OUT : out std_logic;
- D55_READ_IN : in std_logic;
-
- D18_DATA_IN : in std_logic_vector(15 downto 0);
- D18_PACKET_NUM_IN : in std_logic_vector(1 downto 0);
- D18_DATAREADY_IN : in std_logic;
- D18_READ_OUT : out std_logic
- );
-end entity;
-
-
-architecture trb_net_55_to_18_converter_arch of trb_net_55_to_18_converter is
-
-
-
-type CONV_STATE is (IDLE, FIRST, SECOND, THIRD, LAST);
-signal D55to18_state, next_D55to18_state : CONV_STATE;
-signal D18to55_state, next_D18to55_state : CONV_STATE;
-
-signal next_D55_READ_OUT, buf_D55_READ_OUT : std_logic;
-signal next_D18_DATAREADY_OUT, buf_D18_DATAREADY_OUT : std_logic;
-signal next_D18_PACKET_NUM_OUT, buf_D18_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
-signal next_D18_DATA_OUT, buf_D18_DATA_OUT : std_logic_vector(15 downto 0);
-
-
-signal next_D18_READ_OUT, buf_D18_READ_OUT : std_logic;
-signal next_D55_DATAREADY_OUT, buf_D55_DATAREADY_OUT : std_logic;
-signal next_dataread55, dataread55 : std_logic;
- --data from 55 read and waiting to be written
-
-signal next_buf_D55_DATA_IN, buf_D55_DATA_IN : std_logic_vector(55 downto 0);
-signal next_D55_DATA_OUT, buf_D55_DATA_OUT : std_logic_vector(55 downto 0);
- --databuffer for both directions
-begin
------------------------------------------------------------
---Direction 18 to 55
------------------------------------------------------------
-
- D18to55_fsm : process(D55_READ_IN, buf_D55_DATAREADY_OUT, buf_D18_READ_OUT, D18_DATAREADY_IN,
- D18to55_state, buf_D55_DATA_OUT, D18_DATA_IN)
- variable dataisread18, dataisread55 : std_logic;
- begin
- next_D55_DATA_OUT <= buf_D55_DATA_OUT;
- next_D18to55_state <= D18to55_state;
- next_D18_READ_OUT <= '1';
- next_D55_DATAREADY_OUT <= '0';
-
- dataisread55 := D55_READ_IN AND buf_D55_DATAREADY_OUT;
- dataisread18 := buf_D18_READ_OUT AND D18_DATAREADY_IN;
-
-
- case D18to55_state is
- when IDLE =>
- if(dataisread18 = '1') then
- next_D55_DATA_OUT(55 downto 48) <= D18_DATA_IN(7 downto 0);
- next_D18to55_state <= FIRST;
- end if;
- when FIRST =>
- if(dataisread18 = '1') then
- next_D55_DATA_OUT(47 downto 32) <= D18_DATA_IN;
- next_D18to55_state <= SECOND;
- end if;
- when SECOND =>
- if(dataisread18 = '1') then
- next_D55_DATA_OUT(31 downto 16) <= D18_DATA_IN;
- next_D18to55_state <= THIRD;
- end if;
- when THIRD =>
- if(dataisread18 = '1') then
- next_D55_DATA_OUT(15 downto 0) <= D18_DATA_IN;
- next_D55_DATAREADY_OUT <= '1';
- next_D18to55_state <= LAST;
- next_D18_READ_OUT <= '0';
- end if;
- when LAST =>
- if(dataisread55 = '1') then
- next_D55_DATA_OUT <= (others => '0');
- next_D55_DATAREADY_OUT <= '0';
- next_D18to55_state <= IDLE;
- else
- next_D18_READ_OUT <= '0';
- next_D55_DATAREADY_OUT <= '1';
- end if;
- end case;
- end process;
-
- D18to55_fsm_reg : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- buf_D55_DATA_OUT <= (others => '0');
- D18to55_state <= IDLE;
- buf_D55_DATAREADY_OUT <= '0';
- buf_D18_READ_OUT <= '0';
- else
- buf_D55_DATA_OUT <= next_D55_DATA_OUT;
- D18to55_state <= next_D18to55_state;
- buf_D55_DATAREADY_OUT <= next_D55_DATAREADY_OUT;
- buf_D18_READ_OUT <= next_D18_READ_OUT;
- end if;
- end if;
- end process;
-
-D55_DATA_OUT <= buf_D55_DATA_OUT;
-D55_DATAREADY_OUT <= buf_D55_DATAREADY_OUT;
-D18_READ_OUT <= buf_D18_READ_OUT;
-
------------------------------------------------------------
---Direction 55 to 18
------------------------------------------------------------
- D55to18_fsm : process(buf_D18_DATA_OUT, buf_D18_PACKET_NUM_OUT, buf_D18_DATAREADY_OUT,
- D18_READ_IN, D55_DATA_IN, D55_DATAREADY_IN, D55to18_state,
- buf_D55_READ_OUT, buf_D55_DATA_IN, dataread55)
- variable dataisread18, dataisread55 : std_logic;
- begin
- next_D18_DATA_OUT <= buf_D18_DATA_OUT;
- next_D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT;
- next_D55to18_state <= D55to18_state;
- next_D55_READ_OUT <= '0';
- next_buf_D55_DATA_IN <= buf_D55_DATA_IN;
-
- dataisread18 := D18_READ_IN AND buf_D18_DATAREADY_OUT;
- dataisread55 := D55_DATAREADY_IN AND buf_D55_READ_OUT;
-
- if(dataisread18 = '1') then
- next_D18_DATAREADY_OUT <= '0';
- else
- next_D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT;
- end if;
-
-
- case D55to18_state is
- when IDLE =>
- if (dataisread18 = '1' OR buf_D18_DATAREADY_OUT = '0') then
- next_D55_READ_OUT <= '1';
- if dataisread55 = '1' then
- next_buf_D55_DATA_IN(55 downto 0) <= D55_DATA_IN(55 downto 0);
- next_D55_READ_OUT <= '0';
- next_D18_DATA_OUT(7 downto 0) <= D55_DATA_IN(55 downto 48);
- next_D18_DATA_OUT(15 downto 8) <= (others => '0');
- next_D18_PACKET_NUM_OUT <= "00";
- next_D18_DATAREADY_OUT <= '1';
- next_D55to18_state <= FIRST;
- end if;
- end if;
- when FIRST =>
- if(dataisread18 = '1') then
- next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(47 downto 32);
- next_D18_DATAREADY_OUT <= '1';
- next_D18_PACKET_NUM_OUT <= "01";
- next_D55to18_state <= SECOND;
- end if;
- when SECOND =>
- if(dataisread18 = '1') then
- next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(31 downto 16);
- next_D18_DATAREADY_OUT <= '1';
- next_D18_PACKET_NUM_OUT <= "10";
- next_D55to18_state <= THIRD;
- end if;
- when THIRD =>
- if(dataisread18 = '1') then
- next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(15 downto 0);
- next_D18_DATAREADY_OUT <= '1';
- next_D18_PACKET_NUM_OUT <= "11";
- next_D55to18_state <= IDLE;
- next_D55_READ_OUT <= '1';
- end if;
- when others =>
- next_D55to18_state <= IDLE;
- end case;
- end process;
-
- D55to18_fsm_reg : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- buf_D18_DATA_OUT <= (others => '0');
- buf_D55_DATA_IN <= (others => '0');
- buf_D55_READ_OUT <= '0';
- buf_D18_DATAREADY_OUT <= '0';
- buf_D18_PACKET_NUM_OUT <= "00";
- D55to18_state <= IDLE;
- else
- buf_D18_DATA_OUT <= next_D18_DATA_OUT;
- buf_D18_DATAREADY_OUT <= next_D18_DATAREADY_OUT;
- buf_D55_READ_OUT <= next_D55_READ_OUT;
- buf_D55_DATA_IN <= next_buf_D55_DATA_IN;
- buf_D18_PACKET_NUM_OUT <= next_D18_PACKET_NUM_OUT;
- D55to18_state <= next_D55to18_state;
- end if;
- end if;
- end process;
-
-D18_DATA_OUT <= buf_D18_DATA_OUT;
-D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT;
-D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT;
-D55_READ_OUT <= buf_D55_READ_OUT;
-
-
-end architecture;
\ No newline at end of file
+++ /dev/null
---this is a converter from 64/55 Bit to 18 Bit format.
---It's just a quick hack and should not be used in the final network
---for example, no packet number check is implemented and one cycle is wasted
-
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_64_to_18_converter is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- D55_DATA_IN : in std_logic_vector(50 downto 0);
- D55_DATAREADY_IN : in std_logic;
- D55_READ_OUT : out std_logic;
-
- D18_DATA_OUT : out std_logic_vector(15 downto 0);
- D18_PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
- D18_DATAREADY_OUT : out std_logic;
- D18_READ_IN : in std_logic;
-
- D55_DATA_OUT : out std_logic_vector(50 downto 0);
- D55_DATAREADY_OUT : out std_logic;
- D55_READ_IN : in std_logic;
-
- D18_DATA_IN : in std_logic_vector(15 downto 0);
- D18_PACKET_NUM_IN : in std_logic_vector(1 downto 0);
- D18_DATAREADY_IN : in std_logic;
- D18_READ_OUT : out std_logic
- );
-end entity;
-
-
-architecture trb_net_64_to_18_converter_arch of trb_net_64_to_18_converter is
-
-
-
-type CONV_STATE is (IDLE, FIRST, SECOND, THIRD, LAST);
-signal D55to18_state, next_D55to18_state : CONV_STATE;
-signal D18to55_state, next_D18to55_state : CONV_STATE;
-
-signal next_D55_READ_OUT, buf_D55_READ_OUT : std_logic;
-signal next_D18_DATAREADY_OUT, buf_D18_DATAREADY_OUT : std_logic;
-signal next_D18_PACKET_NUM_OUT, buf_D18_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
-signal next_D18_DATA_OUT, buf_D18_DATA_OUT : std_logic_vector(15 downto 0);
-
-
-signal next_D18_READ_OUT, buf_D18_READ_OUT : std_logic;
-signal next_D55_DATAREADY_OUT, buf_D55_DATAREADY_OUT : std_logic;
-signal next_dataread55, dataread55 : std_logic;
- --data from 55 read and waiting to be written
-
-signal next_buf_D55_DATA_IN, buf_D55_DATA_IN : std_logic_vector(50 downto 0);
-signal next_D55_DATA_OUT, buf_D55_DATA_OUT : std_logic_vector(50 downto 0);
- --databuffer for both directions
-begin
------------------------------------------------------------
---Direction 18 to 55
------------------------------------------------------------
-
- D18to55_fsm : process(D55_READ_IN, buf_D55_DATAREADY_OUT, buf_D18_READ_OUT, D18_DATAREADY_IN,
- D18to55_state, buf_D55_DATA_OUT, D18_DATA_IN)
- variable dataisread18, dataisread55 : std_logic;
- begin
- next_D55_DATA_OUT <= buf_D55_DATA_OUT;
- next_D18to55_state <= D18to55_state;
- next_D18_READ_OUT <= '1';
- next_D55_DATAREADY_OUT <= '0';
-
- dataisread55 := D55_READ_IN AND buf_D55_DATAREADY_OUT;
- dataisread18 := buf_D18_READ_OUT AND D18_DATAREADY_IN;
-
-
- case D18to55_state is
- when IDLE =>
- if(dataisread18 = '1') then
- next_D55_DATA_OUT(50 downto 48) <= D18_DATA_IN(2 downto 0);
- next_D18to55_state <= FIRST;
- end if;
- when FIRST =>
- if(dataisread18 = '1') then
- next_D55_DATA_OUT(47 downto 32) <= D18_DATA_IN;
- next_D18to55_state <= SECOND;
- end if;
- when SECOND =>
- if(dataisread18 = '1') then
- next_D55_DATA_OUT(31 downto 16) <= D18_DATA_IN;
- next_D18to55_state <= THIRD;
- end if;
- when THIRD =>
- if(dataisread18 = '1') then
- next_D55_DATA_OUT(15 downto 0) <= D18_DATA_IN;
- next_D55_DATAREADY_OUT <= '1';
- next_D18to55_state <= LAST;
- next_D18_READ_OUT <= '0';
- end if;
- when LAST =>
- if(dataisread55 = '1') then
- next_D55_DATA_OUT <= (others => '0');
- next_D55_DATAREADY_OUT <= '0';
- next_D18to55_state <= IDLE;
- else
- next_D18_READ_OUT <= '0';
- next_D55_DATAREADY_OUT <= '1';
- end if;
- end case;
- end process;
-
- D18to55_fsm_reg : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- buf_D55_DATA_OUT <= (others => '0');
- D18to55_state <= IDLE;
- buf_D55_DATAREADY_OUT <= '0';
- buf_D18_READ_OUT <= '0';
- else
- buf_D55_DATA_OUT <= next_D55_DATA_OUT;
- D18to55_state <= next_D18to55_state;
- buf_D55_DATAREADY_OUT <= next_D55_DATAREADY_OUT;
- buf_D18_READ_OUT <= next_D18_READ_OUT;
- end if;
- end if;
- end process;
-
-D55_DATA_OUT <= buf_D55_DATA_OUT;
-D55_DATAREADY_OUT <= buf_D55_DATAREADY_OUT;
-D18_READ_OUT <= buf_D18_READ_OUT;
-
------------------------------------------------------------
---Direction 55 to 18
------------------------------------------------------------
- D55to18_fsm : process(buf_D18_DATA_OUT, buf_D18_PACKET_NUM_OUT, buf_D18_DATAREADY_OUT,
- D18_READ_IN, D55_DATA_IN, D55_DATAREADY_IN, D55to18_state,
- buf_D55_READ_OUT, buf_D55_DATA_IN, dataread55)
- variable dataisread18, dataisread55 : std_logic;
- begin
- next_D18_DATA_OUT <= buf_D18_DATA_OUT;
- next_D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT;
- next_D55to18_state <= D55to18_state;
- next_D55_READ_OUT <= '0';
- next_buf_D55_DATA_IN <= buf_D55_DATA_IN;
-
- dataisread18 := D18_READ_IN AND buf_D18_DATAREADY_OUT;
- dataisread55 := D55_DATAREADY_IN AND buf_D55_READ_OUT;
-
- if(dataisread18 = '1') then
- next_D18_DATAREADY_OUT <= '0';
- else
- next_D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT;
- end if;
-
-
- case D55to18_state is
- when IDLE =>
- if (dataisread18 = '1' OR buf_D18_DATAREADY_OUT = '0') then
- next_D55_READ_OUT <= '1';
- if dataisread55 = '1' then
- next_buf_D55_DATA_IN(50 downto 0) <= D55_DATA_IN(50 downto 0);
- next_D55_READ_OUT <= '0';
- next_D18_DATA_OUT(2 downto 0) <= D55_DATA_IN(50 downto 48);
- next_D18_DATA_OUT(15 downto 3) <= (others => '0');
- next_D18_PACKET_NUM_OUT <= "00";
- next_D18_DATAREADY_OUT <= '1';
- next_D55to18_state <= FIRST;
- end if;
- end if;
- when FIRST =>
- if(dataisread18 = '1') then
- next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(47 downto 32);
- next_D18_DATAREADY_OUT <= '1';
- next_D18_PACKET_NUM_OUT <= "01";
- next_D55to18_state <= SECOND;
- end if;
- when SECOND =>
- if(dataisread18 = '1') then
- next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(31 downto 16);
- next_D18_DATAREADY_OUT <= '1';
- next_D18_PACKET_NUM_OUT <= "10";
- next_D55to18_state <= THIRD;
- end if;
- when THIRD =>
- if(dataisread18 = '1') then
- next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(15 downto 0);
- next_D18_DATAREADY_OUT <= '1';
- next_D18_PACKET_NUM_OUT <= "11";
- next_D55to18_state <= IDLE;
- next_D55_READ_OUT <= '1';
- end if;
- when others =>
- next_D55to18_state <= IDLE;
- end case;
- end process;
-
- D55to18_fsm_reg : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- buf_D18_DATA_OUT <= (others => '0');
- buf_D55_DATA_IN <= (others => '0');
- buf_D55_READ_OUT <= '0';
- buf_D18_DATAREADY_OUT <= '0';
- buf_D18_PACKET_NUM_OUT <= "00";
- D55to18_state <= IDLE;
- else
- buf_D18_DATA_OUT <= next_D18_DATA_OUT;
- buf_D18_DATAREADY_OUT <= next_D18_DATAREADY_OUT;
- buf_D55_READ_OUT <= next_D55_READ_OUT;
- buf_D55_DATA_IN <= next_buf_D55_DATA_IN;
- buf_D18_PACKET_NUM_OUT <= next_D18_PACKET_NUM_OUT;
- D55to18_state <= next_D55to18_state;
- end if;
- end if;
- end process;
-
-D18_DATA_OUT <= buf_D18_DATA_OUT;
-D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT;
-D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT;
-D55_READ_OUT <= buf_D55_READ_OUT;
-
-
-end architecture;
\ No newline at end of file
+++ /dev/null
--- connection between the TRBNET and any application
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net_active_api is
-
- generic (FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
-
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_INIT_DATAREADY_OUT: out STD_LOGIC;
- INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_IN: in STD_LOGIC;
-
- INT_INIT_DATAREADY_IN: in STD_LOGIC;
- INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_OUT: out STD_LOGIC;
-
-
- INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
- INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_IN: in STD_LOGIC;
-
- INT_REPLY_DATAREADY_IN: in STD_LOGIC;
- INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_OUT: out STD_LOGIC;
-
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- -- not needed now, but later
- );
-end trb_net_active_api;
-
-architecture trb_net_active_api_arch of trb_net_active_api is
-
- component trb_net_base_api is
- generic (API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
- FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Internal direction port
- -- the ports with active or passive in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- INT_MASTER_DATAREADY_OUT: out STD_LOGIC;
- INT_MASTER_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_MASTER_READ_IN: in STD_LOGIC;
-
- INT_MASTER_DATAREADY_IN: in STD_LOGIC;
- INT_MASTER_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_MASTER_READ_OUT: out STD_LOGIC;
-
- INT_SLAVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_SLAVE_DATAREADY_OUT: out STD_LOGIC;
- INT_SLAVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_SLAVE_READ_IN: in STD_LOGIC;
-
- INT_SLAVE_DATAREADY_IN: in STD_LOGIC;
- INT_SLAVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_SLAVE_READ_OUT: out STD_LOGIC;
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- -- not needed now, but later
- );
- end component;
-
-begin
-
- ACTIVE_API: trb_net_base_api
- generic map (
- API_TYPE => 1,
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH
- )
- port map (
- CLK => CLK,
- CLK_EN => CLK_EN,
- RESET => RESET,
-
- APL_DATA_IN => APL_DATA_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
- APL_DATA_OUT => APL_DATA_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
-
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
- INT_MASTER_DATA_OUT => INT_INIT_DATA_OUT,
- INT_MASTER_READ_IN => INT_INIT_READ_IN,
-
- INT_MASTER_DATAREADY_IN => INT_INIT_DATAREADY_IN,
- INT_MASTER_DATA_IN => INT_INIT_DATA_IN,
- INT_MASTER_READ_OUT => INT_INIT_READ_OUT,
-
- INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN,
-
- INT_SLAVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
- INT_SLAVE_DATA_OUT => INT_REPLY_DATA_OUT,
- INT_SLAVE_READ_IN => INT_REPLY_READ_IN,
-
- INT_SLAVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN,
- INT_SLAVE_DATA_IN => INT_REPLY_DATA_IN,
- INT_SLAVE_READ_OUT => INT_REPLY_READ_OUT,
- -- Status and control port
- STAT_FIFO_TO_INT => STAT_FIFO_TO_INT,
- STAT_FIFO_TO_APL => STAT_FIFO_TO_APL
- -- not needed now, but later
- );
-
-end trb_net_active_api_arch;
+++ /dev/null
--- an active api together with an iobuf
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_active_apimbuf is
-
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3; -- or the replyibuf
- FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_api_control_signals: out std_logic_vector(31 downto 0);
- STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-END trb_net_active_apimbuf;
-
-architecture trb_net_active_apimbuf_arch of trb_net_active_apimbuf is
-
-component trb_net_iobuf is
-
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3); -- or the replyibuf
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out STD_LOGIC;
- INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_IN: in STD_LOGIC;
-
- INT_INIT_DATAREADY_IN: in STD_LOGIC;
- INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_OUT: out STD_LOGIC;
-
- INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
- INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_IN: in STD_LOGIC;
-
- INT_REPLY_DATAREADY_IN: in STD_LOGIC;
- INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_OUT: out STD_LOGIC;
-
- -- Status and control port
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
- );
-END component;
-
-component trb_net_active_api is
-
- generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
-
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_INIT_DATAREADY_OUT: out STD_LOGIC;
- INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_IN: in STD_LOGIC;
-
- INT_INIT_DATAREADY_IN: in STD_LOGIC;
- INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_OUT: out STD_LOGIC;
-
-
- INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
- INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_IN: in STD_LOGIC;
-
- INT_REPLY_DATAREADY_IN: in STD_LOGIC;
- INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_OUT: out STD_LOGIC;
-
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-end component;
-
-component trb_net_io_multiplexer is
-
- generic (BUS_WIDTH : integer := 56;
- MULT_WIDTH : integer := 5);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- -- highest bits are mult.
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
-END component;
-
-signal apl_to_buf_INIT_DATAREADY: STD_LOGIC;
-signal apl_to_buf_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal apl_to_buf_INIT_READ : STD_LOGIC;
-
-signal buf_to_apl_INIT_DATAREADY: STD_LOGIC;
-signal buf_to_apl_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal buf_to_apl_INIT_READ : STD_LOGIC;
-
-signal apl_to_buf_REPLY_DATAREADY: STD_LOGIC;
-signal apl_to_buf_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal apl_to_buf_REPLY_READ : STD_LOGIC;
-
-signal buf_to_apl_REPLY_DATAREADY: STD_LOGIC;
-signal buf_to_apl_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal buf_to_apl_REPLY_READ : STD_LOGIC;
-
--- for the connection to the multiplexer
-signal MED_INIT_DATAREADY_OUT : STD_LOGIC;
-signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_INIT_READ_IN : STD_LOGIC;
-
-signal MED_INIT_DATAREADY_IN : STD_LOGIC;
-signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_INIT_READ_OUT : STD_LOGIC;
-
-signal MED_REPLY_DATAREADY_OUT : STD_LOGIC;
-signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_REPLY_READ_IN : STD_LOGIC;
-
-signal MED_REPLY_DATAREADY_IN : STD_LOGIC;
-signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_REPLY_READ_OUT : STD_LOGIC;
-
-signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (1 downto 0);
-signal m_DATA_OUT : STD_LOGIC_VECTOR (101 downto 0);
-signal m_READ_IN : STD_LOGIC_VECTOR (1 downto 0);
-
-signal m_DATAREADY_IN : STD_LOGIC_VECTOR (1 downto 0);
-signal m_DATA_IN : STD_LOGIC_VECTOR (101 downto 0);
-signal m_READ_OUT : STD_LOGIC_VECTOR (1 downto 0);
-
-begin
-
- m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
- m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT;
- m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT;
- MED_INIT_READ_IN <= m_READ_IN(0);
- MED_REPLY_READ_IN <= m_READ_IN(1);
-
- MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
- MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
- MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0);
- MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51);
- m_READ_OUT(0) <= MED_INIT_READ_OUT;
- m_READ_OUT(1) <= MED_REPLY_READ_OUT;
-
-
- ACTIVE_API: trb_net_active_api
-
- generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH)
-
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
-
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
-
- -- Internal direction port
- -- connect via private signals
-
- INT_INIT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
- INT_INIT_DATA_OUT => apl_to_buf_INIT_DATA,
- INT_INIT_READ_IN => apl_to_buf_INIT_READ,
-
- INT_INIT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
- INT_INIT_DATA_IN => buf_to_apl_INIT_DATA,
- INT_INIT_READ_OUT => buf_to_apl_INIT_READ,
-
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT =>apl_to_buf_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => apl_to_buf_REPLY_DATA,
- INT_REPLY_READ_IN => apl_to_buf_REPLY_READ,
-
- INT_REPLY_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => buf_to_apl_REPLY_DATA,
- INT_REPLY_READ_OUT => buf_to_apl_REPLY_READ,
-
- -- Status and control port
- STAT_FIFO_TO_INT => api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => api_stat_fifo_to_apl
- );
-
-STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
-STAT_api_control_signals(3) <= APL_WRITE_IN;
-STAT_api_control_signals(4) <= APL_SEND_IN;
-STAT_api_control_signals(7 downto 5) <= (others => '0');
-STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0);
-STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY;
-STAT_api_control_signals(12) <= apl_to_buf_INIT_READ;
-STAT_api_control_signals(31 downto 13) <= (others => '0');
-
-
-
-IOBUF: trb_net_iobuf
-
- generic map (INIT_DEPTH => INIT_DEPTH,
- REPLY_DEPTH => REPLY_DEPTH)
-
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_INIT_DATA_OUT,
- MED_INIT_READ_IN => MED_INIT_READ_IN,
-
- MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_INIT_DATA_IN,
- MED_INIT_READ_OUT => MED_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
-
- MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
- MED_REPLY_READ_IN => MED_REPLY_READ_IN,
-
- MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_REPLY_DATA_IN,
- MED_REPLY_READ_OUT => MED_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
- INT_INIT_READ_IN => buf_to_apl_INIT_READ,
-
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
-
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
-
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
-
- -- Status and control port
- STAT_GEN => STAT_GEN,
- STAT_LOCKED => STAT_LOCKED,
- STAT_INIT_BUFFER => STAT_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_REPLY_BUFFER,
- CTRL_GEN => CTRL_GEN,
- CTRL_LOCKED => CTRL_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER
- );
-
- MPLEX: trb_net_io_multiplexer
- generic map (BUS_WIDTH => 52,
- MULT_WIDTH => 1)
- port map (
- CLK => CLK,
- RESET => RESET ,
- CLK_EN => CLK_EN,
-
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_READ_OUT => MED_READ_OUT,
-
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_READ_IN => MED_READ_IN,
-
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_READ_IN =>m_READ_OUT,
-
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_READ_OUT =>m_READ_IN,
-
- CTRL => MPLEX_CTRL
-
- );
-
-end trb_net_active_apimbuf_arch;
-
+++ /dev/null
-------------------------------------------------------------------------------
---
--- This is a combination of the fast 8bit lvds interface and an active or
--- passive api, selectable with generic "API_TYPE"
---
-------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-
-
-entity trb_net_apimbuf_fast_lvds is
- generic (
- API_TYPE : integer range 0 to 1 := 0 --0: passive, 1: active api
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- API_RESET : in std_logic;
- CLK_EN : in std_logic;
-
- --LVDS
- LVDS_IN : in std_logic_vector(15 downto 0);
- LVDS_OUT : out std_logic_vector(15 downto 0);
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Status and Control registers
- API_STAT_GEN: out std_logic_vector(31 downto 0);
- API_STAT_LOCKED: out std_logic_vector(31 downto 0);
- API_STAT_INIT_BUFFER: out std_logic_vector(31 downto 0);
- API_STAT_REPLY_BUFFER: out std_logic_vector(31 downto 0);
- API_STAT_control_signals: out std_logic_vector(31 downto 0);
- STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
- API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0);
- LVDS_STAT: out std_logic_vector(31 downto 0);
- LVDS_CTRL: in std_logic_vector(31 downto 0);
- MPLEX_CTRL: in std_logic_vector(31 downto 0)
- );
-end entity;
-
-
-architecture trb_net_apimbuf_fast_lvds_arch of trb_net_apimbuf_fast_lvds is
- component trb_net_55_to_18_converter is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- D55_DATA_IN : in std_logic_vector(55 downto 0);
- D55_DATAREADY_IN : in std_logic;
- D55_READ_OUT : out std_logic;
-
- D18_DATA_OUT : out std_logic_vector(15 downto 0);
- D18_PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
- D18_DATAREADY_OUT : out std_logic;
- D18_READ_IN : in std_logic;
-
- D55_DATA_OUT : out std_logic_vector(55 downto 0);
- D55_DATAREADY_OUT : out std_logic;
- D55_READ_IN : in std_logic;
-
- D18_DATA_IN : in std_logic_vector(15 downto 0);
- D18_PACKET_NUM_IN : in std_logic_vector(1 downto 0);
- D18_DATAREADY_IN : in std_logic;
- D18_READ_OUT : out std_logic
- );
- end component;
-
- component trb_net_active_apimbuf is
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3; -- or the replyibuf
- FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_api_control_signals: out std_logic_vector(31 downto 0);
- STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net_passive_apimbuf is
- generic (
- INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3; -- or the replyibuf
- FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Status and control port
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_api_control_signals: out std_logic_vector(31 downto 0);
- STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
- end component;
-
-
- component trb_net_med_8bit_fast is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- 1st part: from the medium to the internal logic (trbnet)
- INT_DATAREADY_OUT: out STD_LOGIC;
- INT_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word
- INT_PACKET_NR_OUT: out STD_LOGIC_VECTOR(1 downto 0);
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- 2nd part: from the internal logic (trbnet) to the medium
- INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media
- INT_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word
- INT_PACKET_NR_IN : in STD_LOGIC_VECTOR(1 downto 0);
- INT_READ_OUT: out STD_LOGIC; -- offered word is read
- INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- Media direction port
- -- in this case for the cable => 32 lines in total
- MED_DATA_OUT: out STD_LOGIC_VECTOR (12 downto 0); -- Data word
- MED_TRANSMISSION_CLK_OUT: out STD_LOGIC;
- MED_CARRIER_OUT: out STD_LOGIC;
- MED_PARITY_OUT: out STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (12 downto 0); -- Data word
- MED_TRANSMISSION_CLK_IN: in STD_LOGIC;
- MED_CARRIER_IN: in STD_LOGIC;
- MED_PARITY_IN: in STD_LOGIC;
- -- Status and control port => this never can hurt
- STAT: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL: in STD_LOGIC_VECTOR (31 downto 0)
- );
- end component;
-
-
------------------------------------------------------------------------
---media interface signals
------------------------------------------------------------------------
- signal LVDS_INT_DATAREADY_OUT : std_logic;
- signal LVDS_INT_DATA_OUT : std_logic_vector(15 downto 0);
- signal LVDS_INT_READ_IN : std_logic;
- signal LVDS_INT_ERROR_IN : std_logic_vector(2 downto 0);
- signal LVDS_INT_DATAREADY_IN : std_logic;
- signal LVDS_INT_DATA_IN : std_logic_vector(15 downto 0);
- signal LVDS_INT_READ_OUT : std_logic;
- signal LVDS_INT_ERROR_OUT : std_logic_vector(2 downto 0);
- signal LVDS_MED_DATA_OUT : std_logic_vector(12 downto 0);
- signal LVDS_MED_TRANSMISSION_CLK_OUT : std_logic;
- signal LVDS_MED_CARRIER_OUT : std_logic;
- signal LVDS_MED_PARITY_OUT : std_logic;
- signal LVDS_MED_DATA_IN : std_logic_vector(12 downto 0);
- signal LVDS_MED_TRANSMISSION_CLK_IN : std_logic;
- signal LVDS_MED_CARRIER_IN : std_logic;
- signal LVDS_MED_PARITY_IN : std_logic;
- signal LVDS_INT_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
- signal LVDS_INT_PACKET_NUM_IN : std_logic_vector(1 downto 0);
-
-
-
------------------------------------------------------------------------
---API signals
------------------------------------------------------------------------
- signal API_MED_DATAREADY_OUT : std_logic;
- signal API_MED_DATA_OUT : std_logic_vector(51 downto 0);
- signal API_MED_READ_IN : std_logic;
- signal API_MED_ERROR_IN : std_logic_vector(2 downto 0);
- signal API_MED_DATAREADY_IN : std_logic;
- signal API_MED_DATA_IN : std_logic_vector(51 downto 0);
- signal API_MED_READ_OUT : std_logic;
- signal API_MED_ERROR_OUT : std_logic_vector(2 downto 0);
- signal API_ctrl : std_logic_vector(31 downto 0);
- signal C5518_D55_DATA_IN, C5518_D55_DATA_OUT : std_logic_vector(55 downto 0);
-
------------------------------------------------------------------------
---Control signals
------------------------------------------------------------------------
-
-
-
-begin
-
-
------------------------------------------------------------------------
---the media interface
------------------------------------------------------------------------
- lvds: trb_net_med_8bit_fast
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- INT_DATAREADY_OUT => LVDS_INT_DATAREADY_OUT,
- INT_DATA_OUT => LVDS_INT_DATA_OUT,
- INT_PACKET_NR_OUT => LVDS_INT_PACKET_NUM_OUT,
- INT_READ_IN => LVDS_INT_READ_IN,
- INT_ERROR_OUT => LVDS_INT_ERROR_OUT,
- INT_DATAREADY_IN => LVDS_INT_DATAREADY_IN,
- INT_DATA_IN => LVDS_INT_DATA_IN,
- INT_PACKET_NR_IN => LVDS_INT_PACKET_NUM_IN,
- INT_READ_OUT => LVDS_INT_READ_OUT,
- INT_ERROR_IN => LVDS_INT_ERROR_IN,
-
- MED_DATA_OUT => LVDS_MED_DATA_OUT,
- MED_TRANSMISSION_CLK_OUT => LVDS_MED_TRANSMISSION_CLK_OUT,
- MED_CARRIER_OUT => LVDS_MED_CARRIER_OUT,
- MED_PARITY_OUT => LVDS_MED_PARITY_OUT,
- MED_DATA_IN => LVDS_MED_DATA_IN,
- MED_TRANSMISSION_CLK_IN => LVDS_MED_TRANSMISSION_CLK_IN,
- MED_CARRIER_IN => LVDS_MED_CARRIER_IN,
- MED_PARITY_IN => LVDS_MED_PARITY_IN,
- STAT => LVDS_STAT,
- CTRL => LVDS_CTRL
- );
-
- LVDS_OUT(7 downto 0) <= LVDS_MED_DATA_OUT(7 downto 0);
- LVDS_OUT(10) <= C5518_D55_DATA_OUT(48);
- LVDS_OUT(9) <= LVDS_INT_DATA_OUT(0);
- LVDS_OUT(8) <= LVDS_INT_DATAREADY_OUT;
- LVDS_OUT(11) <= LVDS_MED_DATA_OUT(11) and not API_RESET;
- LVDS_OUT(12) <= LVDS_MED_DATA_OUT(12);
- LVDS_OUT(13) <= LVDS_MED_TRANSMISSION_CLK_OUT;
- LVDS_OUT(14) <= LVDS_MED_CARRIER_OUT;
- LVDS_OUT(15) <= LVDS_MED_PARITY_OUT;
- LVDS_MED_DATA_IN <= LVDS_IN(12 downto 0);
- LVDS_MED_TRANSMISSION_CLK_IN <= LVDS_IN(13);
- LVDS_MED_CARRIER_IN <= LVDS_IN(14);
- LVDS_MED_PARITY_IN <= LVDS_IN(15);
-
-
------------------------------------------------------------------------
---bus width converter
------------------------------------------------------------------------
- C5518 : trb_net_55_to_18_converter
- port map(
- -- Misc
- CLK => CLK,
- RESET => API_RESET,
- CLK_EN => CLK_EN,
-
- D55_DATA_IN => C5518_D55_DATA_IN,
- D55_DATAREADY_IN => API_MED_DATAREADY_OUT,
- D55_READ_OUT => API_MED_READ_IN,
-
- D18_DATA_OUT => LVDS_INT_DATA_IN,
- D18_PACKET_NUM_OUT => LVDS_INT_PACKET_NUM_IN,
- D18_DATAREADY_OUT => LVDS_INT_DATAREADY_IN,
- D18_READ_IN => LVDS_INT_READ_OUT,
-
- D55_DATA_OUT => C5518_D55_DATA_OUT,
- D55_DATAREADY_OUT => API_MED_DATAREADY_IN,
- D55_READ_IN => API_MED_READ_OUT,
-
- D18_DATA_IN => LVDS_INT_DATA_OUT,
- D18_PACKET_NUM_IN => LVDS_INT_PACKET_NUM_OUT,
- D18_DATAREADY_IN => LVDS_INT_DATAREADY_OUT,
- D18_READ_OUT => LVDS_INT_READ_IN
- );
-
- C5518_D55_DATA_IN(51 downto 0) <= API_MED_DATA_OUT;
- C5518_D55_DATA_IN(55 downto 52) <= "0000";
- API_MED_DATA_IN <= C5518_D55_DATA_OUT(51 downto 0);
-
------------------------------------------------------------------------
---API
------------------------------------------------------------------------
-
- apigenact : if API_TYPE = 1 generate
- API: trb_net_active_apimbuf
- generic map (
- FIFO_TERM_BUFFER_DEPTH => 3)
- port map (
- CLK => CLK,
- RESET => API_RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
- -- Media direction
- MED_DATAREADY_OUT => API_MED_DATAREADY_OUT,
- MED_DATA_OUT => API_MED_DATA_OUT,
- MED_READ_IN => API_MED_READ_IN,
- MED_ERROR_IN => LVDS_INT_ERROR_OUT,
- MED_DATAREADY_IN => API_MED_DATAREADY_IN,
- MED_DATA_IN => API_MED_DATA_IN,
- MED_READ_OUT => API_MED_READ_OUT,
-
- CTRL_LOCKED => (others => '0'),
- CTRL_GEN => (others => '0'),
-
- STAT_GEN => API_STAT_GEN,
- STAT_LOCKED => API_STAT_LOCKED,
- STAT_INIT_BUFFER => API_STAT_INIT_BUFFER,
- STAT_REPLY_BUFFER => API_STAT_REPLY_BUFFER,
- STAT_api_control_signals => API_STAT_control_signals,
- STAT_MPLEX => STAT_MPLEX,
- STAT_CTRL_INIT_BUFFER => (others => '0'),
- STAT_CTRL_REPLY_BUFFER => (others => '0'),
- MPLEX_CTRL => MPLEX_CTRL,
- API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT,
- API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL
- );
- end generate;
-
- apigenpas : if API_TYPE = 0 generate
- API: trb_net_passive_apimbuf
- generic map (
- FIFO_TERM_BUFFER_DEPTH => 3)
- port map (
- CLK => CLK,
- RESET => API_RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- -- Media direction
- MED_DATAREADY_OUT => API_MED_DATAREADY_OUT,
- MED_DATA_OUT => API_MED_DATA_OUT,
- MED_READ_IN => API_MED_READ_IN,
- MED_ERROR_IN => API_MED_ERROR_IN,
- MED_DATAREADY_IN => API_MED_DATAREADY_IN,
- MED_DATA_IN => API_MED_DATA_IN,
- MED_READ_OUT => API_MED_READ_OUT,
-
- CTRL_LOCKED => (others => '0'),
- CTRL_GEN => (others => '0'),
-
- STAT_GEN => API_STAT_GEN,
- STAT_LOCKED => API_STAT_LOCKED,
- STAT_INIT_BUFFER => API_STAT_INIT_BUFFER,
- STAT_REPLY_BUFFER => API_STAT_REPLY_BUFFER,
- STAT_api_control_signals => API_STAT_control_signals,
- STAT_MPLEX => STAT_MPLEX,
- STAT_CTRL_INIT_BUFFER => (others => '0'),
- STAT_CTRL_REPLY_BUFFER => (others => '0'),
- MPLEX_CTRL => MPLEX_CTRL,
- API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT,
- API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL
- );
- end generate;
-
-end architecture;
-
-
-
-
-
-
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net_base_api is
-
- generic (API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
- FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
-
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- INT_MASTER_DATAREADY_OUT: out STD_LOGIC;
- INT_MASTER_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_MASTER_READ_IN: in STD_LOGIC;
-
- INT_MASTER_DATAREADY_IN: in STD_LOGIC;
- INT_MASTER_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_MASTER_READ_OUT: out STD_LOGIC;
-
-
- INT_SLAVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_SLAVE_DATAREADY_OUT: out STD_LOGIC;
- INT_SLAVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_SLAVE_READ_IN: in STD_LOGIC;
-
- INT_SLAVE_DATAREADY_IN: in STD_LOGIC;
- INT_SLAVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_SLAVE_READ_OUT: out STD_LOGIC;
-
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- -- not needed now, but later
-
- );
-end entity trb_net_base_api;
-
-
-
-architecture trb_net_base_api_arch of trb_net_base_api is
- component trb_net_fifo is
- generic (
- WIDTH : integer := 8; -- FIFO word width
- DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1)
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic; -- Full Flag
- EMPTY_OUT : out std_logic;
- DEPTH_OUT : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component trb_net_dummy_fifo is
- generic (WIDTH : integer := 8); -- Depth of the FIFO, 2^(n+1)
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic; -- Full Flag
- EMPTY_OUT : out std_logic;
- DEPTH_OUT : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component trb_net_sbuf is
- generic (DATA_WIDTH : integer := 56;
- VERSION: integer := 1);
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- -- Port to synchronous output.
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
-
-
- component trb_net_term is
- generic (FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of the master
- -- path, if set to 0 no buffer is used at all
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
- INT_DATAREADY_OUT: out STD_LOGIC;
- INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
- INT_DATAREADY_IN: in STD_LOGIC;
- INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_OUT: out STD_LOGIC;
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
- APL_GOT_TRM: out STD_LOGIC;
- APL_HOLD_TRM: in STD_LOGIC;
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0) -- My own address (temporary solution!!!)
- -- Status and control port
- -- not needed now, but later
- );
- end component;
-
- -- signals for the APL to INT fifo:
- signal fifo_to_int_data_in : std_logic_vector(47 downto 0);
- signal fifo_to_int_write : std_logic;
- signal fifo_to_int_data_out : std_logic_vector(47 downto 0);
- signal fifo_to_int_read : std_logic;
- signal fifo_to_int_full : std_logic;
- signal fifo_to_int_empty : std_logic;
-
- -- signals for the INT to APL:
- signal fifo_to_apl_data_in : std_logic_vector(50 downto 0);
- signal fifo_to_apl_write : std_logic;
- signal fifo_to_apl_data_out : std_logic_vector(50 downto 0);
- signal fifo_to_apl_read : std_logic;
- signal fifo_to_apl_full : std_logic;
- signal fifo_to_apl_empty : std_logic;
-
- -- signals for the test buffer
- signal fifo_term_buffer_data_in : std_logic_vector(50 downto 0);
- signal fifo_term_buffer_write : std_logic;
- signal fifo_term_buffer_data_out : std_logic_vector(50 downto 0);
- signal fifo_term_buffer_read : std_logic;
- signal fifo_term_buffer_full : std_logic;
- signal fifo_term_buffer_empty : std_logic;
-
- signal state_bits : std_logic_vector(2 downto 0);
- type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR);
- type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR);
- signal current_state, next_state : API_STATE;
- signal tb_current_state, tb_next_state : TERM_BUFFER_STATE;
- signal slave_running, next_slave_running : std_logic;
-
- signal combined_header: std_logic_vector(47 downto 0); --stored in sbuf
- -- , registered_header, next_registered_header: std_logic_vector(47 downto 0);
- --signal update_registered_header: std_logic;
- signal combined_trailer, registered_trailer, next_registered_trailer: std_logic_vector(47 downto 0);
- signal update_registered_trailer: std_logic;
- signal tb_registered_trailer, tb_next_registered_trailer: std_logic_vector(47 downto 0);
- signal tb_registered_target, tb_next_registered_target: std_logic_vector(15 downto 0);
-
- signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0);
- signal next_INT_MASTER_DATA_OUT: std_logic_vector(50 downto 0);
- signal next_INT_MASTER_DATAREADY_OUT: std_logic;
- signal sbuf_free, sbuf_next_READ: std_logic;
- signal next_INT_SLAVE_READ_OUT, reg_INT_SLAVE_READ_OUT: std_logic;
- signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic;
- signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(47 downto 0);
- signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0);
-
- type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB);
- signal out_select: OUTPUT_SELECT;
-
-begin
-
----------------------------------------
--- termination for active api
----------------------------------------
-
--- gen_term: if API_TYPE = 1 generate
- TrbNetTerm: trb_net_term
- generic map(FIFO_TERM_BUFFER_DEPTH => 0)
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- INT_DATAREADY_OUT => INT_SLAVE_DATAREADY_OUT,
- INT_DATA_OUT => INT_SLAVE_DATA_OUT,
- INT_READ_IN => INT_SLAVE_READ_IN,
- INT_DATAREADY_IN => INT_MASTER_DATAREADY_IN,
- INT_DATA_IN => INT_MASTER_DATA_IN,
- INT_READ_OUT => INT_MASTER_READ_OUT,
- APL_HOLD_TRM => '0',
- APL_DTYPE_IN => (others => '0'),
- APL_ERROR_PATTERN_IN => (others => '0'),
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN
- );
--- end generate;
-
--- gen_noterm: if API_TYPE = 0 generate
--- INT_SLAVE_READ_OUT <= '0';
---
--- end generate;
-
----------------------------------------
--- fifo to internal
----------------------------------------
-
- CHECK_BUFFER3: if FIFO_TO_INT_DEPTH >0 generate
- FIFO_TO_INT: trb_net_fifo
- generic map (
- WIDTH => 48,
- DEPTH => FIFO_TO_INT_DEPTH)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_int_data_in,
- WRITE_ENABLE_IN => fifo_to_int_write,
- DATA_OUT => fifo_to_int_data_out,
- READ_ENABLE_IN => fifo_to_int_read,
- FULL_OUT => fifo_to_int_full,
- EMPTY_OUT => fifo_to_int_empty
- );
- end generate;
-
- CHECK_BUFFER4: if FIFO_TO_INT_DEPTH =0 generate
- FIFO_TO_INT: trb_net_dummy_fifo
- generic map (
- WIDTH => 48)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_int_data_in,
- WRITE_ENABLE_IN => fifo_to_int_write,
- DATA_OUT => fifo_to_int_data_out,
- READ_ENABLE_IN => fifo_to_int_read,
- FULL_OUT => fifo_to_int_full,
- EMPTY_OUT => fifo_to_int_empty
- );
- end generate CHECK_BUFFER4;
-
- STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0);
- STAT_FIFO_TO_INT(3) <= fifo_to_int_write;
- STAT_FIFO_TO_INT(10 downto 8) <= fifo_to_int_data_out(2 downto 0);
- STAT_FIFO_TO_INT(11) <= fifo_to_int_read;
- STAT_FIFO_TO_INT(14) <= fifo_to_int_full;
- STAT_FIFO_TO_INT(15) <= fifo_to_int_empty;
- STAT_FIFO_TO_INT(7 downto 4) <= (others => '0');
- STAT_FIFO_TO_INT(13 downto 12) <= (others => '0');
- STAT_FIFO_TO_INT(28 downto 16) <= (others => '0');
- STAT_FIFO_TO_INT(31 downto 29) <= state_bits;
----------------------------------------
--- fifo to apl
----------------------------------------
-
- CHECK_BUFFER5: if FIFO_TO_APL_DEPTH >0 generate
- FIFO_TO_APL: trb_net_fifo
- generic map (
- WIDTH => 51,
- DEPTH => FIFO_TO_APL_DEPTH)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_apl_data_in,
- WRITE_ENABLE_IN => fifo_to_apl_write,
- DATA_OUT => fifo_to_apl_data_out,
- READ_ENABLE_IN => fifo_to_apl_read,
- FULL_OUT => fifo_to_apl_full,
- EMPTY_OUT => fifo_to_apl_empty
- );
- end generate CHECK_BUFFER5;
-
- CHECK_BUFFER6: if FIFO_TO_APL_DEPTH =0 generate
- FIFO_TO_APL: trb_net_dummy_fifo
- generic map (
- WIDTH => 51)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_apl_data_in,
- WRITE_ENABLE_IN => fifo_to_apl_write,
- DATA_OUT => fifo_to_apl_data_out,
- READ_ENABLE_IN => fifo_to_apl_read,
- FULL_OUT => fifo_to_apl_full,
- EMPTY_OUT => fifo_to_apl_empty
- );
- end generate CHECK_BUFFER6;
-
- STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0);
- STAT_FIFO_TO_APL(3) <= fifo_to_apl_write;
- STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0);
- STAT_FIFO_TO_APL(11) <= fifo_to_apl_read;
- STAT_FIFO_TO_APL(14) <= fifo_to_apl_full;
- STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty;
- STAT_FIFO_TO_APL(7 downto 4) <= (others => '0');
- --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0');
- STAT_FIFO_TO_APL(31 downto 16) <= (others => '0');
- STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT;
- STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN;
- STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT;
-
----------------------------------------
--- a sbuf on the active channel
----------------------------------------
-
- ACTIVE_SBUF: trb_net_sbuf
- generic map (
- DATA_WIDTH => 51,
- VERSION => 0)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => next_INT_MASTER_DATAREADY_OUT,
- COMB_next_READ_OUT => sbuf_next_READ,
- COMB_READ_IN => '1',
- COMB_DATA_IN => next_INT_MASTER_DATA_OUT,
- SYN_DATAREADY_OUT => INT_MASTER_DATAREADY_OUT,
- SYN_DATA_OUT => INT_MASTER_DATA_OUT,
- SYN_READ_IN => INT_MASTER_READ_IN
- );
-
-
-
- --sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle
- sbuf_free <= sbuf_next_READ;
- next_registered_trailer <= combined_trailer;
- --next_registered_header <= combined_header;
- next_APL_DATA_OUT <= fifo_to_apl_data_out(DWORD_POSITION);
- next_APL_TYP_OUT <= fifo_to_apl_data_out(TYPE_POSITION);
-
-
----------------------------------------
--- select data for int direction
----------------------------------------
- process (out_select, combined_header, registered_trailer,
- fifo_to_int_data_out, combined_trailer)
- begin
- if out_select = HDR then
- next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_HDR;
- next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= combined_header;
- elsif out_select = TRM then
- next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_TRM;
- next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= registered_trailer;
- elsif out_select = TRM_COMB then
- next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_TRM;
- next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= combined_trailer;
- else
- next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_DAT;
- next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out;
- end if;
- end process;
-
-
----------------------------------------
--- the state machine
----------------------------------------
--- gen_active_fsm : if API_TYPE = 1 generate
- STATE_COMB : process(current_state, APL_SEND_IN, combined_header,
- INT_MASTER_READ_IN, APL_WRITE_IN, fifo_to_int_empty,
- fifo_to_int_data_out, combined_trailer, slave_running,
- next_registered_trailer, fifo_to_int_data_out,
- fifo_to_apl_empty, INT_SLAVE_DATAREADY_IN,
- reg_INT_SLAVE_READ_OUT,fifo_to_apl_read,
- reg_APL_DATAREADY_OUT, fifo_to_apl_data_out,
- reg_APL_DATAREADY_OUT, APL_READ_IN, sbuf_free,
- reg_APL_TYP_OUT, APL_SHORT_TRANSFER_IN, fifo_to_apl_full)
- begin -- process
- next_state <= MY_ERROR;
- next_INT_MASTER_DATAREADY_OUT <= '0';
- out_select <= DAT;
- update_registered_trailer <= '0';
- fifo_to_int_read <= '0';
- next_INT_SLAVE_READ_OUT <= '0';
- fifo_to_apl_write <= '0';
- next_APL_DATAREADY_OUT <= '0';
- fifo_to_apl_read <= '0';
- next_slave_running <= slave_running;
- next_sequence_counter <= sequence_counter;
- -------------------------------------------------------------------------------
- -- IDLE
- -------------------------------------------------------------------------------
- if current_state = IDLE then
- if APL_SEND_IN = '1' then
- if APL_SHORT_TRANSFER_IN = '1' and APL_WRITE_IN = '0' and fifo_to_int_empty = '1' then
- next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN
- next_INT_MASTER_DATAREADY_OUT <= '0';
- update_registered_trailer <= '1'; -- moved from SEND_SHORT
- else -- normal transfer, prepare the header
- next_state <= SEND_HEADER;
- out_select <= HDR;
- next_INT_MASTER_DATAREADY_OUT <= '1';
- end if; -- next word will be a header
- else
- next_state <= IDLE;
- end if; -- APL_SEND_IN
- -------------------------------------------------------------------------------
- -- SEND_SHORT
- -------------------------------------------------------------------------------
- elsif current_state = SEND_SHORT then
- next_state <= SEND_SHORT;
- if APL_SEND_IN = '0' then -- terminate the transfer
- next_state <= SEND_TRAILER;
- next_INT_MASTER_DATAREADY_OUT <= '1';
- out_select <= TRM;
- end if;
- -------------------------------------------------------------------------------
- -- SEND_HEADER
- -------------------------------------------------------------------------------
- elsif current_state = SEND_HEADER then
- if sbuf_free = '1' then -- kill current header
- next_state <= RUNNING;
- if fifo_to_int_empty = '1' then
- next_INT_MASTER_DATAREADY_OUT <= '0';
- else
- next_INT_MASTER_DATAREADY_OUT <= '1';
- out_select <= DAT;
- fifo_to_int_read <= '1';
- end if; -- fifo_to_int_empty
- else
- next_state <= SEND_HEADER;
- end if;
- -------------------------------------------------------------------------------
- -- RUNNING
- -------------------------------------------------------------------------------
- elsif current_state = RUNNING then
- if APL_SEND_IN = '0' then -- terminate the transfer
- if fifo_to_int_empty = '1' then -- immediate stop
- next_state <= SEND_TRAILER;
- update_registered_trailer <= '1';
- next_INT_MASTER_DATAREADY_OUT <= '1';
- out_select <= TRM_COMB;
- else
- next_state <= SHUTDOWN;
- update_registered_trailer <= '1';
- if sbuf_free = '1' then
- -- data words have to be prepared
- next_INT_MASTER_DATAREADY_OUT <= '1';
- out_select <= DAT;
- fifo_to_int_read <= '1';
- end if; -- fifo_to_int_empty = '0'
- end if;
- else -- APL_SEND_IN: still running
- next_state <= RUNNING;
- if fifo_to_int_empty = '0' and sbuf_free = '1' then
- -- data words have to be prepared
- next_INT_MASTER_DATAREADY_OUT <= '1';
- out_select <= DAT;
- fifo_to_int_read <= '1';
- end if; -- fifo_to_int_empty = '0'
- end if;
- -------------------------------------------------------------------------------
- -- SHUTDOWN: Empty the pipe
- -------------------------------------------------------------------------------
- elsif current_state = SHUTDOWN then
- next_state <= SHUTDOWN;
- if fifo_to_int_empty = '0' and sbuf_free = '1' then
- -- data words have to be prepared
- next_INT_MASTER_DATAREADY_OUT <= '1';
- out_select <= DAT;
- fifo_to_int_read <= '1';
- elsif sbuf_free = '1' then
- -- we are done
- next_state <= SEND_TRAILER;
- next_INT_MASTER_DATAREADY_OUT <= '1';
- out_select <= TRM;
- end if;
- -------------------------------------------------------------------------------
- -- SEND_TRAILER
- -------------------------------------------------------------------------------
- elsif current_state = SEND_TRAILER then
- if sbuf_free = '1' then -- kill current trailer
- next_state <= WAITING;
- out_select <= TRM;
- next_INT_MASTER_DATAREADY_OUT <= '0';
- next_slave_running <= '0';
- else
- next_state <= SEND_TRAILER;
- end if;
- -------------------------------------------------------------------------------
- -- WAITING => for the answer or a request
- -------------------------------------------------------------------------------
- elsif current_state = WAITING then
- next_state <= WAITING;
- -- here we have to supply the receiver port
- -- part 1: connection to network
- if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then
- next_INT_SLAVE_READ_OUT <= '1';
- end if;
- if reg_INT_SLAVE_READ_OUT = '1' and INT_SLAVE_DATAREADY_IN = '1' then
- fifo_to_apl_write <= '1'; -- use fifo as the pipe
- end if;
-
- -- part 2: connection to apl
--- if fifo_to_apl_empty = '0' then
- if fifo_to_apl_empty = '0' and not (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') then --is this really correct????
- next_APL_DATAREADY_OUT <= '1';
- end if; -- read/no read
-
- if reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1' then
- -- valid read
- fifo_to_apl_read <= '1';
- if (reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR) then
- next_slave_running <= '1';
- end if;
- if reg_APL_TYP_OUT = TYPE_TRM and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1') then --fifo_to_apl_read = '1'
- next_state <= IDLE;
- next_sequence_counter <= sequence_counter +1;
- end if;
- end if;
- -- MISSING: SEQNR check
- -- OPEN QUESTION: Address matching? makes sense for a reply transfer?
- end if; -- end state switch
- end process;
--- end generate;
-
-
-
----------------------------------------
---
----------------------------------------
-
- -- combine the next header
- combined_header(F1_POSITION) <= APL_MY_ADDRESS_IN;
- combined_header(F2_POSITION) <= APL_TARGET_ADDRESS_IN;
- combined_header(15 downto 14) <= (others => '0'); -- LAY
- combined_header(13 downto 12) <= (others => '0'); -- VERS
- combined_header(11 downto 4) <= sequence_counter; -- SEQNR
- combined_header(3 downto 0) <= APL_DTYPE_IN;
- combined_trailer(F1_POSITION) <= APL_ERROR_PATTERN_IN(31 downto 16);
- combined_trailer(F2_POSITION) <= APL_ERROR_PATTERN_IN(15 downto 0);
- combined_trailer(15 downto 14) <= (others => '0'); -- res.
- combined_trailer(13 downto 12) <= (others => '0'); -- VERS
- combined_trailer(11 downto 4) <= sequence_counter; -- SEQNR
- combined_trailer(3 downto 0) <= APL_DTYPE_IN;
- -- this is not very consequent, find a better solution the be independent
- -- with the range
-
- -- connect Transmitter port
- fifo_to_int_data_in <= APL_DATA_IN;
- fifo_to_int_write <= (APL_WRITE_IN and not fifo_to_int_full) when (current_state = IDLE or
- current_state = SEND_HEADER or
- current_state = RUNNING)
-
- else '0';
-
-
- APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing
-
-
- INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- reg_APL_DATAREADY_OUT <= '0';
- reg_APL_DATA_OUT <= (others => '0');
- reg_APL_TYP_OUT <= (others => '0');
- else
- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
- reg_APL_DATA_OUT <= next_APL_DATA_OUT;
- reg_APL_TYP_OUT <= next_APL_TYP_OUT;
- end if;
- end if;
- end process;
-
-
- -- connect receiver
- fifo_to_apl_data_in <= INT_SLAVE_DATA_IN;
-
--- this has to be registered!
--- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
--- reg_APL_DATA_OUT <= next_APL_DATA_OUT;
--- reg_APL_TYP_OUT <= next_APL_TYP_OUT;
-
- APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT;
- APL_DATA_OUT <= reg_APL_DATA_OUT;
- APL_TYP_OUT <= reg_APL_TYP_OUT;
--- APL_RUN_OUT <= '0' when ((current_state = IDLE ))
- APL_RUN_OUT <= '0' when ((current_state = IDLE and API_TYPE = 1)
- or (slave_running = '0' and API_TYPE = 0))
- else '1';
- APL_SEQNR_OUT <= sequence_counter;
-
---removed and put into main state machine
--- generate the sequence counter
--- -- combinatorial part
--- SEQNR_COMB : process(sequence_counter, current_state, next_state)
--- begin
--- if current_state = WAITING and next_state = IDLE then
--- next_sequence_counter <= sequence_counter+1;
--- else
--- next_sequence_counter <= sequence_counter;
--- end if;
--- end process;
-
-
-
- CLK_REG: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- sequence_counter <= (others => '0');
- reg_INT_SLAVE_READ_OUT <= '0';
- if API_TYPE = 1 then
- current_state <= IDLE;
- else
- current_state <= WAITING;
- end if;
- slave_running <= '0';
- tb_current_state <= IDLE;
- tb_registered_trailer <= (others => '0');
- tb_registered_target <= ILLEGAL_ADRESS;
- elsif CLK_EN = '1' then
- sequence_counter <= next_sequence_counter;
- reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT;
- current_state <= next_state;
- slave_running <= next_slave_running;
- tb_current_state <= tb_next_state;
- tb_registered_trailer <= tb_next_registered_trailer;
- tb_registered_target <= tb_next_registered_target;
- else
- sequence_counter <= sequence_counter;
- reg_INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT;
- current_state <= current_state;
- slave_running <= slave_running;
- tb_current_state <= tb_current_state;
- tb_registered_trailer <= tb_registered_trailer;
- tb_registered_target <= tb_registered_target;
- end if;
- end if;
- end process;
-
- REG3 : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- registered_trailer <= (others => '0');
- elsif update_registered_trailer = '1' then
- registered_trailer <= next_registered_trailer;
- else
- registered_trailer <= registered_trailer;
- end if;
- end if;
- end process;
-
-process(current_state)
- begin
- case current_state is
- when IDLE => state_bits <= "000";
- when SEND_HEADER => state_bits <= "001";
- when RUNNING => state_bits <= "010";
- when SHUTDOWN => state_bits <= "011";
- when SEND_SHORT => state_bits <= "100";
- when SEND_TRAILER => state_bits <= "101";
- when WAITING => state_bits <= "110";
- when others => state_bits <= "111";
- end case;
- end process;
-
-
-
-end architecture trb_net_base_api_arch;
-
-
-
+++ /dev/null
--- this is the final endpoint to be used
--- It has 3 channels
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_endpoint_3ch is
-
- -- per channel we have the following generics:
- -- 1.) APIX_FIFO_TO_INT_DEPTH
- -- 2.) APIX_FIFO_TO_APL_DEPTH
- -- 3.) APIX_TYPE (0=active, 1=passive, 99=dummy)
- -- 4.) APIX_INIT_DEPTH
- -- 5.) APIX_REPLY_DEPTH
- -- 6.) APIX_CHANNEL_NUMBER
-
- -- The dummy APL can be used for debugging
- -- In this case, the API lines are use only for sniffing
- -- and the input lines can be driven to any value
- -- with one exeption:
- -- if APL_SEND_IN = '0' the dummy APL will be resetted
-
- generic (
-
- API1_FIFO_TO_INT_DEPTH: integer := 3;
- API1_FIFO_TO_APL_DEPTH: integer := 3;
- API1_TYPE : integer := 0;
- API1_INIT_DEPTH : integer := 3;
- API1_REPLY_DEPTH : integer := 3;
- API1_CHANNEL_NUMBER : integer := 0;
-
- API2_FIFO_TO_INT_DEPTH: integer := 3;
- API2_FIFO_TO_APL_DEPTH: integer := 3;
- API2_TYPE : integer := 0;
- API2_INIT_DEPTH : integer := 3;
- API2_REPLY_DEPTH : integer := 3;
- API2_CHANNEL_NUMBER : integer := 1;
-
- API3_FIFO_TO_INT_DEPTH: integer := 3;
- API3_FIFO_TO_APL_DEPTH: integer := 3;
- API3_TYPE : integer := 0;
- API3_INIT_DEPTH : integer := 3;
- API3_REPLY_DEPTH : integer := 3;
- API3_CHANNEL_NUMBER : integer := 2
-
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- ----------------------------------------------------------------------------
- -- API1
- ----------------------------------------------------------------------------
- -- APL Transmitter port
- APL1_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL1_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL1_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL1_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL1_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL1_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL1_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL1_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL1_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL1_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL1_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL1_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL1_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL1_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- ----------------------------------------------------------------------------
- -- API2
- ----------------------------------------------------------------------------
- -- APL Transmitter port
- APL2_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL2_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL2_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL2_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL2_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL2_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL2_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL2_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL2_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL2_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL2_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL2_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL2_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL2_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- ----------------------------------------------------------------------------
- -- API3
- ----------------------------------------------------------------------------
- -- APL Transmitter port
- APL3_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL3_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL3_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL3_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL3_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL3_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL3_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL3_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL3_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL3_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL3_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL3_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL3_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL3_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
-
- ----------------------------------------------------------------------------
- -- Common API stuff
- ----------------------------------------------------------------------------
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
-
- -- IOBUF ports missing -> Later (BUGBUG)
-
- APL_GOT_TRM : out STD_LOGIC_VECTOR (15 downto 0); --pattern from the
- --unused TERMs
- APL_HOLD_TRM: in STD_LOGIC_VECTOR (15 downto 0); --put to "0"
-
- ---------------------------------------------------------------------------
- -- Media direction port (directly to be connected to MII)
- ---------------------------------------------------------------------------
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (55 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (55 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- MED_MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
- );
-END trb_net_endpoint_3ch;
-
-architecture trb_net_endpoint_3ch_arch of trb_net_endpoint_3ch is
-
- component trb_net_io_multiplexer is
-
- generic (BUS_WIDTH : integer := 56;
- MULT_WIDTH : integer := 5);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- -- highest bits are mult.
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
-END component;
-
-component trb_net_active_apimbuf is
-
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3; -- or the replyibuf
- FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
- );
-END component;
-
-component trb_net_term_mbuf is
-
- generic (FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
- APL_GOT_TRM: out STD_LOGIC;
-
- APL_HOLD_TRM: in STD_LOGIC;
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
- );
-END component;
-
--- for the connection to the multiplexer
-signal MED_INIT_DATAREADY_OUT : STD_LOGIC;
-signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_INIT_READ_IN : STD_LOGIC;
-
-signal MED_INIT_DATAREADY_IN : STD_LOGIC;
-signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_INIT_READ_OUT : STD_LOGIC;
-
-signal MED_REPLY_DATAREADY_OUT : STD_LOGIC;
-signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_REPLY_READ_IN : STD_LOGIC;
-
-signal MED_REPLY_DATAREADY_IN : STD_LOGIC;
-signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_REPLY_READ_OUT : STD_LOGIC;
-
-signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (15 downto 0);
-signal m_DATA_OUT : STD_LOGIC_VECTOR (831 downto 0);
-signal m_READ_IN : STD_LOGIC_VECTOR (15 downto 0);
-
-signal m_DATAREADY_IN : STD_LOGIC_VECTOR (15 downto 0);
-signal m_DATA_IN : STD_LOGIC_VECTOR (831 downto 0);
-signal m_READ_OUT : STD_LOGIC_VECTOR (15 downto 0);
-
-begin
-
-
--- m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
--- m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
--- m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT;
--- m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT;
--- MED_INIT_READ_IN <= m_READ_IN(0);
--- MED_REPLY_READ_IN <= m_READ_IN(1);
-
--- MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
--- MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
--- MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0);
--- MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51);
--- m_READ_OUT(0) <= MED_INIT_READ_OUT;
--- m_READ_OUT(1) <= MED_REPLY_READ_OUT;
-
- G1: for channel in 0 to 15 generate
--------------------------------------------------------------------------------
--- loop over the channels
--------------------------------------------------------------------------------
- GEN_API1: if not (channel = API1_CHANNEL_NUMBER)
- and not (channel = API2_CHANNEL_NUMBER)
- and not (channel = API3_CHANNEL_NUMBER)
- generate
- -- make the term
- TERM: trb_net_term_mbuf
-
- generic map (FIFO_TERM_BUFFER_DEPTH => 0 )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET ,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_DATAREADY_OUT => m_DATAREADY_OUT(channel),
- MED_DATA_OUT => m_DATA_OUT(channel*52+51 downto channel*52),
- MED_READ_IN => m_READ_IN(channel),
-
- MED_DATAREADY_IN => m_DATAREADY_IN(channel),
- MED_DATA_IN => m_DATA_IN(channel*52+51 downto channel*52),
- MED_READ_OUT => m_READ_OUT(channel),
- MED_ERROR_IN => (others => '0'),
-
- APL_GOT_TRM => APL_GOT_TRM(channel),
-
- APL_HOLD_TRM => APL_HOLD_TRM(channel),
- APL_DTYPE_IN => (others => '0'),
- APL_ERROR_PATTERN_IN => (others => '0'),
-
- CTRL_GEN => (others => '0'),
- CTRL_LOCKED => (others => '0'),
- STAT_CTRL_INIT_BUFFER => (others => '0'),
- STAT_CTRL_REPLY_BUFFER=> (others => '0'),
-
- MPLEX_CTRL => APL_MPLEX_CTRL );
- end generate;
- end generate;
-
- MPLEX: trb_net_io_multiplexer
- generic map (BUS_WIDTH => 56,
- MULT_WIDTH => 4)
- port map (
- CLK => CLK,
- RESET => RESET ,
- CLK_EN => CLK_EN,
-
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_READ_OUT => MED_READ_OUT,
-
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_READ_IN => MED_READ_IN,
-
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_READ_IN =>m_READ_OUT,
-
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_READ_OUT =>m_READ_IN,
-
- CTRL => MED_MPLEX_CTRL
- );
-
-API1: trb_net_active_apimbuf
-
- generic map (INIT_DEPTH => API1_INIT_DEPTH,
- REPLY_DEPTH => API1_REPLY_DEPTH,
- FIFO_TO_INT_DEPTH => API1_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => API1_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
-
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_DATAREADY_OUT => m_DATAREADY_OUT(API1_CHANNEL_NUMBER),
- MED_DATA_OUT => m_DATA_OUT(API1_CHANNEL_NUMBER*52+51 downto API1_CHANNEL_NUMBER*52),
- MED_READ_IN => m_READ_IN(API1_CHANNEL_NUMBER),
-
- MED_DATAREADY_IN => m_DATAREADY_IN(API1_CHANNEL_NUMBER),
- MED_DATA_IN => m_DATA_IN(API1_CHANNEL_NUMBER*52+51 downto API1_CHANNEL_NUMBER*52),
- MED_READ_OUT => m_READ_OUT(API1_CHANNEL_NUMBER),
- MED_ERROR_IN => (others => '0'),
-
- -- APL Transmitter port
- APL_DATA_IN => APL1_DATA_IN,
- APL_WRITE_IN => APL1_WRITE_IN,
- APL_FIFO_FULL_OUT => APL1_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL1_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL1_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL1_ERROR_PATTERN_IN,
- APL_SEND_IN => APL1_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL1_TARGET_ADDRESS_IN,
-
- -- Receiver port
- APL_DATA_OUT => APL1_DATA_OUT,
- APL_TYP_OUT => APL1_TYP_OUT,
- APL_DATAREADY_OUT => APL1_DATAREADY_OUT,
- APL_READ_IN => APL1_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL1_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL1_SEQNR_OUT,
-
- CTRL_GEN => (others => '0'),
- CTRL_LOCKED => (others => '0'),
- STAT_CTRL_INIT_BUFFER => (others => '0'),
- STAT_CTRL_REPLY_BUFFER=> (others => '0'),
- MPLEX_CTRL => APL_MPLEX_CTRL
- );
-
-API2: trb_net_active_apimbuf
-
- generic map (INIT_DEPTH => API2_INIT_DEPTH,
- REPLY_DEPTH => API2_REPLY_DEPTH,
- FIFO_TO_INT_DEPTH => API2_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => API2_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
-
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_DATAREADY_OUT => m_DATAREADY_OUT(API2_CHANNEL_NUMBER),
- MED_DATA_OUT => m_DATA_OUT(API2_CHANNEL_NUMBER*52+51 downto API2_CHANNEL_NUMBER*52),
- MED_READ_IN => m_READ_IN(API2_CHANNEL_NUMBER),
-
- MED_DATAREADY_IN => m_DATAREADY_IN(API2_CHANNEL_NUMBER),
- MED_DATA_IN => m_DATA_IN(API2_CHANNEL_NUMBER*52+51 downto API2_CHANNEL_NUMBER*52),
- MED_READ_OUT => m_READ_OUT(API2_CHANNEL_NUMBER),
- MED_ERROR_IN => (others => '0'),
-
- -- APL Transmitter port
- APL_DATA_IN => APL2_DATA_IN,
- APL_WRITE_IN => APL2_WRITE_IN,
- APL_FIFO_FULL_OUT => APL2_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL2_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL2_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL2_ERROR_PATTERN_IN,
- APL_SEND_IN => APL2_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL2_TARGET_ADDRESS_IN,
-
- -- Receiver port
- APL_DATA_OUT => APL2_DATA_OUT,
- APL_TYP_OUT => APL2_TYP_OUT,
- APL_DATAREADY_OUT => APL2_DATAREADY_OUT,
- APL_READ_IN => APL2_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL2_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL2_SEQNR_OUT,
-
- CTRL_GEN => (others => '0'),
- CTRL_LOCKED => (others => '0'),
- STAT_CTRL_INIT_BUFFER => (others => '0'),
- STAT_CTRL_REPLY_BUFFER=> (others => '0'),
- MPLEX_CTRL => APL_MPLEX_CTRL
- );
-
-API3: trb_net_active_apimbuf
-
- generic map (INIT_DEPTH => API3_INIT_DEPTH,
- REPLY_DEPTH => API3_REPLY_DEPTH,
- FIFO_TO_INT_DEPTH => API3_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => API3_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
-
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_DATAREADY_OUT => m_DATAREADY_OUT(API3_CHANNEL_NUMBER),
- MED_DATA_OUT => m_DATA_OUT(API3_CHANNEL_NUMBER*52+51 downto API3_CHANNEL_NUMBER*52),
- MED_READ_IN => m_READ_IN(API3_CHANNEL_NUMBER),
-
- MED_DATAREADY_IN => m_DATAREADY_IN(API3_CHANNEL_NUMBER),
- MED_DATA_IN => m_DATA_IN(API3_CHANNEL_NUMBER*52+51 downto API3_CHANNEL_NUMBER*52),
- MED_READ_OUT => m_READ_OUT(API3_CHANNEL_NUMBER),
- MED_ERROR_IN => (others => '0'),
-
- -- APL Transmitter port
- APL_DATA_IN => APL3_DATA_IN,
- APL_WRITE_IN => APL3_WRITE_IN,
- APL_FIFO_FULL_OUT => APL3_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL3_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL3_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL3_ERROR_PATTERN_IN,
- APL_SEND_IN => APL3_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL3_TARGET_ADDRESS_IN,
-
- -- Receiver port
- APL_DATA_OUT => APL3_DATA_OUT,
- APL_TYP_OUT => APL3_TYP_OUT,
- APL_DATAREADY_OUT => APL3_DATAREADY_OUT,
- APL_READ_IN => APL3_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL3_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL3_SEQNR_OUT,
-
- CTRL_GEN => (others => '0'),
- CTRL_LOCKED => (others => '0'),
- STAT_CTRL_INIT_BUFFER => (others => '0'),
- STAT_CTRL_REPLY_BUFFER=> (others => '0'),
- MPLEX_CTRL => APL_MPLEX_CTRL
- );
-
-
-end trb_net_endpoint_3ch_arch;
-
+++ /dev/null
-
--- This is to be rewritten before it can be fully used. It is not approbriate
--- to use full apis in a hub - rewriting every header takes way too much time
--- and too much buffers
-
---LIMITATIONS:
---------------
--- long transfers are not transmitted, since the addresses do not match!
--- no check for fifo_full on active apis
--- seqnr are not synchronized
--- all outputs must be connected
-
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net_fanout_hub is
- generic(
- OUTPUT_PORTS : integer range 1 to 8 := 4
- );
- port(
- CLK: in std_logic;
- CLK_EN: in std_logic;
- RESET: in std_logic;
-
-
- STAT: out std_logic_vector(31 downto 0)
- );
-end entity;
-
-
-architecture trb_net_fanout_hub_arch of trb_net_fanout_hub is
-
-component trb_net_passive_apimbuf is
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3; -- or the replyibuf
- FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_api_control_signals: out std_logic_vector(31 downto 0);
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
- end component;
-
-component trb_net_active_apimbuf is
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3; -- or the replyibuf
- FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_api_control_signals: out std_logic_vector(31 downto 0);
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-type logic_1_array is array (OUTPUT_PORTS downto 0) of std_logic;
-type vector_3_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(2 downto 0);
-type vector_4_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(3 downto 0);
-type vector_8_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(7 downto 0);
-type vector_16_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(15 downto 0);
-type vector_32_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(31 downto 0);
-type vector_48_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(47 downto 0);
-type vector_52_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(51 downto 0);
-
---(0) of each array is the passive input api
---(x) all others are the active output apis
-
-
-signal MED_DATAREADY_OUT : logic_1_array;
-signal MED_DATA_OUT: vector_52_array;
-signal MED_READ_IN: logic_1_array;
-signal MED_DATAREADY_IN: logic_1_array;
-signal MED_DATA_IN: vector_52_array;
-signal MED_READ_OUT: logic_1_array;
-signal MED_ERROR_IN: vector_3_array;
-signal APL_DATA_IN: vector_48_array;
-signal APL_WRITE_IN: logic_1_array;
-signal APL_FIFO_FULL_OUT: logic_1_array;
-signal APL_SHORT_TRANSFER_IN:logic_1_array;
-signal APL_DTYPE_IN: vector_4_array;
-signal APL_ERROR_PATTERN_IN: vector_32_array;
-signal APL_SEND_IN: logic_1_array;
-signal APL_TARGET_ADDRESS_IN:vector_16_array;
-signal APL_DATA_OUT: vector_48_array;
-signal APL_TYP_OUT: vector_3_array;
-signal APL_DATAREADY_OUT: logic_1_array;
-signal APL_READ_IN: logic_1_array;
-signal APL_RUN_OUT: logic_1_array;
-signal APL_MY_ADDRESS_IN: vector_16_array;
-signal APL_SEQNR_OUT: vector_8_array;
-signal STAT_GEN: vector_32_array;
-signal STAT_LOCKED: vector_32_array;
-signal STAT_INIT_BUFFER: vector_32_array;
-signal STAT_REPLY_BUFFER: vector_32_array;
-signal STAT_api_control_signals: vector_32_array;
-signal CTRL_GEN: vector_32_array;
-signal CTRL_LOCKED: vector_32_array;
-signal STAT_CTRL_INIT_BUFFER: vector_32_array;
-signal STAT_CTRL_REPLY_BUFFER: vector_32_array;
-signal MPLEX_CTRL: vector_32_array;
-signal API_STAT_FIFO_TO_INT: vector_32_array;
-signal API_STAT_FIFO_TO_APL: vector_32_array;
-
-signal this_APL_RUN_OUT, last_APL_RUN_OUT : logic_1_array;
-signal APL_RUN_OUT_fallen, next_APL_RUN_OUT_fallen : logic_1_array;
-signal next_APL_SEND_IN : logic_1_array;
-
-
-
-begin
-
----------------------------------------
---generate all apis
----------------------------------------
-
- output_api: for i in 1 to OUTPUT_PORTS generate
- output_api: trb_net_active_apimbuf
- --no generic map, using defaults
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT(i),
- MED_DATA_OUT => MED_DATA_OUT(i),
- MED_READ_IN => MED_READ_IN(i),
- MED_DATAREADY_IN => MED_DATAREADY_IN(i),
- MED_DATA_IN => MED_DATA_IN(i),
- MED_READ_OUT => MED_READ_OUT(i),
- MED_ERROR_IN => MED_ERROR_IN(i),
- APL_DATA_IN => APL_DATA_IN(1),
- APL_WRITE_IN => APL_WRITE_IN(1),
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT(i),
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(1),
- APL_DTYPE_IN => APL_DTYPE_IN(1),
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN(1),
- APL_SEND_IN => APL_SEND_IN(1),
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN(1),
- APL_DATA_OUT => APL_DATA_OUT(i),
- APL_TYP_OUT => APL_TYP_OUT(i),
- APL_DATAREADY_OUT => APL_DATAREADY_OUT(i),
- APL_READ_IN => APL_READ_IN(1),
- APL_RUN_OUT => APL_RUN_OUT(i),
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN(1),
- APL_SEQNR_OUT => APL_SEQNR_OUT(i),
- STAT_GEN => STAT_GEN(i),
- STAT_LOCKED => STAT_LOCKED(i),
- STAT_INIT_BUFFER => STAT_INIT_BUFFER(i),
- STAT_REPLY_BUFFER => STAT_REPLY_BUFFER(i),
- STAT_api_control_signals => STAT_api_control_signals(i),
- CTRL_GEN => CTRL_GEN(i),
- CTRL_LOCKED => CTRL_LOCKED(i),
- STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER(i),
- STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER(i),
- MPLEX_CTRL => MPLEX_CTRL(i),
- API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT(i),
- API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL(i)
- );
- end generate;
-
-
- input_api: trb_net_passive_apimbuf
- --no generic map, using defaults
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT(0),
- MED_DATA_OUT => MED_DATA_OUT(0),
- MED_READ_IN => MED_READ_IN(0),
- MED_DATAREADY_IN => MED_DATAREADY_IN(0),
- MED_DATA_IN => MED_DATA_IN(0),
- MED_READ_OUT => MED_READ_OUT(0),
- MED_ERROR_IN => MED_ERROR_IN(0),
- ---
- APL_DATA_IN => APL_DATA_IN(0),
- APL_WRITE_IN => APL_WRITE_IN(0),
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT(0),
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(0),
- APL_DTYPE_IN => APL_DTYPE_IN(0),
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN(0),
- APL_SEND_IN => APL_SEND_IN(0),
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN(0),
- APL_DATA_OUT => APL_DATA_OUT(0),
- APL_TYP_OUT => APL_TYP_OUT(0),
- APL_DATAREADY_OUT => APL_DATAREADY_OUT(0),
- APL_READ_IN => APL_READ_IN(0),
- APL_RUN_OUT => APL_RUN_OUT(0),
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN(0),
- APL_SEQNR_OUT => APL_SEQNR_OUT(0),
- ---
- STAT_GEN => STAT_GEN(0),
- STAT_LOCKED => STAT_LOCKED(0),
- STAT_INIT_BUFFER => STAT_INIT_BUFFER(0),
- STAT_REPLY_BUFFER => STAT_REPLY_BUFFER(0),
- STAT_api_control_signals => STAT_api_control_signals(0),
- CTRL_GEN => CTRL_GEN(0),
- CTRL_LOCKED => CTRL_LOCKED(0),
- STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER(0),
- STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER(0),
- MPLEX_CTRL => MPLEX_CTRL(0),
- API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT(0),
- API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL(0)
- );
-
-
-
-
- APL_DATA_IN(1) <= (others => '0');
- APL_SHORT_TRANSFER_IN(1) <= '1';
- APL_SHORT_TRANSFER_IN(0) <= '1';
- APL_ERROR_PATTERN_IN(1) <= APL_DATA_OUT(0)(47 downto 16);
- APL_WRITE_IN(1) <= '0';
- APL_WRITE_IN(0) <= '0';
-
- APL_DTYPE_IN(1) <= APL_DATA_OUT(0)(3 downto 0);
- APL_SEND_IN(1) <= APL_DATAREADY_OUT(0);
- APL_TARGET_ADDRESS_IN(1) <= (others => '0');
- APL_READ_IN(1) <= '1';
- APL_READ_IN(0) <= '1';
- APL_MY_ADDRESS_IN(1) <= (others => '0');
-
---merge all errorpatterns
--------------------------
- process(APL_DATA_OUT)
- variable tmp : std_logic_vector(31 downto 0);
- begin
- tmp := (others => '0');
- for i in 1 to OUTPUT_PORTS loop
- tmp := tmp or APL_DATA_OUT(i)(47 downto 16);
- end loop;
- APL_ERROR_PATTERN_IN(0) <= tmp;
- end process;
-
-
---check for falling run_out for all output apis
------------------------------------------------
- process(last_APL_RUN_OUT, this_APL_RUN_OUT, APL_RUN_OUT_fallen)
- variable tmp : std_logic;
- begin
- next_APL_RUN_OUT_fallen <= APL_RUN_OUT_fallen;
- next_APL_SEND_IN(0) <= '0';
- for i in 1 to OUTPUT_PORTS loop
- if last_APL_RUN_OUT(i)= '1' and this_APL_RUN_OUT(i) = '0' then
- next_APL_RUN_OUT_fallen(i) <= '1';
- end if;
- end loop;
- tmp := '1';
- for i in 1 to OUTPUT_PORTS loop
- tmp := tmp and APL_RUN_OUT_fallen(i);
- end loop;
- if tmp = '1' then
- next_APL_SEND_IN(0) <= '1';
- next_APL_RUN_OUT_fallen <= (others => '0');
- end if;
- end process;
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- this_APL_RUN_OUT <= (others => '0');
- last_APL_RUN_OUT <= (others => '0');
- APL_RUN_OUT_fallen <= (others => '0');
- APL_SEND_IN(0) <= '0';
- else
- this_APL_RUN_OUT <= APL_RUN_OUT;
- last_APL_RUN_OUT <= this_APL_RUN_OUT;
- APL_RUN_OUT_fallen <= next_APL_RUN_OUT_fallen;
- APL_SEND_IN(0) <= next_APL_SEND_IN(0);
- end if;
- end if;
- end process;
-
-
-end architecture;
-
-
-
+++ /dev/null
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo
-
--- taken example from xapp256, but rewritten most of the parts
--- output fully synchonized with a "look-ahead" logic
-
-library ieee;
-
-use ieee.std_logic_1164.all;
-USE ieee.std_logic_signed.ALL;
-USE IEEE.numeric_std.ALL;
-use work.trb_net_std.all;
-
-
-architecture arch_trb_net_fifo of trb_net_fifo is
- component trb_net16_bram_fifo is
- port (clock_in: IN std_logic;
- read_enable_in: IN std_logic;
- write_enable_in: IN std_logic;
- write_data_in: IN std_logic_vector(17 downto 0);
- fifo_gsr_in: IN std_logic;
- read_data_out: OUT std_logic_vector(17 downto 0);
- full_out: OUT std_logic;
- empty_out: OUT std_logic;
- fifocount_out: OUT std_logic_vector(3 downto 0));
- end component;
-
- component shift_lut_x16
- generic (
- ADDRESS_WIDTH : integer := 0
- );
- port (
- D : in std_logic;
- CE : in std_logic;
- CLK : in std_logic;
- A : in std_logic_vector (ADDRESS_WIDTH+3 downto 0);
- Q : out std_logic
- );
- end component;
-
- signal current_ADDRESS_SRL : std_logic_vector(DEPTH+1 downto 0);
- signal next_ADDRESS_SRL : std_logic_vector(DEPTH+1 downto 0);
- signal real_ADDRESS_SRL : std_logic_vector(DEPTH+1 downto 0);
- signal current_DOUT : std_logic_vector(WIDTH -1 downto 0);
- signal next_DOUT : std_logic_vector(WIDTH -1 downto 0);
-
- signal current_FULL, next_FULL : std_logic;
- signal current_EMPTY, next_EMPTY : std_logic;
- signal do_shift, do_shift_internal : std_logic;
- signal fifocount : std_logic_vector(3 downto 0);
-
-begin
-
- gen_shiftreg : if DEPTH /= 8 or WIDTH /= 18 or FORCE_LUT = 1 generate
-
- FULL_OUT <= current_FULL;
- EMPTY_OUT <= current_EMPTY;
- do_shift <= do_shift_internal and CLK_EN;
-
-
- -- generate the shift registers
-
- inst_SRLC256E_MACRO : for i in 0 to (WIDTH - 1) generate
- U1 : shift_lut_x16
- generic map (
- ADDRESS_WIDTH => DEPTH - 3
- )
- port map (
- D => DATA_IN(i),
- CE => do_shift,
- CLK => CLK,
- A => real_ADDRESS_SRL(DEPTH downto 0),
- Q => next_DOUT(i));
- end generate;
-
- reg_counter: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_ADDRESS_SRL <= (others => '0');
- elsif CLK_EN = '1' then
- current_ADDRESS_SRL <= next_ADDRESS_SRL;
- else
- current_ADDRESS_SRL <= current_ADDRESS_SRL;
- end if;
- end if;
- end process;
-
- -- adress logic
- comb_counter: process(WRITE_ENABLE_IN, READ_ENABLE_IN, current_ADDRESS_SRL,
- current_EMPTY, current_FULL)
- begin
- do_shift_internal <= WRITE_ENABLE_IN and not current_FULL;
- next_ADDRESS_SRL <= current_ADDRESS_SRL;
- real_ADDRESS_SRL <= current_ADDRESS_SRL - 1;
-
- -- no activity
- if WRITE_ENABLE_IN = '0' and READ_ENABLE_IN = '0' then
- next_ADDRESS_SRL <= current_ADDRESS_SRL;
- real_ADDRESS_SRL <= current_ADDRESS_SRL - 1;
- -- read from FIFO
- elsif WRITE_ENABLE_IN = '0' and READ_ENABLE_IN = '1' then
- if current_EMPTY = '0' then
- next_ADDRESS_SRL <= current_ADDRESS_SRL - 1;
- real_ADDRESS_SRL <= current_ADDRESS_SRL - 2;
- end if;
- -- write into FIFO
- elsif WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '0' then
- if current_FULL = '0' then
- next_ADDRESS_SRL <= current_ADDRESS_SRL + 1;
- real_ADDRESS_SRL <= current_ADDRESS_SRL - 1;
- end if;
- -- read and write can be done in all cases
- elsif WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '1' then
- next_ADDRESS_SRL <= current_ADDRESS_SRL;
- real_ADDRESS_SRL <= current_ADDRESS_SRL - 2;
- end if;
- end process;
-
-
- -- registered read from FIFO
- reg_output: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_DOUT <= (others => '0');
- elsif CLK_EN = '1' then
- if current_EMPTY = '1' or real_ADDRESS_SRL(DEPTH+1) = '1' then
- current_DOUT <= DATA_IN;
- else
- current_DOUT <= next_DOUT;
- end if;
- end if;
- end if;
- end process;
-
- -- Comparator Block
- next_FULL <= next_ADDRESS_SRL(DEPTH+1);
- -- Empty flag is generated when reading from the last location
- next_EMPTY <= '1' when (next_ADDRESS_SRL(DEPTH+1 downto 0) = 0) else '0';
-
- reg_empty: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_EMPTY <= '1';
- current_FULL <= '0';
- elsif CLK_EN = '1' then
- current_EMPTY <= next_EMPTY;
- current_FULL <= next_FULL;
- else
- current_EMPTY <= current_EMPTY;
- current_FULL <= current_FULL;
- end if;
- end if;
- end process;
-
- FULL_OUT <= current_FULL;
- EMPTY_OUT <= current_EMPTY;
- DATA_OUT <= current_DOUT;
-
-
- -- generate the real depth which is at least 3
- -- 0 -> 2
- -- 1 -> 4
- -- 2 -> 8
- -- 3 -> 16
- CHECK_DEPTH1: if DEPTH>=3 generate
- DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8));
- end generate;
- CHECK_DEPTH2: if DEPTH<3 generate
- DEPTH_OUT <= x"03";
- end generate;
- end generate;
-
-
-
- gen_BRAM : if (DEPTH = 8 and WIDTH = 18) and FORCE_LUT = 0 generate
- bram_fifo:trb_net16_bram_fifo
- port map (
- clock_in => CLK,
- read_enable_in => READ_ENABLE_IN,
- write_enable_in => WRITE_ENABLE_IN,
- write_data_in => DATA_IN,
- fifo_gsr_in => RESET,
- read_data_out => DATA_OUT,
- full_out => FULL_OUT,
- empty_out => EMPTY_OUT,
- fifocount_out => fifocount
- );
-
- DEPTH_OUT <= (others => '1');
- end generate;
-
-
-end arch_trb_net_fifo;
-
-
+++ /dev/null
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_ibuf is
-
- generic (DEPTH : integer := 3); -- Depth of the FIFO, 2^(n+1)
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- Internal direction port
- INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header
- INT_DATAREADY_OUT: out STD_LOGIC;
- INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- Status and control port
- STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0)
- );
-end trb_net_ibuf;
-
-architecture trb_net_ibuf_arch of trb_net_ibuf is
-
-component trb_net_fifo is
-
- generic (WIDTH : integer := 8; -- FIFO word width
- DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1)
-
- port (CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic; -- Full Flag
- EMPTY_OUT : out std_logic;
- DEPTH_OUT : out std_logic_vector(7 downto 0)
- );
-
-end component;
-
- component trb_net_sbuf is
-
- generic (DATA_WIDTH : integer := 56;
- VERSION: integer := 0);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- -- Port to synchronous output.
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
-signal fifo_data_in : std_logic_vector(50 downto 0);
-signal fifo_data_out : std_logic_vector(50 downto 0);
-signal fifo_write, fifo_read : std_logic;
-signal fifo_full, fifo_empty : std_logic;
-signal fifo_depth : std_logic_vector(7 downto 0);
-
-signal next_read_out, reg_read_out : std_logic;
-
-signal got_ack_internal, reg_ack_internal : std_logic; --should be raised for 1 cycle when ack
- --arrived
-signal is_locked, got_locked,release_locked : std_logic;
-signal got_eob_out, reg_eob_out: std_logic;
-signal sbuf_free, comb_next_read: std_logic;
-signal tmp_INT_DATAREADY_OUT: std_logic;
-signal tmp_INT_DATA_OUT: std_logic_vector(50 downto 0);
-signal current_last_header, next_last_header : std_logic_vector(50 downto 0);
-
-type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_LOCKED_ERROR, GOT_UNDEFINED_ERROR);
-signal current_error_state, next_error_state : ERROR_STATE;
-
-signal next_rec_buffer_size_out, current_rec_buffer_size_out
- : std_logic_vector(3 downto 0); -- buffer size control
-
- begin
-
- FIFO: trb_net_fifo
- generic map (
- WIDTH => 51,
- DEPTH => DEPTH)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_data_in,
- WRITE_ENABLE_IN => fifo_write,
- DATA_OUT => fifo_data_out,
- READ_ENABLE_IN => fifo_read,
- FULL_OUT => fifo_full,
- EMPTY_OUT => fifo_empty,
- DEPTH_OUT => fifo_depth
- );
-
- fifo_data_in <= MED_DATA_IN;
-
--- this process controls the writing of the media into the fifo
- FILTER_DATAREADY_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_ERROR_IN,
- fifo_full, is_locked, current_rec_buffer_size_out,
- current_error_state, reg_read_out)
- begin -- process
- got_ack_internal <= '0';
- next_read_out <= '0';
- fifo_write <= '0';
- next_rec_buffer_size_out <= current_rec_buffer_size_out;
- next_error_state <= current_error_state;
-
- if MED_DATAREADY_IN = '1' and reg_read_out= '1' then
- if MED_DATA_IN(TYPE_POSITION) = TYPE_ACK then
- -- BUGBUG: this causes trouble if the IBUF is full -> ack sent even if buffer overflow
- got_ack_internal <= '1';
- if MED_DATA_IN(F1_POSITION) = F1_CHECK_ACK then
- next_rec_buffer_size_out <= MED_DATA_IN(BUFFER_SIZE_POSITION);
- end if;
- -- elsif fifo_full = '0' and is_locked = '0' then
- elsif fifo_full = '0' then -- still ACKs may come even when locked
- fifo_write <= '1';
- next_read_out <= '1';
- elsif fifo_full = '1' then
- next_error_state <= GOT_OVERFLOW_ERROR;
- elsif is_locked = '1' then
- next_error_state <= GOT_LOCKED_ERROR;
- end if; -- end TYPE
- end if; -- end MED_DATAREADY_IN
- if fifo_full = '0' then -- and is_locked = '0' then
- next_read_out <= '1';
- end if;
- end process;
-
- MED_READ_OUT <= reg_read_out;
-
- reg_buffer: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_rec_buffer_size_out <= (others => '0');
- reg_ack_internal <= '0';
- reg_read_out <= '0';
- current_error_state <= IDLE;
- elsif CLK_EN = '1' then
- current_rec_buffer_size_out <= next_rec_buffer_size_out;
- reg_ack_internal <= got_ack_internal;
- reg_read_out <= next_read_out;
- current_error_state <= next_error_state;
- else
- current_rec_buffer_size_out <= current_rec_buffer_size_out;
- reg_ack_internal <= reg_ack_internal;
- reg_read_out <= reg_read_out;
- current_error_state <= current_error_state;
- end if;
- end if;
- end process;
-
-
-
- SBUF: trb_net_sbuf
- generic map (DATA_WIDTH => 51, Version => 0)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => tmp_INT_DATAREADY_OUT,
- COMB_next_READ_OUT => comb_next_read,
- COMB_READ_IN => '1',
- COMB_DATA_IN => tmp_INT_DATA_OUT,
- SYN_DATAREADY_OUT => INT_DATAREADY_OUT,
- SYN_DATA_OUT => INT_DATA_OUT,
- SYN_READ_IN => INT_READ_IN
- );
-
- sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed
-
--- this process controls what will be forwarded to the internal point
- DATA_OUT : process (INT_HEADER_IN, fifo_data_out,
- current_last_header, INT_READ_IN,
- release_locked, is_locked, sbuf_free, fifo_empty)
- begin
- -- tmp_INT_DATA_OUT <= (others => '1');
- tmp_INT_DATA_OUT <= fifo_data_out;
- tmp_INT_DATAREADY_OUT <= '0';
- got_eob_out <= '0';
- fifo_read <= '0';
- got_locked <= is_locked;
- next_last_header <= current_last_header;
-
- if fifo_empty = '0' then
- if sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_DAT then
- -- next data word can be registered
- tmp_INT_DATAREADY_OUT <= '1';
- fifo_read <= '1';
- elsif sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_TRM then
- got_eob_out <= '1'; --exactly when buffer is killed
- tmp_INT_DATAREADY_OUT <= '1';
- if release_locked = '0' then
- got_locked <= '1';
- end if;
- fifo_read <= '1';
- elsif sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_HDR then
- next_last_header <= fifo_data_out;
- tmp_INT_DATAREADY_OUT <= '1';
- fifo_read <= '1';
- elsif fifo_data_out(TYPE_POSITION) = TYPE_EOB then
- fifo_read <= '1';
- got_eob_out <= '1';
- tmp_INT_DATAREADY_OUT <= '0';
- -- this should happen only one CLK cycle
- end if;
- else
- tmp_INT_DATAREADY_OUT <= '0';
- end if;
- end process;
-
---BUGBUG HDR retransmit needed
-
-release_locked <= CTRL_LOCKED(0);
-STAT_LOCKED(0) <= is_locked;
-STAT_LOCKED(15 downto 1) <= (others => '0');
-
-reg_locked: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- is_locked <= '0';
- reg_eob_out <= '0';
- current_last_header <= (others => '0');
- elsif CLK_EN = '1' then
- if release_locked = '1' then
- is_locked <= '0';
- else
- is_locked <= got_locked;
- end if;
- reg_eob_out <= got_eob_out;
- current_last_header <= next_last_header;
- else
- is_locked <= is_locked;
- reg_eob_out <= reg_eob_out;
- current_last_header <= current_last_header;
- end if;
- end if;
- end process;
-
-
-
--- make STAT_BUFFER
- STAT_BUFFER(3 downto 0) <= (fifo_depth(3 downto 0)-1); --divide by 2, since 2
- --buffers have to be stored
- STAT_BUFFER(7 downto 4) <= current_rec_buffer_size_out;
- STAT_BUFFER(8) <= reg_eob_out;
- STAT_BUFFER(9) <= reg_ack_internal;
-
- MAKE_ERROR_BITS : process(current_error_state)
- begin
- if current_error_state = IDLE then
- STAT_BUFFER(11 downto 10) <= "00";
- elsif current_error_state = GOT_OVERFLOW_ERROR then
- STAT_BUFFER(11 downto 10) <= "01";
- elsif current_error_state = GOT_LOCKED_ERROR then
- STAT_BUFFER(11 downto 10) <= "10";
- else
- STAT_BUFFER(11 downto 10) <= "11";
- end if;
- end process;
-
- STAT_BUFFER(31 downto 12) <= (others => '0');
-
-end trb_net_ibuf_arch;
-
+++ /dev/null
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net_io_multiplexer is
-
--- generic (BUS_WIDTH : integer := 56;
--- MULT_WIDTH : integer := 5);
- generic (BUS_WIDTH : integer := 16;
- MULT_WIDTH : integer := 1);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- -- highest bits are mult.
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
-end trb_net_io_multiplexer;
-
-architecture trb_net_io_multiplexer_arch of trb_net_io_multiplexer is
-
- component trb_net_pattern_gen is
-
- generic (MULT_WIDTH : integer := 3);
-
- port(
- INPUT_IN : in STD_LOGIC_VECTOR (MULT_WIDTH-1 downto 0);
- RESULT_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0)
- );
- end component;
-
- component trb_net16_sbuf is
- generic (
- DATA_WIDTH : integer := 16;
- NUM_WIDTH : integer := 2;
- VERSION : integer := 0
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN : in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
- -- Port to synchronous output.
- SYN_DATAREADY_OUT : out STD_LOGIC;
- SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
- SYN_READ_IN : in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER : out STD_LOGIC
- );
- end component;
-
- component trb_net_priority_arbiter is
-
- generic (WIDTH : integer := 16);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
- RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
-
- ENABLE : in std_logic;
- CTRL: in STD_LOGIC_VECTOR (31 downto 0)
- );
- end component;
-
- signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
- signal next_demux_dr, next_demux_dr_tmp: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
--- signal demux_read: STD_LOGIC; -- buffer is read out and killed
- signal current_MED_READ_OUT, next_MED_READ_OUT: STD_LOGIC;
--- signal sbuf_stat: STD_LOGIC_VECTOR (2*(2**MULT_WIDTH)-1 downto 0);
-
- signal tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
- signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
- signal mux_read, mux_enable, mux_next_READ: STD_LOGIC;
- signal current_mux_buffer: STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
-
-
-
- begin
-
-
--------------------------------------------------------------------------------
--- DEMUX
-------------------------------------------------------------------------------
- -- the simpler part is the demux
-
- G1: for i in 0 to 2**MULT_WIDTH-1 generate
- DEMUX_SBUF: trb_net16_sbuf
- generic map (DATA_WIDTH => BUS_WIDTH-MULT_WIDTH, VERSION => 0)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => next_demux_dr(i),
- COMB_next_READ_OUT => demux_next_READ(i),
- COMB_READ_IN => current_demux_READ(i),
- COMB_DATA_IN => MED_DATA_IN (BUS_WIDTH-MULT_WIDTH-1 downto 0),
- SYN_DATAREADY_OUT => INT_DATAREADY_OUT(i),
- SYN_DATA_OUT => INT_DATA_OUT ((BUS_WIDTH-MULT_WIDTH)*(i+1)-1 downto (BUS_WIDTH-MULT_WIDTH)*(i)),
- SYN_READ_IN => INT_READ_IN(i)
- );
- end generate;
-
- STAT(2 downto 0) <= MED_DATA_IN(50 downto 48);
-
- MED_READ_OUT <= current_MED_READ_OUT;
-
- comb_demux : process (next_demux_dr_tmp, demux_next_READ, INT_READ_IN,
- MED_DATAREADY_IN, current_MED_READ_OUT)
- begin -- process
- next_demux_dr <= (others => '0');
- current_demux_READ <= (others => '0');
- -- generate the READ_OUT
- next_MED_READ_OUT <= and_all(demux_next_READ or INT_READ_IN);
- -- (follow instruction on sbuf)
-
- current_demux_READ <= (others => '0');
- if current_MED_READ_OUT = '1' then
- current_demux_READ <= (others => '1');
- end if;
- if current_MED_READ_OUT = '1' and MED_DATAREADY_IN = '1' then
- next_demux_dr <= next_demux_dr_tmp; --enable DR on the sbufs
- end if;
- end process;
-
--- define next DRx
- DEFDR: trb_net_pattern_gen
- generic map (MULT_WIDTH => MULT_WIDTH)
- port map (
- INPUT_IN => MED_DATA_IN(BUS_WIDTH-1 downto (BUS_WIDTH-MULT_WIDTH)),
- RESULT_OUT => next_demux_dr_tmp -- this will have a 1 in ANY case
- );
-
- sync_demux : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_MED_READ_OUT <= '0';
- elsif CLK_EN = '1' then
- current_MED_READ_OUT <= next_MED_READ_OUT;
- else
- current_MED_READ_OUT <= current_MED_READ_OUT;
- end if;
- end if;
- end process;
-
-
--------------------------------------------------------------------------------
--- MUX part with arbitration scheme
--------------------------------------------------------------------------------
-ARBITER: trb_net_priority_arbiter
- generic map (WIDTH => 2**MULT_WIDTH)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- INPUT_IN => INT_DATAREADY_IN,
- RESULT_OUT => tmp_INT_READ_OUT,
- ENABLE => mux_enable,
- CTRL => CTRL
- );
-
--- process (tmp_tmp_INT_READ_OUT, mux_enable)
--- begin
--- if mux_enable = '1' then
--- tmp_INT_READ_OUT <= tmp_tmp_INT_READ_OUT;
--- else
--- tmp_INT_READ_OUT <= (others => '0');
--- end if;
--- end process;
-
--- <= so I have to gate it once more
-INT_READ_OUT <= tmp_INT_READ_OUT;
-
-
-
- MUX_SBUF: trb_net_sbuf
- generic map (DATA_WIDTH => BUS_WIDTH, VERSION => 0)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => mux_read,
- COMB_next_READ_OUT => mux_next_READ,
- COMB_READ_IN => '1',
- COMB_DATA_IN => current_mux_buffer,
- SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
- SYN_DATA_OUT => MED_DATA_OUT,
- SYN_READ_IN => MED_READ_IN
- );
-
-process (tmp_INT_READ_OUT, INT_DATA_IN)
- begin
- current_mux_buffer <= (others => '0');
- for i in 0 to 2**MULT_WIDTH-1 loop
- if tmp_INT_READ_OUT(i) = '1' then
- current_mux_buffer(BUS_WIDTH-MULT_WIDTH-1 downto 0)
- <= INT_DATA_IN((BUS_WIDTH-MULT_WIDTH)*(i+1)-1 downto (BUS_WIDTH-MULT_WIDTH)*(i));
- current_mux_buffer(BUS_WIDTH-1 downto BUS_WIDTH-MULT_WIDTH) <= conv_std_logic_vector(i, MULT_WIDTH);
- end if;
- end loop;
- end process;
-
- mux_enable <= (mux_next_READ); -- or MED_READ_IN
- mux_read <= or_all(tmp_INT_READ_OUT and INT_DATAREADY_IN);
-
-end trb_net_io_multiplexer_arch;
-
+++ /dev/null
--- main working horse for the trbnet
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIOBUF
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_iobuf is
-
- generic (
- SWITCH_OFF_BUFFER_CHECK : integer := 0;
- --switching off erroneous output buffer counter. MUST ONLY be
- --used for short transfers!!!!
- INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3); -- or the replyibuf
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out STD_LOGIC;
- INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_IN: in STD_LOGIC;
-
- INT_INIT_DATAREADY_IN: in STD_LOGIC;
- INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_OUT: out STD_LOGIC;
-
-
- INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
- INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_IN: in STD_LOGIC;
-
- INT_REPLY_DATAREADY_IN: in STD_LOGIC;
- INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_OUT: out STD_LOGIC;
-
- -- Status and control port
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
- );
-END trb_net_iobuf;
-
-architecture trb_net_iobuf_arch of trb_net_iobuf is
-
- component trb_net_ibuf is
-
- generic (DEPTH : integer := 3); -- Depth of the FIFO, 2^(n+1)
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- Internal direction port
- INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header
- INT_DATAREADY_OUT: out STD_LOGIC;
- INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- Status and control port
- STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0)
- );
- END component;
-
- component trb_net_term_ibuf is
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- Internal direction port
- INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header
- INT_DATAREADY_OUT: out STD_LOGIC;
- INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- Status and control port
- STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0)
- );
- END component;
-
- component trb_net_obuf is
- generic (
- DATA_COUNT_WIDTH : integer := 4;
- SWITCH_OFF_BUFFER_CHECK : integer := 0
- --switching off erroneous output buffer counter. MUST ONLY be
- --used for short transfers!!!!
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC;
- -- Internal direction port
- INT_DATAREADY_IN: in STD_LOGIC;
- INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_OUT: out STD_LOGIC;
- -- Status and control port
- STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
- );
- END component;
-
- -- internal signals for the INITIBUF
- signal INITIBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed!
- signal INITIBUF_stat_locked, INITIBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0);
- signal INITIBUF_stat_buffer : STD_LOGIC_VECTOR (31 downto 0);
-
- -- internal signals for the REPLYIBUF
- signal REPLYIBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed!
- signal REPLYIBUF_stat_locked, REPLYIBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0);
- signal REPLYIBUF_stat_buffer : STD_LOGIC_VECTOR (31 downto 0);
-
- -- internal signals for the INITOBUF
- signal INITOBUF_stat_locked, INITOBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0);
- signal INITOBUF_stat_buffer, INITOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0);
-
- -- internal signals for the REPLYOBUF
- signal REPLYOBUF_stat_locked, REPLYOBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0);
- signal REPLYOBUF_stat_buffer, REPLYOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0);
-
--- locking control
- signal INIT_IS_LOCKED, REPLY_IS_LOCKED: STD_LOGIC;
- signal next_INIT_IS_LOCKED, next_REPLY_IS_LOCKED: STD_LOGIC;
-
- begin
-
- GEN_IBUF: if INIT_DEPTH>0 generate
-
- INITIBUF : trb_net_ibuf
- generic map (
- DEPTH => INIT_DEPTH)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_INIT_DATAREADY_IN,
- MED_DATA_IN => MED_INIT_DATA_IN,
- MED_READ_OUT => MED_INIT_READ_OUT,
- MED_ERROR_IN => MED_INIT_ERROR_IN,
- INT_HEADER_IN => '0',
- INT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
- INT_DATA_OUT => INT_INIT_DATA_OUT,
- INT_READ_IN => INT_INIT_READ_IN,
- INT_ERROR_OUT => INITIBUF_error,
- STAT_LOCKED(15 downto 0) => INITIBUF_stat_locked,
- CTRL_LOCKED(15 downto 0) => INITIBUF_ctrl_locked,
- STAT_BUFFER(31 downto 0) => INITIBUF_stat_buffer
- );
-
- REPLYIBUF : trb_net_ibuf
- generic map (
- DEPTH => REPLY_DEPTH)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
- MED_DATA_IN => MED_REPLY_DATA_IN,
- MED_READ_OUT => MED_REPLY_READ_OUT,
- MED_ERROR_IN => MED_REPLY_ERROR_IN,
- INT_HEADER_IN => INT_REPLY_HEADER_IN,
- INT_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
- INT_DATA_OUT => INT_REPLY_DATA_OUT,
- INT_READ_IN => INT_REPLY_READ_IN,
- INT_ERROR_OUT => REPLYIBUF_error,
- STAT_LOCKED(15 downto 0) => REPLYIBUF_stat_locked,
- CTRL_LOCKED(15 downto 0) => REPLYIBUF_ctrl_locked,
- STAT_BUFFER(31 downto 0) => REPLYIBUF_stat_buffer
- );
-
- end generate;
-
- GEN_TERM_IBUF: if INIT_DEPTH=0 generate
-
- INITIBUF : trb_net_term_ibuf
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_INIT_DATAREADY_IN,
- MED_DATA_IN => MED_INIT_DATA_IN,
- MED_READ_OUT => MED_INIT_READ_OUT,
- MED_ERROR_IN => MED_INIT_ERROR_IN,
- INT_HEADER_IN => '0',
- INT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
- INT_DATA_OUT => INT_INIT_DATA_OUT,
- INT_READ_IN => INT_INIT_READ_IN,
- INT_ERROR_OUT => INITIBUF_error,
- STAT_LOCKED(15 downto 0) => INITIBUF_stat_locked,
- CTRL_LOCKED(15 downto 0) => INITIBUF_ctrl_locked,
- STAT_BUFFER(31 downto 0) => INITIBUF_stat_buffer
- );
-
- REPLYIBUF : trb_net_term_ibuf
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
- MED_DATA_IN => MED_REPLY_DATA_IN,
- MED_READ_OUT => MED_REPLY_READ_OUT,
- MED_ERROR_IN => MED_REPLY_ERROR_IN,
- INT_HEADER_IN => INT_REPLY_HEADER_IN,
- INT_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
- INT_DATA_OUT => INT_REPLY_DATA_OUT,
- INT_READ_IN => INT_REPLY_READ_IN,
- INT_ERROR_OUT => REPLYIBUF_error,
- STAT_LOCKED(15 downto 0) => REPLYIBUF_stat_locked,
- CTRL_LOCKED(15 downto 0) => REPLYIBUF_ctrl_locked,
- STAT_BUFFER(31 downto 0) => REPLYIBUF_stat_buffer
- );
-
- end generate;
-
- INITOBUF : trb_net_obuf
- generic map (
- DATA_COUNT_WIDTH => 16,
- SWITCH_OFF_BUFFER_CHECK => SWITCH_OFF_BUFFER_CHECK
- --switching off erroneous output buffer counter. MUST ONLY be
- --used for short transfers!!!!
- )
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
- MED_DATA_OUT => MED_INIT_DATA_OUT,
- MED_READ_IN => MED_INIT_READ_IN,
- INT_DATAREADY_IN => INT_INIT_DATAREADY_IN,
- INT_DATA_IN => INT_INIT_DATA_IN,
- INT_READ_OUT => INT_INIT_READ_OUT,
- STAT_LOCKED(15 downto 0) => INITOBUF_stat_locked,
- CTRL_LOCKED(15 downto 0) => INITOBUF_ctrl_locked,
- STAT_BUFFER(31 downto 0) => INITOBUF_stat_buffer,
- CTRL_BUFFER(31 downto 0) => INITOBUF_ctrl_buffer
- );
-
- REPLYOBUF : trb_net_obuf
- generic map (
- DATA_COUNT_WIDTH => 16,
- SWITCH_OFF_BUFFER_CHECK => SWITCH_OFF_BUFFER_CHECK
- --switching off erroneous output buffer counter. MUST ONLY be
- --used for short transfers!!!!
- )
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
- MED_DATA_OUT => MED_REPLY_DATA_OUT,
- MED_READ_IN => MED_REPLY_READ_IN,
- INT_DATAREADY_IN => INT_REPLY_DATAREADY_IN,
- INT_DATA_IN => INT_REPLY_DATA_IN,
- INT_READ_OUT => INT_REPLY_READ_OUT,
- STAT_LOCKED(15 downto 0) => REPLYOBUF_stat_locked,
- CTRL_LOCKED(15 downto 0) => REPLYOBUF_ctrl_locked,
- STAT_BUFFER(31 downto 0) => REPLYOBUF_stat_buffer,
- CTRL_BUFFER(31 downto 0) => REPLYOBUF_ctrl_buffer
- );
-
--- build the registers according to the wiki page
- STAT_INIT_BUFFER(11 downto 0) <= INITIBUF_stat_buffer(11 downto 0);
- STAT_INIT_BUFFER(15 downto 14) <= INITOBUF_stat_buffer(1 downto 0);
- STAT_INIT_BUFFER(31 downto 16) <= INITOBUF_stat_buffer(31 downto 16);
- STAT_REPLY_BUFFER(11 downto 0) <= REPLYIBUF_stat_buffer(11 downto 0);
- STAT_REPLY_BUFFER(15 downto 14) <= REPLYOBUF_stat_buffer(1 downto 0);
- STAT_REPLY_BUFFER(31 downto 16) <= REPLYOBUF_stat_buffer(31 downto 16);
-
--- build the CTRL register of the OBUFs
- INITOBUF_ctrl_buffer(9 downto 0) <= INITIBUF_stat_buffer(9 downto 0);
- INITOBUF_ctrl_buffer(31 downto 10) <= (others => '0');
- REPLYOBUF_ctrl_buffer(9 downto 0) <= REPLYIBUF_stat_buffer(9 downto 0);
- REPLYOBUF_ctrl_buffer(31 downto 10) <= (others => '0');
-
- STAT_LOCKED(0) <= INIT_IS_LOCKED;
- STAT_LOCKED(1) <= REPLY_IS_LOCKED;
- STAT_LOCKED(31 downto 2) <= (others => '0');
-
- REPLYOBUF_ctrl_locked(15 downto 2) <= (others => '0');
- REPLYIBUF_ctrl_locked(15 downto 2) <= (others => '0');
- INITOBUF_ctrl_locked(15 downto 2) <= (others => '0');
- INITIBUF_ctrl_locked(15 downto 2) <= (others => '0');
-
- -- comb part of the locking control
-comb_locked : process (INIT_IS_LOCKED, REPLY_IS_LOCKED, INITIBUF_stat_locked,
- REPLYOBUF_stat_locked, REPLYIBUF_stat_locked,
- INITOBUF_stat_locked, CTRL_LOCKED)
-
- begin -- process
- next_INIT_IS_LOCKED <= INIT_IS_LOCKED;
- next_REPLY_IS_LOCKED <= REPLY_IS_LOCKED;
- REPLYOBUF_ctrl_locked(1 downto 0) <= (others => '0');
- REPLYIBUF_ctrl_locked(1 downto 0) <= (others => '0');
- INITOBUF_ctrl_locked(1 downto 0) <= (others => '0');
- INITIBUF_ctrl_locked(1 downto 0) <= (others => '0');
-
- if REPLY_IS_LOCKED = '1' then
- -- listen to INITOBUF
- if INITOBUF_stat_locked(0) = '1' or CTRL_LOCKED(1) = '1' then
- next_REPLY_IS_LOCKED <= '0';
- REPLYIBUF_ctrl_locked(0) <= '1';
- else
- next_REPLY_IS_LOCKED <= '1';
- end if;
- else
- -- listen to REPLYIBUF itself
- if REPLYIBUF_stat_locked(0) = '1' then
- next_REPLY_IS_LOCKED <= '1';
- INITOBUF_ctrl_locked(0) <= '1';
- else
- next_REPLY_IS_LOCKED <= '0';
- end if;
- end if;
-
- if INIT_IS_LOCKED = '1' then
- -- listen to REPLYOBUF
- if REPLYOBUF_stat_locked(0) = '1' or CTRL_LOCKED(0) = '1' then
- next_INIT_IS_LOCKED <= '0';
- INITIBUF_ctrl_locked(0) <= '1';
- else
- next_INIT_IS_LOCKED <= '1';
- end if;
- else
- -- listen to INITIBUF itself
- if INITIBUF_stat_locked(0) = '1' then
- next_INIT_IS_LOCKED <= '1';
- REPLYOBUF_ctrl_locked(0) <= '1';
- else
- next_INIT_IS_LOCKED <= '0';
-
- end if;
- end if;
-
- end process;
-
- reg_locked: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- INIT_IS_LOCKED <= '0';
- REPLY_IS_LOCKED <= '1';
- elsif CLK_EN = '1' then
- INIT_IS_LOCKED <= next_INIT_IS_LOCKED;
- REPLY_IS_LOCKED <= next_REPLY_IS_LOCKED;
- else
- INIT_IS_LOCKED <= INIT_IS_LOCKED;
- REPLY_IS_LOCKED <= REPLY_IS_LOCKED;
- end if;
- end if;
- end process;
-
-
-
-
-end trb_net_iobuf_arch;
-
+++ /dev/null
---This entity provides data transfer (64bit) via a smaller (16bit) Bus
---with three bits for debugging (13bit data + 3bit control)
---first 56bit via Bus are for dataword, transmitted Bits 64 downto 56 Bits
---are for debugging
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.trb_net_std.all;
-
-entity trb_net_med_13bit_slow is
-generic(
- TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 2 --even values only!
- );
-
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Internal direction port (MII)
- -- do not change this interface!!!
- -- 1st part: from the medium to the internal logic (trbnet)
- INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media
- --and ready to be read out (the IOBUF MUST read)
- INT_DATA_OUT: out STD_LOGIC_VECTOR (55 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- 2nd part: from the internal logic (trbnet) to the medium
- INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media
- INT_DATA_IN: in STD_LOGIC_VECTOR (55 downto 0); -- Data word
- INT_READ_OUT: out STD_LOGIC; -- offered word is read
- INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- (end do not change this interface!!!)
-
-
- -- Media direction port
- -- in this case for the cable => 32 lines in total
- MED_DATA_OUT: out STD_LOGIC_VECTOR (12 downto 0); -- Data word
- --(incl. debugging errorbits)
- MED_TRANSMISSION_CLK_OUT: out STD_LOGIC;
- MED_CARRIER_OUT: out STD_LOGIC;
- MED_PARITY_OUT: out STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (12 downto 0); -- Data word
- MED_TRANSMISSION_CLK_IN: in STD_LOGIC;
- MED_CARRIER_IN: in STD_LOGIC;
- MED_PARITY_IN: in STD_LOGIC;
-
- -- Status and control port => this never can hurt
- STAT: out STD_LOGIC_VECTOR (31 downto 0);
- --STAT(0): Busy reading from media
- --STAT(1): Busy writing to media
- --STAT(31 downto 28): packets_in (mod 16)
- --STAT(27 downto 24): packets_out (mod 16)
- --STAT(11 downto 8): INT2MED state
- --STAT(15 downto 12): MED2INT state
-
- CTRL: in STD_LOGIC_VECTOR (31 downto 0)
- --CTRL(24..31) -> lvds-data(63 downto 56) via lvds
- --once for each packet
-
- );
-end trb_net_med_13bit_slow;
-
-architecture trb_net_med_13bit_slow_arch of trb_net_med_13bit_slow is
- signal INT2MED_state, next_INT2MED_state : std_logic_vector (3 downto 0);
-
- type MED2INT_STATE_t is (IDLE, RECV2, RECV3, RECV4, RECV5);
- signal MED2INT_state, next_MED2INT_state: MED2INT_STATE_t;
-
- signal DAT_MED2INT, next_DAT_MED2INT :std_logic_vector(51 downto 0);
- signal buf_INT_DATA_IN, next_buf_INT_DATA_IN :std_logic_vector(55 downto 0);
-
- signal next_INT_DATA_OUT, buf_INT_DATA_OUT: std_logic_vector(55 downto 0);
- signal next_buf_MED_DATA_OUT, buf_MED_DATA_OUT: std_logic_vector(12 downto 0);
- signal next_INT_DATAREADY_OUT, buf_INT_DATAREADY_OUT: std_logic;
- signal next_buf_INT_READ_OUT, buf_INT_READ_OUT: std_logic;
-
- signal buf_MED_TRANSMISSION_CLK_OUT: std_logic;
- signal buf_MED_CARRIER_OUT, next_MED_CARRIER_OUT: STD_LOGIC;
- signal buf_MED_PARITY_OUT, next_MED_PARITY_OUT: STD_LOGIC;
- signal my_error,next_my_error : std_logic_vector(2 downto 0);
- signal fatal_error, media_not_connected : std_logic;
- signal next_media_not_connected : std_logic;
- signal transmission_clk_Counter : std_logic_vector(4 downto 0);
- signal next_transmission_clk_Counter : std_logic_vector(4 downto 0);
- signal next_TRANSMISSION_CLK: std_logic;
- signal buf_CTRL, next_STAT, buf_STAT : std_logic_vector(31 downto 0);
- signal next_RECV_STAT, RECV_STAT : std_logic_vector(8 downto 0);
-
- signal last_TRCLK, this_TRCLK: std_logic;
- signal CLK_counter,next_CLK_counter: std_logic_vector(7 downto 0);
-
- signal packets_in_counter, next_packets_in_counter: std_logic_vector(7 downto 0);
- signal packets_in_compl_counter, next_packets_in_compl_counter: std_logic_vector(3 downto 0);
- signal packets_out_counter, next_packets_out_counter: std_logic_vector(3 downto 0);
-
- signal last_MED_TRANSMISSION_CLK_IN : std_logic;
- signal reg_MED_DATA_IN : std_logic_vector(12 downto 0);
- signal reg_MED_TRANSMISSION_CLK_IN, reg_MED_CARRIER_IN : std_logic;
- signal reg_MED_PARITY_IN : std_logic;
- signal med2int_state_sig :std_logic_vector(2 downto 0);
-
-begin
-INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
-INT_DATA_OUT <= buf_INT_DATA_OUT(55 downto 0);
-INT_ERROR_OUT <= my_error;
-INT_READ_OUT <= buf_INT_READ_OUT;
-STAT <= buf_STAT;
-
-MED_DATA_OUT(12 downto 0) <= buf_MED_DATA_OUT;
-MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT;
-MED_CARRIER_OUT <= buf_MED_CARRIER_OUT;
-MED_PARITY_OUT <= buf_MED_PARITY_OUT;
-
-
---TODO:
---------------------------------
-fatal_error <= '0';
-
-
-
---Status word
---------------------------------
-gen_STAT_WORD: process(MED2INT_state,INT2MED_state,buf_INT_DATAREADY_OUT,RECV_STAT,buf_STAT)
- begin
- next_STAT <= (others => '0');
- if MED2INT_state = IDLE then
- next_STAT(0) <= '0';
- else
- next_STAT(0) <= '1';
- end if;
- if INT2MED_state = 0 then
- next_STAT(1) <= '0';
- else
- next_STAT(1) <= '1';
- end if;
- next_STAT(11 downto 8) <= INT2MED_state;
- --next_STAT(15 downto 12) <= MED2INT_state;
- next_STAT(16) <= media_not_connected;
- next_STAT(31 downto 24) <= packets_in_counter;
- --next_STAT(27 downto 24) <= packets_in_compl_counter;
- if buf_INT_DATAREADY_OUT = '1' then
- next_STAT(24 downto 16) <= RECV_STAT(8 downto 0);
- else
- next_STAT(24 downto 16) <= buf_STAT(24 downto 16);
- end if;
- end process;
-
-STAT_reg: process (CLK,RESET)
- begin
- if RESET = '1' then
- buf_STAT <= (others => '0');
- elsif rising_edge(CLK) then
- buf_STAT <= next_STAT;
- else
- buf_STAT <= buf_STAT;
- end if;
- end process;
-
-
---CTRL register
---------------------------------
-CTRL_reg: process (CLK,RESET)
- begin
- if RESET = '1' then
- buf_CTRL <= (others => '0');
- elsif rising_edge(CLK) then
- buf_CTRL <= CTRL;
- --buf_CTRL(31 downto 24) <= packets_in_counter;
- --buf_CTRL(27 downto 24) <= packets_in_compl_counter;
- else
- buf_CTRL <= buf_CTRL;
- end if;
- end process;
-
-
-
---My error bits
---------------------------------
-gen_my_error: process(media_not_connected,fatal_error)
- begin
- if media_not_connected = '1' then
- next_my_error <= "100";
- elsif fatal_error = '1' then
- next_my_error <= "011";
- else
- next_my_error <= "000";
- end if;
- end process;
-
-
-reg_my_error: process(CLK,RESET)
- begin
- if RESET = '1' then
- my_error <= "000";
- elsif rising_edge(CLK) then
- my_error <= next_my_error;
- else
- my_error <= my_error;
- end if;
- end process;
-
-
---Transmission clock generator
---------------------------------
-trans_clk_counter: process (transmission_clk_Counter, buf_MED_TRANSMISSION_CLK_OUT)
- begin
- if transmission_clk_Counter = (TRANSMISSION_CLOCK_DIVIDER/2) - 1 then
- next_transmission_clk_Counter <= (others => '0');
- next_TRANSMISSION_CLK <= not buf_MED_TRANSMISSION_CLK_OUT;
- else
- next_transmission_clk_Counter <= transmission_clk_Counter + 1;
- next_TRANSMISSION_CLK <= buf_MED_TRANSMISSION_CLK_OUT;
- end if;
- end process;
-
-
-trans_clk_counter_reg: process (CLK,RESET)
- begin
- if RESET = '1' then
- transmission_clk_Counter <= (others => '0');
- buf_MED_TRANSMISSION_CLK_OUT <= '0';
- elsif rising_edge(CLK) then
- transmission_clk_Counter <= next_transmission_clk_Counter;
- buf_MED_TRANSMISSION_CLK_OUT <= next_TRANSMISSION_CLK;
- else
- transmission_clk_Counter <= transmission_clk_Counter;
- buf_MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT;
- end if;
- end process;
-
-
-
---Transmission Clock detection
---------------------------------
-trans_clk_reg: process (RESET,CLK)
- begin
- if RESET = '1' then
- last_TRCLK <= '0';
- this_TRCLK <= '0';
- CLK_counter <= (others => '0');
- media_not_connected <= '0';
- elsif rising_edge(CLK) then
- last_TRCLK <= this_TRCLK;
- this_TRCLK <= MED_TRANSMISSION_CLK_IN;
- CLK_counter <= next_CLK_counter;
- media_not_connected <= next_media_not_connected;
- else
- last_TRCLK <= last_TRCLK;
- this_TRCLK <= this_TRCLK;
- CLK_counter <= CLK_counter;
- media_not_connected <= media_not_connected;
- end if;
- end process;
-
-
-
-transCLK_counter: process (this_TRCLK, last_TRCLK, CLK_counter,
- buf_MED_DATA_OUT, buf_MED_CARRIER_OUT,
- buf_MED_PARITY_OUT, buf_CTRL)
- begin
- next_media_not_connected <= '0';
- if last_TRCLK = '0' and this_TRCLK = '1' then
- next_CLK_counter <= (others => '0');
- elsif CLK_counter = 255 then
- next_media_not_connected <= '1';
- next_CLK_counter <= CLK_counter;
- else
- next_CLK_counter <= CLK_counter + 1;
- end if;
- end process;
-
-
-
-
---INT to MED direction
---------------------------------
-INT2MED_fsm: process(buf_INT_DATA_IN,INT2MED_state,
- INT_DATAREADY_IN, INT_DATA_IN, buf_INT_READ_OUT,
- next_TRANSMISSION_CLK, buf_MED_TRANSMISSION_CLK_OUT, buf_MED_DATA_OUT,
- buf_MED_CARRIER_OUT, buf_MED_PARITY_OUT, buf_CTRL)
- variable tmp: std_logic_vector(12 downto 0);
-begin
- next_INT2MED_state <= "0000";
- next_buf_MED_DATA_OUT <= buf_MED_DATA_OUT;
- next_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT;
- next_MED_PARITY_OUT <= buf_MED_PARITY_OUT;
- next_buf_INT_DATA_IN <= buf_INT_DATA_IN;
- next_buf_INT_READ_OUT <= buf_INT_READ_OUT;
-
- next_packets_out_counter <= packets_out_counter;
- case INT2MED_state is
- when "0000" =>
- if INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then
- --generate data word to transmit
- next_buf_INT_DATA_IN(55 downto 0) <= INT_DATA_IN(55 downto 0);
- next_INT2MED_state <= "0001";
- next_buf_INT_READ_OUT <= '0';
- next_packets_out_counter <= packets_out_counter + 1;
- else
- next_buf_INT_READ_OUT <= '1';
- next_MED_CARRIER_OUT <= '0';
- next_MED_PARITY_OUT <= '0';
- end if;
- when "0001" =>
- if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then
- next_buf_MED_DATA_OUT(12 downto 0) <= buf_INT_DATA_IN(12 downto 0);
- next_MED_CARRIER_OUT <= '1';
- next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN(12 downto 0));
- next_INT2MED_state <= "0010";
- else
- next_INT2MED_state <= "0001";
- end if;
- when "0010" =>
- if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then
- next_buf_MED_DATA_OUT(12 downto 0) <= buf_INT_DATA_IN(25 downto 13);
- next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN(25 downto 13));
- next_INT2MED_state <= "0100";
- else
- next_INT2MED_state <= "0010";
- end if;
- when "0100" =>
- if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then
- next_buf_MED_DATA_OUT(12 downto 0) <= buf_INT_DATA_IN(38 downto 26);
- next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN(38 downto 26));
- next_INT2MED_state <= "0110";
- else
- next_INT2MED_state <= "0100";
- end if;
- when "0110" =>
- if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then
- next_buf_MED_DATA_OUT(12 downto 0) <= buf_INT_DATA_IN(51 downto 39);
- next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN(51 downto 39));
- next_INT2MED_state <= "1000";
- else
- next_INT2MED_state <= "0110";
- end if;
- when "1000" =>
- if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then
-
- tmp(3 downto 0) := buf_INT_DATA_IN(55 downto 52);
- tmp(11 downto 4) := buf_CTRL(31 downto 24);
- tmp(12) := buf_CTRL(0);
-
- next_buf_MED_DATA_OUT <= tmp;
- next_MED_PARITY_OUT <= xor_all(tmp);
- next_INT2MED_state <= "1110";
- else
- next_INT2MED_state <= "1000";
- end if;
- when "1110" =>
- if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then
- next_INT2MED_state <= "0000";
- next_MED_CARRIER_OUT <= '0';
- next_buf_MED_DATA_OUT <= (others => '0');
- else
- next_INT2MED_state <= "1110";
- end if;
- when others =>
- next_INT2MED_state <= "0000";
- end case;
-end process;
-
-
-INT2MED_fsm_reg: process(CLK,RESET)
- begin
- if RESET='1' then
- buf_MED_DATA_OUT <= (others => '0');
- INT2MED_state <= "0000";
- buf_INT_DATA_IN <= (others => '0');
- buf_INT_READ_OUT <= '0';
- buf_MED_CARRIER_OUT <= '0';
- buf_MED_PARITY_OUT <= '0';
- packets_out_counter <= (others => '0');
- elsif rising_edge(CLK) then
- INT2MED_state <= next_INT2MED_state;
- buf_INT_DATA_IN <= next_buf_INT_DATA_IN;
- buf_INT_READ_OUT <= next_buf_INT_READ_OUT;
- buf_MED_DATA_OUT(12 downto 0) <= next_buf_MED_DATA_OUT(12 downto 0);
- buf_MED_CARRIER_OUT <= next_MED_CARRIER_OUT;
- buf_MED_PARITY_OUT <= next_MED_PARITY_OUT;
- packets_out_counter <= next_packets_out_counter;
- else
- buf_MED_DATA_OUT <= buf_MED_DATA_OUT;
- buf_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT;
- buf_MED_PARITY_OUT <= buf_MED_PARITY_OUT;
- INT2MED_state <= INT2MED_state;
- buf_INT_READ_OUT <= buf_INT_READ_OUT;
- buf_INT_DATA_IN <= buf_INT_DATA_IN;
- packets_out_counter <= packets_out_counter;
- end if;
- end process;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
---MED to INT direction
---------------------------------
-
-MED2INT_fsm: process(reg_MED_PARITY_IN,MED2INT_state,CLK,reg_MED_DATA_IN,DAT_MED2INT,
- reg_MED_TRANSMISSION_CLK_IN,reg_MED_CARRIER_IN,INT_READ_IN, RECV_STAT,
- media_not_connected,buf_INT_DATAREADY_OUT, buf_INT_DATA_OUT, last_MED_TRANSMISSION_CLK_IN
- )
- begin
- next_DAT_MED2INT <= DAT_MED2INT;
- next_INT_DATA_OUT <= buf_INT_DATA_OUT;
- next_INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
- next_MED2INT_state <= IDLE;
- next_RECV_STAT <= RECV_STAT;
- next_packets_in_counter <= packets_in_counter;
- next_packets_in_compl_counter <= packets_in_compl_counter;
-
- case MED2INT_state is
- when IDLE =>
- if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then
- next_MED2INT_state <= RECV2;
- next_DAT_MED2INT(12 downto 0) <= reg_MED_DATA_IN(12 downto 0);
- end if;
- when RECV2 =>
- if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then
- next_MED2INT_state <= RECV3;
- next_DAT_MED2INT(25 downto 13) <= reg_MED_DATA_IN(12 downto 0);
- else
- next_MED2INT_state <= RECV2;
- end if;
- when RECV3 =>
- if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then
- next_MED2INT_state <= RECV4;
- next_DAT_MED2INT(38 downto 26) <= reg_MED_DATA_IN(12 downto 0);
- else
- next_MED2INT_state <= RECV3;
- end if;
- when RECV4 =>
- if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then
- next_MED2INT_state <= RECV5;
- next_DAT_MED2INT(51 downto 39) <= reg_MED_DATA_IN(12 downto 0);
- else
- next_MED2INT_state <= RECV4;
- end if;
- when RECV5 =>
- if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then
- next_INT_DATA_OUT(51 downto 0) <= DAT_MED2INT(51 downto 0);
- next_INT_DATA_OUT(55 downto 52) <= reg_MED_DATA_IN(3 downto 0);
- next_RECV_STAT <= reg_MED_DATA_IN(12 downto 4);
- next_INT_DATAREADY_OUT <= '1';
- next_MED2INT_state <= IDLE;
- next_packets_in_counter <= packets_in_counter + 1;
- else
- next_MED2INT_state <= RECV5;
- end if;
- when others =>
- next_MED2INT_state <= IDLE;
- end case;
-
- --clear dataready when read
- if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then
- next_INT_DATAREADY_OUT <= '0';
- next_INT_DATA_OUT <= (others => '0');
- end if;
-
- --check parity
- if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' then
- if(xor_all(reg_MED_DATA_IN(12 downto 0)) /= reg_MED_PARITY_IN) then
- next_MED2INT_state <= IDLE;
- end if;
- end if;
-
- --reset on Carrier low
--- if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '0' then
--- next_MED2INT_state <= IDLE;
--- end if;
-
- --reset on not connected
- if media_not_connected = '1' then
- next_MED2INT_state <= IDLE;
- end if;
- end process;
-
-
-process(MED2INT_state)
-begin
- case MED2INT_state is
- when IDLE => med2int_state_sig <= "000";
- when RECV2 => med2int_state_sig <= "001";
- when RECV3 => med2int_state_sig <= "010";
- when RECV4 => med2int_state_sig <= "011";
- when RECV5 => med2int_state_sig <= "100";
- end case;
-end process;
-
-
-MED2INT_fsm_reg: process(CLK,RESET)
- begin
- if RESET='1' then
- MED2INT_state <= IDLE;
- buf_INT_DATAREADY_OUT <= '0';
- DAT_MED2INT <= (others => '0');
- buf_INT_DATA_OUT <= (others => '0');
- RECV_STAT <= (others => '0');
- packets_in_counter <= (others => '0');
- packets_in_compl_counter <= (others => '0');
- last_MED_TRANSMISSION_CLK_IN <= '1';
- elsif rising_edge(CLK) then
- DAT_MED2INT <= next_DAT_MED2INT;
- MED2INT_state <= next_MED2INT_state;
- buf_INT_DATA_OUT <= next_INT_DATA_OUT;
- buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT;
- RECV_STAT <= next_RECV_STAT;
- packets_in_counter <= next_packets_in_counter;
- packets_in_compl_counter <= next_packets_in_compl_counter;
- last_MED_TRANSMISSION_CLK_IN <= reg_MED_TRANSMISSION_CLK_IN;
- else
- buf_INT_DATA_OUT <= buf_INT_DATA_OUT;
- MED2INT_state <= MED2INT_state;
- buf_INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
- DAT_MED2INT <= DAT_MED2INT;
- RECV_STAT <= RECV_STAT;
- packets_in_counter <= packets_in_counter;
- packets_in_compl_counter <= packets_in_compl_counter;
- last_MED_TRANSMISSION_CLK_IN <= last_MED_TRANSMISSION_CLK_IN;
- end if;
- end process;
-
-LVDS_IN_reg: process(CLK, RESET)
- begin
- if RESET='1' then
- reg_MED_TRANSMISSION_CLK_IN <= '0';
- reg_MED_CARRIER_IN <= '0';
- reg_MED_PARITY_IN <= '0';
- reg_MED_DATA_IN <= (others => '0');
- elsif rising_edge(CLK) then
- reg_MED_TRANSMISSION_CLK_IN <= MED_TRANSMISSION_CLK_IN;
- reg_MED_CARRIER_IN <= MED_CARRIER_IN;
- reg_MED_PARITY_IN <= MED_PARITY_IN;
- reg_MED_DATA_IN <= MED_DATA_IN;
- else
- reg_MED_TRANSMISSION_CLK_IN <= reg_MED_TRANSMISSION_CLK_IN;
- reg_MED_CARRIER_IN <= reg_MED_CARRIER_IN;
- reg_MED_PARITY_IN <= reg_MED_PARITY_IN;
- reg_MED_DATA_IN <= reg_MED_DATA_IN;
- end if;
- end process;
-
-
-end trb_net_med_13bit_slow_arch;
-
+++ /dev/null
--- media interface for the 32 lvds lines (16 in each direction)
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/NewTriggerBusMedia
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net_med_32lvds is
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Internal direction port (MII)
- -- do not change this interface!!!
- -- 1st part: from the medium to the internal logic (trbnet)
- INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media
- --and ready to be read out
- INT_DATA_OUT: out STD_LOGIC_VECTOR (55 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- 2nd part: from the internal logic (trbnet) to the medium
- INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read)
- INT_DATA_IN: in STD_LOGIC_VECTOR (55 downto 0); -- Data word
- INT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- (end do not change this interface!!!)
-
-
- -- Media direction port
- -- in this case for the cable => 32 lines in total
- MED_DATA_OUT: out STD_LOGIC_VECTOR (12 downto 0); -- Data word
- MED_TRANSMISSION_CLK_OUT: out STD_LOGIC;
- MED_CARRIER_OUT: out STD_LOGIC;
- MED_PARITY_OUT: out STD_LOGIC;
- MED_DATA_IN: out STD_LOGIC_VECTOR (12 downto 0); -- Data word
- MED_TRANSMISSION_CLK_IN: out STD_LOGIC;
- MED_CARRIER_IN: out STD_LOGIC;
- MED_PARITY_IN: out STD_LOGIC;
-
- -- Status and control port => this never can hurt
- STAT: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- );
-END trb_net_med_32lvds;
+++ /dev/null
---This entity provides data transfer of 55Bit in 4 16Bit packets via a 16Bit Bus
---with 8Bit data width plus 4 control Bits.
---data is repacked to have 8 spare Bits in the end of each word instead on the
---beginning. These Bits may be used for data integrity check later.
---The remaining four Bits on the LVDS cable are free to use at moment but should
---be reserved.
-
--------------------------------------------------
---format on LVDS: 0-7 Data
--- 8-10 free
--- 11 "handshake"
--- 12 first packet indicator
--- 13 transmission clock
--- 14 carrier
--- 15 parity(0-7)
--------------------------------------------------
-
--- "handshake": if this is low, you can not send, if it goes down during a transfer,
--- then probably some data is lost
-
---Please check the timing report for setup/hold-errors on the receiving ports
---In case of an error, adjust the PHASE_SHIFT of the DCM. A change of one unit
---results in a shift of (CLK_PERIOD/256)
---If the timing seems to be correct but the trbnet trb_net doesn't react, try
---shifting the clock by 180 degrees.
-
---Version with spare bits at end, using 18_to16 was 1.8
---
--- Constraints for timing on hadcom dev board:
--- NET "LVDS_IN<13>" TNM_NET = LVDS_IN_CLK_GRP;
--- TIMESPEC "TS_LVDS_IN" = PERIOD LVDS_IN_CLK_GRP 10 ns HIGH 50 %;
--- INST "LVDS_IN<*>" TNM = "IN_DDR";
--- INST "LVDS_OUT<*>" TNM = "OUT_DDR";
--- INST lvds1/buf_MED_IN_fal* TNM = "falling_reg";
--- TIMEGRP "OUT_DDR" OFFSET = OUT 8 ns AFTER "CLK_IN";
--- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 BEFORE "LVDS_IN<13>";
--- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 BEFORE "LVDS_IN<13>" TIMEGRP "falling_reg";
-
-
---Constraints for timing on acromag:
--- #Constraints for LVDS
--- NET "IO59_29P" TNM_NET = LVDS_IN_CLK_GRP;
--- TIMESPEC "TS_LVDS_IN" = PERIOD LVDS_IN_CLK_GRP 10 ns HIGH 50 %;
---
--- INST "io*_*p" TNM = "IN_DDR";
--- INST "io*_*n" TNM = "OUT_DDR";
--- INST trbnetendpoint1/lvds1/buf_MED_IN_fal* TNM = "falling_reg";
---
--- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 ns BEFORE "IO59_29P";
--- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 ns BEFORE "IO59_29P" TIMEGRP "falling_reg";
--- TIMEGRP "OUT_DDR" OFFSET = OUT 6.7 ns AFTER "FPGA_CLK";
-
-
-
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-library unisim;
-use UNISIM.VComponents.all;
-library work;
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_med_8bit_fast is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- 1st part: from the medium to the internal logic (trbnet)
- INT_DATAREADY_OUT: out STD_LOGIC;
- INT_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word
- INT_PACKET_NR_OUT: out STD_LOGIC_VECTOR (1 downto 0);
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- -- 2nd part: from the internal logic (trbnet) to the medium
- INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media
- INT_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word
- INT_PACKET_NR_IN: in STD_LOGIC_VECTOR (1 downto 0);
- INT_READ_OUT: out STD_LOGIC; -- offered word is read
- INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- -- Media direction port
- -- in this case for the cable => 32 lines in total
- MED_DATA_OUT: out STD_LOGIC_VECTOR (12 downto 0); -- Data word
- MED_TRANSMISSION_CLK_OUT: out STD_LOGIC;
- MED_CARRIER_OUT: out STD_LOGIC;
- MED_PARITY_OUT: out STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (12 downto 0); -- Data word
- MED_TRANSMISSION_CLK_IN: in STD_LOGIC;
- MED_CARRIER_IN: in STD_LOGIC;
- MED_PARITY_IN: in STD_LOGIC;
-
- -- Status and control port => this never can hurt
-
- STAT: out STD_LOGIC_VECTOR(31 downto 0);
- --31-16 show the current lvds data output (two times eight bit)
- CTRL: in STD_LOGIC_VECTOR (31 downto 0)
- );
-end entity;
-
-architecture trb_net_med_8bit_fast_arch of trb_net_med_8bit_fast is
-
-component dualdatarate_flipflop
- generic(
- WIDTH : integer := 1
- );
- port(
- C0 : in std_logic;
- C1 : in std_logic;
- CE : in std_logic;
- CLR : in std_logic;
- D0 : in std_logic_vector(WIDTH-1 downto 0);
- D1 : in std_logic_vector(WIDTH-1 downto 0);
- PRE : in std_logic;
- Q : out std_logic_vector(WIDTH-1 downto 0)
- );
-end component;
-
-
-component trb_net_fifo_16bit_bram_dualport
- port (read_clock_in: IN std_logic;
- write_clock_in: IN std_logic;
- read_enable_in: IN std_logic;
- write_enable_in: IN std_logic;
- fifo_gsr_in: IN std_logic; --reset
- write_data_in: IN std_logic_vector(17 downto 0);
- read_data_out: OUT std_logic_vector(17 downto 0);
- full_out: OUT std_logic;
- empty_out: OUT std_logic;
- fifostatus_out: OUT std_logic_vector(3 downto 0)
- );
-end component trb_net_fifo_16bit_bram_dualport;
-
-
- component trb_net_sbuf
- generic (DATA_WIDTH : integer := 16;
- VERSION: integer := 0);
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- -- Port to synchronous output.
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
- component FDDRCPE
- port (
- Q : out STD_ULOGIC;
- C0 : in STD_ULOGIC;
- C1 : in STD_ULOGIC;
- CE : in STD_ULOGIC;
- CLR : in STD_ULOGIC;
- D0 : in STD_ULOGIC;
- D1 : in STD_ULOGIC;
- PRE : in STD_ULOGIC);
- end component;
-
-signal CLK_TRANS : std_logic;
-signal fifo_data_in, next_fifo_data_in : std_logic_vector(17 downto 0);
-signal fifo_data_out : std_logic_vector(17 downto 0);
-signal fifo_full_out, fifo_empty_out : std_logic;
-signal fifo_status_out : std_logic_vector(3 downto 0);
-signal fifo_write_enable, next_fifo_write_enable : std_logic;
-signal fifo_read_enable, last_fifo_read_enable : std_logic;
-
-signal buf_MED_PARITY_OUT : std_logic;
-signal buf_MED_CARRIER_OUT : std_logic;
-signal buf_MED_TRANSMISSION_CLK_OUT : std_logic;
-signal buf_MED_TRANSMISSION_CLK_IN : std_logic;
-signal buf_MED_DATA_OUT : std_logic_vector(12 downto 0);
-signal buf_MED_IN_fal : std_logic_vector(15 downto 0);
-signal buf_MED_IN : std_logic_vector(31 downto 0);
-
-signal buf_INT_DATA_OUT : std_logic_vector(17 downto 0);
-signal buf_INT_DATAREADY_OUT : std_logic;
-signal next_int_packet_nr_out, buf_int_packet_nr_out : std_logic_vector(1 downto 0);
-signal next_send_data_byte1, send_data_byte1 : std_logic_vector(7 downto 0);
-signal next_send_data_byte2, send_data_byte2 : std_logic_vector(7 downto 0);
-signal next_send_data_byte1_parity, send_data_byte1_parity : std_logic;
-signal next_send_data_byte2_parity, send_data_byte2_parity : std_logic;
-signal next_send_dataready, send_dataready : std_logic;
-signal next_send_packet1, send_packet1 : std_logic;
-signal fifo_data_ready : std_logic;
-
-signal buf_int_error_out, next_INT_ERROR_OUT : std_logic_vector(2 downto 0);
-signal buf_INT_READ_OUT : std_logic;
-signal FB_CLK, CLK_FB_Out, CLK_RECV_Out : std_logic;
-signal sbuff_status : std_logic;
-signal sbuff_next_read_out : std_logic;
-signal buf_comb_data_in : std_logic_vector(17 downto 0);
-
-signal DCM_LOCKED, RESET_RECV, next_RESET_RECV : std_logic;
-begin
-
------------------------------------------------------------------------
--- Fifo for incoming data
------------------------------------------------------------------------
- LVDS_FIFO1 : trb_net_fifo_16bit_bram_dualport
- port map(
- read_clock_in => CLK,
- write_clock_in => CLK_TRANS,
- read_enable_in => fifo_read_enable,
- write_enable_in => fifo_write_enable,
- fifo_gsr_in => RESET_RECV,
- write_data_in => fifo_data_in,
- read_data_out => fifo_data_out,
- full_out => fifo_full_out,
- empty_out => fifo_empty_out,
- fifostatus_out => fifo_status_out
- );
-
-
-
-
------------------------------------------------------------------------
--- Getting clock from LVDS
------------------------------------------------------------------------
-
-
-U_DCM_RECV: DCM
- generic map(
- CLKIN_PERIOD => 10.00, -- 30.30ns
- STARTUP_WAIT => FALSE,
- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
- PHASE_SHIFT => 70,
- CLKOUT_PHASE_SHIFT => "FIXED"
- )
- port map (
- CLKIN => MED_TRANSMISSION_CLK_IN,
- CLKFB => FB_CLK,
- DSSEN => '0',
- PSINCDEC => '0',
- PSEN => '0',
- PSCLK => '0',
- RST => RESET,
- CLK0 => CLK_FB_Out, -- for feedback
- CLK180=> CLK_RECV_Out,
- LOCKED => DCM_LOCKED
- );
---
-U3_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);
---U4_BUFG: BUFG port map (I => CLK_RECV_Out, O => CLK_TRANS);
-CLK_TRANS <= FB_CLK;
-
------------------------------------------------------------------------
--- Preparing incoming data for fifo
------------------------------------------------------------------------
-
- recv : process(buf_MED_IN)
- begin
- next_fifo_data_in(7 downto 0) <= buf_MED_IN(7 downto 0);
- next_fifo_data_in(15 downto 8) <= buf_MED_IN(23 downto 16);
- next_fifo_data_in(17) <= ((buf_MED_IN(15) xnor xor_all(buf_MED_IN(7 downto 0))) or not buf_MED_IN(14)) and
- ((buf_MED_IN(31) xnor xor_all(buf_MED_IN(23 downto 16))) or not buf_MED_IN(30));
- --parity check
- next_fifo_data_in(16) <= buf_MED_IN(12); --first packet
- next_fifo_write_enable <= buf_MED_IN(14); --carrier
- end process;
-
-
- recv_reg : process(CLK_TRANS, RESET_RECV)
- begin
- if RESET_RECV = '1' then
- fifo_write_enable <= '0';
- fifo_data_in(15 downto 0) <= (others => '0');
- fifo_data_in(17) <= '0';
- elsif rising_edge(CLK_TRANS) then
- fifo_write_enable <= next_fifo_write_enable;
- fifo_data_in <= next_fifo_data_in;
- else
- fifo_write_enable <= fifo_write_enable;
- fifo_data_in <= fifo_data_in;
- end if;
- end process;
-
------------------------------------------------------------------------
--- Reading data from LVDS
------------------------------------------------------------------------
-
-
- lvds_reg_rising : process(CLK_TRANS, RESET_RECV)
- begin
- if RESET_RECV = '1' then
- buf_MED_IN(31 downto 0) <= (others => '0');
- elsif rising_edge(CLK_TRANS) then
- buf_MED_IN(14) <= MED_CARRIER_IN;
- buf_MED_IN(15) <= MED_PARITY_IN;
- buf_MED_IN(13) <= '0';
- buf_MED_IN(12 downto 0) <= MED_DATA_IN;
- buf_MED_IN(31 downto 16) <= buf_MED_IN_fal;
- else
- buf_MED_IN <= buf_MED_IN;
- end if;
- end process;
-
- lvds_reg_falling : process(CLK_TRANS, RESET_RECV)
- begin
- if RESET_RECV = '1' then
- buf_MED_IN_fal(15 downto 0) <= (others => '0');
- elsif falling_edge(CLK_TRANS) and MED_CARRIER_IN = '1' then
- buf_MED_IN_fal(14) <= MED_CARRIER_IN;
- buf_MED_IN_fal(15) <= MED_PARITY_IN;
- buf_MED_IN_fal(13) <= '1';
- buf_MED_IN_fal(12 downto 0) <= MED_DATA_IN;
- else
- buf_MED_IN_fal <= buf_MED_IN_fal;
- end if;
- end process;
-
------------------------------------------------------------------------
--- Reading data from fifo, offering to INT
------------------------------------------------------------------------
-
- process(sbuff_next_read_out, fifo_empty_out, last_fifo_read_enable,
- fifo_data_out, buf_int_packet_nr_out, DCM_LOCKED)
- begin
- fifo_read_enable <= sbuff_next_read_out and not fifo_empty_out;
- next_int_error_out <= ERROR_OK;
-
- if last_fifo_read_enable = '1' and fifo_data_out(16) = '1' then
- next_int_packet_nr_out <= "00";
- elsif last_fifo_read_enable = '1' then
- next_int_packet_nr_out <= buf_int_packet_nr_out + 1;
- else
- next_int_packet_nr_out <= buf_int_packet_nr_out;
- end if;
-
- if last_fifo_read_enable = '1' then
- --next_int_data_out <= fifo_data_out(15 downto 0);
- --next_int_dataready_out <= '1';
-
- if fifo_data_out(17) = '0' then
- next_int_error_out <= ERROR_FATAL;
- else
- next_int_error_out <= ERROR_OK;
- end if;
- if fifo_data_out(16) = '1' and buf_int_packet_nr_out /= "11" then
- next_int_error_out <= ERROR_ENCOD;
- end if;
- end if;
- if DCM_LOCKED = '0' then --without a locked clock -> no transmission possible
- next_int_error_out <= ERROR_NC;
- end if;
- end process;
-
- process(CLK,RESET_RECV)
- begin
- if rising_edge(CLK) then
- if RESET_RECV = '1' then
- last_fifo_read_enable <= '0';
- buf_int_error_out <= ERROR_NC;
- buf_int_packet_nr_out <= "00";
- else
- last_fifo_read_enable <= fifo_read_enable;
- buf_int_error_out <= next_int_error_out;
- buf_int_packet_nr_out <= next_int_packet_nr_out;
- end if;
- end if;
- end process;
-
-buf_comb_data_in(15 downto 0) <= fifo_data_out(15 downto 0);
-buf_comb_data_in(17 downto 16) <= next_int_packet_nr_out;
-
-
- SBUF_fifo_to_int : trb_net_sbuf
- generic map(DATA_WIDTH => 18, VERSION => 0)
- port map (
- CLK => CLK,
- RESET => RESET_RECV,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => last_fifo_read_enable,
- COMB_next_READ_OUT => sbuff_next_read_out,
- COMB_READ_IN => '1',
- COMB_DATA_IN => buf_comb_data_in,
- -- Port to synchronous output.
- SYN_DATAREADY_OUT => buf_INT_DATAREADY_OUT,
- SYN_DATA_OUT => buf_INT_DATA_OUT,
- SYN_READ_IN => INT_READ_IN,
- -- Status and control port
- STAT_BUFFER => sbuff_status
- );
-
-
-INT_DATA_OUT <= buf_int_data_out(15 downto 0);
-INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
-INT_PACKET_NR_OUT <= buf_int_data_out(17 downto 16);
-INT_ERROR_OUT <= buf_int_error_out;
-
-
------------------------------------------------------------------------
--- Sending data
------------------------------------------------------------------------
-
-buf_INT_READ_OUT <= not RESET_RECV;
-INT_READ_OUT <= buf_INT_READ_OUT;
---RESET_RECV <= RESET or not DCM_LOCKED or not MED_DATA_IN(11);
-
- process(RESET,DCM_LOCKED,MED_DATA_IN(11))
- begin
- if DCM_LOCKED = '0' or not MED_DATA_IN(11) = '1' then
- next_RESET_RECV <= '1';
- else
- next_RESET_RECV <= '0';
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- RESET_RECV <= '1';
- else
- RESET_RECV <= next_RESET_RECV;
- end if;
- end if;
- end process;
-
-
- process(INT_DATAREADY_IN, INT_DATA_IN, INT_PACKET_NR_IN, buf_INT_READ_OUT,
- send_data_byte1, send_data_byte2, send_packet1)
- begin
-
- next_send_dataready <= '0';
- next_send_data_byte1 <= (others => '0'); --send_data_byte1;
- next_send_data_byte2 <= (others => '0'); --send_data_byte2;
- next_send_data_byte1_parity <= '0'; --send_data_byte1_parity;
- next_send_data_byte2_parity <= '0'; --send_data_byte2_parity;
- next_send_packet1 <= '0';
- if INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then
- if INT_PACKET_NR_IN = "00" and send_packet1 = '0' then
- next_send_packet1 <= '1';
- else
- next_send_packet1 <= '0';
- end if;
- next_send_data_byte1 <= INT_DATA_IN(15 downto 8);
- next_send_data_byte2 <= INT_DATA_IN(7 downto 0);
- next_send_dataready <= '1';
- next_send_data_byte2_parity <= xor_all(INT_DATA_IN(7 downto 0));
- next_send_data_byte1_parity <= xor_all(INT_DATA_IN(15 downto 8));
- end if;
- end process;
-
- process(CLK, RESET_RECV)
- begin
- if rising_edge(CLK) then
- if RESET_RECV = '1' then
- send_data_byte1 <= (others => '0');
- send_data_byte2 <= (others => '0');
- send_data_byte1_parity <= '0';
- send_data_byte2_parity <= '0';
- send_dataready <= '0';
- send_packet1 <= '0';
- else
- send_data_byte1 <= next_send_data_byte1 after 1 ns;
- send_data_byte2 <= next_send_data_byte2 after 1 ns;
- send_data_byte1_parity <= next_send_data_byte1_parity after 1 ns;
- send_data_byte2_parity <= next_send_data_byte2_parity after 1 ns;
- send_dataready <= next_send_dataready after 1 ns;
- send_packet1 <= next_send_packet1 after 1 ns;
- end if;
- end if;
- end process;
-
-ddr_ff_dat : dualdatarate_flipflop
- generic map(
- WIDTH => 8
- )
- port map(
- Q => buf_MED_DATA_OUT(7 downto 0),
- C0 => CLK,
- C1 => not CLK,
- CE => '1',
- CLR => '0',
- D0 => send_data_byte2,
- D1 => send_data_byte1,
- PRE => '0'
- );
-
-ddr_ff_parity : dualdatarate_flipflop
- generic map(
- WIDTH => 1
- )
- port map(
- Q(0) => buf_MED_PARITY_OUT,
- C0 => CLK,
- C1 => not CLK,
- CE => '1',
- CLR => '0',
- D0(0) => send_data_byte2_parity,
- D1(0) => send_data_byte1_parity,
- PRE => '0'
- );
-
-ddr_ff_clk : dualdatarate_flipflop
- generic map(
- WIDTH => 1
- )
- port map(
- Q(0) => buf_MED_TRANSMISSION_CLK_OUT,
- C0 => CLK,
- C1 => not CLK,
- CE => '1',
- CLR => '0',
- D0(0) => '1',
- D1(0) => '0',
- PRE => '0'
- );
-
- process(CLK, RESET_RECV)
- begin
- if RESET_RECV = '1' then
- buf_MED_DATA_OUT(12) <= '0';
- buf_MED_CARRIER_OUT <= '0';
- elsif falling_edge(CLK) then
- buf_MED_DATA_OUT(12) <= send_packet1;
- buf_MED_CARRIER_OUT <= send_dataready;
- else
- buf_MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12);
- buf_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT;
- end if;
- end process;
-
-buf_MED_DATA_OUT(11 downto 8) <= "0000";
-
------------------------------------------------------------------------
--- Output generation
------------------------------------------------------------------------
-STAT(23 downto 16) <= send_data_byte1;
-STAT(31 downto 24) <= send_data_byte2;
-STAT(15 downto 0) <= (others => '0');
-
-MED_PARITY_OUT <= buf_MED_PARITY_OUT;
-MED_CARRIER_OUT <= buf_MED_CARRIER_OUT;
-MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT;
-MED_DATA_OUT(8 downto 0) <= buf_MED_DATA_OUT(8 downto 0);
-MED_DATA_OUT(9) <= RESET_RECV;
-MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12);
-
---MED_DATA_OUT(8) <= '0';
---MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12);
---MED_DATA_OUT(9 downto 8) <= buf_int_packet_nr_out;
---MED_DATA_OUT(11 downto 10) <= CONV_PACKET_NR_OUT;
---MED_DATA_OUT(9) <= CLK_TRANS;
---MED_DATA_OUT(8) <= buf_MED_TRANSMISSION_CLK_IN;
-MED_DATA_OUT(10) <= fifo_data_in(0);
-MED_DATA_OUT(11) <= (DCM_LOCKED);-- or (fifo_data_in(17) and not RESET_RECV);
--- MED_DATA_OUT(10) <= CLK_TRANS;
--- MED_DATA_OUT(11) <= fifo_write_enable;
-
-end architecture;
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net_med_8bit_slow is
- generic(
- TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 2 --even values only!
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Internal direction port (MII)
- INT_DATAREADY_OUT : out STD_LOGIC;
- INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN : in STD_LOGIC;
- INT_DATAREADY_IN : in STD_LOGIC;
- INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT : out STD_LOGIC;
- -- Media direction port
- MED_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
- MED_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
- -- Status and control port
- STAT: out STD_LOGIC_VECTOR (31 downto 0);
- --STAT(5 downto 2): Debug bits in
-
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_OP : out std_logic_vector(15 downto 0);
- CTRL_OP : in std_logic_vector(15 downto 0)
- );
-end entity trb_net_med_8bit_slow;
-
-architecture trb_net_med_8bit_slow_arch of trb_net_med_8bit_slow is
-
- signal buf_INT_DATA_IN, next_buf_INT_DATA_IN :std_logic_vector(7 downto 0);
-
- signal next_INT_DATA_OUT, buf_INT_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal next_INT_PACKET_NUM_OUT, buf_INT_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal next_INT_DATAREADY_OUT, buf_INT_DATAREADY_OUT: std_logic;
- signal buf_INT_READ_OUT: std_logic;
- signal reg_MED_FIRST_PACKET_IN : std_logic;
- signal next_buf_MED_DATA_OUT, buf_MED_DATA_OUT: std_logic_vector(7 downto 0);
- signal buf_MED_TRANSMISSION_CLK_OUT: std_logic;
- signal buf_MED_CARRIER_OUT, next_MED_CARRIER_OUT: STD_LOGIC;
- signal buf_MED_PARITY_OUT, next_MED_PARITY_OUT: STD_LOGIC;
- signal buf_MED_FIRST_PACKET_OUT, next_MED_FIRST_PACKET_OUT : std_logic;
- signal my_error : std_logic_vector(2 downto 0);
- signal fatal_error, media_not_connected : std_logic;
- signal next_media_not_connected : std_logic;
- signal transmission_clk_Counter : std_logic_vector(4 downto 0);
- signal next_transmission_clk_Counter : std_logic_vector(4 downto 0);
- signal next_TRANSMISSION_CLK: std_logic;
- signal buf_STAT : std_logic_vector(31 downto 0);
-
- signal last_TRCLK, this_TRCLK: std_logic;
- signal CLK_counter,next_CLK_counter: std_logic_vector(7 downto 0);
-
- signal last_MED_TRANSMISSION_CLK_IN : std_logic;
- signal last_MED_FIRST_PACKET_IN : std_logic;
- signal reg_MED_DATA_IN : std_logic_vector(11 downto 0);
- signal reg_MED_TRANSMISSION_CLK_IN, reg_MED_CARRIER_IN : std_logic;
- signal reg_MED_PARITY_IN : std_logic;
- signal recv_counter : std_logic_vector(3 downto 0);
- signal transmission_running, next_transmission_running : std_logic;
- signal buf_MED_DATA_IN, next_buf_MED_DATA_IN : std_logic_vector(7 downto 0);
-
- signal led_counter : std_logic_vector(18 downto 0);
- signal send_resync_counter : std_logic_vector(11 downto 0);
- signal send_resync : std_logic;
- signal rx_led, tx_led, link_led : std_logic;
- signal trbnet_reset : std_logic;
-
-
-begin
- INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
- INT_DATA_OUT <= buf_INT_DATA_OUT;
- INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT;
- INT_READ_OUT <= buf_INT_READ_OUT;
- STAT <= buf_STAT;
-
- buf_STAT(1 downto 0) <= (others => '0');
- buf_STAT(5 downto 2) <= MED_DATA_IN(11 downto 8);
- buf_STAT(18 downto 6)<= (others => '0');
- buf_STAT(31 downto 19) <= reg_MED_PARITY_IN & reg_MED_CARRIER_IN & reg_MED_TRANSMISSION_CLK_IN & reg_MED_FIRST_PACKET_IN & reg_MED_DATA_IN(11) & reg_MED_DATA_IN(7 downto 0);
-
-
- MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT;
- MED_DATA_OUT(10 downto 8) <= (others => '0');
- MED_DATA_OUT(11) <= (not reset or send_resync);
- MED_DATA_OUT(12) <= buf_MED_FIRST_PACKET_OUT;
- MED_DATA_OUT(13) <= buf_MED_TRANSMISSION_CLK_OUT;
- MED_DATA_OUT(14) <= buf_MED_CARRIER_OUT;
- MED_DATA_OUT(15) <= buf_MED_PARITY_OUT;
-
-
---LED & Stat_OP
- STAT_OP(2 downto 0) <= my_error;
- STAT_OP(8 downto 3) <= (others => '0');
- STAT_OP(9) <= link_led;
- STAT_OP(10) <= rx_led;
- STAT_OP(11) <= tx_led;
- STAT_OP(12) <= '0';
- STAT_OP(13) <= not reg_MED_DATA_IN(11) and not last_MED_TRANSMISSION_CLK_IN and reg_MED_TRANSMISSION_CLK_IN and reg_MED_CARRIER_IN;
- STAT_OP(14) <= (not reg_MED_DATA_IN(11) and reg_MED_CARRIER_IN) or media_not_connected;
- STAT_OP(15) <= (not reg_MED_DATA_IN(11) and not last_MED_TRANSMISSION_CLK_IN and reg_MED_TRANSMISSION_CLK_IN and reg_MED_CARRIER_IN) or media_not_connected;
-
- link_led <= reg_MED_DATA_IN(11);
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if reset = '1' then
- led_counter <= (others => '0');
- rx_led <= '0';
- tx_led <= '0';
- else
- if led_counter(18) = '1' then
- led_counter <= (others => '0');
- else
- led_counter <= led_counter + 1;
- end if;
- if reg_MED_CARRIER_IN = '1' then
- rx_led <= '1';
- elsif led_counter(18) = '1' then
- rx_led <= '0';
- end if;
- if next_MED_CARRIER_OUT = '1' then
- tx_led <= '1';
- elsif led_counter(18) = '1' then
- tx_led <= '0';
- end if;
- end if;
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- send_resync <= '0';
- send_resync_counter <= (others => '0');
- else
- if not (send_resync_counter = 0) then
- send_resync_counter <= send_resync_counter + 1;
- end if;
- if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then
- send_resync <= '1';
- send_resync_counter <= send_resync_counter + 1;
- end if;
- if send_resync_counter = x"00F" then
- send_resync <= '0';
- end if;
- end if;
- end if;
- end process;
-
- --TODO:
- --------------------------------
- fatal_error <= '0';
-
- --My error bits
- --------------------------------
- reg_my_error: process(CLK,RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' or media_not_connected = '1' or MED_DATA_IN(11) = '0' then
- my_error <= ERROR_NC;
- elsif fatal_error = '1' or (INT_READ_IN = '0' and buf_INT_DATAREADY_OUT = '1') then
- my_error <= ERROR_FATAL;
- else
- my_error <= ERROR_OK;
- end if;
- end if;
- end process;
-
-
- --Transmission clock generator
- --------------------------------
- trans_clk_counter: process (transmission_clk_Counter, buf_MED_TRANSMISSION_CLK_OUT)
- begin
- if transmission_clk_Counter = (TRANSMISSION_CLOCK_DIVIDER/2) - 1 then
- next_transmission_clk_Counter <= (others => '0');
- next_TRANSMISSION_CLK <= not buf_MED_TRANSMISSION_CLK_OUT;
- else
- next_transmission_clk_Counter <= transmission_clk_Counter + 1;
- next_TRANSMISSION_CLK <= buf_MED_TRANSMISSION_CLK_OUT;
- end if;
- end process;
-
-
- trans_clk_counter_reg: process (CLK,RESET)
- begin
- if RESET = '1' then
- transmission_clk_Counter <= (others => '0');
- buf_MED_TRANSMISSION_CLK_OUT <= '0';
- elsif rising_edge(CLK) then
- transmission_clk_Counter <= next_transmission_clk_Counter;
- buf_MED_TRANSMISSION_CLK_OUT <= next_TRANSMISSION_CLK;
- else
- transmission_clk_Counter <= transmission_clk_Counter;
- buf_MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT;
- end if;
- end process;
-
-
-
- --Transmission Clock detection
- --------------------------------
- trans_clk_reg: process (RESET,CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- last_TRCLK <= '0';
- this_TRCLK <= '0';
- CLK_counter <= (others => '0');
- media_not_connected <= '0';
- else
- last_TRCLK <= this_TRCLK;
- this_TRCLK <= reg_MED_TRANSMISSION_CLK_IN;
- CLK_counter <= next_CLK_counter;
- media_not_connected <= next_media_not_connected;
- end if;
- end if;
- end process;
-
-
-
- transCLK_counter: process (this_TRCLK, last_TRCLK, CLK_counter,
- buf_MED_DATA_OUT, buf_MED_CARRIER_OUT,
- buf_MED_PARITY_OUT)
- begin
- next_media_not_connected <= '0';
- if RESET = '1' then
- next_CLK_counter <= x"1F";
- elsif last_TRCLK = '0' and this_TRCLK = '1' then
- next_CLK_counter <= (others => '0');
- elsif CLK_counter = 31 then
- next_media_not_connected <= '1';
- next_CLK_counter <= CLK_counter;
- else
- next_CLK_counter <= CLK_counter + 1;
- end if;
- end process;
-
-
-
-
- --INT to MED direction
- --------------------------------
- INT2MED_fsm: process(buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, buf_MED_PARITY_OUT, buf_INT_DATA_IN,
- transmission_running, buf_MED_FIRST_PACKET_OUT, next_TRANSMISSION_CLK,
- buf_MED_TRANSMISSION_CLK_OUT, INT_DATAREADY_IN, INT_DATA_IN,
- buf_INT_READ_OUT, INT_PACKET_NUM_IN)
- begin
- next_buf_MED_DATA_OUT <= buf_MED_DATA_OUT;
- next_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT;
- next_MED_PARITY_OUT <= buf_MED_PARITY_OUT;
- next_buf_INT_DATA_IN <= buf_INT_DATA_IN;
- next_transmission_running <= transmission_running;
- next_MED_FIRST_PACKET_OUT <= buf_MED_FIRST_PACKET_OUT;
- buf_INT_READ_OUT <= '0';
- if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' and transmission_running = '0' then
- next_MED_CARRIER_OUT <= '0';
- end if;
- if(INT_DATAREADY_IN = '1' and transmission_running = '0') then
- if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then
- next_buf_MED_DATA_OUT <= INT_DATA_IN(15 downto 8);
- next_buf_INT_DATA_IN <= INT_DATA_IN(7 downto 0);
- next_MED_CARRIER_OUT <= '1';
- next_MED_PARITY_OUT <= xor_all(INT_DATA_IN(15 downto 8));
- next_transmission_running <= '1';
- buf_INT_READ_OUT <= '1';
- if INT_PACKET_NUM_IN = c_H0 then
- next_MED_FIRST_PACKET_OUT <= '1';
- else
- next_MED_FIRST_PACKET_OUT <= '0';
- end if;
- end if;
- elsif transmission_running = '1' then
- if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then
- next_buf_MED_DATA_OUT <= buf_INT_DATA_IN;
- next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN);
- next_transmission_running <= '0';
- end if;
- end if;
- if send_resync = '1' then
- next_MED_CARRIER_OUT <= '1';
- end if;
- end process;
-
-
- INT2MED_fsm_reg: process(CLK,RESET)
- begin
- if rising_edge(CLK) then
- if RESET='1' then
- buf_MED_DATA_OUT <= (others => '0');
- buf_INT_DATA_IN <= (others => '0');
- buf_MED_CARRIER_OUT <= '0';
- buf_MED_PARITY_OUT <= '0';
- buf_MED_FIRST_PACKET_OUT <= '0';
- transmission_running <= '0';
- else
- buf_INT_DATA_IN <= next_buf_INT_DATA_IN;
- buf_MED_DATA_OUT <= next_buf_MED_DATA_OUT;
- buf_MED_FIRST_PACKET_OUT <= next_MED_FIRST_PACKET_OUT;
- buf_MED_CARRIER_OUT <= next_MED_CARRIER_OUT;
- buf_MED_PARITY_OUT <= next_MED_PARITY_OUT;
- transmission_running <= next_transmission_running;
- end if;
- end if;
- end process;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- --MED to INT direction
- --------------------------------
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- recv_counter <= "0111";
- elsif reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then
- if recv_counter = "1001" then
- recv_counter <= "0000";
- else
- recv_counter <= recv_counter + 1;
- end if;
- last_MED_FIRST_PACKET_IN <= reg_MED_FIRST_PACKET_IN;
- if reg_MED_FIRST_PACKET_IN = '1' and last_MED_FIRST_PACKET_IN = '0' then
- recv_counter <= "1000";
- end if;
- end if;
- end if;
- end process;
-
-
-
- MED2INT_fsm: process(buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT, buf_MED_DATA_IN, last_MED_TRANSMISSION_CLK_IN,
- reg_MED_TRANSMISSION_CLK_IN, reg_MED_DATA_IN, recv_counter, INT_READ_IN, reg_MED_CARRIER_IN,
- buf_INT_PACKET_NUM_OUT, reg_MED_FIRST_PACKET_IN, last_MED_FIRST_PACKET_IN)
- begin
- next_INT_DATA_OUT <= buf_INT_DATA_OUT;
- next_INT_DATAREADY_OUT <= '0'; --buf_INT_DATAREADY_OUT;
- next_buf_MED_DATA_IN <= buf_MED_DATA_IN;
- next_INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT;
-
--- if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then
--- next_INT_DATAREADY_OUT <= '0';
--- end if;
-
- if reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then
- if recv_counter(0) = '1' or (reg_MED_FIRST_PACKET_IN = '1' and last_MED_FIRST_PACKET_IN = '0') then
- next_buf_MED_DATA_IN <= reg_MED_DATA_IN(7 downto 0);
- else
- next_INT_DATA_OUT(7 downto 0) <= reg_MED_DATA_IN(7 downto 0);
- next_INT_DATA_OUT(15 downto 8) <= buf_MED_DATA_IN;
- next_INT_PACKET_NUM_OUT <= recv_counter(3 downto 1);
- next_INT_DATAREADY_OUT <= '1';
- end if;
- end if;
- end process;
-
-
- MED2INT_fsm_reg: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET='1' then
- buf_INT_DATAREADY_OUT <= '0';
- last_MED_TRANSMISSION_CLK_IN <= '1';
- else
- buf_INT_DATA_OUT <= next_INT_DATA_OUT;
- buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT;
- last_MED_TRANSMISSION_CLK_IN <= reg_MED_TRANSMISSION_CLK_IN;
- buf_MED_DATA_IN <= next_buf_MED_DATA_IN;
- buf_INT_PACKET_NUM_OUT <= next_INT_PACKET_NUM_OUT;
- end if;
- end if;
- end process;
-
- LVDS_IN_reg: process(CLK)
- begin
- if rising_edge(CLK) then
- reg_MED_TRANSMISSION_CLK_IN <= MED_DATA_IN(13);
- reg_MED_CARRIER_IN <= MED_DATA_IN(14);
- reg_MED_PARITY_IN <= MED_DATA_IN(15);
- reg_MED_DATA_IN <= MED_DATA_IN(11 downto 0);
- reg_MED_FIRST_PACKET_IN <= MED_DATA_IN(12);
- end if;
- end process;
-
-end architecture;
-
+++ /dev/null
--- media interface for the 32 lvds lines (16 in each direction)
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/NewTriggerBusMedia
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net_med_tlkx501 is
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Internal direction port (MII)
- -- do not change this interface!!!
- -- 1st part: from the medium to the internal logic (trbnet)
- INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media
- --and ready to be read out
- INT_DATA_OUT: out STD_LOGIC_VECTOR (55 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- 2nd part: from the internal logic (trbnet) to the medium
- INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read)
- INT_DATA_IN: in STD_LOGIC_VECTOR (55 downto 0); -- Data word
- INT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- (end do not change this interface!!!)
-
-
- -- Media direction port
- -- marek, please add the lines you need here (the real output pins)
- -- subcomponents like counters, egde detect etc
- -- should be renamed to trb_net_XXX to avoid naming conflics
- --
- --
-
- -- Status and control port => this never can hurt
- STAT: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- );
-END trb_net_med_tlkx501;
+++ /dev/null
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetOBUF
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_obuf is
- generic (
- DATA_COUNT_WIDTH : integer := 4;
- SWITCH_OFF_BUFFER_CHECK : integer := 0
- --switching off erroneous output buffer counter. MUST ONLY be
- --used for short transfers!!!!
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC;
- -- Internal direction port
- INT_DATAREADY_IN: in STD_LOGIC;
- INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_OUT: out STD_LOGIC;
- -- Status and control port
- STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
- );
-end trb_net_obuf;
-
-architecture trb_net_obuf_arch of trb_net_obuf is
-
- component trb_net_sbuf is
- generic (DATA_WIDTH : integer := 56;
- VERSION : integer := 0);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- -- Port to synchronous output.
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
- signal current_output_buffer : STD_LOGIC_VECTOR (50 downto 0);
- signal current_ACK_word, current_EOB_word, current_DATA_word, current_NOP_word :
- STD_LOGIC_VECTOR (50 downto 0);
- signal comb_dataready, comb_next_read, comb_read ,sbuf_free: STD_LOGIC;
- signal reg_INT_READ_OUT , next_INT_READ_OUT:STD_LOGIC;
-
- signal next_SEND_ACK_IN, reg_SEND_ACK_IN : STD_LOGIC;
- signal sent_ACK, sent_EOB, sent_DATA : STD_LOGIC;
-
- signal CURRENT_DATA_COUNT, next_DATA_COUNT : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
--- signal max_DATA_COUNT, next_max_DATA_COUNT : STD_LOGIC_VECTOR (15 downto 0);
- signal max_DATA_COUNT_minus_one, next_max_DATA_COUNT_minus_one : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
- signal max_DATA_COUNT_minus_two, next_max_DATA_COUNT_minus_two : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
- signal tmp_next_max_DATA_COUNT_minus_one : STD_LOGIC_VECTOR (15 downto 0);
- signal tmp_next_max_DATA_COUNT_minus_two : STD_LOGIC_VECTOR (15 downto 0);
- signal TRANSMITTED_BUFFERS, next_TRANSMITTED_BUFFERS : STD_LOGIC_VECTOR (1 downto 0);
- signal increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS : STD_LOGIC;
-
- signal SEND_BUFFER_SIZE_IN : STD_LOGIC_VECTOR (3 downto 0);
- signal REC_BUFFER_SIZE_IN : STD_LOGIC_VECTOR (3 downto 0);
- signal SEND_ACK_IN : STD_LOGIC;
- signal GOT_ACK_IN : STD_LOGIC;
-
- signal is_locked, got_locked,release_locked : std_logic;
-
- -- type BUFFER_STATE is (BUFFER_IDLE, BUFFER_SEND_ACK, BUFFER_SEND_EOB, BUFFER_SEND_DATA, BUFFER_BLOCKED);
-
-
- begin
-
- SBUF: trb_net_sbuf
- generic map (DATA_WIDTH => 51, VERSION => 0)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => comb_dataready,
- COMB_next_READ_OUT => comb_next_read,
- COMB_READ_IN => comb_read,
- COMB_DATA_IN => current_output_buffer,
- SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
- SYN_DATA_OUT => MED_DATA_OUT,
- SYN_READ_IN => MED_READ_IN
- );
-
- decrease_TRANSMITTED_BUFFERS <= GOT_ACK_IN;
- comb_read <= '1';
- INT_READ_OUT <= reg_INT_READ_OUT;
--- sbuf_free <= comb_next_read or MED_READ_IN; --sbuf killed
- sbuf_free <= comb_next_read;
-
- COMB_NEXT_TRANSFER : process(current_NOP_word, MED_READ_IN, comb_next_read,
- CURRENT_DATA_COUNT,reg_SEND_ACK_IN,reg_INT_READ_OUT,
- INT_DATAREADY_IN, INT_DATA_IN, sent_ACK, sent_EOB,
- current_ACK_word,current_EOB_word, sbuf_free, sent_data,
- max_DATA_COUNT_minus_two,next_DATA_COUNT,
- next_TRANSMITTED_BUFFERS)
- begin
- current_output_buffer <= current_NOP_word;
- next_INT_READ_OUT <= '1';
- increase_TRANSMITTED_BUFFERS <= '0';
- next_DATA_COUNT <= CURRENT_DATA_COUNT;
- next_SEND_ACK_IN <= reg_SEND_ACK_IN;
- comb_dataready <= '0';
--- The read of data words have highest priority if this was prepared
- if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
- current_output_buffer <= INT_DATA_IN;
- comb_dataready <= '1'; --I hope sbuf can store
- if INT_DATA_IN(TYPE_POSITION) = TYPE_TRM then --TRM means EOB
- next_DATA_COUNT <= (others => '0');
- increase_TRANSMITTED_BUFFERS <= '1';
- else
- next_DATA_COUNT <= CURRENT_DATA_COUNT +1;
- end if;
--- If we are not able to fill ACK or EOB now, we have to stop activity
- if (sent_ACK = '1' or sent_EOB = '1' ) then
- next_INT_READ_OUT <= '0';
- if sent_ACK = '1' then --BUGBUG: next_SEND_ACK_IN should be a
- --counter (2 may arrive)
- next_SEND_ACK_IN <= '1';
- end if;
- end if;
--- Otherwise we fill the gap
- elsif sent_ACK = '1' and sbuf_free = '1' then
- current_output_buffer <= current_ACK_word;
- next_SEND_ACK_IN <= '0';
- comb_dataready <= '1';
- next_INT_READ_OUT <= '0'; --stop activity to be on the safe side
- elsif sent_ACK = '1' and sbuf_free = '0' then
- next_SEND_ACK_IN <= '1';
- elsif sent_EOB = '1' and sbuf_free = '1' then
- current_output_buffer <= current_EOB_word;
- next_DATA_COUNT <= (others => '0');
- increase_TRANSMITTED_BUFFERS <= '1';
- comb_dataready <= '1';
- next_INT_READ_OUT <= '0'; --stop activity to be on the safe side
- end if;
-
---finally, block data read if the rec buffer is full
- if sent_data = '0' or
- ((current_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = (max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0)))
- and reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1' ) --and INT_DATA_IN(TYPE_POSITION) = TYPE_TRM
- --long version of (next_count = max_count-1)
- or (next_TRANSMITTED_BUFFERS(1) = '1' and SWITCH_OFF_BUFFER_CHECK = 0)
- then
- next_INT_READ_OUT <= '0';
- end if;
---In any case: if sbuf not free, then we stop data taking
- if sbuf_free = '0' then
- next_INT_READ_OUT <= '0';
- end if;
-
- end process;
-
-
- REG : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- reg_SEND_ACK_IN <= '0';
- CURRENT_DATA_COUNT <= (others => '0');
- reg_INT_READ_OUT <= '0';
- elsif CLK_EN = '1' then
- reg_SEND_ACK_IN <= next_SEND_ACK_IN;
- CURRENT_DATA_COUNT <= next_DATA_COUNT;
- reg_INT_READ_OUT <= next_INT_READ_OUT;
- else
- reg_SEND_ACK_IN <= reg_SEND_ACK_IN;
- CURRENT_DATA_COUNT <= CURRENT_DATA_COUNT;
- reg_INT_READ_OUT <= reg_INT_READ_OUT;
- end if;
- end if;
- end process;
-
- -- buffer registers
- STAT_BUFFER(1 downto 0) <= TRANSMITTED_BUFFERS;
- STAT_BUFFER(15 downto 2) <= (others => '0');
- STAT_BUFFER(31 downto 16) <= CURRENT_DATA_COUNT;
- SEND_BUFFER_SIZE_IN <= CTRL_BUFFER(3 downto 0);
- REC_BUFFER_SIZE_IN <= CTRL_BUFFER(7 downto 4);
- SEND_ACK_IN <= CTRL_BUFFER(8);
- GOT_ACK_IN <= CTRL_BUFFER(9);
-
- -- build the words and the internal data readys
- current_ACK_word(TYPE_POSITION) <= TYPE_ACK;
- current_ACK_word(47 downto 20) <= (others => '0');
- current_ACK_word(BUFFER_SIZE_POSITION) <= SEND_BUFFER_SIZE_IN;
- current_ACK_word(15 downto 0) <= (others => '0');
- sent_ACK <= SEND_ACK_IN or reg_SEND_ACK_IN;
-
- current_EOB_word(TYPE_POSITION) <= TYPE_EOB;
- current_EOB_word(47 downto 0) <= (others => '0');
- gen_sent_EOB : process (CURRENT_DATA_COUNT, max_DATA_COUNT_minus_one)
- begin
- if (CURRENT_DATA_COUNT = max_DATA_COUNT_minus_one) then
- sent_EOB <= '1';
- else
- sent_EOB <= '0';
- end if;
- end process;
-
- current_NOP_word(TYPE_POSITION) <= TYPE_ILLEGAL;
- current_NOP_word(47 downto 0) <= (others => '0');
-
- current_DATA_word(50 downto 0) <= INT_DATA_IN;
- sent_DATA <= '1' when (TRANSMITTED_BUFFERS(1) = '0' or SWITCH_OFF_BUFFER_CHECK = 1) else '0';
-
--- generate max_DATA_COUNT, comb. operation which should be registered
--- next_max_DATA_COUNT <= "0000000000000100" when REC_BUFFER_SIZE_IN="0001" else
--- "0000000000001000" when REC_BUFFER_SIZE_IN="0010" else
--- "0000000000010000" when REC_BUFFER_SIZE_IN="0011" else
--- "0000000000100000" when REC_BUFFER_SIZE_IN="0100" else
--- "0000000000000010";
- tmp_next_max_DATA_COUNT_minus_one <= "0000000000000011" when REC_BUFFER_SIZE_IN="0001" else
- "0000000000000111" when REC_BUFFER_SIZE_IN="0010" else
- "0000000000001111" when REC_BUFFER_SIZE_IN="0011" else
- "0000000000011111" when REC_BUFFER_SIZE_IN="0100" else
- "0000000000000001";
- tmp_next_max_DATA_COUNT_minus_two <= "0000000000000010" when REC_BUFFER_SIZE_IN="0001" else
- "0000000000000110" when REC_BUFFER_SIZE_IN="0010" else
- "0000000000001110" when REC_BUFFER_SIZE_IN="0011" else
- "0000000000011110" when REC_BUFFER_SIZE_IN="0100" else
- "0000000000000000";
- next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0) <= tmp_next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0);
- next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0) <= tmp_next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0);
--- next_max_DATA_COUNT <= 2 ** (REC_BUFFER_SIZE_IN + 1);
- -- BUGBUG via pattern_gen
-
- reg_max_DATA_COUNT : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- max_DATA_COUNT_minus_one(0) <= '1';
- max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 1) <= (others => '0');
- max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0) <= (others => '0');
- else
- max_DATA_COUNT_minus_one <= next_max_DATA_COUNT_minus_one;
- max_DATA_COUNT_minus_two <= next_max_DATA_COUNT_minus_two;
- end if;
- end if;
- end process;
-
-
--- increase and decrease transmitted buffers
- comb_TRANSMITTED_BUFFERS : process (increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS, TRANSMITTED_BUFFERS)
- begin
- if (increase_TRANSMITTED_BUFFERS = '1' and decrease_TRANSMITTED_BUFFERS = '0') then
- next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS +1;
- elsif (increase_TRANSMITTED_BUFFERS = '0' and decrease_TRANSMITTED_BUFFERS = '1') then
- next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS -1;
- else
- next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS;
- end if;
- end process;
-
- reg_TRANSMITTED_BUFFERS : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- TRANSMITTED_BUFFERS <= "00";
- elsif CLK_EN = '1' then
- TRANSMITTED_BUFFERS <= next_TRANSMITTED_BUFFERS;
- else
- TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS;
- end if;
- end if;
- end process;
-
-
- --locking control
- comb_locked : process (MED_READ_IN, current_output_buffer, release_locked, is_locked)
-
- begin -- process
- got_locked <= is_locked;
-
- if MED_READ_IN = '1' then
- if current_output_buffer(TYPE_POSITION) = TYPE_TRM and release_locked = '0' then
- got_locked <= '1';
- elsif release_locked = '1' then
- got_locked <= '0';
- end if;
- elsif release_locked = '1' then
- got_locked <= '0';
- end if; -- MED_READ_IN
- end process;
-
- release_locked <= CTRL_LOCKED(0);
- STAT_LOCKED(0) <= is_locked;
- STAT_LOCKED(15 downto 1) <= (others => '0');
-
- reg_locked: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- is_locked <= '0';
- elsif CLK_EN = '1' then
- is_locked <= got_locked;
- else
- is_locked <= is_locked;
- end if;
- end if;
- end process;
-
-
-end trb_net_obuf_arch;
-
+++ /dev/null
--- this is an apl, connecting the old trigger bus to the new system
--------------------------------------------------------------------------------
--- Title : trb_net_old_to_new
--- Project : HADES trigger new net
--------------------------------------------------------------------------------
--- File : trb_net_old_to_new.vhd
--- Author : Tiago Perez (tiago.perez@uni-giessen.de)
--- Created : 2007/01/12
--- Last modified : 2007/02/26 T. Perez
--------------------------------------------------------------------------------
--- Description : Interace between "old" and "new" trigger nets
---
--------------------------------------------------------------------------------
--- Modification history :
--- 2007/01/12 : created
--- L12TrigBusInterface is driven only with the main clock. This
--- used to be 40MHz in "OLD" DTU but now is around 10 times faster.
--- I am not sure how "sharp" are the edges of T and TS in the
--- trigger bus, but now, samplig at ca. 400MHz we may sample T and
--- TS sereval times while falling and still not set. We should
--- chek the quality and "sharpness" of the Triggerbus with a scope
--- and eventually downscale the main clock to sample slower.
--- 2007/02/26: T. Perez (tiago.perez@uni-giessen.de)
--- Change FSM so that all outouts are registered. OUTPUTS are
--- decoded from the next_state to avoid losing CLK cycles. There
--- is an external counter to do the sendig procedure.
--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity trb_net_old_to_new is
- generic (TRIGGER_LEVEL : integer := 1); -- either 1 or 2
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_OUT : out std_logic_vector (47 downto 0); -- Data word "application to network"
- APL_WRITE_OUT : out std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_IN : in std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_OUT : out std_logic; --
- APL_DTYPE_OUT : out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_OUT : out std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_IN : in std_logic_vector (47 downto 0); -- Data word "network to application"
- APL_TYP_IN : in std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_IN : in std_logic; -- Data word is valid and might be read out
- APL_READ_OUT : out std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_IN : in std_logic; -- Data transfer is running
- APL_SEQNR_IN : in std_logic_vector (7 downto 0);
-
- -- the OLD trigger bus
- OLD_T : in std_logic; -- trigger signal
- -- used to strobe the trigger code
- OLD_TS : in std_logic; -- trigger strobe
--- used to strobe the trigger tag and further
--- trigger data nibbles (e.g. trigger priority)
-
- OLD_TD : in std_logic_vector (3 downto 0); -- trigger data lines
--- transmit the trigger data nibbles
- OLD_TB : out std_logic; -- trigger busy
--- wired-or signal, that indicates busy state of one or more DTUs
- OLD_TE : out std_logic -- trigger error
--- wired-or signal, that indicates error state of one or more DTUs
---Ts0..1 trigger spare lines
---free for future purposes
---not connected because useless
-
-
- );
-end trb_net_old_to_new;
-
-architecture behavioral of trb_net_old_to_new is
-
- -- reconstruct the LVL1 or LVL2 trigger
- -- for LVL1: Ignore the BEGRUN and ENDRUN triggers
- -- (please use the generic to check if we have LVL1 or 2)
-
- -- compare to the SEQNR, do not forget the offset by one for LVL1
- -- if a tigger tag mismatch occures, raise the error line
-
- -- feel free to add debug registers
-
- -- COMPONENTS
- -- OLD TRIGGER INTERFACE
- component L12TrigBusInterface
- port (
- TSTR : in std_logic;
- DSTR : in std_logic;
- DIN : in std_logic_vector(3 downto 0);
- BSY : out std_logic;
- ERR : out std_logic;
- RES : in std_logic;
- CLK : in std_logic;
- DVAL : out std_logic;
- TRIGTAG : out std_logic_vector(7 downto 0);
- TRIGCODE : out std_logic_vector(3 downto 0);
- TRIGTAG_MISMATCH : in std_logic;
- BUSY : in std_logic);
- end component;
-
- -- SIGNALS
- signal TRIGTAG_i, TRIGTAG_ii : std_logic_vector(7 downto 0);
- signal TRIGCODE_i : std_logic_vector(3 downto 0);
- signal DVAL_i : std_logic;
- signal TRIGTAG_MISMATCH_reg : std_logic;
-
- type State_Type is (idle, check_code, compare, send, error_1);
- signal present_state, next_state : State_Type;
- signal do_send_cnt : unsigned(2 downto 0);
-
-
-begin
- APL_DATA_OUT(7 downto 0) <= TRIGTAG_ii;
- -----------------------------------------------------------------------------
- -- FIX NON USED OUTPUTS
- -----------------------------------------------------------------------------
- APL_DATA_OUT(47 downto 8) <= (others => '0');
- APL_WRITE_OUT <= '0';
-
- APL_SHORT_TRANSFER_OUT <= '1'; -- short transfer TRUE
- APL_ERROR_PATTERN_OUT <= (others => '0');
- APL_TARGET_ADDRESS_OUT <= (others => '0');
-
- -----------------------------------------------------------------------------
- -- COMPONENTS
- -----------------------------------------------------------------------------
- BusInterfaceOld : L12TrigBusInterface
- port map (
- TSTR => OLD_T,
- DSTR => OLD_TS,
- DIN => OLD_TD,
- BSY => OLD_TB,
- ERR => OLD_TE,
- RES => RESET,
- CLK => CLK,
- DVAL => DVAL_i,
- TRIGTAG => TRIGTAG_i,
- TRIGCODE => TRIGCODE_i,
- TRIGTAG_MISMATCH => TRIGTAG_MISMATCH_reg,
- BUSY => APL_RUN_IN);
-
- -----------------------------------------------------------------------------
- -- DIFF LVL1/LVL2
- -----------------------------------------------------------------------------
- -- filter BEGRUN out
- -- CHANGE: TRIGTAG=TRIGTAG-1
- GEN_L1 : if TRIGGER_LEVEL = 1 generate
- process (CLK, RESET, CLK_EN, TRIGTAG_i)
- begin -- process S
- if RESET = '1' then
- TRIGTAG_ii <= (others => '0');
- elsif CLK'event and CLK = '1' and CLK_EN = '1' then
- TRIGTAG_ii <= TRIGTAG_i - 1;
- end if;
- end process;
- end generate GEN_L1;
-
- -- Register TRIGTAG
- GEN_L2 : if TRIGGER_LEVEL = 2 generate
- process (CLK, RESET, CLK_EN, TRIGTAG_i)
- begin -- process S
- if RESET = '1' then
- TRIGTAG_ii <= (others => '0');
- elsif CLK'event and CLK = '1' and CLK_EN = '1' then
- TRIGTAG_ii <= TRIGTAG_i;
- end if;
- end process;
- end generate GEN_L2;
-
- -----------------------------------------------------------------------------
- -- FSM
- -----------------------------------------------------------------------------
- -- purpose: Register the STATE of the FSM
- -- type : Sequential
- -- inputs : CLK, RESET, next_state
- -- output : next_state
- state_clocked : process (CLK, RESET, CLK_EN)
- begin -- process state_clocked
- if RESET = '1' then -- asynchronous reset (active high)
- present_state <= idle;
- elsif CLK'event and CLK = '1' and CLK_EN = '1' then -- rising clock edge
- present_state <= next_state;
- end if;
- end process state_clocked;
-
- -- purpose: Calculates the next_state of the FSM.
- -- type : combinational
- -- inputs : present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, APL_RUN_IN
- -- outputs: next_state
- FSM : process (present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, TRIGCODE_i, do_send_cnt)
- begin -- process FSM
- next_state <= present_state;
- case present_state is
- when idle =>
- if DVAL_i = '1' then
- next_state <= check_code;
- end if;
- when check_code =>
- -- Check for BEGIN_RUN
- if TRIGCODE_i = x"d" then
- next_state <= idle;
- else
- next_state <= compare;
- end if;
- when compare =>
- if TRIGTAG_ii = APL_SEQNR_IN then
- next_state <= send;
- else
- next_state <= error_1;
- end if;
- when send =>
- if do_send_cnt = 5 then
- --if APL_RUN_IN = '1' then
- next_state <= idle;
- end if;
- when others => null;
- end case;
- end process FSM;
-
- -- purpose: decode and register the output signals of FSM
- -- type : sequentia
- -- inputs : next_state
- -- outputs: TRIGTAG
- decode_output : process (CLK, RESET, CLK_EN, next_state, do_send_cnt)
- begin -- process decode_output
- if RESET = '1' then
- TRIGTAG_MISMATCH_reg <= '0';
- APL_SEND_OUT <= '0';
- APL_READ_OUT <= '0';
-
- APL_DTYPE_OUT <= (others => '0');
- elsif CLK'event and CLK = '1' and CLK_EN = '1' then
- TRIGTAG_MISMATCH_reg <= '0';
- APL_SEND_OUT <= '0';
- APL_READ_OUT <= '0';
-
- APL_DTYPE_OUT <= (others => '0');
-
- case next_state is
- when idle =>
- --when check_code =>
-
- when compare =>
- APL_DTYPE_OUT <= TRIGCODE_i;
-
- when send =>
- APL_DTYPE_OUT <= TRIGCODE_i;
- if do_send_cnt = 1 then
- APL_SEND_OUT <= '1';
- end if;
- if (do_send_cnt = 3) or (do_send_cnt = 4) then
- APL_READ_OUT <= '1';
- end if;
- when error_1 =>
- TRIGTAG_MISMATCH_reg <= '1';
- when others => null;
- end case;
- end if;
- end process decode_output;
-
- send_counter : process (CLK, RESET, present_state)
- begin -- process send
- if RESET = '1' or present_state = idle then -- asynchronous reset (active low)
- do_send_cnt <= (others => '0');
- elsif CLK'event and CLK = '1' and present_state = send then -- rising clock edge
- do_send_cnt <= do_send_cnt+1;
- end if;
- end process send_counter;
-
-end behavioral;
-
+++ /dev/null
--- connection between the TRBNET and any application
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net_passive_api is
-
- generic (FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
-
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_INIT_DATAREADY_OUT: out STD_LOGIC;
- INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_IN: in STD_LOGIC;
-
- INT_INIT_DATAREADY_IN: in STD_LOGIC;
- INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_OUT: out STD_LOGIC;
-
-
- INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
- INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_IN: in STD_LOGIC;
-
- INT_REPLY_DATAREADY_IN: in STD_LOGIC;
- INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_OUT: out STD_LOGIC;
-
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- -- not needed now, but later
- );
-end trb_net_passive_api;
-
-architecture trb_net_passive_api_arch of trb_net_passive_api is
-
- component trb_net_base_api is
- generic (API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
- FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Internal direction port
- -- the ports with active or passive in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- INT_MASTER_DATAREADY_OUT: out STD_LOGIC;
- INT_MASTER_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_MASTER_READ_IN: in STD_LOGIC;
-
- INT_MASTER_DATAREADY_IN: in STD_LOGIC;
- INT_MASTER_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_MASTER_READ_OUT: out STD_LOGIC;
-
- INT_SLAVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_SLAVE_DATAREADY_OUT: out STD_LOGIC;
- INT_SLAVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_SLAVE_READ_IN: in STD_LOGIC;
-
- INT_SLAVE_DATAREADY_IN: in STD_LOGIC;
- INT_SLAVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_SLAVE_READ_OUT: out STD_LOGIC;
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- -- not needed now, but later
- );
- end component;
-
-begin
-
- PASSIVE_API: trb_net_base_api
- generic map (
- API_TYPE => 0,
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => 0
- )
- port map (
- CLK => CLK,
- CLK_EN => CLK_EN,
- RESET => RESET,
-
- APL_DATA_IN => APL_DATA_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
- APL_DATA_OUT => APL_DATA_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
-
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
- INT_MASTER_DATA_OUT => INT_REPLY_DATA_OUT,
- INT_MASTER_READ_IN => INT_REPLY_READ_IN,
-
- INT_MASTER_DATAREADY_IN => INT_REPLY_DATAREADY_IN,
- INT_MASTER_DATA_IN => INT_REPLY_DATA_IN,
- INT_MASTER_READ_OUT => INT_REPLY_READ_OUT,
-
- INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN,
-
- INT_SLAVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
- INT_SLAVE_DATA_OUT => INT_INIT_DATA_OUT,
- INT_SLAVE_READ_IN => INT_INIT_READ_IN,
-
- INT_SLAVE_DATAREADY_IN => INT_INIT_DATAREADY_IN,
- INT_SLAVE_DATA_IN => INT_INIT_DATA_IN,
- INT_SLAVE_READ_OUT => INT_INIT_READ_OUT,
- -- Status and control port
- STAT_FIFO_TO_INT => STAT_FIFO_TO_INT,
- STAT_FIFO_TO_APL => STAT_FIFO_TO_APL
- -- not needed now, but later
- );
-
-end trb_net_passive_api_arch;
+++ /dev/null
--- an active api together with an iobuf
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_passive_apimbuf is
-
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3; -- or the replyibuf
- FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 1 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_Send_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_api_control_signals: out std_logic_vector(31 downto 0);
- STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-end trb_net_passive_apimbuf;
-
-architecture trb_net_passive_apimbuf_arch of trb_net_passive_apimbuf is
-
-component trb_net_iobuf is
-
- generic (SWITCH_OFF_BUFFER_CHECK : integer := 0;
- --switching off erroneous output buffer counter. MUST ONLY be
- --used for short transfers!!!!
- INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3); -- or the replyibuf
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out STD_LOGIC;
- INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_IN: in STD_LOGIC;
-
- INT_INIT_DATAREADY_IN: in STD_LOGIC;
- INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_OUT: out STD_LOGIC;
-
- INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
- INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_IN: in STD_LOGIC;
-
- INT_REPLY_DATAREADY_IN: in STD_LOGIC;
- INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_OUT: out STD_LOGIC;
-
- -- Status and control port
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
- );
-end component;
-
-component trb_net_passive_api is
-
- generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
-
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_Send_IN: in STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_IN: in STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_INIT_DATAREADY_OUT: out STD_LOGIC;
- INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_IN: in STD_LOGIC;
-
- INT_INIT_DATAREADY_IN: in STD_LOGIC;
- INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_OUT: out STD_LOGIC;
-
-
- INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
- INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_IN: in STD_LOGIC;
-
- INT_REPLY_DATAREADY_IN: in STD_LOGIC;
- INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_OUT: out STD_LOGIC;
-
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-end component;
-
-component trb_net_io_multiplexer is
-
- generic (BUS_WIDTH : integer := 56;
- MULT_WIDTH : integer := 5);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- -- highest bits are mult.
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
-end component;
-
-signal apl_to_buf_INIT_DATAREADY: STD_LOGIC;
-signal apl_to_buf_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal apl_to_buf_INIT_READ : STD_LOGIC;
-
-signal buf_to_apl_INIT_DATAREADY: STD_LOGIC;
-signal buf_to_apl_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal buf_to_apl_INIT_READ : STD_LOGIC;
-
-signal apl_to_buf_REPLY_DATAREADY: STD_LOGIC;
-signal apl_to_buf_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal apl_to_buf_REPLY_READ : STD_LOGIC;
-
-signal buf_to_apl_REPLY_DATAREADY: STD_LOGIC;
-signal buf_to_apl_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal buf_to_apl_REPLY_READ : STD_LOGIC;
-
--- for the connection to the multiplexer
-signal MED_INIT_DATAREADY_OUT : STD_LOGIC;
-signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_INIT_READ_IN : STD_LOGIC;
-
-signal MED_INIT_DATAREADY_IN : STD_LOGIC;
-signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_INIT_READ_OUT : STD_LOGIC;
-
-signal MED_REPLY_DATAREADY_OUT : STD_LOGIC;
-signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_REPLY_READ_IN : STD_LOGIC;
-
-signal MED_REPLY_DATAREADY_IN : STD_LOGIC;
-signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_REPLY_READ_OUT : STD_LOGIC;
-
-signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (1 downto 0);
-signal m_DATA_OUT : STD_LOGIC_VECTOR (101 downto 0);
-signal m_READ_IN : STD_LOGIC_VECTOR (1 downto 0);
-
-signal m_DATAREADY_IN : STD_LOGIC_VECTOR (1 downto 0);
-signal m_DATA_IN : STD_LOGIC_VECTOR (101 downto 0);
-signal m_READ_OUT : STD_LOGIC_VECTOR (1 downto 0);
-
-begin
-
- m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
- m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT;
- m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT;
- MED_INIT_READ_IN <= m_READ_IN(0);
- MED_REPLY_READ_IN <= m_READ_IN(1);
-
- MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
- MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
- MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0);
- MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51);
- m_READ_OUT(0) <= MED_INIT_READ_OUT;
- m_READ_OUT(1) <= MED_REPLY_READ_OUT;
-
-
- PASSIVE_API: trb_net_passive_api
-
- generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH)
-
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_Send_IN => APL_Send_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
-
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
-
- -- Internal direction port
- -- connect via private signals
-
- INT_INIT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
- INT_INIT_DATA_OUT => apl_to_buf_INIT_DATA,
- INT_INIT_READ_IN => apl_to_buf_INIT_READ,
-
- INT_INIT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
- INT_INIT_DATA_IN => buf_to_apl_INIT_DATA,
- INT_INIT_READ_OUT => buf_to_apl_INIT_READ,
-
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT =>apl_to_buf_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => apl_to_buf_REPLY_DATA,
- INT_REPLY_READ_IN => apl_to_buf_REPLY_READ,
-
- INT_REPLY_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => buf_to_apl_REPLY_DATA,
- INT_REPLY_READ_OUT => buf_to_apl_REPLY_READ,
-
- -- Status and control port
- STAT_FIFO_TO_INT => api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => api_stat_fifo_to_apl
- );
-
-STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
-STAT_api_control_signals(3) <= APL_WRITE_IN;
-STAT_api_control_signals(4) <= APL_Send_IN;
-STAT_api_control_signals(7 downto 5) <= (others => '0');
-STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0);
-STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY;
-STAT_api_control_signals(12) <= apl_to_buf_INIT_READ;
-STAT_api_control_signals(13) <= MED_INIT_DATAREADY_IN;
-STAT_api_control_signals(14) <= MED_REPLY_DATAREADY_IN;
-STAT_api_control_signals(15) <= MED_REPLY_DATA_IN(48);
-STAT_api_control_signals(16) <= MED_REPLY_DATA_IN(50);
-
-STAT_api_control_signals(31 downto 17) <= (others => '0');
-
-
-
-IOBUF: trb_net_iobuf
-
- generic map (SWITCH_OFF_BUFFER_CHECK => 0,
- --switching off erroneous output buffer counter. MUST ONLY be
- --used for short transfers!!!!
- INIT_DEPTH => INIT_DEPTH,
- REPLY_DEPTH => REPLY_DEPTH)
-
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_INIT_DATA_OUT,
- MED_INIT_READ_IN => MED_INIT_READ_IN,
-
- MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_INIT_DATA_IN,
- MED_INIT_READ_OUT => MED_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
-
- MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
- MED_REPLY_READ_IN => MED_REPLY_READ_IN,
-
- MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_REPLY_DATA_IN,
- MED_REPLY_READ_OUT => MED_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
- INT_INIT_READ_IN => buf_to_apl_INIT_READ,
-
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
-
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
-
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
-
- -- Status and control port
- STAT_GEN => STAT_GEN,
- STAT_LOCKED => STAT_LOCKED,
- STAT_INIT_BUFFER => STAT_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_REPLY_BUFFER,
- CTRL_GEN => CTRL_GEN,
- CTRL_LOCKED => CTRL_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER
- );
-
- MPLEX: trb_net_io_multiplexer
- generic map (BUS_WIDTH => 52,
- MULT_WIDTH => 1)
- port map (
- CLK => CLK,
- RESET => RESET ,
- CLK_EN => CLK_EN,
-
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_READ_OUT => MED_READ_OUT,
-
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_READ_IN => MED_READ_IN,
-
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_READ_IN =>m_READ_OUT,
-
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_READ_OUT =>m_READ_IN,
-
- CTRL => MPLEX_CTRL,
- STAT => STAT_MPLEX
-
- );
-
-end trb_net_passive_apimbuf_arch;
-
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net_priority_encoder_simple is
- generic (
- WIDTH : integer := 8
- );
- port (
- INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
- RESULT_OUT : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
- );
-end entity;
-
-architecture trb_net_priority_encoder_simple_arch of trb_net_priority_encoder_simple is
-
- signal fixed_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
-
- begin
- fixed_pattern(0) <= INPUT_IN(0);
- F1: for i in 1 to WIDTH-1 generate
- process(INPUT_IN)
- begin
- if INPUT_IN(i) = '1' and INPUT_IN(i-1 downto 0) = 0 then
- fixed_pattern(i) <= '1';
- else
- fixed_pattern(i) <= '0';
- end if;
- end process;
- end generate;
-
- RESULT_OUT <= fixed_pattern;
-
-
-end architecture;
-
+++ /dev/null
--- this is just a terminator, which auto-answers requests
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetTerm
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net_term is
-
- generic (FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_DATAREADY_OUT: out STD_LOGIC;
- INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
-
- INT_DATAREADY_IN: in STD_LOGIC;
- INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_OUT: out STD_LOGIC;
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
- APL_GOT_TRM: out STD_LOGIC;
-
- APL_HOLD_TRM: in STD_LOGIC;
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
-
- APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0) -- My own address (temporary solution!!!)
- -- Status and control port
-
- -- not needed now, but later
-
- );
-END trb_net_term;
-
-architecture trb_net_term_arch of trb_net_term is
-
-component trb_net_fifo is
- generic (WIDTH : integer := 8; -- FIFO word width
- DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1)
-
- port (CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic; -- Full Flag
- EMPTY_OUT : out std_logic;
- DEPTH_OUT : out std_logic_vector(7 downto 0)
- );
-
- end component;
-
--- signals for the test buffer
-signal next_APL_DTYPE_OUT, reg_APL_DTYPE_OUT: std_logic_vector(3 downto 0);
-signal next_APL_ERROR_PATTERN_OUT, reg_APL_ERROR_PATTERN_OUT: std_logic_vector(31 downto 0);
-signal next_APL_SEQNR_OUT, reg_APL_SEQNR_OUT: std_logic_vector(7 downto 0);
-signal next_APL_GOT_TRM, reg_APL_GOT_TRM: std_logic;
-
-signal fifo_term_buffer_data_in : std_logic_vector(50 downto 0);
-signal fifo_term_buffer_write : std_logic;
-signal fifo_term_buffer_data_out : std_logic_vector(50 downto 0);
-signal fifo_term_buffer_read : std_logic;
-signal fifo_term_buffer_full : std_logic;
-signal fifo_term_buffer_empty : std_logic;
-
-type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR);
-signal tb_current_state, tb_next_state : TERM_BUFFER_STATE;
-
--- signal combined_header, registered_header, next_registered_header: std_logic_vector(47 downto 0);
--- signal combined_trailer, registered_trailer, next_registered_trailer: std_logic_vector(47 downto 0);
- signal tb_registered_trailer, tb_next_registered_trailer: std_logic_vector(47 downto 0);
- signal tb_registered_target, tb_next_registered_target: std_logic_vector(15 downto 0);
-
--- signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0);
--- signal next_INT_INIT_DATA_OUT: std_logic_vector(50 downto 0);
--- signal next_INT_INIT_DATAREADY_OUT: std_logic;
--- signal sbuf_free, sbuf_next_READ: std_logic;
- signal next_INT_REPLY_READ_OUT, reg_INT_REPLY_READ_OUT: std_logic;
--- signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic;
--- signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(47 downto 0);
--- signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0);
-
-begin
-
-
-CHECK_BUFFER1: if FIFO_TERM_BUFFER_DEPTH >0 generate
- FIFO_TERM_BUFFER: trb_net_fifo
- generic map (
- WIDTH => 51,
- DEPTH => FIFO_TERM_BUFFER_DEPTH)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_term_buffer_data_in,
- WRITE_ENABLE_IN => fifo_term_buffer_write,
- DATA_OUT => fifo_term_buffer_data_out,
- READ_ENABLE_IN => fifo_term_buffer_read,
- FULL_OUT => fifo_term_buffer_full,
- EMPTY_OUT => fifo_term_buffer_empty
- );
-end generate CHECK_BUFFER1;
-CHECK_BUFFER2: if FIFO_TERM_BUFFER_DEPTH =0 generate
- fifo_term_buffer_empty <= '1';
- fifo_term_buffer_full <= '0';
- fifo_term_buffer_data_out <= (others => '0');
-
-end generate CHECK_BUFFER2;
-
- APL_DTYPE_OUT <= reg_APL_DTYPE_OUT;
- APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
- APL_SEQNR_OUT <= reg_APL_SEQNR_OUT;
- APL_GOT_TRM <= reg_APL_GOT_TRM;
-
-
- FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_DATA_IN,
- INT_DATAREADY_IN, tb_next_registered_trailer,
- tb_registered_trailer,
- fifo_term_buffer_empty, fifo_term_buffer_data_out,
- INT_READ_IN, tb_registered_target,
- reg_APL_DTYPE_OUT, reg_APL_ERROR_PATTERN_OUT,
- reg_APL_SEQNR_OUT, reg_APL_GOT_TRM,APL_MY_ADDRESS_IN,
- APL_HOLD_TRM, APL_DTYPE_IN, APL_ERROR_PATTERN_IN)
- begin -- process
- INT_READ_OUT <= '0';
- fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_ILLEGAL;
- fifo_term_buffer_data_in(DWORD_POSITION) <= (others => '0');
- fifo_term_buffer_write <= '0';
- tb_next_state <= MY_ERROR;
- tb_next_registered_trailer <= tb_registered_trailer;
- tb_next_registered_target <= tb_registered_target;
- fifo_term_buffer_read<= '0';
- INT_DATAREADY_OUT <= '0';
- INT_DATA_OUT(DWORD_POSITION) <= (others => '0');
- INT_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL;
- next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT;
- next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
- next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT;
- next_APL_GOT_TRM <= reg_APL_GOT_TRM;
------------------------------------------------------------------------
--- IDLE
------------------------------------------------------------------------
- if tb_current_state = IDLE then
- INT_READ_OUT <= '1'; -- I always can read
- tb_next_state <= IDLE;
- if INT_DATA_IN(TYPE_POSITION) = TYPE_HDR and INT_DATAREADY_IN = '1' then
- -- switch source and target adress
- fifo_term_buffer_data_in(SOURCE_POSITION) <= INT_DATA_IN(TARGET_POSITION);
- fifo_term_buffer_data_in(TARGET_POSITION) <= INT_DATA_IN(SOURCE_POSITION);
- fifo_term_buffer_data_in(F3_POSITION) <= INT_DATA_IN(F3_POSITION);
- fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_HDR;
- tb_next_registered_target <= INT_DATA_IN(TARGET_POSITION);
- if fifo_term_buffer_full = '0' and (INT_DATA_IN(TARGET_POSITION) = APL_MY_ADDRESS_IN
- or INT_DATA_IN(TARGET_POSITION) = BROADCAST_ADRESS) then
- fifo_term_buffer_write <= '1';
- else
- fifo_term_buffer_write <= '0';
- end if;
- elsif INT_DATA_IN(TYPE_POSITION) = TYPE_DAT and INT_DATAREADY_IN = '1' then
- fifo_term_buffer_data_in <= INT_DATA_IN;
- if fifo_term_buffer_full = '0' and (tb_registered_target = APL_MY_ADDRESS_IN
- or tb_registered_target = BROADCAST_ADRESS) then
- fifo_term_buffer_write <= '1';
- else
- fifo_term_buffer_write <= '0';
- end if;
- elsif INT_DATA_IN(TYPE_POSITION) = TYPE_TRM and INT_DATAREADY_IN = '1' then
- --tb_next_registered_trailer <= INT_INIT_DATA_IN(DWORD_POSITION);
- --keep trailer for later use
- -- in addition, write out some debug info
- next_APL_DTYPE_OUT <= INT_DATA_IN(DTYPE_POSITION);
- next_APL_ERROR_PATTERN_OUT <= INT_DATA_IN(ERRORPATTERN_POSITION);
- next_APL_SEQNR_OUT <= INT_DATA_IN(SEQNR_POSITION);
- next_APL_GOT_TRM <= '1';
- tb_next_state <= RUNNING;
- end if;
------------------------------------------------------------------------
--- RUNNING
------------------------------------------------------------------------
- elsif tb_current_state = RUNNING then
- tb_next_state <= RUNNING;
- if fifo_term_buffer_empty = '0' then -- Have buffered stuff
- INT_DATAREADY_OUT <= '1';
- INT_DATA_OUT <= fifo_term_buffer_data_out;
- if (INT_READ_IN = '1') then
- fifo_term_buffer_read <= '1';
- end if;
- elsif APL_HOLD_TRM = '1' then
- tb_next_state <= RUNNING; --hold the line
- else
- tb_next_state <= SEND_TRAILER;
- tb_next_registered_trailer(DTYPE_POSITION) <= APL_DTYPE_IN;
- tb_next_registered_trailer(ERRORPATTERN_POSITION) <= APL_ERROR_PATTERN_IN;
- tb_next_registered_trailer(SEQNR_POSITION) <= reg_APL_SEQNR_OUT;
- tb_next_registered_trailer(15 downto 12) <= (others => '0');
- end if; -- Have buffered stuff
------------------------------------------------------------------------
--- TRAILER
------------------------------------------------------------------------
- elsif tb_current_state = SEND_TRAILER then
- tb_next_state <= SEND_TRAILER ;
- INT_DATAREADY_OUT <= '1';
- INT_DATA_OUT(DWORD_POSITION) <= tb_registered_trailer;
- INT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM;
- if (INT_READ_IN = '1') then
- tb_next_state <= IDLE;
- tb_next_registered_target <= ILLEGAL_ADRESS;
- next_APL_GOT_TRM <= '0';
- end if;
- end if; -- tb_current_state switch
- end process;
-
-CLK_REG: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- tb_current_state <= IDLE;
- tb_registered_trailer <= (others => '0');
- tb_registered_target <= ILLEGAL_ADRESS;
- reg_APL_DTYPE_OUT <= (others => '0');
- reg_APL_ERROR_PATTERN_OUT <= (others => '0');
- reg_APL_SEQNR_OUT <= (others => '0');
- reg_APL_GOT_TRM <= '0';
- else
- tb_current_state <= tb_next_state;
- tb_registered_trailer <= tb_next_registered_trailer;
- tb_registered_target <= tb_next_registered_target;
- reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT;
- reg_APL_ERROR_PATTERN_OUT <= next_APL_ERROR_PATTERN_OUT;
- reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT;
- reg_APL_GOT_TRM <= next_APL_GOT_TRM;
- end if;
- end if;
- end process;
-
-end trb_net_term_arch;
+++ /dev/null
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF
--- This has in principle the same output ports, but internally
--- it keeps only the TRM words
--- EOB are killed
--- ACK are regognized
--- all other words (HDR, DAT) are not stored
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_term_ibuf is
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- Internal direction port
- INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header
- INT_DATAREADY_OUT: out STD_LOGIC;
- INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- Status and control port
- STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0)
- );
-end trb_net_term_ibuf;
-
-architecture trb_net_term_ibuf_arch of trb_net_term_ibuf is
-
- component trb_net_sbuf is
-
- generic (DATA_WIDTH : integer := 56;
- VERSION : integer := 1);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- -- Port to synchronous output.
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
-
-signal got_ack_internal, reg_ack_internal : std_logic; --should be raised for 1 cycle when ack
- --arrived
-signal is_locked, got_locked,release_locked : std_logic;
-signal got_eob_out, reg_eob_out: std_logic;
-signal sbuf_free, comb_next_read: std_logic;
-signal tmp_INT_DATAREADY_OUT: std_logic;
-signal tmp_INT_DATA_OUT: std_logic_vector(50 downto 0);
-
-type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_LOCKED_ERROR, GOT_UNDEFINED_ERROR);
-signal current_error_state, next_error_state : ERROR_STATE;
-
-signal next_rec_buffer_size_out, current_rec_buffer_size_out : std_logic_vector(3 downto 0);
- -- buffer size control
-
- begin
-
-
--- this process controls the writing of the media into the fifo
- FILTER_DATAREADY_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_ERROR_IN,
- is_locked, current_rec_buffer_size_out,
- current_error_state, release_locked,
- sbuf_free)
- begin -- process
- got_ack_internal <= '0';
- next_rec_buffer_size_out <= current_rec_buffer_size_out;
- next_error_state <= current_error_state;
- tmp_INT_DATA_OUT <= (others => '1');
- tmp_INT_DATAREADY_OUT <= '0';
- got_eob_out <= '0';
- got_locked <= is_locked;
-
- if MED_DATAREADY_IN = '1' then -- data word offered
- if MED_DATA_IN(TYPE_POSITION) = TYPE_ACK then
- got_ack_internal <= '1';
- if MED_DATA_IN(F1_POSITION) = F1_CHECK_ACK then
- next_rec_buffer_size_out <= MED_DATA_IN(BUFFER_SIZE_POSITION);
- end if;
- elsif MED_DATA_IN(TYPE_POSITION) = TYPE_TRM then
- got_eob_out <= '1'; --exactly when buffer is killed
- tmp_INT_DATA_OUT <= MED_DATA_IN;
- tmp_INT_DATAREADY_OUT <= '1';
- if release_locked = '0' then
- got_locked <= '1';
- end if;
- elsif MED_DATA_IN(TYPE_POSITION) = TYPE_EOB then
- got_eob_out <= '1';
- tmp_INT_DATAREADY_OUT <= '0';
- -- this should happen only one CLK cycle
- elsif sbuf_free = '0' then
- next_error_state <= GOT_OVERFLOW_ERROR;
- elsif is_locked = '1' then
- next_error_state <= GOT_LOCKED_ERROR;
- end if; -- end TYPE
- end if; -- end MED_DATAREADY_IN
- end process;
-
- MED_READ_OUT <= '1'; -- I always can read
-
-reg_buffer: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_rec_buffer_size_out <= (others => '0');
- reg_ack_internal <= '0';
- current_error_state <= IDLE;
- elsif CLK_EN = '1' then
- current_rec_buffer_size_out <= next_rec_buffer_size_out;
- reg_ack_internal <= got_ack_internal;
- current_error_state <= next_error_state;
- else
- current_rec_buffer_size_out <= current_rec_buffer_size_out;
- reg_ack_internal <= reg_ack_internal;
- current_error_state <= current_error_state;
- end if;
- end if;
- end process;
-
-
-
- SBUF: trb_net_sbuf
- generic map (DATA_WIDTH => 51, VERSION => 0)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => tmp_INT_DATAREADY_OUT,
- COMB_next_READ_OUT => comb_next_read,
- COMB_READ_IN => '1',
- COMB_DATA_IN => tmp_INT_DATA_OUT,
- SYN_DATAREADY_OUT => INT_DATAREADY_OUT,
- SYN_DATA_OUT => INT_DATA_OUT,
- SYN_READ_IN => INT_READ_IN
- );
-
- sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed
-
- release_locked <= CTRL_LOCKED(0);
- STAT_LOCKED(0) <= is_locked;
- STAT_LOCKED(15 downto 1) <= (others => '0');
-
- reg_locked: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- is_locked <= '0';
- reg_eob_out <= '0';
- elsif CLK_EN = '1' then
- if release_locked = '1' then
- is_locked <= '0';
- else
- is_locked <= got_locked;
- end if;
- reg_eob_out <= got_eob_out;
- else
- is_locked <= is_locked;
- reg_eob_out <= reg_eob_out;
- end if;
- end if;
- end process;
-
-
-
--- make STAT_BUFFER
--- STAT_BUFFER(3 downto 0) <= (fifo_depth(3 downto 0)-1); --divide by 2, since 2
- --buffers have to be stored
- STAT_BUFFER(3 downto 0) <= "0111"; --always "biggest fifo"
- STAT_BUFFER(7 downto 4) <= current_rec_buffer_size_out;
-
- STAT_BUFFER(8) <= reg_eob_out;
- STAT_BUFFER(9) <= reg_ack_internal;
-
- MAKE_ERROR_BITS : process(current_error_state)
- begin
- if current_error_state = IDLE then
- STAT_BUFFER(11 downto 10) <= "00";
- elsif current_error_state = GOT_OVERFLOW_ERROR then
- STAT_BUFFER(11 downto 10) <= "01";
- elsif current_error_state = GOT_LOCKED_ERROR then
- STAT_BUFFER(11 downto 10) <= "10";
- else
- STAT_BUFFER(11 downto 10) <= "11";
- end if;
- end process;
-
- STAT_BUFFER(31 downto 12) <= (others => '0');
-
-end trb_net_term_ibuf_arch;
-
+++ /dev/null
--- an active api together with an iobuf
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net_term_mbuf is
-
- generic (FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
- APL_GOT_TRM: out STD_LOGIC;
-
- APL_HOLD_TRM: in STD_LOGIC;
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
- );
-END trb_net_term_mbuf;
-
-architecture trb_net_term_mbuf_arch of trb_net_term_mbuf is
-
-component trb_net_iobuf is
-
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3); -- or the replyibuf
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading
-
- MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out STD_LOGIC;
- INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_IN: in STD_LOGIC;
-
- INT_INIT_DATAREADY_IN: in STD_LOGIC;
- INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_INIT_READ_OUT: out STD_LOGIC;
-
- INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
- INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_IN: in STD_LOGIC;
-
- INT_REPLY_DATAREADY_IN: in STD_LOGIC;
- INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_REPLY_READ_OUT: out STD_LOGIC;
-
- -- Status and control port
- STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
- CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
- CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
- );
-END component;
-
-component trb_net_term is
-
- generic (FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_DATAREADY_OUT: out STD_LOGIC;
- INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_IN: in STD_LOGIC;
-
- INT_DATAREADY_IN: in STD_LOGIC;
- INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
- INT_READ_OUT: out STD_LOGIC;
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
- APL_GOT_TRM: out STD_LOGIC;
-
- APL_HOLD_TRM: in STD_LOGIC;
- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0) -- see NewTriggerBusNetworkDescr
-
-
- -- Status and control port
-
- -- not needed now, but later
-
- );
-END component;
-
-component trb_net_io_multiplexer is
-
- generic (BUS_WIDTH : integer := 56;
- MULT_WIDTH : integer := 5);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- -- highest bits are mult.
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
-END component;
-
-signal apl_to_buf_INIT_DATAREADY: STD_LOGIC;
-signal apl_to_buf_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal apl_to_buf_INIT_READ : STD_LOGIC;
-
-signal buf_to_apl_INIT_DATAREADY: STD_LOGIC;
-signal buf_to_apl_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal buf_to_apl_INIT_READ : STD_LOGIC;
-
-signal apl_to_buf_REPLY_DATAREADY: STD_LOGIC;
-signal apl_to_buf_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal apl_to_buf_REPLY_READ : STD_LOGIC;
-
-signal buf_to_apl_REPLY_DATAREADY: STD_LOGIC;
-signal buf_to_apl_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0);
-signal buf_to_apl_REPLY_READ : STD_LOGIC;
-
--- for the connection to the multiplexer
-signal MED_INIT_DATAREADY_OUT : STD_LOGIC;
-signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_INIT_READ_IN : STD_LOGIC;
-
-signal MED_INIT_DATAREADY_IN : STD_LOGIC;
-signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_INIT_READ_OUT : STD_LOGIC;
-
-signal MED_REPLY_DATAREADY_OUT : STD_LOGIC;
-signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_REPLY_READ_IN : STD_LOGIC;
-
-signal MED_REPLY_DATAREADY_IN : STD_LOGIC;
-signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
-signal MED_REPLY_READ_OUT : STD_LOGIC;
-
-signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (1 downto 0);
-signal m_DATA_OUT : STD_LOGIC_VECTOR (101 downto 0);
-signal m_READ_IN : STD_LOGIC_VECTOR (1 downto 0);
-
-signal m_DATAREADY_IN : STD_LOGIC_VECTOR (1 downto 0);
-signal m_DATA_IN : STD_LOGIC_VECTOR (101 downto 0);
-signal m_READ_OUT : STD_LOGIC_VECTOR (1 downto 0);
-
-begin
-
- m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
- m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT;
- m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT;
- MED_INIT_READ_IN <= m_READ_IN(0);
- MED_REPLY_READ_IN <= m_READ_IN(1);
-
- MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
- MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
- MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0);
- MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51);
- m_READ_OUT(0) <= MED_INIT_READ_OUT;
- m_READ_OUT(1) <= MED_REPLY_READ_OUT;
-
-
- TERM_INIT: trb_net_term
-
- generic map (FIFO_TERM_BUFFER_DEPTH => 0)
-
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => APL_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
- APL_GOT_TRM => APL_GOT_TRM,
-
- APL_HOLD_TRM => APL_HOLD_TRM,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
-
- -- Internal direction port
- -- connect via private signals
-
- INT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
- INT_DATA_OUT => apl_to_buf_INIT_DATA,
- INT_READ_IN => apl_to_buf_INIT_READ,
-
- INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
- INT_DATA_IN => buf_to_apl_INIT_DATA,
- INT_READ_OUT => buf_to_apl_INIT_READ
-
- -- Status and control port
- -- not needed now, but later
- );
-
-TERM_REPLY: trb_net_term
-
- generic map (FIFO_TERM_BUFFER_DEPTH => 0)
-
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- -- "mini" APL, just to see the triggers coming in
-
- APL_HOLD_TRM => '0',
- APL_DTYPE_IN => (others => '0'),
- APL_ERROR_PATTERN_IN => (others => '0'),
-
- -- Internal direction port
- -- connect via private signals
-
- INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY,
- INT_DATA_OUT => apl_to_buf_REPLY_DATA,
- INT_READ_IN => apl_to_buf_REPLY_READ,
-
- INT_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
- INT_DATA_IN => buf_to_apl_REPLY_DATA,
- INT_READ_OUT => buf_to_apl_REPLY_READ
- -- Status and control port
- -- not needed now, but later
- );
-
-IOBUF: trb_net_iobuf
-
- generic map (INIT_DEPTH => 0,
- REPLY_DEPTH => 0)
-
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_INIT_DATA_OUT,
- MED_INIT_READ_IN => MED_INIT_READ_IN,
-
- MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_INIT_DATA_IN,
- MED_INIT_READ_OUT => MED_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
-
- MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
- MED_REPLY_READ_IN => MED_REPLY_READ_IN,
-
- MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_REPLY_DATA_IN,
- MED_REPLY_READ_OUT => MED_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
- INT_INIT_READ_IN => buf_to_apl_INIT_READ,
-
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
-
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
-
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
-
- -- Status and control port
- STAT_GEN => STAT_GEN,
- STAT_LOCKED => STAT_LOCKED,
- STAT_INIT_BUFFER => STAT_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_REPLY_BUFFER,
- CTRL_GEN => CTRL_GEN,
- CTRL_LOCKED => CTRL_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER
- );
-
- MPLEX: trb_net_io_multiplexer
- generic map (BUS_WIDTH => 52,
- MULT_WIDTH => 1)
- port map (
- CLK => CLK,
- RESET => RESET ,
- CLK_EN => CLK_EN,
-
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_READ_OUT => MED_READ_OUT,
-
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_READ_IN => MED_READ_IN,
-
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_READ_IN =>m_READ_OUT,
-
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_READ_OUT =>m_READ_IN,
-
- CTRL => MPLEX_CTRL
-
- );
-
-end trb_net_term_mbuf_arch;
-
+++ /dev/null
-------------------------------------------------------------------------------
---
--- This is a trigger reading application with interrupt signal generation
---
---
-------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.trb_net_std.all;
-
-
-entity trb_net_trigger_reader is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_OUT: out STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_IN: in STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_OUT: out STD_LOGIC; --
- APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_OUT: out STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
- -- Receiver port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_IN: in STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_OUT: out STD_LOGIC; -- Read data word
- -- APL Control port
- APL_RUN_IN: in STD_LOGIC; -- Data transfer is running
- --APL_MY_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_IN: in STD_LOGIC_VECTOR (7 downto 0);
-
- INTERNAL_TIME_OUT: out std_logic_vector(31 downto 0);
-
- TRB_INTERRUPT_OUT: out std_logic_vector(7 downto 0);
- TRB_TRIGGER_NUM_OUT: out std_logic_vector(7 downto 0);
- TRB_TRIGGER_TIME_OUT: out std_logic_vector(31 downto 0);
- TRB_TRIGGER_DATAREADY: out std_logic;
- TRB_TRIGGER_NUM_READ: in std_logic;
- TRB_TRIGGER_TIME_READ: in std_logic;
- TRB_TRIGGER_READ_ERROR: out std_logic;
-
- STAT_TRIGGER_READER: out std_logic_vector(31 downto 0)
- );
-end entity;
-
-
-
-architecture trb_net_trigger_reader_arch of trb_net_trigger_reader is
-
-
- component trb_net_fifo is
- generic (
- WIDTH : integer := 48; -- FIFO word width
- DEPTH : integer := 3); -- Depth of the FIFO, 2^(n+1)
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic; -- Full Flag
- EMPTY_OUT : out std_logic;
- DEPTH_OUT : out std_logic_vector(7 downto 0)
- );
- end component;
-
- signal buf_APL_READ_OUT : std_logic;
- signal buf_APL_DATA_OUT : std_logic_vector(47 downto 0);
- signal buf_APL_WRITE_OUT: std_logic;
- signal buf_APL_SEND_OUT, next_APL_SEND_OUT: std_logic;
- signal buf_APL_ERROR_PATTERN_OUT, next_APL_ERROR_PATTERN_OUT: std_logic_vector(31 downto 0);
- signal count_fifo: std_logic;
-
- signal fifo_data_in, next_fifo_data_in, fifo_data_out : std_logic_vector(39 downto 0);
- signal fifo_write_enable_in, next_fifo_write_enable_in : std_logic;
- signal fifo_read, next_fifo_read : std_logic;
- signal fifo_empty_out : std_logic;
-
- signal buf_TRB_TRIGGER_NUM_OUT : std_logic_vector(7 downto 0);
- signal buf_TRB_TRIGGER_TIME_OUT: std_logic_vector(31 downto 0);
-
- signal last_TRB_TRIGGER_NUM_READ, last_TRB_TRIGGER_TIME_READ : std_logic;
- signal trigger_num_is_read, next_trigger_num_is_read: std_logic;
- signal trigger_time_is_read, next_trigger_time_is_read: std_logic;
- signal buf_TRB_TRIGGER_READ_ERROR, next_TRB_TRIGGER_READ_ERROR: std_logic;
-
- signal next_STAT_TRIGGER_READER, buf_STAT_TRIGGER_READER : std_logic_vector(31 downto 0);
- signal timecounter, next_timecounter : std_logic_vector(31 downto 0);
- signal clkcounter, next_clkcounter : std_logic_vector(6 downto 0);
- --counter for us-timer
- begin
-
-
-
------------------------------------------
--- fifo for trigger data
------------------------------------------
- TRB_TRIGGER_DATAREADY <= not fifo_empty_out;
-
- trigger_fifo : trb_net_fifo
- generic map(
- WIDTH => 40,
- DEPTH => 3
- )
- port map(
- CLK => CLK,
- CLK_EN => CLK_EN,
- RESET => RESET,
- DATA_IN => fifo_data_in,
- WRITE_ENABLE_IN => fifo_write_enable_in,
- DATA_OUT => fifo_data_out,
- READ_ENABLE_IN => fifo_read,
- FULL_OUT => open,
- EMPTY_OUT => fifo_empty_out,
- DEPTH_OUT => open
- );
-
-
------------------------------------------
--- detect and answer triggers
------------------------------------------
- process(APL_DATA_IN, APL_TYP_IN, APL_DATAREADY_IN, buf_APL_READ_OUT, timecounter, APL_SEQNR_IN)
- begin
- next_fifo_write_enable_in <= '0';
- next_fifo_data_in <= (others => '0');
- next_APL_SEND_OUT <= '0';
- if APL_TYP_IN = TYPE_TRM and APL_DATAREADY_IN = '1' and buf_APL_READ_OUT = '1' then
- next_fifo_data_in(7 downto 0) <= APL_SEQNR_IN;
- next_fifo_data_in(39 downto 8)<= timecounter;
- next_fifo_write_enable_in <= '1';
- next_APL_SEND_OUT <= '1';
- next_APL_ERROR_PATTERN_OUT <= x"00000000";
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- fifo_data_in <= (others => '0');
- fifo_write_enable_in <= '0';
- buf_APL_SEND_OUT <= next_APL_SEND_OUT;
- buf_APL_ERROR_PATTERN_OUT <= (others => '0');
- --buf_STAT_TRIGGER_READER <= (others => '0');
- else
- fifo_data_in <= next_fifo_data_in;
- fifo_write_enable_in <= next_fifo_write_enable_in;
- buf_APL_SEND_OUT <= next_APL_SEND_OUT;
- buf_APL_ERROR_PATTERN_OUT <= next_APL_ERROR_PATTERN_OUT;
- --buf_STAT_TRIGGER_READER <= next_STAT_TRIGGER_READER;
- end if;
- end if;
- end process;
-
-buf_STAT_TRIGGER_READER(1) <= fifo_write_enable_in;
-buf_STAT_TRIGGER_READER(2) <= fifo_read;
-
-STAT_TRIGGER_READER <= buf_STAT_TRIGGER_READER;
-
----------------------------------------
--- prepare trigger fifodata for readout
----------------------------------------
-
- buf_TRB_TRIGGER_NUM_OUT <= fifo_data_out(7 downto 0);
- buf_TRB_TRIGGER_TIME_OUT <= fifo_data_out(39 downto 8);
-
-
- process(TRB_TRIGGER_NUM_READ, TRB_TRIGGER_TIME_READ, trigger_num_is_read,
- trigger_time_is_read, buf_TRB_TRIGGER_READ_ERROR, last_TRB_TRIGGER_NUM_READ,
- last_TRB_TRIGGER_TIME_READ, fifo_empty_out)
- begin
- next_trigger_num_is_read <= trigger_num_is_read;
- next_trigger_time_is_read <= trigger_time_is_read;
- fifo_read <= '0';
- next_TRB_TRIGGER_READ_ERROR <= '0';
-
- if trigger_num_is_read = '1' and trigger_time_is_read = '1' then
- next_trigger_num_is_read <= '0';
- next_trigger_time_is_read <= '0';
- fifo_read <= '1';
- next_TRB_TRIGGER_READ_ERROR <= buf_TRB_TRIGGER_READ_ERROR;
- end if;
-
- if TRB_TRIGGER_NUM_READ = '1' then
- next_TRB_TRIGGER_READ_ERROR <= '0';
- if trigger_num_is_read = '1' then
- next_TRB_TRIGGER_READ_ERROR <= '1';
- end if;
- next_trigger_num_is_read <= '1';
- end if;
-
- if TRB_TRIGGER_TIME_READ = '1' then
- next_TRB_TRIGGER_READ_ERROR <= '0';
- if trigger_time_is_read = '1' then
- next_TRB_TRIGGER_READ_ERROR <= '1';
- end if;
- next_trigger_time_is_read <= '1';
- end if;
-
- if fifo_empty_out = '1' then
- next_TRB_TRIGGER_READ_ERROR <= '1';
- end if;
- end process;
-
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
--- last_TRB_TRIGGER_NUM_READ <= '0';
--- last_TRB_TRIGGER_TIME_READ <= '0';
- buf_TRB_TRIGGER_READ_ERROR <= '0';
- trigger_num_is_read <= '0';
- trigger_time_is_read <= '0';
--- fifo_read <= '0';
- else
--- last_TRB_TRIGGER_NUM_READ <= TRB_TRIGGER_NUM_READ;
--- last_TRB_TRIGGER_TIME_READ <= TRB_TRIGGER_TIME_READ;
- buf_TRB_TRIGGER_READ_ERROR <= next_TRB_TRIGGER_READ_ERROR;
- trigger_num_is_read <= next_trigger_num_is_read;
- trigger_time_is_read <= next_trigger_time_is_read;
--- fifo_read <= next_fifo_read;
- end if;
- end if;
- end process;
-
-
------------------------------------------
--- Generate internal 32Bit timer @ 1 MHz
------------------------------------------
-
- process(clkcounter, timecounter)
- begin
- next_clkcounter <= clkcounter + 1;
- next_timecounter <= timecounter;
- if(clkcounter = 98) then
- next_clkcounter <= (others => '0');
- next_timecounter <= timecounter + 1;
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- clkcounter <= (others => '0');
- timecounter <= (others => '0');
- else
- clkcounter <= next_clkcounter;
- timecounter <= next_timecounter;
- end if;
- end if;
- end process;
-
-
-
-
------------------------------------------
--- Output generation
------------------------------------------
- APL_DATA_OUT <= (others => '0');
- APL_READ_OUT <= buf_APL_READ_OUT;
- APL_WRITE_OUT <= '0';
- APL_SEND_OUT <= buf_APL_SEND_OUT;
- APL_ERROR_PATTERN_OUT <= buf_APL_ERROR_PATTERN_OUT;
- APL_TARGET_ADDRESS_OUT <= x"0001";
- APL_DTYPE_OUT <= "0000";
- APL_SHORT_TRANSFER_OUT <= '1';
- buf_APL_READ_OUT <= '1';
-
- TRB_TRIGGER_NUM_OUT <= buf_TRB_TRIGGER_NUM_OUT;
- TRB_TRIGGER_TIME_OUT <= buf_TRB_TRIGGER_TIME_OUT;
- TRB_TRIGGER_READ_ERROR <= buf_TRB_TRIGGER_READ_ERROR;
-
- INTERNAL_TIME_OUT <= timecounter;
-
-end architecture;
+++ /dev/null
--- this is a dummy apl, just sending short transfers / triggers
-
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net_trigger_sender is
- generic (TARGET_ADDRESS : STD_LOGIC_VECTOR (15 downto 0) := x"0002"
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
- APL_WRITE_OUT: out STD_LOGIC; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_IN: in STD_LOGIC; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_OUT: out STD_LOGIC; --
- APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_OUT: out STD_LOGIC; -- Release sending of the data
- APL_TARGET_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
- APL_TYP_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_IN: in STD_LOGIC; -- Data word is valid and might be read out
- APL_READ_OUT: out STD_LOGIC; -- Read data word
-
- -- APL Control port
- APL_RUN_IN: in STD_LOGIC; -- Data transfer is running
--- APL_MY_ADDRESS_OUT: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_IN: in STD_LOGIC_VECTOR (7 downto 0)
-
- );
-end trb_net_trigger_sender;
-
-architecture trb_net_trigger_sender_arch of trb_net_trigger_sender is
-
- type SENDER_STATE is (IDLE, RUNNING, MY_ERROR);
- signal current_state, next_state : SENDER_STATE;
- signal next_counter, counter : std_logic_vector(23 downto 0);
- signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(23 downto 0);
- signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic;
- signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic;
-
- begin
-
- APL_READ_OUT <= '1'; --just read, do not check
- APL_DTYPE_OUT <= x"1";
- APL_ERROR_PATTERN_OUT <= x"00000100";
- APL_TARGET_ADDRESS_OUT <= x"0000";
- --APL_DATA_OUT <= reg_counter;
- APL_SHORT_TRANSFER_OUT <= '1';
- APL_WRITE_OUT <= '0';
- APL_DATA_OUT <= (others => '0');
-
- SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, counter, APL_RUN_IN, RESET)
- begin -- process
- next_APL_SEND_OUT <= '0';
- next_state <= MY_ERROR;
- next_counter <= counter + 1;
--------------------------------------------------------------------------
--- IDLE
--------------------------------------------------------------------------
- if current_state = IDLE then
- if APL_RUN_IN = '0' and counter(7 downto 0) = 0 then
- next_state <= RUNNING;
- next_APL_SEND_OUT <= '1';
- else
- next_state <= IDLE;
- end if;
------------------------------------------------------------------------
--- RUNNING
------------------------------------------------------------------------
- elsif current_state = RUNNING then
- next_state <= RUNNING;
- if APL_RUN_IN = '1' then
- next_state <= IDLE;
- --else
- -- next_state <= RUNNING;
- end if;
- end if; -- end state switch
- end process;
-
-APL_SEND_OUT <= buf_APL_SEND_OUT;
-
- CLK_REG: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_state <= IDLE;
- buf_APL_SEND_OUT <= '0';
- counter <= (others => '0');
- elsif CLK_EN = '1' then
- current_state <= next_state;
- buf_APL_SEND_OUT <= next_APL_SEND_OUT;
- counter <= next_counter;
- else
- current_state <= current_state;
- buf_APL_SEND_OUT <= buf_APL_SEND_OUT;
- counter <= counter;
- end if;
- end if;
- end process;
-
-end trb_net_trigger_sender_arch;
+++ /dev/null
---------------------------------------------------------------------------------
--- The standard endpoint for all devices, like DTU, MU etc.
--- The idea is to be independent from the "user"
---
--- The endpoint works like a RAM
--- Memory Map:
---
--- 0x000 - 0x0FF global registers
---
--- 0x100 - 0x1FF 16 sender ENDOBUFs (each 16 addresses)
---
--- 0x200 - 0x2FF 16 receiver ENDIBUFs (each 16 addresses)
---
--- for each ENDBUF, Adress 0x0 is the FIFO itself
--- 0x1 is the status register
--- 0x2 is the control register
----------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
---Entity decalaration for clock generator
-entity TRBNETENDPOINT is port(
- RESET : in std_logic;
- clk: in std_logic;
---pin connections -------------------------------------------------------
- RD: in STD_LOGIC; -- Read strobe
- WR: in STD_LOGIC; -- Write strobe
- -- for a single transfer, the strobes MUST NOT be longer
- -- then one cycle (already sync signals)
- DATA_OUT: out STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus
- DATA_IN : in STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus
- ADDRESS: in STD_LOGIC_VECTOR (11 downto 0) -- Adress lines for the
- -- given space
- );
-END TRBNETENDPOINT;
-
-architecture arch_TRBNETENDPOINT of TRBNETENDPOINT is
-
- component FIFO is
- generic (WIDTH : integer := 8; -- FIFO word width
- DEPTH : integer := 8); -- Depth of the FIFO
-
- port (DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
- DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Out put data
- CLK : in std_logic; -- System Clock
- RESET : in std_logic; -- System global Reset
- RE : in std_logic; -- Read Enable
- WE : in std_logic; -- Write Enable
- FULL : buffer std_logic; -- Full Flag
- EMPTY : buffer std_logic); -- Empty Flag
- end component;
-
- signal DATA_FIFO1 : STD_LOGIC_VECTOR(31 downto 0);
- signal DATA_FIFO2 : STD_LOGIC_VECTOR(31 downto 0);
-
- signal WE1 : STD_LOGIC;
- signal WE2 : STD_LOGIC;
-
-begin -- arch_TRBNETENRPOINT
-
- FIFO1: FIFO
- generic map (
- WIDTH => 32,
- DEPTH => 8
- )
- port map (
- Data_in => DATA_IN,
- Data_out => DATA_FIFO1,
- clk => clk,
- Reset => RESET,
- WE => WE1,
- RE => '0'
- );
-
- FIFO2: FIFO
- generic map (
- WIDTH => 32,
- DEPTH => 8
- )
- port map (
- Data_in => DATA_IN,
- Data_out => DATA_FIFO2,
- clk => clk,
- Reset => RESET,
- WE => WE2,
- RE => '0'
- );
-
-
-process (CLK)
-begin -- process
- if CLK'event and CLK = '1' then -- rising clock edge
- if RD = '1' and ADDRESS(2) = '1' then
- DATA_OUT <= DATA_FIFO1;
- --DATA_OUT <= x"affeaffe";
- end if;
- if RD = '1' and ADDRESS(2) = '0' then
- --DATA_OUT <= x"deadface";
- DATA_OUT <= DATA_FIFO2;
- end if;
- if WR = '1' and ADDRESS(2) = '1' then
- WE1 <= '1';
- else
- WE1 <= '0';
- end if;
- if WR = '1' and ADDRESS(2) = '0' then
- WE2 <= '1';
- else
- WE2 <= '0';
- end if;
- end if;
-end process;
-
-end arch_TRBNETENDPOINT;
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 26/6/07
--- Design Name: vulom3
--- Module Name: beam_ramp - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: Programmable delayer and shaper for beam signal
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity beam_ramp is
- port ( clk_300MHz : in std_logic;
- clk_50MHz : in std_logic;
- input : in std_logic;
- output_inhibit : out std_logic;
- output_external : out std_logic;
- delay_value : in std_logic_vector(7 downto 0);
- width_value_inhibit : in std_logic_vector(7 downto 0);
- width_value_external : in std_logic_vector(7 downto 0)
- );
-end beam_ramp;
-
-architecture Behavioral of beam_ramp is
-
-signal count_ck : std_logic_vector(23 downto 0);
-signal clk_10Hz : std_logic;
-signal input_r, input_q, output_s_inhibit, output_s_external : std_logic;
-signal count_delay, count_width_inhibit, count_width_external : std_logic_vector(7 downto 0);
-type state_type is (reset, del, wid);
-signal state : state_type;
-
-
-
-begin
-
- ck: process(clk_50MHz)
- begin
- if rising_edge(clk_50MHz) then
- if count_ck = x"2625a0" then --2,5e6
- count_ck <= x"000000";
- clk_10Hz <= not clk_10Hz;
- else
- count_ck <= count_ck + 1;
- end if;
-
- output_inhibit <= output_s_inhibit;
- output_external <= output_s_external;
-
- end if;
- end process;
-
- latch: process(clk_300MHz)
- begin
- if rising_edge(clk_300MHz) then
- if input_r = '1' then
- input_q <= '0';
- elsif input = '1' then
- input_q <= '1';
- end if;
-
- end if;
- end process;
-
- fsm : process(clk_10Hz)
- begin
- if rising_edge(clk_10Hz) then
- case (state) is
-
- when reset =>
- input_r <= '0';
- count_delay <=delay_value;
- count_width_inhibit <= width_value_inhibit;
- count_width_external <= width_value_external + width_value_inhibit;
- if input_q = '0' then
- state <= reset;
- else
- state <= del;
- end if;
-
--- when reset =>
--- input_r <= '0';
--- count_delay <=delay_value;
--- count_width_inhibit <= width_value_inhibit + 1;
--- count_width_external <= width_value_external + 1;
--- if input_q = '0' then
--- state <= reset;
--- else
--- state <= del;
--- end if;
-
- when del =>
- if count_delay = x"00" then
- state <= wid;
- else
- count_delay <= count_delay - 1;
- state <= del;
- end if;
-
- when wid =>
- input_r <= '1';
- if (count_width_inhibit = x"00" and count_width_external = x"00") then
- output_s_inhibit <= '0';
- output_s_external <= '0';
- state <= reset;
- elsif count_width_external = x"00" then
- output_s_inhibit <= '1';
- output_s_external <= '0';
- count_width_inhibit <= count_width_inhibit - 1;
- state <= wid;
- elsif count_width_inhibit = x"00" then
- output_s_inhibit <= '0';
- output_s_external <= '1';
- count_width_external <= count_width_external - 1;
- state <= wid;
- else
- output_s_inhibit <= '1';
- output_s_external <= '1';
- count_width_inhibit <= count_width_inhibit - 1;
- count_width_external <= count_width_external - 1;
- state <= wid;
- end if;
-
- when others =>
- state <= reset;
-
- end case;
- end if;
- end process;
-
-
-
-end Behavioral;
-
-
-
-
-
-
-
---entity beam_ramp is
--- port ( clk_300MHz : in std_logic;
--- clk_50MHz : in std_logic;
--- input : in std_logic;
--- output_inhibit : out std_logic;
--- output_external : out std_logic;
--- delay_value : in std_logic_vector(7 downto 0);
--- width_value_inhibit : in std_logic_vector(7 downto 0);
--- width_value_external : in std_logic_vector(7 downto 0)
--- );
---end beam_ramp;
---
---architecture Behavioral of beam_ramp is
---
---signal count_ck : std_logic_vector(24 downto 0);
---signal clk_10Hz : std_logic;
---signal input_r, input_q, output_s_inhibit, output_s_external : std_logic;
---signal count_delay, count_width_inhibit, count_width_external : std_logic_vector(7 downto 0);
---type state_type is (reset, del, wid);
---signal state : state_type;
---
---
---
---begin
---
--- ck: process(clk_50MHz)
--- begin
--- if rising_edge(clk_50MHz) then
--- count_ck <= count_ck + 1;
--- clk_10Hz <= count_ck(22);
---
--- output_inhibit <= output_s_inhibit;
--- output_external <= output_s_external;
---
--- end if;
--- end process;
---
--- latch: process(clk_300MHz)
--- begin
--- if rising_edge(clk_300MHz) then
--- if input_r = '1' then
--- input_q <= '0';
--- elsif input = '1' then
--- input_q <= '1';
--- end if;
---
--- end if;
--- end process;
---
--- fsm : process(clk_10Hz)
--- begin
--- if rising_edge(clk_10Hz) then
--- case (state) is
---
--- when reset =>
--- input_r <= '0';
--- count_delay <=delay_value;
--- count_width_inhibit <= width_value_inhibit + 1;
--- count_width_external <= width_value_external + 1;
--- if input_q = '0' then
--- state <= reset;
--- else
--- state <= del;
--- end if;
---
--- when del =>
--- if count_delay = x"00" then
--- state <= wid;
--- else
--- count_delay <= count_delay - 1;
--- state <= del;
--- end if;
---
--- when wid =>
--- input_r <= '1';
--- if (count_width_inhibit = x"00" and count_width_external = x"00") then
--- output_s_inhibit <= '0';
--- output_s_external <= '0';
--- state <= reset;
--- elsif count_width_external = x"00" then
--- output_s_inhibit <= '1';
--- output_s_external <= '0';
--- count_width_inhibit <= count_width_inhibit - 1;
--- state <= wid;
--- elsif count_width_inhibit = x"00" then
--- output_s_inhibit <= '0';
--- output_s_external <= '1';
--- count_width_external <= count_width_external - 1;
--- state <= wid;
--- else
--- output_s_inhibit <= '1';
--- output_s_external <= '1';
--- count_width_inhibit <= count_width_inhibit - 1;
--- count_width_external <= count_width_external - 1;
--- state <= wid;
--- end if;
---
--- when others =>
--- state <= reset;
---
--- end case;
--- end if;
--- end process;
---
---
---
---end Behavioral;
\ No newline at end of file
+++ /dev/null
-----------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 09:54:15 07/11/2007
--- Design Name: vulom3
--- Module Name: bus_data_com4 - Behavioral
--- Project Name: triggerbox
--- Target Devices: XC4VLX25-10SF363
--- Tool versions:
--- Description: Data communication to TRB
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments: Whole datastream with 16 bit summer usead as error check
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity bus_data_com5 is
- PORT(
- clk_300MHz : in std_logic;
- clk_100MHz : in std_logic;
- gts_pulse : in std_logic;
- cal_trigger : in std_logic;
- bus_busy : in std_logic; -- not used
- bus_ack : in std_logic;
- bus_retx : in std_logic;
- latch : in std_logic_vector(6 downto 0);
- latch_dsc : in std_logic_vector(6 downto 0);
- scaler_pti1 : in std_logic_vector(31 downto 0);
- scaler_pti2 : in std_logic_vector(31 downto 0);
- scaler_pti3 : in std_logic_vector(31 downto 0);
- scaler_pti4 : in std_logic_vector(31 downto 0);
- scaler_pti5 : in std_logic_vector(31 downto 0);
- scaler_ts : in std_logic_vector(31 downto 0);
- scaler_vs : in std_logic_vector(31 downto 0);
- scaler_dead : in std_logic_vector(31 downto 0);
- bus_inhibit : out std_logic;
- dtu_inhibit : out std_logic;
- ecl_bus_data : out std_logic_vector(1 downto 0);
- ecl_bus_clk : out std_logic;
- com_run : in std_logic;
- dtu_bus_t : out std_logic;
- dtu_bus_ts : out std_logic;
- dtu_bus_td : out std_logic_vector (3 downto 0);
- DTU_CODE_SELECT : in std_logic_vector(4 downto 0);
- out_inhibit : in std_logic;
- cal_inhibit : in std_logic;
- DEBUG_REG_01 : out std_logic_vector(15 downto 0);
- TRB_BUSY_ENABLE : in std_logic
- );
-
-end bus_data_com5;
-
-architecture Behavioral of bus_data_com5 is
-signal count : integer range 0 to 300 := 0;
-signal tag_counter_trb, tag_counter_dtu : std_logic_vector(15 downto 0):=x"0000";
-signal cal_trigger_s, cal_trigger_d1, cal_trigger_pulse, cal_trigger_pulse_d, bus_busy_s, bus_busy_d1 : std_logic := '0';
-type state_type_a is (ready, start_sequence_0, start_sequence_1, start_sequence_2, start_sequence_3,
- start_sequence_4, start_sequence_5, start_sequence_6, start_sequence_7,
- normal_code_0, normal_code_1, calib_code_0, calib_code_1,
- xfer_0, xfer_0alter, xfer_1, xfer_2, xfer_3, xfer_4, xfer_5, xfer_6,
- xfer_7, xfer_8, xfer_9, xfer_10, xfer_11, xfer_12, xfer_13, xfer_14, xfer_15,
- wait_for_busy, hold_busy);
-signal state_a : state_type_a;
-type state_type_b is (tag, latches, scalers_0, scalers_1, scalers_2, scalers_3, scalers_4, scalers_5,
- scalers_6, scalers_7, scalers_8, scalers_9, scalers_10, scalers_11, scalers_12,
- scalers_13, scalers_14, scalers_15, checksum_0, checksum_1, finished);
-signal state_b : state_type_b;
-type state_type_c is (idle, begin_run_0, begin_run_1, end_run_0, end_run_1, norm_event_0, norm_event_1,
- calib_event_0, calib_event_1, tag_low_0, tag_low_1, tag_high_0, tag_high_1,
- tag_prio_0, tag_prio_1, wait_last, count_incr, wait_for_trb);
-signal state_c : state_type_c;
-
-signal xfer_buffer : std_logic_vector(15 downto 0):=x"0000";
-signal latch_s, latch_dsc_s : std_logic_vector(6 downto 0):="0000000";
-signal gts_trb_r, gts_trb_q, gts_q_d, gts_dtu_r, gts_dtu_q : std_logic := '0';
-signal checksum : std_logic_vector(31 downto 0):=x"00000000";
-signal scaler_pti1_s, scaler_pti2_s, scaler_pti3_s, scaler_pti4_s, scaler_pti5_s, scaler_ts_s,
- scaler_vs_s, scaler_dead_s : std_logic_vector(31 downto 0);
-signal com_run_s, trb_run, trb_run_s, bus_ack_s, bus_retx_s : std_logic:='0';
-signal ack_accu, retx_accu : std_logic_vector(3 downto 0);
-signal gts_from_trb, cal_trigger_from_trb : std_logic:='0';
-signal trb_go_norm, trb_go_norm_s, trb_go_calib, trb_go_calib_s, trb_finished : std_logic;
-signal dtu_start : std_logic;
-signal dtu_code : std_logic_vector(3 downto 0);
-signal prepared_code : std_logic_vector(3 downto 0);
-begin
- delay : process(clk_100MHz)
- begin
- if rising_edge(clk_100MHz) then
- scaler_pti1_s <= scaler_pti1;
- scaler_pti2_s <= scaler_pti2;
- scaler_pti3_s <= scaler_pti3;
- scaler_pti4_s <= scaler_pti4;
- scaler_pti5_s <= scaler_pti5;
- scaler_ts_s <= scaler_ts;
- scaler_vs_s <= scaler_vs;
- scaler_dead_s <= scaler_dead;
- latch_s <= latch;
- latch_dsc_s <= latch_dsc;
- bus_busy_s <= bus_busy;
- bus_ack_s <= bus_ack;
- bus_retx_s <= bus_retx;
- end if;
- end process;
- input_gts : process(clk_300MHz)
- begin
- if rising_edge(clk_300MHz) then
- if gts_dtu_r = '1' then --gts latch for trb bus
- gts_dtu_q <= '0';
- elsif gts_pulse = '1' then
- gts_dtu_q <= '1';
- end if;
- dtu_inhibit <= (not com_run) or dtu_start;
--- dtu_inhibit <= dtu_start;
- end if;
- end process;
- input_cal : process(clk_100MHz)
- begin
- if rising_edge(clk_100MHz) then
- cal_trigger_s <= cal_trigger;
- cal_trigger_d1 <= cal_trigger_s;
- cal_trigger_pulse <= cal_trigger_s and not cal_trigger_d1 and not out_inhibit;
- end if;
- end process;
----------------------------------------------------------------------- TRB comm
- fsm : process(clk_100MHz) --TX lenght: 3.1-3.2 µs
- begin
- if rising_edge(clk_100MHz) then
- if com_run = '0' then
- state_a <= ready;
- else
- case state_a is
- when ready =>
- DEBUG_REG_01(4 downto 0) <= "00001";
- ecl_bus_data <= "00";
- ecl_bus_clk <= '0';
- bus_inhibit <= '0';
- trb_finished <= '1';
- trb_go_norm_s <= trb_go_norm;
- trb_go_calib_s <= trb_go_calib;
- if (trb_go_norm or trb_go_calib) = '1' then
- state_a <= start_sequence_0;
- else state_a <= ready;
- end if;
-----------------------------
- when start_sequence_0 =>
- DEBUG_REG_01(4 downto 0) <= "00010";
- trb_finished <= '0';
- bus_inhibit <= '1';
- ecl_bus_data <= "01";
- ecl_bus_clk <= '0';
- ack_accu <= "0000";
- retx_accu <= "0000";
- state_a <= start_sequence_1;
- when start_sequence_1 =>
- DEBUG_REG_01(4 downto 0) <= "00011";
- gts_trb_r <= '1';
- ecl_bus_clk <= '1';
- state_a <= start_sequence_2;
- when start_sequence_2 =>
- DEBUG_REG_01(4 downto 0) <= "00100";
- ecl_bus_data <= "10";
- ecl_bus_clk <= '0';
- state_a <= start_sequence_3;
- when start_sequence_3 =>
- DEBUG_REG_01(4 downto 0) <= "00101";
- ecl_bus_clk <= '1';
- state_a <= start_sequence_4;
- when start_sequence_4 =>
- DEBUG_REG_01(4 downto 0) <= "00110";
- ecl_bus_data <= "01";
- ecl_bus_clk <= '0';
- state_a <= start_sequence_5;
- when start_sequence_5 =>
- DEBUG_REG_01(4 downto 0) <= "00111";
- ecl_bus_clk <= '1';
- state_a <= start_sequence_6;
- when start_sequence_6 =>
- DEBUG_REG_01(4 downto 0) <= "01000";
- ecl_bus_data <= "10";
- ecl_bus_clk <= '0';
- state_a <= start_sequence_7;
- when start_sequence_7 =>
- DEBUG_REG_01(4 downto 0) <= "01001";
- ecl_bus_clk <= '1';
- if trb_go_norm_s = '1' then
- state_a <= normal_code_0;
- elsif trb_go_calib_s = '1' then
- state_a <= calib_code_0;
- else state_a <= ready;
- end if;
-----------------------------------------------
- when normal_code_0 =>
- DEBUG_REG_01(4 downto 0) <= "01010";
- ecl_bus_data <= "01";
- ecl_bus_clk <= '0';
- state_a <= normal_code_1;
- when normal_code_1 =>
- DEBUG_REG_01(4 downto 0) <= "01011";
- checksum <= x"00000001";
- ecl_bus_clk <= '1';
- state_a <= xfer_0;
- when calib_code_0 =>
- DEBUG_REG_01(4 downto 0) <= "01100";
- ecl_bus_data <= "11";
- ecl_bus_clk <= '0';
- state_a <= calib_code_1;
- when calib_code_1 =>
- DEBUG_REG_01(4 downto 0) <= "01101";
- checksum <= x"00000003";
- ecl_bus_clk <= '1';
- state_a <= xfer_0;
----------------------------------------------------
- when xfer_0 =>
- DEBUG_REG_01(4 downto 0) <= "01110";
- checksum <= checksum + xfer_buffer;
- ecl_bus_data <= xfer_buffer(1 downto 0);
- ecl_bus_clk <= '0';
- state_a <= xfer_1;
- when xfer_0alter =>
- DEBUG_REG_01(4 downto 0) <= "01111";
- ecl_bus_data <= xfer_buffer(1 downto 0);
- ecl_bus_clk <= '0';
- state_a <= xfer_1;
- when xfer_1 =>
- DEBUG_REG_01(4 downto 0) <= "10000";
- ecl_bus_clk <= '1';
- state_a <= xfer_2;
- when xfer_2 =>
- DEBUG_REG_01(4 downto 0) <= "10001";
- ecl_bus_data <= xfer_buffer(3 downto 2);
- ecl_bus_clk <= '0';
- state_a <= xfer_3;
- when xfer_3 =>
- DEBUG_REG_01(4 downto 0) <= "10010";
- ecl_bus_clk <= '1';
- state_a <= xfer_4;
- when xfer_4 =>
- DEBUG_REG_01(4 downto 0) <= "10011";
- ecl_bus_data <= xfer_buffer(5 downto 4);
- ecl_bus_clk <= '0';
- state_a <= xfer_5;
- when xfer_5 =>
- DEBUG_REG_01(4 downto 0) <= "10100";
- ecl_bus_clk <= '1';
- state_a <= xfer_6;
- when xfer_6 =>
- DEBUG_REG_01(4 downto 0) <= "10101";
- ecl_bus_data <= xfer_buffer(7 downto 6);
- ecl_bus_clk <= '0';
- state_a <= xfer_7;
- when xfer_7 =>
- DEBUG_REG_01(4 downto 0) <= "10110";
- ecl_bus_clk <= '1';
- state_a <= xfer_8;
- when xfer_8 =>
- DEBUG_REG_01(4 downto 0) <= "10111";
- ecl_bus_data <= xfer_buffer(9 downto 8);
- ecl_bus_clk <= '0';
- state_a <= xfer_9;
- when xfer_9 =>
- DEBUG_REG_01(4 downto 0) <= "11000";
- ecl_bus_clk <= '1';
- state_a <= xfer_10;
- when xfer_10 =>
- DEBUG_REG_01(4 downto 0) <= "11001";
- ecl_bus_data <= xfer_buffer(11 downto 10);
- ecl_bus_clk <= '0';
- state_a <= xfer_11;
-
- when xfer_11 =>
- DEBUG_REG_01(4 downto 0) <= "11010";
- ecl_bus_clk <= '1';
- state_a <= xfer_12;
- when xfer_12 =>
- DEBUG_REG_01(4 downto 0) <= "11011";
- ecl_bus_data <= xfer_buffer(13 downto 12);
- ecl_bus_clk <= '0';
- state_a <= xfer_13;
- when xfer_13 =>
- DEBUG_REG_01(4 downto 0) <= "11100";
- ecl_bus_clk <= '1';
- state_a <= xfer_14;
- when xfer_14 =>
- DEBUG_REG_01(4 downto 0) <= "11101";
- ecl_bus_data <= xfer_buffer(15 downto 14);
- ecl_bus_clk <= '0';
- state_a <= xfer_15;
- when xfer_15 =>
- DEBUG_REG_01(4 downto 0) <= "11110";
- ecl_bus_clk <= '1';
- state_a <= xfer_6;
- if state_b = checksum_0 then
- state_a <= xfer_0alter;
- elsif state_b = checksum_1 then
- state_a <= xfer_0alter;
- elsif state_b = finished then
- state_a <= wait_for_busy;
- else state_a <= xfer_0;
- end if;
------------------------------------------------------
- when wait_for_busy =>
- DEBUG_REG_01(4 downto 0) <= "11110";
- ecl_bus_clk <= '0';
- ecl_bus_data <= "00";
- state_a <= hold_busy;
- when hold_busy =>
- DEBUG_REG_01(4 downto 0) <= "11111";
- if bus_ack_s = '0' and ack_accu /= "0000" then --ack accumulator
- ack_accu <= ack_accu - 1;
- elsif bus_ack_s = '1' and ack_accu /= "1111" then
- ack_accu <= ack_accu + 1;
- end if;
- if bus_retx_s = '0' and retx_accu /= "0000" then --retransmit accumulator
- retx_accu <= retx_accu - 1;
- elsif bus_retx_s = '1' and retx_accu /= "1111" then
- retx_accu <= retx_accu + 1;
- end if;
- if retx_accu = 10 then
- state_a <= start_sequence_0;
- elsif (ack_accu = 10 or com_run = '0') or TRB_BUSY_ENABLE = '0' then
- state_a <= ready;
- else state_a <= hold_busy;
- end if;
----------------------------------------------------------------------
- when others =>
- DEBUG_REG_01(4 downto 0) <= "00000";
- state_a <= ready;
- end case;
- end if;
- end if;
- end process;
- fsm2 : process(clk_100MHz)
- begin
- if rising_edge(clk_100MHz) then
- if com_run = '0' then
- state_b <= tag;
- else
- case state_b is
- when tag =>
- DEBUG_REG_01(9 downto 5) <= "00001";
- xfer_buffer <= tag_counter_dtu - 1;
- if state_a = xfer_13 then
- state_b <= latches;
- else state_b <= tag;
- end if;
- when latches =>
- DEBUG_REG_01(9 downto 5) <= "00010";
- xfer_buffer <= '0' & latch_dsc_s & '0' & latch_s;
- if state_a = xfer_13 then
- state_b <= scalers_0;
- else state_b <= latches;
- end if;
- when scalers_0 =>
- DEBUG_REG_01(9 downto 5) <= "00011";
- xfer_buffer <= scaler_pti1_s(15 downto 0);
- if state_a = xfer_13 then
- state_b <= scalers_1;
- else state_b <= scalers_0;
- end if;
- when scalers_1 =>
- DEBUG_REG_01(9 downto 5) <= "00100";
- xfer_buffer <= scaler_pti1_s(31 downto 16);
- if state_a = xfer_13 then
- state_b <= scalers_2;
- else state_b <= scalers_1;
- end if;
- when scalers_2 =>
- DEBUG_REG_01(9 downto 5) <= "00101";
- xfer_buffer <= scaler_pti2_s(15 downto 0);
- if state_a = xfer_13 then
- state_b <= scalers_3;
- else state_b <= scalers_2;
- end if;
- when scalers_3 =>
- DEBUG_REG_01(9 downto 5) <= "00110";
- xfer_buffer <= scaler_pti2_s(31 downto 16);
- if state_a = xfer_13 then
- state_b <= scalers_4;
- else state_b <= scalers_3;
- end if;
- when scalers_4 =>
- DEBUG_REG_01(9 downto 5) <= "00111";
- xfer_buffer <= scaler_pti3_s(15 downto 0);
- if state_a = xfer_13 then
- state_b <= scalers_5;
- else state_b <= scalers_4;
- end if;
- when scalers_5 =>
- DEBUG_REG_01(9 downto 5) <= "01000";
- xfer_buffer <= scaler_pti3_s(31 downto 16);
- if state_a = xfer_13 then
- state_b <= scalers_6;
- else state_b <= scalers_5;
- end if;
- when scalers_6 =>
- DEBUG_REG_01(9 downto 5) <= "01001";
- xfer_buffer <= scaler_pti4_s(15 downto 0);
- if state_a = xfer_13 then
- state_b <= scalers_7;
- else state_b <= scalers_6;
- end if;
- when scalers_7 =>
- DEBUG_REG_01(9 downto 5) <= "01010";
- xfer_buffer <= scaler_pti4_s(31 downto 16);
- if state_a = xfer_13 then
- state_b <= scalers_8;
- else state_b <= scalers_7;
- end if;
- when scalers_8 =>
- DEBUG_REG_01(9 downto 5) <= "01011";
- xfer_buffer <= scaler_pti5_s(15 downto 0);
- if state_a = xfer_13 then
- state_b <= scalers_9;
- else state_b <= scalers_8;
- end if;
- when scalers_9 =>
- DEBUG_REG_01(9 downto 5) <= "01100";
- xfer_buffer <= scaler_pti5_s(31 downto 16);
- if state_a = xfer_13 then
- state_b <= scalers_10;
- else state_b <= scalers_9;
- end if;
- when scalers_10 =>
- DEBUG_REG_01(9 downto 5) <= "01110";
- xfer_buffer <= scaler_ts_s(15 downto 0);
- if state_a = xfer_13 then
- state_b <= scalers_11;
- else state_b <= scalers_10;
- end if;
- when scalers_11 =>
- DEBUG_REG_01(9 downto 5) <= "01111";
- xfer_buffer <= scaler_ts_s(31 downto 16);
- if state_a = xfer_13 then
- state_b <= scalers_12;
- else state_b <= scalers_11;
- end if;
- when scalers_12 =>
- DEBUG_REG_01(9 downto 5) <= "10000";
- xfer_buffer <= scaler_vs_s(15 downto 0);
- if state_a = xfer_13 then
- state_b <= scalers_13;
- else state_b <= scalers_12;
- end if;
- when scalers_13 =>
- DEBUG_REG_01(9 downto 5) <= "10001";
- xfer_buffer <= scaler_vs_s(31 downto 16);
- if state_a = xfer_13 then
- state_b <= scalers_14;
- else state_b <= scalers_13;
- end if;
- when scalers_14 =>
- DEBUG_REG_01(9 downto 5) <= "10010";
- xfer_buffer <= scaler_dead_s(15 downto 0);
- if state_a = xfer_13 then
- state_b <= scalers_15;
- else state_b <= scalers_14;
- end if;
- when scalers_15 =>
- DEBUG_REG_01(9 downto 5) <= "10011";
- xfer_buffer <= scaler_dead_s(31 downto 16);
- if state_a = xfer_13 then
- state_b <= checksum_0;
- else state_b <= scalers_15;
- end if;
- when checksum_0 =>
- DEBUG_REG_01(9 downto 5) <= "10101";
- xfer_buffer <= checksum(15 downto 0);
- if state_a = xfer_13 then
- state_b <= checksum_1;
- else state_b <= checksum_0;
- end if;
- when checksum_1 =>
- DEBUG_REG_01(9 downto 5) <= "10110";
- xfer_buffer <= checksum(31 downto 16);
- if state_a = xfer_13 then
- state_b <= finished;
- else state_b <= checksum_1;
- end if;
- when finished =>
- DEBUG_REG_01(9 downto 5) <= "10111";
- xfer_buffer <= x"0000";
- if state_a = wait_for_busy then
- state_b <= tag;
- else state_b <= finished;
- end if;
- when others =>
- DEBUG_REG_01(9 downto 5) <= "00000";
- state_b <= tag;
- end case;
- end if;
- end if;
- end process;
----------------------------------------------------------------------- DTU comm
- PREPARE_CODE_FOR_DTU: process (clk_100MHz)
- begin -- process PREPARE_CODE_FOR_DTU
- if rising_edge(clk_100MHz) then
- if com_run_s = '0' then
- prepared_code <= x"d";
- elsif com_run_s = '1' and cal_inhibit = '0' then
- prepared_code <= dtu_code;
- elsif com_run_s = '1' and cal_inhibit = '1' then
- prepared_code <= x"9";
- else
- prepared_code <= dtu_code;
- end if;
- end if;
- end process PREPARE_CODE_FOR_DTU;
- DTU_CODE_CHANGE : process (clk_100MHz)
- begin -- process DTU_CODE_CHANGE
- if rising_edge (clk_100MHz) then
- if DTU_CODE_SELECT(4) = '0' then
- dtu_code <= x"1";
- else
- dtu_code <= DTU_CODE_SELECT(3 downto 0);
- end if;
- end if;
- end process DTU_CODE_CHANGE;
- fsm3 : process(clk_100MHz) --TX lenght: 470 ns + wait time (currently 2.5 µs total)
- begin
- if rising_edge(clk_100MHz) then
- if com_run = '0' then
- state_c <= idle;
- com_run_s <= '0';
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
- dtu_bus_td <= x"d";
- count <= 0;
- trb_go_norm <= '0';
- trb_go_calib <= '0';
- gts_dtu_r <= '0';
- dtu_start <= '0';
- else
- -- implemented default value
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
--- dtu_bus_td <= x"d";
- dtu_bus_td <= prepared_code;
- case state_c is
- when idle =>
- DEBUG_REG_01(14 downto 10)<= "00001";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
--- dtu_bus_td <= x"d";
- count <= 0;
- trb_go_norm <= '0';
- trb_go_calib <= '0';
- gts_dtu_r <= '0';
- dtu_start <= '0';
--- com_run_s <= com_run;
--- if com_run = '1' and com_run_s = '0' then
- if com_run = '1' and com_run_s = '0' then
- state_c <= begin_run_0;
--- elsif com_run = '0' and com_run_s = '1' then
--- state_c <= end_run_0;
- elsif gts_dtu_q = '1' and com_run = '1' then
- state_c <= norm_event_0;
- elsif cal_trigger_pulse = '1' and com_run = '1' then
- state_c <= calib_event_0;
- else state_c <= idle;
- end if;
-------------------------------------
- when begin_run_0 =>
- DEBUG_REG_01(14 downto 10)<= "00010";
- dtu_bus_t <= '1';
- dtu_bus_ts <= '0';
- dtu_bus_td <= x"d";
- -- trb_go_norm <= '1';
- tag_counter_dtu <= x"0000";
- com_run_s <= '1';
- dtu_start <= '1';
- count <= count + 1;
- if count = 4+5 then
- state_c <= begin_run_1;
- else state_c <= begin_run_0;
- end if;
- when begin_run_1 =>
- DEBUG_REG_01(14 downto 10)<= "00011";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
- dtu_bus_td <= x"d";
- count <= count + 1;
- if count = 9+10 then
- state_c <= tag_low_0;
- else state_c <= begin_run_1;
- end if;
--------------------------------------
- when end_run_0 =>
- DEBUG_REG_01(14 downto 10)<= "00100";
- trb_run_s <= '0';
- dtu_bus_t <= '1';
- dtu_bus_ts <= '0';
- dtu_bus_td <= x"e";
- count <= count + 1;
- if count = 4+5 then
- state_c <= end_run_1;
- else state_c <= end_run_0;
- end if;
- when end_run_1 =>
- DEBUG_REG_01(14 downto 10)<= "00101";
- trb_run <= '0';
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
- count <= count + 1;
- if count = 9+10 then
- state_c <= tag_low_0;
- else state_c <= end_run_1;
- end if;
---------------------------------------
- when norm_event_0 =>
- DEBUG_REG_01(14 downto 10)<= "00110";
- trb_go_norm <= '1';
- dtu_bus_t <= '1';
- dtu_bus_ts <= '0';
- dtu_bus_td <= dtu_code;-- "1";
- count <= count + 1;
- if count = 4+5 then
- state_c <= norm_event_1;
- else state_c <= norm_event_0;
- end if;
- when norm_event_1 =>
- DEBUG_REG_01(14 downto 10)<= "00111";
- trb_go_norm <= '0';
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
- dtu_bus_td <= dtu_code;
- count <= count + 1;
- if count = 9+10 then
- state_c <= tag_low_0;
- else state_c <= norm_event_1;
- end if;
----------------------------------------
- when calib_event_0 =>
- DEBUG_REG_01(14 downto 10)<= "01000";
- trb_go_calib <= '1';
- dtu_bus_t <= '1';
- dtu_bus_ts <= '0';
- dtu_bus_td <= x"9";
- count <= count + 1;
- if count = 4+5 then
- state_c <= calib_event_1;
- else state_c <= calib_event_0;
- end if;
- when calib_event_1 =>
- DEBUG_REG_01(14 downto 10)<= "01001";
- trb_go_calib <= '0';
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
- dtu_bus_td <= x"9";
- count <= count + 1;
- if count = 9+10 then
- state_c <= tag_low_0;
- else state_c <= calib_event_1;
- end if;
----------------------------------------------------------
- when tag_low_0 =>
- DEBUG_REG_01(14 downto 10)<= "01010";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '1';
- dtu_bus_td <= tag_counter_dtu(3 downto 0);
- count <= count + 1;
- if count = 14+15 then
- state_c <= tag_low_1;
- else state_c <= tag_low_0;
- end if;
- when tag_low_1 =>
- DEBUG_REG_01(14 downto 10)<= "01011";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
- dtu_bus_td <= tag_counter_dtu(3 downto 0);
- count <= count + 1;
- if count = 19+20 then
- state_c <= tag_high_0;
- else state_c <= tag_low_1;
- end if;
- when tag_high_0 =>
- DEBUG_REG_01(14 downto 10)<= "01100";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '1';
- dtu_bus_td <= tag_counter_dtu(7 downto 4);
- count <= count + 1;
- if count = 24+25 then
- state_c <= tag_high_1;
- else state_c <= tag_high_0;
- end if;
- when tag_high_1 =>
- DEBUG_REG_01(14 downto 10)<= "01101";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
- dtu_bus_td <= tag_counter_dtu(7 downto 4);
- count <= count + 1;
- if count = 29+30 then
- state_c <= tag_prio_0;
- else state_c <= tag_high_1;
- end if;
- when tag_prio_0 =>
- DEBUG_REG_01(14 downto 10)<= "01110";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '1';
- dtu_bus_td <= tag_counter_dtu(7 downto 4);
- count <= count + 1;
- if count = 34+35 then
- state_c <= tag_prio_1;
- else state_c <= tag_prio_0;
- end if;
- when tag_prio_1 =>
- DEBUG_REG_01(14 downto 10)<= "01111";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
- count <= count + 1;
- dtu_bus_td <= tag_counter_dtu(7 downto 4);
- if count = 39+40 then
- state_c <= wait_last;
- else state_c <= tag_prio_1;
- end if;
- when wait_last =>
- DEBUG_REG_01(14 downto 10)<= "10000";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
--- dtu_bus_td <= "0000";
- count <= count + 1;
- if count = 244 then --change this to increase wait time (44 default)
- state_c <= wait_for_trb;
- else state_c <= wait_last;
- end if;
- when wait_for_trb =>
- DEBUG_REG_01(14 downto 10)<= "10001";
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
--- dtu_bus_td <= "0000";
- if trb_finished = '1' or dtu_start = '1' then
- state_c <= count_incr;
- else state_c <= wait_for_trb;
- end if;
- when count_incr =>
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
--- dtu_bus_td <= "0000";
- DEBUG_REG_01(14 downto 10)<= "10010";
- gts_dtu_r <= '1';
- tag_counter_dtu <= tag_counter_dtu + 1;
- state_c <= idle;
- when others =>
- dtu_bus_t <= '0';
- dtu_bus_ts <= '0';
--- dtu_bus_td <= "0000";
- DEBUG_REG_01(14 downto 10)<= "00000";
- state_c <= idle;
- end case;
- end if;
- end if;
- end process;
-end Behavioral;
+++ /dev/null
---------------------------------------------------------------------------------
--- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
---------------------------------------------------------------------------------
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version : 9.1.03i
--- \ \ Application : xaw2vhdl
--- / / Filename : clocking.vhd
--- /___/ /\ Timestamp : 02/25/2008 15:07:58
--- \ \ / \
--- \___\/\___\
---
---Command: xaw2vhdl-intstyle /home/davide/Fpga_projects/vulom3/clocking.xaw -st clocking.vhd
---Design Name: clocking
---Device: xc4vlx25-10sf363
---
--- Module clocking
--- Generated by Xilinx Architecture Wizard
--- Written for synthesis tool: XST
-
-library ieee;
-use ieee.std_logic_1164.ALL;
-use ieee.numeric_std.ALL;
-library UNISIM;
-use UNISIM.Vcomponents.ALL;
-
-entity clocking is
- port ( CLKIN_IN : in std_logic;
- CLKDV_OUT : out std_logic;
- CLKFX_OUT : out std_logic;
- CLKIN_IBUFG_OUT : out std_logic;
- CLK0_OUT : out std_logic;
- LOCKED_OUT : out std_logic);
-end clocking;
-
-architecture BEHAVIORAL of clocking is
- signal CLKDV_BUF : std_logic;
- signal CLKFB_IN : std_logic;
- signal CLKFX_BUF : std_logic;
- signal CLKIN_IBUFG : std_logic;
- signal CLK0_BUF : std_logic;
- signal GND_BIT : std_logic;
- signal GND_BUS_7 : std_logic_vector (6 downto 0);
- signal GND_BUS_16 : std_logic_vector (15 downto 0);
- component BUFG
- port ( I : in std_logic;
- O : out std_logic);
- end component;
-
- component IBUFG
- port ( I : in std_logic;
- O : out std_logic);
- end component;
-
- -- Period Jitter (unit interval) for block DCM_ADV_INST = 0.044 UI
- -- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.146 ns
- component DCM_ADV
- generic( CLK_FEEDBACK : string := "1X";
- CLKDV_DIVIDE : real := 2.0;
- CLKFX_DIVIDE : integer := 1;
- CLKFX_MULTIPLY : integer := 4;
- CLKIN_DIVIDE_BY_2 : boolean := FALSE;
- CLKIN_PERIOD : real := 10.0;
- CLKOUT_PHASE_SHIFT : string := "NONE";
- DCM_AUTOCALIBRATION : boolean := TRUE;
- DCM_PERFORMANCE_MODE : string := "MAX_SPEED";
- DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
- DFS_FREQUENCY_MODE : string := "LOW";
- DLL_FREQUENCY_MODE : string := "LOW";
- DUTY_CYCLE_CORRECTION : boolean := TRUE;
- FACTORY_JF : bit_vector := x"F0F0";
- PHASE_SHIFT : integer := 0;
- STARTUP_WAIT : boolean := FALSE;
- SIM_DEVICE : string := "VIRTEX4");
- port ( CLKIN : in std_logic;
- CLKFB : in std_logic;
- DADDR : in std_logic_vector (6 downto 0);
- DI : in std_logic_vector (15 downto 0);
- DWE : in std_logic;
- DEN : in std_logic;
- DCLK : in std_logic;
- RST : in std_logic;
- PSEN : in std_logic;
- PSINCDEC : in std_logic;
- PSCLK : in std_logic;
- CLK0 : out std_logic;
- CLK90 : out std_logic;
- CLK180 : out std_logic;
- CLK270 : out std_logic;
- CLKDV : out std_logic;
- CLK2X : out std_logic;
- CLK2X180 : out std_logic;
- CLKFX : out std_logic;
- CLKFX180 : out std_logic;
- DRDY : out std_logic;
- DO : out std_logic_vector (15 downto 0);
- LOCKED : out std_logic;
- PSDONE : out std_logic);
- end component;
-
-begin
- GND_BIT <= '0';
- GND_BUS_7(6 downto 0) <= "0000000";
- GND_BUS_16(15 downto 0) <= "0000000000000000";
- CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
- CLK0_OUT <= CLKFB_IN;
- CLKDV_BUFG_INST : BUFG
- port map (I=>CLKDV_BUF,
- O=>CLKDV_OUT);
-
- CLKFX_BUFG_INST : BUFG
- port map (I=>CLKFX_BUF,
- O=>CLKFX_OUT);
-
- CLKIN_IBUFG_INST : IBUFG
- port map (I=>CLKIN_IN,
- O=>CLKIN_IBUFG);
-
- CLK0_BUFG_INST : BUFG
- port map (I=>CLK0_BUF,
- O=>CLKFB_IN);
-
- DCM_ADV_INST : DCM_ADV
- generic map( CLK_FEEDBACK => "1X",
- CLKDV_DIVIDE => 2.0,
- CLKFX_DIVIDE => 1,
- CLKFX_MULTIPLY => 3,
- CLKIN_DIVIDE_BY_2 => FALSE,
- CLKIN_PERIOD => 10.000,
- CLKOUT_PHASE_SHIFT => "NONE",
- DCM_AUTOCALIBRATION => TRUE,
- DCM_PERFORMANCE_MODE => "MAX_SPEED",
- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
- DFS_FREQUENCY_MODE => "HIGH",
- DLL_FREQUENCY_MODE => "LOW",
- DUTY_CYCLE_CORRECTION => TRUE,
- FACTORY_JF => x"F0F0",
- PHASE_SHIFT => 0,
- STARTUP_WAIT => FALSE)
- port map (CLKFB=>CLKFB_IN,
- CLKIN=>CLKIN_IBUFG,
- DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
- DCLK=>GND_BIT,
- DEN=>GND_BIT,
- DI(15 downto 0)=>GND_BUS_16(15 downto 0),
- DWE=>GND_BIT,
- PSCLK=>GND_BIT,
- PSEN=>GND_BIT,
- PSINCDEC=>GND_BIT,
- RST=>GND_BIT,
- CLKDV=>CLKDV_BUF,
- CLKFX=>CLKFX_BUF,
- CLKFX180=>open,
- CLK0=>CLK0_BUF,
- CLK2X=>open,
- CLK2X180=>open,
- CLK90=>open,
- CLK180=>open,
- CLK270=>open,
- DO=>open,
- DRDY=>open,
- LOCKED=>LOCKED_OUT,
- PSDONE=>open);
-
-end BEHAVIORAL;
-
-
+++ /dev/null
-#!/usr/bin/perl
-###########################################
-# Script file to run the flow
-#
-###########################################
-#
-# Command line for synplify_pro
-#
-
-
-use FileHandle;
-
-
-$ENV{LM_LICENSE_FILE}="1709\@hadeb05";
-
-
-
-$PLD_DEVICE="xc4vlx25-10-sf363";
-$TOPNAME="vlogic_1";
-
-
-
-#set -e
-#set -o errexit
-
-system("env| grep LM_");
-
-#$c="/opt/Synplicity/fpga_861/bin/synplify_pro -batch $TOPNAME"."_syn.prj";
-#$c="/opt/Synplicity/fpga_8804/bin/synplify_pro -batch $TOPNAME"."_syn.prj";
-#$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
-$c="/opt/Synplicity/fpga_901/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
-#$c=("( netcat -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)& /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj");
-$r=execute($c, "do_not_exit" );
-
-
-chdir "workdir";
-my $fh = new FileHandle("<trig_box1.srr");
-my @a = <$fh>;
-$fh -> close;
-
-#if ($r) {
-#$c="cat $TOPNAME.srr";
-#system($c);
-#exit 129;
-#}
-
-foreach (@a)
-{
- if(/\@E:/)
- {
- $c="cat $TOPNAME.srr";
- system($c);
- print "bdabdhsadbhjasdhasldhbas";
- exit 129;
- }
-}
-#
-# Command line to synthesize
-#
-
-#chdir "..";
-#$c="xst -intstyle xflow -ifn $TOPNAME.xst -ofn $TOPNAME.syr";
-#execute($c);
-#chdir "workdir";
-
-#
-# Command line for ngdbuild
-#
-#$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf ../$TOPNAME.ngc $TOPNAME.ngd";
-$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf -sd ../ $TOPNAME.edf $TOPNAME.ngd";
-execute($c);
-#
-# Command line for fpgafit
-#
-$c="map -xe n -logic_opt on -retiming on -timing -power off -equivalent_register_removal on -detail -u -p $PLD_DEVICE -cm speed -pr b -k 4 -c 100 -tx off -intstyle xflow -o $TOPNAME"."_map.ncd $TOPNAME.ngd $TOPNAME.pcf";
-execute($c);
-
-#
-# Command line for Place & Route
-#
-
-$c="par -w -intstyle xflow -pl high -rl high -xe n -t 1 $TOPNAME"."_map.ncd $TOPNAME.ncd $TOPNAME.pcf";
-execute($c);
-
-#
-# Command line for genarate programming file (.bit)
-#
-
-
-foreach (<$TOPNAME"."_pad.txt>) {
- @a=split (/\s*\|\s*/,$_);
- if( ($a[2] ne "" &&
- $a[2] ne "Signal Name") &&
- $a[13] ne "LOCATED"
- )
- {
- print "error, pins were assigned automatically:\n$_\n";
- exit;
- }
-}
-
-print "_pad.txt tested for automatically assigned pins\n";
-
-#$c="bitgen -w -intstyle ise -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No $TOPNAME";
-$c="bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DisableBandgap:No -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No $TOPNAME.ncd";
-
-execute($c);
-#
-# Command line for generate .stapl file
-#
-
-$c="XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch ../impact_batch_vulom3.txt";
-
-execute($c);
-
-
-#ssh depc152 'cd ~/files/vhdl/xilinx; . ~/bin/xilinx_setup; XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch conf_xilinx_impact.txt '
-
-#
-#to download file on ETRAX chip
-#
-
-#$c="lftp root:pass@hades18;put RPCBoardContrller;exit";
-#execute($c)
-
-chdir "..";
-
-sub execute {
- my ($c, $op) = @_;
- #print "option: $op \n";
-
- print "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
- }
-
- return $r;
-
-}
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 7/3/07
--- Design Name: vulom3
--- Module Name: delay - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: 16 clock cycle programmable delayer
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity delay is port (
- clk : in std_logic;
- to_be_delayed : in std_logic;
- delay_value : in std_logic_vector(3 downto 0);
- delayed_pulse : out std_logic);
-end delay;
-
-architecture Behavioral of delay is
-signal shift : std_logic_vector (15 downto 0) := x"0000";
-
-begin
-
- process (clk)
- begin
- if rising_edge(clk) then
- shift <= shift (14 downto 0) & to_be_delayed;
-
- case delay_value is
- when "0000" => delayed_pulse <= shift(0);
- when "0001" => delayed_pulse <= shift(1);
- when "0010" => delayed_pulse <= shift(2);
- when "0011" => delayed_pulse <= shift(3);
- when "0100" => delayed_pulse <= shift(4);
- when "0101" => delayed_pulse <= shift(5);
- when "0110" => delayed_pulse <= shift(6);
- when "0111" => delayed_pulse <= shift(7);
- when "1000" => delayed_pulse <= shift(8);
- when "1001" => delayed_pulse <= shift(9);
- when "1010" => delayed_pulse <= shift(10);
- when "1011" => delayed_pulse <= shift(11);
- when "1100" => delayed_pulse <= shift(12);
- when "1101" => delayed_pulse <= shift(13);
- when "1110" => delayed_pulse <= shift(14);
- when "1111" => delayed_pulse <= shift(15);
- when others => delayed_pulse <= 'X';
- end case;
- end if;
- end process;
-
-end Behavioral;
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 7/3/07
--- Design Name: vulom3
--- Module Name: downscale - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: 2^16 programmable divider with output shaper
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library UNISIM;
-use UNISIM.vcomponents.all;
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity downscale is port (
- disable : in std_logic;
- to_be_downscaled : in std_logic;
- downscale_value : in std_logic_vector(3 downto 0);
- clk : in std_logic;
- downscaled : out std_logic);
-end downscale;
-
-architecture Behavioral of downscale is
-signal reset, internal, to_be_downscaled_d : std_logic := '0';
-signal accu : std_logic_vector (15 downto 0) := x"0000";
-
-begin
-
- process(clk)
- begin
- if rising_edge(clk) then
- if disable = '0' then
- to_be_downscaled_d <= to_be_downscaled;
- else to_be_downscaled_d <= '0';
- end if;
-
- if to_be_downscaled_d = '1' then
- accu <= accu + 1;
- end if;
-
- case downscale_value is
- when "0000" => reset <= to_be_downscaled_d; --bypass
- when "0001" => reset <= accu(0);
- when "0010" => reset <= accu(1);
- when "0011" => reset <= accu(2);
- when "0100" => reset <= accu(3);
- when "0101" => reset <= accu(4);
- when "0110" => reset <= accu(5);
- when "0111" => reset <= accu(6);
- when "1000" => reset <= accu(7);
- when "1001" => reset <= accu(8);
- when "1010" => reset <= accu(9);
- when "1011" => reset <= accu(10);
- when "1100" => reset <= accu(11);
- when "1101" => reset <= accu(12);
- when "1110" => reset <= accu(13);
- when "1111" => reset <= accu(14);
- when others => reset <= 'X';
- end case;
-
- internal <= reset;
- downscaled <= (not internal) and reset;
- end if;
- end process;
-
-end Behavioral;
+++ /dev/null
-----------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 17:03:24 03/27/2007
--- Design Name: vulom3
--- Module Name: eco_delay - Behavioral
--- Project Name: triggerbox
--- Target Devices: XC4VLX25-10SF363
--- Tool versions:
--- Description: Fixed delayer with fixed output pulse shaper
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity eco_delay is port (
- clk : in std_logic;
- signal_in : in std_logic;
- signal_out : out std_logic);
-end eco_delay;
-
-architecture Behavioral of eco_delay is
-signal chain : std_logic_vector(31 downto 0);
-signal internal : std_logic;
-signal signal_out_s : std_logic:='0';
-
-begin
-
- signal_out <= signal_out_s;
-
- process (clk)
- begin
- if rising_edge(clk) then
- internal <= signal_in;
- chain <= (chain (30 downto 0) & (not internal and signal_in));
-
- if (chain(15) = '1') then
- signal_out_s <= '1';
- elsif (chain(15) = '0' and chain(27) ='1') then
- signal_out_s <= '0';
- end if;
- end if;
- end process;
-
-end Behavioral;
-
+++ /dev/null
-setMode -bs
-setMode -bs
-setCable -port stapl -file "../trigger_box1.stapl"
-addDevice -p 1 -file "vlogic_1.bit"
-Program -p 1 -defaultVersion 0
-quit
\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 7/3/07
--- Design Name: vulom3
--- Module Name: new_downscale_ck - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: Provides clock downscale, plus calibration and inhibit signals
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity new_downscale_ck is port (
- downscale_value : in std_logic_vector(3 downto 0);
- clk : in std_logic;
- downscaled : out std_logic;
- output_disable : in std_logic;
- global_inhibit : in std_logic;
- scaler_reset : out std_logic;
- cal_inhibit : out std_logic;
- cal_trigger : out std_logic);
-end new_downscale_ck;
-
-architecture Behavioral of new_downscale_ck is
-signal accu_1 : std_logic_vector(21 downto 0);
-signal accu_3 : std_logic_vector(15 downto 0);
-signal accu_4 : std_logic_vector(15 downto 0);
-signal count, count_d, clk_10kHz : std_logic;
-signal accu_2 : std_logic_vector(15 downto 0);
-signal delay_1, delay_2 : std_logic;
-
-
-begin
-
- process(clk) --pulser
- begin
- if rising_edge(clk) then
- accu_1 <= accu_1 + 1;
- case downscale_value is
- when "0000" => count <= accu_1(6);
- when "0001" => count <= accu_1(7);
- when "0010" => count <= accu_1(8);
- when "0011" => count <= accu_1(9);
- when "0100" => count <= accu_1(10);
- when "0101" => count <= accu_1(11);
- when "0110" => count <= accu_1(12);
- when "0111" => count <= accu_1(13);
- when "1000" => count <= accu_1(14);
- when "1001" => count <= accu_1(15);
- when "1010" => count <= accu_1(16);
- when "1011" => count <= accu_1(17);
- when "1100" => count <= accu_1(18);
- when "1101" => count <= accu_1(19);
- when "1110" => count <= accu_1(20);
- when "1111" => count <= accu_1(21);
- when others => count <= 'X';
- end case;
- count_d <= count;
- downscaled <= (not count_d) and count;
- end if;
- end process;
- process(clk) --10 kHz clock generator
- begin
- if rising_edge(clk) then
- if accu_2 = x"3a97" then
- accu_2 <= x"0000";
- clk_10kHz <= not clk_10kHz;
- else
- accu_2 <= accu_2 + 1;
- end if;
- end if;
- end process;
- process(clk_10kHz) --calibration pulse
- begin
- if rising_edge(clk_10kHz) then
- if accu_3 = x"0000" then
- scaler_reset <= '1';
- accu_3 <= accu_3 + 1;
- elsif accu_3 = x"0001" then
- scaler_reset <= '0';
- accu_3 <= accu_3 + 1;
- elsif accu_3 = x"0002" then
- scaler_reset <= '0';
- accu_3 <= accu_3 + 1;
- elsif accu_3 = x"270f" then --10e3
- scaler_reset <= '0';
- accu_3 <= x"0000";
- else accu_3 <= accu_3 + 1;
- end if;
- end if;
- end process;
- process(clk_10kHz) --calibration pulse
- begin
- if rising_edge(clk_10kHz) then
- if accu_4 = x"0000" and global_inhibit = '0' then
- cal_inhibit <= not output_disable;
- cal_trigger <= '0';
- accu_4 <= accu_4 + 1;
- elsif accu_4 = x"0000" and global_inhibit = '1' then
- cal_inhibit <= not output_disable;
- cal_trigger <= '0';
- accu_4 <= accu_4;
- elsif accu_4 = x"0001" then
- cal_inhibit <= not output_disable;
- cal_trigger <= not output_disable;
- accu_4 <= accu_4 + 1;
- elsif accu_4 = x"0002" then
- cal_inhibit <= '0';
- cal_trigger <= '0';
- accu_4 <= accu_4 + 1;
- elsif accu_4 = x"270f" then --10e3
- cal_inhibit <= '0';
- cal_trigger <= '0';
- accu_4 <= x"0000";
- else accu_4 <= accu_4 + 1;
- end if;
- end if;
- end process;
-
-end Behavioral;
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 7/3/07
--- Design Name: vulom3
--- Module Name: one_clock_long - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: One clock cycle pulse shaper
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity one_clock_long is port (
- clk : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
-end one_clock_long;
-
-architecture Behavioral of one_clock_long is
-signal internal, signal_in_s : std_logic;
-
-begin
-
- process (clk)
- begin
- if rising_edge(clk) then
- signal_in_s <= signal_in;
-
- if en_clk = '0' then
- pulse <= '0';
- else
- internal <= signal_in_s;
- pulse <= (not internal) and signal_in_s;
- end if;
- end if;
- end process;
-
-end Behavioral;
-
+++ /dev/null
-
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 09:54:36 03/13/2007
--- Design Name: one_clock_long
--- Module Name: /home/davide/fuffa/one_clock_long_test.vhd
--- Project Name: fuffa
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: one_clock_long
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.all;
-USE ieee.numeric_std.ALL;
-
-ENTITY one_clock_long_test_vhd IS
-END one_clock_long_test_vhd;
-
-ARCHITECTURE behavior OF one_clock_long_test_vhd IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT one_clock_long
- PORT(
- clk : IN std_logic;
- en_clk : IN std_logic;
- signal_in : IN std_logic;
- pulse : OUT std_logic
- );
- END COMPONENT;
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL en_clk : std_logic := '0';
- SIGNAL signal_in : std_logic := '0';
-
- --Outputs
- SIGNAL pulse : std_logic;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: one_clock_long PORT MAP(
- clk => clk,
- en_clk => en_clk,
- signal_in => signal_in,
- pulse => pulse
- );
-
- tb : PROCESS
- BEGIN
-
- clk <= '1';
- wait for 1.42 ns;
- clk <= '0';
- wait for 1.42 ns;
-
- END PROCESS;
-
- stim : process
- begin
- en_clk <= '1';
- signal_in <= '0';
- wait for 12.78 ns;
- signal_in <= '1';
- wait for 14.2 ns;
- signal_in <= '0';
- wait for 14.2 ns;
- signal_in <= '1';
- wait for 1.42 ns;
- signal_in <= '0';
- wait for 14.2 ns;
- signal_in <= '1';
- wait for 14.2 ns;
- signal_in <= '0';
- wait;
- end process;
-
-END;
\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 8/3/07
--- Design Name: vulom3
--- Module Name: scaler - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: 20 bit counter with reset
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity scaler is
- Port ( clk : in std_logic;
- input_pulse : in std_logic;
- scaler_reset : in std_logic;
- scaler_value : out std_logic_vector(19 downto 0));
-end scaler;
-
-architecture Behavioral of scaler is
-signal scaled : std_logic_vector(19 downto 0) := x"00000";
-
-begin
-process(clk)
-begin
- if rising_edge(clk) then
- if scaler_reset = '1' then
- scaled <= x"00000";
- elsif (input_pulse = '1' and scaler_reset = '0') then
- scaled <= scaled + 1;
- end if;
- end if;
-
-
--- if rising_edge(clk) then
--- if (input_pulse = '1' and scaler_reset = '0') then
--- scaled <= scaled + 1;
--- elsif scaler_reset = '1' then
--- scaled <= x"00000";
--- end if;
--- end if;
-
-scaler_value <= scaled;
-
-end process;
-
-
-end Behavioral;
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 8/3/07
--- Design Name: vulom3
--- Module Name: scaler_s - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: 32 bit counter with reset
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity scaler_s is port (
- clk_300MHz : in std_logic;
- clk_100MHz : in std_logic;
- input_pulse : in std_logic;
- scaler_reset : in std_logic;
- scaler_value : out std_logic_vector(31 downto 0));
-end scaler_s;
-
-architecture Behavioral of scaler_s is
-signal scaled : std_logic_vector(31 downto 0) := x"00000000";
-signal r, q : std_logic;
-signal input_pulse_d, shaped_input, scaler_reset_d, shaped_reset : std_logic;
-
-begin
-
- process(clk_300MHz)
- begin
- if rising_edge(clk_300MHz) then
- input_pulse_d <= input_pulse;
- shaped_input <= input_pulse and not input_pulse_d; -- 1 ck shaper
-
- if r = '1' then -- flip-flop
- q <= '0';
- elsif shaped_input = '1' then
- q <= '1';
- end if;
- end if;
- end process;
-
- process(clk_100MHz)
- begin
- if rising_edge(clk_100MHz) then
- scaler_reset_d <= scaler_reset; -- 1 ck shaper
- shaped_reset <= scaler_reset and not scaler_reset_d;
-
- if shaped_reset = '1' then
- scaled <= x"00000000";
- scaler_value <= scaled;
- elsif r = '1' then
- r <= '0';
- elsif q = '1' then
- scaled <= scaled + 1;
- r <= '1';
- end if;
- end if;
- end process;
-
-end Behavioral;
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 8/3/07
--- Design Name: vulom3
--- Module Name: set_width - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: 16 clock cycle programmable pulse shaper
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity set_width is port (
- clk : in std_logic;
- to_be_set : in std_logic;
- width_value : in std_logic_vector(3 downto 0);
- width_adjusted_pulse : out std_logic);
-end set_width;
-
-architecture Behavioral of set_width is
-signal reset, to_be_set_delayed, q : std_logic;
-signal shift :std_logic_vector (15 downto 0);
-
-begin
-
- process (clk)
- begin
-
- if rising_edge(clk) then
- shift <= shift (14 downto 0) & to_be_set;
- to_be_set_delayed <= to_be_set;
-
- case width_value is
- when "0000" => reset <= shift(0);
- when "0001" => reset <= shift(1);
- when "0010" => reset <= shift(2);
- when "0011" => reset <= shift(3);
- when "0100" => reset <= shift(4);
- when "0101" => reset <= shift(5);
- when "0110" => reset <= shift(6);
- when "0111" => reset <= shift(7);
- when "1000" => reset <= shift(8);
- when "1001" => reset <= shift(9);
- when "1010" => reset <= shift(10);
- when "1011" => reset <= shift(11);
- when "1100" => reset <= shift(12);
- when "1101" => reset <= shift(13);
- when "1110" => reset <= shift(14);
- when "1111" => reset <= shift(15);
- when others => reset <= 'X';
- end case;
-
- if (to_be_set_delayed = '0' and reset ='1') then
- width_adjusted_pulse <= '0';
- elsif (to_be_set_delayed = '1' and reset ='0') then
- width_adjusted_pulse <= '1';
- end if;
- end if;
- end process;
-
-end Behavioral;
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 8/3/07
--- Design Name: vulom3
--- Module Name: set_width_special - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: 16 clock cycle programmable pulse shaper specific for output
--- (it can handle pulses wider than 1 ck cycle)
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity set_width_special is port (
- clk : in std_logic;
- to_be_set : in std_logic;
- width_value : in std_logic_vector(3 downto 0);
- width_adjusted_pulse : out std_logic);
-end set_width_special;
-
-architecture Behavioral of set_width_special is
-signal reset_timing_signal, clocked_timing_signal : std_logic;
-signal timing_signal_counter : std_logic_vector(5 downto 0);
-signal start_pulse, end_pulse : std_logic;
-signal during_pulse, to_be_set_synch, to_be_set_synch_delayed : std_logic;
-
-begin
-
- SYNCH_TO_BE_SET: process (CLK)
- begin
- if rising_edge(CLK) then
- to_be_set_synch <= to_be_set;
- to_be_set_synch_delayed <= to_be_set_synch;
- end if;
- end process SYNCH_TO_BE_SET;
- MAKE_START: process (CLK)
- begin
- if rising_edge(CLK) then
- if to_be_set_synch_delayed = '0' and to_be_set_synch = '1' then
- start_pulse <= '1';
- end_pulse <= '0';
- elsif to_be_set_synch_delayed = '1' and to_be_set_synch = '0' then
- start_pulse <= '0';
- end_pulse <= '1';
- else
- start_pulse <= '0';
- end_pulse <= '0';
- end if;
- end if;
- end process MAKE_START;
- DURING_PULSE_PROC: process (CLK)
- begin
- if rising_edge(CLK) then
- if start_pulse = '1' then
- during_pulse <= '1';
- elsif timing_signal_counter(5) = '1' then
- during_pulse <= '0';
- end if;
- end if;
- end process DURING_PULSE_PROC;
-
-
- PULSER_LENGHT_COUNTER: process (CLK)
- begin
- if rising_edge(CLK) then
- if during_pulse = '1' then
- timing_signal_counter <= timing_signal_counter + 1;
- elsif start_pulse = '1' then
- timing_signal_counter <= (others => '0');
- else
- timing_signal_counter <= timing_signal_counter;
- end if;
- end if;
- end process PULSER_LENGHT_COUNTER;
- width_adjusted_pulse <= during_pulse;--to_be_set or during_pulse;
-end Behavioral;
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 9/3/07
--- Design Name: vulom3
--- Module Name: trig_box1 - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: Triggerbox
--- NOTE (1): To enable TOF/MDC part comment lines (a) and (b) and uncomment (c)
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library UNISIM;
-use UNISIM.Vcomponents.ALL;
-
-entity trig_box1 is
- port (clk_50MHz : in std_logic;
- clk_300MHz : in std_logic;
- clk_100MHz : in std_logic;
- ECL : in std_logic_vector(16 downto 1);
- ECO : out std_logic_vector(16 downto 1);
- IOO : in std_logic_vector(16 downto 1);
- TIN : out std_logic_vector(16 downto 1);
- LEMIN : in std_logic_vector(2 downto 1);
- LEMOU : out std_logic_vector(2 downto 1);
- INPUT_ENABLE : in std_logic_vector(7 downto 1);
- DOWNSCALE_REGISTER_1 : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_1 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_1 : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_2 : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_2 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_2 : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_3 : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_3 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_3 : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_4 : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_4 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_4 : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_5 : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_5 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_5 : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_TS : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_TS : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_TS : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_VS : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_VS : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_VS : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_CLOCK : in std_logic_vector(3 downto 0);
- BRANCH_EN_with_MDC_TOF_WIDTH : in std_logic_vector(4 downto 0); --(4) enables branch, (3 downto 0) is the width value
- WIDTH_OUTPUT : in std_logic_vector(3 downto 0);
- MUX_SELECTOR_1 : in std_logic_vector(3 downto 0);
- MUX_SELECTOR_2 : in std_logic_vector(3 downto 0);
- OR_ON_OFF : in std_logic_vector(7 downto 0);
- SCALER_PTI1 : out std_logic_vector(31 downto 0);
- SCALER_PTI2 : out std_logic_vector(31 downto 0);
- SCALER_PTI3 : out std_logic_vector(31 downto 0);
- SCALER_PTI4 : out std_logic_vector(31 downto 0);
- SCALER_PTI5 : out std_logic_vector(31 downto 0);
- SCALER_TS : out std_logic_vector(31 downto 0);
- SCALER_VS : out std_logic_vector(31 downto 0);
- SCALER_MDC_TOF_SELECT : in std_logic_vector(7 downto 0); -- x"yz" y= mdc channel select, z= tof channel select
- SCALER_MDC : out std_logic_vector(31 downto 0);
- SCALER_TOF : out std_logic_vector(31 downto 0);
- SCALER_RESET : in std_logic_vector(7 downto 0);
- PTI5_TS_ALTERNATIVE : in std_logic_vector(7 downto 0);
- DELAY_REGISTER_BEAM : in std_logic_vector(7 downto 0);
- WIDTH_INHIBIT_REGISTER_BEAM : in std_logic_vector(7 downto 0);
- WIDTH_EXTERNAL_REGISTER_BEAM : in std_logic_vector(7 downto 0);
- SCALER_DEAD : out std_logic_vector(31 downto 0);
- TS_GATING_DISABLE : in std_logic_vector(7 downto 1);
- SCALER_PTI1_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_PTI2_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_PTI3_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_PTI4_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_PTI5_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_TS_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_MUX1 : out std_logic_vector(31 downto 0);
- SCALER_MUX2 : out std_logic_vector(31 downto 0);
- DTU_CODE_SELECT : in std_logic_vector(4 downto 0);
- CAL_TRIGGER_DISABLE : in std_logic;
- COM_RUN : in std_logic;
- DTU_ERROR : inout std_logic;
- hpv : inout std_logic_vector(15 downto 0);
- hpw : inout std_logic_vector(15 downto 0);
- DEBUG_REG_00 : out std_logic_vector(31 downto 0);
- TRB_BUSY_ENABLE : in std_logic
- );
-end trig_box1;
-
-
-architecture RTL of trig_box1 is
-
-component ONE_CLOCK_LONG port (
- clk : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
-end component;
-
-component DELAY port (
- clk : in std_logic;
- to_be_delayed : in std_logic;
- delay_value : in std_logic_vector(3 downto 0);
- delayed_pulse : out std_logic);
-end component;
-
-component DOWNSCALE port (
- clk : in std_logic;
- disable : in std_logic;
- to_be_downscaled : in std_logic;
- downscale_value : in std_logic_vector(3 downto 0);
- downscaled : out std_logic);
-end component;
-
-component SET_WIDTH port (
- clk : in std_logic;
- to_be_set : in std_logic;
- width_value : in std_logic_vector(3 downto 0);
- width_adjusted_pulse : out std_logic);
-end component;
-
-component SET_WIDTH_special port (
- clk : in std_logic;
- to_be_set : in std_logic;
- width_value : in std_logic_vector(3 downto 0);
- width_adjusted_pulse : out std_logic);
-end component;
-
-component SCALER port (
- clk : in std_logic;
- input_pulse : in std_logic;
- scaler_reset : in std_logic;
- scaler_value : out std_logic_vector(19 downto 0));
-end component;
-
-component SCALER_S port (
- clk_300MHz : in std_logic;
- clk_100MHz : in std_logic;
- input_pulse : in std_logic;
- scaler_reset : in std_logic;
- scaler_value : out std_logic_vector(31 downto 0));
-end component;
-
-component ECO_DELAY port (
- clk : in std_logic;
- signal_in : in std_logic;
- signal_out : out std_logic);
-end component;
-
-COMPONENT new_downscale_ck
-PORT(
- downscale_value : IN std_logic_vector(3 downto 0);
- clk : IN std_logic;
- downscaled : OUT std_logic;
- output_disable : IN std_logic;
- global_inhibit : in std_logic;
- scaler_reset : OUT std_logic;
- cal_inhibit : OUT std_logic;
- cal_trigger : OUT std_logic
- );
-END COMPONENT;
-
-COMPONENT beam_ramp
-PORT(
- clk_300MHz : IN std_logic;
- clk_50MHz : IN std_logic;
- input : IN std_logic;
- delay_value : IN std_logic_vector(7 downto 0);
- width_value_inhibit : IN std_logic_vector(7 downto 0);
- width_value_external : IN std_logic_vector(7 downto 0);
- output_inhibit : OUT std_logic;
- output_external : OUT std_logic
- );
-END COMPONENT;
-
-COMPONENT bus_data_com5
-PORT(
- clk_300MHz : IN std_logic;
- clk_100MHz : IN std_logic;
- gts_pulse : IN std_logic;
- cal_trigger : IN std_logic;
- bus_busy : IN std_logic; --not used
- bus_ack : in std_logic;
- bus_retx : in std_logic;
- latch : IN std_logic_vector(6 downto 0);
- latch_dsc : IN std_logic_vector(6 downto 0);
- scaler_pti1 : IN std_logic_vector(31 downto 0);
- scaler_pti2 : IN std_logic_vector(31 downto 0);
- scaler_pti3 : IN std_logic_vector(31 downto 0);
- scaler_pti4 : IN std_logic_vector(31 downto 0);
- scaler_pti5 : IN std_logic_vector(31 downto 0);
- scaler_ts : IN std_logic_vector(31 downto 0);
- scaler_vs : IN std_logic_vector(31 downto 0);
- scaler_dead : IN std_logic_vector(31 downto 0);
- bus_inhibit : OUT std_logic;
- dtu_inhibit : out std_logic;
- ecl_bus_data : OUT std_logic_vector(1 downto 0);
- ecl_bus_clk : OUT std_logic;
- com_run : IN std_logic;
- dtu_bus_t : out std_logic;
- dtu_bus_ts : out std_logic;
- dtu_bus_td : out std_logic_vector (3 downto 0);
- DTU_CODE_SELECT : in std_logic_vector(4 downto 0);
- DEBUG_REG_01 : out std_logic_vector(15 downto 0);
- cal_inhibit : in std_logic;
- out_inhibit : in std_logic;
- TRB_BUSY_ENABLE : in std_logic
- );
-END COMPONENT;
-
-
-signal PTI1_ONE_CLOCK, PTI1_DELAYED, PTI1_READY, PTI1_DOWNSCALED, PTI1_SELF_COIN : std_logic;
-signal PTI2_ONE_CLOCK, PTI2_DELAYED, PTI2_READY, PTI2_DOWNSCALED, PTI2_SELF_COIN : std_logic;
-signal PTI3_ONE_CLOCK, PTI3_DELAYED, PTI3_READY, PTI3_DOWNSCALED, PTI3_SELF_COIN : std_logic;
-signal PTI4_ONE_CLOCK, PTI4_DELAYED, PTI4_READY, PTI4_DOWNSCALED, PTI4_SELF_COIN : std_logic;
-signal PTI5_ONE_CLOCK, PTI5_DELAYED, PTI5_READY, PTI5_DOWNSCALED, PTI5_SELF_COIN : std_logic;
-signal TS_ONE_CLOCK, TS_DELAYED, TS_READY, dead, TS_SELF_COIN : std_logic;
-signal VS_ONE_CLOCKS, VS_DELAYED, VS_READY, VS_WIDTH_SET, VS_SELF_COIN : std_logic;
-signal CLOCK_DOWNSCALED, CLOCK_READY : std_logic;
-signal cal_inhibit, cal_trigger, out_inhibit, beam_inhibit, bus_inhibit : std_logic;
-signal GLOBAL_TIMING_SIGNAL_OUT, OR_out : std_logic;
-signal PTI1_and_GTS, PTI2_and_GTS, PTI3_and_GTS, PTI4_and_GTS, PTI5_and_GTS : std_logic;
-signal lemin_s, lemin_s1, mux_out : std_logic_vector(1 downto 0);
-signal mdc_tof_or, mdc_tof_or_width_set, tof_or, tof_or_delayed, tof_mult_2, tof_mult_2_one, mdc_tof_trigger, mdc_tof_trigger_width_set : std_logic;
-signal eco_s, eco_out : std_logic_vector(16 downto 1);
-signal tof_one_clock, tof_del, tof_s, tof_s1, mdc_s, mdc_s1 : std_logic_vector(5 downto 0);
-signal tof_mux, mdc_mux, pti5_mux, ts_mux, mdc_one_clock : std_logic;
-signal scaler_pti1_count, scaler_pti2_count, scaler_pti3_count, scaler_pti4_count, scaler_pti5_count,
- scaler_ts_count, scaler_vs_count, scaler_dead_count : std_logic_vector(31 downto 0);
-signal self_coin_delay_1, self_coin_delay_2, self_coin_delay_3, self_coin_delay_4, self_coin_delay_5 : std_logic_vector(3 downto 0);
-signal scaler_reset_internal : std_logic;
-signal dtu_bus_t, dtu_bus_ts, dtu_bus_tb_s, dtu_inhibit : std_logic;
-signal dtu_bus_td : std_logic_vector(3 downto 0);
-signal GTS_to_databus, CAL_to_databus : std_logic;
-
-begin
-
--------------------------------------------------------------ONE CLOCK LONG
-one1: ONE_CLOCK_LONG port map (
- clk => clk_300MHz,
- en_clk => INPUT_ENABLE(1),
- signal_in => IOO(1),
- pulse => PTI1_ONE_CLOCK);
-
-one2: ONE_CLOCK_LONG port map (
- clk => clk_300MHz,
- en_clk => INPUT_ENABLE(2),
- signal_in => IOO(2),
- pulse => PTI2_ONE_CLOCK);
-
-one3: ONE_CLOCK_LONG port map (
- clk => clk_300MHz,
- en_clk => INPUT_ENABLE(3),
- signal_in => IOO(3),
- pulse => PTI3_ONE_CLOCK);
-
-one4: ONE_CLOCK_LONG port map ( --Directly connected to the OR of TOF, so ECL input n°4 is unused
- clk => clk_300MHz,
- en_clk => INPUT_ENABLE(4),
- signal_in => tof_or,
- pulse => PTI4_ONE_CLOCK);
-
-one5: ONE_CLOCK_LONG port map (
- clk => clk_300MHz,
- en_clk => INPUT_ENABLE(5),
- signal_in => IOO(5),
- pulse => PTI5_ONE_CLOCK);
-
-one6: ONE_CLOCK_LONG port map (
- clk => clk_300MHz,
- en_clk => INPUT_ENABLE(6),
- signal_in => IOO(6),
- pulse => TS_ONE_CLOCK);
-
-one7: ONE_CLOCK_LONG port map (
- clk => clk_300MHz,
- en_clk => INPUT_ENABLE(7),
- signal_in => IOO(7),
- pulse => VS_ONE_CLOCKS);
-
-one_mdc: ONE_CLOCK_LONG port map ( --used only for scaler
- clk => clk_300MHz,
- en_clk => '1',
- signal_in => mdc_mux,
- pulse => mdc_one_clock);
-
-tof_generate_oneclock : for i in 9 to 14 generate
- one_tof: ONE_CLOCK_LONG port map (
- clk => clk_300MHz,
- en_clk => '1', --tof always enabled
- signal_in => ECL(i),
- pulse => tof_one_clock(i-9));
-end generate;
----------------------------------------------\r
-multiplicity: ONE_CLOCK_LONG port map (
- clk => clk_300MHz,
- en_clk => '1',
- signal_in => tof_mult_2,
- pulse => tof_mult_2_one);\r
----------------------------------------------
-one_ck: ONE_CLOCK_LONG port map (
- clk => clk_300MHz,
- en_clk => '1',
- signal_in => CLOCK_DOWNSCALED,
- pulse => CLOCK_READY);
-
--------------------------------------------------------------------------DELAY
-del1: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => PTI1_ONE_CLOCK,
- delay_value => DELAY_REGISTER_1(3 downto 0),
- delayed_pulse => PTI1_DELAYED);
-
-del2: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => PTI2_ONE_CLOCK,
- delay_value => DELAY_REGISTER_2(3 downto 0),
- delayed_pulse => PTI2_DELAYED);
-
-del3: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => PTI3_ONE_CLOCK,
- delay_value => DELAY_REGISTER_3(3 downto 0),
- delayed_pulse => PTI3_DELAYED);
-
-del4: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => PTI4_ONE_CLOCK,
- delay_value => DELAY_REGISTER_4(3 downto 0),
- delayed_pulse => PTI4_DELAYED);
-
-del5: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => pti5_mux,
- delay_value => DELAY_REGISTER_5(3 downto 0),
- delayed_pulse => PTI5_DELAYED);
-
-del6: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => ts_mux,
- delay_value => DELAY_REGISTER_TS(3 downto 0),
- delayed_pulse => TS_DELAYED);
-
-del7: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => VS_ONE_CLOCKS,
- delay_value => DELAY_REGISTER_VS(3 downto 0),
- delayed_pulse => VS_DELAYED);
-
-self_coin_delay_1 <= '0' & WIDTH_REGISTER_1(3 downto 1); --automatic delay = width / 2
-self_coin_delay_2 <= '0' & WIDTH_REGISTER_2(3 downto 1);
-self_coin_delay_3 <= '0' & WIDTH_REGISTER_3(3 downto 1);
-self_coin_delay_4 <= '0' & WIDTH_REGISTER_4(3 downto 1);
-self_coin_delay_5 <= '0' & WIDTH_REGISTER_5(3 downto 1);
-
-del1_self: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => PTI1_DOWNSCALED,
- delay_value => self_coin_delay_1,
- delayed_pulse => PTI1_SELF_COIN);
-
-del2_self: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => PTI2_DOWNSCALED,
- delay_value => self_coin_delay_2,
- delayed_pulse => PTI2_SELF_COIN);
-
-del3_self: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => PTI3_DOWNSCALED,
- delay_value => self_coin_delay_3,
- delayed_pulse => PTI3_SELF_COIN);
-
-del4_self: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => PTI4_DOWNSCALED,
- delay_value => self_coin_delay_4,
- delayed_pulse => PTI4_SELF_COIN);
-
-del5_self: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => PTI5_DOWNSCALED,
- delay_value => self_coin_delay_5,
- delayed_pulse => PTI5_SELF_COIN);
-
-tof_generate_delay : for t in 0 to 5 generate
- del_tof: DELAY port map (
- clk => clk_300MHz,
- to_be_delayed => tof_one_clock(t),
- delay_value => DELAY_REGISTER_4(3 downto 0),
- delayed_pulse => tof_del(t));
-end generate;
-
--------------------------------------------------------------------------SCALER
-scal1: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz, --PTI1÷5 before inhibit
- input_pulse => PTI1_DELAYED,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI1_count);
-
-scal2: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => PTI2_DELAYED,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI2_count);
-
-scal3: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => PTI3_DELAYED,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI3_count);
-
-scal4: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => PTI4_DELAYED,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI4_count);
-
-scal5: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => PTI5_DELAYED,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI5_count);
-
-scal1a: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz, --PTI1÷5 after inhibit
- input_pulse => eco_s(9),
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI1_ACCEPTED);
-
-scal2a: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => eco_s(10),
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI2_ACCEPTED);
-
-scal3a: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => eco_s(11),
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI3_ACCEPTED);
-
-scal4a: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => eco_s(12),
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI4_ACCEPTED);
-
-scal5a: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => eco_s(13),
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_PTI5_ACCEPTED);
-
-scalts: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz, --TS, VS and dead
- input_pulse => TS_DELAYED,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_TS_count);
-
-scalvs: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => VS_DELAYED,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_VS_count);
-
-scaldead: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => dead,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_DEAD_count);
-
-scalmdc: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz, --MDC and TOF
- input_pulse => mdc_one_clock,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_MDC);
-
-scaltof: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => tof_mux,
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_TOF);
-
-scalmux1: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => mux_out(0),
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_MUX1);
-
-scalmux2: SCALER_S port map (
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- input_pulse => mux_out(1),
- scaler_reset => scaler_reset_internal,
- scaler_value => SCALER_MUX2);
-
----------------------------------------------------------------------------DOWNSCALE
-dwsc1: DOWNSCALE port map (
- clk => clk_300MHz,
- disable => out_inhibit,
- to_be_downscaled => PTI1_DELAYED,
- downscale_value => DOWNSCALE_REGISTER_1(3 downto 0),
- downscaled => PTI1_DOWNSCALED);
-
-dwsc2: DOWNSCALE port map (
- clk => clk_300MHz,
- disable => out_inhibit,
- to_be_downscaled => PTI2_DELAYED,
- downscale_value => DOWNSCALE_REGISTER_2(3 downto 0),
- downscaled => PTI2_DOWNSCALED);
-
-dwsc3: DOWNSCALE port map (
- clk => clk_300MHz,
- disable => out_inhibit,
- to_be_downscaled => PTI3_DELAYED,
- downscale_value => DOWNSCALE_REGISTER_3(3 downto 0),
- downscaled => PTI3_DOWNSCALED);
-
-dwsc4: DOWNSCALE port map (
- clk => clk_300MHz,
- disable => out_inhibit,
- to_be_downscaled => PTI4_DELAYED,
- downscale_value => DOWNSCALE_REGISTER_4(3 downto 0),
- downscaled => PTI4_DOWNSCALED);
-
-dwsc5: DOWNSCALE port map (
- clk => clk_300MHz,
- disable => out_inhibit,
- to_be_downscaled => PTI5_DELAYED,
- downscale_value => DOWNSCALE_REGISTER_5(3 downto 0),
- downscaled => PTI5_DOWNSCALED);
-
-dwscts: DOWNSCALE port map (
- clk => clk_300MHz,
- disable => out_inhibit,
- to_be_downscaled => TS_DELAYED,
- downscale_value => DOWNSCALE_REGISTER_TS(3 downto 0),
- downscaled => TS_READY);
-
-dwscvs: DOWNSCALE port map (
- clk => clk_300MHz,
- disable => out_inhibit,
- to_be_downscaled => VS_DELAYED,
- downscale_value => DOWNSCALE_REGISTER_VS(3 downto 0),
- downscaled => VS_READY);
-
--------------------------------------------------------------------------------WIDTH
-setw1: SET_WIDTH port map (
- clk => clk_300MHz,
- to_be_set => PTI1_DOWNSCALED,
- width_value => WIDTH_REGISTER_1(3 downto 0),
- width_adjusted_pulse => PTI1_READY);
-
-setw2: SET_WIDTH port map (
- clk => clk_300MHz,
- to_be_set => PTI2_DOWNSCALED,
- width_value => WIDTH_REGISTER_2(3 downto 0),
- width_adjusted_pulse => PTI2_READY);
-
-setw3: SET_WIDTH port map (
- clk => clk_300MHz,
- to_be_set => PTI3_DOWNSCALED,
- width_value => WIDTH_REGISTER_3(3 downto 0),
- width_adjusted_pulse => PTI3_READY);
-
-setw4: SET_WIDTH port map (
- clk => clk_300MHz,
- to_be_set => PTI4_DOWNSCALED,
- width_value => WIDTH_REGISTER_4(3 downto 0),
- width_adjusted_pulse => PTI4_READY);
-
-setw5: SET_WIDTH port map (
- clk => clk_300MHz,
- to_be_set => PTI5_DOWNSCALED,
- width_value => WIDTH_REGISTER_5(3 downto 0),
- width_adjusted_pulse => PTI5_READY);
-
-setw7: SET_WIDTH port map (
- clk => clk_300MHz,
- to_be_set => VS_DELAYED,
- width_value => WIDTH_REGISTER_VS(3 downto 0),
- width_adjusted_pulse => VS_WIDTH_SET);
-
---*/*/*///*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ --READ NOTE 1)
-mdc_tof_trigger_width_set <= '1'; --(a)
---*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*
-
-setw_mdc_tof_trigger: SET_WIDTH port map (
- clk => clk_300MHz,
- to_be_set => mdc_tof_or,
- width_value => BRANCH_EN_with_MDC_TOF_WIDTH(3 downto 0),
--- width_adjusted_pulse => mdc_tof_trigger_width_set); --(c)
- width_adjusted_pulse => open); --(b)
-
-setwout: SET_WIDTH_special port map (
- clk => clk_300MHz,
- to_be_set => GLOBAL_TIMING_SIGNAL_OUT,
- width_value => x"6", -- fixed to 20 ns
- width_adjusted_pulse => LEMOU(1));
-
-------------------------------------------------------------------------------------------OUTPUT
-delaygen1 : for i in 1 to 7 generate
- delay_out : ECO_DELAY port map (
- clk => clk_300MHz,
- signal_in => eco_s(i),
- signal_out => eco_out(i));
-end generate;
-
-ECO(7 downto 1) <= eco_out(7 downto 1);
-
-setmux1: SET_WIDTH port map (
- clk => clk_300MHz,
- to_be_set => mux_out(0),
- width_value => "0010",
- width_adjusted_pulse => ECO(8));
-
-delaygen2 : for i in 9 to 15 generate
- delay_out : ECO_DELAY port map (
- clk => clk_300MHz,
- signal_in => eco_s(i),
- signal_out => eco_out(i));
-end generate;
-
-ECO(15 downto 9) <= eco_out(15 downto 9);
-
-setmux2: SET_WIDTH port map (
- clk => clk_300MHz,
- to_be_set => mux_out(1),
- width_value => "0010",
- width_adjusted_pulse => ECO(16));
-
-Inst_new_downscale_ck: new_downscale_ck PORT MAP(
- downscale_value => DOWNSCALE_REGISTER_CLOCK(3 downto 0),
- clk => clk_300MHz,
- output_disable => CAL_TRIGGER_DISABLE,
- scaler_reset => scaler_reset_internal,
- downscaled => CLOCK_DOWNSCALED,
- global_inhibit => out_inhibit,
- cal_inhibit => cal_inhibit,
- cal_trigger => cal_trigger);
-
-
-LEMOU(2) <= out_inhibit;--OR_out;-- GLOBAL_TIMING_SIGNAL_OUT; --Now calib pulse is coming out from lemo n°1, this output is unused
-
-Inst_beam_ramp: beam_ramp PORT MAP(
- clk_300MHz => clk_300MHz,
- clk_50MHz => clk_50MHz,
- input => lemin_s(1),
- output_inhibit => beam_inhibit,
- output_external => TIN(12),
- delay_value => DELAY_REGISTER_BEAM,
- width_value_inhibit => WIDTH_INHIBIT_REGISTER_BEAM,
- width_value_external => WIDTH_EXTERNAL_REGISTER_BEAM);
-
---------------BUS COMMUNICATION
-
-Inst_bus_data_com5: bus_data_com5 PORT MAP(
- clk_300MHz => clk_300MHz,
- clk_100MHz => clk_100MHz,
- gts_pulse => GTS_to_databus,
- cal_trigger => cal_trigger,
- bus_busy => IOO(16), --not used
- bus_ack => IOO(15),
- bus_retx => IOO(14),
- latch => eco_out(7 downto 1),
- latch_dsc => eco_out(15 downto 9),
- scaler_pti1 => scaler_pti1_count,
- scaler_pti2 => scaler_pti2_count,
- scaler_pti3 => scaler_pti3_count,
- scaler_pti4 => scaler_pti4_count,
- scaler_pti5 => scaler_pti5_count,
- scaler_ts => scaler_ts_count,
- scaler_vs => scaler_vs_count,
- scaler_dead => scaler_dead_count,
- bus_inhibit => bus_inhibit,
- dtu_inhibit => dtu_inhibit,
- ecl_bus_data => TIN(11 downto 10),
- ecl_bus_clk => open,--TIN(9),
- com_run => com_run,
- dtu_bus_t => dtu_bus_t,
- dtu_bus_ts => dtu_bus_ts,
- dtu_bus_td => dtu_bus_td,
- DTU_CODE_SELECT => DTU_CODE_SELECT,
- DEBUG_REG_01 => DEBUG_REG_00(15 downto 0),
- cal_inhibit => cal_inhibit,
- out_inhibit => out_inhibit,
- TRB_BUSY_ENABLE => TRB_BUSY_ENABLE
- );
-
- --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/
- hpv(14) <= not dtu_bus_t; --This is a "firmware patch": the VME connector
- hpw(14) <= not dtu_bus_ts; --for DTU is reversed (mistake in pcb layout) so
- hpw(10) <= not dtu_bus_td(3); --all the I/Os must be inverted
- hpv(10) <= not dtu_bus_td(2);
- hpw(12) <= not dtu_bus_td(1);
- hpv(12) <= not dtu_bus_td(0);
- hpw(8) <= 'Z';
- ----------------------
- hpv(15) <= dtu_bus_ts; --With this connections all the DTU signals are
- hpv(11) <= dtu_bus_td(3); --on one debug socket (hplv or hplw) that can conveniently
- hpv(13) <= dtu_bus_td(1); --plugged to a logic analyzer. Be aware though, some signals
- hpv(9) <= '0'; --are inverted
- hpv(7 downto 0) <= x"00"; --unused
-
- hpw(15) <= dtu_bus_t;
- hpw(11) <= dtu_bus_td(2);
- hpw(13) <= dtu_bus_td(0);
- hpw(9) <= '0';
- hpw(7 downto 0) <= x"00"; --unused
- --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/
-
- SCALER_PTI1 <= SCALER_PTI1_count;
- SCALER_PTI2 <= SCALER_PTI2_count;
- SCALER_PTI3 <= SCALER_PTI3_count;
- SCALER_PTI4 <= SCALER_PTI4_count;
- SCALER_PTI5 <= SCALER_PTI5_count;
- SCALER_TS <= SCALER_TS_count;
- SCALER_VS <= SCALER_VS_count;
- SCALER_dead <= SCALER_dead_count;
-
-TIN(16 downto 13) <= "0000";
-
---------------PTI5 & TS mux
-
-mdc_tof_mux: process(clk_300MHz)
-begin
- if rising_edge(clk_300MHz) then
-
--- case tof_one_clock is --multiplicity 2 detector
- case ecl(14 downto 9) is --multiplicity 2 detector
- when "000011" => tof_mult_2 <= '1';
- when "000101" => tof_mult_2 <= '1';
- when "001001" => tof_mult_2 <= '1';
- when "010001" => tof_mult_2 <= '1';
- when "100001" => tof_mult_2 <= '1';
- when "000110" => tof_mult_2 <= '1';
- when "001010" => tof_mult_2 <= '1';
- when "010010" => tof_mult_2 <= '1';
- when "100010" => tof_mult_2 <= '1';
- when "001100" => tof_mult_2 <= '1';
- when "010100" => tof_mult_2 <= '1';
- when "100100" => tof_mult_2 <= '1';
- when "011000" => tof_mult_2 <= '1';
- when "101000" => tof_mult_2 <= '1';
- when "110000" => tof_mult_2 <= '1';
- when others => tof_mult_2 <= '0';
- end case;
-
- case PTI5_TS_ALTERNATIVE(4) is
- when '0' => pti5_mux <= PTI5_ONE_CLOCK;
- when '1' => pti5_mux <= tof_mult_2_one;
- when others => pti5_mux <= 'X';
- end case;
-
- case PTI5_TS_ALTERNATIVE(0) is
- when '0' => ts_mux <= TS_ONE_CLOCK;
- when '1' => ts_mux <= tof_or;
- when others => ts_mux <= 'X';
- end case;
- end if;
-end process mdc_tof_mux;
-
---------------MDC & TOF scaler mux
-
-pti5_ts_mux: process(clk_300MHz)
-begin
- if rising_edge(clk_300MHz) then
- case SCALER_MDC_TOF_SELECT(7 downto 4) is
- when x"0" => mdc_mux <= mdc_s1(0);
- when x"1" => mdc_mux <= mdc_s1(1);
- when x"2" => mdc_mux <= mdc_s1(2);
- when x"3" => mdc_mux <= mdc_s1(3);
- when x"4" => mdc_mux <= mdc_s1(4);
- when x"5" => mdc_mux <= mdc_s1(5);
- when others => mdc_mux <= '0';
- end case;
-
- case SCALER_MDC_TOF_SELECT(3 downto 0) is
- when x"0" => tof_mux <= tof_one_clock(0);
- when x"1" => tof_mux <= tof_one_clock(1);
- when x"2" => tof_mux <= tof_one_clock(2);
- when x"3" => tof_mux <= tof_one_clock(3);
- when x"4" => tof_mux <= tof_one_clock(4);
- when x"5" => tof_mux <= tof_one_clock(5);
- when others => tof_mux <= '0';
- end case;
- end if;
-end process pti5_ts_mux;
-
--------------- TOF & MDC logic
-
-tof_mdc_logic: process(clk_300Mhz)
-begin
- if rising_edge(clk_300MHz) then
-
- mdc_s <= ECL(6 downto 1);
- tof_s <= ECL(14 downto 9);
- mdc_s1 <= mdc_s;
- tof_s1 <= tof_s;
-
- mdc_tof_or <= (((tof_del(0) and not mdc_s1(0)) or (tof_del(1) and not mdc_s1(1)) or
- (tof_del(2) and not mdc_s1(2)) or (tof_del(3) and not mdc_s1(3)) or
- (tof_del(4) and not mdc_s1(4)) or (tof_del(5) and not mdc_s1(5)))
- and BRANCH_EN_with_MDC_TOF_WIDTH(4));
-
- tof_or <= (ecl(9) or ecl(10) or ecl(11) or ecl(12) or ecl(13) or ecl(14));
-
- end if;
-end process tof_mdc_logic;
-
--------------- Final AND-OR logic function
-
-logic: process(clk_300MHz)
-begin
- if rising_edge(clk_300MHz) then
-
- -------------------------------------- GATE SELECT SINGLE
-
- PTI1_and_GTS <= ((PTI1_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(1))
- or (PTI1_SELF_COIN and TS_GATING_DISABLE(1)));
- PTI2_and_GTS <= ((PTI2_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(2))
- or (PTI2_SELF_COIN and TS_GATING_DISABLE(2)));
- PTI3_and_GTS <= ((PTI3_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(3))
- or (PTI3_SELF_COIN and TS_GATING_DISABLE(3)));
- PTI4_and_GTS <= ((PTI4_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(4))
- or (PTI4_SELF_COIN and TS_GATING_DISABLE(4)));
- PTI5_and_GTS <= ((PTI5_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(5))
- or (PTI5_SELF_COIN and TS_GATING_DISABLE(5)));
-
- OR_out <= (PTI1_and_GTS and OR_ON_OFF(0)) or
- (PTI2_and_GTS and OR_ON_OFF(1)) or
- (PTI3_and_GTS and OR_ON_OFF(2)) or
- (PTI4_and_GTS and OR_ON_OFF(3)) or
- (PTI5_and_GTS and OR_ON_OFF(4)) or
- (TS_READY and OR_ON_OFF(5)) or
- (VS_READY and OR_ON_OFF(6)) or
- (CLOCK_READY and OR_ON_OFF(7));
-
- lemin_s <= LEMIN;
- lemin_s1 <= lemin_s;
- dtu_bus_tb_s <= not hpv(8); --dtu trigger busy
-
- dead <= TS_DELAYED and (not out_inhibit);
-
- out_inhibit <= lemin_s1(0) or beam_inhibit or bus_inhibit or dtu_inhibit;--
- --or dtu_bus_tb_s;--
- --or (not com_run);
- TIN(9) <= cal_trigger;
- GLOBAL_TIMING_SIGNAL_OUT <= (OR_out and (not out_inhibit) and (not cal_inhibit));
--- and not out_inhibit) or (OR_out and (not out_inhibit) and (not cal_inhibit));
- GTS_to_databus <= OR_out and not out_inhibit and not cal_inhibit;
-
-
- end if;
-end process logic;
-DEBUG_REG_00(31 downto 29) <= OR_out & out_inhibit & cal_inhibit;
-DEBUG_REG_00(28 downto 24) <= lemin_s1(0) & beam_inhibit & bus_inhibit & dtu_inhibit & dtu_bus_tb_s;
----------------- Outputs
-
-assign: process(clk_300MHz)
-begin
- if rising_edge(clk_300MHz) then
-
- eco_s(1) <= PTI1_DELAYED; -- Latches before downscale
- eco_s(2) <= PTI2_DELAYED;
- eco_s(3) <= PTI3_DELAYED;
- eco_s(4) <= PTI4_DELAYED;
- eco_s(5) <= PTI5_DELAYED;
- eco_s(6) <= TS_DELAYED;
- eco_s(7) <= VS_DELAYED;
--- ECO(8) is mux 0
- eco_s(9) <= (OR_ON_OFF(0) and ((PTI1_DOWNSCALED and TS_GATING_DISABLE(1))
- or (PTI1_and_GTS and not TS_GATING_DISABLE(1))));
- eco_s(10) <= (OR_ON_OFF(1) and ((PTI2_DOWNSCALED and TS_GATING_DISABLE(2))
- or (PTI2_and_GTS and not TS_GATING_DISABLE(2))));
- eco_s(11) <= (OR_ON_OFF(2) and ((PTI3_DOWNSCALED and TS_GATING_DISABLE(3))
- or (PTI3_and_GTS and not TS_GATING_DISABLE(3))));
- eco_s(12) <= (OR_ON_OFF(3) and ((PTI4_DOWNSCALED and TS_GATING_DISABLE(4))
- or (PTI4_and_GTS and not TS_GATING_DISABLE(4))));
- eco_s(13) <= (OR_ON_OFF(4) and ((PTI5_DOWNSCALED and TS_GATING_DISABLE(5))
- or (PTI5_and_GTS and not TS_GATING_DISABLE(5))));
-
- eco_s(14) <= TS_READY and OR_ON_OFF(5);
- eco_s(15) <= VS_READY and OR_ON_OFF(6);
--- ECO(16) is mux 1
-
------------------ Multiplexers
-
- case MUX_SELECTOR_1 is --0x5c
-
- when "0000" => mux_out(0) <= PTI1_DELAYED; --0
- when "0001" => mux_out(0) <= PTI2_DELAYED;
- when "0010" => mux_out(0) <= PTI3_DELAYED; --2
- when "0011" => mux_out(0) <= PTI4_DELAYED;
- when "0100" => mux_out(0) <= PTI5_DELAYED; --4
- when "0101" => mux_out(0) <= TS_DELAYED;
- when "0110" => mux_out(0) <= VS_DELAYED; --6
- when "0111" => mux_out(0) <= PTI1_and_GTS;
- when "1000" => mux_out(0) <= PTI2_and_GTS; --8
- when "1001" => mux_out(0) <= PTI3_and_GTS;
- when "1010" => mux_out(0) <= PTI4_and_GTS; --a
- when "1011" => mux_out(0) <= PTI5_and_GTS;
- when "1100" => mux_out(0) <= TS_READY; --c
- when "1101" => mux_out(0) <= VS_READY;
- when "1110" => mux_out(0) <= OR_out; --e
- when "1111" => mux_out(0) <= GLOBAL_TIMING_SIGNAL_OUT;
- when others => mux_out(0) <= 'X';
-
- end case;
-
-
- case MUX_SELECTOR_2 is --0x60
-
- when "0000" => mux_out(1) <= PTI1_DELAYED; --0
- when "0001" => mux_out(1) <= PTI2_DELAYED;
- when "0010" => mux_out(1) <= PTI3_DELAYED; --2
- when "0011" => mux_out(1) <= PTI4_DELAYED;
- when "0100" => mux_out(1) <= PTI5_DELAYED; --4
- when "0101" => mux_out(1) <= TS_DELAYED;
- when "0110" => mux_out(1) <= VS_DELAYED; --6
- when "0111" => mux_out(1) <=tof_mux; --PTI1_READY;
- when "1000" => mux_out(1) <='0'; --PTI2_READY; --8
- when "1001" => mux_out(1) <='0'; --PTI3_READY;
- when "1010" => mux_out(1) <='0'; --PTI4_READY; --a
- when "1011" => mux_out(1) <=mdc_tof_trigger_width_set;--PTI5_READY;
- when "1100" => mux_out(1) <= TS_READY; --c
- when "1101" => mux_out(1) <= VS_READY;
- when "1110" => mux_out(1) <= CLOCK_READY; --e
- when "1111" => mux_out(1) <=mdc_mux; --VS_WIDTH_SET;
- when others => mux_out(1) <= 'X';
-
- end case;
-
- end if;
-end process assign;
-
-end RTL;
+++ /dev/null
-NOTE "CREATOR" "Xilinx iMPACT Software";
-NOTE "DATE" "2008/04/28";
-NOTE "STAPL_VERSION" "JESD71";
-NOTE "ALG_VERSION" "1";
-NOTE "DEVICE" "UNSPECIFIED";
-NOTE "CHECKSUM" "UNSPECIFIED";
-NOTE "IDCODE" "UNSPECIFIED";
-NOTE "USERCODE" "UNSPECIFIED";
-NOTE "TARGET" "UNSPECIFIED";
-NOTE "STACK_DEPTH" "4";
-NOTE "MAX_FREQ" "1000000";
-ACTION RUN_XILINX_PROC "Run Xilinx Procedure" = XILINX_PROC;
-DATA MAINDATA;
-INTEGER I = 0;
-INTEGER D = 0;
-ENDDATA;
-PROCEDURE XILINX_PROC USES ADJUST_DELAY, MAINDATA;
-BOOLEAN X = 0;
-IRSTOP IDLE;
-DRSTOP IDLE;
-STATE RESET IDLE;
-POSTIR 0 ;
-PREIR 0 ;
-POSTDR 0 ;
-PREDR 0 ;
-POSTIR 0 ;
-PREIR 0 ;
-PREDR 0 ;
-POSTDR 0 ;
-' //Loading device with 'idcode' instruction.
-IRSCAN 10, $03c9
- ;
-DRSCAN 32, $00000000
-, COMPARE $f167c093
-, $0fffffff
-, X;
-IF (!X) THEN GOTO F;
-POSTIR 0 ;
-PREIR 0 ;
-POSTDR 0 ;
-PREDR 0 ;
-POSTIR 0 ;
-PREIR 0 ;
-POSTDR 0 ;
-PREDR 0 ;
-POSTIR 0 ;
-PREIR 0 ;
-PREDR 0 ;
-POSTDR 0 ;
-' //Loading device with 'idcode' instruction.
-IRSCAN 10, $03c9
- ;
-DRSCAN 32, $00000000
-, COMPARE $f167c093
-, $0fffffff
-, X;
-IF (!X) THEN GOTO F;
-' //Loading device with 'bypass' instruction.
-IRSCAN 10, $03ff
- ;
-' // Loading device with a `jprogram` instruction.
-IRSCAN 10, $03cb
- ;
-D = 1;
-WAIT D CYCLES;
-' // Loading device with a `bypass` instruction.
-IRSCAN 10, $03ff
- ;
-D = 21000;
-WAIT D CYCLES;
-' // Loading device with a `cfg_in` instruction.
-IRSCAN 10, $03c5
- ;
-D = 100000;
-WAIT D CYCLES;
-' // Check init_complete in ircapture.
-' //Loading device with 'Bypass' instruction.
-IRSCAN 10, $03ff
-, COMPARE $0010
-, $0010
-, X;
-IF (!X) THEN GOTO F;
-' STATE RESET;
-' // Loading device with a `cfg_in` instruction.
-IRSCAN 10, $03c5
-, COMPARE $0000
-, $0000
-, X;
-IF (!X) THEN GOTO F;
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-' WARNING: This STAPL file describes a data shift of more than 16K bits
-' which might exceed the capacity of your run-time environment.
-DRSCAN 7819936, @Kfk30000000@@l@@lAPggP8000003080010000E20000G000006081020GPqfC0e004GcFGo
-1D00GI00000C0m00400060C0W2040006080WqC82421YW09G05G03m@3W@dV@F@x@yp@pV@F
-__@uV@7Vy@ud@dUz@ql@dU_@qt@7U@@m@_Fym@3VCX88P0000GYa6a3G280G0YbC10081000
-0m0020050MhM00000W408820421u1001051uHW0I0wj18D0O638cY1_10G_Gr12baGB0080c
-K06GH90D28KT0wiuGcfeQmB5g0uV1OaY0Rqm3000Ci600YKmF0008NWu10ywZ39IUoWaBPu@
-HA_FaZ@@8v@EM_VZc@puv@BY_lYf@dew@8k_@Xi@ROx@5wm60mTTxaHjxf7Z@vnCeL0mc0u2
-W4Q_yd218fPWP000mJJ008f0LgvqZc34A3L21002qtW1J0OGfhd0u60OoLv006001008TsJ0
-00WX400emM30001yERQW100QnL5001WzeA700G008W0tzg2OJ5Wi8U8xpy10W00000f103I1
-WYnat0008Ax00WcK@VKQ3Qy8XyHC0208GA0FKDX70160MaUC20080000020W00000808GA0I
-ydZ7Y300QFMkyZP850Awx_XLKI300140000900GfXRmtr608W0000W8002000G47OZ100_Zm
-mJ34G0000WG001000WmkDtWK0C00600800000A0VdZHI1cP00W00000H102040145m100040
-20E00O00000410100W0G4000iVD6000ej200aPjPA0G0824004W0W000000202288W000080
-GG2000GG110010010WnoN100cZkjD310G8HG4040G000H001010005140G000KaK0I000000
-51Wzxh0u51mWzZfg50m@B2Fuf20@ZPcWdggi8cPQHuhoY0yVA0C00004y00GgvLm8008Qzn0
-G1C1W2O2m5m4W9W90J000c00K010a2038000@O73002rXX@@Nw@t5@@Rvdv3E648e192QmcV
-6as43L@l10WFd@@r2010GCX904008fm4IXBXt1D0002m@WU0_A1OJFmYKWXD4V8IXJu800CP
-6OJDcmMa60020OkH36QAX_3z00mB_@@l1W000WG0KEbj0wv1u@@t0O210808CsFL000ofL00
-u@@q0WP61000400G0220Wm7L10G8y@@izkf1hD238S3W@@J30082H000WE006c8044404IXA
-E200_@FD0W8600020OW00WIa0I00m@@d00e@y@@w0G62y@lAW0E0cIjk1IR1H00m@@o104Gu
-KrM_@@@@@nWDW00MI0WmbLPTXM_@@70mig00Ww1UL10er30e00m@@d0080Phtt0060A000r0
-00m@@g02S0u@@q000mZP00WuWdf0GaR18E07@ULRhINyQB@@l10q6W6m99py42tsuCgR9yQI
-004QrfE9PcdGFxjG0200100mCuI00004088GYxg0WN08xTO0W00C9F9Lrd0010WVmDOTj402
-6046E3G000QjV3000Cq700wlFXvtPG0000008000085qb00G008WG001000G80SBE3nvpm2_
-C0G08Odt7cbt0000W0600gltZD@P00muq@@9yS73pUR084000010B0p004020000e002khbX
-8RP8uU6YWt04020Lmp0G00000W00O01I0N50i505@V200G00801D5xH692DFj4000mu100Ka
-2O010023lbcwV00somVsRieD30100Y97Z@@t000WIY@21U70eBnYgusZmmjfxU3000GfM00O
-hRF002000009cyAw8dXqyJeck74800G5048CyP0020aXk1006O3bSZtzDeiV30Y004Jk4TqR
-GrtIiyF3@LpGOuda_v306K0QxZaAlP8cy40004i_U2Fb@Gux600f00W000001emmV00G2GOu
-Xa5V2000uID73000G0W8000K0082000I1G2v9W800WK00KA0C0AX82008GEw9iLl10100000
-X010W00Y0GEuC46k1f0mGOuO46V200SC@pUZQsDOvI3I8F10008f0mm1L600G0P1d700G000
-00H1aW38e0GWC00W0020We0220001W3e10004000XXp0G04WiOO8qU3000Grpl1WrK0_@l2m
-0W000O0030000WHW0000GK0WOoD0u00100W0W4m1NqRmYi6000000K0GveFG2g00000001G0
-000W00080010201W0000KOu60411CCS30H40a2W1XXB10040W000000ObF00KXN80004Y6m0
-00800G2082G004WA9XS38100y@@38G001004000060000X0W2I008Gt4823VcG_D0040000V
-w@@n02YWG2vR4Jk1eG0210Wc46EO0DQ0_@l200m20uV0mCpKfg@1NuBIbgM4W4oVmYOcf5X7
-002m@@@R0m00WiwJ00G0000040e900W9mT000Z0008CSOA4mWFTJme00m@@L000A0J0KG2vR
-0O20G13002u200W0e000Wc62cR@310KLVKf6000GArSH1jp044aA9G@m0RO0W00ypBIs7_Xf
-aDe7v700W0000WDRMF01004JC67njHq0ICaS83qY1010000UDdVLnejUyNT236NH7IdiecA0
-CV0YJpZPnO8IXJ6ks000WW4000000810G000m0000102002lCBHaF646k7vrnGnVE14000e0
-00000G000WzbR0P00mC0CeME30000E5k7dOR00WeZe7g00008000apdC8YE60080C2C31Wdm
-dnFy1d10a00c3nWdrD0020qwn6iVy3LSlnCx604r0eUFCQUeY5jL100AGa2608W00GWG0002
-0041001400204a5U20280MvOZCkJ8wQ3QdGYKtD0400HtTCqJX4jaRGMSCagN20088UdnWcz
-C0W0000Y8Y@@D00X0m@@g00OTu@VI001000020004mHr6SZV80001W400088000001000400
-G000X00020W8Y0008dW08004040@@h2BF1W@@b000mm3YF0000404W1W8214200N4x10022H
-4H00040_ht00010Xy9X88201880x_V2000IS100ZYI2008YDOCG4000W81W@@t004H4Y8E44
-000VKoGXT900100002400W0W0047xdGmvU00Otx@@G0208040000412000aGdb8G59WC00Wv
-W001000i40Wn9D000emcO6WPc100m8W0Oc02o8Gphinx@F0GD1uYrD0200000020A001000C
-h2WWGG042p00WW2ONpD00G4OcP001A282000e2000GK0003400W0eaB30004WW01200500G4
-00001BsRmEZU0000pa00GkVUyub100400e80056400000885W@@z00095000000904200040
-002X00040004IeGkV0000IoCX000000Gzv@@O001400G0000Gg@@DWK00000GWQyh0K00mc8
-FG040OHR6W100080006O0GOuF4Y63N@l1O95W@@h00X00G010X100NdQGFf6S3x9ZbRW0100
-CGn040Y280bWW6C2vG930W06Cgh100m10100dpN5PX9XU10W@@h00802000K020200010004
-10O0eN79YarW4rV000800044000502001488g0400126001000482000082W04Fg4h2v100P
-jHQz000W0400mGXRXD000sM1000E00141005sWGGOsBKP2G1WKl040000233F1G00000KHoS
-X40nA0@@B108m00200Q00008040000056G000y50O30LaRmqj9KYi1050W_@d104U0OMr0Ga
-xO2000ow000p00WkXJ000eAcfmVa3UL20er50v0y@V2eA00c_V3000SXli100m@stC00U000
-0uJ10wh20uv18000Cy1e_OFW1000301WtWV0@0x000_100W3000S100q1u0W1mE2ZmmD0040
-00G000W0mXj520WqpnCg0000n103000W083W1G720WC40v3a0000qIoJ8Q03ol81000000WC
-5WgmB0Gh7L000WM7Wmmb00w3kC30HS70KXXJbA3G1w70YsbI000WdtcUBB_@3000uCk39bBa
-Yms6000000WU@@d10084jEQm@@BrmaAT@Z1er4Wbz7h2T6UZRc85U0G00Ikw5DRk1P2PGmAF
-KK1C00O8xUNY2wheJT340014hk7LjPmazI800000G0Gmv6G004uiN3gz33W000VZRGXx608S
-1uIjMwMaa6pJ0100K1_6auj1BdpmjuFKc@6000mNELY2wh8I1Ls9VZPgJ0200mozaSYk100E
-zE_tWW@TgKS9wspWj1j1Cn0mvusCcS8Tbn0000XjvD8_V3G800KrlA0002nE00a1ZGR8kHgE
-6CdEF00OHJILhMupfW@70DF0i3lJpk@010202040NZyW000W6VK1000le10X2xZQhP38000W
-000Oa@44e00a_l1000IMwl500MqXKGLLR60W00000W0W020I100000405K0a8k100100902a
-xlA0H80w7t04100jlLn25s00G0000e0G000A004W00GY0@108Y8@Rg2000Kt000F@RGwtCat
-FF40Qm00009W00008O10Y00G8W0006001C000O010W500000D80CTqs20WqC0018@@R002GW
-3NM2620mjoC8000eTJ32@O60Q400C00AxZXCe@10K80010qyEJ004G0G0Q5G00000OH04002
-0001G0G13800Ws00HSf2PeGWK1O8FgkIB@XQiF100hIYsE100EuGH30E00afe10@00IWB10W
-1m802mT00WqsM2f20JBtY67UQLn130W3amso9hwGUztWSnJ0200GSO6C7B9d_Rm@@60aW1OJ
-kJ2zcXUlDeXkP0000M57C000GL200KJr6HAi4030W7jF1004mcwC00m9AXyJcA@Xa_DOlyD0
-0W00800ysV300W0izL83np0044WrdP0mR1GsyOKxF3fr6I0z600100001mEu6G0G40210G4x
-CaCa100000Y020000P3U6EVF10042XERGJD604400000XF10mGyt00001020agSUW000G7dR
-Krl1000C2i910W0W1_R0104WD@J000Am3@FSyV2040A67t04004000000irrdU8402000000
-022OQy4Agl24000HfRmf@9082euoU980000002eSKCG000kVF3a00100000kO0uMV600K0CG
-n6NTHLnOR00028243K000KF6INPx10H0WY2DukzDAztWgvDOgV3002000R_0000HrX6iXZP0
-002sotW3kzefy400000Ao1uN@4_KtWI50xBmD2y@Xu_D0000g1X0WsLTQr@A_poWUzDW00WG
-6R94DF608000010yyl100ax7fFXWRo9CVI000Y43N2vHRm3_I0000iZU3YXC12000440000X
-02G010W0WG4GFKGhJ00010G00GA20erU3000Xail1lmNnut60H100000W80G0000yS000000
-WG0f0000WGC09aaRKG040000W08000000IftCixj40004W000000C02000000K0W0000A8Z1
-8108W1n0amalE100W2800O0_60W00W00000408K000R_B1K040104X02400054G2Z0e@R308
-D4X40000GPeY0008O10020uM6qWGSr2080mnG64GT5W082Ykt000W000G2W00C200W4a1GmN
-q6qdI2R87LMS60G208aV3001200000140Gl_IW084G00q000G010G40002000H0W6000GQ3A
-0G41GQ30201Y1m000G00e10kzugDaR9t_40yi0i8zO6200W10000G00600mbt60004u4T3wb
-c10CGa4Go89WCWG0D1n0o0g1Y4434f00008at1HI0lZa0o0E1a44383868I0MjmW@h1hxQ32
-fx1L500_F8cnCLCZPm3t@0ulWmCJ110000kILLG0u@WO6pK1W@1FSCJLL220004p0CPN_Jzp
-m1qC4Vj70008P900CNNEzaRmPIW10m3gLTdU3@azrPOsuG0tr04jLEzax1000n5eD0200041
-0WVpP0000OizL4rI29f_m2wXyak1NvRmyq6yFj1zfdm@xO4Hf1xrpW841WHxJ0020Gbz600G
-00GW0000203020hyRGMhF00uGw@V3knnWG@TIW40020000404@@dW010WsrD0WG00C00WGiP
-OUR308000GW0uz@70d50i@79t18HhXdaLl1zhQGemL000040G0800020W04V9K1000MS000V
-zRGO@ayJO5N@BK3@FaJl1G48088000141000CsG65DhV2BxaGs@XG00GW002mMvL00We0008
-Y0GG40GWa4100Oem0akDItR7IVwO0020000GmxaCaNl1RJR0000K5300Tgho6zC4PVBbuN10
-00Zqtt0000OL@6000svCpMYktZPet0200mzn9y@l1088100m4q7V2P@p00W0G000p220XH10
-YWP000eV1mhdjCSQ2xoPmHzC000A8Y@MG002akL2raaGr@6Oa0000000XH00bW100008O200
-4dcA5Qx100W80828FnZ100GW5MPu3Q38bG0000002G1000GaVkb88S3000h_UJBh_Rmiu6iJ
-@3pZRGMsO0W0020W8skzF000G0CA0008AW3yz0Wf3GnNaW800P0Q30200000G08Y00408W0C
-UuKV3Ur73000Gf0@0u010O000I0004012200800WWmZ2I4lk12100oNY4W020W2000082KF1
-3lvdGW_600O08LELkut0200840080A00aQ@600cjw5lbE@POPx4k@tWgjt8GL6_@F1KO0W00
-uN000W00201G0010000a200@@p000m6W00BI0000ET0CfE900W4G00020088Wk4c8cXJmD00
-KO0200mioFf3w4W900ymk40UU000@Guk0m0_1m0000crfL10C3@@@OW8Y0000GL2rO0000Pt
-Q9Y5t00W1O0W9mT0007ly3m000W1W1S8d100aKhpc4WC000O00gdpWH0Iu@V6G50002mE8hS
-F0006a@@90G4t100i2Cy305q70M1000WE0r9srZj21000KA00mfvobJ_3xvx1009@Qh3fVst
-s_N2W9F055RpGIUqcy6dcRm@tCi5l7000WRDPZquv9XS32esWcKJ01020010W8OC8aUCwZdX
-fcD000F@_yO0201uYU30010iO530040_ftWJdhubE3080000K2W000GNw6yLE300W00208G0
-00yhL3QA@1W000pZdmg_90mQ0u@VC80G0zET201008W00aFk10808EdcX8TV00010002800W
-04K04000CSgV2208000102080000GOxv6SHF6m0002@tWc0C00005H10Whfh040WHd@60020
-OC83W000yGd14060knkbMzDOo@4G200G0000G20Gys9qkV2JMN100Wyn_t040000W0WVxV00
-W0m7@Cqwl1v_pmjx9KWU20100AtFXHjVG00WGj@X0o_080zAgdtWbvPuiR34000CRV2Y000A
-_ebiPJe6@420dXXyn000O1r10WL_nu5M3MXt004004W0802X40000CSVFcZdXUzJ8hU6wztW
-41F10000006lcJy0004GUyC80002000K0wUasl10020gCKYUmJOwzM0Ku0CC@68W0G004008
-80m0000W0000W00zidm9q6Cql400WWW000iGl100W8wed10008G0002toWTXD000GGcz9qJF
-6Vq_m@@90014PaQ3W1100001400C00000a0038GX2040WOW002000q3zO0080004W0000miy
-DunJ3W000qyT24004cmZaw@J00mVt5@O4Qb1020150202000GWK00404801e07vR00800091
-0@qNHdA6K1d1@@p00a2WSsC0800mUz90A00O9uG0nt0qI864G80Y6m0000H000e0008000WY
-G00mw76030Wu2E3_@@10043080WI@pWfsCuxr7W102ya@30104cys3F200NyZ1C00020W8bD
-a0O200000CK0000880aql1PkOm@@L0W22OcC6W00000W202e0mg_9080WCB_4Yst02008@_N
-10W1nAth8aX400H0000W10000O60WldDGC00mP@64_76Pv62006082001hO0W00WwhDed_4M
-_N2WK70r@Bn1j9im83lq_GX@O002582S6G80010080520800b0010WzXR010000s0400000A
-00L7t61IbWb10Wv@b0560OnR60020000G800000O2D00040e904ql10000G088P500ua@M00
-y000000W16GsrC0000Swn46_l200v9p@B100mV1820J1c00000U00008v0GEv1000G600Gjg
-V5WnVDey@AESt0w00000000G80a0N2000m10L00080r0002100WodC02030804WKfO8uV90R
-L0i_l40O00w4m0088860304200f000WG000g000O0A000e2m50000mFu@VFyl@0000KW200G
-r@I004Hy@@7YlR3000KU700Arp3Y3Uc20Hk5Wu_B000G0aJEH000WIF0ZYtxLTdK7E3bI@mO
-yF00000q31m2pRaGU200G0AOBd5tdS7TIkE_1G000Nxd0002WbqV000FSALXqwk1pxV200W0
-00G04400MiEXlKO8zV3m000iHj40W20Uf63GXA0D5xnAwCKa_3ZflHOgIqDh100W0800GqNl
-10GG0oyF10W203r@GNzCuVG0usT9wUtWvOD000CGkz9S9W1Pi7I@06yEQ2nWdm5II4yz6txd
-00WXbFZheSV36wtWRmnOUUCI_tWpWPuxV60G00G50001000008eMwJ000G10e0WWwn0Ox2u6
-_R80000200GW490044StZadC8vI6_VaY@3vu@FI_lZb@tev@CUQ@3JFsvtWZ_DegRI00akan
-DLW020wKJ2004W0008sHE1W010W00000W0aYF3Dm@mAy60oT1ORQ9U1j21000bKZnYvFKJQ2
-0000t0dXE0C000I0002WpzJexfD_Qs0000Cq500c5@XxIFPJxDkzgY64U0002Kcv6SRF3zcN
-100vrTjRfAJIG4028414W000008G0a8I10G001W0000G0WG080010021G000G000X820K100
-000G4GWDfDuKw400G08000G000Ony90wk0uNT30AG0y@l104102_s000020010W000qtR2G0
-W06Dd410C2004002o024G01G032W300G50A0P2G02C80641H0W8e000K008020005eW00K00
-000208244G8280C000001000050008008G00K80144000WG40028042G000000IzuR000HK0
-000040GIGrWayb0W0G0400WjqPOET60W020W080X00021YGGGeG60208004100W02418Y00O
-00W0048000428200200G000060001000W80W21G80u5K30Gm00WG00W0100000GG0000ki00
-10aOh1@@d00G4000G000G001010W00uu2300008W00G0000000404017wl1W0GKY000802G0
-002048W202310WW0I0290400910aGK0G02K00GW040m1001aG0412000010004000XEoDeS@
-4G10GW201000008D50G010W02001G0WG00080008G0GW000004WggpZMXPeOO60W8400W00W
-0W0G04aLhD0C000W06Wm9OW000800012mW0lvQGYz60800OcR6I@r00060000815000400OE
-N3000a4@F65ch21W1020W00H43G80O020G08G4014001W8809000404_@l1G140W20000001
-0WCmHr600048rV9W000010000Mz1000000240002ojtWrvDW400GU09804GOP@M0G02A0W20
-80001003G2400000032000100101000a0H0C1a0000092acj1lnRGq@U0eE0uUV30G810002
-40e0sRx9iCQEW1WWEan0W8W1H@R0000280480m000081iZk1V@RGOy9a@V2rrRGSxC0000KB
-0WGe@900G0101000020042008106UdXh3y8gV6m0J4GnW02HHX1I01828092ImW88n100G4X
-WW00EO0H2H0W204402m2Y0WGm005002Y000G1010W0000Dul10840knF11000460000mV301
-W0080000G2a000eIg8C2H49840OCZ7UzEX65814034194G4GGW2a2i4324002100WKC5H045
-W2800a0W2841H0O0004Y08008052080X_@t0a800GW00Yxd180W0F_R08t10000005200828
-Shl1G4HA040A200euo_48W00Kjk7@@p00WC00002WIA00008G41000000P1H00W20800f808
-00403WK000m00WDXC08285Y00WwHC0a0W0f0000002WI000000H0fW4008W00GA0004a6000
-00GGAW0Ot@40W12100000W84f0000W00aY000WGIjzj1Rpg2GK000K400100W00080G0G000
-4GG0410G0W0140004810000G000204WWW2000HG44046l1tTR0G00000120H10W0Pa10G000
-mLQdy6yaa1x@RW9m0000000034820080001GY00CG0WKh9ft@404O080G0K1W1860A4G0K80
-X8c00W81k10G000441gWz@D038Wc0G080G0002080C0B4Ql1004000G14sZ1221C060G0E00
-0Ke80E0008040o8606Cm000030u1O02eH803B0G12000823012404GInN5G8ae001e9W0002
-14444H08400004340800a4C009X0A842Y000008G06000004GO00grq42wt00008400G0W2G
-200840040000O_200400GwfmWQLJ0G488180mbKJupwMGX0W20oD1G00810040001CXG00G3
-4u0010Gl0mLH600A5000082eq0000eQ080odr0GG0101uLGW0020WCP_A3040KW0201ul000
-WFRGG080WyL0400002010000Rq34ij25i1O0W_B210000XW040e00400eU100Ixz40yJ5000
-018CmmNJE01000tT00tf200u00St1_XTsfI0JuBJ00000mN0000000VP2GXdg0000Gax5ft0
-uf3m@@600o9700eAWMF0WNL0W700E_d100W1yF00o1@40S000WB0006W30C0M1w0g100K300
-06000W10003G10LjR0CqL000O00003I1m0w30H0T0C08000y30003000W000W08003WH06Wx
-000t1000000EfK000WB0006030C0t1O0e000S7000E000e900mFm106WV0C0t000s1zbhYW2
-uE70mNc0exS0Y82000N0kx0005000m3v@R000e20000W8Y0y3004bS2JSNH7v90088000mFc
-100000eg7000F4xA0goK0C3mm@Cm03086kPkiEXoctebiJ0sy0i@jMXGpmts9CcT2008023M
-YckPeiR30000fV00OYxA00W04pV2Bpeoezm4O39004fJKFgJoD8CB3000008088zP6w_FX3k
-VexyAgEt0Gm90rQLHa2CKAN5@@Z10402e0022020104G0GWGWWG840O40e008002C0020000
-304000G44mRrD0C00KcR6000W8r03000GjtE30010000GhV0Gejx4cTlYnw8PNl700G86yk1
-0100000Y00I11GWW8214KW4e04000fA080G824A02CG1C000G900GWW08A0H084G822404KW
-20W20000800GK0040W00G10000xlG000WG8000G4000100X0WxiD00W0G1w60400uaU36LtZ
-0wJ000G80340884W0400110G1120400C8SG4G000WG4a0900821034001804I200040GG00W
-W00e0G002G20008011X00001C02000GOM13000120000iu0W000WRuCulE3ImFXF6Dey_4cN
-@400000208400002000400080W8H000010OG2I01G0022000W8204G4C004W058W0400I000
-08802800WG22200001OG0u6130G80000W00010000QwA000W08000G010W8J93EeNYgwse9E
-9002201080WW000C40020W04W1A5q00028000200080002480000H2Ge0005lRmpx60W10Oo
-V3_T@100amrAOmByCSpv6LqdmYX6yAV502GW10O0010u100004044020404IXG8W08000004
-04GG020000o0000000060X0000W0W022002HpNHv_6mqq1uXT66wt010G0V_@Gfz94zl1rAi
-1001040000090G400m2W0220G08000001009000W000404480W80W000W40W0W0400HKqk10
-G0G0020koV23wR008000800000mWE00Cy@30W10Est00W01BKeIr@90G0WOfV300WGaqG200
-02G00W0280G0000010aj@I01K0nQ_C4AP500kGJfl20400nuRmF_9000W8_@4YoV3000DY84
-b0aKWG8W806GK51841Y40G023k458I8Oe220H4ZO04K0M0Ee024DQ8H0G00yA130000eG02G
-m00W020WMyDG000000GWYLD0a03W000WT_J000C200eK10G8G0040001451300G0_@8X6xz0
-XG080O4244CHO10W44D0W4880G0004H10008W8000e0080A0G0101090G8a6Gem004016C0W
-100008GJBI0W000000jpH0WG@P00GWmm@60180enV908000040eoE3400HCkF6005e2Rp0I1
-9a00GcWaK0G0000AI95Y0W0P8eK8300W02WG80O00002fa200GWCOIA00908G40a20W00G0G
-Wh1C0K00G@@600W5lrK380100004WG00001008840W0000Y021000Oym4Iar0014000W00WG
-0000IOCLC4000Syc1C20Ge00eeX0018Y400002W0Y8008Wm0810044G00W10G1000080H400
-4G1045K0261Gy9600GGuCr4YYp0mJE0G000002W080000WWHql643d1G030000WyeB3RyQ00
-01WvuCu@VC0mW0881n0032000K04X1W4Y10H4HGH0A0200082Fm2K8WWme1Z0006W1mC4004
-0GW0O0101oW1e8W5G00YWw@V30WW5W8000044GWK68T0WgrL3040500W32Ju102W0802PObj
-_00110C000XyQ008000G1W@@Z100WH00C4GGG9102100011WC010X80211A88020aW000002
-5e000000028e200W880C0I485000WW8GY0Vb01G00G40000xjJKm04W80000GJ4PmTLU43t6
-00010k90bxc10W23G08Wx5AC0e0mkN42003050180GnD000GV1560800@5010u0W0G040Ku2
-001vlG830000q000040G0001080000GA0000WG9160G00G3000W0000040eW6422uUX2GYbp
-WuUO0400000LaAZD0G0G10000WI00@@B10S000CH000Gt10W000018WN3000tv00kp10WBS1
-0000000W2wZasWtGD0n53mWA6y@F6o100_@t300WPL98n@@Re000WY000C060O0S1vkPGMS6
-000u2u0e9mFG5XV00Up000m1000C000O0E0y6S7W1uE0WsP000CBf1WG70m48300W9u@V300
-aX56d1W040e98YG7mD00WVGiS6000a1u0W0G4000H00v4R00G000W0m003WG00W7n66000L1
-0ea3WxE000000K0mieD0Wg0WVg80VDXVO200010G8Y0000000C0u7L0mNc000Aum30000Wi0
-0_@F18Y80G4H000000050u@@4UYqWr9au@@Ps1FXAb896E60700iFk7hcx4004WUhJO@S3Aq
-qWBqh8oR300CvFikM@@Z4m45Wje8P7_Y0002yYa1nddmYy6aVb1PxX1000U4300zu55001W5
-gC000000G80G00000H800802040m000m_MC0100u6_4wgu10008080G000000WTT203ontWo
-xJ86S6ohhbWnO0e000001000010050012008100000800W000GW2000002000G0ya@40010S
-pF60c70M0FXK_Pu1z4YGE10080f8ZHy@FKhj1G0Wec_t0048000000800300GOrD3MSt0500
-008006kFXynIetj40401080000008610Wb0I82R6ALWXdyDe2R3gj7600G0000900E4SLa1n
-qP0c00W1kJeX@4k64300et3@R0002000W4D4CJhzLa8@3ntdWG00WkdtOWEC0h1048oOb_dW
-0000000GW410sK_X1Gt000OZF10W4zUuzaVAzFXH_b000020004W901G450cJlYFuIuoV600
-Ca3W04OOL3c8aXEFlI000GIy6ySv6RbB1mT5WbKZY000mFZ94cA3000CoTt03CH0pP@m8z60
-010uiH90000nS00OBE30008amV2NPsIHDa4Fl10W4400082LCW1GG0nI_LiPa1tD_00WeM0G
-005lzmhf9qCxFBz@0e00000010GA0080YaaZ40001000m21e00029001000840L@d0OE4G00
-02010XoscXs@DenU3Yc5c@pD81TC00W0010q8vo7000W00H00080mym606GWOMQ32nF1h110
-08000061K5d1ltdmYy6SRKE@fzmwi6Sbl10W00Xe1Oa@@300A0000WG082w@V3MspWh@D00m
-@4A00eZSVuQq4guUckEs008004W100G0002820601ScS5L3bmm@C0y408Oq7k9udQLJ8b@70
-0GY000001002W0W2o0000b20UCd10GW00000G0H40G00mB00mvfC0000dUK20000K4040je_
-0008X3fifhC3Y_j200wh000000L1CsV8003CMzF1000NTka0O00WGf5wgL3o8k20W00003WH
-04Wx000emS6010000G6eoL3000G000m08000mE2WL@J0KuOIUY60S0G87x7s3WXDiB200u0@
-100mZ8u20k840H0aslAmq@0gUZd2q630mY@AzdSjDLpVbmj@60I00uq@A0Tx0avz99m1sdsO
-00002E00G0FpSYJEXV@misCC5F600cs_rwazrL9gy4Q@E100101nQ00G0000I0G0W02GdXGj
-D82T3wsl2mJ60@6BnAJyykk1040000W02001OqO3__t0008WG00OIutWroDusM3whJYahU8Q
-w4sQKb@hn0400800000044zmR000900100rkPGv@600GK000044G088001@@R000Wa7_D0G0
-1mttO00GNRRxJAvMYbsV0000KQtCqOl1Rrd0008Wv@D0m00mrzFiOF3nfN1uE4Wi7GgH_D_z
-_XkYQ1000Xm00WQuOB5qP0W10dKWeW@U0gVBgAJzug@DQel2000qW600w6He_z3Pqv4sntWM
-6n8ryA0086aKWJRjzpc@L0yn0OMFd2wV320209@dmwyRqfl11wd0000C8300r4WKdS9qzu6v
-zdmJrR01008wI600WBSQxF5fzG0eL000W2W000W20WwNJuS_4A_NYe0Ce_V600j0CqZG4082
-M1yahviny00mEmW1008W403mF@F8100uhV9GW00_ul4000EVyyd0vO0140G_0LSPZeXlP091
-0WL_D0400000HWe0me9E3o2xXzjDezlV000WO080eHEL00u1ivjA002SkgMh8b4AwV30DC04
-gjMttRm9@L0001OLy4IotWIgn00005g00WJonuFh4_CtcJBzuzy4Yyt0W000NLZ1006qZjtu
-iyP_v_X4eD8VlPg@d1GH80B_nJkXcHF00uTzDIitWAxFfZuM6ttWay910mMVsEX0W00uRVI0
-002qgQBrph2mW0WzdG2010OCapaaV8000Wy100azW700020001aN5LTl9wcsgGyk1ulieENm
-_40t30G0HR@a0iz1uElVYd5C000GM3002f0F0008HM_Gu@L00ewOzFgAyL5G040Z_72Gi2W0
-uQ95Aa00000GG08QcJC2004F2UploGr@R00usONhwMdt000A0NF420000G860d@VIiSLKaZt
-0e000060aFx3X_NHQk64Gt9no9Hmzy000O_Dhzg7t9000KfKAKqG@VJ_RPdpZ510W_Z@40Wt
-z_ygqtk1J9SInw6aGk4G0000G004NV23sdm8x6aMU5WV00gr@a7t3vu@7A@tWLvV8_S38000
-iDV2jp@GPuI000WH_00mWsdaOF3fJ4rzyR00GEfVPLoUmZiCYQ@@40Xd0SIu3DyLngur5Yl1
-00WPXD00qhD9pF_M0_6y@l100WtoUdaRhMgcDg000G20000001IwForSl1000G3aoWqxhu6V
-300m000WH8UCIMWDgpfD00G@xCxR000G8aYwIYt0XG20000280000Eq1OP7F0WG00I00uHnt
-Qns011000004000GJN00O_LFm000qcnU200000Ss4JR80W80Yz0lGyD0S93maiRaBN2RhL70
-A0000G2000me740KSy6G000000K00000WD0GTbxjnj100H0_@N20G015bZ700G40000U8000
-0000C398mV3sek20OC00020500WiZwU000uO900y@@6a100000000AyVspekzN500Vw@WKqs
-rR4HDCjXpGXu60MR0uGR9AJVZ1j9fny7MOhbzwPe3T3000mBC008k6Xo@lB00g@@QAnzsRSf
-uIjpg2eb2W36QPAiD0G004TTB7y72400000G0000eBxh550007_YKOud001000WFJ@Wg000G
-OxXhkilYa_J0uX0mLwsyc_3PFCpW@guJ00erVFYougy_L10mnvLUibFlD0Z3GUSaXZVJeXQ9
-Y2GYK0euGUx100WBQ00u3pA2es0W000nUdGK0Ri3HN00Ib30IY_xDeSy7Y2gYyWuv@VLc5_X
-dXt8A09o3GbR_@f8E3w0mXe0E9F0L_@@@vjF4O43mcLyixy@vM@@jt@ddFdW40050000m00u
-@V3w0m010O0f0G10G0G1000001800000m0W850Ag48Xa2SIW402Y09G00088I420001Y0H80
-816OA0K45m9pvJ5892019I200004aW0000W4H220HI0oK0e8AWJ2n@@@@dl6U302W0000000
-00500000W20N0amiyd00060000000XWX4h0KF1m@@CeU2085W72vCawvD0m30Guu90600uUS
-600080O00u@V6W0m0a2m3_0Q200000G017z5q40000V100df1PI16000e01WJVI1cH020eWI
-IE@N200zmZp9Amz3WXv5ARMm28rWdPHgvrP_xF400zaJfzVDrRisV2J0amZ@O0000sr00GV3
-dqQEI0002YeFXHwJOszD00SWbphYD_Z1Ol5W928SU_wETT908cZN58Ae97WZy1Bf0XmA00ay
-VNbjB400ci5KqAi4a0050ie0Ol_84F00WHPwg@5XIAGhatD0000oGD21QN0usCpIpW7A100x
-Zq528000q00b_o30WEY5Rv70G000W042008tmPGqCymU00uiSj00u1S9lG002SMLlkEoJef_
-4o_V3GZE0@RnMjxp000WB6k765sC000mt_h20W3ZywJRRiS0SC0iT4Xpgdm9PI000WnY00m4
-U8zg0IjnPm@j6004000GQr4XjaEN2PpLHAW94O899kX1100W40881H36ap0f3007IeIVYCy4
-tIttx100bcEWMwtkh01o04_F38001Me7I00W0Q200U8qffz@@@@C100mQU008yq40004S_m@
-@@d3807W@@J0008KI1Y20C0u@@910S4MJD33tQG39G2C01u@V60100cDdGpDv40004D200rE
-p0A40000811ltOePFaaMHBx75Ol0WnCO0O70mun@@@lD00wS_@NKG1A0ft9HHSRKWy3FoPsR
-zfzxSE00migr3ZLEhuCR9gxibGpPOIJ3wqaX6tDeyS90QZ00010wCqG0500CokGbhp0002eV
-5huhK9000WmQ00eUr4o6tWd_Jutq7W0G0CVg40140QUS6000004G0dVjY23b00GGMmu90001
-000G0000eeOJeH360004yc33fIQ0000YfDUOVVFohNYwKPOaSC0v@0iUV2l_l1O00Wgu1RUz
-A000100004c00mMuGcPF302000WLcy8gG1vp02G0Wvpdv3RF0UE0CjzFnCcGzwvG000Ot@A4
-0008W008RM3MzkeCFjX000002G00400Nopmou90902G80000WuG0400pZd3021WM_Duh_4Mw
-tWemX100WmuzI0040000011000GCC0PRBqkw9KdPBFucmEx600H0u@V60WG0008000884000
-0y2007k@3140WrTbOSzJgbsWBih0600040000W1000_qMSd70W0000046WtW8hVG100GUha0
-000w7v4caF1042000011m0Gy4Y1W8N00500yCVE004000W02000200Auy@miwp3nYB1004Ww
-eCmh00G@uvyiS20080wqt00G0080006Kb40010DDRGLp6W010u2t42WB120080_50004RY01
-0SbrSGW80200Q00002004WsoDuhl4_@F48200F0Sm@@L000mC0keI5812000W000AXF40G00
-001000005Bk16000Uxc1O000m0i300u6000000Wzi100WK18v@@Ao3m0o020O24100G44a09
-fJr20C3000000fT0_@leE1C8yHm_@F10900huA4020Xhen0400mpfOKAE3hQO0800000FEDX
-pGM@jyEi11@@GtuK1Uk1OLvVMTdXZtJ000GGTzIifi100800G00a7U5FenGNy602G000001I
-10WBcJuCpb8000sIl1vXdmsp6GG00O4S36b8XBxD0W00uauO00mWVWy4cH@XGZU8MQ90800i
-CT2xqd00080012000000G400000G00W00110002001406QB110G0010008012040100220G8
-WogD0014nTr600G00A0044004e02000000HL0CQj10840A@sWjfge@Q9ApdX3oD86R3YJtW_
-qD0008000W40200viP0004200800W020W0G000000a00000000140W0000W00G8001a0m@@6
-020400020004YDzD0c00GAD901008rZ42UdXhtPOm@4G000irD3O000ECrWhuC000Gpt@6G0
-008tK3g@tWwtJW00H000G00208@CM10W0008000W00080000mwRCU3UG7ZE@au5o4IdFXlw9
-fJI9kyN5G3A07e7oP_mq5e10400MHF1040W0001I18XWRDW802GrF60000fP@4Y28Xl_J000
-CED1000202fQnGuwOqoY1lYRpz46yN@6DMmmmzF00eZVyV6sF_XTuDe8UFUuNYlQJ00W000G
-002000n8y044GW9@bG020GleFaDQ20wV0M@@110007i@pR76040000W0Gd@604a1PeX40202
-ypl18040Y6nWfyJe303cS81W000000100003B020800KpT90006100GqnVL0110u@V9YzoWb
-1t8zg4MMsWFGC0100GNd9Kpl140H2UYyXr8J00WBTg9CK@V5LjE300I90G20TZQWI0000184
-G400eaI0820W4Y010000H00WID0O0W0820410K20000a100W00082000280410G40WYWn001
-00WAR0002000WK20000cGGe9Ib0020mu5CKAk4dVom@@6WG000140WW0mKYG000000100402
-0C000G0200K08Y180000W10002K85W40A040050W8W0GA090K0C00400500K0001000WT808
-G0000140000G02W10PdA1408eInzuDt7026m00700W0010000W4m0ZRP0fW00OK442020001
-W9YHG0W4410811G0S000a80100W0GmW1G112G004004003W000G0000100G002048W4000Me
-10NG0020WW10I8l9irh4d1Q0G00X@@D0500m@@CqQA3TwO000G00110001e010000W00W9G0
-8000GG4OW00H0AG000040G48e01020G0W008800001A104020600CG00100G0g0440G4080G
-120GG440000Wn000040KHX1008000Y02041OKO90010000381NI00L20G0Gb981020800W80
-W3W000WYWER8600_241W00K80G40uGIX00mLW394000N1H0GC0A40410TI8000a9m10200GY
-W80v1m0000M1HZ0840WP2W0Slk1e00000a4KlE300029000002eW002GbuI0000A1H3gGd10
-i00_700yFLL1UggoYOcf5XFJB2m@MaPcX90@30@XF5030VLB2W@N4ymJ50_7JP2FLH1yW@nC
-JCZPcM4pCj8p00000JL92W@1000Gb@y70000t@F6E6lnR0000y@@z000S000030K0J0l0c0C
-HC1OY00m41W2E205uD0AmFmL0JWx8@06H00kZ0e041G1O2W2u7m5mRmF2JWV400ceK0C005m
-4WBWfy0IG1000mLw80K0N00040E0K1O200e20m@@C0011000uHqv6u00006000003WNth0m4
-0GywQDgF3000rjU00y@lGJpR0400XNALfdsD00qF4RxFTSlHct6C2f100000081M2d1zDR04
-00gqyD00G20G00W0zDOnA3oZp00W04HFR0Wm3W_dVe9y4o1FXZ_DeXQ32axaDY89OFLIIrZ2
-pJ8tzDwu6ZVAD8IX4000GGG00G004mws64fG2008GpenW7rD8HU302008002enB300uqD@@3
-8040Ed@XPjP8GEL0040CJg1hZzmOS6CuE301G80808sJk450Q00000m41000000W40C3l100
-0Gk1@aynb8BS6W08000G20W8W00G04W200001G0080040010a0e0G80W008000G10A8_gX10
-8200G48G00020100KG10040000a00080040G08040000SA508G000008000G002442000080
-G0haBHRQ9KpU8@fR0010G08G0000000Wq4YV20W204094000040G00084WmyJWm00m@@6W00
-Wu8@4000G00110000000jh7mJ000G0484001C0NpBHKy6S3k4HgX108000004G0818004y_k
-1W008YxtWtQC00000W0W0YG0080000440020u11e000100080X@_R0200YC3C01000uC600G
-000GG8M4mWLgO8x1UYXxaFuDewz40009q6X4000uq100C4kJJqRGjh6Crl10G00W0a004100
-G02mAG6000GeqV3oYBXXzJ02200408WA@JW000006SB00100W306mv1G000XuHoQw9alh7jl
-@GYO9y@V20001YvN2000GvcR0ul5WZr_fy@70024iOF30480YrpWxwJ8Bk4kpA1W000nmPG1
-_IG0000000Bx10aEtPOi0X8WYW4_M2x_R0040441200IG008800200fRD300812000a0020G
-200022020G000000W21ODE3Iwt0Z400001000e@20WG0081mVCgSOeA8000000y002000200
-800m@@J003I00400I000roRmn@6G1288A_40020K3Y1d8R00p00K000a000Ujt00001000I2
-fGb8Ga0002W8000Af40W0001aI0004C120e40W0n4uC00c09b00I84G20G90004000WK20H0
-W40G9000W4AG0e4000100WIA1010000f4W00G4000A000W5g0W00001294000W400G4100a0
-G0e40000002GDpPGP@XK5_3a10G1004W00230Q01241080KH9mn0W0WWjED01A0Wm0W04G00
-05021010G10m090G0H0800001WG1G0G8G02P0OcK300mmLpf1O00500X0W00410W1ntx6a5d
-1C000cyF4G820x@d000u8K09WG0GG4G400020G001X3815WH0GW0W004mH820100W0W10G26
-011800G001mHG8Y08000GX83GG01m0mHW0E03101G4W000800W82W0W2G0A000KP51Mm0080
-002020YW00We0m4Fr33Wx1011WzhbW40000122G0000ZAma0008GG4GW0110800404440041
-500041020H680100400142IX00Y0GW48W0W10110amuJ0O0fmD_6000WbI0000Wg020W8400
-0ADrWpyJ8BE3_@76qP1n00mNW8043W200Y0G7BA000_2S9mbWY10H0GdDA400z2TIWOW0a98
-20Y18We0I0DM0C0Gz5210G0W00040qW6210eD000WbFKG080WzN84000020XG0032804el24
-00000k805TU8W100osz100GLXlbGkR600@N4pPkOuR9a0N2oSHLfwYCd2G2M40@b8y0qqV20
-Q900000Wg0000000Gs0WUzp100u@x@6aOP200000mH0e0l1G1S1k2y6S7n5uE20mT405e80A
-0N0KG2S6mFmF20WVKMS645W10k8kI1810e900WBm1WcWv0T0dH00g10000000ep0000N000k
-07080k3u2O410uE00027t080C0Xlv1082WPFau@@A0mFLiuV5Uk80YOFX2sV00GCJ@_600uv
-Y700mrtKDWB33@RGdl9aX53V0520000WgD0bv9HSyy0080yUV3W080Cll100G00008908009
-00mcn60G80PPV3A0t0808022000G000020CFS9000WuL10000Wa000004002010WG02y@F30
-G20ATVckfVuqU3000020G0ekR66f@400ISvdlnHlp00009s930G00_cl1RRRW08040W0GrxR
-00W0402000W80cws00W0W0W20_PoWLrJOWV36Wt0WIC20000WX0000040024002WWQXQ9dvD
-A8r008WWxzN100GmGVD0W000005G00WW400100W8qdC30408001G0000aB00000G02002t8R
-GwRLK7c7FL@010040200G104400004K0500000005002G0GW0000W00XG100004W8aN0C00W
-W0G008AW00000010G0204808W00Gu11W00000G800W8048000m4D4W00e010000800M80000
-G03404W0WEyD0204G204CYl1pjdGpzU4yk10W00G1002008u6S30800Eel100W0180000201
-W00H5y6020000L110002010002000000200W100240000W20e0G2G100WWF0010I00008000
-e0PyR0140acuJOsT3kTAXQf8PTU30100W00004G0LRm6yYh1xuQmlz60010004A000K0G00W
-0W000012009004C4001000M01VAPmiy600872100008H0000800K2G000W0208o_4G000KYO
-2ZYZHxGXaKV2HhP00W000G140W4000G00WKW00W010024W008W400dasWYqCWG02000WWjxD
-0Gd2mTz6ysl1W000110GiJj1xMHoUvLK5U2tfd0YI0W4zP00002G01001200420g2q0e4000
-1W80200WWW0HW000200W98C00W0100OA50W0o8W08000K1i10GG20m00aoS83yHICbC0004X
-100000080W000081_yFX_@DuvV30G010WWW0010OX66izP200sMNgXXE@DeDQFI4t30002vu
-nGozCShU2joR0040YVsD0G01000004WG004W8010002002aG0G3z6iwe1WwT0YztWGZVOR_S
-0W0YK0U2XzRm6y6020002004W0000020054088800501G8000e01G031W803aH02LXa025g0
-GA0W06800424001W0H002H00005q0W4A2W0K004020G0000200620e0ewNt0002mFtUiCV2Z
-mPWf0200002g004KC0020000080200Y1002A00G904442601W01000G040G080400G1100n0
-A631080KI00W000100024000mo600004G1G8G80f3Q0I0008X009Xx100020e00WG00_@l20
-W800G9b0000024L210014b0W4tC8yR30WI00I00000e4080We0C00c14b000800GPlP0WLI9
-0008400X02000040WI0008L2000W02G9X8200000K2a0000004A10000000W204cF64e4IW0
-00W010uNnAo1t0P1GOCW0We0060K088nj40W0AW0000090008G480009WR00oW008208420G
-W8020020140004010mG00W004004000WMkA000G084m0000004210SVJ800WW00080mW0000
-GGqzLO08YWY800OA80G0W30eW203W0WdW005000600G1G0G0WW00m8800c04O0GYG00EWOO0
-20W0GXX100800J0020a00G00y0K00008K0G000K10W9040005EE0OG0G089e8Y10000O2000
-K02G000oVAXkzt0G10G6@L008100K240W088042088080Y00208W5G100402G0Y802AH000Y
-SDe1Wg00tPr00020AG4088WH0WA0Y00W0H00WpRD088GW0000GI3G0100G200jYl1W0HGkrt
-WrwJ87SCsdaXtzP00qP2210GlW80HWRG2S6W21050iR2X00S0008420AO3XWWzNeW5W30sVH
-800E0804X005MW0GOtBKO3m1WLl84004031WG0WIJ848e@2000UrIfB050czY000C0O48210
-AeXGWm_B8G2WVIr30Gu10000q000aol4HWR0ufILgYPc_7ymj8uXBH00uyV300ei300gUhz4
-IEp00hE0000@e20000000Y0W8y3000W8000CCx_F100N60F00000000CG4_00Ges2100EA1E
-30U1Ud0N2Au00YTp00uDmAmFmT00Wx000m1000l100S1E0y6y3m5u7a2G2000@0E0O0i3y3u
-d00mF000000WvuJ000S100y3O0uDmFmFWR000@000m00009181UC8800G4F200F4GHuj0000
-2G0000yra7@J00Wo_NS6000O70000tT00W6V00bz0u@@Gm@@XGy00eg30WWyDm8L7WxE0000
-0W000G1A0WaJTH7SPmmlL4Rc1b@Ani@Cay@300e@R2_XXzDeLn4gtcaI_V00W02AH00m0400
-4G001W00G0WwbV30800zTk10080100020e0us63oxc100201HRGog6CUk1W6A0clpWjaJeuO
-6gttWk2W10048000uiaVuEv4_u@XuTz00W00000UZ200R9CpCyU0KGGwzN3008G0080e5I3k
-6s0W004DxP0010AW080ldRmk260001000080W100040VHm000ZapkDOBz4oMmWRvP0W01G0j
-g0000400A40100W0284400G000040G40002800aD_D020G20008W4W0nrR00008XA0200020
-0K0002e200W00900000040G06SF10C708100YWt00200000100WG00100W0G01000W000000
-0H004I028u903YjN2080090d000W00C80204050010WG442W0W0020WW00c1a000A00aeqmG
-021e00G1m2G0HeW8W8W0K98HC300e201084920010304IKO4001WAP01000eC214G10G0000
-03T024OK19u00C0200G20ZI5e654C000m01G00m0C440428kAd105G00081O200G0X0XG140
-0480050GcHq00044080018000W02H0000W0G0K101008WG2E2Clc1K00W0iW002004We0002
-122101O0O45W4022004018C10481G00801W1002GO4WH0080182LG000005201K00O00000K
-408465G8X0W40100G00144042C610020004W40G00G4jl1400H8480002O000G020Y800024
-000kNt000010a0080001020W0G8010WZ2AC01008100G200401001WY00008200m21644002
-0020e000I0W0G0WWW201091H1100W8081080G10G10g80000200802GUlt000000J8G0200U
-dj1W800WQ0o0500002029010022W8201040mG00XX0G00100YQpD00G0200040030tvRmqT6
-a_l1800000G8_zk1vUb01W00000Y00100W000G01fEU3G000G4000000Ioy6001920008G00
-10802nypGux60H00yti4s_t010000W4008Y000000Q00000W4W80OG8G044W0aH9900WW00C
-00W80G2100Y0W012007OO00004G0C0000000Ge10W8W00000G00W40020300114000200040
-W48G00900B80cjtWY_D00J24000O04W000821840000G2940004m8W0G0010000X00W40H81
-A2010m__DuI03kMV3G400ttp0000aCxCuz@4A@pWjnJOhU308W0z2P2lxR0040W6@J0Gd3GO
-_9000W080580W0WCZD00200280006000010W0W0igV2HsBntrC004000Y0m7@C04000G00Gt
-e60W108iV3000411000400000800420G0000040shl1Zid002000W00000e89W9CgT2TZQ00
-G4WBnC0O00nOS600W4OdV304104Dy65iR0285WKaDWW004418GO002240010g4218W12W0W0
-140G02K00G28022001008000a600H0X0GGK8W8C0012G100Z1G10024W000400C000210000
-TCG66404W0000OG4W0G641Gn802eaGA8300200K10eK00g21AW004XGP810AW0001100200m
-00G0mKuF4qG2000W40YY8A440Y0404900000800OGwft0100WW02200W0GG50401010Z0082
-802K00110090CW128000242808Y20W0W800Wm0100Wemu@60KR0000I00X00G40W00000We0
-0229G08G00GcA00006840WWWGe2c12B0G104010002TrdmVcCSOV20808400G000WWI01000
-8G0e410WWe40401G0W000e4WW4H084WK2000G0000b08MS302Y08XGKgo23I1m00f40G4049
-WI000CZG00e4000Ch0049aR0400H0e4a00W0009A1000002e4b000000WK20210W080b0080
-000KGXnyDG900GCSC00200025Ihx900W801Y050W1040400044001o0Wm00m4G00C00OG010
-G11W900Y0500e0002880600X8Y00e0WX1418W802A00X040W10m04G00A00GH0040000xK00
-0e00G2G002003841Ae000100G00nob008W0A0W0W000I1mW6@DODV3YXZ10100m00W0000G0
-4W04m2e8W0000ZW0W0000GO90GK12600e00GW0o4W408G001W0CW0H1046G8M0800440O0K1
-009C4W08e4i0m200L0006GW0C0802004Xe5He0211000w40mH4001Y008G0W862011G04G88
-067e000WG0220008008O06G20GK0XK0i10e000048_rx3L_R04404H006002040048I40000
-000HG4e008G048180G0BG440081W80840Le0W00GY011400200Y0n0080W0G40X2gar0G000
-040H000W08g4G208mZg6uv410400088G8G000GX08X4100X2500001X0W20GY50044H088e0
-H00f02G8_9G080eWMC020102I010al2W00S0HC8G20g8H00WLJW3140GOu6e00GCCS3y2TMW
-OW0CMy4GdD5300V1T2GOYu60W408MS30uB000Ot3TsGS2v6GW21WW0G3R8648@25y0S8YbBX
-ivCmB4O00100D0001@R00A0000G2@@p0W0W250000j1000000WVK10000lEwV0000egg5I4F
-10yFLgYPCbvYOAp5PMuBoCcN40@3E0_dggmCuXRHggoYCNLsu6WAuX70_pCCpSHKLrYO6000
-ziP6EU2egA0XPc920J0ecU3yJ50uk300c020C30Z3aL105000u200e3mXlPW300O51G1XXR0
-k0kWmmh8HS6K0N0a8k1AoFmp6t00000ix80KWt0aD73nozGsS600060008Osj60a141000GC
-SC00C000G0E30e5200063Ww530000r10000W90000udA0uBL0mT7004ndV0hE00eYs_DmF00
-mOt6m@@zZAu3eg308P70Y65WTj00JuBp18GE600KW000kp100000mV@300O7ei500000G100
-00W0kx00yr4W8U0vk300CG000c0W@@3000WlfxZ10mCWbtUuRx4omrW_jDOJU6oytWeYJ000
-2nS09KOC301U0628XAvgOspAYtt3G000G0280W4000W0000XGHu602W0000440000010W002
-004W0SBU2000802406Uc10000ZZA100400160000GnH80uMS3008004G00801PNQ6000020G
-0q7U9CYc1NPdmj_C4sS2BtToqj9qtF3X_Rmf@I080000Wpr_y9iWk1p@Rm@@LyCd7Rcp0022
-4010A000O000G110000001H01A000Ge00WAooWorD0GG0oOS608800W00OTq60G0Xe4V3000
-G088040000055WYqD00W0200420014W00Godt0G00G9kRmDWCKrT2zqdmmw9ajl10G2000W0
-W103080488008000f042G4A0WW10028O1q_36008240G4GdT60A80G00H0K08WGHD0W00020
-6WJXDe0V3000GvT00O4S34280S5k1@WR0200G0e019PQ004W0008Y610000W00G0WWW00Y00
-0G0AA0400102G0W0006WG00010200040WG08OX00HG15W002034WR1J0W00CGH14800020K0
-W1W0200bI018CG01K18W00GGG9201GO80M9080G050e42000400WeWGG402002AG85000roA
-1840iK000a00Gm0aH0b40WaeG0K6W28m032044Wgee002Z08C8KOG810096W0X4WC80B0000
-0825200G8Yq1j1000001C02m0040O0800bO00Wm02B800eWGG0108W00W140WW000XA002e1
-34040C0W0W0000XAX00A000CG0WG0000W42O0K10iE14R014080210G0Y0880000G00I000O
-YK1020GYW008GGW02840WO0082G0I001004X0801W00400000H00181880C0100003021110
-2000a4W0000W00G00022100m000W010200004010023100WW0W4000880020000100W00OW0
-02m88080001000Y4004WH000A02G0C048002O8Y2G0022W0000G010588020010000e00800
-G802WG080004r31040GG0000200110H0200Y0G10860G0980104I0r8m00Gg02WAYW0034G3
-C02Y0WG80W820041014WG6A480004W00W0008052G02W010H044WY010G400W0400000139Q
-00W02G2100100G4000G80G0Wan9U6aml120000001004W00242001WsxD8DF3W0WGW300000
-mbm0G00W008m0G00240020GG0Y0310G4I0000000801001001m000002040a00010C196ie1
-20G00aW00500ugC3UEo0G000W0G00I0000009oV300022G0e4041mc_6G00000H0e0WG000X
-0vIRmty908100808mz@6C@I2vMRWXm10cXW8004W00W1000101K00000001010002804200W
-21000202HaW_DWGI0000000W84040040080004000W0H000000600010WW2GC00u2c404400
-0880G040008000090100X0W0C533DpRG5X64EN20084A_FXeFC00008w1000184G00800WK0
-G00Qyy40202020eOzJ308009G20H0e00000iTwDexg40200ySd1WK080000821286_7kmt02
-0G8GG0m0001K2b10800oaZXjkD0000809002000400000002G80vZF300O2DjW1010200G00
-2W00G00102a00G9W4060Mst000W000800G81GGG0000000GWYBoD0080qx@6W20G3W04GB@6
-0008I800000081G4G0G40848304G01GW622GK4020G02HXW2040G001208000100G80HTQ00
-4104G506WAGm00We60400004002002KG24eX18000qdb2IY8WGb26AW16WG04GOW4XA0HG08
-0aW0E0Y21W00eW000406e0Ym200OG09XGGLaG0002E2I8G5HKWI4k0G010O18200001C1W06
-1WK80e00821W4GG82x_t0002000K2007280116GG8aG9K00084Y0a0C31GW6W00300WW00W3
-@D04048000O080Wv@P0010040200G200008000WNl0GX01508G0C010M0CWX00CG02q0C0dG
-G0GA20H5XGeWO0OW0W2400W9H1aI8XG60WWAm4W0G0uSU305Y000W000331G140Y2080142K
-J4G004100Xe0X0000004K20810c880b8400002KI9Y000G805O200020OWI4000002Af4000
-0WeXI0WG08Y0We40G0000YIK2I00004H900000120K2000Wx0000000AH98100020b820000
-0GG901000W5bK2W00001Gf1@DWI0000009A9aP0000100Y00C0408g4I00WzyCe8d4Ibp000
-06d1Q0000128008004000GW02000085O108004GQ4220820000801Y00080G40W80004Y5d1
-00010G400X00W0000qx1010000I01haO00K010e0880Y20000W02q00001580200W8003200
-000WW80300m1@680800044440801002d@R0H0G000X08m8012200004000K001M04W10Q051
-G00Y3GM4XWO4A0E00108Wu82W0WS1OEG06WWWi2G3028000W2G_et003840004W1m0m9Y140
-8C001e8000yYQ0O02441M00W0WM02Y00C1O08000O0G0908W5W50202Y4W320W40mWH8N004
-07AYe00000GC2m2O0E41W0iGR28010WGW1W800014WOnz60002420W0008K00GG012W0A08q
-he1080080202e40109G000eWiED000W8001200Y5I400G01M000W008000404W0H2011000y
-700040G210W41H200G2H40G2801060480001441840009808C00G2404W0KA810404Y84002
-092Wafl1W400001041W120200000Y40e09000GR0800E0840W005sWGG8tBKO3W10Sl04006
-021Y00W0R8488z2AC1K0m_B420G10XWG80eW140IYuF4Bk1U1000LxKm6m10vl04007042YG
-0W2Rm98ix5AC1e0GUg06aGk101zNG19W21sVXG000884400008XIG0qA4MUZ1FiR00W00002
-uM1000000udA0G5@u7LOITZ10000Wli10lQ40KWpwEXl0000uk3vIBHOu6C203KHT0Y5t000
-0WGm4000W00Ksz5mgxE700815000000KT0@e2005e0wl@100u3Or200g40YW0000K0g@FG1b
-TSt@1FaRWx00000000uB0u@@_oa@fIt1ml@3WT6000m000e3u0mRG7WEWVGEu6000q400e3m
-1GJWVWV0T0023t00m500mFm10NW76_3Pln0000000AIvYR0T07W4uI8G03I58XK0O00_1E0m
-0S7e3W200mT0008000WW000Cy00K1O0C3u200u6SES20700gwd1tT00EuE0000k3yO0000uE
-m1e_F@D000yb900WK@V008YF0000G4H0d@R0Oc9R1W@@0uk304mg300y7WL70yxF0y30000m
-0yr4W30000cL0GhV6u200cw1Sd3i3Hu3H4@@p00W7600Axyr4p0000Wgw3m@0000W0WFeDeq
-iGYXxXOKD8tV9CF0042t6PXJoWvF0G9000G008W0Wc_D00G080X01G080LkQ080020050fIR
-GhN6ivl1W10e008G0G00O5R30X40aWk10C0000ur5_V2l2O0004aMpD0WG0GMs6yeU2n@Rmm
-P9K8f1bgp0011G000W020GkcbXImb8Ik7oCdX9EPuu@40sc049U5dh3Jnk9Kkj1018GQMt00
-008W00WW0G0saa10040020010G04800uCJ6Czj1fnR0GW0808A000001081y8l10021000Gg
-J008TU3oht0010W@oR0804awsD0000ngx6CmT2txR0GW0W5_DeRS3_Rt0G000XrP042000m0
-0000000I8W440uTS3000We80083G3Ekt04101bBR0WeGXPaD02800210WzQCuyU300eJ1400
-008801201008008GKoUs00WG0K11KK0M00GO0G4W2W0GW008000AaY000000aKG80m400001
-040080WICsWFbD00WW000G14WW026a000382KQ004W28025410090G48828500H0X00K04H0
-446W00040028W0GO20AW449KK84000213XGC8W2010m8W02I2804Y29802H00000UP011WGA
-K41G815e004GW88012AG18g058W14000mG0H0000020WW28000I014X02feX6410WW04G010
-W010W04020e00GG188406001WW2000000GC080mH1n00012Y0o0020084CJ030010W1CG105
-00oeY00K0840028000typ0a800WO2GCK4S00W8091000YA008m408Y8C010024G008000006
-r052W05600G80O00000W5G1018G0000uGW47088L24000500400WGW800200GGG101220441
-0003000W08W04WW00000G0220G800000W10WsQm0810000120Y8000005G000e0000200001
-8sPt00G00m280Ets021240G200G00080O040200n220002tbO00GI00218040000SK000004
-GC82e01m014WW04018W0G1r00008WG000A49W00044CG0K00001218A2A151e810K4C4G120
-0G00000208W200011800C0K1k1X@d010000202@DBH306SjT2m000ImE10180JfR0W000014
-0HYR00000G0c0mW00805002000100140WH00050021006J01W4481W0W00480140m2008W0z
-kl10G24002002050000G9s6001010820cn00200080W0004020002404GN@Fqro3nwQGYo90
-W0600W4000GeaYC00080000aZzDmx09Gz560111K020040080G0000c0044080021000100G
-001190004480G04W4001200W8001G00000G0400000G81H040GG0a0000086NtWIFC8_V3ku
-rWlkJeLT3W1000Wm2evV30008ClX1FzRG70C0W400001000EZVtDW00090G0G001002080W4
-0KGk1080a000412W1G040040004040G00G00WWa_k1010WX014C1k10040080aqzj10W200G
-G04eG51lR0880WqnJOnM6MqnWrBJ08G0000G080000uR0MoqWhmD0600010002140W010014
-000W0W10000000G00Y0018GW002Y0W0020080a280203aR08G0WGvD0000Mvm60100i7P3E8
-qWnpD8US30G0000W00211010G02000DwRmpy6800240WW0001A000402WG02G2100AP6V382
-Y4108K2008015Q088018OG1G0452q8208A18WmW3050eKGmH1a4G84250900800G0O00WWf8
-005000240GG0M1YY08C012002141G8I0G6422820Y0G0o2000H010Y0aud1060010W0090Gu
-8V300WG000G68G1005110m40XCR00000882W240G003018W8ioB30000XL20000U10mW8808
-HG4OG008024K128G12b01121O504X010GQ0Y206A08XWAH28XQ48UeIXAYW0d0A0W1Y04B98
-020WG0W010W0B0Oq02m0W2996S00400H0000G04bK200We02I900002qi4e4800W8IXIA190
-G422f4000G0PM8A1000G4Ge0b00086G9K200003c14b0000410KI9000Y0e4b08001G4GWI0
-000W4002G0IG9b000002HK2H0400824A1Y00000eaI00WG0W8A100H00Y0YI0O0000CAH908
-000005010000a0G92120000WKgtV342088102W2Y0000204G000m0G031A0008PMS30A04W0
-00W10X12K000G000W05000W2008000O0G0a000004200GW2000GH014000C000IWCK002K40
-4000W0h00000104GW25zd002W02000noP000004e04e000GA100000084G05020YG8020000
-9000204ALE3c_t0AW800G10O014Z0u00286422m84445091B01GKWb0G00OHWW0043OXX028
-_0u5G8AHH1G100e8G05106iW00887Hu2200JW82WH00024006WQ00mC150w0401000mQ0098
-GW040m41000kG0040E0W0GKC509G2W188e002G0808W011H040WIG00rWI8G4JWO4F05G830
-4Y4V_R00O02000W0K00Y_t04G0G802W00a0G08W2A000G204W000280G09KW02001a001000
-090W00008W08IiZi18G000528000009M60I0000Gn10G200G0OHW001b0GW000006U00GGeG
-20000A49UZ4W00W0IW0aWG1001028g00I20001GI0XHa004G90W00002200G08YW8qlk1ZxR
-002W00Z080002055paxc148004ZG0Wo00GCe@2A3G41m_B420HI181i@2b2Ga0GQ3010H200
-H8KA09Ga8OFAW7000mHPA99G03YXp0KO150XzNGXDW30sVXG0080864010bCXHG0_BKm4G50
-vl04000142200W8Im880v5A00081SUt60400044G00GCXskt000h_3wFuk30O5E6000@e20G
-4_00Cr100m3KspkR000HNg00mK7000WV_xV00m@G4l0ukV1uF0000040mg3W@V40KzF00800
-MT0yNL00Ax0G4c10mgxtqS9ex0yt@0000e2O0300u1ei50UuH9UE000uj85mFWBWc0@4@0_9
-H2yJYa0d491yEI2u7u4mRmJ1u1w0k0y6qHY2O320000YvJ0f0U300y3u0uTYSF00@070K1k3
-q1Sd00u9YR0d100s1E0K4y3e3W100mF2004000mO0006040g0S1g0m000e32W0C100eI0KLL
-V1m@0mVcfIL11km3YPL540_F8cnCL0uVm3F5W7G5pC3ymL5LL540yF8gMLGW7_WmCpK1W@nK
-cCJbg22JP64p00008NL11Uu3W@@J5WL7GL30W2C000000ew0yt@1Wl@14Og3@@m7mg50WLB0
-4hM0_@F000GK@rt0G5@1Hy10x@30@v70@@F0WoEukx0Waz@G8_0ut@1mUbQCqrU5T8zGO@6K
-5U2zzdGju90089PnQF0G004Sz99yR0000I0020l@O0O00e5pPepS3020W0000fs830840aag
-1zzR0W000020WW00W6TBXK@D0yC3Gau6aQU25tn0800WcED8vx7_8tWKxh00m0m4uFS3_3Bp
-oGZwISnc1Fqo0000Sk200LWl100WW8wOeQVI008024G024002006W_sVe8T308000G00zRT3
-ID8XbRD8B_402W008W08u0300W6MTl1W00OEFtWCTPeaN3oG8XnuPOXF3oil28W000510W04
-0Wu000GG000020H000000W00450WWA00000W20WS_J005G440402488W2W00540aFb1phaGg
-o60EnH8NS3UPt00YG0000050GW0042001084mW40WG0000012014ci12010W008ark108000
-0800842G0020000880040840WW002K000W50200500030040X0280G6W0WGW0A0W00012GA4
-0H00D208G000W020X08010e0G4G51020G4001HG0G11KW88X40eQ001W21W04WY82000I010
-8044I48e4G4085W408400Ka0808Y80002034204WaK8GW00GC880404014G06G14W028I004
-a0204G00QwtWe1D00W0000W00008G0XG0048GX004m020W006048K003410014_d1G0Ga00o
-0aEj1000W4CWC0800062Y0WG44300Y000W1G80A0KG002004W2000K0GCG0004s11011G1GC
-0G0G0W40G0W00008244G2I00050A0O0KWOcb0W40WG0e002000GG00GWI00800W041aZF3G0
-0000400m00001W40240011002800100G840y0D3008G000X200g002c20G0000XO004Gqne1
-00G1WA4008Q008000W1W4800We00G0040270000K0nz_60Sg00000880060W0GW0800b080A
-0W000210G000280G08000W0000Y200101010W03G008G0K40088W0014mrt60A40K0G0mW79
-008G040810220G00002080W10008W0040m3_C0PG0WG00mQN60G800WW81G8GG00W0004004
-WO00G0unM3cEq0000Kc343A_t000c004080001W8800110GS_900G0W022mddCKn26jxR010
-qeKoD008100000W100800001W0G001eF13Ufp00040W02W020000c1evV3G2W000Y08m@4G0
-G418002W000022000OG00W0k@t000GGG008c9m0aW021tPG9eIyEW1@YY100W01010W400wr
-BXqpD8mV30020CmP20020l_t0100W002040400200G0G0mXR600000W800G000mKD0010088
-000a0G000O4020XpsD0011mUy6qul100G1VELYhRm0002a400XuqDeWz4kYB100G0000YW10
-0Cpk10120000G00011080nDW9a3X100G000H00000oq000002XAsD00G81010210400a4004
-40048084x4_IF10G10TcR000WXG4IOJT68W0rW0YB0G00004100020G400W200G0G0GG0000
-041000204W101Y030070e000014406Ae0aA8m2W0W5610W0208u00G02WG048014H08004Y0
-200W1R060W088C014aWH40WAIL258aP080LK2OG18n4Ym0000G10010G020nb8o0000G040Y
-HaYXG00880g0O540W8900008280G1W00B00W4010G004W008006G100O0G000004KW00WWG0
-00G0W08a022W020O180028000004004000eG0Y0G000003i0GK40450004008G08W0020gGt
-0280A004G080IX00200C40000nntP001000100C410f2L10000Afa800001WI0000GK0We4G
-W0W4tCOrR30001axj10G9bG000G01K2008mxE646U2WG9Y0000G00K20001r1000002HYRmA
-u6000K2001Gq0600H0WI000G80WmmDusV3000Aqah7fVR00CH140000m0G001241E30000e0
-80Epk18W0n000W0424Pps423t0000WBlP0080000Ye0W000014W05000A002000000X0W000
-9004_M2RvRG_4F0040OEuA000Y010006G000G200n044W0441GG040O0G113000008e8400W
-G142m0e0W1W0odX600081180001W0G13HO00801eW8A010400C002BW04422000TP020G44A
-80CW2P0H0210m8Q08880E88002Y801C8X0W0e900G0aG1090PtV6000014002A10mlnL0Gi0
-W4GX00G0011402340W0W2000e0G04HiY601H2000080e4800W00010W0200H0X20100H0200
-600008058G00Ga80Y400K0GndNC0N8080H048Y0W08441008001800W4W88H00002@4RW00A
-G08820K00Y_t0001GpyQ04H1aPah82S3840030A19ox4ISp000A2844X005cWGGOtBKO0010
-Sl040070A0YG0W29008iRIsR640d1PZR0oV1000knvYRG2S6080eW1402mVXYmmJ0nW840em
-2402wU1006yE100008G202WG20000000J00eW0WdBYltT0xk0WehPupw7000@e200e103E3F
-10S7SjNB1WP3WmgJ000C1tT00_Q20_o1000W1udAS7000Xu10WbhQ92y4Yy_XOtC0NWVGut9
-000m000WHsR90u208xj40WtWx0T0FRS3000Gug3082y4S06W76k4XZRmLw9000a40000G60W
-gjnW30yZA0000uE0FWB10_f200m4FhRWl000tT00_f2000y00W60000uE70exZqDm400Cr10
-0J00000mg5mN000Og9UT3mklW2K00W@0000W8U1eF000Hy1mT700GPVA03sSd1i@F0000krV
-00a86CZ14pXy90T00Q1jAE8udDjJO0z4cgt0H000WC000800SlM23eRGDn64YU25tp000MH0
-810BflHCACaqT27AOp1Ud4sk4Wt30MRWgQuJ000HIx@C00I000WIm9y6SZj1XmP0008WoqDO
-219000mWI0GA1_DwsxXYp9PPG3k2tWezJ001WoKJ6G01100000L0000008VyR000HG00W2nl
-P0000eBwC8gV30W0100G0000ZMT@90051OBS3UVcXBVD00800400ai7E102G0G8G0a800890
-1C000G0100001800044008404G08W1X00000090H00400014041820102W0YI0800O840800
-00010202W0W4G0WI480004000Wt90Y_t0e000000G4WW00O101908000GedOD0004000WW7q
-DuSVI0001014W0W041008G3101VjR08000141000200044202H00C0G@@9020W2W20261K00
-W804WG00000ayi1040205W000001000cm100100000090001000K000GIXM900C0G002Gq06
-GW000GW0Gdzdymd1JlRGfy60e0020100020O4028NWPW0G04GW0020104024000000u00000
-100GG02004000qPk1GW440G0000eEeOB608011080uB4348000000G100GrpCSxn94110Yky
-1W003HIm0004mhkPuEw44004Czl40MN0sRqZuGQf_V30G0WqmX4N4PmYuCyef1JWQm0_6028
-04W0W0001WYzD00200010000GuE600Etq00200Ffdm60600W0S8z4oHPc6@DOvECMqy10900
-X8y00W0WZnD00GATN66Clv3f0aGb9CqGA95hRGVd9qcm39nd0I000008040000002rTk1tsR
-GGD9KWk1HeR0WS7WbvJuM138W0I45e1P1ymldjK1F3202000002021umX4olt00120000GQ_
-q00201W00808050421uOT30800001008000000A9006fIc0100WrvD08e00040WHsD8I1O08
-0001EGu_V308204MV22210UtF1004Y0401g9n0400X000002Y0W0G004W00080002000W000
-0G0K_X100SsR3C10G0001008C12G200W402Ghj6WA0000008200ulPL100850KI941WG882b
-08800X40X2X000420Af40WIg01hI4000O0YGe400GA20WIKY8b00a5G9080W8200K2008500
-G9bGaG0824K20W0W0W00A1000QfG0WG000bK21A1W4aG94G0cAHA0e408a5W140080WI4000
-HW800qr3jW02000O04G90220W0BgR0C0W040000161G0G0001D004e000140G010W0082e40
-051W10002001W0008W0HW10WA020W00W901W0000ae100W100W020210G8G908020WXnP000
-a0400808CeG0G0001086iA_Yk2402801Zu40m200W0320O0G2W800m1WYG001H18YY2q44O8
-G61310W4YW26W118W0GY04001I8M0We0W801WO10G0OG00C1Wl0ZW0400080GIW1G000mgWI
-O112G06W0G44C0IGW0M8W0A02CG6400140K0002Y441000A0G040mBkd0002ixV38040Ga40
-02012800002K1W4f281000210GG080410C900a0048108I200a002040081W80e000000a80
-04126000W220000940808000068G00G25G44080100180000a0am01a100A1W4200GW48G44
-100000PkNL00b1a3k1480043G0Wo00G4WsGOuC090eM0141MVXUaOG00y5410n0eG0G40qPX
-Y00GlGd98400z2Y0WG0A40820wCe000uB0008aBTUWO00qB820Y1e00W80epc2p28X01C0W0
-G3900aMmD88CX000@30000cPk00gQH0y@YW7Ug0m@KfAc1W@B20@NavK0C0yK1FufgA@JLLM
-aggi80000eOBBW4yF0_3UggoY0ul5XlABgggMaPcH50@30@10LLbOYqg000E97S30k0Q2yJa
-1ud49G69ommbmPHUWpWy0U3G1y3y2uDu7XBmF20WV40Au80K0N0e0@0U1Sb2G2A0000sk71W
-2y605m5mBmRWVaVP1yW2y6S7X0uE20WBpu4000008pWegg1XPcn40@JbgW7SX740yF8ubPG0
-u@WKbgOoCc1mVg2W@220@5agXB8LL50000m@fYgsV0Yu3GNxFmI00epT9IxhY9ukgrL3sl_X
-nnP00W_H2THTMk11yRmit60X80upy4ojAXLosOly70pH0al39RwbMRVcbYk1zmRGWv60W04Q
-zz4AmBX7oVOFq7clqWB@D00GULsIayKWD4020EMlYKYV0080082AW_gU80V60GA0KBQ2hsRm
-rV6K4V2p@9HrzIycF3toR01000008004400Y0080G0OFF302e00W0818102W000W0O0000H0
-0000410OLV30G000000X0020520X0ZVGs00Gw2RyqHElzR0000200010402g@F1201440200
-80GiqS2000400029000m00000040W0004W00kVd100UFb6zGa2XK5e7d@R04200000840888
-001iYT200Ges5FXtvDGW0000W0100000C006_F10C00lt@0uR4WC_VO6iGAgebmas0001001
-0W3@Deb46__@1000Kg304QwyA9000Vzd00G0Xw_J000WIHo6ifl1P@RGTA60008OyV300O0K
-zV20OylZ45iosQfmx4AJd1Wv10Rd2M6@60WG0egR3ATF12200pdA1800001G0Xu_Wj00WttV
-00Y0GE18X0000104GZu68410Ooq40001iSk1Pkm00W000m0000280040izE300cBUv3Za7Gg
-2U3Mic10e0000A000101021vC_4m0000800u0T3W0000K00uG@40190ib@35zW4400WE@DuD
-S3WGG0H80000400b000000YWG100000005K200000WG90000CZ00e4080000X2AHKm2FWV00
-e0y7oqHYtUo14A0004XWYFD004m05000062100040W10Sml1VxR0W80WEFDuDy4Eyd1002qf
-cqoMpg00O0000002E200m020G010c00060G008W020G0UW00e00W8800X001020060Gm8000
-3GG01m0G6zLW1Hy_0Wo0WFUVOrOa0WG0a7i10200WGX0090000008008840000G40E@t00W8
-0G004000400W0y929IS91B2005gp0000ah@DuVvY040mW0200ehG910408RY000K0008010A
-C1X0Gg6em4020eQ080080420W0076G0G0@5KO0W00q60400yyE300ClGW00M@U24000000W0
-9H0O8wb0qI10WP2u3T3000KbrU2XXRGJ@F004HCkV90pS04CZM003WH40Wv000m9000C000C
-160u2O283u700G68CS3000o0S0m083WHYuC0080VxR6000G1_108Ye400J00000kCZYAvF10
-0WgjehYg3WT@300xz@00WWqloaE68LY5Ya8QV8LaA000meN00eGTUUZxs85o9rMCYKudfnt8
-XS3IX9aEt310002w00Wkylg3N3W002Kql1LgPG3x6yCl1nvRGwy6G0020088ma_L00uXCDvA
-6QgeAzPu@V3000Oinl4LnRmq@R0cG1Om_hYXsWX@J0014mt_FaMD300100004S403f@d0000
-S5200frNnjG8DSXG00clJyCgjyDeOy72@EXf@J8506YvcX1ZbG4U1mdeKT_C3px1Jb@F000W
-px00GZ2Kzck10004400WCJA3lPRGktCKzT800k73RrfMlDuw_40W00EVV2XVR0001W6xD850
-6sUp30y60VwHLkt600040080GHs9G000uGV3001045m3r9oGoyICax357B481G9000G02WI0
-WC0G90040800002oK0C0080W800eYwC85W7spF1000GlV@000IYSUT200e008000G0100G00
-404G4D0GHX00200WK0CGH00A08G400W10002Y2m040G0f0OGwz90028W8000Y00Wn@J0GI3m
-JmH12000K00080007400E0010W80900W00G22G00A000101W1000400OA00G000GGK00XWrl
-d0W8000100zf@0000SN200D7xa010200048088000010H0200a00W8000100GG0004400W00
-082000200680W00GQKrWWzC0Y00GjQ6yb@300_EYOs9000S0W000e8820Y1G00W80eJ2100W
-C1E0I1m040G000H0070100059506080m00000W0010000WB2GV6@0Ga5WjeTA2S3mCpK1W@n
-Kc@3kmN4JPk80vWdW@1FSmJLLM4pCj8yL56U2mCJ0WPc96eq6w100Ajs941G1O2W2m4m5mRW
-92JWV400c80K0Hf0O0WBW90J4J0c80I1u1410m9POmq3601W1e@R600eIcksyd7CVp3@FBet
-7nRGLyC000d8JVmEMFXcvJ8SU6gdN2Y008l@@0eZ5W6dU8FihQHlYMt91000Yh10000045mF
-JM12rxV5G8200800CvE300iQsv7owvb04g3mkd7svF600WmD300aomChThrf@I00OgB9LH17
-C0CbEF@4kqWu6KhH5y500gX@G0880@_N100cqt@b8WJ32OhecNK1WH00402WBmh0KV1mCCOK
-iFII0002Oa4W2005jpGafCuL008CSgo@tWpiD8u2I4W000061hKzA00iO6fGNNpVos260410
-uKzA0tQ0yYl4XXNqIv6W0108oTF0080000420G0000XTY010000Glf@1000qC400YzzXmmTw
-eQERotWtlPOkVCm400W9W9000Jm0W90O00uyV60D80y503XXJryS@7lt@l3_VxY@FzFm0mNx
-Zpy@tG@lDr@NZz@qS@@Cu@BJ_@ne@FCx@@2@@kq@VB_@po@@@@@@@@@@@@@_J@FVTj00G8Kt
-_FvyxqVrLaKWAhDxKwk@tlVT0lR0gkugy_H200uaL10WJm7hjVU0Wes5ljeW720IANbzICOX
-4U6NO6000m2500U@t600W0RyZna@9C3V2x_pG9x6avV8hod00WGoar55y61GX_HbqV5z_R0G
-00WoQW1000H__6CLZAVrOGiE9qyl75wi10W0Wy0E100yItFv0010eMY4_@FXr@Veb43I1uXf
-0geqaD0I30i_lDDtZHBGF80008xdSo3m0000yA000Ir@@KXKNg00m@@@aVH8@@@VWKAoC00u
-@VU0W00y@FO00yW_ZwJ0000WFK0_@NeRPO0006G204q1030C00J1WYe0O8FWD000G07008Gg
-Jo7G2108002A0Z6u11I0882a0100WW8H80004824X0W4OWf0GHK060000W840GU0R0000KI0
-0m@@aaFG52462000W4Dm3Wa804a890000GG220000I49804918J1WYe0C00000110Wy0su@V
-Lo7mZe1Ou@@@@@@@@@DUBhA_@F1WV70lnuHW0UaKmO000uT3004db4hUAte3DMyZ1F@q2e70
-W00jPJeM2M3Zg8h88d7000W4vw9lNyJkigKfa400Sq@@t64001vPg2000XiRJep93sxg5GC2
-0@YKtM8g000WW300mOml1000yF49_@V30G6d@@FsYgC0100124Wm@@j0Y71u@@q0GG0y@lD0
-300ok9DG0000800002W8W00u@VL00mAz@lP00G0xzm000040G006sf50480d1P600G0I1000
-00085100018AKEL000GpT00e1Sp008WaGi10I100200SHiA00Qd_@VC0u00800404000C080
-J180X008K08O@@h28W6W@@73G40100004W00880000084aIB00084F00y@FO000A0X010m60
-202400Y080G198400pPL500Cf@@@@@@9uW85WcHA0P0N0Q2o0a1y30983y@lA000e9B00y@F
-O00Wm50ymB8LL5um3F0y70KLLG0mC0AxN500H0tv@Vsy210800000hj10WLrQ@@VaoIFXVqD
-0eR2GnpsK@0R5@f2420W_fPOfC3c08XXXfwxU3008oTXV5RuBnF_9ioF3ZxdmBkT1_T0OWnJ
-0H08qd03hW@mX9Kr8l1000eb800S4PBtanmVzFSCSHzsB10WvxKp55fs2myw@7F@@9pSuZs9
-uJ00u@@6100Gz@@3002W_@@@@@p9zM6000m2U008o@9lSd100BK@@39W41WmvV0a@3Grt@@@
-lDG00000m4a@V200oB6J@@atMj3S3IzUcsID00GJzss9K3UBFaRG01a08008fWS00WG00000
-mK2G3R9qNUB002028udcW_y@@M00Ck@5kD00000W02y@lP0m00ICncyra8BV3wkFA000yq50
-0_@V64G008001wKN2W00GPF4500Mo2zpiK_40Af0yy@d00024100qXF9bq_VQcOiSV20S70M
-xjnexPecV3000mW300eiV9Ipu@PuEfYp480000sG0eLoeUvV90008000OZldXfnLPcVj00WW
-KkA300C000m4bnJ55Qq8eL1WrCK40G00000K00405yR02CW000G3000eDD00KtA38G00YSv@
-hY2P2O30C0G000W0830Giu600F0OhV6s6lbos@V_V6004idmbDpJBK1ug0gX18J7RQdSfQk3
-nG00GI1rTIlbnKdm@tU00608@R600000id0eY2OYa4ZBTcfux4QuP3000mK600AprZ6VUufR
-6oEqWmAufJ@4QrFXrqJ0014m@@600uweRZGQvFXPrDuxS60080z@F3024029ebk6E1qO2GWj
-HLpLKg300U2PclkO30oM@yTs082001G0mh6jKmVELVamAQmKbPQ0008O100aVlDRseo@_@00
-uLyZVIQyc1008008004100aEQQW720Imp612G0xn_000GWsse2000Fx00W@@91201m@@9000
-4wHkA0020SB7L00CGkKQ60W10X1YHYWK1ov1uwfP0G008E00eWy7QquA000WS600M4gb6YD0
-40Gm@@f10uz@@VI0080LDk100000C0000W005Q0000jXUNb0090m8_p300Wde00Gnuj000q4
-0082mF0W7XUuLEj00y2y@@C0uV00006000UFM_@Vr@@Eyj7000Cf10W@n39FLp6kFX8uJO_U
-300WWNY@3Fl@plpyqBh1RypGRz608P0u@V604G0Kvk4zkhI_QTTalblLQ00Wej_jp400WG@i
-6GW01008000H0Wdm@FupV008Q5O_X5Qk18t0058000H00UMmI0010000OjE00amzUbrkHiR9
-008n3000002GWgtCeN4y_@N20006vmR04000mWC0G000002O4KGZ0100000Hywh1000OWC0G
-K2W1@@BNpxOyaQ2VxR00W1E00O0@@Z700Ialth0002000080GX1800Gr00002PeW10200R0W
-dmp40001E2000000000C@k1lItUO2n401u746k100qAS000030004W1mMu@t5Dd5UFJU0I00
-uYe9SgQR_dZ@V0yS0GJuDcmW40000ZbyXpjyRu@A004_a1T5pj7IjxgKAl1lo@Gpy90000CB
-13Ie@XK0C8ZU30u60yIF35rNHRz@ynl700800400Kzs6000G1C00yTF3@_RGp@C48W7dwRJU
-wIqtF3n5OGnw900GABPRv0000z0B6RRL18W0WS@J300WuvlCKF_90009V3mWew8CDTC00aH4
-OhSrdN10G0WWvn0qt2Gpxf1008v@V3K8G0yIS2dwd020010004v@RG8_C000WIj00G5moDdi
-408G0gItWHtb00GNPMnl5vT542000800Svl1010XU@@1Wp80ZA@MuR9axj4T0um_@900o1OB
-@q000W2G000W100000ea_VG100pz46CPg4000uK100K1tRW00GxGdXHwgOCV600SvbdDR060
-00000W2B88Sf4I181I0000a0A00000K20wz@701n0iJUQ000LR0mW@@b0L10mX5UKeUQ000h
-100G0i308jR60Wc00000p100GUs6030000W3my@C008OFAT5BMeYll@lVPCgL_1G004fGnGY
-SL00mqhFWAYa_aSfPeQwYs_i2maD073Rm5eR4fWMZRbGipR0000o800mdfvSSw3VARGEPRKC
-6C@@R00W2po2PhKGR0m30qRSWnh72g00WIZ7Bwj4AbR600v0@@@@@@51004bT00mQ6l5sFCH
-lAnT6J2Qd0e5@n00A0alFF0300ET5iaK@10GOHiwWL0V2jad3W@5WFm7xwI3cyt6000q6600
-QBVimtIu@@P00q4_@@LL6jHh@m0Oy18w@k010000G10120urtv000WmP00GlrvV1E30O0000
-40CrLE0O30M2@@mmBjRtY0uq04l_@BhPJt@F008dCM@@@@@@zA@Flp@lBz@wM@Vks@Zxz@tY
-@ljv@Nh_@qk@@iSi100WhU00eWo6F@N200VT@@NK0gvCM@@Xz@Vys@@E_@jh@@wy@dk@@@0@
-VFo@l3z@vO@@Du@tnD6@@Vo9x9K7W4000OOC00y@lAlLhoKuvqRW400EaJsdmzpz0GE3GX3Q
-TZ@@@@@@ox@dS@@7@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@vm@@D_@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ps8y6y2l1000HQY@X@@J0Cr1m@@o18W0ePU60C0
-00001gUUC000Wp100OJz@@@l20084T@RmP@608O00000280WeUzD8oV90zU0iilSLFO0080W
-0AgOz@700007IXSG0001000G000G000G30600048H33000100001000Hd@C00f2us@w08000
-00WO1W200000HY0000004000000GRQOG706y@l100A2_@NE04W08000gI810020004010001
-010imW46CmW@@D0SL0m@@l10200805104040G800G0000W00a00W0W000g00a0200400QJnW
-W7I00008T10WIAaZ0000W0008100020Gm0040AY0w@V30008140000018002m@@J00m1u@@l
-10X00000GJ660014A5W40400S3W131mm@@60C00u@@tW1000000048000100GW10f0a00080
-O00W31amQ690000DD3s008000024020WG042H00440I0GI0005001P80410W0410S8400004
-28I000a0GKeF9000jx@@t0W0800010200510W2080GL0O0081487000H010a5000W007G0m@
-@C0Gr1u5bt000K040Y0WD0000000i200G008G4000A000G0eN00WK0C00100800040000002
-000meG00u@@q00H41000Wxl7000000iR00G00mC0OY16000COk@300U00300W0M2mW@@P00G
-4s@@i10g000o0g100434f028I1WHa2mE050LWE0g0T0H2s1f0OW85WA0AWa0T00EI910z60@
-@@c@10000W@200@540@B80_700yF0y@V0uVG70CGA0CmV00OPA3000W8G00u@@@@@@@@@9d0
-20000WG2000000G2io000Y0t7nGCSCKnL8WWF0YsAA80008800W200bPb10012_@F11W8W9N
-b0000a6fOu@VC000GhN00u8Ag0000WG00OD16G0000004eoC6_@@400vIJFG506W00G80a00
-0020W0004G000meU600088_F6050004008MFC_@F10f00pgfrAPCy@VE000eC100y@lJ00G2
-080000W0uaC60G02C0s3@@d0020Y0sCuoE3M2G2089Nzlr5180WIzI0H00HI6OK0Y1@@Z10S
-4WE7Z240000G00280000100108qGN2001000A0qbW4Bmnm@@I000W3_00m@@E10O00800000
-400W84PfO000G000Y00W008000G600eq16YsB1G00024000008C2X400c8@@FA0W8000G500
-X400YKG042m@@6e0000800IY6L80000Y0Wm@@R0mW184Cg0a000000W8010008140WG00800
-000H8000018IuCCSIn3400GAXZXBGJ0m00m@@H1W0X020000W40G0W20WG010600400O1E3W
-908Sgu3LGomZYFy@l100aN@@dACH60EG6850562C2W01411Xa81n04100OW02000800000KG
-jd9yHf1G080@dvXD5O08T0m@@E1W00050010m20000800014621000111W00W80Wi9JOQK30
-40Yy@V2081G00000I00uKX7YuwA4020000JMyq0000400W80uAK00020Wc0GxHCaXf400W4g
-1e200qd@@J50g2000000F000Wg0G0308oJ30002i_c4@@J2Wx1W@@T2020004CI2G58403WK
-WE0fW81p1HAW0WK0M300G0G001G4K9b100W02yCXJXDuCL30040SBy30000FUnZ@@dXg0400
-200@300_7ymnCuXB8m3NGCxlWKLr@@J0cd1GtU9KBS2nfQmOh600C1u@V600CzVEgPfC@m@@
-j0Yz1OKskgsYa@@39Ggh_@7rJRDOy2XYK8glWD000Guxk948i100400010K4k1000GUfG500
-0W8600AYcA0000420G0Gm8100060010010000GWfDPGJN64sZ4FIX100YXbHlgtO3G400ylR
-2hSbm@@m0Qg1O8wh00Y0020W0500080020020008004W0040020010000uurDeQz7Uv6ZGpk
-AOD900080W0WuCcP00miKMEL8002000G0W0W08G00004a2PC000WWG00000220119WG40y@l
-A4P00_@dA20080p000W0WWY10c80GGW_6W800G00080W00004ap@5IEyCuM00ORxe0000L@k
-1GO0000020W0G0001m2y60005OrVO00mlCMUK0020m20102O20080XQW00G4082H00000008
-Y00G0G088000004W8GH_@N5GID0nPI541003G820W10mo8gWK08000W5000088W2414W0a80
-X0I89LeMSF00C8LK081X8010800oYGW029G8Wt@D002142000I1bG0WG0GYI0z6k13@J20Wa
-e@@Z220000m010102000C4G00e8408ZU3W140100010O0000884006v_h2ec5W@@T2040rf@
-600G00200004e0080A0W1uW0G0X00GH019802WG00aWWG002aIbdDW9SRI00W8000e4C000S
-00230C206G5100G1204420988G00G00ehVs20Wadd@ZY0020WU100080G040005YG100a9GW
-0000Gx000400141G0W200G0W_Ik@g0A80u@@h00G00WP00G0800000K0G40000y050YPCmm@
-0100ywV1yB0PXfYF00W@@To00008000O020e2S3G5WX0003GW0KW85WAHAWT0I0C0s1s1y3Y
-4W10mbBg000QgDpe00pFNbf100C010G0000287y4eggWBy@1W@11m5Eg00000qL1mOu@t4NH
-00yyxYwg85Q7000lS10WA2Twuu4U0VZk2R100HUSYNjNj4vWBnNuLS8k4W650AkEg8KDuOxD
-gvEXEk810007910W@@DB5bJkYN200lt@@FsSu6qgOE0uV0ohJhDzDu9S3YVC700Weo000A8j
-h7pDuyV6E856000h9fEsNvF4AKB00000HF04LeM00W0001000020G80Ohj6a1P2fzs2510W6
-5CR@V3ogtWLIR10GhSWzQ10040a00002012H0000400WGb002000042I0000GW0v_h2e15Wp
-H0320W1W0001080m0G004000002Q5S9Ixr3y200r2hb00W80000O0C20000W0018A9R008N6
-o4OluO000GWkHPuDZM0Ie0KQDF3z7228W0W0qBeK0000e40800uTz40G204vgAXc5re@O00O
-Wv_u9100O04100u7000A000e80001l100020H0000ymRNj0u81uTvPo1x400W@oF00YUM883
-00LNRsGkI0004eOT3cckYMsJ00GnzKFiD7s6Zm@mFyC0iB0OCSpQw1cWcPGg00mgUW5qU800
-0W2Q@XK0Cu@V300yIa7LNnxL40e0WTuVxg76UxPZ5gJ0000RQ62DUQBTv3Ps3OSRE3FdlH1w
-90M40Oi3y6xy@mIb3Op2Gyaj000CO1W2_@tWE0C006OGA0CqhgzW6002yi50m00dRdW0000C
-0002000m002ibgM00UsB_V600m000W0oyp000W0T0OGA0C4tlJ4HD0QGj5042000000G9a00
-000G0G2000001WPA101W020a2W1dz7LqrgqLy30C8000001WW0u38300818000C503cyQf@@
-D00GTKmelbKmCWwS0o2Ygg4QPhjGKD00adlARvR0400000WDK00s005s000O7100000G1000
-00q6400P0qnC3d87IRp60003850Aw@t000GeDjV200uCW008010080eiGyImW0002DNk4XW7
-80p0HGaHw1GAqYee881AHG7U20Zz_GKzR45m31TRGA0I000u@@@J008X000010590m@J000W
-000410080S0m000400W0fw110mV204G500WU000000G8I0004H04H000a8am@t8A06424HWG
-a0850A00Z3z@l18W00MmC40S801eGrOv3300mbD00Gzw@FFlb087200EWWJ0000um10000vG
-07004EJ1WYe0E1d000820Wbz@Vwi@JzlE0WS11tBX1000000qw400wm7300maFaR0810WAzJ
-00J2aSA0WK0Iejzk0m7GZ00000mABmfl0D1000uB0w6Soa2C05q00uBef5@_Fnm@FSy@2B@V
-mp@3Cz@@M@lls@txz@yY@@kv@hh_@vk@Fky@VR@@sw@Vj@@@@tfPAJ0eK1m@@l5YD3vOJ200
-0y8NbB2V3o0WX6rz000LPuo@@Djw08MxprknVvh08h0m0u@7WUrPFWA0K0Wu@P0000nP@94J
-@@lyt2000ml@V08N0mi@G20108Ne7S700y@lY8G00FyH2000R@@@@@@m0W1000G0GWvF000W
-O7fDwt@@@@3Si13M1eYCIiX500m@@HLeL2@@N400wp3rUxc@P0SI0iN@y0800sjnZ@08fV46
-00WKrcp9d3eobDFy@lG0960_ZmfAA_fsE3c1X1000eA300sl8j@@j10m_p@@98200eGG300Y
-0y@VZ2MP0_@t004SGBBcGf4Hz@FF000uWB00y@V2000Y00080900u@@610m7z@F3W8W01X02
-CEnR@@720e6W@@D00W8200W803AGg82W8400y@lY000m0700y@l1G4H000YAW121091Wu@@D
-20e@z@V3000G20000GX006000S240@@t8OV3W@@D00Y0000W00eW80004YlgH000iXFc0800
-0088W8000G000z@VZ00CsZfY148KG50ro@@c1sh1u@@4000820u0GG0G8H00WqCQqD00m@@6
-0uV000CJbgQX0wdin@@t80WWo@@J0L000k0k800SHJwkn@@r12m1u@V300p9300wY0000008
-0@100rmTUUn6y1t61onmCMR00WifmktgikYXnau@V60zU04fTNXU94000GD000zMpMjrUy@V
-500s4wRpcAzWvyR6E2aXnjDuly4w0WXm3J0KB0GDfL4Y83@h9400GWwJJW000mKhCisg1tjo
-m5ZF0000YY00m@@60101OhERgTSff8Ve7U300i8SVOKb@jHBy9y286lnd0W00W4vJ0CV1mXy
-ayVfGbvd0080Wu2t0400nQAF000c6s20G8dFiLY731YKdXRqsR20004800000OzAot70W000
-G018yHdIWy100G0xDinzn9K7P2WmV0wvFXg6BgXXG00200400W010GywO08000200400008G
-002000000WB620OaT600010003C0rGo4TZ5NhW2000H00WxtD00080400m0fnen16WG00820
-000WPPQy60002401GGW6m41z900040001G010000000K200W00hWBn@@900042000200G8XG
-00000G80000_f80000200I0X0009nkqM_I000GOGV3G000KKm6000000600W0000O00W0000
-002000G87G00W000480Gsk64SLHdVR00A0W@@D000On@@6u0H0000Ge0e0G00000600I@N20
-W880000800W000eWWD80G0W2000000Yg_@t00NW8000AINjbWRtejtD000GKZB6xHRmbZ649
-D3WCN0_@F100W8d0V2000gnMn00481W10WqlV0160800eX2KD0G0G1I840Wc00@@B10eG002
-0e8080o9s0KA0200q6000G362500000J00WoFC04000005Wuzn300G4Y00Ws@VeU6600c1y@
-F9W@V0I@s300WafV@G4u6008010O0Y1a1S60086000ozN200m1000C00000S0m00001zD00W
-80000000TG2000W000W0T0030H000k00ExWae0v10_@zCORWP00u@@4QJm0000O8400w18XM
-bufQ6L2yj5010000gb@MxD0010VD23e51WHh_9i59I4q3W000hIt20008d300vWhu@@L00eD
-zmTXM_1fDln0Ct3mswZ1100000Wmau60440vRCI020004G0u@V3mE200000020W0048000G8
-r8GLP_FijV8he@00Wvu@@JG0200044WG5fwvS38010aU_900800040KRM2WWJ1_lZXC1pvDE
-OsP@XLBs0000Yc00W@@Z200WGHyF01400080mjz90200A6u4sjFXswJ8vE600200WPDgAck2
-dlYybUu@@G0Q7040FR3yRW000W9_9vhV3000mPJ00uZ_n8W00qvE3W0WGQqFXC@D0010GMb9
-C@_300egEU4ZWXu1040G4rCCZV2m00200W0224000K4mAQaW00001000Wt1Wo7buLr4_bCd7
-gb000emLw6G90000000402Wr2t08000042WCkJ0O00G8jIW000080001A1WePH22X0mVL600
-0W00A8mLgFSEv3rpQ0C00WmCD000qwcb6yd93000W00010G0GeyQR0880y@l4010400000a0
-Y0300X1a60K40Gfu_mEkC4O9300000XZ0iug7j0MKmt98000YA4W000AW8XV0000OkmI0001
-0G000000YCkD8VO9caEd4ha000G330400s0000G0G00210A400WWEJ00WZRP0120mPk9SMk1
-000Q80000GA000mAF240m9TV000GOP49SPFC000mU0uW@@PGL10000000mD05c5o@@9000eI
-410G9y6u0008GuewlqW@@J000S400030004030C0o0S1y30usD600600000TAk7W10000G6w
-@V300CZ6Bd1FAp0008W2aCW700GVLH1W1mK000000OW8@L1mb3mw@ibSAC4000000Wv100em
-yF10iJ6999HiJUQ@y0000rq00mzp2D6S580000002Kyj10W0000100010gAU3eG00yulA00W
-f607cFd3vAw44000SPU200G000W00G000WW0Glv600G00W001010WgoJ0800mMy60400StO6
-0ik0i_l1014OgHtWCtV8dw4kAFaWrVOQT3EstWsrJOiU3UdrW1xJOZV3MLFXUrDus_40000A
-D008776MsEaNiPulVCMzt00G000001w8810G080W4008GG0040uA83cJ8XN_be60600K0tsV
-20410wxNYuvD8AVX008GqFF3Lhz0410WoWh8iU30Al0iCF3JpR0008XwzH20G2GOz600W0Ao
-U300101W0W02G0GPsd000cJo01W00080X0G00WWEwd10400fsdm0sy8040ysT30W0WSaV204
-0agKVZb_V00mnRJR600100800OlS9ajO275a30e02000022000000A0WGuKP3G14000808HL
-O0z0C008W0010HKlH11800000880D0G40Y040401080W0G041018G0004006220Q@FXGAC00
-H0mg@CCxl100080000H8D800G08800G00OW1_d00G0G0204ZIdmiqpSjl10410G0W0GO0001
-000eW0mEKC0WGW00X0mS@bePR94040200000WW1000H04028C00000A000WW000100024000
-l6O08W0WWRp100e400W00aG8K00000044373lVN12K0WH_J0008WI80W_@D0yw300W200eaI
-W402800084I0000G018108G294GeI0G0900500800Gsvsa3k15XR0210WOuC8XU3I@MYtzP0
-01000G0G01000WG0000WZN500000088000042BNO0000111W022G4m0W0040000A4GLmpS4l
-100CmWG0490002WW00O210001m01X0Gm4G8004uFz440400000fK_AUCt000MW622804B000
-0000W0q@@680080000W004W@@J0W0WmjmsGW40040G21W0WmrDG40G000W0GK04dvp0W00WU
-@nuxG306Y80W80A6V3YhnWKlDesR3_Et000019yE3G0000040eW4Y10fDWY2000ms0W00qOu
-I0xc0ma@Ia8_38K0W00440000GdK10G0WKl040v@R00A0000G2ez0000eD08004001GJSCC9
-UT000xdfE10W1c@@N1g_FWxzd100uC00G60N000P000G10005100G0C0u20Xm5unmzGux6a3
-k19@R000GG0004y800Aps0WHK1000d100g0O00001920000F4000e900WY000Hy60OyW000m
-9VD8VVOy@l0000Sd300000800003O00ani000800m@01000000uF0@@@000FWntP00F0GIg9
-mB@0m@2004VK500WPBBhLtyy00GTFpHaY3FaoqpPOC3ENFdgsHgr@wYDtWumVeHSR00u_@G_
-F010GkLNYwrVea@4oEF10100xtcmybX0ew10000qFcLCklAXq@04G0002W00GG0WC01840GG
-0088040W3vD08008G2G0000001G0_ut02400ZnR0020WS_buIU34310ibT2DPNHZR9i_U502
-00olz100W0810IQEnW3kD00G1mg@6000060018100W85I00440100WAvD8Rx7_qF100MNxh6
-omtCCy@3b_Rmw@L800G10W00284000002004Iv@XHQVOsVF0J6800002081mUx9aTvCftp00
-08ayoD0G00mjz90081e6jS000GBF00O2TCwpFXyUt8yx400208200OSV300220008ufG30W1
-00HK0eXVU0mGyy@l10W80IZ9700GW200002G0100081H300G0202010W0081Ge5kJuNkS06B
-0CrV2N7Bnyy6akV801G0Ndt0eW60lzc080040010020GQbMYeKR10001v000G0000200QhVZ
-0a310Y000W8110f040000nW40204gMB3W0408WYW0Hb00000XYwJ8pLO000eEBl10800YesW
-wxb0008oLyR000140G020000a8a80fW0c@t0400W0GP40440ga05Q@O3000G000G8c33sA66
-0eD01cRGXvLaYl10030c3ZX@@b00Oe3000H8Y8XWWc0e210G100exR30WIG2040004802G00
-40W0KA40M8F10e00jth2X1000000d1W120002521W000AeYX0pb0Y00000AK0W0000QWkjqW
-4uI04X00mG08000G4212cxt600Tx@fx1000ZLqC8bRC00W0020C000002W0000000aW00000
-W40800W000eW0000K001K0W2G0021480C11G0WG2DuJnM0kV0q_V2ZkB1200000824000g9P
-300WW2031100W81180040002000001G40H6@t0828000040011I000OiL6g_M5000yI400Ug
-FXAxVuPV36LEaD3D000020810020WeH2W10W4qak1000AO0100m6eG5010GR0ex@D000G221
-0W_GL10Gv0200W1pt000040ee4020eQ000Qgl200A0XwR0410E04008K4p00qG300000VzD0
-0000uA0njB48m7Wzt5200@3000UKLLB8G@a9zG0009100G0A0e20101e600GC000m000Wc00
-080700qY0a1000083aVSBAA00IKoWq@h06000P0t00qY0@@N10A000W10000W10L000k0MH0
-0iY0eWDrD01000u1000uh90G0100GH6lk1r2bGU@j00WALu0mCd10000E0h@Z10K5W@@n000
-CW1000000pI600qb000000G0@1GQRBD@l1Ww700a00azF64020MiFXe0sOAECMYtW5yP0600
-G0@9iMD3@Ll1000ME00097NnxrjiXG8pf3Pgt9ijl17uQm@@600a0eyR6Ipt0W000xAx1mT6
-Wv_mO_I3c0ScweJ0W00OOz900400100Imm60G008vT302G0MPh70000100G3S0090nGcnl50
-0H404aO00gY2K00001800X000210040841WW000014103010G02A2ltb0000mymDeyGC00aL
-G10000040G00YxZJu@@404084qW1D_r204040G5000K0cSt0010GdeR0W80001104040_@F1
-00C05@J2WUbWHKDeiS90000EsZ1tOq20004W005G00Y50e0000e0241mV@604M0OLM308901
-AG0cG0000W0WB7DW800GNv6ick4VMO0jH0WhpJG000u8zLaVSB02W0sMs0040Y000G00GIqn
-_3JCpW4GGWwyV8VU600G0W00000GULJTR4Nl1XuNnZz9000HuB_701120000W0X0020001G0
-0C2000020qdX1GO0000W0yml128W000YWSMe1000G0G00Saa10001cbpWk_Jmef2G2yIqqV2
-h_d040GWj@bO0H3Qt@100200018060OqoP204390800W000W0002000pfkDeL_401008100O
-f430008G400u6V600801000MV00G@5Ry@l1W004cgFXqwP8RP3QFM2G001W00W44W00000H0
-00GIZ6010G8hc401GaiHv67IRGG_900uSV1wG04204gl4j5mGt_C000WH01C8G05080S8212
-G00K8WA82Y0G0004W02400aG00GWG4W0280085W0204088808000I100W001010400008e80
-000200G4G00000440W0GG0000WEL0AYT3800000109020OW04OFy4W0000020W2000G00040
-02Dg@0020G42W0AWBHW0WK0X06H0040K805YWW0vRP0490L000A00HH@ot0We020100Uxq00
-0080000100OW0000004128000000800G000mP500O4x7kgB10004600000100a00u@V9GG00
-00100200Ozv6K5C3088be080KxV20G904G200054200000WG140W00G00t3t0Af40blbW000
-840O001CW8K80KBN2008000WmzUE300WGW0008050u@V300KW1004ANS369tWglD0025IA06
-W04W21084X25WNCV0840W00004g010008000WW00G8Bk408001080080mmKr6ywV2000G004
-010G200GWH5p6qKk180000DO0CyD3K000gVa10410003We42000GmOR96oYp02WXI000W806
-OiVF30W26W20120W1K4000B06C04180C00W0200240I4HW320W4W280GW0W001801S029W5W
-000G0G4W0000000C00404800W00600000e0W20040W0600000WD10W3vPucI66cq013m1W10
-YW0G00Y00ujT30004A01040410WC06W0000Y00Ekd100A00W040WYG0040G2220240140000
-0Wa00001001000D062182Wm0W0HG00G4000W0028Ivw94UZ1Rqdms_60080EouD0W40aVl14
-140_@d1080A@@RmhH6SPb1Dqd010400y2000080400008000W0iLeH0020Wjjb020G1W0qBe
-00000wlG8008pE3000W08Jeb40000D100080G20W00520000b90000i6WI_P000K0200WSnJ
-uoS3Gz28002V10C00008X5VC000GX30040@2LA0000wB0z@F30m4007S10OWzb@@3aWcWQL7
-0000WlGL000000mT4100St1@J@@20Yu50mY0WggxXR3000i@@l10rk0wyt04X8u20000000Q
-r000000de00Wc@z00W160mCY1xV0eW2merC000mKW00m@@6O00006000p050K1K1K1m000u6
-0006200W100G5W0WY0L0L0g000u20006000e200m5u002mP02WG00061000X000g200Gm70W
-1G401mFuH2300KejYF3W0W0008Z4JE3000Ced1000m0eE@4006WO0C0p10qE30006000m000
-W1u00WM4AIX4000t9W@Val0eA0hUN_f20Stz0eA00000200C300K50WN54Y80H82000z0000
-1000G4000OW00eWQyV3WP507@p0ypFWo@POMy4uL00i2_6XjNn@mFScl1vwwHitL0000ChMI
-Ywt001W0F3dGypXail1NYdGg76iBk1W000Mto0010WXYRGwu90000iHK3Y6d100Yj00G0U9t
-0G080V@RGJQ60G808d33UfsW@YJeew4UltWIuEv_S36G@XxFC86z7cFN2WU90rpTrGPCq1t3
-jERm3xI00001W20GquF000Wbw00H@@600GWuoT3008000W0evP30240Syk1nzomux9aer3x8
-a004800W00m0G00G400f00OsS3050000002W00WG0400Y0GZXRW004XsqC0G08Kds64V_3G0
-0000qi02000004m8eUSOhA0000H08S00011Wa01015K0200W0GIG080200100WW8G01G8208
-0480100a02G0i_U30400yCX106a05000040G0A00Iol6q0d10690kRd14000FPpGYs6yRQ2X
-wRGVu90G01G000Go_9W000u@V3002400020Y104G08O044208m008G008W10020O61600W00
-G02mSy60000CpS3000W0G180000uDi6S@l10018000G2E01O5y4cOkYnqD0801GZxU4lT202
-He82011GG00eG01G10WSfDenV304001A10Gm0018G00102K0040404800W000W02GWW88080
-DJOmmL6aLN200GgBwuXGvCeAyDwHF100480W00Yq@140W8000004A108000020mMvI4IJ2rQ
-RG3@6C7l1nKOGPrI0sQZunLFwf4c2zD021W0801WMvD0008W0080H00284004040010000G4
-00Y0000240100400G0W00G4GW0010080007sRmaz6SUl100WvXB00A001uuw7000W0002eh_
-7QktW9yP8gzA6Km001041mR0040G2W40028000Y0S@l1821000G0001GukN6G000kia18002
-008010G0y6R3040000GW20000202010000008G000SzM2huRGZ_64NV2VwpGOrL000GubP30
-G001002G0C00020W5_D00G8000001GH000300XG0240001001A00W2vJ0004Pd@6aKV2TgR0
-ua7WGzJ0120mGnC00040004Gzb6azD3lHbGF@L00D800O04G11410O4G4X081000X0K01002
-010H0G0000Y8W08G0A8W0040820100110W0000X0082800C0000Y100H005ER0800010G020
-00000W0C001000a008Wr@J0820000040042000G0G0WK0e1jSQGDbFaoV501000G0CWH20LG
-000f8018W0W00uW04210022580W008WGCWW00882XAI89m800116G_86G120GG0m00801000
-1G00Kw5t00G00020000GiY82G09400H00004095_RG8Z6CYc1000WU3rWS@D0G0G04000000
-37_j140000eW200000W8Ay@l1K0W000000050100004K000G10G085009045W1xXd00K0G00
-000G15G40800f4e_V384000Sd0020040KIXavDG8000408anvPO6V3_dt00W0GHmRmM_R005
-0OwM60020G460eoE30G000002u313Q3G20a50pgd00200WWW20W00000O0000rbAG00W0Wxw
-D0X40mM@9yPV2G000Q@pWK0OOx_D84200W100004040Y04Ce00CG0400K4VW1GWO24800e0H
-0002150O2G0G0080m05AY0000G050022480C108GK0000Gu00880028280W2G10000uA8W0W
-0Sf00020011002001000GW0002240600800030120WAW41gst0090000G0Yzt00W50ZyZX00
-Y04041G0K00G000000100GX050440000Y0001G000202080440080G0e0004010420082108
-0G400W0K08WG100G482008pj400000OFH0W0200e0000000010h6910H0000G00020008000
-86ncz60H00040000Y0004101cbmdyI0000G300mWB6q1W180100044CEV28XG00G34W00000
-D0meV6aSk1QW00o3mW@@D0X000G0w5000qEbW20000v500000G0G020G00000L0000000W4f
-gM30004G0001Kc0040000920FjR0084Xcnn0U8p3UGc7yW7pc1Fye5Uu1PymZoQX7aX@18p3
-FmZ7UWvP@3FyG6uXl80oSH0y@YOcPCfgg0m@@nKcBYfCN4WK0C0pO2W@fgA0GLLXhR00WHk@
-rDmz00000G600000m3FWm@U0n@10Y@30F_70Uun3ym34vV08w1FGqCpWe@1m3pCZgK50Fu1Y
-0K5F60W05101g0K2K4W1g20340WA80AGG0KWY0W0C051A2e0r1K220e60W24005GH0A060M0
-51T0g0g000K10G120W2K405e2GB03WA0604400k10000000wB00002000L01040_980O200W
-00002004W108010H060Z040r000C20W00001G002I1mW0dOOt@70G410H43W__310OcV@VFG
-oE0@uN0t1p0G4Y00Fe00H8wh9u7m050GPB0u1N0i@F0W3E00AeSt141OW100C30YW70G1D00
-mC00000580K9e00WP000000SQ@H0TOBXk30000000WR0s@730uP0pMFsU_60081EXvDAF2cx
-qyuLw4AOZ102000002wYpWbpbugS30Cy0SG93JepGtS9SZU200080800KDT2DOpGpqgaC06J
-iN10040000O8300oxBaVp3PmB9Qy6ZE2g8rI6E@N200JXRapGo1X0801e0y4ATNYboDG0801
-00001W0000140080CTh1n@d0e0008000000K_TJ5W620plLny@6SBc1XXRmpe6q7U24G01go
-@XSZDOKT3UAt00221Pa@mSXCaAT2@Ru1000Sw00G3zymE@904G08R63_@F1e020pzN101001
-040HAa0014XNSD0400qVpFS4U22600UutWoq31008yR@600W0uTT60090Cwl1xmpGih6a3W1
-NsoGFxL8040000WW000WXvDO0U3AhtWzvguolD0Lc0ab@60G020004KCl10I00gcdXluP00W
-000e020000W100cad18W005uho@@60102ue_40m00iWZ1M300kD8aCER1000WW00WTHDOKkG
-6eyXU_JOkV60mOoY002uOV9guCXV6OOc93A@dXC2CO7V3kzt00202PQgY0W00H0005_@0080
-W2QDu_@40Yg000000808mIpC4vz3BNnG0dLiVW1fjR04W0WktVeerDMdVZ2uJ0000Ap00W82
-n008G000GWyoCOGU981W0SIU5W000oP911202voZHev602008qU60000G0040000GhI6qNi1
-00kgBQ8XfwPuaV380800000X200W040WFxD0800mM@64Zl100042apWW1J080YW010300GWn
-tR0004eV_tW0W4mg3C0000W030020GWIoD000810Y0G000006f0ABpWyCPOdE6gRXXB@J080
-00080edJJG080GbZ90900i0y400000030u3S3gQpWd@PG000000IXwnDek@40500G8bW4048
-010A440800W41000Go70000800142WkhP000G20008010W080084000W40000100A10004G0
-000K200bo83baRGB19as@30002@aFXIua0100mceCG420OUT304280200Aw33000M1000G00
-W0CKWm2qD0042008G104400W020W6X0J0OeMC3GW200G0001400500G0G00z@RGC1Cqdk1W4
-0WgmnWHvIOEV62zd10050070W0W00SvV2000HW0S00Gm200W0008Y0280W200084000_bj0W
-W0040AWp@D0008008W109W0W0000aW8020001WW0B080NG10C00WMBr0000100110004Src1
-PyRW20G00G18W0040040spx3jVRmptF0002OSr4cscXH0O000010010000C0700_@F1WW50G
-00W4800010W42500400I88MWztR0224G0G1200G400400eWGupO600008I0000W0000I0W00
-08G2Wt2z10a0X40G0wizXp_DW900mZoCWA20000_ok_6080WG9000OJ0000qKe40000eDKnl
-1G00WWG0001HW30400051H0G00200410z08000a9m1GA0900010C00Gl_6Kkk1NpRGEWRK_T
-5080W1C0000W2AwV3000OcVj10000GLG0i@V2VDa00000000p00000W@BWvmN40@l8cP6S0y
-F0y7Um5_Y0m@5XNLBoCcNKLgI50_7pCz0LL5Bd1x@R00c1Wg_J003000a4000180000g5n01
-00061000100KQC3000100022008QN_4M0n00W10003m002WO8H2610y21000000CsY400060
-0080600021O20000m82W2G405W90A0J0N0k0c8C1CPf0y0W9210N4004000W00aFW10GH000
-0WsGV2080yXF0000Wo6m0000W8_ryD8GE9W8Y0KQz3ThRGpwF008rwKT300c000Cm8XzAG1L
-14zF38Y80U@F1q500000000O03O0000WHNMSc5UTKRw2JLzI000Wpb00GTQRSVh4XGront51
-0O@9f0I_4ddI3nueSL0DA0C6eA@dVrdzU000Wok00m2LR4WE3fuQ00GWao_J00081002a@@D
-W004GlYN10mnje1FcqsWm@D8BT3cJBXeqP8OXk01_0KY@6G0007PqWGLDuDL3G040aOU2040
-WQut00G20DL6Lu_6000WDxXDEX@XFnO8lU30002ypl4tFgoi@d00On@@@DMjtWQpJ0H41W02
-000G0020W000GGirM2Pj9HydEP_d0uiJI4002i@l1010W1W002020000100W4WjsCeoB6W00
-0qDYGvZyWz00WvThOrH3Qjt0W000020WAOtW8xD0000IszF0200001GmSgKLEh1zeSo4@68X
-00OaV30WW4q4931zdW004W1S4AxV60Tt0qw@6dRR0001010a0000G004W040Yn0004200083
-10Y140sYpWI_Peb@4cA09000qg100ovR380G000004O100000204G464W00H008G00KW0008
-58GX402080XP8C090Gmp76yAd14e406p5900v3HGNH95684101008aG80WSnD00003W02G00
-G40G90180800O0200GGYu64MX1ZiQ000800202fvi4W82WC@h00090400084000030e40000
-0muhV3G04000G101G01K4810GW801G0W0100050040G0H00WjuPOb2a000GnP008C@A00410
-000JmH0000Y9000OG081sKt0123a00004Y4S802GOOT60081ivoL00goZMs300010802x5t0
-10G10a0W40000I0022002G10WcuPG0G0mUx6G0008oT3kc29WsD0R_B100eWT2J00000Qb1H
-W0yBW00000XYG80040000W0W2G0008q4WY5tWK_D00m00000qRfZ2000cR00Wogz00O6X000
-000Gc2W@@50vmZg800eq30mpC0O7K0@@RW700000W0000_zV00Cfl144000W70CXDI00ezoc
-T300WcQH0TeZG00S30004000G000m4m0030106Wx000I100G3@901WO200nqFtN5sX1vVx10
-0WgUmJeBK300uPA0L1e1kRdEdA00v6P@IIts9ypk10008MHDXE5_Fgm4iD00y@R8RQdGri90
-8088TNFAOJeujJ000Cq0X5rn63xx758d4WJ@cv2U60001Snl172ZH7Z2PG008vwV0W00qQd1
-x8PmvX85tV200m9FcScydhe7rMM4l5GeE0hZtItyCygeP00WWGA00qD9UbiV20WN_OJpPmbq
-0lU0KQnFvj26000SQ100vrR310GaRPDBOlJMR@Xi@DuYqq01704xnCXXRGyic10007s00G7m
-j00C1000G00002O200beSrm@F00u1CusP00800001OVV9kF_AWpF0jZaPGA9GC00eEmP00S0
-00G0Us3p0040bJzCZwlHrrK10I0OGROW00001W92002qwQ@7oF300qlRaagqVh8WACUns302
-00WS10QiAa0tD00G2mqrCKUz3vbFJPsaaKW1i200gEua6kVebx7Y1lYwkdvfT900e26GU8Ph
-RGvw9C6_OXpz0ek3WqdPe0wPQi8giPbGM00G_5jCOl40010oagB00uDHAGI9yCi3l40404ct
-tfGlV0GP3mU4ErqVK000um600aToCTKMH0@N1We2lkVgk9z@QMj40WFQV@d000GPA5y0E90y
-htIv7J5000Sq200xM1Je_9KT530080000G00G0wm_e00SeaRbAVs@0e00WhsV00X1GVcK1kX
-18f0O6rtWWHV0000C00000022HNJbj00WcCRyyV9kNbXs_z00480010WaUJ004G0008Xf@P0
-G0010004WB20vIFF000YuQF100CmQ_60400eFV30o00a5t3800WxLqi6mnhksD0dt043tCr1
-n6000UF200VzV2WW0Wumg300ImMU5b409Nyb30g2WgWFvwO6UKy@zTa00GTng0HjiNKWwQ0w
-Sxg_z@VLq@JLz@JP@lKt@75_@Gb@@Jw@xq_@DnR7000@Hup4AxR00EJN3slU0JcT00m@@RaS
-S5xw@600@@MFF9tJF_QkY@@H2OS3mjysanE3LwRmGfN100S6O00mV@U4fG5nxRG@_6Kwl1hn
-h500lcRzcStz70hW0ae@3RQhuj@6000051G0GO_2LdQ2nvQGM594kH2f0GHK0R4l_3q200In
-mZK1WPryIpZeYG9g8A0Ckz_1mvDW3emmu@9aAmChXNn@7Ca205H1KnqoF0210ugyJI58aJpD
-00a0m@@CyHk1f0GHK0Xi@V2WZB0c4AaK1Q1011G70Ea205H1GI_@900uulLsGI50c@@@@us@
-Zt@7m910LHVOo_RGJ00eQPdIsFA00dz@@Z12H200000W820oO_@t_n3W10000CWE0O0W10OA
-0K45m900000FW1aAG5j3yGq0g8G201HW480004492100W0HW840a03C50AY2u4000Ww9G2I5
-e24100000GG4004D0CWa804a890000GG220000I49804918J1WYe0E10000cXaeK1gGGWm90
-0001n10f2CJvv@F__@Xt@V0f7MW8FXLomQ@6C@u6nu9ntzd000iUIVUUrtWTzF9SpS0Sa0it
-FU1CU20006d100rEc3200We7D0200GmS64@ACp8AHD3I00mG_qkAI1WY@@n300OyLd94lLT3
-JAn0l6ymB3S5D0QJ0oOXb0K00Gei6azWVXsQ0GG0W@@b00W4o@@@@@Vu9BR0800000XH@@h8
-000280087Gd0004WRWD0Wz3m@@4cG_6000G2qx@@@L7000SYB6CM_3NcRGCy9KtiV00OKY0V
-Za2aRvtA0u20ielVZj720004Y300PDoGTZFa2m3H1WoeNpy@@60dD0M6x1000GD0OGA0F450
-A@@V20a848Y00TzJ200lW@@D000W8400000W421Y8G8II844H0X8100G41G410f0O0a00We0
-GPRu@lXFm0In00m3mRz76Gw6s100Eyt9vG00m14E100007E0000a32u00WmPEf0GHK0F4Gw6
-KE72I5mcy1mudx@x9@@PuK9J@A0081zh5Uloh2eP0W62PBf0RmC00Cb@@@@l1104W@@P0Y00
-GRg9qaj1lhc0Gn7Wat03002GqyFqEl1f08HC0C000W0002OIz6GR000000OMz60000ij_4wh
-FdMvb0800GryF08000040npjC00C020000I00Ws7J00040G020000000I@IpCpgUJ0iS1Ge_
-C08008NV3Is7l9WD0008oel90000ql00GZ_AA000040008Y0WXVP00naRq@Ds1c1@@@0G60W
-@@LimP3G4104xy3O200wSNH040YPKRGe2C00OHlwX61100I04H4Y00mAsC0ox0uqi61000G1
-00eWv7i400KtlYtNN100Pb@@R40c0m@@I0a91u@V51G0WC9k4000OS900qyWY00200009y@@
-3002L_@@@CSi10Y0GW@C485LXup3M08000WoO5Q000B2a@V200clpu_@SsA2000Ya10WMp@@
-NCRo_@1ma80rwxNBkISzl4Q100_@VovUO00m2Jo__5LT2DM@GqLC0qE1u@@@JT@@Jx@lq@@@
-@@@Wn@@Nz@xb@@Tz@@@@@@x795000LRlK@s6y4_90100o2JY2dV00G0000mj1oP8uRI6IdXl
-qDODT9U2NbEFhOQy4010008000mf3m0vCyqCRZdV2000wi5guIzJ02004UG2HqZ100WWvhP0
-010mXP60000P4S3gK0Z@@J00mWJZifz@VEWs00Y_7l9jF1000Fb10W5u1BxX7U@BXi7E100G
-No_@@Mk7@@V2008EL000Tp_@U2vCyF3WEV0Mxz@@@PG400G0EUawF600w1__tC0008lvRm7u
-IiyV800H0UySlmUEHi00GAll100WAs@M00qEswnd00000jz0SRiP00K00400Utg14000cVe5
-b100bX@@wj900400000C0W000008NY030y0Wvr@FU_IFzFX9ku9HQBlY2lHpo100qUOvuzad
-7jXp0Wi4W3uewgm70000kNu6l6w10006D000JlJLVw9y1G2Xg@m7yCK3l4Tnp000Rxaz@@BT
-r1Gisd3lzhYYHd@s000WoV00GnVHbKWJ002A@@F@_tcvqsDAsyahZcv@Va00Ghy@VKjlrIa2
-rz@Vf8G00@_Bd@@h000ms@@p3W10e@D3IIUfM6Sw@@@7QcJ000aw4006UcddbLPHwS00S4iG
-zF@@F6up0Wbjnx@@@Zn_@Nm@l5z@NX@@Ky@@@@@hy@@1_@F1y@FG@@2u@@2wJoyF700CL9x@
-F0000G000@@@3000QK300Dx@@@@@7l@@7g@VXy@Fe@@@@@@Zm@tey@BI@VYs@V8_@5g@@Wy@
-7e@@@@@@ax@7P@@F_@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Pv@@nz@Ny@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@ND800W@@P00004a10W@@R1W00m@@@300000W0Ga2@00W0u@
-VZhCudIAU00WXq@@Y2W2000000008W68Ue6YA000080008f0y0W0Gq0290001QhOiyGU00WX
-u@@@@@@@@@@@@@@@@FC0WG0gtfYYUEv@@70sX000000048Ig0a00088VWM6VvaPOy0000d30
-0WobIOHcGY2ua@@@@@@bIXmWe0Gv@VF004_Y0008LWb000d34003800010b5Y726400Gevob
-04y01O682Y4IF0IXM45519G92wmJ08AWJ00000m0EFL0d000W000010490m@J000W0004161
-m000200GWKzW00uF102e200GF0We0E1000e000aK1S20a5p@@60000_ohD000a9M518A0I00
-W420oY10G2Gg0RSDW1000oo7ua@@@@@@@@@@@@@@@@@@JViE00nMFwLn@@j000Ge8mk0R400
-_0Qw@VE100ao20WN1D1m@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Lw@@_t@dV_@t
-l@Vzz@F@@@@@@@@@@@@@@3r@VG@@7M_@Vj@VNz@lr@@@@@@@@@@@@@@@@@nx@NS@@3@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@F0WGu
-@@bW00000000000195a9008W@@D0080m@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@NS@@3@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@d0000EY000@@Z10G0W@@340G00002s@@
-p1020m@@c1Ie0u@VC0004y@l72000_@7C0008000O9400y@FO0080sOW700Eu@@39004W@@V
-08F0m@@_5AX70000000mGK008xXzAeeY@@V00Wty@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@yF46300G0MXwX@@R1eW2GuRu5idAW7002VZA00047bnmIPIy@lA00OeFJ3i@@D0800I2O
-6a1630040k1B1008001400080a5c40R00_@FA02800440W000KJc13bP00100020W0500100
-00GW04eG00004G008W080010W00000L002000CmPuIumY4000mx200e21II1WY07a000010W
-000100bwPmt3CCjd1060W2tp0G100004000G0qTe1brPGxWCaON2000GINJYp_g850Akz330
-02000G0gMC10010000W0280D_c1008000W0zyW1020G008W4NW1e08G02G01400O523Y3C10
-00io600E9yA4G00G00000W0000800080080000200400YBa142G0JMu1000000no@@7rtc6C
-MP20104180G800000X0000C0902000W401200000Ga0000080G2049NcGZ56SLu3YcQ0_@dA
-1000BFQ0W000020001000208200020G0X0e00008400019W40800G0OWW04H00YG20041000
-O0q0O20402oU81U000pXU5G000m090000H010a009H10081AP09000400400Y0084000I200
-0XX0W0000920ELvXvGD8jG300OB_NO5@@p304000800002G000e0aG00m3I10f20i4A0GY5G
-0XGHe0PW0G0m0198816G4O20G020G15QWH01W1W00G22140G0000e000G0u0660MZ0Co8C3g
-U2WOW0008WdUOW004G400X0CGc088W20I80G0320804GG4W4WH6D3202140442000H0WwFC0
-0001000G40W0jWQ0000G1300dZs51000004W0000GWIAjHQ2000W04012000a2A1m4h60098
-00W0400e4000G020f00Y008Y000H00002000htrMEpPdj000441G0000024G00xmQ0041000
-01K00000G0W0502000000G10080WW0500W00G2800W0030W00e000500G0000IP1e1qJ_hL5
-W004Ndo0G400020402000Y80St930W080G080A440001008800000000B1YW0Crh18000G00
-000100000Af80WvHYwAN3020000W200IW01081b81GA0G08W0G1000008E29Gi00cu8Y04G0
-G02W2G00200005100000IW01000021Wa000080008b002000000ikqc4FfCX1010WwaPW8K0
-0000Gl000V6d000K4K00000m600000090020040200002S0W0000882020GG0W80W3WqUD0K
-l00000009207aW40_8WObDG00000U4000Wg0004P604XU0WoS0e0d180820W000W00_000yH
-K00082O6005ag0000WPcBGL@N4pCl8cP600yF0y@Vm5_Y0000100003910WXRZ220000020O
-000e2m000W10002000OC00mC020L0C0gI1W10e2W003050N0A000MH0KWY0e0S1G1u2u2m4m
-5X9W920024080000B6dMd000cW@@N20_@@mo90_000_8605S600e005BO0000A02W8aF05uC
-0080000GU0G9r6000140p0m@@F0680u@@@@@@@@@3@K_4sK2900vUzQdM2RIy@@9WKD0k2Bg
-quDOy9a000G7O@6PqJLf@p00e3ACy@@I@@ku@VB@@@@@@@@@@@@@@@@@@@@@@VH10eZFSTKB
-Sv400000dD09dBt@@j0000ZE00G5PXy@@@@@RC0002P0005vXn90JaKWYDxBny_GEfv@HY_@
-Zg@t8x@Bw_VYm@Vey@5I@@Ws@78_vBxRG80Gq4G8R@Z1OB0Wa26hFwAIAG55300zm@Vet51K
-K1OP@07IyXk4V0000h@18W@@dSzD600eeTx0anjB1G@5W25@FCz@@Y@@ky@@@@@@@@@@@@@@
-@@@@@@@@@FBy7wYZX_mbeKSC000mqDt3vZpJMuXKQN2zXN1001Wa2yu5z4o7Fd0x@7u02muw
-9Kl_3Vk@m_r9ypk1FjZ10G0WukT20GQpq0OakV2LX7oX5KrzF3WtE0EIGYomDuDS3s3FXS0U
-8mlDYmt9000m0320_@7ZfDmua@7Y28aw_@@@@@pm@@@@@@@@@@@@@@@@@@@@@@@@Wuez@VO0
-0aX52dJ3OvHeRs0CZ1OggF100Wx400u@@bcGpWZ_S20mMxeuLK189@pxHWOjS283b1cm9W90
-EA18Dm4s3KYgoEvd_700W04e@9fyNnG@6aUV20007WE00yee4J_dGr0jKX@L00k@tZtZj@9P
-6khUYC1Wk60HJeoZya0080ONI3QoqWYB@fSJ3a940Kj935NQ0W00W5BJezo4cja100085Rg2
-000aP1I88p4I1WYe0I88b7S500ikIKhzx40Wul@@@1880m1fgyEw3f0Gna39SgQ200w024eY
-tIbOeq708G0aF13XK8nvf6Kug1jj_GA0K45W4XIa000aIG000BmcGBi6020WOQL6YXD100Y0
-9k8n0ba00I0e307I1WYe0auSK3000GhS00u@@Jo9bXpIDufaJ0001r1W3f0GHK0Iy@V200C0
-_@@@DiK7KA0m_6LKBBU1ILXD00W@@BwV8j00yNs5DL@@x4m@7W@@N24HG8a00W@@@Fc2a400
-00m00e30640W143W1zcRGA0F45G5L2m0Wh6mi0E9LWG_@t004810X8G480004Y41100W09G4
-40IWf0GHK0d8G000W74Og021000W840m@@600892019Y400004aW000009H220HI850AY2u4
-90000m08J5G8000E44000GE4W3001d00m@@@7N@@lz@@dw@t9@@Rw@@@@@@@@OyrU0_@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@Vjs@Jxz@pY@liv@7h_@mk@@hy@xQ@@jw@Fh@a50004Vk1vd72
-021W@@D0000ia00W@@J300YHX_6ael1lJdm@@F8G00u@V600yb_@FR0P00Q2Wa85U0ug0mh@
-i180000004W004W000pFOm@@I4im3000ePC00KE@@8000_I8X1ACG00GGA0I4zl72bU0cxd@
-VHO000040W0WpHOe3030100y@V800wXpU0iZHI0G0G0000040010000G000b203Xox1OC4Wn
-vlwG4365vXK0aux_G000Wx000e5@hW80000140000000G000G400008009a20300I00002ao
-V800Y0Yx@A00G100000280qoY100C0000W00Y085064200af0995e5G00004010000W02000
-001000E090400060u00000800WH0CW00006051000010YKm3A200@@JrY360802000W80080
-080088040W000040001H00G0K0a00FFaGI1U008_z@@k41H100G002450004080G400G0020
-Ha2W18A40I1mWyC21u61m@@Q10LUm31yF0YMLF4Tco8QLfo3PAZ@1WAFyWe@7WK0C0qggY70
-00@300vZuXQ10Wieqo0o020a1K002e00a10083G6G6WCWE0P05WK0O00083G10W@@t00GVo@
-@@@@@@@@@VFSk_@V20090I2B10G000Y000000880000044G800412000O_A8IbOw89sc7000
-40W000014GgKLqN6304000000G205001000800001G0001004080000aG3m@@RCf36d2Om60
-DS809rMPm@@F8040eZj46TA110000404020000G000WTSbJRiFr69_nmsS64fG5pCPmHJ6az
-06HJb02000310I8G000G0010G00005010X420000PT0_@@D8200m0W0W4W0Sjt9000WA5Zay
-fmu@VO00OW0004n4004K0G0Z000JKa040WWlzO000100G000G00BLO00coX4vKv@VX0W80is
-X17POGvQC000W0040000030040000C61a1mPD0hx9NgL90040eD13IAaXphC0G80GVb60000
-qu00GYSdy@lG000G1004X11cHW0CAW00WTGIudI3G800aGY1008008000020u_H300uAd8dA
-1ain@@dWO1000H0Y800081m4PVQ00002W0G0rFQ00G000GW000m0000280G200000O000800
-00OA0ASfe@@L10005W000200K082000000ApG40000fa2000000GA00H40000a2490008IgK
-0C0000fL40WIvCeFXMEEDa@@91O00GWSC000W2808Am00A41Ye1ob00W2000vF0100G400qX
-ZAW000U7Pc@@V0W80W00050u00C00GW8008822001W0C2O00YI0mmaW40A0O0G0M14GeW8W6
-10000N46028000W38HkGMeHb@@L1002414000W0G48000LY0WIW81001001220000G41W449
-0000W4000cS30acvC8f0O_KPcVPD00GI300WD00B0040002000H004G041w30GW10AeF0418
-0e0W8G4W02MA0601K0000EIYSg42x3208G_@76d7000GW7C3WJPA0rFGE94jg08w3FGq@1W@
-LL5LL50UuXeLLLHxF000iL_GYSdy@lG000WL00080C000O0000480080I4O2m4m589WEWVWb
-ez0FHW3UY0@W41_1_1y3s3u7u7mJSFWd8u0000PEe0a8t9br_040000300@@t20sH400GAwe
-30D@00ArP400088LLP6@1m@00WPCZWFu11@JL2cfC4KLgKbgKvX7eoCpGm7U0Wg200Wji@@@
-@@@Y000mJ300u@VRgm1c@@z6uQ2m9l5DdIE0001wacXD0I8CS300080000Xm000G04WYP89I
-vDk@s001019WdG7uO0000gdE360pWcpD0004W020100102800000G80020I80m@@9000kC0x
-4knc10002@gc0008W4vCG080mWsFW00000o0GKv600W004001800WOMDeQRC0040A000OME6
-YKmWYpDeHL3000KW002fgz40MK000GWukR96vpW1lV0300mVpHjwh14G01000WSyh10X00AP
-d1000K8200_UrWcat00002040WCtDOqT60020000mwvT3020G08W40841mtqy0W050W00128
-010W8Y0000W820042000W@PNwaaY@30004002000W0v@@74100yGr91tZ1G000001aW0808Y
-80oO041o9220100ZBD0@@3J3m98300WX00mAm9qAbG08000W00Y0008yH3Ait00004p7C300
-8209C4G4H004000004iHaAMns6440008H200W008008oU3a00000u4w@@J00G4C7f160000G
-0200a4X8000002Wj7V0a00mQ@p0G0W0200000G0o800G1GWX80G8cP40J2L3080B02000@B0
-69a400100HG0_hs08000m820m800WKW10500mcsC000K_iVU0G4100XaGH102Y2H0008420W
-f4b08000WAyHIYeE1G000000G0082G4X11pC70000500GC@@d00A5W@@j10Y8KFx6GA00eaV
-3a000000agQS300ezVwO812O0000100W0p1O00000I500f2O0008WK0C8WE3Axt60W10000e
-cZXX@hDubK30GJ0KXd7vBoGvx68400uuR3_Vt00W00DmRGWv6y@FC0050_@t00GG00O00000
-00O03uLU38000WH400000MeuRSGl1riR050Y0X000W0G000C00020m00010O0000WEG1H212
-G70041018W26HG0G08OfzB42W8WGLP00WjQCvU44R2000G0005WG00G0000W0004400NMR00
-8HG00G4000W0b01001G1920mQ@p0010H00000GXQsG01O3000014000000KR300WD00000cS
-06KF4WK00208K0I8000WG100G0Y0eW01C0R0GlR884iX204YWG0m10G8wl107msT39at@C0W
-80Dv40Ir3kZ_2CZgGuBG1uCU0mk@@760O600en6000guB50qCF0eC10WY_B20700000300WO
-000mT000A0C0t1O0GWS6000100mDQW0d0S0000000mD00WVWE1qb0000S700uEmFmTmU0u0@
-000x1GK06ywnC0000006d0m9d0WPUWJcS2pym1sO30DJL0IL0004W0m@@j000cq400WCUj00
-_GL0yG06HVuK8j9Mv4MRs000QPdyknyoLaZQB5xM4WP7W1xXSTx4Uns0000SI000kD6ZZknO
-kxVYtsWZXDu@w40810yqg100G0_4tWTkDG00000WjL0002f77oaLFixj1pQRmGu641h1tTZH
-ZuC00W0urB6040H00W000C000m000400000840GG08082000028G0200K00000q10y1T8020
-0QvE11G000000kysWLnJ8IT30000ko690408010GiRB3W0088000W004uKS308206BU200H0
-000WIC00eLS32jUZEtP0002GVN6CKk100W0o0t020000842Y_RZonh00020H00000G00K0WI
-vr00900020040000m0GG0100W000005oh3wH1xF001G8UT9kFFXfivH600000000600@1dGq
-z90870uIHUcEmW@@JOYC3w6@aCsDefU3ktt0000800J0000G000oCQ7300A0000cWU00mmz6
-aIF3NudmSvRyvl1FCQ0000G0011a800H000c7fDpsR0W0000004HzdGz@6SnQ2bBJI8L9CF@
-300WW4100Ccl1CW00scN505005@p080083040oX04IA8XNcD0qm1G_xs4tl1nwR008Y80000
-W00100805rNBW000000100W04008302W800JCGI1CG11HKAW100O00W800000qc04GrBRKQD
-60000100CcyU2G4H001000XGG008ZOEeg00GAOu@4w_o00800WI4040H00W8me0R3480000G
-aUdk4Ip@X7nbO4R3U8B100400O0001200004X8G00e8H4K8JXPAs202040850000e0WKI1G0
-00008rMdCGAfWu@V30_NGrjk1hk9HYu6izV2W200Y@F1085K8000400IjwY1a2W0000000fG
-CfVO0H004sM200W000244zV2001GkMt0000CK100Mu130020zb@mK19040000001eGW00W00
-00AG002Y00000280mXxj05020E000800048Q86010e14a008W0000C00GAK0030000en04W1
-0000G_Z0WW000W8FbcGrsFaQF302804000G0W0X00110K004WGG0060003m10G01Y3OGHfpK
-S430124GWW4CPl1002W00020Y00eRV30OF0K@jA0008ATqWjQCG0G400000W404080002W0a
-5d1TUhY00008n200WWG0m00G8wl104G2Kes64m0R0000GG800004AnD30000YHOB00004K0G
-WboP0010GRhF000W40042I00WDTDW0mM006WDeG@18004X202W020W0000gjH10m607ntY@4
-1WW@Pm60UD10KLPi100eg7Y@F100Xm@@Z10@pW@@F100eg3000JKr30St80ua0yllA000nP0
-0WxWi0m1_100c300060nmb0C0uW4tI0Ke3000Y000_1G000MJa100004H00sqd1000m80000
-0J0Z000m1C100o2000E00Wi300O703mFGM04GsS9yzeDK500WH10gn60agPyA00e_xKI0000
-0h0005K00X_d3LV10L100w6100G1peA0lZ80_oHMU4p@C00OVIDVlK@b8isA00p0ipl1hAfo
-CkICbG8L_o3000OA200fE@G@U_5@h4000St@FdeZP8xlGUsqW4mDeSy4MVE1080K0010grEX
-JtV0KE9W00G10000zmb0008000a00W8000G0D@F3BcNnBP9aJe4rXd000WWOlJOkh4003000
-00POr400000W2000000W08eAnD0100000580020000G5508Dmi4xiQGWw6C5T2ndRGgw9yZE
-3jhBHN5Laa536000000200140400000G0G1G0A0004000002108G0GUx6aKj100CLBPrWHtP
-03000180000088100_@F10009VgN1Q00W_e9vO030004apV2000GIdMYZeO0000nYT60mw5m
-000GKVI00IW8yV6EsMYl93PuU3AdpZgoI8oU300G00001SvQ3Qps00004000mb600SOP8zsR
-GnMIy3E9pMMnuz6Sgh1HsR0000Y@fDW0000W00mvhD0O02000000CkLzgG20W0Wlo@vuwDW0
-800304uZy72ztWN@D0Km0mj@O080004G0n3gTjOl1Psd0008WQ@JuB_4000W4aI500801080
-CDk101G0RRtW1PM200810000W00W020G001010O0W0004W000W200GW00A8F100102400008
-kS4E6PbR08002028000800104ccg4VfkHLy6000meCUC0G0000c0eST3G000000e00040100
-4110I00G000M00G0GDSU30_w0y@l400WG000A1G0W04m0mw1600808I59MOtWv@t0008LtiI
-4yG2806Y00004@k14I00U0m09a00000X04G0a0U20008i200y@l4W200G864a3k10GA1Qrt0
-8G4Wf2aGu_90021O@@DMMzXSvC04000000Y87C00GXHOu6Ctl1m800000000CW0400G2u602
-e000mcxxeRK_l1HWd00W0Y_mVu7AF000W2000G044GA0FSak1A82uG001WY00O4030308000
-E444e040c01G4e0H0W0I0G000W03000m23Wqxh0AWG8Xe88000080WWG040Y10040WW20WW0
-0440P@p0G00000A02200_N2ZtGh80U30W0G9081gWU600050GW0000110W0001W02000000G
-200WNX00GQnL08GW0G0G88000410020W000W0040000H000000G500hdp0110WwSn0020Y20
-0WBBV00W000208W0R1084ooUB1a500000KG@0484IG9Hy4K00309K000GWv@@I000WL1042s
-G102G000O0000PZ0W202AWKIWS9yqO20e4000080010eYvPkft000WAB@R00@lB0W70X9N1G
-Q7Wz_z8HW4Y0F7000OlI@00G0000C000u200u7WBG4060K08000g00002000_100C3u2W045
-0E0XOtC00002g00Wuch0100k3O2K3a50C0300WE046k100y30000G700eyV60o00000a9u0X
-00W74_l1m004sdc100d_VOlHdT90000CJCvs@F1mdE0pz@JusmSkO200G00000A100eyR600
-00220Xe8n7u400yxD37V@Gmu90040O@x7k0@XRmLH010mzUj00uODhlVoLtcOmJ0840myoF0
-880fqw70no0aAu61ZdGSQCaFO57hJ2W00000W000WG000WCvj10008008000208oy4EbrWOp
-P0000gO00W4tD0050mhu64Vk10200EILYa@9vOO3khFXrkPeg73_@t002400800MXnWEpD00
-008001O0400W008Ylt00480002000SNZ000OJS3wBF104e0ridW0WW00G000002EOdXar2vk
-_4g8dXqtJuxL681000004uv_4000GW000400XmysC0oaGODT30088Ktl1000GYJEX46Ou@@J
-cHwX@@PW001000G0W00G000000mG0008eXT3ggF1W0040500MPF10009000W000G5Tf1G000
-0010S8l1b@b0e0000G0GG004UVNY3x@PfjM008IFH_3200W800020009P_4kAdd28dfOV3ot
-Z1JJ90Ne810000900020G0000PAI00uf0sw_N2000OQ600_@d100300000G010O000P0U6k@
-ScrLj1000uUrF00W6iTJCaC04qZV2@RLnkgK1080W4G00800WIzP0G13mV_6C4V200G00G4I
-W1K62W20GNv6000000C1GuhZ5cb10080Efd1000CG600_@d10K400O4002AGG0071W01Gku6
-8000uGLp8020G0008sj7008eKb832GA10100020a2Y0aGFz9GAe0O8tq00K802e8AFn70OC0
-y_l1G000Y4F10WWGNw@mfvF4zhMG205WCe11002AWz4000GAD22OaT380000082000C00GG8
-1008JeR040W122YHY002AfygO@beC33_Ic100LDj@d0Y00G00L0000K1A40iZY10W0W0008K
-hY1FXRmKoT1008p8400WG1WwPJe@V30yv0e00000800180000004YiR0W1805gj114mMEuF4
-vSQlcPGpzC0700ukV941WJQ20paAx2GkuCiDzO000GD00Wtyc1f@d00WCv8_Dm000Y1W0078
-300OF0o5F1O0C1m0W3o1FXIi7hRwA0FJ0afd40C20rD20wmCs500StUxCyszIdvh2000qC7a
-ev8XIbUZYcDuNO6swMYxsV00mdJTnUSzE3BDfrCxU08h1uIFgsWV3100400W000H0ici77X_
-G8xFKDE3Vi@pQgX40k10002gPt00G080824008000809_y400eT2004OlT323tWoSPOsT9Y_
-NbLrh87S3Uu81000W1ypmGz6SOV2Nsd0Of0WLuC8mU3Ikt0G0400040USoWrE9f6V3w_tWXb
-Vu@VF0GG0qdl14G00wsB10008tsPGWy6000W64080200WnDDua@Gg1tZXu310020W00Wmis0
-04000m8WAsDuz@400qP@Bk19xd0G04000440008sWt0G002B_JIKSdaVU8vwM1WE70W000hs
-dGmz6y1C3fUIL_TU0400O_T3w@t000mCQ200UL@XQmlglDI000Gqlh1V_p000wM0000rxR00
-00ezICuZdk0W00G000eBvAU@q000010400sQd10h60L7qI_w2zam3F_p008W08000G000100
-GavV2000uf8000002gdV301010000000ZmswNDXf1xQoGKvIG00We6C3A@F100VGW040sTb1
-u000200WQqEXz@IBIoD0lk04xj1WoC0G00008W88EH@ocj222W0000G80000000i4S3Upehg
-V3va7900uH6CV2G4000K010YG401e0HMcW5X_640008400qUF30HT0AktWfvJ0G80001GWYH
-xAx1Om0800000I800Gsy60M00m0e1IM6lzyl400Stp@F100AoL_Z1004Xq4rAWSC00W00002
-0200mZqC0A900000000YB00C1G002W00089000m00mpy64e1LG100MQ730mFW0000000e6@F
-3000eD300y@V200W1C000KFIZ000000K9dVcATX@3040WKij10Y00G00G0020pyEsnEs000W
-3i00msjfLKiD00cDEQtWZtDempPI@4ZgpPu5D3sFt000200802001G8000w6S3IDtWnoC0G0
-3IcQ90018G00GW0000mUZ200880W00ijj10080I27Zxh29Gz4MXXXogCOvU3YWt0018G00W0
-000880200W06nCJC00010100mtv9W01G00221000Q51000GG2M1t0000G4080kpE1G00000W
-0sV@100020001UdFXXLD0080Gs_64Nk11hRG__6yLk1BQR02000000e00Y08W020G680200I
-aT90010G0300G08G000001800040000Km000WHG0000wfO0004002qGl1Pbp0020awfPOg_4
-oesWrwD8hZ4QUD14000nv@Gjt641R2Vpd0000eAMC8mU604G0rPV20100C00008000mL0000
-268W00LdR0021mmep1101GbuOa@k1O0000008W2088JV3El@1000WhBP06W0WqmP0000cq00
-WC@D0W40000200009402SE9yaH_J0W0200040000YG40062i200G2jvpGU@6iN_30G004002
-8000102100GGay@J0034000019000x@R0380WIyWf@@40G4H8800ORKFExdXWxD0G00Gn@60
-080000404G8000Y1G000YUd1mIH0buR02G2010002020W00WC26O20042KdXDuJ00W08000o
-2JV0000by80WLJJW0001320mizDOnyMw@8Xzph080400001G0W0HvRm6z6004H00O000G4WA
-sC00000022G1082u0KcC89000Gquv@400uGG00G030WW120984G0G006G04408Y08SUL00W0
-0000XG000X0002G4H3jNHDd6004000G006m000A002420Ard1001000G00002Y0Y10002041
-00C200j_d0m6BWY@D0042004W2Z010A9G0180000G0OPV3A@tZ8_DeeT3G4H0rCh4foZ1200
-0400GLgP00WaG00500100sqs00G80Hbo0000Mm300Bc_mcj90010O3JF6zm0000G00H00002
-G0W08@y72KdXc_b00G00Y20Xm@D0049000000GC013B10W6sX7t0800muwU000W00G000W00
-50000014_@dXh9COiV3oyL20080L@nmYY6000004H0Ge@6yiF3WsV0s_t00G0H0000IDt080
-0001W0M5b40W20K000cxt000104WW0I0zaqRPOUU6MrnWCwP0000DP00W@@D00X00000GGA4
-00008kp4610000W80QjDXmsJeI43QcFXZeP88P3m0024_l1W40000e0q0W11j_GUOFKyC3tr
-OmDgX00W0100000180041H200GQCsZmtOOj@A00Pzbwl1GMV0s@F1mq70lid0Kv70WxE0lwO
-0000Gwh20x@V20iE500m3ORi98j7JbhZ100000C10KyE3000050004Dh1nmb004C0004jm00
-0wgF10LB00C0C2fb1000uW10008000m0G0W1W102030006JJR000G42000VaI2W900WC020O
-0P020o0K02v@VF2Im0WxE0HNRmR26yxu3kZ00000KryV200YhNLm00WS400L_10e000Kv706
-0GKO76xl10ET0AfVijlbOOzAI1l2000aQ500wAsZoqbOjB3oJt01000zad00G0mepL9YLL00
-02s5hJ@@N1GW0Wg_99HRC0aX0q0CC9fd00G000W007ad000GWdcFffPFI5t00400zYR0000S
-V300vWRmhD60080yMU3A8mW9tLPaOLcsEXRmPuXT6YN@100vNFbx1200W8ph0100mJ_6aeb1
-W2004101Cdy900O8czVZFzb0u62G__60000CdV36wdXzxDO8_GouMbhunei262at00W00LoR
-0000I6000fopGtK6azG8080026CXLCC00q00200esDdyaW9RIu@b8_F9Z@F2v@YK_V8c@3ov
-@@@pve@P0040CHA3Pp_0OR6WqxP8PB60008Kj@6L_pG9@U0W000480my@6qGS2X4Rma@U000
-80000100041300xVQ080WWJHPu2w7_b_Xwlte_U94000G000OMy4w0mWK0O8UO6s8@100100
-0Sb100020002020Oc0900W0eyQ3g5WX@7GgIxDM9cXVYP0S60GrsdKk@32001AvkYSwJ0800
-W008000K00010G00004008xE30m000000OKQ30000W0080940Q3l9i2j1jWd08800000utfQ
-mf_6CXe1008eYskY_dD81w4s5t00G000W001G000Y00gEV3G811I22088S3_ps00G0088020
-0H10G000W08Lt@60284000288210028040W0s7mW1CCW8G0000W850121cR00WeQ0004KW00
-W80025000A00nKy6e00GG00W1000120G09rR000W01KG0n@P002A004K0RWR0028004080PW
-002000aG0G000a042WT0D0210W020awwD0110W080a3HDevS3040000W0X00021080080000
-8A_mt0000601000GX404200018000000PE00044400W000W000030010010C0006000400G0
-000WGD_6Cej14X0000100420W0400200WpACW040080802002heR006000440ZpR00200000
-208W00G00080W008000G10Ge00004000140100100082004aG0C0e00sQtWjiDOjP6000mQC
-00uzN30a20S5X1DURm5m6a5F3GW04cPZ14000ZlR008W0G0H08420G0WKiBl1VzRGqpXW004
-8ZU3a000ilj1800Y018GG2Y0u5p4010000eIjER9MilYVyPuGm4000000H0etR30002zyT2O
-021_sdamODuwU600414nl1TypW910WkyQvxoA000n0000100GC0010G400pzAHtrL004GOwt
-70W01010820180000Y5zJ0000Zt00W0HjvDJ3Au@10002000Y00W100W0GG0Wmh9U0410080
-WGU@FG00m8fy7EorW1DJ0082Gt@Ry7X1Lxd00W000410R@R0000820000804m00000G2WWW0
-0G0G804009wdmtyIG00e0944004000K01RsR00101844400440100W590OK@40Ww0aYz3000
-2g7mW6xV0030Gj@6K_l1K100CA0084000e000000G002G0I2GG00AW042W00W2120WZiz000
-W202800GH17cOmj@600900534gAeeaj@P00007@00W0tJ0004mD294yU5rZ_m4u600W0W841
-006400C80264W841W008000I1GzDXCoV2BSR0000001G2000I10KG2020uw@400y9FCv90G0
-80G2000040a82000G821100010840G020001218400008aGA000010m0W08gV@4Ucl5G004D
-1PGm@6KdV2W_B0Mq@480008200002Xe00000OW10000G0060GKH11002ZICA503UJr0eW80f
-NKnbfO00018pV30G0005000084GP0C0000YJ00Gr@aCSk10040C08WA80WKW3100001Y10W0
-Z88OI01G647a5020108enyP000WIejR000011080800WfsV00208O00WTqP000Bsw@j8000P
-ZT3gTt000Y00Q0002G0000002GW2G000000zA00G06A0G000um232wbacaC0GW0B0004W520
-ncd00208W00001U06@@44T0100040W048400002Gl3080aX2zEWWGG6A0G02010100Xe@200
-08GP60GMV0aGJ2000YG40Yasl4000z10000G4H0o000GW1WnzP0004GQtC0000VngV0000w0
-00G_1000400x2u9E1mh1000h000t1g000m0020000G40Yw730600nRR008000002000W1000
-h000INO0GA0C00GrVeT6A9t3WC000T080_1O0W3u200W1000S000uE00mT0NWx0C0m0w000Y
-2WWCOOoxGO60000108mS6IDFXHxDu@V30yB0q_l10WA@2p_ayqhe6V3ym@0KmT5NzRGkzI4q
-D900003IHY4gRf8SIMNpWidbeK@4E57Ze@D00mI48GGW@iF1840000001400LfdmK_6aMl12
-010QGnZWkhObRFAPt0WH104010YD@A1000tYRmLA6W200OsSFkPl2000Ko420IH7ZQvVO9V3
-QVoWntPehS30024y@l1200WMlt0001402G0AMt01100@mdG6I6800X24000W01000WARvb00
-080iG00XSRG4u9008s4000040012W0H0000kbYXPqb0m00mIzaW028000G018001G008080H
-010W0200Z50W14G008O008008004W221W05GmYP60000n00WW00W0000XA2A00404XW03OKU
-604u1Czk1G0W0gW@1000120020004SDV2dbR0080000G0W000K010i_l100WOggmWCzDG802
-00G008004Y0400181800G0200a200000020H0000011W0G0G00XG3CWpqDGGGC4080024000
-0e150000003uHU6000mvO020080040WWsxDeET600020040uga4EmdXDwVeAB3_lnWDsD008
-0008000480TwR0KA000m02G00400040010000X04GWW1cCuRV3Itt0100CKYG0400WW0W008
-01o@@600GuDCV3oUmWfvPe2C6_@tWe9C8Hy40W28qw@3v_R0400XQ@V000Y1OW1WmrD00W00
-0G000W04tsb0044WNVI00WG00D8eT@JucU30@f0K_V20001kbtWz@bO229E@7Za4DedF3408
-0ycl1n5Q00000012W004000X1G000080100XG2010Y0W2Kk_AXryJ0W00mRY60006YK20004
-0WOxD080G00090a000djpmGcCSAv61VYne_600428KG3800800G000020000m@GDump40000
-0IWH00000430004W0200A_@t000Z_L@Rml@CSh@3p@dGW@Li9H2@@7YG01aX_JO6V3UkJ208
-0DG000G0084843WZB0ocC10W0A0Y100120Kwl7hvbG1@6aa23HbQmiM9W000SwV302W01B00
-00aG1080000W04001015400X40WWm00001W0400020004000e010eW42GT40W8I02300X40a
-5c1C320Yep0W0000G3Wm1XW0004Q6L66@mW2OPeiE30000EbA34001kNr00840PGQGf@6000
-1000A8YeG0098X040Y0HWa02G0WWWK0000O0400804H00W2e0C0G000W0810348B44GaG000
-001u00040408G000000gdpIr0000104W80W00002AiLM90018000020G0GzgCyxQ2@4OGsh9
-0G01epr40500000020018H0020000W400k3b100800GA4sVD1G000FzR0100ojDDO@V30wJ0
-4SB30G08wxuXi0IOZN300G45AR5@@p0200YwUVej132wbX_6C00000G40WfVP00GK1e00XSU
-P0000jp10WsUPehr70100K_h1DJO0800gsWD0400mWmX0408u@V300AW00H0WW020051WAUD
-8W23G2000104Og438000skh18844c8q00001b1R00WAfmTVuKM66KW1000W0m08WW000000a
-00000W0WutIupM94000000Xw@@40G40XW18209100G1aRLD000GW00G004028H400081qWL2
-00XO8221CA4300000CfG4SC38080A3mWmWhG80mW00WW@@nOas4_CoWUaD8U53090004G0eO
-P3000m20020GW0Y00000X20000G0G0000810000200eaNMD00GW420G00K00nIQWD00WcZP0
-H20GSlIe000ufL3o7WXOvCOmhDoTB1000400@@0G4H0000W02u70820E000eoT000G00m307
-00SKZl600000@04000WA_XA00WW2_@F100Fo@@p00GbV0E00@@B1Kv7W@@z008hF0_8Y@@J0
-00N00040O001PJP0W0000N000C0C0K1O0W2m000WHMi68000d1G0C2K1W9YC0002000C000w
-0m000e303000006000G100Gv20BOR000P080G0W000W100CXD30O00scsW6QDePE3ocBX8IJ
-eoZ7Igs00W100000000O49j100WK5GL042a40GXx0000WA000Sy300000Kv7g00004GV0000
-a100G6000KS200hmP000820u70000_100Kz@F60K500000u100u@VLsps000027WpG70Ey@l
-7000Gr400atgA@@BK6F6Kne1xVRGthICIz300iGBBJYApn8XSI_@lN2008TjR0080000m000
-60ofEX2Zz0000n3uC00W2e8_7sM@X1CzOOU3MNsWRVCefy4_AF1000W001200100W041W000
-0040401W3HRGOx680014W00mcu900W000mUq7z90W0K0000402S4W000ndpGzz9G0W0u1PCW
-00Wack105W0_@t0001Wpod00G0A2000aW02GX00W088000W106WYpmD8_N308X120O2040W0
-002402m0880008G2jHV2Wx400020W0E0OqU3kut00500V_RGAS64iZ1zjdmNs9K@F31tRm9@
-6K8b10190W000qzk140Y00400Dsl105X00W800002W800IC_6000418010O4280800W82W_f
-tWV@J00005510040G04000402100000801mvf6Sbl1G010wdF10808X5Pm7cI0W00uGd46Ic
-XPwP0080W0G11040000010W0A09000C0W00W20083400W06oB10014u001800022408LU300
-Wgr2R200W10400004700GGmc@CSlD3vsNnD_6i9Y1H1o0000IG040HCPGvsCq8Q2t@810G00
-802001G400202001e7U30kA00002Oxy4WI000400A@@Y0a00000000O2mUw6CJb14100shA1
-0100vU@mVL6WG000001200020804W810000J1O008v@7AqUZUEbOnEC0009G000G08C2100m
-pdJek13MfAX6vmOHS3W4244xl1000NQYt01002XpdGKDgi@_600G00004090000000Y41W4l
-Pu@G3kZFXvvOOXT302080000004020I400000Wa60oct00010BfRGNC8XY21003M3G440W4m
-CWW00W8G000000C00mrv600200C000010XYRP00W000002a0010O010G0aW4A4WC584000Kj
-20000G0006004000400240GWkoyufzJM6q001m4G10085088000uYC30G0000OG0118GCa6q
-m@3080P801020e818GG2Y18210K0000000SH32000282000W080G02G000081WG108a2Xc0F
-100G200828240Sre17udmRs6CGB3BZR01000I10e00008W0Gy@l103J0Yut001905jRmbZOS
-Ts3Tjpm48X02000G00GGJ60A40u2U3MppWiwP8x13000W0030000W04400004K0008mB0208
-00OAU300HGKE_6rsNnGSOqxU2W0000004A384444820880W8400428080GW400000enm@F00
-8m1041000W8G201401G010C01G000GHulRFKEN29_N1HG4Wn9bOnOI0G220WG000W00060G0
-80Wx@RmMuI000M21800500100K0802000W0G0000KM20W80Wx@J0H00qiLjKIU2n6BnHl60J
-Q000i108B00m022DbcGYRIi_l10W_0oYp040022001Gq10000G0000ff11WxSD0020GuRO4l
-f11qPGI_F4DW4x@R000u36000Cu760uKJ1mF08hV6ixk0qLD640m000WP0WheYVg200a100y
-o30400000mFoy31kKqDS6000281E308000O200e3W002030C04XlPGYRC4zV200e200m5G5G
-6WA0CGK090C708yD300010108OHJ364kYH1au5WBk@t00SU000W9yy00gcQ0qa000000Gxk3
-0fpO0000mJsDe6F90OZ8a_F3W82050004DZ1VkRm5n6q1U5xidphtg8000eyU3QwtWGqJ000
-0x4tIKR_6pLMHZvLShd1zzAnNjOiQR2TczGPU9aAG29bVIPwU4UNKWYT0EeJbUxDu5C6E5QZ
-LkU8p_4Iol204008800IEtWpiIegU3000mX8000000000GY3wEPe9O840G4eD300W0010022
-00OWV36XqWCCC000G021W0G008W108000080G0u@V300mO200GG00W000W000500100wREXP
-YguGVC04G0qJF3G0004G808000100GW08000G00FmRW0B04040109W20008G00A114000000
-8G0GeX00gzs0aG018W01K5000e020080WW2002000W3N8800000W209W04200amjPOdv42yF
-10480vARGlzFqsi40001G004008W00XGW010082000800000a0080G00201L40000W0WZ0WW
-000006000Yo7@6G022W2160G0C2G0008W108002W00G0000iS1008400G0W0000130800G00
-miv6040GuBB3gsd1a000V_@mr@680W0fvV6wkZX1@P010e000G01080XfRGz@6000200GW02
-0W1800004G0000805I0eA93IMt000Ms0210000GG08eOG93AytZzBVum@D00E00000020Cmb
-z6KYU2reR0000100120Y0050020100G0808000H01W02800BlD10W21x@R0mbJ00WW00054Y
-XFXmuC8CuA00G0zwfA4010YmtWjyJ823340040022a000mL@6800GG4001041100e0JPOmiw
-6W080O@V3000Jm7000000010GYgrbOAO9oZ1cAnVOxV36_tWgvD000020W400W404001Yqt0
-2089t7@000F3080800G80048i4o3xoXHwnX4rF3G1100600aCF3bpd0040800410100ozEX_
-WJ0400qepC0W_10A20GkEgCmZAm21000000X245004oW69GG00040G810000804840C0a0O0
-0281106808I00K2W4GW040GW000Yf3S3GG0004000000bl1W0A208u10I020AG004P0_DsGF
-XdO9PiU30mW0KXh1rMRGjz6G00mW02Y00201Y002020I006090Y40Y8G08G10080K80WeG20
-000K80900qu@600ueW012410002411xURGHzR0G0WG004n0jj0Af0e2_400021010009851e
-00000042Y4410000104200004I8G000080f000GkeU2jpd08NJWsRF10008001WD8Xf5V300
-04XG0000O00c00WmtC004XX000C0000GG63100413C000000401qijD0041me_90000sD805
-0GGWZWLPC3L000001C00C0000000GG0eK000xto00OG2@_R0H0O2a00001n0K00000O00180
-22Y1Wl@D8qV6004Vlvl12202UcC40020VyRmDld0000Y010mN79iwl100080800igf18HW0Q
-4E10mAG2G00Iwt02000NYPG8S6y0j180WW6_cXe3CedP90L004@fA1yR0w50100080f0000G
-e00180004004WC7000005gT01W0440W040200002G@1080mW2r546k1nvd00001000yIW80g
-xSZ4uEfpU9000HSqj1JtBX62008hF00WV0GbV0000G5000000wRV100G50000We200wJV00G
-T_60W_x7W0000WnG_38000000m@0w0Kv@7AOgsV300w03RRWW00WRwD0u700G6030S04000C
-000W1000t100g1m0S7W10E030006000m100WA000P0K100W0W0ELr000000cK000W10002WA
-04mXCUSGd1hKbG8tXe@@0000ydl08YhpJulV60OA0azM2a10@QHt0KL0W2000EAtW6yO0Sk3
-00100000uh_xHSx6apW15JJrmNR00mj9A93Y1VcuUs00800400WlnP0080GQH9qGk1004000
-00AW000G00GErIy5l1z@R0uz00002XPgLnevgyES5NY7olm6KmE92300ky7Zrrp100GGAy6S
-gE3HAym2mCq6Q5HfO0000000Hm0000D200D3rCXTpmhqI00010000Iz_9SPd1Rbo0W00Yw@D
-eqV3Yzd10084ZzR00WW00000WS00080H0001e4T3Q0@XnhJeXJ32ydX3oD00W2mYu9SUU800
-8YA7d114W000020W0000002401W0a0000402010044051d1vgP0000Eo63020106Bm0241W0
-201010080188CS3Ist00010200201000802v7T3cg@XrMJegz7MGFXDID0080HzuCGY00000
-0W80400080W0204200isk1002eM1m0000K400000SO3008m400G8@608G04010200G01400r
-ya0G0000109000W004GasG2jldm4t9qSR2TjpGujC0000iQS6kFtWL@D00W0GTw90001Ayz7
-0OwK120000G0240000CW0brpmx@CSRV2XiRm3_944E3LF2JIH9qgX4@@p0000QU100dkd000
-440208G08GcbrZf_JeMnG0000A000CsRLczl20C1hBoRm2O6SSz6FYNHq_9qb9FjSNHAxC00
-U0eyV3G020Csk1G0G0YNlbOYV8jTL_T@40008S700QNt00110pv1p1J94CJB9kdGQx9ibV2D
-NPmyxF00GY4W040C080020G800000H000Y4e@KLILnWmxt00G040W0efvn0G00GVZOyLF3WP
-10A@t08G0808GY008000GWOP@AIkt01000Vtd000WWsGIO1xA000G1A018DGCott02100zco
-Gi7LuR00uzV304a000G4w@VO00H0CdACr@d0W002000C@_@GEqI000PfiQ68060ySnCx1x10
-8mXIOn0010000400401f_d0006WZ@b04520200W_wIWW20m@@j0220OaVX_oFXo7D8v@7000
-GY78000000420WlR9vld4AoLY7xb08000000M00007U@mw@600G287S36HtWlzD0H2Gml@I0
-00HEtT6000W8002eE03_@daUoDegjS00W94eE90nN0M@tWhhDW_000z@7mpmR1W2A00000@z
-30rTBnRm6am@600S3kX_1WC000408I4d1000We00008000G0G001W00A0200WAXXZnx@9S6_
-30P00I953P000JRgorsO00mNVaH380000Wg0OkUIA5tfMnJ0001G_pO0Cu0eGdP6Btce8z8I
-S60008C@V2000Gv301yP_9XzR000AWmvD8aV3UxEXYr99BTCwps300Dv9aho6_6K1A31cVIq
-vaKZ@3@DRm@@60qW0ODzMcbd10A00d1@mgcg4KV2000800K0020000G8010400040u020W10
-0z8j100W00000h50004G0W00W100000W0LQAo0000G0G10sldXDpz8VU30G00rtE9Lrd0040
-0400080G8s9oW@@DW800098000C0180000G01080000WMn2@604WWX0000200040G0020001
-0HCcT2bxd0028WZyJ00H0G56C000e0400msb6KSF9H@RGnC60A0040H000002000W000G006
-H8W01ebV3G21000000OZ1000020C0W40A00004O4020G2000008WGm0j@R000GX__JeZ_4gc
-oWLpP0000200090H003ggI8_9qdj1W001G0000W01W0W0000WbUUC000Y00002R300W00000
-01_Sj1ZkOGTv9qjl47vBHy@64Rn3Vh6oNrF0G0G000G020000080W400ULtWkxC0008J0_98
-00000820000aqtJe3830280q_F38200QZoWxyJO_QF6hKYNzDe_x4000400C0W00018W0Wpy
-JOfU6CFJ0U1E300204180a@l74000UtmWp@V0402GymUKXF3ruR000010m10lyR0Y00W7yJ0
-0W8mWUCON00Ox@4gWqWDk31080000W00G0HzNmmcbsqUk4PLy0W000009LTLo0400410021v
-dW80014142rrdW80400GG402000020G0098MGCs6da8yJuqV30010GW00Y440GsV900W1gx_
-40SM0qyl1000418080080W80YGy@904G8AHn4080Y02000104300000WS00Ge00082ivl1W0
-00Y@FXkKbOpT9WJ000W081008000W00m000G40W4G8G2002I80002080440pER0W000W0400
-00WfAe0yxV2W12Y4Y0084008Kb4400000GGPUV682110022000WHln60010OKq4cbNYwkVOb
-I38404yPF30040000IH0000084GPv6qSF30000008YSxl1TiRmjc6ClU2buRGA0C00002H00
-000G80100noaGT_6aNj1dvw1202WJhC81V6400000GG000008G0W1_DO@M3UoF1W@F4t@RG9
-S60142ew@4I4AX70Eu@V3010G200006G0mde6qFU273OmilU00q08cU3E3Y1a0000000m043
-W08O00GGmAF60008000Q080K20W2000eD100000600e00000WWQwDe9Z400000060400000O
-GWorD00W200100CG0W400008BW20002400mZ@6aVX1BAwH9wF050000040a00W@@DG0G0G_z
-9KBh1NwR0WN7W_@J000I0000K00P01fRmv@6C@l10G00000Gill120001400000G0G22mhGI
-yWk4208GIxd10808A0W0YTBXC_D00aD0020Ae0P0004GIXFXy0C0000lZXD00004G100cwt0
-45000004Q0mWB2JG00000GWiaZPW0mM20E09e0P19apGH0Cym@9C300udV0GWC0W0000000G
-k3000000TWx0CxF300gQ0000000p00005e00000Ae00000O6W20eW200O6G10lj4D00000YW
-700W700000y@F30000GL02GvOC0i8YeyUCW000izQ204000m18a3k1n_RW000K3010C03023
-t000S100K1W100030AeCE30C000_21000H008p088Y0m001820003000e000H400Y8W84H08
-0W0G000m0008A00G4200HAG4YK060u0g000x1000700G4100a1WW820208eSE3USFXY8teqV
-6kUp0_@F0xvdW300WRtP0000iW00G8Y000mC0QmF1W006P@@00Gb@_@D004HKd2600u1m@@1
-00000W160@@R0003W70EuLjJoZE10800PNx1uY7WxlDuJT6410020G08XT30020yLF9bQ@G8
-rgCp13du_GK_60000Jn00mS_6ydl1plRGA0CW004exR9EvoWFxu9SSL00qjsglDZd7I9NjKU
-_3nY@0uO700080008000W24aU2820GI1m002000O00m000Sm_3fiBHFvRy9l4L_@0000YT@D
-8ZT3gpAXQvD0000lb10W5tV8oT3_JMYQmJ00W00004WSwJ0001HvzySdl18000Iq@XMxJ00G
-AGIxCG0022800qX_Iibl12000QlpWFwD0000XG00YSDCe7BIsQQZcPJ8I16YjF1mW40jn@01
-W0WEmCe8@7w@n00040ReP00G00000X008800001G00PRPI000Wa8l40040oU8XK@VeN83000
-axE00eF_40G00yEU2RPl1800W0_De8V3gi4cw_X10W@MZ4a0108e3_7I_tWCmb8qZJsyl50c
-B0zBpGkT9Kc@6dc@0G00Xp7dfezJG200000Wr301mx@Cqdl1JtbmxqC0400Ow@42E2Z4NivK
-UF00igbqk4njlHL2H5U_600G00G8000000uY3400000WW21@R00W1WLFI0030000G00C0005
-01QtFXYuDW2000G8000400020001220000010Cm9v6CfGHVEo0000Ua1187wd006000400Hb
-PGJfC000003100G00040W0prWnP6HXK00W0000001000avZQQGGZRyzl7pRrIjmjKul14000
-0fx0Kqz3xtRm0oFyXi1f0GHltFycC6vslHmOX02M08Il4_@FXCxDW000Ghx9SrD3teRmzuC0
-000AXvPorFXS@3nX84G5ICy@l1WG004108y@f1d5OGmy9000YelV3Eht000WGpFQmKHCacy9
-hWknOX6izl100_RduNYggcvJhAgc69G7080000001GA1000000f401000008040I1GYy@D0W
-10G306aWF3f08n4sB10006019000082I08x4OG706a2W40IG0kAqWZyJ0000K306a2m35355
-0W20I42YGWGa0008218Y0008XGW824Ya4f0GHK0dKHZPD3OMwzg0w04OR43Ufm0W800DTcGA
-0F4a0U000e00W10040i0d40O0G0003850AY2uawCY2000902a0WG48240002HYW000GW4822
-09mK0e8AWJ4800acHK00IY0GUY810000vv90000GIad0Ga4I1WYe0EH200GR6s7V0_LnX42G
-0000000GM06AEXJtYQrkV000o2m700000Bf1047eF0xmC9z10008BeUv00001@30GM0_00GX
-DS2Av08RmbkFYA000GU700UjSZ7sF9FAj000000u@jhnbQtuAGz60HAm300WWFqaeFEd000m
-GL000008Gs@CyqP5@xRGse6KM_3GO00gpadQ@bOP06000000WR9T@40800awl10008014G00
-000140Glx940_34800G0040G010W80mT@608W0G000uPlpSrz37uRm3_C0EC00000020WW_J
-JuD03I_sWb@J8NM3six10010000WG0220W000000u6kRK58F0000z500Sa_3L_d00G0W5@Je
-uX700020W00ehS3gatWl@DOjmYEbEXi@D00WPzP@CqTh1dGpmjVUqxG22000G004KhuLAYK0
-2g6ZowD8DOI000WK_l1T5EJ4NaG800emw7Qa5ZE4te4tk00Sc6EE3DVpGxCsCfGHxG@08n3W
-WdVG0080800000400100000WiQC9Xyd0000qFNZ20003N10W1mJ0004H526Shj1f_72000Zu
-@D00020GG001000LxNnpvs000KetV300a@4wV28400U1m001W2B1mmQ_UWG00002a1000000
-5GJDV5uV1W53y8lUIQksWRcfAdS38F00q_F3C80000204LU2ZOdmI_R0004uXY4GW10SERK0
-0IRok@XaJWPVO3ATFX7fN2041mx@60ie0eKU6800500000245mf@de4000080010040G0000
-M00G0WTuRHK1002QF1000O0700_@N200e@_3GLcU@ae0EPXYM8000KnV200KvNbd13W00002
-0008000G400W80800W@y31000Y100O483080100020CBSBtyV2em5Wn@Pm@V1Orxy0W00iVX
-J_zTZ2_bGw00GbI8LC_L00eI3D7ZTuh8JZ4oatW_rDOHU6_hxXFxc9tV90vi0qyl4xgFsrzg
-000Ws@00m4yg0040ewV3kGEX9yJOmUOU6FaUFC000000WpjkyV8cT3E4@XLkJ0040GywCaTC
-CnMBHut9iUz60HF0o4ua_mD0004000a0000004O800G000W0I00180Y1000G00082G030aTu
-69jNHwx9CuE6000mOA0WK0I8xcR0001WlsJ8h@4000400W0WK00maz6e0008x1a_Ds000000
-06vIuNYkgz0100a0000004m0008000m020We_V3G0002W00OwQg0lF0qCeGVKg50000000r2
-600ozF704400W0W0WO0SMIN00YtFeI80000001WY2NB0C60fpp3810YqRGQjoDSF00aPO5Xf
-I2001G080m090W0002LwXA1_3300tcx_vX0W04O000q800000eIXNBWrA0D4c300GXy@D8bz
-k000G6In6ZDJ200GmPd1300WNS@U0G10O0NFcdUCGW00@@d3000100e8vx36000Gm1005xM1
-800aw@310a1m7l6CePN00UrZxd7500Ly30guN1000KvFkUj0MX0CtF60Y00gXE400G000m08
-200yqd1PuSL3tO000HikQI0000Im30000ym@@Q10uHu1Edk4dA0y80NalHsvRCOk100W0Y2F
-Xoml2000gd00WlqRvLx7kM@appv10GXylVvyjk1HXdGfvFym_3lilHCzC00080040oquF0oz
-000WWmjxLSLc1HQ7Ify6KWl7lpNntzC4Jl1NUd0016WmmPGY000220W@@P020010WGYCxDeV
-V60001ieV55ePWG02040W0nhFJm@6qyl1020000020000vfz400800080600WmhxF00W008X
-020000200Gzyunvx9000e100WGraCaz09VtBHH16qz@3WIE0YUpW7@JOY_7gKt30040jvOmF
-S94Xl1XrVIzz6iR@3J8oGEy68800uR06ch6ZwNJel23sCC18W00tHR0040m7qD80@4gv690O
-3VJS_mLdX00100804mbG90002K40000W1WCF5gcOC0ic0qu@CNHRGPq9KhV2Y000E4Nbknhe
-XN90000bQ_30000_RmWoVz02000001WvVDe2O6G400amk1RdJogxLCyg400Sdpp@1000WHmM
-10G4Wc@D0G50008g00100W00Y0202X00aW8080WW0040200W8YG040znU2no72G80W_sPOrV
-3MObXy@D0e12mx@900024012GzgU80000000e800000800820020000W00G00GD@68200G00
-10000200WG@@VIK0X0000K500m5y94IF9brR0bK2000000G90s7F100W2K20000G0iol1003
-029bae0810mU@w@C00208mMFM1t00001vWR020400G00XKRGOuCW100TGyG000ei_w91mNne
-sO000G1G00KWv680H80XWG0280WykDueV3G0GG0U00eQAOw@s30004q100USzaewD0000nGu
-6GW00HW00205000200DjPW00001GW0WD00028ey@V800a0000055W1v3x1006oBTb8N@Ag1u
-1q700000KGT004BU2000gR6F10W16@@J200egK_91uI0mT@j000o0000W06O00MG10CG000L
-_1m03mC2AW2A00L10WU000f2000O200O6WmR6a00mDuN39o2rWePs0004KFyR00W800WPWW0
-m0c100630006000e20082e2mCG408WP000HwbtWfp520pSJ_@9000Qy@V6O2000W@@10c1Go
-wO83000Y8CW10O030O1A0m3sZp0000YG0000G4HKVl7Rp@GszXaAU20M90kSxdK_VOce7W00
-0qZl1Bcl10G0WTRC81024002SUU2PuR00WIC00202040IWVZ0kIe103wuo0000Wt@RmWwC0X
-80O8U3_@ddS@J8hw40_704FU80800_DtWHtDe303oFt000G0jQd000GWotJuQx4wUA180007
-iZ1040WejIui76QYt0000G6608QqwX@HFvyR9000G00108iz7oPt008G0FnR000040001000
-2000gyDJ2hZdmrx6K_k1Fad000uG00W8000WM6F11010fpR000184000028W6Zt008000080
-0a0008000001800400W00000He00W0200W800qvr6W00800001G8008080bvR04000000XnG
-O001004W000WG0000G8G00erR34000WW00W000X0000008000W0400400200002W000G1000
-0vD201008W0000000060000004e00004080804000001801000800040010W0WW002mq06W0
-20uoC3_5p00400ViRG@z6010W82@40080080000e844000080G00W08200G500W0WG000000
-500@@R020OagcC0800008W01400G001020400W800005P104200181000200igl1A0010204
-00001020008X400G0000H0W0400G008WG0081agrC8aV380G00880W0W00W00008000I2040
-000402Oe_4ggFXqwV000no@@600M0Oc@4AwdXj@J00WfX000evtP02H0Gn@60400v7A3UXF1
-0440z@R0028m67C0000a100YKxDOy@70080zH932000QfaaPyJeXV60iy0qrR8LwRGLzL4TV
-2FTbGf_XiDT500WW0G0W00100002Gk@F000EJA00m4_ISgl1pwd00W4WX@P8W@40GW0q_V2n
-uYHe294hh7luRG5WCSbk1040000eCsVV2h_d0W00XVAC8k@70G00K2d1PYcGD1FabS80G04o
-XLYH@DOSf4gut00W80Xkd08722004G0400_@xX3zDOZUIkX7Z3_DuYV3QSnWAYDO463I@@10
-8K90W8100600W01e6F30X00W040W0W000004b380xM_0W040050000800200s6S200001008
-4mJ2n@R00e00002G7jQGy19Sbv32008kunWX2Ce@V9009000I000G0GgkCaM6300S5120W0K
-800GW0mlL900080000400WW8xD0000480000X00FrdGSi9q@M2XK8Hfz6GA18O2GI82K0H00
-00600GzRL0Ga520Y0000XK2100A00084020081Oxz409000000Y000HgvO000014000b00mU
-ub0001mId9is@6ZVR00W0X4ZDe_D3Uqa1000yw7310000Gg0m0000QvSL0A801002mTuL00G
-00020G9t6aGx3000G0A000m00040004G1WyPtONm4w9tWAyJeKz400yV300410PWUsF60000
-001Gm@@900G010G0Ilv60O00u6O900S0008O9EO6kzE10K000004ct0Zvdb00W2mYx600800
-0AWIfwC0y@1eOT3I3o0000002W00000Fxl1208G13G000042010GeqLSnV2a8002lg2aL00r
-6PGZlO4Va100M00G0Wztg19W@00002JJV0006mhS91W400208MQ1@100G00A40c_N20Gs480
-00W200Dkl1t9OGPx9SQMB00WFy0W0qeR5002S0000w00Da10000000x00000000eg0S5j108
-3HCm00q6j7@gP00c1W@@V00W8000uWj4D0O00msRCi3c1byc020005W00003000m0aKT222W
-0g_D10yC00WS300OU1300060OmKZ6GS00u2S30g0G002m000W000WuOvg00WC000p0o00063
-W1Mc5Z6zIONu40m6Ry@@68hF0000_dGX11DR0N10Wa4yu@V6U@q05410PnzGOuCCfy3ZhP00
-04WW3DOXO3Qw_atlD000FuVrF4bS25cYnheX800W008W0C0a1800W81000W00G8028CS3Ucc
-XT@b080WmAvI80000yU0Gtu6CMT2hbd0G0WX9mVuVP92ZZXzYJucu7QKZXeX99nx7000mZF0
-2uaSCUsEXljDOpU9wKtWbxV0010080W04G18AW000I4000W000OGW0010004000W0_6FXwkJ
-umx46TdX2aO00WHSPvI4mb100GW2TN24000Rix100G00400000H008Y00020000nqF6y3Z1X
-KOmIx604100G40002W0A00000W100G40000401B000G00080G24A80100840160000B190WW
-G8800o9tWPoD008G42G002100RFOGAi6aNk1001G0000GW82uWT3kmn010A0pmRmBT6KSU20
-0X0Mhp0GK00000040W20028W04G000005W0080000003A02X01GG8000G00G1240000WHG50
-0G500Ihs680200000Yv0e000W00W00104000GA0WG0024X080W0W00008100Y8G0040X0002
-0004W8Y11W0W00K0105000G0000G00081GSK00000G0WI8W010W00G0G00GG010000010W02
-000300004W0MJo000W0GI004G00Szd12002Uxr0gCG00880W00W0040100W1Y8AY4qD0W20W
-00X0808000KC0001000G00W800000G80G00W041040a121041446040G00@lR0I000204000
-24G340W11W82U3000IH200W080203AGG004zgd00008004GpFO0Y0008001nnR040000WO00
-0000W0208400G2006G00010800010202W0104001008G00eA0228140100W00I00000SC8C0
-W8O0W0opt0800900004G04KmT2L1R0W000Y02G6004ISc1400m201W00000011f2t4_@d104
-H0nmRmXC6W0000a040940WqwDehV3W0W0yll100W4AytWtrIG000W00m0000G0700shcXhvD
-8CU300040e008e_70010KMl1tHP00W0WSzJ00040004e@EC00000K0800G0W00m0oHC1H0W0
-200W0060820000G0GtD60410002G00100020C0800Udo000020W008030WG00007yzRJCG0W
-04004001a4G000004H02000401010000040200000420W84CHX1000050080GG08rS3W0010
-0004006mR_6SrO23mR0000G8001b@p0G0000010rMPGlp60G0182436Kt0000700G000a422
-000q32G8yC80000G08W10010005VoR02a0WyzJ0000ou@90W00GG0000G0WF5C00001W00X@
-@D0100880000240v@R04G0Y23C002G4044WI4D8TV3ktsWMyJ00W0Hyz6W180000W2014G40
-00000W9800000220G00002800284W00W040G000300808G0W@6D002200WGWo_J0080G8m90
-0WW8pV3W202008022060W0000K0G000058048061000K001204fH0GKY0C500Yh0020030Y8
-500040408W9W00G808umT3Axt0e2C001088800809W0YL0ZWK0000H1pTO0W08G0200Y8e08
-004GO490100e82480Y104000H10082000m0G00Ga004811PQ000004WG1HLR0C00GO0052CG
-080040AE000200O00WF@D00H0W01C0GWG0BHQ0H21008e0G00040W0KXj10I00X80282IWGG
-00eHe82a00000041m081W09L01100OGGG000WxG0ISo0000A010008W00n8001H0YOGG80WO
-000q0X111CSX1G00002801002480480Y00048005G40e0WG4W000102020000882DG20WK08
-1b0G0W850850H8Y0a200W0H0qBg1l@RW00G80e00081eGGW0G2000K0G40000I1L100081WK
-000H800080800000WKd_R0000Gz95000H0000I1Z800a084f00002G0a208X06100f0040W8
-0aI800G4000f0G2C1200W002PA0C0G0H000840W4080W0a20041900408210W01010100O00
-4GK006_9l180000Y80000O20m0Gd@6qOJ2TRd0G0840070004W0900iul1G800004A340AL1
-G0500H8W1G80W4G040P00i010XO80G00W4Ye0e0Y029010m00KW000400G108Y940K00WW40
-00O005G2G3P00K0WaG420620G01G006W0G40110G2O4508601400101WWK00130080m4G000
-i2f1W00W0100008W0000GZE60P0A0300844Y0182000405400006GGK00mNw60it002e00w0
-2280640W044m002W402m0Y0O04801120900G407WWGW0100C0W14000O8o0G0008100606GW
-000H6G03000aW00Sm4ul1001P822W02000400611I08Ia22W08W00GCTZ1FuR0b000280A40
-G00000GW40030040W5WF0CuSV38020820000018000q0ID0r12A0820G0W44000008G08I40
-200X00908C258I210400qDX128Y00W00GW00X06000GG0I08008104824G008GW012101089
-04I180W010Y_00Geiv20Y0002m8082g520W0070G10800G002008020000r8000050m20001
-iIrDG0080OB00000AeU020288y@l10G0GK20709K000GB4w300XIcB08204A0X0W8uN0202I
-SXU10GiH3aW8eF00020SXw00WeWm10Y00020G082q700619NGV008KIS10H00O10aG2C08E0
-WepC3HdP6_FpCyF0guX7Ys@00DLv704000000KL500000AL10y00001T300000400qm1W70e
-vM3g@t00W2A@@R0ex60500W000007Hp8ILLHq7UWPEy0pCZAcPcezF0HJrgYsV04j3FeAPcn
-CcHb7yGqFuXeLr3HdfCYMLgymXEuV0Y2m0HhA0f0OW@LLbK0Cm@00DL150YV004@0@8w0x1q
-1i3e0e3G1GK000W200GD064h0C0G0g000m00008000u200m503WA060C0C000H10005000_1
-00K1m0W1W10E0300mU000m100GXRG18L038_1w0q1y3e0C7G1Gqe1Om1s1A0q1K086e0Gy30
-We3G7H7WEWU0x050x1A047K08_10Gq1yZu7C7G7GdG2Cu@V30007uE0000G1500tT020000k
-xkBq0A_i1t0Pm8@9C@j1000e050G0000000Kip0GKdeup2uh@0mV@0mL100WUVy@6000k3S0
-000SmT0u@@040_101000qT3g000Otj0_@FWBbR0000G@h70000zXC0_xV01OI@4000mvk_@t
-ToeF0AuV0070JkhISzRSQl13_R0Wt6Wr@b0214G_zI0100iIRLkzt000042014Ubc10W00G0
-10m000qRc1R_A1000XBgD86i4000G8Q00G010mWG6ybV2574202001W00fURmZ@R4eb1ThNH
-Gt6qBE900OO6hoW9uUW200GnxUSoA3BcBnPw902080100m2SC00080050mQvCa6@34000080
-8W00GuUT3400000z08uA6cbdXnmVW000oduI48l4hqdGgG6KVk1W00GkEFX1@D0008080014
-00020G28020iPl108800W02Kyl1GW00018I0A100000kA00WQaIO_U3000G0080nG0000GW8
-aG00040004H00W0800K00100808W880086Nt00800G010A0o0GW00t@R080W8I000W0W00G0
-K80400001W82000L4HW00000020e2200G0W8e00m014g8080540008W04H5W0040G00400Y8
-004G820gG1000OY1WRyD000w4000218040W02HGK082201400020402000WG800W0YW08601
-0E0Y2c008208WG0003C000801H00G69G84o0WG0Wwqm04A00002O2Zt00W887AdmiO600014
-FO0Ggi9Sqk140a140802000400401100000800W00092G00100C800202I00G020100000Iq
-18UU300I80204uiV308002810HW0000OL1088000011H00SPj14W0100210400mWW0002G41
-4O00009008080010002Gcv60040enE30Y40080000Y8Guz90908WW00208190028W081G0GW
-0108X801224G80000018G000018X00G8000818G0W4W200000WR60008000W011004H00440
-W80aIk1G1000G0Z00002210YX2H40WmW0W0K800e0104210810040CGWKhvR010000W20080
-Gww_XI@DOAy4As7ZyDUeQ@4g@t00W8000YPX8020004umV30G000H010400W000WmVC02000
-034000800030W00Wayl104000H00000002200HW03W0000001Z@F1G00004006wt040G0hgd
-mK990800G002Go@600201004mX9600G0uZE3G01000400501my@6uyC0W8040W020G004001
-040400040G0108082WYdC0m040000100110O80wzE11000hrR0G20WNFVu_JCUGEXXuPutv4
-AmpWl2CO4V3000000Y020400000OW3W0HuR04a00W020G000009010G640000K003W0W0040
-002W800000G082W0MaHzD8hF3040008004080Hh_6KEV202082edXpzJua_4000M8000uXV3
-00G0zBd1@kRmYg98I0000004G00000ibvzR083020GH02020000G008000080084040089@R
-0000GG010W004G024C_l10800_pt0000200100W00Cbl14800080002W08dD3G000002K5G0
-0mMW9Sej18W62Iut00GG01FR00WW004008G10W010G0WG0008010O8KHI0410006CWG92000
-280001OY0WG0H80G20HX4244AAW310I0228G4W400Y8a00C0X0i200GH84120OW0GAvt00WW
-G0K010K1W02100100000W2400C000K0083bMV25Ha0G41e4yPG00000004Y20000GG020082
-00G00G1W1800000W0G0GW0280O2XG0200450000m_a001YGW0OO61140WH0e00C50A1001K8
-4040W21012W8060GI0080I0a0G10I8240601000XGW00WYY000W0G040YW0109O000G44202
-0G000W14WK4084p0008L4Y0041WKI1G0Y060850G4H0000f0O0fa2W4tCG8C1100GA0090G0
-4f8000G9G0WK4414000485YW4200WKI1I400610000xAI1O4W0000WK82p0000I956Y0004W
-Ka8Y05G29GAJG2Y000fa22HGG00Gg009a0000a2W0W800HAI1G400008a808000010W04000
-08bKe000000W002A00000G03C0K00014000OG00G0G1501e00aK0I0O000G0W8200K004252
-06I0G0100G00W2400cK00A01I1XGK0W28WW031G0800006SG00O910eW28540i000W020030
-1W5800CO000002Wae00002010m08041402H82050093QM00404GW0O000e814XW0000G0OOa
-1cR000020G00W1Hz0C160441G04G00e05A01x0G1G006a0n3W0W1W842G8GCY60076X08WI7
-Wm41W0A0G0050002I100B0Qe04O0Q0D130000WW4W022m0WY100WKL0H2G0W0Y5GKGP00000
-HXGG8004OE6188110G0FAHW004WYG2WE00200I0e0I00K4a1e100mH02W2Y10u0GYW000000
-020GSuk14000O010BWG400001W4m0080002WaGW0800020020002K00411021X060400481W
-1001000H0004K00W000900W0205e000YWDCmA0W8e4864m8W8100004KA1I20I200e00G010
-Y00W0K2W8080201G0a2I00000GW8GW0GA000400001210I40200W051gIt00G2WY000wid10
-020000wZXp0H0GeXjP006XDkGV000KmYTBXK0U0W0420YWCX0G80o5wT0Z00mK0W0C204120
-2H@DGc80b2000seftDC200J102n800a8084zt0HY0KAqVJA06WH006H084wl0H01OBH1a00G
-a8084zk0GWWOAKVel10W0GW000G0wF00106KU8wSsC86k40Gqg6sc1KvX@0m@08ZPcHq@3We
-py1HhgAH1mGWS60000000G5Ly300u7Lu70zXCW@100W3Op30gy30zHceoeF7uEL1000Kqp0u
-7m1G5_18cqpTirL00mDgu700y00GdV00800G5@WA000wk100000Kv700qD000005vLG30020
-0083z10000009kbW3s3K7u7evib004@0w8_1q1q3I1u1YEWE0z0T0A0w0K047G9Gk3IaS7m5
-vE8BWSWV09nz0IYa300Wb20b8vE8HoTWVaxWz0A603a8v0b2m3o2e4PEG9c2m30AHo100WQ0
-00G0K1k3W007W10003000u0yjUB000gu7000070u_V38OcPGm3Fm@ggY@1u0FyWWggA1T800
-0ynU8603oPm0FyWW_701fA02ApC4qV0yl@0eALfILgImPCZWggA1pK62cfCgAJPym3oOcP8O
-LL1mC@FiU3uF00Kzl4l3P000000280DxNnrtC47i1201060@10002000uy300CHE3R@dmNuF
-ifV20400Ey@XKoVG400W4000G001vjRGnt6G108OOI30W0CG0008GS36Rp004000W110G280
-040200402G0WfZD8xy400aqCDU204W0EAB110G03aR0008WJsIOak46ynWpqPuvk7Y@dXshC
-u1DCw_n04000GG00_JZ12000Tzd0uC2W_lbueU60004SPE31rNnmxC00C0uUO3W0840000G0
-800G00WeSC00A00000X6wC00800G08WVuJ024G00400K80028416od100W00008r400Cnj10
-G40sJ8X41CO@1600804eV2e000YmrWxvDeZz7QOr0000100G0001300080240WGH50202W40
-2000054Ji10W000a000G00050G00W102800fCR018IWZYCelE3W04000Gl3080010000gI00
-080wzsWXZD0010408O00G02A8Gc0802P44004CY020H1G0W000400W00000A008404W00020
-00804oot00403WG11000GG00BGWG8100e050040b80W00021010W5Ie0080GWH02GG88003W
-0020220e10000480880A0040WY88g3I3800K0006X00WWA000myJ82e094I0G00WG4854100
-820GY00W02CG008840W0GG0024080m0G00002020000200C0000480G10W21W00a00G22200
-02a0Wa@D018000K081W0000a0G23o04a8G0A4010XG80S80G4W0W0G90W001202X0G411Y00
-WW1001080XBW0002W4000K00010GK20YW0P8000W006101CH00eWY100G8J88030H12W981G
-4C8G404W800244010C010W000m0G1018a21Ia050841102G008082O0000W00W08G8100124
-0G48W00G44200ite140000W0KKkF30W004080A0210040C00W41G020004ces0e0003CR00W
-W00e01PWRGOq64b8300meHG00O0000020nzF6000K0005W00000W89000140010022010804
-200G4O0W001010200Y00100008010W02TbR00G8Wm@J000GW0G1002400C00000WW0080400
-GYU909014002Iri600G041W08GG9000W808000WW8G000a0800080WsvD0I042c000mq2008
-000008000400440000100GG0200G0G800000X80mrR60008000W810WfRrD0000eW00YXmI0
-G00408WW3kJ0G00OYr9002010010I8G4a002bzQ00000W4G021216pt00401j@RW86400000
-0Z04012004280I20W4000800000WB130000018pn4cGs00Y00000KW000020n44G040088W0
-10820001000200YG1020008000Al_PG@k6SfY11NcmFz64bk10200080000800080W000Xzy
-IOBU3GK0000400401mIz6W0002Y08GGuC00Ova00X0300W8@D0A00021WX4wJ0081W00000W
-0WhgR020X00000G08WA1m0YW000W0W00000808OoO3wHn006005zPmcz9G040100080205GG
-00VtOmd39yWl1024180W082Ga0G00G2_600200A0WnI_60qR414000WCG028Y40W008Y504U
-W10100000eaeh100XW000X82G0000012G023G00@GOmbu68040W0000000G20200010002G0
-W00W808000W8100W0W1000I180XXGW4200104410X0W020W0Y80I202210080041a802WWn1
-10W0L9X6Y8418W200290410GW2I8WW402W28000OK80G8WG0D0W08YI40005WH020a80WY00
-40W0G8002W0064W2W0084900710aW014H90D0C0H8900fGW8Xa10G000W880414100428280
-0O400W41004410e2W002ZdyD0G12001KG840102Z241108m081GW03W0GO000W001W0I00Om
-080240YOY0B008GG0GOW2AIX10AW0YW402W044e02e0000Wg3HC2G0W0W2O0004W6O0G0mGW
-8864002GW10G061I3G20G28C8X8G00a0WC8K40H10K082g800n20KG0GWG848G8G0WI0W004
-0G00804Y00148K00A482000W485a0000IWK2G0000048514f800002040000005e0000010W
-2000800001840000GW201000400fa00C1008WM90000G4G144@@R0GX6A4010800Y054C200
-8WMI1000070840YG000002fCI1G00e5b0000000K20WWW0004j04C000GKI10000084W00a0
-0000WG06800002900000A00010081eHV36KqWk1D0800GzY94fl1W4020004140000080000
-6000K00480b0G00010a00GF@600900000hf000Y20400008Q0000018@U3m00W11482Ka0W0
-00XA@D0W0G0eAnGO0W0naQ020O1000I0W0142K0100814C0000Waz7D01804W200822m0C80
-0G800005002008W00086aG070W000110H0000WW20Y9OD0004K7a6W018WZe82G1080124px
-o00WA24Y048000000G0K000000840W1000122880G03O0K000T0GHw6qrl102002Jt00008d
-xRGCS6Cdk1804A4081A8208Pn40K0W200004e0mWI600040A080001oSmD004amVo6000W0G
-00WI00001000820wur001e89YR0ex401108Bjd0500aZdD02080821WpvD0008WO08280000
-0W80100001Y10G40008WXFD0022nWm90G08G0mM0001De0W08000C002XiB0m08X2glW0XG2
-20G804240000W500C0s01I50080110EEs00020080W02zJW0002A00404001000W501C0IW0
-000dym2Gku6W0GKG0004wd003W6Ae@02800gaYl1000w5W0108KeN0000aG1000000O0000P
-109000AmM0000WG2C00084ok00000A000oq70000g08liA0kxzH60001500oS700800000m1
-tT00W_0dx0GW20WCw3Wnk2G000o000@@70WxE00tT000000OZ2Zp00WA000Pz1000SOT200F
-0Imt0_@FWy@V01m@02000400uF00mV@3W@f0OGgrL00WB00WV0C0T0P1m1q100a5000S000u
-700G7mF0N060e0k000P10006000i200K3W1W2030K06000C00003000x000S1q1m0e205WA0
-08A030gH0aBk1m0y3W105G700mQ000W100YE000T0g0O0H1W2C300e2000O000W200WLWP08
-Wr0G0Y000630008000G000e3W8G7GK0C0T00WOoDutV3WTNeYV00dx0000000300Ly30gud0
-0yhW400TtWi_d1L_10Zl2e@10W_mD8yR3yFWw3P000000WnT700000WxEmHbV8JV0G5@0WCz
-10Wq4U0W00GA06a073vAyW@1mTW30@FYdm_s9C7i1FX@mKuIi7E6001000O@tC_9NbV20001
-1001jsQ00O0WrlD0304W00001aW0080080200W02W080GivCq1W3G0004001CQR200cNl8F1
-10G00004004000420200mBwIW00GuKSF0G0848S55hR0440WWyIu6_4oNtWfuJ0200GAi6az
-B3WeF0g6t000G0fnQ000002401tjN1080WJnJOsTC_EtWyPDm00W00000W0G1lmP04G00000
-280020038K8l4pVpGmy900440000as10W4mPu5OCoB7ZLvV0100010YW8hD0000008G2I800
-NzP00G00WY0200004G00MZc1LYP0001008W0fzP06G02000W00W804000G00C9P300mWG010
-02000040G0WW000G08048G001OxD30001r@W140000J0Z0W0000H000X00348000840O00q6
-b1v5RmTz60008600402W021IG128009110000G0I00082W0GC00VqRG836W140OkB3000000
-I0G01000W0008000001YQs0W00Gm000W0000GV1004000K20400G0G0W00G21000100G0280
-0001A0800GG8W0W88vwT302G04SS278dm4y6KPl1009G0G9WG0220G08Z14G04023G0G00G0
-000101080a0W9WwfD041000GP00000W001cqt02010Zjd00102820100G018WW80040000fH
-1008400K0000801800144H0G1s6010000G0WG0011210023010W004004400nm@60000H0G0
-mJo6qe03e0G0EasWmhC00W8814004G100002gQq08000G100YWmW18D00010000H0800000W
-DG0Ha4G2H2c000kF280000001m000G04000001W80I08000101000X004000800WG0200002
-15gto00210K0H0Y4qWKhJOge4Uct08W10084WhBp012000880000020200G401G0O8080800
-063qy10W00I0404080S4d100000W48Swl1WkE0G008i2k1PVRm@@C0G00000WGH36Ko93XRZ
-nx7F0G83000G2240G10004050010G00404A0001O1Wn_JOiQ300003001K0G0008200400G8
-02W00100014080000eAF50G028000004Dk12000W080jrl1VaOmFs6808086p7U_GYr@D008
-04W080G00640200001I0020WW00000G0040HyRmMS6Cl_3hPcmYy6CAl10011000000O06W0
-W080008002W00100W0W8H000000108000403vR0000ua@D8H1FIqt000W8pSQ041012W00G9
-0000C180Wm08a0008110080tYRGxl6a3V20W80Eut00I00HaR0800XgvJ0iS2mUM6W00000G
-0W0002000GO00W_6bXRyCeMK96Jf200XW080401Y2A88m06580G008uG0IKI904aM1WA8GH4
-081031280840GH0wkt0004Y0008G40bI84G09410W000W00900000410001401000000IT9I
-G0WK0G00008011100202G840290GH0W00000082W000080008208000IIrWgKJuCV9008000
-01021G809f00405AH000SKQG8E8GG2280mG200H02W20WO81G244G910GLy9G0000080W800
-0G85008G1G414Ic0A01aKW08G2H0102W0000SA30082000aY6Y028188G210C010Y000800G
-Lh90a026400YY00WXwDe103_B23Y000zSQ01000000800W0100W00fW120W2000A0G000001
-YMb1000242000W0I1200040050G428000aA2WW800GAe8Q2530FxQj3X1qA24X000GAj00Y0
-0W4aY0G410080f012H002aYM0W80W40G1WP000000Kc1W8000G1LBkC00a00008IAT6y9D3t
-bO00020W0WX0G00G4000G00e2s70W0O000008WC000844106A0G405HW0C8A00002000C000
-H000e0700e0D900000mCmG0G4800m20WW004045O005c0HK616004400G10yzF303000000m
-G00Oy@4O000CwV2pCPmjhF080040e0WG000000a9WmmM@600WG0000022080e2OGY0n004WX
-0000G2A000X0400000Ie000eX8Y00GGm2W4q020Y2W020G5422H1140Y100Gb000Y00XW500
-1410300A0G01404e8G02G0G801WG02GPT46Q@t0082G36L14D0Wu@DulO3WG00i_l118O008
-00010000W00a00100W0020Lli60W00WY000eM90000G00I0Ucn00W00081009AW0I2000G02
-012WBYD000090200000ax7RmsZ6qdH2PBp000e400009GQmKm9WU9808W12002WVpDG100mW
-o90020100001e_00108G0s2W800A5040Y008W0G0mM2W82mK000Wu2w30Y00eK000820m020
-1GV9066U20G8410W4b2W10C5O10Y00mG000820012000B004845200qDC3W50040OWicb10W
-HuS700mFP0004KGIS600uk30mTN7094TD3000mZFp0y30Ly30oq7g000ar70WxE0eYV00000
-0qu2Vx10YA@TQ@m0SOikD600m02Vp0w0G01TR00100WV000k0T0O0O0W1m000WHER90000t1
-00GA0600G1I24NW49@0SHS1o2e3m5G966k10R7Wa8n58HYBWR4NWr0w0k1KYXXp0YBOlK0I0
-G9IC2IaO4m4n889WG0J09na0IY43mIy600W98iN3W0000O200St10owZ0Kvd3S@E7000E000
-WJ10Gc_0WA_H0PwJ60S71500P000m1mfy9000y30000ar70KzWWnWR0LLvV0an@0Gm7yWWP2
-00WXSF88LLHGggo3EyW7yWApO61@702ggg4CJP8uXEeALfILLHbPcXWpC31LT62Uu14KLLCp
-X7uV0KnCp8e@10Gg200HWN1008W2ibOyR3wVhY3DOu4T900WzK1dGrR@W420XnoD002WGPu6
-80W0edc46tEXzobuoR6cjsWC@D0u11mnTXKPc4x@dGprIqYE3ncRG9UXiRk1TXdmSs6ahU20
-00mpcAXUzs8aE92OR3G8K08001G100qvk10W14000GKhc10000AU9XRuPOykD0000000Xlzl
-VgX@100m400m0ZTs000W0G80100WK00000Y1Iugz60W00yqU3QjdXnoD000088W0mLvD8ZT3
-8800GG000ua18500WstDW000G3f6aWV27wR00G4240mW@EQmiO60G0004000030WsuJ88B3_
-ot0448002024G1X802008a0200002G200G0IG20GG4080G08Gap6G0000140GUK6ihd40020
-W0W0a4b1c100wo@100K0nSO01080W00G0W00AX7ZMPCu@@7WX01O600020K04WW0840WO4G0
-81010Z8Ym086800A206GW08W0RKnWo@D0012mz@90280Coz4G0000400400000Wtpl@J000G
-0000Gm0000G008010008G00K01000010G40K20wksWttDuOX40000W3008uC60002000100I
-0W00W040W00010gvtWX_JeRJ3wwtWofJO5C3Yyd1000G0W04oUm00c40O000oU8XHraOZU3w
-zAX5vCu@V3_9pWTCJu@V3000G801a0G02m6@600WC10024000G100APYRGmbj00C00000Fd1
-0Wt5nu0dMkxF13C0002008002qKc140008I0000100C80mAds0WmgF5M92QbXYryOCiAgus0
-0W000200W10W000001G044020000W00WGs3ba_nD0200G0o606t0OQ6d0000001W8uk40000
-2W00W02000200W000NFqo3_6000WXb00GxEO4cgDO0O0C4800802gKU3C850O40W000008A9
-0W000K110UOzaBtDm00000WgWwMzuOB6oUu4CW10e82548X080L0GK00aG002rWGWA9GY004
-CaST2BzvnBy9W000a0000up1WNQVeeH30080yJ0CxxR00a2G1000I0000GW00W4aY0H0mA@6
-002I00G10000W60C8rMFG40045W100mG000mKPV2n0aGOGRqbB90X0G0GW00A0829000Y014
-0100800002a0Co03NSq20W@fcUteN6Cczr3m000008WG0OGEah10K00IP8XDTC8BaGcptW3L
-J0W40mgaCafR2J_dm47m4TS220100W0G91G1utJ3s@tWtYR1201mSu6OB00OFv7sRncpnJ0r
-IG0G01WzID002HcR0e00X283nRGx_6a3k19D42000400m0G240004Y73G52000EwDaBdtuqC
-3Wi_0G6008AV3I47ZGetOBS3000004m0etDCeI10KAjD0@000O0w0q1m007e300G7000uHUR
-02m000W0073R0006WMgy00401008fmmDGp00GJqC43W19_Rml5aqhk4600uS700001WpTk3E
-04O0000000Wk10000W3k3q00GDUFygD900W_om9g1mbesK3_1tZNKJO2O323d1WGE07XJojq
-ISDD600W0800000Ha0014nBtFCTE3LLRmoT98040e1z40008iWE30008z000SyT53kWHjBXi
-ik1RnoGKwRaKG24001Er6300LsBFG5008G8001m010AUDXaAPugx4QWzXfpD8RM3cAc1mBB0
-tnNHwyFKRA33NdGgvO8G4100040H1000080000410010G00ym_4kgzXfsJ0022mMv9aAl1rb
-R00008s3045tcG0u9aYl1TZP0004WmtVueIFG00000I0000G0W8W0440001008200000GY00
-94000040W0HxeI1u6008V4100mB@ICtl1Xm9HYFX000202140C000000WG004H000ETi10WZ
-00O404_V2@kZH8mCKcU2WZc0080K4fm37udGYmIi3N2Hnl10X000002u100W000000m000WG
-Zu6i_R2PFWnCYL000WL300GLzOC2h1PF8n6PX048YuqhYMpt000o9Xc55040W3zD0WG0mAd5
-9KX1Otpe0000204euBpGYXBas_D0000Zk00W2IT2520m7Y9KVU50001_pg5001n9fw400041
-088290W6ZqWvMh0010mRVdKDl10l20cSr90G0X2W00111G000Y8TU32FS62000TnR000W000
-0uU100Q0CA02000GA2G40000f0OjV6MksWK0U8juG00qx5LOK02A2000004W087S9G800Kvs
-C1XWqj@900510A000X00000A0G000Gm20qOU2JdR08200000000D0Q0M5Z100r2xKN@602G0
-ea@462EXnuDe_GO00Gx5xHKA104W4A0G0000070010f0040Gvddmg_6a2W4HQx1Wf7Wjme2P
-z1000GWDpCO0QRkFB1000Cc000Uz8A000uE0100mU0u00000O00007Wv@J000SGA0IyUS5Vz
-d00WGfehTAFT300000L00eGRa01z0C3tLh79KPw9aXJKPPJohfCSVP8004SJAmiqTtO7@G0z
-50izGNzJdGnuRy2i7000OiA00yrJK0400o1zXQuDuwIR00q46BSK000202000400100GGMK9
-00002G02GM_s0Iy0uo3g6Ft00W000O006rt00004dXQGFNm000WEPJFcZt682103XpGv@6if
-SE00I_7HfhAzPOuiS0ax04CINVm_Gj_6KHUB00WGPD00KFALzj@m0@6K5dD00GGIIbgduD8H
-XAoSV6G90055SLjyF0100u1ORYKWAG000TFaW000YsiJe9C3I_O60003vmx4000A04100000
-0L2002041KG10b00WK0C00W0b40Gfnm9vz@70Wx0COVK030000H0W804TAx4I1mWBND0H00G
-9f6itlAS200Qst920W00W2H80WYW0K80G0A020H4G0008G8WG8G00Y0000480G4000G01t_h
-20WUtNhe2042000082400pIQ02J00G008h6pGutj0g81OePd00i00H00K8000410G0100W50
-014WXa203R5QmbHg000WGr00GpLrzEmTb@R0WIaO4a8n8W9YHGI0X0c0IY91a496eK0IGI01
-0c0Any_R100lP6tE100cXWgg21pC3py70gggCKLL2wX74KcF88LLHG7Um3KLbgK50@dFFC08
-10sUO_jnnOCpP_@t000nZHAy@QxFaWSEU000QNZgSiR9oVF00ajVVSK00000a0GG0G0G000q
-5w64Zh10200sgoca2YQ@V3C0880204ucV3IRFXohj1000SkdH1G0080_4w_tWPu_100FTGA@
-@3p@zuy@EG@dZq@tGzVDM@F3s@nez@BS@@4cG@@R0Wf2WXz_F1tSc@d100D5H5Q@Ez6ikz3R
-xRmSzC49lAk100MrViT2iv@V3004nFe@RlXF38D6WvCp70400008W60CuHXV0GyY4xH_W000
-Ay810004BL_GcYm0M00O5Ng00100008e10327XXxHc10GdvIFNzsw3tfp3Ww3WehZ20G2000
-G00080W0018000GA0IOtz46dT6000qw600gEAAX0008240a10Y20G01000IA064mF3n_t200
-k@azZ20W20006040200G10G00000400u00Kqxy0oQ0OPVd0G00GG0000000150280002Y00W
-002000W0000ud@s000WKG00Gp_EXe000W0u00Y000208082Y400W007824008040WrUj100E
-Ko_E100UGqPcXeLL5FaP6_70Lym3HxV0Ycg00DLL1000m@X_R30G2WEAYY8300H6G6YCWC0T
-0P0A0o0K041e08Y10000830D0dJ7t@lH_@Pi@@5z@Nn@@3w@Vqu@@i_@Dp@@o_@@@@@@@@@@
-@@@@@@@@@@@@f100WsB00GltFa5AF@@@@@@@@@@@@@h800mNs300Dx@VTe@Fdw@nn_@Rk@t6
-y@h9@VQqn20003q00m@@FSFkDXP@@Nu@tb_@Rn@VM_@@@@@@@@@@@@@@@@@@@@@@@@@@@1a_
-@@@@@@@@@@@@@@@@@@@@@@@@@@7r@@@@@@@@@@@@@@_@@@@@@@@@@@@@@@@@@@@@@@@A_@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Vf@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@yWB40_@F40W00@@l7000CX100@@72100W@@@@@Vv000GClmC0000@@7
-3000m@@N400WW@@r20WN@@@51W00u@@40400iinC0100_@73WKF0@@x4000e@@T20003w00W
-k4cvz1s0WLhz@@@@@d90u1W@@T20GGv@@d00048aYJ_@NK080X00000G024xnIBkS200G1G0
-00@@Jo0H60140u@Va00Ghy@lJ0004030020W1y@@b0qh0y@@90060_@d40a00001G102Qy@F
-I000eC100y@lJ8w62000800X0On7a00y4@@@90W80Y3Ih@@b38300G6G600WC@@N4000GV00
-0v3eIFK6y@@@@@hOYRj000Wbw00G_NXy@@ypY13GL3W85S200Wo7MgCxr9E400_@dA400180
-020010W0280000G306W0080100mFR94rs900k3_@FA1100BiPG2040W02885Xa700y@FLG0W
-0W0000W00eYH3WG080000G00WW000W3vIeZgJ00ivV0OK04W00M4HSInIWS00_@t90G08O48
-0G4HG0000040GmzUCq1W1f0G1080010G0ZdW13W2W9kY2020000G00004LxL40008@000@@x
-404020a00P0o00W00000GD0OGA0KK593fCA100041200@@x41gH14WC00G000G010020000G
-GTX600W08W43I1W240010W00BECXj3P0000dO00W@@T2W00gG4WPC34001Ge2TyXM7V8506A
-OqWhJh000X_@@E1004w@V68W00iiQ2PhQGA0K0004Y002m6hO00GKu@Vd000Oqe93@mPmMj6
-S6t33sQ00G0A00000W140000020Gu@@A0N00y@lJ0W18sPp0W0800002m000010063W02010
-O0G0800040010010G00030K01mK0I010010G00030G@@d0600WScIGM00m@@EbHg10001W00
-00002210W00080W80200000W0410400011A0G00044851O0300080002000W000yyL500qd_
-@t9000riX02m600q7h1YWe0008001Y2000204082008001W8I1G2041P20WG04A41200CaC9
-0YD0y@lJ0O00TU00IV1UMcPKZQKv1F4v@08QLzGqPAZeLbAFafC_70gym3Y_V0I1W2HhA0WM
-LL0000uV00u@V60C_0y@VK0@000O0O0a1m00383G1G6W208050GC00WO0P0n0o0QA0IG6GFW
-CW20T050W3A00P006bJY8NRv@VIG4WxG40@06t100_2g@@BgDB3_@@@@@@@@@s3gL8000qq7
-00IfCgrgtuSwP00CIkQEL3bpGyqUiP_6@@d0uH1WTw@FdVrHgj0Cj@LJklah10WrPrQm@Y00
-m0DuFLxHPGCj81oh1O7_y10G0yxBI00mhoQLh79G2Wt0m@@H10G18mUdIpugch@40000021W
-E_N2Kx3mSrs30082100mLqmizF600mJtKdA0_@1tzlKCS@Fq_@1r@@F@D6Al1r2Rm0o21gg1
-ezehYcP9F200@@VrqL8108qky1m_@N8G3C095y900WEs100Lc55800elrAQ3Ejg2tWb2M2GV
-2mo_E10O087u4YNl8000m8600wXFAW00W0200c04900v6teS5b00W__H20S1m8SH10000K0G
-GI1S200G10406432004411_N40WypyZf2020nT@B10S1OPVd00i1q_iJ0008MuSfs@J000O6
-J00Wz_H20GTPEyH10W800WP04000O0003_N4ek7WNFZIW10e@H0W4WNQM7ENLqiIfB2Gr2G8
-r8LQD9jNF3000Iz30095SrEqXqx@900O4gmbg6kL9wQI0La0aVSNfclHtvd0000Ls00GDpuX
-400eoPI00SbVsxLpuom@@@0oM0u@V_1001z@VH0WKhBsFA02000100_@Nez@J00e3mo_H10A
-0SJHdIAWA012W00G000045uVH002wtMFA01e0W80GoUOfuZY20010000C4GgI000GIT79K00
-0@@x42820000G2W00MD3fi7Y200W00G10404G00008e104idb001000H0000O0008mV@5100
-Wqw00GCSH10mPvagY_@t000CW@@J50@@70000_lA0YpqoSlCWm5W100Gbi7Go300Gp_EP000
-u1W3Q__@bp@Fvz@lvk8100030Q0020WXkVu6GF00yJbi@L8002_@t010G02000IdnWwPC8vL
-O0PJ0y@FL0004UJC10001HAymeYISOv6000G9900y@VN0W0080004ze1N4am6xj00WPy@Vd0
-00H00M0100GW400WBAb0W800088WmuX1KM3m@@E10Y020400200e17O0G08O4I6000m10004
-000dU7yu@V6000av200u@@e00WWy@t300080G0GSFH20410_@N500T19xJb000G00008YC0_
-@t00a8000800848I4n041G02H42WMDR1mY1mo_E1WP0mG0G4IGO400W8q100_@t0J1GWG4W0
-0L4Hf28a2m0YC40LejKL1000O2WH10G109000f00WqMPG00G20W80000828W24W0W8W828WV
-L00auz@lJ000bW00H0008a200m@@900Y0G400000WG2100fpE3eF4WmmZI2WXu@@F0000300
-0G7o600eW22000GW2WWcLnZ00mP@EP00060GGe02000KG39Yp02028Gm20002W010000088t
-UL00WtS8DL00GW0200i8S20800QYp00W20G00040G0010a8tVL0fE0iilJ0WwG00eW010Yu@
-V60B082000100W80448000i0GGWW080ashAS300Qst9BDXjYHgqy0U000fzeV@70Wg@fx802
-00081K5WR@L10G@pz8H1WmF00XE0T000g080@@R000210J020k0c0S1P1e2u2G8a5WG0uS@L
-10V2mo_E10e00000eFCuB00mpvmbWT5eFc9Wrk2toT6L_BFohd0ouF0Y7WWcL97UgE8lw6nz
-0G02m@@UKB9IPRwnEwU8700e7_F10SvNbELZcRm9OO0200OyyM0uJ04SLK004023t00100xh
-R0200000400W8W00G0000W0000400W00010BOJ200061300@@x4WW000200fcR0G00attOG0
-000800WmpJuYtJ00C14lEL14OGXzC00004000O7x608000W02W000WP@F9tpe_7@@_r@VV_@
-pt@@FV@lpu@tS_@Ch@@ox@RAJbS@L1iL0mu0i5QcDA300_@daVucvAQOs_7300CibvT5002W
-njJ8sw46vsWehX1C50mIV25_F3084I0I508W000140000005000080000901000084G0G004
-0200LczmWl9GK008rR9000GOC00Of1d8GWGO008W20W0401000m0@@R0804WQpD00G0qgmIy
-Uz6001000OqVg7I9hdmuR6ShU20001G008Ckk128200G00SV860070_@l2G9D0FY45020W8u
-J04W8G6pF0041uBU3wX@4000uK700wuEA458G4080002100WG0004O2sF0011G4O0GhXIy@F
-60WW1grBg35IOg_4ArF1O0903yNn@@U0SO18jte00008100G49H04040008WLspm5c9a8z30
-G00Ii73000aq200Qst9000J8Y2200G00H1K02014G1W00G80p@R0004G00G44820G0G4aDR2
-rX720Wzk65Z2804002I918Y8200e0W60GY80eK@4G0G000G01000IxmCiok120W0w_73GvF0
-@@x40I00GGA00WWaWWH0000IGI20mTpCG90008AfGepF0000v4W7o0z1N200zr7b0G400IG0
-G0000004010002G1Gy@60028000802000000IxTpGMiU00WBFPVd000202G0W2G000W140g0
-00G080020a_V201O000802G08uV@4000W1200eqMF0Gf0iiVKC00W0e0GG0G002201000080
-0Yj@R000GG800042W0GA09aiV29TR0G00000H0V@ZHYqHXi000W0X20Y0002G8082g520WSo
-x30Wi000000500O6O60G00StB600_OJst9000pYmCy4XSoHLpm3erp5LPE24vE4u200Q@t0P
-a1000g@lMYaw@P0qY3GXhH1q100u7e3mEG7WCWE010T020WsyU220008WA00We085W42btWS
-xD8506oXd1A100DxxqIu6000kpTVf0W0000KTtx@d00o0WHwDmpF0mxpC0W20000CpsK6S_l
-400IYous__bRf9TIy100qQkzB@hIn@a0el0ucvesXEXCkVeWRFgx63000Cu000Ai7lPPUO8U
-C008T7fWMTRxH6tg0U008y3ykn@1080895WXW00WEApy@V300G@aile8rM0MD@@KtvyClGcz
-l5GzD0Bx7Lze85_O2_500oKCgBCzu_@700a0000KuKrD00SAczmLBk2pwZR0cw0eSje0400y
-pqC0008sf53a000Fp6rP6E5qs3nCX4W01WYQR1020W20000m00@@N1G56W@@j7000C200W4f
-L10300000200W8@@N100Ll@@@@@Vr10K4zTiGrtuq@@I082089zV_EVltmHQIOIokp300YP@
-@JLksIKkd4jih2Gh3Wdz7xrQ6EkMYbay8ePgIkwaBtL10mDIScpts_Fb@B100WST100rmz@C
-U@l2dY000000KhcilJ0005sn9A0D603s7r@tUaKmX000WRxT900rbhK8AWk5WbzT2049GbYE
-100W0_00GZqp30G6uEJd0050iaw@JfgEWH6Wa28Tjt@BFl800zKbWtrUlRKxh4L@Y10Y0Wau
-nhG_7Ab73000mPXrrtxLyvhA@@R00WuZeh@@l@Y000YoE00eCy@7J@@mu@VfzA0W000008ix
-VC0n10y@lV00001004zay695G8WW0W1x39ev@@@Nbmmt0000YK10Wgh@FCyY0IV0C6_@7agE
-e_5WbzjlGSd00G@ailS7gAHqrU0Sr1uxcn_@d7000q4400Q3QiBQz8UTF008ea8z@7Q@VXu@
-Fe_@1o@@V_@@@@@@@@VOs@@5_@zzZ4mC1WRo6xDw7MaEX1v81000Timm4JdJxiH20WbshyW9
-zjPAt@X0_X14D0m8ucr9z3jXp0020W9nJeTQ340G0qGT2000Gi400SLeMXXd0008Wz2b0410
-Gqz601W0ehW7_@d100bKpgVb000000087hd0081W02U0000oqUIime4020005f0aCBUNnd00
-O0mUnJOEU3cL810000000Oq300i5yL9dNn0yI00m0u@@400W8S_l400ePcatWB1@9SzD01W0
-0000G40200000000H@@V28W4p@@JmX02GeWOy@lGW080c@lYquVORV3EtFXF8JuMV3000meQ
-00uvHy00a0qSF3020000001O00O@_700KSVyeM3xR0GW0001009FO00W0Wy7P0C00G3064oV
-20Y08_@t0015G0860_@t0GP20FFGroa6yZI2LpamBl64Fp300O0oe91W0208081gUW1000Gq
-400YjCXaQQv@VCe000SAQ20085I1GYjHP000eK306G000W0002X08000000G80g181000000
-4s2l_gJSDO6N6I1W200010G4000H4010008040OW040W0KWY400W80igR2004iF7LB0G0W3_
-c0000XNUC01W2mKFC0K0085030304810000Y0WW02M0G000Y0G100Gq@h1WZU0I5t01000V0
-ZqEF94Ci1d1P0020WvECexrD000W20a80400000GWOLD02000000Ub10080W0MSP9a100pic
-G70600G8RhL6QRr0W0I00000W2004bi18R00000gW_0008WYIKu9K4W1002cA3mW@@N204HK
-306y@V20GL00GL0y@V5l0OmE06000O00L100F05p0007va0m000G0D0@@75H4004H044H040
-01G000G000GKA06W0H000800200WK0C000000Cp008o0m00301000300WP000YB00aPWA000
-C0W10000Y200O6000e1TC0G40GhoE1F00e103IJ0Z85g8N16060000W160W1Go_6000LH100
-m@@i56MB0_U0_@N50808fUGoYOjabT8000ea300SLUTt_h200Ra7mTAI1FsaEXyh3fiR60V7
-0ylTN000GYfIYnmVeGS3skk2000G000Gj900yyDIt4nGXzX0200uTl4UwAX5yVubF300Sh_E
-UHDg@mACmW020gXnD0XX04fGKl_n0000ei7gu3U3_nXXXuV000WGsv60000cj00mTK8z6fDb
-yR0000Xm2De6W7001000ezxH@k6rtWLzP0080GF0FKiI80YL0_@FgHGV8AX4Y2WaJHV00800
-000e4NKfHgPkrNY6QsOxVC00qiz@FL00W10000G0060004Gx@98W100008m_3FO0000040GN
-06qe9340W1ksp08000WIF0Mpag0CPe303ERD1100020002zqWe0U8DM30m00KoA39f6o@@42
-0uxSRKaopBXnyIuFF6I1uXt6D8AWAsKbXxzC04L2G3S8bu43XPj400008100@eGrGQB100Gv
-@VmYH9a@@31W92mmN8jmC300m0_@7ZQ0mu@@YGUu1XKW2255f5K2mB292H0p02u11aQwi800
-0X12FY650400W03001d3010eSLF0002aoQK@@R000l000K1408@10GmhIW00040m10300200
-G400W0000v@10I40G000W00aG88Y02H200000W820_@@18Y0000008H8G822Hw@VL0kz0a5a
-Djoym@@6006Dv@@@BST910020C000008020000060800G10O0f0GHK0aKi1L00W0H0841a01
-00WG4H80004814X0G4OW4a205H1G2G24WGiDu@@b000GY80oZ89000088U20000IY880Y818
-92019Y40000adW000009HUc2032IG0Y2uXK0OG200GN9T5en@@Xy@myp000WGY00mjq6SE9U
-@@Z1z10008BeUv0000e910GM0_00G7NGcK038uV0IA0iXO@1000AZ10WhJXPUlYYDsWl2b8R
-L900KsMmw3hukqlGh_TA3vSp0200WQQP8kx7IhD1000u1jRmrr9KyT2fNdJ1hC0200uHx4wo
-DXy9J0410G@_6G10000W0000040100ht@0W00000eXR@Yn4s6iVuCWW20G0000011080400A
-0WV@I0G0000044G400e0200GG002204W00000G040040000000K0000008Wq7w600W0Q@@40
-UL00400W40GGMwOy@@CK2W00000040WeR@40023ykl102G06Pt0K008406GYDt00m00000GU
-@t02G10z@R00X0W_@D00007c00YzmJ02G0GZnF4yHEBfR090OWy_V02W00021brrD00800W0
-000W00byRW000ei7CeFP60200000_OPl7_k69008000010e010G40uHQC00GGSSF3HRRmq@I
-0QC0euwkoWN20G0000W0000010400420mIx6W00000101002YVvVG000000uYKAD8kV3Y18X
-@_J8XsSkdtWL5DOYyAoem0W000Z@dGY_6a0l400AA100000A0fysh0000200287y4UstW7VJ
-010400G4WszJex@4gud1G0000CL0g38XmnP0100Gal@0420000040O6eqeV0040000W0100G
-00104550aRk18000001019W0eyx4G004000001G04000UG300h4aGC06W000AdV304004tSE
-1@R028W000018280MDd10008000e04000G10GG04W009Y_jJ00W000a2eq@PW000000i0000
-0090WMH@Xj@mOaVL0G010000W0Q1m3yC0II100085f000H4104200O60000X4100O204G800
-0a000f0G200300WKI200G40I940G82400000Yu4000g400G4I10400HY8W000W80002000W0
-WNnDG200mz_s04c0O3_7000X800000W02000C00590GJ000K0W40q40020G81004200040Ga
-c00A0012Q2W2004m0W0032Y0000RKG004400e00408A0A00G02000C0008000H1004120000
-YsttcCND001H0210Wv@J00m00000G5G0100100g30004108844IG004Gm18W20W000p28W10
-0020H0402020iW4018A00W100WkX2Y0400280a0G000800200C0W000c18100RbO00O0W@@j
-10H0mh_IG0000040a001080GW0Yq80G01I8G408000W0884e020000KW041W0DW86W00GW00
-a00001G10000Kp200600G2q02800001YeG00004000120882WXk@11X0000G0KV208W44_@F
-1W200082w500Z0DNeN000AqS10H0Ge0O4041r100G8X3q7002bCk0G400K0420HW_00G8Wx2
-000QlGM000Gau20H0001m8041Y200W0W38A40080E0W80OGTO_@F1000L00000m0@30mT@@@
-40GcP000Kn3F4f@18QgEJqoCZebP6p8pCgILgyW7Y_@K0OG6@3GA068QL100Wgl7YEJP4jgK
-vXCZ1W1HhgAW_m3yF00OcP0OXVR00u700060N000P00W_yJWu7000EG7W2mU050n1A0Yx004
-t1w8k3s3K3u7e0G6G1W8Wc2W1ypy3e3e7G7G1WEW20n100W1De0Ga10Wu7G6H6mUWE0P05Wi
-0CW8300H6G600WC0500EPdA00W30eupg@FXA4y0s00G4SG_z@300gHchdgFytOryA_pdXU_J
-uKV3W0000aV0uOVsosR6000mA100_@FA200WnBaJ_z9qDK200sSYKWA102W001G1410Swl1W
-002UUZX2_De6S3000418000010KYu600WGO4Q90gj0q8U220106tN804010W188G04020000
-m00G00108002G0WKG042088G00000802G40400000H01W20W18200QW020008Y08011000a0
-401G0W0eW00010@CP0000IP220PHbGoy9qDV2RFF30G004040W8W003000m0W0040000G0C0
-818080002aiel1nxR0I4040014000C000100840WW0400063000feR0008WUiC00G1MYs9Sy
-O5rI0300W00002G09200800810gCS30100004080E3000824G00800000200W00010M02GW0
-40020W0GOy601409193s@F1Wz8WTuPms3FaxEIf0pmtu60080e@V30900aVP209W00001CX9
-3xad0000O5200HPw40100W000G400AACXKEbuo13kPd100CW00000WH0qrE3hjR0028@WOkA
-fz7IIpWvsDOt_4A@BXy@D8hG300G0Cy_306P0gnmc00310000KG0W9xnurU3_keYTLI00200
-0001000Wa104knOcc@z0W120400m@@DGW00mxZ9i@e100W2000W000W8WV3W000000010g20
-02080m80LTmG2_600GCzg7gwut004H00021ssF11W04JzR0002010G00O8000002Y0000040
-01800010f0QG7b68000u10340000Q210Y00GM064CBIW0W0000G1H0000085eG800000W2W8
-000000eGKa8200aIA0410W00fGG4a9000WKa404100I954Y0000WK00Ip0000850X4H00WKW
-2W0ocr0P052Wa80000IT0NE7FM100e0G100004000M0000000W100W200K02A00002800C00
-00W00m400G10822h2I1m0000K01WG000G10Gou323o3m000ug00WG000G1AG0u0kSw_@10WY
-000040W8022W07W6G20010GC00GH008WYW050101YE210000GG0g84m041Y1K8A0200004X0
-U00580T0028W2GnGKOu0000HHeOG0DIR08JWG90108GC0wPQ904W000800020E8g1G040100
-02W0WieI300000K0G00G60I2000004402W0020GW00000G00I141008zqQ040G00020G0001
-00Gub001041mKg9y@lG010000IW000G400C0040Mb08H0C5O10Y00mG000C2001202H@5048
-0b2ztWH00KA084610G41WGe@60H4Wfa2W10G8410W4101WL10240J1000ZwWj4410Yf00100
-00IKKyo100me0Lm6w730J008cWa0m1C1e4s3G9IEWIaO4a8n8W9oTGI0v0@0IYP1a49789I_
-1Iay3u7v7OFWEWV0bOK06a2W18cWz0q1C55W1000Wr5G9YO2I4v7m400OlkPG2008000uF0y
-00oegg8u3FGmCdXW7U01LL5pSu1Uu1LCpC2wV04agF8eCpGG7Um3KLb@1m1@301dnC2Ueg4C
-JP8uXEeg3TmCp45W14KL000u2u11pK60Ue3U000yF0ZhrLcDv0GX1OnSggW_XieDeVU6wZs0
-8W00NuOm@@94qK2bJPGlb6OD00OfR2@@V300ZUN2J51W0W9ab00W0mcx9SBj1boQGmsCidG2
-Tpc00000WD50Nz6rhy600X1OYNCols0e0W00000H200K0U2000W4000K6k10410k3F1h200p
-YRmTPCCArF04G00G003000GW0H8000G0010001010C0W0020204020W04010800WKW400000
-GX00080WeAVD04W00800040G0402001101044080000W6W9uZAFT300K2100020010012000
-006080018000148mV300080WW40000084Y40088f_d0OG0800200G00000100G0W01080000
-mw00hDdGxwCCsCFG00G000400800020e000WmtD0000Iz@6W040001220000GWm8@@dm@P6y
-1Y10010002W0GG2OxG3000mbfOKXVBHpy60004911FUe7300isVmBq3tIaVl1h4aG@b60000
-W001W800Wo7C0080mkqCG4000n00m5tFSll12O00kRsW_HJ3248oZv6yJz90008HE004p2O4
-000000HCoT200001002aTE63@B10WzaVKZ200Wu2_F000G0049Q856W0W0008YmaY60140e3
-Y76zl2Wi203sx40GWWgyJOhG30060W400O9U3040WW04420004C201G000Xwd0000G00WY3J
-A10W00000KI7W0MmBXlPZ20G1G1z6GW4006000eo400000a2A0k@t00090000f00H0a2G2fn
-R00W2my0I000000W7ZmjD00I1m@@BzYf1Hzpmft600Y0eNV30060000820G00009kOzPedF6
-Y_F106C0dWRGp_Hr@V20G10kSr0WY040002WP00qjl1814000008W00400W8020apyP00W2m
-w@9000W3M1eHFAET_J5nrR01Y000000020G00000040X00000008GW00000100800W00egbA
-00SoCMFIr7N100100C0I01M00G8i140000W0W10G0mM20E0DK0I9000aG1020WG0uWK0C0Re
-020000012099R00010040G01000TzWe0000Ie0010000C0078h5000Et10000L_v7000W160
-0g0GpygO700eRxeE2s00W0080000GI000W1000J000k0C1C1o2W3W000OF000u00mgu60O2s
-307mKA0900006100GU060040000300Wmd1oJ00P1GEu810ow3000GvwCKrV2000KnF00CtF3
-08Y8Yyt30H107Nhrbq64Tg130dmlqI0001eOyD00007XBIRAoGun6K4E3NcPGHl9Kiy3rnLH
-lu900OAiPkA6XVfU2Oe6OC6Y3Z2qD0KY1GO6Hjhk1G000srt000W0VWPms_60400eJy4MOtW
-YkDubTC000WoS00erzJMIj52000m20A000W000L012G008K101W00WKa1Ae0SLk1008WGA00
-1WW0eHS30400CVc10Y04wbF100A2000000WdNR13Tnun@@dG40014G0W00C0G080W8W1080G
-00140104228eWRpDW0K4W2WY008W0O00000240a20114000YW02800FJP0240WwsJ01000Gg
-6WFH39OVO00m004000GJ02P000480G0081000800I0W0280800600G02205010W000800042
-100G10C0000080218000W811040001000W100oU81v2003txHI6p00W0W0400G000002G20m
-1G0038027048W04GEaF1C010G440883Z087eR00G01010GfLO0080WvoJ000700G0000mIVL
-iHHuvG0000000800110WG0G000W80004008k_4o1mW1zD08G0000GG04000001000eSil13c
-dm@@60Y_1uNVd00H4a@d1IW00W0G44tk12W02_@t04I10222Y_@t06G00088000010048001
-0mZw60080eyV3gjE100mag200AcDAW00Gj_R0004G02I80080080902008mC3000W0212110
-010W1aIIOOx@4W80002WW8J@400CV7D3LtoR0080m9VJW0000G048G04000X0oyFXD0C0010
-mI_900W0Ono4MgF10yA0Vcx4040mimIW00000004e0000W0cWW0020H01GYG0G0103880GG4
-G8a00280001080080000I03@d0W0180084v_d0000UQ200fhx4O6004HGW41W18201H6X4ID
-28004M0e201WG89001I0006W0415041880060084CYGG0004H8I401W00Z00W410GG200WW0
-0000C240002010080000uSq2lJ000e00Y42000WKHW8I080I954A500aWK40n0G4000b8CZ4
-00WKaYZI10W0GA1DXJ000Ha2IGI200GAemGX0G00a200240200I19281200bKGmC0000000G
-R6WLcZI1008e004WLGG001G0200001W280K0G400000O0880008W000000G128020000K094
-04400040002000e010P010O2A44I01L6X1000e0000HB008OVdC80W0024X01I0200014cW0
-0060WS2941WW6I50m00K0n0m020W043G8Y701QGu01484440000H840K00075J1922WyGS04
-1E04008G410008012000WrbShZ2120000a8041G001e00041000108G48H20G0b0W00H402I
-2004HG409092000Aa000402080212210W0G088W880bkQ00G0WExD0a000Gt4WbzT20mM24H
-0Gf0W0HWp0wbWH00O8008633tWSmDm5C2GEu60GW08MS3a2z50H00KB080610G0100eN0014
-YX0000oO00GJuH100eYV00dx0tT_XA@00L_10LEaQl100300kx_1Pz10uk30gS7G8Y0W_@7m
-100m3000000WCz1mC00Ou20mJ82000W@_Ay@400CtNVSKIWO2a8v7W9oF82y7GS1_Xy3oA7S
-9GGM0v0c0ACS3a8v68HpF0NaVWi0Y0S1KYI2e4HC000AI1ORTd0mC2ApC4KcPCZCpuV0Sm@0
-Gm@1WW7201pK62Ue3_NLgKLLKPcP8u3FGGLd9HS3Y2m0FyWW_701Tu32ILL4qV0y0LLvV0eo
-CcHm7y0Wg200WbQ00m6tKL9E904082NYa9pDeN@Yo1@XPpDejV6I18XSUPewSI0pf0ChVQph
-RJmUK10010008mGy6CMy3TSR0220W3dI00000G80W@@z00mdrzUIKj@F0005001W0120W280
-0a0080000000DE3t0880000000Wg000008zQ30AG0Exl101100004qIS2Dup0mx6WWmb8lGU
-000K8200040009e000010020800040806000418G820G10JRPGO66W028erG380040200uvU
-3G500W00000G8mVy60000b_00mYvIii7F0090e0040004083400220010000001n000010W0
-580000000WChxR01000800CW0W000080WG200000900WZzJ0m80mw_600Opy@V30240yu@63
-x1300181422000G00W00800020m00000e020010a008043k1bsPWW10WYoV0083m3rF0UV1u
-@@e0G0J0100yBV3MhF10410lf@0K0100W80VSdGoz643U5I600Qst91WW0FRRGg_60208Ot_
-700W8KKU200082ut00W00FEY10YPvRcY2080000H00000JAOmjwFqhU2Fh@mw@9qxl4W1B06
-5cgHrJuFS9UPFXktF1000ViY94PFI2GH00015X0a000Y0020G0X0003wRGcs90041000W100
-e44000fJQGNxU00ua@Xhe0G930L02W00804O0WGAU00H0002400400YW00000010082001GV
-_60G000E00G1s6y_@30B202st9005641000082W081euR30G00q7E39YRW20GW9_D0041H5u
-FqCU2p@dGuL9yiFI0060GOG0G0G0QrV32xmW_mD0042GXy9CRj1jSRm_@60080e806U@F100
-Jkdh75220nJmDuOP3002AKOl1RRR0005WdWP000W200W18440xMRGZiL0EA1OPVd0040X200
-8QT3E@tWk@D0G00m5x6q_T2nbR000WeasP0100GCuF000WtR00Gp_E1oI0G8aW0040008010
-G0GK20508K010000a01000000O00I4t0WGa48000omr000W00f40S0Ie4503v@d00WphVzZQ
-vQ34000CQj1GMV0Ayl2k30Pw300IvsWZ@z0480mSzH1u200e3m500G70S00000TY0d10a409
-Yd000PW4aC000S0000WmmP000aKD3CO600eNVd6fo000D00eUYZxN200WV0000u000WA00er
-@J00a@t27OPWRGA0Ii_V2PXZHBs90ov18itbMsk2W0021Xp0108WUhCOgN3oXUZt@D0000bw
-10WvkVeeYesthYT2sOYs4EFt0002R3epmqU5LKE300100WW0ymU2HYRG_Q6iAi13jRGwRU0S
-r0O0A9kMN82A48XyQ08W0001007pam6y6qLl1W800kVm00400000acAt04002TtdG_z6000W
-1_8WW000W2fFvjA9g_N200e0W0080000kac17rR02W00GW100000G15GW0000G0000WW0800
-1BgR08WWWBrD00080A000GG000W0A6MF100TA00W0_mtWC_g8YzP0I0090H5100504W0egqJ
-0I00200080808lya0GYW104000G00W00e0W00H802000000CG8G80000400WG0uhV3W0000M
-bG02A4G@zRakF3HAGIOxFazW1001000041001001W4W20WL@VOtz700G1inF3000ei500ybn
-I0000402080G001080C20Ws@D0G200008WZmC000GW4G00048W000C000ICpt3X@N1002xyq
-nOR@VcDt008YG08I000204yV24800WC200404W020msPIK4Q56KK0cSDgmHn000GGFE60400
-eGX4gWF10G08B@@00G1WHyDOO1CcuqcXKP0G08W020000W0tvbW008W4HCOXq78000yTk1X@
-N10WDyurZY0800W0000G02G0068000H0Y2ORF300220004000C0X4I0IK402020WG10SNU22
-000ASyX8sJ0i52Gc@LyaL2px330G0G0400280400D00180G41004X0080Y0@4OWP001J1G42
-80a0X20e0008RM3wNt004G5B@@00O0W3bC0N00GZGHH1G0080015000W8b0HvA1ea2Wa@D0W
-G0000GA5100000e0500CZB3a1002Ar0000000ONZ9lY@_DeKE66sN5W000000100G0000a28
-800041e4NJWc10Gg_600L0000G001204128VAA1000G000Hr0a0Ou0W@@hG6G1GWBFanlAvp
-pW0W00S00WF@R000G2020001GHdFo0G880N@d00A0G0082l@_mAj60000dJ00m@@IW088O0H
-3_Uq6400000WA0000009100000X14WdhD00GG0000aVJJ0b00m7@600048@63cazXwuC00mB
-L1MRyl@C000Y8010yrR20Wi1Wm08H500evV3GG8000000z2eW1O34WK20409K0W00840E000
-0B00O0i1205sn0X8wYgdD0Ca2m@@I00OB00W06K0GWSS@100Giw1eK50GLJQP008600000Eh
-ed1mkm2GH18@OL8600qilJ000GD00020C4n080W2W000i6000O00001000104WV040e0S100
-o2000C0000000u700W9OF0G0JPnPm3r9O000m0o000W00002000o5@@l200C100y3W000qOf
-4fyx100Wnr_Dmh00WHULF00006vL0X900Kvl100W6qTUT3Q0YHz0YQk@90WOg700000YQ_k@
-n0W43GerK56k100W0W000K2U5bY@GQu6K8d4FuPGEJ9a8aGZZ9X00GWIuO0040GDlCW00800
-00010GWd@JG08GGnh9S8c1000000ClKlB6jc@pLwB1m@0O7Ug8G0046k1K0000004C0l1DIP
-m5y68010O7P3EIsWOnDW01GW08002000pWPmQy6000WSx56_ucX2npH48G808804005NKOGh
-v90040010I01G0YeHJ0400000W04101PdR0088W5qPutP3G40000mCg9yAUFY1100G5lq244
-0140016G00G01004080100020X03GH00G01CX420008G940024W0a000O8W0G0H2e81e214G
-m@w6G000m00G82Ae020100000G01000000aE3422W00000880400W0avk10002gvp000W0tX
-330W0020m00G142jo0080000040102080200CebX08002052010prt02G00aW51DGeWaol1G
-000800200GGW0240G20WwNJGzG4mU46G060OVT6IHs004080800MywXk5z0254820010G070
-0W000W8q_l1G01480010000W200W0G000W02280001300W0200800028080G0lLO00G0010G
-0dbO00200a00000eU2XdXMuJ8xR32uV6000188100G4000290010000810W1009G0XW0W004
-4008EoTv6qgX1NOR0100WtzCG0880010000W0m00000080082y@V307e0i9K51n@GNydKZl1
-04000WH0000HiCV3W0I280240000qb@6W8020502ms4900800W00028014208W001E0nWhzD
-8LH3000ZIP08ePD6oMqWE_JeUjP80800WW0eHD341000G1000800200G6m00280000040008
-00W0mFK9010G0040m6@600W00200mQW6000406040000000St00W00010CpW1xCX100GmszL
-P4J340000022G0408W00mNmCuH8300W10009u8c4wdC1G000W010EOtWbPIO8T30_m0aem3V
-T6I0@U00H0IW1044HG01ne0OeG080gY0YW41G090GAW5W4Y24X4G020W01102200W2G00000
-00W41G00004040G46000G8280040000004G020W03305000000OM602Q4qWXObu@V6K200y9
-q928018I44Ga8800O020K822WG1W0X2e1A2040a0100044W32GWKWG00GG00W00001GG0000
-20mW040L900e5HW800000W2b0024000008sjt000wU3zR0C0000010W0W0kwtW4GJOkV3A1K
-5000K402089000A0G400001a200000IGg00040810a2Yo0800GAI9G40000850H0I0000IL2
-0P0008bKW0I0000I108100000f04H0200aIA0_@t00TWKO0I81G00GA010Y000eW20H00000
-A008a0000aYP00GiS6KbfA000I8A0000Y0G85000004WC000000020PIK100HWK009004128
-00C000KW00m210000G0A31100014042020AG0G8Q20e004P4H6000G020QsIj1c3404I800B
-00H60KG5x64Fb10000G48000H0OXRLAf8XsoD0a0GW80W0C0020W00m6G820W8081510O0KG
-W8C0W0A858Ge8080G8E2W80048W88CF0G052meG0J00W3a1H4100840G3a204WW8000WtE3G
-900IWG00aW040400G80WWG020Y0H41e800001480020020eHTzdqyl12Y004000W10900004
-G2480W08ICHG014000e0040100W009G000008a00G020004001e00WeaC00K20I20AW0809a
-O000240008W4000A20A48800G010W00000408WG0G00qIX1njRmf7gCLl100M00W8W140001
-WWW00G8KVZ08044G@D484II102n800a8084zk1GY0OAqx0610Wf001O4002404Y_R0CH0A5w
-l1Z00OK0F000WqUqVIM060H004H000O10G01O8Wj0410ne0010G804GiSFqHx6010040GWOU
-00000WjkYwFtnFg0GVa1OHF300S70ex60wZCW300eY@yKqp0mTm1GqF30000000GHqJC0000
-ZuL0t5i00mMq60We000KnF00000mFg0000008q66EL00u2W1u70306WE000T000W2000@W4G
-_1_Xy3s3G7u7WISF0b8v0AHoTGYax0k8t1P1KA0F450387000@V0b5W1uYO2i7G4W9WIKI0b
-8Y1AH4J000@0c0C1O4Bt3TKu140000@A0C_A0000C2004ryvLad1GKp3GqU5000WW7wWHKbA
-pCZ3_702_m34yG08eggGm3Fm@ggYPc10pCZWUu11zNL2wm34qX7K5LLv1FanCcHm@1WWP200
-0GB08OM06GLLUm37yF04S6p8uX00GLf2000W@1OW@PYzk210023IRGFuI4hT800Ksh2dA200
-1z@Rmw@6S@l19@RGr@60010008G0000XtBb8H63ojC10200WkE8g0mWFcbesU90000UGREVb
-inupXGL00uQze0G00asc1FnR0008040W00GW00002K6d100W0Yor00080x2@G4t6W0000000
-nTp600Wc3W01GLq9KrD3HZN1G00eK_F14G4H6y600200W0008G2000306080Eqc10H000100
-000A0008ehQ3g2t0G0000G0Ws@F1GfB0lnuH1_Iyzj15gwHBv6KGV20G020Y00W02001CHW2
-80WCxD010K018W00K00e0W000840000110G088000G01G00XGG04Sbj10008P300000020K0
-0080YZuDe7E3wqE14040000W_ocXI_91802101003000HAO00Y86100E0O00K122q@l108W0
-089100G00100a140024000100kUp000e000W1g2A100Pf@UdmKN6K4U27zRG8xLW400eYsGo
-zdXT2J00e0GDpC012GOb43wWt0G400bTR040001200G0G0_@t0GbE0rKPm9@C45l1ZoR0020
-G00000408QpKbKtD001Gmzx6CVO2Y0002GaXFwJ0H00GEzOiRb1a600wus900e05Bp00G811
-00GjvR001800200000G0120KwV200104W0008G081R3UpCXbxD0000002ieujDuTp4sNNeOz
-Cu3@4000G040023018G00W9@D004Amz_6001eOJS60080W000epO90LW0yh2FbflnAz94jl1
-80GG00000100Pj@402W0r@l102004000SZe1008038DXZ@D0000k@00WSxC8WTa0Gm0KLl1R
-wP001e0IW0G00W04408004O001W40086A1m4G00848021208008W82000018080O06KbXGHC
-0m0000W2iKbJOMJ6kgJbazb00100C2001W0820X0W02001001GO01Da02H1HW00W80808ijl
-100000241004100W00480110G0A080000W82W08s_4c@t0W_A0000GYWNY4Mv1005000H005
-100G4f80008280W00044010W854G004HWK2000Y0A1850qaK0408a2281024GAf000G60040
-0GGK0000f0WI001IaYK0008100000uuI000fI000GaAIN68040aDRE0840G0G0G0G80O0000
-014100O02AGC21620e4080Q80A0GW0I800CeW08a0W0W02202H31062880900420G1400K20
-05Y0nC40WX444G000X00000009DG0004000404000066JU2TFm30000004400i80000W00O0
-0800ma06000003218440W080W0G0060280G1u806GW81I3K0G00083800100A1004400OGW0
-YGo08400C0B0GG004000OL402o10003mZM6yFq31yF30W80H000h0P00W00H104I0W0001HI
-W0200YG1Y00WrwD00G452C0808e00020002004480080g038020402W8501G001WW0G10000
-0G000a6FW080H0aci4Xuc30A1000020G0008040W88J0042WSXC100W0o5041002WG0G4a50
-1619kGV008Kou20H0WG1G8041w300ZmcB8B0008Ik0W800e0CIA060DN000W1Fo21W01Ce@1
-3Y9dX@zv10Pc100G5FyGa_7WefA0HBpCYMcPyFLLfALTGLgAwgKLq7wXeLbAHhALU8JPyF0o
-uX74z@08wCVGqPcXeLL5FSu1_700yF0HxX7YsV000uEx1HdP6WMLLy000yNcDnCL1G701YEW
-E0u0T0A0w0K047e08g10GS7eZe6G7GTWEW2Wz050Y3A04@008_1yJy3e3e7mFG185038o00G
-y3aXu7iNK090000W4W2GC06000q9Ju4Q5tWQNi1o00000000eF00WnN1WxW30_H500yA0yZA
-0aHVO400mFg0m1t1WCw300w60ex60000et@t000m2s5002@l200QC9IJLLSaaulAJKQGK1QT
-Kk4XhMHiu6CRx3reR0000MT000Ledmmt8L0hDR_Z100Mli76Rgs7obEXTuVemz7cvE1W920d
-tomw12TsV5001011000084ij_401000G01uCS3oqc100805@QG3l90000xX33w_F10WA01vR
-GiB64aF9xrZHuPU4TV20080_CtWAPC014008080aG003YR00000002dDXRmmp6y@V2480102
-00yWU2dqRGe@6KiN8n@RmjpFiBj1lvdG8o6i6k10G001024i@l10004100W0G238nQ60LM00
-40GeLT9kXFXEsPuTk42u760W040000000Kiqk4FLd00m0WO_J00G4Gnv6y@l1Q400QlsWr_D
-00u0GKy6W580OoV6_NFXkXo9YbnMInfmyb00001000e0zO86k4CSm4yhF3000W0G00igV2bn
-9HWS9i8NHJQJ20004F300000GAgd100080004AiFXnpP8h3I2_a70001TxRGqw90W0000mPQ
-Px60200eO@429tW4Fa8XV3cpyaTqWX000Ks36Kzl10W00Ycq04000W412618XTWD0040GPb6
-i7l1hpRGWy948N21ynpdpCyb_340W8EKd10010000e9C00G000AXK600G01004W0004000Wo
-_I00W0G@e6yzWDdzRG71FaEI20001YTt0200GGC000YK40H0000I90000H000000g6950Y0H
-000028Y800008WK00040102002850000X00I42004G000G4000100002mIy6KNY1xsr20040
-0G48hNy0H00041002200008W00084000208e0G0W001e20Wc004G0005010000G_A800W200
-K00400B6030WX00AG00G100e0060420P1O0m000W000o00e0080840CiEkSUJbXK@P00C000
-8800O0I008W0C000e800200030004400000WC5H410000OG00G10000084060W00WG2O008G
-GA000400010W024018060H00W1900104020@0opNsF000WeHE3g_t0050a0008008H088IW0
-G0mCf6000rH0401008000XW000K800e000G001202YK814800H00U0t00a000C1080108G10
-GW20mW@60500eIhMW002yuF3nkPG5w60W08o00020OWiOuCG4008061WKvCWB0000PYQ10Ge
-8n10410W20G0G4K700014EGM000GWy20HaDd18A00020EWe000W0u00Y000208002YImuXIl
-5ILL5f@08w0vCmX7yF00O6p4TLgAw@000GuC0YMcP4j3FuVPcnCcHbPCJq@dDN2ou@CbHLLH
-b7UGq@3WeLzXOvCm3@1W@100LL5qHZ3pZRI4xc10P000m0G000a1e08ICS6u0P4n0x1g3a1K
-0e3e0GS000y23K04t108Y1yJS783e6G7Gp2m008w00my3eZ83G7G7WCW2GW09Ga1aX8383G1
-Gc3vIOOez8Y80yRKr9hXKg@F00WsBCXjlXlb8@v1000bz10WOjIRjTR000C5rE6J8dJpKH1I
-u0OIUF_YQcaxT2000bE10WGvD80mhoUG800TudaxHTpBjvVEWZG0IU0fEKGws@7000pu300e
-8bvdSFAGG50TcuHNTKrWLB000Wi900aa66f9U800WwBtyetHsEv43WiD0JviH@alTKV595uH
-GcoX020uyV9000yCLY7V4AKV@2rx6600W0EcHE0090@O_mw@6GP00e1lAQ7HkxLH500JmxqI
-0E50OyVC0410iADLvzF3a00Wo@h000AzMJZj5q@P9z@LK@Nbr@JXzVKQ@@4t@Dvz@IW@dau@
-7H_VHc@F4w@1f_@Fi@tZx@x0@VEo@V3z@rO@@Cu@7Z_@lm@VB_@@@@@jP@@Qu@dc_@dn@VP_
-@d8@@7w@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@VcyrU0_@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@B5000n@@C00On_@@F12000MX0u@@@@@t6000
-G@@d0004000Wc@@@V0f@@@@@@@ZD0Wp_@@zG000m@@120f1u@@Y8000y@l18000_@VU00vm@
-@xnB2d4fG2@@J5mF1W@@T2200m@@HnT00ec8XcNOc@@L10GusN68b0K2@@@3200a@@V00e3m
-PKJ_S530000jA00KZo6dOzm@@@@5132000Q0mW@@D0SY3moCA20048uA6w0m0000OfPKnt9T
-z@@6a844X0X8100G42G4100G2X0H4849000u5a506@@@VA6bMY13zQ8Kg0X45m9@@R0G8200
-0002a0HG081_@lAWu00st3312000X8HG000aAW7H1So@@6880000009Y440Ya00@@B10oX00
-W38u40000ES0000GE4m100XJ0000C000000W43m3oX00WZ890000GG22Gg06Ga4o9G030000
-W300u@@4000Y45m3@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@V208Mx@@@@_3B2000wpm9y@@@
-LSFJAZC0oh1u@V8100Gr7_3PF0P9bI00G_QSzC@@F1miC0@@tudkI000Wni00m4yDkzW4000
-A_@@@@_j1G40mhkC0000DVo9X700C@F3002G_@@@qH_Pku4aC00y@@@HAy@@@@@zy@TN@@st
-@dT_@Nl@Vrz@Fz@@1p@@l_@@@@@ZlZ70001000i4100A6ehs7520mHPA_TH0008TVX0DR0Cy
-WbJQo0D10W@@f2004m@@810Wn@@@@N3Hq@@H200Zp@@@@@@@@@@@@@@@@@@7@@VD@@l3_@ve
-@@Dy@NZ@@@@@VM_@VS@@5@@@C@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ev@7
-w_@Vs@Vd@@FS@@1@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@Fd4000_@V3ma70@@@@@@d0W00u@@D008v@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@Nb@@3t@Vm@@@@@@@@@@@@@@@@@@@@@@@@@@@s000O52000040u@Vjw5G
-800iA@@36040W@@@1qg1m@@V2000LO00Gr12z@VN00ELH0000800u@V9U1uY@@J3G00000W0
-000000K1_@F100G0@@R000W02000JImmr2_1Cf0u@VC0080y@@U00G0A7n0000eqZ00s8814
-000@@R0420WN5Oud4m_@lYM7I000pp@@68W00u@@40040aGnU9AO0020040000C0000008UW
-0000aGY29W0088603W000afX12002ELuX@@JxC33000G3MW0G0000I0201000020W0000000
-21000009800G00@FaGB1iTAI20200006000uZ10000WW0000000204IXn0G0000W00I1mW08
-OBx160010W20002400W100Wl140016040HW041G0020A0W01G0G2000W00190022004020W0
-0000800WsTmivSCG0W0000800024XeOWu0000030G2W00080800G00001000A04W0pZOm@86
-aeHQ4020000080100000104G0W00K024000q_FaY10G000004001a2000900GA4000080G80
-0000b0W02Wm@@cLoY10004020000W008WGGiC60y61100000W20W00000G0028010000KW00
-000088080000G00WavIQ0G0W00001080080C040W00000I00a100Wg400W8000GWW0W02000
-02m800W020ZWe100004G0090004001G020G0C03m@@Z100W004050WG0000I00W000180080
-00WhZ82Y045GG0001040GG002W00000205W0100G800X041040001GmpCc1008o04000O00G
-00W004041H100G003000W3aQ100i0X10010WI0G0G4K701004CGT000KGu00Ia5W18A40020
-84WZP00WebP6@BpC_70gyW7Y_V04jg000mmx3HBpCYcggyWCpeALfo3n0O00Y_G74jgKv@Cp
-281GhA0@@F6G00430W02G6GDWCWQ0T050o0A041000UB050mT002A0T0t1w0g1q1K001e0G4
-G1Wu700H6WEWC0P0T0o0A0a1K0MGIE008W@@R0mO1m8aC0000a200W2fC8693_@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@BVy@nB@Fyp@@Ez@kN
-@Vxs@p_z@hZ@lwv@dk_@el@@vy@RU@@bx@Fv@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@VNH000y@VE000evB00y@FO0004_@d700iF@@@
-@@@CG000u@@M000Wy@l1000ue200y@VT00W0g1GZ@@P0000X500W9DWyO33YK8100xHPFav@
-@90Qp0u@@@@@@@@@@@@@@p5wD4000000Yccn0000qY300_@FD0080H1Wo4DC0uu1u@@@@@Nt
-HZIO_8I02000uY0u@Vd000aByW85G1HXYq251ubG4X8mO01UW0IdMM400WmWG7HJ10200GW1
-0WWp18AWJ000GKa46@@d3mB000LW00oV004yL2800010002000400G800W0000n@30Y80G00
-0WWe0E1100GI1HLQb760000000000YIZc0m80C45G500W400Zc00000K@1m@@@@@@@@@@@@@
-@@@@@PMQCek5WPeOx@@M000o1q700000n2Hdy@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@tL@@Rz@Vyw@@E@@jx@@@@@@@@@@@@Vfy@Fg@@@@@@xw@tE@@hx@@@@@@@@@@@@@@
-@@@@@@Fu@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@F00001000
-WLS0_@@@@@52040000Lq@@@FLY4_@d7000qXKy@@@h200G8xXV8200y@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@Vi@@ru@@ez@7w@@7t@Vn@@@@@@@@@@@@@@@@@@@@@@@21002u@@V0004y@l1000
-01000f9008fW9RE81004000e6@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Xx@Fu
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@D001000
-KX@@@A0001@@d3001W@@P0Om3m@@N1040u@@Y000G3500u@V81000_@V20080000Q_@@a9Cy
-0OH1W@@@@@@j1001y@F3W5T0_@@@oMcv@V900CB@@lS0001AUnWeNC0020GH0Ly@V2WbE0_@
-@@85s8DXA2g9XS5O00WPLJBx5cZ40200_@N20R80@@N7081W60C8K8965YXxZCeIZA_@VC22
-00D0Om44U000000Wys@@@@@@@9ITOQF900u1uH5Et8n0s300@@39000H80000009424HWGa0
-00G8@@@@tXHl000050W14Z13r0mm@@_14Y00000W09G440IW2a0GG481200000YGm@@60002
-C50900000o20u@Vs4400000W4H220HI0I41GG49106nX1009Hf0O00mHG0000oX0E008S200
-041vG00m14S200007EY18XK0e8AWJm900y@@@@@@@@@@@@@X0t302kieP0ouTG3W000000Y0
-000002041200@@t20WQrxzOOXlAsB0fHrC8s0C_@V30O40ViXHugmy@@64800g@p000019cL
-n@@R0000ri00mUSXy@@Cj4OGjhp40h400u43Yb400G0NMQm15LiAB300010W000018G00001
-40WcOVeDH3C000yde4@@l1GD6WmTR10G8m@@a0W12e8Na000GID008SNIYK81GW00RXk1000
-080G000W00010004G00I0mheI00508qtDo_L200V9P0toO58z@@@@@@@@@@@@@@@@@@@@@VR
-_@3vdPfNU4_LBWY00_@FA000a0010180020004402GUnC0G01u@V30840aJf104000O00004
-08@@408002200OBD34000000Wc_00mnJsCkM2JG@0001WynKfnS90000cGc11dd000en@@f2
-W0W001500200W0480000rNT20020@@t000AG0000H0000G00000I0008WprPeVz4gFt00EB0
-NPPJax9yKM50GW00108qek4G00031tW5zD0W00u@@6G04G04000400W40882030G08010002
-0000WtuayIu4Y4kBB11000pZro@@6010G00000C00000020410oWt0XW0W00144228000000
-eWW0000040040G00X020414m0Y00GGG100W22G04G0020100W008GxS60H000eIg0G0880W2
-0GGW00X0W0b0G0214002010W2001W00G0004000080mvQ60W020010n@@UKJl10W0L0801yY
-M2800200G00008002080000280120000008020W2280W02W154G04K100W04004G000W0008
-014G0vrb0z20008808000401W0G0101080208WsxD04500280mCyDO2V38W00y@F9nic000H
-WltD000A000W020e20000W00GKRC30020000G0080000W0408040002W000000000m020004
-41000kR842000002020020W0084040008000G00ICbO2Dnn000WWu@Evk@@RO@@5w@FX@@@@
-@@@@@Vg_@JDJt9NH2Wo0m@@K100W00028000X3pCG0000014XEdh8lU3kUs0800GdFd0000e
-0eD0000El040000G00800000cvb1rGRmyP6y@V8Jp_mAoRKpyC@@R0003@@@@ftNC040Gq@b
-1W020001000804200m5mI4YS2W00000200G0WOHR6ojs00G94nYb08000W0105RR0000Yfeo
-PYP3wxr000002008040000WGG00000W80000W0014ELEXLbD040W00G8WEiJesC60000Yn00
-OqR3E2mWf0CO8O62Ap080000400sAp08000TDRmAqL0000400e0280400m0RDRmnr60001W0
-W0000I0W0000001UlsWLYD00288H00WdlC004000AH0W0W0H1O0040000_9G101000008Y0e
-NR30W0000G40028000K0e808G001owMbZeD00W0W020180002G00cHsWVaD0200ma66000Ge
-yw4003080000212X000W7iDGG00W200W3bDu@V30x20000000048438WliJ0W000420010G4
-0001MvmW4cJG004mfs9Kpy3PRp010000200G014oU81004GT0OW004YNkD87E3_@t0W40000
-10_Pt0000420300G00kzi1000W1Y60SOG200000128q2j1000G40110240OuW4EPdXFFgu@@
-@dh_@uk@@jy@RR@@rw@Fj@@@@@@@@@@@VfxuM500h29brI6SFqYD3zv1Jikg04k0u@@F100G
-oI00u@VIcqZXtgJONl7ovQfxgP00GCOMsC0012ug1LMGEDG7C0zpBnas6iHV2pZRmFzCCteD
-r2Q30004w300pKd000W08040h8A1W00WU4VW000q0ygy@@F00SS@@N200W8@@lnD1f5gz@VY
-@Vdw@l9@@Pw@@@@@@@@@rX1CGY6W@@lAaMa000mAU00CqRLcZ2i@@bx0RCAO36G220nWdGa2
-KLLGB@@Z1H90Wd1ewsQ38022000G00080440XlhDOBR3_McXpu3100ezMs600408ZD6wctW3
-06ukiSkjsW85A24wFGNSIK9t6ji3Z000040002WW080000002eiS3G004yJ73134IMU9KHl4
-8000E0OWG94w4x@B1@@Hq@F4_@@m@@@@@@@@@@@tU00MR9w2pCpTD@R50PP0IOMYWdLv@ViZ
-qrZ8ha00miOcrIaGjA@@R60K6WNYd90B3800000G8u@j7QREA0004C100_@73W0W0000G020
-Yy@V20804_2tWomDG08WmeuC0000SkPg00OHbaDC80010002G00000480080emdP00010202
-W@@Z2Sz1GVxR800004G0Gxr9CGD30001E0OWQlP8eab_@@@2i@V0y@3G@@@t@l@_@t@VF00M
-rv4Bq@@@@@@@@@@@@@@@@@@@@@@@@@tUz@hV@Vwv@V__@bt@@u@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@xt@V_@@tT_@Rl@Vsz@Vz@@@@@@@@@@@l1000m9E00y@VE2000_@t60200D0Om@@a00
-mNu@VH1lO0y@VE0G00YK0uB8ov@@700mIcLF60002_@t60002vJ8n@@y0Sg1e7ZhkAuXa_p1
-000hk00Ww9YQW1600G0y@@F00mjoU8g@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@msY20Gtx
-@@2b453BUPmbN9y876lIn001401200PpX180000A10zKXX000WWvm020WG1T6q2M2bW13084
-W@@F1000bG00Woyof6ECkphYF_m00W04021W85s00WFPTQUKzL50W00G00000G0e4C900804
-zG5ntvHE4C0200u8G30100_tc1W7204001qEe1p3cm2POG4000001mlWOG000iAEI6Ep0014
-020000800MGd12400088000e20m010W04001848Y00c2m0000uM200002000400W80m@@900
-G000W00000uKAC8DH3sJZ1a0010000000XigM20082wLh540W0000WoOm00W0W000W010000
-1024G00GW00W0G0G0G00100800000GQo@@L06000400000IW_1C8oX400001080000WHsZ64
-un3pyPmZZIKQ83RFQ0004m@@P0021GtV60080u0W100400801e5I301000oU0020C000G000
-q0pVKnDWCade44000E3q00004K020_@@@@@@@@@@@@@@@@@@@@@@@VO00@8@@lqki8z@FO08
-08A6s9000mS600_@t918042000W0004Ib1200000108002000a0008010001PRW008WugI00
-0WGQs601000000OWs60G0W8JR300Gm@Li420100001abz3RgLnjQI8008e_O3gwcX6bD8JPF
-W000iIT2v9pW0000Gs60PC@GQn@0W001480m1s6Sxb17jP040008000G010gJ8XvsCeTS3kW
-cX3oCOTi4000GOA008luAW0004M63HASo2QF001001W0GRt9iIj1xRPWW000G04GJSP01W20
-W0000500000000GWX000nM1C00Wx30200102WCqJ0400004008080008000W24iU20G00408
-0abE300A0cNpWFzOOZT3010G0G100004n@@9020W0mJ0180100210tin080000HC0vOR00X0
-8401480080040000WG00008002K0000Xv80200208W04020W02003010000G30WG00000W02
-0X200K30000002W01000iSD340000O0YA8Q3G40010W010040002ag4O0000a00000800ndR
-000080008AG40080010G0080008010008G014GA1t00001004G020004G02K000W10WBmD00
-0W00006W10W13O0G002G00K0030000G0082000048W04Y000jYP000000448Thp0000K0002
-rdP0010WcnJW000m31600000820Gqr6G00008G04001WoxIG001m3s6008Gk90308000m000
-080mkP6080020010G01000SK8I00800W04G0i@_40mG08001e_13000AbJX1lFO0804aJsCW
-K00GD46Ccl18000lMVfWj@@Ny@xL@@Tv@FN@@@@@@@@@@@@LRqT3m4C0R34rGP6q6dATQzmM
-nF000W4600mQ3p30408OjAENR3G000JAdmJtI0sC1uM2g00W0C286jEdG1r6Saj7W0G0000W
-5BS5F4o3W010004G044W000018W82100400200008TYP0000akYDOAPL00SUSoWA@@J2000G
-021004000O400000S_13oEtWlZD0003GwwF4Zz6VbR0uS4Wu3Nw@@408C0CYk1Y000sisWDn
-V00G0GtuOyk_3000uOF00SEvpDH@@Is@d4_@7f@VHy@Fa@@@@@@@@@@@@@@@7Loua00G4v@@
-@@@daRo210003H10W@@Z2002GRr6y@VH00el_@tfllD8ox7_@@70m009A4rwQ9S19IO400oU
-Wg@@N20GzHDr@Fpz@na@@Bx@tI@@hy@@@@@@@@@XbrB020WpbDO@Q3wNsWuTt83v70000dnD
-30804_@VU00W0NAOGrr9K9U216ZHTpI0u008_O6sP_dLbJ0100100000G048100EBF1W0000
-00W4K00yiU20002010000001040qzwFiCT20000HF88qoCI@@R00402015W06000140G2800
-9G10W008000We0220400S0m0D0O000004005WW28oJ814000W000p6dXtnD00Wf70000001G
-vOdGJs900WWu@VRW08000X01W00200O4WAK40100020000WG28e00000GW020P4Omh36G8G1
-00000G0G00100040000G04Bl1Xnp0eC2000000204_@N20240@@R30X0K0010jqRmpr6Cel1
-zbR04G4WHxJ02W4Gws90W00OHS9400000005Y05ma06CcsLvO@@Du@NZ_@pm@VC_@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@FV@@n@@@Fw@t3@@xu@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@bP@@Ou@7c_@Vn@VN_@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@l4600
-00wojIsF60G0020000K40000WXC0C0m40000WW4088204210YW009G0W280m04QCcX4IQWXO
-0C0040800O22m0020G0000WcuW160G00000W10A82030000QqtloCC0W0040000ivEy30_@V
- ;
-' // Loading device with a `jstart` instruction.
-IRSCAN 10, $03cc
- ;
-D = 12;
-WAIT D CYCLES;
-' //Loading device with 'bypass' instruction.
-IRSCAN 10, $03ff
- ;
-' //Loading device with 'bypass' instruction.
-IRSCAN 10, $03ff
- ;
-POSTIR 0 ;
-PREIR 0 ;
-PREDR 0 ;
-POSTDR 0 ;
-POSTIR 0 ;
-PREIR 0 ;
-PREDR 0 ;
-POSTDR 0 ;
-' // Loading device with a `jstart` instruction.
-IRSCAN 10, $03cc
- ;
-D = 12;
-WAIT D CYCLES;
-' // Loading device with a `cfg_in` instruction.
-IRSCAN 10, $03c5
- ;
-DRSCAN 224, $0000000000000000200000008001000c0000000466aa9955ffffffff
- ;
-' //Checking done pin status.
-' //Loading device with 'Bypass' instruction.
-IRSCAN 10, $03ff
-, COMPARE $0021
-, $0020
-, X;
-IF (!X) THEN GOTO F;
-POSTIR 0 ;
-PREIR 0 ;
-POSTDR 0 ;
-PREDR 0 ;
-IRSCAN 10, $03ff
- ;
-DRSCAN 1, $00
- ;
-
-SUCCESS:
-PRINT "Successful File Execution.";
-EXIT 0;
-
-F:
-PRINT "File Execution Failure.";
-EXIT 16;
-
-ENDPROC;
-
-DATA TMPDATA;
-INTEGER TMP_DELAY;
-ENDDATA;
-
-PROCEDURE ADJUST_BIG_DELAY USES TMPDATA, MAINDATA;
-TMP_DELAY = D / 100;
-TMP_DELAY = TMP_DELAY * 25;
-D = D + TMP_DELAY;
-ENDPROC;
-
-PROCEDURE ADJUST_SMALL_DELAY USES TMPDATA, MAINDATA;
-TMP_DELAY = D * 25;
-TMP_DELAY = TMP_DELAY / 100;
-D = D + TMP_DELAY;
-ENDPROC;
-
-PROCEDURE ADJUST_DELAY USES MAINDATA, ADJUST_BIG_DELAY, ADJUST_SMALL_DELAY;
-IF D > 2500 THEN CALL ADJUST_BIG_DELAY;
-IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
-ENDPROC;
-
-CRC 324E;
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Davide Leoni
---
--- Create Date: 5/4/07
--- Design Name: vulom3
--- Module Name: ulogic - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: VME address encoder and decoder, I/O ECL configuration
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-entity ulogic is port (
- RESET : in std_logic;
- CK50 : in std_logic;
- CK300 : in std_logic;
- CK100 : in std_logic;
- LEMOU : out std_logic_vector(2 downto 1); --
- LEMIN : in std_logic_vector(2 downto 1); --
- TIN : out std_logic_vector(16 downto 1);
- EN : out std_logic_vector(4 downto 1);
- ECO : out std_logic_vector(16 downto 1);
- ECL : in std_logic_vector(16 downto 1);
- IOO : in std_logic_vector(16 downto 1);
- FLED_T : out std_logic_vector(6 downto 1);
------------------------------- VME interface -------------------------------------
- U_AD_REG : in std_logic_vector(21 downto 2);
- U_DAT_IN : in std_logic_vector(31 downto 0);
- U_DATA_O : out std_logic_vector(31 downto 0);
- OECSR : in std_logic;
- CKCSR : in std_logic;
- HPV : inout std_logic_vector(15 downto 0);
- HPW : inout std_logic_vector(15 downto 0)
- );
-end ulogic;
-architecture RTL of ulogic is
-signal ckcsro : std_logic_vector (35 downto 0); -- write clock for registers
-signal oecsro : std_logic_vector (35 downto 0); -- read enable for registers
-signal hplx : std_logic_vector (7 downto 0); -- data register for logic analyzer
-signal INPUT_ENABLE : std_logic_vector(7 downto 1);
-signal downscale_register_1, downscale_register_2, downscale_register_3,downscale_register_4, downscale_register_5, downscale_register_ts, downscale_register_vs, downscale_register_clock : std_logic_vector(3 downto 0); --15
-signal delay_register_1, delay_register_2, delay_register_3, delay_register_4, delay_register_5, delay_register_ts, delay_register_vs : std_logic_vector(3 downto 0);
-signal width_register_1, width_register_2, width_register_3, width_register_4, width_register_5, width_register_ts, width_register_vs, width_output : std_logic_vector(3 downto 0);
-signal scaler_pti1, scaler_pti2, scaler_pti3, scaler_pti4, scaler_pti5, scaler_ts, scaler_vs, scaler_mdc, scaler_tof, scaler_dead, scaler_pti1_accepted, scaler_pti2_accepted, scaler_pti3_accepted, scaler_pti4_accepted, scaler_pti5_accepted, scaler_ts_accepted, scaler_vs_accepted, scaler_mux1, scaler_mux2 : std_logic_vector(31 downto 0);
-signal scaler_reset, scaler_mdc_tof_select : std_logic_vector(7 downto 0);
-signal or_on_off : std_logic_vector(7 downto 0);
-signal ts_gating_disable : std_logic_vector(7 downto 1);
-signal pti5_ts_alternative, delay_register_beam, width_inhibit_register_beam, width_external_register_beam : std_logic_vector(7 downto 0);
-signal mux_selector_1, mux_selector_2 : std_logic_vector(3 downto 0);
-signal branch_en_with_mdc_tof_width, dtu_code_select_i: std_logic_vector(4 downto 0);
---signal u_data_o_s : std_logic_vector(31 downto 0);
-signal cal_trigger_disable, com_run, dtu_error : std_logic;
-signal debug_1 : std_logic_vector(31 downto 0);
-signal trb_busy_enable : std_logic;
-component trig_box1
- port (CLK_50MHZ : in std_logic;
- CLK_300MHz : in std_logic;
- CLK_100MHz : in std_logic;
- ECL : in std_logic_vector(16 downto 1);
- ECO : out std_logic_vector(16 downto 1);
- IOO : in std_logic_vector(16 downto 1);
- TIN : out std_logic_vector(16 downto 1);
- LEMIN : in std_logic_vector(2 downto 1);
- LEMOU : out std_logic_vector(2 downto 1);
- INPUT_ENABLE : in std_logic_vector(7 downto 1);
- DOWNSCALE_REGISTER_1 : in std_logic_vector(3 downto 0); --15
- DELAY_REGISTER_1 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_1 : in std_logic_vector(3 downto 0); --4
- DOWNSCALE_REGISTER_2 : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_2 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_2 : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_3 : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_3 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_3 : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_4 : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_4 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_4 : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_5 : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_5 : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_5 : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_TS : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_TS : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_TS : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_VS : in std_logic_vector(3 downto 0);
- DELAY_REGISTER_VS : in std_logic_vector(3 downto 0);
- WIDTH_REGISTER_VS : in std_logic_vector(3 downto 0);
- DOWNSCALE_REGISTER_CLOCK : in std_logic_vector(3 downto 0);
- BRANCH_EN_with_MDC_TOF_WIDTH : in std_logic_vector(4 downto 0);
- WIDTH_OUTPUT : in std_logic_vector(3 downto 0);
- MUX_SELECTOR_1 : in std_logic_vector(3 downto 0);
- MUX_SELECTOR_2 : in std_logic_vector(3 downto 0);
- OR_ON_OFF : in std_logic_vector(7 downto 0);
- SCALER_PTI1 : out std_logic_vector(31 downto 0);
- SCALER_PTI2 : out std_logic_vector(31 downto 0);
- SCALER_PTI3 : out std_logic_vector(31 downto 0);
- SCALER_PTI4 : out std_logic_vector(31 downto 0);
- SCALER_PTI5 : out std_logic_vector(31 downto 0);
- SCALER_TS : out std_logic_vector(31 downto 0);
- SCALER_VS : out std_logic_vector(31 downto 0);
- SCALER_MDC_TOF_SELECT : in std_logic_vector(7 downto 0);
- SCALER_MDC : out std_logic_vector(31 downto 0);
- SCALER_TOF : out std_logic_vector(31 downto 0);
- SCALER_RESET : in std_logic_vector(7 downto 0);
- PTI5_TS_ALTERNATIVE : in std_logic_vector(7 downto 0);
- DELAY_REGISTER_BEAM : in std_logic_vector(7 downto 0);
- WIDTH_INHIBIT_REGISTER_BEAM : in std_logic_vector(7 downto 0);
- WIDTH_EXTERNAL_REGISTER_BEAM : in std_logic_vector(7 downto 0);
- SCALER_DEAD : out std_logic_vector(31 downto 0);
- TS_GATING_DISABLE : in std_logic_vector(7 downto 1);
- SCALER_PTI1_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_PTI2_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_PTI3_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_PTI4_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_PTI5_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_TS_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0);
- SCALER_MUX1 : out std_logic_vector(31 downto 0);
- SCALER_MUX2 : out std_logic_vector(31 downto 0);
- DTU_CODE_SELECT : in std_logic_vector(4 downto 0);
- CAL_TRIGGER_DISABLE : in std_logic;
- COM_RUN : in std_logic;
- DTU_ERROR : out std_logic;
- HPV : inout std_logic_vector(15 downto 0);
- HPW : inout std_logic_vector(15 downto 0);
- DEBUG_REG_00 : out std_logic_vector(31 downto 0);
- TRB_BUSY_ENABLE : in std_logic
- );
-end component;
-begin
- trgb_1 : trig_box1 port map (
- CLK_50MHz => CK50,
- CLK_300MHz => CK300,
- CLK_100MHz => CK100,
- ECL => ECL,
- ECO => ECO,
- IOO => IOO,
- TIN => TIN,
- LEMIN => LEMIN,
- LEMOU => LEMOU,
- INPUT_ENABLE => INPUT_ENABLE,
- DOWNSCALE_REGISTER_1 => downscale_register_1,
- DELAY_REGISTER_1 => delay_register_1,
- WIDTH_REGISTER_1 => width_register_1,
- DOWNSCALE_REGISTER_2 => downscale_register_2,
- DELAY_REGISTER_2 => delay_register_2,
- WIDTH_REGISTER_2 => width_register_2,
- DOWNSCALE_REGISTER_3 => downscale_register_3,
- DELAY_REGISTER_3 => delay_register_3,
- WIDTH_REGISTER_3 => width_register_3,
- DOWNSCALE_REGISTER_4 => downscale_register_4,
- DELAY_REGISTER_4 => delay_register_4,
- WIDTH_REGISTER_4 => width_register_4,
- DOWNSCALE_REGISTER_5 => downscale_register_5,
- DELAY_REGISTER_5 => delay_register_5,
- WIDTH_REGISTER_5 => width_register_5,
- DOWNSCALE_REGISTER_TS => downscale_register_ts,
- DELAY_REGISTER_TS => delay_register_ts,
- WIDTH_REGISTER_TS => width_register_ts,
- DOWNSCALE_REGISTER_VS => downscale_register_vs,
- DELAY_REGISTER_VS => delay_register_vs,
- WIDTH_REGISTER_VS => width_register_vs,
- DOWNSCALE_REGISTER_CLOCK => downscale_register_clock,
- BRANCH_EN_with_MDC_TOF_WIDTH => branch_en_with_mdc_tof_width,
- WIDTH_OUTPUT => width_output,
- MUX_SELECTOR_1 => mux_selector_1,
- MUX_SELECTOR_2 => mux_selector_2,
- OR_ON_OFF => or_on_off,
- SCALER_PTI1 => scaler_pti1,
- SCALER_PTI2 => scaler_pti2,
- SCALER_PTI3 => scaler_pti3,
- SCALER_PTI4 => scaler_pti4,
- SCALER_PTI5 => scaler_pti5,
- SCALER_TS => scaler_ts,
- SCALER_VS => scaler_vs,
- SCALER_MDC_TOF_SELECT => scaler_mdc_tof_select,
- SCALER_MDC => scaler_mdc,
- SCALER_TOF => scaler_tof,
- SCALER_RESET => scaler_reset,
- PTI5_TS_ALTERNATIVE => pti5_ts_alternative,
- DELAY_REGISTER_BEAM => delay_register_beam,
- WIDTH_INHIBIT_REGISTER_BEAM => width_inhibit_register_beam,
- WIDTH_EXTERNAL_REGISTER_BEAM => width_external_register_beam,
- SCALER_DEAD => scaler_dead,
- TS_GATING_DISABLE => ts_gating_disable,
- SCALER_PTI1_ACCEPTED => scaler_pti1_accepted,
- SCALER_PTI2_ACCEPTED => scaler_pti2_accepted,
- SCALER_PTI3_ACCEPTED => scaler_pti3_accepted,
- SCALER_PTI4_ACCEPTED => scaler_pti4_accepted,
- SCALER_PTI5_ACCEPTED => scaler_pti5_accepted,
- SCALER_TS_ACCEPTED => scaler_ts_accepted,
- SCALER_VS_ACCEPTED => scaler_vs_accepted,
- SCALER_MUX1 => scaler_mux1,
- SCALER_MUX2 => scaler_mux2,
- DTU_CODE_SELECT => dtu_code_select_i,
- CAL_TRIGGER_DISABLE => cal_trigger_disable,
- COM_RUN => com_run,
- DTU_ERROR => dtu_error,
- HPV => HPV,
- HPW => HPW,
- DEBUG_REG_00 => debug_1,
- TRB_BUSY_ENABLE => trb_busy_enable
- );
----------------------I/O ecl port settings and led configuration ---------------------------------
--- tin(16 downto 9) <= (others => '0');
- EN(4 downto 1) <= "1011";
--- en(2) <= '1'; -- I/O channel 9 to 16 is an output if 0
--- tin(8 downto 1) <= (others => '0');
--- en(1) <= '1'; -- I/O channel 1 to 8 is an output if 0
- FLED_T(5 downto 1) <= not INPUT_ENABLE(5 downto 1); -- input LEDs
-------------------------------decoder for data registers -----------------------------------------
- process(CK50)
- begin
- if rising_edge(CK50) then
- if CKCSR = '1' then --read from VME bus
- case (U_AD_REG(17 downto 2)) is
- when x"0000" => delay_register_1 <= U_DAT_IN(3 downto 0);
- when x"0001" => delay_register_2 <= U_DAT_IN(3 downto 0);
- when x"0002" => delay_register_3 <= U_DAT_IN(3 downto 0);
- when x"0003" => delay_register_4 <= U_DAT_IN(3 downto 0);
- when x"0004" => delay_register_5 <= U_DAT_IN(3 downto 0);
- when x"0005" => delay_register_ts <= U_DAT_IN(3 downto 0);
- when x"0006" => delay_register_vs <= U_DAT_IN(3 downto 0);
- when x"0007" => downscale_register_1 <= U_DAT_IN(3 downto 0);
- when x"0008" => downscale_register_2 <= U_DAT_IN(3 downto 0);
- when x"0009" => downscale_register_3 <= U_DAT_IN(3 downto 0);
- when x"000a" => downscale_register_4 <= U_DAT_IN(3 downto 0);
- when x"000b" => downscale_register_5 <= U_DAT_IN(3 downto 0);
- when x"000c" => downscale_register_ts <= U_DAT_IN(3 downto 0);
- when x"000d" => downscale_register_vs <= U_DAT_IN(3 downto 0);
- when x"000e" => downscale_register_clock <= U_DAT_IN(3 downto 0);
- when x"000f" => width_register_1 <= U_DAT_IN(3 downto 0);
- when x"0010" => width_register_2 <= U_DAT_IN(3 downto 0);
- when x"0011" => width_register_3 <= U_DAT_IN(3 downto 0);
- when x"0012" => width_register_4 <= U_DAT_IN(3 downto 0);
- when x"0013" => width_register_5 <= U_DAT_IN(3 downto 0);
- when x"0014" => width_register_ts <= U_DAT_IN(3 downto 0);
- when x"0015" => width_register_vs <= U_DAT_IN(3 downto 0);
- when x"0016" => or_on_off <= U_DAT_IN(7 downto 0);
- when x"0017" => mux_selector_1 <= U_DAT_IN(3 downto 0);
- when x"0018" => mux_selector_2 <= U_DAT_IN(3 downto 0);
- -- scalers must not be written by command
- when x"0020" => input_enable <= U_DAT_IN(6 downto 0);
- when x"0021" => width_output <= U_DAT_IN(3 downto 0);
- when x"0022" => com_run <= U_DAT_IN(0);
- when x"0023" => scaler_reset <= U_DAT_IN(7 downto 0);
- when x"0024" => branch_en_with_mdc_tof_width <= U_DAT_IN(4 downto 0);
- when x"0025" => scaler_mdc_tof_select <= U_DAT_IN(7 downto 0);
- -- scalers must not be written by command
- when x"0028" => pti5_ts_alternative <= U_DAT_IN(7 downto 0);
- when x"0029" => delay_register_beam <= U_DAT_IN(7 downto 0);
- when x"002a" => width_inhibit_register_beam <= U_DAT_IN(7 downto 0);
- when x"002b" => width_external_register_beam <= U_DAT_IN(7 downto 0);
- when x"002c" => ts_gating_disable <= U_DAT_IN(6 downto 0);
- -- scalers must not be written by command
- when x"0037" => cal_trigger_disable <= U_DAT_IN(0);
- when x"0038" => dtu_error <= U_DAT_IN(0);
- when x"0039" => dtu_code_select_i <= U_DAT_IN(4 downto 0);
- when x"0041" => trb_busy_enable <= U_DAT_IN(0);
- when others => null;
- end case;
- elsif OECSR = '1' then --write to VME bus
- case (U_AD_REG(17 downto 2)) is
- when x"0000" => U_DATA_O <= x"0000000" & delay_register_1;
- when x"0001" => U_DATA_O <= x"0000000" & delay_register_2;
- when x"0002" => U_DATA_O <= x"0000000" & delay_register_3;
- when x"0003" => U_DATA_O <= x"0000000" & delay_register_4;
- when x"0004" => U_DATA_O <= x"0000000" & delay_register_5;
- when x"0005" => U_DATA_O <= x"0000000" & delay_register_ts;
- when x"0006" => U_DATA_O <= x"0000000" & delay_register_vs;
- when x"0007" => U_DATA_O <= x"0000000" & downscale_register_1;
- when x"0008" => U_DATA_O <= x"0000000" & downscale_register_2;
- when x"0009" => U_DATA_O <= x"0000000" & downscale_register_3;
- when x"000a" => U_DATA_O <= x"0000000" & downscale_register_4;
- when x"000b" => U_DATA_O <= x"0000000" & downscale_register_5;
- when x"000c" => U_DATA_O <= x"0000000" & downscale_register_ts;
- when x"000d" => U_DATA_O <= x"0000000" & downscale_register_vs;
- when x"000e" => U_DATA_O <= x"0000000" & downscale_register_clock;
- when x"000f" => U_DATA_O <= x"0000000" & width_register_1;
- when x"0010" => U_DATA_O <= x"0000000" & width_register_2;
- when x"0011" => U_DATA_O <= x"0000000" & width_register_3;
- when x"0012" => U_DATA_O <= x"0000000" & width_register_4;
- when x"0013" => U_DATA_O <= x"0000000" & width_register_5;
- when x"0014" => U_DATA_O <= x"0000000" & width_register_ts;
- when x"0015" => U_DATA_O <= x"0000000" & width_register_vs;
- when x"0016" => U_DATA_O <= x"000000" & or_on_off;
- when x"0017" => U_DATA_O <= x"0000000" & mux_selector_1;
- when x"0018" => U_DATA_O <= x"0000000" & mux_selector_2;
- when x"0019" => U_DATA_O <= scaler_pti1;
- when x"001a" => U_DATA_O <= scaler_pti2;
- when x"001b" => U_DATA_O <= scaler_pti3;
- when x"001c" => U_DATA_O <= scaler_pti4;
- when x"001d" => U_DATA_O <= scaler_pti5;
- when x"001e" => U_DATA_O <= scaler_ts;
- when x"001f" => U_DATA_O <= scaler_vs;
- when x"0020" => U_DATA_O <= x"000000" & '0' & input_enable;
- when x"0021" => U_DATA_O <= x"0000000" & width_output;
- when x"0022" => U_DATA_O <= x"0000000" & "000" & com_run;
- when x"0023" => U_DATA_O <= x"000000" & scaler_reset;
- when x"0024" => U_DATA_O <= x"000000" & "000" & branch_en_with_mdc_tof_width;
- when x"0025" => U_DATA_O <= x"000000" & scaler_mdc_tof_select;
- when x"0026" => U_DATA_O <= scaler_mdc;
- when x"0027" => U_DATA_O <= scaler_tof;
- when x"0028" => U_DATA_O <= x"000000" & pti5_ts_alternative;
- when x"0029" => U_DATA_O <= x"000000" & delay_register_beam;
- when x"002a" => U_DATA_O <= x"000000" & width_inhibit_register_beam;
- when x"002b" => U_DATA_O <= x"000000" & width_external_register_beam;
- when x"002c" => U_DATA_O <= x"000000" & '0' & ts_gating_disable; --b0
- when x"002d" => U_DATA_O <= scaler_dead;
- when x"002e" => U_DATA_O <= scaler_pti1_accepted;
- when x"002f" => U_DATA_O <= scaler_pti2_accepted;
- when x"0030" => U_DATA_O <= scaler_pti3_accepted;
- when x"0031" => U_DATA_O <= scaler_pti4_accepted;
- when x"0032" => U_DATA_O <= scaler_pti5_accepted;
- when x"0033" => U_DATA_O <= scaler_ts_accepted;
- when x"0034" => U_DATA_O <= scaler_vs_accepted;
- when x"0035" => U_DATA_O <= scaler_mux1;
- when x"0036" => U_DATA_O <= scaler_mux2;
- when x"0037" => U_DATA_O <= x"0000000" & "000" & cal_trigger_disable;
- when x"0038" => U_DATA_O <= x"0000000" & "000" & dtu_error;
- when x"0039" => U_DATA_O <= x"000000" & "000" & dtu_code_select_i;
- when x"0040" => U_DATA_O <= debug_1;
- when x"0041" => U_DATA_O <= x"0000000" & "000" & trb_busy_enable;
- when others => null;
- end case;
- end if;
- end if;
- end process;
-end rtl;
+++ /dev/null
-vhdl work "set_width_special.vhd"
-vhdl work "set_width.vhd"
-vhdl work "scaler_s.vhd"
-vhdl work "one_clock_long.vhd"
-vhdl work "new_downscale_ck.vhd"
-vhdl work "eco_delay.vhd"
-vhdl work "downscale.vhd"
-vhdl work "delay.vhd"
-vhdl work "bus_data_com5.vhd"
-vhdl work "beam_ramp.vhd"
-vhdl work "trig_box1.vhd"
-vhdl work "vmelogic.vhd"
-vhdl work "ulogic.vhd"
-vhdl work "clocking.vhd"
-vhdl work "vlogic_1.vhd"
+++ /dev/null
-# Synplicity, Inc. constraint file
-# /home/marek/vulom3/vlogic_1.sdc
-# Written on Mon Apr 28 11:36:24 2008
-# by Synplify Pro, Version 9.0.1 Scope Editor
-
-#
-# Collections
-#
-
-#
-# Clocks
-#
-
-define_clock {p:vlogic_1|CKFPL} -name {p:vlogic_1|CKFPL} -freq 110 -clockgroup Autoconstr_clkgroup_1 -rise 0 -fall 5 -route 0
-define_clock {n:beam_ramp|clk_10Hz} -name {n:beam_ramp|clk_10Hz} -period 1000 -clockgroup Autoconstr_clkgroup_3 -rise 0 -fall 0.5 -route 0
-define_clock {n:CLKDV_BUFG_INST|CLKDV_OUT} -name {n:CLKDV_BUFG_INST|CLKDV_OUT} -freq 55 -clockgroup Autoconstr_clkgroup_1 -rise 0 -fall 10 -route 0
-define_clock {n:CLKFX_BUFG_INST|CLKFX_OUT} -name {n:CLKFX_BUFG_INST|CLKFX_OUT} -freq 330 -clockgroup Autoconstr_clkgroup_1 -rise 0 -fall 1.5 -route 0
-
-#
-# Clock to Clock
-#
-
-#
-# Inputs/Outputs
-#
-
-#
-# Registers
-#
-
-#
-# Multi-Cycle Paths
-#
-
-#
-# False Paths
-#
-
-#
-# Max Delay Paths
-#
-
-#
-# Attributes
-#
-
-#
-# I/O Standards
-#
-
-#
-# Compile Points
-#
-
-#
-# Other
-#
+++ /dev/null
-NET "AD<0>" LOC = "V16" | IOSTANDARD = "LVTTL";
-NET "AD<1>" LOC = "V15" | IOSTANDARD = "LVTTL";
-NET "AD<2>" LOC = "V6" | IOSTANDARD = "LVTTL";
-NET "AD<3>" LOC = "V5" | IOSTANDARD = "LVTTL";
-NET "AD<4>" LOC = "T14" | IOSTANDARD = "LVTTL";
-NET "AD<5>" LOC = "U13" | IOSTANDARD = "LVTTL";
-NET "AD<6>" LOC = "U8" | IOSTANDARD = "LVTTL";
-NET "AD<7>" LOC = "T7" | IOSTANDARD = "LVTTL";
-NET "AD<8>" LOC = "V13" | IOSTANDARD = "LVTTL";
-NET "AD<9>" LOC = "V12" | IOSTANDARD = "LVTTL";
-NET "AD<10>" LOC = "V9" | IOSTANDARD = "LVTTL";
-NET "AD<11>" LOC = "V8" | IOSTANDARD = "LVTTL";
-NET "AD<12>" LOC = "U12" | IOSTANDARD = "LVTTL";
-NET "AD<13>" LOC = "V11" | IOSTANDARD = "LVTTL";
-NET "AD<14>" LOC = "V10" | IOSTANDARD = "LVTTL";
-NET "AD<15>" LOC = "U9" | IOSTANDARD = "LVTTL";
-NET "AD<16>" LOC = "W13" | IOSTANDARD = "LVTTL";
-NET "AD<17>" LOC = "W12" | IOSTANDARD = "LVTTL";
-NET "AD<18>" LOC = "Y5" | IOSTANDARD = "LVTTL";
-NET "AD<19>" LOC = "W5" | IOSTANDARD = "LVTTL";
-NET "AD<20>" LOC = "Y12" | IOSTANDARD = "LVTTL";
-NET "AD<21>" LOC = "Y11" | IOSTANDARD = "LVTTL";
-NET "AD<22>" LOC = "Y6" | IOSTANDARD = "LVTTL";
-NET "AD<23>" LOC = "W6" | IOSTANDARD = "LVTTL";
-NET "AD<24>" LOC = "W11" | IOSTANDARD = "LVTTL";
-NET "AD<25>" LOC = "W10" | IOSTANDARD = "LVTTL";
-NET "AD<26>" LOC = "Y7" | IOSTANDARD = "LVTTL";
-NET "AD<27>" LOC = "W7" | IOSTANDARD = "LVTTL";
-NET "AD<28>" LOC = "Y10" | IOSTANDARD = "LVTTL";
-NET "AD<29>" LOC = "Y9" | IOSTANDARD = "LVTTL";
-NET "AD<30>" LOC = "W9" | IOSTANDARD = "LVTTL";
-NET "AD<31>" LOC = "W8" | IOSTANDARD = "LVTTL";
-NET "AI<0>" LOC = "L19" | IOSTANDARD = "LVTTL";
-NET "AI<1>" LOC = "M19" | IOSTANDARD = "LVTTL";
-NET "ASI" LOC = "R17" | IOSTANDARD = "LVTTL";
-NET "BERR" LOC = "U16" | IOSTANDARD = "LVTTL";
-NET "BERRO" LOC = "V20" | IOSTANDARD = "LVTTL";
-NET "BLTACK" LOC = "U17" | IOSTANDARD = "LVTTL";
-NET "CAIV" LOC = "R19" | IOSTANDARD = "LVTTL";
-NET "CKFNL" LOC = "B7" | IOSTANDARD = "LVTTL";
-NET "CKFPL" LOC = "A7" | IOSTANDARD = "LVTTL";
-NET "CON<0>" LOC = "F18" | IOSTANDARD = "LVTTL";
-NET "CON<1>" LOC = "E18" | IOSTANDARD = "LVTTL";
-NET "CON<2>" LOC = "C18" | IOSTANDARD = "LVTTL";
-NET "CON<3>" LOC = "C19" | IOSTANDARD = "LVTTL";
-NET "CON<4>" LOC = "F16" | IOSTANDARD = "LVTTL";
-NET "CON<5>" LOC = "F17" | IOSTANDARD = "LVTTL";
-NET "CON<6>" LOC = "D19" | IOSTANDARD = "LVTTL";
-NET "CON<7>" LOC = "E19" | IOSTANDARD = "LVTTL";
-NET "CON<8>" LOC = "G16" | IOSTANDARD = "LVTTL";
-NET "CON<9>" LOC = "G17" | IOSTANDARD = "LVTTL";
-NET "CON<10>" LOC = "E20" | IOSTANDARD = "LVTTL";
-NET "CON<11>" LOC = "F20" | IOSTANDARD = "LVTTL";
-NET "CON<12>" LOC = "H16" | IOSTANDARD = "LVTTL";
-NET "CON<13>" LOC = "H17" | IOSTANDARD = "LVTTL";
-NET "CON<14>" LOC = "F19" | IOSTANDARD = "LVTTL";
-NET "CON<15>" LOC = "G19" | IOSTANDARD = "LVTTL";
-NET "DI<0>" LOC = "N17" | IOSTANDARD = "LVTTL";
-NET "DI<1>" LOC = "N18" | IOSTANDARD = "LVTTL";
-NET "DI<2>" LOC = "N19" | IOSTANDARD = "LVTTL";
-NET "DI<3>" LOC = "P16" | IOSTANDARD = "LVTTL";
-NET "DI<4>" LOC = "P17" | IOSTANDARD = "LVTTL";
-NET "DI<5>" LOC = "P19" | IOSTANDARD = "LVTTL";
-NET "DI<6>" LOC = "P20" | IOSTANDARD = "LVTTL";
-#NET "DOUT_LCD" LOC = "M16" | IOSTANDARD = "LVTTL";
-NET "DS0I" LOC = "T19" | IOSTANDARD = "LVTTL";
-NET "DS1I" LOC = "T20" | IOSTANDARD = "LVTTL";
-NET "ECL<1>" LOC = "B15" | IOSTANDARD = "LVTTL";
-NET "ECL<2>" LOC = "A15" | IOSTANDARD = "LVTTL";
-NET "ECL<3>" LOC = "A16" | IOSTANDARD = "LVTTL";
-NET "ECL<4>" LOC = "B16" | IOSTANDARD = "LVTTL";
-NET "ECL<5>" LOC = "C15" | IOSTANDARD = "LVTTL";
-NET "ECL<6>" LOC = "C16" | IOSTANDARD = "LVTTL";
-NET "ECL<7>" LOC = "B17" | IOSTANDARD = "LVTTL";
-NET "ECL<8>" LOC = "C17" | IOSTANDARD = "LVTTL";
-NET "ECL<9>" LOC = "D16" | IOSTANDARD = "LVTTL";
-NET "ECL<10>" LOC = "E16" | IOSTANDARD = "LVTTL";
-NET "ECL<11>" LOC = "A18" | IOSTANDARD = "LVTTL";
-NET "ECL<12>" LOC = "B18" | IOSTANDARD = "LVTTL";
-NET "ECL<13>" LOC = "D17" | IOSTANDARD = "LVTTL";
-NET "ECL<14>" LOC = "D18" | IOSTANDARD = "LVTTL";
-NET "ECL<15>" LOC = "B19" | IOSTANDARD = "LVTTL";
-NET "ECL<16>" LOC = "C20" | IOSTANDARD = "LVTTL";
-NET "ECO<1>" LOC = "A5" | IOSTANDARD = "LVTTL";
-NET "ECO<2>" LOC = "B5" | IOSTANDARD = "LVTTL";
-NET "ECO<3>" LOC = "C6" | IOSTANDARD = "LVTTL";
-NET "ECO<4>" LOC = "C5" | IOSTANDARD = "LVTTL";
-NET "ECO<5>" LOC = "B4" | IOSTANDARD = "LVTTL";
-NET "ECO<6>" LOC = "C4" | IOSTANDARD = "LVTTL";
-NET "ECO<7>" LOC = "D5" | IOSTANDARD = "LVTTL";
-NET "ECO<8>" LOC = "E5" | IOSTANDARD = "LVTTL";
-NET "ECO<9>" LOC = "A3" | IOSTANDARD = "LVTTL";
-NET "ECO<10>" LOC = "B3" | IOSTANDARD = "LVTTL";
-NET "ECO<11>" LOC = "D4" | IOSTANDARD = "LVTTL";
-NET "ECO<12>" LOC = "D3" | IOSTANDARD = "LVTTL";
-NET "ECO<13>" LOC = "B2" | IOSTANDARD = "LVTTL";
-NET "ECO<14>" LOC = "C1" | IOSTANDARD = "LVTTL";
-NET "ECO<15>" LOC = "F3" | IOSTANDARD = "LVTTL";
-NET "ECO<16>" LOC = "E3" | IOSTANDARD = "LVTTL";
-NET "EN<1>" LOC = "M20" | IOSTANDARD = "LVTTL";
-NET "EN<2>" LOC = "L20" | IOSTANDARD = "LVTTL";
-NET "EN<3>" LOC = "M17" | IOSTANDARD = "LVTTL";
-NET "EN<4>" LOC = "M18" | IOSTANDARD = "LVTTL";
-NET "FLED<1>" LOC = "H20" | IOSTANDARD = "LVTTL";
-NET "FLED<2>" LOC = "J15" | IOSTANDARD = "LVTTL";
-NET "FLED<3>" LOC = "J16" | IOSTANDARD = "LVTTL";
-NET "FLED<4>" LOC = "H18" | IOSTANDARD = "LVTTL";
-NET "FLED<5>" LOC = "H19" | IOSTANDARD = "LVTTL";
-NET "FLED<6>" LOC = "G20" | IOSTANDARD = "LVTTL";
-NET "HPV<0>" LOC = "H1" | IOSTANDARD = "LVTTL" | SLEW = SLOW ;
-NET "HPV<1>" LOC = "G1" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<2>" LOC = "J6" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<3>" LOC = "J5" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<4>" LOC = "H3" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<5>" LOC = "H2" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<6>" LOC = "K5" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<7>" LOC = "K4" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<8>" LOC = "K1" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<9>" LOC = "J2" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<10>" LOC = "L5" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<11>" LOC = "L4" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<12>" LOC = "K3" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<13>" LOC = "K2" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<14>" LOC = "M4" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPV<15>" LOC = "M3" | IOSTANDARD = "LVTTL"| SLEW = SLOW ;
-NET "HPW<0>" LOC = "C3" | IOSTANDARD = "LVTTL";
-NET "HPW<1>" LOC = "C2" | IOSTANDARD = "LVTTL";
-NET "HPW<2>" LOC = "F5" | IOSTANDARD = "LVTTL";
-NET "HPW<3>" LOC = "F4" | IOSTANDARD = "LVTTL";
-NET "HPW<4>" LOC = "D2" | IOSTANDARD = "LVTTL";
-NET "HPW<5>" LOC = "E2" | IOSTANDARD = "LVTTL";
-NET "HPW<6>" LOC = "G5" | IOSTANDARD = "LVTTL";
-NET "HPW<7>" LOC = "G4" | IOSTANDARD = "LVTTL";
-NET "HPW<8>" LOC = "E1" | IOSTANDARD = "LVTTL";
-NET "HPW<9>" LOC = "F1" | IOSTANDARD = "LVTTL";
-NET "HPW<10>" LOC = "H5" | IOSTANDARD = "LVTTL";
-NET "HPW<11>" LOC = "H4" | IOSTANDARD = "LVTTL";
-NET "HPW<12>" LOC = "F2" | IOSTANDARD = "LVTTL";
-NET "HPW<13>" LOC = "G2" | IOSTANDARD = "LVTTL";
-NET "HPW<14>" LOC = "J4" | IOSTANDARD = "LVTTL";
-NET "HPW<15>" LOC = "J3" | IOSTANDARD = "LVTTL";
-NET "IACKII" LOC = "T15" | IOSTANDARD = "LVTTL";
-NET "IACKOU" LOC = "U15" | IOSTANDARD = "LVTTL";
-NET "IOO<1>" LOC = "B12" | IOSTANDARD = "LVTTL";
-NET "IOO<2>" LOC = "A11" | IOSTANDARD = "LVTTL";
-NET "IOO<3>" LOC = "A10" | IOSTANDARD = "LVTTL";
-NET "IOO<4>" LOC = "B9" | IOSTANDARD = "LVTTL";
-NET "IOO<5>" LOC = "C11" | IOSTANDARD = "LVTTL";
-NET "IOO<6>" LOC = "B11" | IOSTANDARD = "LVTTL";
-NET "IOO<7>" LOC = "B10" | IOSTANDARD = "LVTTL";
-NET "IOO<8>" LOC = "C10" | IOSTANDARD = "LVTTL";
-NET "IOO<9>" LOC = "B13" | IOSTANDARD = "LVTTL";
-NET "IOO<10>" LOC = "A13" | IOSTANDARD = "LVTTL";
-NET "IOO<11>" LOC = "A8" | IOSTANDARD = "LVTTL";
-NET "IOO<12>" LOC = "B8" | IOSTANDARD = "LVTTL";
-NET "IOO<13>" LOC = "B14" | IOSTANDARD = "LVTTL";
-NET "IOO<14>" LOC = "A14" | IOSTANDARD = "LVTTL";
-NET "IOO<15>" LOC = "B6" | IOSTANDARD = "LVTTL";
-NET "IOO<16>" LOC = "A6" | IOSTANDARD = "LVTTL";
-NET "IRBLO" LOC = "V19" | IOSTANDARD = "LVTTL";
-NET "LEMIN<1>" LOC = "R4" | IOSTANDARD = "LVTTL";
-NET "LEMIN<2>" LOC = "R3" | IOSTANDARD = "LVTTL";
-NET "LEMOU<1>" LOC = "T2" | IOSTANDARD = "LVTTL";
-NET "LEMOU<2>" LOC = "T1" | IOSTANDARD = "LVTTL";
-NET "OAIV" LOC = "R20" | IOSTANDARD = "LVTTL";
-NET "PRES" LOC = "U19" | IOSTANDARD = "LVTTL";
-NET "RES<1>" LOC = "T18" | IOSTANDARD = "LVTTL";
-NET "RES<2>" LOC = "U18" | IOSTANDARD = "LVTTL";
-NET "SAD<0>" LOC = "M1" | IOSTANDARD = "LVTTL";
-NET "SAD<1>" LOC = "L1" | IOSTANDARD = "LVTTL";
-NET "SAD<2>" LOC = "M6" | IOSTANDARD = "LVTTL";
-NET "SAD<3>" LOC = "M5" | IOSTANDARD = "LVTTL";
-NET "SAD<4>" LOC = "M2" | IOSTANDARD = "LVTTL";
-NET "SAD<5>" LOC = "L2" | IOSTANDARD = "LVTTL";
-NET "SAD<6>" LOC = "N5" | IOSTANDARD = "LVTTL";
-NET "SAD<7>" LOC = "N4" | IOSTANDARD = "LVTTL";
-NET "SAD<8>" LOC = "N3" | IOSTANDARD = "LVTTL";
-NET "SAD<9>" LOC = "N2" | IOSTANDARD = "LVTTL";
-NET "SAD<10>" LOC = "P5" | IOSTANDARD = "LVTTL";
-NET "SAD<11>" LOC = "P4" | IOSTANDARD = "LVTTL";
-NET "SAD<12>" LOC = "P2" | IOSTANDARD = "LVTTL";
-NET "SAD<13>" LOC = "P1" | IOSTANDARD = "LVTTL";
-NET "SAD<14>" LOC = "R2" | IOSTANDARD = "LVTTL";
-NET "SAD<15>" LOC = "R1" | IOSTANDARD = "LVTTL";
-NET "SAD<16>" LOC = "R6" | IOSTANDARD = "LVTTL";
-NET "SAD<17>" LOC = "R5" | IOSTANDARD = "LVTTL";
-NET "SCS" LOC = "V18" | IOSTANDARD = "LVTTL";
-NET "SDA<0>" LOC = "U3" | IOSTANDARD = "LVTTL";
-NET "SDA<1>" LOC = "U2" | IOSTANDARD = "LVTTL";
-NET "SDA<2>" LOC = "T4" | IOSTANDARD = "LVTTL";
-NET "SDA<3>" LOC = "T3" | IOSTANDARD = "LVTTL";
-NET "SDA<4>" LOC = "T6" | IOSTANDARD = "LVTTL";
-NET "SDA<5>" LOC = "U6" | IOSTANDARD = "LVTTL";
-NET "SDA<6>" LOC = "V2" | IOSTANDARD = "LVTTL";
-NET "SDA<7>" LOC = "V1" | IOSTANDARD = "LVTTL";
-NET "SDA<8>" LOC = "U5" | IOSTANDARD = "LVTTL";
-NET "SDA<9>" LOC = "U4" | IOSTANDARD = "LVTTL";
-NET "SDA<10>" LOC = "W3" | IOSTANDARD = "LVTTL";
-NET "SDA<11>" LOC = "W2" | IOSTANDARD = "LVTTL";
-NET "SDA<12>" LOC = "Y4" | IOSTANDARD = "LVTTL";
-NET "SDA<13>" LOC = "W4" | IOSTANDARD = "LVTTL";
-NET "SDA<14>" LOC = "V4" | IOSTANDARD = "LVTTL";
-NET "SDA<15>" LOC = "V3" | IOSTANDARD = "LVTTL";
-NET "SOE" LOC = "V17" | IOSTANDARD = "LVTTL";
-NET "SWE" LOC = "W17" | IOSTANDARD = "LVTTL";
-NET "TIN<1>" LOC = "F15" | IOSTANDARD = "LVTTL";
-NET "TIN<2>" LOC = "E15" | IOSTANDARD = "LVTTL";
-NET "TIN<3>" LOC = "E6" | IOSTANDARD = "LVTTL";
-NET "TIN<4>" LOC = "F6" | IOSTANDARD = "LVTTL";
-NET "TIN<5>" LOC = "D15" | IOSTANDARD = "LVTTL";
-NET "TIN<6>" LOC = "E14" | IOSTANDARD = "LVTTL";
-NET "TIN<7>" LOC = "E7" | IOSTANDARD = "LVTTL";
-NET "TIN<8>" LOC = "D6" | IOSTANDARD = "LVTTL";
-NET "TIN<9>" LOC = "D13" | IOSTANDARD = "LVTTL";
-NET "TIN<10>" LOC = "C13" | IOSTANDARD = "LVTTL";
-NET "TIN<11>" LOC = "C8" | IOSTANDARD = "LVTTL";
-NET "TIN<12>" LOC = "D8" | IOSTANDARD = "LVTTL";
-NET "TIN<13>" LOC = "D12" | IOSTANDARD = "LVTTL";
-NET "TIN<14>" LOC = "C12" | IOSTANDARD = "LVTTL";
-NET "TIN<15>" LOC = "C9" | IOSTANDARD = "LVTTL";
-NET "TIN<16>" LOC = "D9" | IOSTANDARD = "LVTTL";
-NET "WRDIS" LOC = "N16" | IOSTANDARD = "LVTTL";
-NET "WRI" LOC = "R18" | IOSTANDARD = "LVTTL";
-#NET "CKFNL" TNM_NET = CKFNL;
-#TIMESPEC TS_CKFNL = PERIOD "CKFNL" 100 MHz;
-NET "CKFPL" TNM_NET = CKFPL;
-TIMESPEC TS_CKFPL = PERIOD "CKFPL" 100 MHz;
-
-
-#NET "ulg_1/trgb_1/Inst_beam_ramp/clk_10Hz" TNM_NET=ulg_1_trgb_1_Inst_beam_ramp_clk_10Hz ;
-#TIMESPEC TS_ulg_1_trgb_1_Inst_beam_ramp_clk_10Hz = PERIOD "ulg_1_trgb_1_Inst_beam_ramp_clk_10Hz" 1 MHz;# Generated by Xilinx Architecture Wizard
-# --- UCF Template Only ---
-# Cut and paste these attributes into the project's UCF file, if desired
-#INST DCM_ADV_INST CLK_FEEDBACK = 1X;
-#INST DCM_ADV_INST CLKDV_DIVIDE = 2.0;
-#INST DCM_ADV_INST CLKFX_DIVIDE = 1;
-#INST DCM_ADV_INST CLKFX_MULTIPLY = 3;
-#INST DCM_ADV_INST CLKIN_DIVIDE_BY_2 = FALSE;
-#INST DCM_ADV_INST CLKIN_PERIOD = 10.000;
-#INST DCM_ADV_INST CLKOUT_PHASE_SHIFT = NONE;
-#INST DCM_ADV_INST DCM_AUTOCALIBRATION = TRUE;
-#INST DCM_ADV_INST DCM_PERFORMANCE_MODE = MAX_SPEED;
-#INST DCM_ADV_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
-#INST DCM_ADV_INST DFS_FREQUENCY_MODE = HIGH;
-#INST DCM_ADV_INST DLL_FREQUENCY_MODE = LOW;
-#INST DCM_ADV_INST DUTY_CYCLE_CORRECTION = TRUE;
-#INST DCM_ADV_INST FACTORY_JF = F0F0;
-#INST DCM_ADV_INST PHASE_SHIFT = 0;
-#INST DCM_ADV_INST STARTUP_WAIT = FALSE;
+++ /dev/null
---------------------------------------------------------------------------------
--- Company: GSI
--- Engineer: Jan Hoffman, Davide Leoni
---
--- Create Date: 8/8/07
--- Design Name: vulom3
--- Module Name: vlogic_1 - Behavioral
--- Project Name: triggerbox
--- Target Device: XC4VLX25-10SF363
--- Tool versions:
--- Description: Top module, DCM, display, LEDs, VME signals
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity vlogic_1 is
- port (
---............................. VME Signals ............................................
- AD : inout std_logic_vector(31 downto 0); -- VME Address-Data bus
- AMI : in std_logic_vector(5 downto 0); -- VME Address modifier internal
- ASI : in std_logic; -- Address strobe
- WRI : in std_logic; -- write
- BERR : in std_logic; -- bus error for chain block transfer
- BERRO : out std_logic; -- bus error for chain block transfer
- DS0I : in std_logic; -- data strobe
- DS1I : in std_logic; -- data strobe
- IACKII : in std_logic; -- interrupt acknowledge chain
- IACKOU : out std_logic; -- interrupt acknowledge chain
- IRBLO : out std_logic; -- interrupt 4 output to VME or BLACK output
--- MON : in std_logic_vector(7 downto 0); -- VME module number connected to hex. switch VN2 .. VN1
---............................. Buffer/Register Controll Signals ............................................
- CAIV : out std_logic; -- Address buffer clock signal Int->VME
- OAIV : out std_logic; -- Address buffer OE Int->VME
---............................. Front panel Controll Signals ............................................
- ECO : inout std_logic_vector(16 downto 1); --signals to ECL output(1 is the lower connector of ECL OUT)
- EN : out std_logic_vector(4 downto 1); -- ECL enable (EN1 for ch. 1-8, EN2 for ch. 9-16)
- ECL : in std_logic_vector(16 downto 1); -- signals from ECL input (1 is at the lower connector of ECL IN)
- IOO : in std_logic_vector(16 downto 1); -- signals ioo from ECL I/O (1 is at the lower connector)
- TIN : inout std_logic_vector(16 downto 1); -- output signals to ECL I/O (1 is at the lower connector)
- LEMIN : in std_logic_vector(2 downto 1); -- signals from LEMO upper
- LEMOU : out std_logic_vector(2 downto 1); -- signals to LEMO lower
---............................. SRAM Controll Signals ............................................
- SAD : out std_logic_vector(17 downto 0); -- address
- SDA : inout std_logic_vector(15 downto 0); -- data
- SCS : out std_logic;
- SOE : out std_logic;
- SWE : out std_logic;
---............................. DISPLAY and LED Controll Signals ............................................
- DI : inout std_logic_vector(6 downto 0);
- AI : out std_logic_vector(1 downto 0); -- display address ( use 1 and 2 only, 0 and 3 can't be seen)
- WRDIS : out std_logic; -- display write
- FLED : out std_logic_vector(6 downto 1); -- Front panel LED
---............................. Euroball Readot Signals ............................................
--- PASSO : over HPV or HPW
--- RENI : over HPV or HPW
- BLTACK : in std_logic;
---............................. System Signals ............................................
- PRES : in std_logic; -- reset positive from reset IC
--- SRESI : in std_logic; -- reset from VME
- RES : in std_logic_vector(2 downto 1); -- reset from CPLD
- CKFNL : in std_logic; -- Diff 100 MHz ck neg
- CKFPL : in std_logic; -- Diff 100 MHz ck pos
- CON : inout std_logic_vector(15 downto 0); -- Connection between PROG and vlogic_1
- HPV : inout std_logic_vector(15 downto 0); -- Logic analyzer signals
- HPW : inout std_logic_vector(15 downto 0) -- Logic analyzer signals
- );
-end vlogic_1;
-architecture rtl of vlogic_1 is
-component clocking
-port(
- CLKIN_IN : IN std_logic;
- CLKDV_OUT : OUT std_logic;
- CLKFX_OUT : OUT std_logic;
- CLKIN_IBUFG_OUT : OUT std_logic;
- CLK0_OUT : OUT std_logic;
- LOCKED_OUT : OUT std_logic
- );
-end component;
-component ulogic port (
- RESET : in std_logic;
- CK50 : in std_logic;
- CK300 : in std_logic;
- CK100 : in std_logic;
- LEMOU : out std_logic_vector(2 downto 1);
- LEMIN : in std_logic_vector(2 downto 1);
- TIN : out std_logic_vector(16 downto 1);
- ECO : out std_logic_vector(16 downto 1);
- ECL : in std_logic_vector(16 downto 1);
- IOO : in std_logic_vector(16 downto 1);
- EN : out std_logic_vector(4 downto 1);
- FLED_T: out std_logic_vector(6 downto 1); -- to front panel LEDs
---............................. vme interface ....................
- U_AD_REG : in std_logic_vector(21 downto 2);
- U_DAT_IN : in std_logic_vector(31 downto 0);
- U_DATA_O : out std_logic_vector(31 downto 0);
- OECSR, CKCSR : in std_logic;
- HPV : inout std_logic_vector(15 downto 0);
- HPW : inout std_logic_vector(15 downto 0)
- );
-end component;
-
-component vmelogic port (
- ASIS :in std_logic; --
- DSR :in std_logic; --
- AD :inout std_logic_vector(31 downto 0);
- AD_REG :inout std_logic_vector(31 downto 0);
- WRI :in std_logic;
- AMI :in std_logic_vector(5 downto 0);
- CKCSR :out std_logic; -- clock data into csr
- OECSR :out std_logic; -- output data from csr to VME
- CON :inout std_logic_vector(15 downto 0);
- HPLB :out std_logic_vector(15 downto 0);
- CK50 :in std_logic
- );
-end component;
-signal reset : std_logic;
-signal count : std_logic_vector (23 downto 0);
-signal counth : std_logic_vector (27 downto 0);
-signal counf : std_logic_vector (7 downto 0);
-------------------------------------------------------------------------------------------------
-signal tri_dat : std_logic_vector (15 downto 0); -- trigger bus level data
-signal led_out : std_logic_vector (4 downto 1); -- 4 LEDs, on piggy
-signal lemo_dat : std_logic_vector (15 downto 0); -- 4 bit data from LEMO input
-signal enable, oecsr, ckcsr, asis, dsr : std_logic; -- enable internal data bus to outside of fpga
-signal mres, sta_dis : std_logic; -- internal acknowledge
-signal din, dadis : std_logic_vector (31 downto 0); -- internal data bus, CSR
---------------------------------------------------------------------------------------------------
-signal en_trcnt : std_logic;
-constant tr_cnt_dat : std_logic_vector(7 downto 0) := x"20";
-signal tr_cnt : std_logic_vector(7 downto 0);
-signal u_ad_reg : std_logic_vector(21 downto 2);
-signal u_dat_in, u_data_o, ad_reg, pdone :std_logic_vector(31 downto 0);
-signal dis_out :std_logic_vector (1 downto 0);
-signal fled_t : std_logic_vector(6 downto 1);
---
-signal hp : std_logic_vector (3 downto 0); -- states of flash machine
-signal hplb : std_logic_vector (15 downto 0); --
-signal prova, to_LED6, SOFT_RESET : std_logic;
-----------------------------
-signal rst, clk2x, clk0, ck50, ck300, ck100, locked : std_logic; -- internal acknowledge
--------------------------------------------------------------------------------
-signal clk : std_logic;
-begin
- -- CLK ----------------------------------------------------------------------
--- IBUFGDS_CLK : IBUFGDS
--- generic map (
--- IOSTANDARD => "LVDS_25_DCI")
--- port map (
--- O => clk,--CLK,
--- I => CKFPL,
--- IB => CKFNL -- Diff_n clock buffer input (connect to top-level port)
--- );
- Inst_clocking : clocking port map(
- CLKIN_IN => CKFPL,
- CLKDV_OUT => ck50, --50MHz clock
- CLKFX_OUT => ck300, --300MHz clock
- CLKIN_IBUFG_OUT => open,
- CLK0_OUT => ck100, --100MHz clock
- LOCKED_OUT => to_led6);
- ulg_1 : ulogic port map (
- RESET => reset,
- CK50 => CK50,
- CK300 => CK300,
- CK100 => CK100,
- LEMIN => LEMIN,
- LEMOU => LEMOU,
- TIN => TIN,
- EN => EN,
- ECO => ECO,
- ECL => ECL,
- IOO => IOO,
- FLED_T => fled_t,
- U_AD_REG => u_ad_reg,
- U_DAT_IN => u_dat_in,
- U_DATA_O => u_data_o,
- OECSR => oecsr,
- CKCSR => ckcsr,
- HPV => HPV,
- HPW => HPW
- );
- vme_1 : vmelogic port map (
- ASIS => asis,
- DSR => dsr,
- AD => ad,
- AD_REG => ad_reg,
- WRI => WRI,
- AMI => AMI,
- CKCSR => ckcsr,
- OECSR => oecsr,
- CON => CON,
- HPLB => hplb,
- CK50 => ck50);
----------------------------------------------------------------------------------------------
---...............................RESET signal............................................
- reset <= PRES or res(1); -- or not SRESI; -- PRES active high from power IC,
- -- SRESI active low from VME
----------------------------------PANEL LED---------------------------------------------------
- process (ck50)
- begin
- if rising_edge(ck50) then
- FLED(6) <= not to_led6; --led on if pll is working
- FLED(5 downto 1) <= fled_t(5 downto 1); --leds on if inputs enabled
- end if;
- end process;
---............................... signals to/from CPLD .......................................
- mres <= '1';
---............................... display .......................................
- process (ck50)
- begin
- if (ck50'event and ck50 = '1') then
- count <= count + 1;
- end if;
- end process;
- process (count(4))
- begin
- if rising_edge(count(4)) then
- WRDIS <= count(5);
- if count(6) = '0' then
- AI <= "01";
- DI <= CONV_STD_LOGIC_VECTOR(51, 7); -- 33h "3" ascii
- else
- AI <= "10";
- DI <= CONV_STD_LOGIC_VECTOR(51, 7); -- 32h "2" ascii
- end if;
- end if;
- end process;
---............................. VME Signals ............................................
- BERRO <= '1'; -- H means inactive
- IACKOU <= IACKII; -- interrupt acknowledge chain
--- SRESI -- system reset
- process(ck50, asi, ds0i, ds1i)
- begin
- if (ck50'event and ck50 = '1') then
- asis <= not asi;
- dsr <= not ds0i and not ds1i; -- synchronized DS input from VME
- end if;
- end process;
---------------------------- VME address buffer control signals -------------------------------
- CAIV <= '1'; -- clock for address register internal<-VME, disabled
- OAIV <= '1'; -- OE for address register internal<-VME, disabled
- u_ad_reg <= ad_reg(21 downto 2);
- u_dat_in <= ad;
------------------------ DATA MULTIPLEXER for OUTPUT to VME -------------------------------------------
- process(ck50)
- begin
- if (ck50'event and ck50 = '1') then
- if (oecsr = '1') then
- din <= u_data_o; -- data to VME over AD bus
--- elsif (dis_out(1)='1') then din <= dadis; -- display data over AD bus not necessary with vulom3 /*/*/*/*/*/
- else
- din <= (others => '0');
- end if;
- end if;
- end process;
- enable <= oecsr; --or dis_out(1); -- address and data bus output not necessary with vulom3 /*/*/*/*/*/
- AD <= din when enable = '1' else (others => 'Z');
------------------------------------ end of VME -----------------------------------------------
--------------------------------------------------------------------------------
--- * UNUSED @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ Unused Signals @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
----------------------------------------------------------------------------------
- IRBLO <= '1';
- SCS <= '1';
- SOE <= '0';
- SWE <= '0';
- SAD <= (others => '0');
--- con(15 downto 7) <= b"000000000";
-end rtl;
+++ /dev/null
-#-- Synplicity, Inc.
-#-- Version 9.0
-#-- Project file /home/marek/vulom3/vlogic_1_syn.prj
-#-- Written on Mon Apr 28 11:33:20 2008
-
-
-#add_file options
-add_file -vhdl -lib work "vlogic_1.vhd"
-add_file -vhdl -lib work "clocking.vhd"
-add_file -vhdl -lib work "ulogic.vhd"
-add_file -vhdl -lib work "vmelogic.vhd"
-add_file -vhdl -lib work "trig_box1.vhd"
-add_file -vhdl -lib work "one_clock_long.vhd"
-add_file -vhdl -lib work "delay.vhd"
-add_file -vhdl -lib work "downscale.vhd"
-add_file -vhdl -lib work "set_width.vhd"
-add_file -vhdl -lib work "set_width_special.vhd"
-add_file -vhdl -lib work "scaler.vhd"
-add_file -vhdl -lib work "scaler_s.vhd"
-add_file -vhdl -lib work "eco_delay.vhd"
-add_file -vhdl -lib work "new_downscale_ck.vhd"
-add_file -vhdl -lib work "beam_ramp.vhd"
-add_file -vhdl -lib work "bus_data_com5.vhd"
-add_file -constraint "vlogic_1.sdc"
-
-
-#implementation: "workdir"
-impl -add workdir -type fpga
-
-#device options
-set_option -technology VIRTEX4
-set_option -part XC4VLX15
-set_option -package SF363
-set_option -speed_grade -10
-
-#compilation/mapping options
-set_option -default_enum_encoding default
-set_option -resource_sharing 1
-set_option -use_fsm_explorer 1
-set_option -top_module "vlogic_1"
-
-#map options
-set_option -frequency 110.000
-set_option -run_prop_extract 0
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -pipe 1
-set_option -update_models_cp 1
-set_option -verification_mode 0
-set_option -retiming 1
-set_option -no_sequential_opt 0
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-
-
-#sequential_optimizations options
-set_option -symbolic_fsm_compiler 1
-
-#simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 0
-
-#VIF options
-set_option -write_vif 1
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "workdir/vlogic_1.edf"
-
-#
-#implementation attributes
-
-set_option -synthesis_onoff_pragma 0
-impl -active "workdir"
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
---
--- vme_1: vmelogic port map (asis=>asis, dsr=>dsr, ad=>ad, wri=>wri, ami=>ami, mon=>mon, con=>con, xxx=>xxx,
-
- entity vmelogic is
- port (asis :in std_logic; --
- dsr :in std_logic; --
- ad :inout std_logic_vector(31 downto 0);
- ad_reg :inout std_logic_vector(31 downto 0);
- wri :in std_logic;
- ami :in std_logic_vector(5 downto 0);
--- mon :in std_logic_vector(7 downto 0);
- ckcsr :out std_logic; -- clock data into csr
- oecsr :out std_logic; -- output data from csr to VME
- con :inout std_logic_vector(15 downto 0);
- hplb :out std_logic_vector(15 downto 0);
- ck50 :in std_logic
- );
-end vmelogic;
---
-architecture RTL of vmelogic is
--------------------------------------------------------------------------------------------
-------------------------------- vme signals -----------------------------------------------
-signal ckad : std_logic; -- clock for internal address register
-signal stda : std_logic; -- start data phase state machine
-signal wrs : std_logic; -- synchronized VME WRITE
-signal ack_csr : std_logic; -- internal acknowledge csr
-signal ack_hpi : std_logic; -- internal acknowledge hpi
-signal ack_fsh : std_logic; -- internal acknowledge flash
-signal ack_vr : std_logic; -- internal acknowledge vram 32
-signal aph_sta, dph_sta : std_logic_vector (3 downto 0); -- states of aph machine
-signal enable : std_logic; -- enable internal data bus to outside of fpga
---signal vafsh : std_logic_vector (3 downto 0); -- vme address phase outputs for flash
---signal va64 : std_logic_vector (3 downto 0); -- vme data phase for VRAM64 (dual port ram)
-signal vdcsr : std_logic_vector (3 downto 0); -- vme data phase outputs for external vme buffer register
-signal amr : std_logic_vector (5 downto 0); -- internal address modifier register for VME address
-signal int_res : std_logic_vector (23 downto 22); -- internal address register for VME address
-signal sel_rnd : std_logic; -- FLASH, CSR, HPI, DPRAM random access
-signal sel_bt32 : std_logic; -- DPRAM BT 32 access
---signal sel_bt64 : std_logic; -- DPRAM BT 64 access
-signal selcsr : std_logic; -- CSR selected
-signal selflsh : std_logic; -- FLASH selected
-signal ad_co : std_logic_vector (1 downto 0); -- vme address phase outputs for: stda = start data phase...
-signal csr_o : std_logic_vector (1 downto 0); -- vme data phase outputs for csr
-signal pr_ou : std_logic_vector (1 downto 0); -- priority encoder outputs
-signal tr_ou : std_logic_vector (15 downto 0); -- priority encoder outputs
-signal vram : std_logic; -- vram1 or vram2 32/64 bit selected
-signal vulom_sel : std_logic;
-signal ckcsro : std_logic_vector (1 downto 0); -- internal CSR
-signal oecsro : std_logic_vector (1 downto 0); -- internal CSR
-signal din,csrr0,csrr1 : std_logic_vector (31 downto 0); -- internal data bus, CSR
------------------- VME address modifier ------------------------------
-constant am_f :std_logic_vector(5 downto 0) := b"001111";--AM543210=001111 ext. Extended supervisory block transfer
-constant am_e :std_logic_vector(5 downto 0) := b"001110";--AM543210=001110 ext. supervisory program access
-constant am_d :std_logic_vector(5 downto 0) := b"001101";--AM543210=001101 ext. Extended supervisory data access
-constant am_a :std_logic_vector(5 downto 0) := b"001010";--AM543210=001010 ext. Extended non-privileged program access
-constant am_b :std_logic_vector(5 downto 0) := b"001011";--AM543210=001011 ext. Extended non-privileged block transfer
-constant am_9 :std_logic_vector(5 downto 0) := b"001001";--AM543210=001001 ext. Extended non-privileged data access
-constant am_8 :std_logic_vector(5 downto 0) := b"001000";--AM543210=001000 ext. Extended non-privileged 64-bit block transfer
-constant am_1b :std_logic_vector(5 downto 0) := b"011011";--AM543210=011011 ext. Eurogram Readout
-constant am_29 :std_logic_vector(5 downto 0) := b"101001";--AM543210=101001 ext. Direct Configuration of FPGA
------------------- VME addresses --------------------------------------
-constant csr_ad :std_logic_vector(3 downto 2) := b"00";----vmeaddr=XX00 0000 - XX00 000C
---constant sram_ad :std_logic_vector(3 downto 2) := x"01";----vmeaddr=XX40 0000 - XX40 FFFC
--- ............... vme address phase state machine, states declaration .........................
-type vme_adr_typ is (va00,va01,va02,va03,va04,va05,va0b); -- va06,va07,va08,va09,va0a,
-signal vme_adr, vme_anx : vme_adr_typ;
--- ............... vme data phase state machine for CSR .........................
-signal st_csr_drd : std_logic; -- start state machine for CSR read
-signal st_csr_dwr : std_logic; -- start state machine for CSR write
-type vmdacs_typ is (vc00,vc01,vc02,vc03,vc04,vc05,vc06,vc07,vc08,vc09,vc0a,vc0b,vc0c,vc0d,vc0e);
-signal vmdacs, vmdacs_nx : vmdacs_typ;
-
-------------------------------------------------------------------------------------------
-begin ---- BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN
-------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
---..........................................................................................
---...................... VME address phase state machine .......................
- process (vme_adr,asis) -- states are - va00,va01,va02,va03,va04,va05,va06,va07,va08
- begin -- ad_co[]=stda,ckad
- case vme_adr is
- when va00 => ad_co <= b"00"; aph_sta <= x"0";
- if asis ='1' then vme_anx <= va01;
- else vme_anx <= va00;
- end if;
- when va01 => ad_co <= b"00"; aph_sta <= x"1";
- if asis ='1' then vme_anx <= va02;
- else vme_anx <= va00;
- end if;
- when va02 => vme_anx <= va03; ad_co <= b"00"; aph_sta <= x"2";
- when va03 => vme_anx <= va04; ad_co <= b"00"; aph_sta <= x"3";
- when va04 => vme_anx <= va05; ad_co <= b"01"; aph_sta <= x"4";
- when va05 => vme_anx <= va0b; ad_co <= b"11"; aph_sta <= x"5";
- when va0b => ad_co <= b"10"; aph_sta <= x"6";
- if asis ='1' then vme_anx <= va0b;
- else vme_anx <= va00;
- end if;
- end case;
- end process;
--- ............................ clock for address phase state machine ................................
- process(ck50) begin -- 50 MHz clock
- if (ck50'EVENT AND ck50 = '1') then
- vme_adr <= vme_anx;
- end if;
- end process ;
--- .............................. synchronize outputs ..................................
- process(ck50) begin
- if (ck50'EVENT AND ck50 = '1') then
- stda <= ad_co(1); -- start data phase (low=address phase - high =data phase)
- ckad <= ad_co(0); -- ckad = clock for internal address register
- end if;
- end process ;
-----................... end of VME address phase state machine ...................
---
----................... save VME address into FPGA internal address register ...................
- process(ck50, ckad)
- begin
- if (ck50'EVENT AND ck50 = '1') then
- if ckad = '1' then
- ad_reg <= ad; wrs <= wri; amr <= ami;
- end if;
- end if;
- end process;
- int_res <= ad_reg(23 downto 22); -- internal resources
---.................. select SAM4 module = compare address register with hex switch ...............
-
--- process(ck50)--, ad, mon)
--- begin
--- if (ck50'EVENT AND ck50 = '1') then
--- if (ad_reg(31 downto 24) = mon) then -- VN2 31...28, VN1 27...24 --*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/
--- vulom_sel <= '1';
--- else vulom_sel <= '0';
--- end if;
--- end if;
--- end process;
---.................. compare address register and address modifier .............................
- process(ck50, ad_reg, amr)
- begin
- if (ck50'event and ck50 ='1') then
- if ((ad_reg(1 downto 0) = b"00") and (con(7) = '1')) then --(amr = am_9 or amr = am_d) and vulom_sel = '1' then
- sel_rnd <= '1'; -- CSR random access
- else sel_rnd <= '0';
- end if;
- if ((ad_reg(1 downto 0) = b"00") and (con(8) = '1')) then --(amr = am_b) and vulom_sel = '1' then
- sel_bt32 <= '1'; -- BT 32 bit access
- else sel_bt32 <= '0';
- end if;
- end if;
- end process;
--- * CSR0 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ DATA PHASE for CSR @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
---................................ comparator for CSR .......................................
- process(ck50, dsr, stda, wrs, int_res, sel_rnd)
- begin
- if (ck50'event and ck50 ='1') then
- if (dsr='1' and stda='1' and wrs='1' and int_res=csr_ad and sel_rnd='1') then st_csr_drd <= '1'; -- CSR sta-ma
- else st_csr_drd <= '0';
- end if;
- if (dsr='1' and stda='1' and wrs='0' and int_res=csr_ad and sel_rnd='1') then st_csr_dwr <= '1'; -- CSR sta-ma
- else st_csr_dwr <= '0';
- end if;
- if (int_res=csr_ad and sel_rnd='1') then selcsr <= '1'; -- CSR selected
- else selcsr <= '0';
- end if;
- end if;
- end process;
--- csr_o[]=ckcsr,oecsr, vdcsr[]=odvi,cdvi,odiv,cdiv
- process (vmdacs, dsr, st_csr_dwr, st_csr_drd) -- states are - vc00,vc01,vc02,vc03,vc04,vc05,vc06,vc07,vc08
- begin
--- csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1';
- case vmdacs is
- when vc00 => csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; dph_sta <= x"0";
- if st_csr_drd ='1' then vmdacs_nx <= vc01;
- elsif st_csr_dwr ='1' then vmdacs_nx <= vc08;
- else
- vmdacs_nx <= vc00;
- end if;
---
---............................. read csr ................................
- when vc01 => vmdacs_nx <= vc02; csr_o <= b"01"; vdcsr <= b"1010"; ack_csr <='1'; dph_sta <= x"1";
- when vc02 => vmdacs_nx <= vc03; csr_o <= b"01"; vdcsr <= b"1010"; ack_csr <='1'; dph_sta <= x"2";
- when vc03 => vmdacs_nx <= vc04; csr_o <= b"01"; vdcsr <= b"1010"; ack_csr <='1'; dph_sta <= x"3";
- when vc04 => vmdacs_nx <= vc05; csr_o <= b"01"; vdcsr <= b"1001"; ack_csr <='1'; dph_sta <= x"4";
- when vc05 => vmdacs_nx <= vc06; csr_o <= b"01"; vdcsr <= b"1001"; ack_csr <='1'; dph_sta <= x"5";
- when vc06 => csr_o <= b"01"; vdcsr <= b"1001"; ack_csr <='0'; dph_sta <= x"6";
- if dsr ='1' then vmdacs_nx <= vc06;
- else vmdacs_nx <= vc07;
- end if;
- when vc07 => vmdacs_nx <= vc00; csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; dph_sta <= x"7";
---............................. write csr ................................
- when vc08 => vmdacs_nx <= vc09; csr_o <= b"10"; vdcsr <= b"0011"; ack_csr <='1'; dph_sta <= x"8";
- when vc09 => vmdacs_nx <= vc0a; csr_o <= b"10"; vdcsr <= b"0011"; ack_csr <='1'; dph_sta <= x"9";
- when vc0a => vmdacs_nx <= vc0b; csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='1'; dph_sta <= x"a";
- when vc0b => vmdacs_nx <= vc0c; csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='1'; dph_sta <= x"b";
- when vc0c => vmdacs_nx <= vc0d; csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='1'; dph_sta <= x"c";
- when vc0d => csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='0'; dph_sta <= x"d";
- if dsr ='1' then vmdacs_nx <= vc0d;
- else vmdacs_nx <= vc0e;
- end if;
- when vc0e => vmdacs_nx <= vc00; csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; dph_sta <= x"e";
- end case;
- end process;
--- ............................ clock for vmedacs state machine ................................
- process(ck50) begin
- if (ck50'EVENT AND ck50 = '1') then
- vmdacs <= vmdacs_nx;
- end if;
- end process ;
--- .............................. synchronize outputs ..................................
- process(ck50) begin
- if (ck50'EVENT AND ck50 = '1') then
--- csr_o = ckcsr,oecsr,
- ckcsr <= csr_o(1); -- clock data into csr
- oecsr <= csr_o(0); -- output data from csr to VME
- end if;
- end process ;
---------------------------- VME control signals -------------------------------
--- vdbuf = odvi,cdvi,odiv,cdiv
- process(ck50,vdcsr,ack_csr,ack_hpi)
- begin
- if (ck50'event and ck50 ='1') then
- if (selcsr='1') then
- con(4) <= vdcsr(3); -- odvi = OE for data register VME->internal
- con(3) <= vdcsr(2); -- cdvi = clock for data register VME->internal
- con(2) <= vdcsr(1); -- odiv = OE for data register internal->VME
- con(1) <= vdcsr(0); -- cdiv = clock for data register internal->VME
- con(0) <= ack_csr; -- acknowledge from csr
- else
- con(4) <= '1'; con(3) <= '1'; con(2) <= '1'; con(1) <= '1'; con(0) <= '1'; -- inactive
- end if;
- end if;
- end process;
-----------------------------------------------------------------------------------
--- hplb <= (others =>'0');
- hplb(0) <= asis;
- hplb(1) <= ckad;
- hplb(2) <= st_csr_drd;
- hplb(3) <= st_csr_dwr;
- hplb(6 downto 4) <= aph_sta(2 downto 0);
- hplb(7) <= ack_csr;
- hplb(11 downto 8) <= vdcsr;
- hplb(15 downto 12) <= dph_sta;
-
-end RTL;
\ No newline at end of file
+++ /dev/null
-#!/usr/bin/perl
-###########################################
-# Script file to run the flow
-#
-###########################################
-#
-# Command line for synplify_pro
-#
-
-
-use FileHandle;
-
-
-use Data::Dumper;
-
-use warnings;
-use strict;
-
-
-$ENV{LM_LICENSE_FILE}="1710\@cronos.e12.physik.tu-muenchen.de";
-
-my $synplify_path = '/opt/Synplicity/syn_96L2/synplify_linux/bin/';
-
-$ENV{'SYNPLIFY'}="/opt/Synplicity/syn_96L2/synplify_linux/";
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-
-
-my $base = "/opt/lattice/ispLEVER7.2/isptools";
-
-my $FAMILYNAME="LatticeSCM";
-my $PLD_DEVICE="LFSCM3GA25EP1";
-my $PACKAGE="FFBGA1020";
-
-my $TOPNAME="hub";
-
-my $t=time;
-
-my $fh = new FileHandle(">version.vhd");
-
-die "could not open file" if (! defined $fh);
-
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := $t;
-
-end package version;
-
-
-EOF
-
-$fh->close;
-
-
-#set -e
-#set -o errexit
-
-system("env| grep LM_");
-#$c="/opt/Synplicity/fpga_901/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
-#$c="/opt/Synplicity/syn_96L2/synplify_linux/bin/synpwrap_pro.sh -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
-#execute($c);
-#$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
-#$c=("( netcat -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)& /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj");
-#$r=execute($c, "do_not_exit" );
-
-my $c="$synplify_path/synpwrap -Pro -prj $TOPNAME"."_syn.prj";
-my $r=execute($c, "do_not_exit" );
-
-
-chdir "workdir";
-$fh = new FileHandle("<$TOPNAME.srr");
-my @a = <$fh>;
-$fh -> close;
-
-#if ($r) {
-#$c="cat $TOPNAME.srr";
-#system($c);
-#exit 129;
-#}
-
-foreach (@a)
-{
- if( /\@E:/ || /\@E\|/ )
- {
- $c="cat $TOPNAME.srr";
- system($c);
- print "bdabdhsadbhjasdhasldhbas";
- exit 129;
- }
-}
-#if (0){
-
-#$c=("/opt/lattice/isplever7.0/isptools/ispcpld/bin/checkini -err=automake.err /opt/lattice/isplever7.0/isptools/ispcpld/config/or5s00.ini");
-
-
-#$c=("/opt/lattice/isplever7.0/isptools/ispcpld/bin/edfin -i hub.edf -jhd hub.jhd -log hub.log -dev orca -lbp \"/opt/lattice/isplever7.0/isptools/ispfpga/data\"");
-
-#$c=("/opt/lattice/isplever7.0//ispfpga/bin/lin/lci2prf -oc hub.lct -log hub.log ../hub.lpf");
-
-#$c=("export FOUNDRY=\"/opt/lattice/isplever7.0//ispfpga\"");
-
-#$c=("export LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH:/opt/lattice/isplever7.0//ispfpga/bin/lin\"");
-
-$c= qq|$base/ispfpga/bin/lin/edif2ngd -l "$FAMILYNAME" -d "$PLD_DEVICE" "$TOPNAME.edf" "$TOPNAME.ngo"|;
-execute($c);
-
-$c=qq|$base/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
-execute($c);
-
-$c=qq|$base/ispfpga/bin/lin/ngdbuild -a "$FAMILYNAME" -d "$PLD_DEVICE" -p "$base/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-$c=qq|$base/ispfpga/bin/lin/map -a "$FAMILYNAME" -p "$PLD_DEVICE" -t "$PACKAGE" -s 5 "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-system("rm $TOPNAME.ncd");
-#execute($c);
-
-$c=qq|$base/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "$TOPNAME| . "_mpar.rpt" . qq|" -log "$TOPNAME| . "_mpar.log" . qq|" -p "$TOPNAME.p2t" -f "$TOPNAME.p3t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-execute($c);
-
-
-# TWR Timing Report
-#$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|;
-$c=qq|$base/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-$c=qq|$base/ispfpga/bin/lin/trce -c -v 5 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-
-
-$c=("$base/ispfpga/bin/lin/bitgen -w \"hub.ncd\" -f \"hub.t2b\" \"hub.prf\"");
-execute($c);
-#$c=(". ~/bin/ispvm17");
-#execute($c);
-
-$c=q| perl -ne '$in=1 if(/Report Summary/); print if($in==1); $in=0 if(/All preferences were met./)' | . "$TOPNAME.twr.setup";
-execute($c);
-
-chdir "..";
-
-$c=("cat version.vhd | grep VERSION_NUMBER_TIME");
-execute($c);
-
-$c=q!cat version.vhd | perl -ne '($r)=grep(/VERSION_NUMBER_TIME/, $_); if($r) {($n)=$r=~/(\d+);/; printf("%x\n",$n);} '!;
-execute($c);
-
-
-#$c=(". ~/bin/ispvm17");
-
-#$c=("ispvm -infile hub_1.xcf -outfiletype -stp");
-#execute($c);
-
-#$c=("perl -i -ne 'print unless(/!/)' hub_1.svf");
-#execute($c);
-#$c=("impact -batch impact_batch_hub.txt");
-#execute($c);
-#$c=("scp hub_chain.stapl hadaq\@hadeb05:/var/diskless/etrax_fs/");
-#execute($c);
-
-#}
-#$c=("impact -batch impact_batch_hub.txt");
-
-sub execute {
- my ($c, $op) = @_;
- #print "option: $op \n";
-
- print "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
- }
-
- return $r;
-
-}
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_arith.all;
-use IEEE.STD_LOGIC_unsigned.all;
-
-
-entity f_divider is
-
- generic(
- cnt : integer := 4000 -- Der Teiler teilt durch "cnt" , wenn Test = 0 ist. --
- );
-
- port (
- clk : in std_logic;
- ena_cnt : in std_logic;
- f_div : out std_logic
- );
-
-end f_divider;
-
-
-
-architecture arch_f_divider of f_divider is
-
- function How_many_Bits (int : integer) return integer is
- variable i, tmp : integer;
- begin
- tmp := int;
- i := 0;
- while tmp > 0 loop
- tmp := tmp / 2;
- i := i + 1;
- end loop;
- return i;
- end How_many_bits;
-
-
- --+
- --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können? |
- --+
- constant c_counter_width : integer := How_many_Bits(cnt - 2);
-
- --+ ---------------------------------------------------------------------------------------------+
- --| Des Zähler "s_counter" muss ein Bit breiter definiert werden, als zur Abarbeitung des "cnt" |
- --| nötig wäre. Dieses Bit wird beim Zählerunterlauf '1'. Der Zählerablauf wird dadurch ohne |
- --| Komparator erkannt, er steht als getaktetes physikalisches Signal zur Verfügung. |
- --+ ---------------------------------------------------------------------------------------------+
- signal s_counter : std_logic_vector(c_counter_width downto 0) := conv_std_logic_vector(0, c_counter_width+1);
-
- --+ ---------------------------------------------------------------------------------------------+
- --| Teiler muss mit einen um -2 geringeren Wert geladen werden. Da das Neuladen erst durch dem |
- --| Unterlauf Zählers erfolgt. D.h. die Null und minus Eins werden mitgezählt. |
- --+ ---------------------------------------------------------------------------------------------+
- constant c_ld_value : integer := cnt - 2;
-
-begin
- p_f_divider : process (clk)
- begin
- if clk'event and clk = '1' then
- if s_counter(s_counter'high) = '1' then -- Bei underflow wird neu geladen --
- s_counter <= conv_std_logic_vector(c_ld_value, s_counter'length);
- elsif ena_cnt = '1' then
- if s_counter(s_counter'high) = '0' then -- Kein underflow erreicht weiter --
- s_counter <= s_counter - 1; -- subtrahieren. --
- end if;
- end if;
- end if;
- end process p_f_divider;
-
- f_div <= s_counter(s_counter'high);
-
-end arch_f_divider;
-
-
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-
---library synplify;
---use synplify.attributes.all;
-
-
-entity edge_to_pulse is
-
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
-
-end edge_to_pulse;
-
-architecture arch_edge_to_pulse of edge_to_pulse is
- signal signal_sync : std_logic;
- signal old_sync : std_logic;
- type state is (idle, high, wait_for_low); -- state
- signal current_state, next_state : state;
-
-begin -- arch_edge_to_pulse
-
- fsm : process (clock)
- begin -- process fsm
- if rising_edge(clock) then -- rising clock edge
- if en_clk = '1' then
- current_state <= next_state;
- signal_sync <= signal_in;
- end if;
- end if;
- end process fsm;
-
-
- fsm_comb : process (current_state, signal_sync)
- begin -- process fsm_comb
- pulse <= '0';
- case current_state is
- when idle =>
- pulse <= '0';
- if signal_sync = '1' then
- next_state <= high;
- else
- next_state <= idle;
- end if;
- when high =>
- pulse <= '1';
- next_state <= wait_for_low;
--- when wait_for_low_1 =>
--- pulse <= '1';
--- next_state <= wait_for_low;
- when wait_for_low =>
- pulse <= '0';
- if signal_sync = '0' then
- next_state <= idle;
- else
- next_state <= wait_for_low;
- end if;
- when others =>
- next_state <= idle;
- end case;
- end process fsm_comb;
-
-
-end arch_edge_to_pulse;
-
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package support is
-
- component f_divider
- generic (
- cnt : integer);
- port (
- clk : in std_logic;
- ena_cnt : in std_logic;
- f_div : out std_logic);
- end component;
-
- component edge_to_pulse
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
- end component;
-
-
-end support;
-
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library ieee;
-library work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.all;
-use work.trb_net_std.all;
-use work.trb_net16_hub_func.all;
-
-entity flexi_PCS_channel_synch is
- generic (
- SYSTEM : positive);
- port (
- RESET : in std_logic;
- SYSTEM_CLK : in std_logic;
- --to and from media
- TX_CLK : in std_logic;
- RX_CLK : in std_logic;
- RXD : in std_logic_vector(15 downto 0);
- RX_K : in std_logic_vector(1 downto 0);
- RX_RST : out std_logic;
- CV : in std_logic_vector(1 downto 0);
- TXD : out std_logic_vector(15 downto 0);
- TX_K : out std_logic_vector(1 downto 0);
- MEDIA_STATUS : in std_logic_vector(15 downto 0);
- MEDIA_CONTROL : out std_logic_vector(15 downto 0);
- --to and from trbnet
- --to media
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector(15 downto 0);
- MED_READ_OUT : out std_logic;
- --from media
- MED_DATA_OUT : out std_logic_vector(15 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
- --trbnet control and status
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_STAT_OP : out std_logic_vector(15 downto 0);
- MED_CTRL_OP : in std_logic_vector(15 downto 0); --debug
- LINK_DEBUG : out std_logic_vector(31 downto 0)
- );
-end flexi_PCS_channel_synch;
-
-architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is
-
- component flexi_PCS_fifo_EBR
- port (
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(17 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostEmpty : out std_logic;
- AlmostFull : out std_logic
- );
- end component;
-
- component ecp2m_link_fifo
- port (
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(17 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostEmpty : out std_logic;
- AlmostFull : out std_logic
- );
- end component;
- --keep fifos as small as possible, remember but low prioriority
- --disable transmition during synch
- component up_down_counter
- generic (
- NUMBER_OF_BITS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic;
- DOWN_IN : in std_logic);
- end component;
-
- component edge_to_pulse
- port (
- CLOCK : in std_logic;
- EN_CLK : in std_logic;
- SIGNAL_IN : in std_logic;
- PULSE : out std_logic);
- end component;
-
- component cross_clk
- port (
- WrAddress : in std_logic_vector(2 downto 0);
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- WE : in std_logic;
- WrClockEn : in std_logic;
- RdAddress : in std_logic_vector(2 downto 0);
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(31 downto 0));
- end component;
-
- component trbv2_cross_clk
- port (
- addra : in std_logic_vector(2 downto 0);
- addrb : in std_logic_vector(2 downto 0);
- clka : in std_logic;
- clkb : in std_logic;
- dina : in std_logic_vector(31 downto 0);
- dinb : in std_logic_vector(31 downto 0);
- douta : out std_logic_vector(31 downto 0);
- doutb : out std_logic_vector(31 downto 0);
- wea : in std_logic;
- web : in std_logic);
- end component;
-
- component trbv2_link_fifo
- port (
- din : IN std_logic_VECTOR(17 downto 0);
- rd_clk : IN std_logic;
- rd_en : IN std_logic;
- rst : IN std_logic;
- wr_clk : IN std_logic;
- wr_en : IN std_logic;
- almost_empty : OUT std_logic;
- almost_full : OUT std_logic;
- dout : OUT std_logic_VECTOR(17 downto 0);
- empty : OUT std_logic;
- full : OUT std_logic);
- end component;
-
- type SYNC_MACHINE is (FIRST_DUMMY_STATE, START_COUNTER, RESYNC0, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, WAIT_3, NORMAL_OPERATION_1, NORMAL_OPERATION_2);
- signal SYNC_CURRENT, SYNC_NEXT : SYNC_MACHINE;
--- attribute syn_enum_encoding : string;
--- attribute syn_enum_encoding of SYNC_MACHINE : type is "safe";
--- attribute syn_enum_encoding of SYNC_MACHINE : type is "sequential";
-
- signal fsm_debug_register : std_logic_vector(3 downto 0);
- signal resync_counter_up :std_logic;
- signal resync_counter_clr :std_logic;
- signal resync_counter : std_logic_vector(31 downto 0);
- signal cv_i : std_logic_vector(1 downto 0);
- signal cv_or : std_logic;
- signal cv_counter : std_logic_vector(15 downto 0);
- signal rx_rst_i : std_logic;
- signal rxd_synch_i : std_logic_vector(15 downto 0);
- signal rxd_synch_synch_i : std_logic_vector(15 downto 0);
- signal rx_k_synch_i : std_logic_vector(1 downto 0);
- signal rx_k_synch_synch_i : std_logic_vector(1 downto 0);
- signal fifo_data_in : std_logic_vector(17 downto 0);
- signal fifo_data_out : std_logic_vector(17 downto 0);
- signal fifo_wr_en : std_logic;
- signal fifo_rd_en : std_logic;
- signal fifo_rst : std_logic;
- signal fifo_full : std_logic;
- signal fifo_almost_full : std_logic;
- signal fifo_empty : std_logic;
- signal fifo_almost_empty : std_logic;
- signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal start_counter_1 : std_logic_vector(31 downto 0);
- signal start_counter_2 : std_logic_vector(31 downto 0);
- signal fifo_rd_pulse : std_logic;
- signal fifo_rd_cnt : std_logic_vector(15 downto 0);
- signal fifo_wr_cnt : std_logic_vector(15 downto 0);
- signal not_fifo_empty : std_logic;
-
- -----------------------------------------------------------------------------
- -- fifo to optical link
- -----------------------------------------------------------------------------
- signal data_valid_out_i : std_logic;
- signal fifo_opt_not_empty : std_logic;
- signal fifo_opt_empty : std_logic;
- signal fifo_opt_empty_synch : std_logic;
- signal data_opt_in : std_logic_vector(17 downto 0);
- signal txd_fifo_out : std_logic_vector(17 downto 0);
- signal fifo_opt_full : std_logic;
- signal fifo_opt_almost_empty : std_logic;
- signal fifo_opt_almost_full : std_logic;
- signal not_clk : std_logic;
- signal txd_synch_i : std_logic_vector(15 downto 0);
- signal tx_k_i : std_logic;
- signal fifo_opt_empty_synch_synch : std_logic;
- signal fifo_rd_en_hub : std_logic;
--- constant SYSTEM : Integer := 1;
- signal wait_for_write_up : std_logic;
- signal wait_for_write_counter : std_logic_vector(28 downto 0);
- signal link_reset_counter : std_logic_vector(2 downto 0);
- signal link_reset_counter_clr : std_logic;
- signal link_reset_counter_up : std_logic;
- signal link_reset_out : std_logic;
- signal med_error_out_i : std_logic_vector(2 downto 0);
- signal fifo_rst_fsm : std_logic;
- signal fsm_debug_register_fsm: std_logic_vector(3 downto 0);
- signal rx_rst_fsm : std_logic;
- signal resync_counter_up_fsm : std_logic;
- signal resync_counter_clr_fsm : std_logic;
- signal wait_for_write_up_fsm : std_logic;
- signal MED_READ_OUT_fsm : std_logic;
- signal diod_counter : std_logic_vector(28 downto 0);
- signal cv_counter_reset : std_logic;
- signal rx_comma : std_logic_vector(1 downto 0);
- signal rx_comma_synch : std_logic_vector(1 downto 0);
-
- --crossing clk memory
- signal cross_wraddress_i : std_logic_vector(2 downto 0);
- signal cross_data_i : std_logic_vector(31 downto 0);
- signal cross_rdaddress_i : std_logic_vector(2 downto 0);
- signal cross_q_i : std_logic_vector(31 downto 0);
- signal rx_comma_synch_err : std_logic;
- signal lost_connection_count : std_logic_vector(15 downto 0);
-
-begin
-
- --reset from link
- RESET_FROM_LINK: process (RX_CLK, RESET)
- begin
- if rising_edge(RX_CLK) then
- if RESET = '1' then
- link_reset_counter_up <= '0';
- elsif rxd_synch_i = x"ffff" and link_reset_counter < 5 then
- link_reset_counter_up <= '1';
- else
- link_reset_counter_up <= '0';
- end if;
- end if;
- end process RESET_FROM_LINK;
-
- SET_RESET: process (SYSTEM_CLK, RESET)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- link_reset_out <= '0';
- elsif link_reset_counter = 5 then
- link_reset_out <= '1';
- else
- link_reset_out <= '0';
- end if;
- end if;
- end process SET_RESET;
-
- RESET_LINK_ERROR_COUNTER: process (RX_CLK, RESET)
- begin
- if rising_edge(RX_CLK) then
- if RESET = '1' then
- link_reset_counter_clr <= '0';
- elsif link_reset_counter = 3 then
- link_reset_counter_clr <= link_reset_out or RESET;
- elsif link_reset_counter < 3 and rxd_synch_i /= x"ffff" then
- link_reset_counter_clr <= '1';
- else
- link_reset_counter_clr <= '0';
- end if;
- end if;
- end process RESET_LINK_ERROR_COUNTER;
-
- LINK_RESET_COUNTER_INST: up_down_counter
- generic map (
- NUMBER_OF_BITS => 3)
- port map (
- CLK => RX_CLK,
- RESET => link_reset_counter_clr,
- COUNT_OUT => link_reset_counter,
- UP_IN => link_reset_counter_up,
- DOWN_IN => '0');
-
- -- STAT_OP(15) <= link_reset_out;
- --link
-
- MED_STAT_OP(2 downto 0) <= med_error_out_i;
- SEND_ERROR: process (SYSTEM_CLK, RESET,SYNC_CURRENT)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- med_error_out_i <= ERROR_NC;
- elsif SYNC_CURRENT = NORMAL_OPERATION_1 or SYNC_CURRENT = NORMAL_OPERATION_2 then
- med_error_out_i <= ERROR_OK;
- elsif SYNC_CURRENT = WAIT_1 or SYNC_CURRENT = WAIT_2 then
- med_error_out_i <= ERROR_WAIT;
- else
- med_error_out_i <= ERROR_NC;
- end if;
- end if;
- end process SEND_ERROR;
- MED_STAT_OP(15 downto 10) <= (others => '0');
- MED_STAT_OP(8 downto 3) <= (others => '0');
-
- PACKET_NUM: process (SYSTEM_CLK, RESET,fifo_rd_en)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- packet_number <= "011";
- elsif fifo_rd_en = '1' then
- if packet_number = c_max_word_number then
- packet_number <= "000";
- else
- packet_number <= packet_number + 1;
- end if;
- end if;
- end if;
- end process PACKET_NUM;
- MED_PACKET_NUM_OUT <= packet_number;
-
- LINK_STATUS : process (SYSTEM_CLK,RESET)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- RX_RST <= '0';
- LINK_DEBUG(15 downto 0) <= (others => '0');
- else
- RX_RST <= rx_rst_i;
- LINK_DEBUG(3 downto 0) <= fsm_debug_register_fsm;
- LINK_DEBUG(7 downto 4) <= fifo_empty & fifo_full & fifo_opt_empty & fifo_opt_full;--fifo_almost_full &
- --'0';
- LINK_DEBUG(15 downto 8) <= fifo_wr_cnt(3 downto 0) & fifo_rd_cnt(3 downto 0);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); -- LINK_DEBUG(11 downto 8) <= fifo_wr_cnt(4 downto 1);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0);
- LINK_DEBUG(31 downto 16) <= fifo_data_out(3 downto 0) & lost_connection_count(7 downto 0) & '0' & rx_comma_synch & MEDIA_STATUS(0) ;
- end if;
- end if;
- end process LINK_STATUS;
- -- LINK_DEBUG(31 downto 16) <= fifo_data_in(15 downto 0);
-
- -----------------------------------------------------------------------------
- -- data from hub to link
- -----------------------------------------------------------------------------
-
-
- CROSS_WR_ADDRESS: process (RX_CLK, RESET)
- begin
- if rising_edge (RX_CLK) then
- if RESET = '1' then
- cross_wraddress_i <= "000";
- else
- cross_wraddress_i <= cross_wraddress_i + 1;
- end if;
- end if;
- end process CROSS_WR_ADDRESS;
-
- CROSS_RD_ADDRESS: process (SYSTEM_CLK, RESET)
- begin
- if rising_edge (SYSTEM_CLK) then
- if RESET = '1' then
- cross_rdaddress_i <= "000";
- else
- cross_rdaddress_i <= cross_rdaddress_i + 1;
- end if;
- end if;
- end process CROSS_RD_ADDRESS;
-
- cross_data_i <= x"0000000" & "00" & rx_comma;
-
- data_opt_in <= "00" & MED_DATA_IN;
-
- SYSTEM_SCM_MEMa: if SYSTEM=1 generate
- CHANNEL_FIFO_TO_OPT: flexi_PCS_fifo_EBR
- port map (
- Data => data_opt_in,
- WrClock => SYSTEM_CLK,
- RdClock => TX_CLK,
- WrEn => MED_DATAREADY_IN,
- RdEn => fifo_opt_not_empty,
- Reset => fifo_rst,
- RPReset => fifo_rst,
- Q => txd_fifo_out,
- Empty => fifo_opt_empty,
- Full => fifo_opt_full,
- AlmostEmpty => fifo_opt_almost_empty,
- AlmostFull => fifo_opt_almost_full
- );
-
- CROSS_CLK_DPMEM: cross_clk
- port map (
- WrAddress => cross_wraddress_i,
- Data => cross_data_i,
- WrClock => RX_CLK,
- WE => '1',
- WrClockEn => '1',
- RdAddress => cross_rdaddress_i,
- RdClock => SYSTEM_CLK,
- RdClockEn => '1',
- Reset => Reset,
- Q => cross_q_i);
-
- end generate SYSTEM_SCM_MEMa;
-
- SYSTEM_ECP2_MEMa: if SYSTEM=2 generate
- CHANNEL_FIFO_TO_OPT: ecp2m_link_fifo
- port map (
- Data => data_opt_in,
- WrClock => SYSTEM_CLK,
- RdClock => TX_CLK,
- WrEn => MED_DATAREADY_IN,
- RdEn => fifo_opt_not_empty,
- Reset => fifo_rst,
- RPReset => fifo_rst,
- Q => txd_fifo_out,
- Empty => fifo_opt_empty,
- Full => fifo_opt_full,
- AlmostEmpty => fifo_opt_almost_empty,
- AlmostFull => fifo_opt_almost_full
- );
- end generate SYSTEM_ECP2_MEMa;
-
- SYSTEMT_TRBv2_MEMa: if SYSTEM=6 generate
-
- CHANNEL_FIFO_TO_FPGA: trbv2_link_fifo
- port map (
- din => data_opt_in,
- rd_clk => TX_CLK,
- rd_en => fifo_opt_not_empty,
- rst => fifo_rst,
- wr_clk => SYSTEM_CLK,
- wr_en => MED_DATAREADY_IN,
- almost_empty => fifo_opt_almost_empty,
- almost_full => fifo_opt_almost_full,
- dout => txd_fifo_out,
- empty => fifo_opt_empty,
- full => fifo_opt_full);
-
- TRBv2_CROSS_CLK_INST: trbv2_cross_clk
- port map (
- addra => cross_wraddress_i,
- addrb => cross_rdaddress_i,
- clka => RX_CLK,
- clkb => SYSTEM_CLK,
- dina => cross_data_i,
- dinb => x"00000000",
- douta => open,
- doutb => cross_q_i,
- wea => '1',
- web => '0');
-
- end generate SYSTEMT_TRBv2_MEMa;
-
- DATA_SEND_TO_LINK: process (TX_CLK, RESET, MED_DATAREADY_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch)
- begin
- if rising_edge(TX_CLK) then
- if RESET = '1' then
- tx_k_i <= '0';
- txd_synch_i <= (others => '0');
- fifo_opt_empty_synch <= fifo_opt_empty;
- fifo_opt_empty_synch_synch <= fifo_opt_empty_synch;
- fifo_opt_not_empty <= not fifo_opt_empty;
- elsif fifo_opt_empty_synch = '0' and fifo_opt_empty_synch_synch ='0' then
- tx_k_i <= '0';
- txd_synch_i <= txd_fifo_out(15 downto 0);
- fifo_opt_empty_synch <= fifo_opt_empty;
- fifo_opt_empty_synch_synch <= fifo_opt_empty_synch;
- fifo_opt_not_empty <= not fifo_opt_empty;
- else
- tx_k_i <= '1';
- txd_synch_i <= x"c5bc";
- fifo_opt_empty_synch <= fifo_opt_empty;
- fifo_opt_empty_synch_synch <= fifo_opt_empty_synch;
- fifo_opt_not_empty <= not fifo_opt_empty;
- end if;
- end if;
- end process DATA_SEND_TO_LINK;
-
- SYNC_DATA : process (TX_CLK)
- begin
- if rising_edge(TX_CLK) then
- TXD <= txd_synch_i;
- TX_K(0) <= tx_k_i;
- TX_K(1) <= '0';
- end if;
- end process SYNC_DATA;
-
- -----------------------------------------------------------------------------
- -- from link to hub
- -----------------------------------------------------------------------------
- SYSTEM_SCM_MEMb: if SYSTEM=1 generate
- CHANNEL_FIFO_TO_FPGA: flexi_PCS_fifo_EBR
- port map (
- Data => fifo_data_in,
- WrClock => RX_CLK,
- RdClock => SYSTEM_CLK,
- WrEn => fifo_wr_en,
- RdEn => fifo_rd_en,
- Reset => fifo_rst,
- RPReset => fifo_rst,
- Q => fifo_data_out,
- Empty => fifo_empty,
- Full => fifo_full,
- AlmostEmpty => fifo_almost_empty,
- AlmostFull => fifo_almost_full
- );
- end generate SYSTEM_SCM_MEMb;
-
- SYSTEM_ECP2_MEMb: if SYSTEM=2 generate
- CHANNEL_FIFO_TO_FPGA: ecp2m_link_fifo
- port map (
- Data => fifo_data_in,
- WrClock => RX_CLK,
- RdClock => SYSTEM_CLK,
- WrEn => fifo_wr_en,
- RdEn => fifo_rd_en,
- Reset => fifo_rst,
- RPReset => fifo_rst,
- Q => fifo_data_out,
- Empty => fifo_empty,
- Full => fifo_full,
- AlmostEmpty => fifo_almost_empty,
- AlmostFull => fifo_almost_full
- );
- end generate SYSTEM_ECP2_MEMb;
-
- SYSTEM_TRBv2: if SYSTEM=6 generate
-
- CHANNEL_FIFO_TO_FPGA: trbv2_link_fifo
- port map (
- din => fifo_data_in,
- rd_clk => SYSTEM_CLK,
- rd_en => fifo_rd_en,
- rst => fifo_rst,
- wr_clk => RX_CLK,
- wr_en => fifo_wr_en,
- almost_empty => fifo_almost_empty,
- almost_full => fifo_almost_full,
- dout => fifo_data_out,
- empty => fifo_empty,
- full => fifo_full);
-
- end generate SYSTEM_TRBv2;
-
- not_fifo_empty <= not fifo_empty;
- RD_FIFO_PULSE: edge_to_pulse
- port map (
- clock => SYSTEM_CLK,
- en_clk => '1',
- signal_in => not_fifo_empty,
- pulse => fifo_rd_pulse);
-
- READING_THE_FIFO: process (SYSTEM_CLK, RESET, fifo_rd_pulse,MED_READ_IN,fifo_empty,data_valid_out_i)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- data_valid_out_i <= '0';
- fifo_rd_en_hub <= '0';
- elsif fifo_rd_pulse = '1' then
- data_valid_out_i <= '1';
- fifo_rd_en_hub <= MED_READ_IN;
- elsif MED_READ_IN = '1' and fifo_empty = '1' and data_valid_out_i = '1' then
- data_valid_out_i <= '0';
- fifo_rd_en_hub <= '0';
- elsif data_valid_out_i = '1' and fifo_empty = '0' then
- data_valid_out_i <= '1';
- fifo_rd_en_hub <= MED_READ_IN;
- end if;
- end if;
- end process READING_THE_FIFO;
-
- MED_DATAREADY_OUT <= data_valid_out_i;
- fifo_rd_en <= (fifo_rd_en_hub and (not fifo_empty)) or fifo_rd_pulse;
- MED_DATA_OUT <= fifo_data_out(15 downto 0);
-
- VALID_DATA_SEND_TO_API: process (RX_CLK, RESET)
- begin
- if rising_edge(RX_CLK) then
- if RESET = '1' then
- rxd_synch_i <= (others => '0');
- rxd_synch_synch_i <= rxd_synch_i;
- rx_k_synch_i <= "00";
- rx_k_synch_synch_i <= rx_k_synch_i;
- else
- rxd_synch_i <= RXD;
- rxd_synch_synch_i <= rxd_synch_i;
- rx_k_synch_i <= RX_K;
- rx_k_synch_synch_i <= rx_k_synch_i;
- end if;
- end if;
- end process VALID_DATA_SEND_TO_API;
-
-
-
- SHIFT_OR_NOT_DATA_IN: process (RX_CLK, RESET, SYNC_CURRENT)
- begin
- if rising_edge(RX_CLK) then
- if RESET = '1' then
- fifo_data_in <= (others => '0');
- elsif SYNC_CURRENT = NORMAL_OPERATION_2 and CV="00" then
- fifo_data_in <= '0' & (not RX_K(0)) & RXD;
- fifo_wr_en <= not RX_K(0);
- elsif SYNC_CURRENT = NORMAL_OPERATION_1 and CV="00" then
- fifo_data_in <= '0' & (not RX_K(1)) & RXD(7 downto 0) & rxd_synch_i(15 downto 8);
- fifo_wr_en <= not rx_k_synch_i(1);
- else
- fifo_data_in <= (others => '0');
- fifo_wr_en <= '0';
- end if;
- end if;
- end process SHIFT_OR_NOT_DATA_IN;
-
- SAVE_COMA: process (RX_CLK, RESET)
- begin
- if rising_edge(RX_CLK) then
- if RESET = '1' then
- rx_comma <= "00";
- elsif (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' and cv_i = "00" then
- rx_comma <= "01";
- elsif (rxd_synch_i = x"bc50" or rxd_synch_i = x"bcc5") and rx_k_synch_i(1) = '1' and cv_i = "00" then
- rx_comma <= "10";
- elsif cv_i /= "00" then
- rx_comma <= "11";
- else
- rx_comma <= "00";
- end if;
- end if;
- end process SAVE_COMA;
-
-
- SYNC_CLOCK : process (SYSTEM_CLK, RESET)
- begin
- if rising_edge (SYSTEM_CLK) then
- if RESET = '1' then
- SYNC_CURRENT <= FIRST_DUMMY_STATE;--no_sim --
---sim-- SYNC_CURRENT <= NORMAL_OPERATION_2;
- cv_i <= (others => '0');
- fifo_rst <= '1';
- fsm_debug_register <= "1111";
- rx_rst_i <= '0';
- resync_counter_up <= '0';
- resync_counter_clr <= '1';
- wait_for_write_up <= '0';
- MED_READ_OUT <= '0';
- rx_comma_synch <= "00";
- else
- SYNC_CURRENT <= SYNC_NEXT;
- cv_i <= CV;
- fifo_rst <= fifo_rst_fsm;
- fsm_debug_register <= fsm_debug_register_fsm;
- rx_rst_i <= rx_rst_fsm;
- resync_counter_up <= resync_counter_up_fsm;
- resync_counter_clr <= resync_counter_clr_fsm;
- wait_for_write_up <= wait_for_write_up_fsm;
- MED_READ_OUT <= MED_READ_OUT_fsm;
- rx_comma_synch <= cross_q_i(1 downto 0);
- end if;
- end if;
- end process SYNC_CLOCK;
-
- SYNC_FSM : process(SYNC_CURRENT)
- begin
- fifo_rst_fsm <= '0';
- fsm_debug_register_fsm <= "1111";
- rx_rst_fsm <= '0';
- resync_counter_up_fsm <= '1';
- resync_counter_clr_fsm <= '0';
- wait_for_write_up_fsm <= '0';
- MED_READ_OUT_fsm <= '0';
- SYNC_NEXT <= RESYNC0;
-
- case (SYNC_CURRENT) is
- --check the sfp, pll lock and so on
- -- all counters are are only reset in state START_COUNTER
-
- when FIRST_DUMMY_STATE =>
- resync_counter_up_fsm <= '0';
- fsm_debug_register_fsm <= "0001";
- SYNC_NEXT <= START_COUNTER;
-
- when START_COUNTER =>
- fsm_debug_register_fsm <= "0010";
- resync_counter_up_fsm <= '0';
- resync_counter_clr_fsm <= '1';
- fifo_rst_fsm <= '1';
- SYNC_NEXT <= RESYNC0;
-
- when RESYNC0 =>
- fsm_debug_register_fsm <= "0011";
- resync_counter_up_fsm <= '0';
- if MEDIA_STATUS(0) = '1' then
- SYNC_NEXT <= START_COUNTER;
- elsif rx_comma_synch = "01" or rx_comma_synch = "10" then
- SYNC_NEXT <= WAIT_1;
- else
- SYNC_NEXT <= RESYNC1;
- end if;
- --SYNC_NEXT <= RESYNC1;
-
- when RESYNC1 =>
- fsm_debug_register_fsm <= "0100";
- rx_rst_fsm <= '1';
- if resync_counter(9) = '1' then
- SYNC_NEXT <= RESYNC2;
- else
- SYNC_NEXT <= RESYNC1;
- end if;
-
- when RESYNC2 => -- just waiting
- fsm_debug_register_fsm <= "0101";
- if resync_counter(18) = '1' then --at least 400us
- SYNC_NEXT <= RESYNC3;
- else
- SYNC_NEXT <= RESYNC2;
- end if;
-
- when RESYNC3 => -- check for comma
- fsm_debug_register_fsm <= "0110";
- if rx_comma_synch = "01" or rx_comma_synch = "10" then
- SYNC_NEXT <= WAIT_2;--no_sim--
---sim-- SYNC_NEXT <= NORMAL_OPERATION_2;
- else
- SYNC_NEXT <= START_COUNTER;
- end if;
-
- when WAIT_1 => -- wait for comma
- fsm_debug_register_fsm <= "0111";
- if resync_counter(28) = '1' then
- SYNC_NEXT <= WAIT_3;
- elsif resync_counter(27) = '1' and (rx_comma_synch = "00" or rx_comma_synch = "11") then
- SYNC_NEXT <= START_COUNTER;
- else
- SYNC_NEXT <= WAIT_1;
- end if;
-
- when WAIT_3 =>
- fsm_debug_register_fsm <= "1001";
- wait_for_write_up_fsm <= '1';
- if wait_for_write_counter(28)='1' and rx_comma_synch = "01" then
- SYNC_NEXT <= NORMAL_OPERATION_2;
- elsif wait_for_write_counter(28)='1' and rx_comma_synch = "10" then
- SYNC_NEXT <= NORMAL_OPERATION_1;
- elsif rx_comma_synch = "11" then
- SYNC_NEXT <= START_COUNTER;
- else
- SYNC_NEXT <= WAIT_3;
- end if;
-
- when NORMAL_OPERATION_1 =>
---sim-- fifo_rst <=RESET;
- fsm_debug_register_fsm <= "1010";
- resync_counter_up_fsm <= '0';
- MED_READ_OUT_fsm <= '1';
- if rx_comma_synch = "11" then
--- if MEDIA_STATUS(0) = '1' then
-
- SYNC_NEXT <= START_COUNTER;
- else
- SYNC_NEXT <= NORMAL_OPERATION_1;
- end if;
-
- when NORMAL_OPERATION_2 =>
---sim-- fifo_rst <=RESET;
- fsm_debug_register_fsm <= "1011";
- resync_counter_up_fsm <= '0';
- MED_READ_OUT_fsm <= '1';
- if rx_comma_synch = "11" then
--- if MEDIA_STATUS(0) = '1' then
- SYNC_NEXT <= START_COUNTER;
- else
- SYNC_NEXT <= NORMAL_OPERATION_2;
- end if;
-
-
- when others =>
- fsm_debug_register_fsm <= "0000";
- SYNC_NEXT <= START_COUNTER;
-
- end case;
- end process SYNC_FSM;
-
- LED_FOR_LINK: process (SYSTEM_CLK)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- MED_STAT_OP(9) <= '1';
- elsif fsm_debug_register < 9 and fsm_debug_register > 3 then
- MED_STAT_OP(9) <= diod_counter(23);
- elsif fsm_debug_register = 9 then
- MED_STAT_OP(9) <= diod_counter(26);
- elsif fsm_debug_register > 9 then
- MED_STAT_OP(9) <= '0';
- else
- MED_STAT_OP(9) <= '1';
- end if;
- end if;
- end process LED_FOR_LINK;
-
- DIOD_COUNTER_INST: up_down_counter
- generic map (
- NUMBER_OF_BITS => 29)
- port map (
- CLK => SYSTEM_CLK,
- RESET => '0',
- COUNT_OUT => diod_counter,
- UP_IN => '1',
- DOWN_IN => '0');
-
- WAIT_FOR_SENDING: up_down_counter
- generic map (
- NUMBER_OF_BITS => 29)
- port map (
- CLK => SYSTEM_CLK,
- RESET => resync_counter_clr,
- COUNT_OUT => wait_for_write_counter,
- UP_IN => wait_for_write_up,
- DOWN_IN => '0');
-
- RESYNC_COUNTER_INST: up_down_counter
- generic map (
- NUMBER_OF_BITS => 32)
- port map (
- CLK => SYSTEM_CLK,
- RESET => resync_counter_clr,
- COUNT_OUT => resync_counter,
- UP_IN => resync_counter_up,
- DOWN_IN => '0');
-
- cv_or <= cv_i(0) or cv_i(1);
-
- CV_COUNTER_INST: up_down_counter
- generic map (
- NUMBER_OF_BITS => 16)
- port map (
- CLK => RX_CLK,
- RESET => RESET,
- COUNT_OUT => cv_counter,
- UP_IN => cv_or,
- DOWN_IN => '0');
- SYNCH_ERR_COUNT : process (SYSTEM_CLK, RESET)
- begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- rx_comma_synch_err <= '0';
- elsif SYNC_CURRENT = NORMAL_OPERATION_1 or SYNC_CURRENT = NORMAL_OPERATION_2 then
- rx_comma_synch_err <= rx_comma_synch(1) and rx_comma_synch(0);
- else
- rx_comma_synch_err <= '0';
- end if;
- end if;
- end process SYNCH_ERR_COUNT;
-
- LINK_CONECTION_LOST_COUNTER: up_down_counter
- generic map (
- NUMBER_OF_BITS => 16)
- port map (
- CLK => RX_CLK,
- RESET => RESET,
- COUNT_OUT => lost_connection_count,
- UP_IN => rx_comma_synch_err,
- DOWN_IN => '0');
-
- WRITE_COUNTER: up_down_counter
- generic map (
- NUMBER_OF_BITS => 16)
- port map (
- CLK => SYSTEM_CLK,
- RESET => RESET,
- COUNT_OUT => fifo_wr_cnt,
- UP_IN => fifo_wr_en,
- DOWN_IN => '0');
-
- READ_COUNTER: up_down_counter
- generic map (
- NUMBER_OF_BITS => 16)
- port map (
- CLK => SYSTEM_CLK,
- RESET => RESET,
- COUNT_OUT => fifo_rd_cnt,
- UP_IN => MED_DATAREADY_IN,
- DOWN_IN => '0');
-
-end flexi_PCS_channel_synch;
-
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
--- Module Version: 4.2
---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n flexi_PCS_fifo_EBR -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -e
-
--- Tue Nov 27 10:58:36 2007
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library SCM;
-use SCM.COMPONENTS.all;
--- synopsys translate_on
-
-entity flexi_PCS_fifo_EBR is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end flexi_PCS_fifo_EBR;
-
-architecture Structure of flexi_PCS_fifo_EBR is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal Empty_int: std_logic;
- signal Full_int: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component FIFO16KA
- -- synopsys translate_off
- generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
- FULLPOINTER : in std_logic_vector(14 downto 0);
- AFPOINTER1 : in std_logic_vector(14 downto 0);
- AEPOINTER1 : in std_logic_vector(14 downto 0);
- AFPOINTER : in std_logic_vector(14 downto 0);
- AEPOINTER : in std_logic_vector(14 downto 0);
- CSDECODE_R : in std_logic_vector(1 downto 0);
- CSDECODE_W : in std_logic_vector(1 downto 0);
- RESETMODE : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- -- synopsys translate_on
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- FULLI: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; EMPTYI: in std_logic;
- CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
- RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
- RST: in std_logic; RPRST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic;
- EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
- FF: out std_logic);
- end component;
- attribute FULLPOINTER1 : string;
- attribute FULLPOINTER : string;
- attribute AFPOINTER1 : string;
- attribute AFPOINTER : string;
- attribute AEPOINTER1 : string;
- attribute AEPOINTER : string;
- attribute RESETMODE : string;
- attribute REGMODE : string;
- attribute CSDECODE_R : string;
- attribute CSDECODE_W : string;
- attribute DATA_WIDTH_R : string;
- attribute DATA_WIDTH_W : string;
- attribute FULLPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111000001";
- attribute FULLPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111100001";
- attribute AFPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101000001";
- attribute AFPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101100001";
- attribute AEPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101111111";
- attribute AEPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101011111";
- attribute RESETMODE of flexi_PCS_fifo_EBR_0_0 : label is "ASYNC";
- attribute REGMODE of flexi_PCS_fifo_EBR_0_0 : label is "NOREG";
- attribute CSDECODE_R of flexi_PCS_fifo_EBR_0_0 : label is "0b11";
- attribute CSDECODE_W of flexi_PCS_fifo_EBR_0_0 : label is "0b11";
- attribute DATA_WIDTH_R of flexi_PCS_fifo_EBR_0_0 : label is "36";
- attribute DATA_WIDTH_W of flexi_PCS_fifo_EBR_0_0 : label is "36";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- flexi_PCS_fifo_EBR_0_0: FIFO16KA
- -- synopsys translate_off
- generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001",
- AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001",
- AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
- CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- -- synopsys translate_on
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
- DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
- DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
- DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
- DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
- EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi,
- WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
- RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
- DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
- DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
- DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0),
- DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
- DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
- DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
- DO33=>Q(15), DO34=>Q(16), DO35=>Q(17), EF=>Empty_int,
- AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int);
-
- Empty <= Empty_int;
- Full <= Full_int;
-end Structure;
-
--- synopsys translate_off
-library SCM;
-configuration Structure_CON of flexi_PCS_fifo_EBR is
- for Structure
- for all:VHI use entity SCM.VHI(V); end for;
- for all:VLO use entity SCM.VLO(V); end for;
- for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
--- Module Version: 4.2
---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n flexi_PCS_fifo_LUT -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 8 -width 18 -rwidth 18 -pfu_fifo -no_enable -pe 3 -pf 6 -e
-
--- Fri Nov 23 08:28:34 2007
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library SCM;
-use SCM.COMPONENTS.all;
--- synopsys translate_on
-
-entity flexi_PCS_fifo_LUT is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end flexi_PCS_fifo_LUT;
-
-architecture Structure of flexi_PCS_fifo_LUT is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal wptr_3: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal rptr_3: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal empty_i: std_logic;
- signal full_i: std_logic;
- signal rRst: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co1: std_logic;
- signal wcount_3: std_logic;
- signal co0: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co1_1: std_logic;
- signal rcount_3: std_logic;
- signal co0_1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_2: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_2: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal iae_setcount_0: std_logic;
- signal iae_setcount_1: std_logic;
- signal iae_setcount_2: std_logic;
- signal iae_setcount_3: std_logic;
- signal co1_2: std_logic;
- signal ae_setcount_3: std_logic;
- signal co0_4: std_logic;
- signal rden_i: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r1: std_logic;
- signal ae_setcount_0: std_logic;
- signal ae_setcount_1: std_logic;
- signal co0_5: std_logic;
- signal wcount_r2: std_logic;
- signal ae_set_cmp_clr: std_logic;
- signal ae_setcount_2: std_logic;
- signal ae_set_cmp_set: std_logic;
- signal ae_set_d: std_logic;
- signal ae_set_d_c: std_logic;
- signal iaf_setcount_0: std_logic;
- signal iaf_setcount_1: std_logic;
- signal iaf_setcount_2: std_logic;
- signal iaf_setcount_3: std_logic;
- signal co1_3: std_logic;
- signal af_setcount_3: std_logic;
- signal co0_6: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w1: std_logic;
- signal af_setcount_0: std_logic;
- signal af_setcount_1: std_logic;
- signal co0_7: std_logic;
- signal rcount_w2: std_logic;
- signal af_set_cmp_clr: std_logic;
- signal af_setcount_2: std_logic;
- signal af_set_cmp_set: std_logic;
- signal af_set: std_logic;
- signal af_set_c: std_logic;
- signal rdataout17: std_logic;
- signal rdataout16: std_logic;
- signal rdataout15: std_logic;
- signal rdataout14: std_logic;
- signal rdataout13: std_logic;
- signal rdataout12: std_logic;
- signal rdataout11: std_logic;
- signal rdataout10: std_logic;
- signal rdataout9: std_logic;
- signal rdataout8: std_logic;
- signal rdataout7: std_logic;
- signal rdataout6: std_logic;
- signal rdataout5: std_logic;
- signal rdataout4: std_logic;
- signal rdataout3: std_logic;
- signal rdataout2: std_logic;
- signal rdataout1: std_logic;
- signal rdataout0: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal wren_i: std_logic;
- signal scuba_vhi: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component DPR16X2
- -- synopsys translate_off
- generic (INITVAL : in String; GSR : in String);
- -- synopsys translate_on
- port (DI0: in std_logic; DI1: in std_logic;
- WAD3: in std_logic; WAD2: in std_logic;
- WAD1: in std_logic; WAD0: in std_logic; WRE: in std_logic;
- WPE: in std_logic; WCK: in std_logic; RAD3: in std_logic;
- RAD2: in std_logic; RAD1: in std_logic;
- RAD0: in std_logic; WDO0: out std_logic;
- WDO1: out std_logic; RDO0: out std_logic;
- RDO1: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component FADD2
- port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
- B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
- COUT0: out std_logic; S1: out std_logic;
- S0: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
- CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
- end component;
- component AGEB2
- port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
- B0: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component FD1P3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- attribute GSR : string;
- attribute initval : string;
- attribute initval of LUT4_13 : label is "0x6996";
- attribute initval of LUT4_12 : label is "0x6996";
- attribute initval of LUT4_11 : label is "0x6996";
- attribute initval of LUT4_10 : label is "0x6996";
- attribute initval of LUT4_9 : label is "0x6996";
- attribute initval of LUT4_8 : label is "0x6996";
- attribute initval of LUT4_7 : label is "0x0410";
- attribute initval of LUT4_6 : label is "0x1004";
- attribute initval of LUT4_5 : label is "0x0140";
- attribute initval of LUT4_4 : label is "0x4001";
- attribute initval of LUT4_3 : label is "0x13c8";
- attribute initval of LUT4_2 : label is "0x2004";
- attribute initval of LUT4_1 : label is "0x4c32";
- attribute initval of LUT4_0 : label is "0x8001";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute GSR of fifo_pfu_0_0 : label is "ENABLED";
- attribute initval of fifo_pfu_0_0 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_1 : label is "ENABLED";
- attribute initval of fifo_pfu_0_1 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_2 : label is "ENABLED";
- attribute initval of fifo_pfu_0_2 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_3 : label is "ENABLED";
- attribute initval of fifo_pfu_0_3 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_4 : label is "ENABLED";
- attribute initval of fifo_pfu_0_4 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_5 : label is "ENABLED";
- attribute initval of fifo_pfu_0_5 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_6 : label is "ENABLED";
- attribute initval of fifo_pfu_0_6 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_7 : label is "ENABLED";
- attribute initval of fifo_pfu_0_7 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_8 : label is "ENABLED";
- attribute initval of fifo_pfu_0_8 : label is "0x0000000000000000";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t8: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t7: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t6: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t5: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t4: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t3: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t2: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t1: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t0: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- LUT4_13: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_11: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_10: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_9: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_8: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x6996")
- -- synopsys translate_on
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_7: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0410")
- -- synopsys translate_on
- port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_6: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x1004")
- -- synopsys translate_on
- port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_5: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x0140")
- -- synopsys translate_on
- port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_4: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4001")
- -- synopsys translate_on
- port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- LUT4_3: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x13c8")
- -- synopsys translate_on
- port map (AD3=>ae_setcount_3, AD2=>rcount_3, AD1=>w_gcount_r23,
- AD0=>rptr_3, DO0=>ae_set_cmp_set);
-
- LUT4_2: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x2004")
- -- synopsys translate_on
- port map (AD3=>ae_setcount_3, AD2=>rcount_3, AD1=>w_gcount_r23,
- AD0=>rptr_3, DO0=>ae_set_cmp_clr);
-
- LUT4_1: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x4c32")
- -- synopsys translate_on
- port map (AD3=>af_setcount_3, AD2=>wcount_3, AD1=>r_gcount_w23,
- AD0=>wptr_3, DO0=>af_set_cmp_set);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8001")
- -- synopsys translate_on
- port map (AD3=>af_setcount_3, AD2=>wcount_3, AD1=>r_gcount_w23,
- AD0=>wptr_3, DO0=>af_set_cmp_clr);
-
- FF_69: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_68: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_67: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_66: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_65: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_64: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_63: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_62: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_61: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_60: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_59: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_58: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_57: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_56: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_55: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_54: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_53: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_52: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_51: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_50: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_49: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_48: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_47: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_46: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_45: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(0));
-
- FF_44: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(1));
-
- FF_43: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(2));
-
- FF_42: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(3));
-
- FF_41: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(4));
-
- FF_40: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(5));
-
- FF_39: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(6));
-
- FF_38: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(7));
-
- FF_37: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(8));
-
- FF_36: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(9));
-
- FF_35: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(10));
-
- FF_34: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(11));
-
- FF_33: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(12));
-
- FF_32: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(13));
-
- FF_31: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(14));
-
- FF_30: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(15));
-
- FF_29: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(16));
-
- FF_28: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>Q(17));
-
- FF_27: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_26: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_25: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_24: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_23: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_22: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_21: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_20: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_19: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_18: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_17: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_16: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_15: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_14: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_13: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_12: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_11: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- FF_9: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_0);
-
- FF_8: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_1);
-
- FF_7: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_2, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>ae_setcount_2);
-
- FF_6: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iae_setcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>ae_setcount_3);
-
- FF_5: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ae_set_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
-
- FF_4: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_0);
-
- FF_3: FD1P3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_1);
-
- FF_2: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_2);
-
- FF_1: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_3);
-
- FF_0: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
-
- w_gctr_0: CU2
- port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0,
- NC1=>iwcount_1, NC0=>iwcount_0);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC1=>wcount_3, PC0=>wcount_2, CO=>co1,
- NC1=>iwcount_3, NC0=>iwcount_2);
-
- r_gctr_0: CU2
- port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_1,
- NC1=>ircount_1, NC0=>ircount_0);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_1,
- NC1=>ircount_3, NC0=>ircount_2);
-
- empty_cmp_0: AGEB2
- port map (A1=>rcount_1, A0=>rcount_0, B1=>wcount_r1,
- B0=>w_g2b_xor_cluster_0, CI=>rden_i, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A1=>empty_cmp_set, A0=>rcount_2, B1=>empty_cmp_clr,
- B0=>wcount_r2, CI=>co0_2, GE=>empty_d_c);
-
- a0: FADD2
- port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
- B0=>scuba_vlo, CI=>empty_d_c, COUT1=>open, COUT0=>open,
- S1=>open, S0=>empty_d);
-
- full_cmp_0: AGEB2
- port map (A1=>wcount_1, A0=>wcount_0, B1=>rcount_w1,
- B0=>r_g2b_xor_cluster_0, CI=>wren_i, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A1=>full_cmp_set, A0=>wcount_2, B1=>full_cmp_clr,
- B0=>rcount_w2, CI=>co0_3, GE=>full_d_c);
-
- a1: FADD2
- port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
- B0=>scuba_vlo, CI=>full_d_c, COUT1=>open, COUT0=>open,
- S1=>open, S0=>full_d);
-
- ae_set_ctr_0: CU2
- port map (CI=>scuba_vhi, PC1=>ae_setcount_1, PC0=>ae_setcount_0,
- CO=>co0_4, NC1=>iae_setcount_1, NC0=>iae_setcount_0);
-
- ae_set_ctr_1: CU2
- port map (CI=>co0_4, PC1=>ae_setcount_3, PC0=>ae_setcount_2,
- CO=>co1_2, NC1=>iae_setcount_3, NC0=>iae_setcount_2);
-
- ae_set_cmp_0: AGEB2
- port map (A1=>ae_setcount_1, A0=>ae_setcount_0, B1=>wcount_r1,
- B0=>w_g2b_xor_cluster_0, CI=>rden_i, GE=>co0_5);
-
- ae_set_cmp_1: AGEB2
- port map (A1=>ae_set_cmp_set, A0=>ae_setcount_2,
- B1=>ae_set_cmp_clr, B0=>wcount_r2, CI=>co0_5, GE=>ae_set_d_c);
-
- a2: FADD2
- port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
- B0=>scuba_vlo, CI=>ae_set_d_c, COUT1=>open, COUT0=>open,
- S1=>open, S0=>ae_set_d);
-
- af_set_ctr_0: CU2
- port map (CI=>scuba_vhi, PC1=>af_setcount_1, PC0=>af_setcount_0,
- CO=>co0_6, NC1=>iaf_setcount_1, NC0=>iaf_setcount_0);
-
- af_set_ctr_1: CU2
- port map (CI=>co0_6, PC1=>af_setcount_3, PC0=>af_setcount_2,
- CO=>co1_3, NC1=>iaf_setcount_3, NC0=>iaf_setcount_2);
-
- af_set_cmp_0: AGEB2
- port map (A1=>af_setcount_1, A0=>af_setcount_0, B1=>rcount_w1,
- B0=>r_g2b_xor_cluster_0, CI=>wren_i, GE=>co0_7);
-
- af_set_cmp_1: AGEB2
- port map (A1=>af_set_cmp_set, A0=>af_setcount_2,
- B1=>af_set_cmp_clr, B0=>rcount_w2, CI=>co0_7, GE=>af_set_c);
-
- a3: FADD2
- port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
- B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
- S1=>open, S0=>af_set);
-
- fifo_pfu_0_0: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(16), DI1=>Data(17), WAD3=>scuba_vlo,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout16, RDO1=>rdataout17);
-
- fifo_pfu_0_1: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(14), DI1=>Data(15), WAD3=>scuba_vlo,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout14, RDO1=>rdataout15);
-
- fifo_pfu_0_2: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(12), DI1=>Data(13), WAD3=>scuba_vlo,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout12, RDO1=>rdataout13);
-
- fifo_pfu_0_3: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(10), DI1=>Data(11), WAD3=>scuba_vlo,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout10, RDO1=>rdataout11);
-
- fifo_pfu_0_4: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(8), DI1=>Data(9), WAD3=>scuba_vlo,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout8, RDO1=>rdataout9);
-
- fifo_pfu_0_5: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(6), DI1=>Data(7), WAD3=>scuba_vlo,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout6, RDO1=>rdataout7);
-
- fifo_pfu_0_6: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(4), DI1=>Data(5), WAD3=>scuba_vlo,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout4, RDO1=>rdataout5);
-
- fifo_pfu_0_7: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(2), DI1=>Data(3), WAD3=>scuba_vlo,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout2, RDO1=>rdataout3);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- fifo_pfu_0_8: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(0), DI1=>Data(1), WAD3=>scuba_vlo,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout0, RDO1=>rdataout1);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library SCM;
-configuration Structure_CON of flexi_PCS_fifo_LUT is
- for Structure
- for all:DPR16X2 use entity SCM.DPR16X2(V); end for;
- for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
- for all:AND2 use entity SCM.AND2(V); end for;
- for all:OR2 use entity SCM.OR2(V); end for;
- for all:XOR2 use entity SCM.XOR2(V); end for;
- for all:INV use entity SCM.INV(V); end for;
- for all:VHI use entity SCM.VHI(V); end for;
- for all:VLO use entity SCM.VLO(V); end for;
- for all:FADD2 use entity SCM.FADD2(V); end for;
- for all:CU2 use entity SCM.CU2(V); end for;
- for all:AGEB2 use entity SCM.AGEB2(V); end for;
- for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
- for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
- for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
- for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library ieee;
-library work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.all;
-use work.trb_net_std.all;
-
-entity flexi_PCS_synch is
- generic (
- HOW_MANY_CHANNELS : positive;
- SYSTEM : positive
- );
- port (
- RESET : in std_logic;
- SYSTEM_CLK : in std_logic;
- TX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
- RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- TXD : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- MEDIA_STATUS : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MEDIA_CONTROL : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- MED_STAT_OP : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_CTRL_OP : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- LINK_DEBUG : out std_logic_vector(HOW_MANY_CHANNELS*32-1 downto 0)
- );
-end flexi_PCS_synch;
-
-architecture flexi_PCS_synch of flexi_PCS_synch is
-
- component flexi_PCS_channel_synch
- generic (
- SYSTEM : positive
- );
- port (
- RESET : in std_logic;
- SYSTEM_CLK : in std_logic;
- TX_CLK : in std_logic;
- RX_CLK : in std_logic;
- RXD : in std_logic_vector(15 downto 0);
- RX_K : in std_logic_vector(1 downto 0);
- RX_RST : out std_logic;
- CV : in std_logic_vector(1 downto 0);
- TXD : out std_logic_vector(15 downto 0);
- TX_K : out std_logic_vector(1 downto 0);
- MEDIA_STATUS : in std_logic_vector(15 downto 0);
- MEDIA_CONTROL : out std_logic_vector(15 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector(15 downto 0);
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(15 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_STAT_OP : out std_logic_vector(15 downto 0);
- MED_CTRL_OP : in std_logic_vector(15 downto 0);
- LINK_DEBUG : out std_logic_vector(31 downto 0)
- );
- end component;
-
-begin
-
- CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate
- begin
-
- CHANNEL_GENERATE: flexi_PCS_channel_synch
- generic map (
- SYSTEM => SYSTEM
- )
- port map (
- RESET => RESET,
- SYSTEM_CLK => SYSTEM_CLK,
- TX_CLK => TX_CLK(bit_index/4), --4 different channles clk,
- RX_CLK => RX_CLK(bit_index),
- RXD => RXD((bit_index*16+15) downto bit_index*16),
- RX_K => RX_K(bit_index*2+1 downto bit_index*2),
- RX_RST => RX_RST(bit_index),
- CV => CV((bit_index*2+1) downto bit_index*2),
- TXD => TXD((bit_index*16+15) downto bit_index*16),
- TX_K => TX_K(bit_index*2+1 downto bit_index*2),
- MEDIA_STATUS => MEDIA_STATUS((bit_index*16+15) downto bit_index*16),
- MEDIA_CONTROL => MEDIA_CONTROL((bit_index*16+15) downto bit_index*16),
- MED_DATAREADY_IN => MED_DATAREADY_IN(bit_index),
- MED_DATA_IN => MED_DATA_IN((bit_index*16+15) downto bit_index*16),
- MED_READ_OUT => MED_READ_OUT(bit_index),
- MED_DATA_OUT => MED_DATA_OUT((bit_index*16+15) downto bit_index*16),
- MED_DATAREADY_OUT => MED_DATAREADY_OUT(bit_index),
- MED_READ_IN => MED_READ_IN(bit_index),
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH),
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH),
- MED_STAT_OP => MED_STAT_OP((bit_index*16+15) downto bit_index*16),
- MED_CTRL_OP => MED_CTRL_OP((bit_index*16+15) downto bit_index*16),
- LINK_DEBUG => LINK_DEBUG((bit_index*32+31) downto bit_index*32)
- );
-
- end generate;
-
-end flexi_PCS_synch;
+++ /dev/null
-COMMERCIAL;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-#LOCATE COMP "ADDON_RESET" SITE "J21" ;
-#LOCATE COMP "ADO_CLKOUTN" SITE "AE4" ;
-#LOCATE COMP "ADO_CLKOUTP" SITE "AE3" ;
-#LOCATE COMP "ADO_LV_0" SITE "D32" ;
-#LOCATE COMP "ADO_LV_1" SITE "D31" ;
-#LOCATE COMP "ADO_LV_2" SITE "F32" ;
-#LOCATE COMP "ADO_LV_3" SITE "F31" ;
-#LOCATE COMP "ADO_LV_4" SITE "J29" ;
-#LOCATE COMP "ADO_LV_5" SITE "H29" ;
-#LOCATE COMP "ADO_LV_6" SITE "L32" ;
-#LOCATE COMP "ADO_LV_7" SITE "M32" ;
-#LOCATE COMP "ADO_LV_8" SITE "P30" ;
-#LOCATE COMP "ADO_LV_9" SITE "P29" ;
-#LOCATE COMP "ADO_LV_10" SITE "R30" ;
-#LOCATE COMP "ADO_LV_11" SITE "R29" ;
-#LOCATE COMP "ADO_LV_12" SITE "T31" ;
-#LOCATE COMP "ADO_LV_13" SITE "T32" ;
-#LOCATE COMP "ADO_LV_14" SITE "V32" ;
-#LOCATE COMP "ADO_LV_15" SITE "V31" ;
-#LOCATE COMP "ADO_LV_16" SITE "W30" ;
-#LOCATE COMP "ADO_LV_17" SITE "W29" ;
-#LOCATE COMP "ADO_LV_18" SITE "W28" ;
-#LOCATE COMP "ADO_LV_19" SITE "Y28" ;
-#LOCATE COMP "ADO_LV_20" SITE "AB32" ;
-#LOCATE COMP "ADO_LV_21" SITE "AA32" ;
-#LOCATE COMP "ADO_LV_22" SITE "AD29" ;
-#LOCATE COMP "ADO_LV_23" SITE "AD30" ;
-#LOCATE COMP "ADO_LV_24" SITE "AC32" ;
-#LOCATE COMP "ADO_LV_25" SITE "AD32" ;
-#LOCATE COMP "ADO_LV_26" SITE "AE31" ;
-#LOCATE COMP "ADO_LV_27" SITE "AE32" ;
-#LOCATE COMP "ADO_LV_28" SITE "E32" ;
-#LOCATE COMP "ADO_LV_29" SITE "E31" ;
-#LOCATE COMP "ADO_LV_30" SITE "G31" ;
-#LOCATE COMP "ADO_LV_31" SITE "G32" ;
-#LOCATE COMP "ADO_LV_32" SITE "H31" ;
-#LOCATE COMP "ADO_LV_33" SITE "H32" ;
-#LOCATE COMP "ADO_LV_34" SITE "N31" ;
-#LOCATE COMP "ADO_LV_35" SITE "N32" ;
-#LOCATE COMP "ADO_LV_36" SITE "P32" ;
-#LOCATE COMP "ADO_LV_37" SITE "P31" ;
-#LOCATE COMP "ADO_LV_38" SITE "R31" ;
-#LOCATE COMP "ADO_LV_39" SITE "R32" ;
-#LOCATE COMP "ADO_LV_40" SITE "U32" ;
-#LOCATE COMP "ADO_LV_41" SITE "U31" ;
-#LOCATE COMP "ADO_LV_42" SITE "V29" ;
-#LOCATE COMP "ADO_LV_43" SITE "V30" ;
-#LOCATE COMP "ADO_LV_44" SITE "W31" ;
-#LOCATE COMP "ADO_LV_45" SITE "Y31" ;
-#LOCATE COMP "ADO_LV_46" SITE "W32" ;
-#LOCATE COMP "ADO_LV_47" SITE "Y32" ;
-#LOCATE COMP "ADO_LV_48" SITE "AD31" ;
-#LOCATE COMP "ADO_LV_49" SITE "AC31" ;
-#LOCATE COMP "ADO_LV_50" SITE "AC28" ;
-#LOCATE COMP "ADO_LV_51" SITE "AD28" ;
-#LOCATE COMP "ADO_LV_52" SITE "AE30" ;
-#LOCATE COMP "ADO_LV_53" SITE "AE29" ;
-#LOCATE COMP "ADO_LV_54" SITE "AF32" ;
-#LOCATE COMP "ADO_LV_55" SITE "AF31" ;
-#LOCATE COMP "ADO_LV_56" SITE "AG1" ;
-#LOCATE COMP "ADO_LV_57" SITE "AG2" ;
-#LOCATE COMP "ADO_LV_58" SITE "AE2" ;
-#LOCATE COMP "ADO_LV_59" SITE "AE1" ;
-#LOCATE COMP "ADO_LV_60" SITE "AF1" ;
-#LOCATE COMP "ADO_LV_61" SITE "AF2" ;
-LOCATE COMP "ADO_TTL_0" SITE "AJ32" ;
-LOCATE COMP "ADO_TTL_1" SITE "AF27" ;
-LOCATE COMP "ADO_TTL_2" SITE "AK31" ;
-LOCATE COMP "ADO_TTL_3" SITE "AE25" ;
-LOCATE COMP "ADO_TTL_4" SITE "AK30" ;
-LOCATE COMP "ADO_TTL_5" SITE "AD23" ;
-LOCATE COMP "ADO_TTL_6" SITE "AK29" ;
-LOCATE COMP "ADO_TTL_7" SITE "AF26" ;
-LOCATE COMP "ADO_TTL_8" SITE "AJ28" ;
-LOCATE COMP "ADO_TTL_9" SITE "AJ31" ;
-LOCATE COMP "ADO_TTL_10" SITE "AM30" ;
-LOCATE COMP "ADO_TTL_11" SITE "AH29" ;
-LOCATE COMP "ADO_TTL_12" SITE "AJ27" ;
-LOCATE COMP "ADO_TTL_13" SITE "AE22" ;
-LOCATE COMP "ADO_TTL_14" SITE "AL28" ;
-LOCATE COMP "ADO_TTL_15" SITE "AC21" ;
-LOCATE COMP "ADO_TTL_16" SITE "AM28" ;
-LOCATE COMP "ADO_TTL_17" SITE "AG23" ;
-LOCATE COMP "ADO_TTL_18" SITE "AG26" ;
-LOCATE COMP "ADO_TTL_19" SITE "AL26" ;
-LOCATE COMP "ADO_TTL_20" SITE "AK32" ;
-LOCATE COMP "ADO_TTL_21" SITE "AG28" ;
-LOCATE COMP "ADO_TTL_22" SITE "AL31" ;
-LOCATE COMP "ADO_TTL_23" SITE "AE24" ;
-LOCATE COMP "ADO_TTL_24" SITE "AL30" ;
-LOCATE COMP "ADO_TTL_25" SITE "AE23" ;
-LOCATE COMP "ADO_TTL_26" SITE "AL29" ;
-LOCATE COMP "ADO_TTL_27" SITE "AF25" ;
-LOCATE COMP "ADO_TTL_28" SITE "AK28" ;
-LOCATE COMP "ADO_TTL_29" SITE "AH30" ;
-LOCATE COMP "ADO_TTL_30" SITE "AM29" ;
-LOCATE COMP "ADO_TTL_31" SITE "AH28" ;
-LOCATE COMP "ADO_TTL_32" SITE "AK27" ;
-LOCATE COMP "ADO_TTL_33" SITE "AF23" ;
-LOCATE COMP "ADO_TTL_34" SITE "AL27" ;
-LOCATE COMP "ADO_TTL_35" SITE "AD21" ;
-LOCATE COMP "ADO_TTL_36" SITE "AM27" ;
-LOCATE COMP "ADO_TTL_37" SITE "AF22" ;
-LOCATE COMP "ADO_TTL_38" SITE "AG25" ;
-LOCATE COMP "ADO_TTL_39" SITE "AM26" ;
-LOCATE COMP "ADO_TTL_40" SITE "AK24" ;
-LOCATE COMP "ADO_TTL_41" SITE "AE20" ;
-LOCATE COMP "ADO_TTL_42" SITE "AJ24" ;
-LOCATE COMP "ADO_TTL_43" SITE "AE21" ;
-LOCATE COMP "ADO_TTL_44" SITE "AJ22" ;
-LOCATE COMP "ADO_TTL_45" SITE "AK22" ;
-LOCATE COMP "ADO_TTL_46" SITE "AG22" ;
-IOBUF PORT "ADO_TTL_0" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_1" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_2" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_3" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_4" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_5" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_6" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_7" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_8" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_9" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_10" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_11" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_12" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_13" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_14" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_15" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_16" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_17" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_18" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_19" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_20" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_21" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_22" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_23" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_24" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_25" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_26" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_27" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_28" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_29" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_30" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_31" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_32" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_33" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_34" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_35" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_36" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_37" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_38" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_39" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_40" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_41" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_42" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_43" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_44" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_45" IO_TYPE=LVTTL33 ;
-IOBUF PORT "ADO_TTL_46" IO_TYPE=LVTTL33 ;
-LOCATE COMP "DBAD" SITE "AM20" ;
-LOCATE COMP "DGOOD" SITE "AH20" ;
-LOCATE COMP "DINT" SITE "AJ18" ;
-LOCATE COMP "DWAIT" SITE "AH21" ;
-IOBUF PORT "DBAD" IO_TYPE=LVTTL33 ;
-IOBUF PORT "DGOOD" IO_TYPE=LVTTL33 ;
-IOBUF PORT "DINT" IO_TYPE=LVTTL33 ;
-IOBUF PORT "DWAIT" IO_TYPE=LVTTL33 ;
-#LOCATE COMP "FROM_TRB_TO_ADDON_CLK" SITE "T10" ;
-#LOCATE COMP "FROM_TRB_TO_ADDON_CLKB" SITE "T9" ;
-#LOCATE COMP "FS_PE_0" SITE "J13" ;
-#LOCATE COMP "FS_PE_1" SITE "K9" ;
-#LOCATE COMP "FS_PE_2" SITE "J12" ;
-
-LOCATE COMP "FS_PE_5" SITE "AM16" ;
-LOCATE COMP "FS_PE_6" SITE "AL16" ;
-LOCATE COMP "FS_PE_7" SITE "AM15" ;
-LOCATE COMP "FS_PE_8" SITE "AL15" ;
-LOCATE COMP "FS_PE_9" SITE "AM14" ;
-LOCATE COMP "FS_PE_10" SITE "AC16" ;
-LOCATE COMP "FS_PE_12" SITE "AK15" ;
-LOCATE COMP "FS_PE_13" SITE "AH14" ;
-LOCATE COMP "FS_PE_14" SITE "AM13" ;
-LOCATE COMP "FS_PE_15" SITE "AH12" ;
-LOCATE COMP "FS_PE_16" SITE "AK14" ;
-LOCATE COMP "FS_PE_17" SITE "AD15" ;
-
-IOBUF PORT "FS_PE_5" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_6" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_7" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_8" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_9" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_10" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_12" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_13" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_14" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_15" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_16" IO_TYPE=LVTTL33;
-IOBUF PORT "FS_PE_17" IO_TYPE=LVTTL33;
-
-LOCATE COMP "FS_PE_11" SITE "AH16" ;
-IOBUF PORT "FS_PE_11" IO_TYPE=LVTTL33 ;
-
-
-LOCATE COMP "OPLL" SITE "AL11" ;
-LOCATE COMP "IPLL" SITE "AL10" ;
-LOCATE COMP "LOK_1" SITE "AJ1" ;
-LOCATE COMP "LOK_2" SITE "AL2" ;
-LOCATE COMP "LOK_3" SITE "AK3" ;
-LOCATE COMP "LOK_4" SITE "AL4" ;
-LOCATE COMP "LOK_5" SITE "AM4" ;
-LOCATE COMP "LOK_6" SITE "AH5" ;
-LOCATE COMP "LOK_7" SITE "AG5" ;
-LOCATE COMP "LOK_8" SITE "AK5" ;
-LOCATE COMP "LOK_9" SITE "AK6" ;
-LOCATE COMP "LOK_10" SITE "AM5" ;
-LOCATE COMP "LOK_11" SITE "AM6" ;
-LOCATE COMP "LOK_12" SITE "AF8" ;
-LOCATE COMP "LOK_13" SITE "AE9" ;
-LOCATE COMP "LOK_14" SITE "AE10" ;
-LOCATE COMP "LOK_15" SITE "AF11" ;
-LOCATE COMP "LOK_16" SITE "AD12" ;
-IOBUF PORT "IPLL" IO_TYPE=LVTTL33 ;
-IOBUF PORT "OPLL" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_1" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_2" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_3" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_4" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_5" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_6" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_7" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_8" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_9" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_10" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_11" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_12" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_13" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_14" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_15" IO_TYPE=LVTTL33 ;
-IOBUF PORT "LOK_16" IO_TYPE=LVTTL33 ;
-LOCATE COMP "LVDS_CLK_200P" SITE "P3" ;
-#LOCATE COMP "LVDS_CLK_200N" SITE "P4" ;
-IOBUF PORT "LVDS_CLK_200P" IO_TYPE=LVDS ;
-#IOBUF PORT "LVDS_CLK_200N" IO_TYPE=LVDS ;
-FREQUENCY PORT "LVDS_CLK_200P" 110.000000 MHz ;
-#FREQUENCY PORT "LVDS_CLK_200N" 200.000000 MHz ;
-IOBUF PORT "LVDS_CLK_200P" DIFFRESISTOR=120 ;
-
-#LOCATE COMP "RESET" SITE "AL23" ;
-LOCATE COMP "RT_1" SITE "AK1" ;
-LOCATE COMP "RT_2" SITE "AK2" ;
-LOCATE COMP "RT_3" SITE "AJ3" ;
-LOCATE COMP "RT_4" SITE "AL3" ;
-LOCATE COMP "RT_5" SITE "AM3" ;
-LOCATE COMP "RT_6" SITE "AH4" ;
-LOCATE COMP "RT_7" SITE "AF6" ;
-LOCATE COMP "RT_8" SITE "AJ5" ;
-LOCATE COMP "RT_9" SITE "AJ6" ;
-LOCATE COMP "RT_10" SITE "AL5" ;
-LOCATE COMP "RT_11" SITE "AL6" ;
-LOCATE COMP "RT_12" SITE "AF7" ;
-LOCATE COMP "RT_13" SITE "AE8" ;
-LOCATE COMP "RT_14" SITE "AD10" ;
-LOCATE COMP "RT_15" SITE "AE11" ;
-LOCATE COMP "RT_16" SITE "AE12" ;
-IOBUF PORT "RT_1" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_2" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_3" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_4" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_5" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_6" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_7" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_8" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_9" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_10" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_11" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_12" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_13" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_14" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_15" IO_TYPE=LVTTL33 ;
-IOBUF PORT "RT_16" IO_TYPE=LVTTL33 ;
-
-
-
-
-#LOCATE COMP "GBIT_INP_N" SITE "C2" ;
-#LOCATE COMP "GBIT_INP_P" SITE "C1" ;
-#LOCATE COMP "GBIT_OUT_N" SITE "B3" ;
-#LOCATE COMP "GBIT_OUT_P" SITE "A3" ;
-
-#LOCATE COMP "GBIT_SFP_MOD_0" SITE "A19" ;
-#LOCATE COMP "GBIT_SFP_MOD_1" SITE "H18" ;
-#LOCATE COMP "GBIT_SFP_MOD_2" SITE "H17" ;
-
-#LOCATE COMP "GBIT_TX_FAULT" SITE "K15" ;
-#LOCATE COMP "S1_GBIT_SFP_MOD_0" SITE "AG17" ;
-#LOCATE COMP "S1_GBIT_TX_FAULT" SITE "AK21" ;
-#LOCATE COMP "S2_GBIT_TX_DIS" SITE "AF19" ;
-
-#LOCATE COMP "S2_GBIT_SFP_MOD_0" SITE "AC17" ;
-
-#LOCATE COMP "S2_GBIT_TX_FAULT" SITE "AM23" ;
-#LOCATE COMP "S3_GBIT_SFP_MOD_0" SITE "AM17" ;
-#LOCATE COMP "S3_GBIT_TX_FAULT" SITE "AH26" ;
-#LOCATE COMP "S3_GBIT_TX_DIS" SITE "AH25" ;
-
-#LOCATE COMP "S1_GBIT_TX_DIS" SITE "AJ21" ;
-#LOCATE COMP "S1_GBIT_SFP_MOD_1" SITE "AL18" ;
-#LOCATE COMP "S3_GBIT_SFP_MOD_1" SITE "AE17" ;
-#LOCATE COMP "S2_GBIT_SFP_MOD_1" SITE "AD17" ;
-#LOCATE COMP "S2_GBIT_SFP_MOD_2" SITE "AL17" ;
-#LOCATE COMP "S3_GBIT_SFP_MOD_2" SITE "AF17" ;
-#LOCATE COMP "S1_GBIT_SFP_MOD_2" SITE "AM18" ;
-#LOCATE COMP "SERDES_125P" SITE "C5" ;
-#LOCATE COMP "SERDES_200N" SITE "D28" ;
-#LOCATE COMP "SERDES_200P" SITE "C28" ;
-#LOCATE COMP "SERDES_200N" SITE "A_REFCLKN_L" ;
-#LOCATE COMP "SERDES_200P" SITE "A_REFCLKP_L" ;
-
-#LOCATE COMP "SERDES_125N" SITE "D5" ;
-#LOCATE COMP "SFP7_MOD_0" SITE "AE14" ;
-#LOCATE COMP "SFP2_MOD_0" SITE "J18" ;
-#LOCATE COMP "SFP1_MOD_0" SITE "F20" ;
-#LOCATE COMP "SFP4_MOD_0" SITE "D20" ;
-#LOCATE COMP "SFP3_MOD_0" SITE "G20" ;
-#LOCATE COMP "SFP8_MOD_0" SITE "AK12" ;
-#LOCATE COMP "SFP12_MOD_0" SITE "J17" ;
-#LOCATE COMP "SFP9_MOD_0" SITE "AM10" ;
-#LOCATE COMP "SFP5_MOD_0" SITE "C19" ;
-#LOCATE COMP "SFP11_MOD_0" SITE "D18" ;
-#LOCATE COMP "SFP6_MOD_0" SITE "E17" ;
-#LOCATE COMP "SFP10_MOD_0" SITE "AG14" ;
-#LOCATE COMP "SFP12_MOD_1" SITE "L20" ;
-#LOCATE COMP "SFP11_MOD_1" SITE "C18" ;
-#LOCATE COMP "SFP9_MOD_1" SITE "AM11" ;
-#LOCATE COMP "SFP6_MOD_1" SITE "B20" ;
-#LOCATE COMP "SFP8_MOD_1" SITE "AH10" ;
-#LOCATE COMP "SFP4_MOD_1" SITE "G19" ;
-#LOCATE COMP "SFP5_MOD_1" SITE "C20" ;
-#LOCATE COMP "SFP3_MOD_1" SITE "H20" ;
-#LOCATE COMP "SFP7_MOD_1" SITE "AF14" ;
-#LOCATE COMP "SFP1_MOD_1" SITE "E20" ;
-#LOCATE COMP "SFP2_MOD_1" SITE "F19" ;
-#LOCATE COMP "SFP10_MOD_1" SITE "AL12" ;
-#LOCATE COMP "SFP10_MOD_2" SITE "AL13" ;
-#LOCATE COMP "SFP5_MOD_2" SITE "E18" ;
-#LOCATE COMP "SFP4_MOD_2" SITE "H19" ;
-#LOCATE COMP "SFP9_MOD_2" SITE "AG13" ;
-#LOCATE COMP "SFP6_MOD_2" SITE "B19" ;
-#LOCATE COMP "SFP2_MOD_2" SITE "E19" ;
-#LOCATE COMP "SFP7_MOD_2" SITE "AJ12" ;
-#LOCATE COMP "SFP3_MOD_2" SITE "D19" ;
-#LOCATE COMP "SFP1_MOD_2" SITE "K18" ;
-#LOCATE COMP "SFP8_MOD_2" SITE "AH11" ;
-#LOCATE COMP "SFP12_MOD_2" SITE "A20" ;
-#LOCATE COMP "SFP11_MOD_2" SITE "K17" ;
-#IOBUF PORT "SFP7_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP2_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP1_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP4_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP3_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP8_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP12_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP9_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP5_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP11_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP6_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP10_MOD_0" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP12_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP11_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP9_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP6_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP8_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP4_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP5_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP3_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP7_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP1_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP2_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP10_MOD_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP10_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP5_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP4_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP9_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP6_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP2_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP7_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP3_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP1_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP8_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP12_MOD_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "SFP11_MOD_2" IO_TYPE=LVTTL33 ;
-
-#LOCATE COMP "GBIT_SFP_LOS" SITE "J15" ;
-#LOCATE COMP "S2_GBIT_SFP_LOS" SITE "AM22" ;
-#LOCATE COMP "S3_GBIT_SFP_LOS" SITE "AL21" ;
-#LOCATE COMP "S1_GBIT_SFP_LOS" SITE "AE19" ;
-
-
-
-LOCATE COMP "SFP_LOS_1" SITE "A18" ;
-LOCATE COMP "SFP_LOS_2" SITE "A15" ;
-LOCATE COMP "SFP_LOS_3" SITE "B15" ;
-LOCATE COMP "SFP_LOS_4" SITE "G16" ;
-LOCATE COMP "SFP_LOS_5" SITE "H16" ;
-LOCATE COMP "SFP_LOS_6" SITE "J16" ;
-LOCATE COMP "SFP_LOS_7" SITE "L13" ;
-LOCATE COMP "SFP_LOS_8" SITE "C14" ;
-LOCATE COMP "SFP_LOS_9" SITE "E15" ;
-LOCATE COMP "SFP_LOS_10" SITE "G14" ;
-LOCATE COMP "SFP_LOS_11" SITE "E14" ;
-LOCATE COMP "SFP_LOS_12" SITE "F13" ;
-LOCATE COMP "SFP_LOS_13" SITE "J15" ;
-LOCATE COMP "SFP_LOS_14" SITE "AE19" ;
-LOCATE COMP "SFP_LOS_15" SITE "AM22" ;
-LOCATE COMP "SFP_LOS_16" SITE "AL21" ;
-
-IOBUF PORT "SFP_LOS_1" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_2" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_3" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_4" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_5" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_6" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_7" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_8" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_9" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_10" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_11" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_12" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_13" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_14" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_15" IO_TYPE=LVTTL33 ;
-IOBUF PORT "SFP_LOS_16" IO_TYPE=LVTTL33 ;
-
-
-#LOCATE COMP "quad_a/PCSA_INST" SITE "PCS36000" ;
-LOCATE COMP "QUAD_GENERATE_0_QUAD/PCSA_INST" SITE "PCS36000" ;
-LOCATE COMP "QUAD_GENERATE_1_QUAD/PCSA_INST" SITE "PCS36100" ;
-LOCATE COMP "QUAD_GENERATE_2_QUAD/PCSA_INST" SITE "PCS3E100" ;
-LOCATE COMP "QUAD_GENERATE_3_QUAD/PCSA_INST" SITE "PCS3E000" ;
-#LOCATE COMP "TEST/PCSA_INST" SITE "PCS36000" ;
-FREQUENCY NET "ref_pclk_0" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_0" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_1" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_2" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_3" 100.000000MHz;
-FREQUENCY NET "ref_pclk_1" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_4" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_5" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_6" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_7" 100.000000MHz;
-FREQUENCY NET "ref_pclk_2" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_8" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_9" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_10" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_11" 100.000000MHz;
-FREQUENCY NET "ref_pclk_3" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_12" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_13" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_14" 100.000000MHz;
-FREQUENCY NET "rx_clk_i_15" 100.000000MHz;
-
-
-FREQUENCY PORT "ref_pclk_1/QUAD_GENERATE_1_QUAD" 100.000000MHz;
-FREQUENCY PORT "ref_pclk_2/QUAD_GENERATE_2_QUAD" 100.000000MHz;
-FREQUENCY PORT "ref_pclk_3/QUAD_GENERATE_3_QUAD" 100.000000MHz;
-FREQUENCY PORT "ref_pclk_0/QUAD_GENERATE_0_QUAD" 100.000000MHz;
-
-#FREQUENCY PORT "rxa_pclk_a/quad_a" 100.000000MHz;
-#FREQUENCY PORT "rx_1_sclk_a/quad_a" 100.000000MHz;
-#FREQUENCY PORT "rx_2_sclk_a/quad_a" 100.000000MHz;
-#FREQUENCY PORT "rx_3_sclk_a/quad_a" 100.000000MHz;
-#LOCATE COMP "SUPPL_RESET" SITE "B18" ;
-
-
-
-
-
-
-LOCATE COMP "TX_DIS_1" SITE "G17" ;
-LOCATE COMP "TX_DIS_2" SITE "A17" ;
-LOCATE COMP "TX_DIS_3" SITE "A16" ;
-LOCATE COMP "TX_DIS_4" SITE "B16" ;
-LOCATE COMP "TX_DIS_5" SITE "A13" ;
-LOCATE COMP "TX_DIS_6" SITE "H15" ;
-LOCATE COMP "TX_DIS_7" SITE "D15" ;
-LOCATE COMP "TX_DIS_8" SITE "B13" ;
-LOCATE COMP "TX_DIS_9" SITE "C13" ;
-LOCATE COMP "TX_DIS_10" SITE "D14" ;
-LOCATE COMP "TX_DIS_11" SITE "H14" ;
-LOCATE COMP "TX_DIS_12" SITE "G13" ;
-LOCATE COMP "TX_DIS_13" SITE "E13" ;
-LOCATE COMP "TX_DIS_14" SITE "AJ21" ;
-LOCATE COMP "TX_DIS_15" SITE "AF19" ;
-LOCATE COMP "TX_DIS_16" SITE "AH25" ;
-
-IOBUF PORT "TX_DIS_1" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_2" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_3" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_4" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_5" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_6" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_7" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_8" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_9" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_10" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_11" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_12" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_13" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_14" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_15" IO_TYPE=LVTTL33 ;
-IOBUF PORT "TX_DIS_16" IO_TYPE=LVTTL33 ;
-
-#LOCATE COMP "TX_FAULT_1" SITE "F17" ;
-#LOCATE COMP "TX_FAULT_2" SITE "L17" ;
-#LOCATE COMP "TX_FAULT_3" SITE "L16" ;
-#LOCATE COMP "TX_FAULT_4" SITE "F16" ;
-#LOCATE COMP "TX_FAULT_5" SITE "A14" ;
-#LOCATE COMP "TX_FAULT_6" SITE "K16" ;
-#LOCATE COMP "TX_FAULT_7" SITE "C15" ;
-#LOCATE COMP "TX_FAULT_8" SITE "B14" ;
-#LOCATE COMP "TX_FAULT_9" SITE "E16" ;
-#LOCATE COMP "TX_FAULT_10" SITE "D13" ;
-#LOCATE COMP "TX_FAULT_11" SITE "F14" ;
-#LOCATE COMP "TX_FAULT_12" SITE "H13" ;
-#IOBUF PORT "TX_FAULT_1" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_2" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_3" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_4" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_5" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_6" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_7" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_8" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_9" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_10" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_11" IO_TYPE=LVTTL33 ;
-#IOBUF PORT "TX_FAULT_12" IO_TYPE=LVTTL33 ;
-
-
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.all;
-use work.version.all;
-use work.trb_net_std.all;
-use work.trb_net16_hub_func.all;
-use ieee.std_logic_arith.all;
--- library sc;
--- use sc.components.all;
-entity hub is
- generic (
- HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 4
- );
- port (
- LVDS_CLK_200P : in std_logic;
- --addon connector
- ADO_TTL : inout std_logic_vector(46 downto 0);
- --diodes
- DBAD : out std_logic;
- DGOOD : out std_logic;
- DINT : out std_logic;
- DWAIT : out std_logic;
- LOK : out std_logic_vector(16 downto 1);
- RT : out std_logic_vector(16 downto 1);
- --sfp
- TX_DIS : out std_logic_vector(16 downto 1);
- IPLL : out std_logic;
- OPLL : out std_logic;
- --data to/from optical tranceivers
- SFP_INP_N : in std_logic_vector(15 downto 0);
- SFP_INP_P : in std_logic_vector(15 downto 0);
- SFP_OUT_N : out std_logic_vector(15 downto 0);
- SFP_OUT_P : out std_logic_vector(15 downto 0);
- --sfp
- SFP_LOS : in std_logic_vector(16 downto 1);
- --tempsens
- FS_PE_11 : inout std_logic;
- --etrax_interface
- FS_PE : inout std_logic_vector(9 downto 8)--sim--;
---sim-- OPT_DATA_IN : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
---sim-- OPT_DATA_OUT : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
---sim-- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
---sim-- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0)
- );
-end hub;
---add all sfp connections to measure opt. power temp. sens and if there is SFP
-
-architecture hub of hub is
-
- component serdes_fpga_ref_clk
- port(
- rxrefclk : in std_logic;
- refclk : in std_logic;
- hdinp_0 : in std_logic;
- hdinn_0 : in std_logic;
- tclk_0 : in std_logic;
- rclk_0 : in std_logic;
- tx_rst_0 : in std_logic;
- rx_rst_0 : in std_logic;
- txd_0 : in std_logic_vector(15 downto 0);
- tx_k_0 : in std_logic_vector(1 downto 0);
- tx_force_disp_0 : in std_logic_vector(1 downto 0);
- tx_disp_sel_0 : in std_logic_vector(1 downto 0);
- tx_crc_init_0 : in std_logic_vector(1 downto 0);
- word_align_en_0 : in std_logic;
- mca_align_en_0 : in std_logic;
- felb_0 : in std_logic;
- lsm_en_0 : in std_logic;
- hdinp_1 : in std_logic;
- hdinn_1 : in std_logic;
- tclk_1 : in std_logic;
- rclk_1 : in std_logic;
- tx_rst_1 : in std_logic;
- rx_rst_1 : in std_logic;
- txd_1 : in std_logic_vector(15 downto 0);
- tx_k_1 : in std_logic_vector(1 downto 0);
- tx_force_disp_1 : in std_logic_vector(1 downto 0);
- tx_disp_sel_1 : in std_logic_vector(1 downto 0);
- tx_crc_init_1 : in std_logic_vector(1 downto 0);
- word_align_en_1 : in std_logic;
- mca_align_en_1 : in std_logic;
- felb_1 : in std_logic;
- lsm_en_1 : in std_logic;
- hdinp_2 : in std_logic;
- hdinn_2 : in std_logic;
- tclk_2 : in std_logic;
- rclk_2 : in std_logic;
- tx_rst_2 : in std_logic;
- rx_rst_2 : in std_logic;
- txd_2 : in std_logic_vector(15 downto 0);
- tx_k_2 : in std_logic_vector(1 downto 0);
- tx_force_disp_2 : in std_logic_vector(1 downto 0);
- tx_disp_sel_2 : in std_logic_vector(1 downto 0);
- tx_crc_init_2 : in std_logic_vector(1 downto 0);
- word_align_en_2 : in std_logic;
- mca_align_en_2 : in std_logic;
- felb_2 : in std_logic;
- lsm_en_2 : in std_logic;
- hdinp_3 : in std_logic;
- hdinn_3 : in std_logic;
- tclk_3 : in std_logic;
- rclk_3 : in std_logic;
- tx_rst_3 : in std_logic;
- rx_rst_3 : in std_logic;
- txd_3 : in std_logic_vector(15 downto 0);
- tx_k_3 : in std_logic_vector(1 downto 0);
- tx_force_disp_3 : in std_logic_vector(1 downto 0);
- tx_disp_sel_3 : in std_logic_vector(1 downto 0);
- tx_crc_init_3 : in std_logic_vector(1 downto 0);
- word_align_en_3 : in std_logic;
- mca_align_en_3 : in std_logic;
- felb_3 : in std_logic;
- lsm_en_3 : in std_logic;
- mca_resync_01 : in std_logic;
- mca_resync_23 : in std_logic;
- quad_rst : in std_logic;
- serdes_rst : in std_logic;
- rxa_pclk : out std_logic;
- rxb_pclk : out std_logic;
- hdoutp_0 : out std_logic;
- hdoutn_0 : out std_logic;
- ref_0_sclk : out std_logic;
- rx_0_sclk : out std_logic;
- rxd_0 : out std_logic_vector(15 downto 0);
- rx_k_0 : out std_logic_vector(1 downto 0);
- rx_disp_err_detect_0 : out std_logic_vector(1 downto 0);
- rx_cv_detect_0 : out std_logic_vector(1 downto 0);
- rx_crc_eop_0 : out std_logic_vector(1 downto 0);
- lsm_status_0 : out std_logic;
- hdoutp_1 : out std_logic;
- hdoutn_1 : out std_logic;
- ref_1_sclk : out std_logic;
- rx_1_sclk : out std_logic;
- rxd_1 : out std_logic_vector(15 downto 0);
- rx_k_1 : out std_logic_vector(1 downto 0);
- rx_disp_err_detect_1 : out std_logic_vector(1 downto 0);
- rx_cv_detect_1 : out std_logic_vector(1 downto 0);
- rx_crc_eop_1 : out std_logic_vector(1 downto 0);
- lsm_status_1 : out std_logic;
- hdoutp_2 : out std_logic;
- hdoutn_2 : out std_logic;
- ref_2_sclk : out std_logic;
- rx_2_sclk : out std_logic;
- rxd_2 : out std_logic_vector(15 downto 0);
- rx_k_2 : out std_logic_vector(1 downto 0);
- rx_disp_err_detect_2 : out std_logic_vector(1 downto 0);
- rx_cv_detect_2 : out std_logic_vector(1 downto 0);
- rx_crc_eop_2 : out std_logic_vector(1 downto 0);
- lsm_status_2 : out std_logic;
- hdoutp_3 : out std_logic;
- hdoutn_3 : out std_logic;
- ref_3_sclk : out std_logic;
- rx_3_sclk : out std_logic;
- rxd_3 : out std_logic_vector(15 downto 0);
- rx_k_3 : out std_logic_vector(1 downto 0);
- rx_disp_err_detect_3 : out std_logic_vector(1 downto 0);
- rx_cv_detect_3 : out std_logic_vector(1 downto 0);
- rx_crc_eop_3 : out std_logic_vector(1 downto 0);
- lsm_status_3 : out std_logic;
- mca_aligned_01 : out std_logic;
- mca_inskew_01 : out std_logic;
- mca_outskew_01 : out std_logic;
- mca_aligned_23 : out std_logic;
- mca_inskew_23 : out std_logic;
- mca_outskew_23 : out std_logic;
- ref_pclk : out std_logic
- );
- end component;
-
- component up_down_counter
- generic (
- NUMBER_OF_BITS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic;
- DOWN_IN : in std_logic);
- end component;
-
- component flexi_PCS_synch
- generic (
- HOW_MANY_CHANNELS : positive;
- SYSTEM : positive );
- port (
- RESET : in std_logic;
- SYSTEM_CLK : in std_logic;
- TX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
- RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- TXD : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- MEDIA_STATUS : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MEDIA_CONTROL : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- MED_STAT_OP : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_CTRL_OP : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- LINK_DEBUG : out std_logic_vector(HOW_MANY_CHANNELS*32-1 downto 0)
- );
- end component;
-
- component trb_net16_hub_base is
- generic (
- --don't change
- --hub control
- HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
- HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
- HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- --media interfaces
- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 3;
- MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
- -- settings for external api connections
- INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
- INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
- INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6)
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- --Media interfacces
- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
- --INT: interfaces to connect APIs
- INT_INIT_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0);
- INT_INIT_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0);
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0);
- INT_INIT_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_INIT_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_INIT_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
- INT_INIT_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
- INT_REPLY_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0);
- INT_REPLY_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0);
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0);
- INT_REPLY_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_REPLY_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_REPLY_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
- INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
- ONEWIRE : inout std_logic;
- --Fixed status and control ports
- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
- HUB_STAT_GEN : out std_logic_vector (31 downto 0);
- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
- STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
- STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
- STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
- --Additional access to registers
- REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
- REGIO_EXT_REG_DATA_OUT: out std_logic_vector(31 downto 0);
- REGIO_EXT_REG_WRITE_IN: in std_logic;
- REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
-
- --Debugging registers
- STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
- CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
- );
- end component;
-
- component edge_to_pulse
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
- end component;
-
- component etrax_interfacev2
- generic (
- RW_SYSTEM : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DATA_BUS : in std_logic_vector(31 downto 0);
- ETRAX_DATA_BUS_B : inout std_logic_vector(16 downto 0);
- ETRAX_DATA_BUS_B_17 : in std_logic;
- ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
- ETRAX_DATA_BUS_E : inout std_logic_vector(10 downto 9);
- DATA_VALID : in std_logic;
- ETRAX_BUS_BUSY : in std_logic;
- ETRAX_IS_READY_TO_READ : out std_logic;
- TDC_TCK : out std_logic;
- TDC_TDI : out std_logic;
- TDC_TMS : out std_logic;
- TDC_TRST : out std_logic;
- TDC_TDO : in std_logic;
- TDC_RESET : out std_logic;
- EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
- EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
- EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
- EXTERNAL_ACK : out std_logic;
- EXTERNAL_VALID : in std_logic;
- EXTERNAL_MODE : out std_logic_vector(15 downto 0);
- FPGA_REGISTER_00 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_0E : out std_logic_vector(31 downto 0);
--- EXTERNAL_RESET : out std_logic;
- LVL2_VALID : in std_logic);
- end component;
-
- component simple_hub
- generic (
- HOW_MANY_CHANNELS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- DATA_IN_VALID : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- SEND_DATA : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- ENABLE_CHANNELS : in std_logic_vector(15 downto 0);
- READ_DATA : out std_logic_vector(HOW_MANY_CHANNELS -1 downto 0);
- HUB_DEBUG : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
--- constant HOW_MANY_CHANNELS : integer := 16;
- -----------------------------------------------------------------------------
- -- FLEXI_PCS
- -----------------------------------------------------------------------------
- signal ref_pclk : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0);
- signal rxd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- signal rxd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- signal rx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal rx_rst_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- signal cv_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal txd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- signal txd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
- signal tx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal rxb_pclk_a : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0);
- signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- signal link_debug_i : std_logic_vector(HOW_MANY_CHANNELS*32-1 downto 0);
- signal word_align_en : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- -----------------------------------------------------------------------------
- -- hub trb interface
- -----------------------------------------------------------------------------
- signal hub_register_00_i : std_logic_vector(31 downto 0);
- signal hub_register_01_i : std_logic_vector(31 downto 0);
- signal hub_register_02_i : std_logic_vector(31 downto 0);
- signal hub_register_03_i : std_logic_vector(31 downto 0);
- signal hub_register_04_i : std_logic_vector(31 downto 0);
- signal hub_register_05_i : std_logic_vector(31 downto 0);
- signal hub_register_06_i : std_logic_vector(31 downto 0);
- signal hub_register_07_i : std_logic_vector(31 downto 0);
- signal hub_register_08_i : std_logic_vector(31 downto 0);
- signal hub_register_09_i : std_logic_vector(31 downto 0);
- signal hub_register_0a_i : std_logic_vector(31 downto 0);
- signal hub_register_0b_i : std_logic_vector(31 downto 0);
- signal hub_register_0c_i : std_logic_vector(31 downto 0);
- signal hub_register_0d_i : std_logic_vector(31 downto 0);
- signal hub_register_0e_i : std_logic_vector(31 downto 0);
- signal hub_register_0f_i : std_logic_vector(31 downto 0);
- signal hub_register_10_i : std_logic_vector(31 downto 0);
- signal hub_register_11_i : std_logic_vector(31 downto 0);
- signal hub_register_12_i : std_logic_vector(31 downto 0);
- signal hub_register_13_i : std_logic_vector(31 downto 0);
- signal hub_register_14_i : std_logic_vector(31 downto 0);
- signal hub_register_15_i : std_logic_vector(31 downto 0);
- signal hub_register_16_i : std_logic_vector(31 downto 0);
- signal ADO_TTL_12 : std_logic;
- -----------------------------------------------------------------------------
- -- flexi_PCS to hub interface
- -----------------------------------------------------------------------------
- signal med_dataready_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_dataready_in_i_test : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- --test
- signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_dataready_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_read_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_read_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_data_out_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal med_data_out_i_test : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
-
- signal med_data_in_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal med_packet_num_out_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- signal med_error_out_i : std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
- signal med_stat_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal med_ctrl_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal hub_stat_channel_i : std_logic_vector(2**(c_MUX_WIDTH-1)*16-1 downto 0);
- signal hub_stat_gen_i : std_logic_vector(31 downto 0);
-
- -----------------------------------------------------------------------------
- -- other
- -----------------------------------------------------------------------------
- signal hub_register_0e_and_0d : std_logic_vector(15 downto 0) := x"0006";
- signal cv_counter : std_logic_vector(31 downto 0);
- signal cv_countera : std_logic_vector(31 downto 0);
- signal serdes_ref_clk : std_logic;
- signal serdes_ref_lock : std_logic;
- signal serdes_ref_clks : std_logic;
- signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*2 -1 downto 0);
- signal mplex_ctrl_i : std_logic_vector (HOW_MANY_CHANNELS*32-1 downto 0);
- signal word_counter_for_api_00 : std_logic_vector(1 downto 0);
- signal word_counter_for_api_01 : std_logic_vector(1 downto 0);
- signal global_reset_i : std_logic;
- signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0";
- signal registered_signals : std_logic_vector(7 downto 0);
- signal hub_register_0a_i_synch : std_logic_vector(7 downto 0);
- signal hub_register_0e_and_0d_synch : std_logic_vector(15 downto 0);
- signal test_signal : std_logic_vector(1 downto 0);
- signal pulse_test : std_logic;
- signal saved_lvl1_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0');
- signal saved_lvl2_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0');
- signal all_lvl1_ready : std_logic;
- signal all_lvl2_ready : std_logic;
- signal flexi_pcs_ref_clk : std_logic;
- signal lok_i : std_logic_vector(16 downto 1);
- signal not_used_lok : std_logic_vector(15 downto 0);
- signal used_channels_locked : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal channels_locked : std_logic_vector(16 downto 1);
- signal switch_rx_clk : std_logic;
- signal lock_pattern : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal all_lvl1_ready_delay1 : std_logic;
- signal all_lvl1_ready_delay2 : std_logic;
- signal all_lvl2_ready_delay1 : std_logic;
- signal all_lvl2_ready_delay2 : std_logic;
- signal media_status_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- -- etrax interface
--- signal external_address_i : std_logic_vector(31 downto 0);
--- signal external_data_out_i : std_logic_vector(31 downto 0);
--- signal external_data_in_i : std_logic_vector(31 downto 0);
--- signal external_ack_i : std_logic;
--- signal external_valid_i : std_logic;
--- signal external_mode_i : std_logic_vector(7 downto 0);
--- signal data_valid_i : std_logic;
- signal debug_register_00_i : std_logic_vector(7 downto 0);
- signal test2 : std_logic_vector(1 downto 0);
- signal med_read_counter : std_logic_vector(3 downto 0);
- -- simulation
- signal rx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal tx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal cv_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
- signal rx_clk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
- signal ref_pclk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
- constant trb_net_enable : integer := 1;
- --etrax interface
- signal external_address_i : std_logic_vector(31 downto 0);
- signal external_data_out_i : std_logic_vector(31 downto 0);
- signal external_data_in_i : std_logic_vector(31 downto 0);
- signal external_ack_i : std_logic;
- signal external_valid_i : std_logic;
- signal external_mode_i : std_logic_vector(15 downto 0);
- signal fpga_register_00_i : std_logic_vector(31 downto 0);
- signal fpga_register_01_i : std_logic_vector(31 downto 0);
- signal fpga_register_02_i : std_logic_vector(31 downto 0);
- signal fpga_register_03_i : std_logic_vector(31 downto 0);
- signal fpga_register_04_i : std_logic_vector(31 downto 0);
- signal fpga_register_05_i : std_logic_vector(31 downto 0);
- signal fpga_register_06_i : std_logic_vector(31 downto 0):=x"00000003";
- signal fpga_register_07_i : std_logic_vector(31 downto 0);
- signal fpga_register_08_i : std_logic_vector(31 downto 0);
- signal fpga_register_09_i : std_logic_vector(31 downto 0);
- signal fpga_register_0a_i : std_logic_vector(31 downto 0);
- signal fpga_register_0b_i : std_logic_vector(31 downto 0);
- signal fpga_register_0c_i : std_logic_vector(31 downto 0);
- signal fpga_register_0d_i : std_logic_vector(31 downto 0);
- signal fpga_register_0e_i : std_logic_vector(31 downto 0);
- signal free_counter : std_logic_vector(16 downto 0);
- --simple hub
- signal hub_debug_i : std_logic_vector(31 downto 0);
-
- --test
- constant OPT_TEST_MODE : integer := 0;
-
- --trbnet
- signal hub_stat_debug_i : std_logic_vector(63 downto 0);
- signal hub_ctrl_debug_i : std_logic_vector(63 downto 0);
- signal sfp_los_synch : std_logic_vector(16 downto 1);
- signal wait_counter : std_logic_vector(31 downto 0);
- signal wait_counter_up : std_logic;
-begin
-
- GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt)
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_cnt < x"e" then
- global_reset_cnt <= global_reset_cnt + 1;
- global_reset_i <= '1';
- elsif global_reset_cnt = x"e" then
- global_reset_i <= '0';
- global_reset_cnt <= x"e";
- else
- global_reset_i <= '0';
- global_reset_cnt <= global_reset_cnt;
- end if;
- end if;
- end process GLOBAL_RESET;
-
- QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate
- begin
- QUAD : serdes_fpga_ref_clk
- port map (
- rxrefclk => LVDS_CLK_200P,--flexi_pcs_ref_clk,--LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P,
- refclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P,
- hdinp_0 => SFP_INP_P(bit_index*4+0),
- hdinn_0 => SFP_INP_N(bit_index*4+0),
- tclk_0 => ref_pclk(bit_index),
- rclk_0 => rx_clk_i(0+bit_index*4),
- tx_rst_0 => '0',
- rx_rst_0 => rx_rst_i(0+bit_index*4),--hub_register_0a_i(0),
- txd_0 => txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--
- tx_k_0 => tx_k_i(1+bit_index*8 downto 0+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
- tx_force_disp_0 => "00",--hub_register_0a_i(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),
- tx_disp_sel_0 => "00",--hub_register_0a_i(5 downto 4), --"00",--hub_register_0a_i_synch(5 downto 4),--"00",
- tx_crc_init_0 => "00",
- word_align_en_0 => '1',--word_align_en(0+bit_index*4),--'1',
- mca_align_en_0 => '0',
- felb_0 => '0',
- lsm_en_0 => '0',
- hdinp_1 => SFP_INP_P(bit_index*4+1),
- hdinn_1 => SFP_INP_N(bit_index*4+1),
- tclk_1 => ref_pclk(bit_index),
- rclk_1 => rx_clk_i(1+bit_index*4),
- tx_rst_1 => '0',
- rx_rst_1 => rx_rst_i(1+bit_index*4),
- txd_1 => txd_synch_i(31+bit_index*64 downto 16+bit_index*64),
- tx_k_1 => tx_k_i(3+bit_index*8 downto 2+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
- tx_force_disp_1 => "00",--tx_k_i(3+bit_index*8 downto 2+bit_index*8),
- tx_disp_sel_1 => "00",
- tx_crc_init_1 => "00",
- word_align_en_1 => '1',--word_align_en(1+bit_index*4),--'1',--
- mca_align_en_1 => '0',
- felb_1 => '0',
- lsm_en_1 => '0',
- hdinp_2 => SFP_INP_P(bit_index*4+2),
- hdinn_2 => SFP_INP_N(bit_index*4+2),
- tclk_2 => ref_pclk(bit_index),
- rclk_2 => rx_clk_i(2+bit_index*4),
- tx_rst_2 => '0',
- rx_rst_2 => rx_rst_i(2+bit_index*4),
- txd_2 => txd_synch_i(47+bit_index*64 downto 32+bit_index*64),
- tx_k_2 => tx_k_i(5+bit_index*8 downto 4+bit_index*8),--"10",
- tx_force_disp_2 => "00",--
- tx_disp_sel_2 => "00",
- tx_crc_init_2 => "00",
- word_align_en_2 => '1',--word_align_en(2+bit_index*4),--'1',
- mca_align_en_2 => '0',
- felb_2 => '0',
- lsm_en_2 => '0',
- hdinp_3 => SFP_INP_P(bit_index*4+3),
- hdinn_3 => SFP_INP_N(bit_index*4+3),
- tclk_3 => ref_pclk(bit_index),
- rclk_3 => rx_clk_i(3+bit_index*4),
- tx_rst_3 => '0',
- rx_rst_3 => rx_rst_i(3+bit_index*4),
- txd_3 => txd_synch_i(63+bit_index*64 downto 48+bit_index*64),
- tx_k_3 => tx_k_i(7+bit_index*8 downto 6+bit_index*8),--"10",
- tx_force_disp_3 => "00",
- tx_disp_sel_3 => "00",
- tx_crc_init_3 => "00",
- word_align_en_3 => '1',--word_align_en(3+bit_index*4),--'1',
- mca_align_en_3 => '0',
- felb_3 => '0',
- lsm_en_3 => '0',
- mca_resync_01 => '0',
- mca_resync_23 => '0',
- quad_rst => '0',
- serdes_rst => '0',
- rxa_pclk => rx_clk_i(0+bit_index*4),
- rxb_pclk => rxb_pclk_a(bit_index),
- hdoutp_0 => SFP_OUT_P(bit_index*4+0),
- hdoutn_0 => SFP_OUT_N(bit_index*4+0),
- ref_0_sclk => open,
- rx_0_sclk => open,
- rxd_0 => rxd_i(15+bit_index*64 downto 0+bit_index*64),
- rx_k_0 => rx_k_i(1+bit_index*8 downto 0+bit_index*8),
- rx_disp_err_detect_0 => open, --rx_disp_err_detect_0_a,
- rx_cv_detect_0 => cv_i(1+bit_index*8 downto 0+bit_index*8),
- rx_crc_eop_0 => open,
- lsm_status_0 => open,
- hdoutp_1 => SFP_OUT_P(bit_index*4+1),
- hdoutn_1 => SFP_OUT_N(bit_index*4+1),
- ref_1_sclk => open,
- rx_1_sclk => rx_clk_i(1+bit_index*4),
- rxd_1 => rxd_i(31+bit_index*64 downto 16+bit_index*64),
- rx_k_1 => rx_k_i(3+bit_index*8 downto 2+bit_index*8),
- rx_disp_err_detect_1 => open, --rx_disp_err_detect_1_a,
- rx_cv_detect_1 => cv_i(3+bit_index*8 downto 2+bit_index*8),
- rx_crc_eop_1 => open,
- lsm_status_1 => open,
- hdoutp_2 => SFP_OUT_P(bit_index*4+2),
- hdoutn_2 => SFP_OUT_N(bit_index*4+2),
- ref_2_sclk => open,
- rx_2_sclk => rx_clk_i(2+bit_index*4),
- rxd_2 => rxd_i(47+bit_index*64 downto 32+bit_index*64),
- rx_k_2 => rx_k_i(5+bit_index*8 downto 4+bit_index*8),
- rx_disp_err_detect_2 => open, --rx_disp_err_detect_2_a,
- rx_cv_detect_2 => cv_i(5+bit_index*8 downto 4+bit_index*8),
- rx_crc_eop_2 => open,
- lsm_status_2 => open,
- hdoutp_3 => SFP_OUT_P(bit_index*4+3),
- hdoutn_3 => SFP_OUT_N(bit_index*4+3),
- ref_3_sclk => open,
- rx_3_sclk => rx_clk_i(3+bit_index*4),
- rxd_3 => rxd_i(63+bit_index*64 downto 48+bit_index*64),
- rx_k_3 => rx_k_i(7+bit_index*8 downto 6+bit_index*8),
- rx_disp_err_detect_3 => open, --rx_disp_err_detect_3_a,
- rx_cv_detect_3 => cv_i(7+bit_index*8 downto 6+bit_index*8),
- rx_crc_eop_3 => open,
- lsm_status_3 => open,
- mca_aligned_01 => open, --mca_aligned_01_i,
- mca_inskew_01 => open, --mca_inskew_01_i,
- mca_outskew_01 => open, --mca_outskew_01_i,
- mca_aligned_23 => open, --mca_aligned_23_i,
- mca_inskew_23 => open, --mca_inskew_23_i,
- mca_outskew_23 => open, --mca_outskew_23_i,
- ref_pclk => ref_pclk(bit_index)
- );
- end generate QUAD_GENERATE;
- -- word_align_en <= not rx_rst_i;
---sim-- SIMULATION_CONNECTION: for i in 0 to HOW_MANY_CHANNELS-1 generate
---sim-- rx_k_sim(i*2) <= not OPT_DATA_VALID_IN(i);
---sim-- rx_k_sim(i*2+1) <= '0';
---sim-- OPT_DATA_VALID_OUT(i) <= not tx_k_sim(i*2);
---sim-- rx_clk_sim <= (others => LVDS_CLK_200P);
---sim-- ref_pclk_sim <= (others => LVDS_CLK_200P);
---sim-- cv_sim <= (others => '0');
---sim-- end generate SIMULATION_CONNECTION;
- FLEXI_PCS_INT : flexi_PCS_synch
- generic map (
- HOW_MANY_CHANNELS => HOW_MANY_CHANNELS,
- SYSTEM => 1)
- port map (
- RESET => global_reset_i,
- SYSTEM_CLK => LVDS_CLK_200P,
- TX_CLK => ref_pclk, --no_sim--
---sim-- TX_CLK => ref_pclk_sim,
- RX_CLK => rx_clk_i, --no_sim--
---sim-- RX_CLK => rx_clk_sim,
- RXD => rxd_i, --no_sim--
---sim-- RXD => OPT_DATA_IN,
- RX_K => rx_k_i, --no_sim--
---sim-- RX_K => rx_k_sim,
- RX_RST => rx_rst_i,
- CV => cv_i, --no_sim--
---sim-- CV => cv_sim,
- TXD => txd_synch_i, --no_sim--
---sim-- TXD => OPT_DATA_OUT,
- TX_K => tx_k_i, --no_sim--
---sim-- TX_K => tx_k_sim,
- MEDIA_STATUS => media_status_i,
- MEDIA_CONTROL => open,
- MED_DATAREADY_IN => med_dataready_in_i,
- MED_DATA_IN => med_data_in_i,
- MED_READ_OUT => med_read_out_i,
- MED_DATA_OUT => med_data_out_i,
- MED_DATAREADY_OUT => med_dataready_out_i,
- MED_READ_IN => med_read_in_i,
- MED_PACKET_NUM_IN => med_packet_num_in_i,
- MED_PACKET_NUM_OUT => med_packet_num_out_i,
- MED_STAT_OP => med_stat_op_i,
- MED_CTRL_OP => med_ctrl_op_i,
- LINK_DEBUG => link_debug_i
- );
-
- ADO_TTL(15 downto 0) <= link_debug_i(7 downto 4) & med_dataready_out_i(0) & med_packet_num_out_i(2 downto 0) & med_data_out_i(7 downto 0);--link_debug_i(15 downto 0);
- ADO_TTL(34 downto 19) <= link_debug_i(23 downto 22) & LVDS_CLK_200P & med_read_out_i(0) & med_dataready_in_i(0) & med_packet_num_in_i(2 downto 0) & med_data_in_i(7 downto 0);--link_debug_i(31 downto 16);
-
-
- SIMPLE_HUB_GEN : if trb_net_enable = 0 and OPT_TEST_MODE = 0 generate
-
- SIMPLE_HUB_INST : simple_hub
- generic map (
- HOW_MANY_CHANNELS => HOW_MANY_CHANNELS)
- port map (
- CLK => LVDS_CLK_200P,
- RESET => global_reset_i,
- DATA_IN => med_data_out_i,
--- DATA_IN => med_data_out_i_test,
- DATA_OUT => med_data_in_i,
- DATA_IN_VALID => med_dataready_out_i,
- SEND_DATA => med_dataready_in_i,
--- SEND_DATA => med_dataready_in_i_test,
- ENABLE_CHANNELS => fpga_register_06_i(15 downto 0),
- READ_DATA => med_read_in_i,
- HUB_DEBUG => hub_debug_i
- );
-
- end generate SIMPLE_HUB_GEN;
-
- FREE_COUNTER_INST: up_down_counter
- generic map (
- NUMBER_OF_BITS => 17)
- port map (
- CLK => LVDS_CLK_200P,
- RESET => '0',
- COUNT_OUT => free_counter,
- UP_IN => '1',
- DOWN_IN => '0');
-
- WAIT_COUNTER_INST: up_down_counter
- generic map (
- NUMBER_OF_BITS => 32)
- port map (
- CLK => LVDS_CLK_200P,
- RESET => '0',
- COUNT_OUT => wait_counter,
- UP_IN => wait_counter_up,
- DOWN_IN => '0');
-
- wait_counter_up <= '1' when wait_counter(31) = '0' else '0';
-
- ENABLE_OPT_TEST : if OPT_TEST_MODE = 1 generate
-
- SEND_COUNTER: process (LVDS_CLK_200P, global_reset_i)
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' then
- med_dataready_in_i <= (others => '0');
- med_data_in_i <= (others => '0');
--- elsif med_stat_op_i(9)='1' or med_stat_op_i(24)='1' or med_stat_op_i(40)='1' or med_stat_op_i(56)='1' then
- -- elsif link_debug_i(3 downto 0) = x"a" and link_debug_i(35 downto 32) > 10 then
- elsif wait_counter(31) = '1' then
-
- med_dataready_in_i <= free_counter(16) & free_counter(16) &free_counter(16) &free_counter(16);
- med_data_in_i <= free_counter(15 downto 0) & free_counter(15 downto 0) & free_counter(15 downto 0) & free_counter(15 downto 0);
- else
- med_dataready_in_i <= (others => '0');
- med_data_in_i <= (others => '0');
- end if;
- end if;
- end process SEND_COUNTER;
- med_read_in_i <= (others => '1');
--- med_data_in_i <= med_data_out_i;
--- med_dataready_in_i <= med_dataready_out_i;
- end generate ENABLE_OPT_TEST;
-
- ENABLE_TRB_NET: if trb_net_enable = 1 generate
-
- HUB_API: trb_net16_hub_base
- generic map(
- MII_NUMBER => HOW_MANY_CHANNELS
- )
- port map (
- CLK => LVDS_CLK_200P,
- RESET => global_reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_in_i,
- MED_DATA_OUT => med_data_in_i,
- MED_PACKET_NUM_OUT => med_packet_num_in_i,
- MED_READ_IN => med_read_out_i,
- MED_DATAREADY_IN => med_dataready_out_i,
- MED_DATA_IN => med_data_out_i,
- MED_PACKET_NUM_IN => med_packet_num_out_i,
- MED_READ_OUT => med_read_in_i,
- MED_STAT_OP => med_stat_op_i,
- MED_CTRL_OP => med_ctrl_op_i,
- INT_INIT_DATAREADY_OUT => open,
- INT_INIT_DATA_OUT => open,
- INT_INIT_PACKET_NUM_OUT => open,
- INT_INIT_READ_IN => (others => '1'),
- INT_INIT_DATAREADY_IN => (others => '0'),
- INT_INIT_DATA_IN => (others => '0'),
- INT_INIT_PACKET_NUM_IN => (others => '0'),
- INT_INIT_READ_OUT => open,
- INT_REPLY_DATAREADY_OUT => open,
- INT_REPLY_DATA_OUT => open,
- INT_REPLY_PACKET_NUM_OUT => open,
- INT_REPLY_READ_IN => (others => '1'),
- INT_REPLY_DATAREADY_IN => (others => '0'),
- INT_REPLY_DATA_IN => (others => '0'),
- INT_REPLY_PACKET_NUM_IN => (others => '0'),
- INT_REPLY_READ_OUT => open,
- ONEWIRE => FS_PE_11,
- HUB_STAT_CHANNEL => hub_stat_channel_i,
- HUB_STAT_GEN => hub_stat_gen_i,
- MPLEX_CTRL => mplex_ctrl_i,
- MPLEX_STAT => open,
- REGIO_EXT_REG_DATA_IN => (others => '0'),
- REGIO_EXT_REG_DATA_OUT => open,
- REGIO_EXT_REG_WRITE_IN => '0',
- REGIO_EXT_REG_ADDR_IN => (others => '0'),
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-
- end generate ENABLE_TRB_NET;
-
- ETRAX_RW_DATA_INTERFACE : etrax_interfacev2
- generic map (
- RW_SYSTEM => 2)
- port map (
- CLK => LVDS_CLK_200P,
- RESET => global_reset_i,
- DATA_BUS => (others => '0'),
- ETRAX_DATA_BUS_B => open,--(others => '0'),
- ETRAX_DATA_BUS_B_17 => '0',
- ETRAX_DATA_BUS_C => open,--(others => '0'),
- ETRAX_DATA_BUS_E => FS_PE(9 downto 8),
- DATA_VALID => '0',
- ETRAX_BUS_BUSY => '0',
- ETRAX_IS_READY_TO_READ => open,
- TDC_TCK => open,
- TDC_TDI => open,
- TDC_TMS => open,
- TDC_TRST => open,
- TDC_TDO => '0',
- TDC_RESET => open,
- EXTERNAL_ADDRESS => open,
- EXTERNAL_DATA_OUT => open,
- EXTERNAL_DATA_IN => x"ddbbccaa",--external_data_in_i,
- EXTERNAL_ACK => external_ack_i,
- EXTERNAL_VALID => '0',--external_valid_i,
- EXTERNAL_MODE => external_mode_i,
- FPGA_REGISTER_00 => fpga_register_00_i,
- FPGA_REGISTER_01 => fpga_register_01_i,
- FPGA_REGISTER_02 => fpga_register_02_i,
- FPGA_REGISTER_03 => fpga_register_03_i,
- FPGA_REGISTER_04 => fpga_register_04_i,
- FPGA_REGISTER_05 => fpga_register_05_i,
- FPGA_REGISTER_06 => fpga_register_06_i,
- FPGA_REGISTER_07 => fpga_register_07_i,
- FPGA_REGISTER_08 => fpga_register_08_i,
- FPGA_REGISTER_09 => fpga_register_09_i,
- FPGA_REGISTER_0A => fpga_register_0A_i,
- FPGA_REGISTER_0B => fpga_register_0B_i,
- FPGA_REGISTER_0C => fpga_register_0C_i,
- FPGA_REGISTER_0D => fpga_register_0D_i,
- FPGA_REGISTER_0E => fpga_register_0E_i,
- -- EXTERNAL_RESET => open,
- LVL2_VALID => '0');
- fpga_register_00_i <= x"0000"& lok_i;
- fpga_register_01_i <= hub_debug_i;
- fpga_register_02_i <= link_debug_i(31 downto 0);
- fpga_register_03_i <= link_debug_i(63 downto 32);
- fpga_register_04_i <= rxd_i(31 downto 0);
- fpga_register_0A_i <= rxd_i(63 downto 32);
--- fpga_register_02_i <= link_debug_i(95 downto 64);
--- fpga_register_03_i <= link_debug_i(127 downto 96);
--- fpga_register_04_i <= rxd_i(95 downto 64);
--- fpga_register_0A_i <= rxd_i(127 downto 96);
- fpga_register_0B_i <= conv_std_logic_vector(VERSION_NUMBER_TIME,32);
- fpga_register_0C_i <= link_debug_i(95 downto 64);
- fpga_register_0D_i <= link_debug_i(127 downto 96);
--- -- fpga_register_08_i <= rxd_i(63 downto 32);
--- fpga_register_0a_i(15 downto 0) <= cv_i(7 downto 0) & rx_k_i(3 downto 0) & "0000";
-
-
-
- COUNT_LVL1_START: process (LVDS_CLK_200P, global_reset_i )
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' then
- fpga_register_05_i <= (others => '0');
- elsif med_dataready_out_i(0) = '1' and med_data_out_i(15 downto 12) = x"1" then
- fpga_register_05_i <= fpga_register_05_i + 1;
- end if;
- end if;
- end process COUNT_LVL1_START;
-
--- COUNT_LVL1_SEND: process (LVDS_CLK_200P, global_reset_i )
--- begin
--- if rising_edge(LVDS_CLK_200P) then
--- if global_reset_i = '1' then
--- fpga_register_08_i <= (others => '0');
--- elsif med_data_ready_in_i(1) = '1' and med_data_in_i(31 downto 28) = x"1" then
--- fpga_register_08_i <= fpga_register_08_i + 1;
--- end if;
--- end if;
--- end process COUNT_LVL1_SEND;
-
- COUNT_LVL1_SEND_a: process (LVDS_CLK_200P, global_reset_i )
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' then
- fpga_register_09_i <= (others => '0');
- elsif med_dataready_in_i(1) = '1' then
- fpga_register_09_i <= fpga_register_08_i + 1;
- end if;
- end if;
- end process COUNT_LVL1_SEND_a;
-
- COUNT_LVL1_END: process (LVDS_CLK_200P, global_reset_i )
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' then
- fpga_register_07_i <= (others => '0');
- elsif med_dataready_out_i(1) = '1' and med_data_out_i(31 downto 28) = x"1" then
- fpga_register_07_i <= fpga_register_07_i + 1;
- end if;
- end if;
- end process COUNT_LVL1_END;
-
- TX_DIS_g : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
- begin
- TX_DIS(synch_fsm_state+1) <= '0';
- end generate;
-
- TX_DIS_g1 : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
- begin
- WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
- TX_DIS(16-not_connected) <= '1';
- end generate WHEN_NOT_ALL_EN;
- end generate;
-
----------------------------------------------------------------------------
--- setting LED
----------------------------------------------------------------------------
-
- --correct this for channels 11-8 - mirrored due to schematics -- also
- --adressing of sfps !!!
- SYNCH_EXT_SIGNAL: process (LVDS_CLK_200P)
- begin
- if rising_edge(LVDS_CLK_200P) then
- if global_reset_i = '1' then
- sfp_los_synch <= (others => '0');
- else
- sfp_los_synch <= SFP_LOS;
- end if;
- end if;
- end process SYNCH_EXT_SIGNAL;
- LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
- begin
- -- lok_i(synch_fsm_state+1) <= not link_debug_i(2+synch_fsm_state*31);
- lok_i(synch_fsm_state+1) <= med_stat_op_i(9 + synch_fsm_state*16);
- media_status_i(synch_fsm_state*16) <= SFP_LOS(synch_fsm_state+1);
- end generate LOK_STATUS_DIOD_EN;
-
--- LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate
--- begin
--- hub_register_00_i(synch_fsm_state) <= link_debug_i(2+synch_fsm_state*31);
--- end generate LOK_STATUS_REGISTER_0;
-
--- LOK_STATUS_REGISTER_1 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 - 8) generate
--- begin
--- hub_register_01_i(synch_fsm_state) <= link_debug_i(2+synch_fsm_state*31+8*16);
--- end generate LOK_STATUS_REGISTER_1;
-
- LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
- begin
- WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
- lok_i(16-not_connected) <= '1';
- end generate WHEN_NOT_ALL_EN;
- end generate LOK_STATUS_DIOD_DIS;
-
- LOK <= lok_i;
- IPLL <= '0';
- OPLL <= '0';
- DBAD <= '1';
- DGOOD <= '1';
- DINT <= '0';
- DWAIT <= global_reset_i;
-
- CV_COUNTERaaa: process (LVDS_CLK_200P, global_reset_i)
- begin
- if rising_edge(LVDS_CLK_200P) then -- rising clock edge
- if global_reset_i = '1' then -- asynchronous reset (active low)
- cv_counter <= (others => '0');
- else
- cv_counter <= cv_counter + 1;
- end if;
- end if;
- end process CV_COUNTERaaa;
- CV_COUNTERaab: process (ref_pclk(0), global_reset_i)
- begin
- if rising_edge(ref_pclk(0)) then -- rising clock edge
- if global_reset_i = '1' then -- asynchronous reset (active low)
- cv_countera <= (others => '0');
- else
- cv_countera <= cv_countera + 1;
- end if;
- end if;
- end process CV_COUNTERaab;
--- RT(8) <= cv_counter(23);
--- RT(9) <= med_read_in_i(0);
--- RT(16 downto 10) <= link_debug_i(7 downto 1);
--- RT(2) <= flexi_pcs_ref_clk;--cv_counter(0);
--- RT(1) <= not switch_rx_clk;--ref_pclk(0);
-
--- RT(3) <= LVDS_CLK_200P;
-
--- RT(4) <= rx_k_i(0);
-
--- RT(5) <= med_dataready_out_i(0);--serdes_ref_clk;
--- RT(6) <= med_data_out_i(0);--serdes_ref_clks;
--- RT(7) <= med_data_out_i(1);--serdes_ref_lock;
- RT <= (others => '1');
-end hub;
-
+++ /dev/null
-<?xml version='1.0' encoding='utf-8' ?>
-<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
-<ispXCF version="17.0 Linux Beta">
- <Comment></Comment>
- <Chain>
- <Comm>JTAG</Comm>
- <Device>
- <Pos>1</Pos>
- <Vendor>NA</Vendor>
- <Family>Generic JTAG Device</Family>
- <Name>JTAG-NOP</Name>
- <Package>All</Package>
- <PON>JTAG-NOP</PON>
- <Bypass>
- <InstrLen>10</InstrLen>
- <InstrVal>1111111111</InstrVal>
- <BScanLen>1</BScanLen>
- <BScanVal>0</BScanVal>
- </Bypass>
- <Operation>Bypass</Operation>
- <Option>
- <SVFVendor>JTAG STANDARD</SVFVendor>
- <IOState>HighZ</IOState>
- <OverideUES value="TRUE"/>
- <TCKFrequency>1.000000 MHz</TCKFrequency>
- <SVFProcessor>SVF Processor</SVFProcessor>
- </Option>
- </Device>
- <Device>
- <Pos>2</Pos>
- <Ref>hub</Ref>
- <Vendor>Lattice</Vendor>
- <Family>LatticeSCM</Family>
- <Name>LFSCM3GA25E</Name>
- <IDCode>0x0a812157</IDCode>
- <Package>1020-ball FFBGA</Package>
- <PON>LFSCM3GA25EP1-XXFF1020</PON>
- <Bypass>
- <InstrLen>8</InstrLen>
- <InstrVal>11111111</InstrVal>
- <BScanLen>1</BScanLen>
- <BScanVal>0</BScanVal>
- </Bypass>
- <File>/home/marek/trbnet/optical_link/workdir/hub.bit</File>
- <MaskFile>/home/marek/.isplever_lin1/ispvmsystem/Database/xpga/sc/lfsc3ga25e.msk</MaskFile>
- <FileTime>3/31/2009 22:28:11</FileTime>
- <Operation>Fast Program</Operation>
- <Option>
- <SVFVendor>JTAG STANDARD</SVFVendor>
- <IOState>HighZ</IOState>
- <PreloadLength>1095</PreloadLength>
- <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
- <OverideUES value="TRUE"/>
- <TCKFrequency>1.000000 MHz</TCKFrequency>
- <SVFProcessor>SVF Processor</SVFProcessor>
- <AccessMode>JTAG</AccessMode>
- </Option>
- </Device>
- <Device>
- <Pos>3</Pos>
- <Ref>power</Ref>
- <Vendor>NA</Vendor>
- <Family>Generic JTAG Device</Family>
- <Name>JTAG-NOP</Name>
- <Package>All</Package>
- <PON>JTAG-NOP</PON>
- <Bypass>
- <InstrLen>4</InstrLen>
- <InstrVal>1111</InstrVal>
- <BScanLen>1</BScanLen>
- <BScanVal>0</BScanVal>
- </Bypass>
- <Operation>Bypass</Operation>
- <Option>
- <SVFVendor>JTAG STANDARD</SVFVendor>
- <IOState>HighZ</IOState>
- <OverideUES value="TRUE"/>
- <TCKFrequency>1.000000 MHz</TCKFrequency>
- <SVFProcessor>SVF Processor</SVFProcessor>
- </Option>
- </Device>
- </Chain>
- <ProjectOptions>
- <Program>SEQUENTIAL</Program>
- <Process>ENTIRED CHAIN</Process>
- <OperationOverride>No Override</OperationOverride>
- <StartTAP>TLR</StartTAP>
- <EndTAP>TLR</EndTAP>
- <DeGlitch value="TRUE"/>
- <VerifyUsercode value="TRUE"/>
- <PinSetting>
- TMS LOW;
- TCK LOW;
- TDI LOW;
- TDO LOW;
- CableEN HIGH;
- </PinSetting>
- </ProjectOptions>
-</ispXCF>
+++ /dev/null
-#-- Synopsys, Inc.
-#-- Version 9.6L2
-#-- Project file /home/marek/trbnet/optical_link/hub_syn.prj
-#-- Written on Thu Apr 2 10:51:38 2009
-
-
-#add_file options
-add_file -vhdl -lib work "./version.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_hub_func.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/lattice_scm_fifo_18x1k.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/lattice_scm_fifo_18x16.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/lattice_scm_fifo_18x32.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/lattice_scm_fifo_18x64.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "./simple_hub.vhd"
-add_file -vhdl -lib work "./cross_clk.vhd"
-add_file -vhdl -lib work "/home/marek/trbv2/etrax_interfacev2.vhd"
-add_file -vhdl -lib work "./simpleupcounter_32bit.vhd"
-add_file -vhdl -lib work "./hub_etrax_interface.vhd"
-add_file -vhdl -lib work "./hub.vhd"
-add_file -vhdl -lib work "./f_divider.vhd"
-add_file -vhdl -lib work "./simpleupcounter_16bit.vhd"
-add_file -vhdl -lib work "./simpleupcounter_8bit.vhd"
-add_file -vhdl -lib work "./flexi_PCS_synch.vhd"
-add_file -vhdl -lib work "./flexi_PCS_channel_synch.vhd"
-add_file -vhdl -lib work "./flexi_PCS_fifo_LUT.vhd"
-add_file -vhdl -lib work "./flexi_PCS_fifo_EBR.vhd"
-add_file -vhdl -lib work "./serdes_fpga_ref_clk.vhd"
-add_file -vhdl -lib work "./pll_ref.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_hub_base.vhd"
-add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_hub_logic.vhd"
-add_file -vhdl -lib work "../basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "../basics/ram_dp.vhd"
-add_file -vhdl -lib work "../basics/ram_true_dp.vhd"
-add_file -vhdl -lib work "../basics/ram.vhd"
-add_file -vhdl -lib work "../basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../basics/rom_16x16.vhd"
-add_file -vhdl -lib work "../basics/rom_18x128.vhd"
-add_file -vhdl -lib work "../basics/signal_sync.vhd"
-add_file -vhdl -lib work "../basics/wide_adder_17x16.vhd"
-add_file -vhdl -lib work "../basics/wide_adder.vhd"
-add_file -vhdl -lib work "../trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../../trbv2/up_down_counter.vhd"
-add_file -vhdl -lib work "../trb_net16_hub_ipu_logic.vhd"
-
-
-#implementation: "workdir"
-impl -add workdir -type fpga
-
-#device options
-set_option -technology LATTICE-SCM
-set_option -part LFSCM3GA25EP1
-set_option -package FF1020C
-set_option -speed_grade -5
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -default_enum_encoding onehot
-set_option -resource_sharing 1
-set_option -top_module "hub"
-
-#map options
-set_option -frequency 110.000
-set_option -vendor_xcompatible_mode 0
-set_option -vendor_xcompatible_mode 0
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-set_option -fixgatedclocks 0
-set_option -fixgeneratedclocks 3
-set_option -force_gsr no
-
-
-#sequential_optimizations options
-set_option -symbolic_fsm_compiler 1
-
-#simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 0
-
-#set result format/file last
-project -result_file "./workdir/hub.edf"
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -synthesis_onoff_pragma 0
-set_option -project_relative_includes 1
-impl -active "workdir"
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library ieee;
-library work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.all;
-
-entity hub_tb is
-
- port (
- LVDS_CLK_200P : in std_logic;
- LVDS_CLK_200N : in std_logic;
- SERDES_200N : in std_logic;
- SERDES_200P : in std_logic;
- ADO_TTL : inout std_logic_vector(46 downto 0);
- DBAD : out std_logic;
- DGOOD : out std_logic;
- DINT : out std_logic;
- DWAIT : out std_logic;
- LOK : out std_logic_vector(16 downto 1);
- RT : out std_logic_vector(16 downto 1);
- TX_DIS : out std_logic_vector(16 downto 1);
- IPLL : out std_logic;
- OPLL : out std_logic;
- SFP_INP_N : in std_logic_vector(15 downto 0);
- SFP_INP_P : in std_logic_vector(15 downto 0);
- SFP_OUT_N : out std_logic_vector(15 downto 0);
- SFP_OUT_P : out std_logic_vector(15 downto 0);
- AAAAAAAA : in std_logic);
-end hub_tb;
-
-architecture hub_tb of hub_tb is
-
-signal LVDS_CLK_200P_i : std_logic;
-signal LVDS_CLK_200N_i : std_logic;
-signal SERDES_200N_i : std_logic;
-signal SERDES_200P_i : std_logic;
-signal ADO_TTL_i : std_logic_vector(46 downto 0);
-signal DBAD_i : std_logic;
-signal DGOOD_i : std_logic;
-signal DINT_i : std_logic;
-signal DWAIT_i : std_logic;
-signal LOK_i : std_logic_vector(16 downto 1);
-signal RT_i : std_logic_vector(16 downto 1);
-signal TX_DIS_i : std_logic_vector(16 downto 1);
-signal IPLL_i : std_logic;
-signal OPLL_i : std_logic;
-signal SFP_INP_N_i : std_logic_vector(15 downto 0);
-signal SFP_INP_P_i : std_logic_vector(15 downto 0);
-signal SFP_OUT_N_i : std_logic_vector(15 downto 0);
-signal SFP_OUT_P_i : std_logic_vector(15 downto 0);
-
-component hub
- port (
- LVDS_CLK_200P : in std_logic;
--- LVDS_CLK_200N : in std_logic;
--- SERDES_200N : in std_logic;
--- SERDES_200P : in std_logic;
- ADO_TTL : inout std_logic_vector(46 downto 0);
- DBAD : out std_logic;
- DGOOD : out std_logic;
- DINT : out std_logic;
- DWAIT : out std_logic;
- LOK : out std_logic_vector(16 downto 1);
- RT : out std_logic_vector(16 downto 1);
- TX_DIS : out std_logic_vector(16 downto 1);
- IPLL : out std_logic;
- OPLL : out std_logic;
- SFP_INP_N : in std_logic_vector(15 downto 0);
- SFP_INP_P : in std_logic_vector(15 downto 0);
- SFP_OUT_N : out std_logic_vector(15 downto 0);
- SFP_OUT_P : out std_logic_vector(15 downto 0);
- FS_PE_11 : inout std_logic;
- ---------------------------------------------------------------------------
- -- sim
- ---------------------------------------------------------------------------
- OPT_DATA_IN : in std_logic_vector(16*HOW_MANY_CHANNELS-1 downto 0);
- OPT_DATA_OUT : out std_logic_vector(16*HOW_MANY_CHANNELS-1 downto 0);
- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0)
-
-
- );
-end component;
-
-
-begin -- of hub_tb
- HUB_SIM: hub
- port map (
- LVDS_CLK_200P => LVDS_CLK_200P_i,
- ADO_TTL => ADO_TTL_i,
- DBAD => DBAD_i,
- DGOOD => DGOOD_i,
- DINT => DINT_i,
- DWAIT => DWAIT_i,
- LOK => LOK_i,
- RT => RT_i,
- TX_DIS => TX_DIS_i,
- IPLL => IPLL_i,
- OPLL => OPLL_i,
- SFP_INP_N => SFP_INP_N_i,
- SFP_INP_P => SFP_INP_P_i,
- SFP_OUT_N => SFP_OUT_N_i,
- SFP_OUT_P => SFP_OUT_P_i
- FS_PE_11 =>
- OPT_DATA_IN =>
- OPT_DATA_OUT =>
- OPT_DATA_VALID_IN =>
- OPT_DATA_VALID_OUT =>
-
- clock_gclk : process
- begin
- SERDES_200P_i <= '0';
- SERDES_200N_i <= '1';
- wait for 5 ns;
- SERDES_200P_i <= '1';
- SERDES_200N_i <= '0';
- wait for 5 ns;
- end process;
-end hub_tb;
+++ /dev/null
-setMode -bs
-setCable -port stapl -file "hub_chain.stapl"
-addDevice -p 1 -file "hub_1.svf"
-Play
-quit
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
--- Module Version: 3.6
---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n pll_ref -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 100 -mfreq 200 -nfreq 100 -clkos_fdel 0 -fb 1 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e
-
--- Thu Nov 29 18:28:19 2007
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library SCM;
-use SCM.COMPONENTS.all;
--- synopsys translate_on
-
-entity pll_ref is
- generic (
- SMI_OFFSET : in String := "0x410"
- );
- port (
- clk: in std_logic;
- clkop: out std_logic;
- clkos: out std_logic;
- lock: out std_logic);
- attribute dont_touch : string;
- attribute dont_touch of pll_ref : entity is "true";
-end pll_ref;
-
-architecture Structure of pll_ref is
-
- -- internal signal declarations
- signal scuba_vlo: std_logic;
- signal scuba_vhi: std_logic;
- signal clkos_t: std_logic;
- signal clkop_t: std_logic;
- signal clk_t: std_logic;
-
- attribute module_type : string;
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component EHXPLLA
- generic (SMI_OFFSET : in String
- -- synopsys translate_off
- ; GSR : in String; CLKOS_DIV : in Integer;
- CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
- CLKI_DIV : in Integer; CLKOS_FDEL : in Integer;
- CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer;
- CLKOS_MODE : in String; CLKOP_MODE : in String;
- PHASEADJ : in Integer; CLKOS_VCODEL : in Integer
- -- synopsys translate_on
- );
- port (SMIADDR9: in std_logic; SMIADDR8: in std_logic;
- SMIADDR7: in std_logic; SMIADDR6: in std_logic;
- SMIADDR5: in std_logic; SMIADDR4: in std_logic;
- SMIADDR3: in std_logic; SMIADDR2: in std_logic;
- SMIADDR1: in std_logic; SMIADDR0: in std_logic;
- SMIRD: in std_logic; SMIWR: in std_logic;
- SMICLK: in std_logic; SMIWDATA: in std_logic;
- SMIRSTN: in std_logic; CLKI: in std_logic;
- CLKFB: in std_logic; RSTN: in std_logic;
- CLKOS: out std_logic; CLKOP: out std_logic;
- LOCK: out std_logic; CLKINTFB: out std_logic;
- SMIRDATA: out std_logic);
- end component;
- attribute module_type of EHXPLLA : component is "EHXPLLA";
- attribute ip_type : string;
- attribute FREQUENCY_PIN_CLKOS : string;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute VCO_LOWERFREQ : string;
- attribute GMCFREQSEL : string;
- attribute GSR : string;
- attribute SPREAD_DIV2 : string;
- attribute SPREAD_DIV1 : string;
- attribute SPREAD_DRIFT : string;
- attribute SPREAD : string;
- attribute CLKFB_FDEL : string;
- attribute CLKI_FDEL : string;
- attribute CLKFB_PDEL : string;
- attribute CLKI_PDEL : string;
- attribute LF_RESISTOR : string;
- attribute LF_IX5UA : string;
- attribute CLKOS_FDEL : string;
- attribute CLKOS_VCODEL : string;
- attribute PHASEADJ : string;
- attribute CLKOS_MODE : string;
- attribute CLKOP_MODE : string;
- attribute CLKOS_DIV : string;
- attribute CLKOP_DIV : string;
- attribute CLKFB_DIV : string;
- attribute CLKI_DIV : string;
- attribute ip_type of pll_ref_0_0 : label is "EHXPLLA";
- attribute FREQUENCY_PIN_CLKOS of pll_ref_0_0 : label is "100.000000";
- attribute FREQUENCY_PIN_CLKOP of pll_ref_0_0 : label is "200.000000";
- attribute FREQUENCY_PIN_CLKI of pll_ref_0_0 : label is "100.000000";
- attribute VCO_LOWERFREQ of pll_ref_0_0 : label is "DISABLED";
- attribute GMCFREQSEL of pll_ref_0_0 : label is "HIGH";
- attribute GSR of pll_ref_0_0 : label is "DISABLED";
- attribute SPREAD_DIV2 of pll_ref_0_0 : label is "2";
- attribute SPREAD_DIV1 of pll_ref_0_0 : label is "2";
- attribute SPREAD_DRIFT of pll_ref_0_0 : label is "1";
- attribute SPREAD of pll_ref_0_0 : label is "DISABLED";
- attribute CLKFB_FDEL of pll_ref_0_0 : label is "0";
- attribute CLKI_FDEL of pll_ref_0_0 : label is "0";
- attribute CLKFB_PDEL of pll_ref_0_0 : label is "DEL0";
- attribute CLKI_PDEL of pll_ref_0_0 : label is "DEL0";
- attribute LF_RESISTOR of pll_ref_0_0 : label is "0b111010";
- attribute LF_IX5UA of pll_ref_0_0 : label is "31";
- attribute CLKOS_FDEL of pll_ref_0_0 : label is "0";
- attribute CLKOS_VCODEL of pll_ref_0_0 : label is "0";
- attribute PHASEADJ of pll_ref_0_0 : label is "0";
- attribute CLKOS_MODE of pll_ref_0_0 : label is "DIV";
- attribute CLKOP_MODE of pll_ref_0_0 : label is "DIV";
- attribute CLKOS_DIV of pll_ref_0_0 : label is "6";
- attribute CLKOP_DIV of pll_ref_0_0 : label is "3";
- attribute CLKFB_DIV of pll_ref_0_0 : label is "2";
- attribute CLKI_DIV of pll_ref_0_0 : label is "1";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
-
-begin
- -- component instantiation statements
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- pll_ref_0_0: EHXPLLA
- generic map (SMI_OFFSET=> SMI_OFFSET
- -- synopsys translate_off
- , GSR=> "DISABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0,
- CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "DIV",
- CLKOP_MODE=> "DIV", CLKOS_DIV=> 6, CLKOP_DIV=> 3, CLKFB_DIV=> 2,
- CLKI_DIV=> 1
- -- synopsys translate_on
- )
- port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo,
- SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo,
- SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo,
- SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo,
- SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo,
- SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo,
- SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>clkop_t,
- RSTN=>scuba_vhi, CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock,
- CLKINTFB=>open, SMIRDATA=>open);
-
- clkos <= clkos_t;
- clkop <= clkop_t;
- clk_t <= clk;
-end Structure;
-
--- synopsys translate_off
-library SCM;
-configuration Structure_CON of pll_ref is
- for Structure
- for all:VHI use entity SCM.VHI(V); end for;
- for all:VLO use entity SCM.VLO(V); end for;
- for all:EHXPLLA use entity SCM.EHXPLLA(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-to run all:
-
-mkdir workdir;
-cd workdir;
-ln -s ../serdes_fpga_ref_clk.txt serdes_fpga_ref_clk.txt #configuration file for serdes in LATTICE
-ln -s ../hub.lpf hub.lpf #user constraints
-cd ..
-. /your/xilinx/patch/settings.sh #set xilinx enviroment
-. setup_env #check paths for LATTICE
-#change in hub_1.xcf to correct path of out .bit file
-# /your/project/path/workdir/hub.bit or produce it in isp - this for chain
-#FPGA - LATTICE, in future there will be no FPGA on trbv2 for hub
-./compile_hub.pl #run main script
-
+++ /dev/null
-
-
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCS quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCS quad to the final design requirements.
-# channel_0 is in "8b10b" mode
-# channel_1 is in "8b10b" mode
-# channel_2 is in "8b10b" mode
-# channel_3 is in "8b10b" mode
-
-ch0 13 03 # Powerup Channel
-ch0 00 00
-ch1 13 03 # Powerup Channel
-ch1 00 00
-ch2 13 03 # Powerup Channel
-ch2 00 00
-ch3 13 03 # Powerup Channel
-ch3 00 00
-quad 00 00
-quad 01 E4
-quad 28 40 # Reference clock multiplier
-quad 29 11 # FPGA sourced refclk
-quad 02 00 # ref_pclk source is ch0
-quad 04 00 # MCA enable 4 channels
-
-quad 18 10 # 8b10b Mode
-quad 14 FF # Word Alignment Mask
-quad 15 7c # +ve K
-quad 16 b6 # -ve K
-#quad 16 83 # -ve K
-quad 17 36
-
-quad 19 8C # Enable word_align_en port, FPGA bus width is 16-bit/20-bit
-
-#quad 1e 01 #SOP EOP only 1 word 24.04.2008
-#quad 1f ff
-#quad 20 7c
-#quad 21 7c
-#quad 22 5
-#quad 23 7c
-#quad 24 7c
-#quad 25 5
-
-
-ch0 14 90 # 16% pre-emphasis
-ch0 15 10 # +6dB equalization
-ch1 14 90 # 16% pre-emphasis
-ch1 15 10 # +6dB equalization
-ch2 14 90 # 16% pre-emphasis
-ch2 15 10 # +6dB equalization
-ch3 14 90 # 16% pre-emphasis
-ch3 15 10 # +6dB equalization
-
-# These lines must appear last in the autoconfig file. These lines apply the correct
-# reset sequence to the PCS block upon bitstream configuration
-quad 41 00 # de-assert serdes_rst
-quad 40 ff # assert datapath reset for all channels
-quad 40 00 # de-assert datapath reset for all channels
-
-
-
+++ /dev/null
-
-
--- channel_0 is in "8b10b" mode
--- channel_1 is in "8b10b" mode
--- channel_2 is in "8b10b" mode
--- channel_3 is in "8b10b" mode
-
---synopsys translate_off
-
-library pcsa_mti_work;
-use pcsa_mti_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSA is
-GENERIC(
- CONFIG_FILE : String := "serdes_fpga_ref_clk.txt"
- );
-port (
- HDINP0 : in std_logic;
- HDINN0 : in std_logic;
- HDINP1 : in std_logic;
- HDINN1 : in std_logic;
- HDINP2 : in std_logic;
- HDINN2 : in std_logic;
- HDINP3 : in std_logic;
- HDINN3 : in std_logic;
- HDOUTP0 : out std_logic;
- HDOUTN0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTP3 : out std_logic;
- HDOUTN3 : out std_logic;
- REFCLKP : in std_logic;
- REFCLKN : in std_logic;
- RXREFCLKP : in std_logic;
- RXREFCLKN : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_MACRO_RST : in std_logic;
-
- FFC_LANE_TX_RST0 : in std_logic;
- FFC_LANE_TX_RST1 : in std_logic;
- FFC_LANE_TX_RST2 : in std_logic;
- FFC_LANE_TX_RST3 : in std_logic;
-
- FFC_LANE_RX_RST0 : in std_logic;
- FFC_LANE_RX_RST1 : in std_logic;
- FFC_LANE_RX_RST2 : in std_logic;
- FFC_LANE_RX_RST3 : in std_logic;
-
- FFC_PCIE_EI_EN_0 : in std_logic;
- FFC_PCIE_EI_EN_1 : in std_logic;
- FFC_PCIE_EI_EN_2 : in std_logic;
- FFC_PCIE_EI_EN_3 : in std_logic;
-
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
-
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
-
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
-
- FFC_PCIE_TX_0 : in std_logic;
- FFC_PCIE_TX_1 : in std_logic;
- FFC_PCIE_TX_2 : in std_logic;
- FFC_PCIE_TX_3 : in std_logic;
-
- FFC_PCIE_RX_0 : in std_logic;
- FFC_PCIE_RX_1 : in std_logic;
- FFC_PCIE_RX_2 : in std_logic;
- FFC_PCIE_RX_3 : in std_logic;
-
- FFC_SD_0 : in std_logic;
- FFC_SD_1 : in std_logic;
- FFC_SD_2 : in std_logic;
- FFC_SD_3 : in std_logic;
-
- FFC_EN_CGA_0 : in std_logic;
- FFC_EN_CGA_1 : in std_logic;
- FFC_EN_CGA_2 : in std_logic;
- FFC_EN_CGA_3 : in std_logic;
-
- FFC_ALIGN_EN_0 : in std_logic;
- FFC_ALIGN_EN_1 : in std_logic;
- FFC_ALIGN_EN_2 : in std_logic;
- FFC_ALIGN_EN_3 : in std_logic;
-
- FFC_AB_RESET : in std_logic;
- FFC_CD_RESET : in std_logic;
-
- FFS_LS_STATUS_0 : out std_logic;
- FFS_LS_STATUS_1 : out std_logic;
- FFS_LS_STATUS_2 : out std_logic;
- FFS_LS_STATUS_3 : out std_logic;
-
- FFS_AB_STATUS : out std_logic;
- FFS_CD_STATUS : out std_logic;
-
- FFS_AB_ALIGNED : out std_logic;
- FFS_CD_ALIGNED : out std_logic;
-
- FFS_RLOS_LO0 : out std_logic;
- FFS_RLOS_LO1 : out std_logic;
- FFS_RLOS_LO2 : out std_logic;
- FFS_RLOS_LO3 : out std_logic;
-
- FFS_AB_FAILED : out std_logic;
- FFS_CD_FAILED : out std_logic;
-
- FFC_FB_LB_0 : in std_logic;
- FFC_FB_LB_1 : in std_logic;
- FFC_FB_LB_2 : in std_logic;
- FFC_FB_LB_3 : in std_logic;
-
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
-
- FFS_CC_ORUN_0 : out std_logic;
- FFS_CC_ORUN_1 : out std_logic;
- FFS_CC_ORUN_2 : out std_logic;
- FFS_CC_ORUN_3 : out std_logic;
-
- FFS_CC_URUN_0 : out std_logic;
- FFS_CC_URUN_1 : out std_logic;
- FFS_CC_URUN_2 : out std_logic;
- FFS_CC_URUN_3 : out std_logic;
-
- FFC_CK_CORE_TX : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- RDATAO_7 : out std_logic;
- RDATAO_6 : out std_logic;
- RDATAO_5 : out std_logic;
- RDATAO_4 : out std_logic;
- RDATAO_3 : out std_logic;
- RDATAO_2 : out std_logic;
- RDATAO_1 : out std_logic;
- RDATAO_0 : out std_logic;
- INTO : out std_logic;
-
- ADDRI_7 : in std_logic;
- ADDRI_6 : in std_logic;
- ADDRI_5 : in std_logic;
- ADDRI_4 : in std_logic;
- ADDRI_3 : in std_logic;
- ADDRI_2 : in std_logic;
- ADDRI_1 : in std_logic;
- ADDRI_0 : in std_logic;
- WDATAI_7 : in std_logic;
- WDATAI_6 : in std_logic;
- WDATAI_5 : in std_logic;
- WDATAI_4 : in std_logic;
- WDATAI_3 : in std_logic;
- WDATAI_2 : in std_logic;
- WDATAI_1 : in std_logic;
- WDATAI_0 : in std_logic;
- RDI : in std_logic;
- WSTBI : in std_logic;
-
- CS_CHIF_0 : in std_logic;
- CS_CHIF_1 : in std_logic;
- CS_CHIF_2 : in std_logic;
- CS_CHIF_3 : in std_logic;
- CS_QIF : in std_logic;
-
- QUAD_ID_1 : in std_logic;
- QUAD_ID_0 : in std_logic;
-
- FF_SYSCLK_P1 : out std_logic;
-
- FF_SYSCLK0 : out std_logic;
- FF_SYSCLK1 : out std_logic;
- FF_SYSCLK2 : out std_logic;
- FF_SYSCLK3 : out std_logic;
-
- FF_RXCLK_P1 : out std_logic;
- FF_RXCLK_P2 : out std_logic;
-
- FF_RXCLK0 : out std_logic;
- FF_RXCLK1 : out std_logic;
- FF_RXCLK2 : out std_logic;
- FF_RXCLK3 : out std_logic;
-
- QUAD_CLK : out std_logic;
-
- GRP_CLK_P1_3 : in std_logic;
- GRP_CLK_P1_2 : in std_logic;
- GRP_CLK_P1_1 : in std_logic;
- GRP_CLK_P1_0 : in std_logic;
-
- GRP_CLK_P2_3 : in std_logic;
- GRP_CLK_P2_2 : in std_logic;
- GRP_CLK_P2_1 : in std_logic;
- GRP_CLK_P2_0 : in std_logic;
-
- GRP_START_3 : in std_logic;
- GRP_START_2 : in std_logic;
- GRP_START_1 : in std_logic;
- GRP_START_0 : in std_logic;
-
- GRP_DONE_3 : in std_logic;
- GRP_DONE_2 : in std_logic;
- GRP_DONE_1 : in std_logic;
- GRP_DONE_0 : in std_logic;
-
- GRP_DESKEW_ERROR_3 : in std_logic;
- GRP_DESKEW_ERROR_2 : in std_logic;
- GRP_DESKEW_ERROR_1 : in std_logic;
- GRP_DESKEW_ERROR_0 : in std_logic;
-
- IQA_START_LS : out std_logic;
- IQA_DONE_LS : out std_logic;
- IQA_AND_FP1_LS : out std_logic;
- IQA_AND_FP0_LS : out std_logic;
- IQA_OR_FP1_LS : out std_logic;
- IQA_OR_FP0_LS : out std_logic;
- IQA_RST_N : out std_logic;
-
- FF_TCLK0 : in std_logic;
- FF_TCLK1 : in std_logic;
- FF_TCLK2 : in std_logic;
- FF_TCLK3 : in std_logic;
-
- FF_RCLK0 : in std_logic;
- FF_RCLK1 : in std_logic;
- FF_RCLK2 : in std_logic;
- FF_RCLK3 : in std_logic;
- TCK_FMACP : in std_logic;
-
- FF_TXD_0_23 : in std_logic;
- FF_TXD_0_22 : in std_logic;
- FF_TXD_0_21 : in std_logic;
- FF_TXD_0_20 : in std_logic;
- FF_TXD_0_19 : in std_logic;
- FF_TXD_0_18 : in std_logic;
- FF_TXD_0_17 : in std_logic;
- FF_TXD_0_16 : in std_logic;
- FF_TXD_0_15 : in std_logic;
- FF_TXD_0_14 : in std_logic;
- FF_TXD_0_13 : in std_logic;
- FF_TXD_0_12 : in std_logic;
- FF_TXD_0_11 : in std_logic;
- FF_TXD_0_10 : in std_logic;
- FF_TXD_0_9 : in std_logic;
- FF_TXD_0_8 : in std_logic;
- FF_TXD_0_7 : in std_logic;
- FF_TXD_0_6 : in std_logic;
- FF_TXD_0_5 : in std_logic;
- FF_TXD_0_4 : in std_logic;
- FF_TXD_0_3 : in std_logic;
- FF_TXD_0_2 : in std_logic;
- FF_TXD_0_1 : in std_logic;
- FF_TXD_0_0 : in std_logic;
- FB_RXD_0_23 : out std_logic;
- FB_RXD_0_22 : out std_logic;
- FB_RXD_0_21 : out std_logic;
- FB_RXD_0_20 : out std_logic;
- FB_RXD_0_19 : out std_logic;
- FB_RXD_0_18 : out std_logic;
- FB_RXD_0_17 : out std_logic;
- FB_RXD_0_16 : out std_logic;
- FB_RXD_0_15 : out std_logic;
- FB_RXD_0_14 : out std_logic;
- FB_RXD_0_13 : out std_logic;
- FB_RXD_0_12 : out std_logic;
- FB_RXD_0_11 : out std_logic;
- FB_RXD_0_10 : out std_logic;
- FB_RXD_0_9 : out std_logic;
- FB_RXD_0_8 : out std_logic;
- FB_RXD_0_7 : out std_logic;
- FB_RXD_0_6 : out std_logic;
- FB_RXD_0_5 : out std_logic;
- FB_RXD_0_4 : out std_logic;
- FB_RXD_0_3 : out std_logic;
- FB_RXD_0_2 : out std_logic;
- FB_RXD_0_1 : out std_logic;
- FB_RXD_0_0 : out std_logic;
- FF_TXD_1_23 : in std_logic;
- FF_TXD_1_22 : in std_logic;
- FF_TXD_1_21 : in std_logic;
- FF_TXD_1_20 : in std_logic;
- FF_TXD_1_19 : in std_logic;
- FF_TXD_1_18 : in std_logic;
- FF_TXD_1_17 : in std_logic;
- FF_TXD_1_16 : in std_logic;
- FF_TXD_1_15 : in std_logic;
- FF_TXD_1_14 : in std_logic;
- FF_TXD_1_13 : in std_logic;
- FF_TXD_1_12 : in std_logic;
- FF_TXD_1_11 : in std_logic;
- FF_TXD_1_10 : in std_logic;
- FF_TXD_1_9 : in std_logic;
- FF_TXD_1_8 : in std_logic;
- FF_TXD_1_7 : in std_logic;
- FF_TXD_1_6 : in std_logic;
- FF_TXD_1_5 : in std_logic;
- FF_TXD_1_4 : in std_logic;
- FF_TXD_1_3 : in std_logic;
- FF_TXD_1_2 : in std_logic;
- FF_TXD_1_1 : in std_logic;
- FF_TXD_1_0 : in std_logic;
- FB_RXD_1_23 : out std_logic;
- FB_RXD_1_22 : out std_logic;
- FB_RXD_1_21 : out std_logic;
- FB_RXD_1_20 : out std_logic;
- FB_RXD_1_19 : out std_logic;
- FB_RXD_1_18 : out std_logic;
- FB_RXD_1_17 : out std_logic;
- FB_RXD_1_16 : out std_logic;
- FB_RXD_1_15 : out std_logic;
- FB_RXD_1_14 : out std_logic;
- FB_RXD_1_13 : out std_logic;
- FB_RXD_1_12 : out std_logic;
- FB_RXD_1_11 : out std_logic;
- FB_RXD_1_10 : out std_logic;
- FB_RXD_1_9 : out std_logic;
- FB_RXD_1_8 : out std_logic;
- FB_RXD_1_7 : out std_logic;
- FB_RXD_1_6 : out std_logic;
- FB_RXD_1_5 : out std_logic;
- FB_RXD_1_4 : out std_logic;
- FB_RXD_1_3 : out std_logic;
- FB_RXD_1_2 : out std_logic;
- FB_RXD_1_1 : out std_logic;
- FB_RXD_1_0 : out std_logic;
- FF_TXD_2_23 : in std_logic;
- FF_TXD_2_22 : in std_logic;
- FF_TXD_2_21 : in std_logic;
- FF_TXD_2_20 : in std_logic;
- FF_TXD_2_19 : in std_logic;
- FF_TXD_2_18 : in std_logic;
- FF_TXD_2_17 : in std_logic;
- FF_TXD_2_16 : in std_logic;
- FF_TXD_2_15 : in std_logic;
- FF_TXD_2_14 : in std_logic;
- FF_TXD_2_13 : in std_logic;
- FF_TXD_2_12 : in std_logic;
- FF_TXD_2_11 : in std_logic;
- FF_TXD_2_10 : in std_logic;
- FF_TXD_2_9 : in std_logic;
- FF_TXD_2_8 : in std_logic;
- FF_TXD_2_7 : in std_logic;
- FF_TXD_2_6 : in std_logic;
- FF_TXD_2_5 : in std_logic;
- FF_TXD_2_4 : in std_logic;
- FF_TXD_2_3 : in std_logic;
- FF_TXD_2_2 : in std_logic;
- FF_TXD_2_1 : in std_logic;
- FF_TXD_2_0 : in std_logic;
- FB_RXD_2_23 : out std_logic;
- FB_RXD_2_22 : out std_logic;
- FB_RXD_2_21 : out std_logic;
- FB_RXD_2_20 : out std_logic;
- FB_RXD_2_19 : out std_logic;
- FB_RXD_2_18 : out std_logic;
- FB_RXD_2_17 : out std_logic;
- FB_RXD_2_16 : out std_logic;
- FB_RXD_2_15 : out std_logic;
- FB_RXD_2_14 : out std_logic;
- FB_RXD_2_13 : out std_logic;
- FB_RXD_2_12 : out std_logic;
- FB_RXD_2_11 : out std_logic;
- FB_RXD_2_10 : out std_logic;
- FB_RXD_2_9 : out std_logic;
- FB_RXD_2_8 : out std_logic;
- FB_RXD_2_7 : out std_logic;
- FB_RXD_2_6 : out std_logic;
- FB_RXD_2_5 : out std_logic;
- FB_RXD_2_4 : out std_logic;
- FB_RXD_2_3 : out std_logic;
- FB_RXD_2_2 : out std_logic;
- FB_RXD_2_1 : out std_logic;
- FB_RXD_2_0 : out std_logic;
- FF_TXD_3_23 : in std_logic;
- FF_TXD_3_22 : in std_logic;
- FF_TXD_3_21 : in std_logic;
- FF_TXD_3_20 : in std_logic;
- FF_TXD_3_19 : in std_logic;
- FF_TXD_3_18 : in std_logic;
- FF_TXD_3_17 : in std_logic;
- FF_TXD_3_16 : in std_logic;
- FF_TXD_3_15 : in std_logic;
- FF_TXD_3_14 : in std_logic;
- FF_TXD_3_13 : in std_logic;
- FF_TXD_3_12 : in std_logic;
- FF_TXD_3_11 : in std_logic;
- FF_TXD_3_10 : in std_logic;
- FF_TXD_3_9 : in std_logic;
- FF_TXD_3_8 : in std_logic;
- FF_TXD_3_7 : in std_logic;
- FF_TXD_3_6 : in std_logic;
- FF_TXD_3_5 : in std_logic;
- FF_TXD_3_4 : in std_logic;
- FF_TXD_3_3 : in std_logic;
- FF_TXD_3_2 : in std_logic;
- FF_TXD_3_1 : in std_logic;
- FF_TXD_3_0 : in std_logic;
- FB_RXD_3_23 : out std_logic;
- FB_RXD_3_22 : out std_logic;
- FB_RXD_3_21 : out std_logic;
- FB_RXD_3_20 : out std_logic;
- FB_RXD_3_19 : out std_logic;
- FB_RXD_3_18 : out std_logic;
- FB_RXD_3_17 : out std_logic;
- FB_RXD_3_16 : out std_logic;
- FB_RXD_3_15 : out std_logic;
- FB_RXD_3_14 : out std_logic;
- FB_RXD_3_13 : out std_logic;
- FB_RXD_3_12 : out std_logic;
- FB_RXD_3_11 : out std_logic;
- FB_RXD_3_10 : out std_logic;
- FB_RXD_3_9 : out std_logic;
- FB_RXD_3_8 : out std_logic;
- FB_RXD_3_7 : out std_logic;
- FB_RXD_3_6 : out std_logic;
- FB_RXD_3_5 : out std_logic;
- FB_RXD_3_4 : out std_logic;
- FB_RXD_3_3 : out std_logic;
- FB_RXD_3_2 : out std_logic;
- FB_RXD_3_1 : out std_logic;
- FB_RXD_3_0 : out std_logic;
- TCK_FMAC : out std_logic;
- BS4PAD_0 : out std_logic;
- BS4PAD_1 : out std_logic;
- BS4PAD_2 : out std_logic;
- BS4PAD_3 : out std_logic;
- COUT_21 : out std_logic;
- COUT_20 : out std_logic;
- COUT_19 : out std_logic;
- COUT_18 : out std_logic;
- COUT_17 : out std_logic;
- COUT_16 : out std_logic;
- COUT_15 : out std_logic;
- COUT_14 : out std_logic;
- COUT_13 : out std_logic;
- COUT_12 : out std_logic;
- COUT_11 : out std_logic;
- COUT_10 : out std_logic;
- COUT_9 : out std_logic;
- COUT_8 : out std_logic;
- COUT_7 : out std_logic;
- COUT_6 : out std_logic;
- COUT_5 : out std_logic;
- COUT_4 : out std_logic;
- COUT_3 : out std_logic;
- COUT_2 : out std_logic;
- COUT_1 : out std_logic;
- COUT_0 : out std_logic;
- CIN_12 : in std_logic;
- CIN_11 : in std_logic;
- CIN_10 : in std_logic;
- CIN_9 : in std_logic;
- CIN_8 : in std_logic;
- CIN_7 : in std_logic;
- CIN_6 : in std_logic;
- CIN_5 : in std_logic;
- CIN_4 : in std_logic;
- CIN_3 : in std_logic;
- CIN_2 : in std_logic;
- CIN_1 : in std_logic;
- CIN_0 : in std_logic;
- TESTCLK_MACO : in std_logic
-);
-
-end PCSA;
-
-architecture PCSA_arch of PCSA is
-
-component PCSA_sim
-GENERIC(
- CONFIG_FILE : String
- );
-port (
- HDINP0 : in std_logic;
- HDINN0 : in std_logic;
- HDINP1 : in std_logic;
- HDINN1 : in std_logic;
- HDINP2 : in std_logic;
- HDINN2 : in std_logic;
- HDINP3 : in std_logic;
- HDINN3 : in std_logic;
- HDOUTP0 : out std_logic;
- HDOUTN0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTP3 : out std_logic;
- HDOUTN3 : out std_logic;
- REFCLKP : in std_logic;
- REFCLKN : in std_logic;
- RXREFCLKP : in std_logic;
- RXREFCLKN : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_MACRO_RST : in std_logic;
-
- FFC_LANE_TX_RST0 : in std_logic;
- FFC_LANE_TX_RST1 : in std_logic;
- FFC_LANE_TX_RST2 : in std_logic;
- FFC_LANE_TX_RST3 : in std_logic;
-
- FFC_LANE_RX_RST0 : in std_logic;
- FFC_LANE_RX_RST1 : in std_logic;
- FFC_LANE_RX_RST2 : in std_logic;
- FFC_LANE_RX_RST3 : in std_logic;
-
- FFC_PCIE_EI_EN_0 : in std_logic;
- FFC_PCIE_EI_EN_1 : in std_logic;
- FFC_PCIE_EI_EN_2 : in std_logic;
- FFC_PCIE_EI_EN_3 : in std_logic;
-
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
-
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
-
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
-
- FFC_PCIE_TX_0 : in std_logic;
- FFC_PCIE_TX_1 : in std_logic;
- FFC_PCIE_TX_2 : in std_logic;
- FFC_PCIE_TX_3 : in std_logic;
-
- FFC_PCIE_RX_0 : in std_logic;
- FFC_PCIE_RX_1 : in std_logic;
- FFC_PCIE_RX_2 : in std_logic;
- FFC_PCIE_RX_3 : in std_logic;
-
- FFC_SD_0 : in std_logic;
- FFC_SD_1 : in std_logic;
- FFC_SD_2 : in std_logic;
- FFC_SD_3 : in std_logic;
-
- FFC_EN_CGA_0 : in std_logic;
- FFC_EN_CGA_1 : in std_logic;
- FFC_EN_CGA_2 : in std_logic;
- FFC_EN_CGA_3 : in std_logic;
-
- FFC_ALIGN_EN_0 : in std_logic;
- FFC_ALIGN_EN_1 : in std_logic;
- FFC_ALIGN_EN_2 : in std_logic;
- FFC_ALIGN_EN_3 : in std_logic;
-
- FFC_AB_RESET : in std_logic;
- FFC_CD_RESET : in std_logic;
-
- FFS_LS_STATUS_0 : out std_logic;
- FFS_LS_STATUS_1 : out std_logic;
- FFS_LS_STATUS_2 : out std_logic;
- FFS_LS_STATUS_3 : out std_logic;
-
- FFS_AB_STATUS : out std_logic;
- FFS_CD_STATUS : out std_logic;
-
- FFS_AB_ALIGNED : out std_logic;
- FFS_CD_ALIGNED : out std_logic;
-
- FFS_AB_FAILED : out std_logic;
- FFS_CD_FAILED : out std_logic;
-
- FFS_RLOS_LO0 : out std_logic;
- FFS_RLOS_LO1 : out std_logic;
- FFS_RLOS_LO2 : out std_logic;
- FFS_RLOS_LO3 : out std_logic;
-
- FFC_FB_LB_0 : in std_logic;
- FFC_FB_LB_1 : in std_logic;
- FFC_FB_LB_2 : in std_logic;
- FFC_FB_LB_3 : in std_logic;
-
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
-
- FFS_CC_ORUN_0 : out std_logic;
- FFS_CC_ORUN_1 : out std_logic;
- FFS_CC_ORUN_2 : out std_logic;
- FFS_CC_ORUN_3 : out std_logic;
-
- FFS_CC_URUN_0 : out std_logic;
- FFS_CC_URUN_1 : out std_logic;
- FFS_CC_URUN_2 : out std_logic;
- FFS_CC_URUN_3 : out std_logic;
-
- FFC_CK_CORE_TX : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- RDATAO_7 : out std_logic;
- RDATAO_6 : out std_logic;
- RDATAO_5 : out std_logic;
- RDATAO_4 : out std_logic;
- RDATAO_3 : out std_logic;
- RDATAO_2 : out std_logic;
- RDATAO_1 : out std_logic;
- RDATAO_0 : out std_logic;
- INTO : out std_logic;
-
- ADDRI_7 : in std_logic;
- ADDRI_6 : in std_logic;
- ADDRI_5 : in std_logic;
- ADDRI_4 : in std_logic;
- ADDRI_3 : in std_logic;
- ADDRI_2 : in std_logic;
- ADDRI_1 : in std_logic;
- ADDRI_0 : in std_logic;
- WDATAI_7 : in std_logic;
- WDATAI_6 : in std_logic;
- WDATAI_5 : in std_logic;
- WDATAI_4 : in std_logic;
- WDATAI_3 : in std_logic;
- WDATAI_2 : in std_logic;
- WDATAI_1 : in std_logic;
- WDATAI_0 : in std_logic;
- RDI : in std_logic;
- WSTBI : in std_logic;
-
- CS_CHIF_0 : in std_logic;
- CS_CHIF_1 : in std_logic;
- CS_CHIF_2 : in std_logic;
- CS_CHIF_3 : in std_logic;
- CS_QIF : in std_logic;
-
- QUAD_ID_1 : in std_logic;
- QUAD_ID_0 : in std_logic;
-
- FF_SYSCLK_P1 : out std_logic;
-
- FF_SYSCLK0 : out std_logic;
- FF_SYSCLK1 : out std_logic;
- FF_SYSCLK2 : out std_logic;
- FF_SYSCLK3 : out std_logic;
-
- FF_RXCLK_P1 : out std_logic;
- FF_RXCLK_P2 : out std_logic;
-
- FF_RXCLK0 : out std_logic;
- FF_RXCLK1 : out std_logic;
- FF_RXCLK2 : out std_logic;
- FF_RXCLK3 : out std_logic;
-
- QUAD_CLK : out std_logic;
-
- GRP_CLK_P1_3 : in std_logic;
- GRP_CLK_P1_2 : in std_logic;
- GRP_CLK_P1_1 : in std_logic;
- GRP_CLK_P1_0 : in std_logic;
-
- GRP_CLK_P2_3 : in std_logic;
- GRP_CLK_P2_2 : in std_logic;
- GRP_CLK_P2_1 : in std_logic;
- GRP_CLK_P2_0 : in std_logic;
-
- GRP_START_3 : in std_logic;
- GRP_START_2 : in std_logic;
- GRP_START_1 : in std_logic;
- GRP_START_0 : in std_logic;
-
- GRP_DONE_3 : in std_logic;
- GRP_DONE_2 : in std_logic;
- GRP_DONE_1 : in std_logic;
- GRP_DONE_0 : in std_logic;
-
- GRP_DESKEW_ERROR_3 : in std_logic;
- GRP_DESKEW_ERROR_2 : in std_logic;
- GRP_DESKEW_ERROR_1 : in std_logic;
- GRP_DESKEW_ERROR_0 : in std_logic;
-
- IQA_START_LS : out std_logic;
- IQA_DONE_LS : out std_logic;
- IQA_AND_FP1_LS : out std_logic;
- IQA_AND_FP0_LS : out std_logic;
- IQA_OR_FP1_LS : out std_logic;
- IQA_OR_FP0_LS : out std_logic;
- IQA_RST_N : out std_logic;
-
- FF_TCLK0 : in std_logic;
- FF_TCLK1 : in std_logic;
- FF_TCLK2 : in std_logic;
- FF_TCLK3 : in std_logic;
-
- FF_RCLK0 : in std_logic;
- FF_RCLK1 : in std_logic;
- FF_RCLK2 : in std_logic;
- FF_RCLK3 : in std_logic;
- TCK_FMACP : in std_logic;
-
- FF_TXD_0_23 : in std_logic;
- FF_TXD_0_22 : in std_logic;
- FF_TXD_0_21 : in std_logic;
- FF_TXD_0_20 : in std_logic;
- FF_TXD_0_19 : in std_logic;
- FF_TXD_0_18 : in std_logic;
- FF_TXD_0_17 : in std_logic;
- FF_TXD_0_16 : in std_logic;
- FF_TXD_0_15 : in std_logic;
- FF_TXD_0_14 : in std_logic;
- FF_TXD_0_13 : in std_logic;
- FF_TXD_0_12 : in std_logic;
- FF_TXD_0_11 : in std_logic;
- FF_TXD_0_10 : in std_logic;
- FF_TXD_0_9 : in std_logic;
- FF_TXD_0_8 : in std_logic;
- FF_TXD_0_7 : in std_logic;
- FF_TXD_0_6 : in std_logic;
- FF_TXD_0_5 : in std_logic;
- FF_TXD_0_4 : in std_logic;
- FF_TXD_0_3 : in std_logic;
- FF_TXD_0_2 : in std_logic;
- FF_TXD_0_1 : in std_logic;
- FF_TXD_0_0 : in std_logic;
- FB_RXD_0_23 : out std_logic;
- FB_RXD_0_22 : out std_logic;
- FB_RXD_0_21 : out std_logic;
- FB_RXD_0_20 : out std_logic;
- FB_RXD_0_19 : out std_logic;
- FB_RXD_0_18 : out std_logic;
- FB_RXD_0_17 : out std_logic;
- FB_RXD_0_16 : out std_logic;
- FB_RXD_0_15 : out std_logic;
- FB_RXD_0_14 : out std_logic;
- FB_RXD_0_13 : out std_logic;
- FB_RXD_0_12 : out std_logic;
- FB_RXD_0_11 : out std_logic;
- FB_RXD_0_10 : out std_logic;
- FB_RXD_0_9 : out std_logic;
- FB_RXD_0_8 : out std_logic;
- FB_RXD_0_7 : out std_logic;
- FB_RXD_0_6 : out std_logic;
- FB_RXD_0_5 : out std_logic;
- FB_RXD_0_4 : out std_logic;
- FB_RXD_0_3 : out std_logic;
- FB_RXD_0_2 : out std_logic;
- FB_RXD_0_1 : out std_logic;
- FB_RXD_0_0 : out std_logic;
- FF_TXD_1_23 : in std_logic;
- FF_TXD_1_22 : in std_logic;
- FF_TXD_1_21 : in std_logic;
- FF_TXD_1_20 : in std_logic;
- FF_TXD_1_19 : in std_logic;
- FF_TXD_1_18 : in std_logic;
- FF_TXD_1_17 : in std_logic;
- FF_TXD_1_16 : in std_logic;
- FF_TXD_1_15 : in std_logic;
- FF_TXD_1_14 : in std_logic;
- FF_TXD_1_13 : in std_logic;
- FF_TXD_1_12 : in std_logic;
- FF_TXD_1_11 : in std_logic;
- FF_TXD_1_10 : in std_logic;
- FF_TXD_1_9 : in std_logic;
- FF_TXD_1_8 : in std_logic;
- FF_TXD_1_7 : in std_logic;
- FF_TXD_1_6 : in std_logic;
- FF_TXD_1_5 : in std_logic;
- FF_TXD_1_4 : in std_logic;
- FF_TXD_1_3 : in std_logic;
- FF_TXD_1_2 : in std_logic;
- FF_TXD_1_1 : in std_logic;
- FF_TXD_1_0 : in std_logic;
- FB_RXD_1_23 : out std_logic;
- FB_RXD_1_22 : out std_logic;
- FB_RXD_1_21 : out std_logic;
- FB_RXD_1_20 : out std_logic;
- FB_RXD_1_19 : out std_logic;
- FB_RXD_1_18 : out std_logic;
- FB_RXD_1_17 : out std_logic;
- FB_RXD_1_16 : out std_logic;
- FB_RXD_1_15 : out std_logic;
- FB_RXD_1_14 : out std_logic;
- FB_RXD_1_13 : out std_logic;
- FB_RXD_1_12 : out std_logic;
- FB_RXD_1_11 : out std_logic;
- FB_RXD_1_10 : out std_logic;
- FB_RXD_1_9 : out std_logic;
- FB_RXD_1_8 : out std_logic;
- FB_RXD_1_7 : out std_logic;
- FB_RXD_1_6 : out std_logic;
- FB_RXD_1_5 : out std_logic;
- FB_RXD_1_4 : out std_logic;
- FB_RXD_1_3 : out std_logic;
- FB_RXD_1_2 : out std_logic;
- FB_RXD_1_1 : out std_logic;
- FB_RXD_1_0 : out std_logic;
- FF_TXD_2_23 : in std_logic;
- FF_TXD_2_22 : in std_logic;
- FF_TXD_2_21 : in std_logic;
- FF_TXD_2_20 : in std_logic;
- FF_TXD_2_19 : in std_logic;
- FF_TXD_2_18 : in std_logic;
- FF_TXD_2_17 : in std_logic;
- FF_TXD_2_16 : in std_logic;
- FF_TXD_2_15 : in std_logic;
- FF_TXD_2_14 : in std_logic;
- FF_TXD_2_13 : in std_logic;
- FF_TXD_2_12 : in std_logic;
- FF_TXD_2_11 : in std_logic;
- FF_TXD_2_10 : in std_logic;
- FF_TXD_2_9 : in std_logic;
- FF_TXD_2_8 : in std_logic;
- FF_TXD_2_7 : in std_logic;
- FF_TXD_2_6 : in std_logic;
- FF_TXD_2_5 : in std_logic;
- FF_TXD_2_4 : in std_logic;
- FF_TXD_2_3 : in std_logic;
- FF_TXD_2_2 : in std_logic;
- FF_TXD_2_1 : in std_logic;
- FF_TXD_2_0 : in std_logic;
- FB_RXD_2_23 : out std_logic;
- FB_RXD_2_22 : out std_logic;
- FB_RXD_2_21 : out std_logic;
- FB_RXD_2_20 : out std_logic;
- FB_RXD_2_19 : out std_logic;
- FB_RXD_2_18 : out std_logic;
- FB_RXD_2_17 : out std_logic;
- FB_RXD_2_16 : out std_logic;
- FB_RXD_2_15 : out std_logic;
- FB_RXD_2_14 : out std_logic;
- FB_RXD_2_13 : out std_logic;
- FB_RXD_2_12 : out std_logic;
- FB_RXD_2_11 : out std_logic;
- FB_RXD_2_10 : out std_logic;
- FB_RXD_2_9 : out std_logic;
- FB_RXD_2_8 : out std_logic;
- FB_RXD_2_7 : out std_logic;
- FB_RXD_2_6 : out std_logic;
- FB_RXD_2_5 : out std_logic;
- FB_RXD_2_4 : out std_logic;
- FB_RXD_2_3 : out std_logic;
- FB_RXD_2_2 : out std_logic;
- FB_RXD_2_1 : out std_logic;
- FB_RXD_2_0 : out std_logic;
- FF_TXD_3_23 : in std_logic;
- FF_TXD_3_22 : in std_logic;
- FF_TXD_3_21 : in std_logic;
- FF_TXD_3_20 : in std_logic;
- FF_TXD_3_19 : in std_logic;
- FF_TXD_3_18 : in std_logic;
- FF_TXD_3_17 : in std_logic;
- FF_TXD_3_16 : in std_logic;
- FF_TXD_3_15 : in std_logic;
- FF_TXD_3_14 : in std_logic;
- FF_TXD_3_13 : in std_logic;
- FF_TXD_3_12 : in std_logic;
- FF_TXD_3_11 : in std_logic;
- FF_TXD_3_10 : in std_logic;
- FF_TXD_3_9 : in std_logic;
- FF_TXD_3_8 : in std_logic;
- FF_TXD_3_7 : in std_logic;
- FF_TXD_3_6 : in std_logic;
- FF_TXD_3_5 : in std_logic;
- FF_TXD_3_4 : in std_logic;
- FF_TXD_3_3 : in std_logic;
- FF_TXD_3_2 : in std_logic;
- FF_TXD_3_1 : in std_logic;
- FF_TXD_3_0 : in std_logic;
- FB_RXD_3_23 : out std_logic;
- FB_RXD_3_22 : out std_logic;
- FB_RXD_3_21 : out std_logic;
- FB_RXD_3_20 : out std_logic;
- FB_RXD_3_19 : out std_logic;
- FB_RXD_3_18 : out std_logic;
- FB_RXD_3_17 : out std_logic;
- FB_RXD_3_16 : out std_logic;
- FB_RXD_3_15 : out std_logic;
- FB_RXD_3_14 : out std_logic;
- FB_RXD_3_13 : out std_logic;
- FB_RXD_3_12 : out std_logic;
- FB_RXD_3_11 : out std_logic;
- FB_RXD_3_10 : out std_logic;
- FB_RXD_3_9 : out std_logic;
- FB_RXD_3_8 : out std_logic;
- FB_RXD_3_7 : out std_logic;
- FB_RXD_3_6 : out std_logic;
- FB_RXD_3_5 : out std_logic;
- FB_RXD_3_4 : out std_logic;
- FB_RXD_3_3 : out std_logic;
- FB_RXD_3_2 : out std_logic;
- FB_RXD_3_1 : out std_logic;
- FB_RXD_3_0 : out std_logic;
- TCK_FMAC : out std_logic;
- BS4PAD_0 : out std_logic;
- BS4PAD_1 : out std_logic;
- BS4PAD_2 : out std_logic;
- BS4PAD_3 : out std_logic;
- COUT_21 : out std_logic;
- COUT_20 : out std_logic;
- COUT_19 : out std_logic;
- COUT_18 : out std_logic;
- COUT_17 : out std_logic;
- COUT_16 : out std_logic;
- COUT_15 : out std_logic;
- COUT_14 : out std_logic;
- COUT_13 : out std_logic;
- COUT_12 : out std_logic;
- COUT_11 : out std_logic;
- COUT_10 : out std_logic;
- COUT_9 : out std_logic;
- COUT_8 : out std_logic;
- COUT_7 : out std_logic;
- COUT_6 : out std_logic;
- COUT_5 : out std_logic;
- COUT_4 : out std_logic;
- COUT_3 : out std_logic;
- COUT_2 : out std_logic;
- COUT_1 : out std_logic;
- COUT_0 : out std_logic;
- CIN_12 : in std_logic;
- CIN_11 : in std_logic;
- CIN_10 : in std_logic;
- CIN_9 : in std_logic;
- CIN_8 : in std_logic;
- CIN_7 : in std_logic;
- CIN_6 : in std_logic;
- CIN_5 : in std_logic;
- CIN_4 : in std_logic;
- CIN_3 : in std_logic;
- CIN_2 : in std_logic;
- CIN_1 : in std_logic;
- CIN_0 : in std_logic;
- TESTCLK_MACO : in std_logic
-);
-end component;
-
-begin
-
-PCSA_sim_inst : PCSA_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE)
-port map (
- HDINP0 => HDINP0,
- HDINN0 => HDINN0,
- HDINP1 => HDINP1,
- HDINN1 => HDINN1,
- HDINP2 => HDINP2,
- HDINN2 => HDINN2,
- HDINP3 => HDINP3,
- HDINN3 => HDINN3,
- HDOUTP0 => HDOUTP0,
- HDOUTN0 => HDOUTN0,
- HDOUTP1 => HDOUTP1,
- HDOUTN1 => HDOUTN1,
- HDOUTP2 => HDOUTP2,
- HDOUTN2 => HDOUTN2,
- HDOUTP3 => HDOUTP3,
- HDOUTN3 => HDOUTN3,
- REFCLKP => REFCLKP,
- REFCLKN => REFCLKN,
- RXREFCLKP => RXREFCLKP,
- RXREFCLKN => RXREFCLKN,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_LANE_TX_RST0 => FFC_LANE_TX_RST0,
- FFC_LANE_TX_RST1 => FFC_LANE_TX_RST1,
- FFC_LANE_TX_RST2 => FFC_LANE_TX_RST2,
- FFC_LANE_TX_RST3 => FFC_LANE_TX_RST3,
- FFC_LANE_RX_RST0 => FFC_LANE_RX_RST0,
- FFC_LANE_RX_RST1 => FFC_LANE_RX_RST1,
- FFC_LANE_RX_RST2 => FFC_LANE_RX_RST2,
- FFC_LANE_RX_RST3 => FFC_LANE_RX_RST3,
- FFC_PCIE_EI_EN_0 => FFC_PCIE_EI_EN_0,
- FFC_PCIE_EI_EN_1 => FFC_PCIE_EI_EN_1,
- FFC_PCIE_EI_EN_2 => FFC_PCIE_EI_EN_2,
- FFC_PCIE_EI_EN_3 => FFC_PCIE_EI_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFC_PCIE_TX_0 => FFC_PCIE_TX_0,
- FFC_PCIE_TX_1 => FFC_PCIE_TX_1,
- FFC_PCIE_TX_2 => FFC_PCIE_TX_2,
- FFC_PCIE_TX_3 => FFC_PCIE_TX_3,
- FFC_PCIE_RX_0 => FFC_PCIE_RX_0,
- FFC_PCIE_RX_1 => FFC_PCIE_RX_1,
- FFC_PCIE_RX_2 => FFC_PCIE_RX_2,
- FFC_PCIE_RX_3 => FFC_PCIE_RX_3,
- FFC_SD_0 => FFC_SD_0,
- FFC_SD_1 => FFC_SD_1,
- FFC_SD_2 => FFC_SD_2,
- FFC_SD_3 => FFC_SD_3,
- FFC_EN_CGA_0 => FFC_EN_CGA_0,
- FFC_EN_CGA_1 => FFC_EN_CGA_1,
- FFC_EN_CGA_2 => FFC_EN_CGA_2,
- FFC_EN_CGA_3 => FFC_EN_CGA_3,
- FFC_ALIGN_EN_0 => FFC_ALIGN_EN_0,
- FFC_ALIGN_EN_1 => FFC_ALIGN_EN_1,
- FFC_ALIGN_EN_2 => FFC_ALIGN_EN_2,
- FFC_ALIGN_EN_3 => FFC_ALIGN_EN_3,
- FFC_AB_RESET => FFC_AB_RESET,
- FFC_CD_RESET => FFC_CD_RESET,
- FFS_LS_STATUS_0 => FFS_LS_STATUS_0,
- FFS_LS_STATUS_1 => FFS_LS_STATUS_1,
- FFS_LS_STATUS_2 => FFS_LS_STATUS_2,
- FFS_LS_STATUS_3 => FFS_LS_STATUS_3,
- FFS_AB_STATUS => FFS_AB_STATUS,
- FFS_CD_STATUS => FFS_CD_STATUS,
- FFS_AB_ALIGNED => FFS_AB_ALIGNED,
- FFS_CD_ALIGNED => FFS_CD_ALIGNED,
- FFS_AB_FAILED => FFS_AB_FAILED,
- FFS_CD_FAILED => FFS_CD_FAILED,
- FFS_RLOS_LO0 => FFS_RLOS_LO0,
- FFS_RLOS_LO1 => FFS_RLOS_LO1,
- FFS_RLOS_LO2 => FFS_RLOS_LO2,
- FFS_RLOS_LO3 => FFS_RLOS_LO3,
- FFC_FB_LB_0 => FFC_FB_LB_0,
- FFC_FB_LB_1 => FFC_FB_LB_1,
- FFC_FB_LB_2 => FFC_FB_LB_2,
- FFC_FB_LB_3 => FFC_FB_LB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFS_CC_ORUN_0 => FFS_CC_ORUN_0,
- FFS_CC_ORUN_1 => FFS_CC_ORUN_1,
- FFS_CC_ORUN_2 => FFS_CC_ORUN_2,
- FFS_CC_ORUN_3 => FFS_CC_ORUN_3,
- FFS_CC_URUN_0 => FFS_CC_URUN_0,
- FFS_CC_URUN_1 => FFS_CC_URUN_1,
- FFS_CC_URUN_2 => FFS_CC_URUN_2,
- FFS_CC_URUN_3 => FFS_CC_URUN_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_CK_CORE_RX => FFC_CK_CORE_RX,
- BS4PAD_0 => BS4PAD_0,
- BS4PAD_1 => BS4PAD_1,
- BS4PAD_2 => BS4PAD_2,
- BS4PAD_3 => BS4PAD_3,
- RDATAO_7 => RDATAO_7,
- RDATAO_6 => RDATAO_6,
- RDATAO_5 => RDATAO_5,
- RDATAO_4 => RDATAO_4,
- RDATAO_3 => RDATAO_3,
- RDATAO_2 => RDATAO_2,
- RDATAO_1 => RDATAO_1,
- RDATAO_0 => RDATAO_0,
- INTO => INTO,
- ADDRI_7 => ADDRI_7,
- ADDRI_6 => ADDRI_6,
- ADDRI_5 => ADDRI_5,
- ADDRI_4 => ADDRI_4,
- ADDRI_3 => ADDRI_3,
- ADDRI_2 => ADDRI_2,
- ADDRI_1 => ADDRI_1,
- ADDRI_0 => ADDRI_0,
- WDATAI_7 => WDATAI_7,
- WDATAI_6 => WDATAI_6,
- WDATAI_5 => WDATAI_5,
- WDATAI_4 => WDATAI_4,
- WDATAI_3 => WDATAI_3,
- WDATAI_2 => WDATAI_2,
- WDATAI_1 => WDATAI_1,
- WDATAI_0 => WDATAI_0,
- RDI => RDI,
- WSTBI => WSTBI,
- CS_CHIF_0 => CS_CHIF_0,
- CS_CHIF_1 => CS_CHIF_1,
- CS_CHIF_2 => CS_CHIF_2,
- CS_CHIF_3 => CS_CHIF_3,
- CS_QIF => CS_QIF,
- QUAD_ID_1 => QUAD_ID_1,
- QUAD_ID_0 => QUAD_ID_0,
- FF_SYSCLK_P1 => FF_SYSCLK_P1,
- FF_SYSCLK0 => FF_SYSCLK0,
- FF_SYSCLK1 => FF_SYSCLK1,
- FF_SYSCLK2 => FF_SYSCLK2,
- FF_SYSCLK3 => FF_SYSCLK3,
- FF_RXCLK_P1 => FF_RXCLK_P1,
- FF_RXCLK_P2 => FF_RXCLK_P2,
- FF_RXCLK0 => FF_RXCLK0,
- FF_RXCLK1 => FF_RXCLK1,
- FF_RXCLK2 => FF_RXCLK2,
- FF_RXCLK3 => FF_RXCLK3,
- QUAD_CLK => QUAD_CLK,
- GRP_CLK_P1_3 => GRP_CLK_P1_3,
- GRP_CLK_P1_2 => GRP_CLK_P1_2,
- GRP_CLK_P1_1 => GRP_CLK_P1_1,
- GRP_CLK_P1_0 => GRP_CLK_P1_0,
- GRP_CLK_P2_3 => GRP_CLK_P2_3,
- GRP_CLK_P2_2 => GRP_CLK_P2_2,
- GRP_CLK_P2_1 => GRP_CLK_P2_1,
- GRP_CLK_P2_0 => GRP_CLK_P2_0,
- GRP_START_3 => GRP_START_3,
- GRP_START_2 => GRP_START_2,
- GRP_START_1 => GRP_START_1,
- GRP_START_0 => GRP_START_0,
- GRP_DONE_3 => GRP_DONE_3,
- GRP_DONE_2 => GRP_DONE_2,
- GRP_DONE_1 => GRP_DONE_1,
- GRP_DONE_0 => GRP_DONE_0,
- GRP_DESKEW_ERROR_3 => GRP_DESKEW_ERROR_3,
- GRP_DESKEW_ERROR_2 => GRP_DESKEW_ERROR_2,
- GRP_DESKEW_ERROR_1 => GRP_DESKEW_ERROR_1,
- GRP_DESKEW_ERROR_0 => GRP_DESKEW_ERROR_0,
- IQA_START_LS => IQA_START_LS,
- IQA_DONE_LS => IQA_DONE_LS,
- IQA_AND_FP1_LS => IQA_AND_FP1_LS,
- IQA_AND_FP0_LS => IQA_AND_FP0_LS,
- IQA_OR_FP1_LS => IQA_OR_FP1_LS,
- IQA_OR_FP0_LS => IQA_OR_FP0_LS,
- IQA_RST_N => IQA_RST_N,
- FF_TCLK0 => FF_TCLK0,
- FF_TCLK1 => FF_TCLK1,
- FF_TCLK2 => FF_TCLK2,
- FF_TCLK3 => FF_TCLK3,
- FF_RCLK0 => FF_RCLK0,
- FF_RCLK1 => FF_RCLK1,
- FF_RCLK2 => FF_RCLK2,
- FF_RCLK3 => FF_RCLK3,
- TCK_FMACP => TCK_FMACP,
- FF_TXD_0_23 => FF_TXD_0_23,
- FF_TXD_0_22 => FF_TXD_0_22,
- FF_TXD_0_21 => FF_TXD_0_21,
- FF_TXD_0_20 => FF_TXD_0_20,
- FF_TXD_0_19 => FF_TXD_0_19,
- FF_TXD_0_18 => FF_TXD_0_18,
- FF_TXD_0_17 => FF_TXD_0_17,
- FF_TXD_0_16 => FF_TXD_0_16,
- FF_TXD_0_15 => FF_TXD_0_15,
- FF_TXD_0_14 => FF_TXD_0_14,
- FF_TXD_0_13 => FF_TXD_0_13,
- FF_TXD_0_12 => FF_TXD_0_12,
- FF_TXD_0_11 => FF_TXD_0_11,
- FF_TXD_0_10 => FF_TXD_0_10,
- FF_TXD_0_9 => FF_TXD_0_9,
- FF_TXD_0_8 => FF_TXD_0_8,
- FF_TXD_0_7 => FF_TXD_0_7,
- FF_TXD_0_6 => FF_TXD_0_6,
- FF_TXD_0_5 => FF_TXD_0_5,
- FF_TXD_0_4 => FF_TXD_0_4,
- FF_TXD_0_3 => FF_TXD_0_3,
- FF_TXD_0_2 => FF_TXD_0_2,
- FF_TXD_0_1 => FF_TXD_0_1,
- FF_TXD_0_0 => FF_TXD_0_0,
- FB_RXD_0_23 => FB_RXD_0_23,
- FB_RXD_0_22 => FB_RXD_0_22,
- FB_RXD_0_21 => FB_RXD_0_21,
- FB_RXD_0_20 => FB_RXD_0_20,
- FB_RXD_0_19 => FB_RXD_0_19,
- FB_RXD_0_18 => FB_RXD_0_18,
- FB_RXD_0_17 => FB_RXD_0_17,
- FB_RXD_0_16 => FB_RXD_0_16,
- FB_RXD_0_15 => FB_RXD_0_15,
- FB_RXD_0_14 => FB_RXD_0_14,
- FB_RXD_0_13 => FB_RXD_0_13,
- FB_RXD_0_12 => FB_RXD_0_12,
- FB_RXD_0_11 => FB_RXD_0_11,
- FB_RXD_0_10 => FB_RXD_0_10,
- FB_RXD_0_9 => FB_RXD_0_9,
- FB_RXD_0_8 => FB_RXD_0_8,
- FB_RXD_0_7 => FB_RXD_0_7,
- FB_RXD_0_6 => FB_RXD_0_6,
- FB_RXD_0_5 => FB_RXD_0_5,
- FB_RXD_0_4 => FB_RXD_0_4,
- FB_RXD_0_3 => FB_RXD_0_3,
- FB_RXD_0_2 => FB_RXD_0_2,
- FB_RXD_0_1 => FB_RXD_0_1,
- FB_RXD_0_0 => FB_RXD_0_0,
- FF_TXD_1_23 => FF_TXD_1_23,
- FF_TXD_1_22 => FF_TXD_1_22,
- FF_TXD_1_21 => FF_TXD_1_21,
- FF_TXD_1_20 => FF_TXD_1_20,
- FF_TXD_1_19 => FF_TXD_1_19,
- FF_TXD_1_18 => FF_TXD_1_18,
- FF_TXD_1_17 => FF_TXD_1_17,
- FF_TXD_1_16 => FF_TXD_1_16,
- FF_TXD_1_15 => FF_TXD_1_15,
- FF_TXD_1_14 => FF_TXD_1_14,
- FF_TXD_1_13 => FF_TXD_1_13,
- FF_TXD_1_12 => FF_TXD_1_12,
- FF_TXD_1_11 => FF_TXD_1_11,
- FF_TXD_1_10 => FF_TXD_1_10,
- FF_TXD_1_9 => FF_TXD_1_9,
- FF_TXD_1_8 => FF_TXD_1_8,
- FF_TXD_1_7 => FF_TXD_1_7,
- FF_TXD_1_6 => FF_TXD_1_6,
- FF_TXD_1_5 => FF_TXD_1_5,
- FF_TXD_1_4 => FF_TXD_1_4,
- FF_TXD_1_3 => FF_TXD_1_3,
- FF_TXD_1_2 => FF_TXD_1_2,
- FF_TXD_1_1 => FF_TXD_1_1,
- FF_TXD_1_0 => FF_TXD_1_0,
- FB_RXD_1_23 => FB_RXD_1_23,
- FB_RXD_1_22 => FB_RXD_1_22,
- FB_RXD_1_21 => FB_RXD_1_21,
- FB_RXD_1_20 => FB_RXD_1_20,
- FB_RXD_1_19 => FB_RXD_1_19,
- FB_RXD_1_18 => FB_RXD_1_18,
- FB_RXD_1_17 => FB_RXD_1_17,
- FB_RXD_1_16 => FB_RXD_1_16,
- FB_RXD_1_15 => FB_RXD_1_15,
- FB_RXD_1_14 => FB_RXD_1_14,
- FB_RXD_1_13 => FB_RXD_1_13,
- FB_RXD_1_12 => FB_RXD_1_12,
- FB_RXD_1_11 => FB_RXD_1_11,
- FB_RXD_1_10 => FB_RXD_1_10,
- FB_RXD_1_9 => FB_RXD_1_9,
- FB_RXD_1_8 => FB_RXD_1_8,
- FB_RXD_1_7 => FB_RXD_1_7,
- FB_RXD_1_6 => FB_RXD_1_6,
- FB_RXD_1_5 => FB_RXD_1_5,
- FB_RXD_1_4 => FB_RXD_1_4,
- FB_RXD_1_3 => FB_RXD_1_3,
- FB_RXD_1_2 => FB_RXD_1_2,
- FB_RXD_1_1 => FB_RXD_1_1,
- FB_RXD_1_0 => FB_RXD_1_0,
- FF_TXD_2_23 => FF_TXD_2_23,
- FF_TXD_2_22 => FF_TXD_2_22,
- FF_TXD_2_21 => FF_TXD_2_21,
- FF_TXD_2_20 => FF_TXD_2_20,
- FF_TXD_2_19 => FF_TXD_2_19,
- FF_TXD_2_18 => FF_TXD_2_18,
- FF_TXD_2_17 => FF_TXD_2_17,
- FF_TXD_2_16 => FF_TXD_2_16,
- FF_TXD_2_15 => FF_TXD_2_15,
- FF_TXD_2_14 => FF_TXD_2_14,
- FF_TXD_2_13 => FF_TXD_2_13,
- FF_TXD_2_12 => FF_TXD_2_12,
- FF_TXD_2_11 => FF_TXD_2_11,
- FF_TXD_2_10 => FF_TXD_2_10,
- FF_TXD_2_9 => FF_TXD_2_9,
- FF_TXD_2_8 => FF_TXD_2_8,
- FF_TXD_2_7 => FF_TXD_2_7,
- FF_TXD_2_6 => FF_TXD_2_6,
- FF_TXD_2_5 => FF_TXD_2_5,
- FF_TXD_2_4 => FF_TXD_2_4,
- FF_TXD_2_3 => FF_TXD_2_3,
- FF_TXD_2_2 => FF_TXD_2_2,
- FF_TXD_2_1 => FF_TXD_2_1,
- FF_TXD_2_0 => FF_TXD_2_0,
- FB_RXD_2_23 => FB_RXD_2_23,
- FB_RXD_2_22 => FB_RXD_2_22,
- FB_RXD_2_21 => FB_RXD_2_21,
- FB_RXD_2_20 => FB_RXD_2_20,
- FB_RXD_2_19 => FB_RXD_2_19,
- FB_RXD_2_18 => FB_RXD_2_18,
- FB_RXD_2_17 => FB_RXD_2_17,
- FB_RXD_2_16 => FB_RXD_2_16,
- FB_RXD_2_15 => FB_RXD_2_15,
- FB_RXD_2_14 => FB_RXD_2_14,
- FB_RXD_2_13 => FB_RXD_2_13,
- FB_RXD_2_12 => FB_RXD_2_12,
- FB_RXD_2_11 => FB_RXD_2_11,
- FB_RXD_2_10 => FB_RXD_2_10,
- FB_RXD_2_9 => FB_RXD_2_9,
- FB_RXD_2_8 => FB_RXD_2_8,
- FB_RXD_2_7 => FB_RXD_2_7,
- FB_RXD_2_6 => FB_RXD_2_6,
- FB_RXD_2_5 => FB_RXD_2_5,
- FB_RXD_2_4 => FB_RXD_2_4,
- FB_RXD_2_3 => FB_RXD_2_3,
- FB_RXD_2_2 => FB_RXD_2_2,
- FB_RXD_2_1 => FB_RXD_2_1,
- FB_RXD_2_0 => FB_RXD_2_0,
- FF_TXD_3_23 => FF_TXD_3_23,
- FF_TXD_3_22 => FF_TXD_3_22,
- FF_TXD_3_21 => FF_TXD_3_21,
- FF_TXD_3_20 => FF_TXD_3_20,
- FF_TXD_3_19 => FF_TXD_3_19,
- FF_TXD_3_18 => FF_TXD_3_18,
- FF_TXD_3_17 => FF_TXD_3_17,
- FF_TXD_3_16 => FF_TXD_3_16,
- FF_TXD_3_15 => FF_TXD_3_15,
- FF_TXD_3_14 => FF_TXD_3_14,
- FF_TXD_3_13 => FF_TXD_3_13,
- FF_TXD_3_12 => FF_TXD_3_12,
- FF_TXD_3_11 => FF_TXD_3_11,
- FF_TXD_3_10 => FF_TXD_3_10,
- FF_TXD_3_9 => FF_TXD_3_9,
- FF_TXD_3_8 => FF_TXD_3_8,
- FF_TXD_3_7 => FF_TXD_3_7,
- FF_TXD_3_6 => FF_TXD_3_6,
- FF_TXD_3_5 => FF_TXD_3_5,
- FF_TXD_3_4 => FF_TXD_3_4,
- FF_TXD_3_3 => FF_TXD_3_3,
- FF_TXD_3_2 => FF_TXD_3_2,
- FF_TXD_3_1 => FF_TXD_3_1,
- FF_TXD_3_0 => FF_TXD_3_0,
- FB_RXD_3_23 => FB_RXD_3_23,
- FB_RXD_3_22 => FB_RXD_3_22,
- FB_RXD_3_21 => FB_RXD_3_21,
- FB_RXD_3_20 => FB_RXD_3_20,
- FB_RXD_3_19 => FB_RXD_3_19,
- FB_RXD_3_18 => FB_RXD_3_18,
- FB_RXD_3_17 => FB_RXD_3_17,
- FB_RXD_3_16 => FB_RXD_3_16,
- FB_RXD_3_15 => FB_RXD_3_15,
- FB_RXD_3_14 => FB_RXD_3_14,
- FB_RXD_3_13 => FB_RXD_3_13,
- FB_RXD_3_12 => FB_RXD_3_12,
- FB_RXD_3_11 => FB_RXD_3_11,
- FB_RXD_3_10 => FB_RXD_3_10,
- FB_RXD_3_9 => FB_RXD_3_9,
- FB_RXD_3_8 => FB_RXD_3_8,
- FB_RXD_3_7 => FB_RXD_3_7,
- FB_RXD_3_6 => FB_RXD_3_6,
- FB_RXD_3_5 => FB_RXD_3_5,
- FB_RXD_3_4 => FB_RXD_3_4,
- FB_RXD_3_3 => FB_RXD_3_3,
- FB_RXD_3_2 => FB_RXD_3_2,
- FB_RXD_3_1 => FB_RXD_3_1,
- FB_RXD_3_0 => FB_RXD_3_0,
- TCK_FMAC => TCK_FMAC,
- COUT_21 => COUT_21,
- COUT_20 => COUT_20,
- COUT_19 => COUT_19,
- COUT_18 => COUT_18,
- COUT_17 => COUT_17,
- COUT_16 => COUT_16,
- COUT_15 => COUT_15,
- COUT_14 => COUT_14,
- COUT_13 => COUT_13,
- COUT_12 => COUT_12,
- COUT_11 => COUT_11,
- COUT_10 => COUT_10,
- COUT_9 => COUT_9,
- COUT_8 => COUT_8,
- COUT_7 => COUT_7,
- COUT_6 => COUT_6,
- COUT_5 => COUT_5,
- COUT_4 => COUT_4,
- COUT_3 => COUT_3,
- COUT_2 => COUT_2,
- COUT_1 => COUT_1,
- COUT_0 => COUT_0,
- CIN_12 => CIN_12,
- CIN_11 => CIN_11,
- CIN_10 => CIN_10,
- CIN_9 => CIN_9,
- CIN_8 => CIN_8,
- CIN_7 => CIN_7,
- CIN_6 => CIN_6,
- CIN_5 => CIN_5,
- CIN_4 => CIN_4,
- CIN_3 => CIN_3,
- CIN_2 => CIN_2,
- CIN_1 => CIN_1,
- CIN_0 => CIN_0,
- TESTCLK_MACO => TESTCLK_MACO
-);
-
-end PCSA_arch;
-
---synopsys translate_on
-
---synopsys translate_off
-library SC;
-use SC.components.all;
---synopsys translate_on
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-
-entity serdes_fpga_ref_clk is
- GENERIC (USER_CONFIG_FILE : String := "serdes_fpga_ref_clk.txt");
- port (
--- serdes clk pins --
- rxrefclk, refclk : in std_logic;
- rxa_pclk, rxb_pclk : out std_logic;
- hdinp_0, hdinn_0 : in std_logic;
- hdoutp_0, hdoutn_0 : out std_logic;
- tclk_0, rclk_0 : in std_logic;
- tx_rst_0, rx_rst_0 : in std_logic;
- ref_0_sclk, rx_0_sclk : out std_logic;
- txd_0 : in std_logic_vector (15 downto 0);
- tx_k_0, tx_force_disp_0, tx_disp_sel_0 : in std_logic_vector (1 downto 0);
- rxd_0 : out std_logic_vector (15 downto 0);
- rx_k_0, rx_disp_err_detect_0, rx_cv_detect_0 : out std_logic_vector (1 downto 0);
- tx_crc_init_0 : in std_logic_vector (1 downto 0);
- rx_crc_eop_0 : out std_logic_vector (1 downto 0);
- word_align_en_0, mca_align_en_0, felb_0 : in std_logic;
- lsm_en_0 : in std_logic;
- lsm_status_0 : out std_logic;
-
- hdinp_1, hdinn_1 : in std_logic;
- hdoutp_1, hdoutn_1 : out std_logic;
- tclk_1, rclk_1 : in std_logic;
- tx_rst_1, rx_rst_1 : in std_logic;
- ref_1_sclk, rx_1_sclk : out std_logic;
- txd_1 : in std_logic_vector (15 downto 0);
- tx_k_1, tx_force_disp_1, tx_disp_sel_1 : in std_logic_vector (1 downto 0);
- rxd_1 : out std_logic_vector (15 downto 0);
- rx_k_1, rx_disp_err_detect_1, rx_cv_detect_1 : out std_logic_vector (1 downto 0);
- tx_crc_init_1 : in std_logic_vector (1 downto 0);
- rx_crc_eop_1 : out std_logic_vector (1 downto 0);
- word_align_en_1, mca_align_en_1, felb_1 : in std_logic;
- lsm_en_1 : in std_logic;
- lsm_status_1 : out std_logic;
-
- hdinp_2, hdinn_2 : in std_logic;
- hdoutp_2, hdoutn_2 : out std_logic;
- tclk_2, rclk_2 : in std_logic;
- tx_rst_2, rx_rst_2 : in std_logic;
- ref_2_sclk, rx_2_sclk : out std_logic;
- txd_2 : in std_logic_vector (15 downto 0);
- tx_k_2, tx_force_disp_2, tx_disp_sel_2 : in std_logic_vector (1 downto 0);
- rxd_2 : out std_logic_vector (15 downto 0);
- rx_k_2, rx_disp_err_detect_2, rx_cv_detect_2 : out std_logic_vector (1 downto 0);
- tx_crc_init_2 : in std_logic_vector (1 downto 0);
- rx_crc_eop_2 : out std_logic_vector (1 downto 0);
- word_align_en_2, mca_align_en_2, felb_2 : in std_logic;
- lsm_en_2 : in std_logic;
- lsm_status_2 : out std_logic;
-
- hdinp_3, hdinn_3 : in std_logic;
- hdoutp_3, hdoutn_3 : out std_logic;
- tclk_3, rclk_3 : in std_logic;
- tx_rst_3, rx_rst_3 : in std_logic;
- ref_3_sclk, rx_3_sclk : out std_logic;
- txd_3 : in std_logic_vector (15 downto 0);
- tx_k_3, tx_force_disp_3, tx_disp_sel_3 : in std_logic_vector (1 downto 0);
- rxd_3 : out std_logic_vector (15 downto 0);
- rx_k_3, rx_disp_err_detect_3, rx_cv_detect_3 : out std_logic_vector (1 downto 0);
- tx_crc_init_3 : in std_logic_vector (1 downto 0);
- rx_crc_eop_3 : out std_logic_vector (1 downto 0);
- word_align_en_3, mca_align_en_3, felb_3 : in std_logic;
- lsm_en_3 : in std_logic;
- lsm_status_3 : out std_logic;
- mca_resync_01 : in std_logic;
- mca_aligned_01, mca_inskew_01, mca_outskew_01 : out std_logic;
- mca_resync_23 : in std_logic;
- mca_aligned_23, mca_inskew_23, mca_outskew_23 : out std_logic;
- quad_rst, serdes_rst : in std_logic;
- ref_pclk : out std_logic);
-
-end serdes_fpga_ref_clk;
-
-architecture serdes_fpga_ref_clk_arch of serdes_fpga_ref_clk is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-component PCSA
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String
- );
---synopsys translate_on
-port (
- HDINP0 : in std_logic;
- HDINN0 : in std_logic;
- HDINP1 : in std_logic;
- HDINN1 : in std_logic;
- HDINP2 : in std_logic;
- HDINN2 : in std_logic;
- HDINP3 : in std_logic;
- HDINN3 : in std_logic;
- HDOUTP0 : out std_logic;
- HDOUTN0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTP3 : out std_logic;
- HDOUTN3 : out std_logic;
- REFCLKP : in std_logic;
- REFCLKN : in std_logic;
- RXREFCLKP : in std_logic;
- RXREFCLKN : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_MACRO_RST : in std_logic;
-
- FFC_LANE_TX_RST0 : in std_logic;
- FFC_LANE_TX_RST1 : in std_logic;
- FFC_LANE_TX_RST2 : in std_logic;
- FFC_LANE_TX_RST3 : in std_logic;
-
- FFC_LANE_RX_RST0 : in std_logic;
- FFC_LANE_RX_RST1 : in std_logic;
- FFC_LANE_RX_RST2 : in std_logic;
- FFC_LANE_RX_RST3 : in std_logic;
-
- FFC_PCIE_EI_EN_0 : in std_logic;
- FFC_PCIE_EI_EN_1 : in std_logic;
- FFC_PCIE_EI_EN_2 : in std_logic;
- FFC_PCIE_EI_EN_3 : in std_logic;
-
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
-
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
-
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
-
- FFC_PCIE_TX_0 : in std_logic;
- FFC_PCIE_TX_1 : in std_logic;
- FFC_PCIE_TX_2 : in std_logic;
- FFC_PCIE_TX_3 : in std_logic;
-
- FFC_PCIE_RX_0 : in std_logic;
- FFC_PCIE_RX_1 : in std_logic;
- FFC_PCIE_RX_2 : in std_logic;
- FFC_PCIE_RX_3 : in std_logic;
-
- FFC_SD_0 : in std_logic;
- FFC_SD_1 : in std_logic;
- FFC_SD_2 : in std_logic;
- FFC_SD_3 : in std_logic;
-
- FFC_EN_CGA_0 : in std_logic;
- FFC_EN_CGA_1 : in std_logic;
- FFC_EN_CGA_2 : in std_logic;
- FFC_EN_CGA_3 : in std_logic;
-
- FFC_ALIGN_EN_0 : in std_logic;
- FFC_ALIGN_EN_1 : in std_logic;
- FFC_ALIGN_EN_2 : in std_logic;
- FFC_ALIGN_EN_3 : in std_logic;
-
- FFC_AB_RESET : in std_logic;
- FFC_CD_RESET : in std_logic;
-
- FFS_LS_STATUS_0 : out std_logic;
- FFS_LS_STATUS_1 : out std_logic;
- FFS_LS_STATUS_2 : out std_logic;
- FFS_LS_STATUS_3 : out std_logic;
-
- FFS_AB_STATUS : out std_logic;
- FFS_CD_STATUS : out std_logic;
-
- FFS_AB_ALIGNED : out std_logic;
- FFS_CD_ALIGNED : out std_logic;
-
- FFS_AB_FAILED : out std_logic;
- FFS_CD_FAILED : out std_logic;
-
- FFS_RLOS_LO0 : out std_logic;
- FFS_RLOS_LO1 : out std_logic;
- FFS_RLOS_LO2 : out std_logic;
- FFS_RLOS_LO3 : out std_logic;
-
- FFC_FB_LB_0 : in std_logic;
- FFC_FB_LB_1 : in std_logic;
- FFC_FB_LB_2 : in std_logic;
- FFC_FB_LB_3 : in std_logic;
-
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
-
- FFS_CC_ORUN_0 : out std_logic;
- FFS_CC_ORUN_1 : out std_logic;
- FFS_CC_ORUN_2 : out std_logic;
- FFS_CC_ORUN_3 : out std_logic;
-
- FFS_CC_URUN_0 : out std_logic;
- FFS_CC_URUN_1 : out std_logic;
- FFS_CC_URUN_2 : out std_logic;
- FFS_CC_URUN_3 : out std_logic;
-
- FFC_CK_CORE_TX : in std_logic;
- FFC_CK_CORE_RX : in std_logic;
- RDATAO_7 : out std_logic;
- RDATAO_6 : out std_logic;
- RDATAO_5 : out std_logic;
- RDATAO_4 : out std_logic;
- RDATAO_3 : out std_logic;
- RDATAO_2 : out std_logic;
- RDATAO_1 : out std_logic;
- RDATAO_0 : out std_logic;
- INTO : out std_logic;
-
- ADDRI_7 : in std_logic;
- ADDRI_6 : in std_logic;
- ADDRI_5 : in std_logic;
- ADDRI_4 : in std_logic;
- ADDRI_3 : in std_logic;
- ADDRI_2 : in std_logic;
- ADDRI_1 : in std_logic;
- ADDRI_0 : in std_logic;
- WDATAI_7 : in std_logic;
- WDATAI_6 : in std_logic;
- WDATAI_5 : in std_logic;
- WDATAI_4 : in std_logic;
- WDATAI_3 : in std_logic;
- WDATAI_2 : in std_logic;
- WDATAI_1 : in std_logic;
- WDATAI_0 : in std_logic;
- RDI : in std_logic;
- WSTBI : in std_logic;
-
- CS_CHIF_0 : in std_logic;
- CS_CHIF_1 : in std_logic;
- CS_CHIF_2 : in std_logic;
- CS_CHIF_3 : in std_logic;
- CS_QIF : in std_logic;
-
- QUAD_ID_1 : in std_logic;
- QUAD_ID_0 : in std_logic;
-
- FF_SYSCLK_P1 : out std_logic;
-
- FF_SYSCLK0 : out std_logic;
- FF_SYSCLK1 : out std_logic;
- FF_SYSCLK2 : out std_logic;
- FF_SYSCLK3 : out std_logic;
-
- FF_RXCLK_P1 : out std_logic;
- FF_RXCLK_P2 : out std_logic;
-
- FF_RXCLK0 : out std_logic;
- FF_RXCLK1 : out std_logic;
- FF_RXCLK2 : out std_logic;
- FF_RXCLK3 : out std_logic;
-
- QUAD_CLK : out std_logic;
-
- GRP_CLK_P1_3 : in std_logic;
- GRP_CLK_P1_2 : in std_logic;
- GRP_CLK_P1_1 : in std_logic;
- GRP_CLK_P1_0 : in std_logic;
-
- GRP_CLK_P2_3 : in std_logic;
- GRP_CLK_P2_2 : in std_logic;
- GRP_CLK_P2_1 : in std_logic;
- GRP_CLK_P2_0 : in std_logic;
-
- GRP_START_3 : in std_logic;
- GRP_START_2 : in std_logic;
- GRP_START_1 : in std_logic;
- GRP_START_0 : in std_logic;
-
- GRP_DONE_3 : in std_logic;
- GRP_DONE_2 : in std_logic;
- GRP_DONE_1 : in std_logic;
- GRP_DONE_0 : in std_logic;
-
- GRP_DESKEW_ERROR_3 : in std_logic;
- GRP_DESKEW_ERROR_2 : in std_logic;
- GRP_DESKEW_ERROR_1 : in std_logic;
- GRP_DESKEW_ERROR_0 : in std_logic;
-
- IQA_START_LS : out std_logic;
- IQA_DONE_LS : out std_logic;
- IQA_AND_FP1_LS : out std_logic;
- IQA_AND_FP0_LS : out std_logic;
- IQA_OR_FP1_LS : out std_logic;
- IQA_OR_FP0_LS : out std_logic;
- IQA_RST_N : out std_logic;
-
- FF_TCLK0 : in std_logic;
- FF_TCLK1 : in std_logic;
- FF_TCLK2 : in std_logic;
- FF_TCLK3 : in std_logic;
-
- FF_RCLK0 : in std_logic;
- FF_RCLK1 : in std_logic;
- FF_RCLK2 : in std_logic;
- FF_RCLK3 : in std_logic;
- TCK_FMACP : in std_logic;
-
- FF_TXD_0_23 : in std_logic;
- FF_TXD_0_22 : in std_logic;
- FF_TXD_0_21 : in std_logic;
- FF_TXD_0_20 : in std_logic;
- FF_TXD_0_19 : in std_logic;
- FF_TXD_0_18 : in std_logic;
- FF_TXD_0_17 : in std_logic;
- FF_TXD_0_16 : in std_logic;
- FF_TXD_0_15 : in std_logic;
- FF_TXD_0_14 : in std_logic;
- FF_TXD_0_13 : in std_logic;
- FF_TXD_0_12 : in std_logic;
- FF_TXD_0_11 : in std_logic;
- FF_TXD_0_10 : in std_logic;
- FF_TXD_0_9 : in std_logic;
- FF_TXD_0_8 : in std_logic;
- FF_TXD_0_7 : in std_logic;
- FF_TXD_0_6 : in std_logic;
- FF_TXD_0_5 : in std_logic;
- FF_TXD_0_4 : in std_logic;
- FF_TXD_0_3 : in std_logic;
- FF_TXD_0_2 : in std_logic;
- FF_TXD_0_1 : in std_logic;
- FF_TXD_0_0 : in std_logic;
- FB_RXD_0_23 : out std_logic;
- FB_RXD_0_22 : out std_logic;
- FB_RXD_0_21 : out std_logic;
- FB_RXD_0_20 : out std_logic;
- FB_RXD_0_19 : out std_logic;
- FB_RXD_0_18 : out std_logic;
- FB_RXD_0_17 : out std_logic;
- FB_RXD_0_16 : out std_logic;
- FB_RXD_0_15 : out std_logic;
- FB_RXD_0_14 : out std_logic;
- FB_RXD_0_13 : out std_logic;
- FB_RXD_0_12 : out std_logic;
- FB_RXD_0_11 : out std_logic;
- FB_RXD_0_10 : out std_logic;
- FB_RXD_0_9 : out std_logic;
- FB_RXD_0_8 : out std_logic;
- FB_RXD_0_7 : out std_logic;
- FB_RXD_0_6 : out std_logic;
- FB_RXD_0_5 : out std_logic;
- FB_RXD_0_4 : out std_logic;
- FB_RXD_0_3 : out std_logic;
- FB_RXD_0_2 : out std_logic;
- FB_RXD_0_1 : out std_logic;
- FB_RXD_0_0 : out std_logic;
- FF_TXD_1_23 : in std_logic;
- FF_TXD_1_22 : in std_logic;
- FF_TXD_1_21 : in std_logic;
- FF_TXD_1_20 : in std_logic;
- FF_TXD_1_19 : in std_logic;
- FF_TXD_1_18 : in std_logic;
- FF_TXD_1_17 : in std_logic;
- FF_TXD_1_16 : in std_logic;
- FF_TXD_1_15 : in std_logic;
- FF_TXD_1_14 : in std_logic;
- FF_TXD_1_13 : in std_logic;
- FF_TXD_1_12 : in std_logic;
- FF_TXD_1_11 : in std_logic;
- FF_TXD_1_10 : in std_logic;
- FF_TXD_1_9 : in std_logic;
- FF_TXD_1_8 : in std_logic;
- FF_TXD_1_7 : in std_logic;
- FF_TXD_1_6 : in std_logic;
- FF_TXD_1_5 : in std_logic;
- FF_TXD_1_4 : in std_logic;
- FF_TXD_1_3 : in std_logic;
- FF_TXD_1_2 : in std_logic;
- FF_TXD_1_1 : in std_logic;
- FF_TXD_1_0 : in std_logic;
- FB_RXD_1_23 : out std_logic;
- FB_RXD_1_22 : out std_logic;
- FB_RXD_1_21 : out std_logic;
- FB_RXD_1_20 : out std_logic;
- FB_RXD_1_19 : out std_logic;
- FB_RXD_1_18 : out std_logic;
- FB_RXD_1_17 : out std_logic;
- FB_RXD_1_16 : out std_logic;
- FB_RXD_1_15 : out std_logic;
- FB_RXD_1_14 : out std_logic;
- FB_RXD_1_13 : out std_logic;
- FB_RXD_1_12 : out std_logic;
- FB_RXD_1_11 : out std_logic;
- FB_RXD_1_10 : out std_logic;
- FB_RXD_1_9 : out std_logic;
- FB_RXD_1_8 : out std_logic;
- FB_RXD_1_7 : out std_logic;
- FB_RXD_1_6 : out std_logic;
- FB_RXD_1_5 : out std_logic;
- FB_RXD_1_4 : out std_logic;
- FB_RXD_1_3 : out std_logic;
- FB_RXD_1_2 : out std_logic;
- FB_RXD_1_1 : out std_logic;
- FB_RXD_1_0 : out std_logic;
- FF_TXD_2_23 : in std_logic;
- FF_TXD_2_22 : in std_logic;
- FF_TXD_2_21 : in std_logic;
- FF_TXD_2_20 : in std_logic;
- FF_TXD_2_19 : in std_logic;
- FF_TXD_2_18 : in std_logic;
- FF_TXD_2_17 : in std_logic;
- FF_TXD_2_16 : in std_logic;
- FF_TXD_2_15 : in std_logic;
- FF_TXD_2_14 : in std_logic;
- FF_TXD_2_13 : in std_logic;
- FF_TXD_2_12 : in std_logic;
- FF_TXD_2_11 : in std_logic;
- FF_TXD_2_10 : in std_logic;
- FF_TXD_2_9 : in std_logic;
- FF_TXD_2_8 : in std_logic;
- FF_TXD_2_7 : in std_logic;
- FF_TXD_2_6 : in std_logic;
- FF_TXD_2_5 : in std_logic;
- FF_TXD_2_4 : in std_logic;
- FF_TXD_2_3 : in std_logic;
- FF_TXD_2_2 : in std_logic;
- FF_TXD_2_1 : in std_logic;
- FF_TXD_2_0 : in std_logic;
- FB_RXD_2_23 : out std_logic;
- FB_RXD_2_22 : out std_logic;
- FB_RXD_2_21 : out std_logic;
- FB_RXD_2_20 : out std_logic;
- FB_RXD_2_19 : out std_logic;
- FB_RXD_2_18 : out std_logic;
- FB_RXD_2_17 : out std_logic;
- FB_RXD_2_16 : out std_logic;
- FB_RXD_2_15 : out std_logic;
- FB_RXD_2_14 : out std_logic;
- FB_RXD_2_13 : out std_logic;
- FB_RXD_2_12 : out std_logic;
- FB_RXD_2_11 : out std_logic;
- FB_RXD_2_10 : out std_logic;
- FB_RXD_2_9 : out std_logic;
- FB_RXD_2_8 : out std_logic;
- FB_RXD_2_7 : out std_logic;
- FB_RXD_2_6 : out std_logic;
- FB_RXD_2_5 : out std_logic;
- FB_RXD_2_4 : out std_logic;
- FB_RXD_2_3 : out std_logic;
- FB_RXD_2_2 : out std_logic;
- FB_RXD_2_1 : out std_logic;
- FB_RXD_2_0 : out std_logic;
- FF_TXD_3_23 : in std_logic;
- FF_TXD_3_22 : in std_logic;
- FF_TXD_3_21 : in std_logic;
- FF_TXD_3_20 : in std_logic;
- FF_TXD_3_19 : in std_logic;
- FF_TXD_3_18 : in std_logic;
- FF_TXD_3_17 : in std_logic;
- FF_TXD_3_16 : in std_logic;
- FF_TXD_3_15 : in std_logic;
- FF_TXD_3_14 : in std_logic;
- FF_TXD_3_13 : in std_logic;
- FF_TXD_3_12 : in std_logic;
- FF_TXD_3_11 : in std_logic;
- FF_TXD_3_10 : in std_logic;
- FF_TXD_3_9 : in std_logic;
- FF_TXD_3_8 : in std_logic;
- FF_TXD_3_7 : in std_logic;
- FF_TXD_3_6 : in std_logic;
- FF_TXD_3_5 : in std_logic;
- FF_TXD_3_4 : in std_logic;
- FF_TXD_3_3 : in std_logic;
- FF_TXD_3_2 : in std_logic;
- FF_TXD_3_1 : in std_logic;
- FF_TXD_3_0 : in std_logic;
- FB_RXD_3_23 : out std_logic;
- FB_RXD_3_22 : out std_logic;
- FB_RXD_3_21 : out std_logic;
- FB_RXD_3_20 : out std_logic;
- FB_RXD_3_19 : out std_logic;
- FB_RXD_3_18 : out std_logic;
- FB_RXD_3_17 : out std_logic;
- FB_RXD_3_16 : out std_logic;
- FB_RXD_3_15 : out std_logic;
- FB_RXD_3_14 : out std_logic;
- FB_RXD_3_13 : out std_logic;
- FB_RXD_3_12 : out std_logic;
- FB_RXD_3_11 : out std_logic;
- FB_RXD_3_10 : out std_logic;
- FB_RXD_3_9 : out std_logic;
- FB_RXD_3_8 : out std_logic;
- FB_RXD_3_7 : out std_logic;
- FB_RXD_3_6 : out std_logic;
- FB_RXD_3_5 : out std_logic;
- FB_RXD_3_4 : out std_logic;
- FB_RXD_3_3 : out std_logic;
- FB_RXD_3_2 : out std_logic;
- FB_RXD_3_1 : out std_logic;
- FB_RXD_3_0 : out std_logic;
- TCK_FMAC : out std_logic;
- BS4PAD_0 : out std_logic;
- BS4PAD_1 : out std_logic;
- BS4PAD_2 : out std_logic;
- BS4PAD_3 : out std_logic;
- COUT_21 : out std_logic;
- COUT_20 : out std_logic;
- COUT_19 : out std_logic;
- COUT_18 : out std_logic;
- COUT_17 : out std_logic;
- COUT_16 : out std_logic;
- COUT_15 : out std_logic;
- COUT_14 : out std_logic;
- COUT_13 : out std_logic;
- COUT_12 : out std_logic;
- COUT_11 : out std_logic;
- COUT_10 : out std_logic;
- COUT_9 : out std_logic;
- COUT_8 : out std_logic;
- COUT_7 : out std_logic;
- COUT_6 : out std_logic;
- COUT_5 : out std_logic;
- COUT_4 : out std_logic;
- COUT_3 : out std_logic;
- COUT_2 : out std_logic;
- COUT_1 : out std_logic;
- COUT_0 : out std_logic;
- CIN_12 : in std_logic;
- CIN_11 : in std_logic;
- CIN_10 : in std_logic;
- CIN_9 : in std_logic;
- CIN_8 : in std_logic;
- CIN_7 : in std_logic;
- CIN_6 : in std_logic;
- CIN_5 : in std_logic;
- CIN_4 : in std_logic;
- CIN_3 : in std_logic;
- CIN_2 : in std_logic;
- CIN_1 : in std_logic;
- CIN_0 : in std_logic;
- TESTCLK_MACO : in std_logic
-);
-end component;
- attribute IS_ASB: string;
- attribute IS_ASB of PCSA_INST : label is "or5s00/data/or5s00.acd";
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSA_INST : label is USER_CONFIG_FILE;
- attribute CH0_RX_MAXRATE: string;
- attribute CH0_RX_MAXRATE of PCSA_INST : label is "RXF3";
- attribute CH1_RX_MAXRATE: string;
- attribute CH1_RX_MAXRATE of PCSA_INST : label is "RXF3";
- attribute CH2_RX_MAXRATE: string;
- attribute CH2_RX_MAXRATE of PCSA_INST : label is "RXF3";
- attribute CH3_RX_MAXRATE: string;
- attribute CH3_RX_MAXRATE of PCSA_INST : label is "RXF3";
- attribute CH0_TX_MAXRATE: string;
- attribute CH0_TX_MAXRATE of PCSA_INST : label is "TXF2";
- attribute CH1_TX_MAXRATE: string;
- attribute CH1_TX_MAXRATE of PCSA_INST : label is "TXF2";
- attribute CH2_TX_MAXRATE: string;
- attribute CH2_TX_MAXRATE of PCSA_INST : label is "TXF2";
- attribute CH3_TX_MAXRATE: string;
- attribute CH3_TX_MAXRATE of PCSA_INST : label is "TXF2";
- attribute AMP_BOOST: string;
- attribute AMP_BOOST of PCSA_INST : label is "DISABLED";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSA : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN, RXREFCLKP, RXREFCLKN";
-
-signal fpsc_vlo : std_logic := '0';
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-
--- pcs_quad instance
-PCSA_INST : PCSA
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE)
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
- RXREFCLKP => fpsc_vlo,
- RXREFCLKN => fpsc_vlo,
- FFC_CK_CORE_RX => rxrefclk,
- FFC_CK_CORE_TX => refclk,
- CS_CHIF_0 => fpsc_vlo,
- CS_CHIF_1 => fpsc_vlo,
- CS_CHIF_2 => fpsc_vlo,
- CS_CHIF_3 => fpsc_vlo,
- CS_QIF => fpsc_vlo,
- QUAD_ID_0 => fpsc_vlo,
- QUAD_ID_1 => fpsc_vlo,
- ADDRI_0 => fpsc_vlo,
- ADDRI_1 => fpsc_vlo,
- ADDRI_2 => fpsc_vlo,
- ADDRI_3 => fpsc_vlo,
- ADDRI_4 => fpsc_vlo,
- ADDRI_5 => fpsc_vlo,
- ADDRI_6 => fpsc_vlo,
- ADDRI_7 => fpsc_vlo,
- WDATAI_0 => fpsc_vlo,
- WDATAI_1 => fpsc_vlo,
- WDATAI_2 => fpsc_vlo,
- WDATAI_3 => fpsc_vlo,
- WDATAI_4 => fpsc_vlo,
- WDATAI_5 => fpsc_vlo,
- WDATAI_6 => fpsc_vlo,
- WDATAI_7 => fpsc_vlo,
- RDI => fpsc_vlo,
- WSTBI => fpsc_vlo,
- GRP_CLK_P1_0 => fpsc_vlo,
- GRP_CLK_P1_1 => fpsc_vlo,
- GRP_CLK_P1_2 => fpsc_vlo,
- GRP_CLK_P1_3 => fpsc_vlo,
- GRP_CLK_P2_0 => fpsc_vlo,
- GRP_CLK_P2_1 => fpsc_vlo,
- GRP_CLK_P2_2 => fpsc_vlo,
- GRP_CLK_P2_3 => fpsc_vlo,
- GRP_START_0 => fpsc_vlo,
- GRP_START_1 => fpsc_vlo,
- GRP_START_2 => fpsc_vlo,
- GRP_START_3 => fpsc_vlo,
- GRP_DONE_0 => fpsc_vlo,
- GRP_DONE_1 => fpsc_vlo,
- GRP_DONE_2 => fpsc_vlo,
- GRP_DONE_3 => fpsc_vlo,
- GRP_DESKEW_ERROR_0 => fpsc_vlo,
- GRP_DESKEW_ERROR_1 => fpsc_vlo,
- GRP_DESKEW_ERROR_2 => fpsc_vlo,
- GRP_DESKEW_ERROR_3 => fpsc_vlo,
--- to sysbusa
- RDATAO_0 => open,
- RDATAO_1 => open,
- RDATAO_2 => open,
- RDATAO_3 => open,
- RDATAO_4 => open,
- RDATAO_5 => open,
- RDATAO_6 => open,
- RDATAO_7 => open,
- INTO => open,
- QUAD_CLK => open,
- IQA_START_LS => open,
- IQA_DONE_LS => open,
- IQA_AND_FP1_LS => open,
- IQA_AND_FP0_LS => open,
- IQA_OR_FP1_LS => open,
- IQA_OR_FP0_LS => open,
- IQA_RST_N => open,
-
- FF_TXD_0_19 => txd_0(15),
- FF_TXD_0_18 => txd_0(14),
- FF_TXD_0_17 => txd_0(13),
- FF_TXD_0_16 => txd_0(12),
- FF_TXD_0_15 => txd_0(11),
- FF_TXD_0_14 => txd_0(10),
- FF_TXD_0_13 => txd_0(9),
- FF_TXD_0_12 => txd_0(8),
- FF_TXD_0_7 => txd_0(7),
- FF_TXD_0_6 => txd_0(6),
- FF_TXD_0_5 => txd_0(5),
- FF_TXD_0_4 => txd_0(4),
- FF_TXD_0_3 => txd_0(3),
- FF_TXD_0_2 => txd_0(2),
- FF_TXD_0_1 => txd_0(1),
- FF_TXD_0_0 => txd_0(0),
- FB_RXD_0_19 => rxd_0(15),
- FB_RXD_0_18 => rxd_0(14),
- FB_RXD_0_17 => rxd_0(13),
- FB_RXD_0_16 => rxd_0(12),
- FB_RXD_0_15 => rxd_0(11),
- FB_RXD_0_14 => rxd_0(10),
- FB_RXD_0_13 => rxd_0(9),
- FB_RXD_0_12 => rxd_0(8),
- FB_RXD_0_7 => rxd_0(7),
- FB_RXD_0_6 => rxd_0(6),
- FB_RXD_0_5 => rxd_0(5),
- FB_RXD_0_4 => rxd_0(4),
- FB_RXD_0_3 => rxd_0(3),
- FB_RXD_0_2 => rxd_0(2),
- FB_RXD_0_1 => rxd_0(1),
- FB_RXD_0_0 => rxd_0(0),
-
- FF_TXD_0_20 => tx_k_0(1),
- FF_TXD_0_8 => tx_k_0(0),
- FB_RXD_0_20 => rx_k_0(1),
- FB_RXD_0_8 => rx_k_0(0),
-
- FF_TXD_0_21 => tx_force_disp_0(1),
- FF_TXD_0_9 => tx_force_disp_0(0),
-
- FF_TXD_0_22 => tx_disp_sel_0(1),
- FF_TXD_0_10 => tx_disp_sel_0(0),
-
- FF_TXD_0_23 => tx_crc_init_0(1),
- FF_TXD_0_11 => tx_crc_init_0(0),
-
- FB_RXD_0_21 => rx_disp_err_detect_0(1),
- FB_RXD_0_9 => rx_disp_err_detect_0(0),
-
- FB_RXD_0_22 => rx_cv_detect_0(1),
- FB_RXD_0_10 => rx_cv_detect_0(0),
-
- FB_RXD_0_23 => rx_crc_eop_0(1),
- FB_RXD_0_11 => rx_crc_eop_0(0),
-
- FF_TXD_1_19 => txd_1(15),
- FF_TXD_1_18 => txd_1(14),
- FF_TXD_1_17 => txd_1(13),
- FF_TXD_1_16 => txd_1(12),
- FF_TXD_1_15 => txd_1(11),
- FF_TXD_1_14 => txd_1(10),
- FF_TXD_1_13 => txd_1(9),
- FF_TXD_1_12 => txd_1(8),
- FF_TXD_1_7 => txd_1(7),
- FF_TXD_1_6 => txd_1(6),
- FF_TXD_1_5 => txd_1(5),
- FF_TXD_1_4 => txd_1(4),
- FF_TXD_1_3 => txd_1(3),
- FF_TXD_1_2 => txd_1(2),
- FF_TXD_1_1 => txd_1(1),
- FF_TXD_1_0 => txd_1(0),
- FB_RXD_1_19 => rxd_1(15),
- FB_RXD_1_18 => rxd_1(14),
- FB_RXD_1_17 => rxd_1(13),
- FB_RXD_1_16 => rxd_1(12),
- FB_RXD_1_15 => rxd_1(11),
- FB_RXD_1_14 => rxd_1(10),
- FB_RXD_1_13 => rxd_1(9),
- FB_RXD_1_12 => rxd_1(8),
- FB_RXD_1_7 => rxd_1(7),
- FB_RXD_1_6 => rxd_1(6),
- FB_RXD_1_5 => rxd_1(5),
- FB_RXD_1_4 => rxd_1(4),
- FB_RXD_1_3 => rxd_1(3),
- FB_RXD_1_2 => rxd_1(2),
- FB_RXD_1_1 => rxd_1(1),
- FB_RXD_1_0 => rxd_1(0),
-
- FF_TXD_1_20 => tx_k_1(1),
- FF_TXD_1_8 => tx_k_1(0),
- FB_RXD_1_20 => rx_k_1(1),
- FB_RXD_1_8 => rx_k_1(0),
-
- FF_TXD_1_21 => tx_force_disp_1(1),
- FF_TXD_1_9 => tx_force_disp_1(0),
-
- FF_TXD_1_22 => tx_disp_sel_1(1),
- FF_TXD_1_10 => tx_disp_sel_1(0),
- FF_TXD_1_23 => tx_crc_init_1(1),
- FF_TXD_1_11 => tx_crc_init_1(0),
-
- FB_RXD_1_21 => rx_disp_err_detect_1(1),
- FB_RXD_1_9 => rx_disp_err_detect_1(0),
-
- FB_RXD_1_22 => rx_cv_detect_1(1),
- FB_RXD_1_10 => rx_cv_detect_1(0),
-
- FB_RXD_1_23 => rx_crc_eop_1(1),
- FB_RXD_1_11 => rx_crc_eop_1(0),
-
- FF_TXD_2_19 => txd_2(15),
- FF_TXD_2_18 => txd_2(14),
- FF_TXD_2_17 => txd_2(13),
- FF_TXD_2_16 => txd_2(12),
- FF_TXD_2_15 => txd_2(11),
- FF_TXD_2_14 => txd_2(10),
- FF_TXD_2_13 => txd_2(9),
- FF_TXD_2_12 => txd_2(8),
- FF_TXD_2_7 => txd_2(7),
- FF_TXD_2_6 => txd_2(6),
- FF_TXD_2_5 => txd_2(5),
- FF_TXD_2_4 => txd_2(4),
- FF_TXD_2_3 => txd_2(3),
- FF_TXD_2_2 => txd_2(2),
- FF_TXD_2_1 => txd_2(1),
- FF_TXD_2_0 => txd_2(0),
- FB_RXD_2_19 => rxd_2(15),
- FB_RXD_2_18 => rxd_2(14),
- FB_RXD_2_17 => rxd_2(13),
- FB_RXD_2_16 => rxd_2(12),
- FB_RXD_2_15 => rxd_2(11),
- FB_RXD_2_14 => rxd_2(10),
- FB_RXD_2_13 => rxd_2(9),
- FB_RXD_2_12 => rxd_2(8),
- FB_RXD_2_7 => rxd_2(7),
- FB_RXD_2_6 => rxd_2(6),
- FB_RXD_2_5 => rxd_2(5),
- FB_RXD_2_4 => rxd_2(4),
- FB_RXD_2_3 => rxd_2(3),
- FB_RXD_2_2 => rxd_2(2),
- FB_RXD_2_1 => rxd_2(1),
- FB_RXD_2_0 => rxd_2(0),
-
- FF_TXD_2_20 => tx_k_2(1),
- FF_TXD_2_8 => tx_k_2(0),
- FB_RXD_2_20 => rx_k_2(1),
- FB_RXD_2_8 => rx_k_2(0),
-
- FF_TXD_2_21 => tx_force_disp_2(1),
- FF_TXD_2_9 => tx_force_disp_2(0),
-
- FF_TXD_2_22 => tx_disp_sel_2(1),
- FF_TXD_2_10 => tx_disp_sel_2(0),
- FF_TXD_2_23 => tx_crc_init_2(1),
- FF_TXD_2_11 => tx_crc_init_2(0),
-
- FB_RXD_2_21 => rx_disp_err_detect_2(1),
- FB_RXD_2_9 => rx_disp_err_detect_2(0),
-
- FB_RXD_2_22 => rx_cv_detect_2(1),
- FB_RXD_2_10 => rx_cv_detect_2(0),
-
- FB_RXD_2_23 => rx_crc_eop_2(1),
- FB_RXD_2_11 => rx_crc_eop_2(0),
-
- FF_TXD_3_19 => txd_3(15),
- FF_TXD_3_18 => txd_3(14),
- FF_TXD_3_17 => txd_3(13),
- FF_TXD_3_16 => txd_3(12),
- FF_TXD_3_15 => txd_3(11),
- FF_TXD_3_14 => txd_3(10),
- FF_TXD_3_13 => txd_3(9),
- FF_TXD_3_12 => txd_3(8),
- FF_TXD_3_7 => txd_3(7),
- FF_TXD_3_6 => txd_3(6),
- FF_TXD_3_5 => txd_3(5),
- FF_TXD_3_4 => txd_3(4),
- FF_TXD_3_3 => txd_3(3),
- FF_TXD_3_2 => txd_3(2),
- FF_TXD_3_1 => txd_3(1),
- FF_TXD_3_0 => txd_3(0),
- FB_RXD_3_19 => rxd_3(15),
- FB_RXD_3_18 => rxd_3(14),
- FB_RXD_3_17 => rxd_3(13),
- FB_RXD_3_16 => rxd_3(12),
- FB_RXD_3_15 => rxd_3(11),
- FB_RXD_3_14 => rxd_3(10),
- FB_RXD_3_13 => rxd_3(9),
- FB_RXD_3_12 => rxd_3(8),
- FB_RXD_3_7 => rxd_3(7),
- FB_RXD_3_6 => rxd_3(6),
- FB_RXD_3_5 => rxd_3(5),
- FB_RXD_3_4 => rxd_3(4),
- FB_RXD_3_3 => rxd_3(3),
- FB_RXD_3_2 => rxd_3(2),
- FB_RXD_3_1 => rxd_3(1),
- FB_RXD_3_0 => rxd_3(0),
-
- FF_TXD_3_20 => tx_k_3(1),
- FF_TXD_3_8 => tx_k_3(0),
- FB_RXD_3_20 => rx_k_3(1),
- FB_RXD_3_8 => rx_k_3(0),
-
- FF_TXD_3_21 => tx_force_disp_3(1),
- FF_TXD_3_9 => tx_force_disp_3(0),
-
- FF_TXD_3_22 => tx_disp_sel_3(1),
- FF_TXD_3_10 => tx_disp_sel_3(0),
- FF_TXD_3_23 => tx_crc_init_3(1),
- FF_TXD_3_11 => tx_crc_init_3(0),
-
- FB_RXD_3_21 => rx_disp_err_detect_3(1),
- FB_RXD_3_9 => rx_disp_err_detect_3(0),
-
- FB_RXD_3_22 => rx_cv_detect_3(1),
- FB_RXD_3_10 => rx_cv_detect_3(0),
-
- FB_RXD_3_23 => rx_crc_eop_3(1),
- FB_RXD_3_11 => rx_crc_eop_3(0),
-
- HDINP0 => hdinp_0,
- HDINN0 => hdinn_0,
- HDOUTP0 => hdoutp_0,
- HDOUTN0 => hdoutn_0,
- FF_SYSCLK0 => ref_0_sclk,
- FF_RXCLK0 => rx_0_sclk,
- FFC_LANE_TX_RST0 => tx_rst_0,
- FFC_LANE_RX_RST0 => rx_rst_0,
- FF_TCLK0 => tclk_0,
- FF_RCLK0 => rclk_0,
- HDINP1 => hdinp_1,
- HDINN1 => hdinn_1,
- HDOUTP1 => hdoutp_1,
- HDOUTN1 => hdoutn_1,
- FF_SYSCLK1 => ref_1_sclk,
- FF_RXCLK1 => rx_1_sclk,
- FFC_LANE_TX_RST1 => tx_rst_1,
- FFC_LANE_RX_RST1 => rx_rst_1,
- FF_TCLK1 => tclk_1,
- FF_RCLK1 => rclk_1,
- HDINP2 => hdinp_2,
- HDINN2 => hdinn_2,
- HDOUTP2 => hdoutp_2,
- HDOUTN2 => hdoutn_2,
- FF_SYSCLK2 => ref_2_sclk,
- FF_RXCLK2 => rx_2_sclk,
- FFC_LANE_TX_RST2 => tx_rst_2,
- FFC_LANE_RX_RST2 => rx_rst_2,
- FF_TCLK2 => tclk_2,
- FF_RCLK2 => rclk_2,
- HDINP3 => hdinp_3,
- HDINN3 => hdinn_3,
- HDOUTP3 => hdoutp_3,
- HDOUTN3 => hdoutn_3,
- FF_SYSCLK3 => ref_3_sclk,
- FF_RXCLK3 => rx_3_sclk,
- FFC_LANE_TX_RST3 => tx_rst_3,
- FFC_LANE_RX_RST3 => rx_rst_3,
- FF_TCLK3 => tclk_3,
- FF_RCLK3 => rclk_3,
-
- FFC_PCIE_EI_EN_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCIE_TX_0 => fpsc_vlo,
- FFC_PCIE_RX_0 => fpsc_vlo,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFC_PCIE_EI_EN_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCIE_TX_1 => fpsc_vlo,
- FFC_PCIE_RX_1 => fpsc_vlo,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFC_PCIE_EI_EN_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCIE_TX_2 => fpsc_vlo,
- FFC_PCIE_RX_2 => fpsc_vlo,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFC_PCIE_EI_EN_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCIE_TX_3 => fpsc_vlo,
- FFC_PCIE_RX_3 => fpsc_vlo,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
-
- FFC_SD_0 => lsm_en_0,
- FFC_SD_1 => lsm_en_1,
- FFC_SD_2 => lsm_en_2,
- FFC_SD_3 => lsm_en_3,
-
- FFC_EN_CGA_0 => word_align_en_0,
- FFC_EN_CGA_1 => word_align_en_1,
- FFC_EN_CGA_2 => word_align_en_2,
- FFC_EN_CGA_3 => word_align_en_3,
-
- FFC_ALIGN_EN_0 => mca_align_en_0,
- FFC_ALIGN_EN_1 => mca_align_en_1,
- FFC_ALIGN_EN_2 => mca_align_en_2,
- FFC_ALIGN_EN_3 => mca_align_en_3,
-
- FFC_FB_LB_0 => felb_0,
- FFC_FB_LB_1 => felb_1,
- FFC_FB_LB_2 => felb_2,
- FFC_FB_LB_3 => felb_3,
-
- FFS_LS_STATUS_0 => lsm_status_0,
- FFS_LS_STATUS_1 => lsm_status_1,
- FFS_LS_STATUS_2 => lsm_status_2,
- FFS_LS_STATUS_3 => lsm_status_3,
-
- FFS_CC_ORUN_0 => open,
- FFS_CC_URUN_0 => open,
- FFS_CC_ORUN_1 => open,
- FFS_CC_URUN_1 => open,
- FFS_CC_ORUN_2 => open,
- FFS_CC_URUN_2 => open,
- FFS_CC_ORUN_3 => open,
- FFS_CC_URUN_3 => open,
-
- FFC_AB_RESET => mca_resync_01,
-
- FFS_AB_STATUS => mca_aligned_01,
- FFS_AB_ALIGNED => mca_inskew_01,
- FFS_AB_FAILED => mca_outskew_01,
-
- FFC_CD_RESET => mca_resync_23,
- FFS_CD_STATUS => mca_aligned_23,
-
- FFS_CD_ALIGNED => mca_inskew_23,
- FFS_CD_FAILED => mca_outskew_23,
- BS4PAD_0 => open,
- BS4PAD_1 => open,
- BS4PAD_2 => open,
- BS4PAD_3 => open,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- TCK_FMAC => open,
- TCK_FMACP => fpsc_vlo,
- FF_SYSCLK_P1 => ref_pclk,
- FF_RXCLK_P1 => rxa_pclk,
- FF_RXCLK_P2 => rxb_pclk,
- FFC_QUAD_RST => quad_rst,
- FFS_RLOS_LO0 => open,
- FFS_RLOS_LO1 => open,
- FFS_RLOS_LO2 => open,
- FFS_RLOS_LO3 => open,
- COUT_21 => open,
- COUT_20 => open,
- COUT_19 => open,
- COUT_18 => open,
- COUT_17 => open,
- COUT_16 => open,
- COUT_15 => open,
- COUT_14 => open,
- COUT_13 => open,
- COUT_12 => open,
- COUT_11 => open,
- COUT_10 => open,
- COUT_9 => open,
- COUT_8 => open,
- COUT_7 => open,
- COUT_6 => open,
- COUT_5 => open,
- COUT_4 => open,
- COUT_3 => open,
- COUT_2 => open,
- COUT_1 => open,
- COUT_0 => open,
- CIN_12 => fpsc_vlo,
- CIN_11 => fpsc_vlo,
- CIN_10 => fpsc_vlo,
- CIN_9 => fpsc_vlo,
- CIN_8 => fpsc_vlo,
- CIN_7 => fpsc_vlo,
- CIN_6 => fpsc_vlo,
- CIN_5 => fpsc_vlo,
- CIN_4 => fpsc_vlo,
- CIN_3 => fpsc_vlo,
- CIN_2 => fpsc_vlo,
- CIN_1 => fpsc_vlo,
- CIN_0 => fpsc_vlo,
- TESTCLK_MACO => fpsc_vlo,
- FFC_MACRO_RST => serdes_rst);
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-
-end serdes_fpga_ref_clk_arch ;
+++ /dev/null
-export ISPLEVER_PATH=/opt/lattice/isplever7.0/isptools
-
-export ISPCPLD=$ISPLEVER_PATH/ispcpld
-export ISPJTOOLS=$ISPLEVER_PATH/ispjtools
-export PDSPLUS=$ISPLEVER_PATH/ispcomp
-export ISPFPGA=$ISPLEVER_PATH/ispfpga
-export ISPVM_DIR=$ISPLEVER_PATH/ispvmsystem
-export INI_FILE=lsc_7_0.ini
-export MWHOME=$ISPCPLD/mw
-export MWUSER_DIRECTORY=$HOME/isplever_lin_window
-export MWREGISTRY=:$MWUSER_DIRECTORY/hklm_linux.bin
-#unexport LD_LIBRARY_PATH
-#source $MWHOME/setmwruntime.csh
-export COMSPEC=/bin/csh
-export PATH=$PATH:$ISPCPLD/bin:$PDSPLUS/bin:$ISPVM_DIR
-export LD_LIBRARY_PATH=$ISPCPLD/bin:$PDSPLUS/bin:$ISPCPLD/../ispvmsystem/lib:$ISPFPGA/bin/lin:$ISPJTOOLS/vm15/lib/i386:$ISPJTOOLS/vm15/lib/i386/client:$ISPCPLD/tcltk/linux-ix86/lib:$LD_LIBRARY_PATH
-export WINHELPDIR=$ISPCPLD/bin
-export WINHELPPATH=$ISPCPLD/bin
-export ABEL5DEV=$ISPCPLD/lib5
-#export LD_ASSUME_KERNEL 2.4.0
-export MWRT_MODE=professional
-
-export LM_LICENSE_FILE=$ISPCPLD/../license/license.dat:$LM_LICENSE_FILE
-
-sed -e "s?home_dir?$HOME/isplever_lin_window?" -e "s?bin_dir?$ISPLEVER_PATH/ispcpld/bin?" -e "s?isptool_dir?$ISPLEVER_PATH?" $ISPCPLD/config/$INI_FILE > $ISPLEVER_PATH/$INI_FILE
-export LSC_INI_PATH=$ISPLEVER_PATH
-export LSC_INI_FILE=$LSC_INI_PATH/$INI_FILE
-
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-
-
-entity simpleupcounter_16bit is
- Port ( QOUT : out std_logic_vector(15 downto 0);
- UP : in std_logic;
- CLK : in std_logic;
- CLR : in std_logic);
-end simpleupcounter_16bit;
-
-architecture simpleupcounter_16bit of simpleupcounter_16bit is
-
-signal counter: std_logic_vector (15 downto 0);
-
-begin
-
- process (CLR, UP, CLK)
-
- begin
- if CLR = '1' then
- counter <= "0000000000000000";
- elsif clk'event and clk = '1' then
- if UP = '1' then
- counter <= counter + 1;
- else
- counter <= counter;
- end if;
-end if;
-end process;
-
-QOUT <= counter;
-
-end simpleupcounter_16bit;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-
-
-entity simpleupcounter_32bit is
- Port ( QOUT : out std_logic_vector(31 downto 0);
- UP : in std_logic;
- CLK : in std_logic;
- CLR : in std_logic);
-end simpleupcounter_32bit;
-
-architecture simpleupcounter_32bit of simpleupcounter_32bit is
-
-signal counter: std_logic_vector (31 downto 0);
-
-begin
-
- process (CLR, UP, CLK)
-
- begin
- if CLR = '1' then
- counter <= "00000000000000000000000000000000";
- elsif clk'event and clk = '1' then
- if UP = '1' then
- counter <= counter + 1;
- else
- counter <= counter;
- end if;
-end if;
-end process;
-
-QOUT <= counter;
-
-end simpleupcounter_32bit;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-
-
-entity simpleupcounter_8bit is
- Port ( QOUT : out std_logic_vector(7 downto 0);
- UP : in std_logic;
- CLK : in std_logic;
- CLR : in std_logic);
-end simpleupcounter_8bit;
-
-architecture Behavioral of simpleupcounter_8bit is
-
-signal counter: std_logic_vector (7 downto 0);
-
-begin
-
- process (CLR, UP, CLK)
-
- begin
- if CLR = '1' then
- counter <= ( others => '0');
- elsif clk'event and clk = '1' then
- if UP = '1' then
- counter <= counter + 1;
- else
- counter <= counter;
- end if;
-end if;
-end process;
-
-QOUT <= counter;
-
-end Behavioral;
+++ /dev/null
-library IEEE;
-
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.all;
---use work.support.all;
-
-
-entity trb_hub_interface is
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- STROBE : in std_logic;
- INTERNAL_DATA_IN : in std_logic_vector(7 downto 0);
- INTERNAL_DATA_OUT : out std_logic_vector(7 downto 0);
- INTERNAL_ADDRESS : in std_logic_vector(15 downto 0);
- INTERNAL_MODE : in std_logic;
- VALID_DATA_SENT : out std_logic;
- HUB_REGISTER_00 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_01 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_02 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_03 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_04 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_05 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_06 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_07 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_08 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_09 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_0a : out std_logic_vector(7 downto 0);
- HUB_REGISTER_0b : out std_logic_vector(7 downto 0);
- HUB_REGISTER_0c : out std_logic_vector(7 downto 0);
- HUB_REGISTER_0d : out std_logic_vector(7 downto 0);
- HUB_REGISTER_0e : out std_logic_vector(7 downto 0);
- HUB_REGISTER_0f : out std_logic_vector(7 downto 0);
- HUB_REGISTER_10 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_11 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_12 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_13 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_14 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_15 : in std_logic_vector(7 downto 0);
- HUB_REGISTER_16 : in std_logic_vector(7 downto 0)
- );
-end trb_hub_interface;
-architecture trb_hub_interface of trb_hub_interface is
- component edge_to_pulse
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
- end component;
- signal hub_register_08_i : std_logic_vector(7 downto 0);
- signal hub_register_09_i : std_logic_vector(7 downto 0);
- signal hub_register_0a_i : std_logic_vector(7 downto 0);
- signal hub_register_0b_i : std_logic_vector(7 downto 0);
- signal hub_register_0c_i : std_logic_vector(7 downto 0);
- signal hub_register_0d_i : std_logic_vector(7 downto 0);
- signal hub_register_0e_i : std_logic_vector(7 downto 0);
- signal hub_register_0f_i : std_logic_vector(7 downto 0);
- signal saved_address : std_logic_vector(15 downto 0);
- signal saved_mod : std_logic;
- signal saved_data_in : std_logic_vector(7 downto 0);
- signal saved_data_out : std_logic_vector(7 downto 0);
- signal strobe_pulse : std_logic;
- signal data_ready : std_logic;
- type SEND_VALID is
- (IDLE ,VALID_1,VALID_2,VALID_3,VALID_4,VALID_5);
- signal VALID_current, VALID_next: SEND_VALID;
-begin
-
- STROBE_PULSER: edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => STROBE,
- pulse => strobe_pulse);
- SAVE_MOD_ADD_DATA : process (CLK, RESET, strobe_pulse)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- saved_address <= (others => '0');
- saved_mod <= '0';
- saved_data_in <= (others => '0');
- elsif strobe_pulse = '1' then
- saved_address <= INTERNAL_ADDRESS;
- saved_mod <= INTERNAL_MODE;
- saved_data_in <= INTERNAL_DATA_IN;
- end if;
- end if;
- end process SAVE_MOD_ADD_DATA;
-
- DATA_SOURCE_SELECT : process (CLK,RESET,saved_mod,saved_address)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- hub_register_0a_i <= x"00";
- hub_register_0b_i <= x"00";
- hub_register_0c_i <= x"00";
- hub_register_0d_i <= x"00";
- else
- if saved_mod = '1' then
- case saved_address(15 downto 0) is
- when x"0000" => saved_data_out <= HUB_REGISTER_00;
- when x"0001" => saved_data_out <= HUB_REGISTER_01;
- when x"0002" => saved_data_out <= HUB_REGISTER_02;
- when x"0003" => saved_data_out <= HUB_REGISTER_03;
- when x"0004" => saved_data_out <= HUB_REGISTER_04;
- when x"0005" => saved_data_out <= HUB_REGISTER_05;
- when x"0006" => saved_data_out <= HUB_REGISTER_06;
- when x"0007" => saved_data_out <= HUB_REGISTER_07;
- when x"0008" => saved_data_out <= HUB_REGISTER_08;
- when x"0009" => saved_data_out <= HUB_REGISTER_09;
- when x"000a" => saved_data_out <= hub_register_0a_i;
- when x"000b" => saved_data_out <= hub_register_0b_i;
- when x"000c" => saved_data_out <= hub_register_0c_i;
- when x"000d" => saved_data_out <= hub_register_0d_i;
- when x"000e" => saved_data_out <= hub_register_0e_i;
- when x"000f" => saved_data_out <= hub_register_0f_i;
- when x"0010" => saved_data_out <= HUB_REGISTER_10;
- when x"0011" => saved_data_out <= HUB_REGISTER_11;
- when x"0012" => saved_data_out <= HUB_REGISTER_12;
- when x"0013" => saved_data_out <= HUB_REGISTER_13;
- when x"0014" => saved_data_out <= HUB_REGISTER_14;
- when x"0015" => saved_data_out <= HUB_REGISTER_15;
- when x"0016" => saved_data_out <= HUB_REGISTER_16;
-
- when others => saved_data_out <= x"ff";
- end case;
- elsif saved_mod = '0' then
- case saved_address(15 downto 0) is
- when x"000a" => hub_register_0a_i <= saved_data_in;
- when x"000b" => hub_register_0b_i <= saved_data_in;
- when x"000c" => hub_register_0c_i <= saved_data_in;
- when x"000d" => hub_register_0d_i <= saved_data_in;
- when x"000e" => hub_register_0e_i <= saved_data_in;
- when x"000f" => hub_register_0f_i <= saved_data_in;
- when others => null;
- end case;
- end if;
- end if;
- end if;
- end process DATA_SOURCE_SELECT;
- HUB_REGISTER_0a <= hub_register_0a_i;
- HUB_REGISTER_0b <= hub_register_0b_i;
- HUB_REGISTER_0c <= hub_register_0c_i;
- HUB_REGISTER_0d <= hub_register_0d_i;
- HUB_REGISTER_0e <= hub_register_0e_i;
- HUB_REGISTER_0f <= hub_register_0f_i;
- INTERNAL_DATA_OUT <= saved_data_out;
- data_ready <= '1';
- VALID_CLOCKED : process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- VALID_current <= IDLE;
- else
- VALID_current <= VALID_next;
- end if;
- end if;
- end process VALID_CLOCKED;
- SEND_VALID_FSM: process (VALID_current,data_ready,strobe_pulse)
- begin
- case (VALID_current) is
- when IDLE =>
- VALID_DATA_SENT <= '0';
- if strobe_pulse = '1' then
- VALID_next <= VALID_1;
- else
- VALID_next <= IDLE;
- end if;
- when VALID_1 =>
- VALID_DATA_SENT <= '0';
- -- if data_ready = '1' then
- VALID_next <= VALID_2;
- -- else
- -- VALID_next <= VALID_1;
- -- end if;
- when VALID_2 =>
- VALID_DATA_SENT <= '1';
- VALID_next <= VALID_3;
- when VALID_3 =>
- VALID_DATA_SENT <= '1';
- VALID_next <= VALID_4;
- when VALID_4 =>
- VALID_DATA_SENT <= '1';
- VALID_next <= VALID_5;
- when VALID_5 =>
- VALID_DATA_SENT <= '1';
- VALID_next <= IDLE;
- when others =>
- VALID_DATA_SENT <= '0';
- VALID_next <= IDLE;
- end case;
- end process SEND_VALID_FSM;
-
-end trb_hub_interface;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library ieee;
-library work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.all;
-
-entity trbv2_tlk_api is
-
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- TLK_CLK : in std_logic;
- TLK_ENABLE : out std_logic;
- TLK_LCKREFN : out std_logic;
- TLK_LOOPEN : out std_logic;
- TLK_PRBSEN : out std_logic;
- TLK_RXD : in std_logic_vector(15 downto 0);
- TLK_RX_CLK : in std_logic;
- TLK_RX_DV : in std_logic;
- TLK_RX_ER : in std_logic;
- TLK_TXD : out std_logic_vector(15 downto 0);
- TLK_TX_EN : out std_logic;
- TLK_TX_ER : out std_logic;
- DATA_OUT : out std_logic_vector(15 downto 0);
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_VALID_IN : in std_logic;
- DATA_VALID_OUT : out std_logic;
- TLK_API_REGISTER_00 : out std_logic_vector(31 downto 0)
- );
-end trbv2_tlk_api;
-architecture trbv2_tlk_api of trbv2_tlk_api is
- component trbv2_tlk_api_fifo
- port (
- din : IN std_logic_VECTOR(17 downto 0);
- rd_clk : IN std_logic;
- rd_en : IN std_logic;
- rst : IN std_logic;
- wr_clk : IN std_logic;
- wr_en : IN std_logic;
- dout : OUT std_logic_VECTOR(17 downto 0);
- empty : OUT std_logic;
- full : OUT std_logic;
- rd_data_count : OUT std_logic_VECTOR(9 downto 0);
- wr_data_count : OUT std_logic_VECTOR(9 downto 0));
- end component;
- signal fifo_din_a : std_logic_vector(17 downto 0);
- signal fifo_dout_a : std_logic_vector(17 downto 0);
- signal fifo_rst_a : std_logic;
- signal fifo_rd_en_a : std_logic;
- signal fifo_rd_data_count_a : std_logic_vector(9 downto 0);
- signal fifo_wr_data_count_a : std_logic_vector(9 downto 0);
- signal fifo_empty_a : std_logic;
- signal fifo_full_a : std_logic;
- signal fifo_din_m : std_logic_vector(17 downto 0);
- signal fifo_dout_m : std_logic_vector(17 downto 0);
- signal fifo_rst_m : std_logic;
- signal fifo_rd_en_m : std_logic;
- signal fifo_rd_data_count_m : std_logic_vector(9 downto 0);
- signal fifo_wr_data_count_m : std_logic_vector(9 downto 0);
- signal fifo_empty_m : std_logic;
- signal fifo_full_m : std_logic;
- signal reset_fifo_counter : std_logic_vector(7 downto 0);
-begin
- -----------------------------------------------------------------------------
- -- api to media
- -----------------------------------------------------------------------------
- fifo_din_a <= TLK_RX_ER & TLK_RX_DV & TLK_RXD;
-
- OPTICAL_TO_FIFO_TO_API: trbv2_tlk_api_fifo
- port map (
- din => fifo_din_a,
- rd_clk => CLK,
- rd_en => fifo_rd_en_a ,
- rst => fifo_rst_a ,
- wr_clk => TLK_RX_CLK,
- wr_en => '1',
- dout => fifo_dout_a,
- empty => fifo_empty_a,
- full => fifo_full_a,
- rd_data_count => fifo_rd_data_count_a,
- wr_data_count => fifo_wr_data_count_a);
- SYNCH_DATA_OUT: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- DATA_VALID_OUT <= '0';
- DATA_OUT <= x"0000";
- else
- DATA_VALID_OUT <= not(fifo_dout_a(17)) and fifo_dout_a(16);
- DATA_OUT <= fifo_dout_a(15 downto 0);
- end if;
- end if;
- end process SYNCH_DATA_OUT;
-
- -----------------------------------------------------------------------------
- -- media to api
- -----------------------------------------------------------------------------
- fifo_din_m <= '0' & DATA_VALID_IN & DATA_IN;
-
- API_TO_FIFO_TO_OPTICAL: trbv2_tlk_api_fifo
- port map (
- din => fifo_din_m,
- rd_clk => TLK_CLK,
- rd_en => fifo_rd_en_m ,
- rst => fifo_rst_m ,
- wr_clk => CLK,
- wr_en => '1',
- dout => fifo_dout_m,
- empty => fifo_empty_m,
- full => fifo_full_m,
- rd_data_count => fifo_rd_data_count_m,
- wr_data_count => fifo_wr_data_count_m);
-
- TLK_TXD <= fifo_dout_m (15 downto 0);
- TLK_TX_EN <= fifo_dout_m(16);
- TLK_TX_ER <= '0';
- TLK_LOOPEN <= '0';
- TLK_LCKREFN <= '1';
- TLK_ENABLE <= '1';
- TLK_PRBSEN <= '0';
-
- -----------------------------------------------------------------------------
- -- all
- -----------------------------------------------------------------------------
- RESET_FIFO_COUNTER_PROC: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' or fifo_dout_a(17) = '1' then
- reset_fifo_counter <= x"00";
- elsif reset_fifo_counter < x"f0" then
- reset_fifo_counter <= reset_fifo_counter + 1;
- end if;
- end if;
- end process RESET_FIFO_COUNTER_PROC;
- fifo_rst_m <= '1' when reset_fifo_counter < x"40" else '0';
- fifo_rst_a <= '1' when reset_fifo_counter < x"40" else '0';
- fifo_rd_en_m <= '1' when reset_fifo_counter > x"46" else '0';
- fifo_rd_en_a <= '1' when reset_fifo_counter > x"46" else '0';
-end trbv2_tlk_api;
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.4e
-$7gf
\7f41<,[o}e~g`n;"2*447&;:%>-*>;1;8456789:;<9>40123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?1:30?4(79o1:<7GAPTV9TWI@WLG[XTQ[HSGPL9?=878=7<>5IORVP?VUGNUNA]ZV_UJQAVNXIZYN^Y26:1<12>772@D[YY4_RNE\AHVSQV^C^H]G_OGDEQC;13:5=h5>0;KMTPR=X[ELSK[CL^VKV@UO400;2?;4118JJUSS2YXDKRHZLM]WLWCT@VKX_H\[<883:73<990BB][[:QPLCZ@RDEU_D_K\H^LFCDRB400;2<h4118JJUSS2yxdkRkbpu{\pmtb{a626=0=6:33>LHW]]0{~biPelrw}ZrozlycSl}|esv?=?69:?1:<7GAPTV9twi`Wlg{xtQ{hsgplZhboh~n044?>0g855<NFY__6}|`g^dvhiYs`{oxd1750?06?46=AGZ^X7~}of]eqijX|axn
\7feQnsrgqp9?=878>7<>5IORVP?vugnUmyabPtipfwmYimnk
\7fi1750?3`?46=G\^[YY4KECWD[WBXXG^Y044?>0a855<H]]Z^X7JJBTE\SWYWF]X757>11b924?IR\Y__6_JPD@VB[FIRF]626=0>c:33>JSSX\^1[_QKAUC\GJSI\531<3?6;029KPRW]]0omyoPcnwmp9?=878?7<>5OTVSQQ<cmk
\7flS
\7fjPpovq[ujr{8Uy044?>0g855<H]]Z^X7jjbte\vaYwf}xT~1750?3f?46=G\^[YY4kecwd[wbXxg~ySz26:1<10>772F__\XZ5dd`vcZquWyd
\7f~R~cur3\s9?=878?7<>5OTVSQQ<cmk
\7flSz|Ppovq[ujr{;U|044?>0g855<H]]Z^X7jjbte\swYwf}xT~1750?3f?46=G\^[YY4kecwd[rtXxg~ySz26:1<2g>772F__\XZ5re]geqgXkf
\7fex1750?3`?46=G\^[YY4xr^fbpdYdg|d
\7f044?>06850<NFY__6LJKR@>20?699=1:97GAPTV9EABUJ5;?6=0>2:3;>LHW]]0OEC2>7;2=57=603CE\XZ5dhl?52<768>0=54@UURVP?BH]]6:;7>11592<?IR\Y__6iazt=34>5863;;97><5IORVP?BNI59:6=0>2:11>LHW]]0OEO2<1;2=56=4:3E^X][[:EMB867=87;87><5OTVSQQ<CGK68=7>11:625>2=AGZ^X7JFP@>0>58692>1EC^ZT;FJTG:4294:<6:5IORVP?QBI591<3??;58JJUSS2^OI0>4?>0080?IR\Y__6IA_A=194;753=0DYY^ZT;FLTG:4294m79xcx52eb4730$;;=68=;7;7?3?>>812867?0808=32<1?<246OKDSC?4;?<IMNYM1??>89B@ATF48;556OKDSC?578>3HNO^L2>3?`8EABUI5;?6=06;@FGVD:6<720MIJ]A=3=<>GCL[K7>364AEFQE95902KOH_O34?:8EABUI5?546OKDSC?2;><IMNYM1918:CG@WG;0720MIJ]A=;=<>GCL[H7<374AEFQF977601JHI\M<03==>GCL[H7=?06;@FGVG:6;7h0MIJ]B=37>58>3HNO^O2>4?:8EABUJ5;546OKDS@?6;><IMNYN1=18:CG@WD;<720MIJ]B=7=<>GCL[H7:364AEFQF91902KOH_L38?:8EABUJ535o6OCMNQW[@KW\Ph0MAC@SU]EQIJ>3HYRBNQ]EF18FP4?3K_XSD@IO09@e>EF[JKOID@Na:ABWFGCM@DIn6MNSBCGAJSSIk1HM^MNDDMVPG4<KL80OD:4CMIB0>EKCK90OA\6;BMNILRSMM=0O_KNTDF2?A`<LLH^KR\NM^GNTQ_b3MOIYJQ]AL]EQIJa3MOIYJQ]AL]Q@ZCIn2NNNXIPR@O\SWYBF8:0HHLZG^PG[UHSZ5:5==5KECWD[WBXXG^Y0<0>0:FFFPAXZMU[BY\32?33?ACE]NUYHR^ATS>0:46<LLH^KR\K_QLWV929991OIO[H_SF\TKRU4<4:<6JJBTE\VAYWF]X7:3??;EGAQBYULVZEX_28>028@@DROVXOS]@[R=:=57=CMK_LS_JPPOVQ8<<768:0HHLZG^PG[UHSZ535==5KECWD[RTXXG^Y0=0>0:FFFPAX_[U[BY\31?33?ACE]NU\^R^ATS>1:46<LLH^KRY]_QLWV959991OIO[H_VP\TKRU4=4:<6JJBTE\SWYWF]X793??;EGAQBYPZVZEX_29>028@@DROV]YS]@[R=5=55=CMK_LSZ\PPOVQ8=86:2NNNXIPWS]SJQT;13:5==5KECWD[RTXXG^Y040=;EK5?AOF494<7IGN<02=3>BNI5;:2:5KI@>26;1<L@K7=>08;EKB8429?2NBM1?:>69GMD:6>7=0HDO316<4?AOF4825;6JFA=3::3=CAH6:2:5KI@>14;1<L@K7><08;EKB8749?2NBM1<<>69GMD:5<7=0HDO324<4?AOF4;<5;6JFA=04:2=CAH694394DHC?6<813MCJ0?08;EKB866912NBM1=>:1<4?AOF4:;5:6JFA=1=2>BNI5>5:6JFA=7=2>BNI5<5:6JFA=5=2>BNI525:6JFA=;=2>BNJ5:5;6JFB=33:2=CAK6:=394DH@?57803MCI0<=17:FJF9736>1OEO2>5?58@LD;9?4<7IGM<05=3>BNJ5;32:5KIC>2=;0<L@H7=394DH@?65803MCI0??17:FJF9456>1OEO2=3?58@LD;:=4<7IGM<37=3>BNJ58=2:5KIC>13;1<L@H7>508;EKA87?9>2NBN1<17:FJF957601OEO2<1;2=3>BNJ59:2;5KIC>0:3=CAK6?2;5KIC>6:3=CAK6=2;5KIC>4:3=CAK632;5KIC>::3=CAG6;2:5KIO>24;1<L@D7=<08;EKM8449?2NBB1?<>69GMK:6<7=0HD@314<4?AOI48<556JFN=34>5803MCE0<916:FJJ979>2NBB1<16:FJJ959>2NBB1:16:FJJ939>2NBB1816:FJJ919>2NBB1616:FJJ9?9?2NB\L2?>69GMUG;97=0HD^N<3<:?AOWI591<394DHRB86803MC[N1>17:FJTG:66>1OE]L32?;8@LVE4:0;2:5KIQ@?7;0<LFK7<394DNC?55803MEJ0<?17:FLE9756>1OCL2>3?58@JG;9=4<7IAN<07=3>BHI5;=2:5KO@>23;1<LFK7=508;EMB84?9>2NDM1?17:FLE9476>1OCL2=1?58@JG;:;4<7IAN<31=3>BHI58?2:5KO@>11;1<LFK7>;08;EMB8719?2NDM1<7>69GKD:517<0HBO32?58@JG;;9427IAN<2394;1<LFK7?<09;EMB86813MEJ0909;EMB80813MEJ0;09;EMB82813MEJ0509;EMB8<803MEJS_KH6:FLF969?2NDN1??>69GKG:697=0HBL313<4?AIE4895;6J@B=37:2=CGK6:9394DN@?53803MEI0<917:FLF97?6>1OCO2>9?48@JD;97=0HBL321<4?AIE4;;5;6J@B=01:2=CGK69?394DN@?61803MEI0?;17:FLF9416>1OCO2=7?58@JD;:14<7IAM<3;=2>BHJ585;6J@B=13:<=CGK68=7>17:FLF9566?1OCO2<>79GKG:36?1OCO2:>79GKG:16?1OCO28>79GKG:?6?1OCO26>69GKGYUMN=0HB^N<1<4?AIWI5;5;6J@P@>1:<=CGYK7?7>17:FLTD:46>1OC]L30?58@JVE484<7IA_B=0==>BHXK686=08;EMSF959?2NDYY2?>99GKPR;99437IAZT=32:==CG\^7=?07;EMVP974611OCXZ315<;?AIR\5;>255KOTV?538f3ME^X1?8:1<;?AIR\5;<2:5KOTV?5;1<LF__0?08;EMVP959?2NDYY2;>69GKPR;=7=0HB[[<7<4?AIR\5=5;6J@UU>;:2=CG\^753;4ELRW]6=BFH90ICL=;G06?CGK[L90JIM;;GF@A6=ALY>0JI^J4:DE652<N\FG96Hnlrg2?B5<OGN:7D<4I108M44<A;80E>64IOKWTZ6702CEEY^P00:8MKOSXV:946GAIUR\46><AGC_\R>;8:KMMQVX8<20ECG[P^25<>OIA]ZT<:74IOKWWQGSM>1BBDZP0158MKOSW9;<7D@FT^213>OIA]U;?:5FNHV\411<AGC_S=;8;HLJPZ61?2CEEYQ?769JJLRX81=0ECG[_1;4?LHN\V:J;6GAIU]3F2=NF@^T<N94IOKW[5B03@DBXR>J7:KMMQY7N>1BBDZP1158MKOSW8;<7D@FT^313>OIA]U:?:5FNHV\511<AGC_S<;8;HLJPZ71?2CEEYQ>769JJLRX91=0ECG[_0;4?LHN\V;J;6GAIU]2F2=NF@^T=N94IOKW[4B03@DBXR?J7:KMMQY6N>1BBDZP2158MKOSW;;<7D@FT^013>OIA]U9?:5FNHV\611<AGC_S?;8;HLJPZ41?2CEEYQ=769JJLRX:1=0ECG[_3;4?LHN\V8J;6GAIU]1F2=NF@^T>N94IOKW[7B03@DBXR<J7:KMMQY5N>1BBDZP3158MKOSW:;<7D@FT^113>OIA]U8?:5FNHV\711<AGC_S>;8;HLJPZ51?2CEEYQ<769JJLRX;1=0ECG[_2;4?LHN\V9J;6GAIU]0F2=NF@^T?N94IOKW[6B03@DBXR=J7:KMMQY4N?1BBDZPA79JJLRXJ01BBDZPFHNF7>OI^880ECXJRU]@HNYCGHUYIJ?=;HLUAWRXKEATHBLPRDE0?LIE:2FB:6B@AEGG3>JHO@IJ@95CUU37?ISS:=1GYY=;;MWW00=J]QIRo6CnjnpUawunggi0Ad``rWgqwlii:2D:?6@>059M55533G;;895A1177?K77>=1E==9;;O33<1=I99387C?>4:L2552<F8;:86@>1368J474<2D:=9:4N0360>H69?>0B<?84:L25=2<F8;2?6@>259M57633G;9=95A1307?K75?=1E=?6;;O31=6=I9:>0B<=?4:L2742<F89986@>3268J453<2D:?8:4N0150>H6;090B<:;;O3741=I9=;?7C?;259M51533G;?895A1577?K73>=1E=99;;O37<6=I9<90B<8<;O347>H60:1E=4<4N318J7643G8:?6@=239M17=I>;1E;?5A829M<65<F1>87C6:3:L;26=I0>90B56<;O::6>H>;2D2=>5A9218J<3a3GHTNX]_IO]SVJVT?2DNXZA]K59MKKC63F80CF64OWGQBIIP92Z?7]O]T`9SMKYE]ZCOTo5_IO]AQVHFEL90\_Kn;QPLCZCJX]S:86^]OF]FIUR^W]BYI^F30?37?UTHOVOF\YWPTIPFWM:668>0\_AH_DOSP\YS@[OXD1<1159SVJAXMDZ_URZGRDQK8686<2ZYCJQJMQVZ[QNUMZB783?;;QPLCZCJX]STXE\JSI>6:42<X[ELSHC_TX]WLWCT@5<5=95_RNE\AHVSQV^C^H]G<6<20>VUGNUNA]ZV_UJQAVN;07;=7]\@G^GNTQ_X\AXN_E26:1<20>VUGNUNA]ZV_UJQAVN;17;i7]\@G^GNTQ_X\AXN_EQNSRGQP9699k1[^BIPELRW]ZROZLYCSL]\ESV?5;7e3YXDKRKBPU[\PMTB[AUJ_^K]T=0=5g=WZFMTI@^[Y^VKV@UOWHYXI_Z33?3a?UTHOVOF\YWPTIPFWMYF[ZOYX1:11c9SVJAXMDZ_URZGRDQK[DUTM[^793?m;QPLCZCJX]STXE\JSI]BWVCU\5<5=o5_RNE\AHVSQV^C^H]G_@QPAWR;?7;i7]\@G^GNTQ_X\AXN_EQNSRGQP9>99m1[^BIPELRW]ZROZLYCSL]\ESV?=?699k1[^BIPELRW]ZROZLYCSL]\ESV?=;7e3YXDKRKBPU[\PMTB[AUEIJO[E=2=5g=WZFMTI@^[Y^VKV@UOWGOLMYK31?3a?UTHOVOF\YWPTIPFWMYIMNK_I1<11c9SVJAXMDZ_URZGRDQK[KC@I]O7?3?m;QPLCZCJX]STXE\JSI]MABGSM5>5=o5_RNE\AHVSQV^C^H]G_OGDEQC;=7;i7]\@G^GNTQ_X\AXN_EQAEFCWA9099k1[^BIPELRW]ZROZLYCSCKHAUG?3;7e3YXDKRKBPU[\PMTB[AUEIJO[E=:=5a=WZFMTI@^[Y^VKV@UOWGOLMYK39;2=5g=WZFMTI@^[Y^VKV@UOWGOLMYK39?;8TWI@WO_G@<=4PSMD[CSKDV^C^H]G<1<27>VUGNUMYABPTIPFWM:66890\_AH_GWOHZROZLYC0?0>3:RQKBYA]EFTXE\JSI>0:45<X[ELSK[CL^VKV@UO4=4:?6^]OF]EQIJX\AXN_E2:>018TWI@WO_G@RZGRDQK8386;2ZYCJQIUMN\PMTB[A6<2<=4PSMD[CSKDV^C^H]G<9<21>VUGNUMYABPTIPFWM:>294:?6^]OF]EQIJX\AXN_E26>0c8TWI@WO_G@RZGRDQK[DUTM[^7<3?n;QPLCZ@RDEU_D_K\H^CPW@TS484:m6^]OF]EQIJX\AXN_EQNSRGQP9499h1[^BIPFTNO[QNUMZBTM^]JRU>0:4g<X[ELSK[CL^VKV@UOWHYXI_Z34?3b?UTHOVL^@AQ[HSGPLZGT[LX_080>a:RQKBYA]EFTXE\JSI]BWVCU\5<5=l5_RNE\BPJKW]BYI^FPARQFVQ:068k0\_AH_GWOHZROZLYCSL]\ESV?<;7d3YXDKRHZLM]WLWCT@VKX_H\[<883:4g<X[ELSK[CL^VKV@UOWHYXI_Z39?3b?UTHOVL^@AQ[HSGPLZHBOH^N0=0>a:RQKBYA]EFTXE\JSI]MABGSM5;5=l5_RNE\BPJKW]BYI^FPNDEBP@:568k0\_AH_GWOHZROZLYCSCKHAUG?7;7f3YXDKRHZLM]WLWCT@VDNKLZJ<5<2e>VUGNUMYABPTIPFWMYIMNK_I1;11`9SVJAXN\FGSYF]ERJ\J@AF\L6=2<o4PSMD[CSKDV^C^H]G_OGDEQC;?7;j7]\@G^DVHIYS@[OXDR@JG@VF8=86k2ZYCJQIUMN\PMTB[AUEIJO[E=;94;7f3YXDKRHZLM]WLWCT@VDNKLZJ<8<2?T0<ZHGI=;h4R@O\A]RBFZCDBROi;SCN[@^SMGYBCCQM6:PG[FJL991YHRJNT@]@KPHS494:<6\K_ECWEZEH]G^7=3??;SF\@DRFWJE^BY2=>028VAYCI]KTOB[AT=1=55=ULVNJXLQLOTLW818682XOSIO[A^ALQKR;=7;;7_JPD@VB[FIRF]6=2<>4RE]GEQGXKF_EX191119Q@ZBF\HUHCX@[<9<26>TCWMK_MRM@UOV?=?69991YHRJNT@]@KPHS404>7_JPEOa8V@GCW^COXEQNc:PFEAYPAM^CSO84RDE@AD0<ZLMHIO=4RRV2?V><[H\NHLZN129PMHYDGEFB_DAA_BJFGN0<[F_YOH94SSTBHZG03ZX]MAQM4:QPVD2<[ZXI86ZVPDg8Q5)`mgUj
\7f#hhar;8QKBBZOFD[l5ZSDP\EIOF[j1^_H\PVHQJFIC23_KGEI=4VBA:?SOB_V^R\H84WDC?4;0<_LK7=384WDC?6;><_LK7?7>16:UFE959>2]NN1>16:UFF979>2]NN1<18:UFF95=87<0[HL33?`8SWOSMVLB^^Zl;VPJP@YJGMOTMn5XRHVF[HICMVHo7Z\FTD]TMAROWHn0[_G[E^UJ@QNXJ?1\^ROLK79TVZEKC8:0[_QKAUC\GJSI\5:5==5XR^FBPDYDG\D_0<0>0:UQ[AGSIVIDYCZ32?33?RTXLH^JSNAZNU>0:46<_[UOMYOPCNWMP929991\^RJNT@]@KPHS4<4:<6Y]_ECWEZEH]G^7:3??;VP\@DRFWJE^BY28>028SWYCI]KTOB[AT=:=57=PZVNJXLQLOTLW8<<768:0[_QKAUC\GJSI\53596Y]_DL2`>^ND@DS!UJM 1,2$VRRJ):%=-O\CHK6?]IUKP<0T^ZCIC58\VRXOGN<7U][_WA@f>^XKFXNSD@IO028\ZEHZLUBBKAPLHQW2>^cjVCoj6Vkh^RqmhPbzzcdb<>4Xeo\Idlhz_oy
\7fdaa119[`hYJageyZh||inl`?djjgz~Ti`~{yc9bhhit|Vl~`a84b`ahqub<jhi`y}Qbasifv6=ddb8=7na}efgm+qkw'Vil#y|mv3]whnYfx`Umeka!nfmg?agsiVidycz'0(f8`drfWje~by&>)e9geqgXkf
\7fex%<&d:fbpdYdg|d
\7f$>'k;ecweZeh}g~#8$j4d`vb[firf}">%i5kauc\gjsi|!<"h6jnt`]`kphs >#o7io{a^alqkr/0 n0hlzn_bmvjq.>!m1omyoPcnwmp969n2njxlQlotlw8<<76>1ondzjrs3;?ace}nUyhR~ats]shpu6W{6;2<64dd`vcZtcWyd
\7f~R~cur3\v979911oio{h_sf\tkruWyf~
\7f<Q}<3<2<>bbj|mT~iQ
\7fnup\tist9Vx7?3?7;egaqbYulVzex
\7fQ
\7fltq2[w:36820hhlzg^pg[uhszVzgy~?Pr=7=5==cmk
\7flS
\7fjPpovq[ujr{8Uy0;0>8:fffpaXzmU{by|Ppmwp5Zt;?7;37ikmuf]q`Zvi|{U{`x}>_s>;:4g<llh~kR|k_qlwvZvk}z;T~1750?3;?ace}nUyhR~ats]shpu6W{622<<4dd`vcZtcWyd
\7f~R|30?31?ace}nUyhR~ats]q8486:2nnnxiPre]sjqtXz585=?5kecwd[wbXxg~yS
\7f2<>008``droVxoS}`{r^p?0;753moiyjQ}d^rmpwYu4<4:>6jjbte\vaYwf}xT~181139gags`W{nT|cz}_s>4:44<llh~kR|k_qlwvZt;07;?7ikmuf]q`Zvi|{Uy044?>008``droVxoS}`{r^p?=;753moiyjQ}d^rmpwYp494:>6jjbte\vaYwf}xT{1?1139gags`W{nT|cz}_v>1:44<llh~kR|k_qlwvZq;;7;97ikmuf]q`Zvi|{U|090>2:fffpaXzmU{by|Pw=7=57=cmk
\7flS
\7fjPpovq[r:16880hhlzg^pg[uhszV}7;3?=;egaqbYulVzex
\7fQx<9<20>bbj|mT~iQ
\7fnup\s9?=87;97ikmuf]q`Zvi|{U|040>8:fffpaX
\7f{U{by|Ppmwp5Zq;87;37ikmuf]tvZvi|{U{`x}>_v>2:4><llh~kRy}_qlwvZvk}z;T{1<1199gags`W~xT|cz}_qnvw4Yp4:4:46jjbte\swYwf}xT|a{|1^u?0;7?3moiyjQxr^rmpwYwd|y:Sz2:>0:8``droV}yS}`{r^roqv7X
\7f5<5=55kecwd[rtXxg~yS}bzs0]t828602nnnxiPws]sjqtXxe
\7fx=Ry38?3b?ace}nU|~R~ats]shpu6W~626=0>8:fffpaX
\7f{U{by|Ppmwp5Zq;17;37ikmuf]tvZvi|{U{`x}=_v>3:4><llh~kRy}_qlwvZvk}z8T{1?1199gags`W~xT|cz}_qnvw7Yp4;4:46jjbte\swYwf}xT|a{|2^u?7;7?3moiyjQxr^rmpwYwd|y9Sz2;>0:8``droV}yS}`{r^roqv4X
\7f5?5=55kecwd[rtXxg~yS}bzs3]t838602nnnxiPws]sjqtXxe
\7fx>Ry37?3;?ace}nU|~R~ats]shpu5W~632<o4dd`vcZquWyd
\7f~R~cur0\s9?=87;37ikmuf]tvZvi|{U{`x}=_v>::44<llh~kRy}_qlwvZt;87;97ikmuf]tvZvi|{Uy0<0>2:fffpaX
\7f{U{by|Pr=0=57=cmk
\7flSz|Ppovq[w:46880hhlzg^uq[uhszVx783?=;egaqbYpzVzex
\7fQ}<4<26>bbj|mT{
\7fQ
\7fnup\v9099;1oio{h_vp\tkruW{6<2<<4dd`vcZquWyd
\7f~R|38?37?ace}nU|~R~ats]q8<<76880hhlzg^uq[uhszVx753?=;egaqbYpzVzex
\7fQx<1<26>bbj|mT{
\7fQ
\7fnup\s9799;1oio{h_vp\tkruW~692<<4dd`vcZquWyd
\7f~Ry33?31?ace}nU|~R~ats]t8186:2nnnxiPws]sjqtX
\7f5?5=?5kecwd[rtXxg~ySz29>008``droV}yS}`{r^u?3;753moiyjQxr^rmpwYp414:86jjbte\swYwf}xT{1750?31?ace}nU|~R~ats]t8<813mce$='9;ekm,4/03mce$<>&7:fjj-76!>1oec&>2(58`lh/9:#<7iga(06*3>bnf!;>%:5kio*22,1<l`d#=:'9;ekm,7/13mce$>'9;ekm,1/13mce$8'9;ekm,3/13mce$:'9;ekm,=/13mce$4'9;ekm85803mce0<>17:fjj9766>1oec2>2?58`lh;9:4<7iga<06=3>bnf5;>2:5kio>22;?<l`d7=:4?>69gmk:6?7<0hd`31?48`lh;:7<0hd`33?48`lh;<7<0hd`35?48`lh;>7<0hd`37?48`lh;07<0hd`39?58`jss 9#<7iazt)3*<>bh}}":<$64dnww,47.02ndyy&>2(:8`jss 89"46j`uu*20,><lf
\7f\7f$<;&8:flqq.6> 20hb{{(05*3>bh}}"9%:5kotv+7,1<lf
\7f\7f$9'8;emvp-3.?2ndyy&9)69gkpr/? =0hb{{(9+4?air|!3";6j`uu>3:==cg|~7==07;emvp976611ocxz313<;?air|5;8255kotv?518?3me~x1?:>99gkpr;9?4j7iazt=34>58?3me~x1?8>69gkpr;97=0hb{{<3<4?air|595;6j`uu>7:2=cg|~79394dnww83803me~x1917:flqq:?6>1ocxz39?:8aaoa:gmo96kbpu{15>`nnfUlick}aumq[s5X;%*Hc
\7fkheo":*7o6>2lbjbQheogqeqiuW
\7f9T?Ro|4:dvhi><fniiydbk6d9mkwk`mg$hbylck.efjZei|{$licQ}d^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!BcnwmpZeh}g~Tot2?>7g8jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqt(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSnw31?52?kiuenoe"n`{bmi,c`hXkg~y"jka_sf\gkru'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/LalqkrXkf
\7fexRmv<0<\vq0b3geyajka.blwfim(oldTocz}.fgm[wbXkg~y#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Heh}g~Tob{at^az878092dd~`ijn/ampgjl'noeSn`{r/efjZtcWjd
\7f~"ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]`}949W{~=i6``rlefj+ei|kf`#jka_blwv+abfVxoSn`{r.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqYdq595;<5aosodak(df}hgg"ijn^ampw(`mgUyhRmats-dakYeagUhbyQ{oq,amkYdf}U
\7fc}!heo]awfYeagUhby mle]amkYdf}%Fob{at^alqkrXkp682R|{6d9mkwk`mg$hbylck.efjZei|{$licQ}d^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!BcnwmpZeh}g~Tot2;>638jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqt(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSnw34?]qp3c<ffxfkh`!covahn)`mgUhby|!gdl\vaYdf}x$kh`Pbhl\gkrX|fz%nd`Pcov\pjv(oldTn~mPbhl\gkr)jenTnd`Pcov,Ifirf}Uhcx`{_b{?1;163geyajka.blwfim(oldTocz}.fgm[wbXkg~y#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Heh}g~Tob{at^az808Xz}<n7ca}mfgm*fhsjea$kh`Pcovq*bciW{nTocz}/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'DidyczPcnwmpZe~4?4<=6``rlefj+ei|kf`#jka_blwv+abfVxoSn`{r.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqYdq5<5S
\7fz9e:llvhabf'iexobd/fgm[fhsz'mnbR|k_blwv*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Uhu191709mkwk`mg$hbylck.efjZei|{$licQ}d^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!BcnwmpZeh}g~Tot28>^pw2`=ig{glic lnu`oo*abfViex
\7f heo]q`Zei|{%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Ngjsi|VidyczPcx>;:27<ffxfkh`!covahn)`mgUhby|!gdl\vaYdf}x$kh`Pbhl\gkrX|fz%nd`Pcov\pjv(oldTn~mPbhl\gkr)jenTnd`Pcov,Ifirf}Uhcx`{_b{?<;Yu|>?0bb|bgdl-gkredb%licQlnup-c`hXzmUhby| gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[iss494TECXP07d8jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqt(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSua}<0<5b>hhzdmnb#matcnh+bciWjd
\7f~#ijn^pg[fhsz&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQwos>1:3`<ffxfkh`!covahn)`mgUhby|!gdl\vaYdf}x$kh`Pbhl\gkrX|fz%nd`Pcov\pjv(oldTn~mPbhl\gkr)jenTnd`Pcov,Ifirf}Uhcx`{_ymq8681n2dd~`ijn/ampgjl'noeSn`{r/efjZtcWjd
\7f~"ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:36?l0bb|bgdl-gkredb%licQlnup-c`hXzmUhby| gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[}iu4<4=j6``rlefj+ei|kf`#jka_blwv+abfVxoSn`{r.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqY
\7fg{6=2;h4nnpnc`h)kg~i`f!heo]`jqt)oldT~iQlnup,c`hXj`dToczPtnr-flhXkg~Txb~ gdl\fveXj`dTocz!bmf\flhXkg~$Anaznu]`kphsWqey0:09f:llvhabf'iexobd/fgm[fhsz'mnbR|k_blwv*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f27>7d8jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqt(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSua}<8<46>hhzdmnb#matcnh+bciWjd
\7f~#ijn^pg[fhsz&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQwos>::Zts><1ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx1>1649mkwk`mg$hbylck.efjZei|{$licQ}d^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop979><1ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx1<1649mkwk`mg$hbylck.efjZei|{$licQ}d^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop959><1ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx1:1649mkwk`mg$hbylck.efjZei|{$licQ}d^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop939><1ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx181649mkwk`mg$hbylck.efjZei|{$licQ}d^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop919><1ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx161649mkwk`mg$hbylck.efjZei|{$licQ}d^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop9?9>:1ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)dg|d
\7fS=8<;omqibci&jd
\7fnae gdl\gkru&noeS
\7fjPcovq+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]226=ig{glic lnu`oo*abfViex
\7f heo]q`Zei|{%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-`kphsW;<87ca}mfgm*fhsjea$kh`Pcovq*bciW{nTocz}/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'je~byQ<629mkwk`mg$hbylck.efjZei|{$licQ}d^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!lotlw[1043geyajka.blwfim(oldTocz}.fgm[wbXkg~y#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U>:>5aosodak(df}hgg"ijn^ampw(`mgUyhRmats-dakYeagUhbyQ{oq,amkYdf}U
\7fc}!heo]awfYeagUhby mle]amkYdf}%hcx`{_740?kiuenoe"n`{bmi,c`hXkg~y"jka_sf\gkru'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY0>:1ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)dg|d
\7fS58<;omqibci&jd
\7fnae gdl\gkru&noeS
\7fjPcovq+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]:31=ig{glic lnu`oo*abfViex
\7f heo]q`Zei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'DidyczPcnwmpZe~494<86``rlefj+ei|kf`#jka_blwv+abfVxoSn`{r^roqv7(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSnw31?54?kiuenoe"n`{bmi,c`hXkg~y"jka_sf\gkruWyf~
\7f<!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Jkf
\7fexRm`uov\g|:66Vx
\7f;95aosodak(df}hgg"ijn^ampw(`mgUyhRmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/LalqkrXkf
\7fexRmv<3<43>hhzdmnb#matcnh+bciWjd
\7f~#ijn^pg[fhszVzgy~? gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[f
\7f;:7Uyx::4nnpnc`h)kg~i`f!heo]`jqt)oldT~iQlnup\tist9&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQly=1=32=ig{glic lnu`oo*abfViex
\7f heo]q`Zei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'DidyczPcnwmpZe~4:4T~y9;;omqibci&jd
\7fnae gdl\gkru&noeS
\7fjPcovq[ujr{8%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Ngjsi|VidyczPcx>7:21<ffxfkh`!covahn)`mgUhby|!gdl\vaYdf}xT|a{|1.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqYdq5>5S
\7fz84:llvhabf'iexobd/fgm[fhsz'mnbR|k_blwvZvk}z;$kh`Pbhl\gkrX|fz%nd`Pcov\pjv(oldTn~mPbhl\gkr)jenTnd`Pcov,Ifirf}Uhcx`{_b{?1;103geyajka.blwfim(oldTocz}.fgm[wbXkg~yS}bzs0-dakYeagUhbyQ{oq,amkYdf}U
\7fc}!heo]awfYeagUhby mle]amkYdf}%Fob{at^alqkrXkp6>2R|{759mkwk`mg$hbylck.efjZei|{$licQ}d^ampwYwd|y:#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Heh}g~Tob{at^az8380?2dd~`ijn/ampgjl'noeSn`{r/efjZtcWjd
\7f~R~cur3,c`hXj`dToczPtnr-flhXkg~Txb~ gdl\fveXj`dTocz!bmf\flhXkg~$Anaznu]`kphsWjs7:3Q}t668jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]`}919?>1ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7fQ
\7fltq2+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#@m`uov\gjsi|Vir0:0Pru57?kiuenoe"n`{bmi,c`hXkg~y"jka_sf\gkruWyf~
\7f<!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Jkf
\7fexRm`uov\g|:?6>=0bb|bgdl-gkredb%licQlnup-c`hXzmUhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Uhu161_sv4f>hhzdmnb#matcnh+bciWjd
\7f~#ijn^pg[fhszVzgy~? gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[iss494TECXP0678jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:66>?0bb|bgdl-gkredb%licQlnup-c`hXzmUhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f2=>678jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:46>?0bb|bgdl-gkredb%licQlnup-c`hXzmUhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f2;>678jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:26>?0bb|bgdl-gkredb%licQlnup-c`hXzmUhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f29>678jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:06>?0bb|bgdl-gkredb%licQlnup-c`hXzmUhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f27>678jjtjold%oczmlj-dakYdf}x%kh`Pre]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:>6>20bb|bgdl-gkredb%licQlnup-c`hXzmUhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f26>^pw2g=ig{glic lnu`oo*abfViex
\7f heo]q`Zei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'[oxyaz30?4a?kiuenoe"n`{bmi,c`hXkg~y"jka_sf\gkruWyf~
\7f<!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx1?16c9mkwk`mg$hbylck.efjZei|{$licQ}d^ampwYwd|y:#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Wct}e~7>38m;omqibci&jd
\7fnae gdl\gkru&noeS
\7fjPcovq[ujr{8%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Qavsk|595:o5aosodak(df}hgg"ijn^ampw(`mgUyhRmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/Sgpqir;<7<i7ca}mfgm*fhsjea$kh`Pcovq*bciW{nTocz}_qnvw4)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop939>k1ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7fQ
\7fltq2+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#_k|umv?2;0e3geyajka.blwfim(oldTocz}.fgm[wbXkg~yS}bzs0-dakYeagUhbyQ{oq,amkYdf}U
\7fc}!heo]awfYeagUhby mle]amkYdf}%Yi~{ct=5=2g=ig{glic lnu`oo*abfViex
\7f heo]q`Zei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'[oxyaz38?4a?kiuenoe"n`{bmi,c`hXkg~y"jka_sf\gkruWyf~
\7f<!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx171689mkwk`mg$hbylck.efjZei|{$licQ}d^ampwYwd|y:#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U;:45aosodak(df}hgg"ijn^ampw(`mgUyhRmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY6>01ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7fQ
\7fltq2+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]12<=ig{glic lnu`oo*abfViex
\7f heo]q`Zei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'je~byQ<689mkwk`mg$hbylck.efjZei|{$licQ}d^ampwYwd|y:#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U?:45aosodak(df}hgg"ijn^ampw(`mgUyhRmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY2>01ec
\7fcheo,`jqdkc&mnbRmats,dakYulViex
\7fQ
\7fltq2+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]52<=ig{glic lnu`oo*abfViex
\7f heo]q`Zei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'je~byQ8689mkwk`mg$hbylck.efjZei|{$licQ}d^ampwYwd|y:#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U3:45aosodak(df}hgg"ijn^ampw(`mgUyhRmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY>>l1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Jkf
\7fexRm`uov\g|:76?o0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby| gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[f
\7f;97=:7ca}mfgm*fhsjea$kh`Pcovq*bciW~xTocz}/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'DidyczPcnwmpZe~484T~y8j;omqibci&jd
\7fnae gdl\gkru&noeSz|Pcovq+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#@m`uov\gjsi|Vir0?081:llvhabf'iexobd/fgm[fhsz'mnbRy}_blwv*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Uhu1<1_sv5a>hhzdmnb#matcnh+bciWjd
\7f~#ijn^uq[fhsz&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQly=1=34=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Ngjsi|VidyczPcx>0:Zts>l1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Jkf
\7fexRm`uov\g|:36>;0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby| gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[f
\7f;<7Uyx;k4nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup,c`hXj`dToczPtnr-flhXkg~Txb~ gdl\fveXj`dTocz!bmf\flhXkg~$Anaznu]`kphsWjs7939>;omqibci&jd
\7fnae gdl\gkru&noeSz|Pcovq+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#@m`uov\gjsi|Vir080Pru4f?kiuenoe"n`{bmi,c`hXkg~y"jka_vp\gkru'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/LalqkrXkf
\7fexRmv<7<45>hhzdmnb#matcnh+bciWjd
\7f~#ijn^uq[fhsz&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQly=4=[wr1m2dd~`ijn/ampgjl'noeSn`{r/efjZquWjd
\7f~"ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]`}919?81ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Jkf
\7fexRm`uov\g|:06Vx
\7f:h5aosodak(df}hgg"ijn^ampw(`mgU|~Rmats-dakYeagUhbyQ{oq,amkYdf}U
\7fc}!heo]awfYeagUhby mle]amkYdf}%Fob{at^alqkrXkp632:?4nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup,c`hXj`dToczPtnr-flhXkg~Txb~ gdl\fveXj`dTocz!bmf\flhXkg~$Anaznu]`kphsWjs743Q}t678jjtjold%oczmlj-dakYdf}x%kh`Pws]`jqt(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSa{{<1<\MKPX8?l0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby| gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[}iu484=j6``rlefj+ei|kf`#jka_blwv+abfV}ySn`{r.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqY
\7fg{692;h4nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup,c`hXj`dToczPtnr-flhXkg~Txb~ gdl\fveXj`dTocz!bmf\flhXkg~$Anaznu]`kphsWqey0>09f:llvhabf'iexobd/fgm[fhsz'mnbRy}_blwv*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f2;>7d8jjtjold%oczmlj-dakYdf}x%kh`Pws]`jqt(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSua}<4<5b>hhzdmnb#matcnh+bciWjd
\7f~#ijn^uq[fhsz&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQwos>5:3`<ffxfkh`!covahn)`mgUhby|!gdl\swYdf}x$kh`Pbhl\gkrX|fz%nd`Pcov\pjv(oldTn~mPbhl\gkr)jenTnd`Pcov,Ifirf}Uhcx`{_ymq8281n2dd~`ijn/ampgjl'noeSn`{r/efjZquWjd
\7f~"ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:?6?l0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby| gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[}iu404<>6``rlefj+ei|kf`#jka_blwv+abfV}ySn`{r.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqY
\7fg{622R|{649mkwk`mg$hbylck.efjZei|{$licQxr^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop969><1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx1?1649mkwk`mg$hbylck.efjZei|{$licQxr^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop949><1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx1=1649mkwk`mg$hbylck.efjZei|{$licQxr^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop929><1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx1;1649mkwk`mg$hbylck.efjZei|{$licQxr^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop909><1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx191649mkwk`mg$hbylck.efjZei|{$licQxr^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop9>9><1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx171629mkwk`mg$hbylck.efjZei|{$licQxr^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!lotlw[5043geyajka.blwfim(oldTocz}.fgm[rtXkg~y#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U::>5aosodak(df}hgg"ijn^ampw(`mgU|~Rmats-dakYeagUhbyQ{oq,amkYdf}U
\7fc}!heo]awfYeagUhby mle]amkYdf}%hcx`{_340?kiuenoe"n`{bmi,c`hXkg~y"jka_vp\gkru'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY4>:1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7f!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)dg|d
\7fS98<;omqibci&jd
\7fnae gdl\gkru&noeSz|Pcovq+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]626=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-`kphsW?<87ca}mfgm*fhsjea$kh`Pcovq*bciW~xTocz}/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'je~byQ8629mkwk`mg$hbylck.efjZei|{$licQxr^ampw)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!lotlw[=043geyajka.blwfim(oldTocz}.fgm[rtXkg~y#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U2;95aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/LalqkrXkf
\7fexRmv<1<40>hhzdmnb#matcnh+bciWjd
\7f~#ijn^uq[fhszVzgy~? gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[f
\7f;97=<7ca}mfgm*fhsjea$kh`Pcovq*bciW~xTocz}_qnvw4)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!BcnwmpZeh}g~Tot2>>^pw31=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'DidyczPcnwmpZe~4;4<;6``rlefj+ei|kf`#jka_blwv+abfV}ySn`{r^roqv7(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSnw32?]qp22<ffxfkh`!covahn)`mgUhby|!gdl\swYdf}xT|a{|1.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqYdq595;:5aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/LalqkrXkf
\7fexRmv<2<\vq133geyajka.blwfim(oldTocz}.fgm[rtXkg~yS}bzs0-dakYeagUhbyQ{oq,amkYdf}U
\7fc}!heo]awfYeagUhby mle]amkYdf}%Fob{at^alqkrXkp6?2:94nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup\tist9&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQly=6=[wr0<2dd~`ijn/ampgjl'noeSn`{r/efjZquWjd
\7f~R~cur3,c`hXj`dToczPtnr-flhXkg~Txb~ gdl\fveXj`dTocz!bmf\flhXkg~$Anaznu]`kphsWjs79398;omqibci&jd
\7fnae gdl\gkru&noeSz|Pcovq[ujr{8%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Ngjsi|VidyczPcx>6:Zts?=1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq2+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#@m`uov\gjsi|Vir0;087:llvhabf'iexobd/fgm[fhsz'mnbRy}_blwvZvk}z;$kh`Pbhl\gkrX|fz%nd`Pcov\pjv(oldTn~mPbhl\gkr)jenTnd`Pcov,Ifirf}Uhcx`{_b{?2;Yu|>>0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Uhu191769mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y:#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Heh}g~Tob{at^az828Xz}=?7ca}mfgm*fhsjea$kh`Pcovq*bciW~xTocz}_qnvw4)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!BcnwmpZeh}g~Tot27>658jjtjold%oczmlj-dakYdf}x%kh`Pws]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]`}9>9W{~<n6``rlefj+ei|kf`#jka_blwv+abfV}ySn`{r^roqv7(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSa{{<1<\MKPX8>?0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f2>>678jjtjold%oczmlj-dakYdf}x%kh`Pws]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:56>?0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f2<>678jjtjold%oczmlj-dakYdf}x%kh`Pws]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:36>?0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f2:>678jjtjold%oczmlj-dakYdf}x%kh`Pws]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:16>?0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f28>678jjtjold%oczmlj-dakYdf}x%kh`Pws]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:?6>?0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby|Ppmwp5*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Usc
\7f26>6:8jjtjold%oczmlj-dakYdf}x%kh`Pws]`jqtXxe
\7fx="ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]{kw:>6Vx
\7f:o5aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/Sgpqir;87<i7ca}mfgm*fhsjea$kh`Pcovq*bciW~xTocz}_qnvw4)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop979>k1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq2+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#_k|umv?6;0e3geyajka.blwfim(oldTocz}.fgm[rtXkg~yS}bzs0-dakYeagUhbyQ{oq,amkYdf}U
\7fc}!heo]awfYeagUhby mle]amkYdf}%Yi~{ct=1=2g=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'[oxyaz34?4a?kiuenoe"n`{bmi,c`hXkg~y"jka_vp\gkruWyf~
\7f<!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx1;16c9mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y:#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Wct}e~7:38m;omqibci&jd
\7fnae gdl\gkru&noeSz|Pcovq[ujr{8%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Qavsk|5=5:o5aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/Sgpqir;07<i7ca}mfgm*fhsjea$kh`Pcovq*bciW~xTocz}_qnvw4)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop9?9>01ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq2+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]32<=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'je~byQ>689mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y:#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U9:45aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY4>01ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq2+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]72<=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'je~byQ:689mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y:#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U=:45aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu6'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY0>01ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq2+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu];2<=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{U{`x}>/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'je~byQ6759mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y9#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Heh}g~Tob{at^az8580<2dd~`ijn/ampgjl'noeSn`{r/efjZquWjd
\7f~R~cur0,c`hXj`dToczPtnr-flhXkg~Txb~ gdl\fveXj`dTocz!bmf\flhXkg~$Anaznu]`kphsWjs7=398;omqibci&jd
\7fnae gdl\gkru&noeSz|Pcovq[ujr{;%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Ngjsi|VidyczPcx>2:Zts?=1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq1+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#@m`uov\gjsi|Vir0?087:llvhabf'iexobd/fgm[fhsz'mnbRy}_blwvZvk}z8$kh`Pbhl\gkrX|fz%nd`Pcov\pjv(oldTn~mPbhl\gkr)jenTnd`Pcov,Ifirf}Uhcx`{_b{?6;Yu|>>0bb|bgdl-gkredb%licQlnup-c`hX
\7f{Uhby|Ppmwp6*abfVhbbRmat^vlt+dnfViexRz`p.efjZdtkVhbbRmat/`o`ZdnfViex"Clotlw[firf}Uhu1=1769mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y9#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Heh}g~Tob{at^az868Xz}=?7ca}mfgm*fhsjea$kh`Pcovq*bciW~xTocz}_qnvw7)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!BcnwmpZeh}g~Tot2;>658jjtjold%oczmlj-dakYdf}x%kh`Pws]`jqtXxe
\7fx>"ijn^`jjZei|V~d|#lfn^ampZrhx&mnbRl|c^`jjZei|'hghRlfn^amp*Kdg|d
\7fSnaznu]`}929W{~<86``rlefj+ei|kf`#jka_blwv+abfV}ySn`{r^roqv4(oldTnd`Pcov\pjv)j`dToczPtnr,c`hXjziTnd`Pcov-fibXj`dTocz MbmvjqYdg|d
\7fSnw35?54?kiuenoe"n`{bmi,c`hXkg~y"jka_vp\gkruWyf~
\7f?!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Jkf
\7fexRm`uov\g|:26Vx
\7f;95aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu5'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/LalqkrXkf
\7fexRmv<7<43>hhzdmnb#matcnh+bciWjd
\7f~#ijn^uq[fhszVzgy~< gdl\flhXkg~Txb~!bhl\gkrX|fz$kh`Pbra\flhXkg~%najPbhl\gkr(Eje~byQlotlw[f
\7f;>7Uyx::4nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup\tist:&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQly=5=32=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{U{`x}=/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'DidyczPcnwmpZe~4>4T~y9;;omqibci&jd
\7fnae gdl\gkru&noeSz|Pcovq[ujr{;%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Ngjsi|VidyczPcx>;:21<ffxfkh`!covahn)`mgUhby|!gdl\swYdf}xT|a{|2.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqYdq525S
\7fz8b:llvhabf'iexobd/fgm[fhsz'mnbRy}_blwvZvk}z8$kh`Pbhl\gkrX|fz%nd`Pcov\pjv(oldTn~mPbhl\gkr)jenTnd`Pcov,Ifirf}Uhcx`{_mww858XAG\T<:;4nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup\tist:&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQwos>2:23<ffxfkh`!covahn)`mgUhby|!gdl\swYdf}xT|a{|2.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqY
\7fg{692:;4nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup\tist:&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQwos>0:23<ffxfkh`!covahn)`mgUhby|!gdl\swYdf}xT|a{|2.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqY
\7fg{6?2:;4nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup\tist:&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQwos>6:23<ffxfkh`!covahn)`mgUhby|!gdl\swYdf}xT|a{|2.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqY
\7fg{6=2:;4nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup\tist:&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQwos>4:23<ffxfkh`!covahn)`mgUhby|!gdl\swYdf}xT|a{|2.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqY
\7fg{632:;4nnpnc`h)kg~i`f!heo]`jqt)oldT{
\7fQlnup\tist:&mnbRlfn^ampZrhx'hbbRmat^vlt*abfVhxoRlfn^amp+dklVhbbRmat.O`kphsWje~byQwos>::2><ffxfkh`!covahn)`mgUhby|!gdl\swYdf}xT|a{|2.efjZdnfViexRz`p/`jjZei|V~d|"ijn^`pgZdnfViex#lcd^`jjZei|&Ghcx`{_bmvjqY
\7fg{622R|{6c9mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y9#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Wct}e~7<38m;omqibci&jd
\7fnae gdl\gkru&noeSz|Pcovq[ujr{;%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Qavsk|5;5:o5aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu5'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/Sgpqir;:7<i7ca}mfgm*fhsjea$kh`Pcovq*bciW~xTocz}_qnvw7)`mgUiecQlnu]wku(eagUhbyQ{oq-dakYe{jUiecQlnu,ahaYeagUhby!]erwop959>k1ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq1+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#_k|umv?0;0e3geyajka.blwfim(oldTocz}.fgm[rtXkg~yS}bzs3-dakYeagUhbyQ{oq,amkYdf}U
\7fc}!heo]awfYeagUhby mle]amkYdf}%Yi~{ct=7=2g=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{U{`x}=/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'[oxyaz36?4a?kiuenoe"n`{bmi,c`hXkg~y"jka_vp\gkruWyf~
\7f?!heo]amkYdf}U
\7fc} mio]`jqYsgy%licQmsb]amkYdf}$i`iQmio]`jq)Umz
\7fgx1916c9mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y9#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+Wct}e~7438m;omqibci&jd
\7fnae gdl\gkru&noeSz|Pcovq[ujr{;%licQmio]`jqYsgy$iecQlnu]wku)`mgUi
\7fnQmio]`jq(edmUiecQlnu-Qavsk|535:45aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu5'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY7>01ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq1+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]22<=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{U{`x}=/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'je~byQ=689mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y9#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U8:45aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu5'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY3>01ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq1+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]62<=ig{glic lnu`oo*abfViex
\7f heo]tvZei|{U{`x}=/fgm[goiWjd
\7fSya
\7f.ckm[fhsW}e{#jka_cq`[goiWjd
\7f"obk_ckm[fhs'je~byQ9689mkwk`mg$hbylck.efjZei|{$licQxr^ampwYwd|y9#jka_ckm[fhsW}e{"oga_blw[qiw'noeSo}l_ckm[fhs&kfoSoga_blw+firf}U<:45aosodak(df}hgg"ijn^ampw(`mgU|~Rmats]shpu5'noeSoga_blw[qiw&kceSn`{_ums+bciWkyhSoga_blw*gjcWkceSn`{/bmvjqY?>01ec
\7fcheo,`jqdkc&mnbRmats,dakYpzViex
\7fQ
\7fltq1+bciWkceSn`{_ums*goiWjd
\7fSya
\7f/fgm[gudWkceSn`{.cng[goiWjd
\7f#naznu]:76=ig{glic ilcnh+HgclVkgxR|k_ecweZeh}g~TeRokdrwa456799987ca}mfgm*cjedb%FmijPamv\vaYci}kTob{at^k\eabt}k:;<=?=329mkwk`mg$m`obd/Lcg`Zgk|VxoSio{a^alqkrXaVkoh~{m012351543geyajka.gnahn)JimnTmazPre]geqgXkf
\7fexRgPaefpqg6789;=??5aosodak(adkf`#@okd^copZtcWmk
\7fmRm`uov\mZgclz
\7fi<=>?2208jjtjold%jalck.Ob`aYfd}UyhRjnt`]`kphsW`Ujhi}zb12341553geyajka.gnahn)JimnTmazPre]geqgXkf
\7fexRgPaefpqg6789<8>6``rlefj+`kjea$Aljk_`nw[wbXlh~jSnaznu]j[dbc{|h;<=>7369mkwk`mg$m`obd/Lcg`Zgk|VxoSio{a^alqkrXaVkoh~{m0123[f
\7f;979;7ca}mfgm*cjedb%FmijPamv\swYci}kTob{at^k\eab789::<>>4nnpnc`h)nehgg"Cnde]bhqYpzVnjxlQlotlw[lYflm:;<=?=319mkwk`mg$m`obd/Lcg`Zgk|V}ySio{a^alqkrXaVkoh=>?00604>hhzdmnb#hcbmi,IdbcWhf
\7fSz|Pd`vb[firf}UbSljk0123534a3geyajka.gnahn)JimnTmazPws]geqgXkf
\7fexRgPaef34565:o1ec
\7fcheo,ehgjl'DkohRoct^uq[agsiVidyczPi^cg`5678=8m7ca}mfgm*cjedb%FmijPamv\swYci}kTob{at^k\eab789:=>k5aosodak(adkf`#@okd^copZquWmk
\7fmRm`uov\mZgcl9:;<5=;;omqibci&ofi`f!Baef\eirX
\7f{UomyoPcnwmpZoXimn;<=>Pcx>2:7><ffxfkh`!fm`oo*Kt}kU
\7fa}Q
\7fnup\vZbnnoUhu1>1299mkwk`mg$m`obd/LqvfZrjxVzex
\7fQ}_ekebZe~484946``rlefj+`kjea$A~{m_uos[uhszVxThdhi_b{?6;4?3geyajka.gnahn)J{|hTx`~Ppovq[wYcaolTot2<>3:8jjtjold%jalck.OpqgYseyU{by|Pr^fjbcYdq5>5>55aosodak(adkf`#@}zb^vntZvi|{UySigif^az808502dd~`ijn/dofim(Ez
\7fiSyc
\7f_qlwvZtXl`lmSnw36?0;?kiuenoe"kbmlj-NwpdX|dzT|cz}_s]gmc`Xkp6<2?64nnpnc`h)nehgg"C|uc]wiuYwf}xT~Rjffg]`}9>9:01ec
\7fcheo,ehgjl'Dy~nRzbp^rmpwYuWmcmjRbzt=2=6<=ig{glic ilcnh+HurjV~f|R~ats]q[aoanVf~x1?1289mkwk`mg$m`obd/LqvfZrjxVzex
\7fQ}_ekebZjr|585>45aosodak(adkf`#@}zb^vntZvi|{UySigif^nvp959:01ec
\7fcheo,ehgjl'Dy~nRzbp^rmpwYuWmcmjRbzt=6=6<=ig{glic ilcnh+HurjV~f|R~ats]q[aoanVf~x1;1289mkwk`mg$m`obd/LqvfZrjxVzex
\7fQ}_ekebZjr|5<5>45aosodak(adkf`#@}zb^vntZvi|{UySigif^nvp919:01ec
\7fcheo,ehgjl'Dy~nRzbp^rmpwYuWmcmjRbzt=:=6<=ig{glic ilcnh+HurjV~f|R~ats]q[aoanVf~x171289mkwk`mg$m`obd/LqvfZrjxVzex
\7fQ}_ekebZ~hz5:5>45aosodak(adkf`#@}zb^vntZvi|{UySigif^zlv979:01ec
\7fcheo,ehgjl'Dy~nRzbp^rmpwYuWmcmjRv`r=0=6<=ig{glic ilcnh+HurjV~f|R~ats]q[aoanVrd~1=1289mkwk`mg$m`obd/LqvfZrjxVzex
\7fQ}_ekebZ~hz5>5>45aosodak(adkf`#@}zb^vntZvi|{UySigif^zlv939:01ec
\7fcheo,ehgjl'Dy~nRzbp^rmpwYuWmcmjRv`r=4=6<=ig{glic ilcnh+HurjV~f|R~ats]q[aoanVrd~191289mkwk`mg$m`obd/LqvfZrjxVzex
\7fQ}_ekebZ~hz525>45aosodak(adkf`#@}zb^vntZvi|{UySigif^zlv9?9:11ec
\7fcheo,ehgjl'Dy~nRzbp^rmpwYpWmcmjRmv<1<1<>hhzdmnb#hcbmi,IvseW}g{S}`{r^u\`l`aWjs7=3<7;omqibci&ofi`f!Bst`\phvXxg~ySzQkigd\g|:56;20bb|bgdl-bidkc&GxyoQ{mq]sjqtX
\7fVnbjkQly=1=6==ig{glic ilcnh+HurjV~f|R~ats]t[aoanVir090=8:llvhabf'lgnae Mrwa[qkwWyd
\7f~RyPdhde[f
\7f;=7837ca}mfgm*cjedb%F
\7fxlPtlr\tkruW~UoekhPcx>5:7><ffxfkh`!fm`oo*Kt}kU
\7fa}Q
\7fnup\sZbnnoUhu191299mkwk`mg$m`obd/LqvfZrjxVzex
\7fQx_ekebZe~414956``rlefj+`kjea$A~{m_uos[uhszV}Thdhi_mww858512dd~`ijn/dofim(Ez
\7fiSyc
\7f_qlwvZqXl`lmSa{{<0<1=>hhzdmnb#hcbmi,IvseW}g{S}`{r^u\`l`aWe
\7f\7f0?0=9:llvhabf'lgnae Mrwa[qkwWyd
\7f~RyPdhde[iss4:4956``rlefj+`kjea$A~{m_uos[uhszV}Thdhi_mww818512dd~`ijn/dofim(Ez
\7fiSyc
\7f_qlwvZqXl`lmSa{{<4<1=>hhzdmnb#hcbmi,IvseW}g{S}`{r^u\`l`aWe
\7f\7f0;0=9:llvhabf'lgnae Mrwa[qkwWyd
\7f~RyPdhde[iss4>4956``rlefj+`kjea$A~{m_uos[uhszV}Thdhi_mww8=8512dd~`ijn/dofim(Ez
\7fiSyc
\7f_qlwvZqXl`lmSa{{<8<1=>hhzdmnb#hcbmi,IvseW}g{S}`{r^u\`l`aWqey0=0=9:llvhabf'lgnae Mrwa[qkwWyd
\7f~RyPdhde[}iu484956``rlefj+`kjea$A~{m_uos[uhszV}Thdhi_ymq878512dd~`ijn/dofim(Ez
\7fiSyc
\7f_qlwvZqXl`lmSua}<2<1=>hhzdmnb#hcbmi,IvseW}g{S}`{r^u\`l`aWqey090=9:llvhabf'lgnae Mrwa[qkwWyd
\7f~RyPdhde[}iu4<4956``rlefj+`kjea$A~{m_uos[uhszV}Thdhi_ymq838512dd~`ijn/dofim(Ez
\7fiSyc
\7f_qlwvZqXl`lmSua}<6<1=>hhzdmnb#hcbmi,IvseW}g{S}`{r^u\`l`aWqey050=9:llvhabf'lgnae Mrwa[qkwWyd
\7f~RyPdhde[}iu404:=6``rlefj+`kjea$B<>>1:llvhabf'lgnae N0325>hhzdmnb#hcbmi,J44692dd~`ijn/dofim(F89:=6``rlefj+`kjea$B<:>1:llvhabf'lgnae N0725>hhzdmnb#hcbmi,J40692dd~`ijn/dofim(F8=:=6``rlefj+`kjea$B<6>1:llvhabf'lgnae N0;25>hhzdmnb#hcbmi,J76692dd~`ijn/dofim(F;;:=6``rlefj+`kjea$B?<>1:llvhabf'lgnae N3125>hhzdmnb#hcbmi,J72692dd~`ijn/dofim(F;?:<6``rlefj+`kjea$B;??;omqibci&ofi`f!A7028jjtjold%jalck.L;55=ig{glic ilcnh+K?402dd~`ijn/dofim(keafci!lx/pg|*K
\7fg{U{by|Pgb]{kw6789UYi~{ct01;?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/LzlvZvi|{UloRv`r1235ZTb{|f
\7f=>64nnpnc`h)nehgg"mcklmg+f~)zmr$Aua}_qlwvZadWqey<=>=_Sgpqir6;11ec
\7fcheo,ehgjl'jf`abj cy,q`})JpfxT|cz}_fa\|jt7899T^h}zlu30<>hhzdmnb#hcbmi,gimjgm%ht#|kx.O{kwYwf}xTknQwos2341YUmz
\7fgx<=7;omqibci&ofi`f!lljol`*e
\7f&{ns#@v`r^rmpwY`kVrd~=>?5^Pfwpjs9:20bb|bgdl-bidkc&igg`ak/bz-va~(EqeyS}`{r^e`[}iu89:=S_k|umv27==ig{glic ilcnh+fjlefn$ou }dy-N|jtXxg~ySjmPxnp3451XZly~`y?<8:llvhabf'lgnae cminka)dp'xot"Cwos]sjqtXojUsc
\7f>?09]Qavsk|88?7ca}mfgm*cjedb%h`fc`d.a{*wb
\7f'YD_^RLP0368jjtjold%jalck.aoohic'jr%~iv POVQ[GY6:=1ec
\7fcheo,ehgjl'jf`abj cy,q`})WF]XTNR<=4:llvhabf'lgnae cminka)dp'xot"^ATS]A[6433geyajka.gnahn)ddbgdh"mw.sf{+UHSZVHT8?:4nnpnc`h)nehgg"mcklmg+f~)zmr$\CZ]_C]661=ig{glic ilcnh+fjlefn$ou }dy-SJQTXJV<986``rlefj+`kjea$oaeboe-`|+tcp&ZEX_QM_607?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/QLWVZDX0;>0bb|bgdl-bidkc&igg`ak/bz-va~(XG^YSOQ62`9mkwk`mg$m`obd/bnhijb(kq$yhu!_NUP\FZ~hz9:;<?l4nnpnc`h)nehgg"mcklmg+f~)zmr$\CZ]_C]{kw6789;9m6``rlefj+`kjea$oaeboe-`|+tcp&ZEX_QM_ymq4566:k1ec
\7fcheo,ehgjl'jf`abj cy,q`})WF]XTNRv`r123544f3geyajka.gnahn)ddbgdh"mw.sf{+UHSZVHTtb|?0101f>hhzdmnb#hcbmi,gimjgm%ht#|kx.RMPWYEWqey<=>=13c8jjtjold%jalck.aoohic'jr%~iv POVQ[GY
\7fg{:;<><m;omqibci&ofi`f!lljol`*e
\7f&{ns#]@[R^@\|jt78999>l5aosodak(adkf`#nbdmnf,g}(ulq%[BY\PB^zlv567<;h0bb|bgdl-bidkc&igg`ak/bz-va~(XG^YSOQwos234175i2dd~`ijn/dofim(keafci!lx/pg|*VI\[UISua}01266g=ig{glic ilcnh+fjlefn$ou }dy-SJQTXJVrd~=>?500b?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/QLWVZDXpfx;<=8<0:llvhabf'lgnae cminka)dp'xot"^ATS]A[}iu89:==<Q\W113?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/QLWVZDXpfx;<=8>1^QT566<ffxfkh`!fm`oo*ekcdeo#nv!rez,TKRUWKUsc
\7f>?0732[VQ5:k1ec
\7fcheo,ehgjl'jf`abj cy,q`})WF]XTNRv`r123274f3geyajka.gnahn)ddbgdh"mw.sf{+UHSZVHTtb|?0151f>hhzdmnb#hcbmi,gimjgm%ht#|kx.RMPWYEWqey<=>813c8jjtjold%jalck.aoohic'jr%~iv POVQ[GY
\7fg{:;<5<m;omqibci&ofi`f!lljol`*e
\7f&{ns#]@[R^@\|jt7892:>;5aosodak(adkf`#nbdmnf,g}(ulq%{by|Pgb>3:70<ffxfkh`!fm`oo*ekcdeo#nv!rez,tkruWni7=3<9;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`8785>2dd~`ijn/dofim(keafci!lx/pg|*vi|{Ulo1=1279mkwk`mg$m`obd/bnhijb(kq$yhu!
\7fnup\cf:36;<0bb|bgdl-bidkc&igg`ak/bz-va~(xg~ySjm35?05?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/qlwvZad4?49:6``rlefj+`kjea$oaeboe-`|+tcp&zex
\7fQhc=5=63=ig{glic ilcnh+fjlefn$ou }dy-sjqtXoj632?84nnpnc`h)nehgg"mcklmg+f~)zmr$|cz}_fa?=;423geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhS=<:;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[4423geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhS?<:;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[6423geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhS9<:;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[0423geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhS;<:;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[2423geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhS5<:;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[<4>3geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhSu<30?0:?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/qlwvZadWq87=3<6;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[}4;:7827ca}mfgm*cjedb%h`fc`d.a{*wb
\7f'yd
\7f~Ril_y0?7;4>3geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhSu<34?0:?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/qlwvZadWq8793<6;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[}4;>7827ca}mfgm*cjedb%h`fc`d.a{*wb
\7f'yd
\7f~Ril_y0?3;4>3geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhSu<38?0:?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/qlwvZadWq8753<7;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[}4X8;20bb|bgdl-bidkc&igg`ak/bz-va~(xg~ySjmPx3]26==ig{glic ilcnh+fjlefn$ou }dy-sjqtXojUs>R<=8:llvhabf'lgnae cminka)dp'xot"~ats]dgZ~5W:837ca}mfgm*cjedb%h`fc`d.a{*wb
\7f'yd
\7f~Ril_y0\07><ffxfkh`!fm`oo*ekcdeo#nv!rez,tkruWniTt?Q:299mkwk`mg$m`obd/bnhijb(kq$yhu!
\7fnup\cfY
\7f:V<946``rlefj+`kjea$oaeboe-`|+tcp&zex
\7fQhc^z1[24?3geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhSu<P83:8jjtjold%jalck.aoohic'jr%~iv povq[beXp;U2>55aosodak(adkf`#nbdmnf,g}(ulq%{by|Pgb]{858502dd~`ijn/dofim(keafci!lx/pg|*vi|{UloRv31?0;?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/qlwvZadWq692?64nnpnc`h)nehgg"mcklmg+f~)zmr$|cz}_fa\|959:11ec
\7fcheo,ehgjl'jf`abj cy,q`})wf}xTknQw<5<1<>hhzdmnb#hcbmi,gimjgm%ht#|kx.rmpwY`kVr793<7;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[}:16;20bb|bgdl-bidkc&igg`ak/bz-va~(xg~ySjmPx=5=6==ig{glic ilcnh+fjlefn$ou }dy-sjqtXojUs050=8:llvhabf'lgnae cminka)dp'xot"~ats]dgZ~;178<7ca}mfgm*cjedb%h`fc`d.a{*wb
\7f'yd
\7f~Ril_y]362=ig{glic ilcnh+fjlefn$ou }dy-sjqtXojUsS<<8;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[}Y5:>1ec
\7fcheo,ehgjl'jf`abj cy,q`})wf}xTknQw_204?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/qlwvZadWqU?>:5aosodak(adkf`#nbdmnf,g}(ulq%{by|Pgb]{[0403geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhSuQ9269mkwk`mg$m`obd/bnhijb(kq$yhu!
\7fnup\cfY
\7fW>8<7ca}mfgm*cjedb%h`fc`d.a{*wb
\7f'yd
\7f~Ril_y];62=ig{glic ilcnh+fjlefn$ou }dy-sjqtXojUsS4<m;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[}iu89:;>o5aosodak(adkf`#nbdmnf,g}(ulq%{by|Pgb]{kw67888i7ca}mfgm*cjedb%h`fc`d.a{*wb
\7f'yd
\7f~Ril_ymq4565:k1ec
\7fcheo,ehgjl'jf`abj cy,q`})wf}xTknQwos23464e3geyajka.gnahn)ddbgdh"mw.sf{+uhszVmhSua}01276g=ig{glic ilcnh+fjlefn$ou }dy-sjqtXojUsc
\7f>?040a?kiuenoe"kbmlj-`hnkhl&is"
\7fjw/qlwvZadWqey<=>92c9mkwk`mg$m`obd/bnhijb(kq$yhu!
\7fnup\cfY
\7fg{:;<:<m;omqibci&ofi`f!lljol`*e
\7f&{ns#}`{r^e`[}iu89:3?55aosodak(adkf`#nbdmnf,g}(pzq%Ftb|Ppovq[beXpfx;<=>PRdqvhq7402dd~`ijn/dofim(keafci!lx/uq|*K
\7fg{U{by|Pgb]{kw6788UYi~{ct01;?kiuenoe"kbmlj-`hnkhl&is"z|w/LzlvZvi|{UloRv`r1236ZTb{|f
\7f=>64nnpnc`h)nehgg"mcklmg+f~)
\7f{r$Aua}_qlwvZadWqey<=><_Sgpqir6;11ec
\7fcheo,ehgjl'jf`abj cy,tv})JpfxT|cz}_fa\|jt789>T^h}zlu30<>hhzdmnb#hcbmi,gimjgm%ht#y}x.O{kwYwf}xTknQwos2340YUmz
\7fgx<=7;omqibci&ofi`f!lljol`*e
\7f&~xs#@v`r^rmpwY`kVrd~=>?6^Pfwpjs9:20bb|bgdl-bidkc&igg`ak/bz-sw~(EqeyS}`{r^e`[}iu89:<S_k|umv27==ig{glic ilcnh+fjlefn$ou xry-N|jtXxg~ySjmPxnp345>XZly~`y?=4:llvhabf'lgnae cminka)dp'}yt"^ATS]A[5433geyajka.gnahn)ddbgdh"mw.vp{+UHSZVHT=?:4nnpnc`h)nehgg"mcklmg+f~)
\7f{r$\CZ]_C]161=ig{glic ilcnh+fjlefn$ou xry-SJQTXJV9986``rlefj+`kjea$oaeboe-`|+qup&ZEX_QM_507?kiuenoe"kbmlj-`hnkhl&is"z|w/QLWVZDX=;>0bb|bgdl-bidkc&igg`ak/bz-sw~(XG^YSOQ9259mkwk`mg$m`obd/bnhijb(kq$|~u!_NUP\FZ15<2dd~`ijn/dofim(keafci!lx/uq|*VI\[UIS5<;;omqibci&ofi`f!lljol`*e
\7f&~xs#]@[R^@\=7g<ffxfkh`!fm`oo*ekcdeo#nv!wsz,TKRUWKUsc
\7f>?010a?kiuenoe"kbmlj-`hnkhl&is"z|w/QLWVZDXpfx;<=>>2`9mkwk`mg$m`obd/bnhijb(kq$|~u!_NUP\FZ~hz9:;=?l4nnpnc`h)nehgg"mcklmg+f~)
\7f{r$\CZ]_C]{kw6788;9m6``rlefj+`kjea$oaeboe-`|+qup&ZEX_QM_ymq4565:k1ec
\7fcheo,ehgjl'jf`abj cy,tv})WF]XTNRv`r123644f3geyajka.gnahn)ddbgdh"mw.vp{+UHSZVHTtb|?0111f>hhzdmnb#hcbmi,gimjgm%ht#y}x.RMPWYEWqey<=><23c8jjtjold%jalck.aoohic'jr%{
\7fv POVQ[GY
\7fg{:;<9<m;omqibci&ofi`f!lljol`*e
\7f&~xs#]@[R^@\|jt789>:>l5aosodak(adkf`#nbdmnf,g}(pzq%[BY\PB^zlv567=;h0bb|bgdl-bidkc&igg`ak/bz-sw~(XG^YSOQwos234075i2dd~`ijn/dofim(keafci!lx/uq|*VI\[UISua}012575=ig{glic ilcnh+fjlefn$ou xry-SJQTXJVrd~=>?603\WR6482dd~`ijn/dofim(keafci!lx/uq|*VI\[UISua}012554YT_89;7ca}mfgm*cjedb%h`fc`d.a{*rt
\7f'YD_^RLPxnp345069VY\>?l4nnpnc`h)nehgg"mcklmg+f~)
\7f{r$\CZ]_C]{kw678?89m6``rlefj+`kjea$oaeboe-`|+qup&ZEX_QM_ymq4560:k1ec
\7fcheo,ehgjl'jf`abj cy,tv})WF]XTNRv`r123344f3geyajka.gnahn)ddbgdh"mw.vp{+UHSZVHTtb|?01:1f>hhzdmnb#hcbmi,gimjgm%ht#y}x.RMPWYEWqey<=>71348jjtjold%jalck.aoohic'jr%{
\7fv povq[be;878=7ca}mfgm*cjedb%h`fc`d.a{*rt
\7f'yd
\7f~Ril<0<12>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`k585>;5aosodak(adkf`#nbdmnf,g}(pzq%{by|Pgb>0:70<ffxfkh`!fm`oo*ekcdeo#nv!wsz,tkruWni783<9;omqibci&ofi`f!lljol`*e
\7f&~xs#}`{r^e`8085>2dd~`ijn/dofim(keafci!lx/uq|*vi|{Ulo181279mkwk`mg$m`obd/bnhijb(kq$|~u!
\7fnup\cf:06;<0bb|bgdl-bidkc&igg`ak/bz-sw~(xg~ySjm38?05?kiuenoe"kbmlj-`hnkhl&is"z|w/qlwvZad404996``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^211>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kV;996``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^011>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kV9996``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^611>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kV?996``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^411>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kV=996``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^:11>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kV3956``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^z1858512dd~`ijn/dofim(keafci!lx/uq|*vi|{UloRv=<0<1=>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kVr90?0=9:llvhabf'lgnae cminka)dp'}yt"~ats]dgZ~54:4956``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^z1818512dd~`ijn/dofim(keafci!lx/uq|*vi|{UloRv=<4<1=>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kVr90;0=9:llvhabf'lgnae cminka)dp'}yt"~ats]dgZ~54>4956``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^z18=8512dd~`ijn/dofim(keafci!lx/uq|*vi|{UloRv=<8<1<>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kVr9S=<7;omqibci&ofi`f!lljol`*e
\7f&~xs#}`{r^e`[}4X9;20bb|bgdl-bidkc&igg`ak/bz-sw~(xg~ySjmPx3]16==ig{glic ilcnh+fjlefn$ou xry-sjqtXojUs>R==8:llvhabf'lgnae cminka)dp'}yt"~ats]dgZ~5W=837ca}mfgm*cjedb%h`fc`d.a{*rt
\7f'yd
\7f~Ril_y0\17><ffxfkh`!fm`oo*ekcdeo#nv!wsz,tkruWniTt?Q9299mkwk`mg$m`obd/bnhijb(kq$|~u!
\7fnup\cfY
\7f:V=946``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^z1[=4?3geyajka.gnahn)ddbgdh"mw.vp{+uhszVmhSu<P93:8jjtjold%jalck.aoohic'jr%{
\7fv povq[beXp5:5>55aosodak(adkf`#nbdmnf,g}(pzq%{by|Pgb]{848502dd~`ijn/dofim(keafci!lx/uq|*vi|{UloRv32?0;?kiuenoe"kbmlj-`hnkhl&is"z|w/qlwvZadWq682?64nnpnc`h)nehgg"mcklmg+f~)
\7f{r$|cz}_fa\|929:11ec
\7fcheo,ehgjl'jf`abj cy,tv})wf}xTknQw<4<1<>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kVr7:3<7;omqibci&ofi`f!lljol`*e
\7f&~xs#}`{r^e`[}:06;20bb|bgdl-bidkc&igg`ak/bz-sw~(xg~ySjmPx=:=6==ig{glic ilcnh+fjlefn$ou xry-sjqtXojUs040=7:llvhabf'lgnae cminka)dp'}yt"~ats]dgZ~X8;=0bb|bgdl-bidkc&igg`ak/bz-sw~(xg~ySjmPx^313>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kVrT>?94nnpnc`h)nehgg"mcklmg+f~)
\7f{r$|cz}_fa\|Z55?2dd~`ijn/dofim(keafci!lx/uq|*vi|{UloRvP4358jjtjold%jalck.aoohic'jr%{
\7fv povq[beXpV?9;6``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^z\271<ffxfkh`!fm`oo*ekcdeo#nv!wsz,tkruWniTtR9=7:llvhabf'lgnae cminka)dp'}yt"~ats]dgZ~X0;=0bb|bgdl-bidkc&igg`ak/bz-sw~(xg~ySjmPx^;1f>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kVrd~=>?03`8jjtjold%jalck.aoohic'jr%{
\7fv povq[beXpfx;<=?=b:llvhabf'lgnae cminka)dp'}yt"~ats]dgZ~hz9:;>?l4nnpnc`h)nehgg"mcklmg+f~)
\7f{r$|cz}_fa\|jt78999n6``rlefj+`kjea$oaeboe-`|+qup&zex
\7fQhc^zlv567<;h0bb|bgdl-bidkc&igg`ak/bz-sw~(xg~ySjmPxnp34535j2dd~`ijn/dofim(keafci!lx/uq|*vi|{UloRv`r12327d<ffxfkh`!fm`oo*ekcdeo#nv!wsz,tkruWniTtb|?0151f>hhzdmnb#hcbmi,gimjgm%ht#y}x.rmpwY`kVrd~=>?80d8jjtjold%jalck.pg[agsiVidyczPi^22b>hhzdmnb#hcbmi,vaYci}kTob{at^k\54`<ffxfkh`!fm`oo*tcWmk
\7fmRm`uov\mZ46n2dd~`ijn/dofim(zmUomyoPcnwmpZoX;8l0bb|bgdl-bidkc&xoSio{a^alqkrXaV>:j6``rlefj+`kjea$~iQkauc\gjsi|VcT9<h4nnpnc`h)nehgg"|k_ecweZeh}g~TeR8>f:llvhabf'lgnae re]geqgXkf
\7fexRgP70d8jjtjold%jalck.pg[agsiVidyczPi^:2b>hhzdmnb#hcbmi,vaYci}kTob{at^k\=76<ffxfkh`!fm`oo*twzlgdh"\NM^PG[@H6:m1ec
\7fcheo,ehgjl'}byabj adnlcle(kho:#no}rxlfp969:m1ec
\7fcheo,ehgjl'}byabj adnlcle(kho:#no}rxlfp979:m1ec
\7fcheo,ehgjl'}byabj adnlcle(kho:#no}rxlfp949:m1ec
\7fcheo,ehgjl'}byabj adnlcle(kho:#no}rxlfp959;l1ec
\7fcheo,ehgjl'}byabj adnlcle(kho:#h
\7flarg-fla)eezP<P isu,nbltt|:h0bb|bgdl-bidkc&~c~`ak/`gokbod'jkn="k~c`qf*go`&df{W<S!mhf-if
\7f4j2dd~`ijn/dofim(|axfci!nemmdmf)dil;$i|mnsd,amb(jdyQ9Q#cfd/o`}6d<ffxfkh`!fm`oo*rozdeo#lkcofk`+fgb9&ozol}j.ckd*hjwS:W%adj!mb{0f>hhzdmnb#hcbmi,pmtjgm%jiaahib-`e`7(mxij
\7fh mif,nhu]3U'gbh#cly358jjtjold%jalck.vkvhic'hogcjgl/bcf5*p64949;6``rlefj+`kjea$xe|boe-baii`aj%hmh? v0>2:71<ffxfkh`!fm`oo*rozdeo#lkcofk`+fgb9&|:0?0=7:llvhabf'lgnae tipnka)fmeelen!lad3,r4:46;=0bb|bgdl-bidkc&~c~`ak/`gokbod'jkn="x><5<1b>hhzdmnb#hcbmi,pmtjgm%jiaahib-`e`7(~8U;Sl`k012357`<ffxfkh`!fm`oo*rozdeo#lkcofk`+fgb9&|:S<Qnne234575n2dd~`ijn/dofim(|axfci!nemmdmf)dil;$z<Q=_`lg45679;l0bb|bgdl-bidkc&~c~`ak/`gokbod'jkn="x>_2]bja6789;9j6``rlefj+`kjea$xe|boe-baii`aj%hmh? v0]7[dhc89:;=?j4nnpnc`h)nehgg"zgrlmg+dckgnch#noj2.abvw
\7fim}6;2?j4nnpnc`h)nehgg"zgrlmg+dckgnch#noj2.abvw
\7fim}6:2?j4nnpnc`h)nehgg"zgrlmg+dckgnch#noj2.abvw
\7fim}692?j4nnpnc`h)nehgg"zgrlmg+dckgnch#noj2.abvw
\7fim}682>k4nnpnc`h)nehgg"zgrlmg+dckgnch#noj2.grgdub&kcl"`b
\7f[1_-bvr)eocy
\7fy=m;omqibci&ofi`f!{hsol`*gbdfmbo"mne3-fufgtm'hbk#ccpZ3^*hoc&dir?o5aosodak(adkf`#yf}mnf,e`jho`i$olk=/ds`evc)j`m%aa~T2\,nma(jkp9i7ca}mfgm*cjedb%
\7fd
\7fc`d.cfhjank&iji?!jqbcpa+dno'gg|V=R.lkg*he~;k1ec
\7fcheo,ehgjl'}byabj adnlcle(kho9#h
\7flarg-fla)eezP8P bie,ng|403geyajka.gnahn)s`{gdh"ojlnejg*efm;%}=1>1269mkwk`mg$m`obd/ujqijb(ilfdkdm c`g1+s7;978<7ca}mfgm*cjedb%
\7fd
\7fc`d.cfhjank&iji?!y1=0=62=ig{glic ilcnh+qnuefn$mhb`gha,gdc5'
\7f;7?3<8;omqibci&ofi`f!{hsol`*gbdfmbo"mne3-u5929:o1ec
\7fcheo,ehgjl'}byabj adnlcle(kho9#{?P0^cm`567888m7ca}mfgm*cjedb%
\7fd
\7fc`d.cfhjank&iji?!y1^3\ekb789::>k5aosodak(adkf`#yf}mnf,e`jho`i$olk=/w3\6Zgil9:;<<<i;omqibci&ofi`f!{hsol`*gbdfmbo"mne3-u5Z5Xign;<=>>2g9mkwk`mg$m`obd/ujqijb(ilfdkdm c`g1+s7X<Vkeh=>?000g?kiuenoe"kbmlj-wlwkhl&km`bifc.abb4)di{xrbhz30?0g?kiuenoe"kbmlj-wlwkhl&km`bifc.abb4)di{xrbhz31?0g?kiuenoe"kbmlj-wlwkhl&km`bifc.abb4)di{xrbhz32?0g?kiuenoe"kbmlj-wlwkhl&km`bifc.abb4)di{xrbhz33?1f?kiuenoe"kbmlj-wlwkhl&km`bifc.abb4)byjkxi#lfg/oot^6Z&oy
\7f"`hfrrv0f>hhzdmnb#hcbmi,pmtjgm%jjaahib-`ec7(mxij
\7fh mif,nhu]6U'gbh#cly2`8jjtjold%jalck.vkvhic'hlgcjgl/bce5*cvkhyn"ogh.lns_7[)e`n%anw<b:llvhabf'lgnae tipnka)fneelen!lag3,atef{l$iej blqY0Y+knl'ghu>l4nnpnc`h)nehgg"zgrlmg+d`kgnch#noi1.grgdub&kcl"`b
\7f[5_-ilb)ejs9;6``rlefj+`kjea$xe|boe-bbii`aj%hmk? v0>3:71<ffxfkh`!fm`oo*rozdeo#lhcofk`+fga9&|:0<0=7:llvhabf'lgnae tipnka)fneelen!lag3,r4:56;=0bb|bgdl-bidkc&~c~`ak/`dokbod'jkm="x><2<13>hhzdmnb#hcbmi,pmtjgm%jjaahib-`ec7(~86?2?h4nnpnc`h)nehgg"zgrlmg+d`kgnch#noi1.t2[5Yffm:;<=?=f:llvhabf'lgnae tipnka)fneelen!lag3,r4Y6Whdo<=>?13d8jjtjold%jalck.vkvhic'hlgcjgl/bce5*p6W;Ujbi>?0131b>hhzdmnb#hcbmi,pmtjgm%jjaahib-`ec7(~8U8Sl`k012357`<ffxfkh`!fm`oo*rozdeo#lhcofk`+fga9&|:S9Qnne234575l2dd~`ijn/dofim(|axfci!nfmmdmf)dio8$ol|}yogw8585l2dd~`ijn/dofim(|axfci!nfmmdmf)dio8$ol|}yogw8485l2dd~`ijn/dofim(|axfci!nfmmdmf)dio8$ol|}yogw8785l2dd~`ijn/dofim(|axfci!nfmmdmf)dio8$ol|}yogw8684m2dd~`ijn/dofim(|axfci!nfmmdmf)dio8$i|mnsd,amb(jdyQ;Q#h|t/oemwus;k1ec
\7fcheo,ehgjl'}byabj agnlcle(khl9#h
\7flarg-fla)eezP=P bie,ng|5e3geyajka.gnahn)s`{gdh"oilnejg*efn;%n}no|e/`jc+kkxR8V"`gk.laz7g=ig{glic ilcnh+qnuefn$mkb`gha,gd`5'l{hm~k!bhe-iiv\;T$fei bcx1a?kiuenoe"kbmlj-wlwkhl&km`bifc.abb7)byjkxi#lfg/oot^2Z&dco"`mv269mkwk`mg$m`obd/ujqijb(iofdkdm c`d1+s7;878<7ca}mfgm*cjedb%
\7fd
\7fc`d.cehjank&ijj?!y1=3=62=ig{glic ilcnh+qnuefn$mkb`gha,gd`5'
\7f;7>3<8;omqibci&ofi`f!{hsol`*gadfmbo"mnf3-u5959:>1ec
\7fcheo,ehgjl'}byabj agnlcle(khl9#{?34?0e?kiuenoe"kbmlj-wlwkhl&km`bifc.abb7)q9V:Tmcj?01226c=ig{glic ilcnh+qnuefn$mkb`gha,gd`5'
\7f;T=Road123444a3geyajka.gnahn)s`{gdh"oilnejg*efn;%}=R<Paof34566:o1ec
\7fcheo,ehgjl'}byabj agnlcle(khl9#{?P3^cm`567888m7ca}mfgm*cjedb%
\7fd
\7fc`d.cehjank&ijj?!y1^6\ekb789::>55aosodak(adkf`#yf}mnf,aii`aj%NA]ZV_OMMV@A5j2dd~`ijn/dofim(|axfci!jlnejg*CJX]STBB@]EF]j571<ffxfkh`!fm`oo*rozdeo#hb`gha,VDKXMDZ_URg=a:llvhabf'lgnae tipnka)bdfmbo"m>/bcqv|hb|5:5>l5aosodak(adkf`#yf}mnf,aii`aj%h="mnrs{maq:66;k0bb|bgdl-bidkc&~c~`ak/dnlcle(k8%hm
\7f|vndv?6;4f3geyajka.gnahn)s`{gdh"kcofk`+f7(khxyuck{<2<0f>hhzdmnb#hcbmi,pmtjgm%n`bifc.a2+`wdizo%ndi!mmrX4X(a{}$fjd||t2:8jjtjold%jalck.vkvhic'lfdkdm c0-fufgtm'hbk#ccpZ3^*hoc&dir?55aosodak(adkf`#yf}mnf,aii`aj%h="k~c`qf*go`&df{W?S!mhf-if
\7f402dd~`ijn/dofim(|axfci!jlnejg*e6'l{hm~k!bhe-iiv\;T$fei bcx1;?kiuenoe"kbmlj-wlwkhl&ogcjgl/b3,atef{l$iej blqY7Y+knl'ghu?:4nnpnc`h)nehgg"zgrlmg+`jho`i$o<!y1=2=61=ig{glic ilcnh+qnuefn$iaahib-`5*p6484986``rlefj+`kjea$xe|boe-fhjank&i:#{?32?07?kiuenoe"kbmlj-wlwkhl&ogcjgl/b3,r4:46;>0bb|bgdl-bidkc&~c~`ak/dnlcle(k8%}=1:12b9mkwk`mg$m`obd/ujqijb(meelen!l1.t2[5Yffm:;<=?=c:llvhabf'lgnae tipnka)bdfmbo"m>/w3\5Zgil9:;<<<l;omqibci&ofi`f!{hsol`*ckgnch#n? v0]1[dhc89:;=?m4nnpnc`h)nehgg"zgrlmg+`jho`i$o<!y1^1\ekb789::>n5aosodak(adkf`#yf}mnf,aii`aj%h="x>_5]bja6789;9m6``rlefj+`kjea$xe|boe-fhjank&i9#no}rxlfp969:h1ec
\7fcheo,ehgjl'}byabj emmdmf)d:&ij~
\7fwaeu>2:7g<ffxfkh`!fm`oo*rozdeo#hb`gha,g7)di{xrbhz32?0b?kiuenoe"kbmlj-wlwkhl&ogcjgl/b0,gdtuqgo
\7f0>0<b:llvhabf'lgnae tipnka)bdfmbo"m=/ds`evc)j`m%aa~T0\,ewq(jn`xxx>64nnpnc`h)nehgg"zgrlmg+`jho`i$o?!jqbcpa+dno'gg|V?R.lkg*he~;11ec
\7fcheo,ehgjl'}byabj emmdmf)d:&ozol}j.ckd*hjwS;W%adj!mb{0<>hhzdmnb#hcbmi,pmtjgm%n`bifc.a1+`wdizo%ndi!mmrX7X(jam$fot=7;omqibci&ofi`f!{hsol`*ckgnch#n< epabw`(ean$f`}U;]/oj`+kdq;>0bb|bgdl-bidkc&~c~`ak/dnlcle(k;%}=1>1259mkwk`mg$m`obd/ujqijb(meelen!l2.t28485<2dd~`ijn/dofim(|axfci!jlnejg*e5'
\7f;7>3<;;omqibci&ofi`f!{hsol`*ckgnch#n< v0>0:72<ffxfkh`!fm`oo*rozdeo#hb`gha,g7)q95>5>n5aosodak(adkf`#yf}mnf,aii`aj%h>"x>_1]bja6789;9o6``rlefj+`kjea$xe|boe-fhjank&i9#{?P1^cm`567888h7ca}mfgm*cjedb%
\7fd
\7fc`d.gokbod'j8$z<Q=_`lg45679;i0bb|bgdl-bidkc&~c~`ak/dnlcle(k;%}=R=Paof34566:j1ec
\7fcheo,ehgjl'}byabj emmdmf)d:&|:S9Qnne234575<2dd~`ijn/dofim(|axfci!jlnejg*ehey;dyy<;;omqibci&ofi`f!{hsol`*ckgnch#nabp3mvp71<ffxfkh`!fm`oo*rozdeo#kb`gha,BPJKWGEE^HI=a:llvhabf'lgnae tipnka)adfmbo"HZLM]MKKTBOVc:>;5aosodak(adkf`#yf}mnf,bii`aj%YM@QIUMN\m7b<ffxfkh`!fm`oo*rozdeo#kb`gha,gjkw9&ij~
\7fwaeu>3:7b<ffxfkh`!fm`oo*rozdeo#kb`gha,gjkw9&ij~
\7fwaeu>2:7b<ffxfkh`!fm`oo*rozdeo#kb`gha,gjkw9&ij~
\7fwaeu>1:7b<ffxfkh`!fm`oo*rozdeo#kb`gha,gjkw9&ij~
\7fwaeu>0:6c<ffxfkh`!fm`oo*rozdeo#kb`gha,gjkw9&ozol}j.ckd*hjwS9W%j~z!mgkqwq5e3geyajka.gnahn)s`{gdh"hcofk`+fijx8%n}no|e/`jc+kkxR;V"`gk.laz7g=ig{glic ilcnh+qnuefn$jaahib-`khv6'l{hm~k!bhe-iiv\:T$fei bcx1a?kiuenoe"kbmlj-wlwkhl&lgcjgl/bmnt4)byjkxi#lfg/oot^5Z&dco"`mv3c9mkwk`mg$m`obd/ujqijb(neelen!lolr2+`wdizo%ndi!mmrX0X(jam$fot<8;omqibci&ofi`f!{hsol`*`kgnch#nabp0-u5969:>1ec
\7fcheo,ehgjl'}byabj fmmdmf)dgdz:#{?31?04?kiuenoe"kbmlj-wlwkhl&lgcjgl/bmnt4)q9585>:5aosodak(adkf`#yf}mnf,bii`aj%hc`~>/w3?7;403geyajka.gnahn)s`{gdh"hcofk`+fijx8%}=1:12g9mkwk`mg$m`obd/ujqijb(neelen!lolr2+s7X8Vkeh=>?000e?kiuenoe"kbmlj-wlwkhl&lgcjgl/bmnt4)q9V;Tmcj?01226c=ig{glic ilcnh+qnuefn$jaahib-`khv6'
\7f;T>Road123444a3geyajka.gnahn)s`{gdh"hcofk`+fijx8%}=R=Paof34566:o1ec
\7fcheo,ehgjl'}byabj fmmdmf)dgdz:#{?P4^cm`567888o7ca}mfgm*cjedb%
\7fd
\7fc`d.dokbod'jef|?!laspzj`r;878o7ca}mfgm*cjedb%
\7fd
\7fc`d.dokbod'jef|?!laspzj`r;978o7ca}mfgm*cjedb%
\7fd
\7fc`d.dokbod'jef|?!laspzj`r;:78o7ca}mfgm*cjedb%
\7fd
\7fc`d.dokbod'jef|?!laspzj`r;;79n7ca}mfgm*cjedb%
\7fd
\7fc`d.dokbod'jef|?!jqbcpa+dno'gg|V>R.gqw*h`nzz~8n6``rlefj+`kjea$xe|boe-ehjank&ida}< epabw`(ean$f`}U>]/oj`+kdq:h0bb|bgdl-bidkc&~c~`ak/gnlcle(kfg{>"k~c`qf*go`&df{W?S!mhf-if
\7f4j2dd~`ijn/dofim(|axfci!ilnejg*ehey8$i|mnsd,amb(jdyQ8Q#cfd/o`}6d<ffxfkh`!fm`oo*rozdeo#kb`gha,gjkw:&ozol}j.ckd*hjwS=W%adj!mb{13>hhzdmnb#hcbmi,pmtjgm%m`bifc.aliu4(~86;2?94nnpnc`h)nehgg"zgrlmg+cjho`i$obc
\7f2.t28485?2dd~`ijn/dofim(|axfci!ilnejg*ehey8$z<2=>358jjtjold%jalck.vkvhic'ofdkdm cnos6*p64:49;6``rlefj+`kjea$xe|boe-ehjank&ida}< v0>7:7`<ffxfkh`!fm`oo*rozdeo#kb`gha,gjkw:&|:S=Qnne234575n2dd~`ijn/dofim(|axfci!ilnejg*ehey8$z<Q>_`lg45679;l0bb|bgdl-bidkc&~c~`ak/gnlcle(kfg{>"x>_3]bja6789;9j6``rlefj+`kjea$xe|boe-ehjank&ida}< v0]0[dhc89:;=?h4nnpnc`h)nehgg"zgrlmg+cjho`i$obc
\7f2.t2[1Yffm:;<=?=6:llvhabf'lgnae tipnka)adfmbo"m`mq]eqij6:?1ec
\7fcheo,ehgjl'}byabj fmmdmf)dgdzTjxbc2328jjtjold%jalck.vntZvi|{UySigif=2=65=ig{glic ilcnh+qkwWyd
\7f~RyPdhde858582dd~`ijn/dofim(
\7fyxnabj R@O\SWYBF8;m7ca}mfgm*cjedb%|~Rjnt`]`kphsW`U;=k5aosodak(adkf`#z|Pd`vb[firf}UbS<?i;omqibci&ofi`f!xr^fbpdYdg|d
\7fSdQ=1g9mkwk`mg$m`obd/vp\`drfWje~byQf_23e?kiuenoe"kbmlj-tvZbf|hUhcx`{_h]75c=ig{glic ilcnh+rtXlh~jSnaznu]j[07a3geyajka.gnahn)pzVnjxlQlotlw[lY19o1ec
\7fcheo,ehgjl'~xThlzn_bmvjqYnW>;m7ca}mfgm*cjedb%|~Rjnt`]`kphsW`U3=k5aosodak(adkf`#z|Pd`vb[firf}UbS4?8;omqibci&`di`f!}d^pppZ`e9h1ec
\7fcheo,jjgjl'{nT~~zPiov\44><ffxfkh`!io`oo*tcW{y
\7fS
\7fkh169mkwk`mg$bbobd/vp\vvrXnk;37ca}mfgm*lhedb%|~R||t^pfc3?<ffxfkh`!mdoahn)eelg%n`i!ble\mkus'kf`S`kb_fgmawgsg{%}magk.bqwv*tfeeed|V>R.scn*w)q<'xja"]KP/QJJBJBWYXBA#]KP0a8jjtjold%ahcmlj-wiuYuidUyhRka1e9mkwk`mg$fi`lck.vntZtfeVxoSh`>8:muaw`kg~k0|
\7fah_dosp|733yxdkRkbpu{\pmtb{a";%<:4psmd[`kw|pU
\7fd
\7fk|h)3*51=wzfmTi`~{y^vkv`uo ;#:86~}of]fiur~W}byi~f'3(37?uthoVof|ywPtipfwm.3!8>0|
\7fah_dosp|Ys`{oxd%;&159svjaXmdz
\7fuRzgrdqk,3/6<2zycjQjmqvz[qnumzb#;$?;;qplcZcjx}sTxe|jsi*;-42<x{elShc
\7ftx]wlwct`!3"=95
\7frne\ahvsqV~c~h}g<1<20>vugnUna}zv_ujqavn;97;?7}|`g^gntq
\7fX|axn
\7fe2=>068twi`Wlg{xtQ{hsgpl9599=1{~biPelrw}Zrozlyc090>4:rqkbYbey~rSyf}erj?1;733yxdkRkbpu{\pmtb{a6=2<:4psmd[`kw|pU
\7fd
\7fk|h=5=51=wzfmTi`~{y^vkv`uo414::6~}of]fiur~W}byi~f39;2=51=wzfmTi`~{y^vkv`uo404:n6~}of]fiur~W}byi~fParqfvq.7!8h0|
\7fah_dosp|Ys`{oxdRo|sdpw,4/6j2zycjQjmqvz[qnumzbTm~}jru*1-4d<x{elShc
\7ftx]wlwct`Vkx
\7fh|{(2+2f>vugnUna}zv_ujqavnXizyn~y&;)0`8twi`Wlg{xtQ{hsgplZgt{lx
\7f$8'>b:rqkbYbey~rSyf}erj\evubz}"=%<l4psmd[`kw|pU
\7fd
\7fk|h^cpw`ts >#:n6~}of]fiur~W}byi~fParqfvq.?!8h0|
\7fah_dosp|Ys`{oxdRo|sdpw,</6j2zycjQjmqvz[qnumzbTm~}jru>3:4d<x{elShc
\7ftx]wlwct`Vkx
\7fh|{<0<2f>vugnUna}zv_ujqavnXizyn~y2=>0`8twi`Wlg{xtQ{hsgplZgt{lx
\7f0>0>b:rqkbYbey~rSyf}erj\evubz}6?2<l4psmd[`kw|pU
\7fd
\7fk|h^cpw`ts4<4:n6~}of]fiur~W}byi~fParqfvq:168h0|
\7fah_dosp|Ys`{oxdRo|sdpw8286j2zycjQjmqvz[qnumzbTm~}jru>;:4b<x{elShc
\7ftx]wlwct`Vkx
\7fh|{<883:4d<x{elShc
\7ftx]wlwct`Vkx
\7fh|{<8<2f>vugnUna}zv_ujqavnXflmjxh&?)0`8twi`Wlg{xtQ{hsgplZhboh~n$<'>b:rqkbYbey~rSyf}erj\j`af|l"9%<l4psmd[`kw|pU
\7fd
\7fk|h^lfcdrb :#:n6~}of]fiur~W}byi~fPndebp`.3!8h0|
\7fah_dosp|Ys`{oxdR`jg`vf,0/6j2zycjQjmqvz[qnumzbTbhintd*5-4d<x{elShc
\7ftx]wlwct`Vdnklzj(6+2f>vugnUna}zv_ujqavnXflmjxh&7)0`8twi`Wlg{xtQ{hsgplZhboh~n$4'>b:rqkbYbey~rSyf}erj\j`af|l6;2<l4psmd[`kw|pU
\7fd
\7fk|h^lfcdrb484:n6~}of]fiur~W}byi~fPndebp`:568h0|
\7fah_dosp|Ys`{oxdR`jg`vf8686j2zycjQjmqvz[qnumzbTbhintd>7:4d<x{elShc
\7ftx]wlwct`Vdnklzj<4<2f>vugnUna}zv_ujqavnXflmjxh29>0`8twi`Wlg{xtQ{hsgplZhboh~n0:0>b:rqkbYbey~rSyf}erj\j`af|l632<j4psmd[`kw|pU
\7fd
\7fk|h^lfcdrb400;2<l4psmd[`kw|pU
\7fd
\7fk|h^lfcdrb40427}|`g^dvhi743yxdkRhzlm]wlwct`!:"=>5
\7frne\bpjkW}byi~f'1(30?uthoVl~`aQ{hsgpl-4.9:1{~biPftno[qnumzb#?$?<;qplcZ`rdeU
\7fd
\7fk|h)6*56=wzfmTjxbc_ujqavn/= ;87}|`g^dvhiYs`{oxd%8&129svjaXn|fgSyf}erj+3,743yxdkRhzlm]wlwct`!2"=>5
\7frne\bpjkW}byi~f'9(30?uthoVl~`aQ{hsgpl9699:1{~biPftno[qnumzb7=3?<;qplcZ`rdeU
\7fd
\7fk|h=0=56=wzfmTjxbc_ujqavn;;7;87}|`g^dvhiYs`{oxd1:1129svjaXn|fgSyf}erj?1;743yxdkRhzlm]wlwct`5<5=>5
\7frne\bpjkW}byi~f37?30?uthoVl~`aQ{hsgpl9>99<1{~biPftno[qnumzb757>1129svjaXn|fgSyf}erj?=;7f3yxdkRhzlm]wlwct`Vkx
\7fh|{(1+2e>vugnUmyabPtipfwmYf{zoyx%?&1`9svjaXn|fgSyf}erj\evubz}"9%<o4psmd[cskdV~c~h}g_`qpawr/; ;j7}|`g^dvhiYs`{oxdRo|sdpw,1/6i2zycjQiumn\pmtb{aUj
\7f~k}t)7*5d=wzfmTjxbc_ujqavnXizyn~y&9)0c8twi`Wo
\7fg`Rzgrdqk[dutm{~#;$?n;qplcZ`rdeU
\7fd
\7fk|h^cpw`ts 1#:m6~}of]eqijX|axn
\7feQnsrgqp-?.9h1{~biPftno[qnumzbTm~}jru>3:4g<x{elSk{cl^vkv`uoWhyxi
\7fz31?3b?uthoVl~`aQ{hsgplZgt{lx
\7f0?0>a:rqkbYa}efTxe|jsi]bwvcu|595=l5
\7frne\bpjkW}byi~fParqfvq:368k0|
\7fah_gwohZrozlycSl}|esv?1;7f3yxdkRhzlm]wlwct`Vkx
\7fh|{<7<2e>vugnUmyabPtipfwmYf{zoyx1911`9svjaXn|fgSyf}erj\evubz}632<m4psmd[cskdV~c~h}g_`qpawr;13:5=l5
\7frne\bpjkW}byi~fParqfvq:>68k0|
\7fah_gwohZrozlycSckhaug+4,7f3yxdkRhzlm]wlwct`Vdnklzj(0+2e>vugnUmyabPtipfwmYimnk
\7fi%<&1`9svjaXn|fgSyf}erj\j`af|l"8%<o4psmd[cskdV~c~h}g_ogdeqc/< ;j7}|`g^dvhiYs`{oxdR`jg`vf,0/6i2zycjQiumn\pmtb{aUeijo{e)4*5d=wzfmTjxbc_ujqavnXflmjxh&8)0c8twi`Wo
\7fg`Rzgrdqk[kc`i}o#4$?n;qplcZ`rdeU
\7fd
\7fk|h^lfcdrb 0#:m6~}of]eqijX|axn
\7feQaefcwa9699h1{~biPftno[qnumzbTbhintd>2:4g<x{elSk{cl^vkv`uoWgolmyk32?3b?uthoVl~`aQ{hsgplZhboh~n0>0>a:rqkbYa}efTxe|jsi]mabgsm5>5=l5
\7frne\bpjkW}byi~fPndebp`:268k0|
\7fah_gwohZrozlycSckhaug?2;7f3yxdkRhzlm]wlwct`Vdnklzj<6<2e>vugnUmyabPtipfwmYimnk
\7fi1611b9svjaXn|fgSyf}erj\j`af|l626=0>a:rqkbYa}efTxe|jsi]mabgsm535:6|k_bnh55=ulVnjxlQlotlw,5/682xoSio{a^alqkr/9 ;;7
\7fjPd`vb[firf}"9%<>4re]geqgXkf
\7fex%=&119q`Zbf|hUhcx`{(5+24>tcWmk
\7fmRm`uov+1,773{nThlzn_bmvjq.1!8:0~iQkauc\gjsi|!="==5}d^fbpdYdg|d
\7f$5'>0:pg[agsiVidycz'9(33?wbXlh~jSnaznu>3:46<zmUomyoPcnwmp979991yhRjnt`]`kphs4;4:<6|k_ecweZeh}g~7?3??;sf\`drfWje~by2;>028vaYci}kTob{at=7=55=ulVnjxlQlotlw838682xoSio{a^alqkr;?7;;7
\7fjPd`vb[firf}632<<4re]geqgXkf
\7fex1750?33?wbXlh~jSnaznu>::0=ulVoe:6|k_sqw7>tt|>1xndzjrs68wwus9;1
\7f~ox=_unh[dvnWocmc?m4ts`u6ZrkcVk{eRhffn]emciXoldn~lz`r^t0[6Y
\7f{}U:56{addpehjq23
\7fkgei84ws]bgn0<
\7f{Uh`f??;vp\`drfWje~by&?)028swYci}kTob{at)3*55=pzVnjxlQlotlw,7/682}ySio{a^alqkr/; ;;7z|Pd`vb[firf}"?%<>4ws]geqgXkf
\7fex%;&119tvZbf|hUhcx`{(7+24>quWmk
\7fmRm`uov+3,773~xThlzn_bmvjq.?!8:0{
\7fQkauc\gjsi|!3"==5xr^fbpdYdg|d
\7f0=0>0:uq[agsiVidycz31?33?rtXlh~jSnaznu>1:46<
\7f{UomyoPcnwmp959991|~Rjnt`]`kphs4=4:<6y}_ecweZeh}g~793??;vp\`drfWje~by29>028swYci}kTob{at=5=55=pzVnjxlQlotlw8=86:2}ySio{a^alqkr;13:5==5xr^fbpdYdg|d
\7f040:;vp\ak0<
\7f{Uy
\7fy?>;Âɾ¹Ã¸ÐÄÍ´Ì°²Þ·³»g8Õǹ×Ä·ÝηÄγÅÄ
\7fCDu770k1KLu<6c;D90?7|[?k1?9?55;306155;3;2mk7tn3;6>4=i:0<186*=9281<f=z[?31?9?55;306155;3;2mk74S0ca>621290:??:<2282=d`f3Z<26>:9:1827724::0:5lhj;e4`b?6=93;p_;o535391?74:=99?7?6ag;8 7?62:>87{Z=6383>4<62;>=w^8n:262>0<6;;>8>>4>9`d:?!41m3;jo6X=9581
\7fp7e:3;0y<l<:19~ 7662:80n;mi:180b?5=;oqC>;l4Z4g90~7b28l1>84=3;
\7f'631=>jl0(?7>:260?_4>:38p?9=53519yl0di3:17b8me;29 7642?i37c<?2;28?j0el3:1(?><:7a;?k47:3;07b8mc;29 7642?i37c<?2;08?j0ej3:1(?><:7a;?k47:3907b8ma;29 7642?i37c<?2;68?j0e13:1(?><:7a;?k47:3?07b8m8;29 7642?i37c<?2;48?j0e?3:1(?><:7a;?k47:3=07b8m6;29 7642?i37c<?2;:8?j0e=3:1(?><:7a;?k47:3307d8ja;29?j0cm3:1(?><:7g;?k47:3:07b8kd;29 7642?o37c<?2;38?j0ck3:1(?><:7g;?k47:3807b8kb;29 7642?o37c<?2;18?j0ci3:1(?><:7g;?k47:3>07b8k9;29 7642?o37c<?2;78?j0c03:1(?><:7g;?k47:3<07b8k7;29 7642?o37c<?2;58?j0c>3:1(?><:7g;?k47:3207b8k5;29 7642?o37c<?2;;8?j53=3:17b=;2;29?l0c<3:17d8lc;29?j55=3:1(?><:215?k47:3:07b==4;29 7642:9=7c<?2;38?j55;3:1(?><:215?k47:3807b==2;29 7642:9=7c<?2;18?j5593:1(?><:215?k47:3>07b==0;29 7642:9=7c<?2;78?j56n3:1(?><:215?k47:3<07b=>e;29 7642:9=7c<?2;58?j55l3:1(?><:215?k47:3207b==c;29 7642:9=7c<?2;;8?j55j3:1(?><:215?k47:3k07b==a;29 7642:9=7c<?2;`8?j5513:1(?><:215?k47:3i07b==8;29 7642:9=7c<?2;f8?j55?3:1(?><:215?k47:3o07b==6;29 7642:9=7c<?2;d8?j56l3:1(?><:215?k47:3;;76a<1b83>!47;398:6`=03825>=n;9:1<7*=028054=i:981<65f2gd94?"58:08=<5a21095>=n:oo1<7*=028054=i:981>65f2gf94?"58:08=<5a21097>=n:oi1<7*=028054=i:981865f2g`94?"58:08=<5a21091>=n:ok1<7*=028054=i:981:65f2g;94?"58:08=<5a21093>=n;921<7*=028054=i:981465f31594?"58:08=<5a2109=>=n;9<1<7*=028054=i:981m65f31794?"58:08=<5a2109f>=n;9>1<7*=028054=i:981o65f31194?"58:08=<5a2109`>=n;981<7*=028054=i:981i65f31394?"58:08=<5a2109b>=n:o21<7*=028054=i:981==54i3d4>5<#:991?<?4n321>47<3`<i87>5;c05`?6=93:1<vF=6c9'631=:?n0c?>?:188yg72<3:1=7>50zJ12g=#:?=1=8:4o070>5<<uk?o6=465;19<0}O:?h0V8k517y`>46=9l0o6<h5f;06>75=980::7k51782b?4228o1h7<<:03955<a2l0h6p*=6685`5=#9h31=8<4$3;2>6243-;mm7?ie:m1=2<722c=oo4?::k57`<72-8;?78;8:l147<732c=?i4?:%037?0302d9<?4>;:k57f<72-8;?78;8:l147<532c=?o4?:%037?0302d9<?4<;:k57d<72-8;?78;8:l147<332c=?44?:%037?0302d9<?4:;:k57=<72-8;?78;8:l147<132c=?:4?:%037?0302d9<?48;:k573<72-8;?78;8:l147<?32c=?84?:%037?0302d9<?46;:m531<722c=oh4?::m5`7<722c=5>4?:%037?0>l2d9<?4?;:k5=7<72-8;?786d:l147<632c=5<4?:%037?0>l2d9<?4=;:k5=5<72-8;?786d:l147<432c=4k4?:%037?0>l2d9<?4;;:k5<`<72-8;?786d:l147<232c=4i4?:%037?0>l2d9<?49;:k5<f<72-8;?786d:l147<032c=4o4?:%037?0>l2d9<?47;:k5<d<72-8;?786d:l147<>32c=ol4?::m571<722e=?>4?::k1=d<722e=nh4?:%037?0d02d9<?4?;:m5fa<72-8;?78l8:l147<632e=nn4?:%037?0d02d9<?4=;:m5fg<72-8;?78l8:l147<432e=nl4?:%037?0d02d9<?4;;:m5f<<72-8;?78l8:l147<232e=n54?:%037?0d02d9<?49;:m5f2<72-8;?78l8:l147<032e=n;4?:%037?0d02d9<?47;:m5f0<72-8;?78l8:l147<>32c=9>4?:%037?02l2d9<?4?;:k517<72-8;?78:d:l147<632c=9<4?:%037?02l2d9<?4=;:k515<72-8;?78:d:l147<432c=8k4?:%037?02l2d9<?4;;:k50`<72-8;?78:d:l147<232c=8i4?:%037?02l2d9<?49;:k50f<72-8;?78:d:l147<032c=8o4?:%037?02l2d9<?47;:k50d<72-8;?78:d:l147<>32c=il4?::m5``<72-8;?78j8:l147<732e=hi4?:%037?0b02d9<?4>;:m5`f<72-8;?78j8:l147<532e=ho4?:%037?0b02d9<?4<;:m5`d<72-8;?78j8:l147<332e=h44?:%037?0b02d9<?4:;:m5`=<72-8;?78j8:l147<132e=h:4?:%037?0b02d9<?48;:m5`3<72-8;?78j8:l147<?32e=h84?:%037?0b02d9<?46;:m000<722e88?4?::k5`1<722c=;h4?:%037?0?02d9<?4?;:k53a<72-8;?7878:l147<632c=;n4?:%037?0?02d9<?4=;:k53g<72-8;?7878:l147<432c=;l4?:%037?0?02d9<?4;;:k53<<72-8;?7878:l147<232c=;54?:%037?0?02d9<?49;:k532<72-8;?7878:l147<032c=;;4?:%037?0?02d9<?47;:k530<72-8;?7878:l147<>32c95o4?::k5ag<722e=oi4?::m5`6<722e=h<4?::k5gf<722e8>84?:%037?54>2d9<?4?;:m061<72-8;?7=<6:l147<632e8>>4?:%037?54>2d9<?4=;:m067<72-8;?7=<6:l147<432e8><4?:%037?54>2d9<?4;;:m065<72-8;?7=<6:l147<232e8=k4?:%037?54>2d9<?49;:m05`<72-8;?7=<6:l147<032e8>i4?:%037?54>2d9<?47;:m06f<72-8;?7=<6:l147<>32e8>o4?:%037?54>2d9<?4n;:m06d<72-8;?7=<6:l147<e32e8>44?:%037?54>2d9<?4l;:m06=<72-8;?7=<6:l147<c32e8>:4?:%037?54>2d9<?4j;:m063<72-8;?7=<6:l147<a32e8=i4?:%037?54>2d9<?4>0:9l74e=83.9<>4<379m654=9810e>>?:18'655=;8;0b?>=:198m7`a290/>==53038j7652810e?hj:18'655=;8;0b?>=:398m7`c290/>==53038j7652:10e?hl:18'655=;8;0b?>=:598m7`e290/>==53038j7652<10e?hn:18'655=;8;0b?>=:798m7`>290/>==53038j7652>10e>>7:18'655=;8;0b?>=:998m660290/>==53038j7652010e>>9:18'655=;8;0b?>=:`98m662290/>==53038j7652k10e>>;:18'655=;8;0b?>=:b98m664290/>==53038j7652m10e>>=:18'655=;8;0b?>=:d98m666290/>==53038j7652o10e?h7:18'655=;8;0b?>=:028?l4a?3:1(?><:232?k47:3;:76a=9983>>o5100;66g9a983>!47;3<i>6`=0383?>o1i>0;6)<?3;4a6>h58;0:76g9a783>!47;3<i>6`=0381?>o1i<0;6)<?3;4a6>h58;0876g9a583>!47;3<i>6`=0387?>o1i:0;6)<?3;4a6>h58;0>76g9a383>!47;3<i>6`=0385?>o1i80;6)<?3;4a6>h58;0<76g9a183>!47;3<i>6`=038;?>o11o0;6)<?3;4a6>h58;0276a=a783>!47;38j46`=0383?>i5i<0;6)<?3;0b<>h58;0:76a=a583>!47;38j46`=0381?>i5i:0;6)<?3;0b<>h58;0876a=a383>!47;38j46`=0387?>i5i80;6)<?3;0b<>h58;0>76a=a183>!47;38j46`=0385?>i51o0;6)<?3;0b<>h58;0<76a=9d83>!47;38j46`=038;?>i51m0;6)<?3;0b<>h58;0276a=a883>>o1>10;6)<?3;446>h58;0;76g96683>!47;3<<>6`=0382?>o1>?0;6)<?3;446>h58;0976g96483>!47;3<<>6`=0380?>o1>=0;6)<?3;446>h58;0?76g96283>!47;3<<>6`=0386?>o1>;0;6)<?3;446>h58;0=76g96083>!47;3<<>6`=0384?>o1>90;6)<?3;446>h58;0376g95g83>!47;3<<>6`=038:?>o1j=0;66l=8g83>4<729q/>;951468L7>b3A8=n6a>5283>>{e:?21<7k>:0g7>76?sA8=n6*=668001=]=l0:?v?l:0f952<603;26<=51482e?7528h1>94>4;5967<e2h026549:|&5aa<1mj1d:h4?::m5`?6=3`8>57>5;n7a>5<<a;?n6=44o7a94?=h>o0;66a=7d83>>i6<>0;66g=8c83>>i5>00;66a:a;29?l43l3:17b?if;29?j41k3:17b?:1;29?j47=3:17d<8f;29?j45?3:17b<jb;29 7642;oj7c<?2;28?j4b13:1(?><:3gb?k47:3;07b<j8;29 7642;oj7c<?2;08?j4b?3:1(?><:3gb?k47:3907b<j6;29 7642;oj7c<?2;68?j4b=3:1(?><:3gb?k47:3?07b<j4;29 7642;oj7c<?2;48?j4b;3:1(?><:3gb?k47:3=07b<j2;29 7642;oj7c<?2;:8?j4b93:1(?><:3gb?k47:3307b<i6;29 7642;l>7c<?2;28?j4a<3:1(?><:3d6?k47:3;07b<i3;29 7642;l>7c<?2;08?j4a:3:1(?><:3d6?k47:3907b<i1;29 7642;l>7c<?2;68?j4a83:1(?><:3d6?k47:3?07b<jf;29 7642;l>7c<?2;48?j4bm3:1(?><:3d6?k47:3=07b<jd;29 7642;l>7c<?2;:8?j4bk3:1(?><:3d6?k47:3307b<m4;29 7642;h87c<?2;28?j4e:3:1(?><:3`0?k47:3;07b<m1;29 7642;h87c<?2;08?j4e83:1(?><:3`0?k47:3907b<nf;29 7642;h87c<?2;68?j4fm3:1(?><:3`0?k47:3?07b<nd;29 7642;h87c<?2;48?j4fk3:1(?><:3`0?k47:3=07b<nb;29 7642;h87c<?2;:8?j4fi3:1(?><:3`0?k47:3307b<mf;29 7642;hn7c<?2;28?j4el3:1(?><:3`f?k47:3;07b<mc;29 7642;hn7c<?2;08?j4ej3:1(?><:3`f?k47:3907b<ma;29 7642;hn7c<?2;68?j4e13:1(?><:3`f?k47:3?07b<m8;29 7642;hn7c<?2;48?j4e?3:1(?><:3`f?k47:3=07b<m6;29 7642;hn7c<?2;:8?j4e=3:1(?><:3`f?k47:3307b<la;29 7642;i27c<?2;28?j4d03:1(?><:3a:?k47:3;07b<l7;29 7642;i27c<?2;08?j4d>3:1(?><:3a:?k47:3907b<l5;29 7642;i27c<?2;68?j4d<3:1(?><:3a:?k47:3?07b<l3;29 7642;i27c<?2;48?j4d:3:1(?><:3a:?k47:3=07b<l1;29 7642;i27c<?2;:8?j4d83:1(?><:3a:?k47:3307b6::18'655=0=1e>=<50:9l<6<72-8;?76;;o036?7<3f296=4+2119<1=i:981>65`8083>!47;32?7c<?2;18?j>7290/>==5859m654=<21d;k4?:%037?>33g8;>7;4;n5f>5<#:991495a21092>=h?m0;6)<?3;:7?k47:3=07b9l:18'655=0=1e>=<58:9l3g<72-8;?76;;o036??<3f83m7>5$320>7>>3g8;>7>4;n0;<?6=,;:86?66;o036?7<3f83;7>5$320>7>>3g8;>7<4;n0;2?6=,;:86?66;o036?5<3f8397>5$320>7>>3g8;>7:4;n0;0?6=,;:86?66;o036?3<3f83?7>5$320>7>>3g8;>784;n0;6?6=,;:86?66;o036?1<3f83=7>5$320>7>>3g8;>764;n0;4?6=,;:86?66;o036??<3f8o97>5$320>7b33g8;>7>4;n0g7?6=,;:86?j;;o036?7<3f8o>7>5$320>7b33g8;>7<4;n0g5?6=,;:86?j;;o036?5<3f8o<7>5$320>7b33g8;>7:4;n0`b?6=,;:86?j;;o036?3<3f8hi7>5$320>7b33g8;>784;n0``?6=,;:86?j;;o036?1<3f8ho7>5$320>7b33g8;>764;n0`f?6=,;:86?j;;o036??<3f=j6=4+21193<=i:981<65`7983>!47;3=27c<?2;38?j10290/>==5789m654=:21d;;4?:%037?1>3g8;>7=4;n56>5<#:991;45a21090>=h?=0;6)<?3;5:?k47:3?07b9<:18'655=?01e>=<56:9l37<72-8;?796;o036?1<3f=:6=4+21193<=i:981465`7183>!47;3=27c<?2;;8?j4b83:1(?><:3fe?k47:3:07b<ke;29 7642;nm7c<?2;38?j4cl3:1(?><:3fe?k47:3807b<kc;29 7642;nm7c<?2;18?j4cj3:1(?><:3fe?k47:3>07b<ka;29 7642;nm7c<?2;78?j4c13:1(?><:3fe?k47:3<07b<k8;29 7642;nm7c<?2;58?j4c?3:1(?><:3fe?k47:3207b<k6;29 7642;nm7c<?2;;8?j74l3:1(?><:01`?k47:3:07b?<b;29 764289h7c<?2;38?j74i3:1(?><:01`?k47:3807b?<9;29 764289h7c<?2;18?j7403:1(?><:01`?k47:3>07b?<7;29 764289h7c<?2;78?j74>3:1(?><:01`?k47:3<07b?<5;29 764289h7c<?2;58?j73>3:1(?><:01`?k47:3207b?;5;29 764289h7c<?2;;8?j73<3:1(?><:01`?k47:3k07b?;3;29 764289h7c<?2;`8?j73:3:1(?><:01`?k47:3i07b?;1;29 764289h7c<?2;f8?j7383:1(?><:01`?k47:3o07b?<f;29 764289h7c<?2;d8?j74m3:1(?><:01`?k47:3;;76a>3583>!47;3;8o6`=03825>=h:<21<7*=028112=i:981<65`24494?"58:099:5a21095>=h:<?1<7*=028112=i:981>65`24694?"58:099:5a21097>=h:<91<7*=028112=i:981865`24094?"58:099:5a21091>=h:<;1<7*=028112=i:981:65`24294?"58:099:5a21093>=h:=l1<7*=028112=i:981465`25g94?"58:099:5a2109=>=n:8h1<7*=02815d=i:981<65f20;94?"58:09=l5a21095>=n:821<7*=02815d=i:981>65f20594?"58:09=l5a21097>=n:8<1<7*=02815d=i:981865f20794?"58:09=l5a21091>=n:8>1<7*=02815d=i:981:65f20194?"58:09=l5a21093>=n:881<7*=02815d=i:981465f20394?"58:09=l5a2109=>=nl;0;6)<?3;f2?k47:3:07dj?:18'655=l81e>=<51:9jgc<72-8;?7j>;o036?4<3`in6=4+2119`4=i:981?65fce83>!47;3n:7c<?2;68?led290/>==5d09m654==21boo4?:%037?b63g8;>784;hab>5<#:991h<5a21093>=nlk0;6)<?3;f2?k47:3207djn:18'655=l81e>=<59:9j`<<72-8;?7j>;o036?g<3`n36=4+2119`4=i:981n65fd683>!47;3n:7c<?2;a8?lb1290/>==5d09m654=l21bh84?:%037?b63g8;>7k4;hf7>5<#:991h<5a2109b>=nl:0;6)<?3;f2?k47:3;;76gl9;29 7642m;0b?>=:038?l4303:1(?><:364?k47:3:07d<;6;29 7642;><7c<?2;38?l43=3:1(?><:364?k47:3807d<;4;29 7642;><7c<?2;18?l43;3:1(?><:364?k47:3>07d<;2;29 7642;><7c<?2;78?l4393:1(?><:364?k47:3<07d<;0;29 7642;><7c<?2;58?l44n3:1(?><:364?k47:3207d<<e;29 7642;><7c<?2;;8?l44l3:1(?><:31`?k47:3:07d<<b;29 7642;9h7c<?2;38?l44i3:1(?><:31`?k47:3807d<<9;29 7642;9h7c<?2;18?l4403:1(?><:31`?k47:3>07d<<7;29 7642;9h7c<?2;78?l44>3:1(?><:31`?k47:3<07d<<5;29 7642;9h7c<?2;58?l44<3:1(?><:31`?k47:3207d<<3;29 7642;9h7c<?2;;8?l44:3:1(?><:312?k47:3:07d<<0;29 7642;9:7c<?2;38?l45n3:1(?><:312?k47:3807d<=e;29 7642;9:7c<?2;18?l45l3:1(?><:312?k47:3>07d<=c;29 7642;9:7c<?2;78?l45j3:1(?><:312?k47:3<07d<=a;29 7642;9:7c<?2;58?l4513:1(?><:312?k47:3207d<=8;29 7642;9:7c<?2;;8?l45>3:1(?><:306?k47:3:07d<=4;29 7642;8>7c<?2;38?l45;3:1(?><:306?k47:3807d<=2;29 7642;8>7c<?2;18?l4593:1(?><:306?k47:3>07d<=0;29 7642;8>7c<?2;78?l46n3:1(?><:306?k47:3<07d<>e;29 7642;8>7c<?2;58?l46l3:1(?><:306?k47:3207d<>c;29 7642;8>7c<?2;;8?l4683:1(?><:32e?k47:3:07d<?e;29 7642;:m7c<?2;38?l47l3:1(?><:32e?k47:3807d<?c;29 7642;:m7c<?2;18?l47j3:1(?><:32e?k47:3>07d<?a;29 7642;:m7c<?2;78?l4713:1(?><:32e?k47:3<07d<?8;29 7642;:m7c<?2;58?l47?3:1(?><:32e?k47:3207d<?6;29 7642;:m7c<?2;;8?g4?n3:1=7>50z&122<6==1C>5k4H34a?j72;3:17pl=9183>4<729q/>;9527f8L7>b3A8=n6a=0183>>{e>;i1<7:50;2x 70028>n7E<7e:J12g=O=j1/=;<51:k6b?6=3`<i6=44i327>5<<g;>26=44}c41b?6==3:1<v*=66820c=O:1o0D?8m;I7`?!71:3;0e8h50;9j21<722c=n7>5;h030?6=3f8?57>5;|`56`<72=0;6=u+275951c<@;2n7E<9b:J6g>"6>;0:7d;i:188m3d=831b>=:50;9l61?=831vn;<k:186>5<7s-8=;7?;f:J1<`=O:?h0D8m4$041>4=n=o0;66g94;29?l0e2900e?>;:188k72>2900qo:=e;291?6=8r.9::4>4g9K6=c<@;<i7)?92;68m0`=831b:94?::k5f?6=3`8;87>5;n07=?6=3th?>i4?:483>5}#:?=1=9j4H3:f?M41j2.::?4>;h7e>5<<a?>1<75f6983>>o1j3:17b<;9;29?xd3;80;684?:1y'631=9=n0D?6j;I05f>"6>;0:7d;i:188m32=831b:54?::k5f?6=3f8?57>5;|`76c<72<0;6=u+275951b<@;2n7E<9b:&227<63`?m6=44i7694?=n>10;66g9b;29?j4313:17pl;3183>0<729q/>;9515f8L7>b3A8=n6*>6382?l3a2900e;:50;9j2=<722c=n7>5;n07=?6=3th??94?:483>5}#:?=1=9j4H3:f?M41j2.::?4>;h7e>5<<a?>1<75f6983>>o1j3:17b<;9;29?xd3;;0;684?:1y'631=9=n0D?6j;I05f>"6>;0:7d;i:188m32=831b:54?::k5f?6=3f8?57>5;|`776<72<0;6=u+275951b<@;2n7E<9b:&227<63`?m6=44i7694?=n>10;66g9b;29?j4313:17pl;3483>0<729q/>;9515f8L7>b3A8=n6*>6382?l3a2900e;:50;9j2=<722c=n7>5;n07=?6=3th??;4?:483>5}#:?=1=9j4H3:f?M41j2.::?4>;h7e>5<<a?>1<75f6983>>o1j3:17b<;9;29?xd38>0;694?:1y'631=9k;0D?6j;I05f>o1=3:17d69:188m73a2900c<hk:188yg2703:187>50z&122<6j81C>5k4H34a?l022900e5850;9j60`=831d=kj50;9~f17>29086=4?{%053?4?l2B94h5G27`8m33=831b=lo50;9l5cb=831vn9>n:187>5<7s-8=;7?m1:J1<`=O:?h0e;;50;9j<3<722c99k4?::m2ba<722wi8<o50;194?6|,;<<6?6k;I0;a>N5>k1b:84?::k2ed<722e:ji4?::
\7fa05e=83>1<7>t$344>4d63A83i6F=6c9j20<722c3:7>5;h06b?6=3f;mh7>5;|`75g<72:0;6=u+27596=b<@;2n7E<9b:k51?6=3`;jm7>5;n3e`?6=3th?<h4?:583>5}#:?=1=o?4H3:f?M41j2c=97>5;h:5>5<<a;?m6=44o0dg>5<<uk>:o7>53;294~"5>>094i5G29g8L70e3`<>6=44i0cb>5<<g8lo6=44}c624?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb53g>5<4290;w)<97;0;`>N50l1C>;l4i7794?=n9hk1<75`1gf94?=zj=;96=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e<8o1<7=50;2x 7002;2o7E<7e:J12g=n><0;66g>a`83>>i6nm0;66sm40694?2=83:p(?88:0`2?M4?m2B9:o5f6483>>o?>3:17d<:f;29?j7al3:17pl;1g83>6<729q/>;9529f8L7>b3A8=n6g95;29?l7fi3:17b?id;29?xd39?0;694?:1y'631=9k;0D?6j;I05f>o1=3:17d69:188m73a2900c<hk:188yg2583:1?7>50z&122<50m1C>5k4H34a?l022900e<on:188k4`c2900qo:=1;297?6=8r.9::4=8e9K6=c<@;<i7d8::188m4gf2900c<hk:188yg5am3:197>50z&122<6<m1C>5k4H34a?!71:3;0e8h50;9j21<722c=47>5;h4a>5<<g;>26=44}c1e`?6==3:1<v*=66820c=O:1o0D?8m;%356?2<a<l1<75f6583>>o1j3:17d<?4;29?j4313:17pl;0083>0<729q/>;9515f8L7>b3A8=n6*>6382?l3a2900e;:50;9j2=<722c=n7>5;n07=?6=3th8jk4?:483>5}#:?=1=9j4H3:f?M41j2.::?4>;h7e>5<<a?>1<75f6983>>o1j3:17b<;9;29?xd3890;684?:1y'631=9=n0D?6j;I05f>"6>;0:7d;i:188m32=831b:54?::k5f?6=3f8?57>5;|`741<72<0;6=u+275951b<@;2n7E<9b:&227<63`?m6=44i7694?=n>10;66g9b;29?j4313:17pl;0383>0<729q/>;9515f8L7>b3A8=n6*>6382?l3a2900e;:50;9j2=<722c=n7>5;n07=?6=3th?<>4?:483>5}#:?=1=9j4H3:f?M41j2.::?4>;h7e>5<<a?>1<75f6983>>o1j3:17b<;9;29?xd38<0;684?:1y'631=9=n0D?6j;I05f>"6>;0:7d;i:188m32=831b:54?::k5f?6=3f8?57>5;|`743<72<0;6=u+275951b<@;2n7E<9b:&227<63`?m6=44i7694?=n>10;66g9b;29?j4313:17pl<d683>1<729q/>;951c38L7>b3A8=n6g95;29?l>12900e?;i:188k4`c2900qo=k8;290?6=8r.9::4>b09K6=c<@;<i7d8::188m=0=831b>8h50;9l5cb=831vn>k6:180>5<7s-8=;7<7d:J1<`=O:?h0e;;50;9j5dg=831d=kj50;9~f6bf290?6=4?{%053?7e92B94h5G27`8m33=831b4;4?::k11c<722e:ji4?::
\7fa7`g=8391<7>t$344>7>c3A83i6F=6c9j20<722c:ml4?::m2ba<722wi?im50;694?6|,;<<6<l>;I0;a>N5>k1b:84?::k;2?6=3`8>j7>5;n3e`?6=3th8io4?:283>5}#:?=1>5j4H3:f?M41j2c=97>5;h3be?6=3f;mh7>5;|`0``<72=0;6=u+27595g7<@;2n7E<9b:k51?6=3`2=6=44i37e>5<<g8lo6=44}c1fg?6=;3:1<v*=6681<a=O:1o0D?8m;h46>5<<a8kj6=44o0dg>5<<uk9n<7>54;294~"5>>0:n<5G29g8L70e3`<>6=44i9494?=n:<l1<75`1gf94?=zj:oo6=4<:183
\7f!41?383h6F=8d9K63d<a??1<75f1`c94?=h9on1<75rb2g1>5<3290;w)<97;3a5>N50l1C>;l4i7794?=n0?0;66g=5g83>>i6nm0;66sm3dg94?5=83:p(?88:3:g?M4?m2B9:o5f6483>>o6ih0;66a>fe83>>{e;l>1<7:50;2x 70028h:7E<7e:J12g=n><0;66g76;29?l42n3:17b?id;29?xd4mo0;6>4?:1y'631=:1n0D?6j;I05f>o1=3:17d?na;29?j7al3:17pl<e783>1<729q/>;951c38L7>b3A8=n6g95;29?l>12900e?;i:188k4`c2900qo=i0;297?6=8r.9::4=8e9K6=c<@;<i7d8::188m4gf2900c<hk:188yg5a93:1?7>50z&122<50m1C>5k4H34a?l022900e<on:188k4`c2900qo=6e;291?6=8r.9::4>4e9K6=c<@;<i7)?92;38m0`=831b:94?::k5<?6=3`<i6=44o36:>5<<uk92h7>55;294~"5>>0:8k5G29g8L70e3-;=>7:4i4d94?=n>=0;66g9b;29?l47<3:17b<;9;29?xd4i80;684?:1y'631=9=n0D?6j;I05f>"6>;0:7d;i:188m32=831b:54?::k5f?6=3f8?57>5;|`0=c<72<0;6=u+275951b<@;2n7E<9b:&227<63`?m6=44i7694?=n>10;66g9b;29?j4313:17pl<a183>0<729q/>;9515f8L7>b3A8=n6*>6382?l3a2900e;:50;9j2=<722c=n7>5;n07=?6=3th8m94?:483>5}#:?=1=9j4H3:f?M41j2.::?4>;h7e>5<<a?>1<75f6983>>o1j3:17b<;9;29?xd4i;0;684?:1y'631=9=n0D?6j;I05f>"6>;0:7d;i:188m32=831b:54?::k5f?6=3f8?57>5;|`0e6<72<0;6=u+275951b<@;2n7E<9b:&227<63`?m6=44i7694?=n>10;66g9b;29?j4313:17pl<a483>0<729q/>;9515f8L7>b3A8=n6*>6382?l3a2900e;:50;9j2=<722c=n7>5;n07=?6=3th8m;4?:483>5}#:?=1=9j4H3:f?M41j2.::?4>;h7e>5<<a?>1<75f6983>>o1j3:17b<;9;29?xd4?>0;694?:1y'631=9k;0D?6j;I05f>o1=3:17d69:188m73a2900c<hk:188yg5003:187>50z&122<6j81C>5k4H34a?l022900e5850;9j60`=831d=kj50;9~f6>>29086=4?{%053?4?l2B94h5G27`8m33=831b=lo50;9l5cb=831vn>9n:187>5<7s-8=;7?m1:J1<`=O:?h0e;;50;9j<3<722c99k4?::m2ba<722wi?5o50;194?6|,;<<6?6k;I0;a>N5>k1b:84?::k2ed<722e:ji4?::
\7fa72e=83>1<7>t$344>4d63A83i6F=6c9j20<722c3:7>5;h06b?6=3f;mh7>5;|`0<g<72:0;6=u+27596=b<@;2n7E<9b:k51?6=3`;jm7>5;n3e`?6=3th8;h4?:583>5}#:?=1=o?4H3:f?M41j2c=97>5;h:5>5<<a;?m6=44o0dg>5<<uk93o7>53;294~"5>>094i5G29g8L70e3`<>6=44i0cb>5<<g8lo6=44}c1;4?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb2:g>5<4290;w)<97;0;`>N50l1C>;l4i7794?=n9hk1<75`1gf94?=zj:296=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e;1o1<7=50;2x 7002;2o7E<7e:J12g=n><0;66g>a`83>>i6nm0;66sm39694?2=83:p(?88:0`2?M4?m2B9:o5f6483>>o?>3:17d<:f;29?j7al3:17pl<8g83>6<729q/>;9529f8L7>b3A8=n6g95;29?l7fi3:17b?id;29?xd40?0;694?:1y'631=9k;0D?6j;I05f>o1=3:17d69:188m73a2900c<hk:188yg5>83:1?7>50z&122<50m1C>5k4H34a?l022900e<on:188k4`c2900qo=61;297?6=8r.9::4=8e9K6=c<@;<i7d8::188m4gf2900c<hk:188yg5dl3:197>50z&122<6<m1C>5k4H34a?!71:3;0e8h50;9j21<722c=47>5;h4a>5<<g;>26=44}c1`a?6==3:1<v*=66820a=O:1o0D?8m;%356?7<a<l1<75f6583>>o103:17d8m:188k72>2900qo=lf;291?6=8r.9::4>4e9K6=c<@;<i7)?92;38m0`=831b:94?::k5<?6=3`<i6=44o36:>5<<uk9o<7>55;294~"5>>0:8i5G29g8L70e3-;=>7?4i4d94?=n>=0;66g98;29?l0e2900c?:6:188yg5c93:197>50z&122<6<m1C>5k4H34a?!71:3;0e8h50;9j21<722c=47>5;h4a>5<<g;>26=44}c1g6?6==3:1<v*=66820a=O:1o0D?8m;%356?7<a<l1<75f6583>>o103:17d8m:188k72>2900qo=k3;291?6=8r.9::4>4e9K6=c<@;<i7)?92;38m0`=831b:94?::k5<?6=3`<i6=44o36:>5<<uk9o87>55;294~"5>>0:8i5G29g8L70e3-;=>7?4i4d94?=n>=0;66g98;29?l0e2900c?:6:188yg5c=3:197>50z&122<6<m1C>5k4H34a?!71:3;0e8h50;9j21<722c=47>5;h4a>5<<g;>26=44}c1g2?6==3:1<v*=66820a=O:1o0D?8m;%356?7<a<l1<75f6583>>o103:17d8m:188k72>2900qo=n7;290?6=8r.9::4>b09K6=c<@;<i7d8::188m=0=831b>8h50;9l5cb=831vn>o7:187>5<7s-8=;7?m1:J1<`=O:?h0e;;50;9j<3<722c99k4?::m2ba<722wi?o750;194?6|,;<<6?6k;I0;a>N5>k1b:84?::k2ed<722e:ji4?::
\7fa7dg=83>1<7>t$344>4d63A83i6F=6c9j20<722c3:7>5;h06b?6=3f;mh7>5;|`0fd<72:0;6=u+27596=b<@;2n7E<9b:k51?6=3`;jm7>5;n3e`?6=3th8mn4?:583>5}#:?=1=o?4H3:f?M41j2c=97>5;h:5>5<<a;?m6=44o0dg>5<<uk9in7>53;294~"5>>094i5G29g8L70e3`<>6=44i0cb>5<<g8lo6=44}c1ba?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb2``>5<4290;w)<97;0;`>N50l1C>;l4i7794?=n9hk1<75`1gf94?=zj:h;6=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e;kn1<7=50;2x 7002;2o7E<7e:J12g=n><0;66g>a`83>>i6nm0;66sm3c094?2=83:p(?88:0`2?M4?m2B9:o5f6483>>o?>3:17d<:f;29?j7al3:17pl<bd83>6<729q/>;9529f8L7>b3A8=n6g95;29?l7fi3:17b?id;29?xd4j=0;694?:1y'631=9k;0D?6j;I05f>o1=3:17d69:188m73a2900c<hk:188yg5en3:1?7>50z&122<50m1C>5k4H34a?l022900e<on:188k4`c2900qo=m6;290?6=8r.9::4>b09K6=c<@;<i7d8::188m=0=831b>8h50;9l5cb=831vn>m?:180>5<7s-8=;7<7d:J1<`=O:?h0e;;50;9j5dg=831d=kj50;9~f6e629086=4?{%053?4?l2B94h5G27`8m33=831b=lo50;9l5cb=831vn>8k:186>5<7s-8=;7?;d:J1<`=O:?h0(<8=:09j1c<722c=87>5;h4;>5<<a?h1<75`25;94?=zj:<n6=4::183
\7f!41?3;?h6F=8d9K63d<,8<96<5f5g83>>o1<3:17d87:188m3d=831d>9750;9~f60a290>6=4?{%053?73l2B94h5G27`8 405281b9k4?::k50?6=3`<36=44i7`94?=h:=31<75rb253>5<2290;w)<97;37`>N50l1C>;l4$041>4=n=o0;66g94;29?l0?2900e;l50;9l61?=831vn>9>:186>5<7s-8=;7?;d:J1<`=O:?h0(<8=:09j1c<722c=87>5;h4;>5<<a?h1<75`25;94?=zj:=96=4::183
\7f!41?3;?h6F=8d9K63d<,8<96<5f5g83>>o1<3:17d87:188m3d=831d>9750;9~f614290>6=4?{%053?73l2B94h5G27`8 405281b9k4?::k50?6=3`<36=44i7`94?=h:=31<75rb257>5<2290;w)<97;37`>N50l1C>;l4$041>4=n=o0;66g94;29?l0?2900e;l50;9l61?=831vn>9::186>5<7s-8=;7?;d:J1<`=O:?h0(<8=:09j1c<722c=87>5;h4;>5<<a?h1<75`25;94?=zj:==6=4::183
\7f!41?3;?h6F=8d9K63d<,8<96<5f5g83>>o1<3:17d87:188m3d=831d>9750;9~f620290?6=4?{%053?7e92B94h5G27`8m33=831b4;4?::k11c<722e:ji4?::
\7fa71>=83>1<7>t$344>4d63A83i6F=6c9j20<722c3:7>5;h06b?6=3f;mh7>5;|`01<<72:0;6=u+27596=b<@;2n7E<9b:k51?6=3`;jm7>5;n3e`?6=3th88l4?:583>5}#:?=1=o?4H3:f?M41j2c=97>5;h:5>5<<a;?m6=44o0dg>5<<uk9>m7>53;294~"5>>094i5G29g8L70e3`<>6=44i0cb>5<<g8lo6=44}c17g?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb27a>5<4290;w)<97;0;`>N50l1C>;l4i7794?=n9hk1<75`1gf94?=zj:>n6=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e;<i1<7=50;2x 7002;2o7E<7e:J12g=n><0;66g>a`83>>i6nm0;66sm34294?2=83:p(?88:0`2?M4?m2B9:o5f6483>>o?>3:17d<:f;29?j7al3:17pl<5e83>6<729q/>;9529f8L7>b3A8=n6g95;29?l7fi3:17b?id;29?xd4=;0;694?:1y'631=9k;0D?6j;I05f>o1=3:17d69:188m73a2900c<hk:188yg52m3:1?7>50z&122<50m1C>5k4H34a?l022900e<on:188k4`c2900qo=:4;290?6=8r.9::4>b09K6=c<@;<i7d8::188m=0=831b>8h50;9l5cb=831vn>;i:180>5<7s-8=;7<7d:J1<`=O:?h0e;;50;9j5dg=831d=kj50;9~f631290?6=4?{%053?7e92B94h5G27`8m33=831b4;4?::k11c<722e:ji4?::
\7fa736=8391<7>t$344>7>c3A83i6F=6c9j20<722c:ml4?::m2ba<722wi?;?50;194?6|,;<<6?6k;I0;a>N5>k1b:84?::k2ed<722e:ji4?::
\7fa1f`=83>1<7>t$344>4d63A83i6F=6c9j20<722c3:7>5;h06b?6=3f;mh7>5;|`6`5<72=0;6=u+27595g7<@;2n7E<9b:k51?6=3`2=6=44i37e>5<<g8lo6=44}c7g5?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb4f1>5<3290;w)<97;3a5>N50l1C>;l4i7794?=n0?0;66g=5g83>>i6nm0;66sm5e194?2=83:p(?88:0`2?M4?m2B9:o5f6483>>o?>3:17d<:f;29?j7al3:17pl:e383>1<729q/>;951c38L7>b3A8=n6g95;29?l>12900e?;i:188k4`c2900qo;j3;290?6=8r.9::4>b09K6=c<@;<i7d8::188m=0=831b>8h50;9l5cb=831vn8k;:187>5<7s-8=;7?m1:J1<`=O:?h0e;;50;9j<3<722c99k4?::m2ba<722wi9h;50;694?6|,;<<6<l>;I0;a>N5>k1b:84?::k;2?6=3`8>j7>5;n3e`?6=3th>i;4?:583>5}#:?=1=o?4H3:f?M41j2c=97>5;h:5>5<<a;?m6=44o0dg>5<<uk?hm7>54;294~"5>>0:8h5G29g8L70e3-;=>7:4i4d94?=n>k0;66g=0583>>i5<00;66sm5gc94?2=83:p(?88:0`2?M4?m2B9:o5f6483>>o?>3:17d<:f;29?j7al3:17pl:fc83>1<729q/>;951c38L7>b3A8=n6g95;29?l>12900e?;i:188k4`c2900qo;ic;290?6=8r.9::4>b09K6=c<@;<i7d8::188m=0=831b>8h50;9l5cb=831vn8hk:187>5<7s-8=;7?m1:J1<`=O:?h0e;;50;9j<3<722c99k4?::m2ba<722wi9kk50;694?6|,;<<6<l>;I0;a>N5>k1b:84?::k;2?6=3`8>j7>5;n3e`?6=3th=<i4?:583>5}#:?=1=o?4H3:f?M41j2c=97>5;h:5>5<<a;?m6=44o0dg>5<<uk<;i7>54;294~"5>>0:n<5G29g8L70e3`<>6=44i9494?=n:<l1<75`1gf94?=zj?:m6=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e>8:1<7:50;2x 70028h:7E<7e:J12g=n><0;66g76;29?l42n3:17b?id;29?xd1980;694?:1y'631=9k;0D?6j;I05f>o1=3:17d69:188m73a2900c<hk:188yg3a=3:187>50z&122<6<l1C>5k4H34a?!71:3;0e8h50;9j2g<722c9<94?::m10<<722wi95>50;694?6|,;<<6<l>;I0;a>N5>k1b:84?::k;2?6=3`8>j7>5;n3e`?6=3th>4<4?:583>5}#:?=1=o?4H3:f?M41j2c=97>5;h:5>5<<a;?m6=44o0dg>5<<uk?3>7>54;294~"5>>0:n<5G29g8L70e3`<>6=44i9494?=n:<l1<75`1gf94?=zj<286=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e=1>1<7:50;2x 70028h:7E<7e:J12g=n><0;66g76;29?l42n3:17b?id;29?xd21:0;694?:1y'631=9k;0D?6j;I05f>o1=3:17d69:188m73a2900c<hk:188yg3><3:187>50z&122<6j81C>5k4H34a?l022900e5850;9j60`=831d=kj50;9~f0?2290?6=4?{%053?7e92B94h5G27`8m33=831b4;4?::k11c<722e:ji4?::
\7fa1<0=83>1<7>t$344>4d63A83i6F=6c9j20<722c3:7>5;h06b?6=3f;mh7>5;|`6=2<72=0;6=u+27595g7<@;2n7E<9b:k51?6=3`2=6=44i37e>5<<g8lo6=44}c7b2?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb4c4>5<3290;w)<97;3a5>N50l1C>;l4i7794?=n0?0;66g=5g83>>i6nm0;66sm5`:94?2=83:p(?88:0`2?M4?m2B9:o5f6483>>o?>3:17d<:f;29?j7al3:17pl:a883>1<729q/>;951c38L7>b3A8=n6g95;29?l>12900e?;i:188k4`c2900qo;na;290?6=8r.9::4>b09K6=c<@;<i7d8::188m=0=831b>8h50;9l5cb=831vn8l6:187>5<7s-8=;7?m1:J1<`=O:?h0e;;50;9j<3<722c99k4?::m2ba<722wi9oo50;694?6|,;<<6<l>;I0;a>N5>k1b:84?::k;2?6=3`8>j7>5;n3e`?6=3th>no4?:583>5}#:?=1=o?4H3:f?M41j2c=97>5;h:5>5<<a;?m6=44o0dg>5<<uk?io7>54;294~"5>>0:n<5G29g8L70e3`<>6=44i9494?=n:<l1<75`1gf94?=zj<ho6=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e<h31<7:50;2x 70028>h7E<7e:J12g=#9?81=6g:f;29?l0?2900e;l50;9l61?=831vn9o7:187>5<7s-8=;7?;c:J1<`=O:?h0(<8=:09j1c<722c=47>5;h4a>5<<g;>26=44}c6b3?6=<3:1<v*=66820f=O:1o0D?8m;%356?7<a<l1<75f6983>>o1j3:17b<;9;29?xd3i?0;694?:1y'631=9=i0D?6j;I05f>"6>;0:7d;i:188m3>=831b:o4?::m10<<722wi8l;50;694?6|,;<<6<:l;I0;a>N5>k1/=;<51:k6b?6=3`<36=44i7`94?=h:=31<75rb5c7>5<3290;w)<97;37g>N50l1C>;l4$041>4=n=o0;66g98;29?l0e2900c?:6:188yg2f;3:187>50z&122<6<j1C>5k4H34a?!71:3;0e8h50;9j2=<722c=n7>5;n07=?6=3th?m?4?:583>5}#:?=1=9m4H3:f?M41j2.::?4>;h7e>5<<a?21<75f6c83>>i5<00;66sm4`394?2=83:p(?88:06`?M4?m2B9:o5+17095>o2n3:17d87:188m3d=831d>9750;9~f1g7290?6=4?{%053?73k2B94h5G27`8 405281b9k4?::k5<?6=3`<i6=44o36:>5<<uk>n:7>54;294~"5>>0:8n5G29g8L70e3-;=>7?4i4d94?=n>10;66g9b;29?j4313:17pl;e483>1<729q/>;9515a8L7>b3A8=n6*>6382?l3a2900e;650;9j2g<722e9844?::
\7fa0`2=83>1<7>t$344>42d3A83i6F=6c9'534=92c>j7>5;h4;>5<<a?h1<75`25;94?=zj=o86=4;:183
\7f!41?3;?o6F=8d9K63d<,8<96<5f5g83>>o103:17d8m:188k72>2900qo:j2;290?6=8r.9::4>4b9K6=c<@;<i7)?92;38m0`=831b:54?::k5f?6=3f8?57>5;|`7a4<72=0;6=u+275951e<@;2n7E<9b:&227<63`?m6=44i7:94?=n>k0;66a=4883>>{e<l:1<7:50;2x 70028>h7E<7e:J12g=#9?81=6g:f;29?l0?2900e;l50;9l61?=831vn9ji:187>5<7s-8=;7?;c:J1<`=O:?h0(<8=:09j1c<722c=47>5;h4a>5<<g;>26=44}c6ga?6=<3:1<v*=66820f=O:1o0D?8m;%356?7<a<l1<75f6983>>o1j3:17b<;9;29?xd3lm0;694?:1y'631=9=i0D?6j;I05f>"6>;0:7d;i:188m3>=831b:o4?::m10<<722wi8ko50;694?6|,;<<6<:l;I0;a>N5>k1C9n5+17095>o2n3:17d87:188m3d=831d>9750;9~f1`>290?6=4?{%053?73k2B94h5G27`8L0e<,8<96<5f5g83>>o103:17d8m:188k72>2900qo:i8;290?6=8r.9::4>4b9K6=c<@;<i7E;l;%356?7<a<l1<75f6983>>o1j3:17b<;9;29?xd3n>0;694?:1y'631=9=i0D?6j;I05f>N2k2.::?4>;h7e>5<<a?21<75f6c83>>i5<00;66sm4g494?2=83:p(?88:06`?M4?m2B9:o5G5b9'534=92c>j7>5;h4;>5<<a?h1<75`25;94?=zj=l>6=4;:183
\7f!41?3;?o6F=8d9K63d<@<i0(<8=:09j1c<722c=47>5;h4a>5<<g;>26=44}c6e0?6=<3:1<v*=66820f=O:1o0D?8m;I7`?!71:3;0e8h50;9j2=<722c=n7>5;n07=?6=3th?j>4?:583>5}#:?=1=9m4H3:f?M41j2B>o6*>6382?l3a2900e;650;9j2g<722e9844?::
\7fa0c4=83>1<7>t$344>42d3A83i6F=6c9K1f=#9?81=6g:f;29?l0?2900e;l50;9l61?=831vn9h>:187>5<7s-8=;7?;c:J1<`=O:?h0D8m4$041>4=n=o0;66g98;29?l0e2900c?:6:188yg2c:3:187>50z&122<6<j1C>5k4H34a?!71:3;0e8h50;9j2=<722c=n7>5;n07=?6=3th?h<4?:583>5}#:?=1=9m4H3:f?M41j2.::?4>;h7e>5<<a?21<75f6c83>>i5<00;66sm4e294?2=83:p(?88:06`?M4?m2B9:o5+17095>o2n3:17d87:188m3d=831d>9750;9~f1ea290?6=4?{%053?73k2B94h5G27`8 405281b9k4?::k5<?6=3`<i6=44o36:>5<<uk>hi7>54;294~"5>>0:8n5G29g8L70e3-;=>7?4i4d94?=n>10;66g9b;29?j4313:17pl;ce83>1<729q/>;9515a8L7>b3A8=n6*>6382?l3a2900e;650;9j2g<722e9844?::
\7fa0fe=83>1<7>t$344>42d3A83i6F=6c9'534=92c>j7>5;h4;>5<<a?h1<75`25;94?=zj=ii6=4;:183
\7f!41?3;?o6F=8d9K63d<,8<96<5f5g83>>o103:17d8m:188k72>2900qo:la;290?6=8r.9::4>4b9K6=c<@;<i7)?92;38m0`=831b:54?::k5f?6=3f8?57>5;|`7g<<72=0;6=u+275951e<@;2n7E<9b:&227<63`?m6=44i7:94?=n>k0;66a=4883>>{e=8<1<7:50;2x 70028>h7E<7e:J12g=#9?81=6g:f;29?l0?2900e;l50;9l61?=831vn8?::187>5<7s-8=;7?;c:J1<`=O:?h0(<8=:09j1c<722c=47>5;h4a>5<<g;>26=44}c720?6=<3:1<v*=66820f=O:1o0D?8m;%356?7<a<l1<75f6983>>o1j3:17b<;9;29?xd29:0;694?:1y'631=9=i0D?6j;I05f>"6>;0:7d;i:188m3>=831b:o4?::m10<<722wi9<<50;694?6|,;<<6<:l;I0;a>N5>k1/=;<51:k6b?6=3`<36=44i7`94?=h:=31<75rb432>5<3290;w)<97;37g>N50l1C>;l4$041>4=n=o0;66g98;29?l0e2900c?:6:188yg3683:187>50z&122<6<j1C>5k4H34a?!71:3;0e8h50;9j2=<722c=n7>5;n07=?6=3th><k4?:583>5}#:?=1=9m4H3:f?M41j2.::?4>;h7e>5<<a?21<75f6c83>>i5<00;66sm51g94?2=83:p(?88:06`?M4?m2B9:o5+17095>o2n3:17d87:188m3d=831d>9750;9~f06c290?6=4?{%053?73k2B94h5G27`8 405281b9k4?::k5<?6=3`<i6=44o36:>5<<uk?>?7>54;294~"5>>0:8n5G29g8L70e3-;=>7?4i4d94?=n>10;66g9b;29?j4313:17pl:5383>1<729q/>;9515a8L7>b3A8=n6*>6382?l3a2900e;650;9j2g<722e9844?::
\7fa107=83>1<7>t$344>42d3A83i6F=6c9'534=92c>j7>5;h4;>5<<a?h1<75`25;94?=zj<?;6=4;:183
\7f!41?3;?o6F=8d9K63d<,8<96<5f5g83>>o103:17d8m:188k72>2900qo;;f;290?6=8r.9::4>4b9K6=c<@;<i7)?92;38m0`=831b:54?::k5f?6=3f8?57>5;|`60`<72=0;6=u+275951e<@;2n7E<9b:&227<63`?m6=44i7:94?=n>k0;66a=4883>>{e==n1<7:50;2x 70028>h7E<7e:J12g=#9?81=6g:f;29?l0?2900e;l50;9l61?=831vn8:l:187>5<7s-8=;7?;c:J1<`=O:?h0(<8=:09j1c<722c=47>5;h4a>5<<g;>26=44}c77f?6=<3:1<v*=66820f=O:1o0D?8m;%356?7<a<l1<75f6983>>o1j3:17b<;9;29?xd2<h0;694?:1y'631=9=i0D?6j;I05f>"6>;0:7d;i:188m3>=831b:o4?::m10<<722wi9;950;694?6|,;<<6<:l;I0;a>N5>k1C9n5+17095>o2n3:17d87:188m3d=831d>9750;9~f001290?6=4?{%053?73k2B94h5G27`8L0e<,8<96<5f5g83>>o103:17d8m:188k72>2900qo;95;290?6=8r.9::4>4b9K6=c<@;<i7E;l;%356?7<a<l1<75f6983>>o1j3:17b<;9;29?xd2>=0;694?:1y'631=9=i0D?6j;I05f>N2k2.::?4>;h7e>5<<a?21<75f6c83>>i5<00;66sm57194?2=83:p(?88:06`?M4?m2B9:o5G5b9'534=92c>j7>5;h4;>5<<a?h1<75`25;94?=zj<<96=4;:183
\7f!41?3;?o6F=8d9K63d<@<i0(<8=:09j1c<722c=47>5;h4a>5<<g;>26=44}c755?6=<3:1<v*=66820f=O:1o0D?8m;I7`?!71:3;0e8h50;9j2=<722c=n7>5;n07=?6=3th>:=4?:583>5}#:?=1=9m4H3:f?M41j2B>o6*>6382?l3a2900e;650;9j2g<722e9844?::
\7fa10`=83>1<7>t$344>42d3A83i6F=6c9K1f=#9?81=6g:f;29?l0?2900e;l50;9l61?=831vn8;j:187>5<7s-8=;7?;c:J1<`=O:?h0D8m4$041>4=n=o0;66g98;29?l0e2900c?:6:188yg34n3:187>50z&122<6<j1C>5k4H34a?!71:3;0e8h50;9j2=<722c=n7>5;n07=?6=3th>?h4?:583>5}#:?=1=9m4H3:f?M41j2.::?4>;h7e>5<<a?21<75f6c83>>i5<00;66sm52f94?2=83:p(?88:06`?M4?m2B9:o5+17095>o2n3:17d87:188m3d=831d>9750;9~f05d290?6=4?{%053?73k2B94h5G27`8 405281b9k4?::k5<?6=3`<i6=44o36:>5<<uk?8n7>54;294~"5>>0:8n5G29g8L70e3-;=>7?4i4d94?=n>10;66g9b;29?j4313:17pl:3`83>1<729q/>;9515a8L7>b3A8=n6*>6382?l3a2900e;650;9j2g<722e9844?::
\7fa16?=83>1<7>t$344>42d3A83i6F=6c9'534=92c>j7>5;h4;>5<<a?h1<75`25;94?=zj<936=4;:183
\7f!41?3;?o6F=8d9K63d<,8<96<5f5g83>>o103:17d8m:188k72>2900qo;<7;290?6=8r.9::4>4b9K6=c<@;<i7)?92;38m0`=831b:54?::k5f?6=3f8?57>5;|`673<72=0;6=u+275951e<@;2n7E<9b:&227<63`?m6=44i7:94?=n>k0;66a=4883>>{e<??1<7=50;2x 7002;2o7E<7e:J12g=n><0;66g>a`83>>i6nm0;66sm44`94?5=83:p(?88:0cf?M4?m2B9:o5+170973=n9<<1<75f14594?=h9on1<75rb547>5<4290;w)<97;0;`>N50l1C>;l4i7794?=n9hk1<75`1gf94?=zj=?:6=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e<<k1<7=50;2x 70028kn7E<7e:J12g=#9?81?;5f14494?=n9<=1<75`1gf94?=zj=<86=4<:183
\7f!41?383h6F=8d9K63d<a??1<75f1`c94?=h9on1<75rb573>5<3290;w)<97;3a5>N50l1C>;l4i7794?=n0?0;66g=5g83>>i6nm0;66sm44;94?5=83:p(?88:0cf?M4?m2B9:o5+170973=n9<<1<75f14594?=h9on1<75rb541>5<4290;w)<97;0;`>N50l1C>;l4i7794?=n9hk1<75`1gf94?=zj=>m6=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e<<21<7=50;2x 70028kn7E<7e:J12g=#9?81?;5f14494?=n9<=1<75`1gf94?=zj=<:6=4<:183
\7f!41?383h6F=8d9K63d<a??1<75f1`c94?=h9on1<75rb56f>5<3290;w)<97;3a5>N50l1C>;l4i7794?=n0?0;66g=5g83>>i6nm0;66sm44594?5=83:p(?88:0cf?M4?m2B9:o5+170973=n9<<1<75f14594?=h9on1<75rb543>5<4290;w)<97;0;`>N50l1C>;l4i7794?=n9hk1<75`1gf94?=zj=>o6=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e<<<1<7=50;2x 70028kn7E<7e:J12g=#9?81?;5f14494?=n9<=1<75`1gf94?=zj=?m6=4<:183
\7f!41?383h6F=8d9K63d<a??1<75f1`c94?=h9on1<75rb56`>5<3290;w)<97;3a5>N50l1C>;l4i7794?=n0?0;66g=5g83>>i6nm0;66sm44794?5=83:p(?88:0cf?M4?m2B9:o5+170973=n9<<1<75f14594?=h9on1<75rb57f>5<4290;w)<97;0;`>N50l1C>;l4i7794?=n9hk1<75`1gf94?=zj=>i6=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e<<>1<7=50;2x 70028kn7E<7e:J12g=#9?81?;5f14494?=n9<=1<75`1gf94?=zj=?o6=4<:183
\7f!41?383h6F=8d9K63d<a??1<75f1`c94?=h9on1<75rb56b>5<3290;w)<97;3a5>N50l1C>;l4i7794?=n0?0;66g=5g83>>i6nm0;66sm44194?5=83:p(?88:0cf?M4?m2B9:o5+170973=n9<<1<75f14594?=h9on1<75rb57`>5<4290;w)<97;0;`>N50l1C>;l4i7794?=n9hk1<75`1gf94?=zj=>26=4;:183
\7f!41?3;i=6F=8d9K63d<a??1<75f8783>>o5=o0;66a>fe83>>{e<<81<7=50;2x 70028kn7E<7e:J12g=#9?81?;5f14494?=n9<=1<75`1gf94?=zj=296=4<:183
\7f!41?383h6F=8d9K63d<a??1<75f1`c94?=h9on1<75rb55;>5<4290;w)<97;3ba>N50l1C>;l4$041>60<a8?=6=44i074>5<<g8lo6=44}c6;5?6=;3:1<v*=6681<a=O:1o0D?8m;h46>5<<a8kj6=44o0dg>5<<uk>=i7>54;294~"5>>0:n<5G29g8L70e3`<>6=44i9494?=n:<l1<75`1gf94?=zj==<6=4<:183
\7f!41?3;ji6F=8d9K63d<,8<96>84i075>5<<a8?<6=44o0dg>5<<uk>3<7>53;294~"5>>094i5G29g8L70e3`<>6=44i0cb>5<<g8lo6=44}c65`?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb555>5<4290;w)<97;3ba>N50l1C>;l4$041>60<a8?=6=44i074>5<<g8lo6=44}c64b?6=;3:1<v*=6681<a=O:1o0D?8m;h46>5<<a8kj6=44o0dg>5<<uk>=o7>54;294~"5>>0:n<5G29g8L70e3`<>6=44i9494?=n:<l1<75`1gf94?=zj==>6=4<:183
\7f!41?3;ji6F=8d9K63d<,8<96>84i075>5<<a8?<6=44o0dg>5<<uk><i7>53;294~"5>>094i5G29g8L70e3`<>6=44i0cb>5<<g8lo6=44}c65f?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb557>5<4290;w)<97;3ba>N50l1C>;l4$041>60<a8?=6=44i074>5<<g8lo6=44}c64`?6=;3:1<v*=6681<a=O:1o0D?8m;h46>5<<a8kj6=44o0dg>5<<uk>=m7>54;294~"5>>0:n<5G29g8L70e3`<>6=44i9494?=n:<l1<75`1gf94?=zj==86=4<:183
\7f!41?3;ji6F=8d9K63d<,8<96>84i075>5<<a8?<6=44o0dg>5<<uk><o7>53;294~"5>>094i5G29g8L70e3`<>6=44i0cb>5<<g8lo6=44}c65=?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb551>5<4290;w)<97;3ba>N50l1C>;l4$041>60<a8?=6=44i074>5<<g8lo6=44}c64f?6=;3:1<v*=6681<a=O:1o0D?8m;h46>5<<a8kj6=44o0dg>5<<uk>=47>54;294~"5>>0:n<5G29g8L70e3`<>6=44i9494?=n:<l1<75`1gf94?=zj==:6=4<:183
\7f!41?3;ji6F=8d9K63d<,8<96>84i075>5<<a8?<6=44o0dg>5<<uk><m7>53;294~"5>>094i5G29g8L70e3`<>6=44i0cb>5<<g8lo6=44}c653?6=<3:1<v*=6682f4=O:1o0D?8m;h46>5<<a1<1<75f24d94?=h9on1<75rb553>5<4290;w)<97;3ba>N50l1C>;l4$041>60<a8?=6=44i074>5<<g8lo6=44}c64=?6=;3:1<v*=6681<a=O:1o0D?8m;h46>5<<a8kj6=44o0dg>5<<uk>=:7>54;294~"5>>0:n<5G29g8L70e3`<>6=44i9494?=n:<l1<75`1gf94?=zj=<m6=4<:183
\7f!41?3;ji6F=8d9K63d<,8<96>84i075>5<<a8?<6=44o0dg>5<<uk?<m7>54;294~"5>>0:8n5G29g8L70e3-;=>7?4i4d94?=n>10;66g9b;29?j4313:17pl:7883>1<729q/>;9515a8L7>b3A8=n6*>6382?l3a2900e;650;9j2g<722e9844?::
\7fa12>=83>1<7>t$344>42d3A83i6F=6c9'534=92c>j7>5;h4;>5<<a?h1<75`25;94?=zj<=<6=4;:183
\7f!41?3;?o6F=8d9K63d<,8<96<5f5g83>>o103:17d8m:188k72>2900qo;86;290?6=8r.9::4>4b9K6=c<@;<i7)?92;38m0`=831b:54?::k5f?6=3f8?57>5;|`630<72=0;6=u+275951e<@;2n7E<9b:&227<63`?m6=44i7:94?=n>k0;66a=4883>>{e=>>1<7:50;2x 70028>h7E<7e:J12g=#9?81=6g:f;29?l0?2900e;l50;9l61?=831vn89<:187>5<7s-8=;7?;c:J1<`=O:?h0(<8=:09j1c<722c=47>5;h4a>5<<g;>26=44}c746?6=<3:1<v*=66820f=O:1o0D?8m;%356?7<a<l1<75f6983>>o1j3:17b<;9;29?xd2?80;694?:1y'631=9=i0D?6j;I05f>"6>;0:7d;i:188m3>=831b:o4?::m10<<722wi:?o50;694?6|,;<<6<:l;I0;a>N5>k1/=;<51:k6b?6=3`<36=44i7`94?=h:=31<75rb70:>5<3290;w)<97;37g>N50l1C>;l4$041>4=n=o0;66g98;29?l0e2900c?:6:188yg0503:187>50z&122<6<j1C>5k4H34a?!71:3;0e8h50;9j2=<722c=n7>5;n07=?6=3th=>:4?:583>5}#:?=1=9m4H3:f?M41j2.::?4>;h7e>5<<a?21<75f6c83>>i5<00;66sm63494?2=83:p(?88:06`?M4?m2B9:o5+17095>o2n3:17d87:188m3d=831d>9750;9~f342290?6=4?{%053?73k2B94h5G27`8 405281b9k4?::k5<?6=3`<i6=44o36:>5<<uk<987>54;294~"5>>0:8n5G29g8L70e3-;=>7?4i4d94?=n>10;66g9b;29?j4313:17pl92283>1<729q/>;9515a8L7>b3A8=n6*>6382?l3a2900e;650;9j2g<722e9844?::
\7fa274=83>1<7>t$344>42d3A83i6F=6c9'534=92c>j7>5;h4;>5<<a?h1<75`25;94?=zj?8:6=4;:183
\7f!41?3;?o6F=8d9K63d<,8<96<5f5g83>>o103:17d8m:188k72>2900qo;l7;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;l6;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;l5;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;l4;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;l3;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;n1;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;n0;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;6f;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;6e;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;6d;297?6=8r.9::4>ad9K6=c<@;<i7)?92;68m4312900e<;8:188k4`c2900qo;m4;291?6=8r.9::4>b19K6=c<@;<i7)?92;14?l72>3:17d?:7;29?l7203:17d?:9;29?j7al3:17pl:b283>0<729q/>;951c28L7>b3A8=n6*>63803>o6=?0;66g>5683>>o6=10;66g>5883>>i6nm0;66sm5c094?3=83:p(?88:0`3?M4?m2B9:o5+170972=n9<<1<75f14594?=n9<21<75f14;94?=h9on1<75rb4`2>5<2290;w)<97;3a4>N50l1C>;l4$041>61<a8?=6=44i074>5<<a8?36=44i07:>5<<g8lo6=44}c7a4?6==3:1<v*=6682f5=O:1o0D?8m;%356?503`;>:7>5;h363?6=3`;>47>5;h36=?6=3f;mh7>5;|`6<`<72<0;6=u+27595g6<@;2n7E<9b:&227<4?2c:9;4?::k212<722c:954?::k21<<722e:ji4?::
\7fa1=b=83?1<7>t$344>4d73A83i6F=6c9'534=;>1b=8850;9j501=831b=8650;9j50?=831d=kj50;9~f0>d290>6=4?{%053?7e82B94h5G27`8 4052:=0e<;9:188m4302900e<;7:188m43>2900c<hk:188yg3?j3:197>50z&122<6j91C>5k4H34a?!71:39<7d?:6;29?l72?3:17d?:8;29?l7213:17b?id;29?xd20h0;684?:1y'631=9k:0D?6j;I05f>"6>;08;6g>5783>>o6=>0;66g>5983>>o6=00;66a>fe83>>{e=821<7=50;2x 70028kn7E<7e:J12g=#9?81?>5f14494?=n9<=1<75`1gf94?=zj=ki6=4<:183
\7f!41?3;ji6F=8d9K63d<,8<96>=4i075>5<<a8?<6=44o0dg>5<<uk?;o7>53;294~"5>>0:mh5G29g8L70e3-;=>7=<;h362?6=3`;>;7>5;n3e`?6=3th><o4?:283>5}#:?=1=lk4H3:f?M41j2.::?4<3:k213<722c:9:4?::m2ba<722wi9=o50;194?6|,;<<6<oj;I0;a>N5>k1/=;<5329j500=831b=8950;9l5cb=831vn8>6:180>5<7s-8=;7?ne:J1<`=O:?h0(<8=:218m4312900e<;8:188k4`c2900qo;?8;297?6=8r.9::4>ad9K6=c<@;<i7)?92;10?l72>3:17d?:7;29?j7al3:17pl:0683>6<729q/>;951`g8L7>b3A8=n6*>63807>o6=?0;66g>5683>>i6nm0;66sm51494?5=83:p(?88:0cf?M4?m2B9:o5+170976=n9<<1<75f14594?=h9on1<75rb426>5<4290;w)<97;3ba>N50l1C>;l4$041>65<a8?=6=44i074>5<<g8lo6=44}c730?6=;3:1<v*=6682e`=O:1o0D?8m;%356?543`;>:7>5;h363?6=3f;mh7>5;|`7=c<72:0;6=u+27595dc<@;2n7E<9b:&227<4;2c:9;4?::k212<722e:ji4?::
\7fa0<c=8391<7>t$344>4gb3A83i6F=6c9'534=;:1b=8850;9j501=831d=kj50;9~f1?c29086=4?{%053?7fm2B94h5G27`8 4052:90e<;9:188m4302900c<hk:188yg2>k3:1?7>50z&122<6il1C>5k4H34a?!71:3987d?:6;29?l72?3:17b?id;29?xd31k0;6>4?:1y'631=9ho0D?6j;I05f>"6>;08?6g>5783>>o6=>0;66a>fe83>>{e<0k1<7=50;2x 70028kn7E<7e:J12g=#9?81?>5f14494?=n9<=1<75`1gf94?=zj=326=4<:183
\7f!41?3;ji6F=8d9K63d<,8<96>=4i075>5<<a8?<6=44o0dg>5<<uk>247>53;294~"5>>0:mh5G29g8L70e3-;=>7=<;h362?6=3`;>;7>5;n3e`?6=3th?5:4?:283>5}#:?=1=lk4H3:f?M41j2.::?4<3:k213<722c:9:4?::m2ba<722wi9<o50;694?6|,;<<6<oi;I0;a>N5>k1/=;<5399j500=831b=8950;9j50>=831d=kj50;9~f1gc290?6=4?{%053?7fn2B94h5G27`8 4052:20e<;9:188m4302900e<;7:188k4`c2900qo;>c;291?6=8r.9::4>b19K6=c<@;<i7)?92;16?l72>3:17d?:7;29?l7203:17d?:9;29?j7al3:17pl;ag83>0<729q/>;951c28L7>b3A8=n6*>63801>o6=?0;66g>5683>>o6=10;66g>5883>>i6nm0;66sm50g94?5=83:p(?88:0cf?M4?m2B9:o5+170976=n9<<1<75f14594?=h9on1<75rb5`2>5<4290;w)<97;3ba>N50l1C>;l4$041>65<a8?=6=44i074>5<<g8lo6=44}c714?6=<3:1<v*=6682ec=O:1o0D?8m;%356?5?3`;>:7>5;h363?6=3`;>47>5;n3e`?6=3th?n>4?:583>5}#:?=1=lh4H3:f?M41j2.::?4<8:k213<722c:9:4?::k21=<722e:ji4?::
\7fa174=83?1<7>t$344>4d73A83i6F=6c9'534=;<1b=8850;9j501=831b=8650;9j50?=831d=kj50;9~f1d2290>6=4?{%053?7e82B94h5G27`8 4052:?0e<;9:188m4302900e<;7:188m43>2900c<hk:188yg0583:1?7>50z&122<6il1C>5k4H34a?!71:38i7d?:6;29?l72?3:17b?id;29?xd19k0;684?:1y'631=9k:0D?6j;I05f>"6>;08;6g>5783>>o6=>0;66g>5983>>o6=00;66a>fe83>>{e>921<7;50;2x 70028h;7E<7e:J12g=#9?81?:5f14494?=n9<=1<75f14:94?=n9<31<75`1gf94?=zj<l;6=4::183
\7f!41?3;i<6F=8d9K63d<,8<96>94i075>5<<a8?<6=44i07;>5<<a8?26=44o0dg>5<<uk?oh7>55;294~"5>>0:n=5G29g8L70e3-;=>7=8;h362?6=3`;>;7>5;h36<?6=3`;>57>5;n3e`?6=3th==l4?:483>5}#:?=1=o>4H3:f?M41j2.::?4<7:k213<722c:9:4?::k21=<722c:944?::m2ba<722wi:=950;794?6|,;<<6<l?;I0;a>N5>k1/=;<5369j500=831b=8950;9j50>=831b=8750;9l5cb=831vn8ki:186>5<7s-8=;7?m0:J1<`=O:?h0(<8=:258m4312900e<;8:188m43?2900e<;6:188k4`c2900qo;kc;291?6=8r.9::4>b19K6=c<@;<i7)?92;14?l72>3:17d?:7;29?l7203:17d?:9;29?j7al3:17pl91883>0<729q/>;951c28L7>b3A8=n6*>63803>o6=?0;66g>5683>>o6=10;66g>5883>>i6nm0;66sm61494?3=83:p(?88:0`3?M4?m2B9:o5+170972=n9<<1<75f14594?=n9<21<75f14;94?=h9on1<75rb4gf>5<2290;w)<97;3a4>N50l1C>;l4$041>61<a8?=6=44i074>5<<a8?36=44i07:>5<<g8lo6=44}c7gf?6==3:1<v*=6682f5=O:1o0D?8m;%356?503`;>:7>5;h363?6=3`;>47>5;h36=?6=3f;mh7>5;|`55=<72<0;6=u+27595g6<@;2n7E<9b:&227<4?2c:9;4?::k212<722c:954?::k21<<722e:ji4?::
\7fa253=83?1<7>t$344>4d73A83i6F=6c9'534=;>1b=8850;9j501=831b=8650;9j50?=831d=kj50;9~f0cc290>6=4?{%053?7e82B94h5G27`8 4052:=0e<;9:188m4302900e<;7:188m43>2900c<hk:188yg3ci3:197>50z&122<6j91C>5k4H34a?!71:39<7d?:6;29?l72?3:17d?:8;29?l7213:17b?id;29?xd2?k0;6>4?:1y'631=9ho0D?6j;I05f>"6>;09n6g>5783>>o6=>0;66a>fe83>>{e>8=1<7;50;2x 70028h;7E<7e:J12g=#9?81?:5f14494?=n9<=1<75f14:94?=n9<31<75`1gf94?=zj?:?6=4::183
\7f!41?3;i<6F=8d9K63d<,8<96>94i075>5<<a8?<6=44i07;>5<<a8?26=44o0dg>5<<uk?no7>55;294~"5>>0:n=5G29g8L70e3-;=>7=8;h362?6=3`;>;7>5;h36<?6=3`;>57>5;n3e`?6=3th>h44?:483>5}#:?=1=o>4H3:f?M41j2.::?4<7:k213<722c:9:4?::k21=<722c:944?::m2ba<722wi8=750;094?6|,;<<6<ok;I0;a>N5>k1/=;<5279j500=831d=kj50;9~f16e29096=4?{%053?7fl2B94h5G27`8 4052;<0e<;9:188k4`c2900qo:?d;296?6=8r.9::4>ae9K6=c<@;<i7)?92;05?l72>3:17b?id;29?xd38o0;6?4?:1y'631=9hn0D?6j;I05f>"6>;09:6g>5783>>i6nm0;66sm40394?4=83:p(?88:0cg?M4?m2B9:o5+170963=n9<<1<75`1gf94?=zj=;86=4=:183
\7f!41?3;jh6F=8d9K63d<,8<96?84i075>5<<g8lo6=44}c621?6=:3:1<v*=6682ea=O:1o0D?8m;%356?413`;>:7>5;n3e`?6=3th?=:4?:383>5}#:?=1=lj4H3:f?M41j2.::?4=6:k213<722e:ji4?::
\7fa7a?=8381<7>t$344>4gc3A83i6F=6c9'534=:?1b=8850;9l5cb=831vn>jm:181>5<7s-8=;7?nd:J1<`=O:?h0(<8=:348m4312900c<hk:188yg5cl3:1>7>50z&122<6im1C>5k4H34a?!71:38=7d?:6;29?j7al3:17pl<dg83>7<729q/>;951`f8L7>b3A8=n6*>63812>o6=?0;66a>fe83>>{e;l;1<7<50;2x 70028ko7E<7e:J12g=#9?81>;5f14494?=h9on1<75rb2g0>5<5290;w)<97;3b`>N50l1C>;l4$041>70<a8?=6=44o0dg>5<<uk9n97>52;294~"5>>0:mi5G29g8L70e3-;=>7<9;h362?6=3f;mh7>5;|`0a2<72;0;6=u+27595db<@;2n7E<9b:&227<5>2c:9;4?::m2ba<722wi?:750;094?6|,;<<6<ok;I0;a>N5>k1/=;<5279j500=831d=kj50;9~f61e29096=4?{%053?7fl2B94h5G27`8 4052;<0e<;9:188k4`c2900qo=8d;296?6=8r.9::4>ae9K6=c<@;<i7)?92;05?l72>3:17b?id;29?xd4?o0;6?4?:1y'631=9hn0D?6j;I05f>"6>;09:6g>5783>>i6nm0;66sm39394?4=83:p(?88:0cg?M4?m2B9:o5+170963=n9<<1<75`1gf94?=zj:286=4=:183
\7f!41?3;jh6F=8d9K63d<,8<96?84i075>5<<g8lo6=44}c1;1?6=:3:1<v*=6682ea=O:1o0D?8m;%356?413`;>:7>5;n3e`?6=3th84:4?:383>5}#:?=1=lj4H3:f?M41j2.::?4=6:k213<722e:ji4?::
\7fa7d?=8381<7>t$344>4gc3A83i6F=6c9'534=:?1b=8850;9l5cb=831vn>om:181>5<7s-8=;7?nd:J1<`=O:?h0(<8=:348m4312900c<hk:188yg5fl3:1>7>50z&122<6im1C>5k4H34a?!71:38=7d?:6;29?j7al3:17pl<ag83>7<729q/>;951`f8L7>b3A8=n6*>63812>o6=?0;66a>fe83>>{e;k;1<7<50;2x 70028ko7E<7e:J12g=#9?81>;5f14494?=h9on1<75rb2`0>5<5290;w)<97;3b`>N50l1C>;l4$041>70<a8?=6=44o0dg>5<<uk9i97>52;294~"5>>0:mi5G29g8L70e3-;=>7<9;h362?6=3f;mh7>5;|`0f2<72;0;6=u+27595db<@;2n7E<9b:&227<5>2c:9;4?::m2ba<722wi?9750;094?6|,;<<6<ok;I0;a>N5>k1/=;<5279j500=831d=kj50;9~f62e29096=4?{%053?7fl2B94h5G27`8 4052;<0e<;9:188k4`c2900qo=;d;296?6=8r.9::4>ae9K6=c<@;<i7)?92;05?l72>3:17b?id;29?xd4<o0;6?4?:1y'631=9hn0D?6j;I05f>"6>;09:6g>5783>>i6nm0;66sm34394?4=83:p(?88:0cg?M4?m2B9:o5+170963=n9<<1<75`1gf94?=zj:?86=4=:183
\7f!41?3;jh6F=8d9K63d<,8<96?84i075>5<<g8lo6=44}c161?6=:3:1<v*=6682ea=O:1o0D?8m;%356?413`;>:7>5;n3e`?6=3th89:4?:383>5}#:?=1=lj4H3:f?M41j2.::?4=6:k213<722e:ji4?::
\7fa074=8381<7>t$344>4gc3A83i6F=6c9'534=:?1b=8850;9l5cb=831vn>h=:181>5<7s-8=;7?nd:J1<`=O:?h0(<8=:348m4312900c<hk:188yg5>:3:1>7>50z&122<6im1C>5k4H34a?!71:38=7d?:6;29?j7al3:17pl<c383>7<729q/>;951`f8L7>b3A8=n6*>63812>o6=?0;66a>fe83>>{e;?81<7<50;2x 70028ko7E<7e:J12g=#9?81>;5f14494?=h9on1<75rb711>5<3290;w)<97;3bb>N50l1C>;l4$041>42f3`;>:7>5;h363?6=3`;>47>5;n3e`?6=3th?n:4?:283>5}#:?=1=lk4H3:f?M41j2.::?4<3:k213<722c:9:4?::m2ba<722wi8oo50;794?6|,;<<6<l?;I0;a>N5>k1/=;<5349j500=831b=8950;9j50>=831b=8750;9l5cb=831vn9l7:187>5<7s-8=;7?nf:J1<`=O:?h0(<8=:268m4312900e<;8:188m43?2900c<hk:188yg2ek3:197>50z&122<6j91C>5k4H34a?!71:3927d?:6;29?l72?3:17d?:8;29?l7213:17b?id;29?xd3j00;684?:1y'631=9k:0D?6j;I05f>"6>;0896g>5783>>o6=>0;66g>5983>>o6=00;66a>fe83>>{e<ko1<7;50;2x 70028h;7E<7e:J12g=#9?81?85f14494?=n9<=1<75f14:94?=n9<31<75`1gf94?=zj<8?6=4<:183
\7f!41?3;ji6F=8d9K63d<,8<96>=4i075>5<<a8?<6=44o0dg>5<<uk?9;7>55;294~"5>>0:n=5G29g8L70e3-;=>7=:;h362?6=3`;>;7>5;h36<?6=3`;>57>5;n3e`?6=3th>>84?:583>5}#:?=1=lh4H3:f?M41j2.::?4<4:k213<722c:9:4?::k21=<722e:ji4?::
\7fa17?=83?1<7>t$344>4d73A83i6F=6c9'534=;01b=8850;9j501=831b=8650;9j50?=831d=kj50;9~f041290>6=4?{%053?7e82B94h5G27`8 4052:?0e<;9:188m4302900e<;7:188m43>2900c<hk:188yg35j3:197>50z&122<6j91C>5k4H34a?!71:39>7d?:6;29?l72?3:17d?:8;29?l7213:17b?id;29?xd2n=0;684?:1y'631=9k:0D?6j;I05f>"6>;0:9=5f14494?=n9<=1<75f14:94?=n9<31<75`1gf94?=zj<i26=4::183
\7f!41?3;i<6F=8d9K63d<,8<96<;?;h362?6=3`;>;7>5;h36<?6=3`;>57>5;n3e`?6=3th?=54?:383>5}#:?=1=l84H3:f?M41j2c:984?::m2ba<722wi?h650;094?6|,;<<6<o9;I0;a>N5>k1b=8;50;9l5cb=831vn>67:181>5<7s-8=;7?n6:J1<`=O:?h0e<;::188k4`c2900qo=m8;296?6=8r.9::4>a79K6=c<@;<i7d?:5;29?j7al3:17pl<5983>7<729q/>;951`48L7>b3A8=n6g>5483>>i6nm0;66sm62294?e5290;w)<97;07e>N50l1C>;l4Z4g9g~472;;1>:4=8;0`>7b=:l09j7<6:3c975<493w/=;o53:&22g<43-;=o7=4$04g>6=#9?o1?6*>6g80?!708390(<9>:29'524=;2.:;>4<;%340?5<,8=>6>5+16497>"6?>087)?88;18 41>2:1/=:o53:&23g<43-;<o7=4$05g>6=#9>o1?6*>7g80?!7?8390(<6>:29'5=4=;2.:4>4<;%3;0?5<,82>6>5+19497>"60>087)?78;18 4>>2:1/=5o53:&2<g<43-;3o7=4$0:g>6=#91o1?6*>8g80?!7>8390(<7>:29'5<4=;2.:5>4<;%3:0?5<,83>6>5+18497>"61>087)?68;18 4?>2:1/=4o53:&2=g<43-;2o7=4$0;g>6=#90o1?6*>9g80?!7f8390(<o>:29'5d4=;2.:m84>fb9'5d5=:2.:m94=;%36e?5<,8?i6>5+14a97>"6=m087)?:e;18 43a2:1/=l9515`8 4g?28>i7)<;b;3eg>"5<j0:jn5a24c957=i:<h1=?5+27395ce<,8<;6>5+17397>"5?h09;45+26`962?<f;=h6<<4n35g>44<f8:<6=5a13;94>"5>90:8o5+27196>"6>:087)?94;18 4022:1/=;853:&222<43-;=47=4$04:>6=#:?>1>6g90;29?l062900e;850;9j22<722c:854?::k11f<722c99i4?::k20<<722c9:84?::k123<722e=>7>5;n40>5<<a=:1<7*=0280b>h58;0;76g<e;29 7642:l0b?>=:098m6b=83.9<>4<f:l147<532c8o7>5$320>6`<f;:96>54i2`94?"58:08j6`=0387?>o313:1(?><:2d8j7652<10e9650;&146<4n2d9<?49;:k73?6=,;:86>h4n321>2=<a=<1<7*=0280b>h58;0376g;5;29 7642:l0b?>=:898m12=83.9<>4<f:l147<f32c??7>5$320>6`<f;:96o54i5094?"58:08j6`=038`?>o393:1(?><:2d8j7652m10e>o50;&146<4n2d9<?4j;:k64?6=,;:869h4n321>5=<a=o1<7*=0287b>h58;0:76g;d;29 7642=l0b?>=:398m1e=83.9<>4;f:l147<432c?n7>5$320>1`<f;:96954i4;94?"58:0?j6`=0386?>o203:1(?><:5d8j7652?10e8950;&146<3n2d9<?48;:k62?6=,;:869h4n321>==<a<?1<7*=0287b>h58;0276g:4;29 7642=l0b?>=:`98m05=83.9<>4;f:l147<e32c>>7>5$320>1`<f;:96n54i4394?"58:0?j6`=038g?>o3i3:1(?><:5d8j7652l10el>50;&146<>n2d9<?4?;:k:a?6=,;:864h4n321>4=<a0i1<7*=028:b>h58;0976g6b;29 76420l0b?>=:298m<g=83.9<>46f:l147<332c257>5$320><`<f;:96854i8:94?"58:02j6`=0385?>o>?3:1(?><:8d8j7652>10e4850;&146<>n2d9<?47;:k:1?6=,;:864h4n321><=<a0>1<7*=028:b>h58;0j76g63;29 76420l0b?>=:c98m<7=83.9<>46f:l147<d32c2<7>5$320><`<f;:96i54i9d94?"58:02j6`=038f?>o?m3:1(?><:8d8j7652o10e5j50;&146<>n2d9<?4>0:9j<f<72-8;?77i;o036?7632c3n7>5$320><`<f;:96<<4;h:b>5<#:9915k5a210956=<a131<7*=028:b>h58;0:865f8983>!47;33m7c<?2;36?>of?3:1(?><:8d8j76528<07do9:18'655=1o1e>=<51698md3=83.9<>46f:l147<6021bm94?:%037??a3g8;>7?6;:kb7?6=,;:864h4n321>4g<3`k96=4+2119=c=i:981=o54i`394?"58:02j6`=0382g>=n1m0;6)<?3;;e?k47:3;o76g62;29 76420l0b?>=:0g8?l>0290/>==59g9m654=9o10en?50;&146<d82d9<?4?;:kab?6=,;:86n>4n321>4=<akn1<7*=028`4>h58;0976gmc;29 7642j:0b?>=:298mgd=83.9<>4l0:l147<332cim7>5$320>f6<f;:96854ic;94?"58:0h<6`=0385?>oe03:1(?><:b28j7652>10eo950;&146<d82d9<?47;:ka2?6=,;:86n>4n321><=<ak?1<7*=028`4>h58;0j76gm4;29 7642j:0b?>=:c98mg4=83.9<>4l0:l147<d32ci=7>5$320>f6<f;:96i54ic294?"58:0h<6`=038f?>ofn3:1(?><:b28j7652o10elk50;&146<d82d9<?4>0:9jea<72-8;?7m?;o036?7632cjo7>5$320>f6<f;:96<<4;hca>5<#:991o=5a210956=<ahk1<7*=028`4>h58;0:865fa883>!47;3i;7c<?2;36?>od03:1(?><:b28j76528<07dm8:18'655=k91e>=<51698mf0=83.9<>4l0:l147<6021bo84?:%037?e73g8;>7?6;:k`0?6=,;:86n>4n321>4g<3`i86=4+2119g5=i:981=o54ib094?"58:0h<6`=0382g>=njl0;6)<?3;a3?k47:3;o76gm3;29 7642j:0b?>=:0g8?lg?290/>==5c19m654=9o10eh>50;&146<cn2d9<?4?;:kga?6=,;:86ih4n321>4=<amn1<7*=028gb>h58;0976gkc;29 7642ml0b?>=:298m`3=83.9<>4j4:l147<732cn?7>5$320>`2<f;:96<54id094?"58:0n86`=0381?>ob93:1(?><:d68j7652:10e?9<:18'655=:>80b?>=:198m716290/>==52608j7652810e?9?:18'655=:>80b?>=:398m70a290/>==52608j7652:10e?97:18'655=:>=0b?>=:198m711290/>==52658j7652810e?9::18'655=:>=0b?>=:398m713290/>==52658j7652:10ckh50;&146<am2d9<?4?;:me`?6=,;:86kk4n321>4=<goh1<7*=028ea>h58;0976aia;29 7642oo0b?>=:298kc?=83.9<>4ie:l147<332em47>5$320>cc<f;:96854og594?"58:0mi6`=0385?>ia>3:1(?><:gg8j7652>10ck;50;&146<am2d9<?47;:me0?6=,;:86kk4n321><=<go91<7*=028ea>h58;0j76ai2;29 7642oo0b?>=:c98kc6=83.9<>4ie:l147<d32enj7>5$320>cc<f;:96i54odg94?"58:0mi6`=038f?>ibl3:1(?><:gg8j7652o10chm50;&146<am2d9<?4>0:9lag<72-8;?7hj;o036?7632enm7>5$320>cc<f;:96<<4;ng:>5<#:991jh5a210956=<gl21<7*=028ea>h58;0:865`e683>!47;3ln7c<?2;36?>i68?0;6)<?3;df?k47:3;=76a>0483>!47;3ln7c<?2;34?>i68=0;6)<?3;df?k47:3;376a>0283>!47;3ln7c<?2;3:?>i68;0;6)<?3;df?k47:3;j76a>0083>!47;3ln7c<?2;3a?>i6890;6)<?3;df?k47:3;h76aic;29 7642oo0b?>=:0f8?j`6290/>==5fd9m654=9l10ch850;&146<am2d9<?4>f:9l577=83.9<>4>219m654=821d=<h50;&146<6:91e>=<51:9l54b=83.9<>4>219m654=:21d=<m50;&146<6:91e>=<53:9l54d=83.9<>4>219m654=<21d=<o50;&146<6:91e>=<55:9l54?=83.9<>4>219m654=>21d=<650;&146<6:91e>=<57:9l541=83.9<>4>219m654=021d=<850;&146<6:91e>=<59:9l543=83.9<>4>219m654=i21d=<:50;&146<6:91e>=<5b:9l544=83.9<>4>219m654=k21d=<?50;&146<6:91e>=<5d:9l546=83.9<>4>219m654=m21d==h50;&146<6:91e>=<5f:9l55c=83.9<>4>219m654=9910c<>k:18'655=9;:0b?>=:038?j77k3:1(?><:003?k47:3;976a>0c83>!47;3;9<6`=03827>=h99k1<7*=028265=i:981=954o02:>5<#:991=?>4n321>43<3f;947>5$320>4473g8;>7?9;:m262<72-8;?7?=0:l147<6?21d=?850;&146<6:91e>=<51998k442290/>==51328j76528307b?=4;29 764288;7c<?2;3b?>i6::0;6)<?3;314>h58;0:n65`13094?"58:0:>=5a21095f=<g8;n6=4+2119576<f;:96<j4;n327?6=,;:86<<?;o036?7b32e:<54?:%037?7582d9<?4>f:9l57c=83.9<>4>2e9m654=821d=?m50;&146<6:m1e>=<51:9l57d=83.9<>4>2e9m654=:21d=?o50;&146<6:m1e>=<53:9l565=83.9<>4>339m654=821d=>?50;&146<6;;1e>=<51:9l566=83.9<>4>339m654=:21d=?h50;&146<6;;1e>=<53:9~w3c=83;=wS8j;<1:a?033492h78;;<1b5?033492j78;;<1b4?03349j878;;<1b6?03349j?78;;<1b1?03349j:78;;<15`?03349=i78;;<15b?03349<<78;;<145?03349<>78;;<147?03349<878;;<141?03349<:78;;<74f?7al2wx=8?50;7xZ3b<V8?:70;i5;07=>;1:90:9;525g69501<uz8>57>54z\11<=:=>h1=894=711>43134?h57?:6:
\7fp671=83k3wS;m;_04a>X5>01U9l5Q1gd8Z70d3W8;96P=269>6=`=9<901;<i:7`8934c2?h019>8:778916?21<019>n:948916d21<019>j:948917721<019?=:948917321<019?9:94896b02??01>j7:94896bf21<01>jl:94896bb21<01>k?:94896c521<01>k;:94896c121<01>98:778961?21<01>9n:948961d21<01>9j:94896>721<01>6=:94896>321<01>69:94896g02??01>o7:94896gf21<01>ol:94896gb21<01>l?:94896d521<01>l;:94896d121<01>:8:778962?21<01>:n:948962d21<01>:j:948963721<01>;=:948963321<01>;9:94890ea21<018j?:94890b621<018j=:94890b421<018k=:94890c421<018k;:94890c221<018k9:94890`f21<018hm:94890`d21<018hk:94890`b21<01;>k:948936b21<01;>i:948937721<01;?>:94890>721<0186>:94890>521<0186<:94890>321<0187<:94890?321<0187::94890?121<01878:94890g121<018o8:94890g?21<018o6:94890gf21<018l6:94890df21<018lm:94890dd21<018lk:94893572?:01;=?:73893572;?h708<0;06`>;1;90?<63931877>;1;90?>63931875>;1;908m63931864>;1;90>?63931866>;1;90>=6393187e>;1;90j<639318:a>;1;902o639318:f>;1;902m639318:=>;1;9024639318:3>;1;902:639318:1>;1;9028639318:7>;1;902=639318:4>;1;903j639318;a>;1;90h=639318ab>;1;90ih639318ag>;1;90in639318ae>;1;90i5639318a<>;1;90i;639318a2>;1;90i9639318a0>;1;90i>639318a5>;1;90i<639318bb>;1;90ji639318b`>;1;90jo639318bf>;1;90jm639318b=>;1;90h4639318`3>;1;90h:639318`1>;1;90h8639318`7>;1;90h>639318aa>;1;90i?639318b<>;1;90n<639318ga>;1;90n9639318f7>;1;90n>639318f5>;1;909;5526229620<5?9;6?9:;<404?40<2wx>8k50;7xZ73b34<9o7<?4:?56c<58=16:?k52168934c2;:?7p}>4683>3}Y>j1U=994=4ab>72>34?<n7?:6:?577<6=>169n751458yv0a29098vP9f:?76`<1<27?>i494:?774<1<27?>k494:?775<1<27??9494:?777<1<27??>494:?770<1<27??;494:?0b`<1<278ji494:?744<1<278jk494:?745<1<27?<9494:?747<1<27?<>494:?740<1<27?<;494:?0ga<1<278oh494:?0gc<1<278h=494:?0`4<1<278h?494:?0`6<1<278h9494:?0`0<1<278h;494:?565<6nm16:>>5261893572;=:708<0;044>;1;909:k5rs3:a>5<4sW83n639218212=:=o>1=884}r07`?6=<kqU>9j4=70`>0`<5?8o68h4=2;f>0`<5:3o68h4=2c2>0`<5:3m68h4=2c3>0`<5:k?68h4=2c1>0`<5:k868h4=2c6>0`<5:k=68h4=24g>0`<5:<n68h4=24e>0`<5:=;68h4=252>0`<5:=968h4=250>0`<5:=?68h4=256>0`<5:==68h4=4ab>0`<5=n968h4=5f2>0`<5=n;68h4=5ae>0`<5=in68h4=5ag>0`<5=ih68h4=5aa>0`<5=ij68h4=5a:>0`<5<;=68h4=436>0`<5<;?68h4=430>0`<5<;968h4=432>0`<5<;;68h4=42e>0`<5<:n68h4=42g>0`<5<?868h4=471>0`<5<?:68h4=473>0`<5<>m68h4=46f>0`<5<>o68h4=46`>0`<5<>i68h4=46b>0`<5<<<68h4=445>0`<5<<>68h4=447>0`<5<<868h4=441>0`<5<<:68h4=443>0`<5<?m68h4=47f>0`<5<=j68h4=45:>0`<5<=368h4=454>0`<5<==68h4=456>0`<5<=?68h4=450>0`<5<=968h4=452>0`<5?9;6;94}r04b?6==<qU>:h4=70e>0`<5?8n68h4=50f>0`<5=8o68h4=512>0`<5=8m68h4=513>0`<5=9?68h4=511>0`<5=9868h4=516>0`<5=9=68h4=2df>0`<5:lo68h4=522>0`<5:lm68h4=523>0`<5=:?68h4=521>0`<5=:868h4=526>0`<5=:=68h4=2ag>0`<5:in68h4=2ae>0`<5:n;68h4=2f2>0`<5:n968h4=2f0>0`<5:n?68h4=2f6>0`<5:n=68h4=4d6>0`<5=k268h4=5c;>0`<5=k<68h4=5c5>0`<5=k>68h4=5c7>0`<5=k868h4=5c1>0`<5=k:68h4=5c3>0`<5=o=68h4=5g6>0`<5=o?68h4=5g0>0`<5=o968h4=5g2>0`<5=o;68h4=5fe>0`<5=nn68h4=5fg>0`<5=lj68h4=5d:>0`<5=l368h4=5d4>0`<5=l=68h4=5d6>0`<5=l?68h4=5d0>0`<5=l968h4=5d2>0`<5<9m68h4=41f>0`<5<9o68h4=41`>0`<5<9i68h4=41b>0`<5<9268h4=41;>0`<5<9<68h4=415>0`<5?8j68h4=70:>0`<5?8368h4=704>0`<5?8=68h4=706>0`<5?8?68h4=700>0`<5?8968h4=702>0`<5?9;6;84}r0ff?6=?rT9io52504961?<5=?i6<;9;<7b5?72?27>4h4>589>1c6=9<2018jk:07;?xu5m00;65uQ2d;890722;>270::1;:5?822i3;>:63:a08213=:=1o1=894=4d3>43134?oh7?:6:
\7fp6`>=832pR?k7;<720?43127?9=476:?71<<6=?169l>5145890>c28?270;jf;36<>;2lj0:955rs3g4>5<?sW8n;63:12810<=:<=l14;5244:9500<5<k;6<;9;<7;`?72?27>ik4>579>1ae=9<<0q~<j6;29<~X5m?169<<525;8912b21<019;8:075?83>n3;>;63:8b821<=:=lo1=864=4fa>43?3ty9i84?:9y]6`3<5<;:6?:6;<67`?>134>>:7?:6:?6=c<6=?1695m5145890cb28?=70;kb;362>{t:l>1<76t^3g7?836838?563;4b8;2>;3=<0:9;5258g9501<5<2i6<;6;<7f`?72027>hl4>599~w7c42903wS<j3:?64c<5<01689l5879>002=9<<0187j:075?83?j3;>;63:ee8213=:=mk1=884}r0f6?6=0rT9i?5251g961?<5=>j6584=570>43134?2h7?:7:?6<d<6=0169hm514:890b>28?37p}=e083>=}Y:l;018>k:36:?823132=70::2;362>;21m0:9;5259c9501<5<oh6<;9;<7g=?72>2wx484?:9y]6c0<V1?01>j9:36:?834n3<i70:88;362>;28=0:9;523b09500<5?9;6>k4}r:0>5<>sW8m86P73:?0`0<5<0168;k5879>021=9<<018>::075?837<3;>;63<b68213=:>::1?i5rs9094??|V;l87S6=;<1g0?43127?:i476:?733<6=?169=851448906228?<70=m5;362>;1;908o6s|8083><}Y:o80R5?4=2f0>72>34>=o769;<641?72>27><:4>579>150=9<=01>l<:075?804839i7p}70;29=~X5n81U4=523e0961?<5=<i6584=557>43134?;47?:6:?642<6=>16?o?5144893572=30q~9i:18:
\7f[4a82T<j63<d0810<=:<?k14;524619500<5<:26<;9;<73<?72?278mk4>579>266=<11v
\7f:k50;;xZ7ca3W=n70=k0;07=>;3>003:63;738213=:=9k1=884=42:>430349jh7?:6:?575<3?2wx;i4?:8y]6`c<V>n01>mi:36:?821032=70:81;362>;28k0:9;5251c9501<5:ki6<;9;<404?213ty<o7>59z\1aa=Y?j16?nk525;8910021<0199?:075?837k3;>:63:0c8212=:;h31=884=713>13<uz=i6=47{_0fg>X0j278oi4=489>030=0?168;h51448906d28?<70=m8;361>;1;90?86s|2c694?3|V;h?70=n6;07=>;20l0:95525g2950?<5:396<;9;|q1f7<72<qU>o<4=2c6>72>34?3i7?:6:?6b5<6=>16?5951448yv4e93:19vP=b09>7d2=:=30186k:07;?83bn3;>563<848213=z{;h;6=4:{_0a4>;4i:09845259f9500<5<om6<;8;<1;7?72>2wx>lh50;7xZ7ga349j>7<;9:?6<f<6=1169hk514;896>628?=7p}=ad83>0}Y:ho01>o>:36:?83?k3;>:63:ed8212=:;>l1=884}r0b`?6==rT9mi523`2961?<5<2i6<;7;<7f`?721278;i4>579~w7gd290>wS<nc:?0=c<5<01695l5144890cc28?<70=8b;362>{t:hh1<7;t^3ca?85>m38?563:8`821==:=li1=874=25:>4313ty9ml4?:4y]6dg<5:3o6?:6;<7;e?72>27>in4>569>7=>=9<?0q~9n:18:
\7f[4en2T<m63<77810<=:<m81:o5244`9501<5=3<6<;9;<7g`?721278:?4>579>266=<l1v
\7f:650;;xZ7dc3W=370=85;07=>;3=h0:9:5248:9500<5=3<6<;8;<7g`?72?2789:4>579>266=<m1v
\7f:950;;xZ7dd3W=<70=84;07=>;3=00:9:5248;9500<5=336<;8;<7gg?721278984>579>266=<j1v
\7f:850;;xZ7de3W==70=83;07=>;3=10:9:5248c9500<5=326<;8;<7gg?72?2789>4>579>266=<k1v
\7f:;50;;xZ7df3W=>70=82;07=>;3=>0:9:5248`9500<5=3j6<;8;<7gf?7212789<4>579>266==01v
\7f::50;;xZ7d>3W=?70=81;07=>;3=?0:9:5248a9500<5=3i6<;8;<7gf?72?2788k4>579>266==11v
\7f:=50;;xZ7d?3W=870=80;07=>;3=<0:9:5248f9500<5=3h6<;8;<7ge?7212788i4>579>266==>1v
\7f:<50;;xZ7d03W=970=9f;07=>;3==0:9:5248g9500<5=3o6<;8;<7ge?72?2788o4>579>266==?1v
\7f:?50;;xZ7d13W=:70=9e;07=>;3=:0:9:5248d9500<5=3n6<;8;<7g=?721278844>579>266==<1v
\7f:>50;:xZ7d23W=;70=9d;07=>;3=;0:9:5248d9501<5<n26<;8;<16<?72=27=?=4:4:
\7fp6fg=83=pR?mn;<6b=?43127?;54>569>1f1=9<=018l;:07:?806j3;>563909821<=z{;i36=48{_0`<>;3i10984524659501<5<i<6<;9;<7a0?72?27==o4>569>25>=9<=0q~<l7;293~X5k>168l9525;8911128?<70;l6;363>;2j:0:945260c950?<5?:<6<;6;|q1g3<72>qU>n84=5c5>72>34><97?:7:?6g3<6=?169o=51458937f28?<708?7;363>{t:j?1<79t^3a6?82f=38?563;758212=:=j?1=894=4`1>43>34<:57?:9:?543<6=01v
\7f?m;:184
\7f[4d<27?m94=489>025=9<=018m::075?83e:3;>;639188212=:>9<1=894}r0`7?6=?rT9o>524`1961?<5==96<;8;<7`0?72?27>n<4>589>24>=9<301;>::07:?xu5k;0;6:uQ2b0891g52;>270:81;363>;2k=0:9;525c39501<5?;36<;8;<431?72?2wx>n?50;5xZ7e634>j=7<;9:?735<6=>169n=5145890d728?2708>7;36=>;18=0:945rs3a3>5<0sW8h<63;a1810<=:<?l1=894=4a0>43134?i<7?:7:?552<6=>16:=:51458yv4?i3:1>vP=8`9>27g=:=30q~<78;296~X50116:?7525;8yv4??3:1>vP=869>27>=:=30q~<76;296~X50?16:?9525;8yv4?=3:1>vP=849>270=:=30q~<74;296~X50=16:?;525;8yv4?;3:1>vP=829>272=:=30q~<72;296~X50;16:?=525;8yv4?93:1>vP=809>274=:=30q~<70;296~X50916:??525;8yv4c=3:18vP=d49>050=:=301;>7:07;?85a:3;>:6s|2e194?2|V;n870:?5;07=>;1810:9;523d59500<uz8o>7>54z\1`7=:<9>1>974=724>43?349n97?:6:
\7fp6a7=83>pR?j>;<637?43127=<:4>579>7`5=9<<0q~<k0;290~X5l9168=<525;8936128?370=j1;362>{t:jl1<7:t^3ae?827938?5639078213=:;ml1=884}r0`a?6=<rT9oh52412961?<5?:>6<;7;<1g`?72>2wx>nj50;6xZ7ec349mj7<;9:?540<6=?16?il51448yv4dk3:18vP=cb9>7cc=:=301;>;:07;?85c13;>:6s|2b`94?2|V;ii70=id;07=>;18=0:9;523d:9503<uz8n<7>55z\1a5=:<:<1>974=4`7>43?34<:n7?:8:?767<6=?1v
\7f?jj:186
\7f[4cm27??84=489>1g2=9<<01;?m:075?826?3;>:6s|2ef94?3|V;no70:<4;07=>;2j:0:955260c950><5=;>6<;9;|q1`f<72<qU>im4=510>72>34?i?7?:6:?55d<6=?168<=51448yv4cj3:19vP=dc9>064=:=3018l=:07;?80613;>463;108213=z{;nj6=4:{_0ge>;3;80984525c09500<5?;26<;9;<63b?72>2wx>i750;7xZ7b>34>8<7<;9:?6f4<6=116:<6514:8916c28?=7p}=d983>0}Y:m2019<i:36:?83e93;>:639198213=:<9h1=884}r0g3?6==rT9h:5243g961?<5<h;6<;7;<423?72027?<44>579~w7b1290>wS<k6:?76a<5<0169o>51448937028?=70:>8;361>{t9:n1<7<t^01g?80483;8<6s|12`94?4|V89i708<0;33a>{t9:k1<7<t^01b?80483;;h6s|12;94?4|V892708<0;33g>{t9:21<7<t^01;?80483;;n6s|12594?4|V89<708<0;33e>{t9:<1<7<t^015?80483;;56s|12794?4|V89>708<0;31<>{t9=<1<7<t^065?80483;9;6s|15794?4|V8>>708<0;31b>{t9=>1<7<t^067?80483;9:6s|15194?4|V8>8708<0;311>{t9=81<7<t^061?80483;986s|15394?4|V8>:708<0;317>{t9=:1<7<t^063?80483;9>6s|12d94?4|V89m708<0;32a>{t9:o1<7<t^01f?80483;:?6s|12694?4|V89?708<0;33<>{t:<21<7<t^37;?830i38?56s|24494?4|V;?=70;89;07=>{t:<?1<7<t^376?830038?56s|24694?4|V;??70;87;07=>{t:<91<7<t^370?830>38?56s|24094?4|V;?970;85;07=>{t:<;1<7<t^372?830<38?56s|24294?4|V;?;70;83;07=>{t:=l1<7<t^36e?830:38?56s|25g94?4|V;>n70;81;07=>{tl;0;6?uQd39>266=lm1v
\7fi>50;0xZa6<5?9;65j4}rae>5<5sWim708<0;:`?xudm3:1>vPle:?575<?j2wxoi4?:3y]ga=:>::14l5rsba94?4|Vji01;=?:9;8yvee2909wSmm;<404?>?3tyhm7>52z\`e>;1;90j;6s|dc83>7}Ylk16:>>5a79~wag=838pRio4=713>ae<uzn26=4={_f:?80483k>7p}k8;296~Xc027=?=4n4:
\7fp`2<72;qUh:526229e6=z{m<1<7<t^e4893572h80q~j::181
\7f[b234<8<7o>;|qg0?6=:rTo8639318:`>{tl:0;6?uQd29>266=1;1v
\7fn750;0xZf?<5?9;6594}r3a0?6=9:q6>4>52128916021<01>j8:948961021<01>o8:948962021<018mi:77890c52??018hn:778936c2??0186?:77890?42??018o9:77890d>2??019;l:778912>2??01996:77891012??01;=?:06;?xu1:m0;6?u263a92g=:>;n1>974}r41f?6=<kq6:?m525;8934c2?>01>7j:7:896?c2;:?70=n1;4;?85>n3<370=n0;4;?85f<3<370=n2;4;?85f;3<370=n5;4;?85f>3<370=9d;4;?851m3<370=9f;4;?85083<370=81;4;?850:3<370=83;4;?850<3<370=85;4;?850>3<370;la;030>;3l;0=463;d085<>;3l90=463;cg85<>;3kl0=463;ce85<>;3kj0=463;cc85<>;3kh0=463;c885<>;29?0=463:1485<>;29=0=463:1285<>;29;0=463:1085<>;2990=463:0g85<>;28l0=463:0e85<>;2=:0=463:5385<>;2=80=463:5185<>;2<o0=463:4d85<>;2<m0=463:4b85<>;2<k0=463:4`85<>;2>>0=463:6785<>;2><0=463:6585<>;2>:0=463:6385<>;2>80=463:6185<>;2=o0=463:5d85<>;2?h0=463:7885<>;2?10=463:7685<>;2??0=463:7485<>;2?=0=463:7285<>;2?;0=463:7085<>;1;;0:95526229630<uz<9i7>555y>27`=>=16:?k525;8914b2;:?70:=d;4;?82493<370:=f;4;?82483<370:<4;4;?824:3<370:<3;4;?824=3<370:<6;4;?85am3<370=id;030>;3880=463<fg85<>;3890=463;0585<>;38;0=463;0285<>;38<0=463;0785<>;4km0=463<cd85<>;4ko0=463<d185<>;4l80=463<d385<>;4l:0=463<d585<>;4l<0=463<d785<>;2n<09<9524`;92==:<h21:5524`592==:<h<1:5524`792==:<h>1:5524`192==:<h81:5524`392==:<h:1:5524d492==:<l?1:5524d692==:<l91:5524d092==:<l;1:5524d292==:<ml1:5524eg92==:<mn1:5524gc92==:<o31:5524g:92==:<o=1:5524g492==:<o?1:5524g692==:<o91:5524g092==:<o;1:55252d92==:=:o1:55252f92==:=:i1:55252`92==:=:k1:55252;92==:=:21:55252592==:=:<1:55263c92==:>;31:55263:92==:>;=1:55263492==:>;?1:55263692==:>;91:55263092==:>;;1:5526229633<uz<9j7>52z?56c<5<016:?k56c9~w1432909w0:=e;4a?82613;mh6s|43194?5|5=8o6;l4=524>73a34>:47?id:
\7fp071=838p19=>:7`8917d28lo7p};2483>7}:<;l1:o5240c95cb<uz>9:7>52z?775<1j27?=o4>fe9~w14f2909w0:<4;4a?826n3;mh6s|43:94?4|5=996;l4=53g>4`c3ty?>44?:3y>065=>k168<k51gf8yv25j3:1>v3;3485f>;3:90:ji5rs50`>5<5s4>8:78m;<615?7al2wx8=950;1x916028lo70:?8;46?82613<>7p};0883>6}:<921>8h4=53:>4gf34>;57?id:
\7fp05>=839p19>7:0dg?827i3<>70:>a;46?xu38k0;6>u241c960`<5=;j6<on;<63f?7al2wx8=o50;1x916f28lo70:?c;46?826j3<>7p};0e83>6}:<9i1>8h4=53a>4gf34>;h7?id:
\7fp05e=839p19>l:0dg?827m3<>70:>c;46?xu38o0;6>u241g960`<5=;h6<on;<63b?7al2wx8=k50;1x916b28lo70:>0;46?826l3<>7p};1083>6}:<8:1>8h4=53g>4gf34>:=7?id:
\7fp046=839p19??:0dg?826:3<>70:>e;46?xu39:0;6>u2400960`<5=;n6<on;<627?7al2wx8<<50;1x917528lo70:>4;46?826n3<>7p};1483>6}:<8>1>8h4=53e>4gf34>:97?id:
\7fp042=839p19?;:0dg?826>3<>70:=0;46?xu39>0;6>u2404960`<5=8;6<on;<623?7al2wx8<850;0x917128lo70:=1;46?xu3:;0;6?u243395dg<5=896<hk;|q0b1<72;q6?kk56c9>7`?=9on0q~=i3;297~;4nm0=n63<d6811c=:;l21=kj4}r1e3?6=:r7?<<49b:?0af<6nm1v
\7f>h::181
\7f85an3<i70=ja;3e`>{t;o<1<7<t=523>3d<5:oi6<hk;|q0bd<72;q68=:56c9>7``=9on0q~=i8;296~;38;0=n63<ee82ba=z{:l26=4={<637?0e349ni7?id:
\7fp7cd=838p19>::7`896`728lo7p}<fb83>7}:<9<1:o523g395cb<uz9o;7>53z?0`2<6nm16?i65649>7`?=><1v
\7f>j6:180
\7f85c038>j63<e882ed=:;m31=kj4}r1g<?6=;r78h54>fe9>7ag=><16?ho5649~w6be2908w0=ka;06b>;4mh0:ml523e`95cb<uz9om7>53z?0`d<6nm16?im5649>7`d=><1v
\7f>jk:180
\7f85ck38>j63<ec82ed=:;mn1=kj4}r1gg?6=;r78hn4>fe9>7ac=><16?hm5649~w6ba2908w0=ke;06b>;4mj0:ml523ed95cb<uz9oi7>53z?0``<6nm16?h>5649>7`b=><1v
\7f>k>:180
\7f85b838>j63<ee82ed=:;l;1=kj4}r1f4?6=;r78i=4>fe9>7`4=><16?hk5649~w6c42908w0=j2;06b>;4ml0:ml523d195cb<uz9n>7>53z?0a7<6nm16?h:5649>7``=><1v
\7f>k::180
\7f85b<38>j63<eg82ed=:;l?1=kj4}r1f0?6=;r78i94>fe9>7`0=><16?k>5649~w6c02908w0=j6;06b>;4n90:ml523d595cb<uz9n:7>52z?0a3<6nm16?k?5649~w6`52909w0=i1;3be>;4n;0:ji5rs2;7>5<5s492i78m;<1;=?7al2wx?4=50;1x96?c2?h01>98:37e?85?03;mh6s|38594?4|5:k:6;l4=2:`>4`c3ty8584?:3y>7<`=>k16?5o51gf8yv5>>3:1>v3<a185f>;40k0:ji5rs2;b>5<5s49j878m;<1;b?7al2wx?4650;0x96g52?h01>6k:0dg?xu4100;6?u23`192g=:;1o1=kj4}r1:f?6=:r78m849b:?0=5<6nm1v
\7f>7l:181
\7f85f>3<i70=61;3e`>{t;>=1<7=t=254>4`c349<478:;<1;=?023ty8;44?:2y>72>=:<l01>66:0cb?85013;mh6s|36:94?5|5:=36<hk;<14e?023493m78:;|q03g<72:q6?:o524d896>f28kj70=8b;3e`>{t;>k1<7=t=25b>4`c349<o78:;<1;f?023ty8;i4?:2y>72e=:<l01>6m:0cb?850l3;mh6s|36a94?5|5:=h6<hk;<14a?023493o78:;|q03c<72:q6?:k524d896>d28kj70=8f;3e`>{t;>o1<7=t=25f>4`c3493<78:;<1;`?023ty84<4?:2y>7=6=:<l01>6k:0cb?85?93;mh6s|39294?5|5:2;6<hk;<1;6?023493i78:;|q0<6<72:q6?5<524d896>b28kj70=73;3e`>{t;181<7=t=2:1>4`c3493878:;<1;b?023ty8484?:2y>7=2=:<l01>6i:0cb?85?=3;mh6s|39694?5|5:2?6<hk;<1;2?023492<78:;|q0<2<72:q6?58524d896?728kj70=77;3e`>{t;1<1<7<t=2:5>4`c3492=78:;|q0=7<72;q6?4?51`c896?528lo7p}<c283>6}:;jn1:o523`5960`<5:h36<hk;|q0g1<72;q6?nk56c9>7g?=9on0q~=l5;296~;4ko0=n63<b`82ba=z{:i=6=4={<1g4?0e349in7?id:
\7fp7f1=838p1>j>:7`896dd28lo7p}<c983>7}:;m81:o523cf95cb<uz9h57>52z?0`6<1j278nh4>fe9~w6ef2909w0=k4;4a?85en3;mh6s|3b`94?4|5:n>6;l4=2a3>4`c3ty8on4?:3y>7a0=>k16?n?51gf8yv5f?3:1?v3<a682ba=:;h21:8523c;920=z{:k26=4<{<1b<?42n278n44>a`9>7d?=9on0q~=n8;297~;4i10:ji523`c920=:;kk1:85rs2ca>5<4s49jm7<:f:?0fd<6ih16?ll51gf8yv5fi3:1?v3<a`82ba=:;hi1:8523c`920=z{:ko6=4<{<1bg?42n278no4>a`9>7db=9on0q~=nc;297~;4ij0:ji523`g920=:;ki1:85rs2ce>5<4s49ji7<:f:?0ff<6ih16?lh51gf8yv5fm3:1?v3<ad82ba=:;k:1:8523cf920=z{:h:6=4<{<1a4?42n278ni4>a`9>7g7=9on0q~=m0;297~;4j90:ji523c0920=:;ko1:85rs2`0>5<4s49i>7<:f:?0f`<6ih16?o=51gf8yv5e:3:1?v3<b382ba=:;k>1:8523cd920=z{:h>6=4<{<1a0?42n278nk4>a`9>7g3=9on0q~=m4;297~;4j=0:ji523c4920=:;j:1:85rs2`4>5<4s49i:7<:f:?0g5<6ih16?o951gf8yv5e>3:1>v3<b782ba=:;j;1:85rs2a1>5<5s49h=7?na:?0g7<6nm1v
\7f>8<:180
\7f851l3<i70=;7;06b>;4=10:ji5rs247>5<5s49=i78m;<16=?7al2wx?;;50;0x960a2?h01>;n:0dg?xu4>?0;6?u236292g=:;<h1=kj4}r153?6=:r78;<49b:?01f<6nm1v
\7f>87:181
\7f850:3<i70=:d;3e`>{t;?31<7<t=250>3d<5:?n6<hk;|q02d<72;q6?::56c9>70`=9on0q~=9b;296~;4?<0=n63<6182ba=z{:<h6=4={<142?0e349==7?id:
\7fp711=839p1>:8:0dg?85303<>70=:9;46?xu4<00;6>u235:960`<5:?26<on;<17=?7al2wx?9650;1x962?28lo70=;a;46?852i3<>7p}<4c83>6}:;=k1>8h4=27b>4gf349?n7?id:
\7fp71g=839p1>:n:0dg?853k3<>70=:b;46?xu4<m0;6>u235a960`<5:?i6<on;<17`?7al2wx?9m50;1x962d28lo70=;e;46?852k3<>7p}<4g83>6}:;=o1>8h4=27`>4gf349?j7?id:
\7fp71c=839p1>:j:0dg?85283<>70=:d;46?xu4=80;6>u2342960`<5:?o6<on;<165?7al2wx?8>50;1x963728lo70=:2;46?852m3<>7p}<5283>6}:;<81>8h4=27f>4gf349>?7?id:
\7fp704=839p1>;=:0dg?852<3<>70=:f;46?xu4=<0;6>u2346960`<5:?m6<on;<161?7al2wx?8:50;1x963328lo70=:6;46?85183<>7p}<5683>6}:;<<1>8h4=243>4gf349>;7?id:
\7fp700=838p1>;9:0dg?85193<>7p}<6383>7}:;?;1=lo4=241>4`c3ty>h94?:3y>1f`=:<l018j6:0dg?xu2kk0;6?u25bd95cb<5<n;6;;4}r7g1?6=:r7>h=4=5g9>1ag=9on0q~;lc;296~;2l90:ji525e3920=z{<n=6=4={<7g5?42n27>ho4>fe9~w0ec2909w0;k1;3e`>;2l;0=96s|5e594?4|5<n96?;i;<7gg?7al2wx9nk50;0x90b528lo70;k3;46?xu2l10;6?u25e1960`<5<no6<hk;|q6b4<72;q69i=51gf890e>28?27p}:e683>7}:=l81>8h4=4g`>4`c3ty>hh4?:3y>1`4=9on018k<:778yv3b03:1>v3:e2811c=:=ln1=kj4}r7gb?6=:r7>i>4>fe9>1`2=><1v
\7f8k6:181
\7f83b<38>j63:ed82ba=z{<o;6=4={<7f0?7al27>i8495:
\7fp1`g=838p18k::37e?83bn3;mh6s|5d394?4|5<o>6<hk;<7f2?023ty>io4?:3y>1`0=:<l018h?:0dg?xu2n;0;6?u25d495cb<5<i26<;7;|q6g=<72;q69no56c9>1f?=9on0q~;if;296~;2nh099k5261695cb<uz?m:7>52z?6bd<6nm169kl5649~w3672909w0;ib;06b>;18<0:ji5rs4d4>5<5s4?mn7?id:?6bf<1=2wx:=?50;0x90`d2;?m708?6;3e`>{t=o21<7<t=4d`>4`c34?mh78:;|q547<72;q69kj524d8936028lo7p}:f883>7}:=on1=kj4=4df>33<uz<;?7>52z?6b`<5=o16:=651gf8yv06k3:1>v3:fd82ba=:=o>1=874}r426?6=:r7=<i4=5g9>241=9on0q~8?9;296~;18m0:ji5261g920=z{?;86=4={<43a?42n27==54>fe9~w36f2909w08?e;3e`>;18o0=96s|60694?4|5?:m6?;i;<42=?7al2wx:=l50;0x936a28lo708>0;46?xu19<0;6?u2602960`<5?;j6<hk;|q54f<72;q6:<>51gf893762??0q~8>6;296~;198099k5260`95cb<uz<:h7>52z?554<6nm169k:514:8yv3a;3:1>v3:f485f>;2n=0:ji5rs4:6>5<5s4?3<7<:f:?6<d<6nm1v
\7f89l:181
\7f83?83;mh63:80851>{t=1<1<7<t=4:2>73a34?3n7?id:
\7fp12b=838p186>:0dg?83?:3<>7p}:8683>7}:=181>8h4=4:`>4`c3ty>;h4?:3y>1=4=9on0186<:778yv3?03:1>v3:82811c=:=1n1=kj4}r74b?6=:r7>4>4>fe9>1=2=><1v
\7f866:181
\7f83?<38>j63:8d82ba=z{<336=4={<7:7?42n27>5i4>fe9~w0>a2909w0;63;3e`>;21=0=96s|58;94?4|5<3?6?;i;<7:a?7al2wx94>50;0x90?328lo70;65;46?xu21h0;6?u2587960`<5<3m6<hk;|q6=4<72;q694;51gf890?12??0q~;6b;296~;21?099k525`295cb<uz?2>7>52z?6=3<6nm169495649~w0?d2909w0;67;06b>;2i80:ji5rs4ca>5<5s4?j:7<:f:?6f5<6nm1v
\7f8o=:181
\7f83f>3;mh63:a6851>{t=hi1<7<t=4c4>73a34?i=7?id:
\7fp1d5=838p18o8:0dg?83f03<>7p}:ae83>7}:=h21>8h4=4`1>4`c3ty>m94?:3y>1d>=9on018o6:778yv3fm3:1>v3:a8811c=:=k91=kj4}r7b1?6=:r7>m44>fe9>1dg=><1v
\7f8oi:181
\7f83fi38>j63:b582ba=z{<hn6=4={<7a=?42n27>o>4>fe9~w0d22909w0;m9;3e`>;2jh0=96s|5cd94?4|5<hj6?;i;<7`0?7al2wx9o850;0x90df28lo70;mb;46?xu2k90;6?u25c`960`<5<i>6<hk;|q6f2<72;q69ol51gf890dd2??0q~;l1;296~;2jj099k525b495cb<uz?i47>52z?6ff<6nm169oj5649~w0e52909w0;md;06b>;2k>0:ji5rs5f`>5<2s4>j578m;<6f2?43127?mo4>569>0db=9<<019oi:07:?xu3ih0;6?u24`:92g=:<hh1=kj4}r6bg?6=:r7?m:49b:?7ea<6nm1v
\7f9oj:18;
\7f82f>3<i70:nf;3e`>;3j80:9:524c1950><5=h>6<;6;<6ae?72127?nn4>589>0gc=9<30q~:m0;296~;3i<0=n63;b082ba=z{=h96=4={<6b0?0e34>i?7?id:
\7fp0g2=838p19o<:7`891d228lo7p};b783>7}:<h81:o524cc95cb<uz>in7>52z?7e4<1j27?nn4>fe9~w1dc2909w0:n0;4a?82em3;mh6s|4g294?4|5=o=6;l4=5db>72>3ty?ik4?:3y>0`3=>k168k7525;8yv2cj3:18v3;e4810<=:<hh1=884=5cg>43034>jj7?:8:
\7fp0`c=838p19k;:7`891`?2;>27p};d`83>6}:<l>1>974=5cg>43?34>jj7?:7:
\7fp0`b=838p19k<:7`891`02;>27p};d883>7}:<l91>974=5ce>4313ty?in4?:3y>0`4=>k168k8525;8yv2c03:1;v3;e3810<=:<k;1=884=5`0>43034>i97?:8:?7fd<6=>168om5145891db28?<7p};ec83>7}:<l;1:o524g7961?<uz>o;7>56z?7a4<5<0168o=5144891d228?<70:ma;362>;3jj0:9;524cg9500<uz>nm7>52z?7a5<1j27?j94=489~w1b1290>w0:j0;07=>;3j<0:9;524c59500<5=h36<;9;<6a=?72>2wx8h750;0x91ba2?h019h<:36:?xu3l<0;69u24ed961?<5=h<6<;8;<6a<?72?27?n44>569~w1c?2909w0:ke;4a?82a:38?56s|4e694?5|5=nn6?:6;<6a<?72027?n44>599~w1c02909w0:kd;4a?82a938?56s|4e194?4|5=no6?:6;<6a=?7212wx8n650;0x91`f2?h019j=:36:?xu3k>0;6?u24g;92g=:<m;1>974}r6`2?6=:r7?j549b:?7`5<5<01v
\7f9m::181
\7f82a?3<i70:lf;07=>{t<j>1<7<t=5d5>3d<5=in6?:6;|q7g6<72;q68k;56c9>0fb=:=30q~:l2;296~;3n=0=n63;cb810<=z{=i:6=4={<6e7?0e34>hn7<;9:
\7fp0f6=838p19h=:7`891ef2;>27p};bg83>7}:<o;1:o524b;961?<uz>mn7>52z?7`4<1j27?5:4>fe9~w1`d2909w0:k0;4a?82>03;mh6s|4gf94?4|5=im6;l4=5;:>4`c3ty?jh4?:3y>0fc=>k1684o51gf8yv2an3:1>v3;ce85f>;31k0:ji5rs423>5<5s4>ho78m;<6:g?7al2wx9=?50;0x91ee2?h0197k:0dg?xu28;0;6?u24bc92g=:<0o1=kj4}r737?6=:r7?o449b:?7=c<6nm1v
\7f8:6:186
\7f836>3<i70;:3;07=>;2910:9:5250c9500<5<;h6<;6;|q652<72;q69<;56c9>14>=9on0q~;>9;296~;29=0=n63:1`82ba=z{<;i6=47{<727?0e34?:o7?id:?65`<6=>169?>514:8904528?270;=7;36=>;2:00:945253`950?<uz?:h7>52z?657<1j27>=h4>fe9~w07a2909w0;>1;4a?83583;mh6s|53394?4|5<;;6;l4=401>4`c3ty>>>4?:3y>15`=>k169?951gf8yv3503:1>v3:0d85f>;2:00:ji5rs40b>5<5s4?;h78m;<71f?7al2wx98j50;0x90342?h01888:36:?xu2=j0;6?u254092g=:=?<1>974}r77<?6=<r7>9?4=489>14>=9<<018?n:074?836k3;>46s|54`94?4|5<?:6;l4=446>72>3ty>8:4?:2y>107=:=3018?n:07;?836k3;>;6s|54c94?4|5<?;6;l4=447>72>3ty>8;4?:3y>106=:=3018?l:075?xu2=00;6?u255d92g=:=?91>974}r771?6=?r7>8k4=489>14c=9<<018<?:074?835:3;>463:268212=:=;31=894=40a>4303ty>954?:3y>11c=>k169;<525;8yv33<3:1:v3:4d810<=:=;:1=884=401>43034?9;7?:6:?66<<6=?169?l51448yv32?3:1>v3:4e85f>;2>809845rs460>5<2s4??h7<;9:?667<6=?169?:51448904228?=70;=6;362>{t=<<1<7<t=46`>3d<5<<;6?:6;|q607<72=q699m525;8904328?<70;=5;363>;2:?0:9:5rs476>5<5s4??n78m;<76b?4312wx99?50;1x902e2;>270;=5;36<>;2:?0:955rs477>5<5s4??m78m;<76a?4312wx99>50;0x902f2;>270;=6;36=>{t=:?1<7<t=444>3d<5<9m6?:6;|q671<72;q69;856c9>16c=:=30q~;<3;296~;2><0=n63:3e810<=z{<996=4={<750?0e34?8o7<;9:
\7fp167=838p188<:7`8905e2;>27p}:3183>7}:=?81:o5252c961?<uz?9j7>52z?624<1j27>?44=489~w04b2909w0;90;4a?834038?56s|53f94?4|5<?m6;l4=414>72>3ty>>n4?:3y>10c=>k169>8525;8yv3103:1>v3:3d85f>;28=0:ji5rs44:>5<5s4?8h78m;<731?7al2wx9;o50;0x905d2?h018>9:0dg?xu2>k0;6?u252`92g=:=9=1=kj4}r75g?6=:r7>?l49b:?64=<6nm1v
\7f88k:181
\7f83413<i70;?9;3e`>{t=?o1<7<t=41;>3d<5<:j6<hk;|q62c<72;q69>956c9>15d=9on0q~;80;296~;2;?0=n63:0b82ba=z{=?:6=4={<651?0234>>=7?id:
\7fp0<4=838p198::0cb?822j3;mh6s|42c94?4|5=<>6<hk;<74e?0e3ty?9=4?:2y>032=><1688?5649>006=9on0q~:61;297~;3>=0:ml52443960`<5=?j6<hk;|q77<<72;q68;:51gf8901>2?h0q~:;f;297~;3>:0=963;51851>;3<o0:ji5rs5;3>5<4s4>=?7?na:?715<5=o1688751gf8yv2403:1>v3;6282ba=:=>21:o5rs56f>5<4s4>=>78:;<67b?0234>?i7?id:
\7fp0=`=839p198=:0cb?823n38>j63;5982ba=z{=9<6=4={<656?7al27>;:49b:
\7fp01b=839p198>:778912b2??019:k:0dg?xu30l0;6>u247395dg<5=>n6?;i;<663?7al2wx8>k50;0x910628lo70;86;4a?xu3<j0;6>u2472920=:<=n1:85245a95cb<uz>3h7>53z?725<6ih1689j524d8913128lo7p};3e83>7}:<?:1=kj4=456>3d<uz>?n7>53z?71c<1=27?8n495:?70g<6nm1v
\7f96l:180
\7f822n3;jm63;4b811c=:<<?1=kj4}r60g?6=:r7?9k4>fe9>122=>k1v
\7f9:n:180
\7f822m3<>70:;b;46?823i3;mh6s|49`94?5|5=?n6<on;<67f?42n27?994>fe9~w15e2909w0::e;3e`>;2?:0=n6s|45;94?5|5=?o6;;4=56b>33<5=>26<hk;|q7<d<72:q688j51`c8912f2;?m70::3;3e`>{t<:l1<7<t=57g>4`c34?<>78m;|q7<<<72:q688m51`c8912>2;?m70::2;3e`>{t>8o1<7<t=57`>4`c34?<=78m;|q72`<72;q685<5649>03c=9on0q~:78;296~;30;0:ml5246:95cb<uz>??7>52z?7<7<6nm16:?o56c9~w10c2908w0:71;46?821m3<>70:9d;3e`>{t<1=1<7=t=5:2>4gf34>=i7<:f:?732<6nm1v
\7f9:=:181
\7f82?93;mh6392885f>{t<?i1<7=t=5:3>33<5=<o6;;4=54`>4`c3ty?4;4?:2y>0=6=9hk0198k:37e?820>3;mh6s|45394?4|5=2;6<hk;<41<?0e3ty?:o4?:2y>02`=><168;m5649>03d=9on0q~:75;297~;3?o0:ml5247a960`<5==>6<hk;|q705<72;q68:h51gf893402?h0q~:9a;297~;3?l0=963;6c851>;3>h0:ji5rs5:7>5<4s4><i7?na:?72g<5=o168::51gf8yv23?3:1>v3;7d82ba=:>;<1:o5rs54:>5<4s4><h78:;<65e?0234>=57?id:
\7fp0=5=839p199k:0cb?821i38>j63;7282ba=z{=>=6=4={<64`?7al27=>849b:
\7fp03>=839p199l:778910>2??01987:0dg?xu31?0;6>u246a95dg<5=<26?;i;<646?7al2wx89;50;0x911d28lo708=4;4a?xu3>>0;6>u246`920=:<?21:85247595cb<uz>297>53z?73g<6ih168;6524d8911628lo7p};4583>7}:<>h1=kj4=700>3d<uz>=:7>53z?73d<1=27?::495:?723<6nm1v
\7f97;:180
\7f820i3;jm63;66811c=:<>:1=kj4}r67<?6=:r7?;l4>fe9>274=>k1v
\7f97<:180
\7f82013;jm63;67811c=:<?l1=kj4}r42b?6=:r7?;44>fe9>277=>k1v
\7f;=>:181
\7f804:3;mh63931820<=z{8l:6=4={<6a3?7al27?nl4>599~w4`42909w0:m8;3e`>;3jj0:955rs0d6>5<5s4>i57?id:?7f`<6=11v
\7f<h8:181
\7f835<3;mh63:26821==z{8l36=4={<711?7al27>>44>599~w4`>2909w0;=6;3e`>;2:k0:955r}c0:4?6=93:1<v*=66812a=O:1o0D?8m;n034?6=3ty=ol4?:3y]2fg<5;<36?;6;|q1e2<72mqU>l74^7ag?[4f>2T9m85Q2`68Z7g43W8j>6P=a09]6d6<V;3m7S<6e:\1=a=::1l1=8=4}r0:<?6=:rT9555227:91g=z{?ih6=4={_4`g>;5>1099h5rs7f0>5<5sW<o?63=69813`=z{:>96=4={_176>;5>10:8:5rs7gb>5<5sW<nm63=6981<g=z{?n:6=4={_4g5>;5>109:45rs3;4>5<5sW82;63=6986e>{t>k>1<7<t^7`7?841038?h6s|62194?4|V?9870<98;3eb>{t>m81<7<t^7f1?841038=o6s|35794?4|V:>>70<98;365>{t>:>1<7<t^717?841038;96s|6e694?4|V?n?70<98;04b>{t>>>1<7<t^757?8410389;6s|6d;94?4|V?nn70<98;0;e>{t>l=1<7<t^7fg?841038346s|6d494?4|V?nh70<98;0;3>{t>l?1<7<t^7fa?8410383:6s|6d694?4|V?nj70<98;0;1>{t>l91<7<t^7f:?841038386s|6d094?4|V?n370<98;0;7>{t>l;1<7<t^7f4?8410383>6s|6d294?4|V?n=70<98;0;5>{t>ml1<7<t^7f6?8410383<6s|32594?4|V:8>70<98;30`>{t;:?1<7<t^207?84103;8n6s|32694?4|V:8870<98;30e>{t;:91<7<t^201?84103;856s|32094?4|V:8:70<98;30<>{t;:;1<7<t^203?84103;8;6s|32294?4|V:;m70<98;302>{t;;l1<7<t^23f?84103;896s|35294?4|V:8o70<98;372>{t;:l1<7<t^20`?84103;?96s|32g94?4|V:8i70<98;370>{t;:n1<7<t^20b?84103;??6s|32a94?4|V:8270<98;376>{t;:h1<7<t^20;?84103;?=6s|32c94?4|V:8<70<98;374>{t;:31<7<t^205?84103;8j6s|32:94?4|V:;o70<98;30a>{t;;o1<7<t^23`?84103;886s|6b;94?4|V?hn70<98;06<>{t>j=1<7<t^7`g?841038>:6s|6b494?4|V?hh70<98;061>{t>j?1<7<t^7`a?841038>86s|6b694?4|V?hj70<98;067>{t>j91<7<t^7`:?841038>>6s|6b094?4|V?h370<98;065>{t>j;1<7<t^7`4?841038><6s|6b294?4|V?h=70<98;07b>{t>kl1<7<t^7`6?841038?i6s|64g94?4|V??870<98;02f>{t><i1<7<t^771?841038:56s|64`94?4|V??:70<98;02<>{t><k1<7<t^773?841038:;6s|64;94?4|V?>m70<98;022>{t><21<7<t^76f?841038:96s|64594?4|V?>o70<98;020>{t><<1<7<t^76`?841038:?6s|64794?4|V?>i70<98;026>{t><>1<7<t^76b?841038:=6s|30094?4|V::;70<98;f1?xu4990;6?uQ2gd8970?2m:0q~=?f;296~X5nl16>;65cg9~w66b2909wS<id:?12=<dm2wx?=j50;0xZ7`d348=47mk;|q04f<72;qU>kl4=34;>fe<uz9;n7>52z\1bd=::?21oo5rs22b>5<5sW8m563=698`e>{t;8h1<7<t^22;?84103ni7p}<1`83>7}Y;9=01?87:ec8yv5613:1>vP<079>63>=l01v
\7f>?7:181
\7f[57=279:54k8:
\7fp741=838pR>>;;<05<?b03ty8=;4?:3y]755<5;<36i84}r121?6=:rT8<?5227:9`0=z{:;?6=4={_135>;5>10o86s|30194?4|V;l370<98;f0?xu4800;6?uQ2g58970?2j30q~8m3;296~X1i116>;6525:8yv0e93:1>vP9a69>63>=:=<0q~8m0;296~X1i?16>;652578yv0fn3:1>vP9a49>63>=:=>0q~8ne;296~X1i=16>;652518yv0fl3:1>vP9a29>63>=:=80q~8nc;296~X1i;16>;652538yv0fj3:1>vP9a09>63>=:=:0q~8na;296~X1i916>;6522d8yv0f13:1>vP99g9>63>=::o0q~86e;296~X11:16>;6522f8yv0>k3:1>vP9939>63>=::h0q~86b;296~X11816>;6522c8yv0>i3:1>vP9919>63>=::30q~869;296~X10o16>;6522:8yv0>03:1>vP98d9>63>=::=0q~867;296~X10m16>;652248yv0>>3:1>vP98b9>63>=::?0q~865;296~X10k16>;652268yv0><3:1>vP98`9>63>=::90q~879;296~X1?l16>;652208yv0??3:1>vP97e9>63>=:::0q~876;296~X1?j16>;6523d8yv0?=3:1>vP97c9>63>=:;o0q~874;296~X1?h16>;6523f8yv0?;3:1>vP9789>63>=:;i0q~872;296~X1?116>;6523`8yv0?93:1>vP9769>63>=:;k0q~870;296~X1??16>;6523;8yv00n3:1>vP9749>63>=:;20q~883;296~X1>116>;652348yv0093:1>vP9669>63>=:;>0q~880;296~X1>?16>;652318yv01n3:1>vP9649>63>=:;80q~89e;296~X1>=16>;652338yv01l3:1>vP9629>63>=:;:0q~89c;296~X1>;16>;6520d8yv01j3:1>vP9609>63>=:8o0q~89a;296~X1>916>;6520f8yv0113:1>vP95g9>63>=:8i0q~8;9;296~X1;l16>;652028yv03?3:1>vP93e9>63>=:9o0q~8;6;296~X1;j16>;6521f8yv03=3:1>vP93c9>63>=:9i0q~8;4;296~X1;h16>;6521`8yv03;3:1>vP9389>63>=:9k0q~8;2;296~X1;116>;6521;8yv0393:1>vP9369>63>=:920q~8;0;296~X1;?16>;652158yv04n3:1>vP9349>63>=:9<0q~?j7;295~;51909<=5r}r126?6=:rT8<=525e8045=#:?k1=hl4}r124?6=:rT9jk525e81bc=#:?k1=hm4}r13b?6=:rT9jh525e81b`=#:?k1=hj4}r13a?6=:rT9ji525e81ba=#:?k1=hk4}r13`?6=:rT9jn525e81bf=#:?k1=k84}r13g?6=:rT9jo525e81bg=#:?k1=o;4}r13f?6=:rT9jl525e81bd=#:?k1=oj4}r13e?6=:rT9j4525e81b<=#:?k1=n64}r12f?6=:rT8<5525e804==#:?k1=nh4}r12e?6=:rT8<:525e8042=#:?k1=i64}r12=?6=:rT8<;525e8043=#:?k1=h<4}r12<?6=:rT8<8525e8040=#:?k1=h=4}r123?6=:rT8<9525e8041=#:?k1=h:4}r122?6=:rT8<>525e8046=#:?k1=h;4}r121?6=:rT8<?525e8047=#:?k1=h84}r120?6=:rT8<<525e8044=#:?k1=h64}r127?6=:rT9j5525e81b==#:?k1=h74}r13=?6=:rT9j:525e81b2=#:?k1=ho4}r4a0?6=:rT=n9525e85f1=#:?k1=hh4}r4`e?6=:rT=ol525e85gd=#:?k1=k>4}r4`g?6=:rT=on525e85gf=#:?k1=k<4}r4g0?6=:rT=h9525e85`1=#:?k1=k:4}r4fe?6=:rT=il525e85ad=#:?k1=k;4}r103?6=:rT8>8525e8060=#:?k1=o84}r101?6=:rT8>9525e8061=#:?k1=o94}r100?6=:rT8>>525e8066=#:?k1=o64}r107?6=:rT8>?525e8067=#:?k1=o74}r106?6=:rT8><525e8064=#:?k1=oo4}r105?6=:rT8>=525e8065=#:?k1=ol4}r104?6=:rT8=k525e805c=#:?k1=om4}r11b?6=:rT8=h525e805`=#:?k1=ok4}r174?6=:rT8>i525e806a=#:?k1=oh4}r10b?6=:rT8>n525e806f=#:?k1=n>4}r10a?6=:rT8>o525e806g=#:?k1=n?4}r10`?6=:rT8>l525e806d=#:?k1=n<4}r10g?6=:rT8>4525e806<=#:?k1=n=4}r10f?6=:rT8>5525e806==#:?k1=n:4}r10e?6=:rT8>:525e8062=#:?k1=n;4}r10=?6=:rT8>;525e8063=#:?k1=n84}r10<?6=:rT8=i525e805a=#:?k1=n94}r11a?6=:rT8=n525e805f=#:?k1=n74}r176?6=:rT88?525e8007=#:?k1=no4}r171?6=:rT888525e8000=#:?k1=nl4}r4`=?6=:rT=nh525e85f`=#:?k1=nm4}r4`3?6=:rT=ni525e85fa=#:?k1=nj4}r4`2?6=:rT=nn525e85ff=#:?k1=nk4}r4`1?6=:rT=no525e85fg=#:?k1=i>4}r4`0?6=:rT=nl525e85fd=#:?k1=i?4}r4`7?6=:rT=n4525e85f<=#:?k1=i<4}r4`6?6=:rT=n5525e85f==#:?k1=i=4}r4`5?6=:rT=n:525e85f2=#:?k1=i:4}r4`4?6=:rT=n;525e85f3=#:?k1=i;4}r4ab?6=:rT=n8525e85f0=#:?k1=i84}r4f=?6=:rT=hh525e85``=#:?k1=i94}r4f3?6=:rT=hi525e85`a=#:?k1=i74}r4f2?6=:rT=hn525e85`f=#:?k1=io4}r4f1?6=:rT=ho525e85`g=#:?k1=il4}r4f0?6=:rT=hl525e85`d=#:?k1=im4}r4f7?6=:rT=h4525e85`<=#:?k1=ij4}r4f6?6=:rT=h5525e85`==#:?k1=ik4}r4f5?6=:rT=h:525e85`2=#:?k1=ih4}r4f4?6=:rT=h;525e85`3=#:?k1=h>4}r4gb?6=:rT=h8525e85`0=#:?k1=h?4}|lf43<72:qC>;l4}og33?6=;rB9:o5rnd2;>5<4sA8=n6sae1;94?5|@;<i7p`j0`83>6}O:?h0qck?b;297~N5>k1vbh>l:180
\7fM41j2wei=j50;1xL70e3tdn<h4?:2yK63d<ugo;j7>53zJ12g=zfl;;6=4<{I05f>{im8;1<7=tH34a?xhb9;0;6>uG27`8ykc6;3:1?vF=6c9~j`732908wE<9b:
\7fma43=839pD?8m;|lf53<72:qC>;l4}og23?6=;rB9:o5rnd3;>5<4sA8=n6sae0;94?5|@;<i7p`j1`83>6}O:?h0qck>b;297~N5>k1vbh?l:180
\7fM41j2wei<j50;1xL70e3tdn=h4?:2yK63d<ugo:j7>53zJ12g=zfl8;6=4<{I05f>{im;;1<7=tH34a?xhb:;0;6>uG27`8ykc5;3:1?vF=6c9~j`432908wE<9b:
\7fma73=839pD?8m;|lf63<72:qC>;l4}og13?6=;rB9:o5rnd0;>5<4sA8=n6sae3;94?5|@;<i7p`j2`83>6}O:?h0qck=b;297~N5>k1vbh<l:180
\7fM41j2wei?j50;1xL70e3tdn>h4?:2yK63d<ugo9j7>53zJ12g=zfl9;6=4<{I05f>{im:;1<7=tH34a?xhb;;0;6>uG27`8ykc4;3:1?vF=6c9~j`532908wE<9b:
\7fma63=839pD?8m;|lf73<72:qC>;l4}og03?6=;rB9:o5rnd1;>5<4sA8=n6sae2;94?5|@;<i7p`j3`83>6}O:?h0qck<b;297~N5>k1vbh=l:180
\7fM41j2wei>j50;1xL70e3tdn?h4?:2yK63d<ugo8j7>53zJ12g=zfl>;6=4<{I05f>{im=;1<7=tH34a?xhb<;0;6>uG27`8ykc3;3:1?vF=6c9~j`232908wE<9b:
\7fm`=4=83;pD?8m;|lg<<<720qC>;l4}ofa3?6=9rB9:o5rne`;>5<6sA8=n6sadc;94?7|@;<i7p`kb`83>4}O:?h0qcjmb;295~N5>k1vbill:182
\7fM41j2wehoj50;3xL70e3tdonh4?:0yK63d<ugnij7>51zJ12g=zfmi;6=4>{I05f>{ilm91<7?tH34a?xhcl=0;6<uG27`8ykbc=3:1=vF=6c9~jab1290:wE<9b:
\7fm`a1=83;pD?8m;|lg`=<728qC>;l4}ofg=?6=9rB9:o5rnefb>5<6sA8=n6sade`94?7|@;<i7p`kdb83>4}O:?h0qcjkd;295~N5>k1vbijj:182
\7fM41j2wehih50;3xL70e3tdoi=4?:0yK63d<ugnn=7>51zJ12g=zfmo96=4>{I05f>{ill91<7?tH34a?xhcm=0;6<uG27`8ykbb=3:1=vF=6c9~jac1290:wE<9b:
\7fm``1=83;pD?8m;|lga=<728qC>;l4}off=?6=9rB9:o5rnegb>5<6sA8=n6sadd`94?7|@;<i7p`keb83>4}O:?h0qcjjd;295~N5>k1vbikj:182
\7fM41j2wehhh50;3xL70e3tdoj=4?:0yK63d<ugnm=7>51zJ12g=zfml96=4>{I05f>{ilo91<7?tH34a?xhcn=0;6<uG27`8ykba=3:1=vF=6c9~ja`1290:wE<9b:
\7fm`c1=83;pD?8m;|lgb=<728qC>;l4}ofe=?6=9rB9:o5rnedb>5<6sA8=n6sadg`94?7|@;<i7p`kfb83>4}O:?h0qcjid;295~N5>k1vbihj:182
\7fM41j2wehkh50;3xL70e3tdn<=4?:0yK63d<ugo;=7>51zJ12g=zfl:96=4>{I05f>{im991<7?tH34a?xhb8=0;6<uG27`8ykd0?3:1=vF=6c9~jg1c290:wE<9b:
\7fmf=7=83;pD?8m;|la<7<728qC>;l4}o`;7?6=9rB9:o5rnc:7>5<6sA8=n6sab9794?7|@;<i7p`m8783>4}O:?h0qcl77;295~N5>k1vbo67:182
\7fM41j2wen5750;3xL70e3tdi4l4?:0yK63d<ugh3n7>51zJ12g=zfk2h6=4>{I05f>{ij1n1<7?tH34a?xhe0l0;6<uG27`8ykd?n3:1=vF=6c9~jg?7290:wE<9b:
\7fmf<7=83;pD?8m;|la=7<728qC>;l4}o`:7?6=9rB9:o5rnc;7>5<6sA8=n6sab8794?7|@;<i7p`m9783>4}O:?h0qcl67;295~N5>k1vbo77:182
\7fM41j2wen4750;3xL70e3tdi5l4?:0yK63d<ugh2n7>51zJ12g=zfk3h6=4>{I05f>{ij0n1<7?tH34a?xhe1l0;6<uG27`8ykd>n3:1=vF=6c9~jgg7290:wE<9b:
\7fmfd7=83;pD?8m;|lae7<728qC>;l4}o`b7?6=9rB9:o5rncc7>5<6sA8=n6sab`794?7|@;<i7p`ma783>4}O:?h0qcln7;295~N5>k1vboo7:182
\7fM41j2wenl750;3xL70e3tdiml4?:0yK63d<ughjn7>51zJ12g=zfkkh6=4>{I05f>{ijhn1<7?tH34a?xheil0;6<uG27`8ykdfn3:1=vF=6c9~jgd7290:wE<9b:
\7fmfg7=83;pD?8m;|laf7<728qC>;l4}o`a`?6=9rB9:o5rnc`f>5<6sA8=n6sabcd94?7|@;<i7p`mc183>4}O:?h0qcll1;295~N5>k1vbom=:182
\7fM41j2wenn=50;3xL70e3tdio94?:0yK63d<ughh97>51zJ12g=zfki=6=4>{I05f>{ijj=1<7?tH34a?xhek10;6<uG27`8ykdd13:1=vF=6c9~jgef290:wE<9b:
\7fmffd=83;pD?8m;|lagf<728qC>;l4}o```?6=9rB9:o5rncaf>5<6sA8=n6sabbd94?7|@;<i7p`md183>4}O:?h0qclif;295~N5>k1vbn>?:182
\7fM41j2weo=?50;3xL70e3tdh<?4?:0yK63d<ugi;?7>51zJ12g=zfj:?6=4>{I05f>{ik9?1<7?tH34a?xhd8?0;6<uG27`8yke7?3:1=vF=6c9~jf6?290:wE<9b:
\7fmg5?=83;pD?8m;|l`4d<728qC>;l4}oa3f?6=9rB9:o5rnb2`>5<6sA8=n6sac1f94?7|@;<i7p`l0d83>4}O:?h0qcm?f;295~N5>k1vbn??:182
\7fM41j2weo<?50;3xL70e3tdh=?4?:0yK63d<ugi:?7>51zJ12g=zfj;?6=4>{I05f>{ik8?1<7?tH34a?xhd9?0;6<uG27`8yke6?3:1=vF=6c9~jf7?290:wE<9b:
\7fmg4?=83;pD?8m;|l`5d<728qC>;l4}oa2f?6=9rB9:o5rnb3`>5<6sA8=n6sac0f94?7|@;<i7p`l1d83>4}O:?h0qcm>f;295~N5>k1vbn<?:182
\7fM41j2weo??50;3xL70e3tdh>?4?:0yK63d<ugi9?7>51zJ12g=zfj8?6=4>{I05f>{ik;?1<7?tH34a?xhd:?0;6<uG27`8yke5?3:1=vF=6c9~jf4?290:wE<9b:
\7fmg7?=83;pD?8m;|l`6d<728qC>;l4}oa1f?6=9rB9:o5rnb0`>5<6sA8=n6sac3f94?7|@;<i7p`l2d83>4}O:?h0qcm=f;295~N5>k1vbn=?:182
\7fM41j2weo>?50;3xL70e3tdh??4?:0yK63d<ugi8?7>51zJ12g=zfj9?6=4>{I05f>{ik:?1<7?tH34a?xhd;?0;6<uG27`8yke4?3:1=vF=6c9~jf5?290:wE<9b:
\7fmg6?=83;pD?8m;|l`7d<728qC>;l4}oa0f?6=9rB9:o5rnb1`>5<6sA8=n6sac2f94?7|@;<i7p`l3d83>4}O:?h0qcm<f;295~N5>k1vbn:?:182
\7fM41j2weo9?50;3xL70e3tdh8?4?:0yK63d<ugi??7>51zJ12g=zfj>?6=4>{I05f>{ik=?1<7?tH34a?xhd<?0;6<uG27`8yke3?3:1=vF=6c9~jf2?290:wE<9b:
\7fmg1?=83;pD?8m;|l`0d<728qC>;l4}oa7f?6=9rB9:o5rnb6`>5<6sA8=n6sac5f94?7|@;<i7p`l4d83>4}O:?h0qcm;f;295~N5>k1vbn;?:182
\7fM41j2weo8?50;3xL70e3tdh9?4?:0yK63d<ugi>?7>51zJ12g=zfj??6=4>{I05f>{ik<?1<7?tH34a?xhd=?0;6<uG27`8yke2?3:1=vF=6c9~jf3?290:wE<9b:
\7fmg0?=83;pD?8m;|l`1d<728qC>;l4}oa6f?6=9rB9:o5rnb7`>5<6sA8=n6sac4f94?7|@;<i7p`l5d83>4}O:?h0qcm:f;295~N5>k1vbn8?:182
\7fM41j2weo;?50;3xL70e3tdh:?4?:0yK63d<ugi=?7>51zJ12g=zfj<?6=4>{I05f>{ik??1<7?tH34a?xhd>?0;6<uG27`8yke1?3:1=vF=6c9~jf0?290:wE<9b:
\7fmg3?=83;pD?8m;|l`2d<728qC>;l4}oa5f?6=9rB9:o5rnb4`>5<6sA8=n6sac7f94?7|@;<i7p`l6d83>4}O:?h0qcm9f;295~N5>k1vbn9?:182
\7fM41j2weo:?50;3xL70e3tdh;?4?:0yK63d<ugi<?7>51zJ12g=zfj=?6=4>{I05f>{ik>?1<7?tH34a?xhd??0;6<uG27`8yke0?3:1=vF=6c9~jf1?290:wE<9b:
\7fmg2?=83;pD?8m;|l`3d<728qC>;l4}oa4f?6=9rB9:o5rnb5`>5<6sA8=n6sac6f94?7|@;<i7p`l7d83>4}O:?h0qcm8f;295~N5>k1vbn6?:182
\7fM41j2weo5?50;3xL70e3tdh4?4?:0yK63d<ugi3?7>51zJ12g=zfj2?6=4>{I05f>{ik1?1<7?tH34a?xhd0?0;6<uG27`8yke??3:1=vF=6c9~jf>?290:wE<9b:
\7fmg=?=83;pD?8m;|l`<d<728qC>;l4}oa;f?6=9rB9:o5rnb:`>5<6sA8=n6sac9f94?7|@;<i7p`l8d83>4}O:?h0qcm7f;295~N5>k1vbn7?:182
\7fM41j2weo4?50;3xL70e3tdh5?4?:0yK63d<ugi2?7>51zJ12g=zfj3?6=4>{I05f>{ik0?1<7?tH34a?xhd1?0;6<uG27`8yke>?3:1=vF=6c9~jf??290:wE<9b:
\7fmg<?=83;pD?8m;|l`=d<728qC>;l4}oa:f?6=9rB9:o5rnb;`>5<6sA8=n6sac8f94?7|@;<i7p`l9d83>4}O:?h0qcm6f;295~N5>k1vbno?:182
\7fM41j2weol?50;3xL70e3tdhm?4?:0yK63d<ugij?7>51zJ12g=zfjk?6=4>{I05f>{ikh?1<7?tH34a?xhdi?0;6<uG27`8ykef?3:1=vF=6c9~jfg?290:wE<9b:
\7fmgd?=83;pD?8m;|l`ed<728qC>;l4}oabf?6=9rB9:o5rnbc`>5<6sA8=n6sac`f94?7|@;<i7p`lad83>4}O:?h0qcmnf;295~N5>k1vbnl?:182
\7fM41j2weoo?50;3xL70e3tdhn?4?:0yK63d<ugii?7>51zJ12g=zfjh?6=4>{I05f>{ikk?1<7?tH34a?xhdj?0;6<uG27`8ykee?3:1=vF=6c9~jfd?290:wE<9b:
\7fmgg?=83;pD?8m;|l`fd<728qC>;l4}oaaf?6=9rB9:o5rnb``>5<6sA8=n6saccf94?7|@;<i7p`lbd83>4}O:?h0qcmmf;295~N5>k1vbnm?:182
\7fM41j2weon?50;3xL70e3tdho?4?:0yK63d<ugih?7>51zJ12g=zfji?6=4>{I05f>{ikj?1<7?tH34a?xhdk?0;6<uG27`8yked?3:1=vF=6c9~jfe?290:wE<9b:
\7fmgf?=83;pD?8m;|l`gd<728qC>;l4}oa`f?6=9rB9:o5rnba`>5<6sA8=n6sacbf94?7|@;<i7p`lcd83>4}O:?h0qcmlf;295~N5>k1vbnj?:182
\7fM41j2weoi?50;3xL70e3tdhh?4?:0yK63d<ugio?7>51zJ12g=zfjn?6=4>{I05f>{ikm?1<7?tH34a?xhdl?0;6<uG27`8ykec?3:1=vF=6c9~jfb?290:wE<9b:
\7fmga?=83;pD?8m;|l``d<728qC>;l4}oagf?6=9rB9:o5rnbf`>5<6sA8=n6sacef94?7|@;<i7p`ldd83>4}O:?h0qcmkf;295~N5>k1vbnk?:182
\7fM41j2weoh?50;3xL70e3tdhi?4?:0yK63d<ugin?7>51zJ12g=zfjo?6=4>{I05f>{ikl?1<7?tH34a?xhdm?0;6<uG27`8ykeb?3:1=vF=6c9~jfc?290:wE<9b:
\7fmg`?=83;pD?8m;|l`ad<728qC>;l4}oaff?6=9rB9:o5rnbg`>5<6sA8=n6sacdf94?7|@;<i7p`led83>4}O:?h0qcmjf;295~N5>k1vbnh?:182
\7fM41j2weok?50;3xL70e3tdhj?4?:0yK63d<ugim?7>51zJ12g=zfjl?6=4>{I05f>{iko?1<7?tH34a?xhdn?0;6<uG27`8ykea?3:1=vF=6c9~jf`?290:wE<9b:
\7fmgc?=83;pD?8m;|l`bd<728qC>;l4}oaef?6=9rB9:o5rnbd`>5<6sA8=n6sacgf94?7|@;<i7p`lfd83>4}O:?h0qcmif;295~N5>k1vbi>?:182
\7fM41j2weh=?50;3xL70e3tdo<?4?:0yK63d<ugn;?7>51zJ12g=zfm:?6=4>{I05f>{il9?1<7?tH34a?xhc8?0;6<uG27`8ykb7?3:1=vF=6c9~ja6?290:wE<9b:
\7fm`5?=83;pD?8m;|lg4d<728qC>;l4}of3f?6=9rB9:o5rne2`>5<6sA8=n6sad1f94?7|@;<i7p`k0d83>4}O:?h0qcj?f;295~N5>k1vbi??:182
\7fM41j2weh<?50;3xL70e3tdo=?4?:0yK63d<ugn:?7>51zJ12g=zfm;?6=4>{I05f>{il8?1<7?tH34a?xhc9?0;6<uG27`8ykb6?3:1=vF=6c9~ja7?290:wE<9b:
\7fm`4?=83;pD?8m;|lg5d<728qC>;l4}of2f?6=9rB9:o5rne3`>5<6sA8=n6sad0f94?7|@;<i7p`k1d83>4}O:?h0qcj>f;295~N5>k1vbi<?:182
\7fM41j2weh??50;3xL70e3tdo>?4?:0yK63d<ugn9?7>51zJ12g=zfm8?6=4>{I05f>{il;?1<7?tH34a?xhc:?0;6<uG27`8ykb5?3:1=vF=6c9~ja4?290:wE<9b:
\7fm`7?=83;pD?8m;|lg6d<728qC>;l4}of1f?6=9rB9:o5rne0`>5<6sA8=n6sad3f94?7|@;<i7p`k2d83>4}O:?h0qcj=f;295~N5>k1vbi=?:182
\7fM41j2weh>?50;3xL70e3tdo??4?:0yK63d<ugn8?7>51zJ12g=zfm9?6=4>{I05f>{il:?1<7?tH34a?xhc;?0;6<uG27`8ykb4?3:1=vF=6c9~ja5?290:wE<9b:
\7fm`6?=83;pD?8m;|lg7d<728qC>;l4}of0f?6=9rB9:o5rne1`>5<6sA8=n6sad2f94?7|@;<i7p`k3d83>4}O:?h0qcj<f;295~N5>k1vbi:?:182
\7fM41j2weh9?50;3xL70e3tdo8?4?:0yK63d<ugn??7>51zJ12g=zfm>?6=4>{I05f>{il=?1<7?tH34a?xhc<?0;6<uG27`8ykb3?3:1=vF=6c9~ja2?290:wE<9b:
\7fm`1?=83;pD?8m;|lg0d<728qC>;l4}of7f?6=9rB9:o5rne6`>5<6sA8=n6sad5f94?7|@;<i7p`k4d83>4}O:?h0qcj;f;295~N5>k1vbi;?:182
\7fM41j2weh8?50;3xL70e3tdo9?4?:0yK63d<ugn>?7>51zJ12g=zfm??6=4>{I05f>{il<?1<7?tH34a?xhc=?0;6<uG27`8ykb2?3:1=vF=6c9~ja3?290:wE<9b:
\7fm`0?=83;pD?8m;|lg1d<728qC>;l4}of6f?6=9rB9:o5rne7`>5<6sA8=n6sad4f94?7|@;<i7p`k5d83>4}O:?h0qcj:f;295~N5>k1vbi8?:182
\7fM41j2weh;?50;3xL70e3tdo:?4?:0yK63d<ugn=?7>51zJ12g=zfm<?6=4>{I05f>{il??1<7?tH34a?xhc>?0;6<uG27`8ykb1?3:1=vF=6c9~ja0?290:wE<9b:
\7fm`3?=83;pD?8m;|lg2d<728qC>;l4}of5f?6=9rB9:o5rne4`>5<6sA8=n6sad7f94?7|@;<i7p`k6d83>4}O:?h0qcj9f;295~N5>k1vbi9?:182
\7fM41j2weh:?50;3xL70e3tdo;?4?:0yK63d<ugn<?7>51zJ12g=zfm=?6=4>{I05f>{il>?1<7?tH34a?xhc??0;6<uG27`8ykb0?3:1=vF=6c9~ja1?290:wE<9b:
\7fm`2?=83;pD?8m;|lg3d<728qC>;l4}of4f?6=9rB9:o5rne5`>5<6sA8=n6sad6f94?7|@;<i7p`k7d83>4}O:?h0qck?5;295~N5>k1vqpsO@By24=d=;0>25;;r@A@x4xFGXrwKL
\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------
--- This file is owned and controlled by Xilinx and must be used --
--- solely for design, simulation, implementation and creation of --
--- design files limited to Xilinx devices or technologies. Use --
--- with non-Xilinx devices or technologies is expressly prohibited --
--- and immediately terminates your license. --
--- --
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
--- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
--- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
--- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
--- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
--- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
--- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
--- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
--- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
--- FOR A PARTICULAR PURPOSE. --
--- --
--- Xilinx products are not intended for use in life support --
--- appliances, devices, or systems. Use in such applications are --
--- expressly prohibited. --
--- --
--- (c) Copyright 1995-2007 Xilinx, Inc. --
--- All rights reserved. --
---------------------------------------------------------------------------------
--- You must compile the wrapper file trbv2_tlk_api_fifo.vhd when simulating
--- the core, trbv2_tlk_api_fifo. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-Library XilinxCoreLib;
--- synthesis translate_on
-ENTITY trbv2_tlk_api_fifo IS
- port (
- din: IN std_logic_VECTOR(17 downto 0);
- rd_clk: IN std_logic;
- rd_en: IN std_logic;
- rst: IN std_logic;
- wr_clk: IN std_logic;
- wr_en: IN std_logic;
- dout: OUT std_logic_VECTOR(17 downto 0);
- empty: OUT std_logic;
- full: OUT std_logic;
- rd_data_count: OUT std_logic_VECTOR(9 downto 0);
- wr_data_count: OUT std_logic_VECTOR(9 downto 0));
-END trbv2_tlk_api_fifo;
-
-ARCHITECTURE trbv2_tlk_api_fifo_a OF trbv2_tlk_api_fifo IS
--- synthesis translate_off
-component wrapped_trbv2_tlk_api_fifo
- port (
- din: IN std_logic_VECTOR(17 downto 0);
- rd_clk: IN std_logic;
- rd_en: IN std_logic;
- rst: IN std_logic;
- wr_clk: IN std_logic;
- wr_en: IN std_logic;
- dout: OUT std_logic_VECTOR(17 downto 0);
- empty: OUT std_logic;
- full: OUT std_logic;
- rd_data_count: OUT std_logic_VECTOR(9 downto 0);
- wr_data_count: OUT std_logic_VECTOR(9 downto 0));
-end component;
-
--- Configuration specification
- for all : wrapped_trbv2_tlk_api_fifo use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
- generic map(
- c_rd_freq => 100,
- c_wr_response_latency => 1,
- c_has_srst => 0,
- c_has_rd_data_count => 1,
- c_din_width => 18,
- c_has_wr_data_count => 1,
- c_implementation_type => 2,
- c_family => "virtex4",
- c_has_wr_rst => 0,
- c_wr_freq => 100,
- c_underflow_low => 0,
- c_has_meminit_file => 0,
- c_has_overflow => 0,
- c_preload_latency => 1,
- c_dout_width => 18,
- c_rd_depth => 1024,
- c_default_value => "BlankString",
- c_mif_file_name => "BlankString",
- c_has_underflow => 0,
- c_has_rd_rst => 0,
- c_has_almost_full => 0,
- c_has_rst => 1,
- c_data_count_width => 10,
- c_has_wr_ack => 0,
- c_use_ecc => 0,
- c_wr_ack_low => 0,
- c_common_clock => 0,
- c_rd_pntr_width => 10,
- c_has_almost_empty => 0,
- c_rd_data_count_width => 10,
- c_enable_rlocs => 0,
- c_wr_pntr_width => 10,
- c_overflow_low => 0,
- c_prog_empty_type => 0,
- c_optimization_mode => 0,
- c_wr_data_count_width => 10,
- c_preload_regs => 0,
- c_dout_rst_val => "0",
- c_has_data_count => 0,
- c_prog_full_thresh_negate_val => 1021,
- c_wr_depth => 1024,
- c_prog_empty_thresh_negate_val => 3,
- c_prog_empty_thresh_assert_val => 2,
- c_has_valid => 0,
- c_init_wr_pntr_val => 0,
- c_prog_full_thresh_assert_val => 1022,
- c_use_fifo16_flags => 0,
- c_has_backup => 0,
- c_valid_low => 0,
- c_prim_fifo_type => "1kx18",
- c_count_type => 0,
- c_prog_full_type => 0,
- c_memory_type => 1);
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_trbv2_tlk_api_fifo
- port map (
- din => din,
- rd_clk => rd_clk,
- rd_en => rd_en,
- rst => rst,
- wr_clk => wr_clk,
- wr_en => wr_en,
- dout => dout,
- empty => empty,
- full => full,
- rd_data_count => rd_data_count,
- wr_data_count => wr_data_count);
--- synthesis translate_on
-
-END trbv2_tlk_api_fifo_a;
-
jspc29 / trbnet.git / commitdiff